diff --git a/.github/workflows/deploy_qlsofa_hd.yaml b/.github/workflows/deploy_qlsofa_hd.yaml deleted file mode 100644 index a7db792..0000000 --- a/.github/workflows/deploy_qlsofa_hd.yaml +++ /dev/null @@ -1,68 +0,0 @@ -name: Caravel-QLSOFA_HD Deployment -# = = = Env Variable = = = = = -# secrets.TEST_REPO_KEY -# secrets.QLSOFA_HD_KEY -# secrets.SOFA_CHD_KEY -# secrets.QLQLSOFA_HD_KEY -# secrets.QLAP3_KEY -# yq r -X deploy_sofa.yaml > ./workflows/deploy_sofa_hd.yaml -env: - SCAN_DIRECTORY: 'FPGA1212_RESET_HD_SKY_PNR/**' - PROJ_SUFFIX: QLSOFA_HD - DEST_DIR: Caravel-QLSOFA-HD - DEST_REPO: lnis-uofu/Caravel-QLSOFA-HD - REPO_KEY: ${{ secrets.QLSOFA_HD_KEY }} -on: - push: - paths: - - '.github/**' - - 'SynRepoConfig/**' - - '$SCAN_DIRECTORY' - branches: - - ganesh_dev - pull_request: - types: closed - branches: - - master -jobs: - linux: - name: Updating release repository - runs-on: ubuntu-latest - steps: - - name: Checkout SOFA-Chips - uses: actions/checkout@v2 - with: - path: SOFA-Chips - - name: Checkout caravel repo - uses: actions/checkout@master - with: - repository: lnis-uofu/Caravel-QLSOFA-HD - path: Caravel-QLSOFA-HD - - name: Checkout open_mpw_precheck repo - uses: actions/checkout@master - with: - repository: efabless/open_mpw_precheck - path: open_mpw_precheck - - name: Perform checks with open_mpw_precheck - uses: ganeshgore/docker-run-action@49cd3a1 - with: - image: goreganesh/open_mpw_prechecker - options: > - -v ${{github.workspace}}/open_mpw_precheck:/usr/local/bin -v ${{github.workspace}}:/usr/local/workspace -e DEST_DIR=$DEST_DIR -e SCAN_DIRECTORY=$SCAN_DIRECTORY --workdir /usr/local/workspace - - run: cd /usr/local/workspace && pwd && ls && bash ./SOFA-Chips/.github/workflows/perform_precheck.sh - - name: Deploy files - # if: ${{ github.event_name == 'pull_request' && contains(github.ref, "master") && github.event.action == 'merged' }} - run: bash ./SOFA-Chips/.github/workflows/sync_repo.sh - - name: Deploy Changes - uses: peaceiris/actions-gh-pages@v3 - # if: ${{ github.event_name == 'pull_request' && contains(github.ref, "master") && github.event.action == 'merged' }} - with: - user_name: "lnis.uofu" - user_email: "lnis.uofu@gmail.com" - deploy_key: ${{ secrets.QLSOFA_HD_KEY }} - external_repository: lnis-uofu/Caravel-QLSOFA-HD - publish_dir: Caravel-QLSOFA-HD - publish_branch: master - disable_nojekyll: true - commit_message: '[Deployment] ${{ github.event.head_commit.message }}' diff --git a/.github/workflows/deploy_sofa_hd.yaml b/.github/workflows/deploy_sofa_hd.yaml deleted file mode 100644 index 6d55b85..0000000 --- a/.github/workflows/deploy_sofa_hd.yaml +++ /dev/null @@ -1,68 +0,0 @@ -name: Caravel-SOFA_HD Deployment -# = = = Env Variable = = = = = -# secrets.TEST_REPO_KEY -# secrets.SOFA_HD_KEY -# secrets.SOFA_CHD_KEY -# secrets.QLSOFA_HD_KEY -# secrets.QLAP3_KEY -# yq r -X deploy_sofa.yaml > ./workflows/deploy_sofa_hd.yaml -env: - SCAN_DIRECTORY: 'FPGA1212_FLAT_HD_SKY_PNR/**' - PROJ_SUFFIX: SOFA_HD - DEST_DIR: Caravel-SOFA-HD - DEST_REPO: lnis-uofu/Caravel-SOFA-HD - REPO_KEY: ${{ secrets.SOFA_HD_KEY }} -on: - push: - paths: - - '.github/**' - - 'SynRepoConfig/**' - - '$SCAN_DIRECTORY' - branches: - - ganesh_dev - pull_request: - types: closed - branches: - - master -jobs: - linux: - name: Updating release repository - runs-on: ubuntu-latest - steps: - - name: Checkout SOFA-Chips - uses: actions/checkout@v2 - with: - path: SOFA-Chips - - name: Checkout caravel repo - uses: actions/checkout@master - with: - repository: lnis-uofu/Caravel-SOFA-HD - path: Caravel-SOFA-HD - - name: Checkout open_mpw_precheck repo - uses: actions/checkout@master - with: - repository: efabless/open_mpw_precheck - path: open_mpw_precheck - - name: Perform checks with open_mpw_precheck - uses: ganeshgore/docker-run-action@49cd3a1 - with: - image: goreganesh/open_mpw_prechecker - options: > - -v ${{github.workspace}}/open_mpw_precheck:/usr/local/bin -v ${{github.workspace}}:/usr/local/workspace -e DEST_DIR=$DEST_DIR -e SCAN_DIRECTORY=$SCAN_DIRECTORY --workdir /usr/local/workspace - - run: cd /usr/local/workspace && pwd && ls && bash ./SOFA-Chips/.github/workflows/perform_precheck.sh - - name: Deploy files - # if: ${{ github.event_name == 'pull_request' && contains(github.ref, "master") && github.event.action == 'merged' }} - run: bash ./SOFA-Chips/.github/workflows/sync_repo.sh - - name: Deploy Changes - uses: peaceiris/actions-gh-pages@v3 - # if: ${{ github.event_name == 'pull_request' && contains(github.ref, "master") && github.event.action == 'merged' }} - with: - user_name: "lnis.uofu" - user_email: "lnis.uofu@gmail.com" - deploy_key: ${{ secrets.SOFA_HD_KEY }} - external_repository: lnis-uofu/Caravel-SOFA-HD - publish_dir: Caravel-SOFA-HD - publish_branch: master - disable_nojekyll: true - commit_message: '[Deployment] ${{ github.event.head_commit.message }}' diff --git a/.gitignore b/.gitignore index 481c56d..fc48497 100644 --- a/.gitignore +++ b/.gitignore @@ -6,5 +6,8 @@ **/*_task/skywater **/*_Verilog/SRC_Skeleton **/*_Verilog/SRCBackup +**/SRC/top_top_formal_verification.v **/DOC/build **/SRC**/*_tb.v +**/SDC/**/*.sdc +!**/SDC/**/disable_configure_ports.sdc diff --git a/FPGA1212_FLAT_HD_SKY_PNR/FPGA1212_FLAT_HD_SKY_Verilog/SDC/cbx_1__0_.sdc b/FPGA1212_FLAT_HD_SKY_PNR/FPGA1212_FLAT_HD_SKY_Verilog/SDC/cbx_1__0_.sdc deleted file mode 100644 index fc31f23..0000000 --- a/FPGA1212_FLAT_HD_SKY_PNR/FPGA1212_FLAT_HD_SKY_Verilog/SDC/cbx_1__0_.sdc +++ /dev/null @@ -1,144 +0,0 @@ -############################################# -# Synopsys Design Constraints (SDC) -# For FPGA fabric -# Description: Constrain timing of Connection Block cbx_1__0_ for PnR -# Author: Xifan TANG -# Organization: University of Utah -# Date: Sun Nov 29 02:09:07 2020 -############################################# - -############################################# -# Define time unit -############################################# -set_units -time s - -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[0] -to fpga_top/cbx_1__0_/chanx_left_out[0] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[0] -to fpga_top/cbx_1__0_/chanx_right_out[0] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[1] -to fpga_top/cbx_1__0_/chanx_left_out[1] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[1] -to fpga_top/cbx_1__0_/chanx_right_out[1] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[2] -to fpga_top/cbx_1__0_/chanx_left_out[2] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[2] -to fpga_top/cbx_1__0_/chanx_right_out[2] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[3] -to fpga_top/cbx_1__0_/chanx_left_out[3] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[3] -to fpga_top/cbx_1__0_/chanx_right_out[3] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[4] -to fpga_top/cbx_1__0_/chanx_left_out[4] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[4] -to fpga_top/cbx_1__0_/chanx_right_out[4] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[5] -to fpga_top/cbx_1__0_/chanx_left_out[5] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[5] -to fpga_top/cbx_1__0_/chanx_right_out[5] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[6] -to fpga_top/cbx_1__0_/chanx_left_out[6] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[6] -to fpga_top/cbx_1__0_/chanx_right_out[6] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[7] -to fpga_top/cbx_1__0_/chanx_left_out[7] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[7] -to fpga_top/cbx_1__0_/chanx_right_out[7] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[8] -to fpga_top/cbx_1__0_/chanx_left_out[8] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[8] -to fpga_top/cbx_1__0_/chanx_right_out[8] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[9] -to fpga_top/cbx_1__0_/chanx_left_out[9] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[9] -to fpga_top/cbx_1__0_/chanx_right_out[9] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[10] -to fpga_top/cbx_1__0_/chanx_left_out[10] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[10] -to fpga_top/cbx_1__0_/chanx_right_out[10] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[11] -to fpga_top/cbx_1__0_/chanx_left_out[11] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[11] -to fpga_top/cbx_1__0_/chanx_right_out[11] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[12] -to fpga_top/cbx_1__0_/chanx_left_out[12] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[12] -to fpga_top/cbx_1__0_/chanx_right_out[12] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[13] -to fpga_top/cbx_1__0_/chanx_left_out[13] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[13] -to fpga_top/cbx_1__0_/chanx_right_out[13] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[14] -to fpga_top/cbx_1__0_/chanx_left_out[14] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[14] -to fpga_top/cbx_1__0_/chanx_right_out[14] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[15] -to fpga_top/cbx_1__0_/chanx_left_out[15] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[15] -to fpga_top/cbx_1__0_/chanx_right_out[15] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[16] -to fpga_top/cbx_1__0_/chanx_left_out[16] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[16] -to fpga_top/cbx_1__0_/chanx_right_out[16] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[17] -to fpga_top/cbx_1__0_/chanx_left_out[17] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[17] -to fpga_top/cbx_1__0_/chanx_right_out[17] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[18] -to fpga_top/cbx_1__0_/chanx_left_out[18] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[18] -to fpga_top/cbx_1__0_/chanx_right_out[18] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[19] -to fpga_top/cbx_1__0_/chanx_left_out[19] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[19] -to fpga_top/cbx_1__0_/chanx_right_out[19] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[0] -to fpga_top/cbx_1__0_/bottom_grid_pin_0_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[0] -to fpga_top/cbx_1__0_/bottom_grid_pin_0_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[2] -to fpga_top/cbx_1__0_/bottom_grid_pin_0_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[2] -to fpga_top/cbx_1__0_/bottom_grid_pin_0_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[4] -to fpga_top/cbx_1__0_/bottom_grid_pin_0_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[4] -to fpga_top/cbx_1__0_/bottom_grid_pin_0_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[10] -to fpga_top/cbx_1__0_/bottom_grid_pin_0_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[10] -to fpga_top/cbx_1__0_/bottom_grid_pin_0_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[16] -to fpga_top/cbx_1__0_/bottom_grid_pin_0_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[16] -to fpga_top/cbx_1__0_/bottom_grid_pin_0_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[1] -to fpga_top/cbx_1__0_/bottom_grid_pin_2_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[1] -to fpga_top/cbx_1__0_/bottom_grid_pin_2_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[3] -to fpga_top/cbx_1__0_/bottom_grid_pin_2_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[3] -to fpga_top/cbx_1__0_/bottom_grid_pin_2_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[5] -to fpga_top/cbx_1__0_/bottom_grid_pin_2_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[5] -to fpga_top/cbx_1__0_/bottom_grid_pin_2_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[11] -to fpga_top/cbx_1__0_/bottom_grid_pin_2_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[11] -to fpga_top/cbx_1__0_/bottom_grid_pin_2_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[17] -to fpga_top/cbx_1__0_/bottom_grid_pin_2_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[17] -to fpga_top/cbx_1__0_/bottom_grid_pin_2_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[0] -to fpga_top/cbx_1__0_/bottom_grid_pin_4_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[0] -to fpga_top/cbx_1__0_/bottom_grid_pin_4_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[2] -to fpga_top/cbx_1__0_/bottom_grid_pin_4_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[2] -to fpga_top/cbx_1__0_/bottom_grid_pin_4_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[6] -to fpga_top/cbx_1__0_/bottom_grid_pin_4_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[6] -to fpga_top/cbx_1__0_/bottom_grid_pin_4_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[12] -to fpga_top/cbx_1__0_/bottom_grid_pin_4_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[12] -to fpga_top/cbx_1__0_/bottom_grid_pin_4_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[18] -to fpga_top/cbx_1__0_/bottom_grid_pin_4_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[18] -to fpga_top/cbx_1__0_/bottom_grid_pin_4_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[1] -to fpga_top/cbx_1__0_/bottom_grid_pin_6_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[1] -to fpga_top/cbx_1__0_/bottom_grid_pin_6_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[3] -to fpga_top/cbx_1__0_/bottom_grid_pin_6_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[3] -to fpga_top/cbx_1__0_/bottom_grid_pin_6_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[7] -to fpga_top/cbx_1__0_/bottom_grid_pin_6_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[7] -to fpga_top/cbx_1__0_/bottom_grid_pin_6_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[13] -to fpga_top/cbx_1__0_/bottom_grid_pin_6_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[13] -to fpga_top/cbx_1__0_/bottom_grid_pin_6_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[19] -to fpga_top/cbx_1__0_/bottom_grid_pin_6_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[19] -to fpga_top/cbx_1__0_/bottom_grid_pin_6_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[0] -to fpga_top/cbx_1__0_/bottom_grid_pin_8_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[0] -to fpga_top/cbx_1__0_/bottom_grid_pin_8_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[2] -to fpga_top/cbx_1__0_/bottom_grid_pin_8_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[2] -to fpga_top/cbx_1__0_/bottom_grid_pin_8_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[4] -to fpga_top/cbx_1__0_/bottom_grid_pin_8_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[4] -to fpga_top/cbx_1__0_/bottom_grid_pin_8_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[8] -to fpga_top/cbx_1__0_/bottom_grid_pin_8_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[8] -to fpga_top/cbx_1__0_/bottom_grid_pin_8_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[14] -to fpga_top/cbx_1__0_/bottom_grid_pin_8_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[14] -to fpga_top/cbx_1__0_/bottom_grid_pin_8_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[1] -to fpga_top/cbx_1__0_/bottom_grid_pin_10_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[1] -to fpga_top/cbx_1__0_/bottom_grid_pin_10_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[3] -to fpga_top/cbx_1__0_/bottom_grid_pin_10_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[3] -to fpga_top/cbx_1__0_/bottom_grid_pin_10_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[5] -to fpga_top/cbx_1__0_/bottom_grid_pin_10_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[5] -to fpga_top/cbx_1__0_/bottom_grid_pin_10_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[9] -to fpga_top/cbx_1__0_/bottom_grid_pin_10_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[9] -to fpga_top/cbx_1__0_/bottom_grid_pin_10_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[15] -to fpga_top/cbx_1__0_/bottom_grid_pin_10_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[15] -to fpga_top/cbx_1__0_/bottom_grid_pin_10_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[0] -to fpga_top/cbx_1__0_/bottom_grid_pin_12_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[0] -to fpga_top/cbx_1__0_/bottom_grid_pin_12_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[2] -to fpga_top/cbx_1__0_/bottom_grid_pin_12_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[2] -to fpga_top/cbx_1__0_/bottom_grid_pin_12_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[6] -to fpga_top/cbx_1__0_/bottom_grid_pin_12_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[6] -to fpga_top/cbx_1__0_/bottom_grid_pin_12_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[10] -to fpga_top/cbx_1__0_/bottom_grid_pin_12_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[10] -to fpga_top/cbx_1__0_/bottom_grid_pin_12_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[16] -to fpga_top/cbx_1__0_/bottom_grid_pin_12_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[16] -to fpga_top/cbx_1__0_/bottom_grid_pin_12_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[1] -to fpga_top/cbx_1__0_/bottom_grid_pin_14_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[1] -to fpga_top/cbx_1__0_/bottom_grid_pin_14_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[3] -to fpga_top/cbx_1__0_/bottom_grid_pin_14_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[3] -to fpga_top/cbx_1__0_/bottom_grid_pin_14_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[7] -to fpga_top/cbx_1__0_/bottom_grid_pin_14_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[7] -to fpga_top/cbx_1__0_/bottom_grid_pin_14_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[11] -to fpga_top/cbx_1__0_/bottom_grid_pin_14_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[11] -to fpga_top/cbx_1__0_/bottom_grid_pin_14_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[17] -to fpga_top/cbx_1__0_/bottom_grid_pin_14_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[17] -to fpga_top/cbx_1__0_/bottom_grid_pin_14_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[0] -to fpga_top/cbx_1__0_/bottom_grid_pin_16_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[0] -to fpga_top/cbx_1__0_/bottom_grid_pin_16_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[2] -to fpga_top/cbx_1__0_/bottom_grid_pin_16_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[2] -to fpga_top/cbx_1__0_/bottom_grid_pin_16_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[8] -to fpga_top/cbx_1__0_/bottom_grid_pin_16_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[8] -to fpga_top/cbx_1__0_/bottom_grid_pin_16_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[12] -to fpga_top/cbx_1__0_/bottom_grid_pin_16_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[12] -to fpga_top/cbx_1__0_/bottom_grid_pin_16_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[18] -to fpga_top/cbx_1__0_/bottom_grid_pin_16_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[18] -to fpga_top/cbx_1__0_/bottom_grid_pin_16_[0] 7.247000222e-11 diff --git a/FPGA1212_FLAT_HD_SKY_PNR/FPGA1212_FLAT_HD_SKY_Verilog/SDC/cbx_1__12_.sdc b/FPGA1212_FLAT_HD_SKY_PNR/FPGA1212_FLAT_HD_SKY_Verilog/SDC/cbx_1__12_.sdc deleted file mode 100644 index c6fbd27..0000000 --- a/FPGA1212_FLAT_HD_SKY_PNR/FPGA1212_FLAT_HD_SKY_Verilog/SDC/cbx_1__12_.sdc +++ /dev/null @@ -1,208 +0,0 @@ -############################################# -# Synopsys Design Constraints (SDC) -# For FPGA fabric -# Description: Constrain timing of Connection Block cbx_1__12_ for PnR -# Author: Xifan TANG -# Organization: University of Utah -# Date: Sun Nov 29 02:09:07 2020 -############################################# - -############################################# -# Define time unit -############################################# -set_units -time s - -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[0] -to fpga_top/cbx_1__12_/chanx_left_out[0] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[0] -to fpga_top/cbx_1__12_/chanx_right_out[0] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[1] -to fpga_top/cbx_1__12_/chanx_left_out[1] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[1] -to fpga_top/cbx_1__12_/chanx_right_out[1] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[2] -to fpga_top/cbx_1__12_/chanx_left_out[2] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[2] -to fpga_top/cbx_1__12_/chanx_right_out[2] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[3] -to fpga_top/cbx_1__12_/chanx_left_out[3] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[3] -to fpga_top/cbx_1__12_/chanx_right_out[3] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[4] -to fpga_top/cbx_1__12_/chanx_left_out[4] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[4] -to fpga_top/cbx_1__12_/chanx_right_out[4] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[5] -to fpga_top/cbx_1__12_/chanx_left_out[5] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[5] -to fpga_top/cbx_1__12_/chanx_right_out[5] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[6] -to fpga_top/cbx_1__12_/chanx_left_out[6] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[6] -to fpga_top/cbx_1__12_/chanx_right_out[6] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[7] -to fpga_top/cbx_1__12_/chanx_left_out[7] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[7] -to fpga_top/cbx_1__12_/chanx_right_out[7] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[8] -to fpga_top/cbx_1__12_/chanx_left_out[8] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[8] -to fpga_top/cbx_1__12_/chanx_right_out[8] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[9] -to fpga_top/cbx_1__12_/chanx_left_out[9] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[9] -to fpga_top/cbx_1__12_/chanx_right_out[9] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[10] -to fpga_top/cbx_1__12_/chanx_left_out[10] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[10] -to fpga_top/cbx_1__12_/chanx_right_out[10] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[11] -to fpga_top/cbx_1__12_/chanx_left_out[11] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[11] -to fpga_top/cbx_1__12_/chanx_right_out[11] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[12] -to fpga_top/cbx_1__12_/chanx_left_out[12] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[12] -to fpga_top/cbx_1__12_/chanx_right_out[12] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[13] -to fpga_top/cbx_1__12_/chanx_left_out[13] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[13] -to fpga_top/cbx_1__12_/chanx_right_out[13] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[14] -to fpga_top/cbx_1__12_/chanx_left_out[14] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[14] -to fpga_top/cbx_1__12_/chanx_right_out[14] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[15] -to fpga_top/cbx_1__12_/chanx_left_out[15] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[15] -to fpga_top/cbx_1__12_/chanx_right_out[15] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[16] -to fpga_top/cbx_1__12_/chanx_left_out[16] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[16] -to fpga_top/cbx_1__12_/chanx_right_out[16] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[17] -to fpga_top/cbx_1__12_/chanx_left_out[17] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[17] -to fpga_top/cbx_1__12_/chanx_right_out[17] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[18] -to fpga_top/cbx_1__12_/chanx_left_out[18] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[18] -to fpga_top/cbx_1__12_/chanx_right_out[18] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[19] -to fpga_top/cbx_1__12_/chanx_left_out[19] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[19] -to fpga_top/cbx_1__12_/chanx_right_out[19] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[0] -to fpga_top/cbx_1__12_/top_grid_pin_0_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[0] -to fpga_top/cbx_1__12_/top_grid_pin_0_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[2] -to fpga_top/cbx_1__12_/top_grid_pin_0_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[2] -to fpga_top/cbx_1__12_/top_grid_pin_0_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[4] -to fpga_top/cbx_1__12_/top_grid_pin_0_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[4] -to fpga_top/cbx_1__12_/top_grid_pin_0_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[10] -to fpga_top/cbx_1__12_/top_grid_pin_0_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[10] -to fpga_top/cbx_1__12_/top_grid_pin_0_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[16] -to fpga_top/cbx_1__12_/top_grid_pin_0_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[16] -to fpga_top/cbx_1__12_/top_grid_pin_0_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[1] -to fpga_top/cbx_1__12_/bottom_grid_pin_0_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[1] -to fpga_top/cbx_1__12_/bottom_grid_pin_0_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[3] -to fpga_top/cbx_1__12_/bottom_grid_pin_0_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[3] -to fpga_top/cbx_1__12_/bottom_grid_pin_0_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[5] -to fpga_top/cbx_1__12_/bottom_grid_pin_0_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[5] -to fpga_top/cbx_1__12_/bottom_grid_pin_0_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[11] -to fpga_top/cbx_1__12_/bottom_grid_pin_0_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[11] -to fpga_top/cbx_1__12_/bottom_grid_pin_0_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[17] -to fpga_top/cbx_1__12_/bottom_grid_pin_0_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[17] -to fpga_top/cbx_1__12_/bottom_grid_pin_0_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[0] -to fpga_top/cbx_1__12_/bottom_grid_pin_1_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[0] -to fpga_top/cbx_1__12_/bottom_grid_pin_1_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[2] -to fpga_top/cbx_1__12_/bottom_grid_pin_1_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[2] -to fpga_top/cbx_1__12_/bottom_grid_pin_1_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[6] -to fpga_top/cbx_1__12_/bottom_grid_pin_1_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[6] -to fpga_top/cbx_1__12_/bottom_grid_pin_1_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[14] -to fpga_top/cbx_1__12_/bottom_grid_pin_1_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[14] -to fpga_top/cbx_1__12_/bottom_grid_pin_1_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[1] -to fpga_top/cbx_1__12_/bottom_grid_pin_2_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[1] -to fpga_top/cbx_1__12_/bottom_grid_pin_2_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[3] -to fpga_top/cbx_1__12_/bottom_grid_pin_2_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[3] -to fpga_top/cbx_1__12_/bottom_grid_pin_2_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[7] -to fpga_top/cbx_1__12_/bottom_grid_pin_2_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[7] -to fpga_top/cbx_1__12_/bottom_grid_pin_2_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[15] -to fpga_top/cbx_1__12_/bottom_grid_pin_2_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[15] -to fpga_top/cbx_1__12_/bottom_grid_pin_2_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[0] -to fpga_top/cbx_1__12_/bottom_grid_pin_3_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[0] -to fpga_top/cbx_1__12_/bottom_grid_pin_3_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[2] -to fpga_top/cbx_1__12_/bottom_grid_pin_3_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[2] -to fpga_top/cbx_1__12_/bottom_grid_pin_3_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[4] -to fpga_top/cbx_1__12_/bottom_grid_pin_3_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[4] -to fpga_top/cbx_1__12_/bottom_grid_pin_3_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[8] -to fpga_top/cbx_1__12_/bottom_grid_pin_3_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[8] -to fpga_top/cbx_1__12_/bottom_grid_pin_3_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[14] -to fpga_top/cbx_1__12_/bottom_grid_pin_3_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[14] -to fpga_top/cbx_1__12_/bottom_grid_pin_3_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[1] -to fpga_top/cbx_1__12_/bottom_grid_pin_4_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[1] -to fpga_top/cbx_1__12_/bottom_grid_pin_4_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[3] -to fpga_top/cbx_1__12_/bottom_grid_pin_4_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[3] -to fpga_top/cbx_1__12_/bottom_grid_pin_4_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[5] -to fpga_top/cbx_1__12_/bottom_grid_pin_4_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[5] -to fpga_top/cbx_1__12_/bottom_grid_pin_4_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[9] -to fpga_top/cbx_1__12_/bottom_grid_pin_4_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[9] -to fpga_top/cbx_1__12_/bottom_grid_pin_4_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[15] -to fpga_top/cbx_1__12_/bottom_grid_pin_4_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[15] -to fpga_top/cbx_1__12_/bottom_grid_pin_4_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[0] -to fpga_top/cbx_1__12_/bottom_grid_pin_5_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[0] -to fpga_top/cbx_1__12_/bottom_grid_pin_5_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[2] -to fpga_top/cbx_1__12_/bottom_grid_pin_5_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[2] -to fpga_top/cbx_1__12_/bottom_grid_pin_5_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[10] -to fpga_top/cbx_1__12_/bottom_grid_pin_5_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[10] -to fpga_top/cbx_1__12_/bottom_grid_pin_5_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[18] -to fpga_top/cbx_1__12_/bottom_grid_pin_5_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[18] -to fpga_top/cbx_1__12_/bottom_grid_pin_5_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[1] -to fpga_top/cbx_1__12_/bottom_grid_pin_6_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[1] -to fpga_top/cbx_1__12_/bottom_grid_pin_6_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[3] -to fpga_top/cbx_1__12_/bottom_grid_pin_6_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[3] -to fpga_top/cbx_1__12_/bottom_grid_pin_6_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[11] -to fpga_top/cbx_1__12_/bottom_grid_pin_6_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[11] -to fpga_top/cbx_1__12_/bottom_grid_pin_6_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[19] -to fpga_top/cbx_1__12_/bottom_grid_pin_6_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[19] -to fpga_top/cbx_1__12_/bottom_grid_pin_6_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[0] -to fpga_top/cbx_1__12_/bottom_grid_pin_7_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[0] -to fpga_top/cbx_1__12_/bottom_grid_pin_7_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[2] -to fpga_top/cbx_1__12_/bottom_grid_pin_7_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[2] -to fpga_top/cbx_1__12_/bottom_grid_pin_7_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[8] -to fpga_top/cbx_1__12_/bottom_grid_pin_7_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[8] -to fpga_top/cbx_1__12_/bottom_grid_pin_7_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[12] -to fpga_top/cbx_1__12_/bottom_grid_pin_7_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[12] -to fpga_top/cbx_1__12_/bottom_grid_pin_7_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[18] -to fpga_top/cbx_1__12_/bottom_grid_pin_7_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[18] -to fpga_top/cbx_1__12_/bottom_grid_pin_7_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[1] -to fpga_top/cbx_1__12_/bottom_grid_pin_8_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[1] -to fpga_top/cbx_1__12_/bottom_grid_pin_8_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[3] -to fpga_top/cbx_1__12_/bottom_grid_pin_8_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[3] -to fpga_top/cbx_1__12_/bottom_grid_pin_8_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[9] -to fpga_top/cbx_1__12_/bottom_grid_pin_8_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[9] -to fpga_top/cbx_1__12_/bottom_grid_pin_8_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[13] -to fpga_top/cbx_1__12_/bottom_grid_pin_8_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[13] -to fpga_top/cbx_1__12_/bottom_grid_pin_8_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[19] -to fpga_top/cbx_1__12_/bottom_grid_pin_8_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[19] -to fpga_top/cbx_1__12_/bottom_grid_pin_8_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[0] -to fpga_top/cbx_1__12_/bottom_grid_pin_9_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[0] -to fpga_top/cbx_1__12_/bottom_grid_pin_9_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[2] -to fpga_top/cbx_1__12_/bottom_grid_pin_9_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[2] -to fpga_top/cbx_1__12_/bottom_grid_pin_9_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[6] -to fpga_top/cbx_1__12_/bottom_grid_pin_9_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[6] -to fpga_top/cbx_1__12_/bottom_grid_pin_9_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[14] -to fpga_top/cbx_1__12_/bottom_grid_pin_9_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[14] -to fpga_top/cbx_1__12_/bottom_grid_pin_9_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[1] -to fpga_top/cbx_1__12_/bottom_grid_pin_10_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[1] -to fpga_top/cbx_1__12_/bottom_grid_pin_10_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[3] -to fpga_top/cbx_1__12_/bottom_grid_pin_10_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[3] -to fpga_top/cbx_1__12_/bottom_grid_pin_10_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[7] -to fpga_top/cbx_1__12_/bottom_grid_pin_10_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[7] -to fpga_top/cbx_1__12_/bottom_grid_pin_10_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[15] -to fpga_top/cbx_1__12_/bottom_grid_pin_10_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[15] -to fpga_top/cbx_1__12_/bottom_grid_pin_10_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[0] -to fpga_top/cbx_1__12_/bottom_grid_pin_11_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[0] -to fpga_top/cbx_1__12_/bottom_grid_pin_11_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[2] -to fpga_top/cbx_1__12_/bottom_grid_pin_11_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[2] -to fpga_top/cbx_1__12_/bottom_grid_pin_11_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[6] -to fpga_top/cbx_1__12_/bottom_grid_pin_11_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[6] -to fpga_top/cbx_1__12_/bottom_grid_pin_11_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[12] -to fpga_top/cbx_1__12_/bottom_grid_pin_11_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[12] -to fpga_top/cbx_1__12_/bottom_grid_pin_11_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[16] -to fpga_top/cbx_1__12_/bottom_grid_pin_11_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[16] -to fpga_top/cbx_1__12_/bottom_grid_pin_11_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[1] -to fpga_top/cbx_1__12_/bottom_grid_pin_12_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[1] -to fpga_top/cbx_1__12_/bottom_grid_pin_12_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[3] -to fpga_top/cbx_1__12_/bottom_grid_pin_12_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[3] -to fpga_top/cbx_1__12_/bottom_grid_pin_12_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[7] -to fpga_top/cbx_1__12_/bottom_grid_pin_12_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[7] -to fpga_top/cbx_1__12_/bottom_grid_pin_12_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[13] -to fpga_top/cbx_1__12_/bottom_grid_pin_12_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[13] -to fpga_top/cbx_1__12_/bottom_grid_pin_12_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[17] -to fpga_top/cbx_1__12_/bottom_grid_pin_12_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[17] -to fpga_top/cbx_1__12_/bottom_grid_pin_12_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[0] -to fpga_top/cbx_1__12_/bottom_grid_pin_13_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[0] -to fpga_top/cbx_1__12_/bottom_grid_pin_13_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[2] -to fpga_top/cbx_1__12_/bottom_grid_pin_13_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[2] -to fpga_top/cbx_1__12_/bottom_grid_pin_13_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[10] -to fpga_top/cbx_1__12_/bottom_grid_pin_13_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[10] -to fpga_top/cbx_1__12_/bottom_grid_pin_13_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[18] -to fpga_top/cbx_1__12_/bottom_grid_pin_13_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[18] -to fpga_top/cbx_1__12_/bottom_grid_pin_13_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[1] -to fpga_top/cbx_1__12_/bottom_grid_pin_14_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[1] -to fpga_top/cbx_1__12_/bottom_grid_pin_14_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[3] -to fpga_top/cbx_1__12_/bottom_grid_pin_14_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[3] -to fpga_top/cbx_1__12_/bottom_grid_pin_14_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[11] -to fpga_top/cbx_1__12_/bottom_grid_pin_14_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[11] -to fpga_top/cbx_1__12_/bottom_grid_pin_14_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[19] -to fpga_top/cbx_1__12_/bottom_grid_pin_14_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[19] -to fpga_top/cbx_1__12_/bottom_grid_pin_14_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[0] -to fpga_top/cbx_1__12_/bottom_grid_pin_15_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[0] -to fpga_top/cbx_1__12_/bottom_grid_pin_15_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[2] -to fpga_top/cbx_1__12_/bottom_grid_pin_15_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[2] -to fpga_top/cbx_1__12_/bottom_grid_pin_15_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[4] -to fpga_top/cbx_1__12_/bottom_grid_pin_15_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[4] -to fpga_top/cbx_1__12_/bottom_grid_pin_15_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[10] -to fpga_top/cbx_1__12_/bottom_grid_pin_15_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[10] -to fpga_top/cbx_1__12_/bottom_grid_pin_15_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[16] -to fpga_top/cbx_1__12_/bottom_grid_pin_15_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[16] -to fpga_top/cbx_1__12_/bottom_grid_pin_15_[0] 7.247000222e-11 diff --git a/FPGA1212_FLAT_HD_SKY_PNR/FPGA1212_FLAT_HD_SKY_Verilog/SDC/cbx_1__1_.sdc b/FPGA1212_FLAT_HD_SKY_PNR/FPGA1212_FLAT_HD_SKY_Verilog/SDC/cbx_1__1_.sdc deleted file mode 100644 index 493377e..0000000 --- a/FPGA1212_FLAT_HD_SKY_PNR/FPGA1212_FLAT_HD_SKY_Verilog/SDC/cbx_1__1_.sdc +++ /dev/null @@ -1,198 +0,0 @@ -############################################# -# Synopsys Design Constraints (SDC) -# For FPGA fabric -# Description: Constrain timing of Connection Block cbx_1__1_ for PnR -# Author: Xifan TANG -# Organization: University of Utah -# Date: Sun Nov 29 02:09:07 2020 -############################################# - -############################################# -# Define time unit -############################################# -set_units -time s - -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[0] -to fpga_top/cbx_1__1_/chanx_left_out[0] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[0] -to fpga_top/cbx_1__1_/chanx_right_out[0] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[1] -to fpga_top/cbx_1__1_/chanx_left_out[1] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[1] -to fpga_top/cbx_1__1_/chanx_right_out[1] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[2] -to fpga_top/cbx_1__1_/chanx_left_out[2] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[2] -to fpga_top/cbx_1__1_/chanx_right_out[2] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[3] -to fpga_top/cbx_1__1_/chanx_left_out[3] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[3] -to fpga_top/cbx_1__1_/chanx_right_out[3] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[4] -to fpga_top/cbx_1__1_/chanx_left_out[4] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[4] -to fpga_top/cbx_1__1_/chanx_right_out[4] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[5] -to fpga_top/cbx_1__1_/chanx_left_out[5] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[5] -to fpga_top/cbx_1__1_/chanx_right_out[5] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[6] -to fpga_top/cbx_1__1_/chanx_left_out[6] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[6] -to fpga_top/cbx_1__1_/chanx_right_out[6] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[7] -to fpga_top/cbx_1__1_/chanx_left_out[7] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[7] -to fpga_top/cbx_1__1_/chanx_right_out[7] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[8] -to fpga_top/cbx_1__1_/chanx_left_out[8] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[8] -to fpga_top/cbx_1__1_/chanx_right_out[8] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[9] -to fpga_top/cbx_1__1_/chanx_left_out[9] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[9] -to fpga_top/cbx_1__1_/chanx_right_out[9] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[10] -to fpga_top/cbx_1__1_/chanx_left_out[10] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[10] -to fpga_top/cbx_1__1_/chanx_right_out[10] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[11] -to fpga_top/cbx_1__1_/chanx_left_out[11] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[11] -to fpga_top/cbx_1__1_/chanx_right_out[11] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[12] -to fpga_top/cbx_1__1_/chanx_left_out[12] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[12] -to fpga_top/cbx_1__1_/chanx_right_out[12] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[13] -to fpga_top/cbx_1__1_/chanx_left_out[13] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[13] -to fpga_top/cbx_1__1_/chanx_right_out[13] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[14] -to fpga_top/cbx_1__1_/chanx_left_out[14] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[14] -to fpga_top/cbx_1__1_/chanx_right_out[14] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[15] -to fpga_top/cbx_1__1_/chanx_left_out[15] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[15] -to fpga_top/cbx_1__1_/chanx_right_out[15] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[16] -to fpga_top/cbx_1__1_/chanx_left_out[16] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[16] -to fpga_top/cbx_1__1_/chanx_right_out[16] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[17] -to fpga_top/cbx_1__1_/chanx_left_out[17] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[17] -to fpga_top/cbx_1__1_/chanx_right_out[17] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[18] -to fpga_top/cbx_1__1_/chanx_left_out[18] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[18] -to fpga_top/cbx_1__1_/chanx_right_out[18] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[19] -to fpga_top/cbx_1__1_/chanx_left_out[19] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[19] -to fpga_top/cbx_1__1_/chanx_right_out[19] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[0] -to fpga_top/cbx_1__1_/bottom_grid_pin_0_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[0] -to fpga_top/cbx_1__1_/bottom_grid_pin_0_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[2] -to fpga_top/cbx_1__1_/bottom_grid_pin_0_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[2] -to fpga_top/cbx_1__1_/bottom_grid_pin_0_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[4] -to fpga_top/cbx_1__1_/bottom_grid_pin_0_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[4] -to fpga_top/cbx_1__1_/bottom_grid_pin_0_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[10] -to fpga_top/cbx_1__1_/bottom_grid_pin_0_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[10] -to fpga_top/cbx_1__1_/bottom_grid_pin_0_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[16] -to fpga_top/cbx_1__1_/bottom_grid_pin_0_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[16] -to fpga_top/cbx_1__1_/bottom_grid_pin_0_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[1] -to fpga_top/cbx_1__1_/bottom_grid_pin_1_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[1] -to fpga_top/cbx_1__1_/bottom_grid_pin_1_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[3] -to fpga_top/cbx_1__1_/bottom_grid_pin_1_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[3] -to fpga_top/cbx_1__1_/bottom_grid_pin_1_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[5] -to fpga_top/cbx_1__1_/bottom_grid_pin_1_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[5] -to fpga_top/cbx_1__1_/bottom_grid_pin_1_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[13] -to fpga_top/cbx_1__1_/bottom_grid_pin_1_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[13] -to fpga_top/cbx_1__1_/bottom_grid_pin_1_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[0] -to fpga_top/cbx_1__1_/bottom_grid_pin_2_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[0] -to fpga_top/cbx_1__1_/bottom_grid_pin_2_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[2] -to fpga_top/cbx_1__1_/bottom_grid_pin_2_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[2] -to fpga_top/cbx_1__1_/bottom_grid_pin_2_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[6] -to fpga_top/cbx_1__1_/bottom_grid_pin_2_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[6] -to fpga_top/cbx_1__1_/bottom_grid_pin_2_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[14] -to fpga_top/cbx_1__1_/bottom_grid_pin_2_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[14] -to fpga_top/cbx_1__1_/bottom_grid_pin_2_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[1] -to fpga_top/cbx_1__1_/bottom_grid_pin_3_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[1] -to fpga_top/cbx_1__1_/bottom_grid_pin_3_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[3] -to fpga_top/cbx_1__1_/bottom_grid_pin_3_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[3] -to fpga_top/cbx_1__1_/bottom_grid_pin_3_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[7] -to fpga_top/cbx_1__1_/bottom_grid_pin_3_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[7] -to fpga_top/cbx_1__1_/bottom_grid_pin_3_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[13] -to fpga_top/cbx_1__1_/bottom_grid_pin_3_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[13] -to fpga_top/cbx_1__1_/bottom_grid_pin_3_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[19] -to fpga_top/cbx_1__1_/bottom_grid_pin_3_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[19] -to fpga_top/cbx_1__1_/bottom_grid_pin_3_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[0] -to fpga_top/cbx_1__1_/bottom_grid_pin_4_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[0] -to fpga_top/cbx_1__1_/bottom_grid_pin_4_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[2] -to fpga_top/cbx_1__1_/bottom_grid_pin_4_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[2] -to fpga_top/cbx_1__1_/bottom_grid_pin_4_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[4] -to fpga_top/cbx_1__1_/bottom_grid_pin_4_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[4] -to fpga_top/cbx_1__1_/bottom_grid_pin_4_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[8] -to fpga_top/cbx_1__1_/bottom_grid_pin_4_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[8] -to fpga_top/cbx_1__1_/bottom_grid_pin_4_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[14] -to fpga_top/cbx_1__1_/bottom_grid_pin_4_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[14] -to fpga_top/cbx_1__1_/bottom_grid_pin_4_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[1] -to fpga_top/cbx_1__1_/bottom_grid_pin_5_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[1] -to fpga_top/cbx_1__1_/bottom_grid_pin_5_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[3] -to fpga_top/cbx_1__1_/bottom_grid_pin_5_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[3] -to fpga_top/cbx_1__1_/bottom_grid_pin_5_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[9] -to fpga_top/cbx_1__1_/bottom_grid_pin_5_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[9] -to fpga_top/cbx_1__1_/bottom_grid_pin_5_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[17] -to fpga_top/cbx_1__1_/bottom_grid_pin_5_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[17] -to fpga_top/cbx_1__1_/bottom_grid_pin_5_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[0] -to fpga_top/cbx_1__1_/bottom_grid_pin_6_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[0] -to fpga_top/cbx_1__1_/bottom_grid_pin_6_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[2] -to fpga_top/cbx_1__1_/bottom_grid_pin_6_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[2] -to fpga_top/cbx_1__1_/bottom_grid_pin_6_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[10] -to fpga_top/cbx_1__1_/bottom_grid_pin_6_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[10] -to fpga_top/cbx_1__1_/bottom_grid_pin_6_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[18] -to fpga_top/cbx_1__1_/bottom_grid_pin_6_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[18] -to fpga_top/cbx_1__1_/bottom_grid_pin_6_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[1] -to fpga_top/cbx_1__1_/bottom_grid_pin_7_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[1] -to fpga_top/cbx_1__1_/bottom_grid_pin_7_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[3] -to fpga_top/cbx_1__1_/bottom_grid_pin_7_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[3] -to fpga_top/cbx_1__1_/bottom_grid_pin_7_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[7] -to fpga_top/cbx_1__1_/bottom_grid_pin_7_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[7] -to fpga_top/cbx_1__1_/bottom_grid_pin_7_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[11] -to fpga_top/cbx_1__1_/bottom_grid_pin_7_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[11] -to fpga_top/cbx_1__1_/bottom_grid_pin_7_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[17] -to fpga_top/cbx_1__1_/bottom_grid_pin_7_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[17] -to fpga_top/cbx_1__1_/bottom_grid_pin_7_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[0] -to fpga_top/cbx_1__1_/bottom_grid_pin_8_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[0] -to fpga_top/cbx_1__1_/bottom_grid_pin_8_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[2] -to fpga_top/cbx_1__1_/bottom_grid_pin_8_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[2] -to fpga_top/cbx_1__1_/bottom_grid_pin_8_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[8] -to fpga_top/cbx_1__1_/bottom_grid_pin_8_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[8] -to fpga_top/cbx_1__1_/bottom_grid_pin_8_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[12] -to fpga_top/cbx_1__1_/bottom_grid_pin_8_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[12] -to fpga_top/cbx_1__1_/bottom_grid_pin_8_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[18] -to fpga_top/cbx_1__1_/bottom_grid_pin_8_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[18] -to fpga_top/cbx_1__1_/bottom_grid_pin_8_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[1] -to fpga_top/cbx_1__1_/bottom_grid_pin_9_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[1] -to fpga_top/cbx_1__1_/bottom_grid_pin_9_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[3] -to fpga_top/cbx_1__1_/bottom_grid_pin_9_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[3] -to fpga_top/cbx_1__1_/bottom_grid_pin_9_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[5] -to fpga_top/cbx_1__1_/bottom_grid_pin_9_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[5] -to fpga_top/cbx_1__1_/bottom_grid_pin_9_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[13] -to fpga_top/cbx_1__1_/bottom_grid_pin_9_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[13] -to fpga_top/cbx_1__1_/bottom_grid_pin_9_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[0] -to fpga_top/cbx_1__1_/bottom_grid_pin_10_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[0] -to fpga_top/cbx_1__1_/bottom_grid_pin_10_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[2] -to fpga_top/cbx_1__1_/bottom_grid_pin_10_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[2] -to fpga_top/cbx_1__1_/bottom_grid_pin_10_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[6] -to fpga_top/cbx_1__1_/bottom_grid_pin_10_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[6] -to fpga_top/cbx_1__1_/bottom_grid_pin_10_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[14] -to fpga_top/cbx_1__1_/bottom_grid_pin_10_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[14] -to fpga_top/cbx_1__1_/bottom_grid_pin_10_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[1] -to fpga_top/cbx_1__1_/bottom_grid_pin_11_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[1] -to fpga_top/cbx_1__1_/bottom_grid_pin_11_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[3] -to fpga_top/cbx_1__1_/bottom_grid_pin_11_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[3] -to fpga_top/cbx_1__1_/bottom_grid_pin_11_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[5] -to fpga_top/cbx_1__1_/bottom_grid_pin_11_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[5] -to fpga_top/cbx_1__1_/bottom_grid_pin_11_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[11] -to fpga_top/cbx_1__1_/bottom_grid_pin_11_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[11] -to fpga_top/cbx_1__1_/bottom_grid_pin_11_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[15] -to fpga_top/cbx_1__1_/bottom_grid_pin_11_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[15] -to fpga_top/cbx_1__1_/bottom_grid_pin_11_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[0] -to fpga_top/cbx_1__1_/bottom_grid_pin_12_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[0] -to fpga_top/cbx_1__1_/bottom_grid_pin_12_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[2] -to fpga_top/cbx_1__1_/bottom_grid_pin_12_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[2] -to fpga_top/cbx_1__1_/bottom_grid_pin_12_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[6] -to fpga_top/cbx_1__1_/bottom_grid_pin_12_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[6] -to fpga_top/cbx_1__1_/bottom_grid_pin_12_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[12] -to fpga_top/cbx_1__1_/bottom_grid_pin_12_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[12] -to fpga_top/cbx_1__1_/bottom_grid_pin_12_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[16] -to fpga_top/cbx_1__1_/bottom_grid_pin_12_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[16] -to fpga_top/cbx_1__1_/bottom_grid_pin_12_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[1] -to fpga_top/cbx_1__1_/bottom_grid_pin_13_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[1] -to fpga_top/cbx_1__1_/bottom_grid_pin_13_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[3] -to fpga_top/cbx_1__1_/bottom_grid_pin_13_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[3] -to fpga_top/cbx_1__1_/bottom_grid_pin_13_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[9] -to fpga_top/cbx_1__1_/bottom_grid_pin_13_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[9] -to fpga_top/cbx_1__1_/bottom_grid_pin_13_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[17] -to fpga_top/cbx_1__1_/bottom_grid_pin_13_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[17] -to fpga_top/cbx_1__1_/bottom_grid_pin_13_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[0] -to fpga_top/cbx_1__1_/bottom_grid_pin_14_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[0] -to fpga_top/cbx_1__1_/bottom_grid_pin_14_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[2] -to fpga_top/cbx_1__1_/bottom_grid_pin_14_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[2] -to fpga_top/cbx_1__1_/bottom_grid_pin_14_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[10] -to fpga_top/cbx_1__1_/bottom_grid_pin_14_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[10] -to fpga_top/cbx_1__1_/bottom_grid_pin_14_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[18] -to fpga_top/cbx_1__1_/bottom_grid_pin_14_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[18] -to fpga_top/cbx_1__1_/bottom_grid_pin_14_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[1] -to fpga_top/cbx_1__1_/bottom_grid_pin_15_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[1] -to fpga_top/cbx_1__1_/bottom_grid_pin_15_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[3] -to fpga_top/cbx_1__1_/bottom_grid_pin_15_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[3] -to fpga_top/cbx_1__1_/bottom_grid_pin_15_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[9] -to fpga_top/cbx_1__1_/bottom_grid_pin_15_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[9] -to fpga_top/cbx_1__1_/bottom_grid_pin_15_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[15] -to fpga_top/cbx_1__1_/bottom_grid_pin_15_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[15] -to fpga_top/cbx_1__1_/bottom_grid_pin_15_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[19] -to fpga_top/cbx_1__1_/bottom_grid_pin_15_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[19] -to fpga_top/cbx_1__1_/bottom_grid_pin_15_[0] 7.247000222e-11 diff --git a/FPGA1212_FLAT_HD_SKY_PNR/FPGA1212_FLAT_HD_SKY_Verilog/SDC/cby_0__1_.sdc b/FPGA1212_FLAT_HD_SKY_PNR/FPGA1212_FLAT_HD_SKY_Verilog/SDC/cby_0__1_.sdc deleted file mode 100644 index 6eb012e..0000000 --- a/FPGA1212_FLAT_HD_SKY_PNR/FPGA1212_FLAT_HD_SKY_Verilog/SDC/cby_0__1_.sdc +++ /dev/null @@ -1,64 +0,0 @@ -############################################# -# Synopsys Design Constraints (SDC) -# For FPGA fabric -# Description: Constrain timing of Connection Block cby_0__1_ for PnR -# Author: Xifan TANG -# Organization: University of Utah -# Date: Sun Nov 29 02:09:07 2020 -############################################# - -############################################# -# Define time unit -############################################# -set_units -time s - -set_max_delay -from fpga_core_uut/cby_0__1_/chany_bottom_in[0] -to fpga_top/cby_0__1_/chany_bottom_out[0] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_0__1_/chany_top_in[0] -to fpga_top/cby_0__1_/chany_top_out[0] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_0__1_/chany_bottom_in[1] -to fpga_top/cby_0__1_/chany_bottom_out[1] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_0__1_/chany_top_in[1] -to fpga_top/cby_0__1_/chany_top_out[1] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_0__1_/chany_bottom_in[2] -to fpga_top/cby_0__1_/chany_bottom_out[2] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_0__1_/chany_top_in[2] -to fpga_top/cby_0__1_/chany_top_out[2] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_0__1_/chany_bottom_in[3] -to fpga_top/cby_0__1_/chany_bottom_out[3] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_0__1_/chany_top_in[3] -to fpga_top/cby_0__1_/chany_top_out[3] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_0__1_/chany_bottom_in[4] -to fpga_top/cby_0__1_/chany_bottom_out[4] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_0__1_/chany_top_in[4] -to fpga_top/cby_0__1_/chany_top_out[4] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_0__1_/chany_bottom_in[5] -to fpga_top/cby_0__1_/chany_bottom_out[5] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_0__1_/chany_top_in[5] -to fpga_top/cby_0__1_/chany_top_out[5] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_0__1_/chany_bottom_in[6] -to fpga_top/cby_0__1_/chany_bottom_out[6] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_0__1_/chany_top_in[6] -to fpga_top/cby_0__1_/chany_top_out[6] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_0__1_/chany_bottom_in[7] -to fpga_top/cby_0__1_/chany_bottom_out[7] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_0__1_/chany_top_in[7] -to fpga_top/cby_0__1_/chany_top_out[7] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_0__1_/chany_bottom_in[8] -to fpga_top/cby_0__1_/chany_bottom_out[8] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_0__1_/chany_top_in[8] -to fpga_top/cby_0__1_/chany_top_out[8] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_0__1_/chany_bottom_in[9] -to fpga_top/cby_0__1_/chany_bottom_out[9] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_0__1_/chany_top_in[9] -to fpga_top/cby_0__1_/chany_top_out[9] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_0__1_/chany_bottom_in[10] -to fpga_top/cby_0__1_/chany_bottom_out[10] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_0__1_/chany_top_in[10] -to fpga_top/cby_0__1_/chany_top_out[10] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_0__1_/chany_bottom_in[11] -to fpga_top/cby_0__1_/chany_bottom_out[11] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_0__1_/chany_top_in[11] -to fpga_top/cby_0__1_/chany_top_out[11] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_0__1_/chany_bottom_in[12] -to fpga_top/cby_0__1_/chany_bottom_out[12] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_0__1_/chany_top_in[12] -to fpga_top/cby_0__1_/chany_top_out[12] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_0__1_/chany_bottom_in[13] -to fpga_top/cby_0__1_/chany_bottom_out[13] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_0__1_/chany_top_in[13] -to fpga_top/cby_0__1_/chany_top_out[13] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_0__1_/chany_bottom_in[14] -to fpga_top/cby_0__1_/chany_bottom_out[14] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_0__1_/chany_top_in[14] -to fpga_top/cby_0__1_/chany_top_out[14] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_0__1_/chany_bottom_in[15] -to fpga_top/cby_0__1_/chany_bottom_out[15] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_0__1_/chany_top_in[15] -to fpga_top/cby_0__1_/chany_top_out[15] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_0__1_/chany_bottom_in[16] -to fpga_top/cby_0__1_/chany_bottom_out[16] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_0__1_/chany_top_in[16] -to fpga_top/cby_0__1_/chany_top_out[16] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_0__1_/chany_bottom_in[17] -to fpga_top/cby_0__1_/chany_bottom_out[17] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_0__1_/chany_top_in[17] -to fpga_top/cby_0__1_/chany_top_out[17] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_0__1_/chany_bottom_in[18] -to fpga_top/cby_0__1_/chany_bottom_out[18] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_0__1_/chany_top_in[18] -to fpga_top/cby_0__1_/chany_top_out[18] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_0__1_/chany_bottom_in[19] -to fpga_top/cby_0__1_/chany_bottom_out[19] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_0__1_/chany_top_in[19] -to fpga_top/cby_0__1_/chany_top_out[19] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_0__1_/chany_bottom_in[0] -to fpga_top/cby_0__1_/left_grid_pin_0_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_0__1_/chany_top_in[0] -to fpga_top/cby_0__1_/left_grid_pin_0_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_0__1_/chany_bottom_in[2] -to fpga_top/cby_0__1_/left_grid_pin_0_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_0__1_/chany_top_in[2] -to fpga_top/cby_0__1_/left_grid_pin_0_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_0__1_/chany_bottom_in[4] -to fpga_top/cby_0__1_/left_grid_pin_0_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_0__1_/chany_top_in[4] -to fpga_top/cby_0__1_/left_grid_pin_0_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_0__1_/chany_bottom_in[10] -to fpga_top/cby_0__1_/left_grid_pin_0_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_0__1_/chany_top_in[10] -to fpga_top/cby_0__1_/left_grid_pin_0_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_0__1_/chany_bottom_in[16] -to fpga_top/cby_0__1_/left_grid_pin_0_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_0__1_/chany_top_in[16] -to fpga_top/cby_0__1_/left_grid_pin_0_[0] 7.247000222e-11 diff --git a/FPGA1212_FLAT_HD_SKY_PNR/FPGA1212_FLAT_HD_SKY_Verilog/SDC/cby_12__1_.sdc b/FPGA1212_FLAT_HD_SKY_PNR/FPGA1212_FLAT_HD_SKY_Verilog/SDC/cby_12__1_.sdc deleted file mode 100644 index 9263af3..0000000 --- a/FPGA1212_FLAT_HD_SKY_PNR/FPGA1212_FLAT_HD_SKY_Verilog/SDC/cby_12__1_.sdc +++ /dev/null @@ -1,208 +0,0 @@ -############################################# -# Synopsys Design Constraints (SDC) -# For FPGA fabric -# Description: Constrain timing of Connection Block cby_12__1_ for PnR -# Author: Xifan TANG -# Organization: University of Utah -# Date: Sun Nov 29 02:09:07 2020 -############################################# - -############################################# -# Define time unit -############################################# -set_units -time s - -set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[0] -to fpga_top/cby_12__1_/chany_bottom_out[0] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[0] -to fpga_top/cby_12__1_/chany_top_out[0] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[1] -to fpga_top/cby_12__1_/chany_bottom_out[1] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[1] -to fpga_top/cby_12__1_/chany_top_out[1] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[2] -to fpga_top/cby_12__1_/chany_bottom_out[2] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[2] -to fpga_top/cby_12__1_/chany_top_out[2] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[3] -to fpga_top/cby_12__1_/chany_bottom_out[3] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[3] -to fpga_top/cby_12__1_/chany_top_out[3] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[4] -to fpga_top/cby_12__1_/chany_bottom_out[4] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[4] -to fpga_top/cby_12__1_/chany_top_out[4] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[5] -to fpga_top/cby_12__1_/chany_bottom_out[5] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[5] -to fpga_top/cby_12__1_/chany_top_out[5] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[6] -to fpga_top/cby_12__1_/chany_bottom_out[6] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[6] -to fpga_top/cby_12__1_/chany_top_out[6] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[7] -to fpga_top/cby_12__1_/chany_bottom_out[7] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[7] -to fpga_top/cby_12__1_/chany_top_out[7] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[8] -to fpga_top/cby_12__1_/chany_bottom_out[8] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[8] -to fpga_top/cby_12__1_/chany_top_out[8] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[9] -to fpga_top/cby_12__1_/chany_bottom_out[9] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[9] -to fpga_top/cby_12__1_/chany_top_out[9] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[10] -to fpga_top/cby_12__1_/chany_bottom_out[10] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[10] -to fpga_top/cby_12__1_/chany_top_out[10] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[11] -to fpga_top/cby_12__1_/chany_bottom_out[11] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[11] -to fpga_top/cby_12__1_/chany_top_out[11] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[12] -to fpga_top/cby_12__1_/chany_bottom_out[12] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[12] -to fpga_top/cby_12__1_/chany_top_out[12] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[13] -to fpga_top/cby_12__1_/chany_bottom_out[13] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[13] -to fpga_top/cby_12__1_/chany_top_out[13] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[14] -to fpga_top/cby_12__1_/chany_bottom_out[14] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[14] -to fpga_top/cby_12__1_/chany_top_out[14] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[15] -to fpga_top/cby_12__1_/chany_bottom_out[15] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[15] -to fpga_top/cby_12__1_/chany_top_out[15] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[16] -to fpga_top/cby_12__1_/chany_bottom_out[16] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[16] -to fpga_top/cby_12__1_/chany_top_out[16] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[17] -to fpga_top/cby_12__1_/chany_bottom_out[17] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[17] -to fpga_top/cby_12__1_/chany_top_out[17] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[18] -to fpga_top/cby_12__1_/chany_bottom_out[18] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[18] -to fpga_top/cby_12__1_/chany_top_out[18] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[19] -to fpga_top/cby_12__1_/chany_bottom_out[19] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[19] -to fpga_top/cby_12__1_/chany_top_out[19] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[0] -to fpga_top/cby_12__1_/right_grid_pin_0_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[0] -to fpga_top/cby_12__1_/right_grid_pin_0_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[2] -to fpga_top/cby_12__1_/right_grid_pin_0_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[2] -to fpga_top/cby_12__1_/right_grid_pin_0_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[4] -to fpga_top/cby_12__1_/right_grid_pin_0_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[4] -to fpga_top/cby_12__1_/right_grid_pin_0_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[10] -to fpga_top/cby_12__1_/right_grid_pin_0_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[10] -to fpga_top/cby_12__1_/right_grid_pin_0_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[16] -to fpga_top/cby_12__1_/right_grid_pin_0_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[16] -to fpga_top/cby_12__1_/right_grid_pin_0_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[1] -to fpga_top/cby_12__1_/left_grid_pin_16_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[1] -to fpga_top/cby_12__1_/left_grid_pin_16_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[3] -to fpga_top/cby_12__1_/left_grid_pin_16_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[3] -to fpga_top/cby_12__1_/left_grid_pin_16_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[5] -to fpga_top/cby_12__1_/left_grid_pin_16_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[5] -to fpga_top/cby_12__1_/left_grid_pin_16_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[11] -to fpga_top/cby_12__1_/left_grid_pin_16_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[11] -to fpga_top/cby_12__1_/left_grid_pin_16_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[17] -to fpga_top/cby_12__1_/left_grid_pin_16_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[17] -to fpga_top/cby_12__1_/left_grid_pin_16_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[0] -to fpga_top/cby_12__1_/left_grid_pin_17_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[0] -to fpga_top/cby_12__1_/left_grid_pin_17_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[2] -to fpga_top/cby_12__1_/left_grid_pin_17_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[2] -to fpga_top/cby_12__1_/left_grid_pin_17_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[6] -to fpga_top/cby_12__1_/left_grid_pin_17_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[6] -to fpga_top/cby_12__1_/left_grid_pin_17_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[14] -to fpga_top/cby_12__1_/left_grid_pin_17_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[14] -to fpga_top/cby_12__1_/left_grid_pin_17_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[1] -to fpga_top/cby_12__1_/left_grid_pin_18_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[1] -to fpga_top/cby_12__1_/left_grid_pin_18_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[3] -to fpga_top/cby_12__1_/left_grid_pin_18_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[3] -to fpga_top/cby_12__1_/left_grid_pin_18_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[7] -to fpga_top/cby_12__1_/left_grid_pin_18_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[7] -to fpga_top/cby_12__1_/left_grid_pin_18_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[15] -to fpga_top/cby_12__1_/left_grid_pin_18_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[15] -to fpga_top/cby_12__1_/left_grid_pin_18_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[0] -to fpga_top/cby_12__1_/left_grid_pin_19_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[0] -to fpga_top/cby_12__1_/left_grid_pin_19_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[2] -to fpga_top/cby_12__1_/left_grid_pin_19_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[2] -to fpga_top/cby_12__1_/left_grid_pin_19_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[4] -to fpga_top/cby_12__1_/left_grid_pin_19_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[4] -to fpga_top/cby_12__1_/left_grid_pin_19_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[8] -to fpga_top/cby_12__1_/left_grid_pin_19_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[8] -to fpga_top/cby_12__1_/left_grid_pin_19_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[14] -to fpga_top/cby_12__1_/left_grid_pin_19_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[14] -to fpga_top/cby_12__1_/left_grid_pin_19_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[1] -to fpga_top/cby_12__1_/left_grid_pin_20_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[1] -to fpga_top/cby_12__1_/left_grid_pin_20_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[3] -to fpga_top/cby_12__1_/left_grid_pin_20_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[3] -to fpga_top/cby_12__1_/left_grid_pin_20_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[5] -to fpga_top/cby_12__1_/left_grid_pin_20_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[5] -to fpga_top/cby_12__1_/left_grid_pin_20_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[9] -to fpga_top/cby_12__1_/left_grid_pin_20_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[9] -to fpga_top/cby_12__1_/left_grid_pin_20_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[15] -to fpga_top/cby_12__1_/left_grid_pin_20_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[15] -to fpga_top/cby_12__1_/left_grid_pin_20_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[0] -to fpga_top/cby_12__1_/left_grid_pin_21_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[0] -to fpga_top/cby_12__1_/left_grid_pin_21_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[2] -to fpga_top/cby_12__1_/left_grid_pin_21_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[2] -to fpga_top/cby_12__1_/left_grid_pin_21_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[10] -to fpga_top/cby_12__1_/left_grid_pin_21_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[10] -to fpga_top/cby_12__1_/left_grid_pin_21_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[18] -to fpga_top/cby_12__1_/left_grid_pin_21_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[18] -to fpga_top/cby_12__1_/left_grid_pin_21_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[1] -to fpga_top/cby_12__1_/left_grid_pin_22_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[1] -to fpga_top/cby_12__1_/left_grid_pin_22_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[3] -to fpga_top/cby_12__1_/left_grid_pin_22_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[3] -to fpga_top/cby_12__1_/left_grid_pin_22_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[11] -to fpga_top/cby_12__1_/left_grid_pin_22_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[11] -to fpga_top/cby_12__1_/left_grid_pin_22_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[19] -to fpga_top/cby_12__1_/left_grid_pin_22_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[19] -to fpga_top/cby_12__1_/left_grid_pin_22_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[0] -to fpga_top/cby_12__1_/left_grid_pin_23_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[0] -to fpga_top/cby_12__1_/left_grid_pin_23_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[2] -to fpga_top/cby_12__1_/left_grid_pin_23_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[2] -to fpga_top/cby_12__1_/left_grid_pin_23_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[8] -to fpga_top/cby_12__1_/left_grid_pin_23_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[8] -to fpga_top/cby_12__1_/left_grid_pin_23_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[12] -to fpga_top/cby_12__1_/left_grid_pin_23_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[12] -to fpga_top/cby_12__1_/left_grid_pin_23_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[18] -to fpga_top/cby_12__1_/left_grid_pin_23_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[18] -to fpga_top/cby_12__1_/left_grid_pin_23_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[1] -to fpga_top/cby_12__1_/left_grid_pin_24_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[1] -to fpga_top/cby_12__1_/left_grid_pin_24_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[3] -to fpga_top/cby_12__1_/left_grid_pin_24_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[3] -to fpga_top/cby_12__1_/left_grid_pin_24_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[9] -to fpga_top/cby_12__1_/left_grid_pin_24_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[9] -to fpga_top/cby_12__1_/left_grid_pin_24_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[13] -to fpga_top/cby_12__1_/left_grid_pin_24_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[13] -to fpga_top/cby_12__1_/left_grid_pin_24_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[19] -to fpga_top/cby_12__1_/left_grid_pin_24_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[19] -to fpga_top/cby_12__1_/left_grid_pin_24_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[0] -to fpga_top/cby_12__1_/left_grid_pin_25_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[0] -to fpga_top/cby_12__1_/left_grid_pin_25_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[2] -to fpga_top/cby_12__1_/left_grid_pin_25_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[2] -to fpga_top/cby_12__1_/left_grid_pin_25_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[6] -to fpga_top/cby_12__1_/left_grid_pin_25_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[6] -to fpga_top/cby_12__1_/left_grid_pin_25_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[14] -to fpga_top/cby_12__1_/left_grid_pin_25_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[14] -to fpga_top/cby_12__1_/left_grid_pin_25_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[1] -to fpga_top/cby_12__1_/left_grid_pin_26_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[1] -to fpga_top/cby_12__1_/left_grid_pin_26_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[3] -to fpga_top/cby_12__1_/left_grid_pin_26_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[3] -to fpga_top/cby_12__1_/left_grid_pin_26_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[7] -to fpga_top/cby_12__1_/left_grid_pin_26_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[7] -to fpga_top/cby_12__1_/left_grid_pin_26_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[15] -to fpga_top/cby_12__1_/left_grid_pin_26_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[15] -to fpga_top/cby_12__1_/left_grid_pin_26_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[0] -to fpga_top/cby_12__1_/left_grid_pin_27_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[0] -to fpga_top/cby_12__1_/left_grid_pin_27_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[2] -to fpga_top/cby_12__1_/left_grid_pin_27_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[2] -to fpga_top/cby_12__1_/left_grid_pin_27_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[6] -to fpga_top/cby_12__1_/left_grid_pin_27_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[6] -to fpga_top/cby_12__1_/left_grid_pin_27_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[12] -to fpga_top/cby_12__1_/left_grid_pin_27_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[12] -to fpga_top/cby_12__1_/left_grid_pin_27_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[16] -to fpga_top/cby_12__1_/left_grid_pin_27_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[16] -to fpga_top/cby_12__1_/left_grid_pin_27_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[1] -to fpga_top/cby_12__1_/left_grid_pin_28_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[1] -to fpga_top/cby_12__1_/left_grid_pin_28_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[3] -to fpga_top/cby_12__1_/left_grid_pin_28_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[3] -to fpga_top/cby_12__1_/left_grid_pin_28_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[7] -to fpga_top/cby_12__1_/left_grid_pin_28_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[7] -to fpga_top/cby_12__1_/left_grid_pin_28_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[13] -to fpga_top/cby_12__1_/left_grid_pin_28_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[13] -to fpga_top/cby_12__1_/left_grid_pin_28_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[17] -to fpga_top/cby_12__1_/left_grid_pin_28_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[17] -to fpga_top/cby_12__1_/left_grid_pin_28_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[0] -to fpga_top/cby_12__1_/left_grid_pin_29_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[0] -to fpga_top/cby_12__1_/left_grid_pin_29_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[2] -to fpga_top/cby_12__1_/left_grid_pin_29_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[2] -to fpga_top/cby_12__1_/left_grid_pin_29_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[10] -to fpga_top/cby_12__1_/left_grid_pin_29_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[10] -to fpga_top/cby_12__1_/left_grid_pin_29_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[18] -to fpga_top/cby_12__1_/left_grid_pin_29_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[18] -to fpga_top/cby_12__1_/left_grid_pin_29_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[1] -to fpga_top/cby_12__1_/left_grid_pin_30_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[1] -to fpga_top/cby_12__1_/left_grid_pin_30_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[3] -to fpga_top/cby_12__1_/left_grid_pin_30_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[3] -to fpga_top/cby_12__1_/left_grid_pin_30_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[11] -to fpga_top/cby_12__1_/left_grid_pin_30_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[11] -to fpga_top/cby_12__1_/left_grid_pin_30_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[19] -to fpga_top/cby_12__1_/left_grid_pin_30_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[19] -to fpga_top/cby_12__1_/left_grid_pin_30_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[0] -to fpga_top/cby_12__1_/left_grid_pin_31_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[0] -to fpga_top/cby_12__1_/left_grid_pin_31_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[2] -to fpga_top/cby_12__1_/left_grid_pin_31_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[2] -to fpga_top/cby_12__1_/left_grid_pin_31_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[4] -to fpga_top/cby_12__1_/left_grid_pin_31_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[4] -to fpga_top/cby_12__1_/left_grid_pin_31_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[10] -to fpga_top/cby_12__1_/left_grid_pin_31_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[10] -to fpga_top/cby_12__1_/left_grid_pin_31_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[16] -to fpga_top/cby_12__1_/left_grid_pin_31_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[16] -to fpga_top/cby_12__1_/left_grid_pin_31_[0] 7.247000222e-11 diff --git a/FPGA1212_FLAT_HD_SKY_PNR/FPGA1212_FLAT_HD_SKY_Verilog/SDC/cby_1__1_.sdc b/FPGA1212_FLAT_HD_SKY_PNR/FPGA1212_FLAT_HD_SKY_Verilog/SDC/cby_1__1_.sdc deleted file mode 100644 index facf484..0000000 --- a/FPGA1212_FLAT_HD_SKY_PNR/FPGA1212_FLAT_HD_SKY_Verilog/SDC/cby_1__1_.sdc +++ /dev/null @@ -1,198 +0,0 @@ -############################################# -# Synopsys Design Constraints (SDC) -# For FPGA fabric -# Description: Constrain timing of Connection Block cby_1__1_ for PnR -# Author: Xifan TANG -# Organization: University of Utah -# Date: Sun Nov 29 02:09:07 2020 -############################################# - -############################################# -# Define time unit -############################################# -set_units -time s - -set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[0] -to fpga_top/cby_1__1_/chany_bottom_out[0] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[0] -to fpga_top/cby_1__1_/chany_top_out[0] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[1] -to fpga_top/cby_1__1_/chany_bottom_out[1] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[1] -to fpga_top/cby_1__1_/chany_top_out[1] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[2] -to fpga_top/cby_1__1_/chany_bottom_out[2] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[2] -to fpga_top/cby_1__1_/chany_top_out[2] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[3] -to fpga_top/cby_1__1_/chany_bottom_out[3] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[3] -to fpga_top/cby_1__1_/chany_top_out[3] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[4] -to fpga_top/cby_1__1_/chany_bottom_out[4] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[4] -to fpga_top/cby_1__1_/chany_top_out[4] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[5] -to fpga_top/cby_1__1_/chany_bottom_out[5] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[5] -to fpga_top/cby_1__1_/chany_top_out[5] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[6] -to fpga_top/cby_1__1_/chany_bottom_out[6] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[6] -to fpga_top/cby_1__1_/chany_top_out[6] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[7] -to fpga_top/cby_1__1_/chany_bottom_out[7] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[7] -to fpga_top/cby_1__1_/chany_top_out[7] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[8] -to fpga_top/cby_1__1_/chany_bottom_out[8] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[8] -to fpga_top/cby_1__1_/chany_top_out[8] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[9] -to fpga_top/cby_1__1_/chany_bottom_out[9] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[9] -to fpga_top/cby_1__1_/chany_top_out[9] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[10] -to fpga_top/cby_1__1_/chany_bottom_out[10] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[10] -to fpga_top/cby_1__1_/chany_top_out[10] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[11] -to fpga_top/cby_1__1_/chany_bottom_out[11] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[11] -to fpga_top/cby_1__1_/chany_top_out[11] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[12] -to fpga_top/cby_1__1_/chany_bottom_out[12] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[12] -to fpga_top/cby_1__1_/chany_top_out[12] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[13] -to fpga_top/cby_1__1_/chany_bottom_out[13] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[13] -to fpga_top/cby_1__1_/chany_top_out[13] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[14] -to fpga_top/cby_1__1_/chany_bottom_out[14] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[14] -to fpga_top/cby_1__1_/chany_top_out[14] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[15] -to fpga_top/cby_1__1_/chany_bottom_out[15] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[15] -to fpga_top/cby_1__1_/chany_top_out[15] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[16] -to fpga_top/cby_1__1_/chany_bottom_out[16] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[16] -to fpga_top/cby_1__1_/chany_top_out[16] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[17] -to fpga_top/cby_1__1_/chany_bottom_out[17] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[17] -to fpga_top/cby_1__1_/chany_top_out[17] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[18] -to fpga_top/cby_1__1_/chany_bottom_out[18] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[18] -to fpga_top/cby_1__1_/chany_top_out[18] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[19] -to fpga_top/cby_1__1_/chany_bottom_out[19] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[19] -to fpga_top/cby_1__1_/chany_top_out[19] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[0] -to fpga_top/cby_1__1_/left_grid_pin_16_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[0] -to fpga_top/cby_1__1_/left_grid_pin_16_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[2] -to fpga_top/cby_1__1_/left_grid_pin_16_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[2] -to fpga_top/cby_1__1_/left_grid_pin_16_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[4] -to fpga_top/cby_1__1_/left_grid_pin_16_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[4] -to fpga_top/cby_1__1_/left_grid_pin_16_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[10] -to fpga_top/cby_1__1_/left_grid_pin_16_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[10] -to fpga_top/cby_1__1_/left_grid_pin_16_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[16] -to fpga_top/cby_1__1_/left_grid_pin_16_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[16] -to fpga_top/cby_1__1_/left_grid_pin_16_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[1] -to fpga_top/cby_1__1_/left_grid_pin_17_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[1] -to fpga_top/cby_1__1_/left_grid_pin_17_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[3] -to fpga_top/cby_1__1_/left_grid_pin_17_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[3] -to fpga_top/cby_1__1_/left_grid_pin_17_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[5] -to fpga_top/cby_1__1_/left_grid_pin_17_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[5] -to fpga_top/cby_1__1_/left_grid_pin_17_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[13] -to fpga_top/cby_1__1_/left_grid_pin_17_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[13] -to fpga_top/cby_1__1_/left_grid_pin_17_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[0] -to fpga_top/cby_1__1_/left_grid_pin_18_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[0] -to fpga_top/cby_1__1_/left_grid_pin_18_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[2] -to fpga_top/cby_1__1_/left_grid_pin_18_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[2] -to fpga_top/cby_1__1_/left_grid_pin_18_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[6] -to fpga_top/cby_1__1_/left_grid_pin_18_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[6] -to fpga_top/cby_1__1_/left_grid_pin_18_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[14] -to fpga_top/cby_1__1_/left_grid_pin_18_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[14] -to fpga_top/cby_1__1_/left_grid_pin_18_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[1] -to fpga_top/cby_1__1_/left_grid_pin_19_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[1] -to fpga_top/cby_1__1_/left_grid_pin_19_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[3] -to fpga_top/cby_1__1_/left_grid_pin_19_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[3] -to fpga_top/cby_1__1_/left_grid_pin_19_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[7] -to fpga_top/cby_1__1_/left_grid_pin_19_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[7] -to fpga_top/cby_1__1_/left_grid_pin_19_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[13] -to fpga_top/cby_1__1_/left_grid_pin_19_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[13] -to fpga_top/cby_1__1_/left_grid_pin_19_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[19] -to fpga_top/cby_1__1_/left_grid_pin_19_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[19] -to fpga_top/cby_1__1_/left_grid_pin_19_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[0] -to fpga_top/cby_1__1_/left_grid_pin_20_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[0] -to fpga_top/cby_1__1_/left_grid_pin_20_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[2] -to fpga_top/cby_1__1_/left_grid_pin_20_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[2] -to fpga_top/cby_1__1_/left_grid_pin_20_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[4] -to fpga_top/cby_1__1_/left_grid_pin_20_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[4] -to fpga_top/cby_1__1_/left_grid_pin_20_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[8] -to fpga_top/cby_1__1_/left_grid_pin_20_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[8] -to fpga_top/cby_1__1_/left_grid_pin_20_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[14] -to fpga_top/cby_1__1_/left_grid_pin_20_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[14] -to fpga_top/cby_1__1_/left_grid_pin_20_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[1] -to fpga_top/cby_1__1_/left_grid_pin_21_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[1] -to fpga_top/cby_1__1_/left_grid_pin_21_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[3] -to fpga_top/cby_1__1_/left_grid_pin_21_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[3] -to fpga_top/cby_1__1_/left_grid_pin_21_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[9] -to fpga_top/cby_1__1_/left_grid_pin_21_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[9] -to fpga_top/cby_1__1_/left_grid_pin_21_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[17] -to fpga_top/cby_1__1_/left_grid_pin_21_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[17] -to fpga_top/cby_1__1_/left_grid_pin_21_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[0] -to fpga_top/cby_1__1_/left_grid_pin_22_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[0] -to fpga_top/cby_1__1_/left_grid_pin_22_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[2] -to fpga_top/cby_1__1_/left_grid_pin_22_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[2] -to fpga_top/cby_1__1_/left_grid_pin_22_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[10] -to fpga_top/cby_1__1_/left_grid_pin_22_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[10] -to fpga_top/cby_1__1_/left_grid_pin_22_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[18] -to fpga_top/cby_1__1_/left_grid_pin_22_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[18] -to fpga_top/cby_1__1_/left_grid_pin_22_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[1] -to fpga_top/cby_1__1_/left_grid_pin_23_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[1] -to fpga_top/cby_1__1_/left_grid_pin_23_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[3] -to fpga_top/cby_1__1_/left_grid_pin_23_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[3] -to fpga_top/cby_1__1_/left_grid_pin_23_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[7] -to fpga_top/cby_1__1_/left_grid_pin_23_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[7] -to fpga_top/cby_1__1_/left_grid_pin_23_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[11] -to fpga_top/cby_1__1_/left_grid_pin_23_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[11] -to fpga_top/cby_1__1_/left_grid_pin_23_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[17] -to fpga_top/cby_1__1_/left_grid_pin_23_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[17] -to fpga_top/cby_1__1_/left_grid_pin_23_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[0] -to fpga_top/cby_1__1_/left_grid_pin_24_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[0] -to fpga_top/cby_1__1_/left_grid_pin_24_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[2] -to fpga_top/cby_1__1_/left_grid_pin_24_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[2] -to fpga_top/cby_1__1_/left_grid_pin_24_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[8] -to fpga_top/cby_1__1_/left_grid_pin_24_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[8] -to fpga_top/cby_1__1_/left_grid_pin_24_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[12] -to fpga_top/cby_1__1_/left_grid_pin_24_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[12] -to fpga_top/cby_1__1_/left_grid_pin_24_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[18] -to fpga_top/cby_1__1_/left_grid_pin_24_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[18] -to fpga_top/cby_1__1_/left_grid_pin_24_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[1] -to fpga_top/cby_1__1_/left_grid_pin_25_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[1] -to fpga_top/cby_1__1_/left_grid_pin_25_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[3] -to fpga_top/cby_1__1_/left_grid_pin_25_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[3] -to fpga_top/cby_1__1_/left_grid_pin_25_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[5] -to fpga_top/cby_1__1_/left_grid_pin_25_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[5] -to fpga_top/cby_1__1_/left_grid_pin_25_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[13] -to fpga_top/cby_1__1_/left_grid_pin_25_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[13] -to fpga_top/cby_1__1_/left_grid_pin_25_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[0] -to fpga_top/cby_1__1_/left_grid_pin_26_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[0] -to fpga_top/cby_1__1_/left_grid_pin_26_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[2] -to fpga_top/cby_1__1_/left_grid_pin_26_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[2] -to fpga_top/cby_1__1_/left_grid_pin_26_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[6] -to fpga_top/cby_1__1_/left_grid_pin_26_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[6] -to fpga_top/cby_1__1_/left_grid_pin_26_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[14] -to fpga_top/cby_1__1_/left_grid_pin_26_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[14] -to fpga_top/cby_1__1_/left_grid_pin_26_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[1] -to fpga_top/cby_1__1_/left_grid_pin_27_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[1] -to fpga_top/cby_1__1_/left_grid_pin_27_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[3] -to fpga_top/cby_1__1_/left_grid_pin_27_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[3] -to fpga_top/cby_1__1_/left_grid_pin_27_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[5] -to fpga_top/cby_1__1_/left_grid_pin_27_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[5] -to fpga_top/cby_1__1_/left_grid_pin_27_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[11] -to fpga_top/cby_1__1_/left_grid_pin_27_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[11] -to fpga_top/cby_1__1_/left_grid_pin_27_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[15] -to fpga_top/cby_1__1_/left_grid_pin_27_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[15] -to fpga_top/cby_1__1_/left_grid_pin_27_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[0] -to fpga_top/cby_1__1_/left_grid_pin_28_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[0] -to fpga_top/cby_1__1_/left_grid_pin_28_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[2] -to fpga_top/cby_1__1_/left_grid_pin_28_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[2] -to fpga_top/cby_1__1_/left_grid_pin_28_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[6] -to fpga_top/cby_1__1_/left_grid_pin_28_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[6] -to fpga_top/cby_1__1_/left_grid_pin_28_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[12] -to fpga_top/cby_1__1_/left_grid_pin_28_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[12] -to fpga_top/cby_1__1_/left_grid_pin_28_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[16] -to fpga_top/cby_1__1_/left_grid_pin_28_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[16] -to fpga_top/cby_1__1_/left_grid_pin_28_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[1] -to fpga_top/cby_1__1_/left_grid_pin_29_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[1] -to fpga_top/cby_1__1_/left_grid_pin_29_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[3] -to fpga_top/cby_1__1_/left_grid_pin_29_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[3] -to fpga_top/cby_1__1_/left_grid_pin_29_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[9] -to fpga_top/cby_1__1_/left_grid_pin_29_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[9] -to fpga_top/cby_1__1_/left_grid_pin_29_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[17] -to fpga_top/cby_1__1_/left_grid_pin_29_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[17] -to fpga_top/cby_1__1_/left_grid_pin_29_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[0] -to fpga_top/cby_1__1_/left_grid_pin_30_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[0] -to fpga_top/cby_1__1_/left_grid_pin_30_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[2] -to fpga_top/cby_1__1_/left_grid_pin_30_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[2] -to fpga_top/cby_1__1_/left_grid_pin_30_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[10] -to fpga_top/cby_1__1_/left_grid_pin_30_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[10] -to fpga_top/cby_1__1_/left_grid_pin_30_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[18] -to fpga_top/cby_1__1_/left_grid_pin_30_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[18] -to fpga_top/cby_1__1_/left_grid_pin_30_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[1] -to fpga_top/cby_1__1_/left_grid_pin_31_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[1] -to fpga_top/cby_1__1_/left_grid_pin_31_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[3] -to fpga_top/cby_1__1_/left_grid_pin_31_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[3] -to fpga_top/cby_1__1_/left_grid_pin_31_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[9] -to fpga_top/cby_1__1_/left_grid_pin_31_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[9] -to fpga_top/cby_1__1_/left_grid_pin_31_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[15] -to fpga_top/cby_1__1_/left_grid_pin_31_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[15] -to fpga_top/cby_1__1_/left_grid_pin_31_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[19] -to fpga_top/cby_1__1_/left_grid_pin_31_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[19] -to fpga_top/cby_1__1_/left_grid_pin_31_[0] 7.247000222e-11 diff --git a/FPGA1212_FLAT_HD_SKY_PNR/FPGA1212_FLAT_HD_SKY_Verilog/SDC/disable_configurable_memory_outputs.sdc b/FPGA1212_FLAT_HD_SKY_PNR/FPGA1212_FLAT_HD_SKY_Verilog/SDC/disable_configurable_memory_outputs.sdc deleted file mode 100644 index 8da07fe..0000000 --- a/FPGA1212_FLAT_HD_SKY_PNR/FPGA1212_FLAT_HD_SKY_Verilog/SDC/disable_configurable_memory_outputs.sdc +++ /dev/null @@ -1,127 +0,0 @@ -############################################# -# Synopsys Design Constraints (SDC) -# For FPGA fabric -# Description: Disable configurable memory outputs for PnR -# Author: Xifan TANG -# Organization: University of Utah -# Date: Sun Nov 29 02:09:07 2020 -############################################# - -set_disable_timing fpga_core_uut/sb_*__*_/mem_bottom_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q -set_disable_timing fpga_core_uut/sb_*__*_/mem_bottom_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q -set_disable_timing fpga_core_uut/sb_*__*_/mem_bottom_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q -set_disable_timing fpga_core_uut/sb_*__*_/mem_bottom_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q -set_disable_timing fpga_core_uut/sb_*__*_/mem_left_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q -set_disable_timing fpga_core_uut/sb_*__*_/mem_left_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q -set_disable_timing fpga_core_uut/sb_*__*_/mem_left_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q -set_disable_timing fpga_core_uut/sb_*__*_/mem_left_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q -set_disable_timing fpga_core_uut/cbx_*__*_/mem_bottom_ipin_*/sky*_fd_sc_hd__dfxtp_*_*_/Q -set_disable_timing fpga_core_uut/cbx_*__*_/mem_top_ipin_*/sky*_fd_sc_hd__dfxtp_*_*_/Q -set_disable_timing fpga_core_uut/cbx_*__*_/mem_top_ipin_*/sky*_fd_sc_hd__dfxtp_*_*_/Q -set_disable_timing fpga_core_uut/grid_io_top_top_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/EMBEDDED_IO_HD_sky*_fd_sc_hd__dfxtp_*_mem/sky*_fd_sc_hd__dfxtp_*_*_/Q -set_disable_timing fpga_core_uut/sb_*__*_/mem_right_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q -set_disable_timing fpga_core_uut/sb_*__*_/mem_right_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q -set_disable_timing fpga_core_uut/sb_*__*_/mem_right_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q -set_disable_timing fpga_core_uut/sb_*__*_/mem_right_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q -set_disable_timing fpga_core_uut/sb_*__*_/mem_right_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q -set_disable_timing fpga_core_uut/sb_*__*_/mem_right_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q -set_disable_timing fpga_core_uut/sb_*__*_/mem_bottom_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q -set_disable_timing fpga_core_uut/sb_*__*_/mem_bottom_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q -set_disable_timing fpga_core_uut/sb_*__*_/mem_bottom_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q -set_disable_timing fpga_core_uut/sb_*__*_/mem_bottom_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q -set_disable_timing fpga_core_uut/sb_*__*_/mem_left_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q -set_disable_timing fpga_core_uut/sb_*__*_/mem_left_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q -set_disable_timing fpga_core_uut/sb_*__*_/mem_left_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q -set_disable_timing fpga_core_uut/sb_*__*_/mem_left_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q -set_disable_timing fpga_core_uut/sb_*__*_/mem_left_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q -set_disable_timing fpga_core_uut/sb_*__*_/mem_right_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q -set_disable_timing fpga_core_uut/sb_*__*_/mem_right_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q -set_disable_timing fpga_core_uut/sb_*__*_/mem_right_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q -set_disable_timing fpga_core_uut/sb_*__*_/mem_right_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q -set_disable_timing fpga_core_uut/sb_*__*_/mem_bottom_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q -set_disable_timing fpga_core_uut/cby_*__*_/mem_right_ipin_*/sky*_fd_sc_hd__dfxtp_*_*_/Q -set_disable_timing fpga_core_uut/grid_io_left_left_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/EMBEDDED_IO_HD_sky*_fd_sc_hd__dfxtp_*_mem/sky*_fd_sc_hd__dfxtp_*_*_/Q -set_disable_timing fpga_core_uut/grid_clb_*__*_/logical_tile_clb_mode_clb__*/logical_tile_clb_mode_default__fle_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut*_*/frac_lut*_sky*_fd_sc_hd__dfxtp_*_mem/sky*_fd_sc_hd__dfxtp_*_*_/Q -set_disable_timing fpga_core_uut/grid_clb_*__*_/logical_tile_clb_mode_clb__*/logical_tile_clb_mode_default__fle_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_*/mem_frac_logic_out_*/sky*_fd_sc_hd__dfxtp_*_*_/Q -set_disable_timing fpga_core_uut/grid_clb_*__*_/logical_tile_clb_mode_clb__*/logical_tile_clb_mode_default__fle_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_*/mem_fabric_out_*/sky*_fd_sc_hd__dfxtp_*_*_/Q -set_disable_timing fpga_core_uut/grid_clb_*__*_/logical_tile_clb_mode_clb__*/logical_tile_clb_mode_default__fle_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_*/mem_ff_*_D_*/sky*_fd_sc_hd__dfxtp_*_*_/Q -set_disable_timing fpga_core_uut/cby_*__*_/mem_right_ipin_*/sky*_fd_sc_hd__dfxtp_*_*_/Q -set_disable_timing fpga_core_uut/cby_*__*_/mem_right_ipin_*/sky*_fd_sc_hd__dfxtp_*_*_/Q -set_disable_timing fpga_core_uut/cby_*__*_/mem_left_ipin_*/sky*_fd_sc_hd__dfxtp_*_*_/Q -set_disable_timing fpga_core_uut/cby_*__*_/mem_right_ipin_*/sky*_fd_sc_hd__dfxtp_*_*_/Q -set_disable_timing fpga_core_uut/cby_*__*_/mem_right_ipin_*/sky*_fd_sc_hd__dfxtp_*_*_/Q -set_disable_timing fpga_core_uut/grid_io_right_right_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/EMBEDDED_IO_HD_sky*_fd_sc_hd__dfxtp_*_mem/sky*_fd_sc_hd__dfxtp_*_*_/Q -set_disable_timing fpga_core_uut/sb_*__*_/mem_top_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q -set_disable_timing fpga_core_uut/sb_*__*_/mem_top_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q -set_disable_timing fpga_core_uut/sb_*__*_/mem_top_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q -set_disable_timing fpga_core_uut/sb_*__*_/mem_top_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q -set_disable_timing fpga_core_uut/sb_*__*_/mem_top_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q -set_disable_timing fpga_core_uut/sb_*__*_/mem_bottom_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q -set_disable_timing fpga_core_uut/sb_*__*_/mem_bottom_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q -set_disable_timing fpga_core_uut/sb_*__*_/mem_bottom_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q -set_disable_timing fpga_core_uut/sb_*__*_/mem_bottom_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q -set_disable_timing fpga_core_uut/sb_*__*_/mem_bottom_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q -set_disable_timing fpga_core_uut/sb_*__*_/mem_bottom_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q -set_disable_timing fpga_core_uut/sb_*__*_/mem_left_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q -set_disable_timing fpga_core_uut/sb_*__*_/mem_left_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q -set_disable_timing fpga_core_uut/sb_*__*_/mem_left_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q -set_disable_timing fpga_core_uut/sb_*__*_/mem_left_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q -set_disable_timing fpga_core_uut/cbx_*__*_/mem_top_ipin_*/sky*_fd_sc_hd__dfxtp_*_*_/Q -set_disable_timing fpga_core_uut/cbx_*__*_/mem_top_ipin_*/sky*_fd_sc_hd__dfxtp_*_*_/Q -set_disable_timing fpga_core_uut/sb_*__*_/mem_top_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q -set_disable_timing fpga_core_uut/sb_*__*_/mem_top_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q -set_disable_timing fpga_core_uut/sb_*__*_/mem_top_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q -set_disable_timing fpga_core_uut/sb_*__*_/mem_top_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q -set_disable_timing fpga_core_uut/sb_*__*_/mem_right_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q -set_disable_timing fpga_core_uut/sb_*__*_/mem_right_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q -set_disable_timing fpga_core_uut/sb_*__*_/mem_right_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q -set_disable_timing fpga_core_uut/sb_*__*_/mem_right_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q -set_disable_timing fpga_core_uut/sb_*__*_/mem_bottom_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q -set_disable_timing fpga_core_uut/sb_*__*_/mem_bottom_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q -set_disable_timing fpga_core_uut/sb_*__*_/mem_bottom_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q -set_disable_timing fpga_core_uut/sb_*__*_/mem_bottom_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q -set_disable_timing fpga_core_uut/sb_*__*_/mem_left_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q -set_disable_timing fpga_core_uut/sb_*__*_/mem_left_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q -set_disable_timing fpga_core_uut/sb_*__*_/mem_left_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q -set_disable_timing fpga_core_uut/sb_*__*_/mem_left_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q -set_disable_timing fpga_core_uut/sb_*__*_/mem_top_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q -set_disable_timing fpga_core_uut/sb_*__*_/mem_top_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q -set_disable_timing fpga_core_uut/sb_*__*_/mem_top_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q -set_disable_timing fpga_core_uut/sb_*__*_/mem_right_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q -set_disable_timing fpga_core_uut/sb_*__*_/mem_right_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q -set_disable_timing fpga_core_uut/sb_*__*_/mem_right_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q -set_disable_timing fpga_core_uut/sb_*__*_/mem_right_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q -set_disable_timing fpga_core_uut/sb_*__*_/mem_right_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q -set_disable_timing fpga_core_uut/sb_*__*_/mem_bottom_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q -set_disable_timing fpga_core_uut/sb_*__*_/mem_bottom_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q -set_disable_timing fpga_core_uut/sb_*__*_/mem_bottom_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q -set_disable_timing fpga_core_uut/sb_*__*_/mem_top_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q -set_disable_timing fpga_core_uut/sb_*__*_/mem_top_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q -set_disable_timing fpga_core_uut/sb_*__*_/mem_top_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q -set_disable_timing fpga_core_uut/sb_*__*_/mem_top_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q -set_disable_timing fpga_core_uut/sb_*__*_/mem_left_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q -set_disable_timing fpga_core_uut/sb_*__*_/mem_left_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q -set_disable_timing fpga_core_uut/sb_*__*_/mem_left_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q -set_disable_timing fpga_core_uut/sb_*__*_/mem_left_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q -set_disable_timing fpga_core_uut/cbx_*__*_/mem_top_ipin_*/sky*_fd_sc_hd__dfxtp_*_*_/Q -set_disable_timing fpga_core_uut/grid_io_bottom_bottom_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/EMBEDDED_IO_HD_sky*_fd_sc_hd__dfxtp_*_mem/sky*_fd_sc_hd__dfxtp_*_*_/Q -set_disable_timing fpga_core_uut/sb_*__*_/mem_top_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q -set_disable_timing fpga_core_uut/sb_*__*_/mem_top_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q -set_disable_timing fpga_core_uut/sb_*__*_/mem_top_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q -set_disable_timing fpga_core_uut/sb_*__*_/mem_top_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q -set_disable_timing fpga_core_uut/sb_*__*_/mem_top_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q -set_disable_timing fpga_core_uut/sb_*__*_/mem_right_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q -set_disable_timing fpga_core_uut/sb_*__*_/mem_right_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q -set_disable_timing fpga_core_uut/sb_*__*_/mem_right_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q -set_disable_timing fpga_core_uut/sb_*__*_/mem_right_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q -set_disable_timing fpga_core_uut/sb_*__*_/mem_right_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q -set_disable_timing fpga_core_uut/sb_*__*_/mem_left_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q -set_disable_timing fpga_core_uut/sb_*__*_/mem_left_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q -set_disable_timing fpga_core_uut/sb_*__*_/mem_left_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q -set_disable_timing fpga_core_uut/sb_*__*_/mem_left_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q -set_disable_timing fpga_core_uut/sb_*__*_/mem_left_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q -set_disable_timing fpga_core_uut/sb_*__*_/mem_top_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q -set_disable_timing fpga_core_uut/sb_*__*_/mem_right_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q -set_disable_timing fpga_core_uut/sb_*__*_/mem_right_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q -set_disable_timing fpga_core_uut/sb_*__*_/mem_right_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q -set_disable_timing fpga_core_uut/sb_*__*_/mem_right_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q diff --git a/FPGA1212_FLAT_HD_SKY_PNR/FPGA1212_FLAT_HD_SKY_Verilog/SDC/disable_routing_multiplexer_outputs.sdc b/FPGA1212_FLAT_HD_SKY_PNR/FPGA1212_FLAT_HD_SKY_Verilog/SDC/disable_routing_multiplexer_outputs.sdc deleted file mode 100644 index f785ffc..0000000 --- a/FPGA1212_FLAT_HD_SKY_PNR/FPGA1212_FLAT_HD_SKY_Verilog/SDC/disable_routing_multiplexer_outputs.sdc +++ /dev/null @@ -1,122 +0,0 @@ -############################################# -# Synopsys Design Constraints (SDC) -# For FPGA fabric -# Description: Disable routing multiplexer outputs for PnR -# Author: Xifan TANG -# Organization: University of Utah -# Date: Sun Nov 29 02:09:07 2020 -############################################# - -set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/out -set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/out -set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/out -set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/out -set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/out -set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/out -set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/out -set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/out -set_disable_timing fpga_core_uut/cbx_*__*_/mux_top_ipin_*/out -set_disable_timing fpga_core_uut/cbx_*__*_/mux_top_ipin_*/out -set_disable_timing fpga_core_uut/cbx_*__*_/mux_bottom_ipin_*/out -set_disable_timing fpga_core_uut/cbx_*__*_/mux_top_ipin_*/out -set_disable_timing fpga_core_uut/cby_*__*_/mux_right_ipin_*/out -set_disable_timing fpga_core_uut/cby_*__*_/mux_right_ipin_*/out -set_disable_timing fpga_core_uut/cby_*__*_/mux_left_ipin_*/out -set_disable_timing fpga_core_uut/cby_*__*_/mux_right_ipin_*/out -set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/out -set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/out -set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/out -set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/out -set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/out -set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/out -set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/out -set_disable_timing fpga_core_uut/cbx_*__*_/mux_top_ipin_*/out -set_disable_timing fpga_core_uut/cbx_*__*_/mux_top_ipin_*/out -set_disable_timing fpga_core_uut/cby_*__*_/mux_right_ipin_*/out -set_disable_timing fpga_core_uut/cby_*__*_/mux_right_ipin_*/out -set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/out -set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/out -set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/out -set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/out -set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/out -set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/out -set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/out -set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/out -set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/out -set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/out -set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/out -set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/out -set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/out -set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/out -set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/out -set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/out -set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/out -set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/out -set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/out -set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/out -set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/out -set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/out -set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/out -set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/out -set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/out -set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/out -set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/out -set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/out -set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/out -set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/out -set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/out -set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/out -set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/out -set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/out -set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/out -set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/out -set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/out -set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/out -set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/out -set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/out -set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/out -set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/out -set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/out -set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/out -set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/out -set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/out -set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/out -set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/out -set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/out -set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/out -set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/out -set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/out -set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/out -set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/out -set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/out -set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/out -set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/out -set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/out -set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/out -set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/out -set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/out -set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/out -set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/out -set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/out -set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/out -set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/out -set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/out -set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/out -set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/out -set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/out -set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/out -set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/out -set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/out -set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/out -set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/out -set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/out -set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/out -set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/out -set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/out -set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/out -set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/out -set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/out -set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/out -set_disable_timing fpga_core_uut/grid_clb_*__*_/logical_tile_clb_mode_clb__*/logical_tile_clb_mode_default__fle_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_*/mux_frac_logic_out_*/out -set_disable_timing fpga_core_uut/grid_clb_*__*_/logical_tile_clb_mode_clb__*/logical_tile_clb_mode_default__fle_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_*/mux_fabric_out_*/out -set_disable_timing fpga_core_uut/grid_clb_*__*_/logical_tile_clb_mode_clb__*/logical_tile_clb_mode_default__fle_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_*/mux_ff_*_D_*/out diff --git a/FPGA1212_FLAT_HD_SKY_PNR/FPGA1212_FLAT_HD_SKY_Verilog/SDC/disable_sb_outputs.sdc b/FPGA1212_FLAT_HD_SKY_PNR/FPGA1212_FLAT_HD_SKY_Verilog/SDC/disable_sb_outputs.sdc deleted file mode 100644 index 13c97d4..0000000 --- a/FPGA1212_FLAT_HD_SKY_PNR/FPGA1212_FLAT_HD_SKY_Verilog/SDC/disable_sb_outputs.sdc +++ /dev/null @@ -1,75 +0,0 @@ -############################################# -# Synopsys Design Constraints (SDC) -# For FPGA fabric -# Description: Disable Switch Block outputs for PnR -# Author: Xifan TANG -# Organization: University of Utah -# Date: Sun Nov 29 02:09:07 2020 -############################################# - -set_disable_timing fpga_core_uut/sb_*__*_/chany_top_out - -set_disable_timing fpga_core_uut/sb_*__*_/chanx_right_out - -set_disable_timing fpga_core_uut/sb_*__*_/ccff_tail - -set_disable_timing fpga_core_uut/sb_*__*_/chany_top_out - -set_disable_timing fpga_core_uut/sb_*__*_/chanx_right_out - -set_disable_timing fpga_core_uut/sb_*__*_/chany_bottom_out - -set_disable_timing fpga_core_uut/sb_*__*_/ccff_tail - -set_disable_timing fpga_core_uut/sb_*__*_/chanx_right_out - -set_disable_timing fpga_core_uut/sb_*__*_/chany_bottom_out - -set_disable_timing fpga_core_uut/sb_*__*_/ccff_tail - -set_disable_timing fpga_core_uut/sb_*__*_/chany_top_out - -set_disable_timing fpga_core_uut/sb_*__*_/chanx_right_out - -set_disable_timing fpga_core_uut/sb_*__*_/chanx_left_out - -set_disable_timing fpga_core_uut/sb_*__*_/ccff_tail - -set_disable_timing fpga_core_uut/sb_*__*_/chany_top_out - -set_disable_timing fpga_core_uut/sb_*__*_/chanx_right_out - -set_disable_timing fpga_core_uut/sb_*__*_/chany_bottom_out - -set_disable_timing fpga_core_uut/sb_*__*_/chanx_left_out - -set_disable_timing fpga_core_uut/sb_*__*_/ccff_tail - -set_disable_timing fpga_core_uut/sb_*__*_/chanx_right_out - -set_disable_timing fpga_core_uut/sb_*__*_/chany_bottom_out - -set_disable_timing fpga_core_uut/sb_*__*_/chanx_left_out - -set_disable_timing fpga_core_uut/sb_*__*_/ccff_tail - -set_disable_timing fpga_core_uut/sb_*__*_/chany_top_out - -set_disable_timing fpga_core_uut/sb_*__*_/chanx_left_out - -set_disable_timing fpga_core_uut/sb_*__*_/ccff_tail - -set_disable_timing fpga_core_uut/sb_*__*_/chany_top_out - -set_disable_timing fpga_core_uut/sb_*__*_/chany_bottom_out - -set_disable_timing fpga_core_uut/sb_*__*_/chanx_left_out - -set_disable_timing fpga_core_uut/sb_*__*_/ccff_tail - -set_disable_timing fpga_core_uut/sb_*__*_/chany_bottom_out - -set_disable_timing fpga_core_uut/sb_*__*_/chanx_left_out - -set_disable_timing fpga_core_uut/sb_*__*_/ccff_tail - diff --git a/FPGA1212_FLAT_HD_SKY_PNR/FPGA1212_FLAT_HD_SKY_Verilog/SDC/global_ports.sdc b/FPGA1212_FLAT_HD_SKY_PNR/FPGA1212_FLAT_HD_SKY_Verilog/SDC/global_ports.sdc deleted file mode 100644 index 990109f..0000000 --- a/FPGA1212_FLAT_HD_SKY_PNR/FPGA1212_FLAT_HD_SKY_Verilog/SDC/global_ports.sdc +++ /dev/null @@ -1,17 +0,0 @@ -############################################# -# Synopsys Design Constraints (SDC) -# For FPGA fabric -# Description: Clock contraints for PnR -# Author: Xifan TANG -# Organization: University of Utah -# Date: Sun Nov 29 02:09:07 2020 -############################################# - -################################################## -# Create programmable clock -################################################## -create_clock -name prog_clk[0] -period 9.999999939e-09 -waveform {0 4.99999997e-09} [get_ports {prog_clk[0]}] -################################################## -# Create clock -################################################## -create_clock -name clk[0] -period 1.110371906e-09 -waveform {0 5.551859528e-10} [get_ports {clk[0]}] diff --git a/FPGA1212_FLAT_HD_SKY_PNR/FPGA1212_FLAT_HD_SKY_Verilog/SDC/logical_tile_clb_mode_clb_.sdc b/FPGA1212_FLAT_HD_SKY_PNR/FPGA1212_FLAT_HD_SKY_Verilog/SDC/logical_tile_clb_mode_clb_.sdc deleted file mode 100644 index 92d66d1..0000000 --- a/FPGA1212_FLAT_HD_SKY_PNR/FPGA1212_FLAT_HD_SKY_Verilog/SDC/logical_tile_clb_mode_clb_.sdc +++ /dev/null @@ -1,16 +0,0 @@ -############################################# -# Synopsys Design Constraints (SDC) -# For FPGA fabric -# Description: Timing constraints for Grid logical_tile_clb_mode_clb_ in PnR -# Author: Xifan TANG -# Organization: University of Utah -# Date: Sun Nov 29 02:09:07 2020 -############################################# - -############################################# -# Define time unit -############################################# -set_units -time s - -set_max_delay -from fpga_core_uut/grid_clb/logical_tile_clb_mode_clb__0_/clb_reg_in[0] -to fpga_top/grid_clb/logical_tile_clb_mode_default__fle_0/fle_reg_in[0] 1.599999994e-10 -set_max_delay -from fpga_core_uut/grid_clb/logical_tile_clb_mode_clb__0_/clb_sc_in[0] -to fpga_top/grid_clb/logical_tile_clb_mode_default__fle_0/fle_sc_in[0] 1.599999994e-10 diff --git a/FPGA1212_FLAT_HD_SKY_PNR/FPGA1212_FLAT_HD_SKY_Verilog/SDC/logical_tile_clb_mode_default__fle.sdc b/FPGA1212_FLAT_HD_SKY_PNR/FPGA1212_FLAT_HD_SKY_Verilog/SDC/logical_tile_clb_mode_default__fle.sdc deleted file mode 100644 index 77bc245..0000000 --- a/FPGA1212_FLAT_HD_SKY_PNR/FPGA1212_FLAT_HD_SKY_Verilog/SDC/logical_tile_clb_mode_default__fle.sdc +++ /dev/null @@ -1,14 +0,0 @@ -############################################# -# Synopsys Design Constraints (SDC) -# For FPGA fabric -# Description: Timing constraints for Grid logical_tile_clb_mode_default__fle in PnR -# Author: Xifan TANG -# Organization: University of Utah -# Date: Sun Nov 29 02:09:07 2020 -############################################# - -############################################# -# Define time unit -############################################# -set_units -time s - diff --git a/FPGA1212_FLAT_HD_SKY_PNR/FPGA1212_FLAT_HD_SKY_Verilog/SDC/logical_tile_clb_mode_default__fle_mode_physical__fabric.sdc b/FPGA1212_FLAT_HD_SKY_PNR/FPGA1212_FLAT_HD_SKY_Verilog/SDC/logical_tile_clb_mode_default__fle_mode_physical__fabric.sdc deleted file mode 100644 index 207d32a..0000000 --- a/FPGA1212_FLAT_HD_SKY_PNR/FPGA1212_FLAT_HD_SKY_Verilog/SDC/logical_tile_clb_mode_default__fle_mode_physical__fabric.sdc +++ /dev/null @@ -1,22 +0,0 @@ -############################################# -# Synopsys Design Constraints (SDC) -# For FPGA fabric -# Description: Timing constraints for Grid logical_tile_clb_mode_default__fle_mode_physical__fabric in PnR -# Author: Xifan TANG -# Organization: University of Utah -# Date: Sun Nov 29 02:09:07 2020 -############################################# - -############################################# -# Define time unit -############################################# -set_units -time s - -set_max_delay -from fpga_core_uut/grid_clb/fle/fabric/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0/ff_Q[0] -to fpga_top/grid_clb/fle/fabric/logical_tile_clb_mode_default__fle_mode_physical__fabric_0_/fabric_out[0] 4.500000025e-11 -set_max_delay -from fpga_core_uut/grid_clb/fle/fabric/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/frac_logic_out[0] -to fpga_top/grid_clb/fle/fabric/logical_tile_clb_mode_default__fle_mode_physical__fabric_0_/fabric_out[0] 2.500000033e-11 -set_max_delay -from fpga_core_uut/grid_clb/fle/fabric/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1/ff_Q[0] -to fpga_top/grid_clb/fle/fabric/logical_tile_clb_mode_default__fle_mode_physical__fabric_0_/fabric_out[1] 4.500000025e-11 -set_max_delay -from fpga_core_uut/grid_clb/fle/fabric/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/frac_logic_out[1] -to fpga_top/grid_clb/fle/fabric/logical_tile_clb_mode_default__fle_mode_physical__fabric_0_/fabric_out[1] 2.500000033e-11 -set_max_delay -from fpga_core_uut/grid_clb/fle/fabric/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/frac_logic_out[0] -to fpga_top/grid_clb/fle/fabric/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0/ff_D[0] 2.500000033e-11 -set_max_delay -from fpga_core_uut/grid_clb/fle/fabric/logical_tile_clb_mode_default__fle_mode_physical__fabric_0_/fabric_reg_in[0] -to fpga_top/grid_clb/fle/fabric/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0/ff_D[0] 4.500000025e-11 -set_max_delay -from fpga_core_uut/grid_clb/fle/fabric/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/frac_logic_out[1] -to fpga_top/grid_clb/fle/fabric/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1/ff_D[0] 2.500000033e-11 -set_max_delay -from fpga_core_uut/grid_clb/fle/fabric/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0/ff_Q[0] -to fpga_top/grid_clb/fle/fabric/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1/ff_D[0] 4.500000025e-11 diff --git a/FPGA1212_FLAT_HD_SKY_PNR/FPGA1212_FLAT_HD_SKY_Verilog/SDC/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff.sdc b/FPGA1212_FLAT_HD_SKY_PNR/FPGA1212_FLAT_HD_SKY_Verilog/SDC/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff.sdc deleted file mode 100644 index d681f4c..0000000 --- a/FPGA1212_FLAT_HD_SKY_PNR/FPGA1212_FLAT_HD_SKY_Verilog/SDC/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff.sdc +++ /dev/null @@ -1,14 +0,0 @@ -############################################# -# Synopsys Design Constraints (SDC) -# For FPGA fabric -# Description: Timing constraints for Grid logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff in PnR -# Author: Xifan TANG -# Organization: University of Utah -# Date: Sun Nov 29 02:09:07 2020 -############################################# - -############################################# -# Define time unit -############################################# -set_units -time s - diff --git a/FPGA1212_FLAT_HD_SKY_PNR/FPGA1212_FLAT_HD_SKY_Verilog/SDC/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic.sdc b/FPGA1212_FLAT_HD_SKY_PNR/FPGA1212_FLAT_HD_SKY_Verilog/SDC/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic.sdc deleted file mode 100644 index 993d28b..0000000 --- a/FPGA1212_FLAT_HD_SKY_PNR/FPGA1212_FLAT_HD_SKY_Verilog/SDC/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic.sdc +++ /dev/null @@ -1,14 +0,0 @@ -############################################# -# Synopsys Design Constraints (SDC) -# For FPGA fabric -# Description: Timing constraints for Grid logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic in PnR -# Author: Xifan TANG -# Organization: University of Utah -# Date: Sun Nov 29 02:09:07 2020 -############################################# - -############################################# -# Define time unit -############################################# -set_units -time s - diff --git a/FPGA1212_FLAT_HD_SKY_PNR/FPGA1212_FLAT_HD_SKY_Verilog/SDC/logical_tile_io_mode_io_.sdc b/FPGA1212_FLAT_HD_SKY_PNR/FPGA1212_FLAT_HD_SKY_Verilog/SDC/logical_tile_io_mode_io_.sdc deleted file mode 100644 index cdd5327..0000000 --- a/FPGA1212_FLAT_HD_SKY_PNR/FPGA1212_FLAT_HD_SKY_Verilog/SDC/logical_tile_io_mode_io_.sdc +++ /dev/null @@ -1,16 +0,0 @@ -############################################# -# Synopsys Design Constraints (SDC) -# For FPGA fabric -# Description: Timing constraints for Grid logical_tile_io_mode_io_ in PnR -# Author: Xifan TANG -# Organization: University of Utah -# Date: Sun Nov 29 02:09:07 2020 -############################################# - -############################################# -# Define time unit -############################################# -set_units -time s - -set_max_delay -from fpga_core_uut/grid_io_left_left/logical_tile_io_mode_physical__iopad_0/iopad_inpad[0] -to fpga_top/grid_io_left_left/logical_tile_io_mode_io__0_/io_inpad[0] 4.243000049e-11 -set_max_delay -from fpga_core_uut/grid_io_left_left/logical_tile_io_mode_io__0_/io_outpad[0] -to fpga_top/grid_io_left_left/logical_tile_io_mode_physical__iopad_0/iopad_outpad[0] 1.39400002e-11 diff --git a/FPGA1212_FLAT_HD_SKY_PNR/FPGA1212_FLAT_HD_SKY_Verilog/SDC/sb_0__0_.sdc b/FPGA1212_FLAT_HD_SKY_PNR/FPGA1212_FLAT_HD_SKY_Verilog/SDC/sb_0__0_.sdc deleted file mode 100644 index 3b4882a..0000000 --- a/FPGA1212_FLAT_HD_SKY_PNR/FPGA1212_FLAT_HD_SKY_Verilog/SDC/sb_0__0_.sdc +++ /dev/null @@ -1,94 +0,0 @@ -############################################# -# Synopsys Design Constraints (SDC) -# For FPGA fabric -# Description: Constrain timing of Switch Block sb_0__0_ for PnR -# Author: Xifan TANG -# Organization: University of Utah -# Date: Sun Nov 29 02:09:07 2020 -############################################# - -############################################# -# Define time unit -############################################# -set_units -time s - -set_max_delay -from fpga_core_uut/sb_0__0_/top_left_grid_pin_1_[0] -to fpga_top/sb_0__0_/chany_top_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__0_/chanx_right_in[1] -to fpga_top/sb_0__0_/chany_top_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__0_/chanx_right_in[2] -to fpga_top/sb_0__0_/chany_top_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__0_/top_left_grid_pin_1_[0] -to fpga_top/sb_0__0_/chany_top_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__0_/chanx_right_in[3] -to fpga_top/sb_0__0_/chany_top_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__0_/chanx_right_in[4] -to fpga_top/sb_0__0_/chany_top_out[3] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__0_/top_left_grid_pin_1_[0] -to fpga_top/sb_0__0_/chany_top_out[4] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__0_/chanx_right_in[5] -to fpga_top/sb_0__0_/chany_top_out[4] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__0_/chanx_right_in[6] -to fpga_top/sb_0__0_/chany_top_out[5] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__0_/chanx_right_in[7] -to fpga_top/sb_0__0_/chany_top_out[6] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__0_/chanx_right_in[8] -to fpga_top/sb_0__0_/chany_top_out[7] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__0_/chanx_right_in[9] -to fpga_top/sb_0__0_/chany_top_out[8] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__0_/chanx_right_in[10] -to fpga_top/sb_0__0_/chany_top_out[9] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__0_/chanx_right_in[11] -to fpga_top/sb_0__0_/chany_top_out[10] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__0_/chanx_right_in[12] -to fpga_top/sb_0__0_/chany_top_out[11] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__0_/top_left_grid_pin_1_[0] -to fpga_top/sb_0__0_/chany_top_out[12] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__0_/chanx_right_in[13] -to fpga_top/sb_0__0_/chany_top_out[12] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__0_/chanx_right_in[14] -to fpga_top/sb_0__0_/chany_top_out[13] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__0_/chanx_right_in[15] -to fpga_top/sb_0__0_/chany_top_out[14] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__0_/chanx_right_in[16] -to fpga_top/sb_0__0_/chany_top_out[15] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__0_/chanx_right_in[17] -to fpga_top/sb_0__0_/chany_top_out[16] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__0_/chanx_right_in[18] -to fpga_top/sb_0__0_/chany_top_out[17] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__0_/chanx_right_in[19] -to fpga_top/sb_0__0_/chany_top_out[18] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__0_/chanx_right_in[0] -to fpga_top/sb_0__0_/chany_top_out[19] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__0_/chany_top_in[19] -to fpga_top/sb_0__0_/chanx_right_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_1_[0] -to fpga_top/sb_0__0_/chanx_right_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_5_[0] -to fpga_top/sb_0__0_/chanx_right_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_9_[0] -to fpga_top/sb_0__0_/chanx_right_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_13_[0] -to fpga_top/sb_0__0_/chanx_right_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_17_[0] -to fpga_top/sb_0__0_/chanx_right_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__0_/chany_top_in[0] -to fpga_top/sb_0__0_/chanx_right_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_3_[0] -to fpga_top/sb_0__0_/chanx_right_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_7_[0] -to fpga_top/sb_0__0_/chanx_right_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_11_[0] -to fpga_top/sb_0__0_/chanx_right_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_15_[0] -to fpga_top/sb_0__0_/chanx_right_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__0_/chany_top_in[1] -to fpga_top/sb_0__0_/chanx_right_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_1_[0] -to fpga_top/sb_0__0_/chanx_right_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_5_[0] -to fpga_top/sb_0__0_/chanx_right_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_9_[0] -to fpga_top/sb_0__0_/chanx_right_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_13_[0] -to fpga_top/sb_0__0_/chanx_right_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_17_[0] -to fpga_top/sb_0__0_/chanx_right_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__0_/chany_top_in[2] -to fpga_top/sb_0__0_/chanx_right_out[3] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_3_[0] -to fpga_top/sb_0__0_/chanx_right_out[3] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_7_[0] -to fpga_top/sb_0__0_/chanx_right_out[3] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_11_[0] -to fpga_top/sb_0__0_/chanx_right_out[3] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_15_[0] -to fpga_top/sb_0__0_/chanx_right_out[3] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__0_/chany_top_in[3] -to fpga_top/sb_0__0_/chanx_right_out[4] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_1_[0] -to fpga_top/sb_0__0_/chanx_right_out[4] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_17_[0] -to fpga_top/sb_0__0_/chanx_right_out[4] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__0_/chany_top_in[4] -to fpga_top/sb_0__0_/chanx_right_out[5] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_3_[0] -to fpga_top/sb_0__0_/chanx_right_out[5] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__0_/chany_top_in[5] -to fpga_top/sb_0__0_/chanx_right_out[6] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_5_[0] -to fpga_top/sb_0__0_/chanx_right_out[6] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__0_/chany_top_in[6] -to fpga_top/sb_0__0_/chanx_right_out[7] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_7_[0] -to fpga_top/sb_0__0_/chanx_right_out[7] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__0_/chany_top_in[7] -to fpga_top/sb_0__0_/chanx_right_out[8] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_9_[0] -to fpga_top/sb_0__0_/chanx_right_out[8] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__0_/chany_top_in[8] -to fpga_top/sb_0__0_/chanx_right_out[9] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_11_[0] -to fpga_top/sb_0__0_/chanx_right_out[9] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__0_/chany_top_in[9] -to fpga_top/sb_0__0_/chanx_right_out[10] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_13_[0] -to fpga_top/sb_0__0_/chanx_right_out[10] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__0_/chany_top_in[10] -to fpga_top/sb_0__0_/chanx_right_out[11] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_15_[0] -to fpga_top/sb_0__0_/chanx_right_out[11] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__0_/chany_top_in[11] -to fpga_top/sb_0__0_/chanx_right_out[12] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_1_[0] -to fpga_top/sb_0__0_/chanx_right_out[12] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_17_[0] -to fpga_top/sb_0__0_/chanx_right_out[12] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__0_/chany_top_in[12] -to fpga_top/sb_0__0_/chanx_right_out[13] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_3_[0] -to fpga_top/sb_0__0_/chanx_right_out[13] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__0_/chany_top_in[13] -to fpga_top/sb_0__0_/chanx_right_out[14] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_5_[0] -to fpga_top/sb_0__0_/chanx_right_out[14] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__0_/chany_top_in[14] -to fpga_top/sb_0__0_/chanx_right_out[15] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_7_[0] -to fpga_top/sb_0__0_/chanx_right_out[15] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__0_/chany_top_in[15] -to fpga_top/sb_0__0_/chanx_right_out[16] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_9_[0] -to fpga_top/sb_0__0_/chanx_right_out[16] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__0_/chany_top_in[16] -to fpga_top/sb_0__0_/chanx_right_out[17] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_11_[0] -to fpga_top/sb_0__0_/chanx_right_out[17] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__0_/chany_top_in[17] -to fpga_top/sb_0__0_/chanx_right_out[18] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_13_[0] -to fpga_top/sb_0__0_/chanx_right_out[18] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__0_/chany_top_in[18] -to fpga_top/sb_0__0_/chanx_right_out[19] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_15_[0] -to fpga_top/sb_0__0_/chanx_right_out[19] 6.020400151e-11 diff --git a/FPGA1212_FLAT_HD_SKY_PNR/FPGA1212_FLAT_HD_SKY_Verilog/SDC/sb_0__12_.sdc b/FPGA1212_FLAT_HD_SKY_PNR/FPGA1212_FLAT_HD_SKY_Verilog/SDC/sb_0__12_.sdc deleted file mode 100644 index acc213d..0000000 --- a/FPGA1212_FLAT_HD_SKY_PNR/FPGA1212_FLAT_HD_SKY_Verilog/SDC/sb_0__12_.sdc +++ /dev/null @@ -1,94 +0,0 @@ -############################################# -# Synopsys Design Constraints (SDC) -# For FPGA fabric -# Description: Constrain timing of Switch Block sb_0__12_ for PnR -# Author: Xifan TANG -# Organization: University of Utah -# Date: Sun Nov 29 02:09:07 2020 -############################################# - -############################################# -# Define time unit -############################################# -set_units -time s - -set_max_delay -from fpga_core_uut/sb_0__12_/right_top_grid_pin_1_[0] -to fpga_top/sb_0__12_/chanx_right_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__12_/right_bottom_grid_pin_35_[0] -to fpga_top/sb_0__12_/chanx_right_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__12_/right_bottom_grid_pin_37_[0] -to fpga_top/sb_0__12_/chanx_right_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__12_/right_bottom_grid_pin_39_[0] -to fpga_top/sb_0__12_/chanx_right_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__12_/right_bottom_grid_pin_41_[0] -to fpga_top/sb_0__12_/chanx_right_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__12_/chany_bottom_in[18] -to fpga_top/sb_0__12_/chanx_right_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__12_/right_bottom_grid_pin_34_[0] -to fpga_top/sb_0__12_/chanx_right_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__12_/right_bottom_grid_pin_36_[0] -to fpga_top/sb_0__12_/chanx_right_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__12_/right_bottom_grid_pin_38_[0] -to fpga_top/sb_0__12_/chanx_right_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__12_/right_bottom_grid_pin_40_[0] -to fpga_top/sb_0__12_/chanx_right_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__12_/chany_bottom_in[17] -to fpga_top/sb_0__12_/chanx_right_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__12_/right_top_grid_pin_1_[0] -to fpga_top/sb_0__12_/chanx_right_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__12_/right_bottom_grid_pin_35_[0] -to fpga_top/sb_0__12_/chanx_right_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__12_/right_bottom_grid_pin_37_[0] -to fpga_top/sb_0__12_/chanx_right_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__12_/right_bottom_grid_pin_39_[0] -to fpga_top/sb_0__12_/chanx_right_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__12_/right_bottom_grid_pin_41_[0] -to fpga_top/sb_0__12_/chanx_right_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__12_/chany_bottom_in[16] -to fpga_top/sb_0__12_/chanx_right_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__12_/right_bottom_grid_pin_34_[0] -to fpga_top/sb_0__12_/chanx_right_out[3] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__12_/right_bottom_grid_pin_36_[0] -to fpga_top/sb_0__12_/chanx_right_out[3] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__12_/right_bottom_grid_pin_38_[0] -to fpga_top/sb_0__12_/chanx_right_out[3] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__12_/right_bottom_grid_pin_40_[0] -to fpga_top/sb_0__12_/chanx_right_out[3] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__12_/chany_bottom_in[15] -to fpga_top/sb_0__12_/chanx_right_out[3] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__12_/right_top_grid_pin_1_[0] -to fpga_top/sb_0__12_/chanx_right_out[4] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__12_/right_bottom_grid_pin_41_[0] -to fpga_top/sb_0__12_/chanx_right_out[4] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__12_/chany_bottom_in[14] -to fpga_top/sb_0__12_/chanx_right_out[4] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__12_/right_bottom_grid_pin_34_[0] -to fpga_top/sb_0__12_/chanx_right_out[5] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__12_/chany_bottom_in[13] -to fpga_top/sb_0__12_/chanx_right_out[5] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__12_/right_bottom_grid_pin_35_[0] -to fpga_top/sb_0__12_/chanx_right_out[6] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__12_/chany_bottom_in[12] -to fpga_top/sb_0__12_/chanx_right_out[6] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__12_/right_bottom_grid_pin_36_[0] -to fpga_top/sb_0__12_/chanx_right_out[7] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__12_/chany_bottom_in[11] -to fpga_top/sb_0__12_/chanx_right_out[7] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__12_/right_bottom_grid_pin_37_[0] -to fpga_top/sb_0__12_/chanx_right_out[8] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__12_/chany_bottom_in[10] -to fpga_top/sb_0__12_/chanx_right_out[8] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__12_/right_bottom_grid_pin_38_[0] -to fpga_top/sb_0__12_/chanx_right_out[9] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__12_/chany_bottom_in[9] -to fpga_top/sb_0__12_/chanx_right_out[9] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__12_/right_bottom_grid_pin_39_[0] -to fpga_top/sb_0__12_/chanx_right_out[10] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__12_/chany_bottom_in[8] -to fpga_top/sb_0__12_/chanx_right_out[10] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__12_/right_bottom_grid_pin_40_[0] -to fpga_top/sb_0__12_/chanx_right_out[11] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__12_/chany_bottom_in[7] -to fpga_top/sb_0__12_/chanx_right_out[11] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__12_/right_top_grid_pin_1_[0] -to fpga_top/sb_0__12_/chanx_right_out[12] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__12_/right_bottom_grid_pin_41_[0] -to fpga_top/sb_0__12_/chanx_right_out[12] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__12_/chany_bottom_in[6] -to fpga_top/sb_0__12_/chanx_right_out[12] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__12_/right_bottom_grid_pin_34_[0] -to fpga_top/sb_0__12_/chanx_right_out[13] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__12_/chany_bottom_in[5] -to fpga_top/sb_0__12_/chanx_right_out[13] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__12_/right_bottom_grid_pin_35_[0] -to fpga_top/sb_0__12_/chanx_right_out[14] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__12_/chany_bottom_in[4] -to fpga_top/sb_0__12_/chanx_right_out[14] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__12_/right_bottom_grid_pin_36_[0] -to fpga_top/sb_0__12_/chanx_right_out[15] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__12_/chany_bottom_in[3] -to fpga_top/sb_0__12_/chanx_right_out[15] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__12_/right_bottom_grid_pin_37_[0] -to fpga_top/sb_0__12_/chanx_right_out[16] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__12_/chany_bottom_in[2] -to fpga_top/sb_0__12_/chanx_right_out[16] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__12_/right_bottom_grid_pin_38_[0] -to fpga_top/sb_0__12_/chanx_right_out[17] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__12_/chany_bottom_in[1] -to fpga_top/sb_0__12_/chanx_right_out[17] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__12_/right_bottom_grid_pin_39_[0] -to fpga_top/sb_0__12_/chanx_right_out[18] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__12_/chany_bottom_in[0] -to fpga_top/sb_0__12_/chanx_right_out[18] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__12_/right_bottom_grid_pin_40_[0] -to fpga_top/sb_0__12_/chanx_right_out[19] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__12_/chany_bottom_in[19] -to fpga_top/sb_0__12_/chanx_right_out[19] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__12_/chanx_right_in[18] -to fpga_top/sb_0__12_/chany_bottom_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__12_/bottom_left_grid_pin_1_[0] -to fpga_top/sb_0__12_/chany_bottom_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__12_/chanx_right_in[17] -to fpga_top/sb_0__12_/chany_bottom_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__12_/chanx_right_in[16] -to fpga_top/sb_0__12_/chany_bottom_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__12_/bottom_left_grid_pin_1_[0] -to fpga_top/sb_0__12_/chany_bottom_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__12_/chanx_right_in[15] -to fpga_top/sb_0__12_/chany_bottom_out[3] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__12_/chanx_right_in[14] -to fpga_top/sb_0__12_/chany_bottom_out[4] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__12_/bottom_left_grid_pin_1_[0] -to fpga_top/sb_0__12_/chany_bottom_out[4] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__12_/chanx_right_in[13] -to fpga_top/sb_0__12_/chany_bottom_out[5] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__12_/chanx_right_in[12] -to fpga_top/sb_0__12_/chany_bottom_out[6] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__12_/chanx_right_in[11] -to fpga_top/sb_0__12_/chany_bottom_out[7] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__12_/chanx_right_in[10] -to fpga_top/sb_0__12_/chany_bottom_out[8] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__12_/chanx_right_in[9] -to fpga_top/sb_0__12_/chany_bottom_out[9] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__12_/chanx_right_in[8] -to fpga_top/sb_0__12_/chany_bottom_out[10] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__12_/chanx_right_in[7] -to fpga_top/sb_0__12_/chany_bottom_out[11] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__12_/chanx_right_in[6] -to fpga_top/sb_0__12_/chany_bottom_out[12] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__12_/bottom_left_grid_pin_1_[0] -to fpga_top/sb_0__12_/chany_bottom_out[12] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__12_/chanx_right_in[5] -to fpga_top/sb_0__12_/chany_bottom_out[13] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__12_/chanx_right_in[4] -to fpga_top/sb_0__12_/chany_bottom_out[14] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__12_/chanx_right_in[3] -to fpga_top/sb_0__12_/chany_bottom_out[15] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__12_/chanx_right_in[2] -to fpga_top/sb_0__12_/chany_bottom_out[16] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__12_/chanx_right_in[1] -to fpga_top/sb_0__12_/chany_bottom_out[17] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__12_/chanx_right_in[0] -to fpga_top/sb_0__12_/chany_bottom_out[18] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__12_/chanx_right_in[19] -to fpga_top/sb_0__12_/chany_bottom_out[19] 6.020400151e-11 diff --git a/FPGA1212_FLAT_HD_SKY_PNR/FPGA1212_FLAT_HD_SKY_Verilog/SDC/sb_0__1_.sdc b/FPGA1212_FLAT_HD_SKY_PNR/FPGA1212_FLAT_HD_SKY_Verilog/SDC/sb_0__1_.sdc deleted file mode 100644 index 5bcfcf7..0000000 --- a/FPGA1212_FLAT_HD_SKY_PNR/FPGA1212_FLAT_HD_SKY_Verilog/SDC/sb_0__1_.sdc +++ /dev/null @@ -1,158 +0,0 @@ -############################################# -# Synopsys Design Constraints (SDC) -# For FPGA fabric -# Description: Constrain timing of Switch Block sb_0__1_ for PnR -# Author: Xifan TANG -# Organization: University of Utah -# Date: Sun Nov 29 02:09:07 2020 -############################################# - -############################################# -# Define time unit -############################################# -set_units -time s - -set_max_delay -from fpga_core_uut/sb_0__1_/top_left_grid_pin_1_[0] -to fpga_top/sb_0__1_/chany_top_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[1] -to fpga_top/sb_0__1_/chany_top_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[8] -to fpga_top/sb_0__1_/chany_top_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[15] -to fpga_top/sb_0__1_/chany_top_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[2] -to fpga_top/sb_0__1_/chany_top_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[12] -to fpga_top/sb_0__1_/chany_top_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[2] -to fpga_top/sb_0__1_/chany_top_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[9] -to fpga_top/sb_0__1_/chany_top_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[16] -to fpga_top/sb_0__1_/chany_top_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[4] -to fpga_top/sb_0__1_/chany_top_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[13] -to fpga_top/sb_0__1_/chany_top_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/top_left_grid_pin_1_[0] -to fpga_top/sb_0__1_/chany_top_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[3] -to fpga_top/sb_0__1_/chany_top_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[10] -to fpga_top/sb_0__1_/chany_top_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[17] -to fpga_top/sb_0__1_/chany_top_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[5] -to fpga_top/sb_0__1_/chany_top_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[14] -to fpga_top/sb_0__1_/chany_top_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/top_left_grid_pin_1_[0] -to fpga_top/sb_0__1_/chany_top_out[4] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[4] -to fpga_top/sb_0__1_/chany_top_out[4] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[11] -to fpga_top/sb_0__1_/chany_top_out[4] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[18] -to fpga_top/sb_0__1_/chany_top_out[4] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[6] -to fpga_top/sb_0__1_/chany_top_out[4] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[16] -to fpga_top/sb_0__1_/chany_top_out[4] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[5] -to fpga_top/sb_0__1_/chany_top_out[8] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[12] -to fpga_top/sb_0__1_/chany_top_out[8] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[19] -to fpga_top/sb_0__1_/chany_top_out[8] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[8] -to fpga_top/sb_0__1_/chany_top_out[8] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[17] -to fpga_top/sb_0__1_/chany_top_out[8] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[6] -to fpga_top/sb_0__1_/chany_top_out[12] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[13] -to fpga_top/sb_0__1_/chany_top_out[12] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[9] -to fpga_top/sb_0__1_/chany_top_out[12] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[18] -to fpga_top/sb_0__1_/chany_top_out[12] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[0] -to fpga_top/sb_0__1_/chany_top_out[16] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[7] -to fpga_top/sb_0__1_/chany_top_out[16] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[14] -to fpga_top/sb_0__1_/chany_top_out[16] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[10] -to fpga_top/sb_0__1_/chany_top_out[16] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[2] -to fpga_top/sb_0__1_/chanx_right_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/right_bottom_grid_pin_34_[0] -to fpga_top/sb_0__1_/chanx_right_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/right_bottom_grid_pin_36_[0] -to fpga_top/sb_0__1_/chanx_right_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/right_bottom_grid_pin_38_[0] -to fpga_top/sb_0__1_/chanx_right_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/right_bottom_grid_pin_40_[0] -to fpga_top/sb_0__1_/chanx_right_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[2] -to fpga_top/sb_0__1_/chanx_right_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[0] -to fpga_top/sb_0__1_/chanx_right_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[4] -to fpga_top/sb_0__1_/chanx_right_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/right_bottom_grid_pin_35_[0] -to fpga_top/sb_0__1_/chanx_right_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/right_bottom_grid_pin_37_[0] -to fpga_top/sb_0__1_/chanx_right_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/right_bottom_grid_pin_39_[0] -to fpga_top/sb_0__1_/chanx_right_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/right_bottom_grid_pin_41_[0] -to fpga_top/sb_0__1_/chanx_right_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[4] -to fpga_top/sb_0__1_/chanx_right_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[1] -to fpga_top/sb_0__1_/chanx_right_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[5] -to fpga_top/sb_0__1_/chanx_right_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/right_bottom_grid_pin_34_[0] -to fpga_top/sb_0__1_/chanx_right_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/right_bottom_grid_pin_36_[0] -to fpga_top/sb_0__1_/chanx_right_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/right_bottom_grid_pin_38_[0] -to fpga_top/sb_0__1_/chanx_right_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/right_bottom_grid_pin_40_[0] -to fpga_top/sb_0__1_/chanx_right_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[5] -to fpga_top/sb_0__1_/chanx_right_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[3] -to fpga_top/sb_0__1_/chanx_right_out[3] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[6] -to fpga_top/sb_0__1_/chanx_right_out[3] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/right_bottom_grid_pin_35_[0] -to fpga_top/sb_0__1_/chanx_right_out[3] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/right_bottom_grid_pin_37_[0] -to fpga_top/sb_0__1_/chanx_right_out[3] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/right_bottom_grid_pin_39_[0] -to fpga_top/sb_0__1_/chanx_right_out[3] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/right_bottom_grid_pin_41_[0] -to fpga_top/sb_0__1_/chanx_right_out[3] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[6] -to fpga_top/sb_0__1_/chanx_right_out[3] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[7] -to fpga_top/sb_0__1_/chanx_right_out[4] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[8] -to fpga_top/sb_0__1_/chanx_right_out[4] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/right_bottom_grid_pin_34_[0] -to fpga_top/sb_0__1_/chanx_right_out[4] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[8] -to fpga_top/sb_0__1_/chanx_right_out[4] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[9] -to fpga_top/sb_0__1_/chanx_right_out[5] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[11] -to fpga_top/sb_0__1_/chanx_right_out[5] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/right_bottom_grid_pin_35_[0] -to fpga_top/sb_0__1_/chanx_right_out[5] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[9] -to fpga_top/sb_0__1_/chanx_right_out[5] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[10] -to fpga_top/sb_0__1_/chanx_right_out[6] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[15] -to fpga_top/sb_0__1_/chanx_right_out[6] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/right_bottom_grid_pin_36_[0] -to fpga_top/sb_0__1_/chanx_right_out[6] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[10] -to fpga_top/sb_0__1_/chanx_right_out[6] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[12] -to fpga_top/sb_0__1_/chanx_right_out[7] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[19] -to fpga_top/sb_0__1_/chanx_right_out[7] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/right_bottom_grid_pin_37_[0] -to fpga_top/sb_0__1_/chanx_right_out[7] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[12] -to fpga_top/sb_0__1_/chanx_right_out[7] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[13] -to fpga_top/sb_0__1_/chanx_right_out[8] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/right_bottom_grid_pin_38_[0] -to fpga_top/sb_0__1_/chanx_right_out[8] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[13] -to fpga_top/sb_0__1_/chanx_right_out[8] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[14] -to fpga_top/sb_0__1_/chanx_right_out[9] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/right_bottom_grid_pin_39_[0] -to fpga_top/sb_0__1_/chanx_right_out[9] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[14] -to fpga_top/sb_0__1_/chanx_right_out[9] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[16] -to fpga_top/sb_0__1_/chanx_right_out[10] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/right_bottom_grid_pin_40_[0] -to fpga_top/sb_0__1_/chanx_right_out[10] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[16] -to fpga_top/sb_0__1_/chanx_right_out[10] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[17] -to fpga_top/sb_0__1_/chanx_right_out[11] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/right_bottom_grid_pin_41_[0] -to fpga_top/sb_0__1_/chanx_right_out[11] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[17] -to fpga_top/sb_0__1_/chanx_right_out[11] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[18] -to fpga_top/sb_0__1_/chanx_right_out[12] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/right_bottom_grid_pin_34_[0] -to fpga_top/sb_0__1_/chanx_right_out[12] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[18] -to fpga_top/sb_0__1_/chanx_right_out[12] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[19] -to fpga_top/sb_0__1_/chanx_right_out[12] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/right_bottom_grid_pin_35_[0] -to fpga_top/sb_0__1_/chanx_right_out[13] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[15] -to fpga_top/sb_0__1_/chanx_right_out[13] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/right_bottom_grid_pin_36_[0] -to fpga_top/sb_0__1_/chanx_right_out[14] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[11] -to fpga_top/sb_0__1_/chanx_right_out[14] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/right_bottom_grid_pin_37_[0] -to fpga_top/sb_0__1_/chanx_right_out[15] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[7] -to fpga_top/sb_0__1_/chanx_right_out[15] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/right_bottom_grid_pin_38_[0] -to fpga_top/sb_0__1_/chanx_right_out[16] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[3] -to fpga_top/sb_0__1_/chanx_right_out[16] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/right_bottom_grid_pin_39_[0] -to fpga_top/sb_0__1_/chanx_right_out[17] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[1] -to fpga_top/sb_0__1_/chanx_right_out[17] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/right_bottom_grid_pin_40_[0] -to fpga_top/sb_0__1_/chanx_right_out[18] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[0] -to fpga_top/sb_0__1_/chanx_right_out[18] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/right_bottom_grid_pin_41_[0] -to fpga_top/sb_0__1_/chanx_right_out[19] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[2] -to fpga_top/sb_0__1_/chany_bottom_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[12] -to fpga_top/sb_0__1_/chany_bottom_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[5] -to fpga_top/sb_0__1_/chany_bottom_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[12] -to fpga_top/sb_0__1_/chany_bottom_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[19] -to fpga_top/sb_0__1_/chany_bottom_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/bottom_left_grid_pin_1_[0] -to fpga_top/sb_0__1_/chany_bottom_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[4] -to fpga_top/sb_0__1_/chany_bottom_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[13] -to fpga_top/sb_0__1_/chany_bottom_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[4] -to fpga_top/sb_0__1_/chany_bottom_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[11] -to fpga_top/sb_0__1_/chany_bottom_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[18] -to fpga_top/sb_0__1_/chany_bottom_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[5] -to fpga_top/sb_0__1_/chany_bottom_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[14] -to fpga_top/sb_0__1_/chany_bottom_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[3] -to fpga_top/sb_0__1_/chany_bottom_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[10] -to fpga_top/sb_0__1_/chany_bottom_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[17] -to fpga_top/sb_0__1_/chany_bottom_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/bottom_left_grid_pin_1_[0] -to fpga_top/sb_0__1_/chany_bottom_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[6] -to fpga_top/sb_0__1_/chany_bottom_out[4] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[16] -to fpga_top/sb_0__1_/chany_bottom_out[4] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[2] -to fpga_top/sb_0__1_/chany_bottom_out[4] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[9] -to fpga_top/sb_0__1_/chany_bottom_out[4] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[16] -to fpga_top/sb_0__1_/chany_bottom_out[4] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/bottom_left_grid_pin_1_[0] -to fpga_top/sb_0__1_/chany_bottom_out[4] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[8] -to fpga_top/sb_0__1_/chany_bottom_out[8] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[17] -to fpga_top/sb_0__1_/chany_bottom_out[8] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[1] -to fpga_top/sb_0__1_/chany_bottom_out[8] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[8] -to fpga_top/sb_0__1_/chany_bottom_out[8] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[15] -to fpga_top/sb_0__1_/chany_bottom_out[8] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[9] -to fpga_top/sb_0__1_/chany_bottom_out[12] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[18] -to fpga_top/sb_0__1_/chany_bottom_out[12] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[0] -to fpga_top/sb_0__1_/chany_bottom_out[12] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[7] -to fpga_top/sb_0__1_/chany_bottom_out[12] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[14] -to fpga_top/sb_0__1_/chany_bottom_out[12] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[10] -to fpga_top/sb_0__1_/chany_bottom_out[16] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[6] -to fpga_top/sb_0__1_/chany_bottom_out[16] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[13] -to fpga_top/sb_0__1_/chany_bottom_out[16] 6.020400151e-11 diff --git a/FPGA1212_FLAT_HD_SKY_PNR/FPGA1212_FLAT_HD_SKY_Verilog/SDC/sb_12__0_.sdc b/FPGA1212_FLAT_HD_SKY_PNR/FPGA1212_FLAT_HD_SKY_Verilog/SDC/sb_12__0_.sdc deleted file mode 100644 index 10ea317..0000000 --- a/FPGA1212_FLAT_HD_SKY_PNR/FPGA1212_FLAT_HD_SKY_Verilog/SDC/sb_12__0_.sdc +++ /dev/null @@ -1,120 +0,0 @@ -############################################# -# Synopsys Design Constraints (SDC) -# For FPGA fabric -# Description: Constrain timing of Switch Block sb_12__0_ for PnR -# Author: Xifan TANG -# Organization: University of Utah -# Date: Sun Nov 29 02:09:07 2020 -############################################# - -############################################# -# Define time unit -############################################# -set_units -time s - -set_max_delay -from fpga_core_uut/sb_12__0_/top_left_grid_pin_42_[0] -to fpga_top/sb_12__0_/chany_top_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__0_/top_left_grid_pin_44_[0] -to fpga_top/sb_12__0_/chany_top_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__0_/top_left_grid_pin_46_[0] -to fpga_top/sb_12__0_/chany_top_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__0_/top_left_grid_pin_48_[0] -to fpga_top/sb_12__0_/chany_top_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__0_/top_right_grid_pin_1_[0] -to fpga_top/sb_12__0_/chany_top_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__0_/chanx_left_in[0] -to fpga_top/sb_12__0_/chany_top_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__0_/top_left_grid_pin_43_[0] -to fpga_top/sb_12__0_/chany_top_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__0_/top_left_grid_pin_45_[0] -to fpga_top/sb_12__0_/chany_top_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__0_/top_left_grid_pin_47_[0] -to fpga_top/sb_12__0_/chany_top_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__0_/top_left_grid_pin_49_[0] -to fpga_top/sb_12__0_/chany_top_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__0_/chanx_left_in[19] -to fpga_top/sb_12__0_/chany_top_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__0_/top_left_grid_pin_42_[0] -to fpga_top/sb_12__0_/chany_top_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__0_/top_left_grid_pin_44_[0] -to fpga_top/sb_12__0_/chany_top_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__0_/top_left_grid_pin_46_[0] -to fpga_top/sb_12__0_/chany_top_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__0_/top_left_grid_pin_48_[0] -to fpga_top/sb_12__0_/chany_top_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__0_/top_right_grid_pin_1_[0] -to fpga_top/sb_12__0_/chany_top_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__0_/chanx_left_in[18] -to fpga_top/sb_12__0_/chany_top_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__0_/top_left_grid_pin_43_[0] -to fpga_top/sb_12__0_/chany_top_out[3] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__0_/top_left_grid_pin_45_[0] -to fpga_top/sb_12__0_/chany_top_out[3] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__0_/top_left_grid_pin_47_[0] -to fpga_top/sb_12__0_/chany_top_out[3] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__0_/top_left_grid_pin_49_[0] -to fpga_top/sb_12__0_/chany_top_out[3] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__0_/chanx_left_in[17] -to fpga_top/sb_12__0_/chany_top_out[3] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__0_/top_left_grid_pin_42_[0] -to fpga_top/sb_12__0_/chany_top_out[4] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__0_/top_right_grid_pin_1_[0] -to fpga_top/sb_12__0_/chany_top_out[4] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__0_/chanx_left_in[16] -to fpga_top/sb_12__0_/chany_top_out[4] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__0_/top_left_grid_pin_43_[0] -to fpga_top/sb_12__0_/chany_top_out[5] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__0_/chanx_left_in[15] -to fpga_top/sb_12__0_/chany_top_out[5] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__0_/top_left_grid_pin_44_[0] -to fpga_top/sb_12__0_/chany_top_out[6] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__0_/chanx_left_in[14] -to fpga_top/sb_12__0_/chany_top_out[6] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__0_/top_left_grid_pin_45_[0] -to fpga_top/sb_12__0_/chany_top_out[7] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__0_/chanx_left_in[13] -to fpga_top/sb_12__0_/chany_top_out[7] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__0_/top_left_grid_pin_46_[0] -to fpga_top/sb_12__0_/chany_top_out[8] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__0_/chanx_left_in[12] -to fpga_top/sb_12__0_/chany_top_out[8] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__0_/top_left_grid_pin_47_[0] -to fpga_top/sb_12__0_/chany_top_out[9] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__0_/chanx_left_in[11] -to fpga_top/sb_12__0_/chany_top_out[9] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__0_/top_left_grid_pin_48_[0] -to fpga_top/sb_12__0_/chany_top_out[10] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__0_/chanx_left_in[10] -to fpga_top/sb_12__0_/chany_top_out[10] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__0_/top_left_grid_pin_49_[0] -to fpga_top/sb_12__0_/chany_top_out[11] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__0_/chanx_left_in[9] -to fpga_top/sb_12__0_/chany_top_out[11] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__0_/top_left_grid_pin_42_[0] -to fpga_top/sb_12__0_/chany_top_out[12] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__0_/top_right_grid_pin_1_[0] -to fpga_top/sb_12__0_/chany_top_out[12] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__0_/chanx_left_in[8] -to fpga_top/sb_12__0_/chany_top_out[12] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__0_/top_left_grid_pin_43_[0] -to fpga_top/sb_12__0_/chany_top_out[13] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__0_/chanx_left_in[7] -to fpga_top/sb_12__0_/chany_top_out[13] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__0_/chanx_left_in[6] -to fpga_top/sb_12__0_/chany_top_out[14] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__0_/chanx_left_in[5] -to fpga_top/sb_12__0_/chany_top_out[15] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__0_/chanx_left_in[4] -to fpga_top/sb_12__0_/chany_top_out[16] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__0_/chanx_left_in[3] -to fpga_top/sb_12__0_/chany_top_out[17] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__0_/chanx_left_in[2] -to fpga_top/sb_12__0_/chany_top_out[18] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__0_/chanx_left_in[1] -to fpga_top/sb_12__0_/chany_top_out[19] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__0_/chany_top_in[0] -to fpga_top/sb_12__0_/chanx_left_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_1_[0] -to fpga_top/sb_12__0_/chanx_left_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_5_[0] -to fpga_top/sb_12__0_/chanx_left_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_9_[0] -to fpga_top/sb_12__0_/chanx_left_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_13_[0] -to fpga_top/sb_12__0_/chanx_left_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_17_[0] -to fpga_top/sb_12__0_/chanx_left_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__0_/chany_top_in[19] -to fpga_top/sb_12__0_/chanx_left_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_3_[0] -to fpga_top/sb_12__0_/chanx_left_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_7_[0] -to fpga_top/sb_12__0_/chanx_left_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_11_[0] -to fpga_top/sb_12__0_/chanx_left_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_15_[0] -to fpga_top/sb_12__0_/chanx_left_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__0_/chany_top_in[18] -to fpga_top/sb_12__0_/chanx_left_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_1_[0] -to fpga_top/sb_12__0_/chanx_left_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_5_[0] -to fpga_top/sb_12__0_/chanx_left_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_9_[0] -to fpga_top/sb_12__0_/chanx_left_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_13_[0] -to fpga_top/sb_12__0_/chanx_left_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_17_[0] -to fpga_top/sb_12__0_/chanx_left_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__0_/chany_top_in[17] -to fpga_top/sb_12__0_/chanx_left_out[3] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_3_[0] -to fpga_top/sb_12__0_/chanx_left_out[3] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_7_[0] -to fpga_top/sb_12__0_/chanx_left_out[3] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_11_[0] -to fpga_top/sb_12__0_/chanx_left_out[3] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_15_[0] -to fpga_top/sb_12__0_/chanx_left_out[3] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__0_/chany_top_in[16] -to fpga_top/sb_12__0_/chanx_left_out[4] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_1_[0] -to fpga_top/sb_12__0_/chanx_left_out[4] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_17_[0] -to fpga_top/sb_12__0_/chanx_left_out[4] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__0_/chany_top_in[15] -to fpga_top/sb_12__0_/chanx_left_out[5] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_3_[0] -to fpga_top/sb_12__0_/chanx_left_out[5] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__0_/chany_top_in[14] -to fpga_top/sb_12__0_/chanx_left_out[6] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_5_[0] -to fpga_top/sb_12__0_/chanx_left_out[6] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__0_/chany_top_in[13] -to fpga_top/sb_12__0_/chanx_left_out[7] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_7_[0] -to fpga_top/sb_12__0_/chanx_left_out[7] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__0_/chany_top_in[12] -to fpga_top/sb_12__0_/chanx_left_out[8] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_9_[0] -to fpga_top/sb_12__0_/chanx_left_out[8] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__0_/chany_top_in[11] -to fpga_top/sb_12__0_/chanx_left_out[9] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_11_[0] -to fpga_top/sb_12__0_/chanx_left_out[9] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__0_/chany_top_in[10] -to fpga_top/sb_12__0_/chanx_left_out[10] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_13_[0] -to fpga_top/sb_12__0_/chanx_left_out[10] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__0_/chany_top_in[9] -to fpga_top/sb_12__0_/chanx_left_out[11] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_15_[0] -to fpga_top/sb_12__0_/chanx_left_out[11] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__0_/chany_top_in[8] -to fpga_top/sb_12__0_/chanx_left_out[12] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_1_[0] -to fpga_top/sb_12__0_/chanx_left_out[12] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_17_[0] -to fpga_top/sb_12__0_/chanx_left_out[12] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__0_/chany_top_in[7] -to fpga_top/sb_12__0_/chanx_left_out[13] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_3_[0] -to fpga_top/sb_12__0_/chanx_left_out[13] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__0_/chany_top_in[6] -to fpga_top/sb_12__0_/chanx_left_out[14] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_5_[0] -to fpga_top/sb_12__0_/chanx_left_out[14] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__0_/chany_top_in[5] -to fpga_top/sb_12__0_/chanx_left_out[15] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_7_[0] -to fpga_top/sb_12__0_/chanx_left_out[15] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__0_/chany_top_in[4] -to fpga_top/sb_12__0_/chanx_left_out[16] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_9_[0] -to fpga_top/sb_12__0_/chanx_left_out[16] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__0_/chany_top_in[3] -to fpga_top/sb_12__0_/chanx_left_out[17] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_11_[0] -to fpga_top/sb_12__0_/chanx_left_out[17] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__0_/chany_top_in[2] -to fpga_top/sb_12__0_/chanx_left_out[18] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_13_[0] -to fpga_top/sb_12__0_/chanx_left_out[18] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__0_/chany_top_in[1] -to fpga_top/sb_12__0_/chanx_left_out[19] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_15_[0] -to fpga_top/sb_12__0_/chanx_left_out[19] 6.020400151e-11 diff --git a/FPGA1212_FLAT_HD_SKY_PNR/FPGA1212_FLAT_HD_SKY_Verilog/SDC/sb_12__12_.sdc b/FPGA1212_FLAT_HD_SKY_PNR/FPGA1212_FLAT_HD_SKY_Verilog/SDC/sb_12__12_.sdc deleted file mode 100644 index 6419e35..0000000 --- a/FPGA1212_FLAT_HD_SKY_PNR/FPGA1212_FLAT_HD_SKY_Verilog/SDC/sb_12__12_.sdc +++ /dev/null @@ -1,120 +0,0 @@ -############################################# -# Synopsys Design Constraints (SDC) -# For FPGA fabric -# Description: Constrain timing of Switch Block sb_12__12_ for PnR -# Author: Xifan TANG -# Organization: University of Utah -# Date: Sun Nov 29 02:09:07 2020 -############################################# - -############################################# -# Define time unit -############################################# -set_units -time s - -set_max_delay -from fpga_core_uut/sb_12__12_/bottom_right_grid_pin_1_[0] -to fpga_top/sb_12__12_/chany_bottom_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__12_/bottom_left_grid_pin_43_[0] -to fpga_top/sb_12__12_/chany_bottom_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__12_/bottom_left_grid_pin_45_[0] -to fpga_top/sb_12__12_/chany_bottom_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__12_/bottom_left_grid_pin_47_[0] -to fpga_top/sb_12__12_/chany_bottom_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__12_/bottom_left_grid_pin_49_[0] -to fpga_top/sb_12__12_/chany_bottom_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__12_/chanx_left_in[1] -to fpga_top/sb_12__12_/chany_bottom_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__12_/bottom_left_grid_pin_42_[0] -to fpga_top/sb_12__12_/chany_bottom_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__12_/bottom_left_grid_pin_44_[0] -to fpga_top/sb_12__12_/chany_bottom_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__12_/bottom_left_grid_pin_46_[0] -to fpga_top/sb_12__12_/chany_bottom_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__12_/bottom_left_grid_pin_48_[0] -to fpga_top/sb_12__12_/chany_bottom_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__12_/chanx_left_in[2] -to fpga_top/sb_12__12_/chany_bottom_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__12_/bottom_right_grid_pin_1_[0] -to fpga_top/sb_12__12_/chany_bottom_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__12_/bottom_left_grid_pin_43_[0] -to fpga_top/sb_12__12_/chany_bottom_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__12_/bottom_left_grid_pin_45_[0] -to fpga_top/sb_12__12_/chany_bottom_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__12_/bottom_left_grid_pin_47_[0] -to fpga_top/sb_12__12_/chany_bottom_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__12_/bottom_left_grid_pin_49_[0] -to fpga_top/sb_12__12_/chany_bottom_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__12_/chanx_left_in[3] -to fpga_top/sb_12__12_/chany_bottom_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__12_/bottom_left_grid_pin_42_[0] -to fpga_top/sb_12__12_/chany_bottom_out[3] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__12_/bottom_left_grid_pin_44_[0] -to fpga_top/sb_12__12_/chany_bottom_out[3] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__12_/bottom_left_grid_pin_46_[0] -to fpga_top/sb_12__12_/chany_bottom_out[3] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__12_/bottom_left_grid_pin_48_[0] -to fpga_top/sb_12__12_/chany_bottom_out[3] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__12_/chanx_left_in[4] -to fpga_top/sb_12__12_/chany_bottom_out[3] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__12_/bottom_right_grid_pin_1_[0] -to fpga_top/sb_12__12_/chany_bottom_out[4] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__12_/chanx_left_in[5] -to fpga_top/sb_12__12_/chany_bottom_out[4] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__12_/bottom_left_grid_pin_42_[0] -to fpga_top/sb_12__12_/chany_bottom_out[5] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__12_/chanx_left_in[6] -to fpga_top/sb_12__12_/chany_bottom_out[5] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__12_/bottom_left_grid_pin_43_[0] -to fpga_top/sb_12__12_/chany_bottom_out[6] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__12_/chanx_left_in[7] -to fpga_top/sb_12__12_/chany_bottom_out[6] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__12_/bottom_left_grid_pin_44_[0] -to fpga_top/sb_12__12_/chany_bottom_out[7] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__12_/chanx_left_in[8] -to fpga_top/sb_12__12_/chany_bottom_out[7] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__12_/bottom_left_grid_pin_45_[0] -to fpga_top/sb_12__12_/chany_bottom_out[8] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__12_/chanx_left_in[9] -to fpga_top/sb_12__12_/chany_bottom_out[8] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__12_/bottom_left_grid_pin_46_[0] -to fpga_top/sb_12__12_/chany_bottom_out[9] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__12_/chanx_left_in[10] -to fpga_top/sb_12__12_/chany_bottom_out[9] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__12_/bottom_left_grid_pin_47_[0] -to fpga_top/sb_12__12_/chany_bottom_out[10] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__12_/chanx_left_in[11] -to fpga_top/sb_12__12_/chany_bottom_out[10] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__12_/bottom_left_grid_pin_48_[0] -to fpga_top/sb_12__12_/chany_bottom_out[11] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__12_/chanx_left_in[12] -to fpga_top/sb_12__12_/chany_bottom_out[11] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__12_/bottom_right_grid_pin_1_[0] -to fpga_top/sb_12__12_/chany_bottom_out[12] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__12_/bottom_left_grid_pin_49_[0] -to fpga_top/sb_12__12_/chany_bottom_out[12] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__12_/chanx_left_in[13] -to fpga_top/sb_12__12_/chany_bottom_out[12] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__12_/bottom_left_grid_pin_42_[0] -to fpga_top/sb_12__12_/chany_bottom_out[13] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__12_/chanx_left_in[14] -to fpga_top/sb_12__12_/chany_bottom_out[13] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__12_/bottom_left_grid_pin_43_[0] -to fpga_top/sb_12__12_/chany_bottom_out[14] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__12_/chanx_left_in[15] -to fpga_top/sb_12__12_/chany_bottom_out[14] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__12_/chanx_left_in[16] -to fpga_top/sb_12__12_/chany_bottom_out[15] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__12_/chanx_left_in[17] -to fpga_top/sb_12__12_/chany_bottom_out[16] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__12_/chanx_left_in[18] -to fpga_top/sb_12__12_/chany_bottom_out[17] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__12_/chanx_left_in[19] -to fpga_top/sb_12__12_/chany_bottom_out[18] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__12_/chanx_left_in[0] -to fpga_top/sb_12__12_/chany_bottom_out[19] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__12_/chany_bottom_in[19] -to fpga_top/sb_12__12_/chanx_left_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__12_/left_top_grid_pin_1_[0] -to fpga_top/sb_12__12_/chanx_left_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__12_/left_bottom_grid_pin_35_[0] -to fpga_top/sb_12__12_/chanx_left_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__12_/left_bottom_grid_pin_37_[0] -to fpga_top/sb_12__12_/chanx_left_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__12_/left_bottom_grid_pin_39_[0] -to fpga_top/sb_12__12_/chanx_left_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__12_/left_bottom_grid_pin_41_[0] -to fpga_top/sb_12__12_/chanx_left_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__12_/chany_bottom_in[0] -to fpga_top/sb_12__12_/chanx_left_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__12_/left_bottom_grid_pin_34_[0] -to fpga_top/sb_12__12_/chanx_left_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__12_/left_bottom_grid_pin_36_[0] -to fpga_top/sb_12__12_/chanx_left_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__12_/left_bottom_grid_pin_38_[0] -to fpga_top/sb_12__12_/chanx_left_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__12_/left_bottom_grid_pin_40_[0] -to fpga_top/sb_12__12_/chanx_left_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__12_/chany_bottom_in[1] -to fpga_top/sb_12__12_/chanx_left_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__12_/left_top_grid_pin_1_[0] -to fpga_top/sb_12__12_/chanx_left_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__12_/left_bottom_grid_pin_35_[0] -to fpga_top/sb_12__12_/chanx_left_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__12_/left_bottom_grid_pin_37_[0] -to fpga_top/sb_12__12_/chanx_left_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__12_/left_bottom_grid_pin_39_[0] -to fpga_top/sb_12__12_/chanx_left_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__12_/left_bottom_grid_pin_41_[0] -to fpga_top/sb_12__12_/chanx_left_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__12_/chany_bottom_in[2] -to fpga_top/sb_12__12_/chanx_left_out[3] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__12_/left_bottom_grid_pin_34_[0] -to fpga_top/sb_12__12_/chanx_left_out[3] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__12_/left_bottom_grid_pin_36_[0] -to fpga_top/sb_12__12_/chanx_left_out[3] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__12_/left_bottom_grid_pin_38_[0] -to fpga_top/sb_12__12_/chanx_left_out[3] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__12_/left_bottom_grid_pin_40_[0] -to fpga_top/sb_12__12_/chanx_left_out[3] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__12_/chany_bottom_in[3] -to fpga_top/sb_12__12_/chanx_left_out[4] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__12_/left_top_grid_pin_1_[0] -to fpga_top/sb_12__12_/chanx_left_out[4] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__12_/left_bottom_grid_pin_41_[0] -to fpga_top/sb_12__12_/chanx_left_out[4] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__12_/chany_bottom_in[4] -to fpga_top/sb_12__12_/chanx_left_out[5] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__12_/left_bottom_grid_pin_34_[0] -to fpga_top/sb_12__12_/chanx_left_out[5] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__12_/chany_bottom_in[5] -to fpga_top/sb_12__12_/chanx_left_out[6] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__12_/left_bottom_grid_pin_35_[0] -to fpga_top/sb_12__12_/chanx_left_out[6] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__12_/chany_bottom_in[6] -to fpga_top/sb_12__12_/chanx_left_out[7] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__12_/left_bottom_grid_pin_36_[0] -to fpga_top/sb_12__12_/chanx_left_out[7] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__12_/chany_bottom_in[7] -to fpga_top/sb_12__12_/chanx_left_out[8] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__12_/left_bottom_grid_pin_37_[0] -to fpga_top/sb_12__12_/chanx_left_out[8] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__12_/chany_bottom_in[8] -to fpga_top/sb_12__12_/chanx_left_out[9] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__12_/left_bottom_grid_pin_38_[0] -to fpga_top/sb_12__12_/chanx_left_out[9] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__12_/chany_bottom_in[9] -to fpga_top/sb_12__12_/chanx_left_out[10] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__12_/left_bottom_grid_pin_39_[0] -to fpga_top/sb_12__12_/chanx_left_out[10] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__12_/chany_bottom_in[10] -to fpga_top/sb_12__12_/chanx_left_out[11] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__12_/left_bottom_grid_pin_40_[0] -to fpga_top/sb_12__12_/chanx_left_out[11] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__12_/chany_bottom_in[11] -to fpga_top/sb_12__12_/chanx_left_out[12] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__12_/left_top_grid_pin_1_[0] -to fpga_top/sb_12__12_/chanx_left_out[12] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__12_/left_bottom_grid_pin_41_[0] -to fpga_top/sb_12__12_/chanx_left_out[12] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__12_/chany_bottom_in[12] -to fpga_top/sb_12__12_/chanx_left_out[13] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__12_/left_bottom_grid_pin_34_[0] -to fpga_top/sb_12__12_/chanx_left_out[13] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__12_/chany_bottom_in[13] -to fpga_top/sb_12__12_/chanx_left_out[14] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__12_/left_bottom_grid_pin_35_[0] -to fpga_top/sb_12__12_/chanx_left_out[14] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__12_/chany_bottom_in[14] -to fpga_top/sb_12__12_/chanx_left_out[15] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__12_/left_bottom_grid_pin_36_[0] -to fpga_top/sb_12__12_/chanx_left_out[15] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__12_/chany_bottom_in[15] -to fpga_top/sb_12__12_/chanx_left_out[16] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__12_/left_bottom_grid_pin_37_[0] -to fpga_top/sb_12__12_/chanx_left_out[16] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__12_/chany_bottom_in[16] -to fpga_top/sb_12__12_/chanx_left_out[17] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__12_/left_bottom_grid_pin_38_[0] -to fpga_top/sb_12__12_/chanx_left_out[17] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__12_/chany_bottom_in[17] -to fpga_top/sb_12__12_/chanx_left_out[18] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__12_/left_bottom_grid_pin_39_[0] -to fpga_top/sb_12__12_/chanx_left_out[18] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__12_/chany_bottom_in[18] -to fpga_top/sb_12__12_/chanx_left_out[19] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__12_/left_bottom_grid_pin_40_[0] -to fpga_top/sb_12__12_/chanx_left_out[19] 6.020400151e-11 diff --git a/FPGA1212_FLAT_HD_SKY_PNR/FPGA1212_FLAT_HD_SKY_Verilog/SDC/sb_12__1_.sdc b/FPGA1212_FLAT_HD_SKY_PNR/FPGA1212_FLAT_HD_SKY_Verilog/SDC/sb_12__1_.sdc deleted file mode 100644 index 2dd7ba7..0000000 --- a/FPGA1212_FLAT_HD_SKY_PNR/FPGA1212_FLAT_HD_SKY_Verilog/SDC/sb_12__1_.sdc +++ /dev/null @@ -1,206 +0,0 @@ -############################################# -# Synopsys Design Constraints (SDC) -# For FPGA fabric -# Description: Constrain timing of Switch Block sb_12__1_ for PnR -# Author: Xifan TANG -# Organization: University of Utah -# Date: Sun Nov 29 02:09:07 2020 -############################################# - -############################################# -# Define time unit -############################################# -set_units -time s - -set_max_delay -from fpga_core_uut/sb_12__1_/top_left_grid_pin_42_[0] -to fpga_top/sb_12__1_/chany_top_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/top_left_grid_pin_44_[0] -to fpga_top/sb_12__1_/chany_top_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/top_left_grid_pin_46_[0] -to fpga_top/sb_12__1_/chany_top_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/top_left_grid_pin_48_[0] -to fpga_top/sb_12__1_/chany_top_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/top_right_grid_pin_1_[0] -to fpga_top/sb_12__1_/chany_top_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[2] -to fpga_top/sb_12__1_/chany_top_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[12] -to fpga_top/sb_12__1_/chany_top_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[0] -to fpga_top/sb_12__1_/chany_top_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[7] -to fpga_top/sb_12__1_/chany_top_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[14] -to fpga_top/sb_12__1_/chany_top_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/top_left_grid_pin_43_[0] -to fpga_top/sb_12__1_/chany_top_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/top_left_grid_pin_45_[0] -to fpga_top/sb_12__1_/chany_top_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/top_left_grid_pin_47_[0] -to fpga_top/sb_12__1_/chany_top_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/top_left_grid_pin_49_[0] -to fpga_top/sb_12__1_/chany_top_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[4] -to fpga_top/sb_12__1_/chany_top_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[13] -to fpga_top/sb_12__1_/chany_top_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[6] -to fpga_top/sb_12__1_/chany_top_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[13] -to fpga_top/sb_12__1_/chany_top_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/top_left_grid_pin_42_[0] -to fpga_top/sb_12__1_/chany_top_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/top_left_grid_pin_43_[0] -to fpga_top/sb_12__1_/chany_top_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/top_left_grid_pin_44_[0] -to fpga_top/sb_12__1_/chany_top_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/top_left_grid_pin_45_[0] -to fpga_top/sb_12__1_/chany_top_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/top_left_grid_pin_46_[0] -to fpga_top/sb_12__1_/chany_top_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/top_left_grid_pin_47_[0] -to fpga_top/sb_12__1_/chany_top_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/top_left_grid_pin_48_[0] -to fpga_top/sb_12__1_/chany_top_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/top_left_grid_pin_49_[0] -to fpga_top/sb_12__1_/chany_top_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/top_right_grid_pin_1_[0] -to fpga_top/sb_12__1_/chany_top_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[5] -to fpga_top/sb_12__1_/chany_top_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[14] -to fpga_top/sb_12__1_/chany_top_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[5] -to fpga_top/sb_12__1_/chany_top_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[12] -to fpga_top/sb_12__1_/chany_top_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[19] -to fpga_top/sb_12__1_/chany_top_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/top_left_grid_pin_42_[0] -to fpga_top/sb_12__1_/chany_top_out[4] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/top_left_grid_pin_46_[0] -to fpga_top/sb_12__1_/chany_top_out[4] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/top_right_grid_pin_1_[0] -to fpga_top/sb_12__1_/chany_top_out[4] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[6] -to fpga_top/sb_12__1_/chany_top_out[4] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[16] -to fpga_top/sb_12__1_/chany_top_out[4] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[4] -to fpga_top/sb_12__1_/chany_top_out[4] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[11] -to fpga_top/sb_12__1_/chany_top_out[4] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[18] -to fpga_top/sb_12__1_/chany_top_out[4] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/top_left_grid_pin_43_[0] -to fpga_top/sb_12__1_/chany_top_out[8] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/top_left_grid_pin_47_[0] -to fpga_top/sb_12__1_/chany_top_out[8] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[8] -to fpga_top/sb_12__1_/chany_top_out[8] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[17] -to fpga_top/sb_12__1_/chany_top_out[8] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[3] -to fpga_top/sb_12__1_/chany_top_out[8] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[10] -to fpga_top/sb_12__1_/chany_top_out[8] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[17] -to fpga_top/sb_12__1_/chany_top_out[8] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/top_left_grid_pin_44_[0] -to fpga_top/sb_12__1_/chany_top_out[12] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/top_left_grid_pin_48_[0] -to fpga_top/sb_12__1_/chany_top_out[12] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[9] -to fpga_top/sb_12__1_/chany_top_out[12] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[18] -to fpga_top/sb_12__1_/chany_top_out[12] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[2] -to fpga_top/sb_12__1_/chany_top_out[12] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[9] -to fpga_top/sb_12__1_/chany_top_out[12] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[16] -to fpga_top/sb_12__1_/chany_top_out[12] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/top_left_grid_pin_45_[0] -to fpga_top/sb_12__1_/chany_top_out[16] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/top_left_grid_pin_49_[0] -to fpga_top/sb_12__1_/chany_top_out[16] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[10] -to fpga_top/sb_12__1_/chany_top_out[16] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[1] -to fpga_top/sb_12__1_/chany_top_out[16] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[8] -to fpga_top/sb_12__1_/chany_top_out[16] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[15] -to fpga_top/sb_12__1_/chany_top_out[16] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[2] -to fpga_top/sb_12__1_/chany_bottom_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[12] -to fpga_top/sb_12__1_/chany_bottom_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/bottom_right_grid_pin_1_[0] -to fpga_top/sb_12__1_/chany_bottom_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/bottom_left_grid_pin_43_[0] -to fpga_top/sb_12__1_/chany_bottom_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/bottom_left_grid_pin_45_[0] -to fpga_top/sb_12__1_/chany_bottom_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/bottom_left_grid_pin_47_[0] -to fpga_top/sb_12__1_/chany_bottom_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/bottom_left_grid_pin_49_[0] -to fpga_top/sb_12__1_/chany_bottom_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[1] -to fpga_top/sb_12__1_/chany_bottom_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[8] -to fpga_top/sb_12__1_/chany_bottom_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[15] -to fpga_top/sb_12__1_/chany_bottom_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[4] -to fpga_top/sb_12__1_/chany_bottom_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[13] -to fpga_top/sb_12__1_/chany_bottom_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/bottom_left_grid_pin_42_[0] -to fpga_top/sb_12__1_/chany_bottom_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/bottom_left_grid_pin_44_[0] -to fpga_top/sb_12__1_/chany_bottom_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/bottom_left_grid_pin_46_[0] -to fpga_top/sb_12__1_/chany_bottom_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/bottom_left_grid_pin_48_[0] -to fpga_top/sb_12__1_/chany_bottom_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[2] -to fpga_top/sb_12__1_/chany_bottom_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[9] -to fpga_top/sb_12__1_/chany_bottom_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[16] -to fpga_top/sb_12__1_/chany_bottom_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[5] -to fpga_top/sb_12__1_/chany_bottom_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[14] -to fpga_top/sb_12__1_/chany_bottom_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/bottom_right_grid_pin_1_[0] -to fpga_top/sb_12__1_/chany_bottom_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/bottom_left_grid_pin_42_[0] -to fpga_top/sb_12__1_/chany_bottom_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/bottom_left_grid_pin_43_[0] -to fpga_top/sb_12__1_/chany_bottom_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/bottom_left_grid_pin_44_[0] -to fpga_top/sb_12__1_/chany_bottom_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/bottom_left_grid_pin_45_[0] -to fpga_top/sb_12__1_/chany_bottom_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/bottom_left_grid_pin_46_[0] -to fpga_top/sb_12__1_/chany_bottom_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/bottom_left_grid_pin_47_[0] -to fpga_top/sb_12__1_/chany_bottom_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/bottom_left_grid_pin_48_[0] -to fpga_top/sb_12__1_/chany_bottom_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/bottom_left_grid_pin_49_[0] -to fpga_top/sb_12__1_/chany_bottom_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[3] -to fpga_top/sb_12__1_/chany_bottom_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[10] -to fpga_top/sb_12__1_/chany_bottom_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[17] -to fpga_top/sb_12__1_/chany_bottom_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[6] -to fpga_top/sb_12__1_/chany_bottom_out[4] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[16] -to fpga_top/sb_12__1_/chany_bottom_out[4] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/bottom_right_grid_pin_1_[0] -to fpga_top/sb_12__1_/chany_bottom_out[4] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/bottom_left_grid_pin_45_[0] -to fpga_top/sb_12__1_/chany_bottom_out[4] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/bottom_left_grid_pin_49_[0] -to fpga_top/sb_12__1_/chany_bottom_out[4] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[4] -to fpga_top/sb_12__1_/chany_bottom_out[4] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[11] -to fpga_top/sb_12__1_/chany_bottom_out[4] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[18] -to fpga_top/sb_12__1_/chany_bottom_out[4] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[8] -to fpga_top/sb_12__1_/chany_bottom_out[8] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[17] -to fpga_top/sb_12__1_/chany_bottom_out[8] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/bottom_left_grid_pin_42_[0] -to fpga_top/sb_12__1_/chany_bottom_out[8] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/bottom_left_grid_pin_46_[0] -to fpga_top/sb_12__1_/chany_bottom_out[8] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[5] -to fpga_top/sb_12__1_/chany_bottom_out[8] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[12] -to fpga_top/sb_12__1_/chany_bottom_out[8] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[19] -to fpga_top/sb_12__1_/chany_bottom_out[8] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[9] -to fpga_top/sb_12__1_/chany_bottom_out[12] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[18] -to fpga_top/sb_12__1_/chany_bottom_out[12] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/bottom_left_grid_pin_43_[0] -to fpga_top/sb_12__1_/chany_bottom_out[12] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/bottom_left_grid_pin_47_[0] -to fpga_top/sb_12__1_/chany_bottom_out[12] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[6] -to fpga_top/sb_12__1_/chany_bottom_out[12] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[13] -to fpga_top/sb_12__1_/chany_bottom_out[12] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[10] -to fpga_top/sb_12__1_/chany_bottom_out[16] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/bottom_left_grid_pin_44_[0] -to fpga_top/sb_12__1_/chany_bottom_out[16] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/bottom_left_grid_pin_48_[0] -to fpga_top/sb_12__1_/chany_bottom_out[16] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[0] -to fpga_top/sb_12__1_/chany_bottom_out[16] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[7] -to fpga_top/sb_12__1_/chany_bottom_out[16] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[14] -to fpga_top/sb_12__1_/chany_bottom_out[16] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[0] -to fpga_top/sb_12__1_/chanx_left_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[2] -to fpga_top/sb_12__1_/chanx_left_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[2] -to fpga_top/sb_12__1_/chanx_left_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/left_bottom_grid_pin_34_[0] -to fpga_top/sb_12__1_/chanx_left_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/left_bottom_grid_pin_36_[0] -to fpga_top/sb_12__1_/chanx_left_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/left_bottom_grid_pin_38_[0] -to fpga_top/sb_12__1_/chanx_left_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/left_bottom_grid_pin_40_[0] -to fpga_top/sb_12__1_/chanx_left_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[4] -to fpga_top/sb_12__1_/chanx_left_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[0] -to fpga_top/sb_12__1_/chanx_left_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[4] -to fpga_top/sb_12__1_/chanx_left_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/left_bottom_grid_pin_35_[0] -to fpga_top/sb_12__1_/chanx_left_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/left_bottom_grid_pin_37_[0] -to fpga_top/sb_12__1_/chanx_left_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/left_bottom_grid_pin_39_[0] -to fpga_top/sb_12__1_/chanx_left_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/left_bottom_grid_pin_41_[0] -to fpga_top/sb_12__1_/chanx_left_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[5] -to fpga_top/sb_12__1_/chanx_left_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[1] -to fpga_top/sb_12__1_/chanx_left_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[5] -to fpga_top/sb_12__1_/chanx_left_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/left_bottom_grid_pin_34_[0] -to fpga_top/sb_12__1_/chanx_left_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/left_bottom_grid_pin_36_[0] -to fpga_top/sb_12__1_/chanx_left_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/left_bottom_grid_pin_38_[0] -to fpga_top/sb_12__1_/chanx_left_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/left_bottom_grid_pin_40_[0] -to fpga_top/sb_12__1_/chanx_left_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[6] -to fpga_top/sb_12__1_/chanx_left_out[3] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[3] -to fpga_top/sb_12__1_/chanx_left_out[3] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[6] -to fpga_top/sb_12__1_/chanx_left_out[3] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/left_bottom_grid_pin_35_[0] -to fpga_top/sb_12__1_/chanx_left_out[3] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/left_bottom_grid_pin_37_[0] -to fpga_top/sb_12__1_/chanx_left_out[3] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/left_bottom_grid_pin_39_[0] -to fpga_top/sb_12__1_/chanx_left_out[3] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/left_bottom_grid_pin_41_[0] -to fpga_top/sb_12__1_/chanx_left_out[3] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[8] -to fpga_top/sb_12__1_/chanx_left_out[4] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[7] -to fpga_top/sb_12__1_/chanx_left_out[4] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[8] -to fpga_top/sb_12__1_/chanx_left_out[4] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/left_bottom_grid_pin_34_[0] -to fpga_top/sb_12__1_/chanx_left_out[4] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[9] -to fpga_top/sb_12__1_/chanx_left_out[5] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[9] -to fpga_top/sb_12__1_/chanx_left_out[5] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[11] -to fpga_top/sb_12__1_/chanx_left_out[5] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/left_bottom_grid_pin_35_[0] -to fpga_top/sb_12__1_/chanx_left_out[5] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[10] -to fpga_top/sb_12__1_/chanx_left_out[6] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[10] -to fpga_top/sb_12__1_/chanx_left_out[6] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[15] -to fpga_top/sb_12__1_/chanx_left_out[6] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/left_bottom_grid_pin_36_[0] -to fpga_top/sb_12__1_/chanx_left_out[6] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[12] -to fpga_top/sb_12__1_/chanx_left_out[7] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[12] -to fpga_top/sb_12__1_/chanx_left_out[7] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[19] -to fpga_top/sb_12__1_/chanx_left_out[7] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/left_bottom_grid_pin_37_[0] -to fpga_top/sb_12__1_/chanx_left_out[7] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[13] -to fpga_top/sb_12__1_/chanx_left_out[8] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[13] -to fpga_top/sb_12__1_/chanx_left_out[8] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/left_bottom_grid_pin_38_[0] -to fpga_top/sb_12__1_/chanx_left_out[8] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[14] -to fpga_top/sb_12__1_/chanx_left_out[9] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[14] -to fpga_top/sb_12__1_/chanx_left_out[9] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/left_bottom_grid_pin_39_[0] -to fpga_top/sb_12__1_/chanx_left_out[9] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[16] -to fpga_top/sb_12__1_/chanx_left_out[10] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[16] -to fpga_top/sb_12__1_/chanx_left_out[10] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/left_bottom_grid_pin_40_[0] -to fpga_top/sb_12__1_/chanx_left_out[10] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[17] -to fpga_top/sb_12__1_/chanx_left_out[11] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[17] -to fpga_top/sb_12__1_/chanx_left_out[11] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/left_bottom_grid_pin_41_[0] -to fpga_top/sb_12__1_/chanx_left_out[11] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[18] -to fpga_top/sb_12__1_/chanx_left_out[12] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[18] -to fpga_top/sb_12__1_/chanx_left_out[12] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/left_bottom_grid_pin_34_[0] -to fpga_top/sb_12__1_/chanx_left_out[12] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/left_bottom_grid_pin_35_[0] -to fpga_top/sb_12__1_/chanx_left_out[13] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[19] -to fpga_top/sb_12__1_/chanx_left_out[14] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/left_bottom_grid_pin_36_[0] -to fpga_top/sb_12__1_/chanx_left_out[14] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[15] -to fpga_top/sb_12__1_/chanx_left_out[15] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/left_bottom_grid_pin_37_[0] -to fpga_top/sb_12__1_/chanx_left_out[15] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[11] -to fpga_top/sb_12__1_/chanx_left_out[16] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/left_bottom_grid_pin_38_[0] -to fpga_top/sb_12__1_/chanx_left_out[16] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[7] -to fpga_top/sb_12__1_/chanx_left_out[17] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/left_bottom_grid_pin_39_[0] -to fpga_top/sb_12__1_/chanx_left_out[17] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[3] -to fpga_top/sb_12__1_/chanx_left_out[18] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/left_bottom_grid_pin_40_[0] -to fpga_top/sb_12__1_/chanx_left_out[18] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[1] -to fpga_top/sb_12__1_/chanx_left_out[19] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/left_bottom_grid_pin_41_[0] -to fpga_top/sb_12__1_/chanx_left_out[19] 6.020400151e-11 diff --git a/FPGA1212_FLAT_HD_SKY_PNR/FPGA1212_FLAT_HD_SKY_Verilog/SDC/sb_1__0_.sdc b/FPGA1212_FLAT_HD_SKY_PNR/FPGA1212_FLAT_HD_SKY_Verilog/SDC/sb_1__0_.sdc deleted file mode 100644 index a0e1859..0000000 --- a/FPGA1212_FLAT_HD_SKY_PNR/FPGA1212_FLAT_HD_SKY_Verilog/SDC/sb_1__0_.sdc +++ /dev/null @@ -1,200 +0,0 @@ -############################################# -# Synopsys Design Constraints (SDC) -# For FPGA fabric -# Description: Constrain timing of Switch Block sb_1__0_ for PnR -# Author: Xifan TANG -# Organization: University of Utah -# Date: Sun Nov 29 02:09:07 2020 -############################################# - -############################################# -# Define time unit -############################################# -set_units -time s - -set_max_delay -from fpga_core_uut/sb_1__0_/top_left_grid_pin_42_[0] -to fpga_top/sb_1__0_/chany_top_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/top_left_grid_pin_44_[0] -to fpga_top/sb_1__0_/chany_top_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/top_left_grid_pin_46_[0] -to fpga_top/sb_1__0_/chany_top_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/top_left_grid_pin_48_[0] -to fpga_top/sb_1__0_/chany_top_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[1] -to fpga_top/sb_1__0_/chany_top_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[2] -to fpga_top/sb_1__0_/chany_top_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[0] -to fpga_top/sb_1__0_/chany_top_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[2] -to fpga_top/sb_1__0_/chany_top_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/top_left_grid_pin_43_[0] -to fpga_top/sb_1__0_/chany_top_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/top_left_grid_pin_45_[0] -to fpga_top/sb_1__0_/chany_top_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/top_left_grid_pin_47_[0] -to fpga_top/sb_1__0_/chany_top_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/top_left_grid_pin_49_[0] -to fpga_top/sb_1__0_/chany_top_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[3] -to fpga_top/sb_1__0_/chany_top_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[4] -to fpga_top/sb_1__0_/chany_top_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[4] -to fpga_top/sb_1__0_/chany_top_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/top_left_grid_pin_42_[0] -to fpga_top/sb_1__0_/chany_top_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/top_left_grid_pin_44_[0] -to fpga_top/sb_1__0_/chany_top_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/top_left_grid_pin_46_[0] -to fpga_top/sb_1__0_/chany_top_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/top_left_grid_pin_48_[0] -to fpga_top/sb_1__0_/chany_top_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[5] -to fpga_top/sb_1__0_/chany_top_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[7] -to fpga_top/sb_1__0_/chany_top_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[5] -to fpga_top/sb_1__0_/chany_top_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/top_left_grid_pin_43_[0] -to fpga_top/sb_1__0_/chany_top_out[3] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/top_left_grid_pin_45_[0] -to fpga_top/sb_1__0_/chany_top_out[3] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/top_left_grid_pin_47_[0] -to fpga_top/sb_1__0_/chany_top_out[3] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/top_left_grid_pin_49_[0] -to fpga_top/sb_1__0_/chany_top_out[3] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[6] -to fpga_top/sb_1__0_/chany_top_out[3] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[11] -to fpga_top/sb_1__0_/chany_top_out[3] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[6] -to fpga_top/sb_1__0_/chany_top_out[3] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/top_left_grid_pin_42_[0] -to fpga_top/sb_1__0_/chany_top_out[4] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[8] -to fpga_top/sb_1__0_/chany_top_out[4] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[15] -to fpga_top/sb_1__0_/chany_top_out[4] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[8] -to fpga_top/sb_1__0_/chany_top_out[4] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/top_left_grid_pin_43_[0] -to fpga_top/sb_1__0_/chany_top_out[5] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[9] -to fpga_top/sb_1__0_/chany_top_out[5] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[19] -to fpga_top/sb_1__0_/chany_top_out[5] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[9] -to fpga_top/sb_1__0_/chany_top_out[5] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/top_left_grid_pin_44_[0] -to fpga_top/sb_1__0_/chany_top_out[6] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[10] -to fpga_top/sb_1__0_/chany_top_out[6] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[10] -to fpga_top/sb_1__0_/chany_top_out[6] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/top_left_grid_pin_45_[0] -to fpga_top/sb_1__0_/chany_top_out[7] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[12] -to fpga_top/sb_1__0_/chany_top_out[7] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[12] -to fpga_top/sb_1__0_/chany_top_out[7] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/top_left_grid_pin_46_[0] -to fpga_top/sb_1__0_/chany_top_out[8] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[13] -to fpga_top/sb_1__0_/chany_top_out[8] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[13] -to fpga_top/sb_1__0_/chany_top_out[8] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/top_left_grid_pin_47_[0] -to fpga_top/sb_1__0_/chany_top_out[9] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[14] -to fpga_top/sb_1__0_/chany_top_out[9] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[14] -to fpga_top/sb_1__0_/chany_top_out[9] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/top_left_grid_pin_48_[0] -to fpga_top/sb_1__0_/chany_top_out[10] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[16] -to fpga_top/sb_1__0_/chany_top_out[10] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[16] -to fpga_top/sb_1__0_/chany_top_out[10] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/top_left_grid_pin_49_[0] -to fpga_top/sb_1__0_/chany_top_out[11] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[17] -to fpga_top/sb_1__0_/chany_top_out[11] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[17] -to fpga_top/sb_1__0_/chany_top_out[11] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/top_left_grid_pin_42_[0] -to fpga_top/sb_1__0_/chany_top_out[12] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[18] -to fpga_top/sb_1__0_/chany_top_out[12] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[18] -to fpga_top/sb_1__0_/chany_top_out[12] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/top_left_grid_pin_43_[0] -to fpga_top/sb_1__0_/chany_top_out[13] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[19] -to fpga_top/sb_1__0_/chany_top_out[14] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[15] -to fpga_top/sb_1__0_/chany_top_out[15] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[11] -to fpga_top/sb_1__0_/chany_top_out[16] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[7] -to fpga_top/sb_1__0_/chany_top_out[17] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[3] -to fpga_top/sb_1__0_/chany_top_out[18] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[0] -to fpga_top/sb_1__0_/chany_top_out[19] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[1] -to fpga_top/sb_1__0_/chany_top_out[19] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[6] -to fpga_top/sb_1__0_/chanx_right_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[13] -to fpga_top/sb_1__0_/chanx_right_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/right_bottom_grid_pin_1_[0] -to fpga_top/sb_1__0_/chanx_right_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/right_bottom_grid_pin_5_[0] -to fpga_top/sb_1__0_/chanx_right_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/right_bottom_grid_pin_9_[0] -to fpga_top/sb_1__0_/chanx_right_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/right_bottom_grid_pin_13_[0] -to fpga_top/sb_1__0_/chanx_right_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/right_bottom_grid_pin_17_[0] -to fpga_top/sb_1__0_/chanx_right_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[2] -to fpga_top/sb_1__0_/chanx_right_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[12] -to fpga_top/sb_1__0_/chanx_right_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[0] -to fpga_top/sb_1__0_/chanx_right_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[7] -to fpga_top/sb_1__0_/chanx_right_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[14] -to fpga_top/sb_1__0_/chanx_right_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/right_bottom_grid_pin_3_[0] -to fpga_top/sb_1__0_/chanx_right_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/right_bottom_grid_pin_7_[0] -to fpga_top/sb_1__0_/chanx_right_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/right_bottom_grid_pin_11_[0] -to fpga_top/sb_1__0_/chanx_right_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/right_bottom_grid_pin_15_[0] -to fpga_top/sb_1__0_/chanx_right_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[4] -to fpga_top/sb_1__0_/chanx_right_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[13] -to fpga_top/sb_1__0_/chanx_right_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[1] -to fpga_top/sb_1__0_/chanx_right_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[8] -to fpga_top/sb_1__0_/chanx_right_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[15] -to fpga_top/sb_1__0_/chanx_right_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/right_bottom_grid_pin_1_[0] -to fpga_top/sb_1__0_/chanx_right_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/right_bottom_grid_pin_3_[0] -to fpga_top/sb_1__0_/chanx_right_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/right_bottom_grid_pin_5_[0] -to fpga_top/sb_1__0_/chanx_right_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/right_bottom_grid_pin_7_[0] -to fpga_top/sb_1__0_/chanx_right_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/right_bottom_grid_pin_9_[0] -to fpga_top/sb_1__0_/chanx_right_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/right_bottom_grid_pin_11_[0] -to fpga_top/sb_1__0_/chanx_right_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/right_bottom_grid_pin_13_[0] -to fpga_top/sb_1__0_/chanx_right_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/right_bottom_grid_pin_15_[0] -to fpga_top/sb_1__0_/chanx_right_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/right_bottom_grid_pin_17_[0] -to fpga_top/sb_1__0_/chanx_right_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[5] -to fpga_top/sb_1__0_/chanx_right_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[14] -to fpga_top/sb_1__0_/chanx_right_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[2] -to fpga_top/sb_1__0_/chanx_right_out[4] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[9] -to fpga_top/sb_1__0_/chanx_right_out[4] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[16] -to fpga_top/sb_1__0_/chanx_right_out[4] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/right_bottom_grid_pin_1_[0] -to fpga_top/sb_1__0_/chanx_right_out[4] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/right_bottom_grid_pin_9_[0] -to fpga_top/sb_1__0_/chanx_right_out[4] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/right_bottom_grid_pin_17_[0] -to fpga_top/sb_1__0_/chanx_right_out[4] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[6] -to fpga_top/sb_1__0_/chanx_right_out[4] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[16] -to fpga_top/sb_1__0_/chanx_right_out[4] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[3] -to fpga_top/sb_1__0_/chanx_right_out[8] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[10] -to fpga_top/sb_1__0_/chanx_right_out[8] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[17] -to fpga_top/sb_1__0_/chanx_right_out[8] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/right_bottom_grid_pin_3_[0] -to fpga_top/sb_1__0_/chanx_right_out[8] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/right_bottom_grid_pin_11_[0] -to fpga_top/sb_1__0_/chanx_right_out[8] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[8] -to fpga_top/sb_1__0_/chanx_right_out[8] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[17] -to fpga_top/sb_1__0_/chanx_right_out[8] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[4] -to fpga_top/sb_1__0_/chanx_right_out[12] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[11] -to fpga_top/sb_1__0_/chanx_right_out[12] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[18] -to fpga_top/sb_1__0_/chanx_right_out[12] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/right_bottom_grid_pin_5_[0] -to fpga_top/sb_1__0_/chanx_right_out[12] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/right_bottom_grid_pin_13_[0] -to fpga_top/sb_1__0_/chanx_right_out[12] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[9] -to fpga_top/sb_1__0_/chanx_right_out[12] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[18] -to fpga_top/sb_1__0_/chanx_right_out[12] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[5] -to fpga_top/sb_1__0_/chanx_right_out[16] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[12] -to fpga_top/sb_1__0_/chanx_right_out[16] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[19] -to fpga_top/sb_1__0_/chanx_right_out[16] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/right_bottom_grid_pin_7_[0] -to fpga_top/sb_1__0_/chanx_right_out[16] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/right_bottom_grid_pin_15_[0] -to fpga_top/sb_1__0_/chanx_right_out[16] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[10] -to fpga_top/sb_1__0_/chanx_right_out[16] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[0] -to fpga_top/sb_1__0_/chanx_left_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[7] -to fpga_top/sb_1__0_/chanx_left_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[14] -to fpga_top/sb_1__0_/chanx_left_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[2] -to fpga_top/sb_1__0_/chanx_left_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[12] -to fpga_top/sb_1__0_/chanx_left_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/left_bottom_grid_pin_1_[0] -to fpga_top/sb_1__0_/chanx_left_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/left_bottom_grid_pin_5_[0] -to fpga_top/sb_1__0_/chanx_left_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/left_bottom_grid_pin_9_[0] -to fpga_top/sb_1__0_/chanx_left_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/left_bottom_grid_pin_13_[0] -to fpga_top/sb_1__0_/chanx_left_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/left_bottom_grid_pin_17_[0] -to fpga_top/sb_1__0_/chanx_left_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[6] -to fpga_top/sb_1__0_/chanx_left_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[13] -to fpga_top/sb_1__0_/chanx_left_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[4] -to fpga_top/sb_1__0_/chanx_left_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[13] -to fpga_top/sb_1__0_/chanx_left_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/left_bottom_grid_pin_3_[0] -to fpga_top/sb_1__0_/chanx_left_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/left_bottom_grid_pin_7_[0] -to fpga_top/sb_1__0_/chanx_left_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/left_bottom_grid_pin_11_[0] -to fpga_top/sb_1__0_/chanx_left_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/left_bottom_grid_pin_15_[0] -to fpga_top/sb_1__0_/chanx_left_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[5] -to fpga_top/sb_1__0_/chanx_left_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[12] -to fpga_top/sb_1__0_/chanx_left_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[19] -to fpga_top/sb_1__0_/chanx_left_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[5] -to fpga_top/sb_1__0_/chanx_left_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[14] -to fpga_top/sb_1__0_/chanx_left_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/left_bottom_grid_pin_1_[0] -to fpga_top/sb_1__0_/chanx_left_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/left_bottom_grid_pin_3_[0] -to fpga_top/sb_1__0_/chanx_left_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/left_bottom_grid_pin_5_[0] -to fpga_top/sb_1__0_/chanx_left_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/left_bottom_grid_pin_7_[0] -to fpga_top/sb_1__0_/chanx_left_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/left_bottom_grid_pin_9_[0] -to fpga_top/sb_1__0_/chanx_left_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/left_bottom_grid_pin_11_[0] -to fpga_top/sb_1__0_/chanx_left_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/left_bottom_grid_pin_13_[0] -to fpga_top/sb_1__0_/chanx_left_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/left_bottom_grid_pin_15_[0] -to fpga_top/sb_1__0_/chanx_left_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/left_bottom_grid_pin_17_[0] -to fpga_top/sb_1__0_/chanx_left_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[4] -to fpga_top/sb_1__0_/chanx_left_out[4] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[11] -to fpga_top/sb_1__0_/chanx_left_out[4] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[18] -to fpga_top/sb_1__0_/chanx_left_out[4] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[6] -to fpga_top/sb_1__0_/chanx_left_out[4] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[16] -to fpga_top/sb_1__0_/chanx_left_out[4] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/left_bottom_grid_pin_1_[0] -to fpga_top/sb_1__0_/chanx_left_out[4] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/left_bottom_grid_pin_9_[0] -to fpga_top/sb_1__0_/chanx_left_out[4] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/left_bottom_grid_pin_17_[0] -to fpga_top/sb_1__0_/chanx_left_out[4] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[3] -to fpga_top/sb_1__0_/chanx_left_out[8] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[10] -to fpga_top/sb_1__0_/chanx_left_out[8] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[17] -to fpga_top/sb_1__0_/chanx_left_out[8] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[8] -to fpga_top/sb_1__0_/chanx_left_out[8] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[17] -to fpga_top/sb_1__0_/chanx_left_out[8] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/left_bottom_grid_pin_3_[0] -to fpga_top/sb_1__0_/chanx_left_out[8] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/left_bottom_grid_pin_11_[0] -to fpga_top/sb_1__0_/chanx_left_out[8] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[2] -to fpga_top/sb_1__0_/chanx_left_out[12] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[9] -to fpga_top/sb_1__0_/chanx_left_out[12] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[16] -to fpga_top/sb_1__0_/chanx_left_out[12] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[9] -to fpga_top/sb_1__0_/chanx_left_out[12] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[18] -to fpga_top/sb_1__0_/chanx_left_out[12] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/left_bottom_grid_pin_5_[0] -to fpga_top/sb_1__0_/chanx_left_out[12] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/left_bottom_grid_pin_13_[0] -to fpga_top/sb_1__0_/chanx_left_out[12] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[1] -to fpga_top/sb_1__0_/chanx_left_out[16] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[8] -to fpga_top/sb_1__0_/chanx_left_out[16] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[15] -to fpga_top/sb_1__0_/chanx_left_out[16] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[10] -to fpga_top/sb_1__0_/chanx_left_out[16] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/left_bottom_grid_pin_7_[0] -to fpga_top/sb_1__0_/chanx_left_out[16] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/left_bottom_grid_pin_15_[0] -to fpga_top/sb_1__0_/chanx_left_out[16] 6.020400151e-11 diff --git a/FPGA1212_FLAT_HD_SKY_PNR/FPGA1212_FLAT_HD_SKY_Verilog/SDC/sb_1__12_.sdc b/FPGA1212_FLAT_HD_SKY_PNR/FPGA1212_FLAT_HD_SKY_Verilog/SDC/sb_1__12_.sdc deleted file mode 100644 index 17cb8de..0000000 --- a/FPGA1212_FLAT_HD_SKY_PNR/FPGA1212_FLAT_HD_SKY_Verilog/SDC/sb_1__12_.sdc +++ /dev/null @@ -1,200 +0,0 @@ -############################################# -# Synopsys Design Constraints (SDC) -# For FPGA fabric -# Description: Constrain timing of Switch Block sb_1__12_ for PnR -# Author: Xifan TANG -# Organization: University of Utah -# Date: Sun Nov 29 02:09:07 2020 -############################################# - -############################################# -# Define time unit -############################################# -set_units -time s - -set_max_delay -from fpga_core_uut/sb_1__12_/right_top_grid_pin_1_[0] -to fpga_top/sb_1__12_/chanx_right_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/right_bottom_grid_pin_35_[0] -to fpga_top/sb_1__12_/chanx_right_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/right_bottom_grid_pin_37_[0] -to fpga_top/sb_1__12_/chanx_right_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/right_bottom_grid_pin_39_[0] -to fpga_top/sb_1__12_/chanx_right_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/right_bottom_grid_pin_41_[0] -to fpga_top/sb_1__12_/chanx_right_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[5] -to fpga_top/sb_1__12_/chanx_right_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[12] -to fpga_top/sb_1__12_/chanx_right_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[19] -to fpga_top/sb_1__12_/chanx_right_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[2] -to fpga_top/sb_1__12_/chanx_right_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[12] -to fpga_top/sb_1__12_/chanx_right_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/right_bottom_grid_pin_34_[0] -to fpga_top/sb_1__12_/chanx_right_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/right_bottom_grid_pin_36_[0] -to fpga_top/sb_1__12_/chanx_right_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/right_bottom_grid_pin_38_[0] -to fpga_top/sb_1__12_/chanx_right_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/right_bottom_grid_pin_40_[0] -to fpga_top/sb_1__12_/chanx_right_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[4] -to fpga_top/sb_1__12_/chanx_right_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[11] -to fpga_top/sb_1__12_/chanx_right_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[18] -to fpga_top/sb_1__12_/chanx_right_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[4] -to fpga_top/sb_1__12_/chanx_right_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[13] -to fpga_top/sb_1__12_/chanx_right_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/right_top_grid_pin_1_[0] -to fpga_top/sb_1__12_/chanx_right_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/right_bottom_grid_pin_34_[0] -to fpga_top/sb_1__12_/chanx_right_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/right_bottom_grid_pin_35_[0] -to fpga_top/sb_1__12_/chanx_right_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/right_bottom_grid_pin_36_[0] -to fpga_top/sb_1__12_/chanx_right_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/right_bottom_grid_pin_37_[0] -to fpga_top/sb_1__12_/chanx_right_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/right_bottom_grid_pin_38_[0] -to fpga_top/sb_1__12_/chanx_right_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/right_bottom_grid_pin_39_[0] -to fpga_top/sb_1__12_/chanx_right_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/right_bottom_grid_pin_40_[0] -to fpga_top/sb_1__12_/chanx_right_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/right_bottom_grid_pin_41_[0] -to fpga_top/sb_1__12_/chanx_right_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[3] -to fpga_top/sb_1__12_/chanx_right_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[10] -to fpga_top/sb_1__12_/chanx_right_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[17] -to fpga_top/sb_1__12_/chanx_right_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[5] -to fpga_top/sb_1__12_/chanx_right_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[14] -to fpga_top/sb_1__12_/chanx_right_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/right_top_grid_pin_1_[0] -to fpga_top/sb_1__12_/chanx_right_out[4] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/right_bottom_grid_pin_37_[0] -to fpga_top/sb_1__12_/chanx_right_out[4] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/right_bottom_grid_pin_41_[0] -to fpga_top/sb_1__12_/chanx_right_out[4] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[2] -to fpga_top/sb_1__12_/chanx_right_out[4] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[9] -to fpga_top/sb_1__12_/chanx_right_out[4] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[16] -to fpga_top/sb_1__12_/chanx_right_out[4] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[6] -to fpga_top/sb_1__12_/chanx_right_out[4] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[16] -to fpga_top/sb_1__12_/chanx_right_out[4] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/right_bottom_grid_pin_34_[0] -to fpga_top/sb_1__12_/chanx_right_out[8] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/right_bottom_grid_pin_38_[0] -to fpga_top/sb_1__12_/chanx_right_out[8] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[1] -to fpga_top/sb_1__12_/chanx_right_out[8] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[8] -to fpga_top/sb_1__12_/chanx_right_out[8] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[15] -to fpga_top/sb_1__12_/chanx_right_out[8] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[8] -to fpga_top/sb_1__12_/chanx_right_out[8] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[17] -to fpga_top/sb_1__12_/chanx_right_out[8] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/right_bottom_grid_pin_35_[0] -to fpga_top/sb_1__12_/chanx_right_out[12] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/right_bottom_grid_pin_39_[0] -to fpga_top/sb_1__12_/chanx_right_out[12] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[0] -to fpga_top/sb_1__12_/chanx_right_out[12] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[7] -to fpga_top/sb_1__12_/chanx_right_out[12] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[14] -to fpga_top/sb_1__12_/chanx_right_out[12] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[9] -to fpga_top/sb_1__12_/chanx_right_out[12] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[18] -to fpga_top/sb_1__12_/chanx_right_out[12] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/right_bottom_grid_pin_36_[0] -to fpga_top/sb_1__12_/chanx_right_out[16] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/right_bottom_grid_pin_40_[0] -to fpga_top/sb_1__12_/chanx_right_out[16] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[6] -to fpga_top/sb_1__12_/chanx_right_out[16] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[13] -to fpga_top/sb_1__12_/chanx_right_out[16] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[10] -to fpga_top/sb_1__12_/chanx_right_out[16] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[2] -to fpga_top/sb_1__12_/chany_bottom_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/bottom_left_grid_pin_42_[0] -to fpga_top/sb_1__12_/chany_bottom_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/bottom_left_grid_pin_44_[0] -to fpga_top/sb_1__12_/chany_bottom_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/bottom_left_grid_pin_46_[0] -to fpga_top/sb_1__12_/chany_bottom_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/bottom_left_grid_pin_48_[0] -to fpga_top/sb_1__12_/chany_bottom_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[1] -to fpga_top/sb_1__12_/chany_bottom_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[2] -to fpga_top/sb_1__12_/chany_bottom_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[4] -to fpga_top/sb_1__12_/chany_bottom_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/bottom_left_grid_pin_43_[0] -to fpga_top/sb_1__12_/chany_bottom_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/bottom_left_grid_pin_45_[0] -to fpga_top/sb_1__12_/chany_bottom_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/bottom_left_grid_pin_47_[0] -to fpga_top/sb_1__12_/chany_bottom_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/bottom_left_grid_pin_49_[0] -to fpga_top/sb_1__12_/chany_bottom_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[3] -to fpga_top/sb_1__12_/chany_bottom_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[4] -to fpga_top/sb_1__12_/chany_bottom_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[5] -to fpga_top/sb_1__12_/chany_bottom_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/bottom_left_grid_pin_42_[0] -to fpga_top/sb_1__12_/chany_bottom_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/bottom_left_grid_pin_44_[0] -to fpga_top/sb_1__12_/chany_bottom_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/bottom_left_grid_pin_46_[0] -to fpga_top/sb_1__12_/chany_bottom_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/bottom_left_grid_pin_48_[0] -to fpga_top/sb_1__12_/chany_bottom_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[5] -to fpga_top/sb_1__12_/chany_bottom_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[7] -to fpga_top/sb_1__12_/chany_bottom_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[6] -to fpga_top/sb_1__12_/chany_bottom_out[3] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/bottom_left_grid_pin_43_[0] -to fpga_top/sb_1__12_/chany_bottom_out[3] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/bottom_left_grid_pin_45_[0] -to fpga_top/sb_1__12_/chany_bottom_out[3] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/bottom_left_grid_pin_47_[0] -to fpga_top/sb_1__12_/chany_bottom_out[3] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/bottom_left_grid_pin_49_[0] -to fpga_top/sb_1__12_/chany_bottom_out[3] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[6] -to fpga_top/sb_1__12_/chany_bottom_out[3] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[11] -to fpga_top/sb_1__12_/chany_bottom_out[3] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[8] -to fpga_top/sb_1__12_/chany_bottom_out[4] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/bottom_left_grid_pin_42_[0] -to fpga_top/sb_1__12_/chany_bottom_out[4] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[8] -to fpga_top/sb_1__12_/chany_bottom_out[4] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[15] -to fpga_top/sb_1__12_/chany_bottom_out[4] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[9] -to fpga_top/sb_1__12_/chany_bottom_out[5] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/bottom_left_grid_pin_43_[0] -to fpga_top/sb_1__12_/chany_bottom_out[5] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[9] -to fpga_top/sb_1__12_/chany_bottom_out[5] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[19] -to fpga_top/sb_1__12_/chany_bottom_out[5] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[10] -to fpga_top/sb_1__12_/chany_bottom_out[6] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/bottom_left_grid_pin_44_[0] -to fpga_top/sb_1__12_/chany_bottom_out[6] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[10] -to fpga_top/sb_1__12_/chany_bottom_out[6] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[12] -to fpga_top/sb_1__12_/chany_bottom_out[7] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/bottom_left_grid_pin_45_[0] -to fpga_top/sb_1__12_/chany_bottom_out[7] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[12] -to fpga_top/sb_1__12_/chany_bottom_out[7] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[13] -to fpga_top/sb_1__12_/chany_bottom_out[8] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/bottom_left_grid_pin_46_[0] -to fpga_top/sb_1__12_/chany_bottom_out[8] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[13] -to fpga_top/sb_1__12_/chany_bottom_out[8] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[14] -to fpga_top/sb_1__12_/chany_bottom_out[9] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/bottom_left_grid_pin_47_[0] -to fpga_top/sb_1__12_/chany_bottom_out[9] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[14] -to fpga_top/sb_1__12_/chany_bottom_out[9] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[16] -to fpga_top/sb_1__12_/chany_bottom_out[10] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/bottom_left_grid_pin_48_[0] -to fpga_top/sb_1__12_/chany_bottom_out[10] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[16] -to fpga_top/sb_1__12_/chany_bottom_out[10] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[17] -to fpga_top/sb_1__12_/chany_bottom_out[11] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/bottom_left_grid_pin_49_[0] -to fpga_top/sb_1__12_/chany_bottom_out[11] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[17] -to fpga_top/sb_1__12_/chany_bottom_out[11] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[18] -to fpga_top/sb_1__12_/chany_bottom_out[12] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[19] -to fpga_top/sb_1__12_/chany_bottom_out[12] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/bottom_left_grid_pin_42_[0] -to fpga_top/sb_1__12_/chany_bottom_out[12] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[18] -to fpga_top/sb_1__12_/chany_bottom_out[12] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[15] -to fpga_top/sb_1__12_/chany_bottom_out[13] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/bottom_left_grid_pin_43_[0] -to fpga_top/sb_1__12_/chany_bottom_out[13] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[11] -to fpga_top/sb_1__12_/chany_bottom_out[14] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[7] -to fpga_top/sb_1__12_/chany_bottom_out[15] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[3] -to fpga_top/sb_1__12_/chany_bottom_out[16] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[1] -to fpga_top/sb_1__12_/chany_bottom_out[17] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[0] -to fpga_top/sb_1__12_/chany_bottom_out[18] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[0] -to fpga_top/sb_1__12_/chany_bottom_out[19] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[2] -to fpga_top/sb_1__12_/chanx_left_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[12] -to fpga_top/sb_1__12_/chanx_left_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[6] -to fpga_top/sb_1__12_/chanx_left_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[13] -to fpga_top/sb_1__12_/chanx_left_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/left_top_grid_pin_1_[0] -to fpga_top/sb_1__12_/chanx_left_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/left_bottom_grid_pin_35_[0] -to fpga_top/sb_1__12_/chanx_left_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/left_bottom_grid_pin_37_[0] -to fpga_top/sb_1__12_/chanx_left_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/left_bottom_grid_pin_39_[0] -to fpga_top/sb_1__12_/chanx_left_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/left_bottom_grid_pin_41_[0] -to fpga_top/sb_1__12_/chanx_left_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[4] -to fpga_top/sb_1__12_/chanx_left_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[13] -to fpga_top/sb_1__12_/chanx_left_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[0] -to fpga_top/sb_1__12_/chanx_left_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[7] -to fpga_top/sb_1__12_/chanx_left_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[14] -to fpga_top/sb_1__12_/chanx_left_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/left_bottom_grid_pin_34_[0] -to fpga_top/sb_1__12_/chanx_left_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/left_bottom_grid_pin_36_[0] -to fpga_top/sb_1__12_/chanx_left_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/left_bottom_grid_pin_38_[0] -to fpga_top/sb_1__12_/chanx_left_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/left_bottom_grid_pin_40_[0] -to fpga_top/sb_1__12_/chanx_left_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[5] -to fpga_top/sb_1__12_/chanx_left_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[14] -to fpga_top/sb_1__12_/chanx_left_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[1] -to fpga_top/sb_1__12_/chanx_left_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[8] -to fpga_top/sb_1__12_/chanx_left_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[15] -to fpga_top/sb_1__12_/chanx_left_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/left_top_grid_pin_1_[0] -to fpga_top/sb_1__12_/chanx_left_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/left_bottom_grid_pin_34_[0] -to fpga_top/sb_1__12_/chanx_left_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/left_bottom_grid_pin_35_[0] -to fpga_top/sb_1__12_/chanx_left_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/left_bottom_grid_pin_36_[0] -to fpga_top/sb_1__12_/chanx_left_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/left_bottom_grid_pin_37_[0] -to fpga_top/sb_1__12_/chanx_left_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/left_bottom_grid_pin_38_[0] -to fpga_top/sb_1__12_/chanx_left_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/left_bottom_grid_pin_39_[0] -to fpga_top/sb_1__12_/chanx_left_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/left_bottom_grid_pin_40_[0] -to fpga_top/sb_1__12_/chanx_left_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/left_bottom_grid_pin_41_[0] -to fpga_top/sb_1__12_/chanx_left_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[6] -to fpga_top/sb_1__12_/chanx_left_out[4] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[16] -to fpga_top/sb_1__12_/chanx_left_out[4] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[2] -to fpga_top/sb_1__12_/chanx_left_out[4] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[9] -to fpga_top/sb_1__12_/chanx_left_out[4] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[16] -to fpga_top/sb_1__12_/chanx_left_out[4] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/left_top_grid_pin_1_[0] -to fpga_top/sb_1__12_/chanx_left_out[4] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/left_bottom_grid_pin_37_[0] -to fpga_top/sb_1__12_/chanx_left_out[4] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/left_bottom_grid_pin_41_[0] -to fpga_top/sb_1__12_/chanx_left_out[4] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[8] -to fpga_top/sb_1__12_/chanx_left_out[8] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[17] -to fpga_top/sb_1__12_/chanx_left_out[8] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[3] -to fpga_top/sb_1__12_/chanx_left_out[8] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[10] -to fpga_top/sb_1__12_/chanx_left_out[8] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[17] -to fpga_top/sb_1__12_/chanx_left_out[8] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/left_bottom_grid_pin_34_[0] -to fpga_top/sb_1__12_/chanx_left_out[8] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/left_bottom_grid_pin_38_[0] -to fpga_top/sb_1__12_/chanx_left_out[8] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[9] -to fpga_top/sb_1__12_/chanx_left_out[12] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[18] -to fpga_top/sb_1__12_/chanx_left_out[12] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[4] -to fpga_top/sb_1__12_/chanx_left_out[12] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[11] -to fpga_top/sb_1__12_/chanx_left_out[12] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[18] -to fpga_top/sb_1__12_/chanx_left_out[12] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/left_bottom_grid_pin_35_[0] -to fpga_top/sb_1__12_/chanx_left_out[12] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/left_bottom_grid_pin_39_[0] -to fpga_top/sb_1__12_/chanx_left_out[12] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[10] -to fpga_top/sb_1__12_/chanx_left_out[16] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[5] -to fpga_top/sb_1__12_/chanx_left_out[16] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[12] -to fpga_top/sb_1__12_/chanx_left_out[16] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[19] -to fpga_top/sb_1__12_/chanx_left_out[16] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/left_bottom_grid_pin_36_[0] -to fpga_top/sb_1__12_/chanx_left_out[16] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/left_bottom_grid_pin_40_[0] -to fpga_top/sb_1__12_/chanx_left_out[16] 6.020400151e-11 diff --git a/FPGA1212_FLAT_HD_SKY_PNR/FPGA1212_FLAT_HD_SKY_Verilog/SDC/sb_1__1_.sdc b/FPGA1212_FLAT_HD_SKY_PNR/FPGA1212_FLAT_HD_SKY_Verilog/SDC/sb_1__1_.sdc deleted file mode 100644 index 5490fea..0000000 --- a/FPGA1212_FLAT_HD_SKY_PNR/FPGA1212_FLAT_HD_SKY_Verilog/SDC/sb_1__1_.sdc +++ /dev/null @@ -1,322 +0,0 @@ -############################################# -# Synopsys Design Constraints (SDC) -# For FPGA fabric -# Description: Constrain timing of Switch Block sb_1__1_ for PnR -# Author: Xifan TANG -# Organization: University of Utah -# Date: Sun Nov 29 02:09:07 2020 -############################################# - -############################################# -# Define time unit -############################################# -set_units -time s - -set_max_delay -from fpga_core_uut/sb_1__1_/top_left_grid_pin_42_[0] -to fpga_top/sb_1__1_/chany_top_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/top_left_grid_pin_44_[0] -to fpga_top/sb_1__1_/chany_top_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/top_left_grid_pin_46_[0] -to fpga_top/sb_1__1_/chany_top_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/top_left_grid_pin_48_[0] -to fpga_top/sb_1__1_/chany_top_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[1] -to fpga_top/sb_1__1_/chany_top_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[2] -to fpga_top/sb_1__1_/chany_top_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[12] -to fpga_top/sb_1__1_/chany_top_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[2] -to fpga_top/sb_1__1_/chany_top_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[12] -to fpga_top/sb_1__1_/chany_top_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[0] -to fpga_top/sb_1__1_/chany_top_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[2] -to fpga_top/sb_1__1_/chany_top_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[12] -to fpga_top/sb_1__1_/chany_top_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/top_left_grid_pin_43_[0] -to fpga_top/sb_1__1_/chany_top_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/top_left_grid_pin_45_[0] -to fpga_top/sb_1__1_/chany_top_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/top_left_grid_pin_47_[0] -to fpga_top/sb_1__1_/chany_top_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/top_left_grid_pin_49_[0] -to fpga_top/sb_1__1_/chany_top_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[3] -to fpga_top/sb_1__1_/chany_top_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[4] -to fpga_top/sb_1__1_/chany_top_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[13] -to fpga_top/sb_1__1_/chany_top_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[4] -to fpga_top/sb_1__1_/chany_top_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[13] -to fpga_top/sb_1__1_/chany_top_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[4] -to fpga_top/sb_1__1_/chany_top_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[13] -to fpga_top/sb_1__1_/chany_top_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[19] -to fpga_top/sb_1__1_/chany_top_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/top_left_grid_pin_42_[0] -to fpga_top/sb_1__1_/chany_top_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/top_left_grid_pin_43_[0] -to fpga_top/sb_1__1_/chany_top_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/top_left_grid_pin_44_[0] -to fpga_top/sb_1__1_/chany_top_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/top_left_grid_pin_45_[0] -to fpga_top/sb_1__1_/chany_top_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/top_left_grid_pin_46_[0] -to fpga_top/sb_1__1_/chany_top_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/top_left_grid_pin_47_[0] -to fpga_top/sb_1__1_/chany_top_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/top_left_grid_pin_48_[0] -to fpga_top/sb_1__1_/chany_top_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/top_left_grid_pin_49_[0] -to fpga_top/sb_1__1_/chany_top_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[5] -to fpga_top/sb_1__1_/chany_top_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[7] -to fpga_top/sb_1__1_/chany_top_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[14] -to fpga_top/sb_1__1_/chany_top_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[5] -to fpga_top/sb_1__1_/chany_top_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[14] -to fpga_top/sb_1__1_/chany_top_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[5] -to fpga_top/sb_1__1_/chany_top_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[14] -to fpga_top/sb_1__1_/chany_top_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[15] -to fpga_top/sb_1__1_/chany_top_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/top_left_grid_pin_42_[0] -to fpga_top/sb_1__1_/chany_top_out[4] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/top_left_grid_pin_46_[0] -to fpga_top/sb_1__1_/chany_top_out[4] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[6] -to fpga_top/sb_1__1_/chany_top_out[4] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[11] -to fpga_top/sb_1__1_/chany_top_out[4] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[16] -to fpga_top/sb_1__1_/chany_top_out[4] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[6] -to fpga_top/sb_1__1_/chany_top_out[4] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[16] -to fpga_top/sb_1__1_/chany_top_out[4] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[6] -to fpga_top/sb_1__1_/chany_top_out[4] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[11] -to fpga_top/sb_1__1_/chany_top_out[4] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[16] -to fpga_top/sb_1__1_/chany_top_out[4] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/top_left_grid_pin_43_[0] -to fpga_top/sb_1__1_/chany_top_out[8] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/top_left_grid_pin_47_[0] -to fpga_top/sb_1__1_/chany_top_out[8] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[8] -to fpga_top/sb_1__1_/chany_top_out[8] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[15] -to fpga_top/sb_1__1_/chany_top_out[8] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[17] -to fpga_top/sb_1__1_/chany_top_out[8] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[8] -to fpga_top/sb_1__1_/chany_top_out[8] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[17] -to fpga_top/sb_1__1_/chany_top_out[8] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[7] -to fpga_top/sb_1__1_/chany_top_out[8] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[8] -to fpga_top/sb_1__1_/chany_top_out[8] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[17] -to fpga_top/sb_1__1_/chany_top_out[8] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/top_left_grid_pin_44_[0] -to fpga_top/sb_1__1_/chany_top_out[12] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/top_left_grid_pin_48_[0] -to fpga_top/sb_1__1_/chany_top_out[12] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[9] -to fpga_top/sb_1__1_/chany_top_out[12] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[18] -to fpga_top/sb_1__1_/chany_top_out[12] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[19] -to fpga_top/sb_1__1_/chany_top_out[12] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[9] -to fpga_top/sb_1__1_/chany_top_out[12] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[18] -to fpga_top/sb_1__1_/chany_top_out[12] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[3] -to fpga_top/sb_1__1_/chany_top_out[12] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[9] -to fpga_top/sb_1__1_/chany_top_out[12] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[18] -to fpga_top/sb_1__1_/chany_top_out[12] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/top_left_grid_pin_45_[0] -to fpga_top/sb_1__1_/chany_top_out[16] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/top_left_grid_pin_49_[0] -to fpga_top/sb_1__1_/chany_top_out[16] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[0] -to fpga_top/sb_1__1_/chany_top_out[16] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[10] -to fpga_top/sb_1__1_/chany_top_out[16] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[10] -to fpga_top/sb_1__1_/chany_top_out[16] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[1] -to fpga_top/sb_1__1_/chany_top_out[16] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[10] -to fpga_top/sb_1__1_/chany_top_out[16] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[2] -to fpga_top/sb_1__1_/chanx_right_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[12] -to fpga_top/sb_1__1_/chanx_right_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[19] -to fpga_top/sb_1__1_/chanx_right_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/right_bottom_grid_pin_34_[0] -to fpga_top/sb_1__1_/chanx_right_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/right_bottom_grid_pin_36_[0] -to fpga_top/sb_1__1_/chanx_right_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/right_bottom_grid_pin_38_[0] -to fpga_top/sb_1__1_/chanx_right_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/right_bottom_grid_pin_40_[0] -to fpga_top/sb_1__1_/chanx_right_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[2] -to fpga_top/sb_1__1_/chanx_right_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[12] -to fpga_top/sb_1__1_/chanx_right_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[15] -to fpga_top/sb_1__1_/chanx_right_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[2] -to fpga_top/sb_1__1_/chanx_right_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[12] -to fpga_top/sb_1__1_/chanx_right_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[0] -to fpga_top/sb_1__1_/chanx_right_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[4] -to fpga_top/sb_1__1_/chanx_right_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[13] -to fpga_top/sb_1__1_/chanx_right_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/right_bottom_grid_pin_35_[0] -to fpga_top/sb_1__1_/chanx_right_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/right_bottom_grid_pin_37_[0] -to fpga_top/sb_1__1_/chanx_right_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/right_bottom_grid_pin_39_[0] -to fpga_top/sb_1__1_/chanx_right_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/right_bottom_grid_pin_41_[0] -to fpga_top/sb_1__1_/chanx_right_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[4] -to fpga_top/sb_1__1_/chanx_right_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[11] -to fpga_top/sb_1__1_/chanx_right_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[13] -to fpga_top/sb_1__1_/chanx_right_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[4] -to fpga_top/sb_1__1_/chanx_right_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[13] -to fpga_top/sb_1__1_/chanx_right_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[1] -to fpga_top/sb_1__1_/chanx_right_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[5] -to fpga_top/sb_1__1_/chanx_right_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[14] -to fpga_top/sb_1__1_/chanx_right_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/right_bottom_grid_pin_34_[0] -to fpga_top/sb_1__1_/chanx_right_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/right_bottom_grid_pin_35_[0] -to fpga_top/sb_1__1_/chanx_right_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/right_bottom_grid_pin_36_[0] -to fpga_top/sb_1__1_/chanx_right_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/right_bottom_grid_pin_37_[0] -to fpga_top/sb_1__1_/chanx_right_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/right_bottom_grid_pin_38_[0] -to fpga_top/sb_1__1_/chanx_right_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/right_bottom_grid_pin_39_[0] -to fpga_top/sb_1__1_/chanx_right_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/right_bottom_grid_pin_40_[0] -to fpga_top/sb_1__1_/chanx_right_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/right_bottom_grid_pin_41_[0] -to fpga_top/sb_1__1_/chanx_right_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[5] -to fpga_top/sb_1__1_/chanx_right_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[7] -to fpga_top/sb_1__1_/chanx_right_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[14] -to fpga_top/sb_1__1_/chanx_right_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[5] -to fpga_top/sb_1__1_/chanx_right_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[14] -to fpga_top/sb_1__1_/chanx_right_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[3] -to fpga_top/sb_1__1_/chanx_right_out[4] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[6] -to fpga_top/sb_1__1_/chanx_right_out[4] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[16] -to fpga_top/sb_1__1_/chanx_right_out[4] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/right_bottom_grid_pin_34_[0] -to fpga_top/sb_1__1_/chanx_right_out[4] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/right_bottom_grid_pin_38_[0] -to fpga_top/sb_1__1_/chanx_right_out[4] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[3] -to fpga_top/sb_1__1_/chanx_right_out[4] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[6] -to fpga_top/sb_1__1_/chanx_right_out[4] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[16] -to fpga_top/sb_1__1_/chanx_right_out[4] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[6] -to fpga_top/sb_1__1_/chanx_right_out[4] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[16] -to fpga_top/sb_1__1_/chanx_right_out[4] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[7] -to fpga_top/sb_1__1_/chanx_right_out[8] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[8] -to fpga_top/sb_1__1_/chanx_right_out[8] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[17] -to fpga_top/sb_1__1_/chanx_right_out[8] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/right_bottom_grid_pin_35_[0] -to fpga_top/sb_1__1_/chanx_right_out[8] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/right_bottom_grid_pin_39_[0] -to fpga_top/sb_1__1_/chanx_right_out[8] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[1] -to fpga_top/sb_1__1_/chanx_right_out[8] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[8] -to fpga_top/sb_1__1_/chanx_right_out[8] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[17] -to fpga_top/sb_1__1_/chanx_right_out[8] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[8] -to fpga_top/sb_1__1_/chanx_right_out[8] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[17] -to fpga_top/sb_1__1_/chanx_right_out[8] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[9] -to fpga_top/sb_1__1_/chanx_right_out[12] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[11] -to fpga_top/sb_1__1_/chanx_right_out[12] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[18] -to fpga_top/sb_1__1_/chanx_right_out[12] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/right_bottom_grid_pin_36_[0] -to fpga_top/sb_1__1_/chanx_right_out[12] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/right_bottom_grid_pin_40_[0] -to fpga_top/sb_1__1_/chanx_right_out[12] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[0] -to fpga_top/sb_1__1_/chanx_right_out[12] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[9] -to fpga_top/sb_1__1_/chanx_right_out[12] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[18] -to fpga_top/sb_1__1_/chanx_right_out[12] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[9] -to fpga_top/sb_1__1_/chanx_right_out[12] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[18] -to fpga_top/sb_1__1_/chanx_right_out[12] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[10] -to fpga_top/sb_1__1_/chanx_right_out[16] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[15] -to fpga_top/sb_1__1_/chanx_right_out[16] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/right_bottom_grid_pin_37_[0] -to fpga_top/sb_1__1_/chanx_right_out[16] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/right_bottom_grid_pin_41_[0] -to fpga_top/sb_1__1_/chanx_right_out[16] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[10] -to fpga_top/sb_1__1_/chanx_right_out[16] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[19] -to fpga_top/sb_1__1_/chanx_right_out[16] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[10] -to fpga_top/sb_1__1_/chanx_right_out[16] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[2] -to fpga_top/sb_1__1_/chany_bottom_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[12] -to fpga_top/sb_1__1_/chany_bottom_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[2] -to fpga_top/sb_1__1_/chany_bottom_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[12] -to fpga_top/sb_1__1_/chany_bottom_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[15] -to fpga_top/sb_1__1_/chany_bottom_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/bottom_left_grid_pin_42_[0] -to fpga_top/sb_1__1_/chany_bottom_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/bottom_left_grid_pin_44_[0] -to fpga_top/sb_1__1_/chany_bottom_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/bottom_left_grid_pin_46_[0] -to fpga_top/sb_1__1_/chany_bottom_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/bottom_left_grid_pin_48_[0] -to fpga_top/sb_1__1_/chany_bottom_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[1] -to fpga_top/sb_1__1_/chany_bottom_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[2] -to fpga_top/sb_1__1_/chany_bottom_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[12] -to fpga_top/sb_1__1_/chany_bottom_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[4] -to fpga_top/sb_1__1_/chany_bottom_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[13] -to fpga_top/sb_1__1_/chany_bottom_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[4] -to fpga_top/sb_1__1_/chany_bottom_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[11] -to fpga_top/sb_1__1_/chany_bottom_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[13] -to fpga_top/sb_1__1_/chany_bottom_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/bottom_left_grid_pin_43_[0] -to fpga_top/sb_1__1_/chany_bottom_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/bottom_left_grid_pin_45_[0] -to fpga_top/sb_1__1_/chany_bottom_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/bottom_left_grid_pin_47_[0] -to fpga_top/sb_1__1_/chany_bottom_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/bottom_left_grid_pin_49_[0] -to fpga_top/sb_1__1_/chany_bottom_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[3] -to fpga_top/sb_1__1_/chany_bottom_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[4] -to fpga_top/sb_1__1_/chany_bottom_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[13] -to fpga_top/sb_1__1_/chany_bottom_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[5] -to fpga_top/sb_1__1_/chany_bottom_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[14] -to fpga_top/sb_1__1_/chany_bottom_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[5] -to fpga_top/sb_1__1_/chany_bottom_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[7] -to fpga_top/sb_1__1_/chany_bottom_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[14] -to fpga_top/sb_1__1_/chany_bottom_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/bottom_left_grid_pin_42_[0] -to fpga_top/sb_1__1_/chany_bottom_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/bottom_left_grid_pin_43_[0] -to fpga_top/sb_1__1_/chany_bottom_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/bottom_left_grid_pin_44_[0] -to fpga_top/sb_1__1_/chany_bottom_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/bottom_left_grid_pin_45_[0] -to fpga_top/sb_1__1_/chany_bottom_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/bottom_left_grid_pin_46_[0] -to fpga_top/sb_1__1_/chany_bottom_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/bottom_left_grid_pin_47_[0] -to fpga_top/sb_1__1_/chany_bottom_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/bottom_left_grid_pin_48_[0] -to fpga_top/sb_1__1_/chany_bottom_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/bottom_left_grid_pin_49_[0] -to fpga_top/sb_1__1_/chany_bottom_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[5] -to fpga_top/sb_1__1_/chany_bottom_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[7] -to fpga_top/sb_1__1_/chany_bottom_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[14] -to fpga_top/sb_1__1_/chany_bottom_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[6] -to fpga_top/sb_1__1_/chany_bottom_out[4] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[16] -to fpga_top/sb_1__1_/chany_bottom_out[4] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[3] -to fpga_top/sb_1__1_/chany_bottom_out[4] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[6] -to fpga_top/sb_1__1_/chany_bottom_out[4] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[16] -to fpga_top/sb_1__1_/chany_bottom_out[4] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/bottom_left_grid_pin_42_[0] -to fpga_top/sb_1__1_/chany_bottom_out[4] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/bottom_left_grid_pin_46_[0] -to fpga_top/sb_1__1_/chany_bottom_out[4] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[6] -to fpga_top/sb_1__1_/chany_bottom_out[4] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[11] -to fpga_top/sb_1__1_/chany_bottom_out[4] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[16] -to fpga_top/sb_1__1_/chany_bottom_out[4] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[8] -to fpga_top/sb_1__1_/chany_bottom_out[8] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[17] -to fpga_top/sb_1__1_/chany_bottom_out[8] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[1] -to fpga_top/sb_1__1_/chany_bottom_out[8] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[8] -to fpga_top/sb_1__1_/chany_bottom_out[8] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[17] -to fpga_top/sb_1__1_/chany_bottom_out[8] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/bottom_left_grid_pin_43_[0] -to fpga_top/sb_1__1_/chany_bottom_out[8] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/bottom_left_grid_pin_47_[0] -to fpga_top/sb_1__1_/chany_bottom_out[8] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[8] -to fpga_top/sb_1__1_/chany_bottom_out[8] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[15] -to fpga_top/sb_1__1_/chany_bottom_out[8] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[17] -to fpga_top/sb_1__1_/chany_bottom_out[8] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[9] -to fpga_top/sb_1__1_/chany_bottom_out[12] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[18] -to fpga_top/sb_1__1_/chany_bottom_out[12] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[0] -to fpga_top/sb_1__1_/chany_bottom_out[12] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[9] -to fpga_top/sb_1__1_/chany_bottom_out[12] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[18] -to fpga_top/sb_1__1_/chany_bottom_out[12] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/bottom_left_grid_pin_44_[0] -to fpga_top/sb_1__1_/chany_bottom_out[12] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/bottom_left_grid_pin_48_[0] -to fpga_top/sb_1__1_/chany_bottom_out[12] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[9] -to fpga_top/sb_1__1_/chany_bottom_out[12] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[18] -to fpga_top/sb_1__1_/chany_bottom_out[12] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[19] -to fpga_top/sb_1__1_/chany_bottom_out[12] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[10] -to fpga_top/sb_1__1_/chany_bottom_out[16] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[10] -to fpga_top/sb_1__1_/chany_bottom_out[16] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[19] -to fpga_top/sb_1__1_/chany_bottom_out[16] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/bottom_left_grid_pin_45_[0] -to fpga_top/sb_1__1_/chany_bottom_out[16] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/bottom_left_grid_pin_49_[0] -to fpga_top/sb_1__1_/chany_bottom_out[16] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[0] -to fpga_top/sb_1__1_/chany_bottom_out[16] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[10] -to fpga_top/sb_1__1_/chany_bottom_out[16] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[0] -to fpga_top/sb_1__1_/chanx_left_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[2] -to fpga_top/sb_1__1_/chanx_left_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[12] -to fpga_top/sb_1__1_/chanx_left_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[2] -to fpga_top/sb_1__1_/chanx_left_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[12] -to fpga_top/sb_1__1_/chanx_left_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[2] -to fpga_top/sb_1__1_/chanx_left_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[12] -to fpga_top/sb_1__1_/chanx_left_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[19] -to fpga_top/sb_1__1_/chanx_left_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/left_bottom_grid_pin_34_[0] -to fpga_top/sb_1__1_/chanx_left_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/left_bottom_grid_pin_36_[0] -to fpga_top/sb_1__1_/chanx_left_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/left_bottom_grid_pin_38_[0] -to fpga_top/sb_1__1_/chanx_left_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/left_bottom_grid_pin_40_[0] -to fpga_top/sb_1__1_/chanx_left_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[4] -to fpga_top/sb_1__1_/chanx_left_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[13] -to fpga_top/sb_1__1_/chanx_left_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[19] -to fpga_top/sb_1__1_/chanx_left_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[4] -to fpga_top/sb_1__1_/chanx_left_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[13] -to fpga_top/sb_1__1_/chanx_left_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[0] -to fpga_top/sb_1__1_/chanx_left_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[4] -to fpga_top/sb_1__1_/chanx_left_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[13] -to fpga_top/sb_1__1_/chanx_left_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/left_bottom_grid_pin_35_[0] -to fpga_top/sb_1__1_/chanx_left_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/left_bottom_grid_pin_37_[0] -to fpga_top/sb_1__1_/chanx_left_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/left_bottom_grid_pin_39_[0] -to fpga_top/sb_1__1_/chanx_left_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/left_bottom_grid_pin_41_[0] -to fpga_top/sb_1__1_/chanx_left_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[5] -to fpga_top/sb_1__1_/chanx_left_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[14] -to fpga_top/sb_1__1_/chanx_left_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[15] -to fpga_top/sb_1__1_/chanx_left_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[5] -to fpga_top/sb_1__1_/chanx_left_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[14] -to fpga_top/sb_1__1_/chanx_left_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[1] -to fpga_top/sb_1__1_/chanx_left_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[5] -to fpga_top/sb_1__1_/chanx_left_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[14] -to fpga_top/sb_1__1_/chanx_left_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/left_bottom_grid_pin_34_[0] -to fpga_top/sb_1__1_/chanx_left_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/left_bottom_grid_pin_35_[0] -to fpga_top/sb_1__1_/chanx_left_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/left_bottom_grid_pin_36_[0] -to fpga_top/sb_1__1_/chanx_left_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/left_bottom_grid_pin_37_[0] -to fpga_top/sb_1__1_/chanx_left_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/left_bottom_grid_pin_38_[0] -to fpga_top/sb_1__1_/chanx_left_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/left_bottom_grid_pin_39_[0] -to fpga_top/sb_1__1_/chanx_left_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/left_bottom_grid_pin_40_[0] -to fpga_top/sb_1__1_/chanx_left_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/left_bottom_grid_pin_41_[0] -to fpga_top/sb_1__1_/chanx_left_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[6] -to fpga_top/sb_1__1_/chanx_left_out[4] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[11] -to fpga_top/sb_1__1_/chanx_left_out[4] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[16] -to fpga_top/sb_1__1_/chanx_left_out[4] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[6] -to fpga_top/sb_1__1_/chanx_left_out[4] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[16] -to fpga_top/sb_1__1_/chanx_left_out[4] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[3] -to fpga_top/sb_1__1_/chanx_left_out[4] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[6] -to fpga_top/sb_1__1_/chanx_left_out[4] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[16] -to fpga_top/sb_1__1_/chanx_left_out[4] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/left_bottom_grid_pin_34_[0] -to fpga_top/sb_1__1_/chanx_left_out[4] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/left_bottom_grid_pin_38_[0] -to fpga_top/sb_1__1_/chanx_left_out[4] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[7] -to fpga_top/sb_1__1_/chanx_left_out[8] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[8] -to fpga_top/sb_1__1_/chanx_left_out[8] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[17] -to fpga_top/sb_1__1_/chanx_left_out[8] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[8] -to fpga_top/sb_1__1_/chanx_left_out[8] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[17] -to fpga_top/sb_1__1_/chanx_left_out[8] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[7] -to fpga_top/sb_1__1_/chanx_left_out[8] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[8] -to fpga_top/sb_1__1_/chanx_left_out[8] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[17] -to fpga_top/sb_1__1_/chanx_left_out[8] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/left_bottom_grid_pin_35_[0] -to fpga_top/sb_1__1_/chanx_left_out[8] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/left_bottom_grid_pin_39_[0] -to fpga_top/sb_1__1_/chanx_left_out[8] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[3] -to fpga_top/sb_1__1_/chanx_left_out[12] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[9] -to fpga_top/sb_1__1_/chanx_left_out[12] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[18] -to fpga_top/sb_1__1_/chanx_left_out[12] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[9] -to fpga_top/sb_1__1_/chanx_left_out[12] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[18] -to fpga_top/sb_1__1_/chanx_left_out[12] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[9] -to fpga_top/sb_1__1_/chanx_left_out[12] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[11] -to fpga_top/sb_1__1_/chanx_left_out[12] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[18] -to fpga_top/sb_1__1_/chanx_left_out[12] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/left_bottom_grid_pin_36_[0] -to fpga_top/sb_1__1_/chanx_left_out[12] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/left_bottom_grid_pin_40_[0] -to fpga_top/sb_1__1_/chanx_left_out[12] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[1] -to fpga_top/sb_1__1_/chanx_left_out[16] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[10] -to fpga_top/sb_1__1_/chanx_left_out[16] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[10] -to fpga_top/sb_1__1_/chanx_left_out[16] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[10] -to fpga_top/sb_1__1_/chanx_left_out[16] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[15] -to fpga_top/sb_1__1_/chanx_left_out[16] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/left_bottom_grid_pin_37_[0] -to fpga_top/sb_1__1_/chanx_left_out[16] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/left_bottom_grid_pin_41_[0] -to fpga_top/sb_1__1_/chanx_left_out[16] 6.020400151e-11 diff --git a/FPGA1212_RESET_HD_SKY_PNR/FPGA1212_RESET_HD_SKY_Verilog/SDC/cbx_1__0_.sdc b/FPGA1212_RESET_HD_SKY_PNR/FPGA1212_RESET_HD_SKY_Verilog/SDC/cbx_1__0_.sdc deleted file mode 100644 index 1136ff6..0000000 --- a/FPGA1212_RESET_HD_SKY_PNR/FPGA1212_RESET_HD_SKY_Verilog/SDC/cbx_1__0_.sdc +++ /dev/null @@ -1,182 +0,0 @@ -############################################# -# Synopsys Design Constraints (SDC) -# For FPGA fabric -# Description: Constrain timing of Connection Block cbx_1__0_ for PnR -# Author: Xifan TANG -# Organization: University of Utah -# Date: Tue Dec 1 18:12:04 2020 -############################################# - -############################################# -# Define time unit -############################################# -set_units -time s - -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[0] -to fpga_top/cbx_1__0_/chanx_left_out[0] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[0] -to fpga_top/cbx_1__0_/chanx_right_out[0] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[1] -to fpga_top/cbx_1__0_/chanx_left_out[1] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[1] -to fpga_top/cbx_1__0_/chanx_right_out[1] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[2] -to fpga_top/cbx_1__0_/chanx_left_out[2] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[2] -to fpga_top/cbx_1__0_/chanx_right_out[2] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[3] -to fpga_top/cbx_1__0_/chanx_left_out[3] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[3] -to fpga_top/cbx_1__0_/chanx_right_out[3] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[4] -to fpga_top/cbx_1__0_/chanx_left_out[4] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[4] -to fpga_top/cbx_1__0_/chanx_right_out[4] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[5] -to fpga_top/cbx_1__0_/chanx_left_out[5] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[5] -to fpga_top/cbx_1__0_/chanx_right_out[5] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[6] -to fpga_top/cbx_1__0_/chanx_left_out[6] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[6] -to fpga_top/cbx_1__0_/chanx_right_out[6] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[7] -to fpga_top/cbx_1__0_/chanx_left_out[7] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[7] -to fpga_top/cbx_1__0_/chanx_right_out[7] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[8] -to fpga_top/cbx_1__0_/chanx_left_out[8] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[8] -to fpga_top/cbx_1__0_/chanx_right_out[8] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[9] -to fpga_top/cbx_1__0_/chanx_left_out[9] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[9] -to fpga_top/cbx_1__0_/chanx_right_out[9] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[10] -to fpga_top/cbx_1__0_/chanx_left_out[10] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[10] -to fpga_top/cbx_1__0_/chanx_right_out[10] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[11] -to fpga_top/cbx_1__0_/chanx_left_out[11] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[11] -to fpga_top/cbx_1__0_/chanx_right_out[11] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[12] -to fpga_top/cbx_1__0_/chanx_left_out[12] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[12] -to fpga_top/cbx_1__0_/chanx_right_out[12] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[13] -to fpga_top/cbx_1__0_/chanx_left_out[13] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[13] -to fpga_top/cbx_1__0_/chanx_right_out[13] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[14] -to fpga_top/cbx_1__0_/chanx_left_out[14] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[14] -to fpga_top/cbx_1__0_/chanx_right_out[14] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[15] -to fpga_top/cbx_1__0_/chanx_left_out[15] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[15] -to fpga_top/cbx_1__0_/chanx_right_out[15] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[16] -to fpga_top/cbx_1__0_/chanx_left_out[16] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[16] -to fpga_top/cbx_1__0_/chanx_right_out[16] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[17] -to fpga_top/cbx_1__0_/chanx_left_out[17] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[17] -to fpga_top/cbx_1__0_/chanx_right_out[17] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[18] -to fpga_top/cbx_1__0_/chanx_left_out[18] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[18] -to fpga_top/cbx_1__0_/chanx_right_out[18] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[19] -to fpga_top/cbx_1__0_/chanx_left_out[19] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[19] -to fpga_top/cbx_1__0_/chanx_right_out[19] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[20] -to fpga_top/cbx_1__0_/chanx_left_out[20] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[20] -to fpga_top/cbx_1__0_/chanx_right_out[20] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[21] -to fpga_top/cbx_1__0_/chanx_left_out[21] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[21] -to fpga_top/cbx_1__0_/chanx_right_out[21] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[22] -to fpga_top/cbx_1__0_/chanx_left_out[22] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[22] -to fpga_top/cbx_1__0_/chanx_right_out[22] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[23] -to fpga_top/cbx_1__0_/chanx_left_out[23] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[23] -to fpga_top/cbx_1__0_/chanx_right_out[23] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[24] -to fpga_top/cbx_1__0_/chanx_left_out[24] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[24] -to fpga_top/cbx_1__0_/chanx_right_out[24] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[25] -to fpga_top/cbx_1__0_/chanx_left_out[25] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[25] -to fpga_top/cbx_1__0_/chanx_right_out[25] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[26] -to fpga_top/cbx_1__0_/chanx_left_out[26] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[26] -to fpga_top/cbx_1__0_/chanx_right_out[26] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[27] -to fpga_top/cbx_1__0_/chanx_left_out[27] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[27] -to fpga_top/cbx_1__0_/chanx_right_out[27] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[28] -to fpga_top/cbx_1__0_/chanx_left_out[28] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[28] -to fpga_top/cbx_1__0_/chanx_right_out[28] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[29] -to fpga_top/cbx_1__0_/chanx_left_out[29] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[29] -to fpga_top/cbx_1__0_/chanx_right_out[29] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[0] -to fpga_top/cbx_1__0_/bottom_grid_pin_0_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[0] -to fpga_top/cbx_1__0_/bottom_grid_pin_0_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[3] -to fpga_top/cbx_1__0_/bottom_grid_pin_0_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[3] -to fpga_top/cbx_1__0_/bottom_grid_pin_0_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[6] -to fpga_top/cbx_1__0_/bottom_grid_pin_0_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[6] -to fpga_top/cbx_1__0_/bottom_grid_pin_0_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[12] -to fpga_top/cbx_1__0_/bottom_grid_pin_0_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[12] -to fpga_top/cbx_1__0_/bottom_grid_pin_0_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[18] -to fpga_top/cbx_1__0_/bottom_grid_pin_0_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[18] -to fpga_top/cbx_1__0_/bottom_grid_pin_0_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[24] -to fpga_top/cbx_1__0_/bottom_grid_pin_0_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[24] -to fpga_top/cbx_1__0_/bottom_grid_pin_0_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[1] -to fpga_top/cbx_1__0_/bottom_grid_pin_2_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[1] -to fpga_top/cbx_1__0_/bottom_grid_pin_2_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[4] -to fpga_top/cbx_1__0_/bottom_grid_pin_2_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[4] -to fpga_top/cbx_1__0_/bottom_grid_pin_2_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[7] -to fpga_top/cbx_1__0_/bottom_grid_pin_2_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[7] -to fpga_top/cbx_1__0_/bottom_grid_pin_2_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[13] -to fpga_top/cbx_1__0_/bottom_grid_pin_2_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[13] -to fpga_top/cbx_1__0_/bottom_grid_pin_2_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[19] -to fpga_top/cbx_1__0_/bottom_grid_pin_2_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[19] -to fpga_top/cbx_1__0_/bottom_grid_pin_2_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[25] -to fpga_top/cbx_1__0_/bottom_grid_pin_2_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[25] -to fpga_top/cbx_1__0_/bottom_grid_pin_2_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[2] -to fpga_top/cbx_1__0_/bottom_grid_pin_4_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[2] -to fpga_top/cbx_1__0_/bottom_grid_pin_4_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[5] -to fpga_top/cbx_1__0_/bottom_grid_pin_4_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[5] -to fpga_top/cbx_1__0_/bottom_grid_pin_4_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[8] -to fpga_top/cbx_1__0_/bottom_grid_pin_4_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[8] -to fpga_top/cbx_1__0_/bottom_grid_pin_4_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[14] -to fpga_top/cbx_1__0_/bottom_grid_pin_4_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[14] -to fpga_top/cbx_1__0_/bottom_grid_pin_4_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[20] -to fpga_top/cbx_1__0_/bottom_grid_pin_4_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[20] -to fpga_top/cbx_1__0_/bottom_grid_pin_4_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[26] -to fpga_top/cbx_1__0_/bottom_grid_pin_4_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[26] -to fpga_top/cbx_1__0_/bottom_grid_pin_4_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[0] -to fpga_top/cbx_1__0_/bottom_grid_pin_6_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[0] -to fpga_top/cbx_1__0_/bottom_grid_pin_6_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[3] -to fpga_top/cbx_1__0_/bottom_grid_pin_6_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[3] -to fpga_top/cbx_1__0_/bottom_grid_pin_6_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[9] -to fpga_top/cbx_1__0_/bottom_grid_pin_6_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[9] -to fpga_top/cbx_1__0_/bottom_grid_pin_6_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[15] -to fpga_top/cbx_1__0_/bottom_grid_pin_6_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[15] -to fpga_top/cbx_1__0_/bottom_grid_pin_6_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[21] -to fpga_top/cbx_1__0_/bottom_grid_pin_6_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[21] -to fpga_top/cbx_1__0_/bottom_grid_pin_6_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[27] -to fpga_top/cbx_1__0_/bottom_grid_pin_6_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[27] -to fpga_top/cbx_1__0_/bottom_grid_pin_6_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[1] -to fpga_top/cbx_1__0_/bottom_grid_pin_8_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[1] -to fpga_top/cbx_1__0_/bottom_grid_pin_8_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[4] -to fpga_top/cbx_1__0_/bottom_grid_pin_8_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[4] -to fpga_top/cbx_1__0_/bottom_grid_pin_8_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[10] -to fpga_top/cbx_1__0_/bottom_grid_pin_8_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[10] -to fpga_top/cbx_1__0_/bottom_grid_pin_8_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[16] -to fpga_top/cbx_1__0_/bottom_grid_pin_8_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[16] -to fpga_top/cbx_1__0_/bottom_grid_pin_8_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[22] -to fpga_top/cbx_1__0_/bottom_grid_pin_8_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[22] -to fpga_top/cbx_1__0_/bottom_grid_pin_8_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[28] -to fpga_top/cbx_1__0_/bottom_grid_pin_8_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[28] -to fpga_top/cbx_1__0_/bottom_grid_pin_8_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[2] -to fpga_top/cbx_1__0_/bottom_grid_pin_10_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[2] -to fpga_top/cbx_1__0_/bottom_grid_pin_10_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[5] -to fpga_top/cbx_1__0_/bottom_grid_pin_10_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[5] -to fpga_top/cbx_1__0_/bottom_grid_pin_10_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[11] -to fpga_top/cbx_1__0_/bottom_grid_pin_10_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[11] -to fpga_top/cbx_1__0_/bottom_grid_pin_10_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[17] -to fpga_top/cbx_1__0_/bottom_grid_pin_10_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[17] -to fpga_top/cbx_1__0_/bottom_grid_pin_10_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[23] -to fpga_top/cbx_1__0_/bottom_grid_pin_10_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[23] -to fpga_top/cbx_1__0_/bottom_grid_pin_10_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[29] -to fpga_top/cbx_1__0_/bottom_grid_pin_10_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[29] -to fpga_top/cbx_1__0_/bottom_grid_pin_10_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[0] -to fpga_top/cbx_1__0_/bottom_grid_pin_12_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[0] -to fpga_top/cbx_1__0_/bottom_grid_pin_12_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[3] -to fpga_top/cbx_1__0_/bottom_grid_pin_12_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[3] -to fpga_top/cbx_1__0_/bottom_grid_pin_12_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[6] -to fpga_top/cbx_1__0_/bottom_grid_pin_12_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[6] -to fpga_top/cbx_1__0_/bottom_grid_pin_12_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[12] -to fpga_top/cbx_1__0_/bottom_grid_pin_12_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[12] -to fpga_top/cbx_1__0_/bottom_grid_pin_12_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[18] -to fpga_top/cbx_1__0_/bottom_grid_pin_12_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[18] -to fpga_top/cbx_1__0_/bottom_grid_pin_12_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[24] -to fpga_top/cbx_1__0_/bottom_grid_pin_12_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[24] -to fpga_top/cbx_1__0_/bottom_grid_pin_12_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[1] -to fpga_top/cbx_1__0_/bottom_grid_pin_14_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[1] -to fpga_top/cbx_1__0_/bottom_grid_pin_14_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[4] -to fpga_top/cbx_1__0_/bottom_grid_pin_14_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[4] -to fpga_top/cbx_1__0_/bottom_grid_pin_14_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[7] -to fpga_top/cbx_1__0_/bottom_grid_pin_14_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[7] -to fpga_top/cbx_1__0_/bottom_grid_pin_14_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[13] -to fpga_top/cbx_1__0_/bottom_grid_pin_14_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[13] -to fpga_top/cbx_1__0_/bottom_grid_pin_14_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[19] -to fpga_top/cbx_1__0_/bottom_grid_pin_14_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[19] -to fpga_top/cbx_1__0_/bottom_grid_pin_14_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[25] -to fpga_top/cbx_1__0_/bottom_grid_pin_14_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[25] -to fpga_top/cbx_1__0_/bottom_grid_pin_14_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[2] -to fpga_top/cbx_1__0_/bottom_grid_pin_16_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[2] -to fpga_top/cbx_1__0_/bottom_grid_pin_16_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[5] -to fpga_top/cbx_1__0_/bottom_grid_pin_16_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[5] -to fpga_top/cbx_1__0_/bottom_grid_pin_16_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[8] -to fpga_top/cbx_1__0_/bottom_grid_pin_16_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[8] -to fpga_top/cbx_1__0_/bottom_grid_pin_16_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[14] -to fpga_top/cbx_1__0_/bottom_grid_pin_16_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[14] -to fpga_top/cbx_1__0_/bottom_grid_pin_16_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[20] -to fpga_top/cbx_1__0_/bottom_grid_pin_16_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[20] -to fpga_top/cbx_1__0_/bottom_grid_pin_16_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[26] -to fpga_top/cbx_1__0_/bottom_grid_pin_16_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[26] -to fpga_top/cbx_1__0_/bottom_grid_pin_16_[0] 7.247000222e-11 diff --git a/FPGA1212_RESET_HD_SKY_PNR/FPGA1212_RESET_HD_SKY_Verilog/SDC/cbx_1__12_.sdc b/FPGA1212_RESET_HD_SKY_PNR/FPGA1212_RESET_HD_SKY_Verilog/SDC/cbx_1__12_.sdc deleted file mode 100644 index fb5acbe..0000000 --- a/FPGA1212_RESET_HD_SKY_PNR/FPGA1212_RESET_HD_SKY_Verilog/SDC/cbx_1__12_.sdc +++ /dev/null @@ -1,262 +0,0 @@ -############################################# -# Synopsys Design Constraints (SDC) -# For FPGA fabric -# Description: Constrain timing of Connection Block cbx_1__12_ for PnR -# Author: Xifan TANG -# Organization: University of Utah -# Date: Tue Dec 1 18:12:04 2020 -############################################# - -############################################# -# Define time unit -############################################# -set_units -time s - -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[0] -to fpga_top/cbx_1__12_/chanx_left_out[0] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[0] -to fpga_top/cbx_1__12_/chanx_right_out[0] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[1] -to fpga_top/cbx_1__12_/chanx_left_out[1] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[1] -to fpga_top/cbx_1__12_/chanx_right_out[1] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[2] -to fpga_top/cbx_1__12_/chanx_left_out[2] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[2] -to fpga_top/cbx_1__12_/chanx_right_out[2] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[3] -to fpga_top/cbx_1__12_/chanx_left_out[3] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[3] -to fpga_top/cbx_1__12_/chanx_right_out[3] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[4] -to fpga_top/cbx_1__12_/chanx_left_out[4] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[4] -to fpga_top/cbx_1__12_/chanx_right_out[4] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[5] -to fpga_top/cbx_1__12_/chanx_left_out[5] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[5] -to fpga_top/cbx_1__12_/chanx_right_out[5] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[6] -to fpga_top/cbx_1__12_/chanx_left_out[6] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[6] -to fpga_top/cbx_1__12_/chanx_right_out[6] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[7] -to fpga_top/cbx_1__12_/chanx_left_out[7] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[7] -to fpga_top/cbx_1__12_/chanx_right_out[7] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[8] -to fpga_top/cbx_1__12_/chanx_left_out[8] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[8] -to fpga_top/cbx_1__12_/chanx_right_out[8] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[9] -to fpga_top/cbx_1__12_/chanx_left_out[9] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[9] -to fpga_top/cbx_1__12_/chanx_right_out[9] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[10] -to fpga_top/cbx_1__12_/chanx_left_out[10] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[10] -to fpga_top/cbx_1__12_/chanx_right_out[10] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[11] -to fpga_top/cbx_1__12_/chanx_left_out[11] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[11] -to fpga_top/cbx_1__12_/chanx_right_out[11] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[12] -to fpga_top/cbx_1__12_/chanx_left_out[12] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[12] -to fpga_top/cbx_1__12_/chanx_right_out[12] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[13] -to fpga_top/cbx_1__12_/chanx_left_out[13] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[13] -to fpga_top/cbx_1__12_/chanx_right_out[13] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[14] -to fpga_top/cbx_1__12_/chanx_left_out[14] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[14] -to fpga_top/cbx_1__12_/chanx_right_out[14] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[15] -to fpga_top/cbx_1__12_/chanx_left_out[15] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[15] -to fpga_top/cbx_1__12_/chanx_right_out[15] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[16] -to fpga_top/cbx_1__12_/chanx_left_out[16] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[16] -to fpga_top/cbx_1__12_/chanx_right_out[16] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[17] -to fpga_top/cbx_1__12_/chanx_left_out[17] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[17] -to fpga_top/cbx_1__12_/chanx_right_out[17] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[18] -to fpga_top/cbx_1__12_/chanx_left_out[18] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[18] -to fpga_top/cbx_1__12_/chanx_right_out[18] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[19] -to fpga_top/cbx_1__12_/chanx_left_out[19] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[19] -to fpga_top/cbx_1__12_/chanx_right_out[19] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[20] -to fpga_top/cbx_1__12_/chanx_left_out[20] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[20] -to fpga_top/cbx_1__12_/chanx_right_out[20] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[21] -to fpga_top/cbx_1__12_/chanx_left_out[21] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[21] -to fpga_top/cbx_1__12_/chanx_right_out[21] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[22] -to fpga_top/cbx_1__12_/chanx_left_out[22] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[22] -to fpga_top/cbx_1__12_/chanx_right_out[22] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[23] -to fpga_top/cbx_1__12_/chanx_left_out[23] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[23] -to fpga_top/cbx_1__12_/chanx_right_out[23] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[24] -to fpga_top/cbx_1__12_/chanx_left_out[24] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[24] -to fpga_top/cbx_1__12_/chanx_right_out[24] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[25] -to fpga_top/cbx_1__12_/chanx_left_out[25] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[25] -to fpga_top/cbx_1__12_/chanx_right_out[25] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[26] -to fpga_top/cbx_1__12_/chanx_left_out[26] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[26] -to fpga_top/cbx_1__12_/chanx_right_out[26] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[27] -to fpga_top/cbx_1__12_/chanx_left_out[27] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[27] -to fpga_top/cbx_1__12_/chanx_right_out[27] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[28] -to fpga_top/cbx_1__12_/chanx_left_out[28] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[28] -to fpga_top/cbx_1__12_/chanx_right_out[28] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[29] -to fpga_top/cbx_1__12_/chanx_left_out[29] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[29] -to fpga_top/cbx_1__12_/chanx_right_out[29] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[0] -to fpga_top/cbx_1__12_/top_grid_pin_0_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[0] -to fpga_top/cbx_1__12_/top_grid_pin_0_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[3] -to fpga_top/cbx_1__12_/top_grid_pin_0_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[3] -to fpga_top/cbx_1__12_/top_grid_pin_0_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[6] -to fpga_top/cbx_1__12_/top_grid_pin_0_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[6] -to fpga_top/cbx_1__12_/top_grid_pin_0_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[12] -to fpga_top/cbx_1__12_/top_grid_pin_0_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[12] -to fpga_top/cbx_1__12_/top_grid_pin_0_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[18] -to fpga_top/cbx_1__12_/top_grid_pin_0_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[18] -to fpga_top/cbx_1__12_/top_grid_pin_0_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[24] -to fpga_top/cbx_1__12_/top_grid_pin_0_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[24] -to fpga_top/cbx_1__12_/top_grid_pin_0_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[1] -to fpga_top/cbx_1__12_/bottom_grid_pin_0_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[1] -to fpga_top/cbx_1__12_/bottom_grid_pin_0_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[4] -to fpga_top/cbx_1__12_/bottom_grid_pin_0_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[4] -to fpga_top/cbx_1__12_/bottom_grid_pin_0_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[7] -to fpga_top/cbx_1__12_/bottom_grid_pin_0_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[7] -to fpga_top/cbx_1__12_/bottom_grid_pin_0_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[13] -to fpga_top/cbx_1__12_/bottom_grid_pin_0_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[13] -to fpga_top/cbx_1__12_/bottom_grid_pin_0_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[19] -to fpga_top/cbx_1__12_/bottom_grid_pin_0_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[19] -to fpga_top/cbx_1__12_/bottom_grid_pin_0_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[25] -to fpga_top/cbx_1__12_/bottom_grid_pin_0_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[25] -to fpga_top/cbx_1__12_/bottom_grid_pin_0_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[2] -to fpga_top/cbx_1__12_/bottom_grid_pin_1_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[2] -to fpga_top/cbx_1__12_/bottom_grid_pin_1_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[5] -to fpga_top/cbx_1__12_/bottom_grid_pin_1_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[5] -to fpga_top/cbx_1__12_/bottom_grid_pin_1_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[8] -to fpga_top/cbx_1__12_/bottom_grid_pin_1_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[8] -to fpga_top/cbx_1__12_/bottom_grid_pin_1_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[17] -to fpga_top/cbx_1__12_/bottom_grid_pin_1_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[17] -to fpga_top/cbx_1__12_/bottom_grid_pin_1_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[26] -to fpga_top/cbx_1__12_/bottom_grid_pin_1_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[26] -to fpga_top/cbx_1__12_/bottom_grid_pin_1_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[0] -to fpga_top/cbx_1__12_/bottom_grid_pin_2_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[0] -to fpga_top/cbx_1__12_/bottom_grid_pin_2_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[3] -to fpga_top/cbx_1__12_/bottom_grid_pin_2_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[3] -to fpga_top/cbx_1__12_/bottom_grid_pin_2_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[9] -to fpga_top/cbx_1__12_/bottom_grid_pin_2_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[9] -to fpga_top/cbx_1__12_/bottom_grid_pin_2_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[15] -to fpga_top/cbx_1__12_/bottom_grid_pin_2_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[15] -to fpga_top/cbx_1__12_/bottom_grid_pin_2_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[21] -to fpga_top/cbx_1__12_/bottom_grid_pin_2_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[21] -to fpga_top/cbx_1__12_/bottom_grid_pin_2_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[27] -to fpga_top/cbx_1__12_/bottom_grid_pin_2_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[27] -to fpga_top/cbx_1__12_/bottom_grid_pin_2_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[1] -to fpga_top/cbx_1__12_/bottom_grid_pin_3_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[1] -to fpga_top/cbx_1__12_/bottom_grid_pin_3_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[4] -to fpga_top/cbx_1__12_/bottom_grid_pin_3_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[4] -to fpga_top/cbx_1__12_/bottom_grid_pin_3_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[10] -to fpga_top/cbx_1__12_/bottom_grid_pin_3_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[10] -to fpga_top/cbx_1__12_/bottom_grid_pin_3_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[19] -to fpga_top/cbx_1__12_/bottom_grid_pin_3_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[19] -to fpga_top/cbx_1__12_/bottom_grid_pin_3_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[28] -to fpga_top/cbx_1__12_/bottom_grid_pin_3_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[28] -to fpga_top/cbx_1__12_/bottom_grid_pin_3_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[2] -to fpga_top/cbx_1__12_/bottom_grid_pin_4_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[2] -to fpga_top/cbx_1__12_/bottom_grid_pin_4_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[5] -to fpga_top/cbx_1__12_/bottom_grid_pin_4_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[5] -to fpga_top/cbx_1__12_/bottom_grid_pin_4_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[11] -to fpga_top/cbx_1__12_/bottom_grid_pin_4_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[11] -to fpga_top/cbx_1__12_/bottom_grid_pin_4_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[17] -to fpga_top/cbx_1__12_/bottom_grid_pin_4_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[17] -to fpga_top/cbx_1__12_/bottom_grid_pin_4_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[23] -to fpga_top/cbx_1__12_/bottom_grid_pin_4_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[23] -to fpga_top/cbx_1__12_/bottom_grid_pin_4_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[29] -to fpga_top/cbx_1__12_/bottom_grid_pin_4_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[29] -to fpga_top/cbx_1__12_/bottom_grid_pin_4_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[0] -to fpga_top/cbx_1__12_/bottom_grid_pin_5_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[0] -to fpga_top/cbx_1__12_/bottom_grid_pin_5_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[3] -to fpga_top/cbx_1__12_/bottom_grid_pin_5_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[3] -to fpga_top/cbx_1__12_/bottom_grid_pin_5_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[6] -to fpga_top/cbx_1__12_/bottom_grid_pin_5_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[6] -to fpga_top/cbx_1__12_/bottom_grid_pin_5_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[12] -to fpga_top/cbx_1__12_/bottom_grid_pin_5_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[12] -to fpga_top/cbx_1__12_/bottom_grid_pin_5_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[21] -to fpga_top/cbx_1__12_/bottom_grid_pin_5_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[21] -to fpga_top/cbx_1__12_/bottom_grid_pin_5_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[1] -to fpga_top/cbx_1__12_/bottom_grid_pin_6_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[1] -to fpga_top/cbx_1__12_/bottom_grid_pin_6_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[4] -to fpga_top/cbx_1__12_/bottom_grid_pin_6_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[4] -to fpga_top/cbx_1__12_/bottom_grid_pin_6_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[7] -to fpga_top/cbx_1__12_/bottom_grid_pin_6_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[7] -to fpga_top/cbx_1__12_/bottom_grid_pin_6_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[13] -to fpga_top/cbx_1__12_/bottom_grid_pin_6_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[13] -to fpga_top/cbx_1__12_/bottom_grid_pin_6_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[19] -to fpga_top/cbx_1__12_/bottom_grid_pin_6_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[19] -to fpga_top/cbx_1__12_/bottom_grid_pin_6_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[25] -to fpga_top/cbx_1__12_/bottom_grid_pin_6_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[25] -to fpga_top/cbx_1__12_/bottom_grid_pin_6_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[2] -to fpga_top/cbx_1__12_/bottom_grid_pin_7_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[2] -to fpga_top/cbx_1__12_/bottom_grid_pin_7_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[5] -to fpga_top/cbx_1__12_/bottom_grid_pin_7_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[5] -to fpga_top/cbx_1__12_/bottom_grid_pin_7_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[8] -to fpga_top/cbx_1__12_/bottom_grid_pin_7_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[8] -to fpga_top/cbx_1__12_/bottom_grid_pin_7_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[14] -to fpga_top/cbx_1__12_/bottom_grid_pin_7_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[14] -to fpga_top/cbx_1__12_/bottom_grid_pin_7_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[23] -to fpga_top/cbx_1__12_/bottom_grid_pin_7_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[23] -to fpga_top/cbx_1__12_/bottom_grid_pin_7_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[0] -to fpga_top/cbx_1__12_/bottom_grid_pin_8_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[0] -to fpga_top/cbx_1__12_/bottom_grid_pin_8_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[3] -to fpga_top/cbx_1__12_/bottom_grid_pin_8_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[3] -to fpga_top/cbx_1__12_/bottom_grid_pin_8_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[9] -to fpga_top/cbx_1__12_/bottom_grid_pin_8_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[9] -to fpga_top/cbx_1__12_/bottom_grid_pin_8_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[15] -to fpga_top/cbx_1__12_/bottom_grid_pin_8_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[15] -to fpga_top/cbx_1__12_/bottom_grid_pin_8_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[21] -to fpga_top/cbx_1__12_/bottom_grid_pin_8_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[21] -to fpga_top/cbx_1__12_/bottom_grid_pin_8_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[27] -to fpga_top/cbx_1__12_/bottom_grid_pin_8_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[27] -to fpga_top/cbx_1__12_/bottom_grid_pin_8_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[1] -to fpga_top/cbx_1__12_/bottom_grid_pin_9_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[1] -to fpga_top/cbx_1__12_/bottom_grid_pin_9_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[4] -to fpga_top/cbx_1__12_/bottom_grid_pin_9_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[4] -to fpga_top/cbx_1__12_/bottom_grid_pin_9_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[10] -to fpga_top/cbx_1__12_/bottom_grid_pin_9_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[10] -to fpga_top/cbx_1__12_/bottom_grid_pin_9_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[16] -to fpga_top/cbx_1__12_/bottom_grid_pin_9_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[16] -to fpga_top/cbx_1__12_/bottom_grid_pin_9_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[25] -to fpga_top/cbx_1__12_/bottom_grid_pin_9_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[25] -to fpga_top/cbx_1__12_/bottom_grid_pin_9_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[2] -to fpga_top/cbx_1__12_/bottom_grid_pin_10_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[2] -to fpga_top/cbx_1__12_/bottom_grid_pin_10_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[5] -to fpga_top/cbx_1__12_/bottom_grid_pin_10_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[5] -to fpga_top/cbx_1__12_/bottom_grid_pin_10_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[11] -to fpga_top/cbx_1__12_/bottom_grid_pin_10_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[11] -to fpga_top/cbx_1__12_/bottom_grid_pin_10_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[17] -to fpga_top/cbx_1__12_/bottom_grid_pin_10_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[17] -to fpga_top/cbx_1__12_/bottom_grid_pin_10_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[23] -to fpga_top/cbx_1__12_/bottom_grid_pin_10_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[23] -to fpga_top/cbx_1__12_/bottom_grid_pin_10_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[29] -to fpga_top/cbx_1__12_/bottom_grid_pin_10_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[29] -to fpga_top/cbx_1__12_/bottom_grid_pin_10_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[0] -to fpga_top/cbx_1__12_/bottom_grid_pin_11_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[0] -to fpga_top/cbx_1__12_/bottom_grid_pin_11_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[3] -to fpga_top/cbx_1__12_/bottom_grid_pin_11_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[3] -to fpga_top/cbx_1__12_/bottom_grid_pin_11_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[12] -to fpga_top/cbx_1__12_/bottom_grid_pin_11_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[12] -to fpga_top/cbx_1__12_/bottom_grid_pin_11_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[18] -to fpga_top/cbx_1__12_/bottom_grid_pin_11_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[18] -to fpga_top/cbx_1__12_/bottom_grid_pin_11_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[27] -to fpga_top/cbx_1__12_/bottom_grid_pin_11_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[27] -to fpga_top/cbx_1__12_/bottom_grid_pin_11_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[1] -to fpga_top/cbx_1__12_/bottom_grid_pin_12_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[1] -to fpga_top/cbx_1__12_/bottom_grid_pin_12_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[4] -to fpga_top/cbx_1__12_/bottom_grid_pin_12_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[4] -to fpga_top/cbx_1__12_/bottom_grid_pin_12_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[7] -to fpga_top/cbx_1__12_/bottom_grid_pin_12_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[7] -to fpga_top/cbx_1__12_/bottom_grid_pin_12_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[13] -to fpga_top/cbx_1__12_/bottom_grid_pin_12_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[13] -to fpga_top/cbx_1__12_/bottom_grid_pin_12_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[19] -to fpga_top/cbx_1__12_/bottom_grid_pin_12_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[19] -to fpga_top/cbx_1__12_/bottom_grid_pin_12_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[25] -to fpga_top/cbx_1__12_/bottom_grid_pin_12_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[25] -to fpga_top/cbx_1__12_/bottom_grid_pin_12_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[2] -to fpga_top/cbx_1__12_/bottom_grid_pin_13_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[2] -to fpga_top/cbx_1__12_/bottom_grid_pin_13_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[5] -to fpga_top/cbx_1__12_/bottom_grid_pin_13_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[5] -to fpga_top/cbx_1__12_/bottom_grid_pin_13_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[14] -to fpga_top/cbx_1__12_/bottom_grid_pin_13_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[14] -to fpga_top/cbx_1__12_/bottom_grid_pin_13_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[20] -to fpga_top/cbx_1__12_/bottom_grid_pin_13_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[20] -to fpga_top/cbx_1__12_/bottom_grid_pin_13_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[29] -to fpga_top/cbx_1__12_/bottom_grid_pin_13_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[29] -to fpga_top/cbx_1__12_/bottom_grid_pin_13_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[0] -to fpga_top/cbx_1__12_/bottom_grid_pin_14_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[0] -to fpga_top/cbx_1__12_/bottom_grid_pin_14_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[3] -to fpga_top/cbx_1__12_/bottom_grid_pin_14_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[3] -to fpga_top/cbx_1__12_/bottom_grid_pin_14_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[9] -to fpga_top/cbx_1__12_/bottom_grid_pin_14_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[9] -to fpga_top/cbx_1__12_/bottom_grid_pin_14_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[15] -to fpga_top/cbx_1__12_/bottom_grid_pin_14_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[15] -to fpga_top/cbx_1__12_/bottom_grid_pin_14_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[21] -to fpga_top/cbx_1__12_/bottom_grid_pin_14_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[21] -to fpga_top/cbx_1__12_/bottom_grid_pin_14_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[27] -to fpga_top/cbx_1__12_/bottom_grid_pin_14_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[27] -to fpga_top/cbx_1__12_/bottom_grid_pin_14_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[1] -to fpga_top/cbx_1__12_/bottom_grid_pin_15_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[1] -to fpga_top/cbx_1__12_/bottom_grid_pin_15_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[4] -to fpga_top/cbx_1__12_/bottom_grid_pin_15_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[4] -to fpga_top/cbx_1__12_/bottom_grid_pin_15_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[7] -to fpga_top/cbx_1__12_/bottom_grid_pin_15_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[7] -to fpga_top/cbx_1__12_/bottom_grid_pin_15_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[16] -to fpga_top/cbx_1__12_/bottom_grid_pin_15_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[16] -to fpga_top/cbx_1__12_/bottom_grid_pin_15_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[22] -to fpga_top/cbx_1__12_/bottom_grid_pin_15_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[22] -to fpga_top/cbx_1__12_/bottom_grid_pin_15_[0] 7.247000222e-11 diff --git a/FPGA1212_RESET_HD_SKY_PNR/FPGA1212_RESET_HD_SKY_Verilog/SDC/cbx_1__1_.sdc b/FPGA1212_RESET_HD_SKY_PNR/FPGA1212_RESET_HD_SKY_Verilog/SDC/cbx_1__1_.sdc deleted file mode 100644 index 2e703e9..0000000 --- a/FPGA1212_RESET_HD_SKY_PNR/FPGA1212_RESET_HD_SKY_Verilog/SDC/cbx_1__1_.sdc +++ /dev/null @@ -1,250 +0,0 @@ -############################################# -# Synopsys Design Constraints (SDC) -# For FPGA fabric -# Description: Constrain timing of Connection Block cbx_1__1_ for PnR -# Author: Xifan TANG -# Organization: University of Utah -# Date: Tue Dec 1 18:12:04 2020 -############################################# - -############################################# -# Define time unit -############################################# -set_units -time s - -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[0] -to fpga_top/cbx_1__1_/chanx_left_out[0] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[0] -to fpga_top/cbx_1__1_/chanx_right_out[0] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[1] -to fpga_top/cbx_1__1_/chanx_left_out[1] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[1] -to fpga_top/cbx_1__1_/chanx_right_out[1] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[2] -to fpga_top/cbx_1__1_/chanx_left_out[2] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[2] -to fpga_top/cbx_1__1_/chanx_right_out[2] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[3] -to fpga_top/cbx_1__1_/chanx_left_out[3] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[3] -to fpga_top/cbx_1__1_/chanx_right_out[3] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[4] -to fpga_top/cbx_1__1_/chanx_left_out[4] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[4] -to fpga_top/cbx_1__1_/chanx_right_out[4] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[5] -to fpga_top/cbx_1__1_/chanx_left_out[5] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[5] -to fpga_top/cbx_1__1_/chanx_right_out[5] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[6] -to fpga_top/cbx_1__1_/chanx_left_out[6] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[6] -to fpga_top/cbx_1__1_/chanx_right_out[6] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[7] -to fpga_top/cbx_1__1_/chanx_left_out[7] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[7] -to fpga_top/cbx_1__1_/chanx_right_out[7] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[8] -to fpga_top/cbx_1__1_/chanx_left_out[8] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[8] -to fpga_top/cbx_1__1_/chanx_right_out[8] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[9] -to fpga_top/cbx_1__1_/chanx_left_out[9] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[9] -to fpga_top/cbx_1__1_/chanx_right_out[9] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[10] -to fpga_top/cbx_1__1_/chanx_left_out[10] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[10] -to fpga_top/cbx_1__1_/chanx_right_out[10] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[11] -to fpga_top/cbx_1__1_/chanx_left_out[11] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[11] -to fpga_top/cbx_1__1_/chanx_right_out[11] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[12] -to fpga_top/cbx_1__1_/chanx_left_out[12] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[12] -to fpga_top/cbx_1__1_/chanx_right_out[12] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[13] -to fpga_top/cbx_1__1_/chanx_left_out[13] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[13] -to fpga_top/cbx_1__1_/chanx_right_out[13] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[14] -to fpga_top/cbx_1__1_/chanx_left_out[14] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[14] -to fpga_top/cbx_1__1_/chanx_right_out[14] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[15] -to fpga_top/cbx_1__1_/chanx_left_out[15] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[15] -to fpga_top/cbx_1__1_/chanx_right_out[15] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[16] -to fpga_top/cbx_1__1_/chanx_left_out[16] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[16] -to fpga_top/cbx_1__1_/chanx_right_out[16] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[17] -to fpga_top/cbx_1__1_/chanx_left_out[17] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[17] -to fpga_top/cbx_1__1_/chanx_right_out[17] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[18] -to fpga_top/cbx_1__1_/chanx_left_out[18] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[18] -to fpga_top/cbx_1__1_/chanx_right_out[18] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[19] -to fpga_top/cbx_1__1_/chanx_left_out[19] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[19] -to fpga_top/cbx_1__1_/chanx_right_out[19] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[20] -to fpga_top/cbx_1__1_/chanx_left_out[20] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[20] -to fpga_top/cbx_1__1_/chanx_right_out[20] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[21] -to fpga_top/cbx_1__1_/chanx_left_out[21] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[21] -to fpga_top/cbx_1__1_/chanx_right_out[21] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[22] -to fpga_top/cbx_1__1_/chanx_left_out[22] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[22] -to fpga_top/cbx_1__1_/chanx_right_out[22] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[23] -to fpga_top/cbx_1__1_/chanx_left_out[23] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[23] -to fpga_top/cbx_1__1_/chanx_right_out[23] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[24] -to fpga_top/cbx_1__1_/chanx_left_out[24] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[24] -to fpga_top/cbx_1__1_/chanx_right_out[24] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[25] -to fpga_top/cbx_1__1_/chanx_left_out[25] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[25] -to fpga_top/cbx_1__1_/chanx_right_out[25] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[26] -to fpga_top/cbx_1__1_/chanx_left_out[26] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[26] -to fpga_top/cbx_1__1_/chanx_right_out[26] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[27] -to fpga_top/cbx_1__1_/chanx_left_out[27] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[27] -to fpga_top/cbx_1__1_/chanx_right_out[27] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[28] -to fpga_top/cbx_1__1_/chanx_left_out[28] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[28] -to fpga_top/cbx_1__1_/chanx_right_out[28] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[29] -to fpga_top/cbx_1__1_/chanx_left_out[29] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[29] -to fpga_top/cbx_1__1_/chanx_right_out[29] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[0] -to fpga_top/cbx_1__1_/bottom_grid_pin_0_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[0] -to fpga_top/cbx_1__1_/bottom_grid_pin_0_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[3] -to fpga_top/cbx_1__1_/bottom_grid_pin_0_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[3] -to fpga_top/cbx_1__1_/bottom_grid_pin_0_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[6] -to fpga_top/cbx_1__1_/bottom_grid_pin_0_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[6] -to fpga_top/cbx_1__1_/bottom_grid_pin_0_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[12] -to fpga_top/cbx_1__1_/bottom_grid_pin_0_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[12] -to fpga_top/cbx_1__1_/bottom_grid_pin_0_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[18] -to fpga_top/cbx_1__1_/bottom_grid_pin_0_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[18] -to fpga_top/cbx_1__1_/bottom_grid_pin_0_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[24] -to fpga_top/cbx_1__1_/bottom_grid_pin_0_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[24] -to fpga_top/cbx_1__1_/bottom_grid_pin_0_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[1] -to fpga_top/cbx_1__1_/bottom_grid_pin_1_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[1] -to fpga_top/cbx_1__1_/bottom_grid_pin_1_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[4] -to fpga_top/cbx_1__1_/bottom_grid_pin_1_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[4] -to fpga_top/cbx_1__1_/bottom_grid_pin_1_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[7] -to fpga_top/cbx_1__1_/bottom_grid_pin_1_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[7] -to fpga_top/cbx_1__1_/bottom_grid_pin_1_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[16] -to fpga_top/cbx_1__1_/bottom_grid_pin_1_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[16] -to fpga_top/cbx_1__1_/bottom_grid_pin_1_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[25] -to fpga_top/cbx_1__1_/bottom_grid_pin_1_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[25] -to fpga_top/cbx_1__1_/bottom_grid_pin_1_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[2] -to fpga_top/cbx_1__1_/bottom_grid_pin_2_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[2] -to fpga_top/cbx_1__1_/bottom_grid_pin_2_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[5] -to fpga_top/cbx_1__1_/bottom_grid_pin_2_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[5] -to fpga_top/cbx_1__1_/bottom_grid_pin_2_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[8] -to fpga_top/cbx_1__1_/bottom_grid_pin_2_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[8] -to fpga_top/cbx_1__1_/bottom_grid_pin_2_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[14] -to fpga_top/cbx_1__1_/bottom_grid_pin_2_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[14] -to fpga_top/cbx_1__1_/bottom_grid_pin_2_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[20] -to fpga_top/cbx_1__1_/bottom_grid_pin_2_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[20] -to fpga_top/cbx_1__1_/bottom_grid_pin_2_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[26] -to fpga_top/cbx_1__1_/bottom_grid_pin_2_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[26] -to fpga_top/cbx_1__1_/bottom_grid_pin_2_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[0] -to fpga_top/cbx_1__1_/bottom_grid_pin_3_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[0] -to fpga_top/cbx_1__1_/bottom_grid_pin_3_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[3] -to fpga_top/cbx_1__1_/bottom_grid_pin_3_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[3] -to fpga_top/cbx_1__1_/bottom_grid_pin_3_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[9] -to fpga_top/cbx_1__1_/bottom_grid_pin_3_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[9] -to fpga_top/cbx_1__1_/bottom_grid_pin_3_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[18] -to fpga_top/cbx_1__1_/bottom_grid_pin_3_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[18] -to fpga_top/cbx_1__1_/bottom_grid_pin_3_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[27] -to fpga_top/cbx_1__1_/bottom_grid_pin_3_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[27] -to fpga_top/cbx_1__1_/bottom_grid_pin_3_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[1] -to fpga_top/cbx_1__1_/bottom_grid_pin_4_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[1] -to fpga_top/cbx_1__1_/bottom_grid_pin_4_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[4] -to fpga_top/cbx_1__1_/bottom_grid_pin_4_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[4] -to fpga_top/cbx_1__1_/bottom_grid_pin_4_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[10] -to fpga_top/cbx_1__1_/bottom_grid_pin_4_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[10] -to fpga_top/cbx_1__1_/bottom_grid_pin_4_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[16] -to fpga_top/cbx_1__1_/bottom_grid_pin_4_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[16] -to fpga_top/cbx_1__1_/bottom_grid_pin_4_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[22] -to fpga_top/cbx_1__1_/bottom_grid_pin_4_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[22] -to fpga_top/cbx_1__1_/bottom_grid_pin_4_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[28] -to fpga_top/cbx_1__1_/bottom_grid_pin_4_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[28] -to fpga_top/cbx_1__1_/bottom_grid_pin_4_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[2] -to fpga_top/cbx_1__1_/bottom_grid_pin_5_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[2] -to fpga_top/cbx_1__1_/bottom_grid_pin_5_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[5] -to fpga_top/cbx_1__1_/bottom_grid_pin_5_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[5] -to fpga_top/cbx_1__1_/bottom_grid_pin_5_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[11] -to fpga_top/cbx_1__1_/bottom_grid_pin_5_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[11] -to fpga_top/cbx_1__1_/bottom_grid_pin_5_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[20] -to fpga_top/cbx_1__1_/bottom_grid_pin_5_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[20] -to fpga_top/cbx_1__1_/bottom_grid_pin_5_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[29] -to fpga_top/cbx_1__1_/bottom_grid_pin_5_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[29] -to fpga_top/cbx_1__1_/bottom_grid_pin_5_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[0] -to fpga_top/cbx_1__1_/bottom_grid_pin_6_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[0] -to fpga_top/cbx_1__1_/bottom_grid_pin_6_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[3] -to fpga_top/cbx_1__1_/bottom_grid_pin_6_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[3] -to fpga_top/cbx_1__1_/bottom_grid_pin_6_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[6] -to fpga_top/cbx_1__1_/bottom_grid_pin_6_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[6] -to fpga_top/cbx_1__1_/bottom_grid_pin_6_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[12] -to fpga_top/cbx_1__1_/bottom_grid_pin_6_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[12] -to fpga_top/cbx_1__1_/bottom_grid_pin_6_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[18] -to fpga_top/cbx_1__1_/bottom_grid_pin_6_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[18] -to fpga_top/cbx_1__1_/bottom_grid_pin_6_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[24] -to fpga_top/cbx_1__1_/bottom_grid_pin_6_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[24] -to fpga_top/cbx_1__1_/bottom_grid_pin_6_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[1] -to fpga_top/cbx_1__1_/bottom_grid_pin_7_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[1] -to fpga_top/cbx_1__1_/bottom_grid_pin_7_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[4] -to fpga_top/cbx_1__1_/bottom_grid_pin_7_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[4] -to fpga_top/cbx_1__1_/bottom_grid_pin_7_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[7] -to fpga_top/cbx_1__1_/bottom_grid_pin_7_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[7] -to fpga_top/cbx_1__1_/bottom_grid_pin_7_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[13] -to fpga_top/cbx_1__1_/bottom_grid_pin_7_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[13] -to fpga_top/cbx_1__1_/bottom_grid_pin_7_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[22] -to fpga_top/cbx_1__1_/bottom_grid_pin_7_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[22] -to fpga_top/cbx_1__1_/bottom_grid_pin_7_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[2] -to fpga_top/cbx_1__1_/bottom_grid_pin_8_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[2] -to fpga_top/cbx_1__1_/bottom_grid_pin_8_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[5] -to fpga_top/cbx_1__1_/bottom_grid_pin_8_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[5] -to fpga_top/cbx_1__1_/bottom_grid_pin_8_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[8] -to fpga_top/cbx_1__1_/bottom_grid_pin_8_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[8] -to fpga_top/cbx_1__1_/bottom_grid_pin_8_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[14] -to fpga_top/cbx_1__1_/bottom_grid_pin_8_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[14] -to fpga_top/cbx_1__1_/bottom_grid_pin_8_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[20] -to fpga_top/cbx_1__1_/bottom_grid_pin_8_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[20] -to fpga_top/cbx_1__1_/bottom_grid_pin_8_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[26] -to fpga_top/cbx_1__1_/bottom_grid_pin_8_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[26] -to fpga_top/cbx_1__1_/bottom_grid_pin_8_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[0] -to fpga_top/cbx_1__1_/bottom_grid_pin_9_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[0] -to fpga_top/cbx_1__1_/bottom_grid_pin_9_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[3] -to fpga_top/cbx_1__1_/bottom_grid_pin_9_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[3] -to fpga_top/cbx_1__1_/bottom_grid_pin_9_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[9] -to fpga_top/cbx_1__1_/bottom_grid_pin_9_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[9] -to fpga_top/cbx_1__1_/bottom_grid_pin_9_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[15] -to fpga_top/cbx_1__1_/bottom_grid_pin_9_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[15] -to fpga_top/cbx_1__1_/bottom_grid_pin_9_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[24] -to fpga_top/cbx_1__1_/bottom_grid_pin_9_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[24] -to fpga_top/cbx_1__1_/bottom_grid_pin_9_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[1] -to fpga_top/cbx_1__1_/bottom_grid_pin_10_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[1] -to fpga_top/cbx_1__1_/bottom_grid_pin_10_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[4] -to fpga_top/cbx_1__1_/bottom_grid_pin_10_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[4] -to fpga_top/cbx_1__1_/bottom_grid_pin_10_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[10] -to fpga_top/cbx_1__1_/bottom_grid_pin_10_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[10] -to fpga_top/cbx_1__1_/bottom_grid_pin_10_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[16] -to fpga_top/cbx_1__1_/bottom_grid_pin_10_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[16] -to fpga_top/cbx_1__1_/bottom_grid_pin_10_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[22] -to fpga_top/cbx_1__1_/bottom_grid_pin_10_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[22] -to fpga_top/cbx_1__1_/bottom_grid_pin_10_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[28] -to fpga_top/cbx_1__1_/bottom_grid_pin_10_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[28] -to fpga_top/cbx_1__1_/bottom_grid_pin_10_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[2] -to fpga_top/cbx_1__1_/bottom_grid_pin_11_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[2] -to fpga_top/cbx_1__1_/bottom_grid_pin_11_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[5] -to fpga_top/cbx_1__1_/bottom_grid_pin_11_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[5] -to fpga_top/cbx_1__1_/bottom_grid_pin_11_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[11] -to fpga_top/cbx_1__1_/bottom_grid_pin_11_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[11] -to fpga_top/cbx_1__1_/bottom_grid_pin_11_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[17] -to fpga_top/cbx_1__1_/bottom_grid_pin_11_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[17] -to fpga_top/cbx_1__1_/bottom_grid_pin_11_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[26] -to fpga_top/cbx_1__1_/bottom_grid_pin_11_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[26] -to fpga_top/cbx_1__1_/bottom_grid_pin_11_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[0] -to fpga_top/cbx_1__1_/bottom_grid_pin_12_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[0] -to fpga_top/cbx_1__1_/bottom_grid_pin_12_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[3] -to fpga_top/cbx_1__1_/bottom_grid_pin_12_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[3] -to fpga_top/cbx_1__1_/bottom_grid_pin_12_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[6] -to fpga_top/cbx_1__1_/bottom_grid_pin_12_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[6] -to fpga_top/cbx_1__1_/bottom_grid_pin_12_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[12] -to fpga_top/cbx_1__1_/bottom_grid_pin_12_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[12] -to fpga_top/cbx_1__1_/bottom_grid_pin_12_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[18] -to fpga_top/cbx_1__1_/bottom_grid_pin_12_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[18] -to fpga_top/cbx_1__1_/bottom_grid_pin_12_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[24] -to fpga_top/cbx_1__1_/bottom_grid_pin_12_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[24] -to fpga_top/cbx_1__1_/bottom_grid_pin_12_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[1] -to fpga_top/cbx_1__1_/bottom_grid_pin_13_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[1] -to fpga_top/cbx_1__1_/bottom_grid_pin_13_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[4] -to fpga_top/cbx_1__1_/bottom_grid_pin_13_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[4] -to fpga_top/cbx_1__1_/bottom_grid_pin_13_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[13] -to fpga_top/cbx_1__1_/bottom_grid_pin_13_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[13] -to fpga_top/cbx_1__1_/bottom_grid_pin_13_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[19] -to fpga_top/cbx_1__1_/bottom_grid_pin_13_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[19] -to fpga_top/cbx_1__1_/bottom_grid_pin_13_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[28] -to fpga_top/cbx_1__1_/bottom_grid_pin_13_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[28] -to fpga_top/cbx_1__1_/bottom_grid_pin_13_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[2] -to fpga_top/cbx_1__1_/bottom_grid_pin_14_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[2] -to fpga_top/cbx_1__1_/bottom_grid_pin_14_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[5] -to fpga_top/cbx_1__1_/bottom_grid_pin_14_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[5] -to fpga_top/cbx_1__1_/bottom_grid_pin_14_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[8] -to fpga_top/cbx_1__1_/bottom_grid_pin_14_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[8] -to fpga_top/cbx_1__1_/bottom_grid_pin_14_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[14] -to fpga_top/cbx_1__1_/bottom_grid_pin_14_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[14] -to fpga_top/cbx_1__1_/bottom_grid_pin_14_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[20] -to fpga_top/cbx_1__1_/bottom_grid_pin_14_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[20] -to fpga_top/cbx_1__1_/bottom_grid_pin_14_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[26] -to fpga_top/cbx_1__1_/bottom_grid_pin_14_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[26] -to fpga_top/cbx_1__1_/bottom_grid_pin_14_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[0] -to fpga_top/cbx_1__1_/bottom_grid_pin_15_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[0] -to fpga_top/cbx_1__1_/bottom_grid_pin_15_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[3] -to fpga_top/cbx_1__1_/bottom_grid_pin_15_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[3] -to fpga_top/cbx_1__1_/bottom_grid_pin_15_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[6] -to fpga_top/cbx_1__1_/bottom_grid_pin_15_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[6] -to fpga_top/cbx_1__1_/bottom_grid_pin_15_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[15] -to fpga_top/cbx_1__1_/bottom_grid_pin_15_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[15] -to fpga_top/cbx_1__1_/bottom_grid_pin_15_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[21] -to fpga_top/cbx_1__1_/bottom_grid_pin_15_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[21] -to fpga_top/cbx_1__1_/bottom_grid_pin_15_[0] 7.247000222e-11 diff --git a/FPGA1212_RESET_HD_SKY_PNR/FPGA1212_RESET_HD_SKY_Verilog/SDC/cby_0__1_.sdc b/FPGA1212_RESET_HD_SKY_PNR/FPGA1212_RESET_HD_SKY_Verilog/SDC/cby_0__1_.sdc deleted file mode 100644 index e532531..0000000 --- a/FPGA1212_RESET_HD_SKY_PNR/FPGA1212_RESET_HD_SKY_Verilog/SDC/cby_0__1_.sdc +++ /dev/null @@ -1,86 +0,0 @@ -############################################# -# Synopsys Design Constraints (SDC) -# For FPGA fabric -# Description: Constrain timing of Connection Block cby_0__1_ for PnR -# Author: Xifan TANG -# Organization: University of Utah -# Date: Tue Dec 1 18:12:04 2020 -############################################# - -############################################# -# Define time unit -############################################# -set_units -time s - -set_max_delay -from fpga_core_uut/cby_0__1_/chany_bottom_in[0] -to fpga_top/cby_0__1_/chany_bottom_out[0] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_0__1_/chany_top_in[0] -to fpga_top/cby_0__1_/chany_top_out[0] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_0__1_/chany_bottom_in[1] -to fpga_top/cby_0__1_/chany_bottom_out[1] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_0__1_/chany_top_in[1] -to fpga_top/cby_0__1_/chany_top_out[1] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_0__1_/chany_bottom_in[2] -to fpga_top/cby_0__1_/chany_bottom_out[2] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_0__1_/chany_top_in[2] -to fpga_top/cby_0__1_/chany_top_out[2] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_0__1_/chany_bottom_in[3] -to fpga_top/cby_0__1_/chany_bottom_out[3] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_0__1_/chany_top_in[3] -to fpga_top/cby_0__1_/chany_top_out[3] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_0__1_/chany_bottom_in[4] -to fpga_top/cby_0__1_/chany_bottom_out[4] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_0__1_/chany_top_in[4] -to fpga_top/cby_0__1_/chany_top_out[4] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_0__1_/chany_bottom_in[5] -to fpga_top/cby_0__1_/chany_bottom_out[5] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_0__1_/chany_top_in[5] -to fpga_top/cby_0__1_/chany_top_out[5] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_0__1_/chany_bottom_in[6] -to fpga_top/cby_0__1_/chany_bottom_out[6] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_0__1_/chany_top_in[6] -to fpga_top/cby_0__1_/chany_top_out[6] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_0__1_/chany_bottom_in[7] -to fpga_top/cby_0__1_/chany_bottom_out[7] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_0__1_/chany_top_in[7] -to fpga_top/cby_0__1_/chany_top_out[7] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_0__1_/chany_bottom_in[8] -to fpga_top/cby_0__1_/chany_bottom_out[8] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_0__1_/chany_top_in[8] -to fpga_top/cby_0__1_/chany_top_out[8] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_0__1_/chany_bottom_in[9] -to fpga_top/cby_0__1_/chany_bottom_out[9] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_0__1_/chany_top_in[9] -to fpga_top/cby_0__1_/chany_top_out[9] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_0__1_/chany_bottom_in[10] -to fpga_top/cby_0__1_/chany_bottom_out[10] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_0__1_/chany_top_in[10] -to fpga_top/cby_0__1_/chany_top_out[10] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_0__1_/chany_bottom_in[11] -to fpga_top/cby_0__1_/chany_bottom_out[11] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_0__1_/chany_top_in[11] -to fpga_top/cby_0__1_/chany_top_out[11] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_0__1_/chany_bottom_in[12] -to fpga_top/cby_0__1_/chany_bottom_out[12] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_0__1_/chany_top_in[12] -to fpga_top/cby_0__1_/chany_top_out[12] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_0__1_/chany_bottom_in[13] -to fpga_top/cby_0__1_/chany_bottom_out[13] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_0__1_/chany_top_in[13] -to fpga_top/cby_0__1_/chany_top_out[13] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_0__1_/chany_bottom_in[14] -to fpga_top/cby_0__1_/chany_bottom_out[14] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_0__1_/chany_top_in[14] -to fpga_top/cby_0__1_/chany_top_out[14] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_0__1_/chany_bottom_in[15] -to fpga_top/cby_0__1_/chany_bottom_out[15] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_0__1_/chany_top_in[15] -to fpga_top/cby_0__1_/chany_top_out[15] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_0__1_/chany_bottom_in[16] -to fpga_top/cby_0__1_/chany_bottom_out[16] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_0__1_/chany_top_in[16] -to fpga_top/cby_0__1_/chany_top_out[16] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_0__1_/chany_bottom_in[17] -to fpga_top/cby_0__1_/chany_bottom_out[17] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_0__1_/chany_top_in[17] -to fpga_top/cby_0__1_/chany_top_out[17] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_0__1_/chany_bottom_in[18] -to fpga_top/cby_0__1_/chany_bottom_out[18] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_0__1_/chany_top_in[18] -to fpga_top/cby_0__1_/chany_top_out[18] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_0__1_/chany_bottom_in[19] -to fpga_top/cby_0__1_/chany_bottom_out[19] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_0__1_/chany_top_in[19] -to fpga_top/cby_0__1_/chany_top_out[19] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_0__1_/chany_bottom_in[20] -to fpga_top/cby_0__1_/chany_bottom_out[20] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_0__1_/chany_top_in[20] -to fpga_top/cby_0__1_/chany_top_out[20] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_0__1_/chany_bottom_in[21] -to fpga_top/cby_0__1_/chany_bottom_out[21] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_0__1_/chany_top_in[21] -to fpga_top/cby_0__1_/chany_top_out[21] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_0__1_/chany_bottom_in[22] -to fpga_top/cby_0__1_/chany_bottom_out[22] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_0__1_/chany_top_in[22] -to fpga_top/cby_0__1_/chany_top_out[22] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_0__1_/chany_bottom_in[23] -to fpga_top/cby_0__1_/chany_bottom_out[23] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_0__1_/chany_top_in[23] -to fpga_top/cby_0__1_/chany_top_out[23] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_0__1_/chany_bottom_in[24] -to fpga_top/cby_0__1_/chany_bottom_out[24] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_0__1_/chany_top_in[24] -to fpga_top/cby_0__1_/chany_top_out[24] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_0__1_/chany_bottom_in[25] -to fpga_top/cby_0__1_/chany_bottom_out[25] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_0__1_/chany_top_in[25] -to fpga_top/cby_0__1_/chany_top_out[25] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_0__1_/chany_bottom_in[26] -to fpga_top/cby_0__1_/chany_bottom_out[26] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_0__1_/chany_top_in[26] -to fpga_top/cby_0__1_/chany_top_out[26] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_0__1_/chany_bottom_in[27] -to fpga_top/cby_0__1_/chany_bottom_out[27] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_0__1_/chany_top_in[27] -to fpga_top/cby_0__1_/chany_top_out[27] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_0__1_/chany_bottom_in[28] -to fpga_top/cby_0__1_/chany_bottom_out[28] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_0__1_/chany_top_in[28] -to fpga_top/cby_0__1_/chany_top_out[28] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_0__1_/chany_bottom_in[29] -to fpga_top/cby_0__1_/chany_bottom_out[29] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_0__1_/chany_top_in[29] -to fpga_top/cby_0__1_/chany_top_out[29] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_0__1_/chany_bottom_in[0] -to fpga_top/cby_0__1_/left_grid_pin_0_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_0__1_/chany_top_in[0] -to fpga_top/cby_0__1_/left_grid_pin_0_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_0__1_/chany_bottom_in[3] -to fpga_top/cby_0__1_/left_grid_pin_0_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_0__1_/chany_top_in[3] -to fpga_top/cby_0__1_/left_grid_pin_0_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_0__1_/chany_bottom_in[6] -to fpga_top/cby_0__1_/left_grid_pin_0_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_0__1_/chany_top_in[6] -to fpga_top/cby_0__1_/left_grid_pin_0_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_0__1_/chany_bottom_in[12] -to fpga_top/cby_0__1_/left_grid_pin_0_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_0__1_/chany_top_in[12] -to fpga_top/cby_0__1_/left_grid_pin_0_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_0__1_/chany_bottom_in[18] -to fpga_top/cby_0__1_/left_grid_pin_0_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_0__1_/chany_top_in[18] -to fpga_top/cby_0__1_/left_grid_pin_0_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_0__1_/chany_bottom_in[24] -to fpga_top/cby_0__1_/left_grid_pin_0_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_0__1_/chany_top_in[24] -to fpga_top/cby_0__1_/left_grid_pin_0_[0] 7.247000222e-11 diff --git a/FPGA1212_RESET_HD_SKY_PNR/FPGA1212_RESET_HD_SKY_Verilog/SDC/cby_12__1_.sdc b/FPGA1212_RESET_HD_SKY_PNR/FPGA1212_RESET_HD_SKY_Verilog/SDC/cby_12__1_.sdc deleted file mode 100644 index e36c2ee..0000000 --- a/FPGA1212_RESET_HD_SKY_PNR/FPGA1212_RESET_HD_SKY_Verilog/SDC/cby_12__1_.sdc +++ /dev/null @@ -1,262 +0,0 @@ -############################################# -# Synopsys Design Constraints (SDC) -# For FPGA fabric -# Description: Constrain timing of Connection Block cby_12__1_ for PnR -# Author: Xifan TANG -# Organization: University of Utah -# Date: Tue Dec 1 18:12:04 2020 -############################################# - -############################################# -# Define time unit -############################################# -set_units -time s - -set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[0] -to fpga_top/cby_12__1_/chany_bottom_out[0] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[0] -to fpga_top/cby_12__1_/chany_top_out[0] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[1] -to fpga_top/cby_12__1_/chany_bottom_out[1] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[1] -to fpga_top/cby_12__1_/chany_top_out[1] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[2] -to fpga_top/cby_12__1_/chany_bottom_out[2] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[2] -to fpga_top/cby_12__1_/chany_top_out[2] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[3] -to fpga_top/cby_12__1_/chany_bottom_out[3] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[3] -to fpga_top/cby_12__1_/chany_top_out[3] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[4] -to fpga_top/cby_12__1_/chany_bottom_out[4] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[4] -to fpga_top/cby_12__1_/chany_top_out[4] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[5] -to fpga_top/cby_12__1_/chany_bottom_out[5] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[5] -to fpga_top/cby_12__1_/chany_top_out[5] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[6] -to fpga_top/cby_12__1_/chany_bottom_out[6] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[6] -to fpga_top/cby_12__1_/chany_top_out[6] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[7] -to fpga_top/cby_12__1_/chany_bottom_out[7] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[7] -to fpga_top/cby_12__1_/chany_top_out[7] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[8] -to fpga_top/cby_12__1_/chany_bottom_out[8] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[8] -to fpga_top/cby_12__1_/chany_top_out[8] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[9] -to fpga_top/cby_12__1_/chany_bottom_out[9] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[9] -to fpga_top/cby_12__1_/chany_top_out[9] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[10] -to fpga_top/cby_12__1_/chany_bottom_out[10] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[10] -to fpga_top/cby_12__1_/chany_top_out[10] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[11] -to fpga_top/cby_12__1_/chany_bottom_out[11] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[11] -to fpga_top/cby_12__1_/chany_top_out[11] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[12] -to fpga_top/cby_12__1_/chany_bottom_out[12] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[12] -to fpga_top/cby_12__1_/chany_top_out[12] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[13] -to fpga_top/cby_12__1_/chany_bottom_out[13] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[13] -to fpga_top/cby_12__1_/chany_top_out[13] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[14] -to fpga_top/cby_12__1_/chany_bottom_out[14] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[14] -to fpga_top/cby_12__1_/chany_top_out[14] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[15] -to fpga_top/cby_12__1_/chany_bottom_out[15] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[15] -to fpga_top/cby_12__1_/chany_top_out[15] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[16] -to fpga_top/cby_12__1_/chany_bottom_out[16] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[16] -to fpga_top/cby_12__1_/chany_top_out[16] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[17] -to fpga_top/cby_12__1_/chany_bottom_out[17] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[17] -to fpga_top/cby_12__1_/chany_top_out[17] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[18] -to fpga_top/cby_12__1_/chany_bottom_out[18] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[18] -to fpga_top/cby_12__1_/chany_top_out[18] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[19] -to fpga_top/cby_12__1_/chany_bottom_out[19] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[19] -to fpga_top/cby_12__1_/chany_top_out[19] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[20] -to fpga_top/cby_12__1_/chany_bottom_out[20] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[20] -to fpga_top/cby_12__1_/chany_top_out[20] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[21] -to fpga_top/cby_12__1_/chany_bottom_out[21] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[21] -to fpga_top/cby_12__1_/chany_top_out[21] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[22] -to fpga_top/cby_12__1_/chany_bottom_out[22] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[22] -to fpga_top/cby_12__1_/chany_top_out[22] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[23] -to fpga_top/cby_12__1_/chany_bottom_out[23] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[23] -to fpga_top/cby_12__1_/chany_top_out[23] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[24] -to fpga_top/cby_12__1_/chany_bottom_out[24] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[24] -to fpga_top/cby_12__1_/chany_top_out[24] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[25] -to fpga_top/cby_12__1_/chany_bottom_out[25] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[25] -to fpga_top/cby_12__1_/chany_top_out[25] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[26] -to fpga_top/cby_12__1_/chany_bottom_out[26] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[26] -to fpga_top/cby_12__1_/chany_top_out[26] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[27] -to fpga_top/cby_12__1_/chany_bottom_out[27] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[27] -to fpga_top/cby_12__1_/chany_top_out[27] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[28] -to fpga_top/cby_12__1_/chany_bottom_out[28] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[28] -to fpga_top/cby_12__1_/chany_top_out[28] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[29] -to fpga_top/cby_12__1_/chany_bottom_out[29] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[29] -to fpga_top/cby_12__1_/chany_top_out[29] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[0] -to fpga_top/cby_12__1_/right_grid_pin_0_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[0] -to fpga_top/cby_12__1_/right_grid_pin_0_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[3] -to fpga_top/cby_12__1_/right_grid_pin_0_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[3] -to fpga_top/cby_12__1_/right_grid_pin_0_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[6] -to fpga_top/cby_12__1_/right_grid_pin_0_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[6] -to fpga_top/cby_12__1_/right_grid_pin_0_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[12] -to fpga_top/cby_12__1_/right_grid_pin_0_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[12] -to fpga_top/cby_12__1_/right_grid_pin_0_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[18] -to fpga_top/cby_12__1_/right_grid_pin_0_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[18] -to fpga_top/cby_12__1_/right_grid_pin_0_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[24] -to fpga_top/cby_12__1_/right_grid_pin_0_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[24] -to fpga_top/cby_12__1_/right_grid_pin_0_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[1] -to fpga_top/cby_12__1_/left_grid_pin_16_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[1] -to fpga_top/cby_12__1_/left_grid_pin_16_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[4] -to fpga_top/cby_12__1_/left_grid_pin_16_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[4] -to fpga_top/cby_12__1_/left_grid_pin_16_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[7] -to fpga_top/cby_12__1_/left_grid_pin_16_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[7] -to fpga_top/cby_12__1_/left_grid_pin_16_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[13] -to fpga_top/cby_12__1_/left_grid_pin_16_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[13] -to fpga_top/cby_12__1_/left_grid_pin_16_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[19] -to fpga_top/cby_12__1_/left_grid_pin_16_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[19] -to fpga_top/cby_12__1_/left_grid_pin_16_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[25] -to fpga_top/cby_12__1_/left_grid_pin_16_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[25] -to fpga_top/cby_12__1_/left_grid_pin_16_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[2] -to fpga_top/cby_12__1_/left_grid_pin_17_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[2] -to fpga_top/cby_12__1_/left_grid_pin_17_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[5] -to fpga_top/cby_12__1_/left_grid_pin_17_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[5] -to fpga_top/cby_12__1_/left_grid_pin_17_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[8] -to fpga_top/cby_12__1_/left_grid_pin_17_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[8] -to fpga_top/cby_12__1_/left_grid_pin_17_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[17] -to fpga_top/cby_12__1_/left_grid_pin_17_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[17] -to fpga_top/cby_12__1_/left_grid_pin_17_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[26] -to fpga_top/cby_12__1_/left_grid_pin_17_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[26] -to fpga_top/cby_12__1_/left_grid_pin_17_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[0] -to fpga_top/cby_12__1_/left_grid_pin_18_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[0] -to fpga_top/cby_12__1_/left_grid_pin_18_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[3] -to fpga_top/cby_12__1_/left_grid_pin_18_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[3] -to fpga_top/cby_12__1_/left_grid_pin_18_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[9] -to fpga_top/cby_12__1_/left_grid_pin_18_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[9] -to fpga_top/cby_12__1_/left_grid_pin_18_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[15] -to fpga_top/cby_12__1_/left_grid_pin_18_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[15] -to fpga_top/cby_12__1_/left_grid_pin_18_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[21] -to fpga_top/cby_12__1_/left_grid_pin_18_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[21] -to fpga_top/cby_12__1_/left_grid_pin_18_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[27] -to fpga_top/cby_12__1_/left_grid_pin_18_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[27] -to fpga_top/cby_12__1_/left_grid_pin_18_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[1] -to fpga_top/cby_12__1_/left_grid_pin_19_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[1] -to fpga_top/cby_12__1_/left_grid_pin_19_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[4] -to fpga_top/cby_12__1_/left_grid_pin_19_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[4] -to fpga_top/cby_12__1_/left_grid_pin_19_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[10] -to fpga_top/cby_12__1_/left_grid_pin_19_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[10] -to fpga_top/cby_12__1_/left_grid_pin_19_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[19] -to fpga_top/cby_12__1_/left_grid_pin_19_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[19] -to fpga_top/cby_12__1_/left_grid_pin_19_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[28] -to fpga_top/cby_12__1_/left_grid_pin_19_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[28] -to fpga_top/cby_12__1_/left_grid_pin_19_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[2] -to fpga_top/cby_12__1_/left_grid_pin_20_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[2] -to fpga_top/cby_12__1_/left_grid_pin_20_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[5] -to fpga_top/cby_12__1_/left_grid_pin_20_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[5] -to fpga_top/cby_12__1_/left_grid_pin_20_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[11] -to fpga_top/cby_12__1_/left_grid_pin_20_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[11] -to fpga_top/cby_12__1_/left_grid_pin_20_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[17] -to fpga_top/cby_12__1_/left_grid_pin_20_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[17] -to fpga_top/cby_12__1_/left_grid_pin_20_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[23] -to fpga_top/cby_12__1_/left_grid_pin_20_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[23] -to fpga_top/cby_12__1_/left_grid_pin_20_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[29] -to fpga_top/cby_12__1_/left_grid_pin_20_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[29] -to fpga_top/cby_12__1_/left_grid_pin_20_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[0] -to fpga_top/cby_12__1_/left_grid_pin_21_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[0] -to fpga_top/cby_12__1_/left_grid_pin_21_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[3] -to fpga_top/cby_12__1_/left_grid_pin_21_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[3] -to fpga_top/cby_12__1_/left_grid_pin_21_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[6] -to fpga_top/cby_12__1_/left_grid_pin_21_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[6] -to fpga_top/cby_12__1_/left_grid_pin_21_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[12] -to fpga_top/cby_12__1_/left_grid_pin_21_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[12] -to fpga_top/cby_12__1_/left_grid_pin_21_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[21] -to fpga_top/cby_12__1_/left_grid_pin_21_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[21] -to fpga_top/cby_12__1_/left_grid_pin_21_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[1] -to fpga_top/cby_12__1_/left_grid_pin_22_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[1] -to fpga_top/cby_12__1_/left_grid_pin_22_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[4] -to fpga_top/cby_12__1_/left_grid_pin_22_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[4] -to fpga_top/cby_12__1_/left_grid_pin_22_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[7] -to fpga_top/cby_12__1_/left_grid_pin_22_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[7] -to fpga_top/cby_12__1_/left_grid_pin_22_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[13] -to fpga_top/cby_12__1_/left_grid_pin_22_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[13] -to fpga_top/cby_12__1_/left_grid_pin_22_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[19] -to fpga_top/cby_12__1_/left_grid_pin_22_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[19] -to fpga_top/cby_12__1_/left_grid_pin_22_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[25] -to fpga_top/cby_12__1_/left_grid_pin_22_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[25] -to fpga_top/cby_12__1_/left_grid_pin_22_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[2] -to fpga_top/cby_12__1_/left_grid_pin_23_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[2] -to fpga_top/cby_12__1_/left_grid_pin_23_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[5] -to fpga_top/cby_12__1_/left_grid_pin_23_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[5] -to fpga_top/cby_12__1_/left_grid_pin_23_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[8] -to fpga_top/cby_12__1_/left_grid_pin_23_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[8] -to fpga_top/cby_12__1_/left_grid_pin_23_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[14] -to fpga_top/cby_12__1_/left_grid_pin_23_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[14] -to fpga_top/cby_12__1_/left_grid_pin_23_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[23] -to fpga_top/cby_12__1_/left_grid_pin_23_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[23] -to fpga_top/cby_12__1_/left_grid_pin_23_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[0] -to fpga_top/cby_12__1_/left_grid_pin_24_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[0] -to fpga_top/cby_12__1_/left_grid_pin_24_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[3] -to fpga_top/cby_12__1_/left_grid_pin_24_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[3] -to fpga_top/cby_12__1_/left_grid_pin_24_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[9] -to fpga_top/cby_12__1_/left_grid_pin_24_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[9] -to fpga_top/cby_12__1_/left_grid_pin_24_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[15] -to fpga_top/cby_12__1_/left_grid_pin_24_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[15] -to fpga_top/cby_12__1_/left_grid_pin_24_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[21] -to fpga_top/cby_12__1_/left_grid_pin_24_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[21] -to fpga_top/cby_12__1_/left_grid_pin_24_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[27] -to fpga_top/cby_12__1_/left_grid_pin_24_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[27] -to fpga_top/cby_12__1_/left_grid_pin_24_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[1] -to fpga_top/cby_12__1_/left_grid_pin_25_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[1] -to fpga_top/cby_12__1_/left_grid_pin_25_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[4] -to fpga_top/cby_12__1_/left_grid_pin_25_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[4] -to fpga_top/cby_12__1_/left_grid_pin_25_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[10] -to fpga_top/cby_12__1_/left_grid_pin_25_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[10] -to fpga_top/cby_12__1_/left_grid_pin_25_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[16] -to fpga_top/cby_12__1_/left_grid_pin_25_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[16] -to fpga_top/cby_12__1_/left_grid_pin_25_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[25] -to fpga_top/cby_12__1_/left_grid_pin_25_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[25] -to fpga_top/cby_12__1_/left_grid_pin_25_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[2] -to fpga_top/cby_12__1_/left_grid_pin_26_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[2] -to fpga_top/cby_12__1_/left_grid_pin_26_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[5] -to fpga_top/cby_12__1_/left_grid_pin_26_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[5] -to fpga_top/cby_12__1_/left_grid_pin_26_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[11] -to fpga_top/cby_12__1_/left_grid_pin_26_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[11] -to fpga_top/cby_12__1_/left_grid_pin_26_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[17] -to fpga_top/cby_12__1_/left_grid_pin_26_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[17] -to fpga_top/cby_12__1_/left_grid_pin_26_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[23] -to fpga_top/cby_12__1_/left_grid_pin_26_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[23] -to fpga_top/cby_12__1_/left_grid_pin_26_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[29] -to fpga_top/cby_12__1_/left_grid_pin_26_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[29] -to fpga_top/cby_12__1_/left_grid_pin_26_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[0] -to fpga_top/cby_12__1_/left_grid_pin_27_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[0] -to fpga_top/cby_12__1_/left_grid_pin_27_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[3] -to fpga_top/cby_12__1_/left_grid_pin_27_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[3] -to fpga_top/cby_12__1_/left_grid_pin_27_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[12] -to fpga_top/cby_12__1_/left_grid_pin_27_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[12] -to fpga_top/cby_12__1_/left_grid_pin_27_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[18] -to fpga_top/cby_12__1_/left_grid_pin_27_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[18] -to fpga_top/cby_12__1_/left_grid_pin_27_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[27] -to fpga_top/cby_12__1_/left_grid_pin_27_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[27] -to fpga_top/cby_12__1_/left_grid_pin_27_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[1] -to fpga_top/cby_12__1_/left_grid_pin_28_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[1] -to fpga_top/cby_12__1_/left_grid_pin_28_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[4] -to fpga_top/cby_12__1_/left_grid_pin_28_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[4] -to fpga_top/cby_12__1_/left_grid_pin_28_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[7] -to fpga_top/cby_12__1_/left_grid_pin_28_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[7] -to fpga_top/cby_12__1_/left_grid_pin_28_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[13] -to fpga_top/cby_12__1_/left_grid_pin_28_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[13] -to fpga_top/cby_12__1_/left_grid_pin_28_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[19] -to fpga_top/cby_12__1_/left_grid_pin_28_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[19] -to fpga_top/cby_12__1_/left_grid_pin_28_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[25] -to fpga_top/cby_12__1_/left_grid_pin_28_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[25] -to fpga_top/cby_12__1_/left_grid_pin_28_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[2] -to fpga_top/cby_12__1_/left_grid_pin_29_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[2] -to fpga_top/cby_12__1_/left_grid_pin_29_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[5] -to fpga_top/cby_12__1_/left_grid_pin_29_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[5] -to fpga_top/cby_12__1_/left_grid_pin_29_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[14] -to fpga_top/cby_12__1_/left_grid_pin_29_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[14] -to fpga_top/cby_12__1_/left_grid_pin_29_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[20] -to fpga_top/cby_12__1_/left_grid_pin_29_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[20] -to fpga_top/cby_12__1_/left_grid_pin_29_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[29] -to fpga_top/cby_12__1_/left_grid_pin_29_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[29] -to fpga_top/cby_12__1_/left_grid_pin_29_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[0] -to fpga_top/cby_12__1_/left_grid_pin_30_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[0] -to fpga_top/cby_12__1_/left_grid_pin_30_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[3] -to fpga_top/cby_12__1_/left_grid_pin_30_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[3] -to fpga_top/cby_12__1_/left_grid_pin_30_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[9] -to fpga_top/cby_12__1_/left_grid_pin_30_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[9] -to fpga_top/cby_12__1_/left_grid_pin_30_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[15] -to fpga_top/cby_12__1_/left_grid_pin_30_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[15] -to fpga_top/cby_12__1_/left_grid_pin_30_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[21] -to fpga_top/cby_12__1_/left_grid_pin_30_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[21] -to fpga_top/cby_12__1_/left_grid_pin_30_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[27] -to fpga_top/cby_12__1_/left_grid_pin_30_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[27] -to fpga_top/cby_12__1_/left_grid_pin_30_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[1] -to fpga_top/cby_12__1_/left_grid_pin_31_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[1] -to fpga_top/cby_12__1_/left_grid_pin_31_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[4] -to fpga_top/cby_12__1_/left_grid_pin_31_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[4] -to fpga_top/cby_12__1_/left_grid_pin_31_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[7] -to fpga_top/cby_12__1_/left_grid_pin_31_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[7] -to fpga_top/cby_12__1_/left_grid_pin_31_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[16] -to fpga_top/cby_12__1_/left_grid_pin_31_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[16] -to fpga_top/cby_12__1_/left_grid_pin_31_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[22] -to fpga_top/cby_12__1_/left_grid_pin_31_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[22] -to fpga_top/cby_12__1_/left_grid_pin_31_[0] 7.247000222e-11 diff --git a/FPGA1212_RESET_HD_SKY_PNR/FPGA1212_RESET_HD_SKY_Verilog/SDC/cby_1__1_.sdc b/FPGA1212_RESET_HD_SKY_PNR/FPGA1212_RESET_HD_SKY_Verilog/SDC/cby_1__1_.sdc deleted file mode 100644 index edafe30..0000000 --- a/FPGA1212_RESET_HD_SKY_PNR/FPGA1212_RESET_HD_SKY_Verilog/SDC/cby_1__1_.sdc +++ /dev/null @@ -1,250 +0,0 @@ -############################################# -# Synopsys Design Constraints (SDC) -# For FPGA fabric -# Description: Constrain timing of Connection Block cby_1__1_ for PnR -# Author: Xifan TANG -# Organization: University of Utah -# Date: Tue Dec 1 18:12:04 2020 -############################################# - -############################################# -# Define time unit -############################################# -set_units -time s - -set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[0] -to fpga_top/cby_1__1_/chany_bottom_out[0] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[0] -to fpga_top/cby_1__1_/chany_top_out[0] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[1] -to fpga_top/cby_1__1_/chany_bottom_out[1] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[1] -to fpga_top/cby_1__1_/chany_top_out[1] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[2] -to fpga_top/cby_1__1_/chany_bottom_out[2] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[2] -to fpga_top/cby_1__1_/chany_top_out[2] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[3] -to fpga_top/cby_1__1_/chany_bottom_out[3] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[3] -to fpga_top/cby_1__1_/chany_top_out[3] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[4] -to fpga_top/cby_1__1_/chany_bottom_out[4] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[4] -to fpga_top/cby_1__1_/chany_top_out[4] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[5] -to fpga_top/cby_1__1_/chany_bottom_out[5] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[5] -to fpga_top/cby_1__1_/chany_top_out[5] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[6] -to fpga_top/cby_1__1_/chany_bottom_out[6] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[6] -to fpga_top/cby_1__1_/chany_top_out[6] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[7] -to fpga_top/cby_1__1_/chany_bottom_out[7] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[7] -to fpga_top/cby_1__1_/chany_top_out[7] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[8] -to fpga_top/cby_1__1_/chany_bottom_out[8] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[8] -to fpga_top/cby_1__1_/chany_top_out[8] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[9] -to fpga_top/cby_1__1_/chany_bottom_out[9] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[9] -to fpga_top/cby_1__1_/chany_top_out[9] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[10] -to fpga_top/cby_1__1_/chany_bottom_out[10] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[10] -to fpga_top/cby_1__1_/chany_top_out[10] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[11] -to fpga_top/cby_1__1_/chany_bottom_out[11] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[11] -to fpga_top/cby_1__1_/chany_top_out[11] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[12] -to fpga_top/cby_1__1_/chany_bottom_out[12] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[12] -to fpga_top/cby_1__1_/chany_top_out[12] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[13] -to fpga_top/cby_1__1_/chany_bottom_out[13] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[13] -to fpga_top/cby_1__1_/chany_top_out[13] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[14] -to fpga_top/cby_1__1_/chany_bottom_out[14] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[14] -to fpga_top/cby_1__1_/chany_top_out[14] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[15] -to fpga_top/cby_1__1_/chany_bottom_out[15] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[15] -to fpga_top/cby_1__1_/chany_top_out[15] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[16] -to fpga_top/cby_1__1_/chany_bottom_out[16] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[16] -to fpga_top/cby_1__1_/chany_top_out[16] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[17] -to fpga_top/cby_1__1_/chany_bottom_out[17] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[17] -to fpga_top/cby_1__1_/chany_top_out[17] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[18] -to fpga_top/cby_1__1_/chany_bottom_out[18] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[18] -to fpga_top/cby_1__1_/chany_top_out[18] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[19] -to fpga_top/cby_1__1_/chany_bottom_out[19] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[19] -to fpga_top/cby_1__1_/chany_top_out[19] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[20] -to fpga_top/cby_1__1_/chany_bottom_out[20] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[20] -to fpga_top/cby_1__1_/chany_top_out[20] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[21] -to fpga_top/cby_1__1_/chany_bottom_out[21] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[21] -to fpga_top/cby_1__1_/chany_top_out[21] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[22] -to fpga_top/cby_1__1_/chany_bottom_out[22] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[22] -to fpga_top/cby_1__1_/chany_top_out[22] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[23] -to fpga_top/cby_1__1_/chany_bottom_out[23] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[23] -to fpga_top/cby_1__1_/chany_top_out[23] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[24] -to fpga_top/cby_1__1_/chany_bottom_out[24] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[24] -to fpga_top/cby_1__1_/chany_top_out[24] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[25] -to fpga_top/cby_1__1_/chany_bottom_out[25] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[25] -to fpga_top/cby_1__1_/chany_top_out[25] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[26] -to fpga_top/cby_1__1_/chany_bottom_out[26] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[26] -to fpga_top/cby_1__1_/chany_top_out[26] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[27] -to fpga_top/cby_1__1_/chany_bottom_out[27] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[27] -to fpga_top/cby_1__1_/chany_top_out[27] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[28] -to fpga_top/cby_1__1_/chany_bottom_out[28] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[28] -to fpga_top/cby_1__1_/chany_top_out[28] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[29] -to fpga_top/cby_1__1_/chany_bottom_out[29] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[29] -to fpga_top/cby_1__1_/chany_top_out[29] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[0] -to fpga_top/cby_1__1_/left_grid_pin_16_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[0] -to fpga_top/cby_1__1_/left_grid_pin_16_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[3] -to fpga_top/cby_1__1_/left_grid_pin_16_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[3] -to fpga_top/cby_1__1_/left_grid_pin_16_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[6] -to fpga_top/cby_1__1_/left_grid_pin_16_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[6] -to fpga_top/cby_1__1_/left_grid_pin_16_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[12] -to fpga_top/cby_1__1_/left_grid_pin_16_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[12] -to fpga_top/cby_1__1_/left_grid_pin_16_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[18] -to fpga_top/cby_1__1_/left_grid_pin_16_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[18] -to fpga_top/cby_1__1_/left_grid_pin_16_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[24] -to fpga_top/cby_1__1_/left_grid_pin_16_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[24] -to fpga_top/cby_1__1_/left_grid_pin_16_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[1] -to fpga_top/cby_1__1_/left_grid_pin_17_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[1] -to fpga_top/cby_1__1_/left_grid_pin_17_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[4] -to fpga_top/cby_1__1_/left_grid_pin_17_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[4] -to fpga_top/cby_1__1_/left_grid_pin_17_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[7] -to fpga_top/cby_1__1_/left_grid_pin_17_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[7] -to fpga_top/cby_1__1_/left_grid_pin_17_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[16] -to fpga_top/cby_1__1_/left_grid_pin_17_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[16] -to fpga_top/cby_1__1_/left_grid_pin_17_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[25] -to fpga_top/cby_1__1_/left_grid_pin_17_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[25] -to fpga_top/cby_1__1_/left_grid_pin_17_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[2] -to fpga_top/cby_1__1_/left_grid_pin_18_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[2] -to fpga_top/cby_1__1_/left_grid_pin_18_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[5] -to fpga_top/cby_1__1_/left_grid_pin_18_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[5] -to fpga_top/cby_1__1_/left_grid_pin_18_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[8] -to fpga_top/cby_1__1_/left_grid_pin_18_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[8] -to fpga_top/cby_1__1_/left_grid_pin_18_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[14] -to fpga_top/cby_1__1_/left_grid_pin_18_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[14] -to fpga_top/cby_1__1_/left_grid_pin_18_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[20] -to fpga_top/cby_1__1_/left_grid_pin_18_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[20] -to fpga_top/cby_1__1_/left_grid_pin_18_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[26] -to fpga_top/cby_1__1_/left_grid_pin_18_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[26] -to fpga_top/cby_1__1_/left_grid_pin_18_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[0] -to fpga_top/cby_1__1_/left_grid_pin_19_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[0] -to fpga_top/cby_1__1_/left_grid_pin_19_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[3] -to fpga_top/cby_1__1_/left_grid_pin_19_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[3] -to fpga_top/cby_1__1_/left_grid_pin_19_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[9] -to fpga_top/cby_1__1_/left_grid_pin_19_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[9] -to fpga_top/cby_1__1_/left_grid_pin_19_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[18] -to fpga_top/cby_1__1_/left_grid_pin_19_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[18] -to fpga_top/cby_1__1_/left_grid_pin_19_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[27] -to fpga_top/cby_1__1_/left_grid_pin_19_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[27] -to fpga_top/cby_1__1_/left_grid_pin_19_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[1] -to fpga_top/cby_1__1_/left_grid_pin_20_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[1] -to fpga_top/cby_1__1_/left_grid_pin_20_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[4] -to fpga_top/cby_1__1_/left_grid_pin_20_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[4] -to fpga_top/cby_1__1_/left_grid_pin_20_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[10] -to fpga_top/cby_1__1_/left_grid_pin_20_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[10] -to fpga_top/cby_1__1_/left_grid_pin_20_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[16] -to fpga_top/cby_1__1_/left_grid_pin_20_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[16] -to fpga_top/cby_1__1_/left_grid_pin_20_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[22] -to fpga_top/cby_1__1_/left_grid_pin_20_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[22] -to fpga_top/cby_1__1_/left_grid_pin_20_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[28] -to fpga_top/cby_1__1_/left_grid_pin_20_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[28] -to fpga_top/cby_1__1_/left_grid_pin_20_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[2] -to fpga_top/cby_1__1_/left_grid_pin_21_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[2] -to fpga_top/cby_1__1_/left_grid_pin_21_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[5] -to fpga_top/cby_1__1_/left_grid_pin_21_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[5] -to fpga_top/cby_1__1_/left_grid_pin_21_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[11] -to fpga_top/cby_1__1_/left_grid_pin_21_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[11] -to fpga_top/cby_1__1_/left_grid_pin_21_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[20] -to fpga_top/cby_1__1_/left_grid_pin_21_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[20] -to fpga_top/cby_1__1_/left_grid_pin_21_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[29] -to fpga_top/cby_1__1_/left_grid_pin_21_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[29] -to fpga_top/cby_1__1_/left_grid_pin_21_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[0] -to fpga_top/cby_1__1_/left_grid_pin_22_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[0] -to fpga_top/cby_1__1_/left_grid_pin_22_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[3] -to fpga_top/cby_1__1_/left_grid_pin_22_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[3] -to fpga_top/cby_1__1_/left_grid_pin_22_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[6] -to fpga_top/cby_1__1_/left_grid_pin_22_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[6] -to fpga_top/cby_1__1_/left_grid_pin_22_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[12] -to fpga_top/cby_1__1_/left_grid_pin_22_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[12] -to fpga_top/cby_1__1_/left_grid_pin_22_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[18] -to fpga_top/cby_1__1_/left_grid_pin_22_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[18] -to fpga_top/cby_1__1_/left_grid_pin_22_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[24] -to fpga_top/cby_1__1_/left_grid_pin_22_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[24] -to fpga_top/cby_1__1_/left_grid_pin_22_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[1] -to fpga_top/cby_1__1_/left_grid_pin_23_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[1] -to fpga_top/cby_1__1_/left_grid_pin_23_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[4] -to fpga_top/cby_1__1_/left_grid_pin_23_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[4] -to fpga_top/cby_1__1_/left_grid_pin_23_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[7] -to fpga_top/cby_1__1_/left_grid_pin_23_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[7] -to fpga_top/cby_1__1_/left_grid_pin_23_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[13] -to fpga_top/cby_1__1_/left_grid_pin_23_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[13] -to fpga_top/cby_1__1_/left_grid_pin_23_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[22] -to fpga_top/cby_1__1_/left_grid_pin_23_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[22] -to fpga_top/cby_1__1_/left_grid_pin_23_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[2] -to fpga_top/cby_1__1_/left_grid_pin_24_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[2] -to fpga_top/cby_1__1_/left_grid_pin_24_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[5] -to fpga_top/cby_1__1_/left_grid_pin_24_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[5] -to fpga_top/cby_1__1_/left_grid_pin_24_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[8] -to fpga_top/cby_1__1_/left_grid_pin_24_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[8] -to fpga_top/cby_1__1_/left_grid_pin_24_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[14] -to fpga_top/cby_1__1_/left_grid_pin_24_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[14] -to fpga_top/cby_1__1_/left_grid_pin_24_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[20] -to fpga_top/cby_1__1_/left_grid_pin_24_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[20] -to fpga_top/cby_1__1_/left_grid_pin_24_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[26] -to fpga_top/cby_1__1_/left_grid_pin_24_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[26] -to fpga_top/cby_1__1_/left_grid_pin_24_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[0] -to fpga_top/cby_1__1_/left_grid_pin_25_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[0] -to fpga_top/cby_1__1_/left_grid_pin_25_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[3] -to fpga_top/cby_1__1_/left_grid_pin_25_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[3] -to fpga_top/cby_1__1_/left_grid_pin_25_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[9] -to fpga_top/cby_1__1_/left_grid_pin_25_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[9] -to fpga_top/cby_1__1_/left_grid_pin_25_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[15] -to fpga_top/cby_1__1_/left_grid_pin_25_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[15] -to fpga_top/cby_1__1_/left_grid_pin_25_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[24] -to fpga_top/cby_1__1_/left_grid_pin_25_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[24] -to fpga_top/cby_1__1_/left_grid_pin_25_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[1] -to fpga_top/cby_1__1_/left_grid_pin_26_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[1] -to fpga_top/cby_1__1_/left_grid_pin_26_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[4] -to fpga_top/cby_1__1_/left_grid_pin_26_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[4] -to fpga_top/cby_1__1_/left_grid_pin_26_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[10] -to fpga_top/cby_1__1_/left_grid_pin_26_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[10] -to fpga_top/cby_1__1_/left_grid_pin_26_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[16] -to fpga_top/cby_1__1_/left_grid_pin_26_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[16] -to fpga_top/cby_1__1_/left_grid_pin_26_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[22] -to fpga_top/cby_1__1_/left_grid_pin_26_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[22] -to fpga_top/cby_1__1_/left_grid_pin_26_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[28] -to fpga_top/cby_1__1_/left_grid_pin_26_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[28] -to fpga_top/cby_1__1_/left_grid_pin_26_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[2] -to fpga_top/cby_1__1_/left_grid_pin_27_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[2] -to fpga_top/cby_1__1_/left_grid_pin_27_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[5] -to fpga_top/cby_1__1_/left_grid_pin_27_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[5] -to fpga_top/cby_1__1_/left_grid_pin_27_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[11] -to fpga_top/cby_1__1_/left_grid_pin_27_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[11] -to fpga_top/cby_1__1_/left_grid_pin_27_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[17] -to fpga_top/cby_1__1_/left_grid_pin_27_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[17] -to fpga_top/cby_1__1_/left_grid_pin_27_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[26] -to fpga_top/cby_1__1_/left_grid_pin_27_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[26] -to fpga_top/cby_1__1_/left_grid_pin_27_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[0] -to fpga_top/cby_1__1_/left_grid_pin_28_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[0] -to fpga_top/cby_1__1_/left_grid_pin_28_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[3] -to fpga_top/cby_1__1_/left_grid_pin_28_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[3] -to fpga_top/cby_1__1_/left_grid_pin_28_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[6] -to fpga_top/cby_1__1_/left_grid_pin_28_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[6] -to fpga_top/cby_1__1_/left_grid_pin_28_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[12] -to fpga_top/cby_1__1_/left_grid_pin_28_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[12] -to fpga_top/cby_1__1_/left_grid_pin_28_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[18] -to fpga_top/cby_1__1_/left_grid_pin_28_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[18] -to fpga_top/cby_1__1_/left_grid_pin_28_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[24] -to fpga_top/cby_1__1_/left_grid_pin_28_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[24] -to fpga_top/cby_1__1_/left_grid_pin_28_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[1] -to fpga_top/cby_1__1_/left_grid_pin_29_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[1] -to fpga_top/cby_1__1_/left_grid_pin_29_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[4] -to fpga_top/cby_1__1_/left_grid_pin_29_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[4] -to fpga_top/cby_1__1_/left_grid_pin_29_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[13] -to fpga_top/cby_1__1_/left_grid_pin_29_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[13] -to fpga_top/cby_1__1_/left_grid_pin_29_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[19] -to fpga_top/cby_1__1_/left_grid_pin_29_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[19] -to fpga_top/cby_1__1_/left_grid_pin_29_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[28] -to fpga_top/cby_1__1_/left_grid_pin_29_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[28] -to fpga_top/cby_1__1_/left_grid_pin_29_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[2] -to fpga_top/cby_1__1_/left_grid_pin_30_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[2] -to fpga_top/cby_1__1_/left_grid_pin_30_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[5] -to fpga_top/cby_1__1_/left_grid_pin_30_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[5] -to fpga_top/cby_1__1_/left_grid_pin_30_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[8] -to fpga_top/cby_1__1_/left_grid_pin_30_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[8] -to fpga_top/cby_1__1_/left_grid_pin_30_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[14] -to fpga_top/cby_1__1_/left_grid_pin_30_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[14] -to fpga_top/cby_1__1_/left_grid_pin_30_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[20] -to fpga_top/cby_1__1_/left_grid_pin_30_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[20] -to fpga_top/cby_1__1_/left_grid_pin_30_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[26] -to fpga_top/cby_1__1_/left_grid_pin_30_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[26] -to fpga_top/cby_1__1_/left_grid_pin_30_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[0] -to fpga_top/cby_1__1_/left_grid_pin_31_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[0] -to fpga_top/cby_1__1_/left_grid_pin_31_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[3] -to fpga_top/cby_1__1_/left_grid_pin_31_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[3] -to fpga_top/cby_1__1_/left_grid_pin_31_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[6] -to fpga_top/cby_1__1_/left_grid_pin_31_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[6] -to fpga_top/cby_1__1_/left_grid_pin_31_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[15] -to fpga_top/cby_1__1_/left_grid_pin_31_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[15] -to fpga_top/cby_1__1_/left_grid_pin_31_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[21] -to fpga_top/cby_1__1_/left_grid_pin_31_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[21] -to fpga_top/cby_1__1_/left_grid_pin_31_[0] 7.247000222e-11 diff --git a/FPGA1212_RESET_HD_SKY_PNR/FPGA1212_RESET_HD_SKY_Verilog/SDC/disable_configurable_memory_outputs.sdc b/FPGA1212_RESET_HD_SKY_PNR/FPGA1212_RESET_HD_SKY_Verilog/SDC/disable_configurable_memory_outputs.sdc deleted file mode 100644 index 87e6f51..0000000 --- a/FPGA1212_RESET_HD_SKY_PNR/FPGA1212_RESET_HD_SKY_Verilog/SDC/disable_configurable_memory_outputs.sdc +++ /dev/null @@ -1,132 +0,0 @@ -############################################# -# Synopsys Design Constraints (SDC) -# For FPGA fabric -# Description: Disable configurable memory outputs for PnR -# Author: Xifan TANG -# Organization: University of Utah -# Date: Tue Dec 1 18:12:04 2020 -############################################# - -set_disable_timing fpga_core_uut/sb_*__*_/mem_bottom_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q -set_disable_timing fpga_core_uut/sb_*__*_/mem_bottom_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q -set_disable_timing fpga_core_uut/sb_*__*_/mem_bottom_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q -set_disable_timing fpga_core_uut/sb_*__*_/mem_left_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q -set_disable_timing fpga_core_uut/sb_*__*_/mem_left_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q -set_disable_timing fpga_core_uut/sb_*__*_/mem_left_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q -set_disable_timing fpga_core_uut/cbx_*__*_/mem_bottom_ipin_*/sky*_fd_sc_hd__dfrtp_*_*_/Q -set_disable_timing fpga_core_uut/cbx_*__*_/mem_top_ipin_*/sky*_fd_sc_hd__dfrtp_*_*_/Q -set_disable_timing fpga_core_uut/cbx_*__*_/mem_top_ipin_*/sky*_fd_sc_hd__dfrtp_*_*_/Q -set_disable_timing fpga_core_uut/grid_io_top_top_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/EMBEDDED_IO_HD_sky*_fd_sc_hd__dfrtp_*_mem/sky*_fd_sc_hd__dfrtp_*_*_/Q -set_disable_timing fpga_core_uut/sb_*__*_/mem_right_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q -set_disable_timing fpga_core_uut/sb_*__*_/mem_right_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q -set_disable_timing fpga_core_uut/sb_*__*_/mem_right_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q -set_disable_timing fpga_core_uut/sb_*__*_/mem_right_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q -set_disable_timing fpga_core_uut/sb_*__*_/mem_right_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q -set_disable_timing fpga_core_uut/sb_*__*_/mem_right_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q -set_disable_timing fpga_core_uut/sb_*__*_/mem_bottom_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q -set_disable_timing fpga_core_uut/sb_*__*_/mem_bottom_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q -set_disable_timing fpga_core_uut/sb_*__*_/mem_bottom_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q -set_disable_timing fpga_core_uut/sb_*__*_/mem_bottom_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q -set_disable_timing fpga_core_uut/sb_*__*_/mem_bottom_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q -set_disable_timing fpga_core_uut/sb_*__*_/mem_left_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q -set_disable_timing fpga_core_uut/sb_*__*_/mem_left_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q -set_disable_timing fpga_core_uut/sb_*__*_/mem_left_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q -set_disable_timing fpga_core_uut/sb_*__*_/mem_left_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q -set_disable_timing fpga_core_uut/sb_*__*_/mem_left_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q -set_disable_timing fpga_core_uut/sb_*__*_/mem_left_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q -set_disable_timing fpga_core_uut/sb_*__*_/mem_right_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q -set_disable_timing fpga_core_uut/sb_*__*_/mem_right_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q -set_disable_timing fpga_core_uut/sb_*__*_/mem_right_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q -set_disable_timing fpga_core_uut/sb_*__*_/mem_bottom_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q -set_disable_timing fpga_core_uut/cby_*__*_/mem_right_ipin_*/sky*_fd_sc_hd__dfrtp_*_*_/Q -set_disable_timing fpga_core_uut/grid_io_left_left_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/EMBEDDED_IO_HD_sky*_fd_sc_hd__dfrtp_*_mem/sky*_fd_sc_hd__dfrtp_*_*_/Q -set_disable_timing fpga_core_uut/grid_clb_*__*_/logical_tile_clb_mode_clb__*/logical_tile_clb_mode_default__fle_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut*_*/frac_lut*_sky*_fd_sc_hd__dfrtp_*_mem/sky*_fd_sc_hd__dfrtp_*_*_/Q -set_disable_timing fpga_core_uut/grid_clb_*__*_/logical_tile_clb_mode_clb__*/logical_tile_clb_mode_default__fle_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_*/mem_frac_logic_out_*/sky*_fd_sc_hd__dfrtp_*_*_/Q -set_disable_timing fpga_core_uut/grid_clb_*__*_/logical_tile_clb_mode_clb__*/logical_tile_clb_mode_default__fle_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_*/mem_frac_lut*_*_in_*/sky*_fd_sc_hd__dfrtp_*_*_/Q -set_disable_timing fpga_core_uut/grid_clb_*__*_/logical_tile_clb_mode_clb__*/logical_tile_clb_mode_default__fle_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_*/mem_fabric_out_*/sky*_fd_sc_hd__dfrtp_*_*_/Q -set_disable_timing fpga_core_uut/grid_clb_*__*_/logical_tile_clb_mode_clb__*/logical_tile_clb_mode_default__fle_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_*/mem_ff_*_D_*/sky*_fd_sc_hd__dfrtp_*_*_/Q -set_disable_timing fpga_core_uut/cby_*__*_/mem_right_ipin_*/sky*_fd_sc_hd__dfrtp_*_*_/Q -set_disable_timing fpga_core_uut/cby_*__*_/mem_right_ipin_*/sky*_fd_sc_hd__dfrtp_*_*_/Q -set_disable_timing fpga_core_uut/cby_*__*_/mem_left_ipin_*/sky*_fd_sc_hd__dfrtp_*_*_/Q -set_disable_timing fpga_core_uut/cby_*__*_/mem_right_ipin_*/sky*_fd_sc_hd__dfrtp_*_*_/Q -set_disable_timing fpga_core_uut/cby_*__*_/mem_right_ipin_*/sky*_fd_sc_hd__dfrtp_*_*_/Q -set_disable_timing fpga_core_uut/grid_io_right_right_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/EMBEDDED_IO_HD_sky*_fd_sc_hd__dfrtp_*_mem/sky*_fd_sc_hd__dfrtp_*_*_/Q -set_disable_timing fpga_core_uut/sb_*__*_/mem_top_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q -set_disable_timing fpga_core_uut/sb_*__*_/mem_top_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q -set_disable_timing fpga_core_uut/sb_*__*_/mem_top_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q -set_disable_timing fpga_core_uut/sb_*__*_/mem_top_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q -set_disable_timing fpga_core_uut/sb_*__*_/mem_bottom_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q -set_disable_timing fpga_core_uut/sb_*__*_/mem_bottom_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q -set_disable_timing fpga_core_uut/sb_*__*_/mem_bottom_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q -set_disable_timing fpga_core_uut/sb_*__*_/mem_bottom_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q -set_disable_timing fpga_core_uut/sb_*__*_/mem_bottom_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q -set_disable_timing fpga_core_uut/sb_*__*_/mem_bottom_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q -set_disable_timing fpga_core_uut/sb_*__*_/mem_bottom_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q -set_disable_timing fpga_core_uut/sb_*__*_/mem_left_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q -set_disable_timing fpga_core_uut/sb_*__*_/mem_left_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q -set_disable_timing fpga_core_uut/sb_*__*_/mem_left_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q -set_disable_timing fpga_core_uut/sb_*__*_/mem_left_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q -set_disable_timing fpga_core_uut/sb_*__*_/mem_left_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q -set_disable_timing fpga_core_uut/cbx_*__*_/mem_top_ipin_*/sky*_fd_sc_hd__dfrtp_*_*_/Q -set_disable_timing fpga_core_uut/cbx_*__*_/mem_top_ipin_*/sky*_fd_sc_hd__dfrtp_*_*_/Q -set_disable_timing fpga_core_uut/sb_*__*_/mem_top_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q -set_disable_timing fpga_core_uut/sb_*__*_/mem_top_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q -set_disable_timing fpga_core_uut/sb_*__*_/mem_top_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q -set_disable_timing fpga_core_uut/sb_*__*_/mem_top_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q -set_disable_timing fpga_core_uut/sb_*__*_/mem_top_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q -set_disable_timing fpga_core_uut/sb_*__*_/mem_right_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q -set_disable_timing fpga_core_uut/sb_*__*_/mem_right_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q -set_disable_timing fpga_core_uut/sb_*__*_/mem_right_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q -set_disable_timing fpga_core_uut/sb_*__*_/mem_right_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q -set_disable_timing fpga_core_uut/sb_*__*_/mem_right_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q -set_disable_timing fpga_core_uut/sb_*__*_/mem_bottom_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q -set_disable_timing fpga_core_uut/sb_*__*_/mem_bottom_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q -set_disable_timing fpga_core_uut/sb_*__*_/mem_bottom_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q -set_disable_timing fpga_core_uut/sb_*__*_/mem_bottom_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q -set_disable_timing fpga_core_uut/sb_*__*_/mem_bottom_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q -set_disable_timing fpga_core_uut/sb_*__*_/mem_left_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q -set_disable_timing fpga_core_uut/sb_*__*_/mem_left_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q -set_disable_timing fpga_core_uut/sb_*__*_/mem_left_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q -set_disable_timing fpga_core_uut/sb_*__*_/mem_left_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q -set_disable_timing fpga_core_uut/sb_*__*_/mem_left_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q -set_disable_timing fpga_core_uut/sb_*__*_/mem_top_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q -set_disable_timing fpga_core_uut/sb_*__*_/mem_top_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q -set_disable_timing fpga_core_uut/sb_*__*_/mem_top_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q -set_disable_timing fpga_core_uut/sb_*__*_/mem_top_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q -set_disable_timing fpga_core_uut/sb_*__*_/mem_right_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q -set_disable_timing fpga_core_uut/sb_*__*_/mem_right_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q -set_disable_timing fpga_core_uut/sb_*__*_/mem_right_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q -set_disable_timing fpga_core_uut/sb_*__*_/mem_right_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q -set_disable_timing fpga_core_uut/sb_*__*_/mem_right_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q -set_disable_timing fpga_core_uut/sb_*__*_/mem_bottom_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q -set_disable_timing fpga_core_uut/sb_*__*_/mem_bottom_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q -set_disable_timing fpga_core_uut/sb_*__*_/mem_bottom_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q -set_disable_timing fpga_core_uut/sb_*__*_/mem_bottom_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q -set_disable_timing fpga_core_uut/sb_*__*_/mem_top_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q -set_disable_timing fpga_core_uut/sb_*__*_/mem_top_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q -set_disable_timing fpga_core_uut/sb_*__*_/mem_top_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q -set_disable_timing fpga_core_uut/sb_*__*_/mem_left_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q -set_disable_timing fpga_core_uut/sb_*__*_/mem_left_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q -set_disable_timing fpga_core_uut/sb_*__*_/mem_left_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q -set_disable_timing fpga_core_uut/cbx_*__*_/mem_top_ipin_*/sky*_fd_sc_hd__dfrtp_*_*_/Q -set_disable_timing fpga_core_uut/grid_io_bottom_bottom_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/EMBEDDED_IO_HD_sky*_fd_sc_hd__dfrtp_*_mem/sky*_fd_sc_hd__dfrtp_*_*_/Q -set_disable_timing fpga_core_uut/sb_*__*_/mem_top_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q -set_disable_timing fpga_core_uut/sb_*__*_/mem_top_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q -set_disable_timing fpga_core_uut/sb_*__*_/mem_top_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q -set_disable_timing fpga_core_uut/sb_*__*_/mem_top_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q -set_disable_timing fpga_core_uut/sb_*__*_/mem_top_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q -set_disable_timing fpga_core_uut/sb_*__*_/mem_top_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q -set_disable_timing fpga_core_uut/sb_*__*_/mem_right_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q -set_disable_timing fpga_core_uut/sb_*__*_/mem_right_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q -set_disable_timing fpga_core_uut/sb_*__*_/mem_right_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q -set_disable_timing fpga_core_uut/sb_*__*_/mem_right_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q -set_disable_timing fpga_core_uut/sb_*__*_/mem_right_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q -set_disable_timing fpga_core_uut/sb_*__*_/mem_right_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q -set_disable_timing fpga_core_uut/sb_*__*_/mem_left_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q -set_disable_timing fpga_core_uut/sb_*__*_/mem_left_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q -set_disable_timing fpga_core_uut/sb_*__*_/mem_left_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q -set_disable_timing fpga_core_uut/sb_*__*_/mem_left_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q -set_disable_timing fpga_core_uut/sb_*__*_/mem_top_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q -set_disable_timing fpga_core_uut/sb_*__*_/mem_right_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q -set_disable_timing fpga_core_uut/sb_*__*_/mem_right_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q -set_disable_timing fpga_core_uut/sb_*__*_/mem_right_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q diff --git a/FPGA1212_RESET_HD_SKY_PNR/FPGA1212_RESET_HD_SKY_Verilog/SDC/disable_routing_multiplexer_outputs.sdc b/FPGA1212_RESET_HD_SKY_PNR/FPGA1212_RESET_HD_SKY_Verilog/SDC/disable_routing_multiplexer_outputs.sdc deleted file mode 100644 index 282cb87..0000000 --- a/FPGA1212_RESET_HD_SKY_PNR/FPGA1212_RESET_HD_SKY_Verilog/SDC/disable_routing_multiplexer_outputs.sdc +++ /dev/null @@ -1,127 +0,0 @@ -############################################# -# Synopsys Design Constraints (SDC) -# For FPGA fabric -# Description: Disable routing multiplexer outputs for PnR -# Author: Xifan TANG -# Organization: University of Utah -# Date: Tue Dec 1 18:12:04 2020 -############################################# - -set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/out -set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/out -set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/out -set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/out -set_disable_timing fpga_core_uut/cbx_*__*_/mux_top_ipin_*/out -set_disable_timing fpga_core_uut/cbx_*__*_/mux_top_ipin_*/out -set_disable_timing fpga_core_uut/cbx_*__*_/mux_bottom_ipin_*/out -set_disable_timing fpga_core_uut/cbx_*__*_/mux_top_ipin_*/out -set_disable_timing fpga_core_uut/cby_*__*_/mux_right_ipin_*/out -set_disable_timing fpga_core_uut/cby_*__*_/mux_right_ipin_*/out -set_disable_timing fpga_core_uut/cby_*__*_/mux_left_ipin_*/out -set_disable_timing fpga_core_uut/cby_*__*_/mux_right_ipin_*/out -set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/out -set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/out -set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/out -set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/out -set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/out -set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/out -set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/out -set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/out -set_disable_timing fpga_core_uut/cbx_*__*_/mux_top_ipin_*/out -set_disable_timing fpga_core_uut/cbx_*__*_/mux_top_ipin_*/out -set_disable_timing fpga_core_uut/cby_*__*_/mux_right_ipin_*/out -set_disable_timing fpga_core_uut/cby_*__*_/mux_right_ipin_*/out -set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/out -set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/out -set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/out -set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/out -set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/out -set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/out -set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/out -set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/out -set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/out -set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/out -set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/out -set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/out -set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/out -set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/out -set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/out -set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/out -set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/out -set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/out -set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/out -set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/out -set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/out -set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/out -set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/out -set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/out -set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/out -set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/out -set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/out -set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/out -set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/out -set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/out -set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/out -set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/out -set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/out -set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/out -set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/out -set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/out -set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/out -set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/out -set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/out -set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/out -set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/out -set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/out -set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/out -set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/out -set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/out -set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/out -set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/out -set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/out -set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/out -set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/out -set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/out -set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/out -set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/out -set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/out -set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/out -set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/out -set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/out -set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/out -set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/out -set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/out -set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/out -set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/out -set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/out -set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/out -set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/out -set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/out -set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/out -set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/out -set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/out -set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/out -set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/out -set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/out -set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/out -set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/out -set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/out -set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/out -set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/out -set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/out -set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/out -set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/out -set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/out -set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/out -set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/out -set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/out -set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/out -set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/out -set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/out -set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/out -set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/out -set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/out -set_disable_timing fpga_core_uut/grid_clb_*__*_/logical_tile_clb_mode_clb__*/logical_tile_clb_mode_default__fle_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_*/mux_frac_logic_out_*/out -set_disable_timing fpga_core_uut/grid_clb_*__*_/logical_tile_clb_mode_clb__*/logical_tile_clb_mode_default__fle_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_*/mux_frac_lut*_*_in_*/out -set_disable_timing fpga_core_uut/grid_clb_*__*_/logical_tile_clb_mode_clb__*/logical_tile_clb_mode_default__fle_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_*/mux_fabric_out_*/out -set_disable_timing fpga_core_uut/grid_clb_*__*_/logical_tile_clb_mode_clb__*/logical_tile_clb_mode_default__fle_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_*/mux_ff_*_D_*/out diff --git a/FPGA1212_RESET_HD_SKY_PNR/FPGA1212_RESET_HD_SKY_Verilog/SDC/disable_sb_outputs.sdc b/FPGA1212_RESET_HD_SKY_PNR/FPGA1212_RESET_HD_SKY_Verilog/SDC/disable_sb_outputs.sdc deleted file mode 100644 index e8e4de2..0000000 --- a/FPGA1212_RESET_HD_SKY_PNR/FPGA1212_RESET_HD_SKY_Verilog/SDC/disable_sb_outputs.sdc +++ /dev/null @@ -1,75 +0,0 @@ -############################################# -# Synopsys Design Constraints (SDC) -# For FPGA fabric -# Description: Disable Switch Block outputs for PnR -# Author: Xifan TANG -# Organization: University of Utah -# Date: Tue Dec 1 18:12:04 2020 -############################################# - -set_disable_timing fpga_core_uut/sb_*__*_/chany_top_out - -set_disable_timing fpga_core_uut/sb_*__*_/chanx_right_out - -set_disable_timing fpga_core_uut/sb_*__*_/ccff_tail - -set_disable_timing fpga_core_uut/sb_*__*_/chany_top_out - -set_disable_timing fpga_core_uut/sb_*__*_/chanx_right_out - -set_disable_timing fpga_core_uut/sb_*__*_/chany_bottom_out - -set_disable_timing fpga_core_uut/sb_*__*_/ccff_tail - -set_disable_timing fpga_core_uut/sb_*__*_/chanx_right_out - -set_disable_timing fpga_core_uut/sb_*__*_/chany_bottom_out - -set_disable_timing fpga_core_uut/sb_*__*_/ccff_tail - -set_disable_timing fpga_core_uut/sb_*__*_/chany_top_out - -set_disable_timing fpga_core_uut/sb_*__*_/chanx_right_out - -set_disable_timing fpga_core_uut/sb_*__*_/chanx_left_out - -set_disable_timing fpga_core_uut/sb_*__*_/ccff_tail - -set_disable_timing fpga_core_uut/sb_*__*_/chany_top_out - -set_disable_timing fpga_core_uut/sb_*__*_/chanx_right_out - -set_disable_timing fpga_core_uut/sb_*__*_/chany_bottom_out - -set_disable_timing fpga_core_uut/sb_*__*_/chanx_left_out - -set_disable_timing fpga_core_uut/sb_*__*_/ccff_tail - -set_disable_timing fpga_core_uut/sb_*__*_/chanx_right_out - -set_disable_timing fpga_core_uut/sb_*__*_/chany_bottom_out - -set_disable_timing fpga_core_uut/sb_*__*_/chanx_left_out - -set_disable_timing fpga_core_uut/sb_*__*_/ccff_tail - -set_disable_timing fpga_core_uut/sb_*__*_/chany_top_out - -set_disable_timing fpga_core_uut/sb_*__*_/chanx_left_out - -set_disable_timing fpga_core_uut/sb_*__*_/ccff_tail - -set_disable_timing fpga_core_uut/sb_*__*_/chany_top_out - -set_disable_timing fpga_core_uut/sb_*__*_/chany_bottom_out - -set_disable_timing fpga_core_uut/sb_*__*_/chanx_left_out - -set_disable_timing fpga_core_uut/sb_*__*_/ccff_tail - -set_disable_timing fpga_core_uut/sb_*__*_/chany_bottom_out - -set_disable_timing fpga_core_uut/sb_*__*_/chanx_left_out - -set_disable_timing fpga_core_uut/sb_*__*_/ccff_tail - diff --git a/FPGA1212_RESET_HD_SKY_PNR/FPGA1212_RESET_HD_SKY_Verilog/SDC/global_ports.sdc b/FPGA1212_RESET_HD_SKY_PNR/FPGA1212_RESET_HD_SKY_Verilog/SDC/global_ports.sdc deleted file mode 100644 index cb2c606..0000000 --- a/FPGA1212_RESET_HD_SKY_PNR/FPGA1212_RESET_HD_SKY_Verilog/SDC/global_ports.sdc +++ /dev/null @@ -1,17 +0,0 @@ -############################################# -# Synopsys Design Constraints (SDC) -# For FPGA fabric -# Description: Clock contraints for PnR -# Author: Xifan TANG -# Organization: University of Utah -# Date: Tue Dec 1 18:12:04 2020 -############################################# - -################################################## -# Create programmable clock -################################################## -create_clock -name prog_clk[0] -period 9.999999939e-09 -waveform {0 4.99999997e-09} [get_ports {prog_clk[0]}] -################################################## -# Create clock -################################################## -create_clock -name clk[0] -period 8.319719358e-10 -waveform {0 4.159859679e-10} [get_ports {clk[0]}] diff --git a/FPGA1212_RESET_HD_SKY_PNR/FPGA1212_RESET_HD_SKY_Verilog/SDC/logical_tile_clb_mode_clb_.sdc b/FPGA1212_RESET_HD_SKY_PNR/FPGA1212_RESET_HD_SKY_Verilog/SDC/logical_tile_clb_mode_clb_.sdc deleted file mode 100644 index 81b9699..0000000 --- a/FPGA1212_RESET_HD_SKY_PNR/FPGA1212_RESET_HD_SKY_Verilog/SDC/logical_tile_clb_mode_clb_.sdc +++ /dev/null @@ -1,17 +0,0 @@ -############################################# -# Synopsys Design Constraints (SDC) -# For FPGA fabric -# Description: Timing constraints for Grid logical_tile_clb_mode_clb_ in PnR -# Author: Xifan TANG -# Organization: University of Utah -# Date: Tue Dec 1 18:12:04 2020 -############################################# - -############################################# -# Define time unit -############################################# -set_units -time s - -set_max_delay -from fpga_core_uut/grid_clb/logical_tile_clb_mode_clb__0_/clb_reg_in[0] -to fpga_top/grid_clb/logical_tile_clb_mode_default__fle_0/fle_reg_in[0] 1.599999994e-10 -set_max_delay -from fpga_core_uut/grid_clb/logical_tile_clb_mode_clb__0_/clb_sc_in[0] -to fpga_top/grid_clb/logical_tile_clb_mode_default__fle_0/fle_sc_in[0] 1.599999994e-10 -set_max_delay -from fpga_core_uut/grid_clb/logical_tile_clb_mode_clb__0_/clb_cin[0] -to fpga_top/grid_clb/logical_tile_clb_mode_default__fle_0/fle_cin[0] 1.599999994e-10 diff --git a/FPGA1212_RESET_HD_SKY_PNR/FPGA1212_RESET_HD_SKY_Verilog/SDC/logical_tile_clb_mode_default__fle.sdc b/FPGA1212_RESET_HD_SKY_PNR/FPGA1212_RESET_HD_SKY_Verilog/SDC/logical_tile_clb_mode_default__fle.sdc deleted file mode 100644 index 4e14033..0000000 --- a/FPGA1212_RESET_HD_SKY_PNR/FPGA1212_RESET_HD_SKY_Verilog/SDC/logical_tile_clb_mode_default__fle.sdc +++ /dev/null @@ -1,14 +0,0 @@ -############################################# -# Synopsys Design Constraints (SDC) -# For FPGA fabric -# Description: Timing constraints for Grid logical_tile_clb_mode_default__fle in PnR -# Author: Xifan TANG -# Organization: University of Utah -# Date: Tue Dec 1 18:12:04 2020 -############################################# - -############################################# -# Define time unit -############################################# -set_units -time s - diff --git a/FPGA1212_RESET_HD_SKY_PNR/FPGA1212_RESET_HD_SKY_Verilog/SDC/logical_tile_clb_mode_default__fle_mode_physical__fabric.sdc b/FPGA1212_RESET_HD_SKY_PNR/FPGA1212_RESET_HD_SKY_Verilog/SDC/logical_tile_clb_mode_default__fle_mode_physical__fabric.sdc deleted file mode 100644 index f11fe8e..0000000 --- a/FPGA1212_RESET_HD_SKY_PNR/FPGA1212_RESET_HD_SKY_Verilog/SDC/logical_tile_clb_mode_default__fle_mode_physical__fabric.sdc +++ /dev/null @@ -1,22 +0,0 @@ -############################################# -# Synopsys Design Constraints (SDC) -# For FPGA fabric -# Description: Timing constraints for Grid logical_tile_clb_mode_default__fle_mode_physical__fabric in PnR -# Author: Xifan TANG -# Organization: University of Utah -# Date: Tue Dec 1 18:12:04 2020 -############################################# - -############################################# -# Define time unit -############################################# -set_units -time s - -set_max_delay -from fpga_core_uut/grid_clb/fle/fabric/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0/ff_Q[0] -to fpga_top/grid_clb/fle/fabric/logical_tile_clb_mode_default__fle_mode_physical__fabric_0_/fabric_out[0] 4.500000025e-11 -set_max_delay -from fpga_core_uut/grid_clb/fle/fabric/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/frac_logic_out[0] -to fpga_top/grid_clb/fle/fabric/logical_tile_clb_mode_default__fle_mode_physical__fabric_0_/fabric_out[0] 2.500000033e-11 -set_max_delay -from fpga_core_uut/grid_clb/fle/fabric/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1/ff_Q[0] -to fpga_top/grid_clb/fle/fabric/logical_tile_clb_mode_default__fle_mode_physical__fabric_0_/fabric_out[1] 4.500000025e-11 -set_max_delay -from fpga_core_uut/grid_clb/fle/fabric/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/frac_logic_out[1] -to fpga_top/grid_clb/fle/fabric/logical_tile_clb_mode_default__fle_mode_physical__fabric_0_/fabric_out[1] 2.500000033e-11 -set_max_delay -from fpga_core_uut/grid_clb/fle/fabric/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/frac_logic_out[0] -to fpga_top/grid_clb/fle/fabric/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0/ff_D[0] 2.500000033e-11 -set_max_delay -from fpga_core_uut/grid_clb/fle/fabric/logical_tile_clb_mode_default__fle_mode_physical__fabric_0_/fabric_reg_in[0] -to fpga_top/grid_clb/fle/fabric/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0/ff_D[0] 4.500000025e-11 -set_max_delay -from fpga_core_uut/grid_clb/fle/fabric/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/frac_logic_out[1] -to fpga_top/grid_clb/fle/fabric/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1/ff_D[0] 2.500000033e-11 -set_max_delay -from fpga_core_uut/grid_clb/fle/fabric/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0/ff_Q[0] -to fpga_top/grid_clb/fle/fabric/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1/ff_D[0] 4.500000025e-11 diff --git a/FPGA1212_RESET_HD_SKY_PNR/FPGA1212_RESET_HD_SKY_Verilog/SDC/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff.sdc b/FPGA1212_RESET_HD_SKY_PNR/FPGA1212_RESET_HD_SKY_Verilog/SDC/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff.sdc deleted file mode 100644 index befd6fa..0000000 --- a/FPGA1212_RESET_HD_SKY_PNR/FPGA1212_RESET_HD_SKY_Verilog/SDC/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff.sdc +++ /dev/null @@ -1,14 +0,0 @@ -############################################# -# Synopsys Design Constraints (SDC) -# For FPGA fabric -# Description: Timing constraints for Grid logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff in PnR -# Author: Xifan TANG -# Organization: University of Utah -# Date: Tue Dec 1 18:12:04 2020 -############################################# - -############################################# -# Define time unit -############################################# -set_units -time s - diff --git a/FPGA1212_RESET_HD_SKY_PNR/FPGA1212_RESET_HD_SKY_Verilog/SDC/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic.sdc b/FPGA1212_RESET_HD_SKY_PNR/FPGA1212_RESET_HD_SKY_Verilog/SDC/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic.sdc deleted file mode 100644 index 29c5df5..0000000 --- a/FPGA1212_RESET_HD_SKY_PNR/FPGA1212_RESET_HD_SKY_Verilog/SDC/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic.sdc +++ /dev/null @@ -1,14 +0,0 @@ -############################################# -# Synopsys Design Constraints (SDC) -# For FPGA fabric -# Description: Timing constraints for Grid logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic in PnR -# Author: Xifan TANG -# Organization: University of Utah -# Date: Tue Dec 1 18:12:04 2020 -############################################# - -############################################# -# Define time unit -############################################# -set_units -time s - diff --git a/FPGA1212_RESET_HD_SKY_PNR/FPGA1212_RESET_HD_SKY_Verilog/SDC/logical_tile_io_mode_io_.sdc b/FPGA1212_RESET_HD_SKY_PNR/FPGA1212_RESET_HD_SKY_Verilog/SDC/logical_tile_io_mode_io_.sdc deleted file mode 100644 index 811ef68..0000000 --- a/FPGA1212_RESET_HD_SKY_PNR/FPGA1212_RESET_HD_SKY_Verilog/SDC/logical_tile_io_mode_io_.sdc +++ /dev/null @@ -1,16 +0,0 @@ -############################################# -# Synopsys Design Constraints (SDC) -# For FPGA fabric -# Description: Timing constraints for Grid logical_tile_io_mode_io_ in PnR -# Author: Xifan TANG -# Organization: University of Utah -# Date: Tue Dec 1 18:12:04 2020 -############################################# - -############################################# -# Define time unit -############################################# -set_units -time s - -set_max_delay -from fpga_core_uut/grid_io_left_left/logical_tile_io_mode_physical__iopad_0/iopad_inpad[0] -to fpga_top/grid_io_left_left/logical_tile_io_mode_io__0_/io_inpad[0] 4.243000049e-11 -set_max_delay -from fpga_core_uut/grid_io_left_left/logical_tile_io_mode_io__0_/io_outpad[0] -to fpga_top/grid_io_left_left/logical_tile_io_mode_physical__iopad_0/iopad_outpad[0] 1.39400002e-11 diff --git a/FPGA1212_RESET_HD_SKY_PNR/FPGA1212_RESET_HD_SKY_Verilog/SDC/sb_0__0_.sdc b/FPGA1212_RESET_HD_SKY_PNR/FPGA1212_RESET_HD_SKY_Verilog/SDC/sb_0__0_.sdc deleted file mode 100644 index 86b3223..0000000 --- a/FPGA1212_RESET_HD_SKY_PNR/FPGA1212_RESET_HD_SKY_Verilog/SDC/sb_0__0_.sdc +++ /dev/null @@ -1,124 +0,0 @@ -############################################# -# Synopsys Design Constraints (SDC) -# For FPGA fabric -# Description: Constrain timing of Switch Block sb_0__0_ for PnR -# Author: Xifan TANG -# Organization: University of Utah -# Date: Tue Dec 1 18:12:04 2020 -############################################# - -############################################# -# Define time unit -############################################# -set_units -time s - -set_max_delay -from fpga_core_uut/sb_0__0_/top_left_grid_pin_1_[0] -to fpga_top/sb_0__0_/chany_top_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__0_/chanx_right_in[1] -to fpga_top/sb_0__0_/chany_top_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__0_/chanx_right_in[2] -to fpga_top/sb_0__0_/chany_top_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__0_/chanx_right_in[3] -to fpga_top/sb_0__0_/chany_top_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__0_/top_left_grid_pin_1_[0] -to fpga_top/sb_0__0_/chany_top_out[3] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__0_/chanx_right_in[4] -to fpga_top/sb_0__0_/chany_top_out[3] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__0_/chanx_right_in[5] -to fpga_top/sb_0__0_/chany_top_out[4] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__0_/chanx_right_in[6] -to fpga_top/sb_0__0_/chany_top_out[5] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__0_/top_left_grid_pin_1_[0] -to fpga_top/sb_0__0_/chany_top_out[6] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__0_/chanx_right_in[7] -to fpga_top/sb_0__0_/chany_top_out[6] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__0_/chanx_right_in[8] -to fpga_top/sb_0__0_/chany_top_out[7] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__0_/chanx_right_in[9] -to fpga_top/sb_0__0_/chany_top_out[8] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__0_/chanx_right_in[10] -to fpga_top/sb_0__0_/chany_top_out[9] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__0_/chanx_right_in[11] -to fpga_top/sb_0__0_/chany_top_out[10] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__0_/chanx_right_in[12] -to fpga_top/sb_0__0_/chany_top_out[11] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__0_/chanx_right_in[13] -to fpga_top/sb_0__0_/chany_top_out[12] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__0_/chanx_right_in[14] -to fpga_top/sb_0__0_/chany_top_out[13] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__0_/top_left_grid_pin_1_[0] -to fpga_top/sb_0__0_/chany_top_out[14] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__0_/chanx_right_in[15] -to fpga_top/sb_0__0_/chany_top_out[14] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__0_/chanx_right_in[16] -to fpga_top/sb_0__0_/chany_top_out[15] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__0_/chanx_right_in[17] -to fpga_top/sb_0__0_/chany_top_out[16] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__0_/chanx_right_in[18] -to fpga_top/sb_0__0_/chany_top_out[17] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__0_/chanx_right_in[19] -to fpga_top/sb_0__0_/chany_top_out[18] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__0_/chanx_right_in[20] -to fpga_top/sb_0__0_/chany_top_out[19] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__0_/chanx_right_in[21] -to fpga_top/sb_0__0_/chany_top_out[20] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__0_/chanx_right_in[22] -to fpga_top/sb_0__0_/chany_top_out[21] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__0_/top_left_grid_pin_1_[0] -to fpga_top/sb_0__0_/chany_top_out[22] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__0_/chanx_right_in[23] -to fpga_top/sb_0__0_/chany_top_out[22] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__0_/chanx_right_in[24] -to fpga_top/sb_0__0_/chany_top_out[23] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__0_/chanx_right_in[25] -to fpga_top/sb_0__0_/chany_top_out[24] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__0_/chanx_right_in[26] -to fpga_top/sb_0__0_/chany_top_out[25] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__0_/chanx_right_in[27] -to fpga_top/sb_0__0_/chany_top_out[26] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__0_/chanx_right_in[28] -to fpga_top/sb_0__0_/chany_top_out[27] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__0_/chanx_right_in[29] -to fpga_top/sb_0__0_/chany_top_out[28] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__0_/chanx_right_in[0] -to fpga_top/sb_0__0_/chany_top_out[29] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__0_/chany_top_in[29] -to fpga_top/sb_0__0_/chanx_right_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_1_[0] -to fpga_top/sb_0__0_/chanx_right_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_7_[0] -to fpga_top/sb_0__0_/chanx_right_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_13_[0] -to fpga_top/sb_0__0_/chanx_right_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__0_/chany_top_in[0] -to fpga_top/sb_0__0_/chanx_right_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_3_[0] -to fpga_top/sb_0__0_/chanx_right_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_9_[0] -to fpga_top/sb_0__0_/chanx_right_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_15_[0] -to fpga_top/sb_0__0_/chanx_right_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__0_/chany_top_in[1] -to fpga_top/sb_0__0_/chanx_right_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_5_[0] -to fpga_top/sb_0__0_/chanx_right_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_11_[0] -to fpga_top/sb_0__0_/chanx_right_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_17_[0] -to fpga_top/sb_0__0_/chanx_right_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__0_/chany_top_in[2] -to fpga_top/sb_0__0_/chanx_right_out[3] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_1_[0] -to fpga_top/sb_0__0_/chanx_right_out[3] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_7_[0] -to fpga_top/sb_0__0_/chanx_right_out[3] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_13_[0] -to fpga_top/sb_0__0_/chanx_right_out[3] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__0_/chany_top_in[3] -to fpga_top/sb_0__0_/chanx_right_out[4] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_3_[0] -to fpga_top/sb_0__0_/chanx_right_out[4] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_9_[0] -to fpga_top/sb_0__0_/chanx_right_out[4] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_15_[0] -to fpga_top/sb_0__0_/chanx_right_out[4] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__0_/chany_top_in[4] -to fpga_top/sb_0__0_/chanx_right_out[5] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_5_[0] -to fpga_top/sb_0__0_/chanx_right_out[5] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_11_[0] -to fpga_top/sb_0__0_/chanx_right_out[5] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_17_[0] -to fpga_top/sb_0__0_/chanx_right_out[5] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__0_/chany_top_in[5] -to fpga_top/sb_0__0_/chanx_right_out[6] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_1_[0] -to fpga_top/sb_0__0_/chanx_right_out[6] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_17_[0] -to fpga_top/sb_0__0_/chanx_right_out[6] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__0_/chany_top_in[6] -to fpga_top/sb_0__0_/chanx_right_out[7] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_3_[0] -to fpga_top/sb_0__0_/chanx_right_out[7] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__0_/chany_top_in[7] -to fpga_top/sb_0__0_/chanx_right_out[8] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_5_[0] -to fpga_top/sb_0__0_/chanx_right_out[8] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__0_/chany_top_in[8] -to fpga_top/sb_0__0_/chanx_right_out[9] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_7_[0] -to fpga_top/sb_0__0_/chanx_right_out[9] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__0_/chany_top_in[9] -to fpga_top/sb_0__0_/chanx_right_out[10] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_9_[0] -to fpga_top/sb_0__0_/chanx_right_out[10] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__0_/chany_top_in[10] -to fpga_top/sb_0__0_/chanx_right_out[11] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_11_[0] -to fpga_top/sb_0__0_/chanx_right_out[11] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__0_/chany_top_in[11] -to fpga_top/sb_0__0_/chanx_right_out[12] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_13_[0] -to fpga_top/sb_0__0_/chanx_right_out[12] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__0_/chany_top_in[12] -to fpga_top/sb_0__0_/chanx_right_out[13] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_15_[0] -to fpga_top/sb_0__0_/chanx_right_out[13] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__0_/chany_top_in[13] -to fpga_top/sb_0__0_/chanx_right_out[14] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_1_[0] -to fpga_top/sb_0__0_/chanx_right_out[14] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_17_[0] -to fpga_top/sb_0__0_/chanx_right_out[14] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__0_/chany_top_in[14] -to fpga_top/sb_0__0_/chanx_right_out[15] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_3_[0] -to fpga_top/sb_0__0_/chanx_right_out[15] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__0_/chany_top_in[15] -to fpga_top/sb_0__0_/chanx_right_out[16] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_5_[0] -to fpga_top/sb_0__0_/chanx_right_out[16] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__0_/chany_top_in[16] -to fpga_top/sb_0__0_/chanx_right_out[17] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_7_[0] -to fpga_top/sb_0__0_/chanx_right_out[17] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__0_/chany_top_in[17] -to fpga_top/sb_0__0_/chanx_right_out[18] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_9_[0] -to fpga_top/sb_0__0_/chanx_right_out[18] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__0_/chany_top_in[18] -to fpga_top/sb_0__0_/chanx_right_out[19] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_11_[0] -to fpga_top/sb_0__0_/chanx_right_out[19] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__0_/chany_top_in[19] -to fpga_top/sb_0__0_/chanx_right_out[20] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_13_[0] -to fpga_top/sb_0__0_/chanx_right_out[20] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__0_/chany_top_in[20] -to fpga_top/sb_0__0_/chanx_right_out[21] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_15_[0] -to fpga_top/sb_0__0_/chanx_right_out[21] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__0_/chany_top_in[21] -to fpga_top/sb_0__0_/chanx_right_out[22] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_1_[0] -to fpga_top/sb_0__0_/chanx_right_out[22] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_17_[0] -to fpga_top/sb_0__0_/chanx_right_out[22] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__0_/chany_top_in[22] -to fpga_top/sb_0__0_/chanx_right_out[23] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_3_[0] -to fpga_top/sb_0__0_/chanx_right_out[23] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__0_/chany_top_in[23] -to fpga_top/sb_0__0_/chanx_right_out[24] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_5_[0] -to fpga_top/sb_0__0_/chanx_right_out[24] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__0_/chany_top_in[24] -to fpga_top/sb_0__0_/chanx_right_out[25] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_7_[0] -to fpga_top/sb_0__0_/chanx_right_out[25] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__0_/chany_top_in[25] -to fpga_top/sb_0__0_/chanx_right_out[26] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_9_[0] -to fpga_top/sb_0__0_/chanx_right_out[26] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__0_/chany_top_in[26] -to fpga_top/sb_0__0_/chanx_right_out[27] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_11_[0] -to fpga_top/sb_0__0_/chanx_right_out[27] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__0_/chany_top_in[27] -to fpga_top/sb_0__0_/chanx_right_out[28] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_13_[0] -to fpga_top/sb_0__0_/chanx_right_out[28] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__0_/chany_top_in[28] -to fpga_top/sb_0__0_/chanx_right_out[29] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_15_[0] -to fpga_top/sb_0__0_/chanx_right_out[29] 6.020400151e-11 diff --git a/FPGA1212_RESET_HD_SKY_PNR/FPGA1212_RESET_HD_SKY_Verilog/SDC/sb_0__12_.sdc b/FPGA1212_RESET_HD_SKY_PNR/FPGA1212_RESET_HD_SKY_Verilog/SDC/sb_0__12_.sdc deleted file mode 100644 index 3b43f8a..0000000 --- a/FPGA1212_RESET_HD_SKY_PNR/FPGA1212_RESET_HD_SKY_Verilog/SDC/sb_0__12_.sdc +++ /dev/null @@ -1,123 +0,0 @@ -############################################# -# Synopsys Design Constraints (SDC) -# For FPGA fabric -# Description: Constrain timing of Switch Block sb_0__12_ for PnR -# Author: Xifan TANG -# Organization: University of Utah -# Date: Tue Dec 1 18:12:04 2020 -############################################# - -############################################# -# Define time unit -############################################# -set_units -time s - -set_max_delay -from fpga_core_uut/sb_0__12_/right_top_grid_pin_1_[0] -to fpga_top/sb_0__12_/chanx_right_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__12_/right_bottom_grid_pin_38_[0] -to fpga_top/sb_0__12_/chanx_right_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__12_/right_bottom_grid_pin_41_[0] -to fpga_top/sb_0__12_/chanx_right_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__12_/chany_bottom_in[28] -to fpga_top/sb_0__12_/chanx_right_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__12_/right_bottom_grid_pin_36_[0] -to fpga_top/sb_0__12_/chanx_right_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__12_/right_bottom_grid_pin_39_[0] -to fpga_top/sb_0__12_/chanx_right_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__12_/right_bottom_grid_pin_42_[0] -to fpga_top/sb_0__12_/chanx_right_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__12_/chany_bottom_in[27] -to fpga_top/sb_0__12_/chanx_right_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__12_/right_bottom_grid_pin_37_[0] -to fpga_top/sb_0__12_/chanx_right_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__12_/right_bottom_grid_pin_40_[0] -to fpga_top/sb_0__12_/chanx_right_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__12_/right_bottom_grid_pin_43_[0] -to fpga_top/sb_0__12_/chanx_right_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__12_/chany_bottom_in[26] -to fpga_top/sb_0__12_/chanx_right_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__12_/right_top_grid_pin_1_[0] -to fpga_top/sb_0__12_/chanx_right_out[3] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__12_/right_bottom_grid_pin_38_[0] -to fpga_top/sb_0__12_/chanx_right_out[3] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__12_/right_bottom_grid_pin_41_[0] -to fpga_top/sb_0__12_/chanx_right_out[3] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__12_/chany_bottom_in[25] -to fpga_top/sb_0__12_/chanx_right_out[3] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__12_/right_bottom_grid_pin_36_[0] -to fpga_top/sb_0__12_/chanx_right_out[4] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__12_/right_bottom_grid_pin_39_[0] -to fpga_top/sb_0__12_/chanx_right_out[4] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__12_/right_bottom_grid_pin_42_[0] -to fpga_top/sb_0__12_/chanx_right_out[4] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__12_/chany_bottom_in[24] -to fpga_top/sb_0__12_/chanx_right_out[4] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__12_/right_bottom_grid_pin_37_[0] -to fpga_top/sb_0__12_/chanx_right_out[5] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__12_/right_bottom_grid_pin_40_[0] -to fpga_top/sb_0__12_/chanx_right_out[5] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__12_/right_bottom_grid_pin_43_[0] -to fpga_top/sb_0__12_/chanx_right_out[5] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__12_/chany_bottom_in[23] -to fpga_top/sb_0__12_/chanx_right_out[5] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__12_/right_top_grid_pin_1_[0] -to fpga_top/sb_0__12_/chanx_right_out[6] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__12_/chany_bottom_in[22] -to fpga_top/sb_0__12_/chanx_right_out[6] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__12_/right_bottom_grid_pin_36_[0] -to fpga_top/sb_0__12_/chanx_right_out[7] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__12_/chany_bottom_in[21] -to fpga_top/sb_0__12_/chanx_right_out[7] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__12_/right_bottom_grid_pin_37_[0] -to fpga_top/sb_0__12_/chanx_right_out[8] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__12_/chany_bottom_in[20] -to fpga_top/sb_0__12_/chanx_right_out[8] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__12_/right_bottom_grid_pin_38_[0] -to fpga_top/sb_0__12_/chanx_right_out[9] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__12_/chany_bottom_in[19] -to fpga_top/sb_0__12_/chanx_right_out[9] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__12_/right_bottom_grid_pin_39_[0] -to fpga_top/sb_0__12_/chanx_right_out[10] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__12_/chany_bottom_in[18] -to fpga_top/sb_0__12_/chanx_right_out[10] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__12_/right_bottom_grid_pin_40_[0] -to fpga_top/sb_0__12_/chanx_right_out[11] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__12_/chany_bottom_in[17] -to fpga_top/sb_0__12_/chanx_right_out[11] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__12_/right_bottom_grid_pin_41_[0] -to fpga_top/sb_0__12_/chanx_right_out[12] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__12_/chany_bottom_in[16] -to fpga_top/sb_0__12_/chanx_right_out[12] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__12_/right_bottom_grid_pin_42_[0] -to fpga_top/sb_0__12_/chanx_right_out[13] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__12_/chany_bottom_in[15] -to fpga_top/sb_0__12_/chanx_right_out[13] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__12_/right_top_grid_pin_1_[0] -to fpga_top/sb_0__12_/chanx_right_out[14] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__12_/right_bottom_grid_pin_43_[0] -to fpga_top/sb_0__12_/chanx_right_out[14] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__12_/chany_bottom_in[14] -to fpga_top/sb_0__12_/chanx_right_out[14] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__12_/right_bottom_grid_pin_36_[0] -to fpga_top/sb_0__12_/chanx_right_out[15] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__12_/chany_bottom_in[13] -to fpga_top/sb_0__12_/chanx_right_out[15] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__12_/right_bottom_grid_pin_37_[0] -to fpga_top/sb_0__12_/chanx_right_out[16] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__12_/chany_bottom_in[12] -to fpga_top/sb_0__12_/chanx_right_out[16] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__12_/right_bottom_grid_pin_38_[0] -to fpga_top/sb_0__12_/chanx_right_out[17] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__12_/chany_bottom_in[11] -to fpga_top/sb_0__12_/chanx_right_out[17] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__12_/right_bottom_grid_pin_39_[0] -to fpga_top/sb_0__12_/chanx_right_out[18] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__12_/chany_bottom_in[10] -to fpga_top/sb_0__12_/chanx_right_out[18] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__12_/right_bottom_grid_pin_40_[0] -to fpga_top/sb_0__12_/chanx_right_out[19] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__12_/chany_bottom_in[9] -to fpga_top/sb_0__12_/chanx_right_out[19] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__12_/right_bottom_grid_pin_41_[0] -to fpga_top/sb_0__12_/chanx_right_out[20] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__12_/chany_bottom_in[8] -to fpga_top/sb_0__12_/chanx_right_out[20] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__12_/right_bottom_grid_pin_42_[0] -to fpga_top/sb_0__12_/chanx_right_out[21] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__12_/chany_bottom_in[7] -to fpga_top/sb_0__12_/chanx_right_out[21] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__12_/right_top_grid_pin_1_[0] -to fpga_top/sb_0__12_/chanx_right_out[22] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__12_/chany_bottom_in[6] -to fpga_top/sb_0__12_/chanx_right_out[22] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__12_/right_bottom_grid_pin_36_[0] -to fpga_top/sb_0__12_/chanx_right_out[23] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__12_/chany_bottom_in[5] -to fpga_top/sb_0__12_/chanx_right_out[23] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__12_/right_bottom_grid_pin_37_[0] -to fpga_top/sb_0__12_/chanx_right_out[24] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__12_/chany_bottom_in[4] -to fpga_top/sb_0__12_/chanx_right_out[24] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__12_/right_bottom_grid_pin_38_[0] -to fpga_top/sb_0__12_/chanx_right_out[25] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__12_/chany_bottom_in[3] -to fpga_top/sb_0__12_/chanx_right_out[25] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__12_/right_bottom_grid_pin_39_[0] -to fpga_top/sb_0__12_/chanx_right_out[26] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__12_/right_bottom_grid_pin_43_[0] -to fpga_top/sb_0__12_/chanx_right_out[26] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__12_/chany_bottom_in[2] -to fpga_top/sb_0__12_/chanx_right_out[26] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__12_/right_bottom_grid_pin_40_[0] -to fpga_top/sb_0__12_/chanx_right_out[27] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__12_/chany_bottom_in[1] -to fpga_top/sb_0__12_/chanx_right_out[27] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__12_/right_bottom_grid_pin_41_[0] -to fpga_top/sb_0__12_/chanx_right_out[28] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__12_/chany_bottom_in[0] -to fpga_top/sb_0__12_/chanx_right_out[28] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__12_/right_bottom_grid_pin_42_[0] -to fpga_top/sb_0__12_/chanx_right_out[29] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__12_/chany_bottom_in[29] -to fpga_top/sb_0__12_/chanx_right_out[29] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__12_/chanx_right_in[28] -to fpga_top/sb_0__12_/chany_bottom_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__12_/bottom_left_grid_pin_1_[0] -to fpga_top/sb_0__12_/chany_bottom_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__12_/chanx_right_in[27] -to fpga_top/sb_0__12_/chany_bottom_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__12_/chanx_right_in[26] -to fpga_top/sb_0__12_/chany_bottom_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__12_/chanx_right_in[25] -to fpga_top/sb_0__12_/chany_bottom_out[3] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__12_/bottom_left_grid_pin_1_[0] -to fpga_top/sb_0__12_/chany_bottom_out[3] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__12_/chanx_right_in[24] -to fpga_top/sb_0__12_/chany_bottom_out[4] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__12_/chanx_right_in[23] -to fpga_top/sb_0__12_/chany_bottom_out[5] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__12_/chanx_right_in[22] -to fpga_top/sb_0__12_/chany_bottom_out[6] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__12_/bottom_left_grid_pin_1_[0] -to fpga_top/sb_0__12_/chany_bottom_out[6] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__12_/chanx_right_in[21] -to fpga_top/sb_0__12_/chany_bottom_out[7] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__12_/chanx_right_in[20] -to fpga_top/sb_0__12_/chany_bottom_out[8] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__12_/chanx_right_in[19] -to fpga_top/sb_0__12_/chany_bottom_out[9] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__12_/chanx_right_in[18] -to fpga_top/sb_0__12_/chany_bottom_out[10] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__12_/chanx_right_in[17] -to fpga_top/sb_0__12_/chany_bottom_out[11] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__12_/chanx_right_in[16] -to fpga_top/sb_0__12_/chany_bottom_out[12] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__12_/chanx_right_in[15] -to fpga_top/sb_0__12_/chany_bottom_out[13] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__12_/chanx_right_in[14] -to fpga_top/sb_0__12_/chany_bottom_out[14] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__12_/bottom_left_grid_pin_1_[0] -to fpga_top/sb_0__12_/chany_bottom_out[14] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__12_/chanx_right_in[13] -to fpga_top/sb_0__12_/chany_bottom_out[15] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__12_/chanx_right_in[12] -to fpga_top/sb_0__12_/chany_bottom_out[16] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__12_/chanx_right_in[11] -to fpga_top/sb_0__12_/chany_bottom_out[17] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__12_/chanx_right_in[10] -to fpga_top/sb_0__12_/chany_bottom_out[18] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__12_/chanx_right_in[9] -to fpga_top/sb_0__12_/chany_bottom_out[19] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__12_/chanx_right_in[8] -to fpga_top/sb_0__12_/chany_bottom_out[20] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__12_/chanx_right_in[7] -to fpga_top/sb_0__12_/chany_bottom_out[21] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__12_/chanx_right_in[6] -to fpga_top/sb_0__12_/chany_bottom_out[22] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__12_/bottom_left_grid_pin_1_[0] -to fpga_top/sb_0__12_/chany_bottom_out[22] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__12_/chanx_right_in[5] -to fpga_top/sb_0__12_/chany_bottom_out[23] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__12_/chanx_right_in[4] -to fpga_top/sb_0__12_/chany_bottom_out[24] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__12_/chanx_right_in[3] -to fpga_top/sb_0__12_/chany_bottom_out[25] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__12_/chanx_right_in[2] -to fpga_top/sb_0__12_/chany_bottom_out[26] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__12_/chanx_right_in[1] -to fpga_top/sb_0__12_/chany_bottom_out[27] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__12_/chanx_right_in[0] -to fpga_top/sb_0__12_/chany_bottom_out[28] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__12_/chanx_right_in[29] -to fpga_top/sb_0__12_/chany_bottom_out[29] 6.020400151e-11 diff --git a/FPGA1212_RESET_HD_SKY_PNR/FPGA1212_RESET_HD_SKY_Verilog/SDC/sb_0__1_.sdc b/FPGA1212_RESET_HD_SKY_PNR/FPGA1212_RESET_HD_SKY_Verilog/SDC/sb_0__1_.sdc deleted file mode 100644 index 7751db3..0000000 --- a/FPGA1212_RESET_HD_SKY_PNR/FPGA1212_RESET_HD_SKY_Verilog/SDC/sb_0__1_.sdc +++ /dev/null @@ -1,217 +0,0 @@ -############################################# -# Synopsys Design Constraints (SDC) -# For FPGA fabric -# Description: Constrain timing of Switch Block sb_0__1_ for PnR -# Author: Xifan TANG -# Organization: University of Utah -# Date: Tue Dec 1 18:12:04 2020 -############################################# - -############################################# -# Define time unit -############################################# -set_units -time s - -set_max_delay -from fpga_core_uut/sb_0__1_/top_left_grid_pin_1_[0] -to fpga_top/sb_0__1_/chany_top_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[1] -to fpga_top/sb_0__1_/chany_top_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[12] -to fpga_top/sb_0__1_/chany_top_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[23] -to fpga_top/sb_0__1_/chany_top_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[3] -to fpga_top/sb_0__1_/chany_top_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[19] -to fpga_top/sb_0__1_/chany_top_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[2] -to fpga_top/sb_0__1_/chany_top_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[13] -to fpga_top/sb_0__1_/chany_top_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[24] -to fpga_top/sb_0__1_/chany_top_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[6] -to fpga_top/sb_0__1_/chany_top_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[20] -to fpga_top/sb_0__1_/chany_top_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[3] -to fpga_top/sb_0__1_/chany_top_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[14] -to fpga_top/sb_0__1_/chany_top_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[25] -to fpga_top/sb_0__1_/chany_top_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[7] -to fpga_top/sb_0__1_/chany_top_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[22] -to fpga_top/sb_0__1_/chany_top_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/top_left_grid_pin_1_[0] -to fpga_top/sb_0__1_/chany_top_out[3] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[4] -to fpga_top/sb_0__1_/chany_top_out[3] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[15] -to fpga_top/sb_0__1_/chany_top_out[3] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[26] -to fpga_top/sb_0__1_/chany_top_out[3] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[8] -to fpga_top/sb_0__1_/chany_top_out[3] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[23] -to fpga_top/sb_0__1_/chany_top_out[3] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[5] -to fpga_top/sb_0__1_/chany_top_out[5] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[16] -to fpga_top/sb_0__1_/chany_top_out[5] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[27] -to fpga_top/sb_0__1_/chany_top_out[5] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[10] -to fpga_top/sb_0__1_/chany_top_out[5] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[24] -to fpga_top/sb_0__1_/chany_top_out[5] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/top_left_grid_pin_1_[0] -to fpga_top/sb_0__1_/chany_top_out[6] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[6] -to fpga_top/sb_0__1_/chany_top_out[6] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[17] -to fpga_top/sb_0__1_/chany_top_out[6] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[28] -to fpga_top/sb_0__1_/chany_top_out[6] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[11] -to fpga_top/sb_0__1_/chany_top_out[6] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[26] -to fpga_top/sb_0__1_/chany_top_out[6] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[7] -to fpga_top/sb_0__1_/chany_top_out[10] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[18] -to fpga_top/sb_0__1_/chany_top_out[10] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[29] -to fpga_top/sb_0__1_/chany_top_out[10] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[12] -to fpga_top/sb_0__1_/chany_top_out[10] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[27] -to fpga_top/sb_0__1_/chany_top_out[10] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[8] -to fpga_top/sb_0__1_/chany_top_out[14] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[19] -to fpga_top/sb_0__1_/chany_top_out[14] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[14] -to fpga_top/sb_0__1_/chany_top_out[14] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[28] -to fpga_top/sb_0__1_/chany_top_out[14] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[9] -to fpga_top/sb_0__1_/chany_top_out[18] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[20] -to fpga_top/sb_0__1_/chany_top_out[18] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[15] -to fpga_top/sb_0__1_/chany_top_out[18] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[10] -to fpga_top/sb_0__1_/chany_top_out[22] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[21] -to fpga_top/sb_0__1_/chany_top_out[22] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[16] -to fpga_top/sb_0__1_/chany_top_out[22] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[0] -to fpga_top/sb_0__1_/chany_top_out[26] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[11] -to fpga_top/sb_0__1_/chany_top_out[26] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[22] -to fpga_top/sb_0__1_/chany_top_out[26] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[18] -to fpga_top/sb_0__1_/chany_top_out[26] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[3] -to fpga_top/sb_0__1_/chanx_right_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/right_bottom_grid_pin_36_[0] -to fpga_top/sb_0__1_/chanx_right_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/right_bottom_grid_pin_39_[0] -to fpga_top/sb_0__1_/chanx_right_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/right_bottom_grid_pin_42_[0] -to fpga_top/sb_0__1_/chanx_right_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[3] -to fpga_top/sb_0__1_/chanx_right_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[0] -to fpga_top/sb_0__1_/chanx_right_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[6] -to fpga_top/sb_0__1_/chanx_right_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/right_bottom_grid_pin_37_[0] -to fpga_top/sb_0__1_/chanx_right_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/right_bottom_grid_pin_40_[0] -to fpga_top/sb_0__1_/chanx_right_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/right_bottom_grid_pin_43_[0] -to fpga_top/sb_0__1_/chanx_right_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[6] -to fpga_top/sb_0__1_/chanx_right_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[1] -to fpga_top/sb_0__1_/chanx_right_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[7] -to fpga_top/sb_0__1_/chanx_right_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/right_bottom_grid_pin_38_[0] -to fpga_top/sb_0__1_/chanx_right_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/right_bottom_grid_pin_41_[0] -to fpga_top/sb_0__1_/chanx_right_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[7] -to fpga_top/sb_0__1_/chanx_right_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[2] -to fpga_top/sb_0__1_/chanx_right_out[3] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[8] -to fpga_top/sb_0__1_/chanx_right_out[3] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/right_bottom_grid_pin_36_[0] -to fpga_top/sb_0__1_/chanx_right_out[3] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/right_bottom_grid_pin_39_[0] -to fpga_top/sb_0__1_/chanx_right_out[3] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/right_bottom_grid_pin_42_[0] -to fpga_top/sb_0__1_/chanx_right_out[3] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[8] -to fpga_top/sb_0__1_/chanx_right_out[3] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[4] -to fpga_top/sb_0__1_/chanx_right_out[4] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[10] -to fpga_top/sb_0__1_/chanx_right_out[4] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/right_bottom_grid_pin_37_[0] -to fpga_top/sb_0__1_/chanx_right_out[4] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/right_bottom_grid_pin_40_[0] -to fpga_top/sb_0__1_/chanx_right_out[4] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/right_bottom_grid_pin_43_[0] -to fpga_top/sb_0__1_/chanx_right_out[4] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[10] -to fpga_top/sb_0__1_/chanx_right_out[4] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[5] -to fpga_top/sb_0__1_/chanx_right_out[5] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[11] -to fpga_top/sb_0__1_/chanx_right_out[5] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/right_bottom_grid_pin_38_[0] -to fpga_top/sb_0__1_/chanx_right_out[5] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/right_bottom_grid_pin_41_[0] -to fpga_top/sb_0__1_/chanx_right_out[5] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[11] -to fpga_top/sb_0__1_/chanx_right_out[5] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[9] -to fpga_top/sb_0__1_/chanx_right_out[6] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[12] -to fpga_top/sb_0__1_/chanx_right_out[6] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/right_bottom_grid_pin_36_[0] -to fpga_top/sb_0__1_/chanx_right_out[6] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[12] -to fpga_top/sb_0__1_/chanx_right_out[6] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[13] -to fpga_top/sb_0__1_/chanx_right_out[7] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[14] -to fpga_top/sb_0__1_/chanx_right_out[7] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/right_bottom_grid_pin_37_[0] -to fpga_top/sb_0__1_/chanx_right_out[7] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[14] -to fpga_top/sb_0__1_/chanx_right_out[7] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[15] -to fpga_top/sb_0__1_/chanx_right_out[8] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[17] -to fpga_top/sb_0__1_/chanx_right_out[8] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/right_bottom_grid_pin_38_[0] -to fpga_top/sb_0__1_/chanx_right_out[8] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[15] -to fpga_top/sb_0__1_/chanx_right_out[8] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[16] -to fpga_top/sb_0__1_/chanx_right_out[9] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[21] -to fpga_top/sb_0__1_/chanx_right_out[9] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/right_bottom_grid_pin_39_[0] -to fpga_top/sb_0__1_/chanx_right_out[9] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[16] -to fpga_top/sb_0__1_/chanx_right_out[9] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[18] -to fpga_top/sb_0__1_/chanx_right_out[10] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[25] -to fpga_top/sb_0__1_/chanx_right_out[10] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/right_bottom_grid_pin_40_[0] -to fpga_top/sb_0__1_/chanx_right_out[10] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[18] -to fpga_top/sb_0__1_/chanx_right_out[10] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[19] -to fpga_top/sb_0__1_/chanx_right_out[11] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[29] -to fpga_top/sb_0__1_/chanx_right_out[11] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/right_bottom_grid_pin_41_[0] -to fpga_top/sb_0__1_/chanx_right_out[11] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[19] -to fpga_top/sb_0__1_/chanx_right_out[11] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[20] -to fpga_top/sb_0__1_/chanx_right_out[12] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/right_bottom_grid_pin_42_[0] -to fpga_top/sb_0__1_/chanx_right_out[12] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[20] -to fpga_top/sb_0__1_/chanx_right_out[12] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[22] -to fpga_top/sb_0__1_/chanx_right_out[13] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/right_bottom_grid_pin_43_[0] -to fpga_top/sb_0__1_/chanx_right_out[13] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[22] -to fpga_top/sb_0__1_/chanx_right_out[13] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[23] -to fpga_top/sb_0__1_/chanx_right_out[14] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/right_bottom_grid_pin_36_[0] -to fpga_top/sb_0__1_/chanx_right_out[14] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[23] -to fpga_top/sb_0__1_/chanx_right_out[14] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[24] -to fpga_top/sb_0__1_/chanx_right_out[15] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/right_bottom_grid_pin_37_[0] -to fpga_top/sb_0__1_/chanx_right_out[15] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[24] -to fpga_top/sb_0__1_/chanx_right_out[15] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[26] -to fpga_top/sb_0__1_/chanx_right_out[16] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/right_bottom_grid_pin_38_[0] -to fpga_top/sb_0__1_/chanx_right_out[16] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[26] -to fpga_top/sb_0__1_/chanx_right_out[16] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[27] -to fpga_top/sb_0__1_/chanx_right_out[17] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/right_bottom_grid_pin_39_[0] -to fpga_top/sb_0__1_/chanx_right_out[17] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[27] -to fpga_top/sb_0__1_/chanx_right_out[17] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[28] -to fpga_top/sb_0__1_/chanx_right_out[18] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/right_bottom_grid_pin_40_[0] -to fpga_top/sb_0__1_/chanx_right_out[18] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[28] -to fpga_top/sb_0__1_/chanx_right_out[18] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[29] -to fpga_top/sb_0__1_/chanx_right_out[18] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/right_bottom_grid_pin_41_[0] -to fpga_top/sb_0__1_/chanx_right_out[19] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[25] -to fpga_top/sb_0__1_/chanx_right_out[19] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/right_bottom_grid_pin_42_[0] -to fpga_top/sb_0__1_/chanx_right_out[20] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[21] -to fpga_top/sb_0__1_/chanx_right_out[20] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[17] -to fpga_top/sb_0__1_/chanx_right_out[21] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/right_bottom_grid_pin_36_[0] -to fpga_top/sb_0__1_/chanx_right_out[22] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[13] -to fpga_top/sb_0__1_/chanx_right_out[22] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/right_bottom_grid_pin_37_[0] -to fpga_top/sb_0__1_/chanx_right_out[23] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[9] -to fpga_top/sb_0__1_/chanx_right_out[23] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/right_bottom_grid_pin_38_[0] -to fpga_top/sb_0__1_/chanx_right_out[24] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[5] -to fpga_top/sb_0__1_/chanx_right_out[24] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/right_bottom_grid_pin_39_[0] -to fpga_top/sb_0__1_/chanx_right_out[25] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/right_bottom_grid_pin_43_[0] -to fpga_top/sb_0__1_/chanx_right_out[25] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[4] -to fpga_top/sb_0__1_/chanx_right_out[25] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/right_bottom_grid_pin_40_[0] -to fpga_top/sb_0__1_/chanx_right_out[26] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[2] -to fpga_top/sb_0__1_/chanx_right_out[26] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/right_bottom_grid_pin_41_[0] -to fpga_top/sb_0__1_/chanx_right_out[27] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[1] -to fpga_top/sb_0__1_/chanx_right_out[27] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/right_bottom_grid_pin_42_[0] -to fpga_top/sb_0__1_/chanx_right_out[28] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[0] -to fpga_top/sb_0__1_/chanx_right_out[28] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[3] -to fpga_top/sb_0__1_/chany_bottom_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[19] -to fpga_top/sb_0__1_/chany_bottom_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[9] -to fpga_top/sb_0__1_/chany_bottom_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[20] -to fpga_top/sb_0__1_/chany_bottom_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/bottom_left_grid_pin_1_[0] -to fpga_top/sb_0__1_/chany_bottom_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[6] -to fpga_top/sb_0__1_/chany_bottom_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[20] -to fpga_top/sb_0__1_/chany_bottom_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[8] -to fpga_top/sb_0__1_/chany_bottom_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[19] -to fpga_top/sb_0__1_/chany_bottom_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[7] -to fpga_top/sb_0__1_/chany_bottom_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[22] -to fpga_top/sb_0__1_/chany_bottom_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[7] -to fpga_top/sb_0__1_/chany_bottom_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[18] -to fpga_top/sb_0__1_/chany_bottom_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[29] -to fpga_top/sb_0__1_/chany_bottom_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[8] -to fpga_top/sb_0__1_/chany_bottom_out[3] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[23] -to fpga_top/sb_0__1_/chany_bottom_out[3] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[6] -to fpga_top/sb_0__1_/chany_bottom_out[3] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[17] -to fpga_top/sb_0__1_/chany_bottom_out[3] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[28] -to fpga_top/sb_0__1_/chany_bottom_out[3] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/bottom_left_grid_pin_1_[0] -to fpga_top/sb_0__1_/chany_bottom_out[3] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[10] -to fpga_top/sb_0__1_/chany_bottom_out[5] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[24] -to fpga_top/sb_0__1_/chany_bottom_out[5] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[5] -to fpga_top/sb_0__1_/chany_bottom_out[5] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[16] -to fpga_top/sb_0__1_/chany_bottom_out[5] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[27] -to fpga_top/sb_0__1_/chany_bottom_out[5] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[11] -to fpga_top/sb_0__1_/chany_bottom_out[6] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[26] -to fpga_top/sb_0__1_/chany_bottom_out[6] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[4] -to fpga_top/sb_0__1_/chany_bottom_out[6] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[15] -to fpga_top/sb_0__1_/chany_bottom_out[6] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[26] -to fpga_top/sb_0__1_/chany_bottom_out[6] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/bottom_left_grid_pin_1_[0] -to fpga_top/sb_0__1_/chany_bottom_out[6] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[12] -to fpga_top/sb_0__1_/chany_bottom_out[10] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[27] -to fpga_top/sb_0__1_/chany_bottom_out[10] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[3] -to fpga_top/sb_0__1_/chany_bottom_out[10] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[14] -to fpga_top/sb_0__1_/chany_bottom_out[10] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[25] -to fpga_top/sb_0__1_/chany_bottom_out[10] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[14] -to fpga_top/sb_0__1_/chany_bottom_out[14] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[28] -to fpga_top/sb_0__1_/chany_bottom_out[14] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[2] -to fpga_top/sb_0__1_/chany_bottom_out[14] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[13] -to fpga_top/sb_0__1_/chany_bottom_out[14] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[24] -to fpga_top/sb_0__1_/chany_bottom_out[14] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[15] -to fpga_top/sb_0__1_/chany_bottom_out[18] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[1] -to fpga_top/sb_0__1_/chany_bottom_out[18] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[12] -to fpga_top/sb_0__1_/chany_bottom_out[18] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[23] -to fpga_top/sb_0__1_/chany_bottom_out[18] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[16] -to fpga_top/sb_0__1_/chany_bottom_out[22] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[0] -to fpga_top/sb_0__1_/chany_bottom_out[22] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[11] -to fpga_top/sb_0__1_/chany_bottom_out[22] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[22] -to fpga_top/sb_0__1_/chany_bottom_out[22] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[18] -to fpga_top/sb_0__1_/chany_bottom_out[26] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[10] -to fpga_top/sb_0__1_/chany_bottom_out[26] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[21] -to fpga_top/sb_0__1_/chany_bottom_out[26] 6.020400151e-11 diff --git a/FPGA1212_RESET_HD_SKY_PNR/FPGA1212_RESET_HD_SKY_Verilog/SDC/sb_12__0_.sdc b/FPGA1212_RESET_HD_SKY_PNR/FPGA1212_RESET_HD_SKY_Verilog/SDC/sb_12__0_.sdc deleted file mode 100644 index 8933e8f..0000000 --- a/FPGA1212_RESET_HD_SKY_PNR/FPGA1212_RESET_HD_SKY_Verilog/SDC/sb_12__0_.sdc +++ /dev/null @@ -1,156 +0,0 @@ -############################################# -# Synopsys Design Constraints (SDC) -# For FPGA fabric -# Description: Constrain timing of Switch Block sb_12__0_ for PnR -# Author: Xifan TANG -# Organization: University of Utah -# Date: Tue Dec 1 18:12:04 2020 -############################################# - -############################################# -# Define time unit -############################################# -set_units -time s - -set_max_delay -from fpga_core_uut/sb_12__0_/top_left_grid_pin_44_[0] -to fpga_top/sb_12__0_/chany_top_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__0_/top_left_grid_pin_47_[0] -to fpga_top/sb_12__0_/chany_top_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__0_/top_left_grid_pin_50_[0] -to fpga_top/sb_12__0_/chany_top_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__0_/chanx_left_in[0] -to fpga_top/sb_12__0_/chany_top_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__0_/top_left_grid_pin_45_[0] -to fpga_top/sb_12__0_/chany_top_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__0_/top_left_grid_pin_48_[0] -to fpga_top/sb_12__0_/chany_top_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__0_/top_left_grid_pin_51_[0] -to fpga_top/sb_12__0_/chany_top_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__0_/chanx_left_in[29] -to fpga_top/sb_12__0_/chany_top_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__0_/top_left_grid_pin_46_[0] -to fpga_top/sb_12__0_/chany_top_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__0_/top_left_grid_pin_49_[0] -to fpga_top/sb_12__0_/chany_top_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__0_/top_right_grid_pin_1_[0] -to fpga_top/sb_12__0_/chany_top_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__0_/chanx_left_in[28] -to fpga_top/sb_12__0_/chany_top_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__0_/top_left_grid_pin_44_[0] -to fpga_top/sb_12__0_/chany_top_out[3] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__0_/top_left_grid_pin_47_[0] -to fpga_top/sb_12__0_/chany_top_out[3] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__0_/top_left_grid_pin_50_[0] -to fpga_top/sb_12__0_/chany_top_out[3] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__0_/chanx_left_in[27] -to fpga_top/sb_12__0_/chany_top_out[3] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__0_/top_left_grid_pin_45_[0] -to fpga_top/sb_12__0_/chany_top_out[4] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__0_/top_left_grid_pin_48_[0] -to fpga_top/sb_12__0_/chany_top_out[4] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__0_/top_left_grid_pin_51_[0] -to fpga_top/sb_12__0_/chany_top_out[4] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__0_/chanx_left_in[26] -to fpga_top/sb_12__0_/chany_top_out[4] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__0_/top_left_grid_pin_46_[0] -to fpga_top/sb_12__0_/chany_top_out[5] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__0_/top_left_grid_pin_49_[0] -to fpga_top/sb_12__0_/chany_top_out[5] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__0_/top_right_grid_pin_1_[0] -to fpga_top/sb_12__0_/chany_top_out[5] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__0_/chanx_left_in[25] -to fpga_top/sb_12__0_/chany_top_out[5] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__0_/top_left_grid_pin_44_[0] -to fpga_top/sb_12__0_/chany_top_out[6] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__0_/top_right_grid_pin_1_[0] -to fpga_top/sb_12__0_/chany_top_out[6] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__0_/chanx_left_in[24] -to fpga_top/sb_12__0_/chany_top_out[6] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__0_/top_left_grid_pin_45_[0] -to fpga_top/sb_12__0_/chany_top_out[7] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__0_/chanx_left_in[23] -to fpga_top/sb_12__0_/chany_top_out[7] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__0_/top_left_grid_pin_46_[0] -to fpga_top/sb_12__0_/chany_top_out[8] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__0_/chanx_left_in[22] -to fpga_top/sb_12__0_/chany_top_out[8] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__0_/top_left_grid_pin_47_[0] -to fpga_top/sb_12__0_/chany_top_out[9] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__0_/chanx_left_in[21] -to fpga_top/sb_12__0_/chany_top_out[9] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__0_/top_left_grid_pin_48_[0] -to fpga_top/sb_12__0_/chany_top_out[10] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__0_/chanx_left_in[20] -to fpga_top/sb_12__0_/chany_top_out[10] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__0_/top_left_grid_pin_49_[0] -to fpga_top/sb_12__0_/chany_top_out[11] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__0_/chanx_left_in[19] -to fpga_top/sb_12__0_/chany_top_out[11] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__0_/top_left_grid_pin_50_[0] -to fpga_top/sb_12__0_/chany_top_out[12] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__0_/chanx_left_in[18] -to fpga_top/sb_12__0_/chany_top_out[12] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__0_/top_left_grid_pin_51_[0] -to fpga_top/sb_12__0_/chany_top_out[13] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__0_/chanx_left_in[17] -to fpga_top/sb_12__0_/chany_top_out[13] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__0_/top_right_grid_pin_1_[0] -to fpga_top/sb_12__0_/chany_top_out[14] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__0_/chanx_left_in[16] -to fpga_top/sb_12__0_/chany_top_out[14] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__0_/chanx_left_in[15] -to fpga_top/sb_12__0_/chany_top_out[15] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__0_/chanx_left_in[14] -to fpga_top/sb_12__0_/chany_top_out[16] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__0_/chanx_left_in[13] -to fpga_top/sb_12__0_/chany_top_out[17] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__0_/top_left_grid_pin_44_[0] -to fpga_top/sb_12__0_/chany_top_out[18] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__0_/chanx_left_in[12] -to fpga_top/sb_12__0_/chany_top_out[18] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__0_/top_left_grid_pin_45_[0] -to fpga_top/sb_12__0_/chany_top_out[19] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__0_/chanx_left_in[11] -to fpga_top/sb_12__0_/chany_top_out[19] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__0_/top_left_grid_pin_46_[0] -to fpga_top/sb_12__0_/chany_top_out[20] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__0_/chanx_left_in[10] -to fpga_top/sb_12__0_/chany_top_out[20] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__0_/top_left_grid_pin_47_[0] -to fpga_top/sb_12__0_/chany_top_out[21] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__0_/chanx_left_in[9] -to fpga_top/sb_12__0_/chany_top_out[21] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__0_/top_left_grid_pin_48_[0] -to fpga_top/sb_12__0_/chany_top_out[22] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__0_/top_right_grid_pin_1_[0] -to fpga_top/sb_12__0_/chany_top_out[22] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__0_/chanx_left_in[8] -to fpga_top/sb_12__0_/chany_top_out[22] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__0_/top_left_grid_pin_49_[0] -to fpga_top/sb_12__0_/chany_top_out[23] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__0_/chanx_left_in[7] -to fpga_top/sb_12__0_/chany_top_out[23] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__0_/top_left_grid_pin_50_[0] -to fpga_top/sb_12__0_/chany_top_out[24] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__0_/chanx_left_in[6] -to fpga_top/sb_12__0_/chany_top_out[24] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__0_/top_left_grid_pin_51_[0] -to fpga_top/sb_12__0_/chany_top_out[25] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__0_/chanx_left_in[5] -to fpga_top/sb_12__0_/chany_top_out[25] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__0_/chanx_left_in[4] -to fpga_top/sb_12__0_/chany_top_out[26] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__0_/chanx_left_in[3] -to fpga_top/sb_12__0_/chany_top_out[27] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__0_/chanx_left_in[2] -to fpga_top/sb_12__0_/chany_top_out[28] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__0_/chanx_left_in[1] -to fpga_top/sb_12__0_/chany_top_out[29] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__0_/chany_top_in[0] -to fpga_top/sb_12__0_/chanx_left_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_1_[0] -to fpga_top/sb_12__0_/chanx_left_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_7_[0] -to fpga_top/sb_12__0_/chanx_left_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_13_[0] -to fpga_top/sb_12__0_/chanx_left_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__0_/chany_top_in[29] -to fpga_top/sb_12__0_/chanx_left_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_3_[0] -to fpga_top/sb_12__0_/chanx_left_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_9_[0] -to fpga_top/sb_12__0_/chanx_left_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_15_[0] -to fpga_top/sb_12__0_/chanx_left_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__0_/chany_top_in[28] -to fpga_top/sb_12__0_/chanx_left_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_5_[0] -to fpga_top/sb_12__0_/chanx_left_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_11_[0] -to fpga_top/sb_12__0_/chanx_left_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_17_[0] -to fpga_top/sb_12__0_/chanx_left_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__0_/chany_top_in[27] -to fpga_top/sb_12__0_/chanx_left_out[3] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_1_[0] -to fpga_top/sb_12__0_/chanx_left_out[3] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_7_[0] -to fpga_top/sb_12__0_/chanx_left_out[3] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_13_[0] -to fpga_top/sb_12__0_/chanx_left_out[3] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__0_/chany_top_in[26] -to fpga_top/sb_12__0_/chanx_left_out[4] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_3_[0] -to fpga_top/sb_12__0_/chanx_left_out[4] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_9_[0] -to fpga_top/sb_12__0_/chanx_left_out[4] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_15_[0] -to fpga_top/sb_12__0_/chanx_left_out[4] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__0_/chany_top_in[25] -to fpga_top/sb_12__0_/chanx_left_out[5] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_5_[0] -to fpga_top/sb_12__0_/chanx_left_out[5] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_11_[0] -to fpga_top/sb_12__0_/chanx_left_out[5] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_17_[0] -to fpga_top/sb_12__0_/chanx_left_out[5] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__0_/chany_top_in[24] -to fpga_top/sb_12__0_/chanx_left_out[6] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_1_[0] -to fpga_top/sb_12__0_/chanx_left_out[6] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_17_[0] -to fpga_top/sb_12__0_/chanx_left_out[6] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__0_/chany_top_in[23] -to fpga_top/sb_12__0_/chanx_left_out[7] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_3_[0] -to fpga_top/sb_12__0_/chanx_left_out[7] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__0_/chany_top_in[22] -to fpga_top/sb_12__0_/chanx_left_out[8] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_5_[0] -to fpga_top/sb_12__0_/chanx_left_out[8] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__0_/chany_top_in[21] -to fpga_top/sb_12__0_/chanx_left_out[9] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_7_[0] -to fpga_top/sb_12__0_/chanx_left_out[9] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__0_/chany_top_in[20] -to fpga_top/sb_12__0_/chanx_left_out[10] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_9_[0] -to fpga_top/sb_12__0_/chanx_left_out[10] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__0_/chany_top_in[19] -to fpga_top/sb_12__0_/chanx_left_out[11] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_11_[0] -to fpga_top/sb_12__0_/chanx_left_out[11] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__0_/chany_top_in[18] -to fpga_top/sb_12__0_/chanx_left_out[12] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_13_[0] -to fpga_top/sb_12__0_/chanx_left_out[12] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__0_/chany_top_in[17] -to fpga_top/sb_12__0_/chanx_left_out[13] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_15_[0] -to fpga_top/sb_12__0_/chanx_left_out[13] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__0_/chany_top_in[16] -to fpga_top/sb_12__0_/chanx_left_out[14] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_1_[0] -to fpga_top/sb_12__0_/chanx_left_out[14] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_17_[0] -to fpga_top/sb_12__0_/chanx_left_out[14] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__0_/chany_top_in[15] -to fpga_top/sb_12__0_/chanx_left_out[15] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_3_[0] -to fpga_top/sb_12__0_/chanx_left_out[15] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__0_/chany_top_in[14] -to fpga_top/sb_12__0_/chanx_left_out[16] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_5_[0] -to fpga_top/sb_12__0_/chanx_left_out[16] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__0_/chany_top_in[13] -to fpga_top/sb_12__0_/chanx_left_out[17] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_7_[0] -to fpga_top/sb_12__0_/chanx_left_out[17] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__0_/chany_top_in[12] -to fpga_top/sb_12__0_/chanx_left_out[18] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_9_[0] -to fpga_top/sb_12__0_/chanx_left_out[18] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__0_/chany_top_in[11] -to fpga_top/sb_12__0_/chanx_left_out[19] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_11_[0] -to fpga_top/sb_12__0_/chanx_left_out[19] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__0_/chany_top_in[10] -to fpga_top/sb_12__0_/chanx_left_out[20] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_13_[0] -to fpga_top/sb_12__0_/chanx_left_out[20] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__0_/chany_top_in[9] -to fpga_top/sb_12__0_/chanx_left_out[21] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_15_[0] -to fpga_top/sb_12__0_/chanx_left_out[21] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__0_/chany_top_in[8] -to fpga_top/sb_12__0_/chanx_left_out[22] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_1_[0] -to fpga_top/sb_12__0_/chanx_left_out[22] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_17_[0] -to fpga_top/sb_12__0_/chanx_left_out[22] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__0_/chany_top_in[7] -to fpga_top/sb_12__0_/chanx_left_out[23] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_3_[0] -to fpga_top/sb_12__0_/chanx_left_out[23] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__0_/chany_top_in[6] -to fpga_top/sb_12__0_/chanx_left_out[24] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_5_[0] -to fpga_top/sb_12__0_/chanx_left_out[24] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__0_/chany_top_in[5] -to fpga_top/sb_12__0_/chanx_left_out[25] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_7_[0] -to fpga_top/sb_12__0_/chanx_left_out[25] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__0_/chany_top_in[4] -to fpga_top/sb_12__0_/chanx_left_out[26] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_9_[0] -to fpga_top/sb_12__0_/chanx_left_out[26] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__0_/chany_top_in[3] -to fpga_top/sb_12__0_/chanx_left_out[27] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_11_[0] -to fpga_top/sb_12__0_/chanx_left_out[27] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__0_/chany_top_in[2] -to fpga_top/sb_12__0_/chanx_left_out[28] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_13_[0] -to fpga_top/sb_12__0_/chanx_left_out[28] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__0_/chany_top_in[1] -to fpga_top/sb_12__0_/chanx_left_out[29] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_15_[0] -to fpga_top/sb_12__0_/chanx_left_out[29] 6.020400151e-11 diff --git a/FPGA1212_RESET_HD_SKY_PNR/FPGA1212_RESET_HD_SKY_Verilog/SDC/sb_12__12_.sdc b/FPGA1212_RESET_HD_SKY_PNR/FPGA1212_RESET_HD_SKY_Verilog/SDC/sb_12__12_.sdc deleted file mode 100644 index bf48693..0000000 --- a/FPGA1212_RESET_HD_SKY_PNR/FPGA1212_RESET_HD_SKY_Verilog/SDC/sb_12__12_.sdc +++ /dev/null @@ -1,155 +0,0 @@ -############################################# -# Synopsys Design Constraints (SDC) -# For FPGA fabric -# Description: Constrain timing of Switch Block sb_12__12_ for PnR -# Author: Xifan TANG -# Organization: University of Utah -# Date: Tue Dec 1 18:12:04 2020 -############################################# - -############################################# -# Define time unit -############################################# -set_units -time s - -set_max_delay -from fpga_core_uut/sb_12__12_/bottom_right_grid_pin_1_[0] -to fpga_top/sb_12__12_/chany_bottom_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__12_/bottom_left_grid_pin_46_[0] -to fpga_top/sb_12__12_/chany_bottom_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__12_/bottom_left_grid_pin_49_[0] -to fpga_top/sb_12__12_/chany_bottom_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__12_/chanx_left_in[1] -to fpga_top/sb_12__12_/chany_bottom_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__12_/bottom_left_grid_pin_44_[0] -to fpga_top/sb_12__12_/chany_bottom_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__12_/bottom_left_grid_pin_47_[0] -to fpga_top/sb_12__12_/chany_bottom_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__12_/bottom_left_grid_pin_50_[0] -to fpga_top/sb_12__12_/chany_bottom_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__12_/chanx_left_in[2] -to fpga_top/sb_12__12_/chany_bottom_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__12_/bottom_left_grid_pin_45_[0] -to fpga_top/sb_12__12_/chany_bottom_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__12_/bottom_left_grid_pin_48_[0] -to fpga_top/sb_12__12_/chany_bottom_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__12_/bottom_left_grid_pin_51_[0] -to fpga_top/sb_12__12_/chany_bottom_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__12_/chanx_left_in[3] -to fpga_top/sb_12__12_/chany_bottom_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__12_/bottom_right_grid_pin_1_[0] -to fpga_top/sb_12__12_/chany_bottom_out[3] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__12_/bottom_left_grid_pin_46_[0] -to fpga_top/sb_12__12_/chany_bottom_out[3] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__12_/bottom_left_grid_pin_49_[0] -to fpga_top/sb_12__12_/chany_bottom_out[3] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__12_/chanx_left_in[4] -to fpga_top/sb_12__12_/chany_bottom_out[3] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__12_/bottom_left_grid_pin_44_[0] -to fpga_top/sb_12__12_/chany_bottom_out[4] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__12_/bottom_left_grid_pin_47_[0] -to fpga_top/sb_12__12_/chany_bottom_out[4] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__12_/bottom_left_grid_pin_50_[0] -to fpga_top/sb_12__12_/chany_bottom_out[4] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__12_/chanx_left_in[5] -to fpga_top/sb_12__12_/chany_bottom_out[4] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__12_/bottom_left_grid_pin_45_[0] -to fpga_top/sb_12__12_/chany_bottom_out[5] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__12_/bottom_left_grid_pin_48_[0] -to fpga_top/sb_12__12_/chany_bottom_out[5] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__12_/bottom_left_grid_pin_51_[0] -to fpga_top/sb_12__12_/chany_bottom_out[5] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__12_/chanx_left_in[6] -to fpga_top/sb_12__12_/chany_bottom_out[5] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__12_/bottom_right_grid_pin_1_[0] -to fpga_top/sb_12__12_/chany_bottom_out[6] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__12_/chanx_left_in[7] -to fpga_top/sb_12__12_/chany_bottom_out[6] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__12_/bottom_left_grid_pin_44_[0] -to fpga_top/sb_12__12_/chany_bottom_out[7] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__12_/chanx_left_in[8] -to fpga_top/sb_12__12_/chany_bottom_out[7] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__12_/bottom_left_grid_pin_45_[0] -to fpga_top/sb_12__12_/chany_bottom_out[8] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__12_/chanx_left_in[9] -to fpga_top/sb_12__12_/chany_bottom_out[8] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__12_/bottom_left_grid_pin_46_[0] -to fpga_top/sb_12__12_/chany_bottom_out[9] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__12_/chanx_left_in[10] -to fpga_top/sb_12__12_/chany_bottom_out[9] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__12_/bottom_left_grid_pin_47_[0] -to fpga_top/sb_12__12_/chany_bottom_out[10] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__12_/chanx_left_in[11] -to fpga_top/sb_12__12_/chany_bottom_out[10] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__12_/bottom_left_grid_pin_48_[0] -to fpga_top/sb_12__12_/chany_bottom_out[11] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__12_/chanx_left_in[12] -to fpga_top/sb_12__12_/chany_bottom_out[11] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__12_/bottom_left_grid_pin_49_[0] -to fpga_top/sb_12__12_/chany_bottom_out[12] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__12_/chanx_left_in[13] -to fpga_top/sb_12__12_/chany_bottom_out[12] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__12_/bottom_left_grid_pin_50_[0] -to fpga_top/sb_12__12_/chany_bottom_out[13] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__12_/chanx_left_in[14] -to fpga_top/sb_12__12_/chany_bottom_out[13] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__12_/bottom_right_grid_pin_1_[0] -to fpga_top/sb_12__12_/chany_bottom_out[14] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__12_/bottom_left_grid_pin_51_[0] -to fpga_top/sb_12__12_/chany_bottom_out[14] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__12_/chanx_left_in[15] -to fpga_top/sb_12__12_/chany_bottom_out[14] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__12_/chanx_left_in[16] -to fpga_top/sb_12__12_/chany_bottom_out[15] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__12_/chanx_left_in[17] -to fpga_top/sb_12__12_/chany_bottom_out[16] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__12_/chanx_left_in[18] -to fpga_top/sb_12__12_/chany_bottom_out[17] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__12_/chanx_left_in[19] -to fpga_top/sb_12__12_/chany_bottom_out[18] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__12_/bottom_left_grid_pin_44_[0] -to fpga_top/sb_12__12_/chany_bottom_out[19] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__12_/chanx_left_in[20] -to fpga_top/sb_12__12_/chany_bottom_out[19] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__12_/bottom_left_grid_pin_45_[0] -to fpga_top/sb_12__12_/chany_bottom_out[20] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__12_/chanx_left_in[21] -to fpga_top/sb_12__12_/chany_bottom_out[20] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__12_/bottom_left_grid_pin_46_[0] -to fpga_top/sb_12__12_/chany_bottom_out[21] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__12_/chanx_left_in[22] -to fpga_top/sb_12__12_/chany_bottom_out[21] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__12_/bottom_right_grid_pin_1_[0] -to fpga_top/sb_12__12_/chany_bottom_out[22] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__12_/bottom_left_grid_pin_47_[0] -to fpga_top/sb_12__12_/chany_bottom_out[22] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__12_/chanx_left_in[23] -to fpga_top/sb_12__12_/chany_bottom_out[22] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__12_/bottom_left_grid_pin_48_[0] -to fpga_top/sb_12__12_/chany_bottom_out[23] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__12_/chanx_left_in[24] -to fpga_top/sb_12__12_/chany_bottom_out[23] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__12_/bottom_left_grid_pin_49_[0] -to fpga_top/sb_12__12_/chany_bottom_out[24] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__12_/chanx_left_in[25] -to fpga_top/sb_12__12_/chany_bottom_out[24] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__12_/bottom_left_grid_pin_50_[0] -to fpga_top/sb_12__12_/chany_bottom_out[25] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__12_/chanx_left_in[26] -to fpga_top/sb_12__12_/chany_bottom_out[25] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__12_/bottom_left_grid_pin_51_[0] -to fpga_top/sb_12__12_/chany_bottom_out[26] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__12_/chanx_left_in[27] -to fpga_top/sb_12__12_/chany_bottom_out[26] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__12_/chanx_left_in[28] -to fpga_top/sb_12__12_/chany_bottom_out[27] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__12_/chanx_left_in[29] -to fpga_top/sb_12__12_/chany_bottom_out[28] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__12_/chanx_left_in[0] -to fpga_top/sb_12__12_/chany_bottom_out[29] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__12_/chany_bottom_in[29] -to fpga_top/sb_12__12_/chanx_left_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__12_/left_top_grid_pin_1_[0] -to fpga_top/sb_12__12_/chanx_left_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__12_/left_bottom_grid_pin_38_[0] -to fpga_top/sb_12__12_/chanx_left_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__12_/left_bottom_grid_pin_41_[0] -to fpga_top/sb_12__12_/chanx_left_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__12_/chany_bottom_in[0] -to fpga_top/sb_12__12_/chanx_left_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__12_/left_bottom_grid_pin_36_[0] -to fpga_top/sb_12__12_/chanx_left_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__12_/left_bottom_grid_pin_39_[0] -to fpga_top/sb_12__12_/chanx_left_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__12_/left_bottom_grid_pin_42_[0] -to fpga_top/sb_12__12_/chanx_left_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__12_/chany_bottom_in[1] -to fpga_top/sb_12__12_/chanx_left_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__12_/left_bottom_grid_pin_37_[0] -to fpga_top/sb_12__12_/chanx_left_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__12_/left_bottom_grid_pin_40_[0] -to fpga_top/sb_12__12_/chanx_left_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__12_/left_bottom_grid_pin_43_[0] -to fpga_top/sb_12__12_/chanx_left_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__12_/chany_bottom_in[2] -to fpga_top/sb_12__12_/chanx_left_out[3] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__12_/left_top_grid_pin_1_[0] -to fpga_top/sb_12__12_/chanx_left_out[3] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__12_/left_bottom_grid_pin_38_[0] -to fpga_top/sb_12__12_/chanx_left_out[3] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__12_/left_bottom_grid_pin_41_[0] -to fpga_top/sb_12__12_/chanx_left_out[3] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__12_/chany_bottom_in[3] -to fpga_top/sb_12__12_/chanx_left_out[4] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__12_/left_bottom_grid_pin_36_[0] -to fpga_top/sb_12__12_/chanx_left_out[4] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__12_/left_bottom_grid_pin_39_[0] -to fpga_top/sb_12__12_/chanx_left_out[4] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__12_/left_bottom_grid_pin_42_[0] -to fpga_top/sb_12__12_/chanx_left_out[4] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__12_/chany_bottom_in[4] -to fpga_top/sb_12__12_/chanx_left_out[5] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__12_/left_bottom_grid_pin_37_[0] -to fpga_top/sb_12__12_/chanx_left_out[5] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__12_/left_bottom_grid_pin_40_[0] -to fpga_top/sb_12__12_/chanx_left_out[5] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__12_/left_bottom_grid_pin_43_[0] -to fpga_top/sb_12__12_/chanx_left_out[5] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__12_/chany_bottom_in[5] -to fpga_top/sb_12__12_/chanx_left_out[6] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__12_/left_top_grid_pin_1_[0] -to fpga_top/sb_12__12_/chanx_left_out[6] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__12_/chany_bottom_in[6] -to fpga_top/sb_12__12_/chanx_left_out[7] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__12_/left_bottom_grid_pin_36_[0] -to fpga_top/sb_12__12_/chanx_left_out[7] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__12_/chany_bottom_in[7] -to fpga_top/sb_12__12_/chanx_left_out[8] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__12_/left_bottom_grid_pin_37_[0] -to fpga_top/sb_12__12_/chanx_left_out[8] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__12_/chany_bottom_in[8] -to fpga_top/sb_12__12_/chanx_left_out[9] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__12_/left_bottom_grid_pin_38_[0] -to fpga_top/sb_12__12_/chanx_left_out[9] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__12_/chany_bottom_in[9] -to fpga_top/sb_12__12_/chanx_left_out[10] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__12_/left_bottom_grid_pin_39_[0] -to fpga_top/sb_12__12_/chanx_left_out[10] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__12_/chany_bottom_in[10] -to fpga_top/sb_12__12_/chanx_left_out[11] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__12_/left_bottom_grid_pin_40_[0] -to fpga_top/sb_12__12_/chanx_left_out[11] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__12_/chany_bottom_in[11] -to fpga_top/sb_12__12_/chanx_left_out[12] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__12_/left_bottom_grid_pin_41_[0] -to fpga_top/sb_12__12_/chanx_left_out[12] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__12_/chany_bottom_in[12] -to fpga_top/sb_12__12_/chanx_left_out[13] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__12_/left_bottom_grid_pin_42_[0] -to fpga_top/sb_12__12_/chanx_left_out[13] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__12_/chany_bottom_in[13] -to fpga_top/sb_12__12_/chanx_left_out[14] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__12_/left_top_grid_pin_1_[0] -to fpga_top/sb_12__12_/chanx_left_out[14] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__12_/left_bottom_grid_pin_43_[0] -to fpga_top/sb_12__12_/chanx_left_out[14] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__12_/chany_bottom_in[14] -to fpga_top/sb_12__12_/chanx_left_out[15] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__12_/left_bottom_grid_pin_36_[0] -to fpga_top/sb_12__12_/chanx_left_out[15] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__12_/chany_bottom_in[15] -to fpga_top/sb_12__12_/chanx_left_out[16] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__12_/left_bottom_grid_pin_37_[0] -to fpga_top/sb_12__12_/chanx_left_out[16] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__12_/chany_bottom_in[16] -to fpga_top/sb_12__12_/chanx_left_out[17] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__12_/left_bottom_grid_pin_38_[0] -to fpga_top/sb_12__12_/chanx_left_out[17] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__12_/chany_bottom_in[17] -to fpga_top/sb_12__12_/chanx_left_out[18] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__12_/left_bottom_grid_pin_39_[0] -to fpga_top/sb_12__12_/chanx_left_out[18] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__12_/chany_bottom_in[18] -to fpga_top/sb_12__12_/chanx_left_out[19] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__12_/left_bottom_grid_pin_40_[0] -to fpga_top/sb_12__12_/chanx_left_out[19] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__12_/chany_bottom_in[19] -to fpga_top/sb_12__12_/chanx_left_out[20] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__12_/left_bottom_grid_pin_41_[0] -to fpga_top/sb_12__12_/chanx_left_out[20] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__12_/chany_bottom_in[20] -to fpga_top/sb_12__12_/chanx_left_out[21] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__12_/left_bottom_grid_pin_42_[0] -to fpga_top/sb_12__12_/chanx_left_out[21] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__12_/chany_bottom_in[21] -to fpga_top/sb_12__12_/chanx_left_out[22] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__12_/left_top_grid_pin_1_[0] -to fpga_top/sb_12__12_/chanx_left_out[22] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__12_/chany_bottom_in[22] -to fpga_top/sb_12__12_/chanx_left_out[23] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__12_/left_bottom_grid_pin_36_[0] -to fpga_top/sb_12__12_/chanx_left_out[23] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__12_/chany_bottom_in[23] -to fpga_top/sb_12__12_/chanx_left_out[24] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__12_/left_bottom_grid_pin_37_[0] -to fpga_top/sb_12__12_/chanx_left_out[24] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__12_/chany_bottom_in[24] -to fpga_top/sb_12__12_/chanx_left_out[25] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__12_/left_bottom_grid_pin_38_[0] -to fpga_top/sb_12__12_/chanx_left_out[25] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__12_/chany_bottom_in[25] -to fpga_top/sb_12__12_/chanx_left_out[26] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__12_/left_bottom_grid_pin_39_[0] -to fpga_top/sb_12__12_/chanx_left_out[26] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__12_/left_bottom_grid_pin_43_[0] -to fpga_top/sb_12__12_/chanx_left_out[26] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__12_/chany_bottom_in[26] -to fpga_top/sb_12__12_/chanx_left_out[27] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__12_/left_bottom_grid_pin_40_[0] -to fpga_top/sb_12__12_/chanx_left_out[27] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__12_/chany_bottom_in[27] -to fpga_top/sb_12__12_/chanx_left_out[28] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__12_/left_bottom_grid_pin_41_[0] -to fpga_top/sb_12__12_/chanx_left_out[28] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__12_/chany_bottom_in[28] -to fpga_top/sb_12__12_/chanx_left_out[29] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__12_/left_bottom_grid_pin_42_[0] -to fpga_top/sb_12__12_/chanx_left_out[29] 6.020400151e-11 diff --git a/FPGA1212_RESET_HD_SKY_PNR/FPGA1212_RESET_HD_SKY_Verilog/SDC/sb_12__1_.sdc b/FPGA1212_RESET_HD_SKY_PNR/FPGA1212_RESET_HD_SKY_Verilog/SDC/sb_12__1_.sdc deleted file mode 100644 index 4349a6e..0000000 --- a/FPGA1212_RESET_HD_SKY_PNR/FPGA1212_RESET_HD_SKY_Verilog/SDC/sb_12__1_.sdc +++ /dev/null @@ -1,265 +0,0 @@ -############################################# -# Synopsys Design Constraints (SDC) -# For FPGA fabric -# Description: Constrain timing of Switch Block sb_12__1_ for PnR -# Author: Xifan TANG -# Organization: University of Utah -# Date: Tue Dec 1 18:12:04 2020 -############################################# - -############################################# -# Define time unit -############################################# -set_units -time s - -set_max_delay -from fpga_core_uut/sb_12__1_/top_left_grid_pin_44_[0] -to fpga_top/sb_12__1_/chany_top_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/top_left_grid_pin_47_[0] -to fpga_top/sb_12__1_/chany_top_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/top_left_grid_pin_50_[0] -to fpga_top/sb_12__1_/chany_top_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[3] -to fpga_top/sb_12__1_/chany_top_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[19] -to fpga_top/sb_12__1_/chany_top_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[0] -to fpga_top/sb_12__1_/chany_top_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[11] -to fpga_top/sb_12__1_/chany_top_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[22] -to fpga_top/sb_12__1_/chany_top_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/top_left_grid_pin_45_[0] -to fpga_top/sb_12__1_/chany_top_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/top_left_grid_pin_48_[0] -to fpga_top/sb_12__1_/chany_top_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/top_left_grid_pin_51_[0] -to fpga_top/sb_12__1_/chany_top_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[6] -to fpga_top/sb_12__1_/chany_top_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[20] -to fpga_top/sb_12__1_/chany_top_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[10] -to fpga_top/sb_12__1_/chany_top_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[21] -to fpga_top/sb_12__1_/chany_top_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/top_left_grid_pin_46_[0] -to fpga_top/sb_12__1_/chany_top_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/top_left_grid_pin_49_[0] -to fpga_top/sb_12__1_/chany_top_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/top_right_grid_pin_1_[0] -to fpga_top/sb_12__1_/chany_top_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[7] -to fpga_top/sb_12__1_/chany_top_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[22] -to fpga_top/sb_12__1_/chany_top_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[9] -to fpga_top/sb_12__1_/chany_top_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[20] -to fpga_top/sb_12__1_/chany_top_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/top_left_grid_pin_44_[0] -to fpga_top/sb_12__1_/chany_top_out[3] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/top_left_grid_pin_46_[0] -to fpga_top/sb_12__1_/chany_top_out[3] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/top_left_grid_pin_48_[0] -to fpga_top/sb_12__1_/chany_top_out[3] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/top_left_grid_pin_50_[0] -to fpga_top/sb_12__1_/chany_top_out[3] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/top_right_grid_pin_1_[0] -to fpga_top/sb_12__1_/chany_top_out[3] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[8] -to fpga_top/sb_12__1_/chany_top_out[3] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[23] -to fpga_top/sb_12__1_/chany_top_out[3] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[8] -to fpga_top/sb_12__1_/chany_top_out[3] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[19] -to fpga_top/sb_12__1_/chany_top_out[3] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/top_left_grid_pin_45_[0] -to fpga_top/sb_12__1_/chany_top_out[5] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/top_left_grid_pin_47_[0] -to fpga_top/sb_12__1_/chany_top_out[5] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/top_left_grid_pin_49_[0] -to fpga_top/sb_12__1_/chany_top_out[5] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/top_left_grid_pin_51_[0] -to fpga_top/sb_12__1_/chany_top_out[5] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[10] -to fpga_top/sb_12__1_/chany_top_out[5] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[24] -to fpga_top/sb_12__1_/chany_top_out[5] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[7] -to fpga_top/sb_12__1_/chany_top_out[5] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[18] -to fpga_top/sb_12__1_/chany_top_out[5] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[29] -to fpga_top/sb_12__1_/chany_top_out[5] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/top_left_grid_pin_44_[0] -to fpga_top/sb_12__1_/chany_top_out[6] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/top_left_grid_pin_50_[0] -to fpga_top/sb_12__1_/chany_top_out[6] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[11] -to fpga_top/sb_12__1_/chany_top_out[6] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[26] -to fpga_top/sb_12__1_/chany_top_out[6] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[6] -to fpga_top/sb_12__1_/chany_top_out[6] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[17] -to fpga_top/sb_12__1_/chany_top_out[6] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[28] -to fpga_top/sb_12__1_/chany_top_out[6] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/top_left_grid_pin_45_[0] -to fpga_top/sb_12__1_/chany_top_out[10] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/top_left_grid_pin_51_[0] -to fpga_top/sb_12__1_/chany_top_out[10] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[12] -to fpga_top/sb_12__1_/chany_top_out[10] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[27] -to fpga_top/sb_12__1_/chany_top_out[10] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[5] -to fpga_top/sb_12__1_/chany_top_out[10] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[16] -to fpga_top/sb_12__1_/chany_top_out[10] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[27] -to fpga_top/sb_12__1_/chany_top_out[10] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/top_left_grid_pin_46_[0] -to fpga_top/sb_12__1_/chany_top_out[14] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/top_right_grid_pin_1_[0] -to fpga_top/sb_12__1_/chany_top_out[14] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[14] -to fpga_top/sb_12__1_/chany_top_out[14] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[28] -to fpga_top/sb_12__1_/chany_top_out[14] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[4] -to fpga_top/sb_12__1_/chany_top_out[14] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[15] -to fpga_top/sb_12__1_/chany_top_out[14] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[26] -to fpga_top/sb_12__1_/chany_top_out[14] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/top_left_grid_pin_47_[0] -to fpga_top/sb_12__1_/chany_top_out[18] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[15] -to fpga_top/sb_12__1_/chany_top_out[18] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[3] -to fpga_top/sb_12__1_/chany_top_out[18] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[14] -to fpga_top/sb_12__1_/chany_top_out[18] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[25] -to fpga_top/sb_12__1_/chany_top_out[18] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/top_left_grid_pin_48_[0] -to fpga_top/sb_12__1_/chany_top_out[22] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[16] -to fpga_top/sb_12__1_/chany_top_out[22] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[2] -to fpga_top/sb_12__1_/chany_top_out[22] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[13] -to fpga_top/sb_12__1_/chany_top_out[22] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[24] -to fpga_top/sb_12__1_/chany_top_out[22] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/top_left_grid_pin_49_[0] -to fpga_top/sb_12__1_/chany_top_out[26] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[18] -to fpga_top/sb_12__1_/chany_top_out[26] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[1] -to fpga_top/sb_12__1_/chany_top_out[26] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[12] -to fpga_top/sb_12__1_/chany_top_out[26] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[23] -to fpga_top/sb_12__1_/chany_top_out[26] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[3] -to fpga_top/sb_12__1_/chany_bottom_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[19] -to fpga_top/sb_12__1_/chany_bottom_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/bottom_right_grid_pin_1_[0] -to fpga_top/sb_12__1_/chany_bottom_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/bottom_left_grid_pin_46_[0] -to fpga_top/sb_12__1_/chany_bottom_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/bottom_left_grid_pin_49_[0] -to fpga_top/sb_12__1_/chany_bottom_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[1] -to fpga_top/sb_12__1_/chany_bottom_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[12] -to fpga_top/sb_12__1_/chany_bottom_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[23] -to fpga_top/sb_12__1_/chany_bottom_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[6] -to fpga_top/sb_12__1_/chany_bottom_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[20] -to fpga_top/sb_12__1_/chany_bottom_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/bottom_left_grid_pin_44_[0] -to fpga_top/sb_12__1_/chany_bottom_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/bottom_left_grid_pin_47_[0] -to fpga_top/sb_12__1_/chany_bottom_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/bottom_left_grid_pin_50_[0] -to fpga_top/sb_12__1_/chany_bottom_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[2] -to fpga_top/sb_12__1_/chany_bottom_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[13] -to fpga_top/sb_12__1_/chany_bottom_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[24] -to fpga_top/sb_12__1_/chany_bottom_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[7] -to fpga_top/sb_12__1_/chany_bottom_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[22] -to fpga_top/sb_12__1_/chany_bottom_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/bottom_left_grid_pin_45_[0] -to fpga_top/sb_12__1_/chany_bottom_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/bottom_left_grid_pin_48_[0] -to fpga_top/sb_12__1_/chany_bottom_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/bottom_left_grid_pin_51_[0] -to fpga_top/sb_12__1_/chany_bottom_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[3] -to fpga_top/sb_12__1_/chany_bottom_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[14] -to fpga_top/sb_12__1_/chany_bottom_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[25] -to fpga_top/sb_12__1_/chany_bottom_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[8] -to fpga_top/sb_12__1_/chany_bottom_out[3] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[23] -to fpga_top/sb_12__1_/chany_bottom_out[3] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/bottom_right_grid_pin_1_[0] -to fpga_top/sb_12__1_/chany_bottom_out[3] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/bottom_left_grid_pin_45_[0] -to fpga_top/sb_12__1_/chany_bottom_out[3] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/bottom_left_grid_pin_47_[0] -to fpga_top/sb_12__1_/chany_bottom_out[3] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/bottom_left_grid_pin_49_[0] -to fpga_top/sb_12__1_/chany_bottom_out[3] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/bottom_left_grid_pin_51_[0] -to fpga_top/sb_12__1_/chany_bottom_out[3] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[4] -to fpga_top/sb_12__1_/chany_bottom_out[3] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[15] -to fpga_top/sb_12__1_/chany_bottom_out[3] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[26] -to fpga_top/sb_12__1_/chany_bottom_out[3] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[10] -to fpga_top/sb_12__1_/chany_bottom_out[5] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[24] -to fpga_top/sb_12__1_/chany_bottom_out[5] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/bottom_left_grid_pin_44_[0] -to fpga_top/sb_12__1_/chany_bottom_out[5] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/bottom_left_grid_pin_46_[0] -to fpga_top/sb_12__1_/chany_bottom_out[5] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/bottom_left_grid_pin_48_[0] -to fpga_top/sb_12__1_/chany_bottom_out[5] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/bottom_left_grid_pin_50_[0] -to fpga_top/sb_12__1_/chany_bottom_out[5] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[5] -to fpga_top/sb_12__1_/chany_bottom_out[5] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[16] -to fpga_top/sb_12__1_/chany_bottom_out[5] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[27] -to fpga_top/sb_12__1_/chany_bottom_out[5] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[11] -to fpga_top/sb_12__1_/chany_bottom_out[6] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[26] -to fpga_top/sb_12__1_/chany_bottom_out[6] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/bottom_right_grid_pin_1_[0] -to fpga_top/sb_12__1_/chany_bottom_out[6] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/bottom_left_grid_pin_49_[0] -to fpga_top/sb_12__1_/chany_bottom_out[6] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[6] -to fpga_top/sb_12__1_/chany_bottom_out[6] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[17] -to fpga_top/sb_12__1_/chany_bottom_out[6] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[28] -to fpga_top/sb_12__1_/chany_bottom_out[6] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[12] -to fpga_top/sb_12__1_/chany_bottom_out[10] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[27] -to fpga_top/sb_12__1_/chany_bottom_out[10] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/bottom_left_grid_pin_44_[0] -to fpga_top/sb_12__1_/chany_bottom_out[10] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/bottom_left_grid_pin_50_[0] -to fpga_top/sb_12__1_/chany_bottom_out[10] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[7] -to fpga_top/sb_12__1_/chany_bottom_out[10] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[18] -to fpga_top/sb_12__1_/chany_bottom_out[10] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[29] -to fpga_top/sb_12__1_/chany_bottom_out[10] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[14] -to fpga_top/sb_12__1_/chany_bottom_out[14] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[28] -to fpga_top/sb_12__1_/chany_bottom_out[14] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/bottom_left_grid_pin_45_[0] -to fpga_top/sb_12__1_/chany_bottom_out[14] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/bottom_left_grid_pin_51_[0] -to fpga_top/sb_12__1_/chany_bottom_out[14] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[8] -to fpga_top/sb_12__1_/chany_bottom_out[14] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[19] -to fpga_top/sb_12__1_/chany_bottom_out[14] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[15] -to fpga_top/sb_12__1_/chany_bottom_out[18] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/bottom_left_grid_pin_46_[0] -to fpga_top/sb_12__1_/chany_bottom_out[18] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[9] -to fpga_top/sb_12__1_/chany_bottom_out[18] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[20] -to fpga_top/sb_12__1_/chany_bottom_out[18] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[16] -to fpga_top/sb_12__1_/chany_bottom_out[22] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/bottom_left_grid_pin_47_[0] -to fpga_top/sb_12__1_/chany_bottom_out[22] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[10] -to fpga_top/sb_12__1_/chany_bottom_out[22] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[21] -to fpga_top/sb_12__1_/chany_bottom_out[22] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[18] -to fpga_top/sb_12__1_/chany_bottom_out[26] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/bottom_left_grid_pin_48_[0] -to fpga_top/sb_12__1_/chany_bottom_out[26] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[0] -to fpga_top/sb_12__1_/chany_bottom_out[26] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[11] -to fpga_top/sb_12__1_/chany_bottom_out[26] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[22] -to fpga_top/sb_12__1_/chany_bottom_out[26] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[0] -to fpga_top/sb_12__1_/chanx_left_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[3] -to fpga_top/sb_12__1_/chanx_left_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[3] -to fpga_top/sb_12__1_/chanx_left_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/left_bottom_grid_pin_36_[0] -to fpga_top/sb_12__1_/chanx_left_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/left_bottom_grid_pin_39_[0] -to fpga_top/sb_12__1_/chanx_left_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/left_bottom_grid_pin_42_[0] -to fpga_top/sb_12__1_/chanx_left_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[6] -to fpga_top/sb_12__1_/chanx_left_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[0] -to fpga_top/sb_12__1_/chanx_left_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[6] -to fpga_top/sb_12__1_/chanx_left_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/left_bottom_grid_pin_37_[0] -to fpga_top/sb_12__1_/chanx_left_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/left_bottom_grid_pin_40_[0] -to fpga_top/sb_12__1_/chanx_left_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/left_bottom_grid_pin_43_[0] -to fpga_top/sb_12__1_/chanx_left_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[7] -to fpga_top/sb_12__1_/chanx_left_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[1] -to fpga_top/sb_12__1_/chanx_left_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[7] -to fpga_top/sb_12__1_/chanx_left_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/left_bottom_grid_pin_38_[0] -to fpga_top/sb_12__1_/chanx_left_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/left_bottom_grid_pin_41_[0] -to fpga_top/sb_12__1_/chanx_left_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[8] -to fpga_top/sb_12__1_/chanx_left_out[3] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[2] -to fpga_top/sb_12__1_/chanx_left_out[3] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[8] -to fpga_top/sb_12__1_/chanx_left_out[3] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/left_bottom_grid_pin_36_[0] -to fpga_top/sb_12__1_/chanx_left_out[3] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/left_bottom_grid_pin_39_[0] -to fpga_top/sb_12__1_/chanx_left_out[3] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/left_bottom_grid_pin_42_[0] -to fpga_top/sb_12__1_/chanx_left_out[3] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[10] -to fpga_top/sb_12__1_/chanx_left_out[4] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[4] -to fpga_top/sb_12__1_/chanx_left_out[4] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[10] -to fpga_top/sb_12__1_/chanx_left_out[4] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/left_bottom_grid_pin_37_[0] -to fpga_top/sb_12__1_/chanx_left_out[4] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/left_bottom_grid_pin_40_[0] -to fpga_top/sb_12__1_/chanx_left_out[4] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/left_bottom_grid_pin_43_[0] -to fpga_top/sb_12__1_/chanx_left_out[4] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[11] -to fpga_top/sb_12__1_/chanx_left_out[5] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[5] -to fpga_top/sb_12__1_/chanx_left_out[5] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[11] -to fpga_top/sb_12__1_/chanx_left_out[5] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/left_bottom_grid_pin_38_[0] -to fpga_top/sb_12__1_/chanx_left_out[5] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/left_bottom_grid_pin_41_[0] -to fpga_top/sb_12__1_/chanx_left_out[5] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[12] -to fpga_top/sb_12__1_/chanx_left_out[6] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[9] -to fpga_top/sb_12__1_/chanx_left_out[6] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[12] -to fpga_top/sb_12__1_/chanx_left_out[6] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/left_bottom_grid_pin_36_[0] -to fpga_top/sb_12__1_/chanx_left_out[6] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[14] -to fpga_top/sb_12__1_/chanx_left_out[7] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[13] -to fpga_top/sb_12__1_/chanx_left_out[7] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[14] -to fpga_top/sb_12__1_/chanx_left_out[7] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/left_bottom_grid_pin_37_[0] -to fpga_top/sb_12__1_/chanx_left_out[7] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[15] -to fpga_top/sb_12__1_/chanx_left_out[8] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[15] -to fpga_top/sb_12__1_/chanx_left_out[8] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[17] -to fpga_top/sb_12__1_/chanx_left_out[8] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/left_bottom_grid_pin_38_[0] -to fpga_top/sb_12__1_/chanx_left_out[8] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[16] -to fpga_top/sb_12__1_/chanx_left_out[9] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[16] -to fpga_top/sb_12__1_/chanx_left_out[9] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[21] -to fpga_top/sb_12__1_/chanx_left_out[9] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/left_bottom_grid_pin_39_[0] -to fpga_top/sb_12__1_/chanx_left_out[9] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[18] -to fpga_top/sb_12__1_/chanx_left_out[10] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[18] -to fpga_top/sb_12__1_/chanx_left_out[10] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[25] -to fpga_top/sb_12__1_/chanx_left_out[10] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/left_bottom_grid_pin_40_[0] -to fpga_top/sb_12__1_/chanx_left_out[10] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[19] -to fpga_top/sb_12__1_/chanx_left_out[11] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[19] -to fpga_top/sb_12__1_/chanx_left_out[11] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[29] -to fpga_top/sb_12__1_/chanx_left_out[11] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/left_bottom_grid_pin_41_[0] -to fpga_top/sb_12__1_/chanx_left_out[11] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[20] -to fpga_top/sb_12__1_/chanx_left_out[12] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[20] -to fpga_top/sb_12__1_/chanx_left_out[12] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/left_bottom_grid_pin_42_[0] -to fpga_top/sb_12__1_/chanx_left_out[12] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[22] -to fpga_top/sb_12__1_/chanx_left_out[13] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[22] -to fpga_top/sb_12__1_/chanx_left_out[13] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/left_bottom_grid_pin_43_[0] -to fpga_top/sb_12__1_/chanx_left_out[13] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[23] -to fpga_top/sb_12__1_/chanx_left_out[14] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[23] -to fpga_top/sb_12__1_/chanx_left_out[14] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/left_bottom_grid_pin_36_[0] -to fpga_top/sb_12__1_/chanx_left_out[14] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[24] -to fpga_top/sb_12__1_/chanx_left_out[15] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[24] -to fpga_top/sb_12__1_/chanx_left_out[15] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/left_bottom_grid_pin_37_[0] -to fpga_top/sb_12__1_/chanx_left_out[15] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[26] -to fpga_top/sb_12__1_/chanx_left_out[16] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[26] -to fpga_top/sb_12__1_/chanx_left_out[16] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/left_bottom_grid_pin_38_[0] -to fpga_top/sb_12__1_/chanx_left_out[16] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[27] -to fpga_top/sb_12__1_/chanx_left_out[17] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[27] -to fpga_top/sb_12__1_/chanx_left_out[17] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/left_bottom_grid_pin_39_[0] -to fpga_top/sb_12__1_/chanx_left_out[17] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[28] -to fpga_top/sb_12__1_/chanx_left_out[18] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[28] -to fpga_top/sb_12__1_/chanx_left_out[18] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/left_bottom_grid_pin_40_[0] -to fpga_top/sb_12__1_/chanx_left_out[18] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/left_bottom_grid_pin_41_[0] -to fpga_top/sb_12__1_/chanx_left_out[19] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[29] -to fpga_top/sb_12__1_/chanx_left_out[20] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/left_bottom_grid_pin_42_[0] -to fpga_top/sb_12__1_/chanx_left_out[20] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[25] -to fpga_top/sb_12__1_/chanx_left_out[21] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[21] -to fpga_top/sb_12__1_/chanx_left_out[22] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/left_bottom_grid_pin_36_[0] -to fpga_top/sb_12__1_/chanx_left_out[22] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[17] -to fpga_top/sb_12__1_/chanx_left_out[23] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/left_bottom_grid_pin_37_[0] -to fpga_top/sb_12__1_/chanx_left_out[23] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[13] -to fpga_top/sb_12__1_/chanx_left_out[24] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/left_bottom_grid_pin_38_[0] -to fpga_top/sb_12__1_/chanx_left_out[24] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[9] -to fpga_top/sb_12__1_/chanx_left_out[25] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/left_bottom_grid_pin_39_[0] -to fpga_top/sb_12__1_/chanx_left_out[25] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/left_bottom_grid_pin_43_[0] -to fpga_top/sb_12__1_/chanx_left_out[25] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[5] -to fpga_top/sb_12__1_/chanx_left_out[26] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/left_bottom_grid_pin_40_[0] -to fpga_top/sb_12__1_/chanx_left_out[26] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[4] -to fpga_top/sb_12__1_/chanx_left_out[27] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/left_bottom_grid_pin_41_[0] -to fpga_top/sb_12__1_/chanx_left_out[27] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[2] -to fpga_top/sb_12__1_/chanx_left_out[28] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/left_bottom_grid_pin_42_[0] -to fpga_top/sb_12__1_/chanx_left_out[28] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[1] -to fpga_top/sb_12__1_/chanx_left_out[29] 6.020400151e-11 diff --git a/FPGA1212_RESET_HD_SKY_PNR/FPGA1212_RESET_HD_SKY_Verilog/SDC/sb_1__0_.sdc b/FPGA1212_RESET_HD_SKY_PNR/FPGA1212_RESET_HD_SKY_Verilog/SDC/sb_1__0_.sdc deleted file mode 100644 index 6552596..0000000 --- a/FPGA1212_RESET_HD_SKY_PNR/FPGA1212_RESET_HD_SKY_Verilog/SDC/sb_1__0_.sdc +++ /dev/null @@ -1,258 +0,0 @@ -############################################# -# Synopsys Design Constraints (SDC) -# For FPGA fabric -# Description: Constrain timing of Switch Block sb_1__0_ for PnR -# Author: Xifan TANG -# Organization: University of Utah -# Date: Tue Dec 1 18:12:04 2020 -############################################# - -############################################# -# Define time unit -############################################# -set_units -time s - -set_max_delay -from fpga_core_uut/sb_1__0_/top_left_grid_pin_44_[0] -to fpga_top/sb_1__0_/chany_top_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/top_left_grid_pin_47_[0] -to fpga_top/sb_1__0_/chany_top_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/top_left_grid_pin_50_[0] -to fpga_top/sb_1__0_/chany_top_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[1] -to fpga_top/sb_1__0_/chany_top_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[3] -to fpga_top/sb_1__0_/chany_top_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[0] -to fpga_top/sb_1__0_/chany_top_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[3] -to fpga_top/sb_1__0_/chany_top_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/top_left_grid_pin_45_[0] -to fpga_top/sb_1__0_/chany_top_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/top_left_grid_pin_48_[0] -to fpga_top/sb_1__0_/chany_top_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/top_left_grid_pin_51_[0] -to fpga_top/sb_1__0_/chany_top_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[2] -to fpga_top/sb_1__0_/chany_top_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[6] -to fpga_top/sb_1__0_/chany_top_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[6] -to fpga_top/sb_1__0_/chany_top_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/top_left_grid_pin_46_[0] -to fpga_top/sb_1__0_/chany_top_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/top_left_grid_pin_49_[0] -to fpga_top/sb_1__0_/chany_top_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[4] -to fpga_top/sb_1__0_/chany_top_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[7] -to fpga_top/sb_1__0_/chany_top_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[7] -to fpga_top/sb_1__0_/chany_top_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/top_left_grid_pin_44_[0] -to fpga_top/sb_1__0_/chany_top_out[3] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/top_left_grid_pin_47_[0] -to fpga_top/sb_1__0_/chany_top_out[3] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/top_left_grid_pin_50_[0] -to fpga_top/sb_1__0_/chany_top_out[3] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[5] -to fpga_top/sb_1__0_/chany_top_out[3] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[8] -to fpga_top/sb_1__0_/chany_top_out[3] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[8] -to fpga_top/sb_1__0_/chany_top_out[3] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/top_left_grid_pin_45_[0] -to fpga_top/sb_1__0_/chany_top_out[4] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/top_left_grid_pin_48_[0] -to fpga_top/sb_1__0_/chany_top_out[4] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/top_left_grid_pin_51_[0] -to fpga_top/sb_1__0_/chany_top_out[4] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[9] -to fpga_top/sb_1__0_/chany_top_out[4] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[10] -to fpga_top/sb_1__0_/chany_top_out[4] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[10] -to fpga_top/sb_1__0_/chany_top_out[4] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/top_left_grid_pin_46_[0] -to fpga_top/sb_1__0_/chany_top_out[5] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/top_left_grid_pin_49_[0] -to fpga_top/sb_1__0_/chany_top_out[5] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[11] -to fpga_top/sb_1__0_/chany_top_out[5] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[13] -to fpga_top/sb_1__0_/chany_top_out[5] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[11] -to fpga_top/sb_1__0_/chany_top_out[5] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/top_left_grid_pin_44_[0] -to fpga_top/sb_1__0_/chany_top_out[6] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[12] -to fpga_top/sb_1__0_/chany_top_out[6] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[17] -to fpga_top/sb_1__0_/chany_top_out[6] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[12] -to fpga_top/sb_1__0_/chany_top_out[6] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/top_left_grid_pin_45_[0] -to fpga_top/sb_1__0_/chany_top_out[7] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[14] -to fpga_top/sb_1__0_/chany_top_out[7] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[21] -to fpga_top/sb_1__0_/chany_top_out[7] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[14] -to fpga_top/sb_1__0_/chany_top_out[7] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/top_left_grid_pin_46_[0] -to fpga_top/sb_1__0_/chany_top_out[8] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[15] -to fpga_top/sb_1__0_/chany_top_out[8] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[25] -to fpga_top/sb_1__0_/chany_top_out[8] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[15] -to fpga_top/sb_1__0_/chany_top_out[8] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/top_left_grid_pin_47_[0] -to fpga_top/sb_1__0_/chany_top_out[9] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[16] -to fpga_top/sb_1__0_/chany_top_out[9] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[29] -to fpga_top/sb_1__0_/chany_top_out[9] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[16] -to fpga_top/sb_1__0_/chany_top_out[9] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/top_left_grid_pin_48_[0] -to fpga_top/sb_1__0_/chany_top_out[10] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[18] -to fpga_top/sb_1__0_/chany_top_out[10] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[18] -to fpga_top/sb_1__0_/chany_top_out[10] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/top_left_grid_pin_49_[0] -to fpga_top/sb_1__0_/chany_top_out[11] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[19] -to fpga_top/sb_1__0_/chany_top_out[11] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[19] -to fpga_top/sb_1__0_/chany_top_out[11] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/top_left_grid_pin_50_[0] -to fpga_top/sb_1__0_/chany_top_out[12] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[20] -to fpga_top/sb_1__0_/chany_top_out[12] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[20] -to fpga_top/sb_1__0_/chany_top_out[12] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/top_left_grid_pin_51_[0] -to fpga_top/sb_1__0_/chany_top_out[13] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[22] -to fpga_top/sb_1__0_/chany_top_out[13] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[22] -to fpga_top/sb_1__0_/chany_top_out[13] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[23] -to fpga_top/sb_1__0_/chany_top_out[14] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[23] -to fpga_top/sb_1__0_/chany_top_out[14] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[24] -to fpga_top/sb_1__0_/chany_top_out[15] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[24] -to fpga_top/sb_1__0_/chany_top_out[15] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[26] -to fpga_top/sb_1__0_/chany_top_out[16] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[26] -to fpga_top/sb_1__0_/chany_top_out[16] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[27] -to fpga_top/sb_1__0_/chany_top_out[17] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[27] -to fpga_top/sb_1__0_/chany_top_out[17] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/top_left_grid_pin_44_[0] -to fpga_top/sb_1__0_/chany_top_out[18] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[28] -to fpga_top/sb_1__0_/chany_top_out[18] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[28] -to fpga_top/sb_1__0_/chany_top_out[18] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/top_left_grid_pin_45_[0] -to fpga_top/sb_1__0_/chany_top_out[19] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/top_left_grid_pin_46_[0] -to fpga_top/sb_1__0_/chany_top_out[20] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[29] -to fpga_top/sb_1__0_/chany_top_out[20] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/top_left_grid_pin_47_[0] -to fpga_top/sb_1__0_/chany_top_out[21] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[25] -to fpga_top/sb_1__0_/chany_top_out[21] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/top_left_grid_pin_48_[0] -to fpga_top/sb_1__0_/chany_top_out[22] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[21] -to fpga_top/sb_1__0_/chany_top_out[22] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/top_left_grid_pin_49_[0] -to fpga_top/sb_1__0_/chany_top_out[23] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[17] -to fpga_top/sb_1__0_/chany_top_out[23] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/top_left_grid_pin_50_[0] -to fpga_top/sb_1__0_/chany_top_out[24] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[13] -to fpga_top/sb_1__0_/chany_top_out[24] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/top_left_grid_pin_51_[0] -to fpga_top/sb_1__0_/chany_top_out[25] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[9] -to fpga_top/sb_1__0_/chany_top_out[25] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[5] -to fpga_top/sb_1__0_/chany_top_out[26] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[4] -to fpga_top/sb_1__0_/chany_top_out[27] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[2] -to fpga_top/sb_1__0_/chany_top_out[28] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[0] -to fpga_top/sb_1__0_/chany_top_out[29] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[1] -to fpga_top/sb_1__0_/chany_top_out[29] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[10] -to fpga_top/sb_1__0_/chanx_right_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[21] -to fpga_top/sb_1__0_/chanx_right_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/right_bottom_grid_pin_1_[0] -to fpga_top/sb_1__0_/chanx_right_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/right_bottom_grid_pin_7_[0] -to fpga_top/sb_1__0_/chanx_right_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/right_bottom_grid_pin_13_[0] -to fpga_top/sb_1__0_/chanx_right_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[3] -to fpga_top/sb_1__0_/chanx_right_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[19] -to fpga_top/sb_1__0_/chanx_right_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[0] -to fpga_top/sb_1__0_/chanx_right_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[11] -to fpga_top/sb_1__0_/chanx_right_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[22] -to fpga_top/sb_1__0_/chanx_right_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/right_bottom_grid_pin_3_[0] -to fpga_top/sb_1__0_/chanx_right_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/right_bottom_grid_pin_9_[0] -to fpga_top/sb_1__0_/chanx_right_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/right_bottom_grid_pin_15_[0] -to fpga_top/sb_1__0_/chanx_right_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[6] -to fpga_top/sb_1__0_/chanx_right_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[20] -to fpga_top/sb_1__0_/chanx_right_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[1] -to fpga_top/sb_1__0_/chanx_right_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[12] -to fpga_top/sb_1__0_/chanx_right_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[23] -to fpga_top/sb_1__0_/chanx_right_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/right_bottom_grid_pin_5_[0] -to fpga_top/sb_1__0_/chanx_right_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/right_bottom_grid_pin_11_[0] -to fpga_top/sb_1__0_/chanx_right_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/right_bottom_grid_pin_17_[0] -to fpga_top/sb_1__0_/chanx_right_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[7] -to fpga_top/sb_1__0_/chanx_right_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[22] -to fpga_top/sb_1__0_/chanx_right_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[2] -to fpga_top/sb_1__0_/chanx_right_out[3] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[13] -to fpga_top/sb_1__0_/chanx_right_out[3] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[24] -to fpga_top/sb_1__0_/chanx_right_out[3] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/right_bottom_grid_pin_1_[0] -to fpga_top/sb_1__0_/chanx_right_out[3] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/right_bottom_grid_pin_5_[0] -to fpga_top/sb_1__0_/chanx_right_out[3] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/right_bottom_grid_pin_9_[0] -to fpga_top/sb_1__0_/chanx_right_out[3] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/right_bottom_grid_pin_13_[0] -to fpga_top/sb_1__0_/chanx_right_out[3] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/right_bottom_grid_pin_17_[0] -to fpga_top/sb_1__0_/chanx_right_out[3] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[8] -to fpga_top/sb_1__0_/chanx_right_out[3] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[23] -to fpga_top/sb_1__0_/chanx_right_out[3] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[3] -to fpga_top/sb_1__0_/chanx_right_out[5] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[14] -to fpga_top/sb_1__0_/chanx_right_out[5] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[25] -to fpga_top/sb_1__0_/chanx_right_out[5] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/right_bottom_grid_pin_3_[0] -to fpga_top/sb_1__0_/chanx_right_out[5] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/right_bottom_grid_pin_7_[0] -to fpga_top/sb_1__0_/chanx_right_out[5] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/right_bottom_grid_pin_11_[0] -to fpga_top/sb_1__0_/chanx_right_out[5] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/right_bottom_grid_pin_15_[0] -to fpga_top/sb_1__0_/chanx_right_out[5] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[10] -to fpga_top/sb_1__0_/chanx_right_out[5] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[24] -to fpga_top/sb_1__0_/chanx_right_out[5] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[4] -to fpga_top/sb_1__0_/chanx_right_out[6] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[15] -to fpga_top/sb_1__0_/chanx_right_out[6] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[26] -to fpga_top/sb_1__0_/chanx_right_out[6] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/right_bottom_grid_pin_1_[0] -to fpga_top/sb_1__0_/chanx_right_out[6] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/right_bottom_grid_pin_13_[0] -to fpga_top/sb_1__0_/chanx_right_out[6] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[11] -to fpga_top/sb_1__0_/chanx_right_out[6] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[26] -to fpga_top/sb_1__0_/chanx_right_out[6] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[5] -to fpga_top/sb_1__0_/chanx_right_out[10] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[16] -to fpga_top/sb_1__0_/chanx_right_out[10] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[27] -to fpga_top/sb_1__0_/chanx_right_out[10] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/right_bottom_grid_pin_3_[0] -to fpga_top/sb_1__0_/chanx_right_out[10] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/right_bottom_grid_pin_15_[0] -to fpga_top/sb_1__0_/chanx_right_out[10] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[12] -to fpga_top/sb_1__0_/chanx_right_out[10] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[27] -to fpga_top/sb_1__0_/chanx_right_out[10] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[6] -to fpga_top/sb_1__0_/chanx_right_out[14] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[17] -to fpga_top/sb_1__0_/chanx_right_out[14] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[28] -to fpga_top/sb_1__0_/chanx_right_out[14] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/right_bottom_grid_pin_5_[0] -to fpga_top/sb_1__0_/chanx_right_out[14] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/right_bottom_grid_pin_17_[0] -to fpga_top/sb_1__0_/chanx_right_out[14] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[14] -to fpga_top/sb_1__0_/chanx_right_out[14] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[28] -to fpga_top/sb_1__0_/chanx_right_out[14] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[7] -to fpga_top/sb_1__0_/chanx_right_out[18] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[18] -to fpga_top/sb_1__0_/chanx_right_out[18] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[29] -to fpga_top/sb_1__0_/chanx_right_out[18] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/right_bottom_grid_pin_7_[0] -to fpga_top/sb_1__0_/chanx_right_out[18] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[15] -to fpga_top/sb_1__0_/chanx_right_out[18] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[8] -to fpga_top/sb_1__0_/chanx_right_out[22] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[19] -to fpga_top/sb_1__0_/chanx_right_out[22] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/right_bottom_grid_pin_9_[0] -to fpga_top/sb_1__0_/chanx_right_out[22] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[16] -to fpga_top/sb_1__0_/chanx_right_out[22] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[9] -to fpga_top/sb_1__0_/chanx_right_out[26] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[20] -to fpga_top/sb_1__0_/chanx_right_out[26] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/right_bottom_grid_pin_11_[0] -to fpga_top/sb_1__0_/chanx_right_out[26] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[18] -to fpga_top/sb_1__0_/chanx_right_out[26] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[0] -to fpga_top/sb_1__0_/chanx_left_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[11] -to fpga_top/sb_1__0_/chanx_left_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[22] -to fpga_top/sb_1__0_/chanx_left_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[3] -to fpga_top/sb_1__0_/chanx_left_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[19] -to fpga_top/sb_1__0_/chanx_left_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/left_bottom_grid_pin_1_[0] -to fpga_top/sb_1__0_/chanx_left_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/left_bottom_grid_pin_7_[0] -to fpga_top/sb_1__0_/chanx_left_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/left_bottom_grid_pin_13_[0] -to fpga_top/sb_1__0_/chanx_left_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[10] -to fpga_top/sb_1__0_/chanx_left_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[21] -to fpga_top/sb_1__0_/chanx_left_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[6] -to fpga_top/sb_1__0_/chanx_left_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[20] -to fpga_top/sb_1__0_/chanx_left_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/left_bottom_grid_pin_3_[0] -to fpga_top/sb_1__0_/chanx_left_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/left_bottom_grid_pin_9_[0] -to fpga_top/sb_1__0_/chanx_left_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/left_bottom_grid_pin_15_[0] -to fpga_top/sb_1__0_/chanx_left_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[9] -to fpga_top/sb_1__0_/chanx_left_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[20] -to fpga_top/sb_1__0_/chanx_left_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[7] -to fpga_top/sb_1__0_/chanx_left_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[22] -to fpga_top/sb_1__0_/chanx_left_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/left_bottom_grid_pin_5_[0] -to fpga_top/sb_1__0_/chanx_left_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/left_bottom_grid_pin_11_[0] -to fpga_top/sb_1__0_/chanx_left_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/left_bottom_grid_pin_17_[0] -to fpga_top/sb_1__0_/chanx_left_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[8] -to fpga_top/sb_1__0_/chanx_left_out[3] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[19] -to fpga_top/sb_1__0_/chanx_left_out[3] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[8] -to fpga_top/sb_1__0_/chanx_left_out[3] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[23] -to fpga_top/sb_1__0_/chanx_left_out[3] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/left_bottom_grid_pin_1_[0] -to fpga_top/sb_1__0_/chanx_left_out[3] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/left_bottom_grid_pin_5_[0] -to fpga_top/sb_1__0_/chanx_left_out[3] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/left_bottom_grid_pin_9_[0] -to fpga_top/sb_1__0_/chanx_left_out[3] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/left_bottom_grid_pin_13_[0] -to fpga_top/sb_1__0_/chanx_left_out[3] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/left_bottom_grid_pin_17_[0] -to fpga_top/sb_1__0_/chanx_left_out[3] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[7] -to fpga_top/sb_1__0_/chanx_left_out[5] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[18] -to fpga_top/sb_1__0_/chanx_left_out[5] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[29] -to fpga_top/sb_1__0_/chanx_left_out[5] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[10] -to fpga_top/sb_1__0_/chanx_left_out[5] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[24] -to fpga_top/sb_1__0_/chanx_left_out[5] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/left_bottom_grid_pin_3_[0] -to fpga_top/sb_1__0_/chanx_left_out[5] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/left_bottom_grid_pin_7_[0] -to fpga_top/sb_1__0_/chanx_left_out[5] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/left_bottom_grid_pin_11_[0] -to fpga_top/sb_1__0_/chanx_left_out[5] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/left_bottom_grid_pin_15_[0] -to fpga_top/sb_1__0_/chanx_left_out[5] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[6] -to fpga_top/sb_1__0_/chanx_left_out[6] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[17] -to fpga_top/sb_1__0_/chanx_left_out[6] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[28] -to fpga_top/sb_1__0_/chanx_left_out[6] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[11] -to fpga_top/sb_1__0_/chanx_left_out[6] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[26] -to fpga_top/sb_1__0_/chanx_left_out[6] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/left_bottom_grid_pin_1_[0] -to fpga_top/sb_1__0_/chanx_left_out[6] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/left_bottom_grid_pin_13_[0] -to fpga_top/sb_1__0_/chanx_left_out[6] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[5] -to fpga_top/sb_1__0_/chanx_left_out[10] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[16] -to fpga_top/sb_1__0_/chanx_left_out[10] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[27] -to fpga_top/sb_1__0_/chanx_left_out[10] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[12] -to fpga_top/sb_1__0_/chanx_left_out[10] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[27] -to fpga_top/sb_1__0_/chanx_left_out[10] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/left_bottom_grid_pin_3_[0] -to fpga_top/sb_1__0_/chanx_left_out[10] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/left_bottom_grid_pin_15_[0] -to fpga_top/sb_1__0_/chanx_left_out[10] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[4] -to fpga_top/sb_1__0_/chanx_left_out[14] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[15] -to fpga_top/sb_1__0_/chanx_left_out[14] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[26] -to fpga_top/sb_1__0_/chanx_left_out[14] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[14] -to fpga_top/sb_1__0_/chanx_left_out[14] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[28] -to fpga_top/sb_1__0_/chanx_left_out[14] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/left_bottom_grid_pin_5_[0] -to fpga_top/sb_1__0_/chanx_left_out[14] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/left_bottom_grid_pin_17_[0] -to fpga_top/sb_1__0_/chanx_left_out[14] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[3] -to fpga_top/sb_1__0_/chanx_left_out[18] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[14] -to fpga_top/sb_1__0_/chanx_left_out[18] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[25] -to fpga_top/sb_1__0_/chanx_left_out[18] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[15] -to fpga_top/sb_1__0_/chanx_left_out[18] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/left_bottom_grid_pin_7_[0] -to fpga_top/sb_1__0_/chanx_left_out[18] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[2] -to fpga_top/sb_1__0_/chanx_left_out[22] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[13] -to fpga_top/sb_1__0_/chanx_left_out[22] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[24] -to fpga_top/sb_1__0_/chanx_left_out[22] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[16] -to fpga_top/sb_1__0_/chanx_left_out[22] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/left_bottom_grid_pin_9_[0] -to fpga_top/sb_1__0_/chanx_left_out[22] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[1] -to fpga_top/sb_1__0_/chanx_left_out[26] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[12] -to fpga_top/sb_1__0_/chanx_left_out[26] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[23] -to fpga_top/sb_1__0_/chanx_left_out[26] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[18] -to fpga_top/sb_1__0_/chanx_left_out[26] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/left_bottom_grid_pin_11_[0] -to fpga_top/sb_1__0_/chanx_left_out[26] 6.020400151e-11 diff --git a/FPGA1212_RESET_HD_SKY_PNR/FPGA1212_RESET_HD_SKY_Verilog/SDC/sb_1__12_.sdc b/FPGA1212_RESET_HD_SKY_PNR/FPGA1212_RESET_HD_SKY_Verilog/SDC/sb_1__12_.sdc deleted file mode 100644 index 706cc5c..0000000 --- a/FPGA1212_RESET_HD_SKY_PNR/FPGA1212_RESET_HD_SKY_Verilog/SDC/sb_1__12_.sdc +++ /dev/null @@ -1,258 +0,0 @@ -############################################# -# Synopsys Design Constraints (SDC) -# For FPGA fabric -# Description: Constrain timing of Switch Block sb_1__12_ for PnR -# Author: Xifan TANG -# Organization: University of Utah -# Date: Tue Dec 1 18:12:04 2020 -############################################# - -############################################# -# Define time unit -############################################# -set_units -time s - -set_max_delay -from fpga_core_uut/sb_1__12_/right_top_grid_pin_1_[0] -to fpga_top/sb_1__12_/chanx_right_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/right_bottom_grid_pin_38_[0] -to fpga_top/sb_1__12_/chanx_right_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/right_bottom_grid_pin_41_[0] -to fpga_top/sb_1__12_/chanx_right_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[9] -to fpga_top/sb_1__12_/chanx_right_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[20] -to fpga_top/sb_1__12_/chanx_right_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[3] -to fpga_top/sb_1__12_/chanx_right_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[19] -to fpga_top/sb_1__12_/chanx_right_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/right_bottom_grid_pin_36_[0] -to fpga_top/sb_1__12_/chanx_right_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/right_bottom_grid_pin_39_[0] -to fpga_top/sb_1__12_/chanx_right_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/right_bottom_grid_pin_42_[0] -to fpga_top/sb_1__12_/chanx_right_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[8] -to fpga_top/sb_1__12_/chanx_right_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[19] -to fpga_top/sb_1__12_/chanx_right_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[6] -to fpga_top/sb_1__12_/chanx_right_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[20] -to fpga_top/sb_1__12_/chanx_right_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/right_bottom_grid_pin_37_[0] -to fpga_top/sb_1__12_/chanx_right_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/right_bottom_grid_pin_40_[0] -to fpga_top/sb_1__12_/chanx_right_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/right_bottom_grid_pin_43_[0] -to fpga_top/sb_1__12_/chanx_right_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[7] -to fpga_top/sb_1__12_/chanx_right_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[18] -to fpga_top/sb_1__12_/chanx_right_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[29] -to fpga_top/sb_1__12_/chanx_right_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[7] -to fpga_top/sb_1__12_/chanx_right_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[22] -to fpga_top/sb_1__12_/chanx_right_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/right_top_grid_pin_1_[0] -to fpga_top/sb_1__12_/chanx_right_out[3] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/right_bottom_grid_pin_37_[0] -to fpga_top/sb_1__12_/chanx_right_out[3] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/right_bottom_grid_pin_39_[0] -to fpga_top/sb_1__12_/chanx_right_out[3] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/right_bottom_grid_pin_41_[0] -to fpga_top/sb_1__12_/chanx_right_out[3] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/right_bottom_grid_pin_43_[0] -to fpga_top/sb_1__12_/chanx_right_out[3] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[6] -to fpga_top/sb_1__12_/chanx_right_out[3] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[17] -to fpga_top/sb_1__12_/chanx_right_out[3] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[28] -to fpga_top/sb_1__12_/chanx_right_out[3] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[8] -to fpga_top/sb_1__12_/chanx_right_out[3] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[23] -to fpga_top/sb_1__12_/chanx_right_out[3] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/right_bottom_grid_pin_36_[0] -to fpga_top/sb_1__12_/chanx_right_out[5] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/right_bottom_grid_pin_38_[0] -to fpga_top/sb_1__12_/chanx_right_out[5] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/right_bottom_grid_pin_40_[0] -to fpga_top/sb_1__12_/chanx_right_out[5] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/right_bottom_grid_pin_42_[0] -to fpga_top/sb_1__12_/chanx_right_out[5] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[5] -to fpga_top/sb_1__12_/chanx_right_out[5] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[16] -to fpga_top/sb_1__12_/chanx_right_out[5] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[27] -to fpga_top/sb_1__12_/chanx_right_out[5] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[10] -to fpga_top/sb_1__12_/chanx_right_out[5] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[24] -to fpga_top/sb_1__12_/chanx_right_out[5] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/right_top_grid_pin_1_[0] -to fpga_top/sb_1__12_/chanx_right_out[6] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/right_bottom_grid_pin_41_[0] -to fpga_top/sb_1__12_/chanx_right_out[6] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[4] -to fpga_top/sb_1__12_/chanx_right_out[6] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[15] -to fpga_top/sb_1__12_/chanx_right_out[6] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[26] -to fpga_top/sb_1__12_/chanx_right_out[6] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[11] -to fpga_top/sb_1__12_/chanx_right_out[6] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[26] -to fpga_top/sb_1__12_/chanx_right_out[6] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/right_bottom_grid_pin_36_[0] -to fpga_top/sb_1__12_/chanx_right_out[10] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/right_bottom_grid_pin_42_[0] -to fpga_top/sb_1__12_/chanx_right_out[10] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[3] -to fpga_top/sb_1__12_/chanx_right_out[10] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[14] -to fpga_top/sb_1__12_/chanx_right_out[10] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[25] -to fpga_top/sb_1__12_/chanx_right_out[10] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[12] -to fpga_top/sb_1__12_/chanx_right_out[10] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[27] -to fpga_top/sb_1__12_/chanx_right_out[10] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/right_bottom_grid_pin_37_[0] -to fpga_top/sb_1__12_/chanx_right_out[14] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/right_bottom_grid_pin_43_[0] -to fpga_top/sb_1__12_/chanx_right_out[14] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[2] -to fpga_top/sb_1__12_/chanx_right_out[14] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[13] -to fpga_top/sb_1__12_/chanx_right_out[14] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[24] -to fpga_top/sb_1__12_/chanx_right_out[14] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[14] -to fpga_top/sb_1__12_/chanx_right_out[14] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[28] -to fpga_top/sb_1__12_/chanx_right_out[14] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/right_bottom_grid_pin_38_[0] -to fpga_top/sb_1__12_/chanx_right_out[18] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[1] -to fpga_top/sb_1__12_/chanx_right_out[18] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[12] -to fpga_top/sb_1__12_/chanx_right_out[18] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[23] -to fpga_top/sb_1__12_/chanx_right_out[18] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[15] -to fpga_top/sb_1__12_/chanx_right_out[18] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/right_bottom_grid_pin_39_[0] -to fpga_top/sb_1__12_/chanx_right_out[22] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[0] -to fpga_top/sb_1__12_/chanx_right_out[22] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[11] -to fpga_top/sb_1__12_/chanx_right_out[22] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[22] -to fpga_top/sb_1__12_/chanx_right_out[22] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[16] -to fpga_top/sb_1__12_/chanx_right_out[22] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/right_bottom_grid_pin_40_[0] -to fpga_top/sb_1__12_/chanx_right_out[26] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[10] -to fpga_top/sb_1__12_/chanx_right_out[26] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[21] -to fpga_top/sb_1__12_/chanx_right_out[26] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[18] -to fpga_top/sb_1__12_/chanx_right_out[26] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[3] -to fpga_top/sb_1__12_/chany_bottom_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/bottom_left_grid_pin_44_[0] -to fpga_top/sb_1__12_/chany_bottom_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/bottom_left_grid_pin_47_[0] -to fpga_top/sb_1__12_/chany_bottom_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/bottom_left_grid_pin_50_[0] -to fpga_top/sb_1__12_/chany_bottom_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[1] -to fpga_top/sb_1__12_/chany_bottom_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[3] -to fpga_top/sb_1__12_/chany_bottom_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[6] -to fpga_top/sb_1__12_/chany_bottom_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/bottom_left_grid_pin_45_[0] -to fpga_top/sb_1__12_/chany_bottom_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/bottom_left_grid_pin_48_[0] -to fpga_top/sb_1__12_/chany_bottom_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/bottom_left_grid_pin_51_[0] -to fpga_top/sb_1__12_/chany_bottom_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[2] -to fpga_top/sb_1__12_/chany_bottom_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[6] -to fpga_top/sb_1__12_/chany_bottom_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[7] -to fpga_top/sb_1__12_/chany_bottom_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/bottom_left_grid_pin_46_[0] -to fpga_top/sb_1__12_/chany_bottom_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/bottom_left_grid_pin_49_[0] -to fpga_top/sb_1__12_/chany_bottom_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[4] -to fpga_top/sb_1__12_/chany_bottom_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[7] -to fpga_top/sb_1__12_/chany_bottom_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[8] -to fpga_top/sb_1__12_/chany_bottom_out[3] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/bottom_left_grid_pin_44_[0] -to fpga_top/sb_1__12_/chany_bottom_out[3] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/bottom_left_grid_pin_47_[0] -to fpga_top/sb_1__12_/chany_bottom_out[3] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/bottom_left_grid_pin_50_[0] -to fpga_top/sb_1__12_/chany_bottom_out[3] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[5] -to fpga_top/sb_1__12_/chany_bottom_out[3] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[8] -to fpga_top/sb_1__12_/chany_bottom_out[3] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[10] -to fpga_top/sb_1__12_/chany_bottom_out[4] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/bottom_left_grid_pin_45_[0] -to fpga_top/sb_1__12_/chany_bottom_out[4] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/bottom_left_grid_pin_48_[0] -to fpga_top/sb_1__12_/chany_bottom_out[4] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/bottom_left_grid_pin_51_[0] -to fpga_top/sb_1__12_/chany_bottom_out[4] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[9] -to fpga_top/sb_1__12_/chany_bottom_out[4] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[10] -to fpga_top/sb_1__12_/chany_bottom_out[4] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[11] -to fpga_top/sb_1__12_/chany_bottom_out[5] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/bottom_left_grid_pin_46_[0] -to fpga_top/sb_1__12_/chany_bottom_out[5] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/bottom_left_grid_pin_49_[0] -to fpga_top/sb_1__12_/chany_bottom_out[5] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[11] -to fpga_top/sb_1__12_/chany_bottom_out[5] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[13] -to fpga_top/sb_1__12_/chany_bottom_out[5] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[12] -to fpga_top/sb_1__12_/chany_bottom_out[6] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/bottom_left_grid_pin_44_[0] -to fpga_top/sb_1__12_/chany_bottom_out[6] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[12] -to fpga_top/sb_1__12_/chany_bottom_out[6] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[17] -to fpga_top/sb_1__12_/chany_bottom_out[6] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[14] -to fpga_top/sb_1__12_/chany_bottom_out[7] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/bottom_left_grid_pin_45_[0] -to fpga_top/sb_1__12_/chany_bottom_out[7] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[14] -to fpga_top/sb_1__12_/chany_bottom_out[7] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[21] -to fpga_top/sb_1__12_/chany_bottom_out[7] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[15] -to fpga_top/sb_1__12_/chany_bottom_out[8] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/bottom_left_grid_pin_46_[0] -to fpga_top/sb_1__12_/chany_bottom_out[8] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[15] -to fpga_top/sb_1__12_/chany_bottom_out[8] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[25] -to fpga_top/sb_1__12_/chany_bottom_out[8] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[16] -to fpga_top/sb_1__12_/chany_bottom_out[9] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/bottom_left_grid_pin_47_[0] -to fpga_top/sb_1__12_/chany_bottom_out[9] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[16] -to fpga_top/sb_1__12_/chany_bottom_out[9] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[29] -to fpga_top/sb_1__12_/chany_bottom_out[9] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[18] -to fpga_top/sb_1__12_/chany_bottom_out[10] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/bottom_left_grid_pin_48_[0] -to fpga_top/sb_1__12_/chany_bottom_out[10] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[18] -to fpga_top/sb_1__12_/chany_bottom_out[10] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[19] -to fpga_top/sb_1__12_/chany_bottom_out[11] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/bottom_left_grid_pin_49_[0] -to fpga_top/sb_1__12_/chany_bottom_out[11] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[19] -to fpga_top/sb_1__12_/chany_bottom_out[11] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[20] -to fpga_top/sb_1__12_/chany_bottom_out[12] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/bottom_left_grid_pin_50_[0] -to fpga_top/sb_1__12_/chany_bottom_out[12] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[20] -to fpga_top/sb_1__12_/chany_bottom_out[12] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[22] -to fpga_top/sb_1__12_/chany_bottom_out[13] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/bottom_left_grid_pin_51_[0] -to fpga_top/sb_1__12_/chany_bottom_out[13] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[22] -to fpga_top/sb_1__12_/chany_bottom_out[13] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[23] -to fpga_top/sb_1__12_/chany_bottom_out[14] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[23] -to fpga_top/sb_1__12_/chany_bottom_out[14] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[24] -to fpga_top/sb_1__12_/chany_bottom_out[15] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[24] -to fpga_top/sb_1__12_/chany_bottom_out[15] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[26] -to fpga_top/sb_1__12_/chany_bottom_out[16] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[26] -to fpga_top/sb_1__12_/chany_bottom_out[16] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[27] -to fpga_top/sb_1__12_/chany_bottom_out[17] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[27] -to fpga_top/sb_1__12_/chany_bottom_out[17] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[28] -to fpga_top/sb_1__12_/chany_bottom_out[18] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[29] -to fpga_top/sb_1__12_/chany_bottom_out[18] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/bottom_left_grid_pin_44_[0] -to fpga_top/sb_1__12_/chany_bottom_out[18] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[28] -to fpga_top/sb_1__12_/chany_bottom_out[18] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[25] -to fpga_top/sb_1__12_/chany_bottom_out[19] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/bottom_left_grid_pin_45_[0] -to fpga_top/sb_1__12_/chany_bottom_out[19] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[21] -to fpga_top/sb_1__12_/chany_bottom_out[20] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/bottom_left_grid_pin_46_[0] -to fpga_top/sb_1__12_/chany_bottom_out[20] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[17] -to fpga_top/sb_1__12_/chany_bottom_out[21] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/bottom_left_grid_pin_47_[0] -to fpga_top/sb_1__12_/chany_bottom_out[21] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[13] -to fpga_top/sb_1__12_/chany_bottom_out[22] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/bottom_left_grid_pin_48_[0] -to fpga_top/sb_1__12_/chany_bottom_out[22] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[9] -to fpga_top/sb_1__12_/chany_bottom_out[23] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/bottom_left_grid_pin_49_[0] -to fpga_top/sb_1__12_/chany_bottom_out[23] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[5] -to fpga_top/sb_1__12_/chany_bottom_out[24] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/bottom_left_grid_pin_50_[0] -to fpga_top/sb_1__12_/chany_bottom_out[24] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[4] -to fpga_top/sb_1__12_/chany_bottom_out[25] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/bottom_left_grid_pin_51_[0] -to fpga_top/sb_1__12_/chany_bottom_out[25] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[2] -to fpga_top/sb_1__12_/chany_bottom_out[26] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[1] -to fpga_top/sb_1__12_/chany_bottom_out[27] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[0] -to fpga_top/sb_1__12_/chany_bottom_out[28] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[0] -to fpga_top/sb_1__12_/chany_bottom_out[29] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[3] -to fpga_top/sb_1__12_/chanx_left_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[19] -to fpga_top/sb_1__12_/chanx_left_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[10] -to fpga_top/sb_1__12_/chanx_left_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[21] -to fpga_top/sb_1__12_/chanx_left_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/left_top_grid_pin_1_[0] -to fpga_top/sb_1__12_/chanx_left_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/left_bottom_grid_pin_38_[0] -to fpga_top/sb_1__12_/chanx_left_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/left_bottom_grid_pin_41_[0] -to fpga_top/sb_1__12_/chanx_left_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[6] -to fpga_top/sb_1__12_/chanx_left_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[20] -to fpga_top/sb_1__12_/chanx_left_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[0] -to fpga_top/sb_1__12_/chanx_left_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[11] -to fpga_top/sb_1__12_/chanx_left_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[22] -to fpga_top/sb_1__12_/chanx_left_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/left_bottom_grid_pin_36_[0] -to fpga_top/sb_1__12_/chanx_left_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/left_bottom_grid_pin_39_[0] -to fpga_top/sb_1__12_/chanx_left_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/left_bottom_grid_pin_42_[0] -to fpga_top/sb_1__12_/chanx_left_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[7] -to fpga_top/sb_1__12_/chanx_left_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[22] -to fpga_top/sb_1__12_/chanx_left_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[1] -to fpga_top/sb_1__12_/chanx_left_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[12] -to fpga_top/sb_1__12_/chanx_left_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[23] -to fpga_top/sb_1__12_/chanx_left_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/left_bottom_grid_pin_37_[0] -to fpga_top/sb_1__12_/chanx_left_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/left_bottom_grid_pin_40_[0] -to fpga_top/sb_1__12_/chanx_left_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/left_bottom_grid_pin_43_[0] -to fpga_top/sb_1__12_/chanx_left_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[8] -to fpga_top/sb_1__12_/chanx_left_out[3] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[23] -to fpga_top/sb_1__12_/chanx_left_out[3] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[2] -to fpga_top/sb_1__12_/chanx_left_out[3] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[13] -to fpga_top/sb_1__12_/chanx_left_out[3] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[24] -to fpga_top/sb_1__12_/chanx_left_out[3] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/left_top_grid_pin_1_[0] -to fpga_top/sb_1__12_/chanx_left_out[3] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/left_bottom_grid_pin_37_[0] -to fpga_top/sb_1__12_/chanx_left_out[3] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/left_bottom_grid_pin_39_[0] -to fpga_top/sb_1__12_/chanx_left_out[3] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/left_bottom_grid_pin_41_[0] -to fpga_top/sb_1__12_/chanx_left_out[3] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/left_bottom_grid_pin_43_[0] -to fpga_top/sb_1__12_/chanx_left_out[3] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[10] -to fpga_top/sb_1__12_/chanx_left_out[5] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[24] -to fpga_top/sb_1__12_/chanx_left_out[5] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[3] -to fpga_top/sb_1__12_/chanx_left_out[5] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[14] -to fpga_top/sb_1__12_/chanx_left_out[5] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[25] -to fpga_top/sb_1__12_/chanx_left_out[5] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/left_bottom_grid_pin_36_[0] -to fpga_top/sb_1__12_/chanx_left_out[5] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/left_bottom_grid_pin_38_[0] -to fpga_top/sb_1__12_/chanx_left_out[5] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/left_bottom_grid_pin_40_[0] -to fpga_top/sb_1__12_/chanx_left_out[5] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/left_bottom_grid_pin_42_[0] -to fpga_top/sb_1__12_/chanx_left_out[5] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[11] -to fpga_top/sb_1__12_/chanx_left_out[6] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[26] -to fpga_top/sb_1__12_/chanx_left_out[6] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[4] -to fpga_top/sb_1__12_/chanx_left_out[6] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[15] -to fpga_top/sb_1__12_/chanx_left_out[6] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[26] -to fpga_top/sb_1__12_/chanx_left_out[6] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/left_top_grid_pin_1_[0] -to fpga_top/sb_1__12_/chanx_left_out[6] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/left_bottom_grid_pin_41_[0] -to fpga_top/sb_1__12_/chanx_left_out[6] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[12] -to fpga_top/sb_1__12_/chanx_left_out[10] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[27] -to fpga_top/sb_1__12_/chanx_left_out[10] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[5] -to fpga_top/sb_1__12_/chanx_left_out[10] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[16] -to fpga_top/sb_1__12_/chanx_left_out[10] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[27] -to fpga_top/sb_1__12_/chanx_left_out[10] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/left_bottom_grid_pin_36_[0] -to fpga_top/sb_1__12_/chanx_left_out[10] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/left_bottom_grid_pin_42_[0] -to fpga_top/sb_1__12_/chanx_left_out[10] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[14] -to fpga_top/sb_1__12_/chanx_left_out[14] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[28] -to fpga_top/sb_1__12_/chanx_left_out[14] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[6] -to fpga_top/sb_1__12_/chanx_left_out[14] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[17] -to fpga_top/sb_1__12_/chanx_left_out[14] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[28] -to fpga_top/sb_1__12_/chanx_left_out[14] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/left_bottom_grid_pin_37_[0] -to fpga_top/sb_1__12_/chanx_left_out[14] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/left_bottom_grid_pin_43_[0] -to fpga_top/sb_1__12_/chanx_left_out[14] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[15] -to fpga_top/sb_1__12_/chanx_left_out[18] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[7] -to fpga_top/sb_1__12_/chanx_left_out[18] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[18] -to fpga_top/sb_1__12_/chanx_left_out[18] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[29] -to fpga_top/sb_1__12_/chanx_left_out[18] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/left_bottom_grid_pin_38_[0] -to fpga_top/sb_1__12_/chanx_left_out[18] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[16] -to fpga_top/sb_1__12_/chanx_left_out[22] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[8] -to fpga_top/sb_1__12_/chanx_left_out[22] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[19] -to fpga_top/sb_1__12_/chanx_left_out[22] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/left_bottom_grid_pin_39_[0] -to fpga_top/sb_1__12_/chanx_left_out[22] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[18] -to fpga_top/sb_1__12_/chanx_left_out[26] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[9] -to fpga_top/sb_1__12_/chanx_left_out[26] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[20] -to fpga_top/sb_1__12_/chanx_left_out[26] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/left_bottom_grid_pin_40_[0] -to fpga_top/sb_1__12_/chanx_left_out[26] 6.020400151e-11 diff --git a/FPGA1212_RESET_HD_SKY_PNR/FPGA1212_RESET_HD_SKY_Verilog/SDC/sb_1__1_.sdc b/FPGA1212_RESET_HD_SKY_PNR/FPGA1212_RESET_HD_SKY_Verilog/SDC/sb_1__1_.sdc deleted file mode 100644 index 95fb09a..0000000 --- a/FPGA1212_RESET_HD_SKY_PNR/FPGA1212_RESET_HD_SKY_Verilog/SDC/sb_1__1_.sdc +++ /dev/null @@ -1,426 +0,0 @@ -############################################# -# Synopsys Design Constraints (SDC) -# For FPGA fabric -# Description: Constrain timing of Switch Block sb_1__1_ for PnR -# Author: Xifan TANG -# Organization: University of Utah -# Date: Tue Dec 1 18:12:04 2020 -############################################# - -############################################# -# Define time unit -############################################# -set_units -time s - -set_max_delay -from fpga_core_uut/sb_1__1_/top_left_grid_pin_44_[0] -to fpga_top/sb_1__1_/chany_top_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/top_left_grid_pin_47_[0] -to fpga_top/sb_1__1_/chany_top_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/top_left_grid_pin_50_[0] -to fpga_top/sb_1__1_/chany_top_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[1] -to fpga_top/sb_1__1_/chany_top_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[3] -to fpga_top/sb_1__1_/chany_top_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[19] -to fpga_top/sb_1__1_/chany_top_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[3] -to fpga_top/sb_1__1_/chany_top_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[19] -to fpga_top/sb_1__1_/chany_top_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[0] -to fpga_top/sb_1__1_/chany_top_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[3] -to fpga_top/sb_1__1_/chany_top_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[19] -to fpga_top/sb_1__1_/chany_top_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/top_left_grid_pin_45_[0] -to fpga_top/sb_1__1_/chany_top_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/top_left_grid_pin_48_[0] -to fpga_top/sb_1__1_/chany_top_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/top_left_grid_pin_51_[0] -to fpga_top/sb_1__1_/chany_top_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[2] -to fpga_top/sb_1__1_/chany_top_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[6] -to fpga_top/sb_1__1_/chany_top_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[20] -to fpga_top/sb_1__1_/chany_top_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[6] -to fpga_top/sb_1__1_/chany_top_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[20] -to fpga_top/sb_1__1_/chany_top_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[6] -to fpga_top/sb_1__1_/chany_top_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[20] -to fpga_top/sb_1__1_/chany_top_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[29] -to fpga_top/sb_1__1_/chany_top_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/top_left_grid_pin_46_[0] -to fpga_top/sb_1__1_/chany_top_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/top_left_grid_pin_49_[0] -to fpga_top/sb_1__1_/chany_top_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[4] -to fpga_top/sb_1__1_/chany_top_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[7] -to fpga_top/sb_1__1_/chany_top_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[22] -to fpga_top/sb_1__1_/chany_top_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[7] -to fpga_top/sb_1__1_/chany_top_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[22] -to fpga_top/sb_1__1_/chany_top_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[7] -to fpga_top/sb_1__1_/chany_top_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[22] -to fpga_top/sb_1__1_/chany_top_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[25] -to fpga_top/sb_1__1_/chany_top_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/top_left_grid_pin_44_[0] -to fpga_top/sb_1__1_/chany_top_out[3] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/top_left_grid_pin_46_[0] -to fpga_top/sb_1__1_/chany_top_out[3] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/top_left_grid_pin_48_[0] -to fpga_top/sb_1__1_/chany_top_out[3] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/top_left_grid_pin_50_[0] -to fpga_top/sb_1__1_/chany_top_out[3] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[5] -to fpga_top/sb_1__1_/chany_top_out[3] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[8] -to fpga_top/sb_1__1_/chany_top_out[3] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[23] -to fpga_top/sb_1__1_/chany_top_out[3] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[8] -to fpga_top/sb_1__1_/chany_top_out[3] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[23] -to fpga_top/sb_1__1_/chany_top_out[3] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[8] -to fpga_top/sb_1__1_/chany_top_out[3] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[21] -to fpga_top/sb_1__1_/chany_top_out[3] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[23] -to fpga_top/sb_1__1_/chany_top_out[3] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/top_left_grid_pin_45_[0] -to fpga_top/sb_1__1_/chany_top_out[5] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/top_left_grid_pin_47_[0] -to fpga_top/sb_1__1_/chany_top_out[5] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/top_left_grid_pin_49_[0] -to fpga_top/sb_1__1_/chany_top_out[5] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/top_left_grid_pin_51_[0] -to fpga_top/sb_1__1_/chany_top_out[5] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[9] -to fpga_top/sb_1__1_/chany_top_out[5] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[10] -to fpga_top/sb_1__1_/chany_top_out[5] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[24] -to fpga_top/sb_1__1_/chany_top_out[5] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[10] -to fpga_top/sb_1__1_/chany_top_out[5] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[24] -to fpga_top/sb_1__1_/chany_top_out[5] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[10] -to fpga_top/sb_1__1_/chany_top_out[5] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[17] -to fpga_top/sb_1__1_/chany_top_out[5] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[24] -to fpga_top/sb_1__1_/chany_top_out[5] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/top_left_grid_pin_44_[0] -to fpga_top/sb_1__1_/chany_top_out[6] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/top_left_grid_pin_50_[0] -to fpga_top/sb_1__1_/chany_top_out[6] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[11] -to fpga_top/sb_1__1_/chany_top_out[6] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[13] -to fpga_top/sb_1__1_/chany_top_out[6] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[26] -to fpga_top/sb_1__1_/chany_top_out[6] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[11] -to fpga_top/sb_1__1_/chany_top_out[6] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[26] -to fpga_top/sb_1__1_/chany_top_out[6] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[11] -to fpga_top/sb_1__1_/chany_top_out[6] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[13] -to fpga_top/sb_1__1_/chany_top_out[6] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[26] -to fpga_top/sb_1__1_/chany_top_out[6] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/top_left_grid_pin_45_[0] -to fpga_top/sb_1__1_/chany_top_out[10] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/top_left_grid_pin_51_[0] -to fpga_top/sb_1__1_/chany_top_out[10] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[12] -to fpga_top/sb_1__1_/chany_top_out[10] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[17] -to fpga_top/sb_1__1_/chany_top_out[10] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[27] -to fpga_top/sb_1__1_/chany_top_out[10] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[12] -to fpga_top/sb_1__1_/chany_top_out[10] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[27] -to fpga_top/sb_1__1_/chany_top_out[10] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[9] -to fpga_top/sb_1__1_/chany_top_out[10] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[12] -to fpga_top/sb_1__1_/chany_top_out[10] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[27] -to fpga_top/sb_1__1_/chany_top_out[10] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/top_left_grid_pin_46_[0] -to fpga_top/sb_1__1_/chany_top_out[14] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[14] -to fpga_top/sb_1__1_/chany_top_out[14] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[21] -to fpga_top/sb_1__1_/chany_top_out[14] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[28] -to fpga_top/sb_1__1_/chany_top_out[14] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[14] -to fpga_top/sb_1__1_/chany_top_out[14] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[28] -to fpga_top/sb_1__1_/chany_top_out[14] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[5] -to fpga_top/sb_1__1_/chany_top_out[14] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[14] -to fpga_top/sb_1__1_/chany_top_out[14] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[28] -to fpga_top/sb_1__1_/chany_top_out[14] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/top_left_grid_pin_47_[0] -to fpga_top/sb_1__1_/chany_top_out[18] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[15] -to fpga_top/sb_1__1_/chany_top_out[18] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[25] -to fpga_top/sb_1__1_/chany_top_out[18] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[15] -to fpga_top/sb_1__1_/chany_top_out[18] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[4] -to fpga_top/sb_1__1_/chany_top_out[18] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[15] -to fpga_top/sb_1__1_/chany_top_out[18] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/top_left_grid_pin_48_[0] -to fpga_top/sb_1__1_/chany_top_out[22] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[16] -to fpga_top/sb_1__1_/chany_top_out[22] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[29] -to fpga_top/sb_1__1_/chany_top_out[22] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[16] -to fpga_top/sb_1__1_/chany_top_out[22] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[2] -to fpga_top/sb_1__1_/chany_top_out[22] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[16] -to fpga_top/sb_1__1_/chany_top_out[22] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/top_left_grid_pin_49_[0] -to fpga_top/sb_1__1_/chany_top_out[26] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[0] -to fpga_top/sb_1__1_/chany_top_out[26] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[18] -to fpga_top/sb_1__1_/chany_top_out[26] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[18] -to fpga_top/sb_1__1_/chany_top_out[26] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[1] -to fpga_top/sb_1__1_/chany_top_out[26] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[18] -to fpga_top/sb_1__1_/chany_top_out[26] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[3] -to fpga_top/sb_1__1_/chanx_right_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[19] -to fpga_top/sb_1__1_/chanx_right_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[29] -to fpga_top/sb_1__1_/chanx_right_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/right_bottom_grid_pin_36_[0] -to fpga_top/sb_1__1_/chanx_right_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/right_bottom_grid_pin_39_[0] -to fpga_top/sb_1__1_/chanx_right_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/right_bottom_grid_pin_42_[0] -to fpga_top/sb_1__1_/chanx_right_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[3] -to fpga_top/sb_1__1_/chanx_right_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[19] -to fpga_top/sb_1__1_/chanx_right_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[25] -to fpga_top/sb_1__1_/chanx_right_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[3] -to fpga_top/sb_1__1_/chanx_right_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[19] -to fpga_top/sb_1__1_/chanx_right_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[0] -to fpga_top/sb_1__1_/chanx_right_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[6] -to fpga_top/sb_1__1_/chanx_right_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[20] -to fpga_top/sb_1__1_/chanx_right_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/right_bottom_grid_pin_37_[0] -to fpga_top/sb_1__1_/chanx_right_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/right_bottom_grid_pin_40_[0] -to fpga_top/sb_1__1_/chanx_right_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/right_bottom_grid_pin_43_[0] -to fpga_top/sb_1__1_/chanx_right_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[6] -to fpga_top/sb_1__1_/chanx_right_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[20] -to fpga_top/sb_1__1_/chanx_right_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[21] -to fpga_top/sb_1__1_/chanx_right_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[6] -to fpga_top/sb_1__1_/chanx_right_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[20] -to fpga_top/sb_1__1_/chanx_right_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[1] -to fpga_top/sb_1__1_/chanx_right_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[7] -to fpga_top/sb_1__1_/chanx_right_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[22] -to fpga_top/sb_1__1_/chanx_right_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/right_bottom_grid_pin_38_[0] -to fpga_top/sb_1__1_/chanx_right_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/right_bottom_grid_pin_41_[0] -to fpga_top/sb_1__1_/chanx_right_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[7] -to fpga_top/sb_1__1_/chanx_right_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[17] -to fpga_top/sb_1__1_/chanx_right_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[22] -to fpga_top/sb_1__1_/chanx_right_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[7] -to fpga_top/sb_1__1_/chanx_right_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[22] -to fpga_top/sb_1__1_/chanx_right_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[2] -to fpga_top/sb_1__1_/chanx_right_out[3] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[8] -to fpga_top/sb_1__1_/chanx_right_out[3] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[23] -to fpga_top/sb_1__1_/chanx_right_out[3] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/right_bottom_grid_pin_36_[0] -to fpga_top/sb_1__1_/chanx_right_out[3] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/right_bottom_grid_pin_38_[0] -to fpga_top/sb_1__1_/chanx_right_out[3] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/right_bottom_grid_pin_40_[0] -to fpga_top/sb_1__1_/chanx_right_out[3] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/right_bottom_grid_pin_42_[0] -to fpga_top/sb_1__1_/chanx_right_out[3] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[8] -to fpga_top/sb_1__1_/chanx_right_out[3] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[13] -to fpga_top/sb_1__1_/chanx_right_out[3] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[23] -to fpga_top/sb_1__1_/chanx_right_out[3] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[8] -to fpga_top/sb_1__1_/chanx_right_out[3] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[23] -to fpga_top/sb_1__1_/chanx_right_out[3] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[4] -to fpga_top/sb_1__1_/chanx_right_out[5] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[10] -to fpga_top/sb_1__1_/chanx_right_out[5] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[24] -to fpga_top/sb_1__1_/chanx_right_out[5] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/right_bottom_grid_pin_37_[0] -to fpga_top/sb_1__1_/chanx_right_out[5] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/right_bottom_grid_pin_39_[0] -to fpga_top/sb_1__1_/chanx_right_out[5] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/right_bottom_grid_pin_41_[0] -to fpga_top/sb_1__1_/chanx_right_out[5] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/right_bottom_grid_pin_43_[0] -to fpga_top/sb_1__1_/chanx_right_out[5] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[9] -to fpga_top/sb_1__1_/chanx_right_out[5] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[10] -to fpga_top/sb_1__1_/chanx_right_out[5] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[24] -to fpga_top/sb_1__1_/chanx_right_out[5] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[10] -to fpga_top/sb_1__1_/chanx_right_out[5] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[24] -to fpga_top/sb_1__1_/chanx_right_out[5] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[5] -to fpga_top/sb_1__1_/chanx_right_out[6] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[11] -to fpga_top/sb_1__1_/chanx_right_out[6] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[26] -to fpga_top/sb_1__1_/chanx_right_out[6] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/right_bottom_grid_pin_36_[0] -to fpga_top/sb_1__1_/chanx_right_out[6] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/right_bottom_grid_pin_42_[0] -to fpga_top/sb_1__1_/chanx_right_out[6] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[5] -to fpga_top/sb_1__1_/chanx_right_out[6] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[11] -to fpga_top/sb_1__1_/chanx_right_out[6] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[26] -to fpga_top/sb_1__1_/chanx_right_out[6] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[11] -to fpga_top/sb_1__1_/chanx_right_out[6] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[26] -to fpga_top/sb_1__1_/chanx_right_out[6] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[9] -to fpga_top/sb_1__1_/chanx_right_out[10] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[12] -to fpga_top/sb_1__1_/chanx_right_out[10] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[27] -to fpga_top/sb_1__1_/chanx_right_out[10] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/right_bottom_grid_pin_37_[0] -to fpga_top/sb_1__1_/chanx_right_out[10] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/right_bottom_grid_pin_43_[0] -to fpga_top/sb_1__1_/chanx_right_out[10] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[4] -to fpga_top/sb_1__1_/chanx_right_out[10] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[12] -to fpga_top/sb_1__1_/chanx_right_out[10] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[27] -to fpga_top/sb_1__1_/chanx_right_out[10] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[12] -to fpga_top/sb_1__1_/chanx_right_out[10] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[27] -to fpga_top/sb_1__1_/chanx_right_out[10] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[13] -to fpga_top/sb_1__1_/chanx_right_out[14] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[14] -to fpga_top/sb_1__1_/chanx_right_out[14] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[28] -to fpga_top/sb_1__1_/chanx_right_out[14] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/right_bottom_grid_pin_38_[0] -to fpga_top/sb_1__1_/chanx_right_out[14] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[2] -to fpga_top/sb_1__1_/chanx_right_out[14] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[14] -to fpga_top/sb_1__1_/chanx_right_out[14] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[28] -to fpga_top/sb_1__1_/chanx_right_out[14] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[14] -to fpga_top/sb_1__1_/chanx_right_out[14] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[28] -to fpga_top/sb_1__1_/chanx_right_out[14] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[15] -to fpga_top/sb_1__1_/chanx_right_out[18] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[17] -to fpga_top/sb_1__1_/chanx_right_out[18] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/right_bottom_grid_pin_39_[0] -to fpga_top/sb_1__1_/chanx_right_out[18] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[1] -to fpga_top/sb_1__1_/chanx_right_out[18] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[15] -to fpga_top/sb_1__1_/chanx_right_out[18] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[15] -to fpga_top/sb_1__1_/chanx_right_out[18] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[16] -to fpga_top/sb_1__1_/chanx_right_out[22] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[21] -to fpga_top/sb_1__1_/chanx_right_out[22] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/right_bottom_grid_pin_40_[0] -to fpga_top/sb_1__1_/chanx_right_out[22] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[0] -to fpga_top/sb_1__1_/chanx_right_out[22] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[16] -to fpga_top/sb_1__1_/chanx_right_out[22] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[16] -to fpga_top/sb_1__1_/chanx_right_out[22] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[18] -to fpga_top/sb_1__1_/chanx_right_out[26] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[25] -to fpga_top/sb_1__1_/chanx_right_out[26] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/right_bottom_grid_pin_41_[0] -to fpga_top/sb_1__1_/chanx_right_out[26] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[18] -to fpga_top/sb_1__1_/chanx_right_out[26] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[29] -to fpga_top/sb_1__1_/chanx_right_out[26] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[18] -to fpga_top/sb_1__1_/chanx_right_out[26] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[3] -to fpga_top/sb_1__1_/chany_bottom_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[19] -to fpga_top/sb_1__1_/chany_bottom_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[3] -to fpga_top/sb_1__1_/chany_bottom_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[19] -to fpga_top/sb_1__1_/chany_bottom_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[25] -to fpga_top/sb_1__1_/chany_bottom_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/bottom_left_grid_pin_44_[0] -to fpga_top/sb_1__1_/chany_bottom_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/bottom_left_grid_pin_47_[0] -to fpga_top/sb_1__1_/chany_bottom_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/bottom_left_grid_pin_50_[0] -to fpga_top/sb_1__1_/chany_bottom_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[1] -to fpga_top/sb_1__1_/chany_bottom_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[3] -to fpga_top/sb_1__1_/chany_bottom_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[19] -to fpga_top/sb_1__1_/chany_bottom_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[6] -to fpga_top/sb_1__1_/chany_bottom_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[20] -to fpga_top/sb_1__1_/chany_bottom_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[6] -to fpga_top/sb_1__1_/chany_bottom_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[20] -to fpga_top/sb_1__1_/chany_bottom_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[21] -to fpga_top/sb_1__1_/chany_bottom_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/bottom_left_grid_pin_45_[0] -to fpga_top/sb_1__1_/chany_bottom_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/bottom_left_grid_pin_48_[0] -to fpga_top/sb_1__1_/chany_bottom_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/bottom_left_grid_pin_51_[0] -to fpga_top/sb_1__1_/chany_bottom_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[2] -to fpga_top/sb_1__1_/chany_bottom_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[6] -to fpga_top/sb_1__1_/chany_bottom_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[20] -to fpga_top/sb_1__1_/chany_bottom_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[7] -to fpga_top/sb_1__1_/chany_bottom_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[22] -to fpga_top/sb_1__1_/chany_bottom_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[7] -to fpga_top/sb_1__1_/chany_bottom_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[17] -to fpga_top/sb_1__1_/chany_bottom_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[22] -to fpga_top/sb_1__1_/chany_bottom_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/bottom_left_grid_pin_46_[0] -to fpga_top/sb_1__1_/chany_bottom_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/bottom_left_grid_pin_49_[0] -to fpga_top/sb_1__1_/chany_bottom_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[4] -to fpga_top/sb_1__1_/chany_bottom_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[7] -to fpga_top/sb_1__1_/chany_bottom_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[22] -to fpga_top/sb_1__1_/chany_bottom_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[8] -to fpga_top/sb_1__1_/chany_bottom_out[3] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[23] -to fpga_top/sb_1__1_/chany_bottom_out[3] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[8] -to fpga_top/sb_1__1_/chany_bottom_out[3] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[13] -to fpga_top/sb_1__1_/chany_bottom_out[3] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[23] -to fpga_top/sb_1__1_/chany_bottom_out[3] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/bottom_left_grid_pin_44_[0] -to fpga_top/sb_1__1_/chany_bottom_out[3] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/bottom_left_grid_pin_46_[0] -to fpga_top/sb_1__1_/chany_bottom_out[3] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/bottom_left_grid_pin_48_[0] -to fpga_top/sb_1__1_/chany_bottom_out[3] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/bottom_left_grid_pin_50_[0] -to fpga_top/sb_1__1_/chany_bottom_out[3] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[5] -to fpga_top/sb_1__1_/chany_bottom_out[3] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[8] -to fpga_top/sb_1__1_/chany_bottom_out[3] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[23] -to fpga_top/sb_1__1_/chany_bottom_out[3] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[10] -to fpga_top/sb_1__1_/chany_bottom_out[5] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[24] -to fpga_top/sb_1__1_/chany_bottom_out[5] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[9] -to fpga_top/sb_1__1_/chany_bottom_out[5] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[10] -to fpga_top/sb_1__1_/chany_bottom_out[5] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[24] -to fpga_top/sb_1__1_/chany_bottom_out[5] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/bottom_left_grid_pin_45_[0] -to fpga_top/sb_1__1_/chany_bottom_out[5] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/bottom_left_grid_pin_47_[0] -to fpga_top/sb_1__1_/chany_bottom_out[5] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/bottom_left_grid_pin_49_[0] -to fpga_top/sb_1__1_/chany_bottom_out[5] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/bottom_left_grid_pin_51_[0] -to fpga_top/sb_1__1_/chany_bottom_out[5] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[9] -to fpga_top/sb_1__1_/chany_bottom_out[5] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[10] -to fpga_top/sb_1__1_/chany_bottom_out[5] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[24] -to fpga_top/sb_1__1_/chany_bottom_out[5] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[11] -to fpga_top/sb_1__1_/chany_bottom_out[6] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[26] -to fpga_top/sb_1__1_/chany_bottom_out[6] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[5] -to fpga_top/sb_1__1_/chany_bottom_out[6] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[11] -to fpga_top/sb_1__1_/chany_bottom_out[6] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[26] -to fpga_top/sb_1__1_/chany_bottom_out[6] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/bottom_left_grid_pin_44_[0] -to fpga_top/sb_1__1_/chany_bottom_out[6] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/bottom_left_grid_pin_50_[0] -to fpga_top/sb_1__1_/chany_bottom_out[6] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[11] -to fpga_top/sb_1__1_/chany_bottom_out[6] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[13] -to fpga_top/sb_1__1_/chany_bottom_out[6] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[26] -to fpga_top/sb_1__1_/chany_bottom_out[6] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[12] -to fpga_top/sb_1__1_/chany_bottom_out[10] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[27] -to fpga_top/sb_1__1_/chany_bottom_out[10] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[4] -to fpga_top/sb_1__1_/chany_bottom_out[10] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[12] -to fpga_top/sb_1__1_/chany_bottom_out[10] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[27] -to fpga_top/sb_1__1_/chany_bottom_out[10] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/bottom_left_grid_pin_45_[0] -to fpga_top/sb_1__1_/chany_bottom_out[10] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/bottom_left_grid_pin_51_[0] -to fpga_top/sb_1__1_/chany_bottom_out[10] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[12] -to fpga_top/sb_1__1_/chany_bottom_out[10] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[17] -to fpga_top/sb_1__1_/chany_bottom_out[10] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[27] -to fpga_top/sb_1__1_/chany_bottom_out[10] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[14] -to fpga_top/sb_1__1_/chany_bottom_out[14] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[28] -to fpga_top/sb_1__1_/chany_bottom_out[14] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[2] -to fpga_top/sb_1__1_/chany_bottom_out[14] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[14] -to fpga_top/sb_1__1_/chany_bottom_out[14] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[28] -to fpga_top/sb_1__1_/chany_bottom_out[14] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/bottom_left_grid_pin_46_[0] -to fpga_top/sb_1__1_/chany_bottom_out[14] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[14] -to fpga_top/sb_1__1_/chany_bottom_out[14] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[21] -to fpga_top/sb_1__1_/chany_bottom_out[14] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[28] -to fpga_top/sb_1__1_/chany_bottom_out[14] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[15] -to fpga_top/sb_1__1_/chany_bottom_out[18] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[1] -to fpga_top/sb_1__1_/chany_bottom_out[18] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[15] -to fpga_top/sb_1__1_/chany_bottom_out[18] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/bottom_left_grid_pin_47_[0] -to fpga_top/sb_1__1_/chany_bottom_out[18] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[15] -to fpga_top/sb_1__1_/chany_bottom_out[18] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[25] -to fpga_top/sb_1__1_/chany_bottom_out[18] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[16] -to fpga_top/sb_1__1_/chany_bottom_out[22] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[0] -to fpga_top/sb_1__1_/chany_bottom_out[22] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[16] -to fpga_top/sb_1__1_/chany_bottom_out[22] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/bottom_left_grid_pin_48_[0] -to fpga_top/sb_1__1_/chany_bottom_out[22] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[16] -to fpga_top/sb_1__1_/chany_bottom_out[22] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[29] -to fpga_top/sb_1__1_/chany_bottom_out[22] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[18] -to fpga_top/sb_1__1_/chany_bottom_out[26] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[18] -to fpga_top/sb_1__1_/chany_bottom_out[26] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[29] -to fpga_top/sb_1__1_/chany_bottom_out[26] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/bottom_left_grid_pin_49_[0] -to fpga_top/sb_1__1_/chany_bottom_out[26] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[0] -to fpga_top/sb_1__1_/chany_bottom_out[26] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[18] -to fpga_top/sb_1__1_/chany_bottom_out[26] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[0] -to fpga_top/sb_1__1_/chanx_left_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[3] -to fpga_top/sb_1__1_/chanx_left_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[19] -to fpga_top/sb_1__1_/chanx_left_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[3] -to fpga_top/sb_1__1_/chanx_left_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[19] -to fpga_top/sb_1__1_/chanx_left_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[3] -to fpga_top/sb_1__1_/chanx_left_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[19] -to fpga_top/sb_1__1_/chanx_left_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[29] -to fpga_top/sb_1__1_/chanx_left_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/left_bottom_grid_pin_36_[0] -to fpga_top/sb_1__1_/chanx_left_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/left_bottom_grid_pin_39_[0] -to fpga_top/sb_1__1_/chanx_left_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/left_bottom_grid_pin_42_[0] -to fpga_top/sb_1__1_/chanx_left_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[6] -to fpga_top/sb_1__1_/chanx_left_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[20] -to fpga_top/sb_1__1_/chanx_left_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[29] -to fpga_top/sb_1__1_/chanx_left_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[6] -to fpga_top/sb_1__1_/chanx_left_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[20] -to fpga_top/sb_1__1_/chanx_left_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[0] -to fpga_top/sb_1__1_/chanx_left_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[6] -to fpga_top/sb_1__1_/chanx_left_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[20] -to fpga_top/sb_1__1_/chanx_left_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/left_bottom_grid_pin_37_[0] -to fpga_top/sb_1__1_/chanx_left_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/left_bottom_grid_pin_40_[0] -to fpga_top/sb_1__1_/chanx_left_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/left_bottom_grid_pin_43_[0] -to fpga_top/sb_1__1_/chanx_left_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[7] -to fpga_top/sb_1__1_/chanx_left_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[22] -to fpga_top/sb_1__1_/chanx_left_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[25] -to fpga_top/sb_1__1_/chanx_left_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[7] -to fpga_top/sb_1__1_/chanx_left_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[22] -to fpga_top/sb_1__1_/chanx_left_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[1] -to fpga_top/sb_1__1_/chanx_left_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[7] -to fpga_top/sb_1__1_/chanx_left_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[22] -to fpga_top/sb_1__1_/chanx_left_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/left_bottom_grid_pin_38_[0] -to fpga_top/sb_1__1_/chanx_left_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/left_bottom_grid_pin_41_[0] -to fpga_top/sb_1__1_/chanx_left_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[8] -to fpga_top/sb_1__1_/chanx_left_out[3] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[21] -to fpga_top/sb_1__1_/chanx_left_out[3] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[23] -to fpga_top/sb_1__1_/chanx_left_out[3] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[8] -to fpga_top/sb_1__1_/chanx_left_out[3] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[23] -to fpga_top/sb_1__1_/chanx_left_out[3] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[2] -to fpga_top/sb_1__1_/chanx_left_out[3] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[8] -to fpga_top/sb_1__1_/chanx_left_out[3] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[23] -to fpga_top/sb_1__1_/chanx_left_out[3] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/left_bottom_grid_pin_36_[0] -to fpga_top/sb_1__1_/chanx_left_out[3] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/left_bottom_grid_pin_38_[0] -to fpga_top/sb_1__1_/chanx_left_out[3] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/left_bottom_grid_pin_40_[0] -to fpga_top/sb_1__1_/chanx_left_out[3] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/left_bottom_grid_pin_42_[0] -to fpga_top/sb_1__1_/chanx_left_out[3] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[10] -to fpga_top/sb_1__1_/chanx_left_out[5] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[17] -to fpga_top/sb_1__1_/chanx_left_out[5] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[24] -to fpga_top/sb_1__1_/chanx_left_out[5] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[10] -to fpga_top/sb_1__1_/chanx_left_out[5] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[24] -to fpga_top/sb_1__1_/chanx_left_out[5] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[4] -to fpga_top/sb_1__1_/chanx_left_out[5] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[10] -to fpga_top/sb_1__1_/chanx_left_out[5] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[24] -to fpga_top/sb_1__1_/chanx_left_out[5] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/left_bottom_grid_pin_37_[0] -to fpga_top/sb_1__1_/chanx_left_out[5] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/left_bottom_grid_pin_39_[0] -to fpga_top/sb_1__1_/chanx_left_out[5] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/left_bottom_grid_pin_41_[0] -to fpga_top/sb_1__1_/chanx_left_out[5] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/left_bottom_grid_pin_43_[0] -to fpga_top/sb_1__1_/chanx_left_out[5] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[11] -to fpga_top/sb_1__1_/chanx_left_out[6] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[13] -to fpga_top/sb_1__1_/chanx_left_out[6] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[26] -to fpga_top/sb_1__1_/chanx_left_out[6] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[11] -to fpga_top/sb_1__1_/chanx_left_out[6] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[26] -to fpga_top/sb_1__1_/chanx_left_out[6] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[5] -to fpga_top/sb_1__1_/chanx_left_out[6] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[11] -to fpga_top/sb_1__1_/chanx_left_out[6] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[26] -to fpga_top/sb_1__1_/chanx_left_out[6] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/left_bottom_grid_pin_36_[0] -to fpga_top/sb_1__1_/chanx_left_out[6] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/left_bottom_grid_pin_42_[0] -to fpga_top/sb_1__1_/chanx_left_out[6] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[9] -to fpga_top/sb_1__1_/chanx_left_out[10] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[12] -to fpga_top/sb_1__1_/chanx_left_out[10] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[27] -to fpga_top/sb_1__1_/chanx_left_out[10] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[12] -to fpga_top/sb_1__1_/chanx_left_out[10] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[27] -to fpga_top/sb_1__1_/chanx_left_out[10] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[9] -to fpga_top/sb_1__1_/chanx_left_out[10] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[12] -to fpga_top/sb_1__1_/chanx_left_out[10] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[27] -to fpga_top/sb_1__1_/chanx_left_out[10] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/left_bottom_grid_pin_37_[0] -to fpga_top/sb_1__1_/chanx_left_out[10] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/left_bottom_grid_pin_43_[0] -to fpga_top/sb_1__1_/chanx_left_out[10] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[5] -to fpga_top/sb_1__1_/chanx_left_out[14] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[14] -to fpga_top/sb_1__1_/chanx_left_out[14] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[28] -to fpga_top/sb_1__1_/chanx_left_out[14] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[14] -to fpga_top/sb_1__1_/chanx_left_out[14] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[28] -to fpga_top/sb_1__1_/chanx_left_out[14] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[13] -to fpga_top/sb_1__1_/chanx_left_out[14] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[14] -to fpga_top/sb_1__1_/chanx_left_out[14] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[28] -to fpga_top/sb_1__1_/chanx_left_out[14] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/left_bottom_grid_pin_38_[0] -to fpga_top/sb_1__1_/chanx_left_out[14] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[4] -to fpga_top/sb_1__1_/chanx_left_out[18] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[15] -to fpga_top/sb_1__1_/chanx_left_out[18] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[15] -to fpga_top/sb_1__1_/chanx_left_out[18] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[15] -to fpga_top/sb_1__1_/chanx_left_out[18] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[17] -to fpga_top/sb_1__1_/chanx_left_out[18] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/left_bottom_grid_pin_39_[0] -to fpga_top/sb_1__1_/chanx_left_out[18] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[2] -to fpga_top/sb_1__1_/chanx_left_out[22] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[16] -to fpga_top/sb_1__1_/chanx_left_out[22] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[16] -to fpga_top/sb_1__1_/chanx_left_out[22] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[16] -to fpga_top/sb_1__1_/chanx_left_out[22] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[21] -to fpga_top/sb_1__1_/chanx_left_out[22] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/left_bottom_grid_pin_40_[0] -to fpga_top/sb_1__1_/chanx_left_out[22] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[1] -to fpga_top/sb_1__1_/chanx_left_out[26] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[18] -to fpga_top/sb_1__1_/chanx_left_out[26] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[18] -to fpga_top/sb_1__1_/chanx_left_out[26] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[18] -to fpga_top/sb_1__1_/chanx_left_out[26] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[25] -to fpga_top/sb_1__1_/chanx_left_out[26] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/left_bottom_grid_pin_41_[0] -to fpga_top/sb_1__1_/chanx_left_out[26] 6.020400151e-11 diff --git a/FPGA1212_SOFA_CHD_PNR/FPGA1212_SOFA_CHD_Verilog/OpenFPGAEngine.info b/FPGA1212_SOFA_CHD_PNR/FPGA1212_SOFA_CHD_Verilog/OpenFPGAEngine.info index cfb0ff6..3a82e59 100644 --- a/FPGA1212_SOFA_CHD_PNR/FPGA1212_SOFA_CHD_Verilog/OpenFPGAEngine.info +++ b/FPGA1212_SOFA_CHD_PNR/FPGA1212_SOFA_CHD_Verilog/OpenFPGAEngine.info @@ -48,6 +48,7 @@ Untracked files: openfpga_flow/tasks/FPGA1212_FC_HD_SKY_task openfpga_flow/tasks/FPGA1212_FLAT_HD_SKY_task openfpga_flow/tasks/FPGA1212_HIER_SKY_SC_MS_task + openfpga_flow/tasks/FPGA1212_QLSOFA_HD_task openfpga_flow/tasks/FPGA1212_RESET_HD_SKY_task openfpga_flow/tasks/FPGA1212_SOFA_CHD_task openfpga_flow/tasks/FPGA128128_FLAT_task diff --git a/FPGA1212_SOFA_CHD_PNR/FPGA1212_SOFA_CHD_Verilog/SDC/cbx_1__0_.sdc b/FPGA1212_SOFA_CHD_PNR/FPGA1212_SOFA_CHD_Verilog/SDC/cbx_1__0_.sdc deleted file mode 100644 index 1c13b5d..0000000 --- a/FPGA1212_SOFA_CHD_PNR/FPGA1212_SOFA_CHD_Verilog/SDC/cbx_1__0_.sdc +++ /dev/null @@ -1,182 +0,0 @@ -############################################# -# Synopsys Design Constraints (SDC) -# For FPGA fabric -# Description: Constrain timing of Connection Block cbx_1__0_ for PnR -# Author: Xifan TANG -# Organization: University of Utah -# Date: Tue Dec 8 15:34:14 2020 -############################################# - -############################################# -# Define time unit -############################################# -set_units -time s - -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[0] -to fpga_top/cbx_1__0_/chanx_left_out[0] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[0] -to fpga_top/cbx_1__0_/chanx_right_out[0] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[1] -to fpga_top/cbx_1__0_/chanx_left_out[1] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[1] -to fpga_top/cbx_1__0_/chanx_right_out[1] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[2] -to fpga_top/cbx_1__0_/chanx_left_out[2] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[2] -to fpga_top/cbx_1__0_/chanx_right_out[2] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[3] -to fpga_top/cbx_1__0_/chanx_left_out[3] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[3] -to fpga_top/cbx_1__0_/chanx_right_out[3] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[4] -to fpga_top/cbx_1__0_/chanx_left_out[4] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[4] -to fpga_top/cbx_1__0_/chanx_right_out[4] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[5] -to fpga_top/cbx_1__0_/chanx_left_out[5] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[5] -to fpga_top/cbx_1__0_/chanx_right_out[5] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[6] -to fpga_top/cbx_1__0_/chanx_left_out[6] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[6] -to fpga_top/cbx_1__0_/chanx_right_out[6] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[7] -to fpga_top/cbx_1__0_/chanx_left_out[7] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[7] -to fpga_top/cbx_1__0_/chanx_right_out[7] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[8] -to fpga_top/cbx_1__0_/chanx_left_out[8] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[8] -to fpga_top/cbx_1__0_/chanx_right_out[8] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[9] -to fpga_top/cbx_1__0_/chanx_left_out[9] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[9] -to fpga_top/cbx_1__0_/chanx_right_out[9] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[10] -to fpga_top/cbx_1__0_/chanx_left_out[10] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[10] -to fpga_top/cbx_1__0_/chanx_right_out[10] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[11] -to fpga_top/cbx_1__0_/chanx_left_out[11] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[11] -to fpga_top/cbx_1__0_/chanx_right_out[11] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[12] -to fpga_top/cbx_1__0_/chanx_left_out[12] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[12] -to fpga_top/cbx_1__0_/chanx_right_out[12] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[13] -to fpga_top/cbx_1__0_/chanx_left_out[13] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[13] -to fpga_top/cbx_1__0_/chanx_right_out[13] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[14] -to fpga_top/cbx_1__0_/chanx_left_out[14] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[14] -to fpga_top/cbx_1__0_/chanx_right_out[14] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[15] -to fpga_top/cbx_1__0_/chanx_left_out[15] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[15] -to fpga_top/cbx_1__0_/chanx_right_out[15] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[16] -to fpga_top/cbx_1__0_/chanx_left_out[16] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[16] -to fpga_top/cbx_1__0_/chanx_right_out[16] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[17] -to fpga_top/cbx_1__0_/chanx_left_out[17] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[17] -to fpga_top/cbx_1__0_/chanx_right_out[17] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[18] -to fpga_top/cbx_1__0_/chanx_left_out[18] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[18] -to fpga_top/cbx_1__0_/chanx_right_out[18] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[19] -to fpga_top/cbx_1__0_/chanx_left_out[19] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[19] -to fpga_top/cbx_1__0_/chanx_right_out[19] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[20] -to fpga_top/cbx_1__0_/chanx_left_out[20] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[20] -to fpga_top/cbx_1__0_/chanx_right_out[20] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[21] -to fpga_top/cbx_1__0_/chanx_left_out[21] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[21] -to fpga_top/cbx_1__0_/chanx_right_out[21] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[22] -to fpga_top/cbx_1__0_/chanx_left_out[22] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[22] -to fpga_top/cbx_1__0_/chanx_right_out[22] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[23] -to fpga_top/cbx_1__0_/chanx_left_out[23] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[23] -to fpga_top/cbx_1__0_/chanx_right_out[23] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[24] -to fpga_top/cbx_1__0_/chanx_left_out[24] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[24] -to fpga_top/cbx_1__0_/chanx_right_out[24] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[25] -to fpga_top/cbx_1__0_/chanx_left_out[25] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[25] -to fpga_top/cbx_1__0_/chanx_right_out[25] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[26] -to fpga_top/cbx_1__0_/chanx_left_out[26] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[26] -to fpga_top/cbx_1__0_/chanx_right_out[26] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[27] -to fpga_top/cbx_1__0_/chanx_left_out[27] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[27] -to fpga_top/cbx_1__0_/chanx_right_out[27] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[28] -to fpga_top/cbx_1__0_/chanx_left_out[28] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[28] -to fpga_top/cbx_1__0_/chanx_right_out[28] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[29] -to fpga_top/cbx_1__0_/chanx_left_out[29] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[29] -to fpga_top/cbx_1__0_/chanx_right_out[29] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[0] -to fpga_top/cbx_1__0_/bottom_grid_pin_0_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[0] -to fpga_top/cbx_1__0_/bottom_grid_pin_0_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[3] -to fpga_top/cbx_1__0_/bottom_grid_pin_0_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[3] -to fpga_top/cbx_1__0_/bottom_grid_pin_0_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[6] -to fpga_top/cbx_1__0_/bottom_grid_pin_0_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[6] -to fpga_top/cbx_1__0_/bottom_grid_pin_0_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[12] -to fpga_top/cbx_1__0_/bottom_grid_pin_0_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[12] -to fpga_top/cbx_1__0_/bottom_grid_pin_0_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[18] -to fpga_top/cbx_1__0_/bottom_grid_pin_0_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[18] -to fpga_top/cbx_1__0_/bottom_grid_pin_0_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[24] -to fpga_top/cbx_1__0_/bottom_grid_pin_0_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[24] -to fpga_top/cbx_1__0_/bottom_grid_pin_0_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[1] -to fpga_top/cbx_1__0_/bottom_grid_pin_2_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[1] -to fpga_top/cbx_1__0_/bottom_grid_pin_2_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[4] -to fpga_top/cbx_1__0_/bottom_grid_pin_2_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[4] -to fpga_top/cbx_1__0_/bottom_grid_pin_2_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[7] -to fpga_top/cbx_1__0_/bottom_grid_pin_2_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[7] -to fpga_top/cbx_1__0_/bottom_grid_pin_2_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[13] -to fpga_top/cbx_1__0_/bottom_grid_pin_2_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[13] -to fpga_top/cbx_1__0_/bottom_grid_pin_2_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[19] -to fpga_top/cbx_1__0_/bottom_grid_pin_2_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[19] -to fpga_top/cbx_1__0_/bottom_grid_pin_2_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[25] -to fpga_top/cbx_1__0_/bottom_grid_pin_2_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[25] -to fpga_top/cbx_1__0_/bottom_grid_pin_2_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[2] -to fpga_top/cbx_1__0_/bottom_grid_pin_4_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[2] -to fpga_top/cbx_1__0_/bottom_grid_pin_4_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[5] -to fpga_top/cbx_1__0_/bottom_grid_pin_4_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[5] -to fpga_top/cbx_1__0_/bottom_grid_pin_4_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[8] -to fpga_top/cbx_1__0_/bottom_grid_pin_4_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[8] -to fpga_top/cbx_1__0_/bottom_grid_pin_4_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[14] -to fpga_top/cbx_1__0_/bottom_grid_pin_4_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[14] -to fpga_top/cbx_1__0_/bottom_grid_pin_4_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[20] -to fpga_top/cbx_1__0_/bottom_grid_pin_4_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[20] -to fpga_top/cbx_1__0_/bottom_grid_pin_4_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[26] -to fpga_top/cbx_1__0_/bottom_grid_pin_4_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[26] -to fpga_top/cbx_1__0_/bottom_grid_pin_4_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[0] -to fpga_top/cbx_1__0_/bottom_grid_pin_6_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[0] -to fpga_top/cbx_1__0_/bottom_grid_pin_6_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[3] -to fpga_top/cbx_1__0_/bottom_grid_pin_6_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[3] -to fpga_top/cbx_1__0_/bottom_grid_pin_6_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[9] -to fpga_top/cbx_1__0_/bottom_grid_pin_6_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[9] -to fpga_top/cbx_1__0_/bottom_grid_pin_6_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[15] -to fpga_top/cbx_1__0_/bottom_grid_pin_6_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[15] -to fpga_top/cbx_1__0_/bottom_grid_pin_6_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[21] -to fpga_top/cbx_1__0_/bottom_grid_pin_6_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[21] -to fpga_top/cbx_1__0_/bottom_grid_pin_6_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[27] -to fpga_top/cbx_1__0_/bottom_grid_pin_6_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[27] -to fpga_top/cbx_1__0_/bottom_grid_pin_6_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[1] -to fpga_top/cbx_1__0_/bottom_grid_pin_8_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[1] -to fpga_top/cbx_1__0_/bottom_grid_pin_8_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[4] -to fpga_top/cbx_1__0_/bottom_grid_pin_8_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[4] -to fpga_top/cbx_1__0_/bottom_grid_pin_8_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[10] -to fpga_top/cbx_1__0_/bottom_grid_pin_8_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[10] -to fpga_top/cbx_1__0_/bottom_grid_pin_8_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[16] -to fpga_top/cbx_1__0_/bottom_grid_pin_8_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[16] -to fpga_top/cbx_1__0_/bottom_grid_pin_8_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[22] -to fpga_top/cbx_1__0_/bottom_grid_pin_8_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[22] -to fpga_top/cbx_1__0_/bottom_grid_pin_8_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[28] -to fpga_top/cbx_1__0_/bottom_grid_pin_8_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[28] -to fpga_top/cbx_1__0_/bottom_grid_pin_8_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[2] -to fpga_top/cbx_1__0_/bottom_grid_pin_10_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[2] -to fpga_top/cbx_1__0_/bottom_grid_pin_10_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[5] -to fpga_top/cbx_1__0_/bottom_grid_pin_10_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[5] -to fpga_top/cbx_1__0_/bottom_grid_pin_10_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[11] -to fpga_top/cbx_1__0_/bottom_grid_pin_10_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[11] -to fpga_top/cbx_1__0_/bottom_grid_pin_10_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[17] -to fpga_top/cbx_1__0_/bottom_grid_pin_10_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[17] -to fpga_top/cbx_1__0_/bottom_grid_pin_10_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[23] -to fpga_top/cbx_1__0_/bottom_grid_pin_10_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[23] -to fpga_top/cbx_1__0_/bottom_grid_pin_10_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[29] -to fpga_top/cbx_1__0_/bottom_grid_pin_10_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[29] -to fpga_top/cbx_1__0_/bottom_grid_pin_10_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[0] -to fpga_top/cbx_1__0_/bottom_grid_pin_12_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[0] -to fpga_top/cbx_1__0_/bottom_grid_pin_12_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[3] -to fpga_top/cbx_1__0_/bottom_grid_pin_12_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[3] -to fpga_top/cbx_1__0_/bottom_grid_pin_12_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[6] -to fpga_top/cbx_1__0_/bottom_grid_pin_12_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[6] -to fpga_top/cbx_1__0_/bottom_grid_pin_12_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[12] -to fpga_top/cbx_1__0_/bottom_grid_pin_12_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[12] -to fpga_top/cbx_1__0_/bottom_grid_pin_12_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[18] -to fpga_top/cbx_1__0_/bottom_grid_pin_12_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[18] -to fpga_top/cbx_1__0_/bottom_grid_pin_12_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[24] -to fpga_top/cbx_1__0_/bottom_grid_pin_12_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[24] -to fpga_top/cbx_1__0_/bottom_grid_pin_12_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[1] -to fpga_top/cbx_1__0_/bottom_grid_pin_14_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[1] -to fpga_top/cbx_1__0_/bottom_grid_pin_14_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[4] -to fpga_top/cbx_1__0_/bottom_grid_pin_14_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[4] -to fpga_top/cbx_1__0_/bottom_grid_pin_14_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[7] -to fpga_top/cbx_1__0_/bottom_grid_pin_14_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[7] -to fpga_top/cbx_1__0_/bottom_grid_pin_14_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[13] -to fpga_top/cbx_1__0_/bottom_grid_pin_14_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[13] -to fpga_top/cbx_1__0_/bottom_grid_pin_14_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[19] -to fpga_top/cbx_1__0_/bottom_grid_pin_14_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[19] -to fpga_top/cbx_1__0_/bottom_grid_pin_14_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[25] -to fpga_top/cbx_1__0_/bottom_grid_pin_14_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[25] -to fpga_top/cbx_1__0_/bottom_grid_pin_14_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[2] -to fpga_top/cbx_1__0_/bottom_grid_pin_16_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[2] -to fpga_top/cbx_1__0_/bottom_grid_pin_16_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[5] -to fpga_top/cbx_1__0_/bottom_grid_pin_16_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[5] -to fpga_top/cbx_1__0_/bottom_grid_pin_16_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[8] -to fpga_top/cbx_1__0_/bottom_grid_pin_16_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[8] -to fpga_top/cbx_1__0_/bottom_grid_pin_16_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[14] -to fpga_top/cbx_1__0_/bottom_grid_pin_16_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[14] -to fpga_top/cbx_1__0_/bottom_grid_pin_16_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[20] -to fpga_top/cbx_1__0_/bottom_grid_pin_16_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[20] -to fpga_top/cbx_1__0_/bottom_grid_pin_16_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[26] -to fpga_top/cbx_1__0_/bottom_grid_pin_16_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[26] -to fpga_top/cbx_1__0_/bottom_grid_pin_16_[0] 7.247000222e-11 diff --git a/FPGA1212_SOFA_CHD_PNR/FPGA1212_SOFA_CHD_Verilog/SDC/cbx_1__12_.sdc b/FPGA1212_SOFA_CHD_PNR/FPGA1212_SOFA_CHD_Verilog/SDC/cbx_1__12_.sdc deleted file mode 100644 index 2ec03c8..0000000 --- a/FPGA1212_SOFA_CHD_PNR/FPGA1212_SOFA_CHD_Verilog/SDC/cbx_1__12_.sdc +++ /dev/null @@ -1,262 +0,0 @@ -############################################# -# Synopsys Design Constraints (SDC) -# For FPGA fabric -# Description: Constrain timing of Connection Block cbx_1__12_ for PnR -# Author: Xifan TANG -# Organization: University of Utah -# Date: Tue Dec 8 15:34:14 2020 -############################################# - -############################################# -# Define time unit -############################################# -set_units -time s - -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[0] -to fpga_top/cbx_1__12_/chanx_left_out[0] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[0] -to fpga_top/cbx_1__12_/chanx_right_out[0] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[1] -to fpga_top/cbx_1__12_/chanx_left_out[1] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[1] -to fpga_top/cbx_1__12_/chanx_right_out[1] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[2] -to fpga_top/cbx_1__12_/chanx_left_out[2] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[2] -to fpga_top/cbx_1__12_/chanx_right_out[2] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[3] -to fpga_top/cbx_1__12_/chanx_left_out[3] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[3] -to fpga_top/cbx_1__12_/chanx_right_out[3] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[4] -to fpga_top/cbx_1__12_/chanx_left_out[4] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[4] -to fpga_top/cbx_1__12_/chanx_right_out[4] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[5] -to fpga_top/cbx_1__12_/chanx_left_out[5] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[5] -to fpga_top/cbx_1__12_/chanx_right_out[5] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[6] -to fpga_top/cbx_1__12_/chanx_left_out[6] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[6] -to fpga_top/cbx_1__12_/chanx_right_out[6] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[7] -to fpga_top/cbx_1__12_/chanx_left_out[7] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[7] -to fpga_top/cbx_1__12_/chanx_right_out[7] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[8] -to fpga_top/cbx_1__12_/chanx_left_out[8] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[8] -to fpga_top/cbx_1__12_/chanx_right_out[8] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[9] -to fpga_top/cbx_1__12_/chanx_left_out[9] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[9] -to fpga_top/cbx_1__12_/chanx_right_out[9] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[10] -to fpga_top/cbx_1__12_/chanx_left_out[10] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[10] -to fpga_top/cbx_1__12_/chanx_right_out[10] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[11] -to fpga_top/cbx_1__12_/chanx_left_out[11] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[11] -to fpga_top/cbx_1__12_/chanx_right_out[11] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[12] -to fpga_top/cbx_1__12_/chanx_left_out[12] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[12] -to fpga_top/cbx_1__12_/chanx_right_out[12] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[13] -to fpga_top/cbx_1__12_/chanx_left_out[13] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[13] -to fpga_top/cbx_1__12_/chanx_right_out[13] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[14] -to fpga_top/cbx_1__12_/chanx_left_out[14] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[14] -to fpga_top/cbx_1__12_/chanx_right_out[14] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[15] -to fpga_top/cbx_1__12_/chanx_left_out[15] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[15] -to fpga_top/cbx_1__12_/chanx_right_out[15] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[16] -to fpga_top/cbx_1__12_/chanx_left_out[16] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[16] -to fpga_top/cbx_1__12_/chanx_right_out[16] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[17] -to fpga_top/cbx_1__12_/chanx_left_out[17] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[17] -to fpga_top/cbx_1__12_/chanx_right_out[17] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[18] -to fpga_top/cbx_1__12_/chanx_left_out[18] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[18] -to fpga_top/cbx_1__12_/chanx_right_out[18] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[19] -to fpga_top/cbx_1__12_/chanx_left_out[19] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[19] -to fpga_top/cbx_1__12_/chanx_right_out[19] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[20] -to fpga_top/cbx_1__12_/chanx_left_out[20] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[20] -to fpga_top/cbx_1__12_/chanx_right_out[20] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[21] -to fpga_top/cbx_1__12_/chanx_left_out[21] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[21] -to fpga_top/cbx_1__12_/chanx_right_out[21] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[22] -to fpga_top/cbx_1__12_/chanx_left_out[22] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[22] -to fpga_top/cbx_1__12_/chanx_right_out[22] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[23] -to fpga_top/cbx_1__12_/chanx_left_out[23] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[23] -to fpga_top/cbx_1__12_/chanx_right_out[23] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[24] -to fpga_top/cbx_1__12_/chanx_left_out[24] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[24] -to fpga_top/cbx_1__12_/chanx_right_out[24] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[25] -to fpga_top/cbx_1__12_/chanx_left_out[25] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[25] -to fpga_top/cbx_1__12_/chanx_right_out[25] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[26] -to fpga_top/cbx_1__12_/chanx_left_out[26] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[26] -to fpga_top/cbx_1__12_/chanx_right_out[26] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[27] -to fpga_top/cbx_1__12_/chanx_left_out[27] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[27] -to fpga_top/cbx_1__12_/chanx_right_out[27] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[28] -to fpga_top/cbx_1__12_/chanx_left_out[28] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[28] -to fpga_top/cbx_1__12_/chanx_right_out[28] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[29] -to fpga_top/cbx_1__12_/chanx_left_out[29] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[29] -to fpga_top/cbx_1__12_/chanx_right_out[29] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[0] -to fpga_top/cbx_1__12_/top_grid_pin_0_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[0] -to fpga_top/cbx_1__12_/top_grid_pin_0_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[3] -to fpga_top/cbx_1__12_/top_grid_pin_0_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[3] -to fpga_top/cbx_1__12_/top_grid_pin_0_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[6] -to fpga_top/cbx_1__12_/top_grid_pin_0_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[6] -to fpga_top/cbx_1__12_/top_grid_pin_0_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[12] -to fpga_top/cbx_1__12_/top_grid_pin_0_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[12] -to fpga_top/cbx_1__12_/top_grid_pin_0_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[18] -to fpga_top/cbx_1__12_/top_grid_pin_0_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[18] -to fpga_top/cbx_1__12_/top_grid_pin_0_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[24] -to fpga_top/cbx_1__12_/top_grid_pin_0_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[24] -to fpga_top/cbx_1__12_/top_grid_pin_0_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[1] -to fpga_top/cbx_1__12_/bottom_grid_pin_0_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[1] -to fpga_top/cbx_1__12_/bottom_grid_pin_0_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[4] -to fpga_top/cbx_1__12_/bottom_grid_pin_0_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[4] -to fpga_top/cbx_1__12_/bottom_grid_pin_0_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[7] -to fpga_top/cbx_1__12_/bottom_grid_pin_0_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[7] -to fpga_top/cbx_1__12_/bottom_grid_pin_0_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[13] -to fpga_top/cbx_1__12_/bottom_grid_pin_0_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[13] -to fpga_top/cbx_1__12_/bottom_grid_pin_0_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[19] -to fpga_top/cbx_1__12_/bottom_grid_pin_0_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[19] -to fpga_top/cbx_1__12_/bottom_grid_pin_0_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[25] -to fpga_top/cbx_1__12_/bottom_grid_pin_0_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[25] -to fpga_top/cbx_1__12_/bottom_grid_pin_0_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[2] -to fpga_top/cbx_1__12_/bottom_grid_pin_1_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[2] -to fpga_top/cbx_1__12_/bottom_grid_pin_1_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[5] -to fpga_top/cbx_1__12_/bottom_grid_pin_1_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[5] -to fpga_top/cbx_1__12_/bottom_grid_pin_1_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[8] -to fpga_top/cbx_1__12_/bottom_grid_pin_1_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[8] -to fpga_top/cbx_1__12_/bottom_grid_pin_1_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[17] -to fpga_top/cbx_1__12_/bottom_grid_pin_1_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[17] -to fpga_top/cbx_1__12_/bottom_grid_pin_1_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[26] -to fpga_top/cbx_1__12_/bottom_grid_pin_1_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[26] -to fpga_top/cbx_1__12_/bottom_grid_pin_1_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[0] -to fpga_top/cbx_1__12_/bottom_grid_pin_2_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[0] -to fpga_top/cbx_1__12_/bottom_grid_pin_2_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[3] -to fpga_top/cbx_1__12_/bottom_grid_pin_2_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[3] -to fpga_top/cbx_1__12_/bottom_grid_pin_2_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[9] -to fpga_top/cbx_1__12_/bottom_grid_pin_2_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[9] -to fpga_top/cbx_1__12_/bottom_grid_pin_2_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[15] -to fpga_top/cbx_1__12_/bottom_grid_pin_2_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[15] -to fpga_top/cbx_1__12_/bottom_grid_pin_2_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[21] -to fpga_top/cbx_1__12_/bottom_grid_pin_2_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[21] -to fpga_top/cbx_1__12_/bottom_grid_pin_2_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[27] -to fpga_top/cbx_1__12_/bottom_grid_pin_2_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[27] -to fpga_top/cbx_1__12_/bottom_grid_pin_2_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[1] -to fpga_top/cbx_1__12_/bottom_grid_pin_3_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[1] -to fpga_top/cbx_1__12_/bottom_grid_pin_3_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[4] -to fpga_top/cbx_1__12_/bottom_grid_pin_3_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[4] -to fpga_top/cbx_1__12_/bottom_grid_pin_3_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[10] -to fpga_top/cbx_1__12_/bottom_grid_pin_3_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[10] -to fpga_top/cbx_1__12_/bottom_grid_pin_3_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[19] -to fpga_top/cbx_1__12_/bottom_grid_pin_3_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[19] -to fpga_top/cbx_1__12_/bottom_grid_pin_3_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[28] -to fpga_top/cbx_1__12_/bottom_grid_pin_3_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[28] -to fpga_top/cbx_1__12_/bottom_grid_pin_3_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[2] -to fpga_top/cbx_1__12_/bottom_grid_pin_4_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[2] -to fpga_top/cbx_1__12_/bottom_grid_pin_4_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[5] -to fpga_top/cbx_1__12_/bottom_grid_pin_4_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[5] -to fpga_top/cbx_1__12_/bottom_grid_pin_4_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[11] -to fpga_top/cbx_1__12_/bottom_grid_pin_4_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[11] -to fpga_top/cbx_1__12_/bottom_grid_pin_4_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[17] -to fpga_top/cbx_1__12_/bottom_grid_pin_4_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[17] -to fpga_top/cbx_1__12_/bottom_grid_pin_4_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[23] -to fpga_top/cbx_1__12_/bottom_grid_pin_4_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[23] -to fpga_top/cbx_1__12_/bottom_grid_pin_4_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[29] -to fpga_top/cbx_1__12_/bottom_grid_pin_4_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[29] -to fpga_top/cbx_1__12_/bottom_grid_pin_4_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[0] -to fpga_top/cbx_1__12_/bottom_grid_pin_5_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[0] -to fpga_top/cbx_1__12_/bottom_grid_pin_5_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[3] -to fpga_top/cbx_1__12_/bottom_grid_pin_5_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[3] -to fpga_top/cbx_1__12_/bottom_grid_pin_5_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[6] -to fpga_top/cbx_1__12_/bottom_grid_pin_5_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[6] -to fpga_top/cbx_1__12_/bottom_grid_pin_5_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[12] -to fpga_top/cbx_1__12_/bottom_grid_pin_5_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[12] -to fpga_top/cbx_1__12_/bottom_grid_pin_5_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[21] -to fpga_top/cbx_1__12_/bottom_grid_pin_5_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[21] -to fpga_top/cbx_1__12_/bottom_grid_pin_5_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[1] -to fpga_top/cbx_1__12_/bottom_grid_pin_6_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[1] -to fpga_top/cbx_1__12_/bottom_grid_pin_6_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[4] -to fpga_top/cbx_1__12_/bottom_grid_pin_6_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[4] -to fpga_top/cbx_1__12_/bottom_grid_pin_6_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[7] -to fpga_top/cbx_1__12_/bottom_grid_pin_6_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[7] -to fpga_top/cbx_1__12_/bottom_grid_pin_6_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[13] -to fpga_top/cbx_1__12_/bottom_grid_pin_6_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[13] -to fpga_top/cbx_1__12_/bottom_grid_pin_6_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[19] -to fpga_top/cbx_1__12_/bottom_grid_pin_6_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[19] -to fpga_top/cbx_1__12_/bottom_grid_pin_6_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[25] -to fpga_top/cbx_1__12_/bottom_grid_pin_6_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[25] -to fpga_top/cbx_1__12_/bottom_grid_pin_6_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[2] -to fpga_top/cbx_1__12_/bottom_grid_pin_7_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[2] -to fpga_top/cbx_1__12_/bottom_grid_pin_7_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[5] -to fpga_top/cbx_1__12_/bottom_grid_pin_7_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[5] -to fpga_top/cbx_1__12_/bottom_grid_pin_7_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[8] -to fpga_top/cbx_1__12_/bottom_grid_pin_7_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[8] -to fpga_top/cbx_1__12_/bottom_grid_pin_7_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[14] -to fpga_top/cbx_1__12_/bottom_grid_pin_7_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[14] -to fpga_top/cbx_1__12_/bottom_grid_pin_7_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[23] -to fpga_top/cbx_1__12_/bottom_grid_pin_7_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[23] -to fpga_top/cbx_1__12_/bottom_grid_pin_7_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[0] -to fpga_top/cbx_1__12_/bottom_grid_pin_8_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[0] -to fpga_top/cbx_1__12_/bottom_grid_pin_8_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[3] -to fpga_top/cbx_1__12_/bottom_grid_pin_8_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[3] -to fpga_top/cbx_1__12_/bottom_grid_pin_8_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[9] -to fpga_top/cbx_1__12_/bottom_grid_pin_8_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[9] -to fpga_top/cbx_1__12_/bottom_grid_pin_8_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[15] -to fpga_top/cbx_1__12_/bottom_grid_pin_8_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[15] -to fpga_top/cbx_1__12_/bottom_grid_pin_8_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[21] -to fpga_top/cbx_1__12_/bottom_grid_pin_8_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[21] -to fpga_top/cbx_1__12_/bottom_grid_pin_8_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[27] -to fpga_top/cbx_1__12_/bottom_grid_pin_8_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[27] -to fpga_top/cbx_1__12_/bottom_grid_pin_8_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[1] -to fpga_top/cbx_1__12_/bottom_grid_pin_9_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[1] -to fpga_top/cbx_1__12_/bottom_grid_pin_9_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[4] -to fpga_top/cbx_1__12_/bottom_grid_pin_9_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[4] -to fpga_top/cbx_1__12_/bottom_grid_pin_9_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[10] -to fpga_top/cbx_1__12_/bottom_grid_pin_9_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[10] -to fpga_top/cbx_1__12_/bottom_grid_pin_9_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[16] -to fpga_top/cbx_1__12_/bottom_grid_pin_9_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[16] -to fpga_top/cbx_1__12_/bottom_grid_pin_9_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[25] -to fpga_top/cbx_1__12_/bottom_grid_pin_9_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[25] -to fpga_top/cbx_1__12_/bottom_grid_pin_9_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[2] -to fpga_top/cbx_1__12_/bottom_grid_pin_10_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[2] -to fpga_top/cbx_1__12_/bottom_grid_pin_10_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[5] -to fpga_top/cbx_1__12_/bottom_grid_pin_10_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[5] -to fpga_top/cbx_1__12_/bottom_grid_pin_10_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[11] -to fpga_top/cbx_1__12_/bottom_grid_pin_10_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[11] -to fpga_top/cbx_1__12_/bottom_grid_pin_10_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[17] -to fpga_top/cbx_1__12_/bottom_grid_pin_10_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[17] -to fpga_top/cbx_1__12_/bottom_grid_pin_10_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[23] -to fpga_top/cbx_1__12_/bottom_grid_pin_10_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[23] -to fpga_top/cbx_1__12_/bottom_grid_pin_10_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[29] -to fpga_top/cbx_1__12_/bottom_grid_pin_10_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[29] -to fpga_top/cbx_1__12_/bottom_grid_pin_10_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[0] -to fpga_top/cbx_1__12_/bottom_grid_pin_11_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[0] -to fpga_top/cbx_1__12_/bottom_grid_pin_11_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[3] -to fpga_top/cbx_1__12_/bottom_grid_pin_11_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[3] -to fpga_top/cbx_1__12_/bottom_grid_pin_11_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[12] -to fpga_top/cbx_1__12_/bottom_grid_pin_11_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[12] -to fpga_top/cbx_1__12_/bottom_grid_pin_11_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[18] -to fpga_top/cbx_1__12_/bottom_grid_pin_11_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[18] -to fpga_top/cbx_1__12_/bottom_grid_pin_11_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[27] -to fpga_top/cbx_1__12_/bottom_grid_pin_11_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[27] -to fpga_top/cbx_1__12_/bottom_grid_pin_11_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[1] -to fpga_top/cbx_1__12_/bottom_grid_pin_12_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[1] -to fpga_top/cbx_1__12_/bottom_grid_pin_12_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[4] -to fpga_top/cbx_1__12_/bottom_grid_pin_12_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[4] -to fpga_top/cbx_1__12_/bottom_grid_pin_12_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[7] -to fpga_top/cbx_1__12_/bottom_grid_pin_12_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[7] -to fpga_top/cbx_1__12_/bottom_grid_pin_12_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[13] -to fpga_top/cbx_1__12_/bottom_grid_pin_12_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[13] -to fpga_top/cbx_1__12_/bottom_grid_pin_12_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[19] -to fpga_top/cbx_1__12_/bottom_grid_pin_12_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[19] -to fpga_top/cbx_1__12_/bottom_grid_pin_12_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[25] -to fpga_top/cbx_1__12_/bottom_grid_pin_12_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[25] -to fpga_top/cbx_1__12_/bottom_grid_pin_12_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[2] -to fpga_top/cbx_1__12_/bottom_grid_pin_13_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[2] -to fpga_top/cbx_1__12_/bottom_grid_pin_13_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[5] -to fpga_top/cbx_1__12_/bottom_grid_pin_13_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[5] -to fpga_top/cbx_1__12_/bottom_grid_pin_13_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[14] -to fpga_top/cbx_1__12_/bottom_grid_pin_13_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[14] -to fpga_top/cbx_1__12_/bottom_grid_pin_13_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[20] -to fpga_top/cbx_1__12_/bottom_grid_pin_13_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[20] -to fpga_top/cbx_1__12_/bottom_grid_pin_13_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[29] -to fpga_top/cbx_1__12_/bottom_grid_pin_13_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[29] -to fpga_top/cbx_1__12_/bottom_grid_pin_13_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[0] -to fpga_top/cbx_1__12_/bottom_grid_pin_14_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[0] -to fpga_top/cbx_1__12_/bottom_grid_pin_14_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[3] -to fpga_top/cbx_1__12_/bottom_grid_pin_14_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[3] -to fpga_top/cbx_1__12_/bottom_grid_pin_14_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[9] -to fpga_top/cbx_1__12_/bottom_grid_pin_14_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[9] -to fpga_top/cbx_1__12_/bottom_grid_pin_14_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[15] -to fpga_top/cbx_1__12_/bottom_grid_pin_14_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[15] -to fpga_top/cbx_1__12_/bottom_grid_pin_14_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[21] -to fpga_top/cbx_1__12_/bottom_grid_pin_14_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[21] -to fpga_top/cbx_1__12_/bottom_grid_pin_14_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[27] -to fpga_top/cbx_1__12_/bottom_grid_pin_14_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[27] -to fpga_top/cbx_1__12_/bottom_grid_pin_14_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[1] -to fpga_top/cbx_1__12_/bottom_grid_pin_15_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[1] -to fpga_top/cbx_1__12_/bottom_grid_pin_15_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[4] -to fpga_top/cbx_1__12_/bottom_grid_pin_15_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[4] -to fpga_top/cbx_1__12_/bottom_grid_pin_15_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[7] -to fpga_top/cbx_1__12_/bottom_grid_pin_15_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[7] -to fpga_top/cbx_1__12_/bottom_grid_pin_15_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[16] -to fpga_top/cbx_1__12_/bottom_grid_pin_15_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[16] -to fpga_top/cbx_1__12_/bottom_grid_pin_15_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[22] -to fpga_top/cbx_1__12_/bottom_grid_pin_15_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[22] -to fpga_top/cbx_1__12_/bottom_grid_pin_15_[0] 7.247000222e-11 diff --git a/FPGA1212_SOFA_CHD_PNR/FPGA1212_SOFA_CHD_Verilog/SDC/cbx_1__1_.sdc b/FPGA1212_SOFA_CHD_PNR/FPGA1212_SOFA_CHD_Verilog/SDC/cbx_1__1_.sdc deleted file mode 100644 index 6610665..0000000 --- a/FPGA1212_SOFA_CHD_PNR/FPGA1212_SOFA_CHD_Verilog/SDC/cbx_1__1_.sdc +++ /dev/null @@ -1,250 +0,0 @@ -############################################# -# Synopsys Design Constraints (SDC) -# For FPGA fabric -# Description: Constrain timing of Connection Block cbx_1__1_ for PnR -# Author: Xifan TANG -# Organization: University of Utah -# Date: Tue Dec 8 15:34:14 2020 -############################################# - -############################################# -# Define time unit -############################################# -set_units -time s - -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[0] -to fpga_top/cbx_1__1_/chanx_left_out[0] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[0] -to fpga_top/cbx_1__1_/chanx_right_out[0] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[1] -to fpga_top/cbx_1__1_/chanx_left_out[1] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[1] -to fpga_top/cbx_1__1_/chanx_right_out[1] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[2] -to fpga_top/cbx_1__1_/chanx_left_out[2] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[2] -to fpga_top/cbx_1__1_/chanx_right_out[2] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[3] -to fpga_top/cbx_1__1_/chanx_left_out[3] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[3] -to fpga_top/cbx_1__1_/chanx_right_out[3] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[4] -to fpga_top/cbx_1__1_/chanx_left_out[4] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[4] -to fpga_top/cbx_1__1_/chanx_right_out[4] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[5] -to fpga_top/cbx_1__1_/chanx_left_out[5] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[5] -to fpga_top/cbx_1__1_/chanx_right_out[5] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[6] -to fpga_top/cbx_1__1_/chanx_left_out[6] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[6] -to fpga_top/cbx_1__1_/chanx_right_out[6] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[7] -to fpga_top/cbx_1__1_/chanx_left_out[7] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[7] -to fpga_top/cbx_1__1_/chanx_right_out[7] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[8] -to fpga_top/cbx_1__1_/chanx_left_out[8] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[8] -to fpga_top/cbx_1__1_/chanx_right_out[8] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[9] -to fpga_top/cbx_1__1_/chanx_left_out[9] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[9] -to fpga_top/cbx_1__1_/chanx_right_out[9] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[10] -to fpga_top/cbx_1__1_/chanx_left_out[10] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[10] -to fpga_top/cbx_1__1_/chanx_right_out[10] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[11] -to fpga_top/cbx_1__1_/chanx_left_out[11] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[11] -to fpga_top/cbx_1__1_/chanx_right_out[11] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[12] -to fpga_top/cbx_1__1_/chanx_left_out[12] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[12] -to fpga_top/cbx_1__1_/chanx_right_out[12] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[13] -to fpga_top/cbx_1__1_/chanx_left_out[13] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[13] -to fpga_top/cbx_1__1_/chanx_right_out[13] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[14] -to fpga_top/cbx_1__1_/chanx_left_out[14] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[14] -to fpga_top/cbx_1__1_/chanx_right_out[14] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[15] -to fpga_top/cbx_1__1_/chanx_left_out[15] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[15] -to fpga_top/cbx_1__1_/chanx_right_out[15] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[16] -to fpga_top/cbx_1__1_/chanx_left_out[16] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[16] -to fpga_top/cbx_1__1_/chanx_right_out[16] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[17] -to fpga_top/cbx_1__1_/chanx_left_out[17] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[17] -to fpga_top/cbx_1__1_/chanx_right_out[17] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[18] -to fpga_top/cbx_1__1_/chanx_left_out[18] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[18] -to fpga_top/cbx_1__1_/chanx_right_out[18] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[19] -to fpga_top/cbx_1__1_/chanx_left_out[19] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[19] -to fpga_top/cbx_1__1_/chanx_right_out[19] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[20] -to fpga_top/cbx_1__1_/chanx_left_out[20] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[20] -to fpga_top/cbx_1__1_/chanx_right_out[20] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[21] -to fpga_top/cbx_1__1_/chanx_left_out[21] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[21] -to fpga_top/cbx_1__1_/chanx_right_out[21] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[22] -to fpga_top/cbx_1__1_/chanx_left_out[22] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[22] -to fpga_top/cbx_1__1_/chanx_right_out[22] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[23] -to fpga_top/cbx_1__1_/chanx_left_out[23] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[23] -to fpga_top/cbx_1__1_/chanx_right_out[23] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[24] -to fpga_top/cbx_1__1_/chanx_left_out[24] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[24] -to fpga_top/cbx_1__1_/chanx_right_out[24] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[25] -to fpga_top/cbx_1__1_/chanx_left_out[25] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[25] -to fpga_top/cbx_1__1_/chanx_right_out[25] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[26] -to fpga_top/cbx_1__1_/chanx_left_out[26] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[26] -to fpga_top/cbx_1__1_/chanx_right_out[26] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[27] -to fpga_top/cbx_1__1_/chanx_left_out[27] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[27] -to fpga_top/cbx_1__1_/chanx_right_out[27] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[28] -to fpga_top/cbx_1__1_/chanx_left_out[28] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[28] -to fpga_top/cbx_1__1_/chanx_right_out[28] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[29] -to fpga_top/cbx_1__1_/chanx_left_out[29] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[29] -to fpga_top/cbx_1__1_/chanx_right_out[29] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[0] -to fpga_top/cbx_1__1_/bottom_grid_pin_0_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[0] -to fpga_top/cbx_1__1_/bottom_grid_pin_0_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[3] -to fpga_top/cbx_1__1_/bottom_grid_pin_0_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[3] -to fpga_top/cbx_1__1_/bottom_grid_pin_0_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[6] -to fpga_top/cbx_1__1_/bottom_grid_pin_0_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[6] -to fpga_top/cbx_1__1_/bottom_grid_pin_0_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[12] -to fpga_top/cbx_1__1_/bottom_grid_pin_0_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[12] -to fpga_top/cbx_1__1_/bottom_grid_pin_0_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[18] -to fpga_top/cbx_1__1_/bottom_grid_pin_0_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[18] -to fpga_top/cbx_1__1_/bottom_grid_pin_0_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[24] -to fpga_top/cbx_1__1_/bottom_grid_pin_0_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[24] -to fpga_top/cbx_1__1_/bottom_grid_pin_0_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[1] -to fpga_top/cbx_1__1_/bottom_grid_pin_1_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[1] -to fpga_top/cbx_1__1_/bottom_grid_pin_1_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[4] -to fpga_top/cbx_1__1_/bottom_grid_pin_1_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[4] -to fpga_top/cbx_1__1_/bottom_grid_pin_1_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[7] -to fpga_top/cbx_1__1_/bottom_grid_pin_1_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[7] -to fpga_top/cbx_1__1_/bottom_grid_pin_1_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[16] -to fpga_top/cbx_1__1_/bottom_grid_pin_1_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[16] -to fpga_top/cbx_1__1_/bottom_grid_pin_1_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[25] -to fpga_top/cbx_1__1_/bottom_grid_pin_1_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[25] -to fpga_top/cbx_1__1_/bottom_grid_pin_1_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[2] -to fpga_top/cbx_1__1_/bottom_grid_pin_2_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[2] -to fpga_top/cbx_1__1_/bottom_grid_pin_2_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[5] -to fpga_top/cbx_1__1_/bottom_grid_pin_2_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[5] -to fpga_top/cbx_1__1_/bottom_grid_pin_2_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[8] -to fpga_top/cbx_1__1_/bottom_grid_pin_2_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[8] -to fpga_top/cbx_1__1_/bottom_grid_pin_2_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[14] -to fpga_top/cbx_1__1_/bottom_grid_pin_2_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[14] -to fpga_top/cbx_1__1_/bottom_grid_pin_2_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[20] -to fpga_top/cbx_1__1_/bottom_grid_pin_2_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[20] -to fpga_top/cbx_1__1_/bottom_grid_pin_2_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[26] -to fpga_top/cbx_1__1_/bottom_grid_pin_2_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[26] -to fpga_top/cbx_1__1_/bottom_grid_pin_2_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[0] -to fpga_top/cbx_1__1_/bottom_grid_pin_3_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[0] -to fpga_top/cbx_1__1_/bottom_grid_pin_3_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[3] -to fpga_top/cbx_1__1_/bottom_grid_pin_3_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[3] -to fpga_top/cbx_1__1_/bottom_grid_pin_3_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[9] -to fpga_top/cbx_1__1_/bottom_grid_pin_3_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[9] -to fpga_top/cbx_1__1_/bottom_grid_pin_3_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[18] -to fpga_top/cbx_1__1_/bottom_grid_pin_3_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[18] -to fpga_top/cbx_1__1_/bottom_grid_pin_3_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[27] -to fpga_top/cbx_1__1_/bottom_grid_pin_3_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[27] -to fpga_top/cbx_1__1_/bottom_grid_pin_3_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[1] -to fpga_top/cbx_1__1_/bottom_grid_pin_4_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[1] -to fpga_top/cbx_1__1_/bottom_grid_pin_4_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[4] -to fpga_top/cbx_1__1_/bottom_grid_pin_4_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[4] -to fpga_top/cbx_1__1_/bottom_grid_pin_4_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[10] -to fpga_top/cbx_1__1_/bottom_grid_pin_4_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[10] -to fpga_top/cbx_1__1_/bottom_grid_pin_4_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[16] -to fpga_top/cbx_1__1_/bottom_grid_pin_4_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[16] -to fpga_top/cbx_1__1_/bottom_grid_pin_4_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[22] -to fpga_top/cbx_1__1_/bottom_grid_pin_4_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[22] -to fpga_top/cbx_1__1_/bottom_grid_pin_4_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[28] -to fpga_top/cbx_1__1_/bottom_grid_pin_4_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[28] -to fpga_top/cbx_1__1_/bottom_grid_pin_4_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[2] -to fpga_top/cbx_1__1_/bottom_grid_pin_5_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[2] -to fpga_top/cbx_1__1_/bottom_grid_pin_5_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[5] -to fpga_top/cbx_1__1_/bottom_grid_pin_5_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[5] -to fpga_top/cbx_1__1_/bottom_grid_pin_5_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[11] -to fpga_top/cbx_1__1_/bottom_grid_pin_5_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[11] -to fpga_top/cbx_1__1_/bottom_grid_pin_5_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[20] -to fpga_top/cbx_1__1_/bottom_grid_pin_5_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[20] -to fpga_top/cbx_1__1_/bottom_grid_pin_5_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[29] -to fpga_top/cbx_1__1_/bottom_grid_pin_5_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[29] -to fpga_top/cbx_1__1_/bottom_grid_pin_5_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[0] -to fpga_top/cbx_1__1_/bottom_grid_pin_6_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[0] -to fpga_top/cbx_1__1_/bottom_grid_pin_6_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[3] -to fpga_top/cbx_1__1_/bottom_grid_pin_6_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[3] -to fpga_top/cbx_1__1_/bottom_grid_pin_6_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[6] -to fpga_top/cbx_1__1_/bottom_grid_pin_6_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[6] -to fpga_top/cbx_1__1_/bottom_grid_pin_6_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[12] -to fpga_top/cbx_1__1_/bottom_grid_pin_6_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[12] -to fpga_top/cbx_1__1_/bottom_grid_pin_6_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[18] -to fpga_top/cbx_1__1_/bottom_grid_pin_6_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[18] -to fpga_top/cbx_1__1_/bottom_grid_pin_6_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[24] -to fpga_top/cbx_1__1_/bottom_grid_pin_6_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[24] -to fpga_top/cbx_1__1_/bottom_grid_pin_6_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[1] -to fpga_top/cbx_1__1_/bottom_grid_pin_7_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[1] -to fpga_top/cbx_1__1_/bottom_grid_pin_7_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[4] -to fpga_top/cbx_1__1_/bottom_grid_pin_7_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[4] -to fpga_top/cbx_1__1_/bottom_grid_pin_7_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[7] -to fpga_top/cbx_1__1_/bottom_grid_pin_7_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[7] -to fpga_top/cbx_1__1_/bottom_grid_pin_7_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[13] -to fpga_top/cbx_1__1_/bottom_grid_pin_7_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[13] -to fpga_top/cbx_1__1_/bottom_grid_pin_7_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[22] -to fpga_top/cbx_1__1_/bottom_grid_pin_7_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[22] -to fpga_top/cbx_1__1_/bottom_grid_pin_7_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[2] -to fpga_top/cbx_1__1_/bottom_grid_pin_8_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[2] -to fpga_top/cbx_1__1_/bottom_grid_pin_8_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[5] -to fpga_top/cbx_1__1_/bottom_grid_pin_8_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[5] -to fpga_top/cbx_1__1_/bottom_grid_pin_8_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[8] -to fpga_top/cbx_1__1_/bottom_grid_pin_8_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[8] -to fpga_top/cbx_1__1_/bottom_grid_pin_8_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[14] -to fpga_top/cbx_1__1_/bottom_grid_pin_8_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[14] -to fpga_top/cbx_1__1_/bottom_grid_pin_8_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[20] -to fpga_top/cbx_1__1_/bottom_grid_pin_8_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[20] -to fpga_top/cbx_1__1_/bottom_grid_pin_8_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[26] -to fpga_top/cbx_1__1_/bottom_grid_pin_8_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[26] -to fpga_top/cbx_1__1_/bottom_grid_pin_8_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[0] -to fpga_top/cbx_1__1_/bottom_grid_pin_9_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[0] -to fpga_top/cbx_1__1_/bottom_grid_pin_9_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[3] -to fpga_top/cbx_1__1_/bottom_grid_pin_9_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[3] -to fpga_top/cbx_1__1_/bottom_grid_pin_9_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[9] -to fpga_top/cbx_1__1_/bottom_grid_pin_9_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[9] -to fpga_top/cbx_1__1_/bottom_grid_pin_9_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[15] -to fpga_top/cbx_1__1_/bottom_grid_pin_9_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[15] -to fpga_top/cbx_1__1_/bottom_grid_pin_9_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[24] -to fpga_top/cbx_1__1_/bottom_grid_pin_9_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[24] -to fpga_top/cbx_1__1_/bottom_grid_pin_9_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[1] -to fpga_top/cbx_1__1_/bottom_grid_pin_10_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[1] -to fpga_top/cbx_1__1_/bottom_grid_pin_10_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[4] -to fpga_top/cbx_1__1_/bottom_grid_pin_10_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[4] -to fpga_top/cbx_1__1_/bottom_grid_pin_10_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[10] -to fpga_top/cbx_1__1_/bottom_grid_pin_10_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[10] -to fpga_top/cbx_1__1_/bottom_grid_pin_10_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[16] -to fpga_top/cbx_1__1_/bottom_grid_pin_10_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[16] -to fpga_top/cbx_1__1_/bottom_grid_pin_10_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[22] -to fpga_top/cbx_1__1_/bottom_grid_pin_10_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[22] -to fpga_top/cbx_1__1_/bottom_grid_pin_10_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[28] -to fpga_top/cbx_1__1_/bottom_grid_pin_10_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[28] -to fpga_top/cbx_1__1_/bottom_grid_pin_10_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[2] -to fpga_top/cbx_1__1_/bottom_grid_pin_11_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[2] -to fpga_top/cbx_1__1_/bottom_grid_pin_11_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[5] -to fpga_top/cbx_1__1_/bottom_grid_pin_11_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[5] -to fpga_top/cbx_1__1_/bottom_grid_pin_11_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[11] -to fpga_top/cbx_1__1_/bottom_grid_pin_11_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[11] -to fpga_top/cbx_1__1_/bottom_grid_pin_11_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[17] -to fpga_top/cbx_1__1_/bottom_grid_pin_11_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[17] -to fpga_top/cbx_1__1_/bottom_grid_pin_11_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[26] -to fpga_top/cbx_1__1_/bottom_grid_pin_11_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[26] -to fpga_top/cbx_1__1_/bottom_grid_pin_11_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[0] -to fpga_top/cbx_1__1_/bottom_grid_pin_12_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[0] -to fpga_top/cbx_1__1_/bottom_grid_pin_12_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[3] -to fpga_top/cbx_1__1_/bottom_grid_pin_12_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[3] -to fpga_top/cbx_1__1_/bottom_grid_pin_12_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[6] -to fpga_top/cbx_1__1_/bottom_grid_pin_12_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[6] -to fpga_top/cbx_1__1_/bottom_grid_pin_12_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[12] -to fpga_top/cbx_1__1_/bottom_grid_pin_12_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[12] -to fpga_top/cbx_1__1_/bottom_grid_pin_12_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[18] -to fpga_top/cbx_1__1_/bottom_grid_pin_12_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[18] -to fpga_top/cbx_1__1_/bottom_grid_pin_12_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[24] -to fpga_top/cbx_1__1_/bottom_grid_pin_12_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[24] -to fpga_top/cbx_1__1_/bottom_grid_pin_12_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[1] -to fpga_top/cbx_1__1_/bottom_grid_pin_13_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[1] -to fpga_top/cbx_1__1_/bottom_grid_pin_13_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[4] -to fpga_top/cbx_1__1_/bottom_grid_pin_13_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[4] -to fpga_top/cbx_1__1_/bottom_grid_pin_13_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[13] -to fpga_top/cbx_1__1_/bottom_grid_pin_13_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[13] -to fpga_top/cbx_1__1_/bottom_grid_pin_13_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[19] -to fpga_top/cbx_1__1_/bottom_grid_pin_13_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[19] -to fpga_top/cbx_1__1_/bottom_grid_pin_13_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[28] -to fpga_top/cbx_1__1_/bottom_grid_pin_13_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[28] -to fpga_top/cbx_1__1_/bottom_grid_pin_13_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[2] -to fpga_top/cbx_1__1_/bottom_grid_pin_14_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[2] -to fpga_top/cbx_1__1_/bottom_grid_pin_14_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[5] -to fpga_top/cbx_1__1_/bottom_grid_pin_14_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[5] -to fpga_top/cbx_1__1_/bottom_grid_pin_14_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[8] -to fpga_top/cbx_1__1_/bottom_grid_pin_14_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[8] -to fpga_top/cbx_1__1_/bottom_grid_pin_14_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[14] -to fpga_top/cbx_1__1_/bottom_grid_pin_14_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[14] -to fpga_top/cbx_1__1_/bottom_grid_pin_14_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[20] -to fpga_top/cbx_1__1_/bottom_grid_pin_14_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[20] -to fpga_top/cbx_1__1_/bottom_grid_pin_14_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[26] -to fpga_top/cbx_1__1_/bottom_grid_pin_14_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[26] -to fpga_top/cbx_1__1_/bottom_grid_pin_14_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[0] -to fpga_top/cbx_1__1_/bottom_grid_pin_15_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[0] -to fpga_top/cbx_1__1_/bottom_grid_pin_15_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[3] -to fpga_top/cbx_1__1_/bottom_grid_pin_15_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[3] -to fpga_top/cbx_1__1_/bottom_grid_pin_15_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[6] -to fpga_top/cbx_1__1_/bottom_grid_pin_15_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[6] -to fpga_top/cbx_1__1_/bottom_grid_pin_15_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[15] -to fpga_top/cbx_1__1_/bottom_grid_pin_15_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[15] -to fpga_top/cbx_1__1_/bottom_grid_pin_15_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[21] -to fpga_top/cbx_1__1_/bottom_grid_pin_15_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[21] -to fpga_top/cbx_1__1_/bottom_grid_pin_15_[0] 7.247000222e-11 diff --git a/FPGA1212_SOFA_CHD_PNR/FPGA1212_SOFA_CHD_Verilog/SDC/cby_0__1_.sdc b/FPGA1212_SOFA_CHD_PNR/FPGA1212_SOFA_CHD_Verilog/SDC/cby_0__1_.sdc deleted file mode 100644 index e578abc..0000000 --- a/FPGA1212_SOFA_CHD_PNR/FPGA1212_SOFA_CHD_Verilog/SDC/cby_0__1_.sdc +++ /dev/null @@ -1,86 +0,0 @@ -############################################# -# Synopsys Design Constraints (SDC) -# For FPGA fabric -# Description: Constrain timing of Connection Block cby_0__1_ for PnR -# Author: Xifan TANG -# Organization: University of Utah -# Date: Tue Dec 8 15:34:14 2020 -############################################# - -############################################# -# Define time unit -############################################# -set_units -time s - -set_max_delay -from fpga_core_uut/cby_0__1_/chany_bottom_in[0] -to fpga_top/cby_0__1_/chany_bottom_out[0] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_0__1_/chany_top_in[0] -to fpga_top/cby_0__1_/chany_top_out[0] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_0__1_/chany_bottom_in[1] -to fpga_top/cby_0__1_/chany_bottom_out[1] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_0__1_/chany_top_in[1] -to fpga_top/cby_0__1_/chany_top_out[1] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_0__1_/chany_bottom_in[2] -to fpga_top/cby_0__1_/chany_bottom_out[2] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_0__1_/chany_top_in[2] -to fpga_top/cby_0__1_/chany_top_out[2] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_0__1_/chany_bottom_in[3] -to fpga_top/cby_0__1_/chany_bottom_out[3] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_0__1_/chany_top_in[3] -to fpga_top/cby_0__1_/chany_top_out[3] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_0__1_/chany_bottom_in[4] -to fpga_top/cby_0__1_/chany_bottom_out[4] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_0__1_/chany_top_in[4] -to fpga_top/cby_0__1_/chany_top_out[4] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_0__1_/chany_bottom_in[5] -to fpga_top/cby_0__1_/chany_bottom_out[5] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_0__1_/chany_top_in[5] -to fpga_top/cby_0__1_/chany_top_out[5] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_0__1_/chany_bottom_in[6] -to fpga_top/cby_0__1_/chany_bottom_out[6] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_0__1_/chany_top_in[6] -to fpga_top/cby_0__1_/chany_top_out[6] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_0__1_/chany_bottom_in[7] -to fpga_top/cby_0__1_/chany_bottom_out[7] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_0__1_/chany_top_in[7] -to fpga_top/cby_0__1_/chany_top_out[7] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_0__1_/chany_bottom_in[8] -to fpga_top/cby_0__1_/chany_bottom_out[8] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_0__1_/chany_top_in[8] -to fpga_top/cby_0__1_/chany_top_out[8] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_0__1_/chany_bottom_in[9] -to fpga_top/cby_0__1_/chany_bottom_out[9] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_0__1_/chany_top_in[9] -to fpga_top/cby_0__1_/chany_top_out[9] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_0__1_/chany_bottom_in[10] -to fpga_top/cby_0__1_/chany_bottom_out[10] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_0__1_/chany_top_in[10] -to fpga_top/cby_0__1_/chany_top_out[10] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_0__1_/chany_bottom_in[11] -to fpga_top/cby_0__1_/chany_bottom_out[11] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_0__1_/chany_top_in[11] -to fpga_top/cby_0__1_/chany_top_out[11] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_0__1_/chany_bottom_in[12] -to fpga_top/cby_0__1_/chany_bottom_out[12] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_0__1_/chany_top_in[12] -to fpga_top/cby_0__1_/chany_top_out[12] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_0__1_/chany_bottom_in[13] -to fpga_top/cby_0__1_/chany_bottom_out[13] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_0__1_/chany_top_in[13] -to fpga_top/cby_0__1_/chany_top_out[13] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_0__1_/chany_bottom_in[14] -to fpga_top/cby_0__1_/chany_bottom_out[14] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_0__1_/chany_top_in[14] -to fpga_top/cby_0__1_/chany_top_out[14] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_0__1_/chany_bottom_in[15] -to fpga_top/cby_0__1_/chany_bottom_out[15] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_0__1_/chany_top_in[15] -to fpga_top/cby_0__1_/chany_top_out[15] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_0__1_/chany_bottom_in[16] -to fpga_top/cby_0__1_/chany_bottom_out[16] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_0__1_/chany_top_in[16] -to fpga_top/cby_0__1_/chany_top_out[16] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_0__1_/chany_bottom_in[17] -to fpga_top/cby_0__1_/chany_bottom_out[17] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_0__1_/chany_top_in[17] -to fpga_top/cby_0__1_/chany_top_out[17] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_0__1_/chany_bottom_in[18] -to fpga_top/cby_0__1_/chany_bottom_out[18] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_0__1_/chany_top_in[18] -to fpga_top/cby_0__1_/chany_top_out[18] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_0__1_/chany_bottom_in[19] -to fpga_top/cby_0__1_/chany_bottom_out[19] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_0__1_/chany_top_in[19] -to fpga_top/cby_0__1_/chany_top_out[19] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_0__1_/chany_bottom_in[20] -to fpga_top/cby_0__1_/chany_bottom_out[20] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_0__1_/chany_top_in[20] -to fpga_top/cby_0__1_/chany_top_out[20] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_0__1_/chany_bottom_in[21] -to fpga_top/cby_0__1_/chany_bottom_out[21] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_0__1_/chany_top_in[21] -to fpga_top/cby_0__1_/chany_top_out[21] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_0__1_/chany_bottom_in[22] -to fpga_top/cby_0__1_/chany_bottom_out[22] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_0__1_/chany_top_in[22] -to fpga_top/cby_0__1_/chany_top_out[22] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_0__1_/chany_bottom_in[23] -to fpga_top/cby_0__1_/chany_bottom_out[23] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_0__1_/chany_top_in[23] -to fpga_top/cby_0__1_/chany_top_out[23] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_0__1_/chany_bottom_in[24] -to fpga_top/cby_0__1_/chany_bottom_out[24] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_0__1_/chany_top_in[24] -to fpga_top/cby_0__1_/chany_top_out[24] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_0__1_/chany_bottom_in[25] -to fpga_top/cby_0__1_/chany_bottom_out[25] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_0__1_/chany_top_in[25] -to fpga_top/cby_0__1_/chany_top_out[25] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_0__1_/chany_bottom_in[26] -to fpga_top/cby_0__1_/chany_bottom_out[26] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_0__1_/chany_top_in[26] -to fpga_top/cby_0__1_/chany_top_out[26] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_0__1_/chany_bottom_in[27] -to fpga_top/cby_0__1_/chany_bottom_out[27] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_0__1_/chany_top_in[27] -to fpga_top/cby_0__1_/chany_top_out[27] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_0__1_/chany_bottom_in[28] -to fpga_top/cby_0__1_/chany_bottom_out[28] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_0__1_/chany_top_in[28] -to fpga_top/cby_0__1_/chany_top_out[28] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_0__1_/chany_bottom_in[29] -to fpga_top/cby_0__1_/chany_bottom_out[29] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_0__1_/chany_top_in[29] -to fpga_top/cby_0__1_/chany_top_out[29] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_0__1_/chany_bottom_in[0] -to fpga_top/cby_0__1_/left_grid_pin_0_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_0__1_/chany_top_in[0] -to fpga_top/cby_0__1_/left_grid_pin_0_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_0__1_/chany_bottom_in[3] -to fpga_top/cby_0__1_/left_grid_pin_0_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_0__1_/chany_top_in[3] -to fpga_top/cby_0__1_/left_grid_pin_0_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_0__1_/chany_bottom_in[6] -to fpga_top/cby_0__1_/left_grid_pin_0_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_0__1_/chany_top_in[6] -to fpga_top/cby_0__1_/left_grid_pin_0_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_0__1_/chany_bottom_in[12] -to fpga_top/cby_0__1_/left_grid_pin_0_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_0__1_/chany_top_in[12] -to fpga_top/cby_0__1_/left_grid_pin_0_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_0__1_/chany_bottom_in[18] -to fpga_top/cby_0__1_/left_grid_pin_0_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_0__1_/chany_top_in[18] -to fpga_top/cby_0__1_/left_grid_pin_0_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_0__1_/chany_bottom_in[24] -to fpga_top/cby_0__1_/left_grid_pin_0_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_0__1_/chany_top_in[24] -to fpga_top/cby_0__1_/left_grid_pin_0_[0] 7.247000222e-11 diff --git a/FPGA1212_SOFA_CHD_PNR/FPGA1212_SOFA_CHD_Verilog/SDC/cby_12__1_.sdc b/FPGA1212_SOFA_CHD_PNR/FPGA1212_SOFA_CHD_Verilog/SDC/cby_12__1_.sdc deleted file mode 100644 index e02c262..0000000 --- a/FPGA1212_SOFA_CHD_PNR/FPGA1212_SOFA_CHD_Verilog/SDC/cby_12__1_.sdc +++ /dev/null @@ -1,262 +0,0 @@ -############################################# -# Synopsys Design Constraints (SDC) -# For FPGA fabric -# Description: Constrain timing of Connection Block cby_12__1_ for PnR -# Author: Xifan TANG -# Organization: University of Utah -# Date: Tue Dec 8 15:34:14 2020 -############################################# - -############################################# -# Define time unit -############################################# -set_units -time s - -set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[0] -to fpga_top/cby_12__1_/chany_bottom_out[0] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[0] -to fpga_top/cby_12__1_/chany_top_out[0] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[1] -to fpga_top/cby_12__1_/chany_bottom_out[1] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[1] -to fpga_top/cby_12__1_/chany_top_out[1] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[2] -to fpga_top/cby_12__1_/chany_bottom_out[2] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[2] -to fpga_top/cby_12__1_/chany_top_out[2] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[3] -to fpga_top/cby_12__1_/chany_bottom_out[3] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[3] -to fpga_top/cby_12__1_/chany_top_out[3] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[4] -to fpga_top/cby_12__1_/chany_bottom_out[4] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[4] -to fpga_top/cby_12__1_/chany_top_out[4] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[5] -to fpga_top/cby_12__1_/chany_bottom_out[5] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[5] -to fpga_top/cby_12__1_/chany_top_out[5] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[6] -to fpga_top/cby_12__1_/chany_bottom_out[6] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[6] -to fpga_top/cby_12__1_/chany_top_out[6] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[7] -to fpga_top/cby_12__1_/chany_bottom_out[7] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[7] -to fpga_top/cby_12__1_/chany_top_out[7] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[8] -to fpga_top/cby_12__1_/chany_bottom_out[8] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[8] -to fpga_top/cby_12__1_/chany_top_out[8] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[9] -to fpga_top/cby_12__1_/chany_bottom_out[9] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[9] -to fpga_top/cby_12__1_/chany_top_out[9] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[10] -to fpga_top/cby_12__1_/chany_bottom_out[10] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[10] -to fpga_top/cby_12__1_/chany_top_out[10] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[11] -to fpga_top/cby_12__1_/chany_bottom_out[11] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[11] -to fpga_top/cby_12__1_/chany_top_out[11] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[12] -to fpga_top/cby_12__1_/chany_bottom_out[12] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[12] -to fpga_top/cby_12__1_/chany_top_out[12] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[13] -to fpga_top/cby_12__1_/chany_bottom_out[13] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[13] -to fpga_top/cby_12__1_/chany_top_out[13] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[14] -to fpga_top/cby_12__1_/chany_bottom_out[14] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[14] -to fpga_top/cby_12__1_/chany_top_out[14] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[15] -to fpga_top/cby_12__1_/chany_bottom_out[15] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[15] -to fpga_top/cby_12__1_/chany_top_out[15] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[16] -to fpga_top/cby_12__1_/chany_bottom_out[16] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[16] -to fpga_top/cby_12__1_/chany_top_out[16] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[17] -to fpga_top/cby_12__1_/chany_bottom_out[17] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[17] -to fpga_top/cby_12__1_/chany_top_out[17] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[18] -to fpga_top/cby_12__1_/chany_bottom_out[18] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[18] -to fpga_top/cby_12__1_/chany_top_out[18] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[19] -to fpga_top/cby_12__1_/chany_bottom_out[19] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[19] -to fpga_top/cby_12__1_/chany_top_out[19] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[20] -to fpga_top/cby_12__1_/chany_bottom_out[20] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[20] -to fpga_top/cby_12__1_/chany_top_out[20] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[21] -to fpga_top/cby_12__1_/chany_bottom_out[21] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[21] -to fpga_top/cby_12__1_/chany_top_out[21] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[22] -to fpga_top/cby_12__1_/chany_bottom_out[22] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[22] -to fpga_top/cby_12__1_/chany_top_out[22] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[23] -to fpga_top/cby_12__1_/chany_bottom_out[23] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[23] -to fpga_top/cby_12__1_/chany_top_out[23] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[24] -to fpga_top/cby_12__1_/chany_bottom_out[24] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[24] -to fpga_top/cby_12__1_/chany_top_out[24] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[25] -to fpga_top/cby_12__1_/chany_bottom_out[25] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[25] -to fpga_top/cby_12__1_/chany_top_out[25] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[26] -to fpga_top/cby_12__1_/chany_bottom_out[26] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[26] -to fpga_top/cby_12__1_/chany_top_out[26] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[27] -to fpga_top/cby_12__1_/chany_bottom_out[27] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[27] -to fpga_top/cby_12__1_/chany_top_out[27] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[28] -to fpga_top/cby_12__1_/chany_bottom_out[28] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[28] -to fpga_top/cby_12__1_/chany_top_out[28] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[29] -to fpga_top/cby_12__1_/chany_bottom_out[29] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[29] -to fpga_top/cby_12__1_/chany_top_out[29] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[0] -to fpga_top/cby_12__1_/right_grid_pin_0_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[0] -to fpga_top/cby_12__1_/right_grid_pin_0_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[3] -to fpga_top/cby_12__1_/right_grid_pin_0_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[3] -to fpga_top/cby_12__1_/right_grid_pin_0_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[6] -to fpga_top/cby_12__1_/right_grid_pin_0_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[6] -to fpga_top/cby_12__1_/right_grid_pin_0_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[12] -to fpga_top/cby_12__1_/right_grid_pin_0_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[12] -to fpga_top/cby_12__1_/right_grid_pin_0_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[18] -to fpga_top/cby_12__1_/right_grid_pin_0_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[18] -to fpga_top/cby_12__1_/right_grid_pin_0_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[24] -to fpga_top/cby_12__1_/right_grid_pin_0_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[24] -to fpga_top/cby_12__1_/right_grid_pin_0_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[1] -to fpga_top/cby_12__1_/left_grid_pin_16_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[1] -to fpga_top/cby_12__1_/left_grid_pin_16_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[4] -to fpga_top/cby_12__1_/left_grid_pin_16_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[4] -to fpga_top/cby_12__1_/left_grid_pin_16_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[7] -to fpga_top/cby_12__1_/left_grid_pin_16_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[7] -to fpga_top/cby_12__1_/left_grid_pin_16_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[13] -to fpga_top/cby_12__1_/left_grid_pin_16_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[13] -to fpga_top/cby_12__1_/left_grid_pin_16_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[19] -to fpga_top/cby_12__1_/left_grid_pin_16_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[19] -to fpga_top/cby_12__1_/left_grid_pin_16_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[25] -to fpga_top/cby_12__1_/left_grid_pin_16_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[25] -to fpga_top/cby_12__1_/left_grid_pin_16_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[2] -to fpga_top/cby_12__1_/left_grid_pin_17_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[2] -to fpga_top/cby_12__1_/left_grid_pin_17_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[5] -to fpga_top/cby_12__1_/left_grid_pin_17_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[5] -to fpga_top/cby_12__1_/left_grid_pin_17_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[8] -to fpga_top/cby_12__1_/left_grid_pin_17_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[8] -to fpga_top/cby_12__1_/left_grid_pin_17_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[17] -to fpga_top/cby_12__1_/left_grid_pin_17_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[17] -to fpga_top/cby_12__1_/left_grid_pin_17_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[26] -to fpga_top/cby_12__1_/left_grid_pin_17_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[26] -to fpga_top/cby_12__1_/left_grid_pin_17_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[0] -to fpga_top/cby_12__1_/left_grid_pin_18_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[0] -to fpga_top/cby_12__1_/left_grid_pin_18_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[3] -to fpga_top/cby_12__1_/left_grid_pin_18_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[3] -to fpga_top/cby_12__1_/left_grid_pin_18_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[9] -to fpga_top/cby_12__1_/left_grid_pin_18_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[9] -to fpga_top/cby_12__1_/left_grid_pin_18_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[15] -to fpga_top/cby_12__1_/left_grid_pin_18_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[15] -to fpga_top/cby_12__1_/left_grid_pin_18_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[21] -to fpga_top/cby_12__1_/left_grid_pin_18_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[21] -to fpga_top/cby_12__1_/left_grid_pin_18_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[27] -to fpga_top/cby_12__1_/left_grid_pin_18_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[27] -to fpga_top/cby_12__1_/left_grid_pin_18_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[1] -to fpga_top/cby_12__1_/left_grid_pin_19_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[1] -to fpga_top/cby_12__1_/left_grid_pin_19_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[4] -to fpga_top/cby_12__1_/left_grid_pin_19_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[4] -to fpga_top/cby_12__1_/left_grid_pin_19_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[10] -to fpga_top/cby_12__1_/left_grid_pin_19_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[10] -to fpga_top/cby_12__1_/left_grid_pin_19_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[19] -to fpga_top/cby_12__1_/left_grid_pin_19_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[19] -to fpga_top/cby_12__1_/left_grid_pin_19_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[28] -to fpga_top/cby_12__1_/left_grid_pin_19_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[28] -to fpga_top/cby_12__1_/left_grid_pin_19_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[2] -to fpga_top/cby_12__1_/left_grid_pin_20_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[2] -to fpga_top/cby_12__1_/left_grid_pin_20_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[5] -to fpga_top/cby_12__1_/left_grid_pin_20_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[5] -to fpga_top/cby_12__1_/left_grid_pin_20_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[11] -to fpga_top/cby_12__1_/left_grid_pin_20_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[11] -to fpga_top/cby_12__1_/left_grid_pin_20_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[17] -to fpga_top/cby_12__1_/left_grid_pin_20_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[17] -to fpga_top/cby_12__1_/left_grid_pin_20_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[23] -to fpga_top/cby_12__1_/left_grid_pin_20_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[23] -to fpga_top/cby_12__1_/left_grid_pin_20_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[29] -to fpga_top/cby_12__1_/left_grid_pin_20_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[29] -to fpga_top/cby_12__1_/left_grid_pin_20_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[0] -to fpga_top/cby_12__1_/left_grid_pin_21_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[0] -to fpga_top/cby_12__1_/left_grid_pin_21_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[3] -to fpga_top/cby_12__1_/left_grid_pin_21_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[3] -to fpga_top/cby_12__1_/left_grid_pin_21_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[6] -to fpga_top/cby_12__1_/left_grid_pin_21_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[6] -to fpga_top/cby_12__1_/left_grid_pin_21_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[12] -to fpga_top/cby_12__1_/left_grid_pin_21_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[12] -to fpga_top/cby_12__1_/left_grid_pin_21_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[21] -to fpga_top/cby_12__1_/left_grid_pin_21_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[21] -to fpga_top/cby_12__1_/left_grid_pin_21_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[1] -to fpga_top/cby_12__1_/left_grid_pin_22_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[1] -to fpga_top/cby_12__1_/left_grid_pin_22_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[4] -to fpga_top/cby_12__1_/left_grid_pin_22_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[4] -to fpga_top/cby_12__1_/left_grid_pin_22_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[7] -to fpga_top/cby_12__1_/left_grid_pin_22_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[7] -to fpga_top/cby_12__1_/left_grid_pin_22_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[13] -to fpga_top/cby_12__1_/left_grid_pin_22_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[13] -to fpga_top/cby_12__1_/left_grid_pin_22_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[19] -to fpga_top/cby_12__1_/left_grid_pin_22_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[19] -to fpga_top/cby_12__1_/left_grid_pin_22_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[25] -to fpga_top/cby_12__1_/left_grid_pin_22_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[25] -to fpga_top/cby_12__1_/left_grid_pin_22_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[2] -to fpga_top/cby_12__1_/left_grid_pin_23_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[2] -to fpga_top/cby_12__1_/left_grid_pin_23_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[5] -to fpga_top/cby_12__1_/left_grid_pin_23_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[5] -to fpga_top/cby_12__1_/left_grid_pin_23_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[8] -to fpga_top/cby_12__1_/left_grid_pin_23_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[8] -to fpga_top/cby_12__1_/left_grid_pin_23_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[14] -to fpga_top/cby_12__1_/left_grid_pin_23_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[14] -to fpga_top/cby_12__1_/left_grid_pin_23_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[23] -to fpga_top/cby_12__1_/left_grid_pin_23_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[23] -to fpga_top/cby_12__1_/left_grid_pin_23_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[0] -to fpga_top/cby_12__1_/left_grid_pin_24_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[0] -to fpga_top/cby_12__1_/left_grid_pin_24_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[3] -to fpga_top/cby_12__1_/left_grid_pin_24_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[3] -to fpga_top/cby_12__1_/left_grid_pin_24_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[9] -to fpga_top/cby_12__1_/left_grid_pin_24_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[9] -to fpga_top/cby_12__1_/left_grid_pin_24_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[15] -to fpga_top/cby_12__1_/left_grid_pin_24_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[15] -to fpga_top/cby_12__1_/left_grid_pin_24_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[21] -to fpga_top/cby_12__1_/left_grid_pin_24_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[21] -to fpga_top/cby_12__1_/left_grid_pin_24_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[27] -to fpga_top/cby_12__1_/left_grid_pin_24_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[27] -to fpga_top/cby_12__1_/left_grid_pin_24_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[1] -to fpga_top/cby_12__1_/left_grid_pin_25_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[1] -to fpga_top/cby_12__1_/left_grid_pin_25_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[4] -to fpga_top/cby_12__1_/left_grid_pin_25_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[4] -to fpga_top/cby_12__1_/left_grid_pin_25_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[10] -to fpga_top/cby_12__1_/left_grid_pin_25_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[10] -to fpga_top/cby_12__1_/left_grid_pin_25_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[16] -to fpga_top/cby_12__1_/left_grid_pin_25_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[16] -to fpga_top/cby_12__1_/left_grid_pin_25_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[25] -to fpga_top/cby_12__1_/left_grid_pin_25_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[25] -to fpga_top/cby_12__1_/left_grid_pin_25_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[2] -to fpga_top/cby_12__1_/left_grid_pin_26_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[2] -to fpga_top/cby_12__1_/left_grid_pin_26_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[5] -to fpga_top/cby_12__1_/left_grid_pin_26_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[5] -to fpga_top/cby_12__1_/left_grid_pin_26_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[11] -to fpga_top/cby_12__1_/left_grid_pin_26_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[11] -to fpga_top/cby_12__1_/left_grid_pin_26_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[17] -to fpga_top/cby_12__1_/left_grid_pin_26_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[17] -to fpga_top/cby_12__1_/left_grid_pin_26_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[23] -to fpga_top/cby_12__1_/left_grid_pin_26_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[23] -to fpga_top/cby_12__1_/left_grid_pin_26_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[29] -to fpga_top/cby_12__1_/left_grid_pin_26_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[29] -to fpga_top/cby_12__1_/left_grid_pin_26_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[0] -to fpga_top/cby_12__1_/left_grid_pin_27_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[0] -to fpga_top/cby_12__1_/left_grid_pin_27_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[3] -to fpga_top/cby_12__1_/left_grid_pin_27_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[3] -to fpga_top/cby_12__1_/left_grid_pin_27_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[12] -to fpga_top/cby_12__1_/left_grid_pin_27_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[12] -to fpga_top/cby_12__1_/left_grid_pin_27_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[18] -to fpga_top/cby_12__1_/left_grid_pin_27_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[18] -to fpga_top/cby_12__1_/left_grid_pin_27_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[27] -to fpga_top/cby_12__1_/left_grid_pin_27_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[27] -to fpga_top/cby_12__1_/left_grid_pin_27_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[1] -to fpga_top/cby_12__1_/left_grid_pin_28_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[1] -to fpga_top/cby_12__1_/left_grid_pin_28_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[4] -to fpga_top/cby_12__1_/left_grid_pin_28_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[4] -to fpga_top/cby_12__1_/left_grid_pin_28_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[7] -to fpga_top/cby_12__1_/left_grid_pin_28_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[7] -to fpga_top/cby_12__1_/left_grid_pin_28_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[13] -to fpga_top/cby_12__1_/left_grid_pin_28_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[13] -to fpga_top/cby_12__1_/left_grid_pin_28_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[19] -to fpga_top/cby_12__1_/left_grid_pin_28_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[19] -to fpga_top/cby_12__1_/left_grid_pin_28_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[25] -to fpga_top/cby_12__1_/left_grid_pin_28_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[25] -to fpga_top/cby_12__1_/left_grid_pin_28_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[2] -to fpga_top/cby_12__1_/left_grid_pin_29_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[2] -to fpga_top/cby_12__1_/left_grid_pin_29_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[5] -to fpga_top/cby_12__1_/left_grid_pin_29_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[5] -to fpga_top/cby_12__1_/left_grid_pin_29_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[14] -to fpga_top/cby_12__1_/left_grid_pin_29_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[14] -to fpga_top/cby_12__1_/left_grid_pin_29_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[20] -to fpga_top/cby_12__1_/left_grid_pin_29_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[20] -to fpga_top/cby_12__1_/left_grid_pin_29_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[29] -to fpga_top/cby_12__1_/left_grid_pin_29_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[29] -to fpga_top/cby_12__1_/left_grid_pin_29_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[0] -to fpga_top/cby_12__1_/left_grid_pin_30_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[0] -to fpga_top/cby_12__1_/left_grid_pin_30_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[3] -to fpga_top/cby_12__1_/left_grid_pin_30_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[3] -to fpga_top/cby_12__1_/left_grid_pin_30_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[9] -to fpga_top/cby_12__1_/left_grid_pin_30_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[9] -to fpga_top/cby_12__1_/left_grid_pin_30_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[15] -to fpga_top/cby_12__1_/left_grid_pin_30_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[15] -to fpga_top/cby_12__1_/left_grid_pin_30_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[21] -to fpga_top/cby_12__1_/left_grid_pin_30_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[21] -to fpga_top/cby_12__1_/left_grid_pin_30_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[27] -to fpga_top/cby_12__1_/left_grid_pin_30_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[27] -to fpga_top/cby_12__1_/left_grid_pin_30_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[1] -to fpga_top/cby_12__1_/left_grid_pin_31_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[1] -to fpga_top/cby_12__1_/left_grid_pin_31_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[4] -to fpga_top/cby_12__1_/left_grid_pin_31_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[4] -to fpga_top/cby_12__1_/left_grid_pin_31_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[7] -to fpga_top/cby_12__1_/left_grid_pin_31_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[7] -to fpga_top/cby_12__1_/left_grid_pin_31_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[16] -to fpga_top/cby_12__1_/left_grid_pin_31_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[16] -to fpga_top/cby_12__1_/left_grid_pin_31_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[22] -to fpga_top/cby_12__1_/left_grid_pin_31_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[22] -to fpga_top/cby_12__1_/left_grid_pin_31_[0] 7.247000222e-11 diff --git a/FPGA1212_SOFA_CHD_PNR/FPGA1212_SOFA_CHD_Verilog/SDC/cby_1__1_.sdc b/FPGA1212_SOFA_CHD_PNR/FPGA1212_SOFA_CHD_Verilog/SDC/cby_1__1_.sdc deleted file mode 100644 index db536ab..0000000 --- a/FPGA1212_SOFA_CHD_PNR/FPGA1212_SOFA_CHD_Verilog/SDC/cby_1__1_.sdc +++ /dev/null @@ -1,250 +0,0 @@ -############################################# -# Synopsys Design Constraints (SDC) -# For FPGA fabric -# Description: Constrain timing of Connection Block cby_1__1_ for PnR -# Author: Xifan TANG -# Organization: University of Utah -# Date: Tue Dec 8 15:34:14 2020 -############################################# - -############################################# -# Define time unit -############################################# -set_units -time s - -set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[0] -to fpga_top/cby_1__1_/chany_bottom_out[0] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[0] -to fpga_top/cby_1__1_/chany_top_out[0] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[1] -to fpga_top/cby_1__1_/chany_bottom_out[1] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[1] -to fpga_top/cby_1__1_/chany_top_out[1] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[2] -to fpga_top/cby_1__1_/chany_bottom_out[2] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[2] -to fpga_top/cby_1__1_/chany_top_out[2] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[3] -to fpga_top/cby_1__1_/chany_bottom_out[3] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[3] -to fpga_top/cby_1__1_/chany_top_out[3] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[4] -to fpga_top/cby_1__1_/chany_bottom_out[4] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[4] -to fpga_top/cby_1__1_/chany_top_out[4] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[5] -to fpga_top/cby_1__1_/chany_bottom_out[5] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[5] -to fpga_top/cby_1__1_/chany_top_out[5] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[6] -to fpga_top/cby_1__1_/chany_bottom_out[6] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[6] -to fpga_top/cby_1__1_/chany_top_out[6] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[7] -to fpga_top/cby_1__1_/chany_bottom_out[7] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[7] -to fpga_top/cby_1__1_/chany_top_out[7] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[8] -to fpga_top/cby_1__1_/chany_bottom_out[8] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[8] -to fpga_top/cby_1__1_/chany_top_out[8] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[9] -to fpga_top/cby_1__1_/chany_bottom_out[9] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[9] -to fpga_top/cby_1__1_/chany_top_out[9] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[10] -to fpga_top/cby_1__1_/chany_bottom_out[10] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[10] -to fpga_top/cby_1__1_/chany_top_out[10] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[11] -to fpga_top/cby_1__1_/chany_bottom_out[11] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[11] -to fpga_top/cby_1__1_/chany_top_out[11] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[12] -to fpga_top/cby_1__1_/chany_bottom_out[12] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[12] -to fpga_top/cby_1__1_/chany_top_out[12] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[13] -to fpga_top/cby_1__1_/chany_bottom_out[13] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[13] -to fpga_top/cby_1__1_/chany_top_out[13] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[14] -to fpga_top/cby_1__1_/chany_bottom_out[14] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[14] -to fpga_top/cby_1__1_/chany_top_out[14] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[15] -to fpga_top/cby_1__1_/chany_bottom_out[15] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[15] -to fpga_top/cby_1__1_/chany_top_out[15] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[16] -to fpga_top/cby_1__1_/chany_bottom_out[16] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[16] -to fpga_top/cby_1__1_/chany_top_out[16] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[17] -to fpga_top/cby_1__1_/chany_bottom_out[17] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[17] -to fpga_top/cby_1__1_/chany_top_out[17] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[18] -to fpga_top/cby_1__1_/chany_bottom_out[18] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[18] -to fpga_top/cby_1__1_/chany_top_out[18] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[19] -to fpga_top/cby_1__1_/chany_bottom_out[19] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[19] -to fpga_top/cby_1__1_/chany_top_out[19] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[20] -to fpga_top/cby_1__1_/chany_bottom_out[20] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[20] -to fpga_top/cby_1__1_/chany_top_out[20] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[21] -to fpga_top/cby_1__1_/chany_bottom_out[21] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[21] -to fpga_top/cby_1__1_/chany_top_out[21] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[22] -to fpga_top/cby_1__1_/chany_bottom_out[22] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[22] -to fpga_top/cby_1__1_/chany_top_out[22] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[23] -to fpga_top/cby_1__1_/chany_bottom_out[23] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[23] -to fpga_top/cby_1__1_/chany_top_out[23] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[24] -to fpga_top/cby_1__1_/chany_bottom_out[24] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[24] -to fpga_top/cby_1__1_/chany_top_out[24] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[25] -to fpga_top/cby_1__1_/chany_bottom_out[25] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[25] -to fpga_top/cby_1__1_/chany_top_out[25] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[26] -to fpga_top/cby_1__1_/chany_bottom_out[26] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[26] -to fpga_top/cby_1__1_/chany_top_out[26] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[27] -to fpga_top/cby_1__1_/chany_bottom_out[27] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[27] -to fpga_top/cby_1__1_/chany_top_out[27] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[28] -to fpga_top/cby_1__1_/chany_bottom_out[28] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[28] -to fpga_top/cby_1__1_/chany_top_out[28] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[29] -to fpga_top/cby_1__1_/chany_bottom_out[29] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[29] -to fpga_top/cby_1__1_/chany_top_out[29] 2.272500113e-12 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[0] -to fpga_top/cby_1__1_/left_grid_pin_16_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[0] -to fpga_top/cby_1__1_/left_grid_pin_16_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[3] -to fpga_top/cby_1__1_/left_grid_pin_16_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[3] -to fpga_top/cby_1__1_/left_grid_pin_16_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[6] -to fpga_top/cby_1__1_/left_grid_pin_16_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[6] -to fpga_top/cby_1__1_/left_grid_pin_16_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[12] -to fpga_top/cby_1__1_/left_grid_pin_16_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[12] -to fpga_top/cby_1__1_/left_grid_pin_16_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[18] -to fpga_top/cby_1__1_/left_grid_pin_16_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[18] -to fpga_top/cby_1__1_/left_grid_pin_16_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[24] -to fpga_top/cby_1__1_/left_grid_pin_16_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[24] -to fpga_top/cby_1__1_/left_grid_pin_16_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[1] -to fpga_top/cby_1__1_/left_grid_pin_17_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[1] -to fpga_top/cby_1__1_/left_grid_pin_17_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[4] -to fpga_top/cby_1__1_/left_grid_pin_17_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[4] -to fpga_top/cby_1__1_/left_grid_pin_17_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[7] -to fpga_top/cby_1__1_/left_grid_pin_17_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[7] -to fpga_top/cby_1__1_/left_grid_pin_17_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[16] -to fpga_top/cby_1__1_/left_grid_pin_17_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[16] -to fpga_top/cby_1__1_/left_grid_pin_17_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[25] -to fpga_top/cby_1__1_/left_grid_pin_17_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[25] -to fpga_top/cby_1__1_/left_grid_pin_17_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[2] -to fpga_top/cby_1__1_/left_grid_pin_18_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[2] -to fpga_top/cby_1__1_/left_grid_pin_18_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[5] -to fpga_top/cby_1__1_/left_grid_pin_18_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[5] -to fpga_top/cby_1__1_/left_grid_pin_18_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[8] -to fpga_top/cby_1__1_/left_grid_pin_18_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[8] -to fpga_top/cby_1__1_/left_grid_pin_18_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[14] -to fpga_top/cby_1__1_/left_grid_pin_18_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[14] -to fpga_top/cby_1__1_/left_grid_pin_18_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[20] -to fpga_top/cby_1__1_/left_grid_pin_18_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[20] -to fpga_top/cby_1__1_/left_grid_pin_18_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[26] -to fpga_top/cby_1__1_/left_grid_pin_18_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[26] -to fpga_top/cby_1__1_/left_grid_pin_18_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[0] -to fpga_top/cby_1__1_/left_grid_pin_19_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[0] -to fpga_top/cby_1__1_/left_grid_pin_19_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[3] -to fpga_top/cby_1__1_/left_grid_pin_19_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[3] -to fpga_top/cby_1__1_/left_grid_pin_19_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[9] -to fpga_top/cby_1__1_/left_grid_pin_19_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[9] -to fpga_top/cby_1__1_/left_grid_pin_19_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[18] -to fpga_top/cby_1__1_/left_grid_pin_19_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[18] -to fpga_top/cby_1__1_/left_grid_pin_19_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[27] -to fpga_top/cby_1__1_/left_grid_pin_19_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[27] -to fpga_top/cby_1__1_/left_grid_pin_19_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[1] -to fpga_top/cby_1__1_/left_grid_pin_20_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[1] -to fpga_top/cby_1__1_/left_grid_pin_20_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[4] -to fpga_top/cby_1__1_/left_grid_pin_20_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[4] -to fpga_top/cby_1__1_/left_grid_pin_20_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[10] -to fpga_top/cby_1__1_/left_grid_pin_20_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[10] -to fpga_top/cby_1__1_/left_grid_pin_20_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[16] -to fpga_top/cby_1__1_/left_grid_pin_20_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[16] -to fpga_top/cby_1__1_/left_grid_pin_20_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[22] -to fpga_top/cby_1__1_/left_grid_pin_20_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[22] -to fpga_top/cby_1__1_/left_grid_pin_20_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[28] -to fpga_top/cby_1__1_/left_grid_pin_20_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[28] -to fpga_top/cby_1__1_/left_grid_pin_20_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[2] -to fpga_top/cby_1__1_/left_grid_pin_21_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[2] -to fpga_top/cby_1__1_/left_grid_pin_21_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[5] -to fpga_top/cby_1__1_/left_grid_pin_21_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[5] -to fpga_top/cby_1__1_/left_grid_pin_21_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[11] -to fpga_top/cby_1__1_/left_grid_pin_21_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[11] -to fpga_top/cby_1__1_/left_grid_pin_21_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[20] -to fpga_top/cby_1__1_/left_grid_pin_21_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[20] -to fpga_top/cby_1__1_/left_grid_pin_21_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[29] -to fpga_top/cby_1__1_/left_grid_pin_21_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[29] -to fpga_top/cby_1__1_/left_grid_pin_21_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[0] -to fpga_top/cby_1__1_/left_grid_pin_22_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[0] -to fpga_top/cby_1__1_/left_grid_pin_22_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[3] -to fpga_top/cby_1__1_/left_grid_pin_22_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[3] -to fpga_top/cby_1__1_/left_grid_pin_22_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[6] -to fpga_top/cby_1__1_/left_grid_pin_22_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[6] -to fpga_top/cby_1__1_/left_grid_pin_22_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[12] -to fpga_top/cby_1__1_/left_grid_pin_22_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[12] -to fpga_top/cby_1__1_/left_grid_pin_22_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[18] -to fpga_top/cby_1__1_/left_grid_pin_22_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[18] -to fpga_top/cby_1__1_/left_grid_pin_22_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[24] -to fpga_top/cby_1__1_/left_grid_pin_22_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[24] -to fpga_top/cby_1__1_/left_grid_pin_22_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[1] -to fpga_top/cby_1__1_/left_grid_pin_23_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[1] -to fpga_top/cby_1__1_/left_grid_pin_23_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[4] -to fpga_top/cby_1__1_/left_grid_pin_23_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[4] -to fpga_top/cby_1__1_/left_grid_pin_23_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[7] -to fpga_top/cby_1__1_/left_grid_pin_23_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[7] -to fpga_top/cby_1__1_/left_grid_pin_23_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[13] -to fpga_top/cby_1__1_/left_grid_pin_23_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[13] -to fpga_top/cby_1__1_/left_grid_pin_23_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[22] -to fpga_top/cby_1__1_/left_grid_pin_23_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[22] -to fpga_top/cby_1__1_/left_grid_pin_23_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[2] -to fpga_top/cby_1__1_/left_grid_pin_24_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[2] -to fpga_top/cby_1__1_/left_grid_pin_24_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[5] -to fpga_top/cby_1__1_/left_grid_pin_24_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[5] -to fpga_top/cby_1__1_/left_grid_pin_24_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[8] -to fpga_top/cby_1__1_/left_grid_pin_24_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[8] -to fpga_top/cby_1__1_/left_grid_pin_24_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[14] -to fpga_top/cby_1__1_/left_grid_pin_24_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[14] -to fpga_top/cby_1__1_/left_grid_pin_24_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[20] -to fpga_top/cby_1__1_/left_grid_pin_24_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[20] -to fpga_top/cby_1__1_/left_grid_pin_24_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[26] -to fpga_top/cby_1__1_/left_grid_pin_24_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[26] -to fpga_top/cby_1__1_/left_grid_pin_24_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[0] -to fpga_top/cby_1__1_/left_grid_pin_25_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[0] -to fpga_top/cby_1__1_/left_grid_pin_25_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[3] -to fpga_top/cby_1__1_/left_grid_pin_25_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[3] -to fpga_top/cby_1__1_/left_grid_pin_25_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[9] -to fpga_top/cby_1__1_/left_grid_pin_25_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[9] -to fpga_top/cby_1__1_/left_grid_pin_25_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[15] -to fpga_top/cby_1__1_/left_grid_pin_25_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[15] -to fpga_top/cby_1__1_/left_grid_pin_25_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[24] -to fpga_top/cby_1__1_/left_grid_pin_25_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[24] -to fpga_top/cby_1__1_/left_grid_pin_25_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[1] -to fpga_top/cby_1__1_/left_grid_pin_26_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[1] -to fpga_top/cby_1__1_/left_grid_pin_26_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[4] -to fpga_top/cby_1__1_/left_grid_pin_26_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[4] -to fpga_top/cby_1__1_/left_grid_pin_26_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[10] -to fpga_top/cby_1__1_/left_grid_pin_26_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[10] -to fpga_top/cby_1__1_/left_grid_pin_26_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[16] -to fpga_top/cby_1__1_/left_grid_pin_26_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[16] -to fpga_top/cby_1__1_/left_grid_pin_26_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[22] -to fpga_top/cby_1__1_/left_grid_pin_26_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[22] -to fpga_top/cby_1__1_/left_grid_pin_26_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[28] -to fpga_top/cby_1__1_/left_grid_pin_26_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[28] -to fpga_top/cby_1__1_/left_grid_pin_26_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[2] -to fpga_top/cby_1__1_/left_grid_pin_27_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[2] -to fpga_top/cby_1__1_/left_grid_pin_27_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[5] -to fpga_top/cby_1__1_/left_grid_pin_27_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[5] -to fpga_top/cby_1__1_/left_grid_pin_27_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[11] -to fpga_top/cby_1__1_/left_grid_pin_27_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[11] -to fpga_top/cby_1__1_/left_grid_pin_27_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[17] -to fpga_top/cby_1__1_/left_grid_pin_27_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[17] -to fpga_top/cby_1__1_/left_grid_pin_27_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[26] -to fpga_top/cby_1__1_/left_grid_pin_27_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[26] -to fpga_top/cby_1__1_/left_grid_pin_27_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[0] -to fpga_top/cby_1__1_/left_grid_pin_28_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[0] -to fpga_top/cby_1__1_/left_grid_pin_28_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[3] -to fpga_top/cby_1__1_/left_grid_pin_28_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[3] -to fpga_top/cby_1__1_/left_grid_pin_28_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[6] -to fpga_top/cby_1__1_/left_grid_pin_28_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[6] -to fpga_top/cby_1__1_/left_grid_pin_28_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[12] -to fpga_top/cby_1__1_/left_grid_pin_28_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[12] -to fpga_top/cby_1__1_/left_grid_pin_28_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[18] -to fpga_top/cby_1__1_/left_grid_pin_28_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[18] -to fpga_top/cby_1__1_/left_grid_pin_28_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[24] -to fpga_top/cby_1__1_/left_grid_pin_28_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[24] -to fpga_top/cby_1__1_/left_grid_pin_28_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[1] -to fpga_top/cby_1__1_/left_grid_pin_29_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[1] -to fpga_top/cby_1__1_/left_grid_pin_29_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[4] -to fpga_top/cby_1__1_/left_grid_pin_29_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[4] -to fpga_top/cby_1__1_/left_grid_pin_29_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[13] -to fpga_top/cby_1__1_/left_grid_pin_29_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[13] -to fpga_top/cby_1__1_/left_grid_pin_29_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[19] -to fpga_top/cby_1__1_/left_grid_pin_29_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[19] -to fpga_top/cby_1__1_/left_grid_pin_29_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[28] -to fpga_top/cby_1__1_/left_grid_pin_29_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[28] -to fpga_top/cby_1__1_/left_grid_pin_29_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[2] -to fpga_top/cby_1__1_/left_grid_pin_30_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[2] -to fpga_top/cby_1__1_/left_grid_pin_30_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[5] -to fpga_top/cby_1__1_/left_grid_pin_30_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[5] -to fpga_top/cby_1__1_/left_grid_pin_30_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[8] -to fpga_top/cby_1__1_/left_grid_pin_30_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[8] -to fpga_top/cby_1__1_/left_grid_pin_30_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[14] -to fpga_top/cby_1__1_/left_grid_pin_30_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[14] -to fpga_top/cby_1__1_/left_grid_pin_30_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[20] -to fpga_top/cby_1__1_/left_grid_pin_30_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[20] -to fpga_top/cby_1__1_/left_grid_pin_30_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[26] -to fpga_top/cby_1__1_/left_grid_pin_30_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[26] -to fpga_top/cby_1__1_/left_grid_pin_30_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[0] -to fpga_top/cby_1__1_/left_grid_pin_31_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[0] -to fpga_top/cby_1__1_/left_grid_pin_31_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[3] -to fpga_top/cby_1__1_/left_grid_pin_31_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[3] -to fpga_top/cby_1__1_/left_grid_pin_31_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[6] -to fpga_top/cby_1__1_/left_grid_pin_31_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[6] -to fpga_top/cby_1__1_/left_grid_pin_31_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[15] -to fpga_top/cby_1__1_/left_grid_pin_31_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[15] -to fpga_top/cby_1__1_/left_grid_pin_31_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[21] -to fpga_top/cby_1__1_/left_grid_pin_31_[0] 7.247000222e-11 -set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[21] -to fpga_top/cby_1__1_/left_grid_pin_31_[0] 7.247000222e-11 diff --git a/FPGA1212_SOFA_CHD_PNR/FPGA1212_SOFA_CHD_Verilog/SDC/disable_configurable_memory_outputs.sdc b/FPGA1212_SOFA_CHD_PNR/FPGA1212_SOFA_CHD_Verilog/SDC/disable_configurable_memory_outputs.sdc deleted file mode 100644 index 4861fa1..0000000 --- a/FPGA1212_SOFA_CHD_PNR/FPGA1212_SOFA_CHD_Verilog/SDC/disable_configurable_memory_outputs.sdc +++ /dev/null @@ -1,132 +0,0 @@ -############################################# -# Synopsys Design Constraints (SDC) -# For FPGA fabric -# Description: Disable configurable memory outputs for PnR -# Author: Xifan TANG -# Organization: University of Utah -# Date: Tue Dec 8 15:34:14 2020 -############################################# - -set_disable_timing fpga_core_uut/sb_*__*_/mem_bottom_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q -set_disable_timing fpga_core_uut/sb_*__*_/mem_bottom_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q -set_disable_timing fpga_core_uut/sb_*__*_/mem_bottom_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q -set_disable_timing fpga_core_uut/sb_*__*_/mem_left_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q -set_disable_timing fpga_core_uut/sb_*__*_/mem_left_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q -set_disable_timing fpga_core_uut/sb_*__*_/mem_left_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q -set_disable_timing fpga_core_uut/cbx_*__*_/mem_bottom_ipin_*/sky*_fd_sc_hd__dfrtp_*_*_/Q -set_disable_timing fpga_core_uut/cbx_*__*_/mem_top_ipin_*/sky*_fd_sc_hd__dfrtp_*_*_/Q -set_disable_timing fpga_core_uut/cbx_*__*_/mem_top_ipin_*/sky*_fd_sc_hd__dfrtp_*_*_/Q -set_disable_timing fpga_core_uut/grid_io_top_top_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/EMBEDDED_IO_HD_sky*_fd_sc_hd__dfrtp_*_mem/sky*_fd_sc_hd__dfrtp_*_*_/Q -set_disable_timing fpga_core_uut/sb_*__*_/mem_right_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q -set_disable_timing fpga_core_uut/sb_*__*_/mem_right_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q -set_disable_timing fpga_core_uut/sb_*__*_/mem_right_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q -set_disable_timing fpga_core_uut/sb_*__*_/mem_right_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q -set_disable_timing fpga_core_uut/sb_*__*_/mem_right_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q -set_disable_timing fpga_core_uut/sb_*__*_/mem_right_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q -set_disable_timing fpga_core_uut/sb_*__*_/mem_bottom_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q -set_disable_timing fpga_core_uut/sb_*__*_/mem_bottom_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q -set_disable_timing fpga_core_uut/sb_*__*_/mem_bottom_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q -set_disable_timing fpga_core_uut/sb_*__*_/mem_bottom_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q -set_disable_timing fpga_core_uut/sb_*__*_/mem_bottom_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q -set_disable_timing fpga_core_uut/sb_*__*_/mem_left_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q -set_disable_timing fpga_core_uut/sb_*__*_/mem_left_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q -set_disable_timing fpga_core_uut/sb_*__*_/mem_left_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q -set_disable_timing fpga_core_uut/sb_*__*_/mem_left_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q -set_disable_timing fpga_core_uut/sb_*__*_/mem_left_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q -set_disable_timing fpga_core_uut/sb_*__*_/mem_left_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q -set_disable_timing fpga_core_uut/sb_*__*_/mem_right_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q -set_disable_timing fpga_core_uut/sb_*__*_/mem_right_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q -set_disable_timing fpga_core_uut/sb_*__*_/mem_right_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q -set_disable_timing fpga_core_uut/sb_*__*_/mem_bottom_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q -set_disable_timing fpga_core_uut/cby_*__*_/mem_right_ipin_*/sky*_fd_sc_hd__dfrtp_*_*_/Q -set_disable_timing fpga_core_uut/grid_io_left_left_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/EMBEDDED_IO_HD_sky*_fd_sc_hd__dfrtp_*_mem/sky*_fd_sc_hd__dfrtp_*_*_/Q -set_disable_timing fpga_core_uut/grid_clb_*__*_/logical_tile_clb_mode_clb__*/logical_tile_clb_mode_default__fle_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut*_*/frac_lut*_sky*_fd_sc_hd__dfrtp_*_mem/sky*_fd_sc_hd__dfrtp_*_*_/Q -set_disable_timing fpga_core_uut/grid_clb_*__*_/logical_tile_clb_mode_clb__*/logical_tile_clb_mode_default__fle_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_*/mem_frac_logic_out_*/sky*_fd_sc_hd__dfrtp_*_*_/Q -set_disable_timing fpga_core_uut/grid_clb_*__*_/logical_tile_clb_mode_clb__*/logical_tile_clb_mode_default__fle_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_*/mem_frac_lut*_*_in_*/sky*_fd_sc_hd__dfrtp_*_*_/Q -set_disable_timing fpga_core_uut/grid_clb_*__*_/logical_tile_clb_mode_clb__*/logical_tile_clb_mode_default__fle_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_*/mem_fabric_out_*/sky*_fd_sc_hd__dfrtp_*_*_/Q -set_disable_timing fpga_core_uut/grid_clb_*__*_/logical_tile_clb_mode_clb__*/logical_tile_clb_mode_default__fle_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_*/mem_ff_*_D_*/sky*_fd_sc_hd__dfrtp_*_*_/Q -set_disable_timing fpga_core_uut/cby_*__*_/mem_right_ipin_*/sky*_fd_sc_hd__dfrtp_*_*_/Q -set_disable_timing fpga_core_uut/cby_*__*_/mem_right_ipin_*/sky*_fd_sc_hd__dfrtp_*_*_/Q -set_disable_timing fpga_core_uut/cby_*__*_/mem_left_ipin_*/sky*_fd_sc_hd__dfrtp_*_*_/Q -set_disable_timing fpga_core_uut/cby_*__*_/mem_right_ipin_*/sky*_fd_sc_hd__dfrtp_*_*_/Q -set_disable_timing fpga_core_uut/cby_*__*_/mem_right_ipin_*/sky*_fd_sc_hd__dfrtp_*_*_/Q -set_disable_timing fpga_core_uut/grid_io_right_right_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/EMBEDDED_IO_HD_sky*_fd_sc_hd__dfrtp_*_mem/sky*_fd_sc_hd__dfrtp_*_*_/Q -set_disable_timing fpga_core_uut/sb_*__*_/mem_top_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q -set_disable_timing fpga_core_uut/sb_*__*_/mem_top_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q -set_disable_timing fpga_core_uut/sb_*__*_/mem_top_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q -set_disable_timing fpga_core_uut/sb_*__*_/mem_top_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q -set_disable_timing fpga_core_uut/sb_*__*_/mem_bottom_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q -set_disable_timing fpga_core_uut/sb_*__*_/mem_bottom_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q -set_disable_timing fpga_core_uut/sb_*__*_/mem_bottom_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q -set_disable_timing fpga_core_uut/sb_*__*_/mem_bottom_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q -set_disable_timing fpga_core_uut/sb_*__*_/mem_bottom_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q -set_disable_timing fpga_core_uut/sb_*__*_/mem_bottom_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q -set_disable_timing fpga_core_uut/sb_*__*_/mem_bottom_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q -set_disable_timing fpga_core_uut/sb_*__*_/mem_left_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q -set_disable_timing fpga_core_uut/sb_*__*_/mem_left_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q -set_disable_timing fpga_core_uut/sb_*__*_/mem_left_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q -set_disable_timing fpga_core_uut/sb_*__*_/mem_left_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q -set_disable_timing fpga_core_uut/sb_*__*_/mem_left_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q -set_disable_timing fpga_core_uut/cbx_*__*_/mem_top_ipin_*/sky*_fd_sc_hd__dfrtp_*_*_/Q -set_disable_timing fpga_core_uut/cbx_*__*_/mem_top_ipin_*/sky*_fd_sc_hd__dfrtp_*_*_/Q -set_disable_timing fpga_core_uut/sb_*__*_/mem_top_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q -set_disable_timing fpga_core_uut/sb_*__*_/mem_top_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q -set_disable_timing fpga_core_uut/sb_*__*_/mem_top_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q -set_disable_timing fpga_core_uut/sb_*__*_/mem_top_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q -set_disable_timing fpga_core_uut/sb_*__*_/mem_top_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q -set_disable_timing fpga_core_uut/sb_*__*_/mem_right_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q -set_disable_timing fpga_core_uut/sb_*__*_/mem_right_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q -set_disable_timing fpga_core_uut/sb_*__*_/mem_right_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q -set_disable_timing fpga_core_uut/sb_*__*_/mem_right_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q -set_disable_timing fpga_core_uut/sb_*__*_/mem_right_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q -set_disable_timing fpga_core_uut/sb_*__*_/mem_bottom_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q -set_disable_timing fpga_core_uut/sb_*__*_/mem_bottom_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q -set_disable_timing fpga_core_uut/sb_*__*_/mem_bottom_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q -set_disable_timing fpga_core_uut/sb_*__*_/mem_bottom_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q -set_disable_timing fpga_core_uut/sb_*__*_/mem_bottom_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q -set_disable_timing fpga_core_uut/sb_*__*_/mem_left_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q -set_disable_timing fpga_core_uut/sb_*__*_/mem_left_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q -set_disable_timing fpga_core_uut/sb_*__*_/mem_left_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q -set_disable_timing fpga_core_uut/sb_*__*_/mem_left_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q -set_disable_timing fpga_core_uut/sb_*__*_/mem_left_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q -set_disable_timing fpga_core_uut/sb_*__*_/mem_top_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q -set_disable_timing fpga_core_uut/sb_*__*_/mem_top_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q -set_disable_timing fpga_core_uut/sb_*__*_/mem_top_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q -set_disable_timing fpga_core_uut/sb_*__*_/mem_top_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q -set_disable_timing fpga_core_uut/sb_*__*_/mem_right_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q -set_disable_timing fpga_core_uut/sb_*__*_/mem_right_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q -set_disable_timing fpga_core_uut/sb_*__*_/mem_right_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q -set_disable_timing fpga_core_uut/sb_*__*_/mem_right_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q -set_disable_timing fpga_core_uut/sb_*__*_/mem_right_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q -set_disable_timing fpga_core_uut/sb_*__*_/mem_bottom_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q -set_disable_timing fpga_core_uut/sb_*__*_/mem_bottom_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q -set_disable_timing fpga_core_uut/sb_*__*_/mem_bottom_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q -set_disable_timing fpga_core_uut/sb_*__*_/mem_bottom_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q -set_disable_timing fpga_core_uut/sb_*__*_/mem_top_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q -set_disable_timing fpga_core_uut/sb_*__*_/mem_top_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q -set_disable_timing fpga_core_uut/sb_*__*_/mem_top_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q -set_disable_timing fpga_core_uut/sb_*__*_/mem_left_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q -set_disable_timing fpga_core_uut/sb_*__*_/mem_left_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q -set_disable_timing fpga_core_uut/sb_*__*_/mem_left_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q -set_disable_timing fpga_core_uut/cbx_*__*_/mem_top_ipin_*/sky*_fd_sc_hd__dfrtp_*_*_/Q -set_disable_timing fpga_core_uut/grid_io_bottom_bottom_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/EMBEDDED_IO_HD_sky*_fd_sc_hd__dfrtp_*_mem/sky*_fd_sc_hd__dfrtp_*_*_/Q -set_disable_timing fpga_core_uut/sb_*__*_/mem_top_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q -set_disable_timing fpga_core_uut/sb_*__*_/mem_top_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q -set_disable_timing fpga_core_uut/sb_*__*_/mem_top_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q -set_disable_timing fpga_core_uut/sb_*__*_/mem_top_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q -set_disable_timing fpga_core_uut/sb_*__*_/mem_top_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q -set_disable_timing fpga_core_uut/sb_*__*_/mem_top_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q -set_disable_timing fpga_core_uut/sb_*__*_/mem_right_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q -set_disable_timing fpga_core_uut/sb_*__*_/mem_right_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q -set_disable_timing fpga_core_uut/sb_*__*_/mem_right_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q -set_disable_timing fpga_core_uut/sb_*__*_/mem_right_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q -set_disable_timing fpga_core_uut/sb_*__*_/mem_right_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q -set_disable_timing fpga_core_uut/sb_*__*_/mem_right_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q -set_disable_timing fpga_core_uut/sb_*__*_/mem_left_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q -set_disable_timing fpga_core_uut/sb_*__*_/mem_left_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q -set_disable_timing fpga_core_uut/sb_*__*_/mem_left_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q -set_disable_timing fpga_core_uut/sb_*__*_/mem_left_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q -set_disable_timing fpga_core_uut/sb_*__*_/mem_top_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q -set_disable_timing fpga_core_uut/sb_*__*_/mem_right_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q -set_disable_timing fpga_core_uut/sb_*__*_/mem_right_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q -set_disable_timing fpga_core_uut/sb_*__*_/mem_right_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q diff --git a/FPGA1212_SOFA_CHD_PNR/FPGA1212_SOFA_CHD_Verilog/SDC/disable_configure_ports.sdc b/FPGA1212_SOFA_CHD_PNR/FPGA1212_SOFA_CHD_Verilog/SDC/disable_configure_ports.sdc index e1ef320..cef27d3 100644 --- a/FPGA1212_SOFA_CHD_PNR/FPGA1212_SOFA_CHD_Verilog/SDC/disable_configure_ports.sdc +++ b/FPGA1212_SOFA_CHD_PNR/FPGA1212_SOFA_CHD_Verilog/SDC/disable_configure_ports.sdc @@ -4,7 +4,7 @@ # Description: Disable configuration outputs of all the programmable cells for PnR # Author: Xifan TANG # Organization: University of Utah -# Date: Tue Dec 8 15:34:14 2020 +# Date: Sun Dec 13 16:23:06 2020 ############################################# set_disable_timing fpga_core_uut/grid_clb_*__*_/logical_tile_clb_mode_clb__*/logical_tile_clb_mode_default__fle_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut*_*/frac_lut*_*_/sram diff --git a/FPGA1212_SOFA_CHD_PNR/FPGA1212_SOFA_CHD_Verilog/SDC/disable_routing_multiplexer_outputs.sdc b/FPGA1212_SOFA_CHD_PNR/FPGA1212_SOFA_CHD_Verilog/SDC/disable_routing_multiplexer_outputs.sdc deleted file mode 100644 index 7763e22..0000000 --- a/FPGA1212_SOFA_CHD_PNR/FPGA1212_SOFA_CHD_Verilog/SDC/disable_routing_multiplexer_outputs.sdc +++ /dev/null @@ -1,127 +0,0 @@ -############################################# -# Synopsys Design Constraints (SDC) -# For FPGA fabric -# Description: Disable routing multiplexer outputs for PnR -# Author: Xifan TANG -# Organization: University of Utah -# Date: Tue Dec 8 15:34:14 2020 -############################################# - -set_disable_timing fpga_core_uut/cbx_*__*_/mux_top_ipin_*/out -set_disable_timing fpga_core_uut/cbx_*__*_/mux_top_ipin_*/out -set_disable_timing fpga_core_uut/cbx_*__*_/mux_bottom_ipin_*/out -set_disable_timing fpga_core_uut/cbx_*__*_/mux_top_ipin_*/out -set_disable_timing fpga_core_uut/cby_*__*_/mux_right_ipin_*/out -set_disable_timing fpga_core_uut/cby_*__*_/mux_right_ipin_*/out -set_disable_timing fpga_core_uut/cby_*__*_/mux_left_ipin_*/out -set_disable_timing fpga_core_uut/cby_*__*_/mux_right_ipin_*/out -set_disable_timing fpga_core_uut/cbx_*__*_/mux_top_ipin_*/out -set_disable_timing fpga_core_uut/cbx_*__*_/mux_top_ipin_*/out -set_disable_timing fpga_core_uut/cby_*__*_/mux_right_ipin_*/out -set_disable_timing fpga_core_uut/cby_*__*_/mux_right_ipin_*/out -set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/out -set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/out -set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/out -set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/out -set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/out -set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/out -set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/out -set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/out -set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/out -set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/out -set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/out -set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/out -set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/out -set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/out -set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/out -set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/out -set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/out -set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/out -set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/out -set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/out -set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/out -set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/out -set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/out -set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/out -set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/out -set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/out -set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/out -set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/out -set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/out -set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/out -set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/out -set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/out -set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/out -set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/out -set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/out -set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/out -set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/out -set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/out -set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/out -set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/out -set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/out -set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/out -set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/out -set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/out -set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/out -set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/out -set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/out -set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/out -set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/out -set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/out -set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/out -set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/out -set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/out -set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/out -set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/out -set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/out -set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/out -set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/out -set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/out -set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/out -set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/out -set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/out -set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/out -set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/out -set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/out -set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/out -set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/out -set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/out -set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/out -set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/out -set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/out -set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/out -set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/out -set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/out -set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/out -set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/out -set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/out -set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/out -set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/out -set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/out -set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/out -set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/out -set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/out -set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/out -set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/out -set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/out -set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/out -set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/out -set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/out -set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/out -set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/out -set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/out -set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/out -set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/out -set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/out -set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/out -set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/out -set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/out -set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/out -set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/out -set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/out -set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/out -set_disable_timing fpga_core_uut/grid_clb_*__*_/logical_tile_clb_mode_clb__*/logical_tile_clb_mode_default__fle_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_*/mux_fabric_out_*/out -set_disable_timing fpga_core_uut/grid_clb_*__*_/logical_tile_clb_mode_clb__*/logical_tile_clb_mode_default__fle_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_*/mux_frac_logic_out_*/out -set_disable_timing fpga_core_uut/grid_clb_*__*_/logical_tile_clb_mode_clb__*/logical_tile_clb_mode_default__fle_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_*/mux_frac_lut*_*_in_*/out -set_disable_timing fpga_core_uut/grid_clb_*__*_/logical_tile_clb_mode_clb__*/logical_tile_clb_mode_default__fle_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_*/mux_ff_*_D_*/out diff --git a/FPGA1212_SOFA_CHD_PNR/FPGA1212_SOFA_CHD_Verilog/SDC/disable_sb_outputs.sdc b/FPGA1212_SOFA_CHD_PNR/FPGA1212_SOFA_CHD_Verilog/SDC/disable_sb_outputs.sdc deleted file mode 100644 index 134f4c5..0000000 --- a/FPGA1212_SOFA_CHD_PNR/FPGA1212_SOFA_CHD_Verilog/SDC/disable_sb_outputs.sdc +++ /dev/null @@ -1,75 +0,0 @@ -############################################# -# Synopsys Design Constraints (SDC) -# For FPGA fabric -# Description: Disable Switch Block outputs for PnR -# Author: Xifan TANG -# Organization: University of Utah -# Date: Tue Dec 8 15:34:14 2020 -############################################# - -set_disable_timing fpga_core_uut/sb_*__*_/chany_top_out - -set_disable_timing fpga_core_uut/sb_*__*_/chanx_right_out - -set_disable_timing fpga_core_uut/sb_*__*_/ccff_tail - -set_disable_timing fpga_core_uut/sb_*__*_/chany_top_out - -set_disable_timing fpga_core_uut/sb_*__*_/chanx_right_out - -set_disable_timing fpga_core_uut/sb_*__*_/chany_bottom_out - -set_disable_timing fpga_core_uut/sb_*__*_/ccff_tail - -set_disable_timing fpga_core_uut/sb_*__*_/chanx_right_out - -set_disable_timing fpga_core_uut/sb_*__*_/chany_bottom_out - -set_disable_timing fpga_core_uut/sb_*__*_/ccff_tail - -set_disable_timing fpga_core_uut/sb_*__*_/chany_top_out - -set_disable_timing fpga_core_uut/sb_*__*_/chanx_right_out - -set_disable_timing fpga_core_uut/sb_*__*_/chanx_left_out - -set_disable_timing fpga_core_uut/sb_*__*_/ccff_tail - -set_disable_timing fpga_core_uut/sb_*__*_/chany_top_out - -set_disable_timing fpga_core_uut/sb_*__*_/chanx_right_out - -set_disable_timing fpga_core_uut/sb_*__*_/chany_bottom_out - -set_disable_timing fpga_core_uut/sb_*__*_/chanx_left_out - -set_disable_timing fpga_core_uut/sb_*__*_/ccff_tail - -set_disable_timing fpga_core_uut/sb_*__*_/chanx_right_out - -set_disable_timing fpga_core_uut/sb_*__*_/chany_bottom_out - -set_disable_timing fpga_core_uut/sb_*__*_/chanx_left_out - -set_disable_timing fpga_core_uut/sb_*__*_/ccff_tail - -set_disable_timing fpga_core_uut/sb_*__*_/chany_top_out - -set_disable_timing fpga_core_uut/sb_*__*_/chanx_left_out - -set_disable_timing fpga_core_uut/sb_*__*_/ccff_tail - -set_disable_timing fpga_core_uut/sb_*__*_/chany_top_out - -set_disable_timing fpga_core_uut/sb_*__*_/chany_bottom_out - -set_disable_timing fpga_core_uut/sb_*__*_/chanx_left_out - -set_disable_timing fpga_core_uut/sb_*__*_/ccff_tail - -set_disable_timing fpga_core_uut/sb_*__*_/chany_bottom_out - -set_disable_timing fpga_core_uut/sb_*__*_/chanx_left_out - -set_disable_timing fpga_core_uut/sb_*__*_/ccff_tail - diff --git a/FPGA1212_SOFA_CHD_PNR/FPGA1212_SOFA_CHD_Verilog/SDC/global_ports.sdc b/FPGA1212_SOFA_CHD_PNR/FPGA1212_SOFA_CHD_Verilog/SDC/global_ports.sdc deleted file mode 100644 index 87d09a9..0000000 --- a/FPGA1212_SOFA_CHD_PNR/FPGA1212_SOFA_CHD_Verilog/SDC/global_ports.sdc +++ /dev/null @@ -1,17 +0,0 @@ -############################################# -# Synopsys Design Constraints (SDC) -# For FPGA fabric -# Description: Clock contraints for PnR -# Author: Xifan TANG -# Organization: University of Utah -# Date: Tue Dec 8 15:34:14 2020 -############################################# - -################################################## -# Create programmable clock -################################################## -create_clock -name prog_clk[0] -period 9.999999939e-09 -waveform {0 4.99999997e-09} [get_ports {prog_clk[0]}] -################################################## -# Create clock -################################################## -create_clock -name clk[0] -period 8.319719358e-10 -waveform {0 4.159859679e-10} [get_ports {clk[0]}] diff --git a/FPGA1212_SOFA_CHD_PNR/FPGA1212_SOFA_CHD_Verilog/SDC/logical_tile_clb_mode_clb_.sdc b/FPGA1212_SOFA_CHD_PNR/FPGA1212_SOFA_CHD_Verilog/SDC/logical_tile_clb_mode_clb_.sdc deleted file mode 100644 index bb037ef..0000000 --- a/FPGA1212_SOFA_CHD_PNR/FPGA1212_SOFA_CHD_Verilog/SDC/logical_tile_clb_mode_clb_.sdc +++ /dev/null @@ -1,17 +0,0 @@ -############################################# -# Synopsys Design Constraints (SDC) -# For FPGA fabric -# Description: Timing constraints for Grid logical_tile_clb_mode_clb_ in PnR -# Author: Xifan TANG -# Organization: University of Utah -# Date: Tue Dec 8 15:34:14 2020 -############################################# - -############################################# -# Define time unit -############################################# -set_units -time s - -set_max_delay -from fpga_core_uut/grid_clb/logical_tile_clb_mode_clb__0_/clb_reg_in[0] -to fpga_top/grid_clb/logical_tile_clb_mode_default__fle_0/fle_reg_in[0] 1.599999994e-10 -set_max_delay -from fpga_core_uut/grid_clb/logical_tile_clb_mode_clb__0_/clb_sc_in[0] -to fpga_top/grid_clb/logical_tile_clb_mode_default__fle_0/fle_sc_in[0] 1.599999994e-10 -set_max_delay -from fpga_core_uut/grid_clb/logical_tile_clb_mode_clb__0_/clb_cin[0] -to fpga_top/grid_clb/logical_tile_clb_mode_default__fle_0/fle_cin[0] 1.599999994e-10 diff --git a/FPGA1212_SOFA_CHD_PNR/FPGA1212_SOFA_CHD_Verilog/SDC/logical_tile_clb_mode_default__fle.sdc b/FPGA1212_SOFA_CHD_PNR/FPGA1212_SOFA_CHD_Verilog/SDC/logical_tile_clb_mode_default__fle.sdc deleted file mode 100644 index 28614db..0000000 --- a/FPGA1212_SOFA_CHD_PNR/FPGA1212_SOFA_CHD_Verilog/SDC/logical_tile_clb_mode_default__fle.sdc +++ /dev/null @@ -1,14 +0,0 @@ -############################################# -# Synopsys Design Constraints (SDC) -# For FPGA fabric -# Description: Timing constraints for Grid logical_tile_clb_mode_default__fle in PnR -# Author: Xifan TANG -# Organization: University of Utah -# Date: Tue Dec 8 15:34:14 2020 -############################################# - -############################################# -# Define time unit -############################################# -set_units -time s - diff --git a/FPGA1212_SOFA_CHD_PNR/FPGA1212_SOFA_CHD_Verilog/SDC/logical_tile_clb_mode_default__fle_mode_physical__fabric.sdc b/FPGA1212_SOFA_CHD_PNR/FPGA1212_SOFA_CHD_Verilog/SDC/logical_tile_clb_mode_default__fle_mode_physical__fabric.sdc deleted file mode 100644 index 501dc7b..0000000 --- a/FPGA1212_SOFA_CHD_PNR/FPGA1212_SOFA_CHD_Verilog/SDC/logical_tile_clb_mode_default__fle_mode_physical__fabric.sdc +++ /dev/null @@ -1,22 +0,0 @@ -############################################# -# Synopsys Design Constraints (SDC) -# For FPGA fabric -# Description: Timing constraints for Grid logical_tile_clb_mode_default__fle_mode_physical__fabric in PnR -# Author: Xifan TANG -# Organization: University of Utah -# Date: Tue Dec 8 15:34:14 2020 -############################################# - -############################################# -# Define time unit -############################################# -set_units -time s - -set_max_delay -from fpga_core_uut/grid_clb/fle/fabric/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0/ff_Q[0] -to fpga_top/grid_clb/fle/fabric/logical_tile_clb_mode_default__fle_mode_physical__fabric_0_/fabric_out[0] 4.500000025e-11 -set_max_delay -from fpga_core_uut/grid_clb/fle/fabric/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/frac_logic_out[0] -to fpga_top/grid_clb/fle/fabric/logical_tile_clb_mode_default__fle_mode_physical__fabric_0_/fabric_out[0] 2.500000033e-11 -set_max_delay -from fpga_core_uut/grid_clb/fle/fabric/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1/ff_Q[0] -to fpga_top/grid_clb/fle/fabric/logical_tile_clb_mode_default__fle_mode_physical__fabric_0_/fabric_out[1] 4.500000025e-11 -set_max_delay -from fpga_core_uut/grid_clb/fle/fabric/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/frac_logic_out[1] -to fpga_top/grid_clb/fle/fabric/logical_tile_clb_mode_default__fle_mode_physical__fabric_0_/fabric_out[1] 2.500000033e-11 -set_max_delay -from fpga_core_uut/grid_clb/fle/fabric/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/frac_logic_out[0] -to fpga_top/grid_clb/fle/fabric/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0/ff_D[0] 2.500000033e-11 -set_max_delay -from fpga_core_uut/grid_clb/fle/fabric/logical_tile_clb_mode_default__fle_mode_physical__fabric_0_/fabric_reg_in[0] -to fpga_top/grid_clb/fle/fabric/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0/ff_D[0] 4.500000025e-11 -set_max_delay -from fpga_core_uut/grid_clb/fle/fabric/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/frac_logic_out[1] -to fpga_top/grid_clb/fle/fabric/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1/ff_D[0] 2.500000033e-11 -set_max_delay -from fpga_core_uut/grid_clb/fle/fabric/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0/ff_Q[0] -to fpga_top/grid_clb/fle/fabric/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1/ff_D[0] 4.500000025e-11 diff --git a/FPGA1212_SOFA_CHD_PNR/FPGA1212_SOFA_CHD_Verilog/SDC/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff.sdc b/FPGA1212_SOFA_CHD_PNR/FPGA1212_SOFA_CHD_Verilog/SDC/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff.sdc deleted file mode 100644 index 721977b..0000000 --- a/FPGA1212_SOFA_CHD_PNR/FPGA1212_SOFA_CHD_Verilog/SDC/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff.sdc +++ /dev/null @@ -1,14 +0,0 @@ -############################################# -# Synopsys Design Constraints (SDC) -# For FPGA fabric -# Description: Timing constraints for Grid logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff in PnR -# Author: Xifan TANG -# Organization: University of Utah -# Date: Tue Dec 8 15:34:14 2020 -############################################# - -############################################# -# Define time unit -############################################# -set_units -time s - diff --git a/FPGA1212_SOFA_CHD_PNR/FPGA1212_SOFA_CHD_Verilog/SDC/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic.sdc b/FPGA1212_SOFA_CHD_PNR/FPGA1212_SOFA_CHD_Verilog/SDC/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic.sdc deleted file mode 100644 index 5009dfc..0000000 --- a/FPGA1212_SOFA_CHD_PNR/FPGA1212_SOFA_CHD_Verilog/SDC/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic.sdc +++ /dev/null @@ -1,14 +0,0 @@ -############################################# -# Synopsys Design Constraints (SDC) -# For FPGA fabric -# Description: Timing constraints for Grid logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic in PnR -# Author: Xifan TANG -# Organization: University of Utah -# Date: Tue Dec 8 15:34:14 2020 -############################################# - -############################################# -# Define time unit -############################################# -set_units -time s - diff --git a/FPGA1212_SOFA_CHD_PNR/FPGA1212_SOFA_CHD_Verilog/SDC/logical_tile_io_mode_io_.sdc b/FPGA1212_SOFA_CHD_PNR/FPGA1212_SOFA_CHD_Verilog/SDC/logical_tile_io_mode_io_.sdc deleted file mode 100644 index 354627c..0000000 --- a/FPGA1212_SOFA_CHD_PNR/FPGA1212_SOFA_CHD_Verilog/SDC/logical_tile_io_mode_io_.sdc +++ /dev/null @@ -1,16 +0,0 @@ -############################################# -# Synopsys Design Constraints (SDC) -# For FPGA fabric -# Description: Timing constraints for Grid logical_tile_io_mode_io_ in PnR -# Author: Xifan TANG -# Organization: University of Utah -# Date: Tue Dec 8 15:34:14 2020 -############################################# - -############################################# -# Define time unit -############################################# -set_units -time s - -set_max_delay -from fpga_core_uut/grid_io_left_left/logical_tile_io_mode_physical__iopad_0/iopad_inpad[0] -to fpga_top/grid_io_left_left/logical_tile_io_mode_io__0_/io_inpad[0] 4.243000049e-11 -set_max_delay -from fpga_core_uut/grid_io_left_left/logical_tile_io_mode_io__0_/io_outpad[0] -to fpga_top/grid_io_left_left/logical_tile_io_mode_physical__iopad_0/iopad_outpad[0] 1.39400002e-11 diff --git a/FPGA1212_SOFA_CHD_PNR/FPGA1212_SOFA_CHD_Verilog/SDC/sb_0__0_.sdc b/FPGA1212_SOFA_CHD_PNR/FPGA1212_SOFA_CHD_Verilog/SDC/sb_0__0_.sdc deleted file mode 100644 index 9d604eb..0000000 --- a/FPGA1212_SOFA_CHD_PNR/FPGA1212_SOFA_CHD_Verilog/SDC/sb_0__0_.sdc +++ /dev/null @@ -1,124 +0,0 @@ -############################################# -# Synopsys Design Constraints (SDC) -# For FPGA fabric -# Description: Constrain timing of Switch Block sb_0__0_ for PnR -# Author: Xifan TANG -# Organization: University of Utah -# Date: Tue Dec 8 15:34:14 2020 -############################################# - -############################################# -# Define time unit -############################################# -set_units -time s - -set_max_delay -from fpga_core_uut/sb_0__0_/top_left_grid_pin_1_[0] -to fpga_top/sb_0__0_/chany_top_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__0_/chanx_right_in[1] -to fpga_top/sb_0__0_/chany_top_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__0_/chanx_right_in[2] -to fpga_top/sb_0__0_/chany_top_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__0_/chanx_right_in[3] -to fpga_top/sb_0__0_/chany_top_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__0_/top_left_grid_pin_1_[0] -to fpga_top/sb_0__0_/chany_top_out[3] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__0_/chanx_right_in[4] -to fpga_top/sb_0__0_/chany_top_out[3] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__0_/chanx_right_in[5] -to fpga_top/sb_0__0_/chany_top_out[4] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__0_/chanx_right_in[6] -to fpga_top/sb_0__0_/chany_top_out[5] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__0_/top_left_grid_pin_1_[0] -to fpga_top/sb_0__0_/chany_top_out[6] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__0_/chanx_right_in[7] -to fpga_top/sb_0__0_/chany_top_out[6] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__0_/chanx_right_in[8] -to fpga_top/sb_0__0_/chany_top_out[7] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__0_/chanx_right_in[9] -to fpga_top/sb_0__0_/chany_top_out[8] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__0_/chanx_right_in[10] -to fpga_top/sb_0__0_/chany_top_out[9] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__0_/chanx_right_in[11] -to fpga_top/sb_0__0_/chany_top_out[10] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__0_/chanx_right_in[12] -to fpga_top/sb_0__0_/chany_top_out[11] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__0_/chanx_right_in[13] -to fpga_top/sb_0__0_/chany_top_out[12] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__0_/chanx_right_in[14] -to fpga_top/sb_0__0_/chany_top_out[13] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__0_/top_left_grid_pin_1_[0] -to fpga_top/sb_0__0_/chany_top_out[14] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__0_/chanx_right_in[15] -to fpga_top/sb_0__0_/chany_top_out[14] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__0_/chanx_right_in[16] -to fpga_top/sb_0__0_/chany_top_out[15] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__0_/chanx_right_in[17] -to fpga_top/sb_0__0_/chany_top_out[16] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__0_/chanx_right_in[18] -to fpga_top/sb_0__0_/chany_top_out[17] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__0_/chanx_right_in[19] -to fpga_top/sb_0__0_/chany_top_out[18] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__0_/chanx_right_in[20] -to fpga_top/sb_0__0_/chany_top_out[19] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__0_/chanx_right_in[21] -to fpga_top/sb_0__0_/chany_top_out[20] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__0_/chanx_right_in[22] -to fpga_top/sb_0__0_/chany_top_out[21] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__0_/top_left_grid_pin_1_[0] -to fpga_top/sb_0__0_/chany_top_out[22] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__0_/chanx_right_in[23] -to fpga_top/sb_0__0_/chany_top_out[22] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__0_/chanx_right_in[24] -to fpga_top/sb_0__0_/chany_top_out[23] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__0_/chanx_right_in[25] -to fpga_top/sb_0__0_/chany_top_out[24] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__0_/chanx_right_in[26] -to fpga_top/sb_0__0_/chany_top_out[25] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__0_/chanx_right_in[27] -to fpga_top/sb_0__0_/chany_top_out[26] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__0_/chanx_right_in[28] -to fpga_top/sb_0__0_/chany_top_out[27] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__0_/chanx_right_in[29] -to fpga_top/sb_0__0_/chany_top_out[28] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__0_/chanx_right_in[0] -to fpga_top/sb_0__0_/chany_top_out[29] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__0_/chany_top_in[29] -to fpga_top/sb_0__0_/chanx_right_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_1_[0] -to fpga_top/sb_0__0_/chanx_right_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_7_[0] -to fpga_top/sb_0__0_/chanx_right_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_13_[0] -to fpga_top/sb_0__0_/chanx_right_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__0_/chany_top_in[0] -to fpga_top/sb_0__0_/chanx_right_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_3_[0] -to fpga_top/sb_0__0_/chanx_right_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_9_[0] -to fpga_top/sb_0__0_/chanx_right_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_15_[0] -to fpga_top/sb_0__0_/chanx_right_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__0_/chany_top_in[1] -to fpga_top/sb_0__0_/chanx_right_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_5_[0] -to fpga_top/sb_0__0_/chanx_right_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_11_[0] -to fpga_top/sb_0__0_/chanx_right_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_17_[0] -to fpga_top/sb_0__0_/chanx_right_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__0_/chany_top_in[2] -to fpga_top/sb_0__0_/chanx_right_out[3] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_1_[0] -to fpga_top/sb_0__0_/chanx_right_out[3] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_7_[0] -to fpga_top/sb_0__0_/chanx_right_out[3] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_13_[0] -to fpga_top/sb_0__0_/chanx_right_out[3] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__0_/chany_top_in[3] -to fpga_top/sb_0__0_/chanx_right_out[4] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_3_[0] -to fpga_top/sb_0__0_/chanx_right_out[4] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_9_[0] -to fpga_top/sb_0__0_/chanx_right_out[4] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_15_[0] -to fpga_top/sb_0__0_/chanx_right_out[4] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__0_/chany_top_in[4] -to fpga_top/sb_0__0_/chanx_right_out[5] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_5_[0] -to fpga_top/sb_0__0_/chanx_right_out[5] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_11_[0] -to fpga_top/sb_0__0_/chanx_right_out[5] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_17_[0] -to fpga_top/sb_0__0_/chanx_right_out[5] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__0_/chany_top_in[5] -to fpga_top/sb_0__0_/chanx_right_out[6] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_1_[0] -to fpga_top/sb_0__0_/chanx_right_out[6] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_17_[0] -to fpga_top/sb_0__0_/chanx_right_out[6] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__0_/chany_top_in[6] -to fpga_top/sb_0__0_/chanx_right_out[7] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_3_[0] -to fpga_top/sb_0__0_/chanx_right_out[7] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__0_/chany_top_in[7] -to fpga_top/sb_0__0_/chanx_right_out[8] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_5_[0] -to fpga_top/sb_0__0_/chanx_right_out[8] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__0_/chany_top_in[8] -to fpga_top/sb_0__0_/chanx_right_out[9] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_7_[0] -to fpga_top/sb_0__0_/chanx_right_out[9] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__0_/chany_top_in[9] -to fpga_top/sb_0__0_/chanx_right_out[10] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_9_[0] -to fpga_top/sb_0__0_/chanx_right_out[10] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__0_/chany_top_in[10] -to fpga_top/sb_0__0_/chanx_right_out[11] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_11_[0] -to fpga_top/sb_0__0_/chanx_right_out[11] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__0_/chany_top_in[11] -to fpga_top/sb_0__0_/chanx_right_out[12] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_13_[0] -to fpga_top/sb_0__0_/chanx_right_out[12] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__0_/chany_top_in[12] -to fpga_top/sb_0__0_/chanx_right_out[13] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_15_[0] -to fpga_top/sb_0__0_/chanx_right_out[13] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__0_/chany_top_in[13] -to fpga_top/sb_0__0_/chanx_right_out[14] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_1_[0] -to fpga_top/sb_0__0_/chanx_right_out[14] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_17_[0] -to fpga_top/sb_0__0_/chanx_right_out[14] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__0_/chany_top_in[14] -to fpga_top/sb_0__0_/chanx_right_out[15] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_3_[0] -to fpga_top/sb_0__0_/chanx_right_out[15] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__0_/chany_top_in[15] -to fpga_top/sb_0__0_/chanx_right_out[16] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_5_[0] -to fpga_top/sb_0__0_/chanx_right_out[16] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__0_/chany_top_in[16] -to fpga_top/sb_0__0_/chanx_right_out[17] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_7_[0] -to fpga_top/sb_0__0_/chanx_right_out[17] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__0_/chany_top_in[17] -to fpga_top/sb_0__0_/chanx_right_out[18] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_9_[0] -to fpga_top/sb_0__0_/chanx_right_out[18] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__0_/chany_top_in[18] -to fpga_top/sb_0__0_/chanx_right_out[19] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_11_[0] -to fpga_top/sb_0__0_/chanx_right_out[19] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__0_/chany_top_in[19] -to fpga_top/sb_0__0_/chanx_right_out[20] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_13_[0] -to fpga_top/sb_0__0_/chanx_right_out[20] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__0_/chany_top_in[20] -to fpga_top/sb_0__0_/chanx_right_out[21] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_15_[0] -to fpga_top/sb_0__0_/chanx_right_out[21] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__0_/chany_top_in[21] -to fpga_top/sb_0__0_/chanx_right_out[22] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_1_[0] -to fpga_top/sb_0__0_/chanx_right_out[22] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_17_[0] -to fpga_top/sb_0__0_/chanx_right_out[22] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__0_/chany_top_in[22] -to fpga_top/sb_0__0_/chanx_right_out[23] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_3_[0] -to fpga_top/sb_0__0_/chanx_right_out[23] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__0_/chany_top_in[23] -to fpga_top/sb_0__0_/chanx_right_out[24] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_5_[0] -to fpga_top/sb_0__0_/chanx_right_out[24] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__0_/chany_top_in[24] -to fpga_top/sb_0__0_/chanx_right_out[25] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_7_[0] -to fpga_top/sb_0__0_/chanx_right_out[25] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__0_/chany_top_in[25] -to fpga_top/sb_0__0_/chanx_right_out[26] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_9_[0] -to fpga_top/sb_0__0_/chanx_right_out[26] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__0_/chany_top_in[26] -to fpga_top/sb_0__0_/chanx_right_out[27] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_11_[0] -to fpga_top/sb_0__0_/chanx_right_out[27] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__0_/chany_top_in[27] -to fpga_top/sb_0__0_/chanx_right_out[28] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_13_[0] -to fpga_top/sb_0__0_/chanx_right_out[28] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__0_/chany_top_in[28] -to fpga_top/sb_0__0_/chanx_right_out[29] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_15_[0] -to fpga_top/sb_0__0_/chanx_right_out[29] 6.020400151e-11 diff --git a/FPGA1212_SOFA_CHD_PNR/FPGA1212_SOFA_CHD_Verilog/SDC/sb_0__12_.sdc b/FPGA1212_SOFA_CHD_PNR/FPGA1212_SOFA_CHD_Verilog/SDC/sb_0__12_.sdc deleted file mode 100644 index 0905bc3..0000000 --- a/FPGA1212_SOFA_CHD_PNR/FPGA1212_SOFA_CHD_Verilog/SDC/sb_0__12_.sdc +++ /dev/null @@ -1,123 +0,0 @@ -############################################# -# Synopsys Design Constraints (SDC) -# For FPGA fabric -# Description: Constrain timing of Switch Block sb_0__12_ for PnR -# Author: Xifan TANG -# Organization: University of Utah -# Date: Tue Dec 8 15:34:14 2020 -############################################# - -############################################# -# Define time unit -############################################# -set_units -time s - -set_max_delay -from fpga_core_uut/sb_0__12_/right_top_grid_pin_1_[0] -to fpga_top/sb_0__12_/chanx_right_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__12_/right_bottom_grid_pin_38_[0] -to fpga_top/sb_0__12_/chanx_right_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__12_/right_bottom_grid_pin_41_[0] -to fpga_top/sb_0__12_/chanx_right_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__12_/chany_bottom_in[28] -to fpga_top/sb_0__12_/chanx_right_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__12_/right_bottom_grid_pin_36_[0] -to fpga_top/sb_0__12_/chanx_right_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__12_/right_bottom_grid_pin_39_[0] -to fpga_top/sb_0__12_/chanx_right_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__12_/right_bottom_grid_pin_42_[0] -to fpga_top/sb_0__12_/chanx_right_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__12_/chany_bottom_in[27] -to fpga_top/sb_0__12_/chanx_right_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__12_/right_bottom_grid_pin_37_[0] -to fpga_top/sb_0__12_/chanx_right_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__12_/right_bottom_grid_pin_40_[0] -to fpga_top/sb_0__12_/chanx_right_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__12_/right_bottom_grid_pin_43_[0] -to fpga_top/sb_0__12_/chanx_right_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__12_/chany_bottom_in[26] -to fpga_top/sb_0__12_/chanx_right_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__12_/right_top_grid_pin_1_[0] -to fpga_top/sb_0__12_/chanx_right_out[3] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__12_/right_bottom_grid_pin_38_[0] -to fpga_top/sb_0__12_/chanx_right_out[3] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__12_/right_bottom_grid_pin_41_[0] -to fpga_top/sb_0__12_/chanx_right_out[3] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__12_/chany_bottom_in[25] -to fpga_top/sb_0__12_/chanx_right_out[3] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__12_/right_bottom_grid_pin_36_[0] -to fpga_top/sb_0__12_/chanx_right_out[4] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__12_/right_bottom_grid_pin_39_[0] -to fpga_top/sb_0__12_/chanx_right_out[4] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__12_/right_bottom_grid_pin_42_[0] -to fpga_top/sb_0__12_/chanx_right_out[4] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__12_/chany_bottom_in[24] -to fpga_top/sb_0__12_/chanx_right_out[4] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__12_/right_bottom_grid_pin_37_[0] -to fpga_top/sb_0__12_/chanx_right_out[5] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__12_/right_bottom_grid_pin_40_[0] -to fpga_top/sb_0__12_/chanx_right_out[5] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__12_/right_bottom_grid_pin_43_[0] -to fpga_top/sb_0__12_/chanx_right_out[5] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__12_/chany_bottom_in[23] -to fpga_top/sb_0__12_/chanx_right_out[5] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__12_/right_top_grid_pin_1_[0] -to fpga_top/sb_0__12_/chanx_right_out[6] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__12_/chany_bottom_in[22] -to fpga_top/sb_0__12_/chanx_right_out[6] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__12_/right_bottom_grid_pin_36_[0] -to fpga_top/sb_0__12_/chanx_right_out[7] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__12_/chany_bottom_in[21] -to fpga_top/sb_0__12_/chanx_right_out[7] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__12_/right_bottom_grid_pin_37_[0] -to fpga_top/sb_0__12_/chanx_right_out[8] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__12_/chany_bottom_in[20] -to fpga_top/sb_0__12_/chanx_right_out[8] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__12_/right_bottom_grid_pin_38_[0] -to fpga_top/sb_0__12_/chanx_right_out[9] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__12_/chany_bottom_in[19] -to fpga_top/sb_0__12_/chanx_right_out[9] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__12_/right_bottom_grid_pin_39_[0] -to fpga_top/sb_0__12_/chanx_right_out[10] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__12_/chany_bottom_in[18] -to fpga_top/sb_0__12_/chanx_right_out[10] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__12_/right_bottom_grid_pin_40_[0] -to fpga_top/sb_0__12_/chanx_right_out[11] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__12_/chany_bottom_in[17] -to fpga_top/sb_0__12_/chanx_right_out[11] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__12_/right_bottom_grid_pin_41_[0] -to fpga_top/sb_0__12_/chanx_right_out[12] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__12_/chany_bottom_in[16] -to fpga_top/sb_0__12_/chanx_right_out[12] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__12_/right_bottom_grid_pin_42_[0] -to fpga_top/sb_0__12_/chanx_right_out[13] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__12_/chany_bottom_in[15] -to fpga_top/sb_0__12_/chanx_right_out[13] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__12_/right_top_grid_pin_1_[0] -to fpga_top/sb_0__12_/chanx_right_out[14] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__12_/right_bottom_grid_pin_43_[0] -to fpga_top/sb_0__12_/chanx_right_out[14] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__12_/chany_bottom_in[14] -to fpga_top/sb_0__12_/chanx_right_out[14] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__12_/right_bottom_grid_pin_36_[0] -to fpga_top/sb_0__12_/chanx_right_out[15] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__12_/chany_bottom_in[13] -to fpga_top/sb_0__12_/chanx_right_out[15] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__12_/right_bottom_grid_pin_37_[0] -to fpga_top/sb_0__12_/chanx_right_out[16] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__12_/chany_bottom_in[12] -to fpga_top/sb_0__12_/chanx_right_out[16] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__12_/right_bottom_grid_pin_38_[0] -to fpga_top/sb_0__12_/chanx_right_out[17] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__12_/chany_bottom_in[11] -to fpga_top/sb_0__12_/chanx_right_out[17] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__12_/right_bottom_grid_pin_39_[0] -to fpga_top/sb_0__12_/chanx_right_out[18] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__12_/chany_bottom_in[10] -to fpga_top/sb_0__12_/chanx_right_out[18] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__12_/right_bottom_grid_pin_40_[0] -to fpga_top/sb_0__12_/chanx_right_out[19] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__12_/chany_bottom_in[9] -to fpga_top/sb_0__12_/chanx_right_out[19] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__12_/right_bottom_grid_pin_41_[0] -to fpga_top/sb_0__12_/chanx_right_out[20] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__12_/chany_bottom_in[8] -to fpga_top/sb_0__12_/chanx_right_out[20] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__12_/right_bottom_grid_pin_42_[0] -to fpga_top/sb_0__12_/chanx_right_out[21] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__12_/chany_bottom_in[7] -to fpga_top/sb_0__12_/chanx_right_out[21] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__12_/right_top_grid_pin_1_[0] -to fpga_top/sb_0__12_/chanx_right_out[22] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__12_/chany_bottom_in[6] -to fpga_top/sb_0__12_/chanx_right_out[22] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__12_/right_bottom_grid_pin_36_[0] -to fpga_top/sb_0__12_/chanx_right_out[23] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__12_/chany_bottom_in[5] -to fpga_top/sb_0__12_/chanx_right_out[23] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__12_/right_bottom_grid_pin_37_[0] -to fpga_top/sb_0__12_/chanx_right_out[24] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__12_/chany_bottom_in[4] -to fpga_top/sb_0__12_/chanx_right_out[24] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__12_/right_bottom_grid_pin_38_[0] -to fpga_top/sb_0__12_/chanx_right_out[25] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__12_/chany_bottom_in[3] -to fpga_top/sb_0__12_/chanx_right_out[25] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__12_/right_bottom_grid_pin_39_[0] -to fpga_top/sb_0__12_/chanx_right_out[26] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__12_/right_bottom_grid_pin_43_[0] -to fpga_top/sb_0__12_/chanx_right_out[26] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__12_/chany_bottom_in[2] -to fpga_top/sb_0__12_/chanx_right_out[26] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__12_/right_bottom_grid_pin_40_[0] -to fpga_top/sb_0__12_/chanx_right_out[27] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__12_/chany_bottom_in[1] -to fpga_top/sb_0__12_/chanx_right_out[27] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__12_/right_bottom_grid_pin_41_[0] -to fpga_top/sb_0__12_/chanx_right_out[28] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__12_/chany_bottom_in[0] -to fpga_top/sb_0__12_/chanx_right_out[28] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__12_/right_bottom_grid_pin_42_[0] -to fpga_top/sb_0__12_/chanx_right_out[29] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__12_/chany_bottom_in[29] -to fpga_top/sb_0__12_/chanx_right_out[29] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__12_/chanx_right_in[28] -to fpga_top/sb_0__12_/chany_bottom_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__12_/bottom_left_grid_pin_1_[0] -to fpga_top/sb_0__12_/chany_bottom_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__12_/chanx_right_in[27] -to fpga_top/sb_0__12_/chany_bottom_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__12_/chanx_right_in[26] -to fpga_top/sb_0__12_/chany_bottom_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__12_/chanx_right_in[25] -to fpga_top/sb_0__12_/chany_bottom_out[3] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__12_/bottom_left_grid_pin_1_[0] -to fpga_top/sb_0__12_/chany_bottom_out[3] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__12_/chanx_right_in[24] -to fpga_top/sb_0__12_/chany_bottom_out[4] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__12_/chanx_right_in[23] -to fpga_top/sb_0__12_/chany_bottom_out[5] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__12_/chanx_right_in[22] -to fpga_top/sb_0__12_/chany_bottom_out[6] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__12_/bottom_left_grid_pin_1_[0] -to fpga_top/sb_0__12_/chany_bottom_out[6] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__12_/chanx_right_in[21] -to fpga_top/sb_0__12_/chany_bottom_out[7] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__12_/chanx_right_in[20] -to fpga_top/sb_0__12_/chany_bottom_out[8] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__12_/chanx_right_in[19] -to fpga_top/sb_0__12_/chany_bottom_out[9] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__12_/chanx_right_in[18] -to fpga_top/sb_0__12_/chany_bottom_out[10] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__12_/chanx_right_in[17] -to fpga_top/sb_0__12_/chany_bottom_out[11] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__12_/chanx_right_in[16] -to fpga_top/sb_0__12_/chany_bottom_out[12] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__12_/chanx_right_in[15] -to fpga_top/sb_0__12_/chany_bottom_out[13] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__12_/chanx_right_in[14] -to fpga_top/sb_0__12_/chany_bottom_out[14] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__12_/bottom_left_grid_pin_1_[0] -to fpga_top/sb_0__12_/chany_bottom_out[14] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__12_/chanx_right_in[13] -to fpga_top/sb_0__12_/chany_bottom_out[15] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__12_/chanx_right_in[12] -to fpga_top/sb_0__12_/chany_bottom_out[16] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__12_/chanx_right_in[11] -to fpga_top/sb_0__12_/chany_bottom_out[17] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__12_/chanx_right_in[10] -to fpga_top/sb_0__12_/chany_bottom_out[18] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__12_/chanx_right_in[9] -to fpga_top/sb_0__12_/chany_bottom_out[19] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__12_/chanx_right_in[8] -to fpga_top/sb_0__12_/chany_bottom_out[20] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__12_/chanx_right_in[7] -to fpga_top/sb_0__12_/chany_bottom_out[21] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__12_/chanx_right_in[6] -to fpga_top/sb_0__12_/chany_bottom_out[22] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__12_/bottom_left_grid_pin_1_[0] -to fpga_top/sb_0__12_/chany_bottom_out[22] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__12_/chanx_right_in[5] -to fpga_top/sb_0__12_/chany_bottom_out[23] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__12_/chanx_right_in[4] -to fpga_top/sb_0__12_/chany_bottom_out[24] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__12_/chanx_right_in[3] -to fpga_top/sb_0__12_/chany_bottom_out[25] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__12_/chanx_right_in[2] -to fpga_top/sb_0__12_/chany_bottom_out[26] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__12_/chanx_right_in[1] -to fpga_top/sb_0__12_/chany_bottom_out[27] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__12_/chanx_right_in[0] -to fpga_top/sb_0__12_/chany_bottom_out[28] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__12_/chanx_right_in[29] -to fpga_top/sb_0__12_/chany_bottom_out[29] 6.020400151e-11 diff --git a/FPGA1212_SOFA_CHD_PNR/FPGA1212_SOFA_CHD_Verilog/SDC/sb_0__1_.sdc b/FPGA1212_SOFA_CHD_PNR/FPGA1212_SOFA_CHD_Verilog/SDC/sb_0__1_.sdc deleted file mode 100644 index cfa325f..0000000 --- a/FPGA1212_SOFA_CHD_PNR/FPGA1212_SOFA_CHD_Verilog/SDC/sb_0__1_.sdc +++ /dev/null @@ -1,217 +0,0 @@ -############################################# -# Synopsys Design Constraints (SDC) -# For FPGA fabric -# Description: Constrain timing of Switch Block sb_0__1_ for PnR -# Author: Xifan TANG -# Organization: University of Utah -# Date: Tue Dec 8 15:34:14 2020 -############################################# - -############################################# -# Define time unit -############################################# -set_units -time s - -set_max_delay -from fpga_core_uut/sb_0__1_/top_left_grid_pin_1_[0] -to fpga_top/sb_0__1_/chany_top_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[1] -to fpga_top/sb_0__1_/chany_top_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[12] -to fpga_top/sb_0__1_/chany_top_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[23] -to fpga_top/sb_0__1_/chany_top_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[3] -to fpga_top/sb_0__1_/chany_top_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[19] -to fpga_top/sb_0__1_/chany_top_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[2] -to fpga_top/sb_0__1_/chany_top_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[13] -to fpga_top/sb_0__1_/chany_top_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[24] -to fpga_top/sb_0__1_/chany_top_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[6] -to fpga_top/sb_0__1_/chany_top_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[20] -to fpga_top/sb_0__1_/chany_top_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[3] -to fpga_top/sb_0__1_/chany_top_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[14] -to fpga_top/sb_0__1_/chany_top_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[25] -to fpga_top/sb_0__1_/chany_top_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[7] -to fpga_top/sb_0__1_/chany_top_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[22] -to fpga_top/sb_0__1_/chany_top_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/top_left_grid_pin_1_[0] -to fpga_top/sb_0__1_/chany_top_out[3] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[4] -to fpga_top/sb_0__1_/chany_top_out[3] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[15] -to fpga_top/sb_0__1_/chany_top_out[3] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[26] -to fpga_top/sb_0__1_/chany_top_out[3] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[8] -to fpga_top/sb_0__1_/chany_top_out[3] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[23] -to fpga_top/sb_0__1_/chany_top_out[3] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[5] -to fpga_top/sb_0__1_/chany_top_out[5] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[16] -to fpga_top/sb_0__1_/chany_top_out[5] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[27] -to fpga_top/sb_0__1_/chany_top_out[5] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[10] -to fpga_top/sb_0__1_/chany_top_out[5] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[24] -to fpga_top/sb_0__1_/chany_top_out[5] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/top_left_grid_pin_1_[0] -to fpga_top/sb_0__1_/chany_top_out[6] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[6] -to fpga_top/sb_0__1_/chany_top_out[6] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[17] -to fpga_top/sb_0__1_/chany_top_out[6] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[28] -to fpga_top/sb_0__1_/chany_top_out[6] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[11] -to fpga_top/sb_0__1_/chany_top_out[6] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[26] -to fpga_top/sb_0__1_/chany_top_out[6] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[7] -to fpga_top/sb_0__1_/chany_top_out[10] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[18] -to fpga_top/sb_0__1_/chany_top_out[10] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[29] -to fpga_top/sb_0__1_/chany_top_out[10] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[12] -to fpga_top/sb_0__1_/chany_top_out[10] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[27] -to fpga_top/sb_0__1_/chany_top_out[10] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[8] -to fpga_top/sb_0__1_/chany_top_out[14] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[19] -to fpga_top/sb_0__1_/chany_top_out[14] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[14] -to fpga_top/sb_0__1_/chany_top_out[14] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[28] -to fpga_top/sb_0__1_/chany_top_out[14] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[9] -to fpga_top/sb_0__1_/chany_top_out[18] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[20] -to fpga_top/sb_0__1_/chany_top_out[18] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[15] -to fpga_top/sb_0__1_/chany_top_out[18] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[10] -to fpga_top/sb_0__1_/chany_top_out[22] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[21] -to fpga_top/sb_0__1_/chany_top_out[22] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[16] -to fpga_top/sb_0__1_/chany_top_out[22] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[0] -to fpga_top/sb_0__1_/chany_top_out[26] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[11] -to fpga_top/sb_0__1_/chany_top_out[26] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[22] -to fpga_top/sb_0__1_/chany_top_out[26] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[18] -to fpga_top/sb_0__1_/chany_top_out[26] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[3] -to fpga_top/sb_0__1_/chanx_right_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/right_bottom_grid_pin_36_[0] -to fpga_top/sb_0__1_/chanx_right_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/right_bottom_grid_pin_39_[0] -to fpga_top/sb_0__1_/chanx_right_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/right_bottom_grid_pin_42_[0] -to fpga_top/sb_0__1_/chanx_right_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[3] -to fpga_top/sb_0__1_/chanx_right_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[0] -to fpga_top/sb_0__1_/chanx_right_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[6] -to fpga_top/sb_0__1_/chanx_right_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/right_bottom_grid_pin_37_[0] -to fpga_top/sb_0__1_/chanx_right_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/right_bottom_grid_pin_40_[0] -to fpga_top/sb_0__1_/chanx_right_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/right_bottom_grid_pin_43_[0] -to fpga_top/sb_0__1_/chanx_right_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[6] -to fpga_top/sb_0__1_/chanx_right_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[1] -to fpga_top/sb_0__1_/chanx_right_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[7] -to fpga_top/sb_0__1_/chanx_right_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/right_bottom_grid_pin_38_[0] -to fpga_top/sb_0__1_/chanx_right_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/right_bottom_grid_pin_41_[0] -to fpga_top/sb_0__1_/chanx_right_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[7] -to fpga_top/sb_0__1_/chanx_right_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[2] -to fpga_top/sb_0__1_/chanx_right_out[3] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[8] -to fpga_top/sb_0__1_/chanx_right_out[3] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/right_bottom_grid_pin_36_[0] -to fpga_top/sb_0__1_/chanx_right_out[3] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/right_bottom_grid_pin_39_[0] -to fpga_top/sb_0__1_/chanx_right_out[3] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/right_bottom_grid_pin_42_[0] -to fpga_top/sb_0__1_/chanx_right_out[3] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[8] -to fpga_top/sb_0__1_/chanx_right_out[3] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[4] -to fpga_top/sb_0__1_/chanx_right_out[4] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[10] -to fpga_top/sb_0__1_/chanx_right_out[4] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/right_bottom_grid_pin_37_[0] -to fpga_top/sb_0__1_/chanx_right_out[4] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/right_bottom_grid_pin_40_[0] -to fpga_top/sb_0__1_/chanx_right_out[4] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/right_bottom_grid_pin_43_[0] -to fpga_top/sb_0__1_/chanx_right_out[4] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[10] -to fpga_top/sb_0__1_/chanx_right_out[4] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[5] -to fpga_top/sb_0__1_/chanx_right_out[5] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[11] -to fpga_top/sb_0__1_/chanx_right_out[5] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/right_bottom_grid_pin_38_[0] -to fpga_top/sb_0__1_/chanx_right_out[5] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/right_bottom_grid_pin_41_[0] -to fpga_top/sb_0__1_/chanx_right_out[5] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[11] -to fpga_top/sb_0__1_/chanx_right_out[5] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[9] -to fpga_top/sb_0__1_/chanx_right_out[6] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[12] -to fpga_top/sb_0__1_/chanx_right_out[6] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/right_bottom_grid_pin_36_[0] -to fpga_top/sb_0__1_/chanx_right_out[6] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[12] -to fpga_top/sb_0__1_/chanx_right_out[6] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[13] -to fpga_top/sb_0__1_/chanx_right_out[7] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[14] -to fpga_top/sb_0__1_/chanx_right_out[7] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/right_bottom_grid_pin_37_[0] -to fpga_top/sb_0__1_/chanx_right_out[7] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[14] -to fpga_top/sb_0__1_/chanx_right_out[7] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[15] -to fpga_top/sb_0__1_/chanx_right_out[8] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[17] -to fpga_top/sb_0__1_/chanx_right_out[8] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/right_bottom_grid_pin_38_[0] -to fpga_top/sb_0__1_/chanx_right_out[8] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[15] -to fpga_top/sb_0__1_/chanx_right_out[8] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[16] -to fpga_top/sb_0__1_/chanx_right_out[9] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[21] -to fpga_top/sb_0__1_/chanx_right_out[9] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/right_bottom_grid_pin_39_[0] -to fpga_top/sb_0__1_/chanx_right_out[9] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[16] -to fpga_top/sb_0__1_/chanx_right_out[9] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[18] -to fpga_top/sb_0__1_/chanx_right_out[10] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[25] -to fpga_top/sb_0__1_/chanx_right_out[10] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/right_bottom_grid_pin_40_[0] -to fpga_top/sb_0__1_/chanx_right_out[10] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[18] -to fpga_top/sb_0__1_/chanx_right_out[10] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[19] -to fpga_top/sb_0__1_/chanx_right_out[11] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[29] -to fpga_top/sb_0__1_/chanx_right_out[11] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/right_bottom_grid_pin_41_[0] -to fpga_top/sb_0__1_/chanx_right_out[11] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[19] -to fpga_top/sb_0__1_/chanx_right_out[11] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[20] -to fpga_top/sb_0__1_/chanx_right_out[12] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/right_bottom_grid_pin_42_[0] -to fpga_top/sb_0__1_/chanx_right_out[12] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[20] -to fpga_top/sb_0__1_/chanx_right_out[12] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[22] -to fpga_top/sb_0__1_/chanx_right_out[13] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/right_bottom_grid_pin_43_[0] -to fpga_top/sb_0__1_/chanx_right_out[13] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[22] -to fpga_top/sb_0__1_/chanx_right_out[13] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[23] -to fpga_top/sb_0__1_/chanx_right_out[14] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/right_bottom_grid_pin_36_[0] -to fpga_top/sb_0__1_/chanx_right_out[14] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[23] -to fpga_top/sb_0__1_/chanx_right_out[14] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[24] -to fpga_top/sb_0__1_/chanx_right_out[15] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/right_bottom_grid_pin_37_[0] -to fpga_top/sb_0__1_/chanx_right_out[15] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[24] -to fpga_top/sb_0__1_/chanx_right_out[15] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[26] -to fpga_top/sb_0__1_/chanx_right_out[16] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/right_bottom_grid_pin_38_[0] -to fpga_top/sb_0__1_/chanx_right_out[16] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[26] -to fpga_top/sb_0__1_/chanx_right_out[16] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[27] -to fpga_top/sb_0__1_/chanx_right_out[17] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/right_bottom_grid_pin_39_[0] -to fpga_top/sb_0__1_/chanx_right_out[17] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[27] -to fpga_top/sb_0__1_/chanx_right_out[17] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[28] -to fpga_top/sb_0__1_/chanx_right_out[18] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/right_bottom_grid_pin_40_[0] -to fpga_top/sb_0__1_/chanx_right_out[18] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[28] -to fpga_top/sb_0__1_/chanx_right_out[18] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[29] -to fpga_top/sb_0__1_/chanx_right_out[18] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/right_bottom_grid_pin_41_[0] -to fpga_top/sb_0__1_/chanx_right_out[19] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[25] -to fpga_top/sb_0__1_/chanx_right_out[19] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/right_bottom_grid_pin_42_[0] -to fpga_top/sb_0__1_/chanx_right_out[20] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[21] -to fpga_top/sb_0__1_/chanx_right_out[20] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[17] -to fpga_top/sb_0__1_/chanx_right_out[21] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/right_bottom_grid_pin_36_[0] -to fpga_top/sb_0__1_/chanx_right_out[22] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[13] -to fpga_top/sb_0__1_/chanx_right_out[22] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/right_bottom_grid_pin_37_[0] -to fpga_top/sb_0__1_/chanx_right_out[23] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[9] -to fpga_top/sb_0__1_/chanx_right_out[23] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/right_bottom_grid_pin_38_[0] -to fpga_top/sb_0__1_/chanx_right_out[24] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[5] -to fpga_top/sb_0__1_/chanx_right_out[24] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/right_bottom_grid_pin_39_[0] -to fpga_top/sb_0__1_/chanx_right_out[25] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/right_bottom_grid_pin_43_[0] -to fpga_top/sb_0__1_/chanx_right_out[25] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[4] -to fpga_top/sb_0__1_/chanx_right_out[25] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/right_bottom_grid_pin_40_[0] -to fpga_top/sb_0__1_/chanx_right_out[26] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[2] -to fpga_top/sb_0__1_/chanx_right_out[26] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/right_bottom_grid_pin_41_[0] -to fpga_top/sb_0__1_/chanx_right_out[27] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[1] -to fpga_top/sb_0__1_/chanx_right_out[27] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/right_bottom_grid_pin_42_[0] -to fpga_top/sb_0__1_/chanx_right_out[28] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[0] -to fpga_top/sb_0__1_/chanx_right_out[28] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[3] -to fpga_top/sb_0__1_/chany_bottom_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[19] -to fpga_top/sb_0__1_/chany_bottom_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[9] -to fpga_top/sb_0__1_/chany_bottom_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[20] -to fpga_top/sb_0__1_/chany_bottom_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/bottom_left_grid_pin_1_[0] -to fpga_top/sb_0__1_/chany_bottom_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[6] -to fpga_top/sb_0__1_/chany_bottom_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[20] -to fpga_top/sb_0__1_/chany_bottom_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[8] -to fpga_top/sb_0__1_/chany_bottom_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[19] -to fpga_top/sb_0__1_/chany_bottom_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[7] -to fpga_top/sb_0__1_/chany_bottom_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[22] -to fpga_top/sb_0__1_/chany_bottom_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[7] -to fpga_top/sb_0__1_/chany_bottom_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[18] -to fpga_top/sb_0__1_/chany_bottom_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[29] -to fpga_top/sb_0__1_/chany_bottom_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[8] -to fpga_top/sb_0__1_/chany_bottom_out[3] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[23] -to fpga_top/sb_0__1_/chany_bottom_out[3] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[6] -to fpga_top/sb_0__1_/chany_bottom_out[3] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[17] -to fpga_top/sb_0__1_/chany_bottom_out[3] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[28] -to fpga_top/sb_0__1_/chany_bottom_out[3] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/bottom_left_grid_pin_1_[0] -to fpga_top/sb_0__1_/chany_bottom_out[3] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[10] -to fpga_top/sb_0__1_/chany_bottom_out[5] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[24] -to fpga_top/sb_0__1_/chany_bottom_out[5] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[5] -to fpga_top/sb_0__1_/chany_bottom_out[5] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[16] -to fpga_top/sb_0__1_/chany_bottom_out[5] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[27] -to fpga_top/sb_0__1_/chany_bottom_out[5] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[11] -to fpga_top/sb_0__1_/chany_bottom_out[6] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[26] -to fpga_top/sb_0__1_/chany_bottom_out[6] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[4] -to fpga_top/sb_0__1_/chany_bottom_out[6] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[15] -to fpga_top/sb_0__1_/chany_bottom_out[6] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[26] -to fpga_top/sb_0__1_/chany_bottom_out[6] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/bottom_left_grid_pin_1_[0] -to fpga_top/sb_0__1_/chany_bottom_out[6] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[12] -to fpga_top/sb_0__1_/chany_bottom_out[10] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[27] -to fpga_top/sb_0__1_/chany_bottom_out[10] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[3] -to fpga_top/sb_0__1_/chany_bottom_out[10] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[14] -to fpga_top/sb_0__1_/chany_bottom_out[10] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[25] -to fpga_top/sb_0__1_/chany_bottom_out[10] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[14] -to fpga_top/sb_0__1_/chany_bottom_out[14] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[28] -to fpga_top/sb_0__1_/chany_bottom_out[14] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[2] -to fpga_top/sb_0__1_/chany_bottom_out[14] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[13] -to fpga_top/sb_0__1_/chany_bottom_out[14] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[24] -to fpga_top/sb_0__1_/chany_bottom_out[14] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[15] -to fpga_top/sb_0__1_/chany_bottom_out[18] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[1] -to fpga_top/sb_0__1_/chany_bottom_out[18] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[12] -to fpga_top/sb_0__1_/chany_bottom_out[18] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[23] -to fpga_top/sb_0__1_/chany_bottom_out[18] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[16] -to fpga_top/sb_0__1_/chany_bottom_out[22] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[0] -to fpga_top/sb_0__1_/chany_bottom_out[22] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[11] -to fpga_top/sb_0__1_/chany_bottom_out[22] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[22] -to fpga_top/sb_0__1_/chany_bottom_out[22] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[18] -to fpga_top/sb_0__1_/chany_bottom_out[26] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[10] -to fpga_top/sb_0__1_/chany_bottom_out[26] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[21] -to fpga_top/sb_0__1_/chany_bottom_out[26] 6.020400151e-11 diff --git a/FPGA1212_SOFA_CHD_PNR/FPGA1212_SOFA_CHD_Verilog/SDC/sb_12__0_.sdc b/FPGA1212_SOFA_CHD_PNR/FPGA1212_SOFA_CHD_Verilog/SDC/sb_12__0_.sdc deleted file mode 100644 index 5ee905a..0000000 --- a/FPGA1212_SOFA_CHD_PNR/FPGA1212_SOFA_CHD_Verilog/SDC/sb_12__0_.sdc +++ /dev/null @@ -1,156 +0,0 @@ -############################################# -# Synopsys Design Constraints (SDC) -# For FPGA fabric -# Description: Constrain timing of Switch Block sb_12__0_ for PnR -# Author: Xifan TANG -# Organization: University of Utah -# Date: Tue Dec 8 15:34:14 2020 -############################################# - -############################################# -# Define time unit -############################################# -set_units -time s - -set_max_delay -from fpga_core_uut/sb_12__0_/top_left_grid_pin_44_[0] -to fpga_top/sb_12__0_/chany_top_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__0_/top_left_grid_pin_47_[0] -to fpga_top/sb_12__0_/chany_top_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__0_/top_left_grid_pin_50_[0] -to fpga_top/sb_12__0_/chany_top_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__0_/chanx_left_in[0] -to fpga_top/sb_12__0_/chany_top_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__0_/top_left_grid_pin_45_[0] -to fpga_top/sb_12__0_/chany_top_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__0_/top_left_grid_pin_48_[0] -to fpga_top/sb_12__0_/chany_top_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__0_/top_left_grid_pin_51_[0] -to fpga_top/sb_12__0_/chany_top_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__0_/chanx_left_in[29] -to fpga_top/sb_12__0_/chany_top_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__0_/top_left_grid_pin_46_[0] -to fpga_top/sb_12__0_/chany_top_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__0_/top_left_grid_pin_49_[0] -to fpga_top/sb_12__0_/chany_top_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__0_/top_right_grid_pin_1_[0] -to fpga_top/sb_12__0_/chany_top_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__0_/chanx_left_in[28] -to fpga_top/sb_12__0_/chany_top_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__0_/top_left_grid_pin_44_[0] -to fpga_top/sb_12__0_/chany_top_out[3] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__0_/top_left_grid_pin_47_[0] -to fpga_top/sb_12__0_/chany_top_out[3] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__0_/top_left_grid_pin_50_[0] -to fpga_top/sb_12__0_/chany_top_out[3] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__0_/chanx_left_in[27] -to fpga_top/sb_12__0_/chany_top_out[3] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__0_/top_left_grid_pin_45_[0] -to fpga_top/sb_12__0_/chany_top_out[4] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__0_/top_left_grid_pin_48_[0] -to fpga_top/sb_12__0_/chany_top_out[4] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__0_/top_left_grid_pin_51_[0] -to fpga_top/sb_12__0_/chany_top_out[4] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__0_/chanx_left_in[26] -to fpga_top/sb_12__0_/chany_top_out[4] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__0_/top_left_grid_pin_46_[0] -to fpga_top/sb_12__0_/chany_top_out[5] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__0_/top_left_grid_pin_49_[0] -to fpga_top/sb_12__0_/chany_top_out[5] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__0_/top_right_grid_pin_1_[0] -to fpga_top/sb_12__0_/chany_top_out[5] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__0_/chanx_left_in[25] -to fpga_top/sb_12__0_/chany_top_out[5] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__0_/top_left_grid_pin_44_[0] -to fpga_top/sb_12__0_/chany_top_out[6] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__0_/top_right_grid_pin_1_[0] -to fpga_top/sb_12__0_/chany_top_out[6] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__0_/chanx_left_in[24] -to fpga_top/sb_12__0_/chany_top_out[6] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__0_/top_left_grid_pin_45_[0] -to fpga_top/sb_12__0_/chany_top_out[7] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__0_/chanx_left_in[23] -to fpga_top/sb_12__0_/chany_top_out[7] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__0_/top_left_grid_pin_46_[0] -to fpga_top/sb_12__0_/chany_top_out[8] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__0_/chanx_left_in[22] -to fpga_top/sb_12__0_/chany_top_out[8] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__0_/top_left_grid_pin_47_[0] -to fpga_top/sb_12__0_/chany_top_out[9] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__0_/chanx_left_in[21] -to fpga_top/sb_12__0_/chany_top_out[9] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__0_/top_left_grid_pin_48_[0] -to fpga_top/sb_12__0_/chany_top_out[10] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__0_/chanx_left_in[20] -to fpga_top/sb_12__0_/chany_top_out[10] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__0_/top_left_grid_pin_49_[0] -to fpga_top/sb_12__0_/chany_top_out[11] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__0_/chanx_left_in[19] -to fpga_top/sb_12__0_/chany_top_out[11] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__0_/top_left_grid_pin_50_[0] -to fpga_top/sb_12__0_/chany_top_out[12] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__0_/chanx_left_in[18] -to fpga_top/sb_12__0_/chany_top_out[12] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__0_/top_left_grid_pin_51_[0] -to fpga_top/sb_12__0_/chany_top_out[13] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__0_/chanx_left_in[17] -to fpga_top/sb_12__0_/chany_top_out[13] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__0_/top_right_grid_pin_1_[0] -to fpga_top/sb_12__0_/chany_top_out[14] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__0_/chanx_left_in[16] -to fpga_top/sb_12__0_/chany_top_out[14] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__0_/chanx_left_in[15] -to fpga_top/sb_12__0_/chany_top_out[15] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__0_/chanx_left_in[14] -to fpga_top/sb_12__0_/chany_top_out[16] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__0_/chanx_left_in[13] -to fpga_top/sb_12__0_/chany_top_out[17] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__0_/top_left_grid_pin_44_[0] -to fpga_top/sb_12__0_/chany_top_out[18] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__0_/chanx_left_in[12] -to fpga_top/sb_12__0_/chany_top_out[18] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__0_/top_left_grid_pin_45_[0] -to fpga_top/sb_12__0_/chany_top_out[19] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__0_/chanx_left_in[11] -to fpga_top/sb_12__0_/chany_top_out[19] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__0_/top_left_grid_pin_46_[0] -to fpga_top/sb_12__0_/chany_top_out[20] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__0_/chanx_left_in[10] -to fpga_top/sb_12__0_/chany_top_out[20] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__0_/top_left_grid_pin_47_[0] -to fpga_top/sb_12__0_/chany_top_out[21] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__0_/chanx_left_in[9] -to fpga_top/sb_12__0_/chany_top_out[21] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__0_/top_left_grid_pin_48_[0] -to fpga_top/sb_12__0_/chany_top_out[22] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__0_/top_right_grid_pin_1_[0] -to fpga_top/sb_12__0_/chany_top_out[22] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__0_/chanx_left_in[8] -to fpga_top/sb_12__0_/chany_top_out[22] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__0_/top_left_grid_pin_49_[0] -to fpga_top/sb_12__0_/chany_top_out[23] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__0_/chanx_left_in[7] -to fpga_top/sb_12__0_/chany_top_out[23] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__0_/top_left_grid_pin_50_[0] -to fpga_top/sb_12__0_/chany_top_out[24] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__0_/chanx_left_in[6] -to fpga_top/sb_12__0_/chany_top_out[24] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__0_/top_left_grid_pin_51_[0] -to fpga_top/sb_12__0_/chany_top_out[25] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__0_/chanx_left_in[5] -to fpga_top/sb_12__0_/chany_top_out[25] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__0_/chanx_left_in[4] -to fpga_top/sb_12__0_/chany_top_out[26] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__0_/chanx_left_in[3] -to fpga_top/sb_12__0_/chany_top_out[27] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__0_/chanx_left_in[2] -to fpga_top/sb_12__0_/chany_top_out[28] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__0_/chanx_left_in[1] -to fpga_top/sb_12__0_/chany_top_out[29] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__0_/chany_top_in[0] -to fpga_top/sb_12__0_/chanx_left_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_1_[0] -to fpga_top/sb_12__0_/chanx_left_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_7_[0] -to fpga_top/sb_12__0_/chanx_left_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_13_[0] -to fpga_top/sb_12__0_/chanx_left_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__0_/chany_top_in[29] -to fpga_top/sb_12__0_/chanx_left_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_3_[0] -to fpga_top/sb_12__0_/chanx_left_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_9_[0] -to fpga_top/sb_12__0_/chanx_left_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_15_[0] -to fpga_top/sb_12__0_/chanx_left_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__0_/chany_top_in[28] -to fpga_top/sb_12__0_/chanx_left_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_5_[0] -to fpga_top/sb_12__0_/chanx_left_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_11_[0] -to fpga_top/sb_12__0_/chanx_left_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_17_[0] -to fpga_top/sb_12__0_/chanx_left_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__0_/chany_top_in[27] -to fpga_top/sb_12__0_/chanx_left_out[3] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_1_[0] -to fpga_top/sb_12__0_/chanx_left_out[3] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_7_[0] -to fpga_top/sb_12__0_/chanx_left_out[3] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_13_[0] -to fpga_top/sb_12__0_/chanx_left_out[3] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__0_/chany_top_in[26] -to fpga_top/sb_12__0_/chanx_left_out[4] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_3_[0] -to fpga_top/sb_12__0_/chanx_left_out[4] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_9_[0] -to fpga_top/sb_12__0_/chanx_left_out[4] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_15_[0] -to fpga_top/sb_12__0_/chanx_left_out[4] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__0_/chany_top_in[25] -to fpga_top/sb_12__0_/chanx_left_out[5] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_5_[0] -to fpga_top/sb_12__0_/chanx_left_out[5] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_11_[0] -to fpga_top/sb_12__0_/chanx_left_out[5] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_17_[0] -to fpga_top/sb_12__0_/chanx_left_out[5] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__0_/chany_top_in[24] -to fpga_top/sb_12__0_/chanx_left_out[6] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_1_[0] -to fpga_top/sb_12__0_/chanx_left_out[6] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_17_[0] -to fpga_top/sb_12__0_/chanx_left_out[6] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__0_/chany_top_in[23] -to fpga_top/sb_12__0_/chanx_left_out[7] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_3_[0] -to fpga_top/sb_12__0_/chanx_left_out[7] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__0_/chany_top_in[22] -to fpga_top/sb_12__0_/chanx_left_out[8] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_5_[0] -to fpga_top/sb_12__0_/chanx_left_out[8] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__0_/chany_top_in[21] -to fpga_top/sb_12__0_/chanx_left_out[9] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_7_[0] -to fpga_top/sb_12__0_/chanx_left_out[9] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__0_/chany_top_in[20] -to fpga_top/sb_12__0_/chanx_left_out[10] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_9_[0] -to fpga_top/sb_12__0_/chanx_left_out[10] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__0_/chany_top_in[19] -to fpga_top/sb_12__0_/chanx_left_out[11] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_11_[0] -to fpga_top/sb_12__0_/chanx_left_out[11] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__0_/chany_top_in[18] -to fpga_top/sb_12__0_/chanx_left_out[12] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_13_[0] -to fpga_top/sb_12__0_/chanx_left_out[12] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__0_/chany_top_in[17] -to fpga_top/sb_12__0_/chanx_left_out[13] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_15_[0] -to fpga_top/sb_12__0_/chanx_left_out[13] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__0_/chany_top_in[16] -to fpga_top/sb_12__0_/chanx_left_out[14] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_1_[0] -to fpga_top/sb_12__0_/chanx_left_out[14] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_17_[0] -to fpga_top/sb_12__0_/chanx_left_out[14] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__0_/chany_top_in[15] -to fpga_top/sb_12__0_/chanx_left_out[15] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_3_[0] -to fpga_top/sb_12__0_/chanx_left_out[15] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__0_/chany_top_in[14] -to fpga_top/sb_12__0_/chanx_left_out[16] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_5_[0] -to fpga_top/sb_12__0_/chanx_left_out[16] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__0_/chany_top_in[13] -to fpga_top/sb_12__0_/chanx_left_out[17] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_7_[0] -to fpga_top/sb_12__0_/chanx_left_out[17] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__0_/chany_top_in[12] -to fpga_top/sb_12__0_/chanx_left_out[18] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_9_[0] -to fpga_top/sb_12__0_/chanx_left_out[18] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__0_/chany_top_in[11] -to fpga_top/sb_12__0_/chanx_left_out[19] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_11_[0] -to fpga_top/sb_12__0_/chanx_left_out[19] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__0_/chany_top_in[10] -to fpga_top/sb_12__0_/chanx_left_out[20] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_13_[0] -to fpga_top/sb_12__0_/chanx_left_out[20] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__0_/chany_top_in[9] -to fpga_top/sb_12__0_/chanx_left_out[21] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_15_[0] -to fpga_top/sb_12__0_/chanx_left_out[21] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__0_/chany_top_in[8] -to fpga_top/sb_12__0_/chanx_left_out[22] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_1_[0] -to fpga_top/sb_12__0_/chanx_left_out[22] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_17_[0] -to fpga_top/sb_12__0_/chanx_left_out[22] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__0_/chany_top_in[7] -to fpga_top/sb_12__0_/chanx_left_out[23] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_3_[0] -to fpga_top/sb_12__0_/chanx_left_out[23] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__0_/chany_top_in[6] -to fpga_top/sb_12__0_/chanx_left_out[24] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_5_[0] -to fpga_top/sb_12__0_/chanx_left_out[24] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__0_/chany_top_in[5] -to fpga_top/sb_12__0_/chanx_left_out[25] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_7_[0] -to fpga_top/sb_12__0_/chanx_left_out[25] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__0_/chany_top_in[4] -to fpga_top/sb_12__0_/chanx_left_out[26] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_9_[0] -to fpga_top/sb_12__0_/chanx_left_out[26] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__0_/chany_top_in[3] -to fpga_top/sb_12__0_/chanx_left_out[27] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_11_[0] -to fpga_top/sb_12__0_/chanx_left_out[27] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__0_/chany_top_in[2] -to fpga_top/sb_12__0_/chanx_left_out[28] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_13_[0] -to fpga_top/sb_12__0_/chanx_left_out[28] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__0_/chany_top_in[1] -to fpga_top/sb_12__0_/chanx_left_out[29] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_15_[0] -to fpga_top/sb_12__0_/chanx_left_out[29] 6.020400151e-11 diff --git a/FPGA1212_SOFA_CHD_PNR/FPGA1212_SOFA_CHD_Verilog/SDC/sb_12__12_.sdc b/FPGA1212_SOFA_CHD_PNR/FPGA1212_SOFA_CHD_Verilog/SDC/sb_12__12_.sdc deleted file mode 100644 index 0bf6433..0000000 --- a/FPGA1212_SOFA_CHD_PNR/FPGA1212_SOFA_CHD_Verilog/SDC/sb_12__12_.sdc +++ /dev/null @@ -1,155 +0,0 @@ -############################################# -# Synopsys Design Constraints (SDC) -# For FPGA fabric -# Description: Constrain timing of Switch Block sb_12__12_ for PnR -# Author: Xifan TANG -# Organization: University of Utah -# Date: Tue Dec 8 15:34:14 2020 -############################################# - -############################################# -# Define time unit -############################################# -set_units -time s - -set_max_delay -from fpga_core_uut/sb_12__12_/bottom_right_grid_pin_1_[0] -to fpga_top/sb_12__12_/chany_bottom_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__12_/bottom_left_grid_pin_46_[0] -to fpga_top/sb_12__12_/chany_bottom_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__12_/bottom_left_grid_pin_49_[0] -to fpga_top/sb_12__12_/chany_bottom_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__12_/chanx_left_in[1] -to fpga_top/sb_12__12_/chany_bottom_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__12_/bottom_left_grid_pin_44_[0] -to fpga_top/sb_12__12_/chany_bottom_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__12_/bottom_left_grid_pin_47_[0] -to fpga_top/sb_12__12_/chany_bottom_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__12_/bottom_left_grid_pin_50_[0] -to fpga_top/sb_12__12_/chany_bottom_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__12_/chanx_left_in[2] -to fpga_top/sb_12__12_/chany_bottom_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__12_/bottom_left_grid_pin_45_[0] -to fpga_top/sb_12__12_/chany_bottom_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__12_/bottom_left_grid_pin_48_[0] -to fpga_top/sb_12__12_/chany_bottom_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__12_/bottom_left_grid_pin_51_[0] -to fpga_top/sb_12__12_/chany_bottom_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__12_/chanx_left_in[3] -to fpga_top/sb_12__12_/chany_bottom_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__12_/bottom_right_grid_pin_1_[0] -to fpga_top/sb_12__12_/chany_bottom_out[3] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__12_/bottom_left_grid_pin_46_[0] -to fpga_top/sb_12__12_/chany_bottom_out[3] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__12_/bottom_left_grid_pin_49_[0] -to fpga_top/sb_12__12_/chany_bottom_out[3] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__12_/chanx_left_in[4] -to fpga_top/sb_12__12_/chany_bottom_out[3] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__12_/bottom_left_grid_pin_44_[0] -to fpga_top/sb_12__12_/chany_bottom_out[4] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__12_/bottom_left_grid_pin_47_[0] -to fpga_top/sb_12__12_/chany_bottom_out[4] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__12_/bottom_left_grid_pin_50_[0] -to fpga_top/sb_12__12_/chany_bottom_out[4] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__12_/chanx_left_in[5] -to fpga_top/sb_12__12_/chany_bottom_out[4] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__12_/bottom_left_grid_pin_45_[0] -to fpga_top/sb_12__12_/chany_bottom_out[5] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__12_/bottom_left_grid_pin_48_[0] -to fpga_top/sb_12__12_/chany_bottom_out[5] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__12_/bottom_left_grid_pin_51_[0] -to fpga_top/sb_12__12_/chany_bottom_out[5] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__12_/chanx_left_in[6] -to fpga_top/sb_12__12_/chany_bottom_out[5] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__12_/bottom_right_grid_pin_1_[0] -to fpga_top/sb_12__12_/chany_bottom_out[6] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__12_/chanx_left_in[7] -to fpga_top/sb_12__12_/chany_bottom_out[6] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__12_/bottom_left_grid_pin_44_[0] -to fpga_top/sb_12__12_/chany_bottom_out[7] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__12_/chanx_left_in[8] -to fpga_top/sb_12__12_/chany_bottom_out[7] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__12_/bottom_left_grid_pin_45_[0] -to fpga_top/sb_12__12_/chany_bottom_out[8] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__12_/chanx_left_in[9] -to fpga_top/sb_12__12_/chany_bottom_out[8] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__12_/bottom_left_grid_pin_46_[0] -to fpga_top/sb_12__12_/chany_bottom_out[9] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__12_/chanx_left_in[10] -to fpga_top/sb_12__12_/chany_bottom_out[9] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__12_/bottom_left_grid_pin_47_[0] -to fpga_top/sb_12__12_/chany_bottom_out[10] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__12_/chanx_left_in[11] -to fpga_top/sb_12__12_/chany_bottom_out[10] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__12_/bottom_left_grid_pin_48_[0] -to fpga_top/sb_12__12_/chany_bottom_out[11] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__12_/chanx_left_in[12] -to fpga_top/sb_12__12_/chany_bottom_out[11] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__12_/bottom_left_grid_pin_49_[0] -to fpga_top/sb_12__12_/chany_bottom_out[12] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__12_/chanx_left_in[13] -to fpga_top/sb_12__12_/chany_bottom_out[12] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__12_/bottom_left_grid_pin_50_[0] -to fpga_top/sb_12__12_/chany_bottom_out[13] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__12_/chanx_left_in[14] -to fpga_top/sb_12__12_/chany_bottom_out[13] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__12_/bottom_right_grid_pin_1_[0] -to fpga_top/sb_12__12_/chany_bottom_out[14] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__12_/bottom_left_grid_pin_51_[0] -to fpga_top/sb_12__12_/chany_bottom_out[14] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__12_/chanx_left_in[15] -to fpga_top/sb_12__12_/chany_bottom_out[14] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__12_/chanx_left_in[16] -to fpga_top/sb_12__12_/chany_bottom_out[15] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__12_/chanx_left_in[17] -to fpga_top/sb_12__12_/chany_bottom_out[16] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__12_/chanx_left_in[18] -to fpga_top/sb_12__12_/chany_bottom_out[17] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__12_/chanx_left_in[19] -to fpga_top/sb_12__12_/chany_bottom_out[18] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__12_/bottom_left_grid_pin_44_[0] -to fpga_top/sb_12__12_/chany_bottom_out[19] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__12_/chanx_left_in[20] -to fpga_top/sb_12__12_/chany_bottom_out[19] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__12_/bottom_left_grid_pin_45_[0] -to fpga_top/sb_12__12_/chany_bottom_out[20] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__12_/chanx_left_in[21] -to fpga_top/sb_12__12_/chany_bottom_out[20] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__12_/bottom_left_grid_pin_46_[0] -to fpga_top/sb_12__12_/chany_bottom_out[21] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__12_/chanx_left_in[22] -to fpga_top/sb_12__12_/chany_bottom_out[21] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__12_/bottom_right_grid_pin_1_[0] -to fpga_top/sb_12__12_/chany_bottom_out[22] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__12_/bottom_left_grid_pin_47_[0] -to fpga_top/sb_12__12_/chany_bottom_out[22] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__12_/chanx_left_in[23] -to fpga_top/sb_12__12_/chany_bottom_out[22] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__12_/bottom_left_grid_pin_48_[0] -to fpga_top/sb_12__12_/chany_bottom_out[23] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__12_/chanx_left_in[24] -to fpga_top/sb_12__12_/chany_bottom_out[23] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__12_/bottom_left_grid_pin_49_[0] -to fpga_top/sb_12__12_/chany_bottom_out[24] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__12_/chanx_left_in[25] -to fpga_top/sb_12__12_/chany_bottom_out[24] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__12_/bottom_left_grid_pin_50_[0] -to fpga_top/sb_12__12_/chany_bottom_out[25] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__12_/chanx_left_in[26] -to fpga_top/sb_12__12_/chany_bottom_out[25] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__12_/bottom_left_grid_pin_51_[0] -to fpga_top/sb_12__12_/chany_bottom_out[26] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__12_/chanx_left_in[27] -to fpga_top/sb_12__12_/chany_bottom_out[26] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__12_/chanx_left_in[28] -to fpga_top/sb_12__12_/chany_bottom_out[27] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__12_/chanx_left_in[29] -to fpga_top/sb_12__12_/chany_bottom_out[28] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__12_/chanx_left_in[0] -to fpga_top/sb_12__12_/chany_bottom_out[29] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__12_/chany_bottom_in[29] -to fpga_top/sb_12__12_/chanx_left_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__12_/left_top_grid_pin_1_[0] -to fpga_top/sb_12__12_/chanx_left_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__12_/left_bottom_grid_pin_38_[0] -to fpga_top/sb_12__12_/chanx_left_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__12_/left_bottom_grid_pin_41_[0] -to fpga_top/sb_12__12_/chanx_left_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__12_/chany_bottom_in[0] -to fpga_top/sb_12__12_/chanx_left_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__12_/left_bottom_grid_pin_36_[0] -to fpga_top/sb_12__12_/chanx_left_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__12_/left_bottom_grid_pin_39_[0] -to fpga_top/sb_12__12_/chanx_left_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__12_/left_bottom_grid_pin_42_[0] -to fpga_top/sb_12__12_/chanx_left_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__12_/chany_bottom_in[1] -to fpga_top/sb_12__12_/chanx_left_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__12_/left_bottom_grid_pin_37_[0] -to fpga_top/sb_12__12_/chanx_left_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__12_/left_bottom_grid_pin_40_[0] -to fpga_top/sb_12__12_/chanx_left_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__12_/left_bottom_grid_pin_43_[0] -to fpga_top/sb_12__12_/chanx_left_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__12_/chany_bottom_in[2] -to fpga_top/sb_12__12_/chanx_left_out[3] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__12_/left_top_grid_pin_1_[0] -to fpga_top/sb_12__12_/chanx_left_out[3] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__12_/left_bottom_grid_pin_38_[0] -to fpga_top/sb_12__12_/chanx_left_out[3] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__12_/left_bottom_grid_pin_41_[0] -to fpga_top/sb_12__12_/chanx_left_out[3] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__12_/chany_bottom_in[3] -to fpga_top/sb_12__12_/chanx_left_out[4] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__12_/left_bottom_grid_pin_36_[0] -to fpga_top/sb_12__12_/chanx_left_out[4] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__12_/left_bottom_grid_pin_39_[0] -to fpga_top/sb_12__12_/chanx_left_out[4] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__12_/left_bottom_grid_pin_42_[0] -to fpga_top/sb_12__12_/chanx_left_out[4] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__12_/chany_bottom_in[4] -to fpga_top/sb_12__12_/chanx_left_out[5] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__12_/left_bottom_grid_pin_37_[0] -to fpga_top/sb_12__12_/chanx_left_out[5] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__12_/left_bottom_grid_pin_40_[0] -to fpga_top/sb_12__12_/chanx_left_out[5] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__12_/left_bottom_grid_pin_43_[0] -to fpga_top/sb_12__12_/chanx_left_out[5] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__12_/chany_bottom_in[5] -to fpga_top/sb_12__12_/chanx_left_out[6] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__12_/left_top_grid_pin_1_[0] -to fpga_top/sb_12__12_/chanx_left_out[6] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__12_/chany_bottom_in[6] -to fpga_top/sb_12__12_/chanx_left_out[7] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__12_/left_bottom_grid_pin_36_[0] -to fpga_top/sb_12__12_/chanx_left_out[7] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__12_/chany_bottom_in[7] -to fpga_top/sb_12__12_/chanx_left_out[8] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__12_/left_bottom_grid_pin_37_[0] -to fpga_top/sb_12__12_/chanx_left_out[8] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__12_/chany_bottom_in[8] -to fpga_top/sb_12__12_/chanx_left_out[9] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__12_/left_bottom_grid_pin_38_[0] -to fpga_top/sb_12__12_/chanx_left_out[9] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__12_/chany_bottom_in[9] -to fpga_top/sb_12__12_/chanx_left_out[10] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__12_/left_bottom_grid_pin_39_[0] -to fpga_top/sb_12__12_/chanx_left_out[10] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__12_/chany_bottom_in[10] -to fpga_top/sb_12__12_/chanx_left_out[11] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__12_/left_bottom_grid_pin_40_[0] -to fpga_top/sb_12__12_/chanx_left_out[11] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__12_/chany_bottom_in[11] -to fpga_top/sb_12__12_/chanx_left_out[12] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__12_/left_bottom_grid_pin_41_[0] -to fpga_top/sb_12__12_/chanx_left_out[12] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__12_/chany_bottom_in[12] -to fpga_top/sb_12__12_/chanx_left_out[13] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__12_/left_bottom_grid_pin_42_[0] -to fpga_top/sb_12__12_/chanx_left_out[13] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__12_/chany_bottom_in[13] -to fpga_top/sb_12__12_/chanx_left_out[14] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__12_/left_top_grid_pin_1_[0] -to fpga_top/sb_12__12_/chanx_left_out[14] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__12_/left_bottom_grid_pin_43_[0] -to fpga_top/sb_12__12_/chanx_left_out[14] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__12_/chany_bottom_in[14] -to fpga_top/sb_12__12_/chanx_left_out[15] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__12_/left_bottom_grid_pin_36_[0] -to fpga_top/sb_12__12_/chanx_left_out[15] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__12_/chany_bottom_in[15] -to fpga_top/sb_12__12_/chanx_left_out[16] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__12_/left_bottom_grid_pin_37_[0] -to fpga_top/sb_12__12_/chanx_left_out[16] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__12_/chany_bottom_in[16] -to fpga_top/sb_12__12_/chanx_left_out[17] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__12_/left_bottom_grid_pin_38_[0] -to fpga_top/sb_12__12_/chanx_left_out[17] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__12_/chany_bottom_in[17] -to fpga_top/sb_12__12_/chanx_left_out[18] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__12_/left_bottom_grid_pin_39_[0] -to fpga_top/sb_12__12_/chanx_left_out[18] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__12_/chany_bottom_in[18] -to fpga_top/sb_12__12_/chanx_left_out[19] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__12_/left_bottom_grid_pin_40_[0] -to fpga_top/sb_12__12_/chanx_left_out[19] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__12_/chany_bottom_in[19] -to fpga_top/sb_12__12_/chanx_left_out[20] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__12_/left_bottom_grid_pin_41_[0] -to fpga_top/sb_12__12_/chanx_left_out[20] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__12_/chany_bottom_in[20] -to fpga_top/sb_12__12_/chanx_left_out[21] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__12_/left_bottom_grid_pin_42_[0] -to fpga_top/sb_12__12_/chanx_left_out[21] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__12_/chany_bottom_in[21] -to fpga_top/sb_12__12_/chanx_left_out[22] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__12_/left_top_grid_pin_1_[0] -to fpga_top/sb_12__12_/chanx_left_out[22] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__12_/chany_bottom_in[22] -to fpga_top/sb_12__12_/chanx_left_out[23] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__12_/left_bottom_grid_pin_36_[0] -to fpga_top/sb_12__12_/chanx_left_out[23] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__12_/chany_bottom_in[23] -to fpga_top/sb_12__12_/chanx_left_out[24] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__12_/left_bottom_grid_pin_37_[0] -to fpga_top/sb_12__12_/chanx_left_out[24] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__12_/chany_bottom_in[24] -to fpga_top/sb_12__12_/chanx_left_out[25] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__12_/left_bottom_grid_pin_38_[0] -to fpga_top/sb_12__12_/chanx_left_out[25] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__12_/chany_bottom_in[25] -to fpga_top/sb_12__12_/chanx_left_out[26] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__12_/left_bottom_grid_pin_39_[0] -to fpga_top/sb_12__12_/chanx_left_out[26] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__12_/left_bottom_grid_pin_43_[0] -to fpga_top/sb_12__12_/chanx_left_out[26] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__12_/chany_bottom_in[26] -to fpga_top/sb_12__12_/chanx_left_out[27] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__12_/left_bottom_grid_pin_40_[0] -to fpga_top/sb_12__12_/chanx_left_out[27] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__12_/chany_bottom_in[27] -to fpga_top/sb_12__12_/chanx_left_out[28] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__12_/left_bottom_grid_pin_41_[0] -to fpga_top/sb_12__12_/chanx_left_out[28] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__12_/chany_bottom_in[28] -to fpga_top/sb_12__12_/chanx_left_out[29] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__12_/left_bottom_grid_pin_42_[0] -to fpga_top/sb_12__12_/chanx_left_out[29] 6.020400151e-11 diff --git a/FPGA1212_SOFA_CHD_PNR/FPGA1212_SOFA_CHD_Verilog/SDC/sb_12__1_.sdc b/FPGA1212_SOFA_CHD_PNR/FPGA1212_SOFA_CHD_Verilog/SDC/sb_12__1_.sdc deleted file mode 100644 index 917a554..0000000 --- a/FPGA1212_SOFA_CHD_PNR/FPGA1212_SOFA_CHD_Verilog/SDC/sb_12__1_.sdc +++ /dev/null @@ -1,265 +0,0 @@ -############################################# -# Synopsys Design Constraints (SDC) -# For FPGA fabric -# Description: Constrain timing of Switch Block sb_12__1_ for PnR -# Author: Xifan TANG -# Organization: University of Utah -# Date: Tue Dec 8 15:34:14 2020 -############################################# - -############################################# -# Define time unit -############################################# -set_units -time s - -set_max_delay -from fpga_core_uut/sb_12__1_/top_left_grid_pin_44_[0] -to fpga_top/sb_12__1_/chany_top_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/top_left_grid_pin_47_[0] -to fpga_top/sb_12__1_/chany_top_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/top_left_grid_pin_50_[0] -to fpga_top/sb_12__1_/chany_top_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[3] -to fpga_top/sb_12__1_/chany_top_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[19] -to fpga_top/sb_12__1_/chany_top_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[0] -to fpga_top/sb_12__1_/chany_top_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[11] -to fpga_top/sb_12__1_/chany_top_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[22] -to fpga_top/sb_12__1_/chany_top_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/top_left_grid_pin_45_[0] -to fpga_top/sb_12__1_/chany_top_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/top_left_grid_pin_48_[0] -to fpga_top/sb_12__1_/chany_top_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/top_left_grid_pin_51_[0] -to fpga_top/sb_12__1_/chany_top_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[6] -to fpga_top/sb_12__1_/chany_top_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[20] -to fpga_top/sb_12__1_/chany_top_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[10] -to fpga_top/sb_12__1_/chany_top_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[21] -to fpga_top/sb_12__1_/chany_top_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/top_left_grid_pin_46_[0] -to fpga_top/sb_12__1_/chany_top_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/top_left_grid_pin_49_[0] -to fpga_top/sb_12__1_/chany_top_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/top_right_grid_pin_1_[0] -to fpga_top/sb_12__1_/chany_top_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[7] -to fpga_top/sb_12__1_/chany_top_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[22] -to fpga_top/sb_12__1_/chany_top_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[9] -to fpga_top/sb_12__1_/chany_top_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[20] -to fpga_top/sb_12__1_/chany_top_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/top_left_grid_pin_44_[0] -to fpga_top/sb_12__1_/chany_top_out[3] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/top_left_grid_pin_46_[0] -to fpga_top/sb_12__1_/chany_top_out[3] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/top_left_grid_pin_48_[0] -to fpga_top/sb_12__1_/chany_top_out[3] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/top_left_grid_pin_50_[0] -to fpga_top/sb_12__1_/chany_top_out[3] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/top_right_grid_pin_1_[0] -to fpga_top/sb_12__1_/chany_top_out[3] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[8] -to fpga_top/sb_12__1_/chany_top_out[3] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[23] -to fpga_top/sb_12__1_/chany_top_out[3] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[8] -to fpga_top/sb_12__1_/chany_top_out[3] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[19] -to fpga_top/sb_12__1_/chany_top_out[3] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/top_left_grid_pin_45_[0] -to fpga_top/sb_12__1_/chany_top_out[5] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/top_left_grid_pin_47_[0] -to fpga_top/sb_12__1_/chany_top_out[5] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/top_left_grid_pin_49_[0] -to fpga_top/sb_12__1_/chany_top_out[5] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/top_left_grid_pin_51_[0] -to fpga_top/sb_12__1_/chany_top_out[5] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[10] -to fpga_top/sb_12__1_/chany_top_out[5] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[24] -to fpga_top/sb_12__1_/chany_top_out[5] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[7] -to fpga_top/sb_12__1_/chany_top_out[5] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[18] -to fpga_top/sb_12__1_/chany_top_out[5] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[29] -to fpga_top/sb_12__1_/chany_top_out[5] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/top_left_grid_pin_44_[0] -to fpga_top/sb_12__1_/chany_top_out[6] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/top_left_grid_pin_50_[0] -to fpga_top/sb_12__1_/chany_top_out[6] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[11] -to fpga_top/sb_12__1_/chany_top_out[6] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[26] -to fpga_top/sb_12__1_/chany_top_out[6] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[6] -to fpga_top/sb_12__1_/chany_top_out[6] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[17] -to fpga_top/sb_12__1_/chany_top_out[6] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[28] -to fpga_top/sb_12__1_/chany_top_out[6] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/top_left_grid_pin_45_[0] -to fpga_top/sb_12__1_/chany_top_out[10] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/top_left_grid_pin_51_[0] -to fpga_top/sb_12__1_/chany_top_out[10] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[12] -to fpga_top/sb_12__1_/chany_top_out[10] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[27] -to fpga_top/sb_12__1_/chany_top_out[10] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[5] -to fpga_top/sb_12__1_/chany_top_out[10] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[16] -to fpga_top/sb_12__1_/chany_top_out[10] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[27] -to fpga_top/sb_12__1_/chany_top_out[10] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/top_left_grid_pin_46_[0] -to fpga_top/sb_12__1_/chany_top_out[14] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/top_right_grid_pin_1_[0] -to fpga_top/sb_12__1_/chany_top_out[14] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[14] -to fpga_top/sb_12__1_/chany_top_out[14] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[28] -to fpga_top/sb_12__1_/chany_top_out[14] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[4] -to fpga_top/sb_12__1_/chany_top_out[14] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[15] -to fpga_top/sb_12__1_/chany_top_out[14] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[26] -to fpga_top/sb_12__1_/chany_top_out[14] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/top_left_grid_pin_47_[0] -to fpga_top/sb_12__1_/chany_top_out[18] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[15] -to fpga_top/sb_12__1_/chany_top_out[18] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[3] -to fpga_top/sb_12__1_/chany_top_out[18] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[14] -to fpga_top/sb_12__1_/chany_top_out[18] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[25] -to fpga_top/sb_12__1_/chany_top_out[18] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/top_left_grid_pin_48_[0] -to fpga_top/sb_12__1_/chany_top_out[22] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[16] -to fpga_top/sb_12__1_/chany_top_out[22] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[2] -to fpga_top/sb_12__1_/chany_top_out[22] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[13] -to fpga_top/sb_12__1_/chany_top_out[22] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[24] -to fpga_top/sb_12__1_/chany_top_out[22] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/top_left_grid_pin_49_[0] -to fpga_top/sb_12__1_/chany_top_out[26] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[18] -to fpga_top/sb_12__1_/chany_top_out[26] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[1] -to fpga_top/sb_12__1_/chany_top_out[26] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[12] -to fpga_top/sb_12__1_/chany_top_out[26] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[23] -to fpga_top/sb_12__1_/chany_top_out[26] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[3] -to fpga_top/sb_12__1_/chany_bottom_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[19] -to fpga_top/sb_12__1_/chany_bottom_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/bottom_right_grid_pin_1_[0] -to fpga_top/sb_12__1_/chany_bottom_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/bottom_left_grid_pin_46_[0] -to fpga_top/sb_12__1_/chany_bottom_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/bottom_left_grid_pin_49_[0] -to fpga_top/sb_12__1_/chany_bottom_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[1] -to fpga_top/sb_12__1_/chany_bottom_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[12] -to fpga_top/sb_12__1_/chany_bottom_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[23] -to fpga_top/sb_12__1_/chany_bottom_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[6] -to fpga_top/sb_12__1_/chany_bottom_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[20] -to fpga_top/sb_12__1_/chany_bottom_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/bottom_left_grid_pin_44_[0] -to fpga_top/sb_12__1_/chany_bottom_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/bottom_left_grid_pin_47_[0] -to fpga_top/sb_12__1_/chany_bottom_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/bottom_left_grid_pin_50_[0] -to fpga_top/sb_12__1_/chany_bottom_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[2] -to fpga_top/sb_12__1_/chany_bottom_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[13] -to fpga_top/sb_12__1_/chany_bottom_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[24] -to fpga_top/sb_12__1_/chany_bottom_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[7] -to fpga_top/sb_12__1_/chany_bottom_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[22] -to fpga_top/sb_12__1_/chany_bottom_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/bottom_left_grid_pin_45_[0] -to fpga_top/sb_12__1_/chany_bottom_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/bottom_left_grid_pin_48_[0] -to fpga_top/sb_12__1_/chany_bottom_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/bottom_left_grid_pin_51_[0] -to fpga_top/sb_12__1_/chany_bottom_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[3] -to fpga_top/sb_12__1_/chany_bottom_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[14] -to fpga_top/sb_12__1_/chany_bottom_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[25] -to fpga_top/sb_12__1_/chany_bottom_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[8] -to fpga_top/sb_12__1_/chany_bottom_out[3] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[23] -to fpga_top/sb_12__1_/chany_bottom_out[3] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/bottom_right_grid_pin_1_[0] -to fpga_top/sb_12__1_/chany_bottom_out[3] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/bottom_left_grid_pin_45_[0] -to fpga_top/sb_12__1_/chany_bottom_out[3] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/bottom_left_grid_pin_47_[0] -to fpga_top/sb_12__1_/chany_bottom_out[3] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/bottom_left_grid_pin_49_[0] -to fpga_top/sb_12__1_/chany_bottom_out[3] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/bottom_left_grid_pin_51_[0] -to fpga_top/sb_12__1_/chany_bottom_out[3] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[4] -to fpga_top/sb_12__1_/chany_bottom_out[3] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[15] -to fpga_top/sb_12__1_/chany_bottom_out[3] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[26] -to fpga_top/sb_12__1_/chany_bottom_out[3] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[10] -to fpga_top/sb_12__1_/chany_bottom_out[5] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[24] -to fpga_top/sb_12__1_/chany_bottom_out[5] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/bottom_left_grid_pin_44_[0] -to fpga_top/sb_12__1_/chany_bottom_out[5] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/bottom_left_grid_pin_46_[0] -to fpga_top/sb_12__1_/chany_bottom_out[5] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/bottom_left_grid_pin_48_[0] -to fpga_top/sb_12__1_/chany_bottom_out[5] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/bottom_left_grid_pin_50_[0] -to fpga_top/sb_12__1_/chany_bottom_out[5] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[5] -to fpga_top/sb_12__1_/chany_bottom_out[5] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[16] -to fpga_top/sb_12__1_/chany_bottom_out[5] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[27] -to fpga_top/sb_12__1_/chany_bottom_out[5] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[11] -to fpga_top/sb_12__1_/chany_bottom_out[6] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[26] -to fpga_top/sb_12__1_/chany_bottom_out[6] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/bottom_right_grid_pin_1_[0] -to fpga_top/sb_12__1_/chany_bottom_out[6] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/bottom_left_grid_pin_49_[0] -to fpga_top/sb_12__1_/chany_bottom_out[6] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[6] -to fpga_top/sb_12__1_/chany_bottom_out[6] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[17] -to fpga_top/sb_12__1_/chany_bottom_out[6] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[28] -to fpga_top/sb_12__1_/chany_bottom_out[6] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[12] -to fpga_top/sb_12__1_/chany_bottom_out[10] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[27] -to fpga_top/sb_12__1_/chany_bottom_out[10] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/bottom_left_grid_pin_44_[0] -to fpga_top/sb_12__1_/chany_bottom_out[10] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/bottom_left_grid_pin_50_[0] -to fpga_top/sb_12__1_/chany_bottom_out[10] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[7] -to fpga_top/sb_12__1_/chany_bottom_out[10] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[18] -to fpga_top/sb_12__1_/chany_bottom_out[10] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[29] -to fpga_top/sb_12__1_/chany_bottom_out[10] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[14] -to fpga_top/sb_12__1_/chany_bottom_out[14] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[28] -to fpga_top/sb_12__1_/chany_bottom_out[14] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/bottom_left_grid_pin_45_[0] -to fpga_top/sb_12__1_/chany_bottom_out[14] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/bottom_left_grid_pin_51_[0] -to fpga_top/sb_12__1_/chany_bottom_out[14] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[8] -to fpga_top/sb_12__1_/chany_bottom_out[14] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[19] -to fpga_top/sb_12__1_/chany_bottom_out[14] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[15] -to fpga_top/sb_12__1_/chany_bottom_out[18] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/bottom_left_grid_pin_46_[0] -to fpga_top/sb_12__1_/chany_bottom_out[18] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[9] -to fpga_top/sb_12__1_/chany_bottom_out[18] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[20] -to fpga_top/sb_12__1_/chany_bottom_out[18] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[16] -to fpga_top/sb_12__1_/chany_bottom_out[22] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/bottom_left_grid_pin_47_[0] -to fpga_top/sb_12__1_/chany_bottom_out[22] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[10] -to fpga_top/sb_12__1_/chany_bottom_out[22] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[21] -to fpga_top/sb_12__1_/chany_bottom_out[22] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[18] -to fpga_top/sb_12__1_/chany_bottom_out[26] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/bottom_left_grid_pin_48_[0] -to fpga_top/sb_12__1_/chany_bottom_out[26] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[0] -to fpga_top/sb_12__1_/chany_bottom_out[26] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[11] -to fpga_top/sb_12__1_/chany_bottom_out[26] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[22] -to fpga_top/sb_12__1_/chany_bottom_out[26] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[0] -to fpga_top/sb_12__1_/chanx_left_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[3] -to fpga_top/sb_12__1_/chanx_left_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[3] -to fpga_top/sb_12__1_/chanx_left_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/left_bottom_grid_pin_36_[0] -to fpga_top/sb_12__1_/chanx_left_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/left_bottom_grid_pin_39_[0] -to fpga_top/sb_12__1_/chanx_left_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/left_bottom_grid_pin_42_[0] -to fpga_top/sb_12__1_/chanx_left_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[6] -to fpga_top/sb_12__1_/chanx_left_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[0] -to fpga_top/sb_12__1_/chanx_left_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[6] -to fpga_top/sb_12__1_/chanx_left_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/left_bottom_grid_pin_37_[0] -to fpga_top/sb_12__1_/chanx_left_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/left_bottom_grid_pin_40_[0] -to fpga_top/sb_12__1_/chanx_left_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/left_bottom_grid_pin_43_[0] -to fpga_top/sb_12__1_/chanx_left_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[7] -to fpga_top/sb_12__1_/chanx_left_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[1] -to fpga_top/sb_12__1_/chanx_left_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[7] -to fpga_top/sb_12__1_/chanx_left_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/left_bottom_grid_pin_38_[0] -to fpga_top/sb_12__1_/chanx_left_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/left_bottom_grid_pin_41_[0] -to fpga_top/sb_12__1_/chanx_left_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[8] -to fpga_top/sb_12__1_/chanx_left_out[3] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[2] -to fpga_top/sb_12__1_/chanx_left_out[3] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[8] -to fpga_top/sb_12__1_/chanx_left_out[3] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/left_bottom_grid_pin_36_[0] -to fpga_top/sb_12__1_/chanx_left_out[3] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/left_bottom_grid_pin_39_[0] -to fpga_top/sb_12__1_/chanx_left_out[3] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/left_bottom_grid_pin_42_[0] -to fpga_top/sb_12__1_/chanx_left_out[3] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[10] -to fpga_top/sb_12__1_/chanx_left_out[4] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[4] -to fpga_top/sb_12__1_/chanx_left_out[4] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[10] -to fpga_top/sb_12__1_/chanx_left_out[4] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/left_bottom_grid_pin_37_[0] -to fpga_top/sb_12__1_/chanx_left_out[4] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/left_bottom_grid_pin_40_[0] -to fpga_top/sb_12__1_/chanx_left_out[4] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/left_bottom_grid_pin_43_[0] -to fpga_top/sb_12__1_/chanx_left_out[4] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[11] -to fpga_top/sb_12__1_/chanx_left_out[5] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[5] -to fpga_top/sb_12__1_/chanx_left_out[5] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[11] -to fpga_top/sb_12__1_/chanx_left_out[5] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/left_bottom_grid_pin_38_[0] -to fpga_top/sb_12__1_/chanx_left_out[5] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/left_bottom_grid_pin_41_[0] -to fpga_top/sb_12__1_/chanx_left_out[5] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[12] -to fpga_top/sb_12__1_/chanx_left_out[6] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[9] -to fpga_top/sb_12__1_/chanx_left_out[6] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[12] -to fpga_top/sb_12__1_/chanx_left_out[6] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/left_bottom_grid_pin_36_[0] -to fpga_top/sb_12__1_/chanx_left_out[6] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[14] -to fpga_top/sb_12__1_/chanx_left_out[7] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[13] -to fpga_top/sb_12__1_/chanx_left_out[7] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[14] -to fpga_top/sb_12__1_/chanx_left_out[7] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/left_bottom_grid_pin_37_[0] -to fpga_top/sb_12__1_/chanx_left_out[7] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[15] -to fpga_top/sb_12__1_/chanx_left_out[8] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[15] -to fpga_top/sb_12__1_/chanx_left_out[8] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[17] -to fpga_top/sb_12__1_/chanx_left_out[8] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/left_bottom_grid_pin_38_[0] -to fpga_top/sb_12__1_/chanx_left_out[8] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[16] -to fpga_top/sb_12__1_/chanx_left_out[9] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[16] -to fpga_top/sb_12__1_/chanx_left_out[9] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[21] -to fpga_top/sb_12__1_/chanx_left_out[9] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/left_bottom_grid_pin_39_[0] -to fpga_top/sb_12__1_/chanx_left_out[9] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[18] -to fpga_top/sb_12__1_/chanx_left_out[10] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[18] -to fpga_top/sb_12__1_/chanx_left_out[10] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[25] -to fpga_top/sb_12__1_/chanx_left_out[10] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/left_bottom_grid_pin_40_[0] -to fpga_top/sb_12__1_/chanx_left_out[10] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[19] -to fpga_top/sb_12__1_/chanx_left_out[11] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[19] -to fpga_top/sb_12__1_/chanx_left_out[11] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[29] -to fpga_top/sb_12__1_/chanx_left_out[11] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/left_bottom_grid_pin_41_[0] -to fpga_top/sb_12__1_/chanx_left_out[11] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[20] -to fpga_top/sb_12__1_/chanx_left_out[12] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[20] -to fpga_top/sb_12__1_/chanx_left_out[12] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/left_bottom_grid_pin_42_[0] -to fpga_top/sb_12__1_/chanx_left_out[12] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[22] -to fpga_top/sb_12__1_/chanx_left_out[13] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[22] -to fpga_top/sb_12__1_/chanx_left_out[13] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/left_bottom_grid_pin_43_[0] -to fpga_top/sb_12__1_/chanx_left_out[13] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[23] -to fpga_top/sb_12__1_/chanx_left_out[14] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[23] -to fpga_top/sb_12__1_/chanx_left_out[14] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/left_bottom_grid_pin_36_[0] -to fpga_top/sb_12__1_/chanx_left_out[14] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[24] -to fpga_top/sb_12__1_/chanx_left_out[15] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[24] -to fpga_top/sb_12__1_/chanx_left_out[15] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/left_bottom_grid_pin_37_[0] -to fpga_top/sb_12__1_/chanx_left_out[15] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[26] -to fpga_top/sb_12__1_/chanx_left_out[16] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[26] -to fpga_top/sb_12__1_/chanx_left_out[16] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/left_bottom_grid_pin_38_[0] -to fpga_top/sb_12__1_/chanx_left_out[16] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[27] -to fpga_top/sb_12__1_/chanx_left_out[17] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[27] -to fpga_top/sb_12__1_/chanx_left_out[17] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/left_bottom_grid_pin_39_[0] -to fpga_top/sb_12__1_/chanx_left_out[17] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[28] -to fpga_top/sb_12__1_/chanx_left_out[18] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[28] -to fpga_top/sb_12__1_/chanx_left_out[18] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/left_bottom_grid_pin_40_[0] -to fpga_top/sb_12__1_/chanx_left_out[18] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/left_bottom_grid_pin_41_[0] -to fpga_top/sb_12__1_/chanx_left_out[19] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[29] -to fpga_top/sb_12__1_/chanx_left_out[20] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/left_bottom_grid_pin_42_[0] -to fpga_top/sb_12__1_/chanx_left_out[20] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[25] -to fpga_top/sb_12__1_/chanx_left_out[21] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[21] -to fpga_top/sb_12__1_/chanx_left_out[22] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/left_bottom_grid_pin_36_[0] -to fpga_top/sb_12__1_/chanx_left_out[22] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[17] -to fpga_top/sb_12__1_/chanx_left_out[23] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/left_bottom_grid_pin_37_[0] -to fpga_top/sb_12__1_/chanx_left_out[23] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[13] -to fpga_top/sb_12__1_/chanx_left_out[24] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/left_bottom_grid_pin_38_[0] -to fpga_top/sb_12__1_/chanx_left_out[24] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[9] -to fpga_top/sb_12__1_/chanx_left_out[25] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/left_bottom_grid_pin_39_[0] -to fpga_top/sb_12__1_/chanx_left_out[25] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/left_bottom_grid_pin_43_[0] -to fpga_top/sb_12__1_/chanx_left_out[25] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[5] -to fpga_top/sb_12__1_/chanx_left_out[26] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/left_bottom_grid_pin_40_[0] -to fpga_top/sb_12__1_/chanx_left_out[26] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[4] -to fpga_top/sb_12__1_/chanx_left_out[27] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/left_bottom_grid_pin_41_[0] -to fpga_top/sb_12__1_/chanx_left_out[27] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[2] -to fpga_top/sb_12__1_/chanx_left_out[28] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/left_bottom_grid_pin_42_[0] -to fpga_top/sb_12__1_/chanx_left_out[28] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[1] -to fpga_top/sb_12__1_/chanx_left_out[29] 6.020400151e-11 diff --git a/FPGA1212_SOFA_CHD_PNR/FPGA1212_SOFA_CHD_Verilog/SDC/sb_1__0_.sdc b/FPGA1212_SOFA_CHD_PNR/FPGA1212_SOFA_CHD_Verilog/SDC/sb_1__0_.sdc deleted file mode 100644 index 2a26a8f..0000000 --- a/FPGA1212_SOFA_CHD_PNR/FPGA1212_SOFA_CHD_Verilog/SDC/sb_1__0_.sdc +++ /dev/null @@ -1,258 +0,0 @@ -############################################# -# Synopsys Design Constraints (SDC) -# For FPGA fabric -# Description: Constrain timing of Switch Block sb_1__0_ for PnR -# Author: Xifan TANG -# Organization: University of Utah -# Date: Tue Dec 8 15:34:14 2020 -############################################# - -############################################# -# Define time unit -############################################# -set_units -time s - -set_max_delay -from fpga_core_uut/sb_1__0_/top_left_grid_pin_44_[0] -to fpga_top/sb_1__0_/chany_top_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/top_left_grid_pin_47_[0] -to fpga_top/sb_1__0_/chany_top_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/top_left_grid_pin_50_[0] -to fpga_top/sb_1__0_/chany_top_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[1] -to fpga_top/sb_1__0_/chany_top_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[3] -to fpga_top/sb_1__0_/chany_top_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[0] -to fpga_top/sb_1__0_/chany_top_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[3] -to fpga_top/sb_1__0_/chany_top_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/top_left_grid_pin_45_[0] -to fpga_top/sb_1__0_/chany_top_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/top_left_grid_pin_48_[0] -to fpga_top/sb_1__0_/chany_top_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/top_left_grid_pin_51_[0] -to fpga_top/sb_1__0_/chany_top_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[2] -to fpga_top/sb_1__0_/chany_top_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[6] -to fpga_top/sb_1__0_/chany_top_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[6] -to fpga_top/sb_1__0_/chany_top_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/top_left_grid_pin_46_[0] -to fpga_top/sb_1__0_/chany_top_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/top_left_grid_pin_49_[0] -to fpga_top/sb_1__0_/chany_top_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[4] -to fpga_top/sb_1__0_/chany_top_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[7] -to fpga_top/sb_1__0_/chany_top_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[7] -to fpga_top/sb_1__0_/chany_top_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/top_left_grid_pin_44_[0] -to fpga_top/sb_1__0_/chany_top_out[3] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/top_left_grid_pin_47_[0] -to fpga_top/sb_1__0_/chany_top_out[3] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/top_left_grid_pin_50_[0] -to fpga_top/sb_1__0_/chany_top_out[3] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[5] -to fpga_top/sb_1__0_/chany_top_out[3] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[8] -to fpga_top/sb_1__0_/chany_top_out[3] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[8] -to fpga_top/sb_1__0_/chany_top_out[3] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/top_left_grid_pin_45_[0] -to fpga_top/sb_1__0_/chany_top_out[4] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/top_left_grid_pin_48_[0] -to fpga_top/sb_1__0_/chany_top_out[4] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/top_left_grid_pin_51_[0] -to fpga_top/sb_1__0_/chany_top_out[4] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[9] -to fpga_top/sb_1__0_/chany_top_out[4] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[10] -to fpga_top/sb_1__0_/chany_top_out[4] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[10] -to fpga_top/sb_1__0_/chany_top_out[4] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/top_left_grid_pin_46_[0] -to fpga_top/sb_1__0_/chany_top_out[5] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/top_left_grid_pin_49_[0] -to fpga_top/sb_1__0_/chany_top_out[5] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[11] -to fpga_top/sb_1__0_/chany_top_out[5] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[13] -to fpga_top/sb_1__0_/chany_top_out[5] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[11] -to fpga_top/sb_1__0_/chany_top_out[5] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/top_left_grid_pin_44_[0] -to fpga_top/sb_1__0_/chany_top_out[6] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[12] -to fpga_top/sb_1__0_/chany_top_out[6] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[17] -to fpga_top/sb_1__0_/chany_top_out[6] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[12] -to fpga_top/sb_1__0_/chany_top_out[6] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/top_left_grid_pin_45_[0] -to fpga_top/sb_1__0_/chany_top_out[7] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[14] -to fpga_top/sb_1__0_/chany_top_out[7] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[21] -to fpga_top/sb_1__0_/chany_top_out[7] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[14] -to fpga_top/sb_1__0_/chany_top_out[7] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/top_left_grid_pin_46_[0] -to fpga_top/sb_1__0_/chany_top_out[8] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[15] -to fpga_top/sb_1__0_/chany_top_out[8] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[25] -to fpga_top/sb_1__0_/chany_top_out[8] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[15] -to fpga_top/sb_1__0_/chany_top_out[8] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/top_left_grid_pin_47_[0] -to fpga_top/sb_1__0_/chany_top_out[9] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[16] -to fpga_top/sb_1__0_/chany_top_out[9] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[29] -to fpga_top/sb_1__0_/chany_top_out[9] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[16] -to fpga_top/sb_1__0_/chany_top_out[9] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/top_left_grid_pin_48_[0] -to fpga_top/sb_1__0_/chany_top_out[10] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[18] -to fpga_top/sb_1__0_/chany_top_out[10] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[18] -to fpga_top/sb_1__0_/chany_top_out[10] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/top_left_grid_pin_49_[0] -to fpga_top/sb_1__0_/chany_top_out[11] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[19] -to fpga_top/sb_1__0_/chany_top_out[11] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[19] -to fpga_top/sb_1__0_/chany_top_out[11] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/top_left_grid_pin_50_[0] -to fpga_top/sb_1__0_/chany_top_out[12] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[20] -to fpga_top/sb_1__0_/chany_top_out[12] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[20] -to fpga_top/sb_1__0_/chany_top_out[12] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/top_left_grid_pin_51_[0] -to fpga_top/sb_1__0_/chany_top_out[13] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[22] -to fpga_top/sb_1__0_/chany_top_out[13] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[22] -to fpga_top/sb_1__0_/chany_top_out[13] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[23] -to fpga_top/sb_1__0_/chany_top_out[14] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[23] -to fpga_top/sb_1__0_/chany_top_out[14] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[24] -to fpga_top/sb_1__0_/chany_top_out[15] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[24] -to fpga_top/sb_1__0_/chany_top_out[15] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[26] -to fpga_top/sb_1__0_/chany_top_out[16] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[26] -to fpga_top/sb_1__0_/chany_top_out[16] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[27] -to fpga_top/sb_1__0_/chany_top_out[17] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[27] -to fpga_top/sb_1__0_/chany_top_out[17] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/top_left_grid_pin_44_[0] -to fpga_top/sb_1__0_/chany_top_out[18] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[28] -to fpga_top/sb_1__0_/chany_top_out[18] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[28] -to fpga_top/sb_1__0_/chany_top_out[18] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/top_left_grid_pin_45_[0] -to fpga_top/sb_1__0_/chany_top_out[19] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/top_left_grid_pin_46_[0] -to fpga_top/sb_1__0_/chany_top_out[20] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[29] -to fpga_top/sb_1__0_/chany_top_out[20] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/top_left_grid_pin_47_[0] -to fpga_top/sb_1__0_/chany_top_out[21] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[25] -to fpga_top/sb_1__0_/chany_top_out[21] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/top_left_grid_pin_48_[0] -to fpga_top/sb_1__0_/chany_top_out[22] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[21] -to fpga_top/sb_1__0_/chany_top_out[22] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/top_left_grid_pin_49_[0] -to fpga_top/sb_1__0_/chany_top_out[23] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[17] -to fpga_top/sb_1__0_/chany_top_out[23] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/top_left_grid_pin_50_[0] -to fpga_top/sb_1__0_/chany_top_out[24] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[13] -to fpga_top/sb_1__0_/chany_top_out[24] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/top_left_grid_pin_51_[0] -to fpga_top/sb_1__0_/chany_top_out[25] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[9] -to fpga_top/sb_1__0_/chany_top_out[25] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[5] -to fpga_top/sb_1__0_/chany_top_out[26] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[4] -to fpga_top/sb_1__0_/chany_top_out[27] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[2] -to fpga_top/sb_1__0_/chany_top_out[28] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[0] -to fpga_top/sb_1__0_/chany_top_out[29] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[1] -to fpga_top/sb_1__0_/chany_top_out[29] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[10] -to fpga_top/sb_1__0_/chanx_right_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[21] -to fpga_top/sb_1__0_/chanx_right_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/right_bottom_grid_pin_1_[0] -to fpga_top/sb_1__0_/chanx_right_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/right_bottom_grid_pin_7_[0] -to fpga_top/sb_1__0_/chanx_right_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/right_bottom_grid_pin_13_[0] -to fpga_top/sb_1__0_/chanx_right_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[3] -to fpga_top/sb_1__0_/chanx_right_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[19] -to fpga_top/sb_1__0_/chanx_right_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[0] -to fpga_top/sb_1__0_/chanx_right_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[11] -to fpga_top/sb_1__0_/chanx_right_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[22] -to fpga_top/sb_1__0_/chanx_right_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/right_bottom_grid_pin_3_[0] -to fpga_top/sb_1__0_/chanx_right_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/right_bottom_grid_pin_9_[0] -to fpga_top/sb_1__0_/chanx_right_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/right_bottom_grid_pin_15_[0] -to fpga_top/sb_1__0_/chanx_right_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[6] -to fpga_top/sb_1__0_/chanx_right_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[20] -to fpga_top/sb_1__0_/chanx_right_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[1] -to fpga_top/sb_1__0_/chanx_right_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[12] -to fpga_top/sb_1__0_/chanx_right_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[23] -to fpga_top/sb_1__0_/chanx_right_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/right_bottom_grid_pin_5_[0] -to fpga_top/sb_1__0_/chanx_right_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/right_bottom_grid_pin_11_[0] -to fpga_top/sb_1__0_/chanx_right_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/right_bottom_grid_pin_17_[0] -to fpga_top/sb_1__0_/chanx_right_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[7] -to fpga_top/sb_1__0_/chanx_right_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[22] -to fpga_top/sb_1__0_/chanx_right_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[2] -to fpga_top/sb_1__0_/chanx_right_out[3] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[13] -to fpga_top/sb_1__0_/chanx_right_out[3] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[24] -to fpga_top/sb_1__0_/chanx_right_out[3] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/right_bottom_grid_pin_1_[0] -to fpga_top/sb_1__0_/chanx_right_out[3] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/right_bottom_grid_pin_5_[0] -to fpga_top/sb_1__0_/chanx_right_out[3] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/right_bottom_grid_pin_9_[0] -to fpga_top/sb_1__0_/chanx_right_out[3] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/right_bottom_grid_pin_13_[0] -to fpga_top/sb_1__0_/chanx_right_out[3] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/right_bottom_grid_pin_17_[0] -to fpga_top/sb_1__0_/chanx_right_out[3] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[8] -to fpga_top/sb_1__0_/chanx_right_out[3] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[23] -to fpga_top/sb_1__0_/chanx_right_out[3] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[3] -to fpga_top/sb_1__0_/chanx_right_out[5] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[14] -to fpga_top/sb_1__0_/chanx_right_out[5] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[25] -to fpga_top/sb_1__0_/chanx_right_out[5] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/right_bottom_grid_pin_3_[0] -to fpga_top/sb_1__0_/chanx_right_out[5] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/right_bottom_grid_pin_7_[0] -to fpga_top/sb_1__0_/chanx_right_out[5] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/right_bottom_grid_pin_11_[0] -to fpga_top/sb_1__0_/chanx_right_out[5] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/right_bottom_grid_pin_15_[0] -to fpga_top/sb_1__0_/chanx_right_out[5] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[10] -to fpga_top/sb_1__0_/chanx_right_out[5] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[24] -to fpga_top/sb_1__0_/chanx_right_out[5] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[4] -to fpga_top/sb_1__0_/chanx_right_out[6] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[15] -to fpga_top/sb_1__0_/chanx_right_out[6] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[26] -to fpga_top/sb_1__0_/chanx_right_out[6] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/right_bottom_grid_pin_1_[0] -to fpga_top/sb_1__0_/chanx_right_out[6] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/right_bottom_grid_pin_13_[0] -to fpga_top/sb_1__0_/chanx_right_out[6] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[11] -to fpga_top/sb_1__0_/chanx_right_out[6] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[26] -to fpga_top/sb_1__0_/chanx_right_out[6] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[5] -to fpga_top/sb_1__0_/chanx_right_out[10] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[16] -to fpga_top/sb_1__0_/chanx_right_out[10] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[27] -to fpga_top/sb_1__0_/chanx_right_out[10] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/right_bottom_grid_pin_3_[0] -to fpga_top/sb_1__0_/chanx_right_out[10] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/right_bottom_grid_pin_15_[0] -to fpga_top/sb_1__0_/chanx_right_out[10] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[12] -to fpga_top/sb_1__0_/chanx_right_out[10] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[27] -to fpga_top/sb_1__0_/chanx_right_out[10] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[6] -to fpga_top/sb_1__0_/chanx_right_out[14] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[17] -to fpga_top/sb_1__0_/chanx_right_out[14] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[28] -to fpga_top/sb_1__0_/chanx_right_out[14] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/right_bottom_grid_pin_5_[0] -to fpga_top/sb_1__0_/chanx_right_out[14] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/right_bottom_grid_pin_17_[0] -to fpga_top/sb_1__0_/chanx_right_out[14] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[14] -to fpga_top/sb_1__0_/chanx_right_out[14] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[28] -to fpga_top/sb_1__0_/chanx_right_out[14] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[7] -to fpga_top/sb_1__0_/chanx_right_out[18] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[18] -to fpga_top/sb_1__0_/chanx_right_out[18] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[29] -to fpga_top/sb_1__0_/chanx_right_out[18] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/right_bottom_grid_pin_7_[0] -to fpga_top/sb_1__0_/chanx_right_out[18] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[15] -to fpga_top/sb_1__0_/chanx_right_out[18] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[8] -to fpga_top/sb_1__0_/chanx_right_out[22] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[19] -to fpga_top/sb_1__0_/chanx_right_out[22] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/right_bottom_grid_pin_9_[0] -to fpga_top/sb_1__0_/chanx_right_out[22] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[16] -to fpga_top/sb_1__0_/chanx_right_out[22] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[9] -to fpga_top/sb_1__0_/chanx_right_out[26] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[20] -to fpga_top/sb_1__0_/chanx_right_out[26] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/right_bottom_grid_pin_11_[0] -to fpga_top/sb_1__0_/chanx_right_out[26] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[18] -to fpga_top/sb_1__0_/chanx_right_out[26] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[0] -to fpga_top/sb_1__0_/chanx_left_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[11] -to fpga_top/sb_1__0_/chanx_left_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[22] -to fpga_top/sb_1__0_/chanx_left_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[3] -to fpga_top/sb_1__0_/chanx_left_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[19] -to fpga_top/sb_1__0_/chanx_left_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/left_bottom_grid_pin_1_[0] -to fpga_top/sb_1__0_/chanx_left_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/left_bottom_grid_pin_7_[0] -to fpga_top/sb_1__0_/chanx_left_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/left_bottom_grid_pin_13_[0] -to fpga_top/sb_1__0_/chanx_left_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[10] -to fpga_top/sb_1__0_/chanx_left_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[21] -to fpga_top/sb_1__0_/chanx_left_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[6] -to fpga_top/sb_1__0_/chanx_left_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[20] -to fpga_top/sb_1__0_/chanx_left_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/left_bottom_grid_pin_3_[0] -to fpga_top/sb_1__0_/chanx_left_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/left_bottom_grid_pin_9_[0] -to fpga_top/sb_1__0_/chanx_left_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/left_bottom_grid_pin_15_[0] -to fpga_top/sb_1__0_/chanx_left_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[9] -to fpga_top/sb_1__0_/chanx_left_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[20] -to fpga_top/sb_1__0_/chanx_left_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[7] -to fpga_top/sb_1__0_/chanx_left_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[22] -to fpga_top/sb_1__0_/chanx_left_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/left_bottom_grid_pin_5_[0] -to fpga_top/sb_1__0_/chanx_left_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/left_bottom_grid_pin_11_[0] -to fpga_top/sb_1__0_/chanx_left_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/left_bottom_grid_pin_17_[0] -to fpga_top/sb_1__0_/chanx_left_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[8] -to fpga_top/sb_1__0_/chanx_left_out[3] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[19] -to fpga_top/sb_1__0_/chanx_left_out[3] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[8] -to fpga_top/sb_1__0_/chanx_left_out[3] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[23] -to fpga_top/sb_1__0_/chanx_left_out[3] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/left_bottom_grid_pin_1_[0] -to fpga_top/sb_1__0_/chanx_left_out[3] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/left_bottom_grid_pin_5_[0] -to fpga_top/sb_1__0_/chanx_left_out[3] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/left_bottom_grid_pin_9_[0] -to fpga_top/sb_1__0_/chanx_left_out[3] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/left_bottom_grid_pin_13_[0] -to fpga_top/sb_1__0_/chanx_left_out[3] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/left_bottom_grid_pin_17_[0] -to fpga_top/sb_1__0_/chanx_left_out[3] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[7] -to fpga_top/sb_1__0_/chanx_left_out[5] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[18] -to fpga_top/sb_1__0_/chanx_left_out[5] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[29] -to fpga_top/sb_1__0_/chanx_left_out[5] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[10] -to fpga_top/sb_1__0_/chanx_left_out[5] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[24] -to fpga_top/sb_1__0_/chanx_left_out[5] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/left_bottom_grid_pin_3_[0] -to fpga_top/sb_1__0_/chanx_left_out[5] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/left_bottom_grid_pin_7_[0] -to fpga_top/sb_1__0_/chanx_left_out[5] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/left_bottom_grid_pin_11_[0] -to fpga_top/sb_1__0_/chanx_left_out[5] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/left_bottom_grid_pin_15_[0] -to fpga_top/sb_1__0_/chanx_left_out[5] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[6] -to fpga_top/sb_1__0_/chanx_left_out[6] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[17] -to fpga_top/sb_1__0_/chanx_left_out[6] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[28] -to fpga_top/sb_1__0_/chanx_left_out[6] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[11] -to fpga_top/sb_1__0_/chanx_left_out[6] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[26] -to fpga_top/sb_1__0_/chanx_left_out[6] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/left_bottom_grid_pin_1_[0] -to fpga_top/sb_1__0_/chanx_left_out[6] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/left_bottom_grid_pin_13_[0] -to fpga_top/sb_1__0_/chanx_left_out[6] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[5] -to fpga_top/sb_1__0_/chanx_left_out[10] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[16] -to fpga_top/sb_1__0_/chanx_left_out[10] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[27] -to fpga_top/sb_1__0_/chanx_left_out[10] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[12] -to fpga_top/sb_1__0_/chanx_left_out[10] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[27] -to fpga_top/sb_1__0_/chanx_left_out[10] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/left_bottom_grid_pin_3_[0] -to fpga_top/sb_1__0_/chanx_left_out[10] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/left_bottom_grid_pin_15_[0] -to fpga_top/sb_1__0_/chanx_left_out[10] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[4] -to fpga_top/sb_1__0_/chanx_left_out[14] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[15] -to fpga_top/sb_1__0_/chanx_left_out[14] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[26] -to fpga_top/sb_1__0_/chanx_left_out[14] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[14] -to fpga_top/sb_1__0_/chanx_left_out[14] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[28] -to fpga_top/sb_1__0_/chanx_left_out[14] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/left_bottom_grid_pin_5_[0] -to fpga_top/sb_1__0_/chanx_left_out[14] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/left_bottom_grid_pin_17_[0] -to fpga_top/sb_1__0_/chanx_left_out[14] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[3] -to fpga_top/sb_1__0_/chanx_left_out[18] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[14] -to fpga_top/sb_1__0_/chanx_left_out[18] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[25] -to fpga_top/sb_1__0_/chanx_left_out[18] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[15] -to fpga_top/sb_1__0_/chanx_left_out[18] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/left_bottom_grid_pin_7_[0] -to fpga_top/sb_1__0_/chanx_left_out[18] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[2] -to fpga_top/sb_1__0_/chanx_left_out[22] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[13] -to fpga_top/sb_1__0_/chanx_left_out[22] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[24] -to fpga_top/sb_1__0_/chanx_left_out[22] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[16] -to fpga_top/sb_1__0_/chanx_left_out[22] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/left_bottom_grid_pin_9_[0] -to fpga_top/sb_1__0_/chanx_left_out[22] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[1] -to fpga_top/sb_1__0_/chanx_left_out[26] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[12] -to fpga_top/sb_1__0_/chanx_left_out[26] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[23] -to fpga_top/sb_1__0_/chanx_left_out[26] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[18] -to fpga_top/sb_1__0_/chanx_left_out[26] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__0_/left_bottom_grid_pin_11_[0] -to fpga_top/sb_1__0_/chanx_left_out[26] 6.020400151e-11 diff --git a/FPGA1212_SOFA_CHD_PNR/FPGA1212_SOFA_CHD_Verilog/SDC/sb_1__12_.sdc b/FPGA1212_SOFA_CHD_PNR/FPGA1212_SOFA_CHD_Verilog/SDC/sb_1__12_.sdc deleted file mode 100644 index 1b03b66..0000000 --- a/FPGA1212_SOFA_CHD_PNR/FPGA1212_SOFA_CHD_Verilog/SDC/sb_1__12_.sdc +++ /dev/null @@ -1,258 +0,0 @@ -############################################# -# Synopsys Design Constraints (SDC) -# For FPGA fabric -# Description: Constrain timing of Switch Block sb_1__12_ for PnR -# Author: Xifan TANG -# Organization: University of Utah -# Date: Tue Dec 8 15:34:14 2020 -############################################# - -############################################# -# Define time unit -############################################# -set_units -time s - -set_max_delay -from fpga_core_uut/sb_1__12_/right_top_grid_pin_1_[0] -to fpga_top/sb_1__12_/chanx_right_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/right_bottom_grid_pin_38_[0] -to fpga_top/sb_1__12_/chanx_right_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/right_bottom_grid_pin_41_[0] -to fpga_top/sb_1__12_/chanx_right_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[9] -to fpga_top/sb_1__12_/chanx_right_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[20] -to fpga_top/sb_1__12_/chanx_right_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[3] -to fpga_top/sb_1__12_/chanx_right_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[19] -to fpga_top/sb_1__12_/chanx_right_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/right_bottom_grid_pin_36_[0] -to fpga_top/sb_1__12_/chanx_right_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/right_bottom_grid_pin_39_[0] -to fpga_top/sb_1__12_/chanx_right_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/right_bottom_grid_pin_42_[0] -to fpga_top/sb_1__12_/chanx_right_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[8] -to fpga_top/sb_1__12_/chanx_right_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[19] -to fpga_top/sb_1__12_/chanx_right_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[6] -to fpga_top/sb_1__12_/chanx_right_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[20] -to fpga_top/sb_1__12_/chanx_right_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/right_bottom_grid_pin_37_[0] -to fpga_top/sb_1__12_/chanx_right_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/right_bottom_grid_pin_40_[0] -to fpga_top/sb_1__12_/chanx_right_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/right_bottom_grid_pin_43_[0] -to fpga_top/sb_1__12_/chanx_right_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[7] -to fpga_top/sb_1__12_/chanx_right_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[18] -to fpga_top/sb_1__12_/chanx_right_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[29] -to fpga_top/sb_1__12_/chanx_right_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[7] -to fpga_top/sb_1__12_/chanx_right_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[22] -to fpga_top/sb_1__12_/chanx_right_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/right_top_grid_pin_1_[0] -to fpga_top/sb_1__12_/chanx_right_out[3] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/right_bottom_grid_pin_37_[0] -to fpga_top/sb_1__12_/chanx_right_out[3] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/right_bottom_grid_pin_39_[0] -to fpga_top/sb_1__12_/chanx_right_out[3] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/right_bottom_grid_pin_41_[0] -to fpga_top/sb_1__12_/chanx_right_out[3] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/right_bottom_grid_pin_43_[0] -to fpga_top/sb_1__12_/chanx_right_out[3] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[6] -to fpga_top/sb_1__12_/chanx_right_out[3] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[17] -to fpga_top/sb_1__12_/chanx_right_out[3] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[28] -to fpga_top/sb_1__12_/chanx_right_out[3] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[8] -to fpga_top/sb_1__12_/chanx_right_out[3] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[23] -to fpga_top/sb_1__12_/chanx_right_out[3] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/right_bottom_grid_pin_36_[0] -to fpga_top/sb_1__12_/chanx_right_out[5] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/right_bottom_grid_pin_38_[0] -to fpga_top/sb_1__12_/chanx_right_out[5] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/right_bottom_grid_pin_40_[0] -to fpga_top/sb_1__12_/chanx_right_out[5] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/right_bottom_grid_pin_42_[0] -to fpga_top/sb_1__12_/chanx_right_out[5] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[5] -to fpga_top/sb_1__12_/chanx_right_out[5] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[16] -to fpga_top/sb_1__12_/chanx_right_out[5] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[27] -to fpga_top/sb_1__12_/chanx_right_out[5] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[10] -to fpga_top/sb_1__12_/chanx_right_out[5] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[24] -to fpga_top/sb_1__12_/chanx_right_out[5] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/right_top_grid_pin_1_[0] -to fpga_top/sb_1__12_/chanx_right_out[6] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/right_bottom_grid_pin_41_[0] -to fpga_top/sb_1__12_/chanx_right_out[6] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[4] -to fpga_top/sb_1__12_/chanx_right_out[6] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[15] -to fpga_top/sb_1__12_/chanx_right_out[6] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[26] -to fpga_top/sb_1__12_/chanx_right_out[6] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[11] -to fpga_top/sb_1__12_/chanx_right_out[6] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[26] -to fpga_top/sb_1__12_/chanx_right_out[6] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/right_bottom_grid_pin_36_[0] -to fpga_top/sb_1__12_/chanx_right_out[10] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/right_bottom_grid_pin_42_[0] -to fpga_top/sb_1__12_/chanx_right_out[10] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[3] -to fpga_top/sb_1__12_/chanx_right_out[10] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[14] -to fpga_top/sb_1__12_/chanx_right_out[10] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[25] -to fpga_top/sb_1__12_/chanx_right_out[10] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[12] -to fpga_top/sb_1__12_/chanx_right_out[10] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[27] -to fpga_top/sb_1__12_/chanx_right_out[10] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/right_bottom_grid_pin_37_[0] -to fpga_top/sb_1__12_/chanx_right_out[14] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/right_bottom_grid_pin_43_[0] -to fpga_top/sb_1__12_/chanx_right_out[14] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[2] -to fpga_top/sb_1__12_/chanx_right_out[14] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[13] -to fpga_top/sb_1__12_/chanx_right_out[14] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[24] -to fpga_top/sb_1__12_/chanx_right_out[14] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[14] -to fpga_top/sb_1__12_/chanx_right_out[14] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[28] -to fpga_top/sb_1__12_/chanx_right_out[14] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/right_bottom_grid_pin_38_[0] -to fpga_top/sb_1__12_/chanx_right_out[18] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[1] -to fpga_top/sb_1__12_/chanx_right_out[18] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[12] -to fpga_top/sb_1__12_/chanx_right_out[18] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[23] -to fpga_top/sb_1__12_/chanx_right_out[18] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[15] -to fpga_top/sb_1__12_/chanx_right_out[18] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/right_bottom_grid_pin_39_[0] -to fpga_top/sb_1__12_/chanx_right_out[22] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[0] -to fpga_top/sb_1__12_/chanx_right_out[22] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[11] -to fpga_top/sb_1__12_/chanx_right_out[22] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[22] -to fpga_top/sb_1__12_/chanx_right_out[22] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[16] -to fpga_top/sb_1__12_/chanx_right_out[22] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/right_bottom_grid_pin_40_[0] -to fpga_top/sb_1__12_/chanx_right_out[26] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[10] -to fpga_top/sb_1__12_/chanx_right_out[26] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[21] -to fpga_top/sb_1__12_/chanx_right_out[26] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[18] -to fpga_top/sb_1__12_/chanx_right_out[26] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[3] -to fpga_top/sb_1__12_/chany_bottom_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/bottom_left_grid_pin_44_[0] -to fpga_top/sb_1__12_/chany_bottom_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/bottom_left_grid_pin_47_[0] -to fpga_top/sb_1__12_/chany_bottom_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/bottom_left_grid_pin_50_[0] -to fpga_top/sb_1__12_/chany_bottom_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[1] -to fpga_top/sb_1__12_/chany_bottom_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[3] -to fpga_top/sb_1__12_/chany_bottom_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[6] -to fpga_top/sb_1__12_/chany_bottom_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/bottom_left_grid_pin_45_[0] -to fpga_top/sb_1__12_/chany_bottom_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/bottom_left_grid_pin_48_[0] -to fpga_top/sb_1__12_/chany_bottom_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/bottom_left_grid_pin_51_[0] -to fpga_top/sb_1__12_/chany_bottom_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[2] -to fpga_top/sb_1__12_/chany_bottom_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[6] -to fpga_top/sb_1__12_/chany_bottom_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[7] -to fpga_top/sb_1__12_/chany_bottom_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/bottom_left_grid_pin_46_[0] -to fpga_top/sb_1__12_/chany_bottom_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/bottom_left_grid_pin_49_[0] -to fpga_top/sb_1__12_/chany_bottom_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[4] -to fpga_top/sb_1__12_/chany_bottom_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[7] -to fpga_top/sb_1__12_/chany_bottom_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[8] -to fpga_top/sb_1__12_/chany_bottom_out[3] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/bottom_left_grid_pin_44_[0] -to fpga_top/sb_1__12_/chany_bottom_out[3] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/bottom_left_grid_pin_47_[0] -to fpga_top/sb_1__12_/chany_bottom_out[3] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/bottom_left_grid_pin_50_[0] -to fpga_top/sb_1__12_/chany_bottom_out[3] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[5] -to fpga_top/sb_1__12_/chany_bottom_out[3] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[8] -to fpga_top/sb_1__12_/chany_bottom_out[3] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[10] -to fpga_top/sb_1__12_/chany_bottom_out[4] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/bottom_left_grid_pin_45_[0] -to fpga_top/sb_1__12_/chany_bottom_out[4] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/bottom_left_grid_pin_48_[0] -to fpga_top/sb_1__12_/chany_bottom_out[4] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/bottom_left_grid_pin_51_[0] -to fpga_top/sb_1__12_/chany_bottom_out[4] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[9] -to fpga_top/sb_1__12_/chany_bottom_out[4] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[10] -to fpga_top/sb_1__12_/chany_bottom_out[4] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[11] -to fpga_top/sb_1__12_/chany_bottom_out[5] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/bottom_left_grid_pin_46_[0] -to fpga_top/sb_1__12_/chany_bottom_out[5] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/bottom_left_grid_pin_49_[0] -to fpga_top/sb_1__12_/chany_bottom_out[5] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[11] -to fpga_top/sb_1__12_/chany_bottom_out[5] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[13] -to fpga_top/sb_1__12_/chany_bottom_out[5] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[12] -to fpga_top/sb_1__12_/chany_bottom_out[6] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/bottom_left_grid_pin_44_[0] -to fpga_top/sb_1__12_/chany_bottom_out[6] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[12] -to fpga_top/sb_1__12_/chany_bottom_out[6] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[17] -to fpga_top/sb_1__12_/chany_bottom_out[6] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[14] -to fpga_top/sb_1__12_/chany_bottom_out[7] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/bottom_left_grid_pin_45_[0] -to fpga_top/sb_1__12_/chany_bottom_out[7] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[14] -to fpga_top/sb_1__12_/chany_bottom_out[7] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[21] -to fpga_top/sb_1__12_/chany_bottom_out[7] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[15] -to fpga_top/sb_1__12_/chany_bottom_out[8] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/bottom_left_grid_pin_46_[0] -to fpga_top/sb_1__12_/chany_bottom_out[8] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[15] -to fpga_top/sb_1__12_/chany_bottom_out[8] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[25] -to fpga_top/sb_1__12_/chany_bottom_out[8] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[16] -to fpga_top/sb_1__12_/chany_bottom_out[9] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/bottom_left_grid_pin_47_[0] -to fpga_top/sb_1__12_/chany_bottom_out[9] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[16] -to fpga_top/sb_1__12_/chany_bottom_out[9] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[29] -to fpga_top/sb_1__12_/chany_bottom_out[9] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[18] -to fpga_top/sb_1__12_/chany_bottom_out[10] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/bottom_left_grid_pin_48_[0] -to fpga_top/sb_1__12_/chany_bottom_out[10] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[18] -to fpga_top/sb_1__12_/chany_bottom_out[10] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[19] -to fpga_top/sb_1__12_/chany_bottom_out[11] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/bottom_left_grid_pin_49_[0] -to fpga_top/sb_1__12_/chany_bottom_out[11] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[19] -to fpga_top/sb_1__12_/chany_bottom_out[11] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[20] -to fpga_top/sb_1__12_/chany_bottom_out[12] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/bottom_left_grid_pin_50_[0] -to fpga_top/sb_1__12_/chany_bottom_out[12] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[20] -to fpga_top/sb_1__12_/chany_bottom_out[12] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[22] -to fpga_top/sb_1__12_/chany_bottom_out[13] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/bottom_left_grid_pin_51_[0] -to fpga_top/sb_1__12_/chany_bottom_out[13] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[22] -to fpga_top/sb_1__12_/chany_bottom_out[13] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[23] -to fpga_top/sb_1__12_/chany_bottom_out[14] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[23] -to fpga_top/sb_1__12_/chany_bottom_out[14] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[24] -to fpga_top/sb_1__12_/chany_bottom_out[15] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[24] -to fpga_top/sb_1__12_/chany_bottom_out[15] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[26] -to fpga_top/sb_1__12_/chany_bottom_out[16] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[26] -to fpga_top/sb_1__12_/chany_bottom_out[16] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[27] -to fpga_top/sb_1__12_/chany_bottom_out[17] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[27] -to fpga_top/sb_1__12_/chany_bottom_out[17] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[28] -to fpga_top/sb_1__12_/chany_bottom_out[18] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[29] -to fpga_top/sb_1__12_/chany_bottom_out[18] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/bottom_left_grid_pin_44_[0] -to fpga_top/sb_1__12_/chany_bottom_out[18] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[28] -to fpga_top/sb_1__12_/chany_bottom_out[18] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[25] -to fpga_top/sb_1__12_/chany_bottom_out[19] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/bottom_left_grid_pin_45_[0] -to fpga_top/sb_1__12_/chany_bottom_out[19] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[21] -to fpga_top/sb_1__12_/chany_bottom_out[20] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/bottom_left_grid_pin_46_[0] -to fpga_top/sb_1__12_/chany_bottom_out[20] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[17] -to fpga_top/sb_1__12_/chany_bottom_out[21] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/bottom_left_grid_pin_47_[0] -to fpga_top/sb_1__12_/chany_bottom_out[21] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[13] -to fpga_top/sb_1__12_/chany_bottom_out[22] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/bottom_left_grid_pin_48_[0] -to fpga_top/sb_1__12_/chany_bottom_out[22] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[9] -to fpga_top/sb_1__12_/chany_bottom_out[23] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/bottom_left_grid_pin_49_[0] -to fpga_top/sb_1__12_/chany_bottom_out[23] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[5] -to fpga_top/sb_1__12_/chany_bottom_out[24] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/bottom_left_grid_pin_50_[0] -to fpga_top/sb_1__12_/chany_bottom_out[24] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[4] -to fpga_top/sb_1__12_/chany_bottom_out[25] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/bottom_left_grid_pin_51_[0] -to fpga_top/sb_1__12_/chany_bottom_out[25] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[2] -to fpga_top/sb_1__12_/chany_bottom_out[26] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[1] -to fpga_top/sb_1__12_/chany_bottom_out[27] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[0] -to fpga_top/sb_1__12_/chany_bottom_out[28] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[0] -to fpga_top/sb_1__12_/chany_bottom_out[29] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[3] -to fpga_top/sb_1__12_/chanx_left_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[19] -to fpga_top/sb_1__12_/chanx_left_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[10] -to fpga_top/sb_1__12_/chanx_left_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[21] -to fpga_top/sb_1__12_/chanx_left_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/left_top_grid_pin_1_[0] -to fpga_top/sb_1__12_/chanx_left_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/left_bottom_grid_pin_38_[0] -to fpga_top/sb_1__12_/chanx_left_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/left_bottom_grid_pin_41_[0] -to fpga_top/sb_1__12_/chanx_left_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[6] -to fpga_top/sb_1__12_/chanx_left_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[20] -to fpga_top/sb_1__12_/chanx_left_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[0] -to fpga_top/sb_1__12_/chanx_left_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[11] -to fpga_top/sb_1__12_/chanx_left_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[22] -to fpga_top/sb_1__12_/chanx_left_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/left_bottom_grid_pin_36_[0] -to fpga_top/sb_1__12_/chanx_left_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/left_bottom_grid_pin_39_[0] -to fpga_top/sb_1__12_/chanx_left_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/left_bottom_grid_pin_42_[0] -to fpga_top/sb_1__12_/chanx_left_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[7] -to fpga_top/sb_1__12_/chanx_left_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[22] -to fpga_top/sb_1__12_/chanx_left_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[1] -to fpga_top/sb_1__12_/chanx_left_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[12] -to fpga_top/sb_1__12_/chanx_left_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[23] -to fpga_top/sb_1__12_/chanx_left_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/left_bottom_grid_pin_37_[0] -to fpga_top/sb_1__12_/chanx_left_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/left_bottom_grid_pin_40_[0] -to fpga_top/sb_1__12_/chanx_left_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/left_bottom_grid_pin_43_[0] -to fpga_top/sb_1__12_/chanx_left_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[8] -to fpga_top/sb_1__12_/chanx_left_out[3] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[23] -to fpga_top/sb_1__12_/chanx_left_out[3] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[2] -to fpga_top/sb_1__12_/chanx_left_out[3] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[13] -to fpga_top/sb_1__12_/chanx_left_out[3] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[24] -to fpga_top/sb_1__12_/chanx_left_out[3] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/left_top_grid_pin_1_[0] -to fpga_top/sb_1__12_/chanx_left_out[3] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/left_bottom_grid_pin_37_[0] -to fpga_top/sb_1__12_/chanx_left_out[3] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/left_bottom_grid_pin_39_[0] -to fpga_top/sb_1__12_/chanx_left_out[3] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/left_bottom_grid_pin_41_[0] -to fpga_top/sb_1__12_/chanx_left_out[3] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/left_bottom_grid_pin_43_[0] -to fpga_top/sb_1__12_/chanx_left_out[3] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[10] -to fpga_top/sb_1__12_/chanx_left_out[5] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[24] -to fpga_top/sb_1__12_/chanx_left_out[5] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[3] -to fpga_top/sb_1__12_/chanx_left_out[5] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[14] -to fpga_top/sb_1__12_/chanx_left_out[5] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[25] -to fpga_top/sb_1__12_/chanx_left_out[5] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/left_bottom_grid_pin_36_[0] -to fpga_top/sb_1__12_/chanx_left_out[5] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/left_bottom_grid_pin_38_[0] -to fpga_top/sb_1__12_/chanx_left_out[5] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/left_bottom_grid_pin_40_[0] -to fpga_top/sb_1__12_/chanx_left_out[5] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/left_bottom_grid_pin_42_[0] -to fpga_top/sb_1__12_/chanx_left_out[5] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[11] -to fpga_top/sb_1__12_/chanx_left_out[6] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[26] -to fpga_top/sb_1__12_/chanx_left_out[6] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[4] -to fpga_top/sb_1__12_/chanx_left_out[6] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[15] -to fpga_top/sb_1__12_/chanx_left_out[6] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[26] -to fpga_top/sb_1__12_/chanx_left_out[6] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/left_top_grid_pin_1_[0] -to fpga_top/sb_1__12_/chanx_left_out[6] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/left_bottom_grid_pin_41_[0] -to fpga_top/sb_1__12_/chanx_left_out[6] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[12] -to fpga_top/sb_1__12_/chanx_left_out[10] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[27] -to fpga_top/sb_1__12_/chanx_left_out[10] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[5] -to fpga_top/sb_1__12_/chanx_left_out[10] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[16] -to fpga_top/sb_1__12_/chanx_left_out[10] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[27] -to fpga_top/sb_1__12_/chanx_left_out[10] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/left_bottom_grid_pin_36_[0] -to fpga_top/sb_1__12_/chanx_left_out[10] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/left_bottom_grid_pin_42_[0] -to fpga_top/sb_1__12_/chanx_left_out[10] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[14] -to fpga_top/sb_1__12_/chanx_left_out[14] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[28] -to fpga_top/sb_1__12_/chanx_left_out[14] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[6] -to fpga_top/sb_1__12_/chanx_left_out[14] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[17] -to fpga_top/sb_1__12_/chanx_left_out[14] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[28] -to fpga_top/sb_1__12_/chanx_left_out[14] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/left_bottom_grid_pin_37_[0] -to fpga_top/sb_1__12_/chanx_left_out[14] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/left_bottom_grid_pin_43_[0] -to fpga_top/sb_1__12_/chanx_left_out[14] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[15] -to fpga_top/sb_1__12_/chanx_left_out[18] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[7] -to fpga_top/sb_1__12_/chanx_left_out[18] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[18] -to fpga_top/sb_1__12_/chanx_left_out[18] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[29] -to fpga_top/sb_1__12_/chanx_left_out[18] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/left_bottom_grid_pin_38_[0] -to fpga_top/sb_1__12_/chanx_left_out[18] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[16] -to fpga_top/sb_1__12_/chanx_left_out[22] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[8] -to fpga_top/sb_1__12_/chanx_left_out[22] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[19] -to fpga_top/sb_1__12_/chanx_left_out[22] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/left_bottom_grid_pin_39_[0] -to fpga_top/sb_1__12_/chanx_left_out[22] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[18] -to fpga_top/sb_1__12_/chanx_left_out[26] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[9] -to fpga_top/sb_1__12_/chanx_left_out[26] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[20] -to fpga_top/sb_1__12_/chanx_left_out[26] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__12_/left_bottom_grid_pin_40_[0] -to fpga_top/sb_1__12_/chanx_left_out[26] 6.020400151e-11 diff --git a/FPGA1212_SOFA_CHD_PNR/FPGA1212_SOFA_CHD_Verilog/SDC/sb_1__1_.sdc b/FPGA1212_SOFA_CHD_PNR/FPGA1212_SOFA_CHD_Verilog/SDC/sb_1__1_.sdc deleted file mode 100644 index fd335ab..0000000 --- a/FPGA1212_SOFA_CHD_PNR/FPGA1212_SOFA_CHD_Verilog/SDC/sb_1__1_.sdc +++ /dev/null @@ -1,426 +0,0 @@ -############################################# -# Synopsys Design Constraints (SDC) -# For FPGA fabric -# Description: Constrain timing of Switch Block sb_1__1_ for PnR -# Author: Xifan TANG -# Organization: University of Utah -# Date: Tue Dec 8 15:34:14 2020 -############################################# - -############################################# -# Define time unit -############################################# -set_units -time s - -set_max_delay -from fpga_core_uut/sb_1__1_/top_left_grid_pin_44_[0] -to fpga_top/sb_1__1_/chany_top_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/top_left_grid_pin_47_[0] -to fpga_top/sb_1__1_/chany_top_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/top_left_grid_pin_50_[0] -to fpga_top/sb_1__1_/chany_top_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[1] -to fpga_top/sb_1__1_/chany_top_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[3] -to fpga_top/sb_1__1_/chany_top_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[19] -to fpga_top/sb_1__1_/chany_top_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[3] -to fpga_top/sb_1__1_/chany_top_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[19] -to fpga_top/sb_1__1_/chany_top_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[0] -to fpga_top/sb_1__1_/chany_top_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[3] -to fpga_top/sb_1__1_/chany_top_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[19] -to fpga_top/sb_1__1_/chany_top_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/top_left_grid_pin_45_[0] -to fpga_top/sb_1__1_/chany_top_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/top_left_grid_pin_48_[0] -to fpga_top/sb_1__1_/chany_top_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/top_left_grid_pin_51_[0] -to fpga_top/sb_1__1_/chany_top_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[2] -to fpga_top/sb_1__1_/chany_top_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[6] -to fpga_top/sb_1__1_/chany_top_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[20] -to fpga_top/sb_1__1_/chany_top_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[6] -to fpga_top/sb_1__1_/chany_top_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[20] -to fpga_top/sb_1__1_/chany_top_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[6] -to fpga_top/sb_1__1_/chany_top_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[20] -to fpga_top/sb_1__1_/chany_top_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[29] -to fpga_top/sb_1__1_/chany_top_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/top_left_grid_pin_46_[0] -to fpga_top/sb_1__1_/chany_top_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/top_left_grid_pin_49_[0] -to fpga_top/sb_1__1_/chany_top_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[4] -to fpga_top/sb_1__1_/chany_top_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[7] -to fpga_top/sb_1__1_/chany_top_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[22] -to fpga_top/sb_1__1_/chany_top_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[7] -to fpga_top/sb_1__1_/chany_top_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[22] -to fpga_top/sb_1__1_/chany_top_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[7] -to fpga_top/sb_1__1_/chany_top_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[22] -to fpga_top/sb_1__1_/chany_top_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[25] -to fpga_top/sb_1__1_/chany_top_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/top_left_grid_pin_44_[0] -to fpga_top/sb_1__1_/chany_top_out[3] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/top_left_grid_pin_46_[0] -to fpga_top/sb_1__1_/chany_top_out[3] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/top_left_grid_pin_48_[0] -to fpga_top/sb_1__1_/chany_top_out[3] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/top_left_grid_pin_50_[0] -to fpga_top/sb_1__1_/chany_top_out[3] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[5] -to fpga_top/sb_1__1_/chany_top_out[3] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[8] -to fpga_top/sb_1__1_/chany_top_out[3] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[23] -to fpga_top/sb_1__1_/chany_top_out[3] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[8] -to fpga_top/sb_1__1_/chany_top_out[3] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[23] -to fpga_top/sb_1__1_/chany_top_out[3] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[8] -to fpga_top/sb_1__1_/chany_top_out[3] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[21] -to fpga_top/sb_1__1_/chany_top_out[3] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[23] -to fpga_top/sb_1__1_/chany_top_out[3] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/top_left_grid_pin_45_[0] -to fpga_top/sb_1__1_/chany_top_out[5] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/top_left_grid_pin_47_[0] -to fpga_top/sb_1__1_/chany_top_out[5] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/top_left_grid_pin_49_[0] -to fpga_top/sb_1__1_/chany_top_out[5] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/top_left_grid_pin_51_[0] -to fpga_top/sb_1__1_/chany_top_out[5] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[9] -to fpga_top/sb_1__1_/chany_top_out[5] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[10] -to fpga_top/sb_1__1_/chany_top_out[5] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[24] -to fpga_top/sb_1__1_/chany_top_out[5] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[10] -to fpga_top/sb_1__1_/chany_top_out[5] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[24] -to fpga_top/sb_1__1_/chany_top_out[5] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[10] -to fpga_top/sb_1__1_/chany_top_out[5] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[17] -to fpga_top/sb_1__1_/chany_top_out[5] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[24] -to fpga_top/sb_1__1_/chany_top_out[5] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/top_left_grid_pin_44_[0] -to fpga_top/sb_1__1_/chany_top_out[6] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/top_left_grid_pin_50_[0] -to fpga_top/sb_1__1_/chany_top_out[6] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[11] -to fpga_top/sb_1__1_/chany_top_out[6] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[13] -to fpga_top/sb_1__1_/chany_top_out[6] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[26] -to fpga_top/sb_1__1_/chany_top_out[6] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[11] -to fpga_top/sb_1__1_/chany_top_out[6] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[26] -to fpga_top/sb_1__1_/chany_top_out[6] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[11] -to fpga_top/sb_1__1_/chany_top_out[6] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[13] -to fpga_top/sb_1__1_/chany_top_out[6] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[26] -to fpga_top/sb_1__1_/chany_top_out[6] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/top_left_grid_pin_45_[0] -to fpga_top/sb_1__1_/chany_top_out[10] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/top_left_grid_pin_51_[0] -to fpga_top/sb_1__1_/chany_top_out[10] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[12] -to fpga_top/sb_1__1_/chany_top_out[10] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[17] -to fpga_top/sb_1__1_/chany_top_out[10] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[27] -to fpga_top/sb_1__1_/chany_top_out[10] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[12] -to fpga_top/sb_1__1_/chany_top_out[10] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[27] -to fpga_top/sb_1__1_/chany_top_out[10] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[9] -to fpga_top/sb_1__1_/chany_top_out[10] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[12] -to fpga_top/sb_1__1_/chany_top_out[10] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[27] -to fpga_top/sb_1__1_/chany_top_out[10] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/top_left_grid_pin_46_[0] -to fpga_top/sb_1__1_/chany_top_out[14] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[14] -to fpga_top/sb_1__1_/chany_top_out[14] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[21] -to fpga_top/sb_1__1_/chany_top_out[14] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[28] -to fpga_top/sb_1__1_/chany_top_out[14] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[14] -to fpga_top/sb_1__1_/chany_top_out[14] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[28] -to fpga_top/sb_1__1_/chany_top_out[14] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[5] -to fpga_top/sb_1__1_/chany_top_out[14] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[14] -to fpga_top/sb_1__1_/chany_top_out[14] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[28] -to fpga_top/sb_1__1_/chany_top_out[14] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/top_left_grid_pin_47_[0] -to fpga_top/sb_1__1_/chany_top_out[18] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[15] -to fpga_top/sb_1__1_/chany_top_out[18] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[25] -to fpga_top/sb_1__1_/chany_top_out[18] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[15] -to fpga_top/sb_1__1_/chany_top_out[18] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[4] -to fpga_top/sb_1__1_/chany_top_out[18] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[15] -to fpga_top/sb_1__1_/chany_top_out[18] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/top_left_grid_pin_48_[0] -to fpga_top/sb_1__1_/chany_top_out[22] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[16] -to fpga_top/sb_1__1_/chany_top_out[22] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[29] -to fpga_top/sb_1__1_/chany_top_out[22] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[16] -to fpga_top/sb_1__1_/chany_top_out[22] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[2] -to fpga_top/sb_1__1_/chany_top_out[22] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[16] -to fpga_top/sb_1__1_/chany_top_out[22] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/top_left_grid_pin_49_[0] -to fpga_top/sb_1__1_/chany_top_out[26] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[0] -to fpga_top/sb_1__1_/chany_top_out[26] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[18] -to fpga_top/sb_1__1_/chany_top_out[26] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[18] -to fpga_top/sb_1__1_/chany_top_out[26] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[1] -to fpga_top/sb_1__1_/chany_top_out[26] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[18] -to fpga_top/sb_1__1_/chany_top_out[26] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[3] -to fpga_top/sb_1__1_/chanx_right_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[19] -to fpga_top/sb_1__1_/chanx_right_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[29] -to fpga_top/sb_1__1_/chanx_right_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/right_bottom_grid_pin_36_[0] -to fpga_top/sb_1__1_/chanx_right_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/right_bottom_grid_pin_39_[0] -to fpga_top/sb_1__1_/chanx_right_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/right_bottom_grid_pin_42_[0] -to fpga_top/sb_1__1_/chanx_right_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[3] -to fpga_top/sb_1__1_/chanx_right_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[19] -to fpga_top/sb_1__1_/chanx_right_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[25] -to fpga_top/sb_1__1_/chanx_right_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[3] -to fpga_top/sb_1__1_/chanx_right_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[19] -to fpga_top/sb_1__1_/chanx_right_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[0] -to fpga_top/sb_1__1_/chanx_right_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[6] -to fpga_top/sb_1__1_/chanx_right_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[20] -to fpga_top/sb_1__1_/chanx_right_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/right_bottom_grid_pin_37_[0] -to fpga_top/sb_1__1_/chanx_right_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/right_bottom_grid_pin_40_[0] -to fpga_top/sb_1__1_/chanx_right_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/right_bottom_grid_pin_43_[0] -to fpga_top/sb_1__1_/chanx_right_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[6] -to fpga_top/sb_1__1_/chanx_right_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[20] -to fpga_top/sb_1__1_/chanx_right_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[21] -to fpga_top/sb_1__1_/chanx_right_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[6] -to fpga_top/sb_1__1_/chanx_right_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[20] -to fpga_top/sb_1__1_/chanx_right_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[1] -to fpga_top/sb_1__1_/chanx_right_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[7] -to fpga_top/sb_1__1_/chanx_right_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[22] -to fpga_top/sb_1__1_/chanx_right_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/right_bottom_grid_pin_38_[0] -to fpga_top/sb_1__1_/chanx_right_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/right_bottom_grid_pin_41_[0] -to fpga_top/sb_1__1_/chanx_right_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[7] -to fpga_top/sb_1__1_/chanx_right_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[17] -to fpga_top/sb_1__1_/chanx_right_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[22] -to fpga_top/sb_1__1_/chanx_right_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[7] -to fpga_top/sb_1__1_/chanx_right_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[22] -to fpga_top/sb_1__1_/chanx_right_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[2] -to fpga_top/sb_1__1_/chanx_right_out[3] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[8] -to fpga_top/sb_1__1_/chanx_right_out[3] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[23] -to fpga_top/sb_1__1_/chanx_right_out[3] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/right_bottom_grid_pin_36_[0] -to fpga_top/sb_1__1_/chanx_right_out[3] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/right_bottom_grid_pin_38_[0] -to fpga_top/sb_1__1_/chanx_right_out[3] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/right_bottom_grid_pin_40_[0] -to fpga_top/sb_1__1_/chanx_right_out[3] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/right_bottom_grid_pin_42_[0] -to fpga_top/sb_1__1_/chanx_right_out[3] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[8] -to fpga_top/sb_1__1_/chanx_right_out[3] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[13] -to fpga_top/sb_1__1_/chanx_right_out[3] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[23] -to fpga_top/sb_1__1_/chanx_right_out[3] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[8] -to fpga_top/sb_1__1_/chanx_right_out[3] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[23] -to fpga_top/sb_1__1_/chanx_right_out[3] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[4] -to fpga_top/sb_1__1_/chanx_right_out[5] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[10] -to fpga_top/sb_1__1_/chanx_right_out[5] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[24] -to fpga_top/sb_1__1_/chanx_right_out[5] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/right_bottom_grid_pin_37_[0] -to fpga_top/sb_1__1_/chanx_right_out[5] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/right_bottom_grid_pin_39_[0] -to fpga_top/sb_1__1_/chanx_right_out[5] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/right_bottom_grid_pin_41_[0] -to fpga_top/sb_1__1_/chanx_right_out[5] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/right_bottom_grid_pin_43_[0] -to fpga_top/sb_1__1_/chanx_right_out[5] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[9] -to fpga_top/sb_1__1_/chanx_right_out[5] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[10] -to fpga_top/sb_1__1_/chanx_right_out[5] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[24] -to fpga_top/sb_1__1_/chanx_right_out[5] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[10] -to fpga_top/sb_1__1_/chanx_right_out[5] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[24] -to fpga_top/sb_1__1_/chanx_right_out[5] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[5] -to fpga_top/sb_1__1_/chanx_right_out[6] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[11] -to fpga_top/sb_1__1_/chanx_right_out[6] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[26] -to fpga_top/sb_1__1_/chanx_right_out[6] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/right_bottom_grid_pin_36_[0] -to fpga_top/sb_1__1_/chanx_right_out[6] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/right_bottom_grid_pin_42_[0] -to fpga_top/sb_1__1_/chanx_right_out[6] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[5] -to fpga_top/sb_1__1_/chanx_right_out[6] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[11] -to fpga_top/sb_1__1_/chanx_right_out[6] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[26] -to fpga_top/sb_1__1_/chanx_right_out[6] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[11] -to fpga_top/sb_1__1_/chanx_right_out[6] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[26] -to fpga_top/sb_1__1_/chanx_right_out[6] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[9] -to fpga_top/sb_1__1_/chanx_right_out[10] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[12] -to fpga_top/sb_1__1_/chanx_right_out[10] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[27] -to fpga_top/sb_1__1_/chanx_right_out[10] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/right_bottom_grid_pin_37_[0] -to fpga_top/sb_1__1_/chanx_right_out[10] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/right_bottom_grid_pin_43_[0] -to fpga_top/sb_1__1_/chanx_right_out[10] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[4] -to fpga_top/sb_1__1_/chanx_right_out[10] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[12] -to fpga_top/sb_1__1_/chanx_right_out[10] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[27] -to fpga_top/sb_1__1_/chanx_right_out[10] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[12] -to fpga_top/sb_1__1_/chanx_right_out[10] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[27] -to fpga_top/sb_1__1_/chanx_right_out[10] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[13] -to fpga_top/sb_1__1_/chanx_right_out[14] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[14] -to fpga_top/sb_1__1_/chanx_right_out[14] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[28] -to fpga_top/sb_1__1_/chanx_right_out[14] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/right_bottom_grid_pin_38_[0] -to fpga_top/sb_1__1_/chanx_right_out[14] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[2] -to fpga_top/sb_1__1_/chanx_right_out[14] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[14] -to fpga_top/sb_1__1_/chanx_right_out[14] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[28] -to fpga_top/sb_1__1_/chanx_right_out[14] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[14] -to fpga_top/sb_1__1_/chanx_right_out[14] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[28] -to fpga_top/sb_1__1_/chanx_right_out[14] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[15] -to fpga_top/sb_1__1_/chanx_right_out[18] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[17] -to fpga_top/sb_1__1_/chanx_right_out[18] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/right_bottom_grid_pin_39_[0] -to fpga_top/sb_1__1_/chanx_right_out[18] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[1] -to fpga_top/sb_1__1_/chanx_right_out[18] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[15] -to fpga_top/sb_1__1_/chanx_right_out[18] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[15] -to fpga_top/sb_1__1_/chanx_right_out[18] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[16] -to fpga_top/sb_1__1_/chanx_right_out[22] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[21] -to fpga_top/sb_1__1_/chanx_right_out[22] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/right_bottom_grid_pin_40_[0] -to fpga_top/sb_1__1_/chanx_right_out[22] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[0] -to fpga_top/sb_1__1_/chanx_right_out[22] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[16] -to fpga_top/sb_1__1_/chanx_right_out[22] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[16] -to fpga_top/sb_1__1_/chanx_right_out[22] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[18] -to fpga_top/sb_1__1_/chanx_right_out[26] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[25] -to fpga_top/sb_1__1_/chanx_right_out[26] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/right_bottom_grid_pin_41_[0] -to fpga_top/sb_1__1_/chanx_right_out[26] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[18] -to fpga_top/sb_1__1_/chanx_right_out[26] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[29] -to fpga_top/sb_1__1_/chanx_right_out[26] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[18] -to fpga_top/sb_1__1_/chanx_right_out[26] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[3] -to fpga_top/sb_1__1_/chany_bottom_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[19] -to fpga_top/sb_1__1_/chany_bottom_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[3] -to fpga_top/sb_1__1_/chany_bottom_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[19] -to fpga_top/sb_1__1_/chany_bottom_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[25] -to fpga_top/sb_1__1_/chany_bottom_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/bottom_left_grid_pin_44_[0] -to fpga_top/sb_1__1_/chany_bottom_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/bottom_left_grid_pin_47_[0] -to fpga_top/sb_1__1_/chany_bottom_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/bottom_left_grid_pin_50_[0] -to fpga_top/sb_1__1_/chany_bottom_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[1] -to fpga_top/sb_1__1_/chany_bottom_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[3] -to fpga_top/sb_1__1_/chany_bottom_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[19] -to fpga_top/sb_1__1_/chany_bottom_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[6] -to fpga_top/sb_1__1_/chany_bottom_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[20] -to fpga_top/sb_1__1_/chany_bottom_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[6] -to fpga_top/sb_1__1_/chany_bottom_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[20] -to fpga_top/sb_1__1_/chany_bottom_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[21] -to fpga_top/sb_1__1_/chany_bottom_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/bottom_left_grid_pin_45_[0] -to fpga_top/sb_1__1_/chany_bottom_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/bottom_left_grid_pin_48_[0] -to fpga_top/sb_1__1_/chany_bottom_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/bottom_left_grid_pin_51_[0] -to fpga_top/sb_1__1_/chany_bottom_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[2] -to fpga_top/sb_1__1_/chany_bottom_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[6] -to fpga_top/sb_1__1_/chany_bottom_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[20] -to fpga_top/sb_1__1_/chany_bottom_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[7] -to fpga_top/sb_1__1_/chany_bottom_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[22] -to fpga_top/sb_1__1_/chany_bottom_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[7] -to fpga_top/sb_1__1_/chany_bottom_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[17] -to fpga_top/sb_1__1_/chany_bottom_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[22] -to fpga_top/sb_1__1_/chany_bottom_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/bottom_left_grid_pin_46_[0] -to fpga_top/sb_1__1_/chany_bottom_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/bottom_left_grid_pin_49_[0] -to fpga_top/sb_1__1_/chany_bottom_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[4] -to fpga_top/sb_1__1_/chany_bottom_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[7] -to fpga_top/sb_1__1_/chany_bottom_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[22] -to fpga_top/sb_1__1_/chany_bottom_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[8] -to fpga_top/sb_1__1_/chany_bottom_out[3] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[23] -to fpga_top/sb_1__1_/chany_bottom_out[3] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[8] -to fpga_top/sb_1__1_/chany_bottom_out[3] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[13] -to fpga_top/sb_1__1_/chany_bottom_out[3] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[23] -to fpga_top/sb_1__1_/chany_bottom_out[3] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/bottom_left_grid_pin_44_[0] -to fpga_top/sb_1__1_/chany_bottom_out[3] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/bottom_left_grid_pin_46_[0] -to fpga_top/sb_1__1_/chany_bottom_out[3] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/bottom_left_grid_pin_48_[0] -to fpga_top/sb_1__1_/chany_bottom_out[3] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/bottom_left_grid_pin_50_[0] -to fpga_top/sb_1__1_/chany_bottom_out[3] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[5] -to fpga_top/sb_1__1_/chany_bottom_out[3] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[8] -to fpga_top/sb_1__1_/chany_bottom_out[3] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[23] -to fpga_top/sb_1__1_/chany_bottom_out[3] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[10] -to fpga_top/sb_1__1_/chany_bottom_out[5] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[24] -to fpga_top/sb_1__1_/chany_bottom_out[5] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[9] -to fpga_top/sb_1__1_/chany_bottom_out[5] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[10] -to fpga_top/sb_1__1_/chany_bottom_out[5] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[24] -to fpga_top/sb_1__1_/chany_bottom_out[5] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/bottom_left_grid_pin_45_[0] -to fpga_top/sb_1__1_/chany_bottom_out[5] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/bottom_left_grid_pin_47_[0] -to fpga_top/sb_1__1_/chany_bottom_out[5] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/bottom_left_grid_pin_49_[0] -to fpga_top/sb_1__1_/chany_bottom_out[5] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/bottom_left_grid_pin_51_[0] -to fpga_top/sb_1__1_/chany_bottom_out[5] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[9] -to fpga_top/sb_1__1_/chany_bottom_out[5] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[10] -to fpga_top/sb_1__1_/chany_bottom_out[5] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[24] -to fpga_top/sb_1__1_/chany_bottom_out[5] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[11] -to fpga_top/sb_1__1_/chany_bottom_out[6] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[26] -to fpga_top/sb_1__1_/chany_bottom_out[6] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[5] -to fpga_top/sb_1__1_/chany_bottom_out[6] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[11] -to fpga_top/sb_1__1_/chany_bottom_out[6] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[26] -to fpga_top/sb_1__1_/chany_bottom_out[6] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/bottom_left_grid_pin_44_[0] -to fpga_top/sb_1__1_/chany_bottom_out[6] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/bottom_left_grid_pin_50_[0] -to fpga_top/sb_1__1_/chany_bottom_out[6] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[11] -to fpga_top/sb_1__1_/chany_bottom_out[6] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[13] -to fpga_top/sb_1__1_/chany_bottom_out[6] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[26] -to fpga_top/sb_1__1_/chany_bottom_out[6] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[12] -to fpga_top/sb_1__1_/chany_bottom_out[10] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[27] -to fpga_top/sb_1__1_/chany_bottom_out[10] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[4] -to fpga_top/sb_1__1_/chany_bottom_out[10] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[12] -to fpga_top/sb_1__1_/chany_bottom_out[10] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[27] -to fpga_top/sb_1__1_/chany_bottom_out[10] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/bottom_left_grid_pin_45_[0] -to fpga_top/sb_1__1_/chany_bottom_out[10] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/bottom_left_grid_pin_51_[0] -to fpga_top/sb_1__1_/chany_bottom_out[10] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[12] -to fpga_top/sb_1__1_/chany_bottom_out[10] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[17] -to fpga_top/sb_1__1_/chany_bottom_out[10] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[27] -to fpga_top/sb_1__1_/chany_bottom_out[10] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[14] -to fpga_top/sb_1__1_/chany_bottom_out[14] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[28] -to fpga_top/sb_1__1_/chany_bottom_out[14] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[2] -to fpga_top/sb_1__1_/chany_bottom_out[14] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[14] -to fpga_top/sb_1__1_/chany_bottom_out[14] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[28] -to fpga_top/sb_1__1_/chany_bottom_out[14] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/bottom_left_grid_pin_46_[0] -to fpga_top/sb_1__1_/chany_bottom_out[14] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[14] -to fpga_top/sb_1__1_/chany_bottom_out[14] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[21] -to fpga_top/sb_1__1_/chany_bottom_out[14] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[28] -to fpga_top/sb_1__1_/chany_bottom_out[14] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[15] -to fpga_top/sb_1__1_/chany_bottom_out[18] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[1] -to fpga_top/sb_1__1_/chany_bottom_out[18] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[15] -to fpga_top/sb_1__1_/chany_bottom_out[18] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/bottom_left_grid_pin_47_[0] -to fpga_top/sb_1__1_/chany_bottom_out[18] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[15] -to fpga_top/sb_1__1_/chany_bottom_out[18] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[25] -to fpga_top/sb_1__1_/chany_bottom_out[18] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[16] -to fpga_top/sb_1__1_/chany_bottom_out[22] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[0] -to fpga_top/sb_1__1_/chany_bottom_out[22] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[16] -to fpga_top/sb_1__1_/chany_bottom_out[22] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/bottom_left_grid_pin_48_[0] -to fpga_top/sb_1__1_/chany_bottom_out[22] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[16] -to fpga_top/sb_1__1_/chany_bottom_out[22] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[29] -to fpga_top/sb_1__1_/chany_bottom_out[22] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[18] -to fpga_top/sb_1__1_/chany_bottom_out[26] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[18] -to fpga_top/sb_1__1_/chany_bottom_out[26] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[29] -to fpga_top/sb_1__1_/chany_bottom_out[26] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/bottom_left_grid_pin_49_[0] -to fpga_top/sb_1__1_/chany_bottom_out[26] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[0] -to fpga_top/sb_1__1_/chany_bottom_out[26] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[18] -to fpga_top/sb_1__1_/chany_bottom_out[26] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[0] -to fpga_top/sb_1__1_/chanx_left_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[3] -to fpga_top/sb_1__1_/chanx_left_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[19] -to fpga_top/sb_1__1_/chanx_left_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[3] -to fpga_top/sb_1__1_/chanx_left_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[19] -to fpga_top/sb_1__1_/chanx_left_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[3] -to fpga_top/sb_1__1_/chanx_left_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[19] -to fpga_top/sb_1__1_/chanx_left_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[29] -to fpga_top/sb_1__1_/chanx_left_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/left_bottom_grid_pin_36_[0] -to fpga_top/sb_1__1_/chanx_left_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/left_bottom_grid_pin_39_[0] -to fpga_top/sb_1__1_/chanx_left_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/left_bottom_grid_pin_42_[0] -to fpga_top/sb_1__1_/chanx_left_out[0] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[6] -to fpga_top/sb_1__1_/chanx_left_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[20] -to fpga_top/sb_1__1_/chanx_left_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[29] -to fpga_top/sb_1__1_/chanx_left_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[6] -to fpga_top/sb_1__1_/chanx_left_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[20] -to fpga_top/sb_1__1_/chanx_left_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[0] -to fpga_top/sb_1__1_/chanx_left_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[6] -to fpga_top/sb_1__1_/chanx_left_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[20] -to fpga_top/sb_1__1_/chanx_left_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/left_bottom_grid_pin_37_[0] -to fpga_top/sb_1__1_/chanx_left_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/left_bottom_grid_pin_40_[0] -to fpga_top/sb_1__1_/chanx_left_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/left_bottom_grid_pin_43_[0] -to fpga_top/sb_1__1_/chanx_left_out[1] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[7] -to fpga_top/sb_1__1_/chanx_left_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[22] -to fpga_top/sb_1__1_/chanx_left_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[25] -to fpga_top/sb_1__1_/chanx_left_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[7] -to fpga_top/sb_1__1_/chanx_left_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[22] -to fpga_top/sb_1__1_/chanx_left_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[1] -to fpga_top/sb_1__1_/chanx_left_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[7] -to fpga_top/sb_1__1_/chanx_left_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[22] -to fpga_top/sb_1__1_/chanx_left_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/left_bottom_grid_pin_38_[0] -to fpga_top/sb_1__1_/chanx_left_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/left_bottom_grid_pin_41_[0] -to fpga_top/sb_1__1_/chanx_left_out[2] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[8] -to fpga_top/sb_1__1_/chanx_left_out[3] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[21] -to fpga_top/sb_1__1_/chanx_left_out[3] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[23] -to fpga_top/sb_1__1_/chanx_left_out[3] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[8] -to fpga_top/sb_1__1_/chanx_left_out[3] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[23] -to fpga_top/sb_1__1_/chanx_left_out[3] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[2] -to fpga_top/sb_1__1_/chanx_left_out[3] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[8] -to fpga_top/sb_1__1_/chanx_left_out[3] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[23] -to fpga_top/sb_1__1_/chanx_left_out[3] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/left_bottom_grid_pin_36_[0] -to fpga_top/sb_1__1_/chanx_left_out[3] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/left_bottom_grid_pin_38_[0] -to fpga_top/sb_1__1_/chanx_left_out[3] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/left_bottom_grid_pin_40_[0] -to fpga_top/sb_1__1_/chanx_left_out[3] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/left_bottom_grid_pin_42_[0] -to fpga_top/sb_1__1_/chanx_left_out[3] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[10] -to fpga_top/sb_1__1_/chanx_left_out[5] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[17] -to fpga_top/sb_1__1_/chanx_left_out[5] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[24] -to fpga_top/sb_1__1_/chanx_left_out[5] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[10] -to fpga_top/sb_1__1_/chanx_left_out[5] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[24] -to fpga_top/sb_1__1_/chanx_left_out[5] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[4] -to fpga_top/sb_1__1_/chanx_left_out[5] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[10] -to fpga_top/sb_1__1_/chanx_left_out[5] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[24] -to fpga_top/sb_1__1_/chanx_left_out[5] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/left_bottom_grid_pin_37_[0] -to fpga_top/sb_1__1_/chanx_left_out[5] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/left_bottom_grid_pin_39_[0] -to fpga_top/sb_1__1_/chanx_left_out[5] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/left_bottom_grid_pin_41_[0] -to fpga_top/sb_1__1_/chanx_left_out[5] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/left_bottom_grid_pin_43_[0] -to fpga_top/sb_1__1_/chanx_left_out[5] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[11] -to fpga_top/sb_1__1_/chanx_left_out[6] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[13] -to fpga_top/sb_1__1_/chanx_left_out[6] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[26] -to fpga_top/sb_1__1_/chanx_left_out[6] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[11] -to fpga_top/sb_1__1_/chanx_left_out[6] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[26] -to fpga_top/sb_1__1_/chanx_left_out[6] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[5] -to fpga_top/sb_1__1_/chanx_left_out[6] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[11] -to fpga_top/sb_1__1_/chanx_left_out[6] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[26] -to fpga_top/sb_1__1_/chanx_left_out[6] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/left_bottom_grid_pin_36_[0] -to fpga_top/sb_1__1_/chanx_left_out[6] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/left_bottom_grid_pin_42_[0] -to fpga_top/sb_1__1_/chanx_left_out[6] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[9] -to fpga_top/sb_1__1_/chanx_left_out[10] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[12] -to fpga_top/sb_1__1_/chanx_left_out[10] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[27] -to fpga_top/sb_1__1_/chanx_left_out[10] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[12] -to fpga_top/sb_1__1_/chanx_left_out[10] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[27] -to fpga_top/sb_1__1_/chanx_left_out[10] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[9] -to fpga_top/sb_1__1_/chanx_left_out[10] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[12] -to fpga_top/sb_1__1_/chanx_left_out[10] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[27] -to fpga_top/sb_1__1_/chanx_left_out[10] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/left_bottom_grid_pin_37_[0] -to fpga_top/sb_1__1_/chanx_left_out[10] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/left_bottom_grid_pin_43_[0] -to fpga_top/sb_1__1_/chanx_left_out[10] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[5] -to fpga_top/sb_1__1_/chanx_left_out[14] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[14] -to fpga_top/sb_1__1_/chanx_left_out[14] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[28] -to fpga_top/sb_1__1_/chanx_left_out[14] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[14] -to fpga_top/sb_1__1_/chanx_left_out[14] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[28] -to fpga_top/sb_1__1_/chanx_left_out[14] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[13] -to fpga_top/sb_1__1_/chanx_left_out[14] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[14] -to fpga_top/sb_1__1_/chanx_left_out[14] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[28] -to fpga_top/sb_1__1_/chanx_left_out[14] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/left_bottom_grid_pin_38_[0] -to fpga_top/sb_1__1_/chanx_left_out[14] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[4] -to fpga_top/sb_1__1_/chanx_left_out[18] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[15] -to fpga_top/sb_1__1_/chanx_left_out[18] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[15] -to fpga_top/sb_1__1_/chanx_left_out[18] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[15] -to fpga_top/sb_1__1_/chanx_left_out[18] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[17] -to fpga_top/sb_1__1_/chanx_left_out[18] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/left_bottom_grid_pin_39_[0] -to fpga_top/sb_1__1_/chanx_left_out[18] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[2] -to fpga_top/sb_1__1_/chanx_left_out[22] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[16] -to fpga_top/sb_1__1_/chanx_left_out[22] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[16] -to fpga_top/sb_1__1_/chanx_left_out[22] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[16] -to fpga_top/sb_1__1_/chanx_left_out[22] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[21] -to fpga_top/sb_1__1_/chanx_left_out[22] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/left_bottom_grid_pin_40_[0] -to fpga_top/sb_1__1_/chanx_left_out[22] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[1] -to fpga_top/sb_1__1_/chanx_left_out[26] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[18] -to fpga_top/sb_1__1_/chanx_left_out[26] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[18] -to fpga_top/sb_1__1_/chanx_left_out[26] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[18] -to fpga_top/sb_1__1_/chanx_left_out[26] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[25] -to fpga_top/sb_1__1_/chanx_left_out[26] 6.020400151e-11 -set_max_delay -from fpga_core_uut/sb_1__1_/left_bottom_grid_pin_41_[0] -to fpga_top/sb_1__1_/chanx_left_out[26] 6.020400151e-11 diff --git a/FPGA1212_SOFA_CHD_PNR/FPGA1212_SOFA_CHD_Verilog/SRC/sub_module/mux_primitives.v b/FPGA1212_SOFA_CHD_PNR/FPGA1212_SOFA_CHD_Verilog/SRC/sub_module/mux_primitives.v index a53cdb6..db2e273 100644 --- a/FPGA1212_SOFA_CHD_PNR/FPGA1212_SOFA_CHD_Verilog/SRC/sub_module/mux_primitives.v +++ b/FPGA1212_SOFA_CHD_PNR/FPGA1212_SOFA_CHD_Verilog/SRC/sub_module/mux_primitives.v @@ -36,6 +36,7 @@ output [0:0] out; // // +wire [0:0] out_inv; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0( .Q1(in[0]), .Q2(in[1]), @@ -43,7 +44,11 @@ output [0:0] out; .S0B(mem_inv[0]), .S1(mem[1]), .S1B(mem_inv[1]), - .Z(out[0]) + .Z(out_inv[0]) + ); + sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0( + .A(out_inv[0]), + .Y(out[0]) ); scs8hd_muxinv2_1 scs8hd_muxinv2_1_1( .Q1(in[2]), @@ -52,7 +57,11 @@ output [0:0] out; .S0B(mem_inv[2]), .S1(mem[3]), .S1B(mem_inv[3]), - .Z(out[0]) + .Z(out_inv[0]) + ); + sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1( + .A(out_inv[0]), + .Y(out[0]) ); endmodule // @@ -87,6 +96,7 @@ output [0:0] out; // // +wire [0:0] out_inv; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0( .Q1(in[0]), .Q2(in[1]), @@ -94,7 +104,11 @@ output [0:0] out; .S0B(mem_inv[0]), .S1(mem[1]), .S1B(mem_inv[1]), - .Z(out[0]) + .Z(out_inv[0]) + ); + sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0( + .A(out_inv[0]), + .Y(out[0]) ); endmodule // @@ -129,6 +143,7 @@ output [0:0] out; // // +wire [0:0] out_inv; scs8hd_muxinv3_1 scs8hd_muxinv3_1_0( .Q1(in[0]), .Q2(in[1]), @@ -139,7 +154,11 @@ output [0:0] out; .S1B(mem_inv[1]), .S2(mem[2]), .S2B(mem_inv[2]), - .Z(out[0]) + .Z(out_inv[0]) + ); + sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0( + .A(out_inv[0]), + .Y(out[0]) ); endmodule // @@ -174,6 +193,7 @@ output [0:0] out; // // +wire [0:0] out_inv; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0( .Q1(in[0]), .Q2(in[1]), @@ -181,7 +201,11 @@ output [0:0] out; .S0B(mem_inv[0]), .S1(mem[1]), .S1B(mem_inv[1]), - .Z(out[0]) + .Z(out_inv[0]) + ); + sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0( + .A(out_inv[0]), + .Y(out[0]) ); endmodule // @@ -216,6 +240,7 @@ output [0:0] out; // // +wire [0:0] out_inv; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0( .Q1(in[0]), .Q2(in[1]), @@ -223,7 +248,11 @@ output [0:0] out; .S0B(mem_inv[0]), .S1(mem[1]), .S1B(mem_inv[1]), - .Z(out[0]) + .Z(out_inv[0]) + ); + sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0( + .A(out_inv[0]), + .Y(out[0]) ); scs8hd_muxinv2_1 scs8hd_muxinv2_1_1( .Q1(in[2]), @@ -232,7 +261,11 @@ output [0:0] out; .S0B(mem_inv[2]), .S1(mem[3]), .S1B(mem_inv[3]), - .Z(out[0]) + .Z(out_inv[0]) + ); + sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1( + .A(out_inv[0]), + .Y(out[0]) ); endmodule // @@ -267,6 +300,7 @@ output [0:0] out; // // +wire [0:0] out_inv; sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0( .A1(in[0]), .A0(in[1]), diff --git a/FPGA1212_SOFA_CHD_PNR/FPGA1212_SOFA_CHD_Verilog/TESTBENCH/top/fabric_bitstream.xml b/FPGA1212_SOFA_CHD_PNR/FPGA1212_SOFA_CHD_Verilog/TESTBENCH/top/fabric_bitstream.xml index 7adedbe..1d5a066 100644 --- a/FPGA1212_SOFA_CHD_PNR/FPGA1212_SOFA_CHD_Verilog/TESTBENCH/top/fabric_bitstream.xml +++ b/FPGA1212_SOFA_CHD_PNR/FPGA1212_SOFA_CHD_Verilog/TESTBENCH/top/fabric_bitstream.xml @@ -2,7 +2,7 @@ - Fabric bitstream - Author: Xifan TANG - Organization: University of Utah - - Date: Tue Dec 8 15:34:09 2020 + - Date: Sun Dec 13 16:23:01 2020 --> diff --git a/FPGA1212_SOFA_CHD_PNR/FPGA1212_SOFA_CHD_Verilog/TESTBENCH/top/fabric_indepenent_bitstream.xml b/FPGA1212_SOFA_CHD_PNR/FPGA1212_SOFA_CHD_Verilog/TESTBENCH/top/fabric_indepenent_bitstream.xml index 74ceb13..c012b6a 100644 --- a/FPGA1212_SOFA_CHD_PNR/FPGA1212_SOFA_CHD_Verilog/TESTBENCH/top/fabric_indepenent_bitstream.xml +++ b/FPGA1212_SOFA_CHD_PNR/FPGA1212_SOFA_CHD_Verilog/TESTBENCH/top/fabric_indepenent_bitstream.xml @@ -2,7 +2,7 @@ - Architecture independent bitstream - Author: Xifan TANG - Organization: University of Utah - - Date: Tue Dec 8 15:34:08 2020 + - Date: Sun Dec 13 16:23:00 2020 --> diff --git a/FPGA1212_SOFA_CHD_PNR/FPGA1212_SOFA_CHD_Verilog/openfpgashell.log b/FPGA1212_SOFA_CHD_PNR/FPGA1212_SOFA_CHD_Verilog/openfpgashell.log index ba36bdb..05232e2 100644 --- a/FPGA1212_SOFA_CHD_PNR/FPGA1212_SOFA_CHD_Verilog/openfpgashell.log +++ b/FPGA1212_SOFA_CHD_PNR/FPGA1212_SOFA_CHD_Verilog/openfpgashell.log @@ -281,12 +281,12 @@ Device Utilization: 0.02 (target 1.00) Netlist conversion complete. -# Packing took 0.03 seconds (max_rss 10.7 MiB, delta_rss +0.7 MiB) +# Packing took 0.01 seconds (max_rss 10.7 MiB, delta_rss +0.7 MiB) # Load Packing Begin loading packed FPGA netlist file. Netlist generated from file 'top.net'. Detected 0 constant generators (to see names run with higher pack verbosity) -Finished loading packed FPGA netlist file (took 0.02 seconds). +Finished loading packed FPGA netlist file (took 0 seconds). Warning 65: Treated 0 constant nets as global which will not be routed (to see net names increase packer verbosity). # Load Packing took 0.01 seconds (max_rss 10.7 MiB, delta_rss +0.1 MiB) Warning 66: Netlist contains 0 global net to non-global architecture pin connections @@ -374,10 +374,10 @@ Warning 105: in check_rr_node: RR node: 1645 type: OPIN location: (12,1) pin: 53 Warning 106: in check_rr_node: RR node: 1646 type: OPIN location: (12,1) pin: 54 pin_name: clb.cout[0] capacity: 1 has no out-going edges. Warning 107: in check_rr_graph: fringe node 15912 CHANX at (1,1) has no fanin. This is possible on a fringe node based on low Fc_out, N, and certain lengths. -## Build tileable routing resource graph took 0.19 seconds (max_rss 20.1 MiB, delta_rss +9.3 MiB) +## Build tileable routing resource graph took 0.29 seconds (max_rss 20.1 MiB, delta_rss +9.3 MiB) RR Graph Nodes: 23404 RR Graph Edges: 121880 -# Create Device took 0.19 seconds (max_rss 20.1 MiB, delta_rss +9.3 MiB) +# Create Device took 0.29 seconds (max_rss 20.1 MiB, delta_rss +9.3 MiB) # Placement ## Computing placement delta delay look-up @@ -418,12 +418,12 @@ Warning 140: in check_rr_node: RR node: 13066 type: OPIN location: (11,1) pin: 5 Warning 141: in check_rr_node: RR node: 14352 type: OPIN location: (12,1) pin: 52 pin_name: clb.reg_out[0] capacity: 1 has no out-going edges. Warning 142: in check_rr_node: RR node: 14353 type: OPIN location: (12,1) pin: 53 pin_name: clb.sc_out[0] capacity: 1 has no out-going edges. Warning 143: in check_rr_node: RR node: 14354 type: OPIN location: (12,1) pin: 54 pin_name: clb.cout[0] capacity: 1 has no out-going edges. -### Build routing resource graph took 0.08 seconds (max_rss 20.8 MiB, delta_rss +0.5 MiB) +### Build routing resource graph took 0.10 seconds (max_rss 20.8 MiB, delta_rss +0.5 MiB) RR Graph Nodes: 23120 RR Graph Edges: 105560 ### Computing delta delays -### Computing delta delays took 0.03 seconds (max_rss 20.8 MiB, delta_rss +0.0 MiB) -## Computing placement delta delay look-up took 0.11 seconds (max_rss 20.8 MiB, delta_rss +0.5 MiB) +### Computing delta delays took 0.04 seconds (max_rss 20.8 MiB, delta_rss +0.0 MiB) +## Computing placement delta delay look-up took 0.15 seconds (max_rss 20.8 MiB, delta_rss +0.5 MiB) There are 3 point to point connections in this circuit. @@ -526,7 +526,7 @@ Placement total # of swap attempts: 232 Swaps aborted : 0 ( 0.0 %) Aborted Move Reasons: -# Placement took 0.11 seconds (max_rss 21.2 MiB, delta_rss +1.1 MiB) +# Placement took 0.15 seconds (max_rss 21.2 MiB, delta_rss +1.1 MiB) # Routing ## Build tileable routing resource graph @@ -570,7 +570,7 @@ Warning 178: in check_rr_node: RR node: 1645 type: OPIN location: (12,1) pin: 53 Warning 179: in check_rr_node: RR node: 1646 type: OPIN location: (12,1) pin: 54 pin_name: clb.cout[0] capacity: 1 has no out-going edges. Warning 180: in check_rr_graph: fringe node 15912 CHANX at (1,1) has no fanin. This is possible on a fringe node based on low Fc_out, N, and certain lengths. -## Build tileable routing resource graph took 0.14 seconds (max_rss 21.5 MiB, delta_rss +0.3 MiB) +## Build tileable routing resource graph took 0.19 seconds (max_rss 21.5 MiB, delta_rss +0.3 MiB) RR Graph Nodes: 23404 RR Graph Edges: 121880 Confirming router algorithm: TIMING_DRIVEN. @@ -583,7 +583,7 @@ Restoring best routing Critical path: 0.69331 ns Successfully routed after 1 routing iterations. Router Stats: total_nets_routed: 3 total_connections_routed: 3 total_heap_pushes: 124 total_heap_pops: 52 -# Routing took 0.15 seconds (max_rss 22.3 MiB, delta_rss +1.1 MiB) +# Routing took 0.20 seconds (max_rss 22.3 MiB, delta_rss +1.1 MiB) Checking to ensure routing is legal... Completed routing consistency check successfully. @@ -701,9 +701,9 @@ Setup slack histogram: [ -6.9e-10: -6.9e-10) 0 ( 0.0%) | [ -6.9e-10: -6.9e-10) 0 ( 0.0%) | -Timing analysis took 0.000266012 seconds (0.000240965 STA, 2.5047e-05 slack) (43 full updates: 41 setup, 0 hold, 2 combined). +Timing analysis took 0.000354561 seconds (0.000323356 STA, 3.1205e-05 slack) (43 full updates: 41 setup, 0 hold, 2 combined). VPR suceeded -The entire flow of VPR took 0.53 seconds (max_rss 22.5 MiB) +The entire flow of VPR took 0.72 seconds (max_rss 22.5 MiB) Command line to execute: read_openfpga_arch -f /research/ece/lnis/USERS/DARPA_ERI/GF14nm_chip_2019/ICC2_Methodology_Flow/GANESH/FROG_PnR/FPGA1212_SOFA_CHD_PNR/FPGA1212_SOFA_CHD_task/run001/vpr_arch/top/MIN_ROUTE_CHAN_WIDTH/arch/openfpga_arch.xml @@ -935,7 +935,7 @@ Annotating previous nodes for rr_node...Done with 15 nodes mapping [99%] Backannotated GSB[12][11] [100%] Backannotated GSB[12][12] Backannotated 169 General Switch Blocks (GSBs). -# Build General Switch Block(GSB) annotation on top of routing resource graph took 0.00 seconds (max_rss 22.8 MiB, delta_rss +0.0 MiB) +# Build General Switch Block(GSB) annotation on top of routing resource graph took 0.01 seconds (max_rss 22.8 MiB, delta_rss +0.0 MiB) # Sort incoming edges for each routing track output node of General Switch Block(GSB) [0%] Sorted edges for GSB[0][0] [1%] Sorted edges for GSB[0][1] @@ -1107,7 +1107,7 @@ Backannotated 169 General Switch Blocks (GSBs). [99%] Sorted edges for GSB[12][11] [100%] Sorted edges for GSB[12][12] Sorted edges for 169 General Switch Blocks (GSBs). -# Sort incoming edges for each routing track output node of General Switch Block(GSB) took 0.07 seconds (max_rss 23.3 MiB, delta_rss +0.5 MiB) +# Sort incoming edges for each routing track output node of General Switch Block(GSB) took 0.09 seconds (max_rss 23.3 MiB, delta_rss +0.5 MiB) # Build a library of physical multiplexers Built a multiplexer library of 16 physical multiplexers. Maximum multiplexer size is 16. @@ -1124,7 +1124,7 @@ Average net density: 0.42 Median net density: 0.00 Average net density after weighting: 0.42 Will apply 2 operating clock cycles to simulations -Link OpenFPGA architecture to VPR architecture took 0.08 seconds (max_rss 23.6 MiB, delta_rss +0.8 MiB) +Link OpenFPGA architecture to VPR architecture took 0.10 seconds (max_rss 23.6 MiB, delta_rss +0.8 MiB) Command line to execute: build_fabric --compress_routing --duplicate_grid_pin --load_fabric_key /research/ece/lnis/USERS/DARPA_ERI/Tapeout/May2020/OpenFPGA_for_Chip/openfpga_flow/tasks/FPGA1212_SOFA_CHD_task/arch/fabric_key.xml @@ -1138,7 +1138,7 @@ Confirm selected options when call command 'build_fabric': --verbose: off Identify unique General Switch Blocks (GSBs) Detected 9 unique general switch blocks from a total of 169 (compression rate=1777.78%) -Identify unique General Switch Blocks (GSBs) took 0.12 seconds (max_rss 23.6 MiB, delta_rss +0.0 MiB) +Identify unique General Switch Blocks (GSBs) took 0.16 seconds (max_rss 23.6 MiB, delta_rss +0.0 MiB) Read Fabric Key Read Fabric Key took 0.00 seconds (max_rss 23.7 MiB, delta_rss +0.1 MiB) @@ -1180,9 +1180,9 @@ Building physical tiles...Done ## Add module nets for inter-tile connections ## Add module nets for inter-tile connections took 0.00 seconds (max_rss 53.1 MiB, delta_rss +0.5 MiB) ## Add module nets for configuration buses -## Add module nets for configuration buses took 0.03 seconds (max_rss 55.1 MiB, delta_rss +1.5 MiB) -# Build FPGA fabric module took 0.19 seconds (max_rss 55.1 MiB, delta_rss +27.1 MiB) -Build fabric module graph took 0.21 seconds (max_rss 55.1 MiB, delta_rss +31.4 MiB) +## Add module nets for configuration buses took 0.01 seconds (max_rss 55.1 MiB, delta_rss +1.5 MiB) +# Build FPGA fabric module took 0.17 seconds (max_rss 55.1 MiB, delta_rss +27.1 MiB) +Build fabric module graph took 0.19 seconds (max_rss 55.1 MiB, delta_rss +31.4 MiB) Create I/O location mapping for top module Create I/O location mapping for top module took 0.00 seconds (max_rss 55.1 MiB, delta_rss +0.0 MiB) Create global port info for top module @@ -1217,10 +1217,10 @@ Generating bitstream for X-direction Connection blocks ...Done Generating bitstream for Y-direction Connection blocks ...Done Build fabric-independent bitstream for implementation 'top' - took 0.26 seconds (max_rss 60.4 MiB, delta_rss +5.2 MiB) + took 0.15 seconds (max_rss 60.4 MiB, delta_rss +5.2 MiB) Warning 185: Directory path is empty and nothing will be created. Write 81452 architecture independent bitstream into XML file 'fabric_indepenent_bitstream.xml' -Write 81452 architecture independent bitstream into XML file 'fabric_indepenent_bitstream.xml' took 0.73 seconds (max_rss 60.4 MiB, delta_rss +0.0 MiB) +Write 81452 architecture independent bitstream into XML file 'fabric_indepenent_bitstream.xml' took 0.60 seconds (max_rss 60.4 MiB, delta_rss +0.0 MiB) Command line to execute: build_fabric_bitstream @@ -1231,7 +1231,7 @@ Build fabric dependent bitstream Build fabric dependent bitstream - took 0.09 seconds (max_rss 65.5 MiB, delta_rss +5.2 MiB) + took 0.04 seconds (max_rss 65.5 MiB, delta_rss +5.2 MiB) Command line to execute: write_fabric_bitstream --format plain_text --file fabric_bitstream.bit @@ -1251,7 +1251,7 @@ Confirm selected options when call command 'write_fabric_bitstream': --verbose: off Warning 187: Directory path is empty and nothing will be created. Write 81452 fabric bitstream into xml file 'fabric_bitstream.xml' -Write 81452 fabric bitstream into xml file 'fabric_bitstream.xml' took 0.16 seconds (max_rss 65.5 MiB, delta_rss +0.0 MiB) +Write 81452 fabric bitstream into xml file 'fabric_bitstream.xml' took 0.14 seconds (max_rss 65.5 MiB, delta_rss +0.0 MiB) Command line to execute: write_fabric_verilog --file ./SRC --explicit_port_mapping --verbose @@ -1314,7 +1314,7 @@ Building physical tiles...Done Writing Verilog netlist for top-level module of FPGA fabric './SRC/fpga_top.v'...Done Written 92 Verilog modules in total Write Verilog netlists for FPGA fabric - took 0.64 seconds (max_rss 68.4 MiB, delta_rss +2.8 MiB) + took 0.45 seconds (max_rss 68.4 MiB, delta_rss +2.8 MiB) Command line to execute: write_verilog_testbench --file ./SRC --reference_benchmark_file_path top_output_verilog.v --print_top_testbench --print_preconfig_top_testbench --print_simulation_ini ./SimulationDeck/simulation_deck.ini --explicit_port_mapping @@ -1336,17 +1336,17 @@ Write Verilog testbenches for FPGA fabric Warning 189: Directory './SRC' already exists. Will overwrite contents # Write pre-configured FPGA top-level Verilog netlist for design 'top' -# Write pre-configured FPGA top-level Verilog netlist for design 'top' took 3.54 seconds (max_rss 68.4 MiB, delta_rss +0.0 MiB) +# Write pre-configured FPGA top-level Verilog netlist for design 'top' took 3.67 seconds (max_rss 68.4 MiB, delta_rss +0.0 MiB) # Write configuration-skip testbench for FPGA top-level Verilog netlist implemented by 'top' # Write configuration-skip testbench for FPGA top-level Verilog netlist implemented by 'top' took 0.00 seconds (max_rss 68.4 MiB, delta_rss +0.0 MiB) # Write autocheck testbench for FPGA top-level Verilog netlist for 'top' Will use 81453 configuration clock cycles to top testbench -# Write autocheck testbench for FPGA top-level Verilog netlist for 'top' took 0.21 seconds (max_rss 68.5 MiB, delta_rss +0.1 MiB) +# Write autocheck testbench for FPGA top-level Verilog netlist for 'top' took 0.23 seconds (max_rss 68.5 MiB, delta_rss +0.1 MiB) Succeed to create directory './SimulationDeck' # Write exchangeable file containing simulation information './SimulationDeck/simulation_deck.ini' # Write exchangeable file containing simulation information './SimulationDeck/simulation_deck.ini' took 0.00 seconds (max_rss 68.5 MiB, delta_rss +0.0 MiB) Write Verilog testbenches for FPGA fabric - took 3.77 seconds (max_rss 68.5 MiB, delta_rss +0.1 MiB) + took 3.93 seconds (max_rss 68.5 MiB, delta_rss +0.2 MiB) Command line to execute: write_pnr_sdc --file ./SDC @@ -1370,17 +1370,17 @@ Succeed to create directory './SDC' Write SDC for constraining clocks for P&R flow './SDC/global_ports.sdc' Write SDC for constraining clocks for P&R flow './SDC/global_ports.sdc' took 0.00 seconds (max_rss 68.5 MiB, delta_rss +0.0 MiB) Write SDC to disable configurable memory outputs for P&R flow './SDC/disable_configurable_memory_outputs.sdc' -Write SDC to disable configurable memory outputs for P&R flow './SDC/disable_configurable_memory_outputs.sdc' took 0.01 seconds (max_rss 68.6 MiB, delta_rss +0.1 MiB) +Write SDC to disable configurable memory outputs for P&R flow './SDC/disable_configurable_memory_outputs.sdc' took 0.01 seconds (max_rss 68.6 MiB, delta_rss +0.0 MiB) Write SDC to disable routing multiplexer outputs for P&R flow './SDC/disable_routing_multiplexer_outputs.sdc' -Write SDC to disable routing multiplexer outputs for P&R flow './SDC/disable_routing_multiplexer_outputs.sdc' took 0.07 seconds (max_rss 68.6 MiB, delta_rss +0.0 MiB) +Write SDC to disable routing multiplexer outputs for P&R flow './SDC/disable_routing_multiplexer_outputs.sdc' took 0.05 seconds (max_rss 68.6 MiB, delta_rss +0.0 MiB) Write SDC to disable switch block outputs for P&R flow './SDC/disable_sb_outputs.sdc' Write SDC to disable switch block outputs for P&R flow './SDC/disable_sb_outputs.sdc' took 0.00 seconds (max_rss 68.6 MiB, delta_rss +0.0 MiB) Write SDC for constrain Switch Block timing for P&R flow Write SDC for constrain Switch Block timing for P&R flow took 0.04 seconds (max_rss 68.6 MiB, delta_rss +0.0 MiB) Write SDC for constrain Connection Block timing for P&R flow -Write SDC for constrain Connection Block timing for P&R flow took 0.02 seconds (max_rss 68.6 MiB, delta_rss +0.0 MiB) +Write SDC for constrain Connection Block timing for P&R flow took 0.01 seconds (max_rss 68.6 MiB, delta_rss +0.0 MiB) Write SDC for constraining grid timing for P&R flow -Write SDC for constraining grid timing for P&R flow took 0.02 seconds (max_rss 68.6 MiB, delta_rss +0.0 MiB) +Write SDC for constraining grid timing for P&R flow took 0.01 seconds (max_rss 68.6 MiB, delta_rss +0.0 MiB) Command line to execute: write_sdc_disable_timing_configure_ports --file ./SDC/disable_configure_ports.sdc @@ -1390,7 +1390,7 @@ Confirm selected options when call command 'write_sdc_disable_timing_configure_p --verbose: off Warning 190: Directory './SDC' already exists. Will overwrite contents Write SDC to disable timing on configuration outputs of programmable cells for P&R flow './SDC/disable_configure_ports.sdc' -Write SDC to disable timing on configuration outputs of programmable cells for P&R flow './SDC/disable_configure_ports.sdc' took 0.10 seconds (max_rss 68.6 MiB, delta_rss +0.0 MiB) +Write SDC to disable timing on configuration outputs of programmable cells for P&R flow './SDC/disable_configure_ports.sdc' took 0.11 seconds (max_rss 68.6 MiB, delta_rss +0.0 MiB) Command line to execute: write_analysis_sdc --file ./SDC_analysis @@ -1401,7 +1401,7 @@ Confirm selected options when call command 'write_analysis_sdc': --time_unit: off Succeed to create directory './SDC_analysis' Generating SDC for Timing/Power analysis on the mapped FPGA './SDC_analysis/top_fpga_top_analysis.sdc' -Generating SDC for Timing/Power analysis on the mapped FPGA './SDC_analysis/top_fpga_top_analysis.sdc' took 0.97 seconds (max_rss 68.6 MiB, delta_rss +0.0 MiB) +Generating SDC for Timing/Power analysis on the mapped FPGA './SDC_analysis/top_fpga_top_analysis.sdc' took 1.01 seconds (max_rss 68.6 MiB, delta_rss +0.0 MiB) Command line to execute: exit @@ -1409,6 +1409,6 @@ Confirm selected options when call command 'exit': Finish execution with 0 errors -The entire OpenFPGA flow took 7.48 seconds +The entire OpenFPGA flow took 7.3 seconds Thank you for using OpenFPGA! diff --git a/FPGA1212_SOFA_CHD_PNR/README.md b/FPGA1212_SOFA_CHD_PNR/README.md new file mode 100644 index 0000000..87abac1 --- /dev/null +++ b/FPGA1212_SOFA_CHD_PNR/README.md @@ -0,0 +1,3 @@ +## FPGA1212_SOFA_CHD_PNR + +https://skywater-openfpga.readthedocs.io/en/latest/datasheet/qlsofa_hd/ diff --git a/FPGA1212_SOFA_CHD_PNR/Verification/ConfigChainTestFull_run/ccff_test.vcd b/FPGA1212_SOFA_CHD_PNR/Verification/ConfigChainTestFull_run/ccff_test.vcd new file mode 100644 index 0000000..a48f3ff --- /dev/null +++ b/FPGA1212_SOFA_CHD_PNR/Verification/ConfigChainTestFull_run/ccff_test.vcd @@ -0,0 +1,2668395 @@ +$date + Tue Dec 8 15:40:19 2020 +$end +$version + QuestaSim Version 2019.4 +$end +$timescale + 1ps +$end + +$scope module fpga_top $end +$var wire 1 ! io_in [37] $end +$var wire 1 " io_in [36] $end + +$scope module fpga_core_uut $end +$var wire 1 ! prog_clk [0] $end +$var wire 1 # Reset [0] $end +$var wire 1 $ pReset [0] $end + +$scope module sb_12__12_ $end +$var wire 1 % ccff_head [0] $end +$var wire 1 & ccff_tail [0] $end +$upscope $end +$var wire 1 % ccff_head [0] $end +$var wire 1 ' ccff_tail [0] $end + +$scope module sb_12__12_ $end +$var wire 1 ( pReset [0] $end +$var wire 1 ) chany_bottom_in [0] $end +$var wire 1 * chany_bottom_in [1] $end +$var wire 1 + chany_bottom_in [2] $end +$var wire 1 , chany_bottom_in [3] $end +$var wire 1 - chany_bottom_in [4] $end +$var wire 1 . chany_bottom_in [5] $end +$var wire 1 / chany_bottom_in [6] $end +$var wire 1 0 chany_bottom_in [7] $end +$var wire 1 1 chany_bottom_in [8] $end +$var wire 1 2 chany_bottom_in [9] $end +$var wire 1 3 chany_bottom_in [10] $end +$var wire 1 4 chany_bottom_in [11] $end +$var wire 1 5 chany_bottom_in [12] $end +$var wire 1 6 chany_bottom_in [13] $end +$var wire 1 7 chany_bottom_in [14] $end +$var wire 1 8 chany_bottom_in [15] $end +$var wire 1 9 chany_bottom_in [16] $end +$var wire 1 : chany_bottom_in [17] $end +$var wire 1 ; chany_bottom_in [18] $end +$var wire 1 < chany_bottom_in [19] $end +$var wire 1 = chany_bottom_in [20] $end +$var wire 1 > chany_bottom_in [21] $end +$var wire 1 ? chany_bottom_in [22] $end +$var wire 1 @ chany_bottom_in [23] $end +$var wire 1 A chany_bottom_in [24] $end +$var wire 1 B chany_bottom_in [25] $end +$var wire 1 C chany_bottom_in [26] $end +$var wire 1 D chany_bottom_in [27] $end +$var wire 1 E chany_bottom_in [28] $end +$var wire 1 F chany_bottom_in [29] $end +$var wire 1 G bottom_right_grid_pin_1_ [0] $end +$var wire 1 H bottom_left_grid_pin_44_ [0] $end +$var wire 1 I bottom_left_grid_pin_45_ [0] $end +$var wire 1 J bottom_left_grid_pin_46_ [0] $end +$var wire 1 K bottom_left_grid_pin_47_ [0] $end +$var wire 1 L bottom_left_grid_pin_48_ [0] $end +$var wire 1 M bottom_left_grid_pin_49_ [0] $end +$var wire 1 N bottom_left_grid_pin_50_ [0] $end +$var wire 1 O bottom_left_grid_pin_51_ [0] $end +$var wire 1 P chanx_left_in [0] $end +$var wire 1 Q chanx_left_in [1] $end +$var wire 1 R chanx_left_in [2] $end +$var wire 1 S chanx_left_in [3] $end +$var wire 1 T chanx_left_in [4] $end +$var wire 1 U chanx_left_in [5] $end +$var wire 1 V chanx_left_in [6] $end +$var wire 1 W chanx_left_in [7] $end +$var wire 1 X chanx_left_in [8] $end +$var wire 1 Y chanx_left_in [9] $end +$var wire 1 Z chanx_left_in [10] $end +$var wire 1 [ chanx_left_in [11] $end +$var wire 1 \ chanx_left_in [12] $end +$var wire 1 ] chanx_left_in [13] $end +$var wire 1 ^ chanx_left_in [14] $end +$var wire 1 _ chanx_left_in [15] $end +$var wire 1 ` chanx_left_in [16] $end +$var wire 1 a chanx_left_in [17] $end +$var wire 1 b chanx_left_in [18] $end +$var wire 1 c chanx_left_in [19] $end +$var wire 1 d chanx_left_in [20] $end +$var wire 1 e chanx_left_in [21] $end +$var wire 1 f chanx_left_in [22] $end +$var wire 1 g chanx_left_in [23] $end +$var wire 1 h chanx_left_in [24] $end +$var wire 1 i chanx_left_in [25] $end +$var wire 1 j chanx_left_in [26] $end +$var wire 1 k chanx_left_in [27] $end +$var wire 1 l chanx_left_in [28] $end +$var wire 1 m chanx_left_in [29] $end +$var wire 1 n left_top_grid_pin_1_ [0] $end +$var wire 1 o left_bottom_grid_pin_36_ [0] $end +$var wire 1 p left_bottom_grid_pin_37_ [0] $end +$var wire 1 q left_bottom_grid_pin_38_ [0] $end +$var wire 1 r left_bottom_grid_pin_39_ [0] $end +$var wire 1 s left_bottom_grid_pin_40_ [0] $end +$var wire 1 t left_bottom_grid_pin_41_ [0] $end +$var wire 1 u left_bottom_grid_pin_42_ [0] $end +$var wire 1 v left_bottom_grid_pin_43_ [0] $end +$var wire 1 % ccff_head [0] $end +$var wire 1 w chany_bottom_out [0] $end +$var wire 1 x chany_bottom_out [1] $end +$var wire 1 y chany_bottom_out [2] $end +$var wire 1 z chany_bottom_out [3] $end +$var wire 1 { chany_bottom_out [4] $end +$var wire 1 | chany_bottom_out [5] $end +$var wire 1 } chany_bottom_out [6] $end +$var wire 1 ~ chany_bottom_out [7] $end +$var wire 1 !! chany_bottom_out [8] $end +$var wire 1 "! chany_bottom_out [9] $end +$var wire 1 #! chany_bottom_out [10] $end +$var wire 1 $! chany_bottom_out [11] $end +$var wire 1 %! chany_bottom_out [12] $end +$var wire 1 &! chany_bottom_out [13] $end +$var wire 1 '! chany_bottom_out [14] $end +$var wire 1 (! chany_bottom_out [15] $end +$var wire 1 )! chany_bottom_out [16] $end +$var wire 1 *! chany_bottom_out [17] $end +$var wire 1 +! chany_bottom_out [18] $end +$var wire 1 ,! chany_bottom_out [19] $end +$var wire 1 -! chany_bottom_out [20] $end +$var wire 1 .! chany_bottom_out [21] $end +$var wire 1 /! chany_bottom_out [22] $end +$var wire 1 0! chany_bottom_out [23] $end +$var wire 1 1! chany_bottom_out [24] $end +$var wire 1 2! chany_bottom_out [25] $end +$var wire 1 3! chany_bottom_out [26] $end +$var wire 1 4! chany_bottom_out [27] $end +$var wire 1 5! chany_bottom_out [28] $end +$var wire 1 6! chany_bottom_out [29] $end +$var wire 1 7! chanx_left_out [0] $end +$var wire 1 8! chanx_left_out [1] $end +$var wire 1 9! chanx_left_out [2] $end +$var wire 1 :! chanx_left_out [3] $end +$var wire 1 ;! chanx_left_out [4] $end +$var wire 1 ! chanx_left_out [7] $end +$var wire 1 ?! chanx_left_out [8] $end +$var wire 1 @! chanx_left_out [9] $end +$var wire 1 A! chanx_left_out [10] $end +$var wire 1 B! chanx_left_out [11] $end +$var wire 1 C! chanx_left_out [12] $end +$var wire 1 D! chanx_left_out [13] $end +$var wire 1 E! chanx_left_out [14] $end +$var wire 1 F! chanx_left_out [15] $end +$var wire 1 G! chanx_left_out [16] $end +$var wire 1 H! chanx_left_out [17] $end +$var wire 1 I! chanx_left_out [18] $end +$var wire 1 J! chanx_left_out [19] $end +$var wire 1 K! chanx_left_out [20] $end +$var wire 1 L! chanx_left_out [21] $end +$var wire 1 M! chanx_left_out [22] $end +$var wire 1 N! chanx_left_out [23] $end +$var wire 1 O! chanx_left_out [24] $end +$var wire 1 P! chanx_left_out [25] $end +$var wire 1 Q! chanx_left_out [26] $end +$var wire 1 R! chanx_left_out [27] $end +$var wire 1 S! chanx_left_out [28] $end +$var wire 1 T! chanx_left_out [29] $end +$var wire 1 & ccff_tail [0] $end +$var wire 1 U! SC_IN_BOT $end +$var wire 1 V! SC_OUT_BOT $end +$var wire 1 W! pReset_W_in $end +$var wire 1 X! prog_clk_0_S_in $end +$var wire 1 Y! prog_clk [0] $end +$var wire 1 Z! prog_clk_0 $end +$var wire 1 [! mux_2level_tapbuf_size2_0_sram [0] $end +$var wire 1 \! mux_2level_tapbuf_size2_0_sram [1] $end +$var wire 1 ]! mux_2level_tapbuf_size2_10_sram [0] $end +$var wire 1 ^! mux_2level_tapbuf_size2_10_sram [1] $end +$var wire 1 _! mux_2level_tapbuf_size2_11_sram [0] $end +$var wire 1 `! mux_2level_tapbuf_size2_11_sram [1] $end +$var wire 1 a! mux_2level_tapbuf_size2_12_sram [0] $end +$var wire 1 b! mux_2level_tapbuf_size2_12_sram [1] $end +$var wire 1 c! mux_2level_tapbuf_size2_13_sram [0] $end +$var wire 1 d! mux_2level_tapbuf_size2_13_sram [1] $end +$var wire 1 e! mux_2level_tapbuf_size2_14_sram [0] $end +$var wire 1 f! mux_2level_tapbuf_size2_14_sram [1] $end +$var wire 1 g! mux_2level_tapbuf_size2_15_sram [0] $end +$var wire 1 h! mux_2level_tapbuf_size2_15_sram [1] $end +$var wire 1 i! mux_2level_tapbuf_size2_16_sram [0] $end +$var wire 1 j! mux_2level_tapbuf_size2_16_sram [1] $end +$var wire 1 k! mux_2level_tapbuf_size2_17_sram [0] $end +$var wire 1 l! mux_2level_tapbuf_size2_17_sram [1] $end +$var wire 1 m! mux_2level_tapbuf_size2_18_sram [0] $end +$var wire 1 n! mux_2level_tapbuf_size2_18_sram [1] $end +$var wire 1 o! mux_2level_tapbuf_size2_19_sram [0] $end +$var wire 1 p! mux_2level_tapbuf_size2_19_sram [1] $end +$var wire 1 q! mux_2level_tapbuf_size2_1_sram [0] $end +$var wire 1 r! mux_2level_tapbuf_size2_1_sram [1] $end +$var wire 1 s! mux_2level_tapbuf_size2_20_sram [0] $end +$var wire 1 t! mux_2level_tapbuf_size2_20_sram [1] $end +$var wire 1 u! mux_2level_tapbuf_size2_21_sram [0] $end +$var wire 1 v! mux_2level_tapbuf_size2_21_sram [1] $end +$var wire 1 w! mux_2level_tapbuf_size2_22_sram [0] $end +$var wire 1 x! mux_2level_tapbuf_size2_22_sram [1] $end +$var wire 1 y! mux_2level_tapbuf_size2_23_sram [0] $end +$var wire 1 z! mux_2level_tapbuf_size2_23_sram [1] $end +$var wire 1 {! mux_2level_tapbuf_size2_24_sram [0] $end +$var wire 1 |! mux_2level_tapbuf_size2_24_sram [1] $end +$var wire 1 }! mux_2level_tapbuf_size2_25_sram [0] $end +$var wire 1 ~! mux_2level_tapbuf_size2_25_sram [1] $end +$var wire 1 !" mux_2level_tapbuf_size2_26_sram [0] $end +$var wire 1 "" mux_2level_tapbuf_size2_26_sram [1] $end +$var wire 1 #" mux_2level_tapbuf_size2_27_sram [0] $end +$var wire 1 $" mux_2level_tapbuf_size2_27_sram [1] $end +$var wire 1 %" mux_2level_tapbuf_size2_28_sram [0] $end +$var wire 1 &" mux_2level_tapbuf_size2_28_sram [1] $end +$var wire 1 '" mux_2level_tapbuf_size2_29_sram [0] $end +$var wire 1 (" mux_2level_tapbuf_size2_29_sram [1] $end +$var wire 1 )" mux_2level_tapbuf_size2_2_sram [0] $end +$var wire 1 *" mux_2level_tapbuf_size2_2_sram [1] $end +$var wire 1 +" mux_2level_tapbuf_size2_30_sram [0] $end +$var wire 1 ," mux_2level_tapbuf_size2_30_sram [1] $end +$var wire 1 -" mux_2level_tapbuf_size2_31_sram [0] $end +$var wire 1 ." mux_2level_tapbuf_size2_31_sram [1] $end +$var wire 1 /" mux_2level_tapbuf_size2_32_sram [0] $end +$var wire 1 0" mux_2level_tapbuf_size2_32_sram [1] $end +$var wire 1 1" mux_2level_tapbuf_size2_33_sram [0] $end +$var wire 1 2" mux_2level_tapbuf_size2_33_sram [1] $end +$var wire 1 3" mux_2level_tapbuf_size2_34_sram [0] $end +$var wire 1 4" mux_2level_tapbuf_size2_34_sram [1] $end +$var wire 1 5" mux_2level_tapbuf_size2_35_sram [0] $end +$var wire 1 6" mux_2level_tapbuf_size2_35_sram [1] $end +$var wire 1 7" mux_2level_tapbuf_size2_36_sram [0] $end +$var wire 1 8" mux_2level_tapbuf_size2_36_sram [1] $end +$var wire 1 9" mux_2level_tapbuf_size2_3_sram [0] $end +$var wire 1 :" mux_2level_tapbuf_size2_3_sram [1] $end +$var wire 1 ;" mux_2level_tapbuf_size2_4_sram [0] $end +$var wire 1 <" mux_2level_tapbuf_size2_4_sram [1] $end +$var wire 1 =" mux_2level_tapbuf_size2_5_sram [0] $end +$var wire 1 >" mux_2level_tapbuf_size2_5_sram [1] $end +$var wire 1 ?" mux_2level_tapbuf_size2_6_sram [0] $end +$var wire 1 @" mux_2level_tapbuf_size2_6_sram [1] $end +$var wire 1 A" mux_2level_tapbuf_size2_7_sram [0] $end +$var wire 1 B" mux_2level_tapbuf_size2_7_sram [1] $end +$var wire 1 C" mux_2level_tapbuf_size2_8_sram [0] $end +$var wire 1 D" mux_2level_tapbuf_size2_8_sram [1] $end +$var wire 1 E" mux_2level_tapbuf_size2_9_sram [0] $end +$var wire 1 F" mux_2level_tapbuf_size2_9_sram [1] $end +$var wire 1 G" mux_2level_tapbuf_size2_mem_0_ccff_tail [0] $end +$var wire 1 H" mux_2level_tapbuf_size2_mem_10_ccff_tail [0] $end +$var wire 1 I" mux_2level_tapbuf_size2_mem_11_ccff_tail [0] $end +$var wire 1 J" mux_2level_tapbuf_size2_mem_12_ccff_tail [0] $end +$var wire 1 K" mux_2level_tapbuf_size2_mem_13_ccff_tail [0] $end +$var wire 1 L" mux_2level_tapbuf_size2_mem_14_ccff_tail [0] $end +$var wire 1 M" mux_2level_tapbuf_size2_mem_15_ccff_tail [0] $end +$var wire 1 N" mux_2level_tapbuf_size2_mem_16_ccff_tail [0] $end +$var wire 1 O" mux_2level_tapbuf_size2_mem_17_ccff_tail [0] $end +$var wire 1 P" mux_2level_tapbuf_size2_mem_18_ccff_tail [0] $end +$var wire 1 Q" mux_2level_tapbuf_size2_mem_19_ccff_tail [0] $end +$var wire 1 R" mux_2level_tapbuf_size2_mem_1_ccff_tail [0] $end +$var wire 1 S" mux_2level_tapbuf_size2_mem_20_ccff_tail [0] $end +$var wire 1 T" mux_2level_tapbuf_size2_mem_21_ccff_tail [0] $end +$var wire 1 U" mux_2level_tapbuf_size2_mem_22_ccff_tail [0] $end +$var wire 1 V" mux_2level_tapbuf_size2_mem_23_ccff_tail [0] $end +$var wire 1 W" mux_2level_tapbuf_size2_mem_24_ccff_tail [0] $end +$var wire 1 X" mux_2level_tapbuf_size2_mem_25_ccff_tail [0] $end +$var wire 1 Y" mux_2level_tapbuf_size2_mem_26_ccff_tail [0] $end +$var wire 1 Z" mux_2level_tapbuf_size2_mem_27_ccff_tail [0] $end +$var wire 1 [" mux_2level_tapbuf_size2_mem_28_ccff_tail [0] $end +$var wire 1 \" mux_2level_tapbuf_size2_mem_29_ccff_tail [0] $end +$var wire 1 ]" mux_2level_tapbuf_size2_mem_2_ccff_tail [0] $end +$var wire 1 ^" mux_2level_tapbuf_size2_mem_30_ccff_tail [0] $end +$var wire 1 _" mux_2level_tapbuf_size2_mem_31_ccff_tail [0] $end +$var wire 1 `" mux_2level_tapbuf_size2_mem_32_ccff_tail [0] $end +$var wire 1 a" mux_2level_tapbuf_size2_mem_33_ccff_tail [0] $end +$var wire 1 b" mux_2level_tapbuf_size2_mem_34_ccff_tail [0] $end +$var wire 1 c" mux_2level_tapbuf_size2_mem_35_ccff_tail [0] $end +$var wire 1 d" mux_2level_tapbuf_size2_mem_3_ccff_tail [0] $end +$var wire 1 e" mux_2level_tapbuf_size2_mem_4_ccff_tail [0] $end +$var wire 1 f" mux_2level_tapbuf_size2_mem_5_ccff_tail [0] $end +$var wire 1 g" mux_2level_tapbuf_size2_mem_6_ccff_tail [0] $end +$var wire 1 h" mux_2level_tapbuf_size2_mem_7_ccff_tail [0] $end +$var wire 1 i" mux_2level_tapbuf_size2_mem_8_ccff_tail [0] $end +$var wire 1 j" mux_2level_tapbuf_size2_mem_9_ccff_tail [0] $end +$var wire 1 k" mux_2level_tapbuf_size3_0_sram [0] $end +$var wire 1 l" mux_2level_tapbuf_size3_0_sram [1] $end +$var wire 1 m" mux_2level_tapbuf_size3_1_sram [0] $end +$var wire 1 n" mux_2level_tapbuf_size3_1_sram [1] $end +$var wire 1 o" mux_2level_tapbuf_size3_2_sram [0] $end +$var wire 1 p" mux_2level_tapbuf_size3_2_sram [1] $end +$var wire 1 q" mux_2level_tapbuf_size3_3_sram [0] $end +$var wire 1 r" mux_2level_tapbuf_size3_3_sram [1] $end +$var wire 1 s" mux_2level_tapbuf_size3_mem_0_ccff_tail [0] $end +$var wire 1 t" mux_2level_tapbuf_size3_mem_1_ccff_tail [0] $end +$var wire 1 u" mux_2level_tapbuf_size3_mem_2_ccff_tail [0] $end +$var wire 1 v" mux_2level_tapbuf_size3_mem_3_ccff_tail [0] $end +$var wire 1 w" mux_2level_tapbuf_size4_0_sram [0] $end +$var wire 1 x" mux_2level_tapbuf_size4_0_sram [1] $end +$var wire 1 y" mux_2level_tapbuf_size4_0_sram [2] $end +$var wire 1 z" mux_2level_tapbuf_size4_0_sram [3] $end +$var wire 1 {" mux_2level_tapbuf_size4_10_sram [0] $end +$var wire 1 |" mux_2level_tapbuf_size4_10_sram [1] $end +$var wire 1 }" mux_2level_tapbuf_size4_10_sram [2] $end +$var wire 1 ~" mux_2level_tapbuf_size4_10_sram [3] $end +$var wire 1 !# mux_2level_tapbuf_size4_11_sram [0] $end +$var wire 1 "# mux_2level_tapbuf_size4_11_sram [1] $end +$var wire 1 ## mux_2level_tapbuf_size4_11_sram [2] $end +$var wire 1 $# mux_2level_tapbuf_size4_11_sram [3] $end +$var wire 1 %# mux_2level_tapbuf_size4_1_sram [0] $end +$var wire 1 &# mux_2level_tapbuf_size4_1_sram [1] $end +$var wire 1 '# mux_2level_tapbuf_size4_1_sram [2] $end +$var wire 1 (# mux_2level_tapbuf_size4_1_sram [3] $end +$var wire 1 )# mux_2level_tapbuf_size4_2_sram [0] $end +$var wire 1 *# mux_2level_tapbuf_size4_2_sram [1] $end +$var wire 1 +# mux_2level_tapbuf_size4_2_sram [2] $end +$var wire 1 ,# mux_2level_tapbuf_size4_2_sram [3] $end +$var wire 1 -# mux_2level_tapbuf_size4_3_sram [0] $end +$var wire 1 .# mux_2level_tapbuf_size4_3_sram [1] $end +$var wire 1 /# mux_2level_tapbuf_size4_3_sram [2] $end +$var wire 1 0# mux_2level_tapbuf_size4_3_sram [3] $end +$var wire 1 1# mux_2level_tapbuf_size4_4_sram [0] $end +$var wire 1 2# mux_2level_tapbuf_size4_4_sram [1] $end +$var wire 1 3# mux_2level_tapbuf_size4_4_sram [2] $end +$var wire 1 4# mux_2level_tapbuf_size4_4_sram [3] $end +$var wire 1 5# mux_2level_tapbuf_size4_5_sram [0] $end +$var wire 1 6# mux_2level_tapbuf_size4_5_sram [1] $end +$var wire 1 7# mux_2level_tapbuf_size4_5_sram [2] $end +$var wire 1 8# mux_2level_tapbuf_size4_5_sram [3] $end +$var wire 1 9# mux_2level_tapbuf_size4_6_sram [0] $end +$var wire 1 :# mux_2level_tapbuf_size4_6_sram [1] $end +$var wire 1 ;# mux_2level_tapbuf_size4_6_sram [2] $end +$var wire 1 <# mux_2level_tapbuf_size4_6_sram [3] $end +$var wire 1 =# mux_2level_tapbuf_size4_7_sram [0] $end +$var wire 1 ># mux_2level_tapbuf_size4_7_sram [1] $end +$var wire 1 ?# mux_2level_tapbuf_size4_7_sram [2] $end +$var wire 1 @# mux_2level_tapbuf_size4_7_sram [3] $end +$var wire 1 A# mux_2level_tapbuf_size4_8_sram [0] $end +$var wire 1 B# mux_2level_tapbuf_size4_8_sram [1] $end +$var wire 1 C# mux_2level_tapbuf_size4_8_sram [2] $end +$var wire 1 D# mux_2level_tapbuf_size4_8_sram [3] $end +$var wire 1 E# mux_2level_tapbuf_size4_9_sram [0] $end +$var wire 1 F# mux_2level_tapbuf_size4_9_sram [1] $end +$var wire 1 G# mux_2level_tapbuf_size4_9_sram [2] $end +$var wire 1 H# mux_2level_tapbuf_size4_9_sram [3] $end +$var wire 1 I# mux_2level_tapbuf_size4_mem_0_ccff_tail [0] $end +$var wire 1 J# mux_2level_tapbuf_size4_mem_10_ccff_tail [0] $end +$var wire 1 K# mux_2level_tapbuf_size4_mem_11_ccff_tail [0] $end +$var wire 1 L# mux_2level_tapbuf_size4_mem_1_ccff_tail [0] $end +$var wire 1 M# mux_2level_tapbuf_size4_mem_2_ccff_tail [0] $end +$var wire 1 N# mux_2level_tapbuf_size4_mem_3_ccff_tail [0] $end +$var wire 1 O# mux_2level_tapbuf_size4_mem_4_ccff_tail [0] $end +$var wire 1 P# mux_2level_tapbuf_size4_mem_5_ccff_tail [0] $end +$var wire 1 Q# mux_2level_tapbuf_size4_mem_6_ccff_tail [0] $end +$var wire 1 R# mux_2level_tapbuf_size4_mem_7_ccff_tail [0] $end +$var wire 1 S# mux_2level_tapbuf_size4_mem_8_ccff_tail [0] $end +$var wire 1 T# mux_2level_tapbuf_size4_mem_9_ccff_tail [0] $end +$var wire 1 U# SYNOPSYS_UNCONNECTED_1 $end +$var wire 1 V# SYNOPSYS_UNCONNECTED_2 $end +$var wire 1 W# SYNOPSYS_UNCONNECTED_3 $end +$var wire 1 X# SYNOPSYS_UNCONNECTED_4 $end +$var wire 1 Y# optlc_net_178 $end +$var wire 1 Z# SYNOPSYS_UNCONNECTED_5 $end +$var wire 1 [# SYNOPSYS_UNCONNECTED_6 $end +$var wire 1 \# SYNOPSYS_UNCONNECTED_7 $end +$var wire 1 ]# SYNOPSYS_UNCONNECTED_8 $end +$var wire 1 ^# SYNOPSYS_UNCONNECTED_9 $end +$var wire 1 _# SYNOPSYS_UNCONNECTED_10 $end +$var wire 1 `# SYNOPSYS_UNCONNECTED_11 $end +$var wire 1 a# SYNOPSYS_UNCONNECTED_12 $end +$var wire 1 b# optlc_net_174 $end +$var wire 1 c# SYNOPSYS_UNCONNECTED_13 $end +$var wire 1 d# SYNOPSYS_UNCONNECTED_14 $end +$var wire 1 e# SYNOPSYS_UNCONNECTED_15 $end +$var wire 1 f# SYNOPSYS_UNCONNECTED_16 $end +$var wire 1 g# SYNOPSYS_UNCONNECTED_17 $end +$var wire 1 h# SYNOPSYS_UNCONNECTED_18 $end +$var wire 1 i# SYNOPSYS_UNCONNECTED_19 $end +$var wire 1 j# SYNOPSYS_UNCONNECTED_20 $end +$var wire 1 k# optlc_net_177 $end +$var wire 1 l# SYNOPSYS_UNCONNECTED_21 $end +$var wire 1 m# SYNOPSYS_UNCONNECTED_22 $end +$var wire 1 n# SYNOPSYS_UNCONNECTED_23 $end +$var wire 1 o# SYNOPSYS_UNCONNECTED_24 $end +$var wire 1 p# SYNOPSYS_UNCONNECTED_25 $end +$var wire 1 q# SYNOPSYS_UNCONNECTED_26 $end +$var wire 1 r# SYNOPSYS_UNCONNECTED_27 $end +$var wire 1 s# SYNOPSYS_UNCONNECTED_28 $end +$var wire 1 t# SYNOPSYS_UNCONNECTED_29 $end +$var wire 1 u# SYNOPSYS_UNCONNECTED_30 $end +$var wire 1 v# SYNOPSYS_UNCONNECTED_31 $end +$var wire 1 w# SYNOPSYS_UNCONNECTED_32 $end +$var wire 1 x# SYNOPSYS_UNCONNECTED_33 $end +$var wire 1 y# SYNOPSYS_UNCONNECTED_34 $end +$var wire 1 z# SYNOPSYS_UNCONNECTED_35 $end +$var wire 1 {# SYNOPSYS_UNCONNECTED_36 $end +$var wire 1 |# SYNOPSYS_UNCONNECTED_37 $end +$var wire 1 }# SYNOPSYS_UNCONNECTED_38 $end +$var wire 1 ~# SYNOPSYS_UNCONNECTED_39 $end +$var wire 1 !$ SYNOPSYS_UNCONNECTED_40 $end +$var wire 1 "$ SYNOPSYS_UNCONNECTED_41 $end +$var wire 1 #$ SYNOPSYS_UNCONNECTED_42 $end +$var wire 1 $$ SYNOPSYS_UNCONNECTED_43 $end +$var wire 1 %$ SYNOPSYS_UNCONNECTED_44 $end +$var wire 1 &$ SYNOPSYS_UNCONNECTED_45 $end +$var wire 1 '$ SYNOPSYS_UNCONNECTED_46 $end +$var wire 1 ($ SYNOPSYS_UNCONNECTED_47 $end +$var wire 1 )$ SYNOPSYS_UNCONNECTED_48 $end +$var wire 1 *$ SYNOPSYS_UNCONNECTED_49 $end +$var wire 1 +$ SYNOPSYS_UNCONNECTED_50 $end +$var wire 1 ,$ SYNOPSYS_UNCONNECTED_51 $end +$var wire 1 -$ SYNOPSYS_UNCONNECTED_52 $end +$var wire 1 .$ optlc_net_175 $end +$var wire 1 /$ SYNOPSYS_UNCONNECTED_53 $end +$var wire 1 0$ SYNOPSYS_UNCONNECTED_54 $end +$var wire 1 1$ SYNOPSYS_UNCONNECTED_55 $end +$var wire 1 2$ SYNOPSYS_UNCONNECTED_56 $end +$var wire 1 3$ SYNOPSYS_UNCONNECTED_57 $end +$var wire 1 4$ SYNOPSYS_UNCONNECTED_58 $end +$var wire 1 5$ optlc_net_179 $end +$var wire 1 6$ SYNOPSYS_UNCONNECTED_59 $end +$var wire 1 7$ SYNOPSYS_UNCONNECTED_60 $end +$var wire 1 8$ SYNOPSYS_UNCONNECTED_61 $end +$var wire 1 9$ SYNOPSYS_UNCONNECTED_62 $end +$var wire 1 :$ SYNOPSYS_UNCONNECTED_63 $end +$var wire 1 ;$ SYNOPSYS_UNCONNECTED_64 $end +$var wire 1 <$ SYNOPSYS_UNCONNECTED_65 $end +$var wire 1 =$ SYNOPSYS_UNCONNECTED_66 $end +$var wire 1 >$ SYNOPSYS_UNCONNECTED_67 $end +$var wire 1 ?$ SYNOPSYS_UNCONNECTED_68 $end +$var wire 1 @$ SYNOPSYS_UNCONNECTED_69 $end +$var wire 1 A$ SYNOPSYS_UNCONNECTED_70 $end +$var wire 1 B$ SYNOPSYS_UNCONNECTED_71 $end +$var wire 1 C$ SYNOPSYS_UNCONNECTED_72 $end +$var wire 1 D$ SYNOPSYS_UNCONNECTED_73 $end +$var wire 1 E$ SYNOPSYS_UNCONNECTED_74 $end +$var wire 1 F$ SYNOPSYS_UNCONNECTED_75 $end +$var wire 1 G$ SYNOPSYS_UNCONNECTED_76 $end +$var wire 1 H$ SYNOPSYS_UNCONNECTED_77 $end +$var wire 1 I$ SYNOPSYS_UNCONNECTED_78 $end +$var wire 1 J$ SYNOPSYS_UNCONNECTED_79 $end +$var wire 1 K$ SYNOPSYS_UNCONNECTED_80 $end +$var wire 1 L$ optlc_net_176 $end +$var wire 1 M$ SYNOPSYS_UNCONNECTED_81 $end +$var wire 1 N$ SYNOPSYS_UNCONNECTED_82 $end +$var wire 1 O$ SYNOPSYS_UNCONNECTED_83 $end +$var wire 1 P$ SYNOPSYS_UNCONNECTED_84 $end +$var wire 1 Q$ SYNOPSYS_UNCONNECTED_85 $end +$var wire 1 R$ SYNOPSYS_UNCONNECTED_86 $end +$var wire 1 S$ SYNOPSYS_UNCONNECTED_87 $end +$var wire 1 T$ SYNOPSYS_UNCONNECTED_88 $end +$var wire 1 U$ SYNOPSYS_UNCONNECTED_89 $end +$var wire 1 V$ SYNOPSYS_UNCONNECTED_90 $end +$var wire 1 W$ SYNOPSYS_UNCONNECTED_91 $end +$var wire 1 X$ SYNOPSYS_UNCONNECTED_92 $end +$var wire 1 Y$ SYNOPSYS_UNCONNECTED_93 $end +$var wire 1 Z$ SYNOPSYS_UNCONNECTED_94 $end +$var wire 1 [$ SYNOPSYS_UNCONNECTED_95 $end +$var wire 1 \$ SYNOPSYS_UNCONNECTED_96 $end +$var wire 1 ]$ SYNOPSYS_UNCONNECTED_97 $end +$var wire 1 ^$ SYNOPSYS_UNCONNECTED_98 $end +$var wire 1 _$ SYNOPSYS_UNCONNECTED_99 $end +$var wire 1 `$ SYNOPSYS_UNCONNECTED_100 $end +$var wire 1 a$ SYNOPSYS_UNCONNECTED_101 $end +$var wire 1 b$ SYNOPSYS_UNCONNECTED_102 $end +$var wire 1 c$ SYNOPSYS_UNCONNECTED_103 $end +$var wire 1 d$ SYNOPSYS_UNCONNECTED_104 $end +$var wire 1 e$ SYNOPSYS_UNCONNECTED_105 $end +$var wire 1 f$ SYNOPSYS_UNCONNECTED_106 $end +$var wire 1 g$ SYNOPSYS_UNCONNECTED_107 $end +$var wire 1 h$ SYNOPSYS_UNCONNECTED_108 $end +$var wire 1 i$ SYNOPSYS_UNCONNECTED_109 $end +$var wire 1 j$ SYNOPSYS_UNCONNECTED_110 $end +$var wire 1 k$ SYNOPSYS_UNCONNECTED_111 $end +$var wire 1 l$ SYNOPSYS_UNCONNECTED_112 $end +$var wire 1 m$ SYNOPSYS_UNCONNECTED_113 $end +$var wire 1 n$ SYNOPSYS_UNCONNECTED_114 $end +$var wire 1 o$ SYNOPSYS_UNCONNECTED_115 $end +$var wire 1 p$ SYNOPSYS_UNCONNECTED_116 $end +$var wire 1 q$ SYNOPSYS_UNCONNECTED_117 $end +$var wire 1 r$ SYNOPSYS_UNCONNECTED_118 $end +$var wire 1 s$ SYNOPSYS_UNCONNECTED_119 $end +$var wire 1 t$ SYNOPSYS_UNCONNECTED_120 $end +$var wire 1 u$ SYNOPSYS_UNCONNECTED_121 $end +$var wire 1 v$ SYNOPSYS_UNCONNECTED_122 $end +$var wire 1 w$ SYNOPSYS_UNCONNECTED_123 $end +$var wire 1 x$ SYNOPSYS_UNCONNECTED_124 $end +$var wire 1 y$ SYNOPSYS_UNCONNECTED_125 $end +$var wire 1 z$ SYNOPSYS_UNCONNECTED_126 $end +$var wire 1 {$ SYNOPSYS_UNCONNECTED_127 $end +$var wire 1 |$ SYNOPSYS_UNCONNECTED_128 $end +$var wire 1 }$ SYNOPSYS_UNCONNECTED_129 $end +$var wire 1 ~$ SYNOPSYS_UNCONNECTED_130 $end +$var wire 1 !% SYNOPSYS_UNCONNECTED_131 $end +$var wire 1 "% SYNOPSYS_UNCONNECTED_132 $end +$var wire 1 #% SYNOPSYS_UNCONNECTED_133 $end +$var wire 1 $% SYNOPSYS_UNCONNECTED_134 $end +$var wire 1 %% SYNOPSYS_UNCONNECTED_135 $end +$var wire 1 &% SYNOPSYS_UNCONNECTED_136 $end + +$scope module mux_bottom_track_1 $end +$var wire 1 G in [0] $end +$var wire 1 J in [1] $end +$var wire 1 M in [2] $end +$var wire 1 Q in [3] $end +$var wire 1 w" sram [0] $end +$var wire 1 x" sram [1] $end +$var wire 1 y" sram [2] $end +$var wire 1 z" sram [3] $end +$var wire 1 U# sram_inv [0] $end +$var wire 1 V# sram_inv [1] $end +$var wire 1 W# sram_inv [2] $end +$var wire 1 X# sram_inv [3] $end +$var wire 1 w out [0] $end +$var wire 1 Y# p0 $end +$var wire 1 '% local_encoder2to3_0_data [0] $end +$var wire 1 (% local_encoder2to3_0_data [1] $end +$var wire 1 )% local_encoder2to3_0_data [2] $end +$var wire 1 *% local_encoder2to3_0_data_inv [0] $end +$var wire 1 +% local_encoder2to3_0_data_inv [1] $end +$var wire 1 ,% local_encoder2to3_0_data_inv [2] $end +$var wire 1 -% local_encoder2to3_1_data [0] $end +$var wire 1 .% local_encoder2to3_1_data [1] $end +$var wire 1 /% local_encoder2to3_1_data [2] $end +$var wire 1 0% local_encoder2to3_1_data_inv [0] $end +$var wire 1 1% local_encoder2to3_1_data_inv [1] $end +$var wire 1 2% local_encoder2to3_1_data_inv [2] $end +$var wire 1 3% mux_2level_tapbuf_basis_input3_mem3_0_out [0] $end +$var wire 1 4% mux_2level_tapbuf_basis_input3_mem3_1_out [0] $end +$var wire 1 5% SYNOPSYS_UNCONNECTED_1 $end +$var wire 1 6% BUF_net_86 $end + +$scope module local_encoder2to3_0_ $end +$var wire 1 w" addr [0] $end +$var wire 1 x" addr [1] $end +$var wire 1 '% data [0] $end +$var wire 1 (% data [1] $end +$var wire 1 )% data [2] $end +$var wire 1 *% data_inv [0] $end +$var wire 1 +% data_inv [1] $end +$var wire 1 ,% data_inv [2] $end + +$scope module U8 $end +$var wire 1 *% Y $end +$var wire 1 '% A $end +$var supply1 1 7% VPWR $end +$var supply0 1 8% VGND $end +$var supply1 1 9% VPB $end +$var supply0 1 :% VNB $end + +$scope module base $end +$var wire 1 *% Y $end +$var wire 1 '% A $end +$var wire 1 ;% not0_out_Y $end +$upscope $end +$upscope $end + +$scope module U9 $end +$var wire 1 (% Y $end +$var wire 1 +% A $end +$var supply1 1 <% VPWR $end +$var supply0 1 =% VGND $end +$var supply1 1 >% VPB $end +$var supply0 1 ?% VNB $end + +$scope module base $end +$var wire 1 (% Y $end +$var wire 1 +% A $end +$var wire 1 @% not0_out_Y $end +$upscope $end +$upscope $end + +$scope module U10 $end +$var wire 1 +% Y $end +$var wire 1 w" A $end +$var wire 1 ,% B $end +$var supply1 1 A% VPWR $end +$var supply0 1 B% VGND $end +$var supply1 1 C% VPB $end +$var supply0 1 D% VNB $end + +$scope module base $end +$var wire 1 +% Y $end +$var wire 1 w" A $end +$var wire 1 ,% B $end +$var wire 1 E% nand0_out_Y $end +$upscope $end +$upscope $end + +$scope module U11 $end +$var wire 1 ,% Y $end +$var wire 1 )% A $end +$var supply1 1 F% VPWR $end +$var supply0 1 G% VGND $end +$var supply1 1 H% VPB $end +$var supply0 1 I% VNB $end + +$scope module base $end +$var wire 1 ,% Y $end +$var wire 1 )% A $end +$var wire 1 J% not0_out_Y $end +$upscope $end +$upscope $end + +$scope module U12 $end +$var wire 1 '% Y $end +$var wire 1 )% A $end +$var wire 1 w" B $end +$var supply1 1 K% VPWR $end +$var supply0 1 L% VGND $end +$var supply1 1 M% VPB $end +$var supply0 1 N% VNB $end + +$scope module base $end +$var wire 1 '% Y $end +$var wire 1 )% A $end +$var wire 1 w" B $end +$var wire 1 O% nor0_out_Y $end +$upscope $end +$upscope $end + +$scope module FTB_1__0 $end +$var wire 1 )% X $end +$var wire 1 x" A $end +$var supply1 1 P% VPWR $end +$var supply0 1 Q% VGND $end +$var supply1 1 R% VPB $end +$var supply0 1 S% VNB $end + +$scope module base $end +$var wire 1 )% X $end +$var wire 1 x" A $end +$var wire 1 T% buf0_out_X $end +$upscope $end +$upscope $end +$upscope $end + +$scope module local_encoder2to3_1_ $end +$var wire 1 y" addr [0] $end +$var wire 1 z" addr [1] $end +$var wire 1 -% data [0] $end +$var wire 1 .% data [1] $end +$var wire 1 /% data [2] $end +$var wire 1 0% data_inv [0] $end +$var wire 1 1% data_inv [1] $end +$var wire 1 2% data_inv [2] $end + +$scope module U8 $end +$var wire 1 0% Y $end +$var wire 1 -% A $end +$var supply1 1 U% VPWR $end +$var supply0 1 V% VGND $end +$var supply1 1 W% VPB $end +$var supply0 1 X% VNB $end + +$scope module base $end +$var wire 1 0% Y $end +$var wire 1 -% A $end +$var wire 1 Y% not0_out_Y $end +$upscope $end +$upscope $end + +$scope module U9 $end +$var wire 1 .% Y $end +$var wire 1 1% A $end +$var supply1 1 Z% VPWR $end +$var supply0 1 [% VGND $end +$var supply1 1 \% VPB $end +$var supply0 1 ]% VNB $end + +$scope module base $end +$var wire 1 .% Y $end +$var wire 1 1% A $end +$var wire 1 ^% not0_out_Y $end +$upscope $end +$upscope $end + +$scope module U10 $end +$var wire 1 1% Y $end +$var wire 1 y" A $end +$var wire 1 2% B $end +$var supply1 1 _% VPWR $end +$var supply0 1 `% VGND $end +$var supply1 1 a% VPB $end +$var supply0 1 b% VNB $end + +$scope module base $end +$var wire 1 1% Y $end +$var wire 1 y" A $end +$var wire 1 2% B $end +$var wire 1 c% nand0_out_Y $end +$upscope $end +$upscope $end + +$scope module U11 $end +$var wire 1 2% Y $end +$var wire 1 /% A $end +$var supply1 1 d% VPWR $end +$var supply0 1 e% VGND $end +$var supply1 1 f% VPB $end +$var supply0 1 g% VNB $end + +$scope module base $end +$var wire 1 2% Y $end +$var wire 1 /% A $end +$var wire 1 h% not0_out_Y $end +$upscope $end +$upscope $end + +$scope module U12 $end +$var wire 1 -% Y $end +$var wire 1 /% A $end +$var wire 1 y" B $end +$var supply1 1 i% VPWR $end +$var supply0 1 j% VGND $end +$var supply1 1 k% VPB $end +$var supply0 1 l% VNB $end + +$scope module base $end +$var wire 1 -% Y $end +$var wire 1 /% A $end +$var wire 1 y" B $end +$var wire 1 m% nor0_out_Y $end +$upscope $end +$upscope $end + +$scope module FTB_2__1 $end +$var wire 1 /% X $end +$var wire 1 z" A $end +$var supply1 1 n% VPWR $end +$var supply0 1 o% VGND $end +$var supply1 1 p% VPB $end +$var supply0 1 q% VNB $end + +$scope module base $end +$var wire 1 /% X $end +$var wire 1 z" A $end +$var wire 1 r% buf0_out_X $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mux_l1_in_0_ $end +$var wire 1 G in [0] $end +$var wire 1 J in [1] $end +$var wire 1 M in [2] $end +$var wire 1 '% mem [0] $end +$var wire 1 (% mem [1] $end +$var wire 1 )% mem [2] $end +$var wire 1 *% mem_inv [0] $end +$var wire 1 +% mem_inv [1] $end +$var wire 1 ,% mem_inv [2] $end +$var wire 1 3% out [0] $end + +$scope module scs8hd_muxinv3_1_0 $end +$var wire 1 3% Z $end +$var wire 1 G Q1 $end +$var wire 1 J Q2 $end +$var wire 1 M Q3 $end +$var wire 1 '% S0 $end +$var wire 1 *% S0B $end +$var wire 1 (% S1 $end +$var wire 1 +% S1B $end +$var wire 1 )% S2 $end +$var wire 1 ,% S2B $end +$var wire 1 s% Q1__bar $end +$var wire 1 t% Q2__bar $end +$var wire 1 u% Q3__bar $end +$upscope $end +$upscope $end + +$scope module mux_l2_in_0_ $end +$var wire 1 3% in [0] $end +$var wire 1 Q in [1] $end +$var wire 1 5% in [2] $end +$var wire 1 -% mem [0] $end +$var wire 1 .% mem [1] $end +$var wire 1 /% mem [2] $end +$var wire 1 0% mem_inv [0] $end +$var wire 1 1% mem_inv [1] $end +$var wire 1 2% mem_inv [2] $end +$var wire 1 4% out [0] $end +$var wire 1 Y# p0 $end + +$scope module scs8hd_muxinv3_1_0 $end +$var wire 1 4% Z $end +$var wire 1 3% Q1 $end +$var wire 1 Q Q2 $end +$var wire 1 Y# Q3 $end +$var wire 1 -% S0 $end +$var wire 1 0% S0B $end +$var wire 1 .% S1 $end +$var wire 1 1% S1B $end +$var wire 1 /% S2 $end +$var wire 1 2% S2B $end +$var wire 1 v% Q1__bar $end +$var wire 1 w% Q2__bar $end +$var wire 1 x% Q3__bar $end +$upscope $end +$upscope $end + +$scope module BINV_R_85 $end +$var wire 1 w Y $end +$var wire 1 6% A $end +$var supply1 1 y% VPWR $end +$var supply0 1 z% VGND $end +$var supply1 1 {% VPB $end +$var supply0 1 |% VNB $end + +$scope module base $end +$var wire 1 w Y $end +$var wire 1 6% A $end +$var wire 1 }% not0_out_Y $end +$upscope $end +$upscope $end + +$scope module BINV_R_86 $end +$var wire 1 6% Y $end +$var wire 1 4% A $end +$var supply1 1 ~% VPWR $end +$var supply0 1 !& VGND $end +$var supply1 1 "& VPB $end +$var supply0 1 #& VNB $end + +$scope module base $end +$var wire 1 6% Y $end +$var wire 1 4% A $end +$var wire 1 $& not0_out_Y $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mux_bottom_track_3 $end +$var wire 1 H in [0] $end +$var wire 1 K in [1] $end +$var wire 1 N in [2] $end +$var wire 1 R in [3] $end +$var wire 1 %# sram [0] $end +$var wire 1 &# sram [1] $end +$var wire 1 '# sram [2] $end +$var wire 1 (# sram [3] $end +$var wire 1 Z# sram_inv [0] $end +$var wire 1 [# sram_inv [1] $end +$var wire 1 \# sram_inv [2] $end +$var wire 1 ]# sram_inv [3] $end +$var wire 1 x out [0] $end +$var wire 1 Y# p0 $end +$var wire 1 %& local_encoder2to3_0_data [0] $end +$var wire 1 && local_encoder2to3_0_data [1] $end +$var wire 1 '& local_encoder2to3_0_data [2] $end +$var wire 1 (& local_encoder2to3_0_data_inv [0] $end +$var wire 1 )& local_encoder2to3_0_data_inv [1] $end +$var wire 1 *& local_encoder2to3_0_data_inv [2] $end +$var wire 1 +& local_encoder2to3_1_data [0] $end +$var wire 1 ,& local_encoder2to3_1_data [1] $end +$var wire 1 -& local_encoder2to3_1_data [2] $end +$var wire 1 .& local_encoder2to3_1_data_inv [0] $end +$var wire 1 /& local_encoder2to3_1_data_inv [1] $end +$var wire 1 0& local_encoder2to3_1_data_inv [2] $end +$var wire 1 1& mux_2level_tapbuf_basis_input3_mem3_0_out [0] $end +$var wire 1 2& mux_2level_tapbuf_basis_input3_mem3_1_out [0] $end +$var wire 1 3& SYNOPSYS_UNCONNECTED_1 $end +$var wire 1 4& BUF_net_88 $end + +$scope module local_encoder2to3_0_ $end +$var wire 1 %# addr [0] $end +$var wire 1 &# addr [1] $end +$var wire 1 %& data [0] $end +$var wire 1 && data [1] $end +$var wire 1 '& data [2] $end +$var wire 1 (& data_inv [0] $end +$var wire 1 )& data_inv [1] $end +$var wire 1 *& data_inv [2] $end + +$scope module U8 $end +$var wire 1 (& Y $end +$var wire 1 %& A $end +$var supply1 1 5& VPWR $end +$var supply0 1 6& VGND $end +$var supply1 1 7& VPB $end +$var supply0 1 8& VNB $end + +$scope module base $end +$var wire 1 (& Y $end +$var wire 1 %& A $end +$var wire 1 9& not0_out_Y $end +$upscope $end +$upscope $end + +$scope module U9 $end +$var wire 1 && Y $end +$var wire 1 )& A $end +$var supply1 1 :& VPWR $end +$var supply0 1 ;& VGND $end +$var supply1 1 <& VPB $end +$var supply0 1 =& VNB $end + +$scope module base $end +$var wire 1 && Y $end +$var wire 1 )& A $end +$var wire 1 >& not0_out_Y $end +$upscope $end +$upscope $end + +$scope module U10 $end +$var wire 1 )& Y $end +$var wire 1 %# A $end +$var wire 1 *& B $end +$var supply1 1 ?& VPWR $end +$var supply0 1 @& VGND $end +$var supply1 1 A& VPB $end +$var supply0 1 B& VNB $end + +$scope module base $end +$var wire 1 )& Y $end +$var wire 1 %# A $end +$var wire 1 *& B $end +$var wire 1 C& nand0_out_Y $end +$upscope $end +$upscope $end + +$scope module U11 $end +$var wire 1 *& Y $end +$var wire 1 '& A $end +$var supply1 1 D& VPWR $end +$var supply0 1 E& VGND $end +$var supply1 1 F& VPB $end +$var supply0 1 G& VNB $end + +$scope module base $end +$var wire 1 *& Y $end +$var wire 1 '& A $end +$var wire 1 H& not0_out_Y $end +$upscope $end +$upscope $end + +$scope module U12 $end +$var wire 1 %& Y $end +$var wire 1 '& A $end +$var wire 1 %# B $end +$var supply1 1 I& VPWR $end +$var supply0 1 J& VGND $end +$var supply1 1 K& VPB $end +$var supply0 1 L& VNB $end + +$scope module base $end +$var wire 1 %& Y $end +$var wire 1 '& A $end +$var wire 1 %# B $end +$var wire 1 M& nor0_out_Y $end +$upscope $end +$upscope $end + +$scope module FTB_3__2 $end +$var wire 1 '& X $end +$var wire 1 &# A $end +$var supply1 1 N& VPWR $end +$var supply0 1 O& VGND $end +$var supply1 1 P& VPB $end +$var supply0 1 Q& VNB $end + +$scope module base $end +$var wire 1 '& X $end +$var wire 1 &# A $end +$var wire 1 R& buf0_out_X $end +$upscope $end +$upscope $end +$upscope $end + +$scope module local_encoder2to3_1_ $end +$var wire 1 '# addr [0] $end +$var wire 1 (# addr [1] $end +$var wire 1 +& data [0] $end +$var wire 1 ,& data [1] $end +$var wire 1 -& data [2] $end +$var wire 1 .& data_inv [0] $end +$var wire 1 /& data_inv [1] $end +$var wire 1 0& data_inv [2] $end + +$scope module U8 $end +$var wire 1 .& Y $end +$var wire 1 +& A $end +$var supply1 1 S& VPWR $end +$var supply0 1 T& VGND $end +$var supply1 1 U& VPB $end +$var supply0 1 V& VNB $end + +$scope module base $end +$var wire 1 .& Y $end +$var wire 1 +& A $end +$var wire 1 W& not0_out_Y $end +$upscope $end +$upscope $end + +$scope module U9 $end +$var wire 1 ,& Y $end +$var wire 1 /& A $end +$var supply1 1 X& VPWR $end +$var supply0 1 Y& VGND $end +$var supply1 1 Z& VPB $end +$var supply0 1 [& VNB $end + +$scope module base $end +$var wire 1 ,& Y $end +$var wire 1 /& A $end +$var wire 1 \& not0_out_Y $end +$upscope $end +$upscope $end + +$scope module U10 $end +$var wire 1 /& Y $end +$var wire 1 '# A $end +$var wire 1 0& B $end +$var supply1 1 ]& VPWR $end +$var supply0 1 ^& VGND $end +$var supply1 1 _& VPB $end +$var supply0 1 `& VNB $end + +$scope module base $end +$var wire 1 /& Y $end +$var wire 1 '# A $end +$var wire 1 0& B $end +$var wire 1 a& nand0_out_Y $end +$upscope $end +$upscope $end + +$scope module U11 $end +$var wire 1 0& Y $end +$var wire 1 -& A $end +$var supply1 1 b& VPWR $end +$var supply0 1 c& VGND $end +$var supply1 1 d& VPB $end +$var supply0 1 e& VNB $end + +$scope module base $end +$var wire 1 0& Y $end +$var wire 1 -& A $end +$var wire 1 f& not0_out_Y $end +$upscope $end +$upscope $end + +$scope module U12 $end +$var wire 1 +& Y $end +$var wire 1 -& A $end +$var wire 1 '# B $end +$var supply1 1 g& VPWR $end +$var supply0 1 h& VGND $end +$var supply1 1 i& VPB $end +$var supply0 1 j& VNB $end + +$scope module base $end +$var wire 1 +& Y $end +$var wire 1 -& A $end +$var wire 1 '# B $end +$var wire 1 k& nor0_out_Y $end +$upscope $end +$upscope $end + +$scope module FTB_4__3 $end +$var wire 1 -& X $end +$var wire 1 (# A $end +$var supply1 1 l& VPWR $end +$var supply0 1 m& VGND $end +$var supply1 1 n& VPB $end +$var supply0 1 o& VNB $end + +$scope module base $end +$var wire 1 -& X $end +$var wire 1 (# A $end +$var wire 1 p& buf0_out_X $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mux_l1_in_0_ $end +$var wire 1 H in [0] $end +$var wire 1 K in [1] $end +$var wire 1 N in [2] $end +$var wire 1 %& mem [0] $end +$var wire 1 && mem [1] $end +$var wire 1 '& mem [2] $end +$var wire 1 (& mem_inv [0] $end +$var wire 1 )& mem_inv [1] $end +$var wire 1 *& mem_inv [2] $end +$var wire 1 1& out [0] $end + +$scope module scs8hd_muxinv3_1_0 $end +$var wire 1 1& Z $end +$var wire 1 H Q1 $end +$var wire 1 K Q2 $end +$var wire 1 N Q3 $end +$var wire 1 %& S0 $end +$var wire 1 (& S0B $end +$var wire 1 && S1 $end +$var wire 1 )& S1B $end +$var wire 1 '& S2 $end +$var wire 1 *& S2B $end +$var wire 1 q& Q1__bar $end +$var wire 1 r& Q2__bar $end +$var wire 1 s& Q3__bar $end +$upscope $end +$upscope $end + +$scope module mux_l2_in_0_ $end +$var wire 1 1& in [0] $end +$var wire 1 R in [1] $end +$var wire 1 3& in [2] $end +$var wire 1 +& mem [0] $end +$var wire 1 ,& mem [1] $end +$var wire 1 -& mem [2] $end +$var wire 1 .& mem_inv [0] $end +$var wire 1 /& mem_inv [1] $end +$var wire 1 0& mem_inv [2] $end +$var wire 1 2& out [0] $end +$var wire 1 Y# p0 $end + +$scope module scs8hd_muxinv3_1_0 $end +$var wire 1 2& Z $end +$var wire 1 1& Q1 $end +$var wire 1 R Q2 $end +$var wire 1 Y# Q3 $end +$var wire 1 +& S0 $end +$var wire 1 .& S0B $end +$var wire 1 ,& S1 $end +$var wire 1 /& S1B $end +$var wire 1 -& S2 $end +$var wire 1 0& S2B $end +$var wire 1 t& Q1__bar $end +$var wire 1 u& Q2__bar $end +$var wire 1 v& Q3__bar $end +$upscope $end +$upscope $end + +$scope module BINV_R_87 $end +$var wire 1 x Y $end +$var wire 1 4& A $end +$var supply1 1 w& VPWR $end +$var supply0 1 x& VGND $end +$var supply1 1 y& VPB $end +$var supply0 1 z& VNB $end + +$scope module base $end +$var wire 1 x Y $end +$var wire 1 4& A $end +$var wire 1 {& not0_out_Y $end +$upscope $end +$upscope $end + +$scope module BINV_R_88 $end +$var wire 1 4& Y $end +$var wire 1 2& A $end +$var supply1 1 |& VPWR $end +$var supply0 1 }& VGND $end +$var supply1 1 ~& VPB $end +$var supply0 1 !' VNB $end + +$scope module base $end +$var wire 1 4& Y $end +$var wire 1 2& A $end +$var wire 1 "' not0_out_Y $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mux_bottom_track_5 $end +$var wire 1 I in [0] $end +$var wire 1 L in [1] $end +$var wire 1 O in [2] $end +$var wire 1 S in [3] $end +$var wire 1 )# sram [0] $end +$var wire 1 *# sram [1] $end +$var wire 1 +# sram [2] $end +$var wire 1 ,# sram [3] $end +$var wire 1 ^# sram_inv [0] $end +$var wire 1 _# sram_inv [1] $end +$var wire 1 `# sram_inv [2] $end +$var wire 1 a# sram_inv [3] $end +$var wire 1 y out [0] $end +$var wire 1 b# p0 $end +$var wire 1 #' local_encoder2to3_0_data [0] $end +$var wire 1 $' local_encoder2to3_0_data [1] $end +$var wire 1 %' local_encoder2to3_0_data [2] $end +$var wire 1 &' local_encoder2to3_0_data_inv [0] $end +$var wire 1 '' local_encoder2to3_0_data_inv [1] $end +$var wire 1 (' local_encoder2to3_0_data_inv [2] $end +$var wire 1 )' local_encoder2to3_1_data [0] $end +$var wire 1 *' local_encoder2to3_1_data [1] $end +$var wire 1 +' local_encoder2to3_1_data [2] $end +$var wire 1 ,' local_encoder2to3_1_data_inv [0] $end +$var wire 1 -' local_encoder2to3_1_data_inv [1] $end +$var wire 1 .' local_encoder2to3_1_data_inv [2] $end +$var wire 1 /' mux_2level_tapbuf_basis_input3_mem3_0_out [0] $end +$var wire 1 0' mux_2level_tapbuf_basis_input3_mem3_1_out [0] $end +$var wire 1 1' SYNOPSYS_UNCONNECTED_1 $end + +$scope module local_encoder2to3_0_ $end +$var wire 1 )# addr [0] $end +$var wire 1 *# addr [1] $end +$var wire 1 #' data [0] $end +$var wire 1 $' data [1] $end +$var wire 1 %' data [2] $end +$var wire 1 &' data_inv [0] $end +$var wire 1 '' data_inv [1] $end +$var wire 1 (' data_inv [2] $end + +$scope module U8 $end +$var wire 1 &' Y $end +$var wire 1 #' A $end +$var supply1 1 2' VPWR $end +$var supply0 1 3' VGND $end +$var supply1 1 4' VPB $end +$var supply0 1 5' VNB $end + +$scope module base $end +$var wire 1 &' Y $end +$var wire 1 #' A $end +$var wire 1 6' not0_out_Y $end +$upscope $end +$upscope $end + +$scope module U9 $end +$var wire 1 $' Y $end +$var wire 1 '' A $end +$var supply1 1 7' VPWR $end +$var supply0 1 8' VGND $end +$var supply1 1 9' VPB $end +$var supply0 1 :' VNB $end + +$scope module base $end +$var wire 1 $' Y $end +$var wire 1 '' A $end +$var wire 1 ;' not0_out_Y $end +$upscope $end +$upscope $end + +$scope module U10 $end +$var wire 1 '' Y $end +$var wire 1 )# A $end +$var wire 1 (' B $end +$var supply1 1 <' VPWR $end +$var supply0 1 =' VGND $end +$var supply1 1 >' VPB $end +$var supply0 1 ?' VNB $end + +$scope module base $end +$var wire 1 '' Y $end +$var wire 1 )# A $end +$var wire 1 (' B $end +$var wire 1 @' nand0_out_Y $end +$upscope $end +$upscope $end + +$scope module U11 $end +$var wire 1 (' Y $end +$var wire 1 %' A $end +$var supply1 1 A' VPWR $end +$var supply0 1 B' VGND $end +$var supply1 1 C' VPB $end +$var supply0 1 D' VNB $end + +$scope module base $end +$var wire 1 (' Y $end +$var wire 1 %' A $end +$var wire 1 E' not0_out_Y $end +$upscope $end +$upscope $end + +$scope module U12 $end +$var wire 1 #' Y $end +$var wire 1 %' A $end +$var wire 1 )# B $end +$var supply1 1 F' VPWR $end +$var supply0 1 G' VGND $end +$var supply1 1 H' VPB $end +$var supply0 1 I' VNB $end + +$scope module base $end +$var wire 1 #' Y $end +$var wire 1 %' A $end +$var wire 1 )# B $end +$var wire 1 J' nor0_out_Y $end +$upscope $end +$upscope $end + +$scope module FTB_5__4 $end +$var wire 1 %' X $end +$var wire 1 *# A $end +$var supply1 1 K' VPWR $end +$var supply0 1 L' VGND $end +$var supply1 1 M' VPB $end +$var supply0 1 N' VNB $end + +$scope module base $end +$var wire 1 %' X $end +$var wire 1 *# A $end +$var wire 1 O' buf0_out_X $end +$upscope $end +$upscope $end +$upscope $end + +$scope module local_encoder2to3_1_ $end +$var wire 1 +# addr [0] $end +$var wire 1 ,# addr [1] $end +$var wire 1 )' data [0] $end +$var wire 1 *' data [1] $end +$var wire 1 +' data [2] $end +$var wire 1 ,' data_inv [0] $end +$var wire 1 -' data_inv [1] $end +$var wire 1 .' data_inv [2] $end + +$scope module U8 $end +$var wire 1 ,' Y $end +$var wire 1 )' A $end +$var supply1 1 P' VPWR $end +$var supply0 1 Q' VGND $end +$var supply1 1 R' VPB $end +$var supply0 1 S' VNB $end + +$scope module base $end +$var wire 1 ,' Y $end +$var wire 1 )' A $end +$var wire 1 T' not0_out_Y $end +$upscope $end +$upscope $end + +$scope module U9 $end +$var wire 1 *' Y $end +$var wire 1 -' A $end +$var supply1 1 U' VPWR $end +$var supply0 1 V' VGND $end +$var supply1 1 W' VPB $end +$var supply0 1 X' VNB $end + +$scope module base $end +$var wire 1 *' Y $end +$var wire 1 -' A $end +$var wire 1 Y' not0_out_Y $end +$upscope $end +$upscope $end + +$scope module U10 $end +$var wire 1 -' Y $end +$var wire 1 +# A $end +$var wire 1 .' B $end +$var supply1 1 Z' VPWR $end +$var supply0 1 [' VGND $end +$var supply1 1 \' VPB $end +$var supply0 1 ]' VNB $end + +$scope module base $end +$var wire 1 -' Y $end +$var wire 1 +# A $end +$var wire 1 .' B $end +$var wire 1 ^' nand0_out_Y $end +$upscope $end +$upscope $end + +$scope module U11 $end +$var wire 1 .' Y $end +$var wire 1 +' A $end +$var supply1 1 _' VPWR $end +$var supply0 1 `' VGND $end +$var supply1 1 a' VPB $end +$var supply0 1 b' VNB $end + +$scope module base $end +$var wire 1 .' Y $end +$var wire 1 +' A $end +$var wire 1 c' not0_out_Y $end +$upscope $end +$upscope $end + +$scope module U12 $end +$var wire 1 )' Y $end +$var wire 1 +' A $end +$var wire 1 +# B $end +$var supply1 1 d' VPWR $end +$var supply0 1 e' VGND $end +$var supply1 1 f' VPB $end +$var supply0 1 g' VNB $end + +$scope module base $end +$var wire 1 )' Y $end +$var wire 1 +' A $end +$var wire 1 +# B $end +$var wire 1 h' nor0_out_Y $end +$upscope $end +$upscope $end + +$scope module FTB_6__5 $end +$var wire 1 +' X $end +$var wire 1 ,# A $end +$var supply1 1 i' VPWR $end +$var supply0 1 j' VGND $end +$var supply1 1 k' VPB $end +$var supply0 1 l' VNB $end + +$scope module base $end +$var wire 1 +' X $end +$var wire 1 ,# A $end +$var wire 1 m' buf0_out_X $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mux_l1_in_0_ $end +$var wire 1 I in [0] $end +$var wire 1 L in [1] $end +$var wire 1 O in [2] $end +$var wire 1 #' mem [0] $end +$var wire 1 $' mem [1] $end +$var wire 1 %' mem [2] $end +$var wire 1 &' mem_inv [0] $end +$var wire 1 '' mem_inv [1] $end +$var wire 1 (' mem_inv [2] $end +$var wire 1 /' out [0] $end + +$scope module scs8hd_muxinv3_1_0 $end +$var wire 1 /' Z $end +$var wire 1 I Q1 $end +$var wire 1 L Q2 $end +$var wire 1 O Q3 $end +$var wire 1 #' S0 $end +$var wire 1 &' S0B $end +$var wire 1 $' S1 $end +$var wire 1 '' S1B $end +$var wire 1 %' S2 $end +$var wire 1 (' S2B $end +$var wire 1 n' Q1__bar $end +$var wire 1 o' Q2__bar $end +$var wire 1 p' Q3__bar $end +$upscope $end +$upscope $end + +$scope module mux_l2_in_0_ $end +$var wire 1 /' in [0] $end +$var wire 1 S in [1] $end +$var wire 1 1' in [2] $end +$var wire 1 )' mem [0] $end +$var wire 1 *' mem [1] $end +$var wire 1 +' mem [2] $end +$var wire 1 ,' mem_inv [0] $end +$var wire 1 -' mem_inv [1] $end +$var wire 1 .' mem_inv [2] $end +$var wire 1 0' out [0] $end +$var wire 1 b# p0 $end + +$scope module scs8hd_muxinv3_1_0 $end +$var wire 1 0' Z $end +$var wire 1 /' Q1 $end +$var wire 1 S Q2 $end +$var wire 1 b# Q3 $end +$var wire 1 )' S0 $end +$var wire 1 ,' S0B $end +$var wire 1 *' S1 $end +$var wire 1 -' S1B $end +$var wire 1 +' S2 $end +$var wire 1 .' S2B $end +$var wire 1 q' Q1__bar $end +$var wire 1 r' Q2__bar $end +$var wire 1 s' Q3__bar $end +$upscope $end +$upscope $end + +$scope module BUFT_RR_89 $end +$var wire 1 y X $end +$var wire 1 0' A $end +$var supply1 1 t' VPWR $end +$var supply0 1 u' VGND $end +$var supply1 1 v' VPB $end +$var supply0 1 w' VNB $end + +$scope module base $end +$var wire 1 y X $end +$var wire 1 0' A $end +$var wire 1 x' buf0_out_X $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mux_bottom_track_7 $end +$var wire 1 G in [0] $end +$var wire 1 J in [1] $end +$var wire 1 M in [2] $end +$var wire 1 T in [3] $end +$var wire 1 -# sram [0] $end +$var wire 1 .# sram [1] $end +$var wire 1 /# sram [2] $end +$var wire 1 0# sram [3] $end +$var wire 1 c# sram_inv [0] $end +$var wire 1 d# sram_inv [1] $end +$var wire 1 e# sram_inv [2] $end +$var wire 1 f# sram_inv [3] $end +$var wire 1 z out [0] $end +$var wire 1 Y# p0 $end +$var wire 1 y' local_encoder2to3_0_data [0] $end +$var wire 1 z' local_encoder2to3_0_data [1] $end +$var wire 1 {' local_encoder2to3_0_data [2] $end +$var wire 1 |' local_encoder2to3_0_data_inv [0] $end +$var wire 1 }' local_encoder2to3_0_data_inv [1] $end +$var wire 1 ~' local_encoder2to3_0_data_inv [2] $end +$var wire 1 !( local_encoder2to3_1_data [0] $end +$var wire 1 "( local_encoder2to3_1_data [1] $end +$var wire 1 #( local_encoder2to3_1_data [2] $end +$var wire 1 $( local_encoder2to3_1_data_inv [0] $end +$var wire 1 %( local_encoder2to3_1_data_inv [1] $end +$var wire 1 &( local_encoder2to3_1_data_inv [2] $end +$var wire 1 '( mux_2level_tapbuf_basis_input3_mem3_0_out [0] $end +$var wire 1 (( mux_2level_tapbuf_basis_input3_mem3_1_out [0] $end +$var wire 1 )( SYNOPSYS_UNCONNECTED_1 $end +$var wire 1 *( BUF_net_91 $end + +$scope module local_encoder2to3_0_ $end +$var wire 1 -# addr [0] $end +$var wire 1 .# addr [1] $end +$var wire 1 y' data [0] $end +$var wire 1 z' data [1] $end +$var wire 1 {' data [2] $end +$var wire 1 |' data_inv [0] $end +$var wire 1 }' data_inv [1] $end +$var wire 1 ~' data_inv [2] $end + +$scope module U8 $end +$var wire 1 |' Y $end +$var wire 1 y' A $end +$var supply1 1 +( VPWR $end +$var supply0 1 ,( VGND $end +$var supply1 1 -( VPB $end +$var supply0 1 .( VNB $end + +$scope module base $end +$var wire 1 |' Y $end +$var wire 1 y' A $end +$var wire 1 /( not0_out_Y $end +$upscope $end +$upscope $end + +$scope module U9 $end +$var wire 1 z' Y $end +$var wire 1 }' A $end +$var supply1 1 0( VPWR $end +$var supply0 1 1( VGND $end +$var supply1 1 2( VPB $end +$var supply0 1 3( VNB $end + +$scope module base $end +$var wire 1 z' Y $end +$var wire 1 }' A $end +$var wire 1 4( not0_out_Y $end +$upscope $end +$upscope $end + +$scope module U10 $end +$var wire 1 }' Y $end +$var wire 1 -# A $end +$var wire 1 ~' B $end +$var supply1 1 5( VPWR $end +$var supply0 1 6( VGND $end +$var supply1 1 7( VPB $end +$var supply0 1 8( VNB $end + +$scope module base $end +$var wire 1 }' Y $end +$var wire 1 -# A $end +$var wire 1 ~' B $end +$var wire 1 9( nand0_out_Y $end +$upscope $end +$upscope $end + +$scope module U11 $end +$var wire 1 ~' Y $end +$var wire 1 {' A $end +$var supply1 1 :( VPWR $end +$var supply0 1 ;( VGND $end +$var supply1 1 <( VPB $end +$var supply0 1 =( VNB $end + +$scope module base $end +$var wire 1 ~' Y $end +$var wire 1 {' A $end +$var wire 1 >( not0_out_Y $end +$upscope $end +$upscope $end + +$scope module U12 $end +$var wire 1 y' Y $end +$var wire 1 {' A $end +$var wire 1 -# B $end +$var supply1 1 ?( VPWR $end +$var supply0 1 @( VGND $end +$var supply1 1 A( VPB $end +$var supply0 1 B( VNB $end + +$scope module base $end +$var wire 1 y' Y $end +$var wire 1 {' A $end +$var wire 1 -# B $end +$var wire 1 C( nor0_out_Y $end +$upscope $end +$upscope $end + +$scope module FTB_7__6 $end +$var wire 1 {' X $end +$var wire 1 .# A $end +$var supply1 1 D( VPWR $end +$var supply0 1 E( VGND $end +$var supply1 1 F( VPB $end +$var supply0 1 G( VNB $end + +$scope module base $end +$var wire 1 {' X $end +$var wire 1 .# A $end +$var wire 1 H( buf0_out_X $end +$upscope $end +$upscope $end +$upscope $end + +$scope module local_encoder2to3_1_ $end +$var wire 1 /# addr [0] $end +$var wire 1 0# addr [1] $end +$var wire 1 !( data [0] $end +$var wire 1 "( data [1] $end +$var wire 1 #( data [2] $end +$var wire 1 $( data_inv [0] $end +$var wire 1 %( data_inv [1] $end +$var wire 1 &( data_inv [2] $end + +$scope module U8 $end +$var wire 1 $( Y $end +$var wire 1 !( A $end +$var supply1 1 I( VPWR $end +$var supply0 1 J( VGND $end +$var supply1 1 K( VPB $end +$var supply0 1 L( VNB $end + +$scope module base $end +$var wire 1 $( Y $end +$var wire 1 !( A $end +$var wire 1 M( not0_out_Y $end +$upscope $end +$upscope $end + +$scope module U9 $end +$var wire 1 "( Y $end +$var wire 1 %( A $end +$var supply1 1 N( VPWR $end +$var supply0 1 O( VGND $end +$var supply1 1 P( VPB $end +$var supply0 1 Q( VNB $end + +$scope module base $end +$var wire 1 "( Y $end +$var wire 1 %( A $end +$var wire 1 R( not0_out_Y $end +$upscope $end +$upscope $end + +$scope module U10 $end +$var wire 1 %( Y $end +$var wire 1 /# A $end +$var wire 1 &( B $end +$var supply1 1 S( VPWR $end +$var supply0 1 T( VGND $end +$var supply1 1 U( VPB $end +$var supply0 1 V( VNB $end + +$scope module base $end +$var wire 1 %( Y $end +$var wire 1 /# A $end +$var wire 1 &( B $end +$var wire 1 W( nand0_out_Y $end +$upscope $end +$upscope $end + +$scope module U11 $end +$var wire 1 &( Y $end +$var wire 1 #( A $end +$var supply1 1 X( VPWR $end +$var supply0 1 Y( VGND $end +$var supply1 1 Z( VPB $end +$var supply0 1 [( VNB $end + +$scope module base $end +$var wire 1 &( Y $end +$var wire 1 #( A $end +$var wire 1 \( not0_out_Y $end +$upscope $end +$upscope $end + +$scope module U12 $end +$var wire 1 !( Y $end +$var wire 1 #( A $end +$var wire 1 /# B $end +$var supply1 1 ]( VPWR $end +$var supply0 1 ^( VGND $end +$var supply1 1 _( VPB $end +$var supply0 1 `( VNB $end + +$scope module base $end +$var wire 1 !( Y $end +$var wire 1 #( A $end +$var wire 1 /# B $end +$var wire 1 a( nor0_out_Y $end +$upscope $end +$upscope $end + +$scope module FTB_8__7 $end +$var wire 1 #( X $end +$var wire 1 0# A $end +$var supply1 1 b( VPWR $end +$var supply0 1 c( VGND $end +$var supply1 1 d( VPB $end +$var supply0 1 e( VNB $end + +$scope module base $end +$var wire 1 #( X $end +$var wire 1 0# A $end +$var wire 1 f( buf0_out_X $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mux_l1_in_0_ $end +$var wire 1 G in [0] $end +$var wire 1 J in [1] $end +$var wire 1 M in [2] $end +$var wire 1 y' mem [0] $end +$var wire 1 z' mem [1] $end +$var wire 1 {' mem [2] $end +$var wire 1 |' mem_inv [0] $end +$var wire 1 }' mem_inv [1] $end +$var wire 1 ~' mem_inv [2] $end +$var wire 1 '( out [0] $end + +$scope module scs8hd_muxinv3_1_0 $end +$var wire 1 '( Z $end +$var wire 1 G Q1 $end +$var wire 1 J Q2 $end +$var wire 1 M Q3 $end +$var wire 1 y' S0 $end +$var wire 1 |' S0B $end +$var wire 1 z' S1 $end +$var wire 1 }' S1B $end +$var wire 1 {' S2 $end +$var wire 1 ~' S2B $end +$var wire 1 g( Q1__bar $end +$var wire 1 h( Q2__bar $end +$var wire 1 i( Q3__bar $end +$upscope $end +$upscope $end + +$scope module mux_l2_in_0_ $end +$var wire 1 '( in [0] $end +$var wire 1 T in [1] $end +$var wire 1 )( in [2] $end +$var wire 1 !( mem [0] $end +$var wire 1 "( mem [1] $end +$var wire 1 #( mem [2] $end +$var wire 1 $( mem_inv [0] $end +$var wire 1 %( mem_inv [1] $end +$var wire 1 &( mem_inv [2] $end +$var wire 1 (( out [0] $end +$var wire 1 Y# p0 $end + +$scope module scs8hd_muxinv3_1_0 $end +$var wire 1 (( Z $end +$var wire 1 '( Q1 $end +$var wire 1 T Q2 $end +$var wire 1 Y# Q3 $end +$var wire 1 !( S0 $end +$var wire 1 $( S0B $end +$var wire 1 "( S1 $end +$var wire 1 %( S1B $end +$var wire 1 #( S2 $end +$var wire 1 &( S2B $end +$var wire 1 j( Q1__bar $end +$var wire 1 k( Q2__bar $end +$var wire 1 l( Q3__bar $end +$upscope $end +$upscope $end + +$scope module BINV_R_90 $end +$var wire 1 z Y $end +$var wire 1 *( A $end +$var supply1 1 m( VPWR $end +$var supply0 1 n( VGND $end +$var supply1 1 o( VPB $end +$var supply0 1 p( VNB $end + +$scope module base $end +$var wire 1 z Y $end +$var wire 1 *( A $end +$var wire 1 q( not0_out_Y $end +$upscope $end +$upscope $end + +$scope module BINV_R_91 $end +$var wire 1 *( Y $end +$var wire 1 (( A $end +$var supply1 1 r( VPWR $end +$var supply0 1 s( VGND $end +$var supply1 1 t( VPB $end +$var supply0 1 u( VNB $end + +$scope module base $end +$var wire 1 *( Y $end +$var wire 1 (( A $end +$var wire 1 v( not0_out_Y $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mux_bottom_track_9 $end +$var wire 1 H in [0] $end +$var wire 1 K in [1] $end +$var wire 1 N in [2] $end +$var wire 1 U in [3] $end +$var wire 1 1# sram [0] $end +$var wire 1 2# sram [1] $end +$var wire 1 3# sram [2] $end +$var wire 1 4# sram [3] $end +$var wire 1 g# sram_inv [0] $end +$var wire 1 h# sram_inv [1] $end +$var wire 1 i# sram_inv [2] $end +$var wire 1 j# sram_inv [3] $end +$var wire 1 { out [0] $end +$var wire 1 k# p0 $end +$var wire 1 w( local_encoder2to3_0_data [0] $end +$var wire 1 x( local_encoder2to3_0_data [1] $end +$var wire 1 y( local_encoder2to3_0_data [2] $end +$var wire 1 z( local_encoder2to3_0_data_inv [0] $end +$var wire 1 {( local_encoder2to3_0_data_inv [1] $end +$var wire 1 |( local_encoder2to3_0_data_inv [2] $end +$var wire 1 }( local_encoder2to3_1_data [0] $end +$var wire 1 ~( local_encoder2to3_1_data [1] $end +$var wire 1 !) local_encoder2to3_1_data [2] $end +$var wire 1 ") local_encoder2to3_1_data_inv [0] $end +$var wire 1 #) local_encoder2to3_1_data_inv [1] $end +$var wire 1 $) local_encoder2to3_1_data_inv [2] $end +$var wire 1 %) mux_2level_tapbuf_basis_input3_mem3_0_out [0] $end +$var wire 1 &) mux_2level_tapbuf_basis_input3_mem3_1_out [0] $end +$var wire 1 ') SYNOPSYS_UNCONNECTED_1 $end +$var wire 1 () BUF_net_93 $end + +$scope module local_encoder2to3_0_ $end +$var wire 1 1# addr [0] $end +$var wire 1 2# addr [1] $end +$var wire 1 w( data [0] $end +$var wire 1 x( data [1] $end +$var wire 1 y( data [2] $end +$var wire 1 z( data_inv [0] $end +$var wire 1 {( data_inv [1] $end +$var wire 1 |( data_inv [2] $end + +$scope module U8 $end +$var wire 1 z( Y $end +$var wire 1 w( A $end +$var supply1 1 )) VPWR $end +$var supply0 1 *) VGND $end +$var supply1 1 +) VPB $end +$var supply0 1 ,) VNB $end + +$scope module base $end +$var wire 1 z( Y $end +$var wire 1 w( A $end +$var wire 1 -) not0_out_Y $end +$upscope $end +$upscope $end + +$scope module U9 $end +$var wire 1 x( Y $end +$var wire 1 {( A $end +$var supply1 1 .) VPWR $end +$var supply0 1 /) VGND $end +$var supply1 1 0) VPB $end +$var supply0 1 1) VNB $end + +$scope module base $end +$var wire 1 x( Y $end +$var wire 1 {( A $end +$var wire 1 2) not0_out_Y $end +$upscope $end +$upscope $end + +$scope module U10 $end +$var wire 1 {( Y $end +$var wire 1 1# A $end +$var wire 1 |( B $end +$var supply1 1 3) VPWR $end +$var supply0 1 4) VGND $end +$var supply1 1 5) VPB $end +$var supply0 1 6) VNB $end + +$scope module base $end +$var wire 1 {( Y $end +$var wire 1 1# A $end +$var wire 1 |( B $end +$var wire 1 7) nand0_out_Y $end +$upscope $end +$upscope $end + +$scope module U11 $end +$var wire 1 |( Y $end +$var wire 1 y( A $end +$var supply1 1 8) VPWR $end +$var supply0 1 9) VGND $end +$var supply1 1 :) VPB $end +$var supply0 1 ;) VNB $end + +$scope module base $end +$var wire 1 |( Y $end +$var wire 1 y( A $end +$var wire 1 <) not0_out_Y $end +$upscope $end +$upscope $end + +$scope module U12 $end +$var wire 1 w( Y $end +$var wire 1 y( A $end +$var wire 1 1# B $end +$var supply1 1 =) VPWR $end +$var supply0 1 >) VGND $end +$var supply1 1 ?) VPB $end +$var supply0 1 @) VNB $end + +$scope module base $end +$var wire 1 w( Y $end +$var wire 1 y( A $end +$var wire 1 1# B $end +$var wire 1 A) nor0_out_Y $end +$upscope $end +$upscope $end + +$scope module FTB_9__8 $end +$var wire 1 y( X $end +$var wire 1 2# A $end +$var supply1 1 B) VPWR $end +$var supply0 1 C) VGND $end +$var supply1 1 D) VPB $end +$var supply0 1 E) VNB $end + +$scope module base $end +$var wire 1 y( X $end +$var wire 1 2# A $end +$var wire 1 F) buf0_out_X $end +$upscope $end +$upscope $end +$upscope $end + +$scope module local_encoder2to3_1_ $end +$var wire 1 3# addr [0] $end +$var wire 1 4# addr [1] $end +$var wire 1 }( data [0] $end +$var wire 1 ~( data [1] $end +$var wire 1 !) data [2] $end +$var wire 1 ") data_inv [0] $end +$var wire 1 #) data_inv [1] $end +$var wire 1 $) data_inv [2] $end + +$scope module U8 $end +$var wire 1 ") Y $end +$var wire 1 }( A $end +$var supply1 1 G) VPWR $end +$var supply0 1 H) VGND $end +$var supply1 1 I) VPB $end +$var supply0 1 J) VNB $end + +$scope module base $end +$var wire 1 ") Y $end +$var wire 1 }( A $end +$var wire 1 K) not0_out_Y $end +$upscope $end +$upscope $end + +$scope module U9 $end +$var wire 1 ~( Y $end +$var wire 1 #) A $end +$var supply1 1 L) VPWR $end +$var supply0 1 M) VGND $end +$var supply1 1 N) VPB $end +$var supply0 1 O) VNB $end + +$scope module base $end +$var wire 1 ~( Y $end +$var wire 1 #) A $end +$var wire 1 P) not0_out_Y $end +$upscope $end +$upscope $end + +$scope module U10 $end +$var wire 1 #) Y $end +$var wire 1 3# A $end +$var wire 1 $) B $end +$var supply1 1 Q) VPWR $end +$var supply0 1 R) VGND $end +$var supply1 1 S) VPB $end +$var supply0 1 T) VNB $end + +$scope module base $end +$var wire 1 #) Y $end +$var wire 1 3# A $end +$var wire 1 $) B $end +$var wire 1 U) nand0_out_Y $end +$upscope $end +$upscope $end + +$scope module U11 $end +$var wire 1 $) Y $end +$var wire 1 !) A $end +$var supply1 1 V) VPWR $end +$var supply0 1 W) VGND $end +$var supply1 1 X) VPB $end +$var supply0 1 Y) VNB $end + +$scope module base $end +$var wire 1 $) Y $end +$var wire 1 !) A $end +$var wire 1 Z) not0_out_Y $end +$upscope $end +$upscope $end + +$scope module U12 $end +$var wire 1 }( Y $end +$var wire 1 !) A $end +$var wire 1 3# B $end +$var supply1 1 [) VPWR $end +$var supply0 1 \) VGND $end +$var supply1 1 ]) VPB $end +$var supply0 1 ^) VNB $end + +$scope module base $end +$var wire 1 }( Y $end +$var wire 1 !) A $end +$var wire 1 3# B $end +$var wire 1 _) nor0_out_Y $end +$upscope $end +$upscope $end + +$scope module FTB_10__9 $end +$var wire 1 !) X $end +$var wire 1 4# A $end +$var supply1 1 `) VPWR $end +$var supply0 1 a) VGND $end +$var supply1 1 b) VPB $end +$var supply0 1 c) VNB $end + +$scope module base $end +$var wire 1 !) X $end +$var wire 1 4# A $end +$var wire 1 d) buf0_out_X $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mux_l1_in_0_ $end +$var wire 1 H in [0] $end +$var wire 1 K in [1] $end +$var wire 1 N in [2] $end +$var wire 1 w( mem [0] $end +$var wire 1 x( mem [1] $end +$var wire 1 y( mem [2] $end +$var wire 1 z( mem_inv [0] $end +$var wire 1 {( mem_inv [1] $end +$var wire 1 |( mem_inv [2] $end +$var wire 1 %) out [0] $end + +$scope module scs8hd_muxinv3_1_0 $end +$var wire 1 %) Z $end +$var wire 1 H Q1 $end +$var wire 1 K Q2 $end +$var wire 1 N Q3 $end +$var wire 1 w( S0 $end +$var wire 1 z( S0B $end +$var wire 1 x( S1 $end +$var wire 1 {( S1B $end +$var wire 1 y( S2 $end +$var wire 1 |( S2B $end +$var wire 1 e) Q1__bar $end +$var wire 1 f) Q2__bar $end +$var wire 1 g) Q3__bar $end +$upscope $end +$upscope $end + +$scope module mux_l2_in_0_ $end +$var wire 1 %) in [0] $end +$var wire 1 U in [1] $end +$var wire 1 ') in [2] $end +$var wire 1 }( mem [0] $end +$var wire 1 ~( mem [1] $end +$var wire 1 !) mem [2] $end +$var wire 1 ") mem_inv [0] $end +$var wire 1 #) mem_inv [1] $end +$var wire 1 $) mem_inv [2] $end +$var wire 1 &) out [0] $end +$var wire 1 k# p0 $end + +$scope module scs8hd_muxinv3_1_0 $end +$var wire 1 &) Z $end +$var wire 1 %) Q1 $end +$var wire 1 U Q2 $end +$var wire 1 k# Q3 $end +$var wire 1 }( S0 $end +$var wire 1 ") S0B $end +$var wire 1 ~( S1 $end +$var wire 1 #) S1B $end +$var wire 1 !) S2 $end +$var wire 1 $) S2B $end +$var wire 1 h) Q1__bar $end +$var wire 1 i) Q2__bar $end +$var wire 1 j) Q3__bar $end +$upscope $end +$upscope $end + +$scope module BINV_R_92 $end +$var wire 1 { Y $end +$var wire 1 () A $end +$var supply1 1 k) VPWR $end +$var supply0 1 l) VGND $end +$var supply1 1 m) VPB $end +$var supply0 1 n) VNB $end + +$scope module base $end +$var wire 1 { Y $end +$var wire 1 () A $end +$var wire 1 o) not0_out_Y $end +$upscope $end +$upscope $end + +$scope module BINV_R_93 $end +$var wire 1 () Y $end +$var wire 1 &) A $end +$var supply1 1 p) VPWR $end +$var supply0 1 q) VGND $end +$var supply1 1 r) VPB $end +$var supply0 1 s) VNB $end + +$scope module base $end +$var wire 1 () Y $end +$var wire 1 &) A $end +$var wire 1 t) not0_out_Y $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mux_bottom_track_11 $end +$var wire 1 I in [0] $end +$var wire 1 L in [1] $end +$var wire 1 O in [2] $end +$var wire 1 V in [3] $end +$var wire 1 5# sram [0] $end +$var wire 1 6# sram [1] $end +$var wire 1 7# sram [2] $end +$var wire 1 8# sram [3] $end +$var wire 1 l# sram_inv [0] $end +$var wire 1 m# sram_inv [1] $end +$var wire 1 n# sram_inv [2] $end +$var wire 1 o# sram_inv [3] $end +$var wire 1 | out [0] $end +$var wire 1 b# p0 $end +$var wire 1 u) local_encoder2to3_0_data [0] $end +$var wire 1 v) local_encoder2to3_0_data [1] $end +$var wire 1 w) local_encoder2to3_0_data [2] $end +$var wire 1 x) local_encoder2to3_0_data_inv [0] $end +$var wire 1 y) local_encoder2to3_0_data_inv [1] $end +$var wire 1 z) local_encoder2to3_0_data_inv [2] $end +$var wire 1 {) local_encoder2to3_1_data [0] $end +$var wire 1 |) local_encoder2to3_1_data [1] $end +$var wire 1 }) local_encoder2to3_1_data [2] $end +$var wire 1 ~) local_encoder2to3_1_data_inv [0] $end +$var wire 1 !* local_encoder2to3_1_data_inv [1] $end +$var wire 1 "* local_encoder2to3_1_data_inv [2] $end +$var wire 1 #* mux_2level_tapbuf_basis_input3_mem3_0_out [0] $end +$var wire 1 $* mux_2level_tapbuf_basis_input3_mem3_1_out [0] $end +$var wire 1 %* SYNOPSYS_UNCONNECTED_1 $end +$var wire 1 &* BUF_net_95 $end + +$scope module local_encoder2to3_0_ $end +$var wire 1 5# addr [0] $end +$var wire 1 6# addr [1] $end +$var wire 1 u) data [0] $end +$var wire 1 v) data [1] $end +$var wire 1 w) data [2] $end +$var wire 1 x) data_inv [0] $end +$var wire 1 y) data_inv [1] $end +$var wire 1 z) data_inv [2] $end + +$scope module U8 $end +$var wire 1 x) Y $end +$var wire 1 u) A $end +$var supply1 1 '* VPWR $end +$var supply0 1 (* VGND $end +$var supply1 1 )* VPB $end +$var supply0 1 ** VNB $end + +$scope module base $end +$var wire 1 x) Y $end +$var wire 1 u) A $end +$var wire 1 +* not0_out_Y $end +$upscope $end +$upscope $end + +$scope module U9 $end +$var wire 1 v) Y $end +$var wire 1 y) A $end +$var supply1 1 ,* VPWR $end +$var supply0 1 -* VGND $end +$var supply1 1 .* VPB $end +$var supply0 1 /* VNB $end + +$scope module base $end +$var wire 1 v) Y $end +$var wire 1 y) A $end +$var wire 1 0* not0_out_Y $end +$upscope $end +$upscope $end + +$scope module U10 $end +$var wire 1 y) Y $end +$var wire 1 5# A $end +$var wire 1 z) B $end +$var supply1 1 1* VPWR $end +$var supply0 1 2* VGND $end +$var supply1 1 3* VPB $end +$var supply0 1 4* VNB $end + +$scope module base $end +$var wire 1 y) Y $end +$var wire 1 5# A $end +$var wire 1 z) B $end +$var wire 1 5* nand0_out_Y $end +$upscope $end +$upscope $end + +$scope module U11 $end +$var wire 1 z) Y $end +$var wire 1 w) A $end +$var supply1 1 6* VPWR $end +$var supply0 1 7* VGND $end +$var supply1 1 8* VPB $end +$var supply0 1 9* VNB $end + +$scope module base $end +$var wire 1 z) Y $end +$var wire 1 w) A $end +$var wire 1 :* not0_out_Y $end +$upscope $end +$upscope $end + +$scope module U12 $end +$var wire 1 u) Y $end +$var wire 1 w) A $end +$var wire 1 5# B $end +$var supply1 1 ;* VPWR $end +$var supply0 1 <* VGND $end +$var supply1 1 =* VPB $end +$var supply0 1 >* VNB $end + +$scope module base $end +$var wire 1 u) Y $end +$var wire 1 w) A $end +$var wire 1 5# B $end +$var wire 1 ?* nor0_out_Y $end +$upscope $end +$upscope $end + +$scope module FTB_11__10 $end +$var wire 1 w) X $end +$var wire 1 6# A $end +$var supply1 1 @* VPWR $end +$var supply0 1 A* VGND $end +$var supply1 1 B* VPB $end +$var supply0 1 C* VNB $end + +$scope module base $end +$var wire 1 w) X $end +$var wire 1 6# A $end +$var wire 1 D* buf0_out_X $end +$upscope $end +$upscope $end +$upscope $end + +$scope module local_encoder2to3_1_ $end +$var wire 1 7# addr [0] $end +$var wire 1 8# addr [1] $end +$var wire 1 {) data [0] $end +$var wire 1 |) data [1] $end +$var wire 1 }) data [2] $end +$var wire 1 ~) data_inv [0] $end +$var wire 1 !* data_inv [1] $end +$var wire 1 "* data_inv [2] $end + +$scope module U8 $end +$var wire 1 ~) Y $end +$var wire 1 {) A $end +$var supply1 1 E* VPWR $end +$var supply0 1 F* VGND $end +$var supply1 1 G* VPB $end +$var supply0 1 H* VNB $end + +$scope module base $end +$var wire 1 ~) Y $end +$var wire 1 {) A $end +$var wire 1 I* not0_out_Y $end +$upscope $end +$upscope $end + +$scope module U9 $end +$var wire 1 |) Y $end +$var wire 1 !* A $end +$var supply1 1 J* VPWR $end +$var supply0 1 K* VGND $end +$var supply1 1 L* VPB $end +$var supply0 1 M* VNB $end + +$scope module base $end +$var wire 1 |) Y $end +$var wire 1 !* A $end +$var wire 1 N* not0_out_Y $end +$upscope $end +$upscope $end + +$scope module U10 $end +$var wire 1 !* Y $end +$var wire 1 7# A $end +$var wire 1 "* B $end +$var supply1 1 O* VPWR $end +$var supply0 1 P* VGND $end +$var supply1 1 Q* VPB $end +$var supply0 1 R* VNB $end + +$scope module base $end +$var wire 1 !* Y $end +$var wire 1 7# A $end +$var wire 1 "* B $end +$var wire 1 S* nand0_out_Y $end +$upscope $end +$upscope $end + +$scope module U11 $end +$var wire 1 "* Y $end +$var wire 1 }) A $end +$var supply1 1 T* VPWR $end +$var supply0 1 U* VGND $end +$var supply1 1 V* VPB $end +$var supply0 1 W* VNB $end + +$scope module base $end +$var wire 1 "* Y $end +$var wire 1 }) A $end +$var wire 1 X* not0_out_Y $end +$upscope $end +$upscope $end + +$scope module U12 $end +$var wire 1 {) Y $end +$var wire 1 }) A $end +$var wire 1 7# B $end +$var supply1 1 Y* VPWR $end +$var supply0 1 Z* VGND $end +$var supply1 1 [* VPB $end +$var supply0 1 \* VNB $end + +$scope module base $end +$var wire 1 {) Y $end +$var wire 1 }) A $end +$var wire 1 7# B $end +$var wire 1 ]* nor0_out_Y $end +$upscope $end +$upscope $end + +$scope module FTB_12__11 $end +$var wire 1 }) X $end +$var wire 1 8# A $end +$var supply1 1 ^* VPWR $end +$var supply0 1 _* VGND $end +$var supply1 1 `* VPB $end +$var supply0 1 a* VNB $end + +$scope module base $end +$var wire 1 }) X $end +$var wire 1 8# A $end +$var wire 1 b* buf0_out_X $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mux_l1_in_0_ $end +$var wire 1 I in [0] $end +$var wire 1 L in [1] $end +$var wire 1 O in [2] $end +$var wire 1 u) mem [0] $end +$var wire 1 v) mem [1] $end +$var wire 1 w) mem [2] $end +$var wire 1 x) mem_inv [0] $end +$var wire 1 y) mem_inv [1] $end +$var wire 1 z) mem_inv [2] $end +$var wire 1 #* out [0] $end + +$scope module scs8hd_muxinv3_1_0 $end +$var wire 1 #* Z $end +$var wire 1 I Q1 $end +$var wire 1 L Q2 $end +$var wire 1 O Q3 $end +$var wire 1 u) S0 $end +$var wire 1 x) S0B $end +$var wire 1 v) S1 $end +$var wire 1 y) S1B $end +$var wire 1 w) S2 $end +$var wire 1 z) S2B $end +$var wire 1 c* Q1__bar $end +$var wire 1 d* Q2__bar $end +$var wire 1 e* Q3__bar $end +$upscope $end +$upscope $end + +$scope module mux_l2_in_0_ $end +$var wire 1 #* in [0] $end +$var wire 1 V in [1] $end +$var wire 1 %* in [2] $end +$var wire 1 {) mem [0] $end +$var wire 1 |) mem [1] $end +$var wire 1 }) mem [2] $end +$var wire 1 ~) mem_inv [0] $end +$var wire 1 !* mem_inv [1] $end +$var wire 1 "* mem_inv [2] $end +$var wire 1 $* out [0] $end +$var wire 1 b# p0 $end + +$scope module scs8hd_muxinv3_1_0 $end +$var wire 1 $* Z $end +$var wire 1 #* Q1 $end +$var wire 1 V Q2 $end +$var wire 1 b# Q3 $end +$var wire 1 {) S0 $end +$var wire 1 ~) S0B $end +$var wire 1 |) S1 $end +$var wire 1 !* S1B $end +$var wire 1 }) S2 $end +$var wire 1 "* S2B $end +$var wire 1 f* Q1__bar $end +$var wire 1 g* Q2__bar $end +$var wire 1 h* Q3__bar $end +$upscope $end +$upscope $end + +$scope module BINV_R_94 $end +$var wire 1 | Y $end +$var wire 1 &* A $end +$var supply1 1 i* VPWR $end +$var supply0 1 j* VGND $end +$var supply1 1 k* VPB $end +$var supply0 1 l* VNB $end + +$scope module base $end +$var wire 1 | Y $end +$var wire 1 &* A $end +$var wire 1 m* not0_out_Y $end +$upscope $end +$upscope $end + +$scope module BINV_R_95 $end +$var wire 1 &* Y $end +$var wire 1 $* A $end +$var supply1 1 n* VPWR $end +$var supply0 1 o* VGND $end +$var supply1 1 p* VPB $end +$var supply0 1 q* VNB $end + +$scope module base $end +$var wire 1 &* Y $end +$var wire 1 $* A $end +$var wire 1 r* not0_out_Y $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mux_left_track_1 $end +$var wire 1 F in [0] $end +$var wire 1 n in [1] $end +$var wire 1 q in [2] $end +$var wire 1 t in [3] $end +$var wire 1 9# sram [0] $end +$var wire 1 :# sram [1] $end +$var wire 1 ;# sram [2] $end +$var wire 1 <# sram [3] $end +$var wire 1 p# sram_inv [0] $end +$var wire 1 q# sram_inv [1] $end +$var wire 1 r# sram_inv [2] $end +$var wire 1 s# sram_inv [3] $end +$var wire 1 7! out [0] $end +$var wire 1 b# p0 $end +$var wire 1 s* local_encoder2to3_0_data [0] $end +$var wire 1 t* local_encoder2to3_0_data [1] $end +$var wire 1 u* local_encoder2to3_0_data [2] $end +$var wire 1 v* local_encoder2to3_0_data_inv [0] $end +$var wire 1 w* local_encoder2to3_0_data_inv [1] $end +$var wire 1 x* local_encoder2to3_0_data_inv [2] $end +$var wire 1 y* local_encoder2to3_1_data [0] $end +$var wire 1 z* local_encoder2to3_1_data [1] $end +$var wire 1 {* local_encoder2to3_1_data [2] $end +$var wire 1 |* local_encoder2to3_1_data_inv [0] $end +$var wire 1 }* local_encoder2to3_1_data_inv [1] $end +$var wire 1 ~* local_encoder2to3_1_data_inv [2] $end +$var wire 1 !+ mux_2level_tapbuf_basis_input3_mem3_0_out [0] $end +$var wire 1 "+ mux_2level_tapbuf_basis_input3_mem3_1_out [0] $end +$var wire 1 #+ SYNOPSYS_UNCONNECTED_1 $end +$var wire 1 $+ BUF_net_97 $end + +$scope module local_encoder2to3_0_ $end +$var wire 1 9# addr [0] $end +$var wire 1 :# addr [1] $end +$var wire 1 s* data [0] $end +$var wire 1 t* data [1] $end +$var wire 1 u* data [2] $end +$var wire 1 v* data_inv [0] $end +$var wire 1 w* data_inv [1] $end +$var wire 1 x* data_inv [2] $end + +$scope module U8 $end +$var wire 1 v* Y $end +$var wire 1 s* A $end +$var supply1 1 %+ VPWR $end +$var supply0 1 &+ VGND $end +$var supply1 1 '+ VPB $end +$var supply0 1 (+ VNB $end + +$scope module base $end +$var wire 1 v* Y $end +$var wire 1 s* A $end +$var wire 1 )+ not0_out_Y $end +$upscope $end +$upscope $end + +$scope module U9 $end +$var wire 1 t* Y $end +$var wire 1 w* A $end +$var supply1 1 *+ VPWR $end +$var supply0 1 ++ VGND $end +$var supply1 1 ,+ VPB $end +$var supply0 1 -+ VNB $end + +$scope module base $end +$var wire 1 t* Y $end +$var wire 1 w* A $end +$var wire 1 .+ not0_out_Y $end +$upscope $end +$upscope $end + +$scope module U10 $end +$var wire 1 w* Y $end +$var wire 1 9# A $end +$var wire 1 x* B $end +$var supply1 1 /+ VPWR $end +$var supply0 1 0+ VGND $end +$var supply1 1 1+ VPB $end +$var supply0 1 2+ VNB $end + +$scope module base $end +$var wire 1 w* Y $end +$var wire 1 9# A $end +$var wire 1 x* B $end +$var wire 1 3+ nand0_out_Y $end +$upscope $end +$upscope $end + +$scope module U11 $end +$var wire 1 x* Y $end +$var wire 1 u* A $end +$var supply1 1 4+ VPWR $end +$var supply0 1 5+ VGND $end +$var supply1 1 6+ VPB $end +$var supply0 1 7+ VNB $end + +$scope module base $end +$var wire 1 x* Y $end +$var wire 1 u* A $end +$var wire 1 8+ not0_out_Y $end +$upscope $end +$upscope $end + +$scope module U12 $end +$var wire 1 s* Y $end +$var wire 1 u* A $end +$var wire 1 9# B $end +$var supply1 1 9+ VPWR $end +$var supply0 1 :+ VGND $end +$var supply1 1 ;+ VPB $end +$var supply0 1 <+ VNB $end + +$scope module base $end +$var wire 1 s* Y $end +$var wire 1 u* A $end +$var wire 1 9# B $end +$var wire 1 =+ nor0_out_Y $end +$upscope $end +$upscope $end + +$scope module FTB_13__12 $end +$var wire 1 u* X $end +$var wire 1 :# A $end +$var supply1 1 >+ VPWR $end +$var supply0 1 ?+ VGND $end +$var supply1 1 @+ VPB $end +$var supply0 1 A+ VNB $end + +$scope module base $end +$var wire 1 u* X $end +$var wire 1 :# A $end +$var wire 1 B+ buf0_out_X $end +$upscope $end +$upscope $end +$upscope $end + +$scope module local_encoder2to3_1_ $end +$var wire 1 ;# addr [0] $end +$var wire 1 <# addr [1] $end +$var wire 1 y* data [0] $end +$var wire 1 z* data [1] $end +$var wire 1 {* data [2] $end +$var wire 1 |* data_inv [0] $end +$var wire 1 }* data_inv [1] $end +$var wire 1 ~* data_inv [2] $end + +$scope module U8 $end +$var wire 1 |* Y $end +$var wire 1 y* A $end +$var supply1 1 C+ VPWR $end +$var supply0 1 D+ VGND $end +$var supply1 1 E+ VPB $end +$var supply0 1 F+ VNB $end + +$scope module base $end +$var wire 1 |* Y $end +$var wire 1 y* A $end +$var wire 1 G+ not0_out_Y $end +$upscope $end +$upscope $end + +$scope module U9 $end +$var wire 1 z* Y $end +$var wire 1 }* A $end +$var supply1 1 H+ VPWR $end +$var supply0 1 I+ VGND $end +$var supply1 1 J+ VPB $end +$var supply0 1 K+ VNB $end + +$scope module base $end +$var wire 1 z* Y $end +$var wire 1 }* A $end +$var wire 1 L+ not0_out_Y $end +$upscope $end +$upscope $end + +$scope module U10 $end +$var wire 1 }* Y $end +$var wire 1 ;# A $end +$var wire 1 ~* B $end +$var supply1 1 M+ VPWR $end +$var supply0 1 N+ VGND $end +$var supply1 1 O+ VPB $end +$var supply0 1 P+ VNB $end + +$scope module base $end +$var wire 1 }* Y $end +$var wire 1 ;# A $end +$var wire 1 ~* B $end +$var wire 1 Q+ nand0_out_Y $end +$upscope $end +$upscope $end + +$scope module U11 $end +$var wire 1 ~* Y $end +$var wire 1 {* A $end +$var supply1 1 R+ VPWR $end +$var supply0 1 S+ VGND $end +$var supply1 1 T+ VPB $end +$var supply0 1 U+ VNB $end + +$scope module base $end +$var wire 1 ~* Y $end +$var wire 1 {* A $end +$var wire 1 V+ not0_out_Y $end +$upscope $end +$upscope $end + +$scope module U12 $end +$var wire 1 y* Y $end +$var wire 1 {* A $end +$var wire 1 ;# B $end +$var supply1 1 W+ VPWR $end +$var supply0 1 X+ VGND $end +$var supply1 1 Y+ VPB $end +$var supply0 1 Z+ VNB $end + +$scope module base $end +$var wire 1 y* Y $end +$var wire 1 {* A $end +$var wire 1 ;# B $end +$var wire 1 [+ nor0_out_Y $end +$upscope $end +$upscope $end + +$scope module FTB_14__13 $end +$var wire 1 {* X $end +$var wire 1 <# A $end +$var supply1 1 \+ VPWR $end +$var supply0 1 ]+ VGND $end +$var supply1 1 ^+ VPB $end +$var supply0 1 _+ VNB $end + +$scope module base $end +$var wire 1 {* X $end +$var wire 1 <# A $end +$var wire 1 `+ buf0_out_X $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mux_l1_in_0_ $end +$var wire 1 F in [0] $end +$var wire 1 n in [1] $end +$var wire 1 q in [2] $end +$var wire 1 s* mem [0] $end +$var wire 1 t* mem [1] $end +$var wire 1 u* mem [2] $end +$var wire 1 v* mem_inv [0] $end +$var wire 1 w* mem_inv [1] $end +$var wire 1 x* mem_inv [2] $end +$var wire 1 !+ out [0] $end + +$scope module scs8hd_muxinv3_1_0 $end +$var wire 1 !+ Z $end +$var wire 1 F Q1 $end +$var wire 1 n Q2 $end +$var wire 1 q Q3 $end +$var wire 1 s* S0 $end +$var wire 1 v* S0B $end +$var wire 1 t* S1 $end +$var wire 1 w* S1B $end +$var wire 1 u* S2 $end +$var wire 1 x* S2B $end +$var wire 1 a+ Q1__bar $end +$var wire 1 b+ Q2__bar $end +$var wire 1 c+ Q3__bar $end +$upscope $end +$upscope $end + +$scope module mux_l2_in_0_ $end +$var wire 1 !+ in [0] $end +$var wire 1 t in [1] $end +$var wire 1 #+ in [2] $end +$var wire 1 y* mem [0] $end +$var wire 1 z* mem [1] $end +$var wire 1 {* mem [2] $end +$var wire 1 |* mem_inv [0] $end +$var wire 1 }* mem_inv [1] $end +$var wire 1 ~* mem_inv [2] $end +$var wire 1 "+ out [0] $end +$var wire 1 b# p0 $end + +$scope module scs8hd_muxinv3_1_0 $end +$var wire 1 "+ Z $end +$var wire 1 !+ Q1 $end +$var wire 1 t Q2 $end +$var wire 1 b# Q3 $end +$var wire 1 y* S0 $end +$var wire 1 |* S0B $end +$var wire 1 z* S1 $end +$var wire 1 }* S1B $end +$var wire 1 {* S2 $end +$var wire 1 ~* S2B $end +$var wire 1 d+ Q1__bar $end +$var wire 1 e+ Q2__bar $end +$var wire 1 f+ Q3__bar $end +$upscope $end +$upscope $end + +$scope module BINV_R_96 $end +$var wire 1 7! Y $end +$var wire 1 $+ A $end +$var supply1 1 g+ VPWR $end +$var supply0 1 h+ VGND $end +$var supply1 1 i+ VPB $end +$var supply0 1 j+ VNB $end + +$scope module base $end +$var wire 1 7! Y $end +$var wire 1 $+ A $end +$var wire 1 k+ not0_out_Y $end +$upscope $end +$upscope $end + +$scope module BINV_R_97 $end +$var wire 1 $+ Y $end +$var wire 1 "+ A $end +$var supply1 1 l+ VPWR $end +$var supply0 1 m+ VGND $end +$var supply1 1 n+ VPB $end +$var supply0 1 o+ VNB $end + +$scope module base $end +$var wire 1 $+ Y $end +$var wire 1 "+ A $end +$var wire 1 p+ not0_out_Y $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mux_left_track_3 $end +$var wire 1 ) in [0] $end +$var wire 1 o in [1] $end +$var wire 1 r in [2] $end +$var wire 1 u in [3] $end +$var wire 1 =# sram [0] $end +$var wire 1 ># sram [1] $end +$var wire 1 ?# sram [2] $end +$var wire 1 @# sram [3] $end +$var wire 1 t# sram_inv [0] $end +$var wire 1 u# sram_inv [1] $end +$var wire 1 v# sram_inv [2] $end +$var wire 1 w# sram_inv [3] $end +$var wire 1 8! out [0] $end +$var wire 1 b# p0 $end +$var wire 1 q+ local_encoder2to3_0_data [0] $end +$var wire 1 r+ local_encoder2to3_0_data [1] $end +$var wire 1 s+ local_encoder2to3_0_data [2] $end +$var wire 1 t+ local_encoder2to3_0_data_inv [0] $end +$var wire 1 u+ local_encoder2to3_0_data_inv [1] $end +$var wire 1 v+ local_encoder2to3_0_data_inv [2] $end +$var wire 1 w+ local_encoder2to3_1_data [0] $end +$var wire 1 x+ local_encoder2to3_1_data [1] $end +$var wire 1 y+ local_encoder2to3_1_data [2] $end +$var wire 1 z+ local_encoder2to3_1_data_inv [0] $end +$var wire 1 {+ local_encoder2to3_1_data_inv [1] $end +$var wire 1 |+ local_encoder2to3_1_data_inv [2] $end +$var wire 1 }+ mux_2level_tapbuf_basis_input3_mem3_0_out [0] $end +$var wire 1 ~+ mux_2level_tapbuf_basis_input3_mem3_1_out [0] $end +$var wire 1 !, SYNOPSYS_UNCONNECTED_1 $end +$var wire 1 ", BUF_net_99 $end + +$scope module local_encoder2to3_0_ $end +$var wire 1 =# addr [0] $end +$var wire 1 ># addr [1] $end +$var wire 1 q+ data [0] $end +$var wire 1 r+ data [1] $end +$var wire 1 s+ data [2] $end +$var wire 1 t+ data_inv [0] $end +$var wire 1 u+ data_inv [1] $end +$var wire 1 v+ data_inv [2] $end + +$scope module U8 $end +$var wire 1 t+ Y $end +$var wire 1 q+ A $end +$var supply1 1 #, VPWR $end +$var supply0 1 $, VGND $end +$var supply1 1 %, VPB $end +$var supply0 1 &, VNB $end + +$scope module base $end +$var wire 1 t+ Y $end +$var wire 1 q+ A $end +$var wire 1 ', not0_out_Y $end +$upscope $end +$upscope $end + +$scope module U9 $end +$var wire 1 r+ Y $end +$var wire 1 u+ A $end +$var supply1 1 (, VPWR $end +$var supply0 1 ), VGND $end +$var supply1 1 *, VPB $end +$var supply0 1 +, VNB $end + +$scope module base $end +$var wire 1 r+ Y $end +$var wire 1 u+ A $end +$var wire 1 ,, not0_out_Y $end +$upscope $end +$upscope $end + +$scope module U10 $end +$var wire 1 u+ Y $end +$var wire 1 =# A $end +$var wire 1 v+ B $end +$var supply1 1 -, VPWR $end +$var supply0 1 ., VGND $end +$var supply1 1 /, VPB $end +$var supply0 1 0, VNB $end + +$scope module base $end +$var wire 1 u+ Y $end +$var wire 1 =# A $end +$var wire 1 v+ B $end +$var wire 1 1, nand0_out_Y $end +$upscope $end +$upscope $end + +$scope module U11 $end +$var wire 1 v+ Y $end +$var wire 1 s+ A $end +$var supply1 1 2, VPWR $end +$var supply0 1 3, VGND $end +$var supply1 1 4, VPB $end +$var supply0 1 5, VNB $end + +$scope module base $end +$var wire 1 v+ Y $end +$var wire 1 s+ A $end +$var wire 1 6, not0_out_Y $end +$upscope $end +$upscope $end + +$scope module U12 $end +$var wire 1 q+ Y $end +$var wire 1 s+ A $end +$var wire 1 =# B $end +$var supply1 1 7, VPWR $end +$var supply0 1 8, VGND $end +$var supply1 1 9, VPB $end +$var supply0 1 :, VNB $end + +$scope module base $end +$var wire 1 q+ Y $end +$var wire 1 s+ A $end +$var wire 1 =# B $end +$var wire 1 ;, nor0_out_Y $end +$upscope $end +$upscope $end + +$scope module FTB_15__14 $end +$var wire 1 s+ X $end +$var wire 1 ># A $end +$var supply1 1 <, VPWR $end +$var supply0 1 =, VGND $end +$var supply1 1 >, VPB $end +$var supply0 1 ?, VNB $end + +$scope module base $end +$var wire 1 s+ X $end +$var wire 1 ># A $end +$var wire 1 @, buf0_out_X $end +$upscope $end +$upscope $end +$upscope $end + +$scope module local_encoder2to3_1_ $end +$var wire 1 ?# addr [0] $end +$var wire 1 @# addr [1] $end +$var wire 1 w+ data [0] $end +$var wire 1 x+ data [1] $end +$var wire 1 y+ data [2] $end +$var wire 1 z+ data_inv [0] $end +$var wire 1 {+ data_inv [1] $end +$var wire 1 |+ data_inv [2] $end + +$scope module U8 $end +$var wire 1 z+ Y $end +$var wire 1 w+ A $end +$var supply1 1 A, VPWR $end +$var supply0 1 B, VGND $end +$var supply1 1 C, VPB $end +$var supply0 1 D, VNB $end + +$scope module base $end +$var wire 1 z+ Y $end +$var wire 1 w+ A $end +$var wire 1 E, not0_out_Y $end +$upscope $end +$upscope $end + +$scope module U9 $end +$var wire 1 x+ Y $end +$var wire 1 {+ A $end +$var supply1 1 F, VPWR $end +$var supply0 1 G, VGND $end +$var supply1 1 H, VPB $end +$var supply0 1 I, VNB $end + +$scope module base $end +$var wire 1 x+ Y $end +$var wire 1 {+ A $end +$var wire 1 J, not0_out_Y $end +$upscope $end +$upscope $end + +$scope module U10 $end +$var wire 1 {+ Y $end +$var wire 1 ?# A $end +$var wire 1 |+ B $end +$var supply1 1 K, VPWR $end +$var supply0 1 L, VGND $end +$var supply1 1 M, VPB $end +$var supply0 1 N, VNB $end + +$scope module base $end +$var wire 1 {+ Y $end +$var wire 1 ?# A $end +$var wire 1 |+ B $end +$var wire 1 O, nand0_out_Y $end +$upscope $end +$upscope $end + +$scope module U11 $end +$var wire 1 |+ Y $end +$var wire 1 y+ A $end +$var supply1 1 P, VPWR $end +$var supply0 1 Q, VGND $end +$var supply1 1 R, VPB $end +$var supply0 1 S, VNB $end + +$scope module base $end +$var wire 1 |+ Y $end +$var wire 1 y+ A $end +$var wire 1 T, not0_out_Y $end +$upscope $end +$upscope $end + +$scope module U12 $end +$var wire 1 w+ Y $end +$var wire 1 y+ A $end +$var wire 1 ?# B $end +$var supply1 1 U, VPWR $end +$var supply0 1 V, VGND $end +$var supply1 1 W, VPB $end +$var supply0 1 X, VNB $end + +$scope module base $end +$var wire 1 w+ Y $end +$var wire 1 y+ A $end +$var wire 1 ?# B $end +$var wire 1 Y, nor0_out_Y $end +$upscope $end +$upscope $end + +$scope module FTB_16__15 $end +$var wire 1 y+ X $end +$var wire 1 @# A $end +$var supply1 1 Z, VPWR $end +$var supply0 1 [, VGND $end +$var supply1 1 \, VPB $end +$var supply0 1 ], VNB $end + +$scope module base $end +$var wire 1 y+ X $end +$var wire 1 @# A $end +$var wire 1 ^, buf0_out_X $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mux_l1_in_0_ $end +$var wire 1 ) in [0] $end +$var wire 1 o in [1] $end +$var wire 1 r in [2] $end +$var wire 1 q+ mem [0] $end +$var wire 1 r+ mem [1] $end +$var wire 1 s+ mem [2] $end +$var wire 1 t+ mem_inv [0] $end +$var wire 1 u+ mem_inv [1] $end +$var wire 1 v+ mem_inv [2] $end +$var wire 1 }+ out [0] $end + +$scope module scs8hd_muxinv3_1_0 $end +$var wire 1 }+ Z $end +$var wire 1 ) Q1 $end +$var wire 1 o Q2 $end +$var wire 1 r Q3 $end +$var wire 1 q+ S0 $end +$var wire 1 t+ S0B $end +$var wire 1 r+ S1 $end +$var wire 1 u+ S1B $end +$var wire 1 s+ S2 $end +$var wire 1 v+ S2B $end +$var wire 1 _, Q1__bar $end +$var wire 1 `, Q2__bar $end +$var wire 1 a, Q3__bar $end +$upscope $end +$upscope $end + +$scope module mux_l2_in_0_ $end +$var wire 1 }+ in [0] $end +$var wire 1 u in [1] $end +$var wire 1 !, in [2] $end +$var wire 1 w+ mem [0] $end +$var wire 1 x+ mem [1] $end +$var wire 1 y+ mem [2] $end +$var wire 1 z+ mem_inv [0] $end +$var wire 1 {+ mem_inv [1] $end +$var wire 1 |+ mem_inv [2] $end +$var wire 1 ~+ out [0] $end +$var wire 1 b# p0 $end + +$scope module scs8hd_muxinv3_1_0 $end +$var wire 1 ~+ Z $end +$var wire 1 }+ Q1 $end +$var wire 1 u Q2 $end +$var wire 1 b# Q3 $end +$var wire 1 w+ S0 $end +$var wire 1 z+ S0B $end +$var wire 1 x+ S1 $end +$var wire 1 {+ S1B $end +$var wire 1 y+ S2 $end +$var wire 1 |+ S2B $end +$var wire 1 b, Q1__bar $end +$var wire 1 c, Q2__bar $end +$var wire 1 d, Q3__bar $end +$upscope $end +$upscope $end + +$scope module BINV_R_98 $end +$var wire 1 8! Y $end +$var wire 1 ", A $end +$var supply1 1 e, VPWR $end +$var supply0 1 f, VGND $end +$var supply1 1 g, VPB $end +$var supply0 1 h, VNB $end + +$scope module base $end +$var wire 1 8! Y $end +$var wire 1 ", A $end +$var wire 1 i, not0_out_Y $end +$upscope $end +$upscope $end + +$scope module BINV_R_99 $end +$var wire 1 ", Y $end +$var wire 1 ~+ A $end +$var supply1 1 j, VPWR $end +$var supply0 1 k, VGND $end +$var supply1 1 l, VPB $end +$var supply0 1 m, VNB $end + +$scope module base $end +$var wire 1 ", Y $end +$var wire 1 ~+ A $end +$var wire 1 n, not0_out_Y $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mux_left_track_5 $end +$var wire 1 * in [0] $end +$var wire 1 p in [1] $end +$var wire 1 s in [2] $end +$var wire 1 v in [3] $end +$var wire 1 A# sram [0] $end +$var wire 1 B# sram [1] $end +$var wire 1 C# sram [2] $end +$var wire 1 D# sram [3] $end +$var wire 1 x# sram_inv [0] $end +$var wire 1 y# sram_inv [1] $end +$var wire 1 z# sram_inv [2] $end +$var wire 1 {# sram_inv [3] $end +$var wire 1 9! out [0] $end +$var wire 1 b# p0 $end +$var wire 1 o, local_encoder2to3_0_data [0] $end +$var wire 1 p, local_encoder2to3_0_data [1] $end +$var wire 1 q, local_encoder2to3_0_data [2] $end +$var wire 1 r, local_encoder2to3_0_data_inv [0] $end +$var wire 1 s, local_encoder2to3_0_data_inv [1] $end +$var wire 1 t, local_encoder2to3_0_data_inv [2] $end +$var wire 1 u, local_encoder2to3_1_data [0] $end +$var wire 1 v, local_encoder2to3_1_data [1] $end +$var wire 1 w, local_encoder2to3_1_data [2] $end +$var wire 1 x, local_encoder2to3_1_data_inv [0] $end +$var wire 1 y, local_encoder2to3_1_data_inv [1] $end +$var wire 1 z, local_encoder2to3_1_data_inv [2] $end +$var wire 1 {, mux_2level_tapbuf_basis_input3_mem3_0_out [0] $end +$var wire 1 |, mux_2level_tapbuf_basis_input3_mem3_1_out [0] $end +$var wire 1 }, SYNOPSYS_UNCONNECTED_1 $end +$var wire 1 ~, BUF_net_101 $end + +$scope module local_encoder2to3_0_ $end +$var wire 1 A# addr [0] $end +$var wire 1 B# addr [1] $end +$var wire 1 o, data [0] $end +$var wire 1 p, data [1] $end +$var wire 1 q, data [2] $end +$var wire 1 r, data_inv [0] $end +$var wire 1 s, data_inv [1] $end +$var wire 1 t, data_inv [2] $end + +$scope module U8 $end +$var wire 1 r, Y $end +$var wire 1 o, A $end +$var supply1 1 !- VPWR $end +$var supply0 1 "- VGND $end +$var supply1 1 #- VPB $end +$var supply0 1 $- VNB $end + +$scope module base $end +$var wire 1 r, Y $end +$var wire 1 o, A $end +$var wire 1 %- not0_out_Y $end +$upscope $end +$upscope $end + +$scope module U9 $end +$var wire 1 p, Y $end +$var wire 1 s, A $end +$var supply1 1 &- VPWR $end +$var supply0 1 '- VGND $end +$var supply1 1 (- VPB $end +$var supply0 1 )- VNB $end + +$scope module base $end +$var wire 1 p, Y $end +$var wire 1 s, A $end +$var wire 1 *- not0_out_Y $end +$upscope $end +$upscope $end + +$scope module U10 $end +$var wire 1 s, Y $end +$var wire 1 A# A $end +$var wire 1 t, B $end +$var supply1 1 +- VPWR $end +$var supply0 1 ,- VGND $end +$var supply1 1 -- VPB $end +$var supply0 1 .- VNB $end + +$scope module base $end +$var wire 1 s, Y $end +$var wire 1 A# A $end +$var wire 1 t, B $end +$var wire 1 /- nand0_out_Y $end +$upscope $end +$upscope $end + +$scope module U11 $end +$var wire 1 t, Y $end +$var wire 1 q, A $end +$var supply1 1 0- VPWR $end +$var supply0 1 1- VGND $end +$var supply1 1 2- VPB $end +$var supply0 1 3- VNB $end + +$scope module base $end +$var wire 1 t, Y $end +$var wire 1 q, A $end +$var wire 1 4- not0_out_Y $end +$upscope $end +$upscope $end + +$scope module U12 $end +$var wire 1 o, Y $end +$var wire 1 q, A $end +$var wire 1 A# B $end +$var supply1 1 5- VPWR $end +$var supply0 1 6- VGND $end +$var supply1 1 7- VPB $end +$var supply0 1 8- VNB $end + +$scope module base $end +$var wire 1 o, Y $end +$var wire 1 q, A $end +$var wire 1 A# B $end +$var wire 1 9- nor0_out_Y $end +$upscope $end +$upscope $end + +$scope module FTB_17__16 $end +$var wire 1 q, X $end +$var wire 1 B# A $end +$var supply1 1 :- VPWR $end +$var supply0 1 ;- VGND $end +$var supply1 1 <- VPB $end +$var supply0 1 =- VNB $end + +$scope module base $end +$var wire 1 q, X $end +$var wire 1 B# A $end +$var wire 1 >- buf0_out_X $end +$upscope $end +$upscope $end +$upscope $end + +$scope module local_encoder2to3_1_ $end +$var wire 1 C# addr [0] $end +$var wire 1 D# addr [1] $end +$var wire 1 u, data [0] $end +$var wire 1 v, data [1] $end +$var wire 1 w, data [2] $end +$var wire 1 x, data_inv [0] $end +$var wire 1 y, data_inv [1] $end +$var wire 1 z, data_inv [2] $end + +$scope module U8 $end +$var wire 1 x, Y $end +$var wire 1 u, A $end +$var supply1 1 ?- VPWR $end +$var supply0 1 @- VGND $end +$var supply1 1 A- VPB $end +$var supply0 1 B- VNB $end + +$scope module base $end +$var wire 1 x, Y $end +$var wire 1 u, A $end +$var wire 1 C- not0_out_Y $end +$upscope $end +$upscope $end + +$scope module U9 $end +$var wire 1 v, Y $end +$var wire 1 y, A $end +$var supply1 1 D- VPWR $end +$var supply0 1 E- VGND $end +$var supply1 1 F- VPB $end +$var supply0 1 G- VNB $end + +$scope module base $end +$var wire 1 v, Y $end +$var wire 1 y, A $end +$var wire 1 H- not0_out_Y $end +$upscope $end +$upscope $end + +$scope module U10 $end +$var wire 1 y, Y $end +$var wire 1 C# A $end +$var wire 1 z, B $end +$var supply1 1 I- VPWR $end +$var supply0 1 J- VGND $end +$var supply1 1 K- VPB $end +$var supply0 1 L- VNB $end + +$scope module base $end +$var wire 1 y, Y $end +$var wire 1 C# A $end +$var wire 1 z, B $end +$var wire 1 M- nand0_out_Y $end +$upscope $end +$upscope $end + +$scope module U11 $end +$var wire 1 z, Y $end +$var wire 1 w, A $end +$var supply1 1 N- VPWR $end +$var supply0 1 O- VGND $end +$var supply1 1 P- VPB $end +$var supply0 1 Q- VNB $end + +$scope module base $end +$var wire 1 z, Y $end +$var wire 1 w, A $end +$var wire 1 R- not0_out_Y $end +$upscope $end +$upscope $end + +$scope module U12 $end +$var wire 1 u, Y $end +$var wire 1 w, A $end +$var wire 1 C# B $end +$var supply1 1 S- VPWR $end +$var supply0 1 T- VGND $end +$var supply1 1 U- VPB $end +$var supply0 1 V- VNB $end + +$scope module base $end +$var wire 1 u, Y $end +$var wire 1 w, A $end +$var wire 1 C# B $end +$var wire 1 W- nor0_out_Y $end +$upscope $end +$upscope $end + +$scope module FTB_18__17 $end +$var wire 1 w, X $end +$var wire 1 D# A $end +$var supply1 1 X- VPWR $end +$var supply0 1 Y- VGND $end +$var supply1 1 Z- VPB $end +$var supply0 1 [- VNB $end + +$scope module base $end +$var wire 1 w, X $end +$var wire 1 D# A $end +$var wire 1 \- buf0_out_X $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mux_l1_in_0_ $end +$var wire 1 * in [0] $end +$var wire 1 p in [1] $end +$var wire 1 s in [2] $end +$var wire 1 o, mem [0] $end +$var wire 1 p, mem [1] $end +$var wire 1 q, mem [2] $end +$var wire 1 r, mem_inv [0] $end +$var wire 1 s, mem_inv [1] $end +$var wire 1 t, mem_inv [2] $end +$var wire 1 {, out [0] $end + +$scope module scs8hd_muxinv3_1_0 $end +$var wire 1 {, Z $end +$var wire 1 * Q1 $end +$var wire 1 p Q2 $end +$var wire 1 s Q3 $end +$var wire 1 o, S0 $end +$var wire 1 r, S0B $end +$var wire 1 p, S1 $end +$var wire 1 s, S1B $end +$var wire 1 q, S2 $end +$var wire 1 t, S2B $end +$var wire 1 ]- Q1__bar $end +$var wire 1 ^- Q2__bar $end +$var wire 1 _- Q3__bar $end +$upscope $end +$upscope $end + +$scope module mux_l2_in_0_ $end +$var wire 1 {, in [0] $end +$var wire 1 v in [1] $end +$var wire 1 }, in [2] $end +$var wire 1 u, mem [0] $end +$var wire 1 v, mem [1] $end +$var wire 1 w, mem [2] $end +$var wire 1 x, mem_inv [0] $end +$var wire 1 y, mem_inv [1] $end +$var wire 1 z, mem_inv [2] $end +$var wire 1 |, out [0] $end +$var wire 1 b# p0 $end + +$scope module scs8hd_muxinv3_1_0 $end +$var wire 1 |, Z $end +$var wire 1 {, Q1 $end +$var wire 1 v Q2 $end +$var wire 1 b# Q3 $end +$var wire 1 u, S0 $end +$var wire 1 x, S0B $end +$var wire 1 v, S1 $end +$var wire 1 y, S1B $end +$var wire 1 w, S2 $end +$var wire 1 z, S2B $end +$var wire 1 `- Q1__bar $end +$var wire 1 a- Q2__bar $end +$var wire 1 b- Q3__bar $end +$upscope $end +$upscope $end + +$scope module BINV_R_100 $end +$var wire 1 9! Y $end +$var wire 1 ~, A $end +$var supply1 1 c- VPWR $end +$var supply0 1 d- VGND $end +$var supply1 1 e- VPB $end +$var supply0 1 f- VNB $end + +$scope module base $end +$var wire 1 9! Y $end +$var wire 1 ~, A $end +$var wire 1 g- not0_out_Y $end +$upscope $end +$upscope $end + +$scope module BINV_R_101 $end +$var wire 1 ~, Y $end +$var wire 1 |, A $end +$var supply1 1 h- VPWR $end +$var supply0 1 i- VGND $end +$var supply1 1 j- VPB $end +$var supply0 1 k- VNB $end + +$scope module base $end +$var wire 1 ~, Y $end +$var wire 1 |, A $end +$var wire 1 l- not0_out_Y $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mux_left_track_7 $end +$var wire 1 + in [0] $end +$var wire 1 n in [1] $end +$var wire 1 q in [2] $end +$var wire 1 t in [3] $end +$var wire 1 E# sram [0] $end +$var wire 1 F# sram [1] $end +$var wire 1 G# sram [2] $end +$var wire 1 H# sram [3] $end +$var wire 1 |# sram_inv [0] $end +$var wire 1 }# sram_inv [1] $end +$var wire 1 ~# sram_inv [2] $end +$var wire 1 !$ sram_inv [3] $end +$var wire 1 :! out [0] $end +$var wire 1 b# p0 $end +$var wire 1 m- local_encoder2to3_0_data [0] $end +$var wire 1 n- local_encoder2to3_0_data [1] $end +$var wire 1 o- local_encoder2to3_0_data [2] $end +$var wire 1 p- local_encoder2to3_0_data_inv [0] $end +$var wire 1 q- local_encoder2to3_0_data_inv [1] $end +$var wire 1 r- local_encoder2to3_0_data_inv [2] $end +$var wire 1 s- local_encoder2to3_1_data [0] $end +$var wire 1 t- local_encoder2to3_1_data [1] $end +$var wire 1 u- local_encoder2to3_1_data [2] $end +$var wire 1 v- local_encoder2to3_1_data_inv [0] $end +$var wire 1 w- local_encoder2to3_1_data_inv [1] $end +$var wire 1 x- local_encoder2to3_1_data_inv [2] $end +$var wire 1 y- mux_2level_tapbuf_basis_input3_mem3_0_out [0] $end +$var wire 1 z- mux_2level_tapbuf_basis_input3_mem3_1_out [0] $end +$var wire 1 {- SYNOPSYS_UNCONNECTED_1 $end +$var wire 1 |- BUF_net_103 $end + +$scope module local_encoder2to3_0_ $end +$var wire 1 E# addr [0] $end +$var wire 1 F# addr [1] $end +$var wire 1 m- data [0] $end +$var wire 1 n- data [1] $end +$var wire 1 o- data [2] $end +$var wire 1 p- data_inv [0] $end +$var wire 1 q- data_inv [1] $end +$var wire 1 r- data_inv [2] $end + +$scope module U8 $end +$var wire 1 p- Y $end +$var wire 1 m- A $end +$var supply1 1 }- VPWR $end +$var supply0 1 ~- VGND $end +$var supply1 1 !. VPB $end +$var supply0 1 ". VNB $end + +$scope module base $end +$var wire 1 p- Y $end +$var wire 1 m- A $end +$var wire 1 #. not0_out_Y $end +$upscope $end +$upscope $end + +$scope module U9 $end +$var wire 1 n- Y $end +$var wire 1 q- A $end +$var supply1 1 $. VPWR $end +$var supply0 1 %. VGND $end +$var supply1 1 &. VPB $end +$var supply0 1 '. VNB $end + +$scope module base $end +$var wire 1 n- Y $end +$var wire 1 q- A $end +$var wire 1 (. not0_out_Y $end +$upscope $end +$upscope $end + +$scope module U10 $end +$var wire 1 q- Y $end +$var wire 1 E# A $end +$var wire 1 r- B $end +$var supply1 1 ). VPWR $end +$var supply0 1 *. VGND $end +$var supply1 1 +. VPB $end +$var supply0 1 ,. VNB $end + +$scope module base $end +$var wire 1 q- Y $end +$var wire 1 E# A $end +$var wire 1 r- B $end +$var wire 1 -. nand0_out_Y $end +$upscope $end +$upscope $end + +$scope module U11 $end +$var wire 1 r- Y $end +$var wire 1 o- A $end +$var supply1 1 .. VPWR $end +$var supply0 1 /. VGND $end +$var supply1 1 0. VPB $end +$var supply0 1 1. VNB $end + +$scope module base $end +$var wire 1 r- Y $end +$var wire 1 o- A $end +$var wire 1 2. not0_out_Y $end +$upscope $end +$upscope $end + +$scope module U12 $end +$var wire 1 m- Y $end +$var wire 1 o- A $end +$var wire 1 E# B $end +$var supply1 1 3. VPWR $end +$var supply0 1 4. VGND $end +$var supply1 1 5. VPB $end +$var supply0 1 6. VNB $end + +$scope module base $end +$var wire 1 m- Y $end +$var wire 1 o- A $end +$var wire 1 E# B $end +$var wire 1 7. nor0_out_Y $end +$upscope $end +$upscope $end + +$scope module FTB_19__18 $end +$var wire 1 o- X $end +$var wire 1 F# A $end +$var supply1 1 8. VPWR $end +$var supply0 1 9. VGND $end +$var supply1 1 :. VPB $end +$var supply0 1 ;. VNB $end + +$scope module base $end +$var wire 1 o- X $end +$var wire 1 F# A $end +$var wire 1 <. buf0_out_X $end +$upscope $end +$upscope $end +$upscope $end + +$scope module local_encoder2to3_1_ $end +$var wire 1 G# addr [0] $end +$var wire 1 H# addr [1] $end +$var wire 1 s- data [0] $end +$var wire 1 t- data [1] $end +$var wire 1 u- data [2] $end +$var wire 1 v- data_inv [0] $end +$var wire 1 w- data_inv [1] $end +$var wire 1 x- data_inv [2] $end + +$scope module U8 $end +$var wire 1 v- Y $end +$var wire 1 s- A $end +$var supply1 1 =. VPWR $end +$var supply0 1 >. VGND $end +$var supply1 1 ?. VPB $end +$var supply0 1 @. VNB $end + +$scope module base $end +$var wire 1 v- Y $end +$var wire 1 s- A $end +$var wire 1 A. not0_out_Y $end +$upscope $end +$upscope $end + +$scope module U9 $end +$var wire 1 t- Y $end +$var wire 1 w- A $end +$var supply1 1 B. VPWR $end +$var supply0 1 C. VGND $end +$var supply1 1 D. VPB $end +$var supply0 1 E. VNB $end + +$scope module base $end +$var wire 1 t- Y $end +$var wire 1 w- A $end +$var wire 1 F. not0_out_Y $end +$upscope $end +$upscope $end + +$scope module U10 $end +$var wire 1 w- Y $end +$var wire 1 G# A $end +$var wire 1 x- B $end +$var supply1 1 G. VPWR $end +$var supply0 1 H. VGND $end +$var supply1 1 I. VPB $end +$var supply0 1 J. VNB $end + +$scope module base $end +$var wire 1 w- Y $end +$var wire 1 G# A $end +$var wire 1 x- B $end +$var wire 1 K. nand0_out_Y $end +$upscope $end +$upscope $end + +$scope module U11 $end +$var wire 1 x- Y $end +$var wire 1 u- A $end +$var supply1 1 L. VPWR $end +$var supply0 1 M. VGND $end +$var supply1 1 N. VPB $end +$var supply0 1 O. VNB $end + +$scope module base $end +$var wire 1 x- Y $end +$var wire 1 u- A $end +$var wire 1 P. not0_out_Y $end +$upscope $end +$upscope $end + +$scope module U12 $end +$var wire 1 s- Y $end +$var wire 1 u- A $end +$var wire 1 G# B $end +$var supply1 1 Q. VPWR $end +$var supply0 1 R. VGND $end +$var supply1 1 S. VPB $end +$var supply0 1 T. VNB $end + +$scope module base $end +$var wire 1 s- Y $end +$var wire 1 u- A $end +$var wire 1 G# B $end +$var wire 1 U. nor0_out_Y $end +$upscope $end +$upscope $end + +$scope module FTB_20__19 $end +$var wire 1 u- X $end +$var wire 1 H# A $end +$var supply1 1 V. VPWR $end +$var supply0 1 W. VGND $end +$var supply1 1 X. VPB $end +$var supply0 1 Y. VNB $end + +$scope module base $end +$var wire 1 u- X $end +$var wire 1 H# A $end +$var wire 1 Z. buf0_out_X $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mux_l1_in_0_ $end +$var wire 1 + in [0] $end +$var wire 1 n in [1] $end +$var wire 1 q in [2] $end +$var wire 1 m- mem [0] $end +$var wire 1 n- mem [1] $end +$var wire 1 o- mem [2] $end +$var wire 1 p- mem_inv [0] $end +$var wire 1 q- mem_inv [1] $end +$var wire 1 r- mem_inv [2] $end +$var wire 1 y- out [0] $end + +$scope module scs8hd_muxinv3_1_0 $end +$var wire 1 y- Z $end +$var wire 1 + Q1 $end +$var wire 1 n Q2 $end +$var wire 1 q Q3 $end +$var wire 1 m- S0 $end +$var wire 1 p- S0B $end +$var wire 1 n- S1 $end +$var wire 1 q- S1B $end +$var wire 1 o- S2 $end +$var wire 1 r- S2B $end +$var wire 1 [. Q1__bar $end +$var wire 1 \. Q2__bar $end +$var wire 1 ]. Q3__bar $end +$upscope $end +$upscope $end + +$scope module mux_l2_in_0_ $end +$var wire 1 y- in [0] $end +$var wire 1 t in [1] $end +$var wire 1 {- in [2] $end +$var wire 1 s- mem [0] $end +$var wire 1 t- mem [1] $end +$var wire 1 u- mem [2] $end +$var wire 1 v- mem_inv [0] $end +$var wire 1 w- mem_inv [1] $end +$var wire 1 x- mem_inv [2] $end +$var wire 1 z- out [0] $end +$var wire 1 b# p0 $end + +$scope module scs8hd_muxinv3_1_0 $end +$var wire 1 z- Z $end +$var wire 1 y- Q1 $end +$var wire 1 t Q2 $end +$var wire 1 b# Q3 $end +$var wire 1 s- S0 $end +$var wire 1 v- S0B $end +$var wire 1 t- S1 $end +$var wire 1 w- S1B $end +$var wire 1 u- S2 $end +$var wire 1 x- S2B $end +$var wire 1 ^. Q1__bar $end +$var wire 1 _. Q2__bar $end +$var wire 1 `. Q3__bar $end +$upscope $end +$upscope $end + +$scope module BINV_R_102 $end +$var wire 1 :! Y $end +$var wire 1 |- A $end +$var supply1 1 a. VPWR $end +$var supply0 1 b. VGND $end +$var supply1 1 c. VPB $end +$var supply0 1 d. VNB $end + +$scope module base $end +$var wire 1 :! Y $end +$var wire 1 |- A $end +$var wire 1 e. not0_out_Y $end +$upscope $end +$upscope $end + +$scope module BINV_R_103 $end +$var wire 1 |- Y $end +$var wire 1 z- A $end +$var supply1 1 f. VPWR $end +$var supply0 1 g. VGND $end +$var supply1 1 h. VPB $end +$var supply0 1 i. VNB $end + +$scope module base $end +$var wire 1 |- Y $end +$var wire 1 z- A $end +$var wire 1 j. not0_out_Y $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mux_left_track_9 $end +$var wire 1 , in [0] $end +$var wire 1 o in [1] $end +$var wire 1 r in [2] $end +$var wire 1 u in [3] $end +$var wire 1 {" sram [0] $end +$var wire 1 |" sram [1] $end +$var wire 1 }" sram [2] $end +$var wire 1 ~" sram [3] $end +$var wire 1 "$ sram_inv [0] $end +$var wire 1 #$ sram_inv [1] $end +$var wire 1 $$ sram_inv [2] $end +$var wire 1 %$ sram_inv [3] $end +$var wire 1 ;! out [0] $end +$var wire 1 b# p0 $end +$var wire 1 k. local_encoder2to3_0_data [0] $end +$var wire 1 l. local_encoder2to3_0_data [1] $end +$var wire 1 m. local_encoder2to3_0_data [2] $end +$var wire 1 n. local_encoder2to3_0_data_inv [0] $end +$var wire 1 o. local_encoder2to3_0_data_inv [1] $end +$var wire 1 p. local_encoder2to3_0_data_inv [2] $end +$var wire 1 q. local_encoder2to3_1_data [0] $end +$var wire 1 r. local_encoder2to3_1_data [1] $end +$var wire 1 s. local_encoder2to3_1_data [2] $end +$var wire 1 t. local_encoder2to3_1_data_inv [0] $end +$var wire 1 u. local_encoder2to3_1_data_inv [1] $end +$var wire 1 v. local_encoder2to3_1_data_inv [2] $end +$var wire 1 w. mux_2level_tapbuf_basis_input3_mem3_0_out [0] $end +$var wire 1 x. mux_2level_tapbuf_basis_input3_mem3_1_out [0] $end +$var wire 1 y. SYNOPSYS_UNCONNECTED_1 $end +$var wire 1 z. BUF_net_105 $end + +$scope module local_encoder2to3_0_ $end +$var wire 1 {" addr [0] $end +$var wire 1 |" addr [1] $end +$var wire 1 k. data [0] $end +$var wire 1 l. data [1] $end +$var wire 1 m. data [2] $end +$var wire 1 n. data_inv [0] $end +$var wire 1 o. data_inv [1] $end +$var wire 1 p. data_inv [2] $end + +$scope module U8 $end +$var wire 1 n. Y $end +$var wire 1 k. A $end +$var supply1 1 {. VPWR $end +$var supply0 1 |. VGND $end +$var supply1 1 }. VPB $end +$var supply0 1 ~. VNB $end + +$scope module base $end +$var wire 1 n. Y $end +$var wire 1 k. A $end +$var wire 1 !/ not0_out_Y $end +$upscope $end +$upscope $end + +$scope module U9 $end +$var wire 1 l. Y $end +$var wire 1 o. A $end +$var supply1 1 "/ VPWR $end +$var supply0 1 #/ VGND $end +$var supply1 1 $/ VPB $end +$var supply0 1 %/ VNB $end + +$scope module base $end +$var wire 1 l. Y $end +$var wire 1 o. A $end +$var wire 1 &/ not0_out_Y $end +$upscope $end +$upscope $end + +$scope module U10 $end +$var wire 1 o. Y $end +$var wire 1 {" A $end +$var wire 1 p. B $end +$var supply1 1 '/ VPWR $end +$var supply0 1 (/ VGND $end +$var supply1 1 )/ VPB $end +$var supply0 1 */ VNB $end + +$scope module base $end +$var wire 1 o. Y $end +$var wire 1 {" A $end +$var wire 1 p. B $end +$var wire 1 +/ nand0_out_Y $end +$upscope $end +$upscope $end + +$scope module U11 $end +$var wire 1 p. Y $end +$var wire 1 m. A $end +$var supply1 1 ,/ VPWR $end +$var supply0 1 -/ VGND $end +$var supply1 1 ./ VPB $end +$var supply0 1 // VNB $end + +$scope module base $end +$var wire 1 p. Y $end +$var wire 1 m. A $end +$var wire 1 0/ not0_out_Y $end +$upscope $end +$upscope $end + +$scope module U12 $end +$var wire 1 k. Y $end +$var wire 1 m. A $end +$var wire 1 {" B $end +$var supply1 1 1/ VPWR $end +$var supply0 1 2/ VGND $end +$var supply1 1 3/ VPB $end +$var supply0 1 4/ VNB $end + +$scope module base $end +$var wire 1 k. Y $end +$var wire 1 m. A $end +$var wire 1 {" B $end +$var wire 1 5/ nor0_out_Y $end +$upscope $end +$upscope $end + +$scope module FTB_21__20 $end +$var wire 1 m. X $end +$var wire 1 |" A $end +$var supply1 1 6/ VPWR $end +$var supply0 1 7/ VGND $end +$var supply1 1 8/ VPB $end +$var supply0 1 9/ VNB $end + +$scope module base $end +$var wire 1 m. X $end +$var wire 1 |" A $end +$var wire 1 :/ buf0_out_X $end +$upscope $end +$upscope $end +$upscope $end + +$scope module local_encoder2to3_1_ $end +$var wire 1 }" addr [0] $end +$var wire 1 ~" addr [1] $end +$var wire 1 q. data [0] $end +$var wire 1 r. data [1] $end +$var wire 1 s. data [2] $end +$var wire 1 t. data_inv [0] $end +$var wire 1 u. data_inv [1] $end +$var wire 1 v. data_inv [2] $end + +$scope module U8 $end +$var wire 1 t. Y $end +$var wire 1 q. A $end +$var supply1 1 ;/ VPWR $end +$var supply0 1 / VNB $end + +$scope module base $end +$var wire 1 t. Y $end +$var wire 1 q. A $end +$var wire 1 ?/ not0_out_Y $end +$upscope $end +$upscope $end + +$scope module U9 $end +$var wire 1 r. Y $end +$var wire 1 u. A $end +$var supply1 1 @/ VPWR $end +$var supply0 1 A/ VGND $end +$var supply1 1 B/ VPB $end +$var supply0 1 C/ VNB $end + +$scope module base $end +$var wire 1 r. Y $end +$var wire 1 u. A $end +$var wire 1 D/ not0_out_Y $end +$upscope $end +$upscope $end + +$scope module U10 $end +$var wire 1 u. Y $end +$var wire 1 }" A $end +$var wire 1 v. B $end +$var supply1 1 E/ VPWR $end +$var supply0 1 F/ VGND $end +$var supply1 1 G/ VPB $end +$var supply0 1 H/ VNB $end + +$scope module base $end +$var wire 1 u. Y $end +$var wire 1 }" A $end +$var wire 1 v. B $end +$var wire 1 I/ nand0_out_Y $end +$upscope $end +$upscope $end + +$scope module U11 $end +$var wire 1 v. Y $end +$var wire 1 s. A $end +$var supply1 1 J/ VPWR $end +$var supply0 1 K/ VGND $end +$var supply1 1 L/ VPB $end +$var supply0 1 M/ VNB $end + +$scope module base $end +$var wire 1 v. Y $end +$var wire 1 s. A $end +$var wire 1 N/ not0_out_Y $end +$upscope $end +$upscope $end + +$scope module U12 $end +$var wire 1 q. Y $end +$var wire 1 s. A $end +$var wire 1 }" B $end +$var supply1 1 O/ VPWR $end +$var supply0 1 P/ VGND $end +$var supply1 1 Q/ VPB $end +$var supply0 1 R/ VNB $end + +$scope module base $end +$var wire 1 q. Y $end +$var wire 1 s. A $end +$var wire 1 }" B $end +$var wire 1 S/ nor0_out_Y $end +$upscope $end +$upscope $end + +$scope module FTB_22__21 $end +$var wire 1 s. X $end +$var wire 1 ~" A $end +$var supply1 1 T/ VPWR $end +$var supply0 1 U/ VGND $end +$var supply1 1 V/ VPB $end +$var supply0 1 W/ VNB $end + +$scope module base $end +$var wire 1 s. X $end +$var wire 1 ~" A $end +$var wire 1 X/ buf0_out_X $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mux_l1_in_0_ $end +$var wire 1 , in [0] $end +$var wire 1 o in [1] $end +$var wire 1 r in [2] $end +$var wire 1 k. mem [0] $end +$var wire 1 l. mem [1] $end +$var wire 1 m. mem [2] $end +$var wire 1 n. mem_inv [0] $end +$var wire 1 o. mem_inv [1] $end +$var wire 1 p. mem_inv [2] $end +$var wire 1 w. out [0] $end + +$scope module scs8hd_muxinv3_1_0 $end +$var wire 1 w. Z $end +$var wire 1 , Q1 $end +$var wire 1 o Q2 $end +$var wire 1 r Q3 $end +$var wire 1 k. S0 $end +$var wire 1 n. S0B $end +$var wire 1 l. S1 $end +$var wire 1 o. S1B $end +$var wire 1 m. S2 $end +$var wire 1 p. S2B $end +$var wire 1 Y/ Q1__bar $end +$var wire 1 Z/ Q2__bar $end +$var wire 1 [/ Q3__bar $end +$upscope $end +$upscope $end + +$scope module mux_l2_in_0_ $end +$var wire 1 w. in [0] $end +$var wire 1 u in [1] $end +$var wire 1 y. in [2] $end +$var wire 1 q. mem [0] $end +$var wire 1 r. mem [1] $end +$var wire 1 s. mem [2] $end +$var wire 1 t. mem_inv [0] $end +$var wire 1 u. mem_inv [1] $end +$var wire 1 v. mem_inv [2] $end +$var wire 1 x. out [0] $end +$var wire 1 b# p0 $end + +$scope module scs8hd_muxinv3_1_0 $end +$var wire 1 x. Z $end +$var wire 1 w. Q1 $end +$var wire 1 u Q2 $end +$var wire 1 b# Q3 $end +$var wire 1 q. S0 $end +$var wire 1 t. S0B $end +$var wire 1 r. S1 $end +$var wire 1 u. S1B $end +$var wire 1 s. S2 $end +$var wire 1 v. S2B $end +$var wire 1 \/ Q1__bar $end +$var wire 1 ]/ Q2__bar $end +$var wire 1 ^/ Q3__bar $end +$upscope $end +$upscope $end + +$scope module BINV_R_104 $end +$var wire 1 ;! Y $end +$var wire 1 z. A $end +$var supply1 1 _/ VPWR $end +$var supply0 1 `/ VGND $end +$var supply1 1 a/ VPB $end +$var supply0 1 b/ VNB $end + +$scope module base $end +$var wire 1 ;! Y $end +$var wire 1 z. A $end +$var wire 1 c/ not0_out_Y $end +$upscope $end +$upscope $end + +$scope module BINV_R_105 $end +$var wire 1 z. Y $end +$var wire 1 x. A $end +$var supply1 1 d/ VPWR $end +$var supply0 1 e/ VGND $end +$var supply1 1 f/ VPB $end +$var supply0 1 g/ VNB $end + +$scope module base $end +$var wire 1 z. Y $end +$var wire 1 x. A $end +$var wire 1 h/ not0_out_Y $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mux_left_track_11 $end +$var wire 1 - in [0] $end +$var wire 1 p in [1] $end +$var wire 1 s in [2] $end +$var wire 1 v in [3] $end +$var wire 1 !# sram [0] $end +$var wire 1 "# sram [1] $end +$var wire 1 ## sram [2] $end +$var wire 1 $# sram [3] $end +$var wire 1 &$ sram_inv [0] $end +$var wire 1 '$ sram_inv [1] $end +$var wire 1 ($ sram_inv [2] $end +$var wire 1 )$ sram_inv [3] $end +$var wire 1 0 VPWR $end +$var supply0 1 ?0 VGND $end +$var supply1 1 @0 VPB $end +$var supply0 1 A0 VNB $end + +$scope module base $end +$var wire 1 p/ Y $end +$var wire 1 s/ A $end +$var wire 1 B0 not0_out_Y $end +$upscope $end +$upscope $end + +$scope module U10 $end +$var wire 1 s/ Y $end +$var wire 1 ## A $end +$var wire 1 t/ B $end +$var supply1 1 C0 VPWR $end +$var supply0 1 D0 VGND $end +$var supply1 1 E0 VPB $end +$var supply0 1 F0 VNB $end + +$scope module base $end +$var wire 1 s/ Y $end +$var wire 1 ## A $end +$var wire 1 t/ B $end +$var wire 1 G0 nand0_out_Y $end +$upscope $end +$upscope $end + +$scope module U11 $end +$var wire 1 t/ Y $end +$var wire 1 q/ A $end +$var supply1 1 H0 VPWR $end +$var supply0 1 I0 VGND $end +$var supply1 1 J0 VPB $end +$var supply0 1 K0 VNB $end + +$scope module base $end +$var wire 1 t/ Y $end +$var wire 1 q/ A $end +$var wire 1 L0 not0_out_Y $end +$upscope $end +$upscope $end + +$scope module U12 $end +$var wire 1 o/ Y $end +$var wire 1 q/ A $end +$var wire 1 ## B $end +$var supply1 1 M0 VPWR $end +$var supply0 1 N0 VGND $end +$var supply1 1 O0 VPB $end +$var supply0 1 P0 VNB $end + +$scope module base $end +$var wire 1 o/ Y $end +$var wire 1 q/ A $end +$var wire 1 ## B $end +$var wire 1 Q0 nor0_out_Y $end +$upscope $end +$upscope $end + +$scope module FTB_24__23 $end +$var wire 1 q/ X $end +$var wire 1 $# A $end +$var supply1 1 R0 VPWR $end +$var supply0 1 S0 VGND $end +$var supply1 1 T0 VPB $end +$var supply0 1 U0 VNB $end + +$scope module base $end +$var wire 1 q/ X $end +$var wire 1 $# A $end +$var wire 1 V0 buf0_out_X $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mux_l1_in_0_ $end +$var wire 1 - in [0] $end +$var wire 1 p in [1] $end +$var wire 1 s in [2] $end +$var wire 1 i/ mem [0] $end +$var wire 1 j/ mem [1] $end +$var wire 1 k/ mem [2] $end +$var wire 1 l/ mem_inv [0] $end +$var wire 1 m/ mem_inv [1] $end +$var wire 1 n/ mem_inv [2] $end +$var wire 1 u/ out [0] $end + +$scope module scs8hd_muxinv3_1_0 $end +$var wire 1 u/ Z $end +$var wire 1 - Q1 $end +$var wire 1 p Q2 $end +$var wire 1 s Q3 $end +$var wire 1 i/ S0 $end +$var wire 1 l/ S0B $end +$var wire 1 j/ S1 $end +$var wire 1 m/ S1B $end +$var wire 1 k/ S2 $end +$var wire 1 n/ S2B $end +$var wire 1 W0 Q1__bar $end +$var wire 1 X0 Q2__bar $end +$var wire 1 Y0 Q3__bar $end +$upscope $end +$upscope $end + +$scope module mux_l2_in_0_ $end +$var wire 1 u/ in [0] $end +$var wire 1 v in [1] $end +$var wire 1 w/ in [2] $end +$var wire 1 o/ mem [0] $end +$var wire 1 p/ mem [1] $end +$var wire 1 q/ mem [2] $end +$var wire 1 r/ mem_inv [0] $end +$var wire 1 s/ mem_inv [1] $end +$var wire 1 t/ mem_inv [2] $end +$var wire 1 v/ out [0] $end +$var wire 1 b# p0 $end + +$scope module scs8hd_muxinv3_1_0 $end +$var wire 1 v/ Z $end +$var wire 1 u/ Q1 $end +$var wire 1 v Q2 $end +$var wire 1 b# Q3 $end +$var wire 1 o/ S0 $end +$var wire 1 r/ S0B $end +$var wire 1 p/ S1 $end +$var wire 1 s/ S1B $end +$var wire 1 q/ S2 $end +$var wire 1 t/ S2B $end +$var wire 1 Z0 Q1__bar $end +$var wire 1 [0 Q2__bar $end +$var wire 1 \0 Q3__bar $end +$upscope $end +$upscope $end + +$scope module BINV_R_106 $end +$var wire 1 1 VNB $end + +$scope module base $end +$var wire 1 g0 X $end +$var wire 1 k0 A $end +$var wire 1 ?1 buf0_out_X $end +$upscope $end +$upscope $end + +$scope module ropt_h_inst_1433 $end +$var wire 1 i0 X $end +$var wire 1 l0 A $end +$var supply1 1 @1 VPWR $end +$var supply0 1 A1 VGND $end +$var supply1 1 B1 VPB $end +$var supply0 1 C1 VNB $end + +$scope module base $end +$var wire 1 i0 X $end +$var wire 1 l0 A $end +$var wire 1 D1 buf0_out_X $end +$upscope $end +$upscope $end + +$scope module ropt_h_inst_1434 $end +$var wire 1 l0 X $end +$var wire 1 h0 A $end +$var supply1 1 E1 VPWR $end +$var supply0 1 F1 VGND $end +$var supply1 1 G1 VPB $end +$var supply0 1 H1 VNB $end + +$scope module base $end +$var wire 1 l0 X $end +$var wire 1 h0 A $end +$var wire 1 I1 buf0_out_X $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mem_bottom_track_3 $end +$var wire 1 ( pReset [0] $end +$var wire 1 Y! prog_clk [0] $end +$var wire 1 I# ccff_head [0] $end +$var wire 1 L# ccff_tail [0] $end +$var wire 1 %# mem_out [0] $end +$var wire 1 &# mem_out [1] $end +$var wire 1 '# mem_out [2] $end +$var wire 1 (# mem_out [3] $end + +$scope module sky130_fd_sc_hd__dfrtp_1_0_ $end +$var wire 1 %# Q $end +$var wire 1 Y! CLK $end +$var wire 1 I# D $end +$var wire 1 ( RESET_B $end +$var supply1 1 J1 VPWR $end +$var supply0 1 K1 VGND $end +$var supply1 1 L1 VPB $end +$var supply0 1 M1 VNB $end + +$scope module base $end +$var wire 1 %# Q $end +$var wire 1 Y! CLK $end +$var wire 1 I# D $end +$var wire 1 ( RESET_B $end +$var wire 1 N1 buf_Q $end +$var wire 1 O1 RESET $end +$upscope $end +$upscope $end + +$scope module sky130_fd_sc_hd__dfrtp_1_1_ $end +$var wire 1 &# Q $end +$var wire 1 Y! CLK $end +$var wire 1 %# D $end +$var wire 1 ( RESET_B $end +$var supply1 1 P1 VPWR $end +$var supply0 1 Q1 VGND $end +$var supply1 1 R1 VPB $end +$var supply0 1 S1 VNB $end + +$scope module base $end +$var wire 1 &# Q $end +$var wire 1 Y! CLK $end +$var wire 1 %# D $end +$var wire 1 ( RESET_B $end +$var wire 1 T1 buf_Q $end +$var wire 1 U1 RESET $end +$upscope $end +$upscope $end + +$scope module sky130_fd_sc_hd__dfrtp_1_2_ $end +$var wire 1 '# Q $end +$var wire 1 Y! CLK $end +$var wire 1 &# D $end +$var wire 1 ( RESET_B $end +$var supply1 1 V1 VPWR $end +$var supply0 1 W1 VGND $end +$var supply1 1 X1 VPB $end +$var supply0 1 Y1 VNB $end + +$scope module base $end +$var wire 1 '# Q $end +$var wire 1 Y! CLK $end +$var wire 1 &# D $end +$var wire 1 ( RESET_B $end +$var wire 1 Z1 buf_Q $end +$var wire 1 [1 RESET $end +$upscope $end +$upscope $end + +$scope module sky130_fd_sc_hd__dfrtp_1_3_ $end +$var wire 1 (# Q $end +$var wire 1 Y! CLK $end +$var wire 1 '# D $end +$var wire 1 ( RESET_B $end +$var supply1 1 \1 VPWR $end +$var supply0 1 ]1 VGND $end +$var supply1 1 ^1 VPB $end +$var supply0 1 _1 VNB $end + +$scope module base $end +$var wire 1 (# Q $end +$var wire 1 Y! CLK $end +$var wire 1 '# D $end +$var wire 1 ( RESET_B $end +$var wire 1 `1 buf_Q $end +$var wire 1 a1 RESET $end +$upscope $end +$upscope $end + +$scope module FTB_26__25 $end +$var wire 1 L# X $end +$var wire 1 (# A $end +$var supply1 1 b1 VPWR $end +$var supply0 1 c1 VGND $end +$var supply1 1 d1 VPB $end +$var supply0 1 e1 VNB $end + +$scope module base $end +$var wire 1 L# X $end +$var wire 1 (# A $end +$var wire 1 f1 buf0_out_X $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mem_bottom_track_5 $end +$var wire 1 ( pReset [0] $end +$var wire 1 Y! prog_clk [0] $end +$var wire 1 L# ccff_head [0] $end +$var wire 1 M# ccff_tail [0] $end +$var wire 1 )# mem_out [0] $end +$var wire 1 *# mem_out [1] $end +$var wire 1 +# mem_out [2] $end +$var wire 1 ,# mem_out [3] $end + +$scope module sky130_fd_sc_hd__dfrtp_1_0_ $end +$var wire 1 )# Q $end +$var wire 1 Y! CLK $end +$var wire 1 L# D $end +$var wire 1 ( RESET_B $end +$var supply1 1 g1 VPWR $end +$var supply0 1 h1 VGND $end +$var supply1 1 i1 VPB $end +$var supply0 1 j1 VNB $end + +$scope module base $end +$var wire 1 )# Q $end +$var wire 1 Y! CLK $end +$var wire 1 L# D $end +$var wire 1 ( RESET_B $end +$var wire 1 k1 buf_Q $end +$var wire 1 l1 RESET $end +$upscope $end +$upscope $end + +$scope module sky130_fd_sc_hd__dfrtp_1_1_ $end +$var wire 1 *# Q $end +$var wire 1 Y! CLK $end +$var wire 1 )# D $end +$var wire 1 ( RESET_B $end +$var supply1 1 m1 VPWR $end +$var supply0 1 n1 VGND $end +$var supply1 1 o1 VPB $end +$var supply0 1 p1 VNB $end + +$scope module base $end +$var wire 1 *# Q $end +$var wire 1 Y! CLK $end +$var wire 1 )# D $end +$var wire 1 ( RESET_B $end +$var wire 1 q1 buf_Q $end +$var wire 1 r1 RESET $end +$upscope $end +$upscope $end + +$scope module sky130_fd_sc_hd__dfrtp_1_2_ $end +$var wire 1 +# Q $end +$var wire 1 Y! CLK $end +$var wire 1 *# D $end +$var wire 1 ( RESET_B $end +$var supply1 1 s1 VPWR $end +$var supply0 1 t1 VGND $end +$var supply1 1 u1 VPB $end +$var supply0 1 v1 VNB $end + +$scope module base $end +$var wire 1 +# Q $end +$var wire 1 Y! CLK $end +$var wire 1 *# D $end +$var wire 1 ( RESET_B $end +$var wire 1 w1 buf_Q $end +$var wire 1 x1 RESET $end +$upscope $end +$upscope $end + +$scope module sky130_fd_sc_hd__dfrtp_1_3_ $end +$var wire 1 ,# Q $end +$var wire 1 Y! CLK $end +$var wire 1 +# D $end +$var wire 1 ( RESET_B $end +$var supply1 1 y1 VPWR $end +$var supply0 1 z1 VGND $end +$var supply1 1 {1 VPB $end +$var supply0 1 |1 VNB $end + +$scope module base $end +$var wire 1 ,# Q $end +$var wire 1 Y! CLK $end +$var wire 1 +# D $end +$var wire 1 ( RESET_B $end +$var wire 1 }1 buf_Q $end +$var wire 1 ~1 RESET $end +$upscope $end +$upscope $end + +$scope module FTB_27__26 $end +$var wire 1 M# X $end +$var wire 1 ,# A $end +$var supply1 1 !2 VPWR $end +$var supply0 1 "2 VGND $end +$var supply1 1 #2 VPB $end +$var supply0 1 $2 VNB $end + +$scope module base $end +$var wire 1 M# X $end +$var wire 1 ,# A $end +$var wire 1 %2 buf0_out_X $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mem_bottom_track_7 $end +$var wire 1 ( pReset [0] $end +$var wire 1 Y! prog_clk [0] $end +$var wire 1 M# ccff_head [0] $end +$var wire 1 N# ccff_tail [0] $end +$var wire 1 -# mem_out [0] $end +$var wire 1 .# mem_out [1] $end +$var wire 1 /# mem_out [2] $end +$var wire 1 0# mem_out [3] $end + +$scope module sky130_fd_sc_hd__dfrtp_1_0_ $end +$var wire 1 -# Q $end +$var wire 1 Y! CLK $end +$var wire 1 M# D $end +$var wire 1 ( RESET_B $end +$var supply1 1 &2 VPWR $end +$var supply0 1 '2 VGND $end +$var supply1 1 (2 VPB $end +$var supply0 1 )2 VNB $end + +$scope module base $end +$var wire 1 -# Q $end +$var wire 1 Y! CLK $end +$var wire 1 M# D $end +$var wire 1 ( RESET_B $end +$var wire 1 *2 buf_Q $end +$var wire 1 +2 RESET $end +$upscope $end +$upscope $end + +$scope module sky130_fd_sc_hd__dfrtp_1_1_ $end +$var wire 1 .# Q $end +$var wire 1 Y! CLK $end +$var wire 1 -# D $end +$var wire 1 ( RESET_B $end +$var supply1 1 ,2 VPWR $end +$var supply0 1 -2 VGND $end +$var supply1 1 .2 VPB $end +$var supply0 1 /2 VNB $end + +$scope module base $end +$var wire 1 .# Q $end +$var wire 1 Y! CLK $end +$var wire 1 -# D $end +$var wire 1 ( RESET_B $end +$var wire 1 02 buf_Q $end +$var wire 1 12 RESET $end +$upscope $end +$upscope $end + +$scope module sky130_fd_sc_hd__dfrtp_1_2_ $end +$var wire 1 /# Q $end +$var wire 1 Y! CLK $end +$var wire 1 .# D $end +$var wire 1 ( RESET_B $end +$var supply1 1 22 VPWR $end +$var supply0 1 32 VGND $end +$var supply1 1 42 VPB $end +$var supply0 1 52 VNB $end + +$scope module base $end +$var wire 1 /# Q $end +$var wire 1 Y! CLK $end +$var wire 1 .# D $end +$var wire 1 ( RESET_B $end +$var wire 1 62 buf_Q $end +$var wire 1 72 RESET $end +$upscope $end +$upscope $end + +$scope module sky130_fd_sc_hd__dfrtp_1_3_ $end +$var wire 1 0# Q $end +$var wire 1 Y! CLK $end +$var wire 1 /# D $end +$var wire 1 ( RESET_B $end +$var supply1 1 82 VPWR $end +$var supply0 1 92 VGND $end +$var supply1 1 :2 VPB $end +$var supply0 1 ;2 VNB $end + +$scope module base $end +$var wire 1 0# Q $end +$var wire 1 Y! CLK $end +$var wire 1 /# D $end +$var wire 1 ( RESET_B $end +$var wire 1 <2 buf_Q $end +$var wire 1 =2 RESET $end +$upscope $end +$upscope $end + +$scope module FTB_28__27 $end +$var wire 1 N# X $end +$var wire 1 0# A $end +$var supply1 1 >2 VPWR $end +$var supply0 1 ?2 VGND $end +$var supply1 1 @2 VPB $end +$var supply0 1 A2 VNB $end + +$scope module base $end +$var wire 1 N# X $end +$var wire 1 0# A $end +$var wire 1 B2 buf0_out_X $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mem_bottom_track_9 $end +$var wire 1 ( pReset [0] $end +$var wire 1 Y! prog_clk [0] $end +$var wire 1 N# ccff_head [0] $end +$var wire 1 O# ccff_tail [0] $end +$var wire 1 1# mem_out [0] $end +$var wire 1 2# mem_out [1] $end +$var wire 1 3# mem_out [2] $end +$var wire 1 4# mem_out [3] $end + +$scope module sky130_fd_sc_hd__dfrtp_1_0_ $end +$var wire 1 1# Q $end +$var wire 1 Y! CLK $end +$var wire 1 N# D $end +$var wire 1 ( RESET_B $end +$var supply1 1 C2 VPWR $end +$var supply0 1 D2 VGND $end +$var supply1 1 E2 VPB $end +$var supply0 1 F2 VNB $end + +$scope module base $end +$var wire 1 1# Q $end +$var wire 1 Y! CLK $end +$var wire 1 N# D $end +$var wire 1 ( RESET_B $end +$var wire 1 G2 buf_Q $end +$var wire 1 H2 RESET $end +$upscope $end +$upscope $end + +$scope module sky130_fd_sc_hd__dfrtp_1_1_ $end +$var wire 1 2# Q $end +$var wire 1 Y! CLK $end +$var wire 1 1# D $end +$var wire 1 ( RESET_B $end +$var supply1 1 I2 VPWR $end +$var supply0 1 J2 VGND $end +$var supply1 1 K2 VPB $end +$var supply0 1 L2 VNB $end + +$scope module base $end +$var wire 1 2# Q $end +$var wire 1 Y! CLK $end +$var wire 1 1# D $end +$var wire 1 ( RESET_B $end +$var wire 1 M2 buf_Q $end +$var wire 1 N2 RESET $end +$upscope $end +$upscope $end + +$scope module sky130_fd_sc_hd__dfrtp_1_2_ $end +$var wire 1 3# Q $end +$var wire 1 Y! CLK $end +$var wire 1 2# D $end +$var wire 1 ( RESET_B $end +$var supply1 1 O2 VPWR $end +$var supply0 1 P2 VGND $end +$var supply1 1 Q2 VPB $end +$var supply0 1 R2 VNB $end + +$scope module base $end +$var wire 1 3# Q $end +$var wire 1 Y! CLK $end +$var wire 1 2# D $end +$var wire 1 ( RESET_B $end +$var wire 1 S2 buf_Q $end +$var wire 1 T2 RESET $end +$upscope $end +$upscope $end + +$scope module sky130_fd_sc_hd__dfrtp_1_3_ $end +$var wire 1 4# Q $end +$var wire 1 Y! CLK $end +$var wire 1 3# D $end +$var wire 1 ( RESET_B $end +$var supply1 1 U2 VPWR $end +$var supply0 1 V2 VGND $end +$var supply1 1 W2 VPB $end +$var supply0 1 X2 VNB $end + +$scope module base $end +$var wire 1 4# Q $end +$var wire 1 Y! CLK $end +$var wire 1 3# D $end +$var wire 1 ( RESET_B $end +$var wire 1 Y2 buf_Q $end +$var wire 1 Z2 RESET $end +$upscope $end +$upscope $end + +$scope module FTB_29__28 $end +$var wire 1 O# X $end +$var wire 1 4# A $end +$var supply1 1 [2 VPWR $end +$var supply0 1 \2 VGND $end +$var supply1 1 ]2 VPB $end +$var supply0 1 ^2 VNB $end + +$scope module base $end +$var wire 1 O# X $end +$var wire 1 4# A $end +$var wire 1 _2 buf0_out_X $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mem_bottom_track_11 $end +$var wire 1 ( pReset [0] $end +$var wire 1 Y! prog_clk [0] $end +$var wire 1 O# ccff_head [0] $end +$var wire 1 P# ccff_tail [0] $end +$var wire 1 5# mem_out [0] $end +$var wire 1 6# mem_out [1] $end +$var wire 1 7# mem_out [2] $end +$var wire 1 8# mem_out [3] $end + +$scope module sky130_fd_sc_hd__dfrtp_1_0_ $end +$var wire 1 5# Q $end +$var wire 1 Y! CLK $end +$var wire 1 O# D $end +$var wire 1 ( RESET_B $end +$var supply1 1 `2 VPWR $end +$var supply0 1 a2 VGND $end +$var supply1 1 b2 VPB $end +$var supply0 1 c2 VNB $end + +$scope module base $end +$var wire 1 5# Q $end +$var wire 1 Y! CLK $end +$var wire 1 O# D $end +$var wire 1 ( RESET_B $end +$var wire 1 d2 buf_Q $end +$var wire 1 e2 RESET $end +$upscope $end +$upscope $end + +$scope module sky130_fd_sc_hd__dfrtp_1_1_ $end +$var wire 1 6# Q $end +$var wire 1 Y! CLK $end +$var wire 1 5# D $end +$var wire 1 ( RESET_B $end +$var supply1 1 f2 VPWR $end +$var supply0 1 g2 VGND $end +$var supply1 1 h2 VPB $end +$var supply0 1 i2 VNB $end + +$scope module base $end +$var wire 1 6# Q $end +$var wire 1 Y! CLK $end +$var wire 1 5# D $end +$var wire 1 ( RESET_B $end +$var wire 1 j2 buf_Q $end +$var wire 1 k2 RESET $end +$upscope $end +$upscope $end + +$scope module sky130_fd_sc_hd__dfrtp_1_2_ $end +$var wire 1 7# Q $end +$var wire 1 Y! CLK $end +$var wire 1 6# D $end +$var wire 1 ( RESET_B $end +$var supply1 1 l2 VPWR $end +$var supply0 1 m2 VGND $end +$var supply1 1 n2 VPB $end +$var supply0 1 o2 VNB $end + +$scope module base $end +$var wire 1 7# Q $end +$var wire 1 Y! CLK $end +$var wire 1 6# D $end +$var wire 1 ( RESET_B $end +$var wire 1 p2 buf_Q $end +$var wire 1 q2 RESET $end +$upscope $end +$upscope $end + +$scope module sky130_fd_sc_hd__dfrtp_1_3_ $end +$var wire 1 8# Q $end +$var wire 1 Y! CLK $end +$var wire 1 7# D $end +$var wire 1 ( RESET_B $end +$var supply1 1 r2 VPWR $end +$var supply0 1 s2 VGND $end +$var supply1 1 t2 VPB $end +$var supply0 1 u2 VNB $end + +$scope module base $end +$var wire 1 8# Q $end +$var wire 1 Y! CLK $end +$var wire 1 7# D $end +$var wire 1 ( RESET_B $end +$var wire 1 v2 buf_Q $end +$var wire 1 w2 RESET $end +$upscope $end +$upscope $end + +$scope module FTB_30__29 $end +$var wire 1 P# X $end +$var wire 1 8# A $end +$var supply1 1 x2 VPWR $end +$var supply0 1 y2 VGND $end +$var supply1 1 z2 VPB $end +$var supply0 1 {2 VNB $end + +$scope module base $end +$var wire 1 P# X $end +$var wire 1 8# A $end +$var wire 1 |2 buf0_out_X $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mem_left_track_1 $end +$var wire 1 ( pReset [0] $end +$var wire 1 Y! prog_clk [0] $end +$var wire 1 L" ccff_head [0] $end +$var wire 1 Q# ccff_tail [0] $end +$var wire 1 9# mem_out [0] $end +$var wire 1 :# mem_out [1] $end +$var wire 1 ;# mem_out [2] $end +$var wire 1 <# mem_out [3] $end + +$scope module sky130_fd_sc_hd__dfrtp_1_0_ $end +$var wire 1 9# Q $end +$var wire 1 Y! CLK $end +$var wire 1 L" D $end +$var wire 1 ( RESET_B $end +$var supply1 1 }2 VPWR $end +$var supply0 1 ~2 VGND $end +$var supply1 1 !3 VPB $end +$var supply0 1 "3 VNB $end + +$scope module base $end +$var wire 1 9# Q $end +$var wire 1 Y! CLK $end +$var wire 1 L" D $end +$var wire 1 ( RESET_B $end +$var wire 1 #3 buf_Q $end +$var wire 1 $3 RESET $end +$upscope $end +$upscope $end + +$scope module sky130_fd_sc_hd__dfrtp_1_1_ $end +$var wire 1 :# Q $end +$var wire 1 Y! CLK $end +$var wire 1 9# D $end +$var wire 1 ( RESET_B $end +$var supply1 1 %3 VPWR $end +$var supply0 1 &3 VGND $end +$var supply1 1 '3 VPB $end +$var supply0 1 (3 VNB $end + +$scope module base $end +$var wire 1 :# Q $end +$var wire 1 Y! CLK $end +$var wire 1 9# D $end +$var wire 1 ( RESET_B $end +$var wire 1 )3 buf_Q $end +$var wire 1 *3 RESET $end +$upscope $end +$upscope $end + +$scope module sky130_fd_sc_hd__dfrtp_1_2_ $end +$var wire 1 ;# Q $end +$var wire 1 Y! CLK $end +$var wire 1 :# D $end +$var wire 1 ( RESET_B $end +$var supply1 1 +3 VPWR $end +$var supply0 1 ,3 VGND $end +$var supply1 1 -3 VPB $end +$var supply0 1 .3 VNB $end + +$scope module base $end +$var wire 1 ;# Q $end +$var wire 1 Y! CLK $end +$var wire 1 :# D $end +$var wire 1 ( RESET_B $end +$var wire 1 /3 buf_Q $end +$var wire 1 03 RESET $end +$upscope $end +$upscope $end + +$scope module sky130_fd_sc_hd__dfrtp_1_3_ $end +$var wire 1 <# Q $end +$var wire 1 Y! CLK $end +$var wire 1 ;# D $end +$var wire 1 ( RESET_B $end +$var supply1 1 13 VPWR $end +$var supply0 1 23 VGND $end +$var supply1 1 33 VPB $end +$var supply0 1 43 VNB $end + +$scope module base $end +$var wire 1 <# Q $end +$var wire 1 Y! CLK $end +$var wire 1 ;# D $end +$var wire 1 ( RESET_B $end +$var wire 1 53 buf_Q $end +$var wire 1 63 RESET $end +$upscope $end +$upscope $end + +$scope module FTB_31__30 $end +$var wire 1 Q# X $end +$var wire 1 <# A $end +$var supply1 1 73 VPWR $end +$var supply0 1 83 VGND $end +$var supply1 1 93 VPB $end +$var supply0 1 :3 VNB $end + +$scope module base $end +$var wire 1 Q# X $end +$var wire 1 <# A $end +$var wire 1 ;3 buf0_out_X $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mem_left_track_3 $end +$var wire 1 ( pReset [0] $end +$var wire 1 Y! prog_clk [0] $end +$var wire 1 Q# ccff_head [0] $end +$var wire 1 R# ccff_tail [0] $end +$var wire 1 =# mem_out [0] $end +$var wire 1 ># mem_out [1] $end +$var wire 1 ?# mem_out [2] $end +$var wire 1 @# mem_out [3] $end + +$scope module sky130_fd_sc_hd__dfrtp_1_0_ $end +$var wire 1 =# Q $end +$var wire 1 Y! CLK $end +$var wire 1 Q# D $end +$var wire 1 ( RESET_B $end +$var supply1 1 <3 VPWR $end +$var supply0 1 =3 VGND $end +$var supply1 1 >3 VPB $end +$var supply0 1 ?3 VNB $end + +$scope module base $end +$var wire 1 =# Q $end +$var wire 1 Y! CLK $end +$var wire 1 Q# D $end +$var wire 1 ( RESET_B $end +$var wire 1 @3 buf_Q $end +$var wire 1 A3 RESET $end +$upscope $end +$upscope $end + +$scope module sky130_fd_sc_hd__dfrtp_1_1_ $end +$var wire 1 ># Q $end +$var wire 1 Y! CLK $end +$var wire 1 =# D $end +$var wire 1 ( RESET_B $end +$var supply1 1 B3 VPWR $end +$var supply0 1 C3 VGND $end +$var supply1 1 D3 VPB $end +$var supply0 1 E3 VNB $end + +$scope module base $end +$var wire 1 ># Q $end +$var wire 1 Y! CLK $end +$var wire 1 =# D $end +$var wire 1 ( RESET_B $end +$var wire 1 F3 buf_Q $end +$var wire 1 G3 RESET $end +$upscope $end +$upscope $end + +$scope module sky130_fd_sc_hd__dfrtp_1_2_ $end +$var wire 1 ?# Q $end +$var wire 1 Y! CLK $end +$var wire 1 ># D $end +$var wire 1 ( RESET_B $end +$var supply1 1 H3 VPWR $end +$var supply0 1 I3 VGND $end +$var supply1 1 J3 VPB $end +$var supply0 1 K3 VNB $end + +$scope module base $end +$var wire 1 ?# Q $end +$var wire 1 Y! CLK $end +$var wire 1 ># D $end +$var wire 1 ( RESET_B $end +$var wire 1 L3 buf_Q $end +$var wire 1 M3 RESET $end +$upscope $end +$upscope $end + +$scope module sky130_fd_sc_hd__dfrtp_1_3_ $end +$var wire 1 @# Q $end +$var wire 1 Y! CLK $end +$var wire 1 ?# D $end +$var wire 1 ( RESET_B $end +$var supply1 1 N3 VPWR $end +$var supply0 1 O3 VGND $end +$var supply1 1 P3 VPB $end +$var supply0 1 Q3 VNB $end + +$scope module base $end +$var wire 1 @# Q $end +$var wire 1 Y! CLK $end +$var wire 1 ?# D $end +$var wire 1 ( RESET_B $end +$var wire 1 R3 buf_Q $end +$var wire 1 S3 RESET $end +$upscope $end +$upscope $end + +$scope module FTB_32__31 $end +$var wire 1 R# X $end +$var wire 1 @# A $end +$var supply1 1 T3 VPWR $end +$var supply0 1 U3 VGND $end +$var supply1 1 V3 VPB $end +$var supply0 1 W3 VNB $end + +$scope module base $end +$var wire 1 R# X $end +$var wire 1 @# A $end +$var wire 1 X3 buf0_out_X $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mem_left_track_5 $end +$var wire 1 ( pReset [0] $end +$var wire 1 Y! prog_clk [0] $end +$var wire 1 R# ccff_head [0] $end +$var wire 1 S# ccff_tail [0] $end +$var wire 1 A# mem_out [0] $end +$var wire 1 B# mem_out [1] $end +$var wire 1 C# mem_out [2] $end +$var wire 1 D# mem_out [3] $end + +$scope module sky130_fd_sc_hd__dfrtp_1_0_ $end +$var wire 1 A# Q $end +$var wire 1 Y! CLK $end +$var wire 1 R# D $end +$var wire 1 ( RESET_B $end +$var supply1 1 Y3 VPWR $end +$var supply0 1 Z3 VGND $end +$var supply1 1 [3 VPB $end +$var supply0 1 \3 VNB $end + +$scope module base $end +$var wire 1 A# Q $end +$var wire 1 Y! CLK $end +$var wire 1 R# D $end +$var wire 1 ( RESET_B $end +$var wire 1 ]3 buf_Q $end +$var wire 1 ^3 RESET $end +$upscope $end +$upscope $end + +$scope module sky130_fd_sc_hd__dfrtp_1_1_ $end +$var wire 1 B# Q $end +$var wire 1 Y! CLK $end +$var wire 1 A# D $end +$var wire 1 ( RESET_B $end +$var supply1 1 _3 VPWR $end +$var supply0 1 `3 VGND $end +$var supply1 1 a3 VPB $end +$var supply0 1 b3 VNB $end + +$scope module base $end +$var wire 1 B# Q $end +$var wire 1 Y! CLK $end +$var wire 1 A# D $end +$var wire 1 ( RESET_B $end +$var wire 1 c3 buf_Q $end +$var wire 1 d3 RESET $end +$upscope $end +$upscope $end + +$scope module sky130_fd_sc_hd__dfrtp_1_2_ $end +$var wire 1 C# Q $end +$var wire 1 Y! CLK $end +$var wire 1 B# D $end +$var wire 1 ( RESET_B $end +$var supply1 1 e3 VPWR $end +$var supply0 1 f3 VGND $end +$var supply1 1 g3 VPB $end +$var supply0 1 h3 VNB $end + +$scope module base $end +$var wire 1 C# Q $end +$var wire 1 Y! CLK $end +$var wire 1 B# D $end +$var wire 1 ( RESET_B $end +$var wire 1 i3 buf_Q $end +$var wire 1 j3 RESET $end +$upscope $end +$upscope $end + +$scope module sky130_fd_sc_hd__dfrtp_1_3_ $end +$var wire 1 D# Q $end +$var wire 1 Y! CLK $end +$var wire 1 C# D $end +$var wire 1 ( RESET_B $end +$var supply1 1 k3 VPWR $end +$var supply0 1 l3 VGND $end +$var supply1 1 m3 VPB $end +$var supply0 1 n3 VNB $end + +$scope module base $end +$var wire 1 D# Q $end +$var wire 1 Y! CLK $end +$var wire 1 C# D $end +$var wire 1 ( RESET_B $end +$var wire 1 o3 buf_Q $end +$var wire 1 p3 RESET $end +$upscope $end +$upscope $end + +$scope module FTB_33__32 $end +$var wire 1 S# X $end +$var wire 1 D# A $end +$var supply1 1 q3 VPWR $end +$var supply0 1 r3 VGND $end +$var supply1 1 s3 VPB $end +$var supply0 1 t3 VNB $end + +$scope module base $end +$var wire 1 S# X $end +$var wire 1 D# A $end +$var wire 1 u3 buf0_out_X $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mem_left_track_7 $end +$var wire 1 ( pReset [0] $end +$var wire 1 Y! prog_clk [0] $end +$var wire 1 S# ccff_head [0] $end +$var wire 1 T# ccff_tail [0] $end +$var wire 1 E# mem_out [0] $end +$var wire 1 F# mem_out [1] $end +$var wire 1 G# mem_out [2] $end +$var wire 1 H# mem_out [3] $end + +$scope module sky130_fd_sc_hd__dfrtp_1_0_ $end +$var wire 1 E# Q $end +$var wire 1 Y! CLK $end +$var wire 1 S# D $end +$var wire 1 ( RESET_B $end +$var supply1 1 v3 VPWR $end +$var supply0 1 w3 VGND $end +$var supply1 1 x3 VPB $end +$var supply0 1 y3 VNB $end + +$scope module base $end +$var wire 1 E# Q $end +$var wire 1 Y! CLK $end +$var wire 1 S# D $end +$var wire 1 ( RESET_B $end +$var wire 1 z3 buf_Q $end +$var wire 1 {3 RESET $end +$upscope $end +$upscope $end + +$scope module sky130_fd_sc_hd__dfrtp_1_1_ $end +$var wire 1 F# Q $end +$var wire 1 Y! CLK $end +$var wire 1 E# D $end +$var wire 1 ( RESET_B $end +$var supply1 1 |3 VPWR $end +$var supply0 1 }3 VGND $end +$var supply1 1 ~3 VPB $end +$var supply0 1 !4 VNB $end + +$scope module base $end +$var wire 1 F# Q $end +$var wire 1 Y! CLK $end +$var wire 1 E# D $end +$var wire 1 ( RESET_B $end +$var wire 1 "4 buf_Q $end +$var wire 1 #4 RESET $end +$upscope $end +$upscope $end + +$scope module sky130_fd_sc_hd__dfrtp_1_2_ $end +$var wire 1 G# Q $end +$var wire 1 Y! CLK $end +$var wire 1 F# D $end +$var wire 1 ( RESET_B $end +$var supply1 1 $4 VPWR $end +$var supply0 1 %4 VGND $end +$var supply1 1 &4 VPB $end +$var supply0 1 '4 VNB $end + +$scope module base $end +$var wire 1 G# Q $end +$var wire 1 Y! CLK $end +$var wire 1 F# D $end +$var wire 1 ( RESET_B $end +$var wire 1 (4 buf_Q $end +$var wire 1 )4 RESET $end +$upscope $end +$upscope $end + +$scope module sky130_fd_sc_hd__dfrtp_1_3_ $end +$var wire 1 H# Q $end +$var wire 1 Y! CLK $end +$var wire 1 G# D $end +$var wire 1 ( RESET_B $end +$var supply1 1 *4 VPWR $end +$var supply0 1 +4 VGND $end +$var supply1 1 ,4 VPB $end +$var supply0 1 -4 VNB $end + +$scope module base $end +$var wire 1 H# Q $end +$var wire 1 Y! CLK $end +$var wire 1 G# D $end +$var wire 1 ( RESET_B $end +$var wire 1 .4 buf_Q $end +$var wire 1 /4 RESET $end +$upscope $end +$upscope $end + +$scope module FTB_34__33 $end +$var wire 1 T# X $end +$var wire 1 H# A $end +$var supply1 1 04 VPWR $end +$var supply0 1 14 VGND $end +$var supply1 1 24 VPB $end +$var supply0 1 34 VNB $end + +$scope module base $end +$var wire 1 T# X $end +$var wire 1 H# A $end +$var wire 1 44 buf0_out_X $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mem_left_track_9 $end +$var wire 1 ( pReset [0] $end +$var wire 1 Y! prog_clk [0] $end +$var wire 1 T# ccff_head [0] $end +$var wire 1 J# ccff_tail [0] $end +$var wire 1 {" mem_out [0] $end +$var wire 1 |" mem_out [1] $end +$var wire 1 }" mem_out [2] $end +$var wire 1 ~" mem_out [3] $end + +$scope module sky130_fd_sc_hd__dfrtp_1_0_ $end +$var wire 1 {" Q $end +$var wire 1 Y! CLK $end +$var wire 1 T# D $end +$var wire 1 ( RESET_B $end +$var supply1 1 54 VPWR $end +$var supply0 1 64 VGND $end +$var supply1 1 74 VPB $end +$var supply0 1 84 VNB $end + +$scope module base $end +$var wire 1 {" Q $end +$var wire 1 Y! CLK $end +$var wire 1 T# D $end +$var wire 1 ( RESET_B $end +$var wire 1 94 buf_Q $end +$var wire 1 :4 RESET $end +$upscope $end +$upscope $end + +$scope module sky130_fd_sc_hd__dfrtp_1_1_ $end +$var wire 1 |" Q $end +$var wire 1 Y! CLK $end +$var wire 1 {" D $end +$var wire 1 ( RESET_B $end +$var supply1 1 ;4 VPWR $end +$var supply0 1 <4 VGND $end +$var supply1 1 =4 VPB $end +$var supply0 1 >4 VNB $end + +$scope module base $end +$var wire 1 |" Q $end +$var wire 1 Y! CLK $end +$var wire 1 {" D $end +$var wire 1 ( RESET_B $end +$var wire 1 ?4 buf_Q $end +$var wire 1 @4 RESET $end +$upscope $end +$upscope $end + +$scope module sky130_fd_sc_hd__dfrtp_1_2_ $end +$var wire 1 }" Q $end +$var wire 1 Y! CLK $end +$var wire 1 |" D $end +$var wire 1 ( RESET_B $end +$var supply1 1 A4 VPWR $end +$var supply0 1 B4 VGND $end +$var supply1 1 C4 VPB $end +$var supply0 1 D4 VNB $end + +$scope module base $end +$var wire 1 }" Q $end +$var wire 1 Y! CLK $end +$var wire 1 |" D $end +$var wire 1 ( RESET_B $end +$var wire 1 E4 buf_Q $end +$var wire 1 F4 RESET $end +$upscope $end +$upscope $end + +$scope module sky130_fd_sc_hd__dfrtp_1_3_ $end +$var wire 1 ~" Q $end +$var wire 1 Y! CLK $end +$var wire 1 }" D $end +$var wire 1 ( RESET_B $end +$var supply1 1 G4 VPWR $end +$var supply0 1 H4 VGND $end +$var supply1 1 I4 VPB $end +$var supply0 1 J4 VNB $end + +$scope module base $end +$var wire 1 ~" Q $end +$var wire 1 Y! CLK $end +$var wire 1 }" D $end +$var wire 1 ( RESET_B $end +$var wire 1 K4 buf_Q $end +$var wire 1 L4 RESET $end +$upscope $end +$upscope $end + +$scope module FTB_35__34 $end +$var wire 1 J# X $end +$var wire 1 ~" A $end +$var supply1 1 M4 VPWR $end +$var supply0 1 N4 VGND $end +$var supply1 1 O4 VPB $end +$var supply0 1 P4 VNB $end + +$scope module base $end +$var wire 1 J# X $end +$var wire 1 ~" A $end +$var wire 1 Q4 buf0_out_X $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mem_left_track_11 $end +$var wire 1 ( pReset [0] $end +$var wire 1 Y! prog_clk [0] $end +$var wire 1 J# ccff_head [0] $end +$var wire 1 K# ccff_tail [0] $end +$var wire 1 !# mem_out [0] $end +$var wire 1 "# mem_out [1] $end +$var wire 1 ## mem_out [2] $end +$var wire 1 $# mem_out [3] $end + +$scope module sky130_fd_sc_hd__dfrtp_1_0_ $end +$var wire 1 !# Q $end +$var wire 1 Y! CLK $end +$var wire 1 J# D $end +$var wire 1 ( RESET_B $end +$var supply1 1 R4 VPWR $end +$var supply0 1 S4 VGND $end +$var supply1 1 T4 VPB $end +$var supply0 1 U4 VNB $end + +$scope module base $end +$var wire 1 !# Q $end +$var wire 1 Y! CLK $end +$var wire 1 J# D $end +$var wire 1 ( RESET_B $end +$var wire 1 V4 buf_Q $end +$var wire 1 W4 RESET $end +$upscope $end +$upscope $end + +$scope module sky130_fd_sc_hd__dfrtp_1_1_ $end +$var wire 1 "# Q $end +$var wire 1 Y! CLK $end +$var wire 1 !# D $end +$var wire 1 ( RESET_B $end +$var supply1 1 X4 VPWR $end +$var supply0 1 Y4 VGND $end +$var supply1 1 Z4 VPB $end +$var supply0 1 [4 VNB $end + +$scope module base $end +$var wire 1 "# Q $end +$var wire 1 Y! CLK $end +$var wire 1 !# D $end +$var wire 1 ( RESET_B $end +$var wire 1 \4 buf_Q $end +$var wire 1 ]4 RESET $end +$upscope $end +$upscope $end + +$scope module sky130_fd_sc_hd__dfrtp_1_2_ $end +$var wire 1 ## Q $end +$var wire 1 Y! CLK $end +$var wire 1 "# D $end +$var wire 1 ( RESET_B $end +$var supply1 1 ^4 VPWR $end +$var supply0 1 _4 VGND $end +$var supply1 1 `4 VPB $end +$var supply0 1 a4 VNB $end + +$scope module base $end +$var wire 1 ## Q $end +$var wire 1 Y! CLK $end +$var wire 1 "# D $end +$var wire 1 ( RESET_B $end +$var wire 1 b4 buf_Q $end +$var wire 1 c4 RESET $end +$upscope $end +$upscope $end + +$scope module sky130_fd_sc_hd__dfrtp_1_3_ $end +$var wire 1 $# Q $end +$var wire 1 Y! CLK $end +$var wire 1 ## D $end +$var wire 1 ( RESET_B $end +$var supply1 1 d4 VPWR $end +$var supply0 1 e4 VGND $end +$var supply1 1 f4 VPB $end +$var supply0 1 g4 VNB $end + +$scope module base $end +$var wire 1 $# Q $end +$var wire 1 Y! CLK $end +$var wire 1 ## D $end +$var wire 1 ( RESET_B $end +$var wire 1 h4 buf_Q $end +$var wire 1 i4 RESET $end +$upscope $end +$upscope $end + +$scope module FTB_36__35 $end +$var wire 1 K# X $end +$var wire 1 $# A $end +$var supply1 1 j4 VPWR $end +$var supply0 1 k4 VGND $end +$var supply1 1 l4 VPB $end +$var supply0 1 m4 VNB $end + +$scope module base $end +$var wire 1 K# X $end +$var wire 1 $# A $end +$var wire 1 n4 buf0_out_X $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mux_bottom_track_13 $end +$var wire 1 G in [0] $end +$var wire 1 W in [1] $end +$var wire 1 [! sram [0] $end +$var wire 1 \! sram [1] $end +$var wire 1 *$ sram_inv [0] $end +$var wire 1 +$ sram_inv [1] $end +$var wire 1 } out [0] $end +$var wire 1 k# p0 $end +$var wire 1 o4 mux_2level_tapbuf_basis_input2_mem1_0_out [0] $end +$var wire 1 p4 mux_2level_tapbuf_basis_input2_mem1_1_out [0] $end +$var wire 1 q4 SYNOPSYS_UNCONNECTED_1 $end +$var wire 1 r4 SYNOPSYS_UNCONNECTED_2 $end +$var wire 1 s4 SYNOPSYS_UNCONNECTED_3 $end + +$scope module mux_l1_in_0_ $end +$var wire 1 G in [0] $end +$var wire 1 W in [1] $end +$var wire 1 [! mem [0] $end +$var wire 1 q4 mem_inv [0] $end +$var wire 1 o4 out [0] $end + +$scope module sky130_fd_sc_hd__mux2_1_0 $end +$var wire 1 o4 X $end +$var wire 1 W A0 $end +$var wire 1 G A1 $end +$var wire 1 [! S $end +$var supply1 1 t4 VPWR $end +$var supply0 1 u4 VGND $end +$var supply1 1 v4 VPB $end +$var supply0 1 w4 VNB $end + +$scope module base $end +$var wire 1 o4 X $end +$var wire 1 W A0 $end +$var wire 1 G A1 $end +$var wire 1 [! S $end +$var wire 1 x4 mux_2to10_out_X $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mux_l2_in_0_ $end +$var wire 1 o4 in [0] $end +$var wire 1 r4 in [1] $end +$var wire 1 \! mem [0] $end +$var wire 1 s4 mem_inv [0] $end +$var wire 1 p4 out [0] $end +$var wire 1 k# p0 $end + +$scope module sky130_fd_sc_hd__mux2_1_0 $end +$var wire 1 p4 X $end +$var wire 1 k# A0 $end +$var wire 1 o4 A1 $end +$var wire 1 \! S $end +$var supply1 1 y4 VPWR $end +$var supply0 1 z4 VGND $end +$var supply1 1 {4 VPB $end +$var supply0 1 |4 VNB $end + +$scope module base $end +$var wire 1 p4 X $end +$var wire 1 k# A0 $end +$var wire 1 o4 A1 $end +$var wire 1 \! S $end +$var wire 1 }4 mux_2to10_out_X $end +$upscope $end +$upscope $end +$upscope $end + +$scope module BUFT_RR_108 $end +$var wire 1 } X $end +$var wire 1 p4 A $end +$var supply1 1 ~4 VPWR $end +$var supply0 1 !5 VGND $end +$var supply1 1 "5 VPB $end +$var supply0 1 #5 VNB $end + +$scope module base $end +$var wire 1 } X $end +$var wire 1 p4 A $end +$var wire 1 $5 buf0_out_X $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mux_bottom_track_15 $end +$var wire 1 H in [0] $end +$var wire 1 X in [1] $end +$var wire 1 q! sram [0] $end +$var wire 1 r! sram [1] $end +$var wire 1 ,$ sram_inv [0] $end +$var wire 1 -$ sram_inv [1] $end +$var wire 1 ~ out [0] $end +$var wire 1 .$ p0 $end +$var wire 1 %5 mux_2level_tapbuf_basis_input2_mem1_0_out [0] $end +$var wire 1 &5 mux_2level_tapbuf_basis_input2_mem1_1_out [0] $end +$var wire 1 '5 SYNOPSYS_UNCONNECTED_1 $end +$var wire 1 (5 SYNOPSYS_UNCONNECTED_2 $end +$var wire 1 )5 SYNOPSYS_UNCONNECTED_3 $end + +$scope module mux_l1_in_0_ $end +$var wire 1 H in [0] $end +$var wire 1 X in [1] $end +$var wire 1 q! mem [0] $end +$var wire 1 '5 mem_inv [0] $end +$var wire 1 %5 out [0] $end + +$scope module sky130_fd_sc_hd__mux2_1_0 $end +$var wire 1 %5 X $end +$var wire 1 X A0 $end +$var wire 1 H A1 $end +$var wire 1 q! S $end +$var supply1 1 *5 VPWR $end +$var supply0 1 +5 VGND $end +$var supply1 1 ,5 VPB $end +$var supply0 1 -5 VNB $end + +$scope module base $end +$var wire 1 %5 X $end +$var wire 1 X A0 $end +$var wire 1 H A1 $end +$var wire 1 q! S $end +$var wire 1 .5 mux_2to10_out_X $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mux_l2_in_0_ $end +$var wire 1 %5 in [0] $end +$var wire 1 (5 in [1] $end +$var wire 1 r! mem [0] $end +$var wire 1 )5 mem_inv [0] $end +$var wire 1 &5 out [0] $end +$var wire 1 .$ p0 $end + +$scope module sky130_fd_sc_hd__mux2_1_0 $end +$var wire 1 &5 X $end +$var wire 1 .$ A0 $end +$var wire 1 %5 A1 $end +$var wire 1 r! S $end +$var supply1 1 /5 VPWR $end +$var supply0 1 05 VGND $end +$var supply1 1 15 VPB $end +$var supply0 1 25 VNB $end + +$scope module base $end +$var wire 1 &5 X $end +$var wire 1 .$ A0 $end +$var wire 1 %5 A1 $end +$var wire 1 r! S $end +$var wire 1 35 mux_2to10_out_X $end +$upscope $end +$upscope $end +$upscope $end + +$scope module BUFT_RR_109 $end +$var wire 1 ~ X $end +$var wire 1 &5 A $end +$var supply1 1 45 VPWR $end +$var supply0 1 55 VGND $end +$var supply1 1 65 VPB $end +$var supply0 1 75 VNB $end + +$scope module base $end +$var wire 1 ~ X $end +$var wire 1 &5 A $end +$var wire 1 85 buf0_out_X $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mux_bottom_track_17 $end +$var wire 1 I in [0] $end +$var wire 1 Y in [1] $end +$var wire 1 )" sram [0] $end +$var wire 1 *" sram [1] $end +$var wire 1 /$ sram_inv [0] $end +$var wire 1 0$ sram_inv [1] $end +$var wire 1 !! out [0] $end +$var wire 1 .$ p0 $end +$var wire 1 95 mux_2level_tapbuf_basis_input2_mem1_0_out [0] $end +$var wire 1 :5 mux_2level_tapbuf_basis_input2_mem1_1_out [0] $end +$var wire 1 ;5 SYNOPSYS_UNCONNECTED_1 $end +$var wire 1 <5 SYNOPSYS_UNCONNECTED_2 $end +$var wire 1 =5 SYNOPSYS_UNCONNECTED_3 $end +$var wire 1 >5 BUF_net_111 $end + +$scope module mux_l1_in_0_ $end +$var wire 1 I in [0] $end +$var wire 1 Y in [1] $end +$var wire 1 )" mem [0] $end +$var wire 1 ;5 mem_inv [0] $end +$var wire 1 95 out [0] $end + +$scope module sky130_fd_sc_hd__mux2_1_0 $end +$var wire 1 95 X $end +$var wire 1 Y A0 $end +$var wire 1 I A1 $end +$var wire 1 )" S $end +$var supply1 1 ?5 VPWR $end +$var supply0 1 @5 VGND $end +$var supply1 1 A5 VPB $end +$var supply0 1 B5 VNB $end + +$scope module base $end +$var wire 1 95 X $end +$var wire 1 Y A0 $end +$var wire 1 I A1 $end +$var wire 1 )" S $end +$var wire 1 C5 mux_2to10_out_X $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mux_l2_in_0_ $end +$var wire 1 95 in [0] $end +$var wire 1 <5 in [1] $end +$var wire 1 *" mem [0] $end +$var wire 1 =5 mem_inv [0] $end +$var wire 1 :5 out [0] $end +$var wire 1 .$ p0 $end + +$scope module sky130_fd_sc_hd__mux2_1_0 $end +$var wire 1 :5 X $end +$var wire 1 .$ A0 $end +$var wire 1 95 A1 $end +$var wire 1 *" S $end +$var supply1 1 D5 VPWR $end +$var supply0 1 E5 VGND $end +$var supply1 1 F5 VPB $end +$var supply0 1 G5 VNB $end + +$scope module base $end +$var wire 1 :5 X $end +$var wire 1 .$ A0 $end +$var wire 1 95 A1 $end +$var wire 1 *" S $end +$var wire 1 H5 mux_2to10_out_X $end +$upscope $end +$upscope $end +$upscope $end + +$scope module BINV_R_110 $end +$var wire 1 !! Y $end +$var wire 1 >5 A $end +$var supply1 1 I5 VPWR $end +$var supply0 1 J5 VGND $end +$var supply1 1 K5 VPB $end +$var supply0 1 L5 VNB $end + +$scope module base $end +$var wire 1 !! Y $end +$var wire 1 >5 A $end +$var wire 1 M5 not0_out_Y $end +$upscope $end +$upscope $end + +$scope module BINV_R_111 $end +$var wire 1 >5 Y $end +$var wire 1 :5 A $end +$var supply1 1 N5 VPWR $end +$var supply0 1 O5 VGND $end +$var supply1 1 P5 VPB $end +$var supply0 1 Q5 VNB $end + +$scope module base $end +$var wire 1 >5 Y $end +$var wire 1 :5 A $end +$var wire 1 R5 not0_out_Y $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mux_bottom_track_19 $end +$var wire 1 J in [0] $end +$var wire 1 Z in [1] $end +$var wire 1 9" sram [0] $end +$var wire 1 :" sram [1] $end +$var wire 1 1$ sram_inv [0] $end +$var wire 1 2$ sram_inv [1] $end +$var wire 1 "! out [0] $end +$var wire 1 .$ p0 $end +$var wire 1 S5 mux_2level_tapbuf_basis_input2_mem1_0_out [0] $end +$var wire 1 T5 mux_2level_tapbuf_basis_input2_mem1_1_out [0] $end +$var wire 1 U5 SYNOPSYS_UNCONNECTED_1 $end +$var wire 1 V5 SYNOPSYS_UNCONNECTED_2 $end +$var wire 1 W5 SYNOPSYS_UNCONNECTED_3 $end + +$scope module sky130_fd_sc_hd__buf_4_0_ $end +$var wire 1 "! X $end +$var wire 1 T5 A $end +$var supply1 1 X5 VPWR $end +$var supply0 1 Y5 VGND $end +$var supply1 1 Z5 VPB $end +$var supply0 1 [5 VNB $end + +$scope module base $end +$var wire 1 "! X $end +$var wire 1 T5 A $end +$var wire 1 \5 buf0_out_X $end +$upscope $end +$upscope $end + +$scope module mux_l1_in_0_ $end +$var wire 1 J in [0] $end +$var wire 1 Z in [1] $end +$var wire 1 9" mem [0] $end +$var wire 1 U5 mem_inv [0] $end +$var wire 1 S5 out [0] $end + +$scope module sky130_fd_sc_hd__mux2_1_0 $end +$var wire 1 S5 X $end +$var wire 1 Z A0 $end +$var wire 1 J A1 $end +$var wire 1 9" S $end +$var supply1 1 ]5 VPWR $end +$var supply0 1 ^5 VGND $end +$var supply1 1 _5 VPB $end +$var supply0 1 `5 VNB $end + +$scope module base $end +$var wire 1 S5 X $end +$var wire 1 Z A0 $end +$var wire 1 J A1 $end +$var wire 1 9" S $end +$var wire 1 a5 mux_2to10_out_X $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mux_l2_in_0_ $end +$var wire 1 S5 in [0] $end +$var wire 1 V5 in [1] $end +$var wire 1 :" mem [0] $end +$var wire 1 W5 mem_inv [0] $end +$var wire 1 T5 out [0] $end +$var wire 1 .$ p0 $end + +$scope module sky130_fd_sc_hd__mux2_1_0 $end +$var wire 1 T5 X $end +$var wire 1 .$ A0 $end +$var wire 1 S5 A1 $end +$var wire 1 :" S $end +$var supply1 1 b5 VPWR $end +$var supply0 1 c5 VGND $end +$var supply1 1 d5 VPB $end +$var supply0 1 e5 VNB $end + +$scope module base $end +$var wire 1 T5 X $end +$var wire 1 .$ A0 $end +$var wire 1 S5 A1 $end +$var wire 1 :" S $end +$var wire 1 f5 mux_2to10_out_X $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mux_bottom_track_21 $end +$var wire 1 K in [0] $end +$var wire 1 [ in [1] $end +$var wire 1 ;" sram [0] $end +$var wire 1 <" sram [1] $end +$var wire 1 3$ sram_inv [0] $end +$var wire 1 4$ sram_inv [1] $end +$var wire 1 #! out [0] $end +$var wire 1 5$ p0 $end +$var wire 1 g5 mux_2level_tapbuf_basis_input2_mem1_0_out [0] $end +$var wire 1 h5 mux_2level_tapbuf_basis_input2_mem1_1_out [0] $end +$var wire 1 i5 SYNOPSYS_UNCONNECTED_1 $end +$var wire 1 j5 SYNOPSYS_UNCONNECTED_2 $end +$var wire 1 k5 SYNOPSYS_UNCONNECTED_3 $end +$var wire 1 l5 BUF_net_113 $end + +$scope module mux_l1_in_0_ $end +$var wire 1 K in [0] $end +$var wire 1 [ in [1] $end +$var wire 1 ;" mem [0] $end +$var wire 1 i5 mem_inv [0] $end +$var wire 1 g5 out [0] $end + +$scope module sky130_fd_sc_hd__mux2_1_0 $end +$var wire 1 g5 X $end +$var wire 1 [ A0 $end +$var wire 1 K A1 $end +$var wire 1 ;" S $end +$var supply1 1 m5 VPWR $end +$var supply0 1 n5 VGND $end +$var supply1 1 o5 VPB $end +$var supply0 1 p5 VNB $end + +$scope module base $end +$var wire 1 g5 X $end +$var wire 1 [ A0 $end +$var wire 1 K A1 $end +$var wire 1 ;" S $end +$var wire 1 q5 mux_2to10_out_X $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mux_l2_in_0_ $end +$var wire 1 g5 in [0] $end +$var wire 1 j5 in [1] $end +$var wire 1 <" mem [0] $end +$var wire 1 k5 mem_inv [0] $end +$var wire 1 h5 out [0] $end +$var wire 1 5$ p0 $end + +$scope module sky130_fd_sc_hd__mux2_1_0 $end +$var wire 1 h5 X $end +$var wire 1 5$ A0 $end +$var wire 1 g5 A1 $end +$var wire 1 <" S $end +$var supply1 1 r5 VPWR $end +$var supply0 1 s5 VGND $end +$var supply1 1 t5 VPB $end +$var supply0 1 u5 VNB $end + +$scope module base $end +$var wire 1 h5 X $end +$var wire 1 5$ A0 $end +$var wire 1 g5 A1 $end +$var wire 1 <" S $end +$var wire 1 v5 mux_2to10_out_X $end +$upscope $end +$upscope $end +$upscope $end + +$scope module BINV_R_112 $end +$var wire 1 #! Y $end +$var wire 1 l5 A $end +$var supply1 1 w5 VPWR $end +$var supply0 1 x5 VGND $end +$var supply1 1 y5 VPB $end +$var supply0 1 z5 VNB $end + +$scope module base $end +$var wire 1 #! Y $end +$var wire 1 l5 A $end +$var wire 1 {5 not0_out_Y $end +$upscope $end +$upscope $end + +$scope module BINV_R_113 $end +$var wire 1 l5 Y $end +$var wire 1 h5 A $end +$var supply1 1 |5 VPWR $end +$var supply0 1 }5 VGND $end +$var supply1 1 ~5 VPB $end +$var supply0 1 !6 VNB $end + +$scope module base $end +$var wire 1 l5 Y $end +$var wire 1 h5 A $end +$var wire 1 "6 not0_out_Y $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mux_bottom_track_23 $end +$var wire 1 L in [0] $end +$var wire 1 \ in [1] $end +$var wire 1 =" sram [0] $end +$var wire 1 >" sram [1] $end +$var wire 1 6$ sram_inv [0] $end +$var wire 1 7$ sram_inv [1] $end +$var wire 1 $! out [0] $end +$var wire 1 5$ p0 $end +$var wire 1 #6 mux_2level_tapbuf_basis_input2_mem1_0_out [0] $end +$var wire 1 $6 mux_2level_tapbuf_basis_input2_mem1_1_out [0] $end +$var wire 1 %6 SYNOPSYS_UNCONNECTED_1 $end +$var wire 1 &6 SYNOPSYS_UNCONNECTED_2 $end +$var wire 1 '6 SYNOPSYS_UNCONNECTED_3 $end +$var wire 1 (6 BUF_net_115 $end + +$scope module mux_l1_in_0_ $end +$var wire 1 L in [0] $end +$var wire 1 \ in [1] $end +$var wire 1 =" mem [0] $end +$var wire 1 %6 mem_inv [0] $end +$var wire 1 #6 out [0] $end + +$scope module sky130_fd_sc_hd__mux2_1_0 $end +$var wire 1 #6 X $end +$var wire 1 \ A0 $end +$var wire 1 L A1 $end +$var wire 1 =" S $end +$var supply1 1 )6 VPWR $end +$var supply0 1 *6 VGND $end +$var supply1 1 +6 VPB $end +$var supply0 1 ,6 VNB $end + +$scope module base $end +$var wire 1 #6 X $end +$var wire 1 \ A0 $end +$var wire 1 L A1 $end +$var wire 1 =" S $end +$var wire 1 -6 mux_2to10_out_X $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mux_l2_in_0_ $end +$var wire 1 #6 in [0] $end +$var wire 1 &6 in [1] $end +$var wire 1 >" mem [0] $end +$var wire 1 '6 mem_inv [0] $end +$var wire 1 $6 out [0] $end +$var wire 1 5$ p0 $end + +$scope module sky130_fd_sc_hd__mux2_1_0 $end +$var wire 1 $6 X $end +$var wire 1 5$ A0 $end +$var wire 1 #6 A1 $end +$var wire 1 >" S $end +$var supply1 1 .6 VPWR $end +$var supply0 1 /6 VGND $end +$var supply1 1 06 VPB $end +$var supply0 1 16 VNB $end + +$scope module base $end +$var wire 1 $6 X $end +$var wire 1 5$ A0 $end +$var wire 1 #6 A1 $end +$var wire 1 >" S $end +$var wire 1 26 mux_2to10_out_X $end +$upscope $end +$upscope $end +$upscope $end + +$scope module BINV_R_114 $end +$var wire 1 $! Y $end +$var wire 1 (6 A $end +$var supply1 1 36 VPWR $end +$var supply0 1 46 VGND $end +$var supply1 1 56 VPB $end +$var supply0 1 66 VNB $end + +$scope module base $end +$var wire 1 $! Y $end +$var wire 1 (6 A $end +$var wire 1 76 not0_out_Y $end +$upscope $end +$upscope $end + +$scope module BINV_R_115 $end +$var wire 1 (6 Y $end +$var wire 1 $6 A $end +$var supply1 1 86 VPWR $end +$var supply0 1 96 VGND $end +$var supply1 1 :6 VPB $end +$var supply0 1 ;6 VNB $end + +$scope module base $end +$var wire 1 (6 Y $end +$var wire 1 $6 A $end +$var wire 1 <6 not0_out_Y $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mux_bottom_track_25 $end +$var wire 1 M in [0] $end +$var wire 1 ] in [1] $end +$var wire 1 ?" sram [0] $end +$var wire 1 @" sram [1] $end +$var wire 1 8$ sram_inv [0] $end +$var wire 1 9$ sram_inv [1] $end +$var wire 1 %! out [0] $end +$var wire 1 Y# p0 $end +$var wire 1 =6 mux_2level_tapbuf_basis_input2_mem1_0_out [0] $end +$var wire 1 >6 mux_2level_tapbuf_basis_input2_mem1_1_out [0] $end +$var wire 1 ?6 SYNOPSYS_UNCONNECTED_1 $end +$var wire 1 @6 SYNOPSYS_UNCONNECTED_2 $end +$var wire 1 A6 SYNOPSYS_UNCONNECTED_3 $end +$var wire 1 B6 BUF_net_117 $end + +$scope module mux_l1_in_0_ $end +$var wire 1 M in [0] $end +$var wire 1 ] in [1] $end +$var wire 1 ?" mem [0] $end +$var wire 1 ?6 mem_inv [0] $end +$var wire 1 =6 out [0] $end + +$scope module sky130_fd_sc_hd__mux2_1_0 $end +$var wire 1 =6 X $end +$var wire 1 ] A0 $end +$var wire 1 M A1 $end +$var wire 1 ?" S $end +$var supply1 1 C6 VPWR $end +$var supply0 1 D6 VGND $end +$var supply1 1 E6 VPB $end +$var supply0 1 F6 VNB $end + +$scope module base $end +$var wire 1 =6 X $end +$var wire 1 ] A0 $end +$var wire 1 M A1 $end +$var wire 1 ?" S $end +$var wire 1 G6 mux_2to10_out_X $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mux_l2_in_0_ $end +$var wire 1 =6 in [0] $end +$var wire 1 @6 in [1] $end +$var wire 1 @" mem [0] $end +$var wire 1 A6 mem_inv [0] $end +$var wire 1 >6 out [0] $end +$var wire 1 Y# p0 $end + +$scope module sky130_fd_sc_hd__mux2_1_0 $end +$var wire 1 >6 X $end +$var wire 1 Y# A0 $end +$var wire 1 =6 A1 $end +$var wire 1 @" S $end +$var supply1 1 H6 VPWR $end +$var supply0 1 I6 VGND $end +$var supply1 1 J6 VPB $end +$var supply0 1 K6 VNB $end + +$scope module base $end +$var wire 1 >6 X $end +$var wire 1 Y# A0 $end +$var wire 1 =6 A1 $end +$var wire 1 @" S $end +$var wire 1 L6 mux_2to10_out_X $end +$upscope $end +$upscope $end +$upscope $end + +$scope module BINV_R_116 $end +$var wire 1 %! Y $end +$var wire 1 B6 A $end +$var supply1 1 M6 VPWR $end +$var supply0 1 N6 VGND $end +$var supply1 1 O6 VPB $end +$var supply0 1 P6 VNB $end + +$scope module base $end +$var wire 1 %! Y $end +$var wire 1 B6 A $end +$var wire 1 Q6 not0_out_Y $end +$upscope $end +$upscope $end + +$scope module BINV_R_117 $end +$var wire 1 B6 Y $end +$var wire 1 >6 A $end +$var supply1 1 R6 VPWR $end +$var supply0 1 S6 VGND $end +$var supply1 1 T6 VPB $end +$var supply0 1 U6 VNB $end + +$scope module base $end +$var wire 1 B6 Y $end +$var wire 1 >6 A $end +$var wire 1 V6 not0_out_Y $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mux_bottom_track_27 $end +$var wire 1 N in [0] $end +$var wire 1 ^ in [1] $end +$var wire 1 A" sram [0] $end +$var wire 1 B" sram [1] $end +$var wire 1 :$ sram_inv [0] $end +$var wire 1 ;$ sram_inv [1] $end +$var wire 1 &! out [0] $end +$var wire 1 k# p0 $end +$var wire 1 W6 mux_2level_tapbuf_basis_input2_mem1_0_out [0] $end +$var wire 1 X6 mux_2level_tapbuf_basis_input2_mem1_1_out [0] $end +$var wire 1 Y6 SYNOPSYS_UNCONNECTED_1 $end +$var wire 1 Z6 SYNOPSYS_UNCONNECTED_2 $end +$var wire 1 [6 SYNOPSYS_UNCONNECTED_3 $end +$var wire 1 \6 BUF_net_119 $end + +$scope module mux_l1_in_0_ $end +$var wire 1 N in [0] $end +$var wire 1 ^ in [1] $end +$var wire 1 A" mem [0] $end +$var wire 1 Y6 mem_inv [0] $end +$var wire 1 W6 out [0] $end + +$scope module sky130_fd_sc_hd__mux2_1_0 $end +$var wire 1 W6 X $end +$var wire 1 ^ A0 $end +$var wire 1 N A1 $end +$var wire 1 A" S $end +$var supply1 1 ]6 VPWR $end +$var supply0 1 ^6 VGND $end +$var supply1 1 _6 VPB $end +$var supply0 1 `6 VNB $end + +$scope module base $end +$var wire 1 W6 X $end +$var wire 1 ^ A0 $end +$var wire 1 N A1 $end +$var wire 1 A" S $end +$var wire 1 a6 mux_2to10_out_X $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mux_l2_in_0_ $end +$var wire 1 W6 in [0] $end +$var wire 1 Z6 in [1] $end +$var wire 1 B" mem [0] $end +$var wire 1 [6 mem_inv [0] $end +$var wire 1 X6 out [0] $end +$var wire 1 k# p0 $end + +$scope module sky130_fd_sc_hd__mux2_1_0 $end +$var wire 1 X6 X $end +$var wire 1 k# A0 $end +$var wire 1 W6 A1 $end +$var wire 1 B" S $end +$var supply1 1 b6 VPWR $end +$var supply0 1 c6 VGND $end +$var supply1 1 d6 VPB $end +$var supply0 1 e6 VNB $end + +$scope module base $end +$var wire 1 X6 X $end +$var wire 1 k# A0 $end +$var wire 1 W6 A1 $end +$var wire 1 B" S $end +$var wire 1 f6 mux_2to10_out_X $end +$upscope $end +$upscope $end +$upscope $end + +$scope module BINV_R_118 $end +$var wire 1 &! Y $end +$var wire 1 \6 A $end +$var supply1 1 g6 VPWR $end +$var supply0 1 h6 VGND $end +$var supply1 1 i6 VPB $end +$var supply0 1 j6 VNB $end + +$scope module base $end +$var wire 1 &! Y $end +$var wire 1 \6 A $end +$var wire 1 k6 not0_out_Y $end +$upscope $end +$upscope $end + +$scope module BINV_R_119 $end +$var wire 1 \6 Y $end +$var wire 1 X6 A $end +$var supply1 1 l6 VPWR $end +$var supply0 1 m6 VGND $end +$var supply1 1 n6 VPB $end +$var supply0 1 o6 VNB $end + +$scope module base $end +$var wire 1 \6 Y $end +$var wire 1 X6 A $end +$var wire 1 p6 not0_out_Y $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mux_bottom_track_39 $end +$var wire 1 H in [0] $end +$var wire 1 d in [1] $end +$var wire 1 C" sram [0] $end +$var wire 1 D" sram [1] $end +$var wire 1 <$ sram_inv [0] $end +$var wire 1 =$ sram_inv [1] $end +$var wire 1 ,! out [0] $end +$var wire 1 5$ p0 $end +$var wire 1 q6 mux_2level_tapbuf_basis_input2_mem1_0_out [0] $end +$var wire 1 r6 mux_2level_tapbuf_basis_input2_mem1_1_out [0] $end +$var wire 1 s6 SYNOPSYS_UNCONNECTED_1 $end +$var wire 1 t6 SYNOPSYS_UNCONNECTED_2 $end +$var wire 1 u6 SYNOPSYS_UNCONNECTED_3 $end +$var wire 1 v6 BUF_net_121 $end + +$scope module mux_l1_in_0_ $end +$var wire 1 H in [0] $end +$var wire 1 d in [1] $end +$var wire 1 C" mem [0] $end +$var wire 1 s6 mem_inv [0] $end +$var wire 1 q6 out [0] $end + +$scope module sky130_fd_sc_hd__mux2_1_0 $end +$var wire 1 q6 X $end +$var wire 1 d A0 $end +$var wire 1 H A1 $end +$var wire 1 C" S $end +$var supply1 1 w6 VPWR $end +$var supply0 1 x6 VGND $end +$var supply1 1 y6 VPB $end +$var supply0 1 z6 VNB $end + +$scope module base $end +$var wire 1 q6 X $end +$var wire 1 d A0 $end +$var wire 1 H A1 $end +$var wire 1 C" S $end +$var wire 1 {6 mux_2to10_out_X $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mux_l2_in_0_ $end +$var wire 1 q6 in [0] $end +$var wire 1 t6 in [1] $end +$var wire 1 D" mem [0] $end +$var wire 1 u6 mem_inv [0] $end +$var wire 1 r6 out [0] $end +$var wire 1 5$ p0 $end + +$scope module sky130_fd_sc_hd__mux2_1_0 $end +$var wire 1 r6 X $end +$var wire 1 5$ A0 $end +$var wire 1 q6 A1 $end +$var wire 1 D" S $end +$var supply1 1 |6 VPWR $end +$var supply0 1 }6 VGND $end +$var supply1 1 ~6 VPB $end +$var supply0 1 !7 VNB $end + +$scope module base $end +$var wire 1 r6 X $end +$var wire 1 5$ A0 $end +$var wire 1 q6 A1 $end +$var wire 1 D" S $end +$var wire 1 "7 mux_2to10_out_X $end +$upscope $end +$upscope $end +$upscope $end + +$scope module BINV_R_120 $end +$var wire 1 ,! Y $end +$var wire 1 v6 A $end +$var supply1 1 #7 VPWR $end +$var supply0 1 $7 VGND $end +$var supply1 1 %7 VPB $end +$var supply0 1 &7 VNB $end + +$scope module base $end +$var wire 1 ,! Y $end +$var wire 1 v6 A $end +$var wire 1 '7 not0_out_Y $end +$upscope $end +$upscope $end + +$scope module BINV_R_121 $end +$var wire 1 v6 Y $end +$var wire 1 r6 A $end +$var supply1 1 (7 VPWR $end +$var supply0 1 )7 VGND $end +$var supply1 1 *7 VPB $end +$var supply0 1 +7 VNB $end + +$scope module base $end +$var wire 1 v6 Y $end +$var wire 1 r6 A $end +$var wire 1 ,7 not0_out_Y $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mux_bottom_track_41 $end +$var wire 1 I in [0] $end +$var wire 1 e in [1] $end +$var wire 1 E" sram [0] $end +$var wire 1 F" sram [1] $end +$var wire 1 >$ sram_inv [0] $end +$var wire 1 ?$ sram_inv [1] $end +$var wire 1 -! out [0] $end +$var wire 1 .$ p0 $end +$var wire 1 -7 mux_2level_tapbuf_basis_input2_mem1_0_out [0] $end +$var wire 1 .7 mux_2level_tapbuf_basis_input2_mem1_1_out [0] $end +$var wire 1 /7 SYNOPSYS_UNCONNECTED_1 $end +$var wire 1 07 SYNOPSYS_UNCONNECTED_2 $end +$var wire 1 17 SYNOPSYS_UNCONNECTED_3 $end + +$scope module sky130_fd_sc_hd__buf_4_0_ $end +$var wire 1 -! X $end +$var wire 1 .7 A $end +$var supply1 1 27 VPWR $end +$var supply0 1 37 VGND $end +$var supply1 1 47 VPB $end +$var supply0 1 57 VNB $end + +$scope module base $end +$var wire 1 -! X $end +$var wire 1 .7 A $end +$var wire 1 67 buf0_out_X $end +$upscope $end +$upscope $end + +$scope module mux_l1_in_0_ $end +$var wire 1 I in [0] $end +$var wire 1 e in [1] $end +$var wire 1 E" mem [0] $end +$var wire 1 /7 mem_inv [0] $end +$var wire 1 -7 out [0] $end + +$scope module sky130_fd_sc_hd__mux2_1_0 $end +$var wire 1 -7 X $end +$var wire 1 e A0 $end +$var wire 1 I A1 $end +$var wire 1 E" S $end +$var supply1 1 77 VPWR $end +$var supply0 1 87 VGND $end +$var supply1 1 97 VPB $end +$var supply0 1 :7 VNB $end + +$scope module base $end +$var wire 1 -7 X $end +$var wire 1 e A0 $end +$var wire 1 I A1 $end +$var wire 1 E" S $end +$var wire 1 ;7 mux_2to10_out_X $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mux_l2_in_0_ $end +$var wire 1 -7 in [0] $end +$var wire 1 07 in [1] $end +$var wire 1 F" mem [0] $end +$var wire 1 17 mem_inv [0] $end +$var wire 1 .7 out [0] $end +$var wire 1 .$ p0 $end + +$scope module sky130_fd_sc_hd__mux2_1_0 $end +$var wire 1 .7 X $end +$var wire 1 .$ A0 $end +$var wire 1 -7 A1 $end +$var wire 1 F" S $end +$var supply1 1 <7 VPWR $end +$var supply0 1 =7 VGND $end +$var supply1 1 >7 VPB $end +$var supply0 1 ?7 VNB $end + +$scope module base $end +$var wire 1 .7 X $end +$var wire 1 .$ A0 $end +$var wire 1 -7 A1 $end +$var wire 1 F" S $end +$var wire 1 @7 mux_2to10_out_X $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mux_bottom_track_43 $end +$var wire 1 J in [0] $end +$var wire 1 f in [1] $end +$var wire 1 ]! sram [0] $end +$var wire 1 ^! sram [1] $end +$var wire 1 @$ sram_inv [0] $end +$var wire 1 A$ sram_inv [1] $end +$var wire 1 .! out [0] $end +$var wire 1 .$ p0 $end +$var wire 1 A7 mux_2level_tapbuf_basis_input2_mem1_0_out [0] $end +$var wire 1 B7 mux_2level_tapbuf_basis_input2_mem1_1_out [0] $end +$var wire 1 C7 SYNOPSYS_UNCONNECTED_1 $end +$var wire 1 D7 SYNOPSYS_UNCONNECTED_2 $end +$var wire 1 E7 SYNOPSYS_UNCONNECTED_3 $end +$var wire 1 F7 BUF_net_123 $end + +$scope module mux_l1_in_0_ $end +$var wire 1 J in [0] $end +$var wire 1 f in [1] $end +$var wire 1 ]! mem [0] $end +$var wire 1 C7 mem_inv [0] $end +$var wire 1 A7 out [0] $end + +$scope module sky130_fd_sc_hd__mux2_1_0 $end +$var wire 1 A7 X $end +$var wire 1 f A0 $end +$var wire 1 J A1 $end +$var wire 1 ]! S $end +$var supply1 1 G7 VPWR $end +$var supply0 1 H7 VGND $end +$var supply1 1 I7 VPB $end +$var supply0 1 J7 VNB $end + +$scope module base $end +$var wire 1 A7 X $end +$var wire 1 f A0 $end +$var wire 1 J A1 $end +$var wire 1 ]! S $end +$var wire 1 K7 mux_2to10_out_X $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mux_l2_in_0_ $end +$var wire 1 A7 in [0] $end +$var wire 1 D7 in [1] $end +$var wire 1 ^! mem [0] $end +$var wire 1 E7 mem_inv [0] $end +$var wire 1 B7 out [0] $end +$var wire 1 .$ p0 $end + +$scope module sky130_fd_sc_hd__mux2_1_0 $end +$var wire 1 B7 X $end +$var wire 1 .$ A0 $end +$var wire 1 A7 A1 $end +$var wire 1 ^! S $end +$var supply1 1 L7 VPWR $end +$var supply0 1 M7 VGND $end +$var supply1 1 N7 VPB $end +$var supply0 1 O7 VNB $end + +$scope module base $end +$var wire 1 B7 X $end +$var wire 1 .$ A0 $end +$var wire 1 A7 A1 $end +$var wire 1 ^! S $end +$var wire 1 P7 mux_2to10_out_X $end +$upscope $end +$upscope $end +$upscope $end + +$scope module BINV_R_122 $end +$var wire 1 .! Y $end +$var wire 1 F7 A $end +$var supply1 1 Q7 VPWR $end +$var supply0 1 R7 VGND $end +$var supply1 1 S7 VPB $end +$var supply0 1 T7 VNB $end + +$scope module base $end +$var wire 1 .! Y $end +$var wire 1 F7 A $end +$var wire 1 U7 not0_out_Y $end +$upscope $end +$upscope $end + +$scope module BINV_R_123 $end +$var wire 1 F7 Y $end +$var wire 1 B7 A $end +$var supply1 1 V7 VPWR $end +$var supply0 1 W7 VGND $end +$var supply1 1 X7 VPB $end +$var supply0 1 Y7 VNB $end + +$scope module base $end +$var wire 1 F7 Y $end +$var wire 1 B7 A $end +$var wire 1 Z7 not0_out_Y $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mux_bottom_track_47 $end +$var wire 1 L in [0] $end +$var wire 1 h in [1] $end +$var wire 1 _! sram [0] $end +$var wire 1 `! sram [1] $end +$var wire 1 B$ sram_inv [0] $end +$var wire 1 C$ sram_inv [1] $end +$var wire 1 0! out [0] $end +$var wire 1 .$ p0 $end +$var wire 1 [7 mux_2level_tapbuf_basis_input2_mem1_0_out [0] $end +$var wire 1 \7 mux_2level_tapbuf_basis_input2_mem1_1_out [0] $end +$var wire 1 ]7 SYNOPSYS_UNCONNECTED_1 $end +$var wire 1 ^7 SYNOPSYS_UNCONNECTED_2 $end +$var wire 1 _7 SYNOPSYS_UNCONNECTED_3 $end +$var wire 1 `7 BUF_net_125 $end + +$scope module mux_l1_in_0_ $end +$var wire 1 L in [0] $end +$var wire 1 h in [1] $end +$var wire 1 _! mem [0] $end +$var wire 1 ]7 mem_inv [0] $end +$var wire 1 [7 out [0] $end + +$scope module sky130_fd_sc_hd__mux2_1_0 $end +$var wire 1 [7 X $end +$var wire 1 h A0 $end +$var wire 1 L A1 $end +$var wire 1 _! S $end +$var supply1 1 a7 VPWR $end +$var supply0 1 b7 VGND $end +$var supply1 1 c7 VPB $end +$var supply0 1 d7 VNB $end + +$scope module base $end +$var wire 1 [7 X $end +$var wire 1 h A0 $end +$var wire 1 L A1 $end +$var wire 1 _! S $end +$var wire 1 e7 mux_2to10_out_X $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mux_l2_in_0_ $end +$var wire 1 [7 in [0] $end +$var wire 1 ^7 in [1] $end +$var wire 1 `! mem [0] $end +$var wire 1 _7 mem_inv [0] $end +$var wire 1 \7 out [0] $end +$var wire 1 .$ p0 $end + +$scope module sky130_fd_sc_hd__mux2_1_0 $end +$var wire 1 \7 X $end +$var wire 1 .$ A0 $end +$var wire 1 [7 A1 $end +$var wire 1 `! S $end +$var supply1 1 f7 VPWR $end +$var supply0 1 g7 VGND $end +$var supply1 1 h7 VPB $end +$var supply0 1 i7 VNB $end + +$scope module base $end +$var wire 1 \7 X $end +$var wire 1 .$ A0 $end +$var wire 1 [7 A1 $end +$var wire 1 `! S $end +$var wire 1 j7 mux_2to10_out_X $end +$upscope $end +$upscope $end +$upscope $end + +$scope module BINV_R_124 $end +$var wire 1 0! Y $end +$var wire 1 `7 A $end +$var supply1 1 k7 VPWR $end +$var supply0 1 l7 VGND $end +$var supply1 1 m7 VPB $end +$var supply0 1 n7 VNB $end + +$scope module base $end +$var wire 1 0! Y $end +$var wire 1 `7 A $end +$var wire 1 o7 not0_out_Y $end +$upscope $end +$upscope $end + +$scope module BINV_R_125 $end +$var wire 1 `7 Y $end +$var wire 1 \7 A $end +$var supply1 1 p7 VPWR $end +$var supply0 1 q7 VGND $end +$var supply1 1 r7 VPB $end +$var supply0 1 s7 VNB $end + +$scope module base $end +$var wire 1 `7 Y $end +$var wire 1 \7 A $end +$var wire 1 t7 not0_out_Y $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mux_bottom_track_49 $end +$var wire 1 M in [0] $end +$var wire 1 i in [1] $end +$var wire 1 a! sram [0] $end +$var wire 1 b! sram [1] $end +$var wire 1 D$ sram_inv [0] $end +$var wire 1 E$ sram_inv [1] $end +$var wire 1 1! out [0] $end +$var wire 1 k# p0 $end +$var wire 1 u7 mux_2level_tapbuf_basis_input2_mem1_0_out [0] $end +$var wire 1 v7 mux_2level_tapbuf_basis_input2_mem1_1_out [0] $end +$var wire 1 w7 SYNOPSYS_UNCONNECTED_1 $end +$var wire 1 x7 SYNOPSYS_UNCONNECTED_2 $end +$var wire 1 y7 SYNOPSYS_UNCONNECTED_3 $end +$var wire 1 z7 BUF_net_127 $end + +$scope module mux_l1_in_0_ $end +$var wire 1 M in [0] $end +$var wire 1 i in [1] $end +$var wire 1 a! mem [0] $end +$var wire 1 w7 mem_inv [0] $end +$var wire 1 u7 out [0] $end + +$scope module sky130_fd_sc_hd__mux2_1_0 $end +$var wire 1 u7 X $end +$var wire 1 i A0 $end +$var wire 1 M A1 $end +$var wire 1 a! S $end +$var supply1 1 {7 VPWR $end +$var supply0 1 |7 VGND $end +$var supply1 1 }7 VPB $end +$var supply0 1 ~7 VNB $end + +$scope module base $end +$var wire 1 u7 X $end +$var wire 1 i A0 $end +$var wire 1 M A1 $end +$var wire 1 a! S $end +$var wire 1 !8 mux_2to10_out_X $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mux_l2_in_0_ $end +$var wire 1 u7 in [0] $end +$var wire 1 x7 in [1] $end +$var wire 1 b! mem [0] $end +$var wire 1 y7 mem_inv [0] $end +$var wire 1 v7 out [0] $end +$var wire 1 k# p0 $end + +$scope module sky130_fd_sc_hd__mux2_1_0 $end +$var wire 1 v7 X $end +$var wire 1 k# A0 $end +$var wire 1 u7 A1 $end +$var wire 1 b! S $end +$var supply1 1 "8 VPWR $end +$var supply0 1 #8 VGND $end +$var supply1 1 $8 VPB $end +$var supply0 1 %8 VNB $end + +$scope module base $end +$var wire 1 v7 X $end +$var wire 1 k# A0 $end +$var wire 1 u7 A1 $end +$var wire 1 b! S $end +$var wire 1 &8 mux_2to10_out_X $end +$upscope $end +$upscope $end +$upscope $end + +$scope module BINV_R_126 $end +$var wire 1 1! Y $end +$var wire 1 z7 A $end +$var supply1 1 '8 VPWR $end +$var supply0 1 (8 VGND $end +$var supply1 1 )8 VPB $end +$var supply0 1 *8 VNB $end + +$scope module base $end +$var wire 1 1! Y $end +$var wire 1 z7 A $end +$var wire 1 +8 not0_out_Y $end +$upscope $end +$upscope $end + +$scope module BINV_R_127 $end +$var wire 1 z7 Y $end +$var wire 1 v7 A $end +$var supply1 1 ,8 VPWR $end +$var supply0 1 -8 VGND $end +$var supply1 1 .8 VPB $end +$var supply0 1 /8 VNB $end + +$scope module base $end +$var wire 1 z7 Y $end +$var wire 1 v7 A $end +$var wire 1 08 not0_out_Y $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mux_bottom_track_51 $end +$var wire 1 N in [0] $end +$var wire 1 j in [1] $end +$var wire 1 c! sram [0] $end +$var wire 1 d! sram [1] $end +$var wire 1 F$ sram_inv [0] $end +$var wire 1 G$ sram_inv [1] $end +$var wire 1 2! out [0] $end +$var wire 1 k# p0 $end +$var wire 1 18 mux_2level_tapbuf_basis_input2_mem1_0_out [0] $end +$var wire 1 28 mux_2level_tapbuf_basis_input2_mem1_1_out [0] $end +$var wire 1 38 SYNOPSYS_UNCONNECTED_1 $end +$var wire 1 48 SYNOPSYS_UNCONNECTED_2 $end +$var wire 1 58 SYNOPSYS_UNCONNECTED_3 $end +$var wire 1 68 BUF_net_129 $end + +$scope module mux_l1_in_0_ $end +$var wire 1 N in [0] $end +$var wire 1 j in [1] $end +$var wire 1 c! mem [0] $end +$var wire 1 38 mem_inv [0] $end +$var wire 1 18 out [0] $end + +$scope module sky130_fd_sc_hd__mux2_1_0 $end +$var wire 1 18 X $end +$var wire 1 j A0 $end +$var wire 1 N A1 $end +$var wire 1 c! S $end +$var supply1 1 78 VPWR $end +$var supply0 1 88 VGND $end +$var supply1 1 98 VPB $end +$var supply0 1 :8 VNB $end + +$scope module base $end +$var wire 1 18 X $end +$var wire 1 j A0 $end +$var wire 1 N A1 $end +$var wire 1 c! S $end +$var wire 1 ;8 mux_2to10_out_X $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mux_l2_in_0_ $end +$var wire 1 18 in [0] $end +$var wire 1 48 in [1] $end +$var wire 1 d! mem [0] $end +$var wire 1 58 mem_inv [0] $end +$var wire 1 28 out [0] $end +$var wire 1 k# p0 $end + +$scope module sky130_fd_sc_hd__mux2_1_0 $end +$var wire 1 28 X $end +$var wire 1 k# A0 $end +$var wire 1 18 A1 $end +$var wire 1 d! S $end +$var supply1 1 <8 VPWR $end +$var supply0 1 =8 VGND $end +$var supply1 1 >8 VPB $end +$var supply0 1 ?8 VNB $end + +$scope module base $end +$var wire 1 28 X $end +$var wire 1 k# A0 $end +$var wire 1 18 A1 $end +$var wire 1 d! S $end +$var wire 1 @8 mux_2to10_out_X $end +$upscope $end +$upscope $end +$upscope $end + +$scope module BINV_R_128 $end +$var wire 1 2! Y $end +$var wire 1 68 A $end +$var supply1 1 A8 VPWR $end +$var supply0 1 B8 VGND $end +$var supply1 1 C8 VPB $end +$var supply0 1 D8 VNB $end + +$scope module base $end +$var wire 1 2! Y $end +$var wire 1 68 A $end +$var wire 1 E8 not0_out_Y $end +$upscope $end +$upscope $end + +$scope module BINV_R_129 $end +$var wire 1 68 Y $end +$var wire 1 28 A $end +$var supply1 1 F8 VPWR $end +$var supply0 1 G8 VGND $end +$var supply1 1 H8 VPB $end +$var supply0 1 I8 VNB $end + +$scope module base $end +$var wire 1 68 Y $end +$var wire 1 28 A $end +$var wire 1 J8 not0_out_Y $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mux_bottom_track_53 $end +$var wire 1 O in [0] $end +$var wire 1 k in [1] $end +$var wire 1 e! sram [0] $end +$var wire 1 f! sram [1] $end +$var wire 1 H$ sram_inv [0] $end +$var wire 1 I$ sram_inv [1] $end +$var wire 1 3! out [0] $end +$var wire 1 b# p0 $end +$var wire 1 K8 mux_2level_tapbuf_basis_input2_mem1_0_out [0] $end +$var wire 1 L8 mux_2level_tapbuf_basis_input2_mem1_1_out [0] $end +$var wire 1 M8 SYNOPSYS_UNCONNECTED_1 $end +$var wire 1 N8 SYNOPSYS_UNCONNECTED_2 $end +$var wire 1 O8 SYNOPSYS_UNCONNECTED_3 $end +$var wire 1 P8 BUF_net_131 $end + +$scope module mux_l1_in_0_ $end +$var wire 1 O in [0] $end +$var wire 1 k in [1] $end +$var wire 1 e! mem [0] $end +$var wire 1 M8 mem_inv [0] $end +$var wire 1 K8 out [0] $end + +$scope module sky130_fd_sc_hd__mux2_1_0 $end +$var wire 1 K8 X $end +$var wire 1 k A0 $end +$var wire 1 O A1 $end +$var wire 1 e! S $end +$var supply1 1 Q8 VPWR $end +$var supply0 1 R8 VGND $end +$var supply1 1 S8 VPB $end +$var supply0 1 T8 VNB $end + +$scope module base $end +$var wire 1 K8 X $end +$var wire 1 k A0 $end +$var wire 1 O A1 $end +$var wire 1 e! S $end +$var wire 1 U8 mux_2to10_out_X $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mux_l2_in_0_ $end +$var wire 1 K8 in [0] $end +$var wire 1 N8 in [1] $end +$var wire 1 f! mem [0] $end +$var wire 1 O8 mem_inv [0] $end +$var wire 1 L8 out [0] $end +$var wire 1 b# p0 $end + +$scope module sky130_fd_sc_hd__mux2_1_0 $end +$var wire 1 L8 X $end +$var wire 1 b# A0 $end +$var wire 1 K8 A1 $end +$var wire 1 f! S $end +$var supply1 1 V8 VPWR $end +$var supply0 1 W8 VGND $end +$var supply1 1 X8 VPB $end +$var supply0 1 Y8 VNB $end + +$scope module base $end +$var wire 1 L8 X $end +$var wire 1 b# A0 $end +$var wire 1 K8 A1 $end +$var wire 1 f! S $end +$var wire 1 Z8 mux_2to10_out_X $end +$upscope $end +$upscope $end +$upscope $end + +$scope module BINV_R_130 $end +$var wire 1 3! Y $end +$var wire 1 P8 A $end +$var supply1 1 [8 VPWR $end +$var supply0 1 \8 VGND $end +$var supply1 1 ]8 VPB $end +$var supply0 1 ^8 VNB $end + +$scope module base $end +$var wire 1 3! Y $end +$var wire 1 P8 A $end +$var wire 1 _8 not0_out_Y $end +$upscope $end +$upscope $end + +$scope module BINV_R_131 $end +$var wire 1 P8 Y $end +$var wire 1 L8 A $end +$var supply1 1 `8 VPWR $end +$var supply0 1 a8 VGND $end +$var supply1 1 b8 VPB $end +$var supply0 1 c8 VNB $end + +$scope module base $end +$var wire 1 P8 Y $end +$var wire 1 L8 A $end +$var wire 1 d8 not0_out_Y $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mux_left_track_13 $end +$var wire 1 . in [0] $end +$var wire 1 n in [1] $end +$var wire 1 g! sram [0] $end +$var wire 1 h! sram [1] $end +$var wire 1 J$ sram_inv [0] $end +$var wire 1 K$ sram_inv [1] $end +$var wire 1 =! out [0] $end +$var wire 1 L$ p0 $end +$var wire 1 e8 mux_2level_tapbuf_basis_input2_mem1_0_out [0] $end +$var wire 1 f8 mux_2level_tapbuf_basis_input2_mem1_1_out [0] $end +$var wire 1 g8 SYNOPSYS_UNCONNECTED_1 $end +$var wire 1 h8 SYNOPSYS_UNCONNECTED_2 $end +$var wire 1 i8 SYNOPSYS_UNCONNECTED_3 $end +$var wire 1 j8 BUF_net_133 $end + +$scope module mux_l1_in_0_ $end +$var wire 1 . in [0] $end +$var wire 1 n in [1] $end +$var wire 1 g! mem [0] $end +$var wire 1 g8 mem_inv [0] $end +$var wire 1 e8 out [0] $end + +$scope module sky130_fd_sc_hd__mux2_1_0 $end +$var wire 1 e8 X $end +$var wire 1 n A0 $end +$var wire 1 . A1 $end +$var wire 1 g! S $end +$var supply1 1 k8 VPWR $end +$var supply0 1 l8 VGND $end +$var supply1 1 m8 VPB $end +$var supply0 1 n8 VNB $end + +$scope module base $end +$var wire 1 e8 X $end +$var wire 1 n A0 $end +$var wire 1 . A1 $end +$var wire 1 g! S $end +$var wire 1 o8 mux_2to10_out_X $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mux_l2_in_0_ $end +$var wire 1 e8 in [0] $end +$var wire 1 h8 in [1] $end +$var wire 1 h! mem [0] $end +$var wire 1 i8 mem_inv [0] $end +$var wire 1 f8 out [0] $end +$var wire 1 L$ p0 $end + +$scope module sky130_fd_sc_hd__mux2_1_0 $end +$var wire 1 f8 X $end +$var wire 1 L$ A0 $end +$var wire 1 e8 A1 $end +$var wire 1 h! S $end +$var supply1 1 p8 VPWR $end +$var supply0 1 q8 VGND $end +$var supply1 1 r8 VPB $end +$var supply0 1 s8 VNB $end + +$scope module base $end +$var wire 1 f8 X $end +$var wire 1 L$ A0 $end +$var wire 1 e8 A1 $end +$var wire 1 h! S $end +$var wire 1 t8 mux_2to10_out_X $end +$upscope $end +$upscope $end +$upscope $end + +$scope module BINV_R_132 $end +$var wire 1 =! Y $end +$var wire 1 j8 A $end +$var supply1 1 u8 VPWR $end +$var supply0 1 v8 VGND $end +$var supply1 1 w8 VPB $end +$var supply0 1 x8 VNB $end + +$scope module base $end +$var wire 1 =! Y $end +$var wire 1 j8 A $end +$var wire 1 y8 not0_out_Y $end +$upscope $end +$upscope $end + +$scope module BINV_R_133 $end +$var wire 1 j8 Y $end +$var wire 1 f8 A $end +$var supply1 1 z8 VPWR $end +$var supply0 1 {8 VGND $end +$var supply1 1 |8 VPB $end +$var supply0 1 }8 VNB $end + +$scope module base $end +$var wire 1 j8 Y $end +$var wire 1 f8 A $end +$var wire 1 ~8 not0_out_Y $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mux_left_track_15 $end +$var wire 1 / in [0] $end +$var wire 1 o in [1] $end +$var wire 1 i! sram [0] $end +$var wire 1 j! sram [1] $end +$var wire 1 M$ sram_inv [0] $end +$var wire 1 N$ sram_inv [1] $end +$var wire 1 >! out [0] $end +$var wire 1 L$ p0 $end +$var wire 1 !9 mux_2level_tapbuf_basis_input2_mem1_0_out [0] $end +$var wire 1 "9 mux_2level_tapbuf_basis_input2_mem1_1_out [0] $end +$var wire 1 #9 SYNOPSYS_UNCONNECTED_1 $end +$var wire 1 $9 SYNOPSYS_UNCONNECTED_2 $end +$var wire 1 %9 SYNOPSYS_UNCONNECTED_3 $end +$var wire 1 &9 BUF_net_135 $end + +$scope module mux_l1_in_0_ $end +$var wire 1 / in [0] $end +$var wire 1 o in [1] $end +$var wire 1 i! mem [0] $end +$var wire 1 #9 mem_inv [0] $end +$var wire 1 !9 out [0] $end + +$scope module sky130_fd_sc_hd__mux2_1_0 $end +$var wire 1 !9 X $end +$var wire 1 o A0 $end +$var wire 1 / A1 $end +$var wire 1 i! S $end +$var supply1 1 '9 VPWR $end +$var supply0 1 (9 VGND $end +$var supply1 1 )9 VPB $end +$var supply0 1 *9 VNB $end + +$scope module base $end +$var wire 1 !9 X $end +$var wire 1 o A0 $end +$var wire 1 / A1 $end +$var wire 1 i! S $end +$var wire 1 +9 mux_2to10_out_X $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mux_l2_in_0_ $end +$var wire 1 !9 in [0] $end +$var wire 1 $9 in [1] $end +$var wire 1 j! mem [0] $end +$var wire 1 %9 mem_inv [0] $end +$var wire 1 "9 out [0] $end +$var wire 1 L$ p0 $end + +$scope module sky130_fd_sc_hd__mux2_1_0 $end +$var wire 1 "9 X $end +$var wire 1 L$ A0 $end +$var wire 1 !9 A1 $end +$var wire 1 j! S $end +$var supply1 1 ,9 VPWR $end +$var supply0 1 -9 VGND $end +$var supply1 1 .9 VPB $end +$var supply0 1 /9 VNB $end + +$scope module base $end +$var wire 1 "9 X $end +$var wire 1 L$ A0 $end +$var wire 1 !9 A1 $end +$var wire 1 j! S $end +$var wire 1 09 mux_2to10_out_X $end +$upscope $end +$upscope $end +$upscope $end + +$scope module BINV_R_134 $end +$var wire 1 >! Y $end +$var wire 1 &9 A $end +$var supply1 1 19 VPWR $end +$var supply0 1 29 VGND $end +$var supply1 1 39 VPB $end +$var supply0 1 49 VNB $end + +$scope module base $end +$var wire 1 >! Y $end +$var wire 1 &9 A $end +$var wire 1 59 not0_out_Y $end +$upscope $end +$upscope $end + +$scope module BINV_R_135 $end +$var wire 1 &9 Y $end +$var wire 1 "9 A $end +$var supply1 1 69 VPWR $end +$var supply0 1 79 VGND $end +$var supply1 1 89 VPB $end +$var supply0 1 99 VNB $end + +$scope module base $end +$var wire 1 &9 Y $end +$var wire 1 "9 A $end +$var wire 1 :9 not0_out_Y $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mux_left_track_17 $end +$var wire 1 0 in [0] $end +$var wire 1 p in [1] $end +$var wire 1 k! sram [0] $end +$var wire 1 l! sram [1] $end +$var wire 1 O$ sram_inv [0] $end +$var wire 1 P$ sram_inv [1] $end +$var wire 1 ?! out [0] $end +$var wire 1 L$ p0 $end +$var wire 1 ;9 mux_2level_tapbuf_basis_input2_mem1_0_out [0] $end +$var wire 1 <9 mux_2level_tapbuf_basis_input2_mem1_1_out [0] $end +$var wire 1 =9 SYNOPSYS_UNCONNECTED_1 $end +$var wire 1 >9 SYNOPSYS_UNCONNECTED_2 $end +$var wire 1 ?9 SYNOPSYS_UNCONNECTED_3 $end +$var wire 1 @9 BUF_net_137 $end + +$scope module mux_l1_in_0_ $end +$var wire 1 0 in [0] $end +$var wire 1 p in [1] $end +$var wire 1 k! mem [0] $end +$var wire 1 =9 mem_inv [0] $end +$var wire 1 ;9 out [0] $end + +$scope module sky130_fd_sc_hd__mux2_1_0 $end +$var wire 1 ;9 X $end +$var wire 1 p A0 $end +$var wire 1 0 A1 $end +$var wire 1 k! S $end +$var supply1 1 A9 VPWR $end +$var supply0 1 B9 VGND $end +$var supply1 1 C9 VPB $end +$var supply0 1 D9 VNB $end + +$scope module base $end +$var wire 1 ;9 X $end +$var wire 1 p A0 $end +$var wire 1 0 A1 $end +$var wire 1 k! S $end +$var wire 1 E9 mux_2to10_out_X $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mux_l2_in_0_ $end +$var wire 1 ;9 in [0] $end +$var wire 1 >9 in [1] $end +$var wire 1 l! mem [0] $end +$var wire 1 ?9 mem_inv [0] $end +$var wire 1 <9 out [0] $end +$var wire 1 L$ p0 $end + +$scope module sky130_fd_sc_hd__mux2_1_0 $end +$var wire 1 <9 X $end +$var wire 1 L$ A0 $end +$var wire 1 ;9 A1 $end +$var wire 1 l! S $end +$var supply1 1 F9 VPWR $end +$var supply0 1 G9 VGND $end +$var supply1 1 H9 VPB $end +$var supply0 1 I9 VNB $end + +$scope module base $end +$var wire 1 <9 X $end +$var wire 1 L$ A0 $end +$var wire 1 ;9 A1 $end +$var wire 1 l! S $end +$var wire 1 J9 mux_2to10_out_X $end +$upscope $end +$upscope $end +$upscope $end + +$scope module BINV_R_136 $end +$var wire 1 ?! Y $end +$var wire 1 @9 A $end +$var supply1 1 K9 VPWR $end +$var supply0 1 L9 VGND $end +$var supply1 1 M9 VPB $end +$var supply0 1 N9 VNB $end + +$scope module base $end +$var wire 1 ?! Y $end +$var wire 1 @9 A $end +$var wire 1 O9 not0_out_Y $end +$upscope $end +$upscope $end + +$scope module BINV_R_137 $end +$var wire 1 @9 Y $end +$var wire 1 <9 A $end +$var supply1 1 P9 VPWR $end +$var supply0 1 Q9 VGND $end +$var supply1 1 R9 VPB $end +$var supply0 1 S9 VNB $end + +$scope module base $end +$var wire 1 @9 Y $end +$var wire 1 <9 A $end +$var wire 1 T9 not0_out_Y $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mux_left_track_19 $end +$var wire 1 1 in [0] $end +$var wire 1 q in [1] $end +$var wire 1 m! sram [0] $end +$var wire 1 n! sram [1] $end +$var wire 1 Q$ sram_inv [0] $end +$var wire 1 R$ sram_inv [1] $end +$var wire 1 @! out [0] $end +$var wire 1 L$ p0 $end +$var wire 1 U9 mux_2level_tapbuf_basis_input2_mem1_0_out [0] $end +$var wire 1 V9 mux_2level_tapbuf_basis_input2_mem1_1_out [0] $end +$var wire 1 W9 SYNOPSYS_UNCONNECTED_1 $end +$var wire 1 X9 SYNOPSYS_UNCONNECTED_2 $end +$var wire 1 Y9 SYNOPSYS_UNCONNECTED_3 $end +$var wire 1 Z9 BUF_net_139 $end + +$scope module mux_l1_in_0_ $end +$var wire 1 1 in [0] $end +$var wire 1 q in [1] $end +$var wire 1 m! mem [0] $end +$var wire 1 W9 mem_inv [0] $end +$var wire 1 U9 out [0] $end + +$scope module sky130_fd_sc_hd__mux2_1_0 $end +$var wire 1 U9 X $end +$var wire 1 q A0 $end +$var wire 1 1 A1 $end +$var wire 1 m! S $end +$var supply1 1 [9 VPWR $end +$var supply0 1 \9 VGND $end +$var supply1 1 ]9 VPB $end +$var supply0 1 ^9 VNB $end + +$scope module base $end +$var wire 1 U9 X $end +$var wire 1 q A0 $end +$var wire 1 1 A1 $end +$var wire 1 m! S $end +$var wire 1 _9 mux_2to10_out_X $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mux_l2_in_0_ $end +$var wire 1 U9 in [0] $end +$var wire 1 X9 in [1] $end +$var wire 1 n! mem [0] $end +$var wire 1 Y9 mem_inv [0] $end +$var wire 1 V9 out [0] $end +$var wire 1 L$ p0 $end + +$scope module sky130_fd_sc_hd__mux2_1_0 $end +$var wire 1 V9 X $end +$var wire 1 L$ A0 $end +$var wire 1 U9 A1 $end +$var wire 1 n! S $end +$var supply1 1 `9 VPWR $end +$var supply0 1 a9 VGND $end +$var supply1 1 b9 VPB $end +$var supply0 1 c9 VNB $end + +$scope module base $end +$var wire 1 V9 X $end +$var wire 1 L$ A0 $end +$var wire 1 U9 A1 $end +$var wire 1 n! S $end +$var wire 1 d9 mux_2to10_out_X $end +$upscope $end +$upscope $end +$upscope $end + +$scope module BINV_R_138 $end +$var wire 1 @! Y $end +$var wire 1 Z9 A $end +$var supply1 1 e9 VPWR $end +$var supply0 1 f9 VGND $end +$var supply1 1 g9 VPB $end +$var supply0 1 h9 VNB $end + +$scope module base $end +$var wire 1 @! Y $end +$var wire 1 Z9 A $end +$var wire 1 i9 not0_out_Y $end +$upscope $end +$upscope $end + +$scope module BINV_R_139 $end +$var wire 1 Z9 Y $end +$var wire 1 V9 A $end +$var supply1 1 j9 VPWR $end +$var supply0 1 k9 VGND $end +$var supply1 1 l9 VPB $end +$var supply0 1 m9 VNB $end + +$scope module base $end +$var wire 1 Z9 Y $end +$var wire 1 V9 A $end +$var wire 1 n9 not0_out_Y $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mux_left_track_21 $end +$var wire 1 2 in [0] $end +$var wire 1 r in [1] $end +$var wire 1 o! sram [0] $end +$var wire 1 p! sram [1] $end +$var wire 1 S$ sram_inv [0] $end +$var wire 1 T$ sram_inv [1] $end +$var wire 1 A! out [0] $end +$var wire 1 .$ p0 $end +$var wire 1 o9 mux_2level_tapbuf_basis_input2_mem1_0_out [0] $end +$var wire 1 p9 mux_2level_tapbuf_basis_input2_mem1_1_out [0] $end +$var wire 1 q9 SYNOPSYS_UNCONNECTED_1 $end +$var wire 1 r9 SYNOPSYS_UNCONNECTED_2 $end +$var wire 1 s9 SYNOPSYS_UNCONNECTED_3 $end +$var wire 1 t9 BUF_net_141 $end + +$scope module mux_l1_in_0_ $end +$var wire 1 2 in [0] $end +$var wire 1 r in [1] $end +$var wire 1 o! mem [0] $end +$var wire 1 q9 mem_inv [0] $end +$var wire 1 o9 out [0] $end + +$scope module sky130_fd_sc_hd__mux2_1_0 $end +$var wire 1 o9 X $end +$var wire 1 r A0 $end +$var wire 1 2 A1 $end +$var wire 1 o! S $end +$var supply1 1 u9 VPWR $end +$var supply0 1 v9 VGND $end +$var supply1 1 w9 VPB $end +$var supply0 1 x9 VNB $end + +$scope module base $end +$var wire 1 o9 X $end +$var wire 1 r A0 $end +$var wire 1 2 A1 $end +$var wire 1 o! S $end +$var wire 1 y9 mux_2to10_out_X $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mux_l2_in_0_ $end +$var wire 1 o9 in [0] $end +$var wire 1 r9 in [1] $end +$var wire 1 p! mem [0] $end +$var wire 1 s9 mem_inv [0] $end +$var wire 1 p9 out [0] $end +$var wire 1 .$ p0 $end + +$scope module sky130_fd_sc_hd__mux2_1_0 $end +$var wire 1 p9 X $end +$var wire 1 .$ A0 $end +$var wire 1 o9 A1 $end +$var wire 1 p! S $end +$var supply1 1 z9 VPWR $end +$var supply0 1 {9 VGND $end +$var supply1 1 |9 VPB $end +$var supply0 1 }9 VNB $end + +$scope module base $end +$var wire 1 p9 X $end +$var wire 1 .$ A0 $end +$var wire 1 o9 A1 $end +$var wire 1 p! S $end +$var wire 1 ~9 mux_2to10_out_X $end +$upscope $end +$upscope $end +$upscope $end + +$scope module BINV_R_140 $end +$var wire 1 A! Y $end +$var wire 1 t9 A $end +$var supply1 1 !: VPWR $end +$var supply0 1 ": VGND $end +$var supply1 1 #: VPB $end +$var supply0 1 $: VNB $end + +$scope module base $end +$var wire 1 A! Y $end +$var wire 1 t9 A $end +$var wire 1 %: not0_out_Y $end +$upscope $end +$upscope $end + +$scope module BINV_R_141 $end +$var wire 1 t9 Y $end +$var wire 1 p9 A $end +$var supply1 1 &: VPWR $end +$var supply0 1 ': VGND $end +$var supply1 1 (: VPB $end +$var supply0 1 ): VNB $end + +$scope module base $end +$var wire 1 t9 Y $end +$var wire 1 p9 A $end +$var wire 1 *: not0_out_Y $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mux_left_track_23 $end +$var wire 1 3 in [0] $end +$var wire 1 s in [1] $end +$var wire 1 s! sram [0] $end +$var wire 1 t! sram [1] $end +$var wire 1 U$ sram_inv [0] $end +$var wire 1 V$ sram_inv [1] $end +$var wire 1 B! out [0] $end +$var wire 1 .$ p0 $end +$var wire 1 +: mux_2level_tapbuf_basis_input2_mem1_0_out [0] $end +$var wire 1 ,: mux_2level_tapbuf_basis_input2_mem1_1_out [0] $end +$var wire 1 -: SYNOPSYS_UNCONNECTED_1 $end +$var wire 1 .: SYNOPSYS_UNCONNECTED_2 $end +$var wire 1 /: SYNOPSYS_UNCONNECTED_3 $end + +$scope module sky130_fd_sc_hd__buf_4_0_ $end +$var wire 1 B! X $end +$var wire 1 ,: A $end +$var supply1 1 0: VPWR $end +$var supply0 1 1: VGND $end +$var supply1 1 2: VPB $end +$var supply0 1 3: VNB $end + +$scope module base $end +$var wire 1 B! X $end +$var wire 1 ,: A $end +$var wire 1 4: buf0_out_X $end +$upscope $end +$upscope $end + +$scope module mux_l1_in_0_ $end +$var wire 1 3 in [0] $end +$var wire 1 s in [1] $end +$var wire 1 s! mem [0] $end +$var wire 1 -: mem_inv [0] $end +$var wire 1 +: out [0] $end + +$scope module sky130_fd_sc_hd__mux2_1_0 $end +$var wire 1 +: X $end +$var wire 1 s A0 $end +$var wire 1 3 A1 $end +$var wire 1 s! S $end +$var supply1 1 5: VPWR $end +$var supply0 1 6: VGND $end +$var supply1 1 7: VPB $end +$var supply0 1 8: VNB $end + +$scope module base $end +$var wire 1 +: X $end +$var wire 1 s A0 $end +$var wire 1 3 A1 $end +$var wire 1 s! S $end +$var wire 1 9: mux_2to10_out_X $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mux_l2_in_0_ $end +$var wire 1 +: in [0] $end +$var wire 1 .: in [1] $end +$var wire 1 t! mem [0] $end +$var wire 1 /: mem_inv [0] $end +$var wire 1 ,: out [0] $end +$var wire 1 .$ p0 $end + +$scope module sky130_fd_sc_hd__mux2_1_0 $end +$var wire 1 ,: X $end +$var wire 1 .$ A0 $end +$var wire 1 +: A1 $end +$var wire 1 t! S $end +$var supply1 1 :: VPWR $end +$var supply0 1 ;: VGND $end +$var supply1 1 <: VPB $end +$var supply0 1 =: VNB $end + +$scope module base $end +$var wire 1 ,: X $end +$var wire 1 .$ A0 $end +$var wire 1 +: A1 $end +$var wire 1 t! S $end +$var wire 1 >: mux_2to10_out_X $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mux_left_track_25 $end +$var wire 1 4 in [0] $end +$var wire 1 t in [1] $end +$var wire 1 u! sram [0] $end +$var wire 1 v! sram [1] $end +$var wire 1 W$ sram_inv [0] $end +$var wire 1 X$ sram_inv [1] $end +$var wire 1 C! out [0] $end +$var wire 1 .$ p0 $end +$var wire 1 ?: mux_2level_tapbuf_basis_input2_mem1_0_out [0] $end +$var wire 1 @: mux_2level_tapbuf_basis_input2_mem1_1_out [0] $end +$var wire 1 A: SYNOPSYS_UNCONNECTED_1 $end +$var wire 1 B: SYNOPSYS_UNCONNECTED_2 $end +$var wire 1 C: SYNOPSYS_UNCONNECTED_3 $end +$var wire 1 D: BUF_net_143 $end + +$scope module mux_l1_in_0_ $end +$var wire 1 4 in [0] $end +$var wire 1 t in [1] $end +$var wire 1 u! mem [0] $end +$var wire 1 A: mem_inv [0] $end +$var wire 1 ?: out [0] $end + +$scope module sky130_fd_sc_hd__mux2_1_0 $end +$var wire 1 ?: X $end +$var wire 1 t A0 $end +$var wire 1 4 A1 $end +$var wire 1 u! S $end +$var supply1 1 E: VPWR $end +$var supply0 1 F: VGND $end +$var supply1 1 G: VPB $end +$var supply0 1 H: VNB $end + +$scope module base $end +$var wire 1 ?: X $end +$var wire 1 t A0 $end +$var wire 1 4 A1 $end +$var wire 1 u! S $end +$var wire 1 I: mux_2to10_out_X $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mux_l2_in_0_ $end +$var wire 1 ?: in [0] $end +$var wire 1 B: in [1] $end +$var wire 1 v! mem [0] $end +$var wire 1 C: mem_inv [0] $end +$var wire 1 @: out [0] $end +$var wire 1 .$ p0 $end + +$scope module sky130_fd_sc_hd__mux2_1_0 $end +$var wire 1 @: X $end +$var wire 1 .$ A0 $end +$var wire 1 ?: A1 $end +$var wire 1 v! S $end +$var supply1 1 J: VPWR $end +$var supply0 1 K: VGND $end +$var supply1 1 L: VPB $end +$var supply0 1 M: VNB $end + +$scope module base $end +$var wire 1 @: X $end +$var wire 1 .$ A0 $end +$var wire 1 ?: A1 $end +$var wire 1 v! S $end +$var wire 1 N: mux_2to10_out_X $end +$upscope $end +$upscope $end +$upscope $end + +$scope module BINV_R_142 $end +$var wire 1 C! Y $end +$var wire 1 D: A $end +$var supply1 1 O: VPWR $end +$var supply0 1 P: VGND $end +$var supply1 1 Q: VPB $end +$var supply0 1 R: VNB $end + +$scope module base $end +$var wire 1 C! Y $end +$var wire 1 D: A $end +$var wire 1 S: not0_out_Y $end +$upscope $end +$upscope $end + +$scope module BINV_R_143 $end +$var wire 1 D: Y $end +$var wire 1 @: A $end +$var supply1 1 T: VPWR $end +$var supply0 1 U: VGND $end +$var supply1 1 V: VPB $end +$var supply0 1 W: VNB $end + +$scope module base $end +$var wire 1 D: Y $end +$var wire 1 @: A $end +$var wire 1 X: not0_out_Y $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mux_left_track_27 $end +$var wire 1 5 in [0] $end +$var wire 1 u in [1] $end +$var wire 1 w! sram [0] $end +$var wire 1 x! sram [1] $end +$var wire 1 Y$ sram_inv [0] $end +$var wire 1 Z$ sram_inv [1] $end +$var wire 1 D! out [0] $end +$var wire 1 .$ p0 $end +$var wire 1 Y: mux_2level_tapbuf_basis_input2_mem1_0_out [0] $end +$var wire 1 Z: mux_2level_tapbuf_basis_input2_mem1_1_out [0] $end +$var wire 1 [: SYNOPSYS_UNCONNECTED_1 $end +$var wire 1 \: SYNOPSYS_UNCONNECTED_2 $end +$var wire 1 ]: SYNOPSYS_UNCONNECTED_3 $end + +$scope module sky130_fd_sc_hd__buf_4_0_ $end +$var wire 1 D! X $end +$var wire 1 Z: A $end +$var supply1 1 ^: VPWR $end +$var supply0 1 _: VGND $end +$var supply1 1 `: VPB $end +$var supply0 1 a: VNB $end + +$scope module base $end +$var wire 1 D! X $end +$var wire 1 Z: A $end +$var wire 1 b: buf0_out_X $end +$upscope $end +$upscope $end + +$scope module mux_l1_in_0_ $end +$var wire 1 5 in [0] $end +$var wire 1 u in [1] $end +$var wire 1 w! mem [0] $end +$var wire 1 [: mem_inv [0] $end +$var wire 1 Y: out [0] $end + +$scope module sky130_fd_sc_hd__mux2_1_0 $end +$var wire 1 Y: X $end +$var wire 1 u A0 $end +$var wire 1 5 A1 $end +$var wire 1 w! S $end +$var supply1 1 c: VPWR $end +$var supply0 1 d: VGND $end +$var supply1 1 e: VPB $end +$var supply0 1 f: VNB $end + +$scope module base $end +$var wire 1 Y: X $end +$var wire 1 u A0 $end +$var wire 1 5 A1 $end +$var wire 1 w! S $end +$var wire 1 g: mux_2to10_out_X $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mux_l2_in_0_ $end +$var wire 1 Y: in [0] $end +$var wire 1 \: in [1] $end +$var wire 1 x! mem [0] $end +$var wire 1 ]: mem_inv [0] $end +$var wire 1 Z: out [0] $end +$var wire 1 .$ p0 $end + +$scope module sky130_fd_sc_hd__mux2_1_0 $end +$var wire 1 Z: X $end +$var wire 1 .$ A0 $end +$var wire 1 Y: A1 $end +$var wire 1 x! S $end +$var supply1 1 h: VPWR $end +$var supply0 1 i: VGND $end +$var supply1 1 j: VPB $end +$var supply0 1 k: VNB $end + +$scope module base $end +$var wire 1 Z: X $end +$var wire 1 .$ A0 $end +$var wire 1 Y: A1 $end +$var wire 1 x! S $end +$var wire 1 l: mux_2to10_out_X $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mux_left_track_31 $end +$var wire 1 7 in [0] $end +$var wire 1 o in [1] $end +$var wire 1 y! sram [0] $end +$var wire 1 z! sram [1] $end +$var wire 1 [$ sram_inv [0] $end +$var wire 1 \$ sram_inv [1] $end +$var wire 1 F! out [0] $end +$var wire 1 L$ p0 $end +$var wire 1 m: mux_2level_tapbuf_basis_input2_mem1_0_out [0] $end +$var wire 1 n: mux_2level_tapbuf_basis_input2_mem1_1_out [0] $end +$var wire 1 o: SYNOPSYS_UNCONNECTED_1 $end +$var wire 1 p: SYNOPSYS_UNCONNECTED_2 $end +$var wire 1 q: SYNOPSYS_UNCONNECTED_3 $end +$var wire 1 r: BUF_net_145 $end + +$scope module mux_l1_in_0_ $end +$var wire 1 7 in [0] $end +$var wire 1 o in [1] $end +$var wire 1 y! mem [0] $end +$var wire 1 o: mem_inv [0] $end +$var wire 1 m: out [0] $end + +$scope module sky130_fd_sc_hd__mux2_1_0 $end +$var wire 1 m: X $end +$var wire 1 o A0 $end +$var wire 1 7 A1 $end +$var wire 1 y! S $end +$var supply1 1 s: VPWR $end +$var supply0 1 t: VGND $end +$var supply1 1 u: VPB $end +$var supply0 1 v: VNB $end + +$scope module base $end +$var wire 1 m: X $end +$var wire 1 o A0 $end +$var wire 1 7 A1 $end +$var wire 1 y! S $end +$var wire 1 w: mux_2to10_out_X $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mux_l2_in_0_ $end +$var wire 1 m: in [0] $end +$var wire 1 p: in [1] $end +$var wire 1 z! mem [0] $end +$var wire 1 q: mem_inv [0] $end +$var wire 1 n: out [0] $end +$var wire 1 L$ p0 $end + +$scope module sky130_fd_sc_hd__mux2_1_0 $end +$var wire 1 n: X $end +$var wire 1 L$ A0 $end +$var wire 1 m: A1 $end +$var wire 1 z! S $end +$var supply1 1 x: VPWR $end +$var supply0 1 y: VGND $end +$var supply1 1 z: VPB $end +$var supply0 1 {: VNB $end + +$scope module base $end +$var wire 1 n: X $end +$var wire 1 L$ A0 $end +$var wire 1 m: A1 $end +$var wire 1 z! S $end +$var wire 1 |: mux_2to10_out_X $end +$upscope $end +$upscope $end +$upscope $end + +$scope module BINV_R_144 $end +$var wire 1 F! Y $end +$var wire 1 r: A $end +$var supply1 1 }: VPWR $end +$var supply0 1 ~: VGND $end +$var supply1 1 !; VPB $end +$var supply0 1 "; VNB $end + +$scope module base $end +$var wire 1 F! Y $end +$var wire 1 r: A $end +$var wire 1 #; not0_out_Y $end +$upscope $end +$upscope $end + +$scope module BINV_R_145 $end +$var wire 1 r: Y $end +$var wire 1 n: A $end +$var supply1 1 $; VPWR $end +$var supply0 1 %; VGND $end +$var supply1 1 &; VPB $end +$var supply0 1 '; VNB $end + +$scope module base $end +$var wire 1 r: Y $end +$var wire 1 n: A $end +$var wire 1 (; not0_out_Y $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mux_left_track_33 $end +$var wire 1 8 in [0] $end +$var wire 1 p in [1] $end +$var wire 1 {! sram [0] $end +$var wire 1 |! sram [1] $end +$var wire 1 ]$ sram_inv [0] $end +$var wire 1 ^$ sram_inv [1] $end +$var wire 1 G! out [0] $end +$var wire 1 L$ p0 $end +$var wire 1 ); mux_2level_tapbuf_basis_input2_mem1_0_out [0] $end +$var wire 1 *; mux_2level_tapbuf_basis_input2_mem1_1_out [0] $end +$var wire 1 +; SYNOPSYS_UNCONNECTED_1 $end +$var wire 1 ,; SYNOPSYS_UNCONNECTED_2 $end +$var wire 1 -; SYNOPSYS_UNCONNECTED_3 $end +$var wire 1 .; BUF_net_147 $end + +$scope module mux_l1_in_0_ $end +$var wire 1 8 in [0] $end +$var wire 1 p in [1] $end +$var wire 1 {! mem [0] $end +$var wire 1 +; mem_inv [0] $end +$var wire 1 ); out [0] $end + +$scope module sky130_fd_sc_hd__mux2_1_0 $end +$var wire 1 ); X $end +$var wire 1 p A0 $end +$var wire 1 8 A1 $end +$var wire 1 {! S $end +$var supply1 1 /; VPWR $end +$var supply0 1 0; VGND $end +$var supply1 1 1; VPB $end +$var supply0 1 2; VNB $end + +$scope module base $end +$var wire 1 ); X $end +$var wire 1 p A0 $end +$var wire 1 8 A1 $end +$var wire 1 {! S $end +$var wire 1 3; mux_2to10_out_X $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mux_l2_in_0_ $end +$var wire 1 ); in [0] $end +$var wire 1 ,; in [1] $end +$var wire 1 |! mem [0] $end +$var wire 1 -; mem_inv [0] $end +$var wire 1 *; out [0] $end +$var wire 1 L$ p0 $end + +$scope module sky130_fd_sc_hd__mux2_1_0 $end +$var wire 1 *; X $end +$var wire 1 L$ A0 $end +$var wire 1 ); A1 $end +$var wire 1 |! S $end +$var supply1 1 4; VPWR $end +$var supply0 1 5; VGND $end +$var supply1 1 6; VPB $end +$var supply0 1 7; VNB $end + +$scope module base $end +$var wire 1 *; X $end +$var wire 1 L$ A0 $end +$var wire 1 ); A1 $end +$var wire 1 |! S $end +$var wire 1 8; mux_2to10_out_X $end +$upscope $end +$upscope $end +$upscope $end + +$scope module BINV_R_146 $end +$var wire 1 G! Y $end +$var wire 1 .; A $end +$var supply1 1 9; VPWR $end +$var supply0 1 :; VGND $end +$var supply1 1 ;; VPB $end +$var supply0 1 <; VNB $end + +$scope module base $end +$var wire 1 G! Y $end +$var wire 1 .; A $end +$var wire 1 =; not0_out_Y $end +$upscope $end +$upscope $end + +$scope module BINV_R_147 $end +$var wire 1 .; Y $end +$var wire 1 *; A $end +$var supply1 1 >; VPWR $end +$var supply0 1 ?; VGND $end +$var supply1 1 @; VPB $end +$var supply0 1 A; VNB $end + +$scope module base $end +$var wire 1 .; Y $end +$var wire 1 *; A $end +$var wire 1 B; not0_out_Y $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mux_left_track_35 $end +$var wire 1 9 in [0] $end +$var wire 1 q in [1] $end +$var wire 1 }! sram [0] $end +$var wire 1 ~! sram [1] $end +$var wire 1 _$ sram_inv [0] $end +$var wire 1 `$ sram_inv [1] $end +$var wire 1 H! out [0] $end +$var wire 1 L$ p0 $end +$var wire 1 C; mux_2level_tapbuf_basis_input2_mem1_0_out [0] $end +$var wire 1 D; mux_2level_tapbuf_basis_input2_mem1_1_out [0] $end +$var wire 1 E; SYNOPSYS_UNCONNECTED_1 $end +$var wire 1 F; SYNOPSYS_UNCONNECTED_2 $end +$var wire 1 G; SYNOPSYS_UNCONNECTED_3 $end +$var wire 1 H; BUF_net_149 $end + +$scope module mux_l1_in_0_ $end +$var wire 1 9 in [0] $end +$var wire 1 q in [1] $end +$var wire 1 }! mem [0] $end +$var wire 1 E; mem_inv [0] $end +$var wire 1 C; out [0] $end + +$scope module sky130_fd_sc_hd__mux2_1_0 $end +$var wire 1 C; X $end +$var wire 1 q A0 $end +$var wire 1 9 A1 $end +$var wire 1 }! S $end +$var supply1 1 I; VPWR $end +$var supply0 1 J; VGND $end +$var supply1 1 K; VPB $end +$var supply0 1 L; VNB $end + +$scope module base $end +$var wire 1 C; X $end +$var wire 1 q A0 $end +$var wire 1 9 A1 $end +$var wire 1 }! S $end +$var wire 1 M; mux_2to10_out_X $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mux_l2_in_0_ $end +$var wire 1 C; in [0] $end +$var wire 1 F; in [1] $end +$var wire 1 ~! mem [0] $end +$var wire 1 G; mem_inv [0] $end +$var wire 1 D; out [0] $end +$var wire 1 L$ p0 $end + +$scope module sky130_fd_sc_hd__mux2_1_0 $end +$var wire 1 D; X $end +$var wire 1 L$ A0 $end +$var wire 1 C; A1 $end +$var wire 1 ~! S $end +$var supply1 1 N; VPWR $end +$var supply0 1 O; VGND $end +$var supply1 1 P; VPB $end +$var supply0 1 Q; VNB $end + +$scope module base $end +$var wire 1 D; X $end +$var wire 1 L$ A0 $end +$var wire 1 C; A1 $end +$var wire 1 ~! S $end +$var wire 1 R; mux_2to10_out_X $end +$upscope $end +$upscope $end +$upscope $end + +$scope module BINV_R_148 $end +$var wire 1 H! Y $end +$var wire 1 H; A $end +$var supply1 1 S; VPWR $end +$var supply0 1 T; VGND $end +$var supply1 1 U; VPB $end +$var supply0 1 V; VNB $end + +$scope module base $end +$var wire 1 H! Y $end +$var wire 1 H; A $end +$var wire 1 W; not0_out_Y $end +$upscope $end +$upscope $end + +$scope module BINV_R_149 $end +$var wire 1 H; Y $end +$var wire 1 D; A $end +$var supply1 1 X; VPWR $end +$var supply0 1 Y; VGND $end +$var supply1 1 Z; VPB $end +$var supply0 1 [; VNB $end + +$scope module base $end +$var wire 1 H; Y $end +$var wire 1 D; A $end +$var wire 1 \; not0_out_Y $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mux_left_track_37 $end +$var wire 1 : in [0] $end +$var wire 1 r in [1] $end +$var wire 1 !" sram [0] $end +$var wire 1 "" sram [1] $end +$var wire 1 a$ sram_inv [0] $end +$var wire 1 b$ sram_inv [1] $end +$var wire 1 I! out [0] $end +$var wire 1 L$ p0 $end +$var wire 1 ]; mux_2level_tapbuf_basis_input2_mem1_0_out [0] $end +$var wire 1 ^; mux_2level_tapbuf_basis_input2_mem1_1_out [0] $end +$var wire 1 _; SYNOPSYS_UNCONNECTED_1 $end +$var wire 1 `; SYNOPSYS_UNCONNECTED_2 $end +$var wire 1 a; SYNOPSYS_UNCONNECTED_3 $end +$var wire 1 b; BUF_net_151 $end + +$scope module mux_l1_in_0_ $end +$var wire 1 : in [0] $end +$var wire 1 r in [1] $end +$var wire 1 !" mem [0] $end +$var wire 1 _; mem_inv [0] $end +$var wire 1 ]; out [0] $end + +$scope module sky130_fd_sc_hd__mux2_1_0 $end +$var wire 1 ]; X $end +$var wire 1 r A0 $end +$var wire 1 : A1 $end +$var wire 1 !" S $end +$var supply1 1 c; VPWR $end +$var supply0 1 d; VGND $end +$var supply1 1 e; VPB $end +$var supply0 1 f; VNB $end + +$scope module base $end +$var wire 1 ]; X $end +$var wire 1 r A0 $end +$var wire 1 : A1 $end +$var wire 1 !" S $end +$var wire 1 g; mux_2to10_out_X $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mux_l2_in_0_ $end +$var wire 1 ]; in [0] $end +$var wire 1 `; in [1] $end +$var wire 1 "" mem [0] $end +$var wire 1 a; mem_inv [0] $end +$var wire 1 ^; out [0] $end +$var wire 1 L$ p0 $end + +$scope module sky130_fd_sc_hd__mux2_1_0 $end +$var wire 1 ^; X $end +$var wire 1 L$ A0 $end +$var wire 1 ]; A1 $end +$var wire 1 "" S $end +$var supply1 1 h; VPWR $end +$var supply0 1 i; VGND $end +$var supply1 1 j; VPB $end +$var supply0 1 k; VNB $end + +$scope module base $end +$var wire 1 ^; X $end +$var wire 1 L$ A0 $end +$var wire 1 ]; A1 $end +$var wire 1 "" S $end +$var wire 1 l; mux_2to10_out_X $end +$upscope $end +$upscope $end +$upscope $end + +$scope module BINV_R_150 $end +$var wire 1 I! Y $end +$var wire 1 b; A $end +$var supply1 1 m; VPWR $end +$var supply0 1 n; VGND $end +$var supply1 1 o; VPB $end +$var supply0 1 p; VNB $end + +$scope module base $end +$var wire 1 I! Y $end +$var wire 1 b; A $end +$var wire 1 q; not0_out_Y $end +$upscope $end +$upscope $end + +$scope module BINV_R_151 $end +$var wire 1 b; Y $end +$var wire 1 ^; A $end +$var supply1 1 r; VPWR $end +$var supply0 1 s; VGND $end +$var supply1 1 t; VPB $end +$var supply0 1 u; VNB $end + +$scope module base $end +$var wire 1 b; Y $end +$var wire 1 ^; A $end +$var wire 1 v; not0_out_Y $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mux_left_track_39 $end +$var wire 1 ; in [0] $end +$var wire 1 s in [1] $end +$var wire 1 #" sram [0] $end +$var wire 1 $" sram [1] $end +$var wire 1 c$ sram_inv [0] $end +$var wire 1 d$ sram_inv [1] $end +$var wire 1 J! out [0] $end +$var wire 1 L$ p0 $end +$var wire 1 w; mux_2level_tapbuf_basis_input2_mem1_0_out [0] $end +$var wire 1 x; mux_2level_tapbuf_basis_input2_mem1_1_out [0] $end +$var wire 1 y; SYNOPSYS_UNCONNECTED_1 $end +$var wire 1 z; SYNOPSYS_UNCONNECTED_2 $end +$var wire 1 {; SYNOPSYS_UNCONNECTED_3 $end +$var wire 1 |; BUF_net_153 $end + +$scope module mux_l1_in_0_ $end +$var wire 1 ; in [0] $end +$var wire 1 s in [1] $end +$var wire 1 #" mem [0] $end +$var wire 1 y; mem_inv [0] $end +$var wire 1 w; out [0] $end + +$scope module sky130_fd_sc_hd__mux2_1_0 $end +$var wire 1 w; X $end +$var wire 1 s A0 $end +$var wire 1 ; A1 $end +$var wire 1 #" S $end +$var supply1 1 }; VPWR $end +$var supply0 1 ~; VGND $end +$var supply1 1 !< VPB $end +$var supply0 1 "< VNB $end + +$scope module base $end +$var wire 1 w; X $end +$var wire 1 s A0 $end +$var wire 1 ; A1 $end +$var wire 1 #" S $end +$var wire 1 #< mux_2to10_out_X $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mux_l2_in_0_ $end +$var wire 1 w; in [0] $end +$var wire 1 z; in [1] $end +$var wire 1 $" mem [0] $end +$var wire 1 {; mem_inv [0] $end +$var wire 1 x; out [0] $end +$var wire 1 L$ p0 $end + +$scope module sky130_fd_sc_hd__mux2_1_0 $end +$var wire 1 x; X $end +$var wire 1 L$ A0 $end +$var wire 1 w; A1 $end +$var wire 1 $" S $end +$var supply1 1 $< VPWR $end +$var supply0 1 %< VGND $end +$var supply1 1 &< VPB $end +$var supply0 1 '< VNB $end + +$scope module base $end +$var wire 1 x; X $end +$var wire 1 L$ A0 $end +$var wire 1 w; A1 $end +$var wire 1 $" S $end +$var wire 1 (< mux_2to10_out_X $end +$upscope $end +$upscope $end +$upscope $end + +$scope module BINV_R_152 $end +$var wire 1 J! Y $end +$var wire 1 |; A $end +$var supply1 1 )< VPWR $end +$var supply0 1 *< VGND $end +$var supply1 1 +< VPB $end +$var supply0 1 ,< VNB $end + +$scope module base $end +$var wire 1 J! Y $end +$var wire 1 |; A $end +$var wire 1 -< not0_out_Y $end +$upscope $end +$upscope $end + +$scope module BINV_R_153 $end +$var wire 1 |; Y $end +$var wire 1 x; A $end +$var supply1 1 .< VPWR $end +$var supply0 1 /< VGND $end +$var supply1 1 0< VPB $end +$var supply0 1 1< VNB $end + +$scope module base $end +$var wire 1 |; Y $end +$var wire 1 x; A $end +$var wire 1 2< not0_out_Y $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mux_left_track_41 $end +$var wire 1 < in [0] $end +$var wire 1 t in [1] $end +$var wire 1 %" sram [0] $end +$var wire 1 &" sram [1] $end +$var wire 1 e$ sram_inv [0] $end +$var wire 1 f$ sram_inv [1] $end +$var wire 1 K! out [0] $end +$var wire 1 L$ p0 $end +$var wire 1 3< mux_2level_tapbuf_basis_input2_mem1_0_out [0] $end +$var wire 1 4< mux_2level_tapbuf_basis_input2_mem1_1_out [0] $end +$var wire 1 5< SYNOPSYS_UNCONNECTED_1 $end +$var wire 1 6< SYNOPSYS_UNCONNECTED_2 $end +$var wire 1 7< SYNOPSYS_UNCONNECTED_3 $end +$var wire 1 8< BUF_net_155 $end + +$scope module mux_l1_in_0_ $end +$var wire 1 < in [0] $end +$var wire 1 t in [1] $end +$var wire 1 %" mem [0] $end +$var wire 1 5< mem_inv [0] $end +$var wire 1 3< out [0] $end + +$scope module sky130_fd_sc_hd__mux2_1_0 $end +$var wire 1 3< X $end +$var wire 1 t A0 $end +$var wire 1 < A1 $end +$var wire 1 %" S $end +$var supply1 1 9< VPWR $end +$var supply0 1 :< VGND $end +$var supply1 1 ;< VPB $end +$var supply0 1 << VNB $end + +$scope module base $end +$var wire 1 3< X $end +$var wire 1 t A0 $end +$var wire 1 < A1 $end +$var wire 1 %" S $end +$var wire 1 =< mux_2to10_out_X $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mux_l2_in_0_ $end +$var wire 1 3< in [0] $end +$var wire 1 6< in [1] $end +$var wire 1 &" mem [0] $end +$var wire 1 7< mem_inv [0] $end +$var wire 1 4< out [0] $end +$var wire 1 L$ p0 $end + +$scope module sky130_fd_sc_hd__mux2_1_0 $end +$var wire 1 4< X $end +$var wire 1 L$ A0 $end +$var wire 1 3< A1 $end +$var wire 1 &" S $end +$var supply1 1 >< VPWR $end +$var supply0 1 ?< VGND $end +$var supply1 1 @< VPB $end +$var supply0 1 A< VNB $end + +$scope module base $end +$var wire 1 4< X $end +$var wire 1 L$ A0 $end +$var wire 1 3< A1 $end +$var wire 1 &" S $end +$var wire 1 B< mux_2to10_out_X $end +$upscope $end +$upscope $end +$upscope $end + +$scope module BINV_R_154 $end +$var wire 1 K! Y $end +$var wire 1 8< A $end +$var supply1 1 C< VPWR $end +$var supply0 1 D< VGND $end +$var supply1 1 E< VPB $end +$var supply0 1 F< VNB $end + +$scope module base $end +$var wire 1 K! Y $end +$var wire 1 8< A $end +$var wire 1 G< not0_out_Y $end +$upscope $end +$upscope $end + +$scope module BINV_R_155 $end +$var wire 1 8< Y $end +$var wire 1 4< A $end +$var supply1 1 H< VPWR $end +$var supply0 1 I< VGND $end +$var supply1 1 J< VPB $end +$var supply0 1 K< VNB $end + +$scope module base $end +$var wire 1 8< Y $end +$var wire 1 4< A $end +$var wire 1 L< not0_out_Y $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mux_left_track_43 $end +$var wire 1 = in [0] $end +$var wire 1 u in [1] $end +$var wire 1 '" sram [0] $end +$var wire 1 (" sram [1] $end +$var wire 1 g$ sram_inv [0] $end +$var wire 1 h$ sram_inv [1] $end +$var wire 1 L! out [0] $end +$var wire 1 L$ p0 $end +$var wire 1 M< mux_2level_tapbuf_basis_input2_mem1_0_out [0] $end +$var wire 1 N< mux_2level_tapbuf_basis_input2_mem1_1_out [0] $end +$var wire 1 O< SYNOPSYS_UNCONNECTED_1 $end +$var wire 1 P< SYNOPSYS_UNCONNECTED_2 $end +$var wire 1 Q< SYNOPSYS_UNCONNECTED_3 $end +$var wire 1 R< BUF_net_157 $end + +$scope module mux_l1_in_0_ $end +$var wire 1 = in [0] $end +$var wire 1 u in [1] $end +$var wire 1 '" mem [0] $end +$var wire 1 O< mem_inv [0] $end +$var wire 1 M< out [0] $end + +$scope module sky130_fd_sc_hd__mux2_1_0 $end +$var wire 1 M< X $end +$var wire 1 u A0 $end +$var wire 1 = A1 $end +$var wire 1 '" S $end +$var supply1 1 S< VPWR $end +$var supply0 1 T< VGND $end +$var supply1 1 U< VPB $end +$var supply0 1 V< VNB $end + +$scope module base $end +$var wire 1 M< X $end +$var wire 1 u A0 $end +$var wire 1 = A1 $end +$var wire 1 '" S $end +$var wire 1 W< mux_2to10_out_X $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mux_l2_in_0_ $end +$var wire 1 M< in [0] $end +$var wire 1 P< in [1] $end +$var wire 1 (" mem [0] $end +$var wire 1 Q< mem_inv [0] $end +$var wire 1 N< out [0] $end +$var wire 1 L$ p0 $end + +$scope module sky130_fd_sc_hd__mux2_1_0 $end +$var wire 1 N< X $end +$var wire 1 L$ A0 $end +$var wire 1 M< A1 $end +$var wire 1 (" S $end +$var supply1 1 X< VPWR $end +$var supply0 1 Y< VGND $end +$var supply1 1 Z< VPB $end +$var supply0 1 [< VNB $end + +$scope module base $end +$var wire 1 N< X $end +$var wire 1 L$ A0 $end +$var wire 1 M< A1 $end +$var wire 1 (" S $end +$var wire 1 \< mux_2to10_out_X $end +$upscope $end +$upscope $end +$upscope $end + +$scope module BINV_R_156 $end +$var wire 1 L! Y $end +$var wire 1 R< A $end +$var supply1 1 ]< VPWR $end +$var supply0 1 ^< VGND $end +$var supply1 1 _< VPB $end +$var supply0 1 `< VNB $end + +$scope module base $end +$var wire 1 L! Y $end +$var wire 1 R< A $end +$var wire 1 a< not0_out_Y $end +$upscope $end +$upscope $end + +$scope module BINV_R_157 $end +$var wire 1 R< Y $end +$var wire 1 N< A $end +$var supply1 1 b< VPWR $end +$var supply0 1 c< VGND $end +$var supply1 1 d< VPB $end +$var supply0 1 e< VNB $end + +$scope module base $end +$var wire 1 R< Y $end +$var wire 1 N< A $end +$var wire 1 f< not0_out_Y $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mux_left_track_45 $end +$var wire 1 > in [0] $end +$var wire 1 n in [1] $end +$var wire 1 +" sram [0] $end +$var wire 1 ," sram [1] $end +$var wire 1 i$ sram_inv [0] $end +$var wire 1 j$ sram_inv [1] $end +$var wire 1 M! out [0] $end +$var wire 1 L$ p0 $end +$var wire 1 g< mux_2level_tapbuf_basis_input2_mem1_0_out [0] $end +$var wire 1 h< mux_2level_tapbuf_basis_input2_mem1_1_out [0] $end +$var wire 1 i< SYNOPSYS_UNCONNECTED_1 $end +$var wire 1 j< SYNOPSYS_UNCONNECTED_2 $end +$var wire 1 k< SYNOPSYS_UNCONNECTED_3 $end +$var wire 1 l< BUF_net_159 $end + +$scope module mux_l1_in_0_ $end +$var wire 1 > in [0] $end +$var wire 1 n in [1] $end +$var wire 1 +" mem [0] $end +$var wire 1 i< mem_inv [0] $end +$var wire 1 g< out [0] $end + +$scope module sky130_fd_sc_hd__mux2_1_0 $end +$var wire 1 g< X $end +$var wire 1 n A0 $end +$var wire 1 > A1 $end +$var wire 1 +" S $end +$var supply1 1 m< VPWR $end +$var supply0 1 n< VGND $end +$var supply1 1 o< VPB $end +$var supply0 1 p< VNB $end + +$scope module base $end +$var wire 1 g< X $end +$var wire 1 n A0 $end +$var wire 1 > A1 $end +$var wire 1 +" S $end +$var wire 1 q< mux_2to10_out_X $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mux_l2_in_0_ $end +$var wire 1 g< in [0] $end +$var wire 1 j< in [1] $end +$var wire 1 ," mem [0] $end +$var wire 1 k< mem_inv [0] $end +$var wire 1 h< out [0] $end +$var wire 1 L$ p0 $end + +$scope module sky130_fd_sc_hd__mux2_1_0 $end +$var wire 1 h< X $end +$var wire 1 L$ A0 $end +$var wire 1 g< A1 $end +$var wire 1 ," S $end +$var supply1 1 r< VPWR $end +$var supply0 1 s< VGND $end +$var supply1 1 t< VPB $end +$var supply0 1 u< VNB $end + +$scope module base $end +$var wire 1 h< X $end +$var wire 1 L$ A0 $end +$var wire 1 g< A1 $end +$var wire 1 ," S $end +$var wire 1 v< mux_2to10_out_X $end +$upscope $end +$upscope $end +$upscope $end + +$scope module BINV_R_158 $end +$var wire 1 M! Y $end +$var wire 1 l< A $end +$var supply1 1 w< VPWR $end +$var supply0 1 x< VGND $end +$var supply1 1 y< VPB $end +$var supply0 1 z< VNB $end + +$scope module base $end +$var wire 1 M! Y $end +$var wire 1 l< A $end +$var wire 1 {< not0_out_Y $end +$upscope $end +$upscope $end + +$scope module BINV_R_159 $end +$var wire 1 l< Y $end +$var wire 1 h< A $end +$var supply1 1 |< VPWR $end +$var supply0 1 }< VGND $end +$var supply1 1 ~< VPB $end +$var supply0 1 != VNB $end + +$scope module base $end +$var wire 1 l< Y $end +$var wire 1 h< A $end +$var wire 1 "= not0_out_Y $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mux_left_track_47 $end +$var wire 1 ? in [0] $end +$var wire 1 o in [1] $end +$var wire 1 -" sram [0] $end +$var wire 1 ." sram [1] $end +$var wire 1 k$ sram_inv [0] $end +$var wire 1 l$ sram_inv [1] $end +$var wire 1 N! out [0] $end +$var wire 1 L$ p0 $end +$var wire 1 #= mux_2level_tapbuf_basis_input2_mem1_0_out [0] $end +$var wire 1 $= mux_2level_tapbuf_basis_input2_mem1_1_out [0] $end +$var wire 1 %= SYNOPSYS_UNCONNECTED_1 $end +$var wire 1 &= SYNOPSYS_UNCONNECTED_2 $end +$var wire 1 '= SYNOPSYS_UNCONNECTED_3 $end +$var wire 1 (= BUF_net_161 $end + +$scope module mux_l1_in_0_ $end +$var wire 1 ? in [0] $end +$var wire 1 o in [1] $end +$var wire 1 -" mem [0] $end +$var wire 1 %= mem_inv [0] $end +$var wire 1 #= out [0] $end + +$scope module sky130_fd_sc_hd__mux2_1_0 $end +$var wire 1 #= X $end +$var wire 1 o A0 $end +$var wire 1 ? A1 $end +$var wire 1 -" S $end +$var supply1 1 )= VPWR $end +$var supply0 1 *= VGND $end +$var supply1 1 += VPB $end +$var supply0 1 ,= VNB $end + +$scope module base $end +$var wire 1 #= X $end +$var wire 1 o A0 $end +$var wire 1 ? A1 $end +$var wire 1 -" S $end +$var wire 1 -= mux_2to10_out_X $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mux_l2_in_0_ $end +$var wire 1 #= in [0] $end +$var wire 1 &= in [1] $end +$var wire 1 ." mem [0] $end +$var wire 1 '= mem_inv [0] $end +$var wire 1 $= out [0] $end +$var wire 1 L$ p0 $end + +$scope module sky130_fd_sc_hd__mux2_1_0 $end +$var wire 1 $= X $end +$var wire 1 L$ A0 $end +$var wire 1 #= A1 $end +$var wire 1 ." S $end +$var supply1 1 .= VPWR $end +$var supply0 1 /= VGND $end +$var supply1 1 0= VPB $end +$var supply0 1 1= VNB $end + +$scope module base $end +$var wire 1 $= X $end +$var wire 1 L$ A0 $end +$var wire 1 #= A1 $end +$var wire 1 ." S $end +$var wire 1 2= mux_2to10_out_X $end +$upscope $end +$upscope $end +$upscope $end + +$scope module BINV_R_160 $end +$var wire 1 N! Y $end +$var wire 1 (= A $end +$var supply1 1 3= VPWR $end +$var supply0 1 4= VGND $end +$var supply1 1 5= VPB $end +$var supply0 1 6= VNB $end + +$scope module base $end +$var wire 1 N! Y $end +$var wire 1 (= A $end +$var wire 1 7= not0_out_Y $end +$upscope $end +$upscope $end + +$scope module BINV_R_161 $end +$var wire 1 (= Y $end +$var wire 1 $= A $end +$var supply1 1 8= VPWR $end +$var supply0 1 9= VGND $end +$var supply1 1 := VPB $end +$var supply0 1 ;= VNB $end + +$scope module base $end +$var wire 1 (= Y $end +$var wire 1 $= A $end +$var wire 1 <= not0_out_Y $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mux_left_track_49 $end +$var wire 1 @ in [0] $end +$var wire 1 p in [1] $end +$var wire 1 /" sram [0] $end +$var wire 1 0" sram [1] $end +$var wire 1 m$ sram_inv [0] $end +$var wire 1 n$ sram_inv [1] $end +$var wire 1 O! out [0] $end +$var wire 1 L$ p0 $end +$var wire 1 == mux_2level_tapbuf_basis_input2_mem1_0_out [0] $end +$var wire 1 >= mux_2level_tapbuf_basis_input2_mem1_1_out [0] $end +$var wire 1 ?= SYNOPSYS_UNCONNECTED_1 $end +$var wire 1 @= SYNOPSYS_UNCONNECTED_2 $end +$var wire 1 A= SYNOPSYS_UNCONNECTED_3 $end +$var wire 1 B= BUF_net_163 $end + +$scope module mux_l1_in_0_ $end +$var wire 1 @ in [0] $end +$var wire 1 p in [1] $end +$var wire 1 /" mem [0] $end +$var wire 1 ?= mem_inv [0] $end +$var wire 1 == out [0] $end + +$scope module sky130_fd_sc_hd__mux2_1_0 $end +$var wire 1 == X $end +$var wire 1 p A0 $end +$var wire 1 @ A1 $end +$var wire 1 /" S $end +$var supply1 1 C= VPWR $end +$var supply0 1 D= VGND $end +$var supply1 1 E= VPB $end +$var supply0 1 F= VNB $end + +$scope module base $end +$var wire 1 == X $end +$var wire 1 p A0 $end +$var wire 1 @ A1 $end +$var wire 1 /" S $end +$var wire 1 G= mux_2to10_out_X $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mux_l2_in_0_ $end +$var wire 1 == in [0] $end +$var wire 1 @= in [1] $end +$var wire 1 0" mem [0] $end +$var wire 1 A= mem_inv [0] $end +$var wire 1 >= out [0] $end +$var wire 1 L$ p0 $end + +$scope module sky130_fd_sc_hd__mux2_1_0 $end +$var wire 1 >= X $end +$var wire 1 L$ A0 $end +$var wire 1 == A1 $end +$var wire 1 0" S $end +$var supply1 1 H= VPWR $end +$var supply0 1 I= VGND $end +$var supply1 1 J= VPB $end +$var supply0 1 K= VNB $end + +$scope module base $end +$var wire 1 >= X $end +$var wire 1 L$ A0 $end +$var wire 1 == A1 $end +$var wire 1 0" S $end +$var wire 1 L= mux_2to10_out_X $end +$upscope $end +$upscope $end +$upscope $end + +$scope module BINV_R_162 $end +$var wire 1 O! Y $end +$var wire 1 B= A $end +$var supply1 1 M= VPWR $end +$var supply0 1 N= VGND $end +$var supply1 1 O= VPB $end +$var supply0 1 P= VNB $end + +$scope module base $end +$var wire 1 O! Y $end +$var wire 1 B= A $end +$var wire 1 Q= not0_out_Y $end +$upscope $end +$upscope $end + +$scope module BINV_R_163 $end +$var wire 1 B= Y $end +$var wire 1 >= A $end +$var supply1 1 R= VPWR $end +$var supply0 1 S= VGND $end +$var supply1 1 T= VPB $end +$var supply0 1 U= VNB $end + +$scope module base $end +$var wire 1 B= Y $end +$var wire 1 >= A $end +$var wire 1 V= not0_out_Y $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mux_left_track_51 $end +$var wire 1 A in [0] $end +$var wire 1 q in [1] $end +$var wire 1 1" sram [0] $end +$var wire 1 2" sram [1] $end +$var wire 1 o$ sram_inv [0] $end +$var wire 1 p$ sram_inv [1] $end +$var wire 1 P! out [0] $end +$var wire 1 L$ p0 $end +$var wire 1 W= mux_2level_tapbuf_basis_input2_mem1_0_out [0] $end +$var wire 1 X= mux_2level_tapbuf_basis_input2_mem1_1_out [0] $end +$var wire 1 Y= SYNOPSYS_UNCONNECTED_1 $end +$var wire 1 Z= SYNOPSYS_UNCONNECTED_2 $end +$var wire 1 [= SYNOPSYS_UNCONNECTED_3 $end +$var wire 1 \= BUF_net_165 $end + +$scope module mux_l1_in_0_ $end +$var wire 1 A in [0] $end +$var wire 1 q in [1] $end +$var wire 1 1" mem [0] $end +$var wire 1 Y= mem_inv [0] $end +$var wire 1 W= out [0] $end + +$scope module sky130_fd_sc_hd__mux2_1_0 $end +$var wire 1 W= X $end +$var wire 1 q A0 $end +$var wire 1 A A1 $end +$var wire 1 1" S $end +$var supply1 1 ]= VPWR $end +$var supply0 1 ^= VGND $end +$var supply1 1 _= VPB $end +$var supply0 1 `= VNB $end + +$scope module base $end +$var wire 1 W= X $end +$var wire 1 q A0 $end +$var wire 1 A A1 $end +$var wire 1 1" S $end +$var wire 1 a= mux_2to10_out_X $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mux_l2_in_0_ $end +$var wire 1 W= in [0] $end +$var wire 1 Z= in [1] $end +$var wire 1 2" mem [0] $end +$var wire 1 [= mem_inv [0] $end +$var wire 1 X= out [0] $end +$var wire 1 L$ p0 $end + +$scope module sky130_fd_sc_hd__mux2_1_0 $end +$var wire 1 X= X $end +$var wire 1 L$ A0 $end +$var wire 1 W= A1 $end +$var wire 1 2" S $end +$var supply1 1 b= VPWR $end +$var supply0 1 c= VGND $end +$var supply1 1 d= VPB $end +$var supply0 1 e= VNB $end + +$scope module base $end +$var wire 1 X= X $end +$var wire 1 L$ A0 $end +$var wire 1 W= A1 $end +$var wire 1 2" S $end +$var wire 1 f= mux_2to10_out_X $end +$upscope $end +$upscope $end +$upscope $end + +$scope module BINV_R_164 $end +$var wire 1 P! Y $end +$var wire 1 \= A $end +$var supply1 1 g= VPWR $end +$var supply0 1 h= VGND $end +$var supply1 1 i= VPB $end +$var supply0 1 j= VNB $end + +$scope module base $end +$var wire 1 P! Y $end +$var wire 1 \= A $end +$var wire 1 k= not0_out_Y $end +$upscope $end +$upscope $end + +$scope module BINV_R_165 $end +$var wire 1 \= Y $end +$var wire 1 X= A $end +$var supply1 1 l= VPWR $end +$var supply0 1 m= VGND $end +$var supply1 1 n= VPB $end +$var supply0 1 o= VNB $end + +$scope module base $end +$var wire 1 \= Y $end +$var wire 1 X= A $end +$var wire 1 p= not0_out_Y $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mux_left_track_55 $end +$var wire 1 C in [0] $end +$var wire 1 s in [1] $end +$var wire 1 3" sram [0] $end +$var wire 1 4" sram [1] $end +$var wire 1 q$ sram_inv [0] $end +$var wire 1 r$ sram_inv [1] $end +$var wire 1 R! out [0] $end +$var wire 1 .$ p0 $end +$var wire 1 q= mux_2level_tapbuf_basis_input2_mem1_0_out [0] $end +$var wire 1 r= mux_2level_tapbuf_basis_input2_mem1_1_out [0] $end +$var wire 1 s= SYNOPSYS_UNCONNECTED_1 $end +$var wire 1 t= SYNOPSYS_UNCONNECTED_2 $end +$var wire 1 u= SYNOPSYS_UNCONNECTED_3 $end +$var wire 1 v= BUF_net_167 $end + +$scope module mux_l1_in_0_ $end +$var wire 1 C in [0] $end +$var wire 1 s in [1] $end +$var wire 1 3" mem [0] $end +$var wire 1 s= mem_inv [0] $end +$var wire 1 q= out [0] $end + +$scope module sky130_fd_sc_hd__mux2_1_0 $end +$var wire 1 q= X $end +$var wire 1 s A0 $end +$var wire 1 C A1 $end +$var wire 1 3" S $end +$var supply1 1 w= VPWR $end +$var supply0 1 x= VGND $end +$var supply1 1 y= VPB $end +$var supply0 1 z= VNB $end + +$scope module base $end +$var wire 1 q= X $end +$var wire 1 s A0 $end +$var wire 1 C A1 $end +$var wire 1 3" S $end +$var wire 1 {= mux_2to10_out_X $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mux_l2_in_0_ $end +$var wire 1 q= in [0] $end +$var wire 1 t= in [1] $end +$var wire 1 4" mem [0] $end +$var wire 1 u= mem_inv [0] $end +$var wire 1 r= out [0] $end +$var wire 1 .$ p0 $end + +$scope module sky130_fd_sc_hd__mux2_1_0 $end +$var wire 1 r= X $end +$var wire 1 .$ A0 $end +$var wire 1 q= A1 $end +$var wire 1 4" S $end +$var supply1 1 |= VPWR $end +$var supply0 1 }= VGND $end +$var supply1 1 ~= VPB $end +$var supply0 1 !> VNB $end + +$scope module base $end +$var wire 1 r= X $end +$var wire 1 .$ A0 $end +$var wire 1 q= A1 $end +$var wire 1 4" S $end +$var wire 1 "> mux_2to10_out_X $end +$upscope $end +$upscope $end +$upscope $end + +$scope module BINV_R_166 $end +$var wire 1 R! Y $end +$var wire 1 v= A $end +$var supply1 1 #> VPWR $end +$var supply0 1 $> VGND $end +$var supply1 1 %> VPB $end +$var supply0 1 &> VNB $end + +$scope module base $end +$var wire 1 R! Y $end +$var wire 1 v= A $end +$var wire 1 '> not0_out_Y $end +$upscope $end +$upscope $end + +$scope module BINV_R_167 $end +$var wire 1 v= Y $end +$var wire 1 r= A $end +$var supply1 1 (> VPWR $end +$var supply0 1 )> VGND $end +$var supply1 1 *> VPB $end +$var supply0 1 +> VNB $end + +$scope module base $end +$var wire 1 v= Y $end +$var wire 1 r= A $end +$var wire 1 ,> not0_out_Y $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mux_left_track_57 $end +$var wire 1 D in [0] $end +$var wire 1 t in [1] $end +$var wire 1 5" sram [0] $end +$var wire 1 6" sram [1] $end +$var wire 1 s$ sram_inv [0] $end +$var wire 1 t$ sram_inv [1] $end +$var wire 1 S! out [0] $end +$var wire 1 .$ p0 $end +$var wire 1 -> mux_2level_tapbuf_basis_input2_mem1_0_out [0] $end +$var wire 1 .> mux_2level_tapbuf_basis_input2_mem1_1_out [0] $end +$var wire 1 /> SYNOPSYS_UNCONNECTED_1 $end +$var wire 1 0> SYNOPSYS_UNCONNECTED_2 $end +$var wire 1 1> SYNOPSYS_UNCONNECTED_3 $end +$var wire 1 2> BUF_net_169 $end + +$scope module mux_l1_in_0_ $end +$var wire 1 D in [0] $end +$var wire 1 t in [1] $end +$var wire 1 5" mem [0] $end +$var wire 1 /> mem_inv [0] $end +$var wire 1 -> out [0] $end + +$scope module sky130_fd_sc_hd__mux2_1_0 $end +$var wire 1 -> X $end +$var wire 1 t A0 $end +$var wire 1 D A1 $end +$var wire 1 5" S $end +$var supply1 1 3> VPWR $end +$var supply0 1 4> VGND $end +$var supply1 1 5> VPB $end +$var supply0 1 6> VNB $end + +$scope module base $end +$var wire 1 -> X $end +$var wire 1 t A0 $end +$var wire 1 D A1 $end +$var wire 1 5" S $end +$var wire 1 7> mux_2to10_out_X $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mux_l2_in_0_ $end +$var wire 1 -> in [0] $end +$var wire 1 0> in [1] $end +$var wire 1 6" mem [0] $end +$var wire 1 1> mem_inv [0] $end +$var wire 1 .> out [0] $end +$var wire 1 .$ p0 $end + +$scope module sky130_fd_sc_hd__mux2_1_0 $end +$var wire 1 .> X $end +$var wire 1 .$ A0 $end +$var wire 1 -> A1 $end +$var wire 1 6" S $end +$var supply1 1 8> VPWR $end +$var supply0 1 9> VGND $end +$var supply1 1 :> VPB $end +$var supply0 1 ;> VNB $end + +$scope module base $end +$var wire 1 .> X $end +$var wire 1 .$ A0 $end +$var wire 1 -> A1 $end +$var wire 1 6" S $end +$var wire 1 <> mux_2to10_out_X $end +$upscope $end +$upscope $end +$upscope $end + +$scope module BINV_R_168 $end +$var wire 1 S! Y $end +$var wire 1 2> A $end +$var supply1 1 => VPWR $end +$var supply0 1 >> VGND $end +$var supply1 1 ?> VPB $end +$var supply0 1 @> VNB $end + +$scope module base $end +$var wire 1 S! Y $end +$var wire 1 2> A $end +$var wire 1 A> not0_out_Y $end +$upscope $end +$upscope $end + +$scope module BINV_R_169 $end +$var wire 1 2> Y $end +$var wire 1 .> A $end +$var supply1 1 B> VPWR $end +$var supply0 1 C> VGND $end +$var supply1 1 D> VPB $end +$var supply0 1 E> VNB $end + +$scope module base $end +$var wire 1 2> Y $end +$var wire 1 .> A $end +$var wire 1 F> not0_out_Y $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mux_left_track_59 $end +$var wire 1 E in [0] $end +$var wire 1 u in [1] $end +$var wire 1 7" sram [0] $end +$var wire 1 8" sram [1] $end +$var wire 1 u$ sram_inv [0] $end +$var wire 1 v$ sram_inv [1] $end +$var wire 1 T! out [0] $end +$var wire 1 .$ p0 $end +$var wire 1 G> mux_2level_tapbuf_basis_input2_mem1_0_out [0] $end +$var wire 1 H> mux_2level_tapbuf_basis_input2_mem1_1_out [0] $end +$var wire 1 I> SYNOPSYS_UNCONNECTED_1 $end +$var wire 1 J> SYNOPSYS_UNCONNECTED_2 $end +$var wire 1 K> SYNOPSYS_UNCONNECTED_3 $end + +$scope module sky130_fd_sc_hd__buf_4_0_ $end +$var wire 1 T! X $end +$var wire 1 H> A $end +$var supply1 1 L> VPWR $end +$var supply0 1 M> VGND $end +$var supply1 1 N> VPB $end +$var supply0 1 O> VNB $end + +$scope module base $end +$var wire 1 T! X $end +$var wire 1 H> A $end +$var wire 1 P> buf0_out_X $end +$upscope $end +$upscope $end + +$scope module mux_l1_in_0_ $end +$var wire 1 E in [0] $end +$var wire 1 u in [1] $end +$var wire 1 7" mem [0] $end +$var wire 1 I> mem_inv [0] $end +$var wire 1 G> out [0] $end + +$scope module sky130_fd_sc_hd__mux2_1_0 $end +$var wire 1 G> X $end +$var wire 1 u A0 $end +$var wire 1 E A1 $end +$var wire 1 7" S $end +$var supply1 1 Q> VPWR $end +$var supply0 1 R> VGND $end +$var supply1 1 S> VPB $end +$var supply0 1 T> VNB $end + +$scope module base $end +$var wire 1 G> X $end +$var wire 1 u A0 $end +$var wire 1 E A1 $end +$var wire 1 7" S $end +$var wire 1 U> mux_2to10_out_X $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mux_l2_in_0_ $end +$var wire 1 G> in [0] $end +$var wire 1 J> in [1] $end +$var wire 1 8" mem [0] $end +$var wire 1 K> mem_inv [0] $end +$var wire 1 H> out [0] $end +$var wire 1 .$ p0 $end + +$scope module sky130_fd_sc_hd__mux2_1_0 $end +$var wire 1 H> X $end +$var wire 1 .$ A0 $end +$var wire 1 G> A1 $end +$var wire 1 8" S $end +$var supply1 1 V> VPWR $end +$var supply0 1 W> VGND $end +$var supply1 1 X> VPB $end +$var supply0 1 Y> VNB $end + +$scope module base $end +$var wire 1 H> X $end +$var wire 1 .$ A0 $end +$var wire 1 G> A1 $end +$var wire 1 8" S $end +$var wire 1 Z> mux_2to10_out_X $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mem_bottom_track_13 $end +$var wire 1 ( pReset [0] $end +$var wire 1 Y! prog_clk [0] $end +$var wire 1 P# ccff_head [0] $end +$var wire 1 G" ccff_tail [0] $end +$var wire 1 [! mem_out [0] $end +$var wire 1 \! mem_out [1] $end + +$scope module sky130_fd_sc_hd__dfrtp_1_0_ $end +$var wire 1 [! Q $end +$var wire 1 Y! CLK $end +$var wire 1 P# D $end +$var wire 1 ( RESET_B $end +$var supply1 1 [> VPWR $end +$var supply0 1 \> VGND $end +$var supply1 1 ]> VPB $end +$var supply0 1 ^> VNB $end + +$scope module base $end +$var wire 1 [! Q $end +$var wire 1 Y! CLK $end +$var wire 1 P# D $end +$var wire 1 ( RESET_B $end +$var wire 1 _> buf_Q $end +$var wire 1 `> RESET $end +$upscope $end +$upscope $end + +$scope module sky130_fd_sc_hd__dfrtp_1_1_ $end +$var wire 1 \! Q $end +$var wire 1 Y! CLK $end +$var wire 1 [! D $end +$var wire 1 ( RESET_B $end +$var supply1 1 a> VPWR $end +$var supply0 1 b> VGND $end +$var supply1 1 c> VPB $end +$var supply0 1 d> VNB $end + +$scope module base $end +$var wire 1 \! Q $end +$var wire 1 Y! CLK $end +$var wire 1 [! D $end +$var wire 1 ( RESET_B $end +$var wire 1 e> buf_Q $end +$var wire 1 f> RESET $end +$upscope $end +$upscope $end + +$scope module FTB_37__36 $end +$var wire 1 G" X $end +$var wire 1 \! A $end +$var supply1 1 g> VPWR $end +$var supply0 1 h> VGND $end +$var supply1 1 i> VPB $end +$var supply0 1 j> VNB $end + +$scope module base $end +$var wire 1 G" X $end +$var wire 1 \! A $end +$var wire 1 k> buf0_out_X $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mem_bottom_track_15 $end +$var wire 1 ( pReset [0] $end +$var wire 1 Y! prog_clk [0] $end +$var wire 1 G" ccff_head [0] $end +$var wire 1 R" ccff_tail [0] $end +$var wire 1 q! mem_out [0] $end +$var wire 1 r! mem_out [1] $end + +$scope module sky130_fd_sc_hd__dfrtp_1_0_ $end +$var wire 1 q! Q $end +$var wire 1 Y! CLK $end +$var wire 1 G" D $end +$var wire 1 ( RESET_B $end +$var supply1 1 l> VPWR $end +$var supply0 1 m> VGND $end +$var supply1 1 n> VPB $end +$var supply0 1 o> VNB $end + +$scope module base $end +$var wire 1 q! Q $end +$var wire 1 Y! CLK $end +$var wire 1 G" D $end +$var wire 1 ( RESET_B $end +$var wire 1 p> buf_Q $end +$var wire 1 q> RESET $end +$upscope $end +$upscope $end + +$scope module sky130_fd_sc_hd__dfrtp_1_1_ $end +$var wire 1 r! Q $end +$var wire 1 Y! CLK $end +$var wire 1 q! D $end +$var wire 1 ( RESET_B $end +$var supply1 1 r> VPWR $end +$var supply0 1 s> VGND $end +$var supply1 1 t> VPB $end +$var supply0 1 u> VNB $end + +$scope module base $end +$var wire 1 r! Q $end +$var wire 1 Y! CLK $end +$var wire 1 q! D $end +$var wire 1 ( RESET_B $end +$var wire 1 v> buf_Q $end +$var wire 1 w> RESET $end +$upscope $end +$upscope $end + +$scope module FTB_38__37 $end +$var wire 1 R" X $end +$var wire 1 r! A $end +$var supply1 1 x> VPWR $end +$var supply0 1 y> VGND $end +$var supply1 1 z> VPB $end +$var supply0 1 {> VNB $end + +$scope module base $end +$var wire 1 R" X $end +$var wire 1 r! A $end +$var wire 1 |> buf0_out_X $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mem_bottom_track_17 $end +$var wire 1 ( pReset [0] $end +$var wire 1 Y! prog_clk [0] $end +$var wire 1 R" ccff_head [0] $end +$var wire 1 ]" ccff_tail [0] $end +$var wire 1 )" mem_out [0] $end +$var wire 1 *" mem_out [1] $end + +$scope module sky130_fd_sc_hd__dfrtp_1_0_ $end +$var wire 1 )" Q $end +$var wire 1 Y! CLK $end +$var wire 1 R" D $end +$var wire 1 ( RESET_B $end +$var supply1 1 }> VPWR $end +$var supply0 1 ~> VGND $end +$var supply1 1 !? VPB $end +$var supply0 1 "? VNB $end + +$scope module base $end +$var wire 1 )" Q $end +$var wire 1 Y! CLK $end +$var wire 1 R" D $end +$var wire 1 ( RESET_B $end +$var wire 1 #? buf_Q $end +$var wire 1 $? RESET $end +$upscope $end +$upscope $end + +$scope module sky130_fd_sc_hd__dfrtp_1_1_ $end +$var wire 1 *" Q $end +$var wire 1 Y! CLK $end +$var wire 1 )" D $end +$var wire 1 ( RESET_B $end +$var supply1 1 %? VPWR $end +$var supply0 1 &? VGND $end +$var supply1 1 '? VPB $end +$var supply0 1 (? VNB $end + +$scope module base $end +$var wire 1 *" Q $end +$var wire 1 Y! CLK $end +$var wire 1 )" D $end +$var wire 1 ( RESET_B $end +$var wire 1 )? buf_Q $end +$var wire 1 *? RESET $end +$upscope $end +$upscope $end + +$scope module FTB_39__38 $end +$var wire 1 ]" X $end +$var wire 1 *" A $end +$var supply1 1 +? VPWR $end +$var supply0 1 ,? VGND $end +$var supply1 1 -? VPB $end +$var supply0 1 .? VNB $end + +$scope module base $end +$var wire 1 ]" X $end +$var wire 1 *" A $end +$var wire 1 /? buf0_out_X $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mem_bottom_track_19 $end +$var wire 1 ( pReset [0] $end +$var wire 1 Y! prog_clk [0] $end +$var wire 1 ]" ccff_head [0] $end +$var wire 1 d" ccff_tail [0] $end +$var wire 1 9" mem_out [0] $end +$var wire 1 :" mem_out [1] $end + +$scope module sky130_fd_sc_hd__dfrtp_1_0_ $end +$var wire 1 9" Q $end +$var wire 1 Y! CLK $end +$var wire 1 ]" D $end +$var wire 1 ( RESET_B $end +$var supply1 1 0? VPWR $end +$var supply0 1 1? VGND $end +$var supply1 1 2? VPB $end +$var supply0 1 3? VNB $end + +$scope module base $end +$var wire 1 9" Q $end +$var wire 1 Y! CLK $end +$var wire 1 ]" D $end +$var wire 1 ( RESET_B $end +$var wire 1 4? buf_Q $end +$var wire 1 5? RESET $end +$upscope $end +$upscope $end + +$scope module sky130_fd_sc_hd__dfrtp_1_1_ $end +$var wire 1 :" Q $end +$var wire 1 Y! CLK $end +$var wire 1 9" D $end +$var wire 1 ( RESET_B $end +$var supply1 1 6? VPWR $end +$var supply0 1 7? VGND $end +$var supply1 1 8? VPB $end +$var supply0 1 9? VNB $end + +$scope module base $end +$var wire 1 :" Q $end +$var wire 1 Y! CLK $end +$var wire 1 9" D $end +$var wire 1 ( RESET_B $end +$var wire 1 :? buf_Q $end +$var wire 1 ;? RESET $end +$upscope $end +$upscope $end + +$scope module FTB_40__39 $end +$var wire 1 d" X $end +$var wire 1 :" A $end +$var supply1 1 ? VPB $end +$var supply0 1 ?? VNB $end + +$scope module base $end +$var wire 1 d" X $end +$var wire 1 :" A $end +$var wire 1 @? buf0_out_X $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mem_bottom_track_21 $end +$var wire 1 ( pReset [0] $end +$var wire 1 Y! prog_clk [0] $end +$var wire 1 d" ccff_head [0] $end +$var wire 1 e" ccff_tail [0] $end +$var wire 1 ;" mem_out [0] $end +$var wire 1 <" mem_out [1] $end + +$scope module sky130_fd_sc_hd__dfrtp_1_0_ $end +$var wire 1 ;" Q $end +$var wire 1 Y! CLK $end +$var wire 1 d" D $end +$var wire 1 ( RESET_B $end +$var supply1 1 A? VPWR $end +$var supply0 1 B? VGND $end +$var supply1 1 C? VPB $end +$var supply0 1 D? VNB $end + +$scope module base $end +$var wire 1 ;" Q $end +$var wire 1 Y! CLK $end +$var wire 1 d" D $end +$var wire 1 ( RESET_B $end +$var wire 1 E? buf_Q $end +$var wire 1 F? RESET $end +$upscope $end +$upscope $end + +$scope module sky130_fd_sc_hd__dfrtp_1_1_ $end +$var wire 1 <" Q $end +$var wire 1 Y! CLK $end +$var wire 1 ;" D $end +$var wire 1 ( RESET_B $end +$var supply1 1 G? VPWR $end +$var supply0 1 H? VGND $end +$var supply1 1 I? VPB $end +$var supply0 1 J? VNB $end + +$scope module base $end +$var wire 1 <" Q $end +$var wire 1 Y! CLK $end +$var wire 1 ;" D $end +$var wire 1 ( RESET_B $end +$var wire 1 K? buf_Q $end +$var wire 1 L? RESET $end +$upscope $end +$upscope $end + +$scope module FTB_41__40 $end +$var wire 1 e" X $end +$var wire 1 <" A $end +$var supply1 1 M? VPWR $end +$var supply0 1 N? VGND $end +$var supply1 1 O? VPB $end +$var supply0 1 P? VNB $end + +$scope module base $end +$var wire 1 e" X $end +$var wire 1 <" A $end +$var wire 1 Q? buf0_out_X $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mem_bottom_track_23 $end +$var wire 1 ( pReset [0] $end +$var wire 1 Y! prog_clk [0] $end +$var wire 1 e" ccff_head [0] $end +$var wire 1 f" ccff_tail [0] $end +$var wire 1 =" mem_out [0] $end +$var wire 1 >" mem_out [1] $end + +$scope module sky130_fd_sc_hd__dfrtp_1_0_ $end +$var wire 1 =" Q $end +$var wire 1 Y! CLK $end +$var wire 1 e" D $end +$var wire 1 ( RESET_B $end +$var supply1 1 R? VPWR $end +$var supply0 1 S? VGND $end +$var supply1 1 T? VPB $end +$var supply0 1 U? VNB $end + +$scope module base $end +$var wire 1 =" Q $end +$var wire 1 Y! CLK $end +$var wire 1 e" D $end +$var wire 1 ( RESET_B $end +$var wire 1 V? buf_Q $end +$var wire 1 W? RESET $end +$upscope $end +$upscope $end + +$scope module sky130_fd_sc_hd__dfrtp_1_1_ $end +$var wire 1 >" Q $end +$var wire 1 Y! CLK $end +$var wire 1 =" D $end +$var wire 1 ( RESET_B $end +$var supply1 1 X? VPWR $end +$var supply0 1 Y? VGND $end +$var supply1 1 Z? VPB $end +$var supply0 1 [? VNB $end + +$scope module base $end +$var wire 1 >" Q $end +$var wire 1 Y! CLK $end +$var wire 1 =" D $end +$var wire 1 ( RESET_B $end +$var wire 1 \? buf_Q $end +$var wire 1 ]? RESET $end +$upscope $end +$upscope $end + +$scope module FTB_42__41 $end +$var wire 1 f" X $end +$var wire 1 >" A $end +$var supply1 1 ^? VPWR $end +$var supply0 1 _? VGND $end +$var supply1 1 `? VPB $end +$var supply0 1 a? VNB $end + +$scope module base $end +$var wire 1 f" X $end +$var wire 1 >" A $end +$var wire 1 b? buf0_out_X $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mem_bottom_track_25 $end +$var wire 1 ( pReset [0] $end +$var wire 1 Y! prog_clk [0] $end +$var wire 1 f" ccff_head [0] $end +$var wire 1 g" ccff_tail [0] $end +$var wire 1 ?" mem_out [0] $end +$var wire 1 @" mem_out [1] $end + +$scope module sky130_fd_sc_hd__dfrtp_1_0_ $end +$var wire 1 ?" Q $end +$var wire 1 Y! CLK $end +$var wire 1 f" D $end +$var wire 1 ( RESET_B $end +$var supply1 1 c? VPWR $end +$var supply0 1 d? VGND $end +$var supply1 1 e? VPB $end +$var supply0 1 f? VNB $end + +$scope module base $end +$var wire 1 ?" Q $end +$var wire 1 Y! CLK $end +$var wire 1 f" D $end +$var wire 1 ( RESET_B $end +$var wire 1 g? buf_Q $end +$var wire 1 h? RESET $end +$upscope $end +$upscope $end + +$scope module sky130_fd_sc_hd__dfrtp_1_1_ $end +$var wire 1 @" Q $end +$var wire 1 Y! CLK $end +$var wire 1 ?" D $end +$var wire 1 ( RESET_B $end +$var supply1 1 i? VPWR $end +$var supply0 1 j? VGND $end +$var supply1 1 k? VPB $end +$var supply0 1 l? VNB $end + +$scope module base $end +$var wire 1 @" Q $end +$var wire 1 Y! CLK $end +$var wire 1 ?" D $end +$var wire 1 ( RESET_B $end +$var wire 1 m? buf_Q $end +$var wire 1 n? RESET $end +$upscope $end +$upscope $end + +$scope module FTB_43__42 $end +$var wire 1 g" X $end +$var wire 1 @" A $end +$var supply1 1 o? VPWR $end +$var supply0 1 p? VGND $end +$var supply1 1 q? VPB $end +$var supply0 1 r? VNB $end + +$scope module base $end +$var wire 1 g" X $end +$var wire 1 @" A $end +$var wire 1 s? buf0_out_X $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mem_bottom_track_27 $end +$var wire 1 ( pReset [0] $end +$var wire 1 Y! prog_clk [0] $end +$var wire 1 g" ccff_head [0] $end +$var wire 1 h" ccff_tail [0] $end +$var wire 1 A" mem_out [0] $end +$var wire 1 B" mem_out [1] $end + +$scope module sky130_fd_sc_hd__dfrtp_1_0_ $end +$var wire 1 A" Q $end +$var wire 1 Y! CLK $end +$var wire 1 g" D $end +$var wire 1 ( RESET_B $end +$var supply1 1 t? VPWR $end +$var supply0 1 u? VGND $end +$var supply1 1 v? VPB $end +$var supply0 1 w? VNB $end + +$scope module base $end +$var wire 1 A" Q $end +$var wire 1 Y! CLK $end +$var wire 1 g" D $end +$var wire 1 ( RESET_B $end +$var wire 1 x? buf_Q $end +$var wire 1 y? RESET $end +$upscope $end +$upscope $end + +$scope module sky130_fd_sc_hd__dfrtp_1_1_ $end +$var wire 1 B" Q $end +$var wire 1 Y! CLK $end +$var wire 1 A" D $end +$var wire 1 ( RESET_B $end +$var supply1 1 z? VPWR $end +$var supply0 1 {? VGND $end +$var supply1 1 |? VPB $end +$var supply0 1 }? VNB $end + +$scope module base $end +$var wire 1 B" Q $end +$var wire 1 Y! CLK $end +$var wire 1 A" D $end +$var wire 1 ( RESET_B $end +$var wire 1 ~? buf_Q $end +$var wire 1 !@ RESET $end +$upscope $end +$upscope $end + +$scope module FTB_44__43 $end +$var wire 1 h" X $end +$var wire 1 B" A $end +$var supply1 1 "@ VPWR $end +$var supply0 1 #@ VGND $end +$var supply1 1 $@ VPB $end +$var supply0 1 %@ VNB $end + +$scope module base $end +$var wire 1 h" X $end +$var wire 1 B" A $end +$var wire 1 &@ buf0_out_X $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mem_bottom_track_39 $end +$var wire 1 ( pReset [0] $end +$var wire 1 Y! prog_clk [0] $end +$var wire 1 s" ccff_head [0] $end +$var wire 1 i" ccff_tail [0] $end +$var wire 1 C" mem_out [0] $end +$var wire 1 D" mem_out [1] $end + +$scope module sky130_fd_sc_hd__dfrtp_1_0_ $end +$var wire 1 C" Q $end +$var wire 1 Y! CLK $end +$var wire 1 s" D $end +$var wire 1 ( RESET_B $end +$var supply1 1 '@ VPWR $end +$var supply0 1 (@ VGND $end +$var supply1 1 )@ VPB $end +$var supply0 1 *@ VNB $end + +$scope module base $end +$var wire 1 C" Q $end +$var wire 1 Y! CLK $end +$var wire 1 s" D $end +$var wire 1 ( RESET_B $end +$var wire 1 +@ buf_Q $end +$var wire 1 ,@ RESET $end +$upscope $end +$upscope $end + +$scope module sky130_fd_sc_hd__dfrtp_1_1_ $end +$var wire 1 D" Q $end +$var wire 1 Y! CLK $end +$var wire 1 C" D $end +$var wire 1 ( RESET_B $end +$var supply1 1 -@ VPWR $end +$var supply0 1 .@ VGND $end +$var supply1 1 /@ VPB $end +$var supply0 1 0@ VNB $end + +$scope module base $end +$var wire 1 D" Q $end +$var wire 1 Y! CLK $end +$var wire 1 C" D $end +$var wire 1 ( RESET_B $end +$var wire 1 1@ buf_Q $end +$var wire 1 2@ RESET $end +$upscope $end +$upscope $end + +$scope module FTB_45__44 $end +$var wire 1 i" X $end +$var wire 1 D" A $end +$var supply1 1 3@ VPWR $end +$var supply0 1 4@ VGND $end +$var supply1 1 5@ VPB $end +$var supply0 1 6@ VNB $end + +$scope module base $end +$var wire 1 i" X $end +$var wire 1 D" A $end +$var wire 1 7@ buf0_out_X $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mem_bottom_track_41 $end +$var wire 1 ( pReset [0] $end +$var wire 1 Y! prog_clk [0] $end +$var wire 1 i" ccff_head [0] $end +$var wire 1 j" ccff_tail [0] $end +$var wire 1 E" mem_out [0] $end +$var wire 1 F" mem_out [1] $end + +$scope module sky130_fd_sc_hd__dfrtp_1_0_ $end +$var wire 1 E" Q $end +$var wire 1 Y! CLK $end +$var wire 1 i" D $end +$var wire 1 ( RESET_B $end +$var supply1 1 8@ VPWR $end +$var supply0 1 9@ VGND $end +$var supply1 1 :@ VPB $end +$var supply0 1 ;@ VNB $end + +$scope module base $end +$var wire 1 E" Q $end +$var wire 1 Y! CLK $end +$var wire 1 i" D $end +$var wire 1 ( RESET_B $end +$var wire 1 <@ buf_Q $end +$var wire 1 =@ RESET $end +$upscope $end +$upscope $end + +$scope module sky130_fd_sc_hd__dfrtp_1_1_ $end +$var wire 1 F" Q $end +$var wire 1 Y! CLK $end +$var wire 1 E" D $end +$var wire 1 ( RESET_B $end +$var supply1 1 >@ VPWR $end +$var supply0 1 ?@ VGND $end +$var supply1 1 @@ VPB $end +$var supply0 1 A@ VNB $end + +$scope module base $end +$var wire 1 F" Q $end +$var wire 1 Y! CLK $end +$var wire 1 E" D $end +$var wire 1 ( RESET_B $end +$var wire 1 B@ buf_Q $end +$var wire 1 C@ RESET $end +$upscope $end +$upscope $end + +$scope module FTB_46__45 $end +$var wire 1 j" X $end +$var wire 1 F" A $end +$var supply1 1 D@ VPWR $end +$var supply0 1 E@ VGND $end +$var supply1 1 F@ VPB $end +$var supply0 1 G@ VNB $end + +$scope module base $end +$var wire 1 j" X $end +$var wire 1 F" A $end +$var wire 1 H@ buf0_out_X $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mem_bottom_track_43 $end +$var wire 1 ( pReset [0] $end +$var wire 1 Y! prog_clk [0] $end +$var wire 1 j" ccff_head [0] $end +$var wire 1 H" ccff_tail [0] $end +$var wire 1 ]! mem_out [0] $end +$var wire 1 ^! mem_out [1] $end + +$scope module sky130_fd_sc_hd__dfrtp_1_0_ $end +$var wire 1 ]! Q $end +$var wire 1 Y! CLK $end +$var wire 1 j" D $end +$var wire 1 ( RESET_B $end +$var supply1 1 I@ VPWR $end +$var supply0 1 J@ VGND $end +$var supply1 1 K@ VPB $end +$var supply0 1 L@ VNB $end + +$scope module base $end +$var wire 1 ]! Q $end +$var wire 1 Y! CLK $end +$var wire 1 j" D $end +$var wire 1 ( RESET_B $end +$var wire 1 M@ buf_Q $end +$var wire 1 N@ RESET $end +$upscope $end +$upscope $end + +$scope module sky130_fd_sc_hd__dfrtp_1_1_ $end +$var wire 1 ^! Q $end +$var wire 1 Y! CLK $end +$var wire 1 ]! D $end +$var wire 1 ( RESET_B $end +$var supply1 1 O@ VPWR $end +$var supply0 1 P@ VGND $end +$var supply1 1 Q@ VPB $end +$var supply0 1 R@ VNB $end + +$scope module base $end +$var wire 1 ^! Q $end +$var wire 1 Y! CLK $end +$var wire 1 ]! D $end +$var wire 1 ( RESET_B $end +$var wire 1 S@ buf_Q $end +$var wire 1 T@ RESET $end +$upscope $end +$upscope $end + +$scope module FTB_47__46 $end +$var wire 1 H" X $end +$var wire 1 ^! A $end +$var supply1 1 U@ VPWR $end +$var supply0 1 V@ VGND $end +$var supply1 1 W@ VPB $end +$var supply0 1 X@ VNB $end + +$scope module base $end +$var wire 1 H" X $end +$var wire 1 ^! A $end +$var wire 1 Y@ buf0_out_X $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mem_bottom_track_47 $end +$var wire 1 ( pReset [0] $end +$var wire 1 Y! prog_clk [0] $end +$var wire 1 t" ccff_head [0] $end +$var wire 1 I" ccff_tail [0] $end +$var wire 1 _! mem_out [0] $end +$var wire 1 `! mem_out [1] $end + +$scope module sky130_fd_sc_hd__dfrtp_1_0_ $end +$var wire 1 _! Q $end +$var wire 1 Y! CLK $end +$var wire 1 t" D $end +$var wire 1 ( RESET_B $end +$var supply1 1 Z@ VPWR $end +$var supply0 1 [@ VGND $end +$var supply1 1 \@ VPB $end +$var supply0 1 ]@ VNB $end + +$scope module base $end +$var wire 1 _! Q $end +$var wire 1 Y! CLK $end +$var wire 1 t" D $end +$var wire 1 ( RESET_B $end +$var wire 1 ^@ buf_Q $end +$var wire 1 _@ RESET $end +$upscope $end +$upscope $end + +$scope module sky130_fd_sc_hd__dfrtp_1_1_ $end +$var wire 1 `! Q $end +$var wire 1 Y! CLK $end +$var wire 1 _! D $end +$var wire 1 ( RESET_B $end +$var supply1 1 `@ VPWR $end +$var supply0 1 a@ VGND $end +$var supply1 1 b@ VPB $end +$var supply0 1 c@ VNB $end + +$scope module base $end +$var wire 1 `! Q $end +$var wire 1 Y! CLK $end +$var wire 1 _! D $end +$var wire 1 ( RESET_B $end +$var wire 1 d@ buf_Q $end +$var wire 1 e@ RESET $end +$upscope $end +$upscope $end + +$scope module FTB_48__47 $end +$var wire 1 I" X $end +$var wire 1 `! A $end +$var supply1 1 f@ VPWR $end +$var supply0 1 g@ VGND $end +$var supply1 1 h@ VPB $end +$var supply0 1 i@ VNB $end + +$scope module base $end +$var wire 1 I" X $end +$var wire 1 `! A $end +$var wire 1 j@ buf0_out_X $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mem_bottom_track_49 $end +$var wire 1 ( pReset [0] $end +$var wire 1 Y! prog_clk [0] $end +$var wire 1 I" ccff_head [0] $end +$var wire 1 J" ccff_tail [0] $end +$var wire 1 a! mem_out [0] $end +$var wire 1 b! mem_out [1] $end + +$scope module sky130_fd_sc_hd__dfrtp_1_0_ $end +$var wire 1 a! Q $end +$var wire 1 Y! CLK $end +$var wire 1 I" D $end +$var wire 1 ( RESET_B $end +$var supply1 1 k@ VPWR $end +$var supply0 1 l@ VGND $end +$var supply1 1 m@ VPB $end +$var supply0 1 n@ VNB $end + +$scope module base $end +$var wire 1 a! Q $end +$var wire 1 Y! CLK $end +$var wire 1 I" D $end +$var wire 1 ( RESET_B $end +$var wire 1 o@ buf_Q $end +$var wire 1 p@ RESET $end +$upscope $end +$upscope $end + +$scope module sky130_fd_sc_hd__dfrtp_1_1_ $end +$var wire 1 b! Q $end +$var wire 1 Y! CLK $end +$var wire 1 a! D $end +$var wire 1 ( RESET_B $end +$var supply1 1 q@ VPWR $end +$var supply0 1 r@ VGND $end +$var supply1 1 s@ VPB $end +$var supply0 1 t@ VNB $end + +$scope module base $end +$var wire 1 b! Q $end +$var wire 1 Y! CLK $end +$var wire 1 a! D $end +$var wire 1 ( RESET_B $end +$var wire 1 u@ buf_Q $end +$var wire 1 v@ RESET $end +$upscope $end +$upscope $end + +$scope module FTB_49__48 $end +$var wire 1 J" X $end +$var wire 1 b! A $end +$var supply1 1 w@ VPWR $end +$var supply0 1 x@ VGND $end +$var supply1 1 y@ VPB $end +$var supply0 1 z@ VNB $end + +$scope module base $end +$var wire 1 J" X $end +$var wire 1 b! A $end +$var wire 1 {@ buf0_out_X $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mem_bottom_track_51 $end +$var wire 1 ( pReset [0] $end +$var wire 1 Y! prog_clk [0] $end +$var wire 1 J" ccff_head [0] $end +$var wire 1 K" ccff_tail [0] $end +$var wire 1 c! mem_out [0] $end +$var wire 1 d! mem_out [1] $end + +$scope module sky130_fd_sc_hd__dfrtp_1_0_ $end +$var wire 1 c! Q $end +$var wire 1 Y! CLK $end +$var wire 1 J" D $end +$var wire 1 ( RESET_B $end +$var supply1 1 |@ VPWR $end +$var supply0 1 }@ VGND $end +$var supply1 1 ~@ VPB $end +$var supply0 1 !A VNB $end + +$scope module base $end +$var wire 1 c! Q $end +$var wire 1 Y! CLK $end +$var wire 1 J" D $end +$var wire 1 ( RESET_B $end +$var wire 1 "A buf_Q $end +$var wire 1 #A RESET $end +$upscope $end +$upscope $end + +$scope module sky130_fd_sc_hd__dfrtp_1_1_ $end +$var wire 1 d! Q $end +$var wire 1 Y! CLK $end +$var wire 1 c! D $end +$var wire 1 ( RESET_B $end +$var supply1 1 $A VPWR $end +$var supply0 1 %A VGND $end +$var supply1 1 &A VPB $end +$var supply0 1 'A VNB $end + +$scope module base $end +$var wire 1 d! Q $end +$var wire 1 Y! CLK $end +$var wire 1 c! D $end +$var wire 1 ( RESET_B $end +$var wire 1 (A buf_Q $end +$var wire 1 )A RESET $end +$upscope $end +$upscope $end + +$scope module FTB_50__49 $end +$var wire 1 K" X $end +$var wire 1 d! A $end +$var supply1 1 *A VPWR $end +$var supply0 1 +A VGND $end +$var supply1 1 ,A VPB $end +$var supply0 1 -A VNB $end + +$scope module base $end +$var wire 1 K" X $end +$var wire 1 d! A $end +$var wire 1 .A buf0_out_X $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mem_bottom_track_53 $end +$var wire 1 ( pReset [0] $end +$var wire 1 Y! prog_clk [0] $end +$var wire 1 K" ccff_head [0] $end +$var wire 1 L" ccff_tail [0] $end +$var wire 1 e! mem_out [0] $end +$var wire 1 f! mem_out [1] $end + +$scope module sky130_fd_sc_hd__dfrtp_1_0_ $end +$var wire 1 e! Q $end +$var wire 1 Y! CLK $end +$var wire 1 K" D $end +$var wire 1 ( RESET_B $end +$var supply1 1 /A VPWR $end +$var supply0 1 0A VGND $end +$var supply1 1 1A VPB $end +$var supply0 1 2A VNB $end + +$scope module base $end +$var wire 1 e! Q $end +$var wire 1 Y! CLK $end +$var wire 1 K" D $end +$var wire 1 ( RESET_B $end +$var wire 1 3A buf_Q $end +$var wire 1 4A RESET $end +$upscope $end +$upscope $end + +$scope module sky130_fd_sc_hd__dfrtp_1_1_ $end +$var wire 1 f! Q $end +$var wire 1 Y! CLK $end +$var wire 1 e! D $end +$var wire 1 ( RESET_B $end +$var supply1 1 5A VPWR $end +$var supply0 1 6A VGND $end +$var supply1 1 7A VPB $end +$var supply0 1 8A VNB $end + +$scope module base $end +$var wire 1 f! Q $end +$var wire 1 Y! CLK $end +$var wire 1 e! D $end +$var wire 1 ( RESET_B $end +$var wire 1 9A buf_Q $end +$var wire 1 :A RESET $end +$upscope $end +$upscope $end + +$scope module FTB_51__50 $end +$var wire 1 L" X $end +$var wire 1 f! A $end +$var supply1 1 ;A VPWR $end +$var supply0 1 A VNB $end + +$scope module base $end +$var wire 1 L" X $end +$var wire 1 f! A $end +$var wire 1 ?A buf0_out_X $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mem_left_track_13 $end +$var wire 1 ( pReset [0] $end +$var wire 1 Y! prog_clk [0] $end +$var wire 1 K# ccff_head [0] $end +$var wire 1 M" ccff_tail [0] $end +$var wire 1 g! mem_out [0] $end +$var wire 1 h! mem_out [1] $end + +$scope module sky130_fd_sc_hd__dfrtp_1_0_ $end +$var wire 1 g! Q $end +$var wire 1 Y! CLK $end +$var wire 1 K# D $end +$var wire 1 ( RESET_B $end +$var supply1 1 @A VPWR $end +$var supply0 1 AA VGND $end +$var supply1 1 BA VPB $end +$var supply0 1 CA VNB $end + +$scope module base $end +$var wire 1 g! Q $end +$var wire 1 Y! CLK $end +$var wire 1 K# D $end +$var wire 1 ( RESET_B $end +$var wire 1 DA buf_Q $end +$var wire 1 EA RESET $end +$upscope $end +$upscope $end + +$scope module sky130_fd_sc_hd__dfrtp_1_1_ $end +$var wire 1 h! Q $end +$var wire 1 Y! CLK $end +$var wire 1 g! D $end +$var wire 1 ( RESET_B $end +$var supply1 1 FA VPWR $end +$var supply0 1 GA VGND $end +$var supply1 1 HA VPB $end +$var supply0 1 IA VNB $end + +$scope module base $end +$var wire 1 h! Q $end +$var wire 1 Y! CLK $end +$var wire 1 g! D $end +$var wire 1 ( RESET_B $end +$var wire 1 JA buf_Q $end +$var wire 1 KA RESET $end +$upscope $end +$upscope $end + +$scope module FTB_52__51 $end +$var wire 1 M" X $end +$var wire 1 h! A $end +$var supply1 1 LA VPWR $end +$var supply0 1 MA VGND $end +$var supply1 1 NA VPB $end +$var supply0 1 OA VNB $end + +$scope module base $end +$var wire 1 M" X $end +$var wire 1 h! A $end +$var wire 1 PA buf0_out_X $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mem_left_track_15 $end +$var wire 1 ( pReset [0] $end +$var wire 1 Y! prog_clk [0] $end +$var wire 1 M" ccff_head [0] $end +$var wire 1 N" ccff_tail [0] $end +$var wire 1 i! mem_out [0] $end +$var wire 1 j! mem_out [1] $end + +$scope module sky130_fd_sc_hd__dfrtp_1_0_ $end +$var wire 1 i! Q $end +$var wire 1 Y! CLK $end +$var wire 1 M" D $end +$var wire 1 ( RESET_B $end +$var supply1 1 QA VPWR $end +$var supply0 1 RA VGND $end +$var supply1 1 SA VPB $end +$var supply0 1 TA VNB $end + +$scope module base $end +$var wire 1 i! Q $end +$var wire 1 Y! CLK $end +$var wire 1 M" D $end +$var wire 1 ( RESET_B $end +$var wire 1 UA buf_Q $end +$var wire 1 VA RESET $end +$upscope $end +$upscope $end + +$scope module sky130_fd_sc_hd__dfrtp_1_1_ $end +$var wire 1 j! Q $end +$var wire 1 Y! CLK $end +$var wire 1 i! D $end +$var wire 1 ( RESET_B $end +$var supply1 1 WA VPWR $end +$var supply0 1 XA VGND $end +$var supply1 1 YA VPB $end +$var supply0 1 ZA VNB $end + +$scope module base $end +$var wire 1 j! Q $end +$var wire 1 Y! CLK $end +$var wire 1 i! D $end +$var wire 1 ( RESET_B $end +$var wire 1 [A buf_Q $end +$var wire 1 \A RESET $end +$upscope $end +$upscope $end + +$scope module FTB_53__52 $end +$var wire 1 N" X $end +$var wire 1 j! A $end +$var supply1 1 ]A VPWR $end +$var supply0 1 ^A VGND $end +$var supply1 1 _A VPB $end +$var supply0 1 `A VNB $end + +$scope module base $end +$var wire 1 N" X $end +$var wire 1 j! A $end +$var wire 1 aA buf0_out_X $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mem_left_track_17 $end +$var wire 1 ( pReset [0] $end +$var wire 1 Y! prog_clk [0] $end +$var wire 1 N" ccff_head [0] $end +$var wire 1 O" ccff_tail [0] $end +$var wire 1 k! mem_out [0] $end +$var wire 1 l! mem_out [1] $end + +$scope module sky130_fd_sc_hd__dfrtp_1_0_ $end +$var wire 1 k! Q $end +$var wire 1 Y! CLK $end +$var wire 1 N" D $end +$var wire 1 ( RESET_B $end +$var supply1 1 bA VPWR $end +$var supply0 1 cA VGND $end +$var supply1 1 dA VPB $end +$var supply0 1 eA VNB $end + +$scope module base $end +$var wire 1 k! Q $end +$var wire 1 Y! CLK $end +$var wire 1 N" D $end +$var wire 1 ( RESET_B $end +$var wire 1 fA buf_Q $end +$var wire 1 gA RESET $end +$upscope $end +$upscope $end + +$scope module sky130_fd_sc_hd__dfrtp_1_1_ $end +$var wire 1 l! Q $end +$var wire 1 Y! CLK $end +$var wire 1 k! D $end +$var wire 1 ( RESET_B $end +$var supply1 1 hA VPWR $end +$var supply0 1 iA VGND $end +$var supply1 1 jA VPB $end +$var supply0 1 kA VNB $end + +$scope module base $end +$var wire 1 l! Q $end +$var wire 1 Y! CLK $end +$var wire 1 k! D $end +$var wire 1 ( RESET_B $end +$var wire 1 lA buf_Q $end +$var wire 1 mA RESET $end +$upscope $end +$upscope $end + +$scope module FTB_54__53 $end +$var wire 1 O" X $end +$var wire 1 l! A $end +$var supply1 1 nA VPWR $end +$var supply0 1 oA VGND $end +$var supply1 1 pA VPB $end +$var supply0 1 qA VNB $end + +$scope module base $end +$var wire 1 O" X $end +$var wire 1 l! A $end +$var wire 1 rA buf0_out_X $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mem_left_track_19 $end +$var wire 1 ( pReset [0] $end +$var wire 1 Y! prog_clk [0] $end +$var wire 1 O" ccff_head [0] $end +$var wire 1 P" ccff_tail [0] $end +$var wire 1 m! mem_out [0] $end +$var wire 1 n! mem_out [1] $end + +$scope module sky130_fd_sc_hd__dfrtp_1_0_ $end +$var wire 1 m! Q $end +$var wire 1 Y! CLK $end +$var wire 1 O" D $end +$var wire 1 ( RESET_B $end +$var supply1 1 sA VPWR $end +$var supply0 1 tA VGND $end +$var supply1 1 uA VPB $end +$var supply0 1 vA VNB $end + +$scope module base $end +$var wire 1 m! Q $end +$var wire 1 Y! CLK $end +$var wire 1 O" D $end +$var wire 1 ( RESET_B $end +$var wire 1 wA buf_Q $end +$var wire 1 xA RESET $end +$upscope $end +$upscope $end + +$scope module sky130_fd_sc_hd__dfrtp_1_1_ $end +$var wire 1 n! Q $end +$var wire 1 Y! CLK $end +$var wire 1 m! D $end +$var wire 1 ( RESET_B $end +$var supply1 1 yA VPWR $end +$var supply0 1 zA VGND $end +$var supply1 1 {A VPB $end +$var supply0 1 |A VNB $end + +$scope module base $end +$var wire 1 n! Q $end +$var wire 1 Y! CLK $end +$var wire 1 m! D $end +$var wire 1 ( RESET_B $end +$var wire 1 }A buf_Q $end +$var wire 1 ~A RESET $end +$upscope $end +$upscope $end + +$scope module FTB_55__54 $end +$var wire 1 P" X $end +$var wire 1 n! A $end +$var supply1 1 !B VPWR $end +$var supply0 1 "B VGND $end +$var supply1 1 #B VPB $end +$var supply0 1 $B VNB $end + +$scope module base $end +$var wire 1 P" X $end +$var wire 1 n! A $end +$var wire 1 %B buf0_out_X $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mem_left_track_21 $end +$var wire 1 ( pReset [0] $end +$var wire 1 Y! prog_clk [0] $end +$var wire 1 P" ccff_head [0] $end +$var wire 1 Q" ccff_tail [0] $end +$var wire 1 o! mem_out [0] $end +$var wire 1 p! mem_out [1] $end + +$scope module sky130_fd_sc_hd__dfrtp_1_0_ $end +$var wire 1 o! Q $end +$var wire 1 Y! CLK $end +$var wire 1 P" D $end +$var wire 1 ( RESET_B $end +$var supply1 1 &B VPWR $end +$var supply0 1 'B VGND $end +$var supply1 1 (B VPB $end +$var supply0 1 )B VNB $end + +$scope module base $end +$var wire 1 o! Q $end +$var wire 1 Y! CLK $end +$var wire 1 P" D $end +$var wire 1 ( RESET_B $end +$var wire 1 *B buf_Q $end +$var wire 1 +B RESET $end +$upscope $end +$upscope $end + +$scope module sky130_fd_sc_hd__dfrtp_1_1_ $end +$var wire 1 p! Q $end +$var wire 1 Y! CLK $end +$var wire 1 o! D $end +$var wire 1 ( RESET_B $end +$var supply1 1 ,B VPWR $end +$var supply0 1 -B VGND $end +$var supply1 1 .B VPB $end +$var supply0 1 /B VNB $end + +$scope module base $end +$var wire 1 p! Q $end +$var wire 1 Y! CLK $end +$var wire 1 o! D $end +$var wire 1 ( RESET_B $end +$var wire 1 0B buf_Q $end +$var wire 1 1B RESET $end +$upscope $end +$upscope $end + +$scope module FTB_56__55 $end +$var wire 1 Q" X $end +$var wire 1 p! A $end +$var supply1 1 2B VPWR $end +$var supply0 1 3B VGND $end +$var supply1 1 4B VPB $end +$var supply0 1 5B VNB $end + +$scope module base $end +$var wire 1 Q" X $end +$var wire 1 p! A $end +$var wire 1 6B buf0_out_X $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mem_left_track_23 $end +$var wire 1 ( pReset [0] $end +$var wire 1 Y! prog_clk [0] $end +$var wire 1 Q" ccff_head [0] $end +$var wire 1 S" ccff_tail [0] $end +$var wire 1 s! mem_out [0] $end +$var wire 1 t! mem_out [1] $end + +$scope module sky130_fd_sc_hd__dfrtp_1_0_ $end +$var wire 1 s! Q $end +$var wire 1 Y! CLK $end +$var wire 1 Q" D $end +$var wire 1 ( RESET_B $end +$var supply1 1 7B VPWR $end +$var supply0 1 8B VGND $end +$var supply1 1 9B VPB $end +$var supply0 1 :B VNB $end + +$scope module base $end +$var wire 1 s! Q $end +$var wire 1 Y! CLK $end +$var wire 1 Q" D $end +$var wire 1 ( RESET_B $end +$var wire 1 ;B buf_Q $end +$var wire 1 B VGND $end +$var supply1 1 ?B VPB $end +$var supply0 1 @B VNB $end + +$scope module base $end +$var wire 1 t! Q $end +$var wire 1 Y! CLK $end +$var wire 1 s! D $end +$var wire 1 ( RESET_B $end +$var wire 1 AB buf_Q $end +$var wire 1 BB RESET $end +$upscope $end +$upscope $end + +$scope module FTB_57__56 $end +$var wire 1 S" X $end +$var wire 1 t! A $end +$var supply1 1 CB VPWR $end +$var supply0 1 DB VGND $end +$var supply1 1 EB VPB $end +$var supply0 1 FB VNB $end + +$scope module base $end +$var wire 1 S" X $end +$var wire 1 t! A $end +$var wire 1 GB buf0_out_X $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mem_left_track_25 $end +$var wire 1 ( pReset [0] $end +$var wire 1 Y! prog_clk [0] $end +$var wire 1 S" ccff_head [0] $end +$var wire 1 T" ccff_tail [0] $end +$var wire 1 u! mem_out [0] $end +$var wire 1 v! mem_out [1] $end + +$scope module sky130_fd_sc_hd__dfrtp_1_0_ $end +$var wire 1 u! Q $end +$var wire 1 Y! CLK $end +$var wire 1 S" D $end +$var wire 1 ( RESET_B $end +$var supply1 1 HB VPWR $end +$var supply0 1 IB VGND $end +$var supply1 1 JB VPB $end +$var supply0 1 KB VNB $end + +$scope module base $end +$var wire 1 u! Q $end +$var wire 1 Y! CLK $end +$var wire 1 S" D $end +$var wire 1 ( RESET_B $end +$var wire 1 LB buf_Q $end +$var wire 1 MB RESET $end +$upscope $end +$upscope $end + +$scope module sky130_fd_sc_hd__dfrtp_1_1_ $end +$var wire 1 v! Q $end +$var wire 1 Y! CLK $end +$var wire 1 u! D $end +$var wire 1 ( RESET_B $end +$var supply1 1 NB VPWR $end +$var supply0 1 OB VGND $end +$var supply1 1 PB VPB $end +$var supply0 1 QB VNB $end + +$scope module base $end +$var wire 1 v! Q $end +$var wire 1 Y! CLK $end +$var wire 1 u! D $end +$var wire 1 ( RESET_B $end +$var wire 1 RB buf_Q $end +$var wire 1 SB RESET $end +$upscope $end +$upscope $end + +$scope module FTB_58__57 $end +$var wire 1 T" X $end +$var wire 1 v! A $end +$var supply1 1 TB VPWR $end +$var supply0 1 UB VGND $end +$var supply1 1 VB VPB $end +$var supply0 1 WB VNB $end + +$scope module base $end +$var wire 1 T" X $end +$var wire 1 v! A $end +$var wire 1 XB buf0_out_X $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mem_left_track_27 $end +$var wire 1 ( pReset [0] $end +$var wire 1 Y! prog_clk [0] $end +$var wire 1 T" ccff_head [0] $end +$var wire 1 U" ccff_tail [0] $end +$var wire 1 w! mem_out [0] $end +$var wire 1 x! mem_out [1] $end + +$scope module sky130_fd_sc_hd__dfrtp_1_0_ $end +$var wire 1 w! Q $end +$var wire 1 Y! CLK $end +$var wire 1 T" D $end +$var wire 1 ( RESET_B $end +$var supply1 1 YB VPWR $end +$var supply0 1 ZB VGND $end +$var supply1 1 [B VPB $end +$var supply0 1 \B VNB $end + +$scope module base $end +$var wire 1 w! Q $end +$var wire 1 Y! CLK $end +$var wire 1 T" D $end +$var wire 1 ( RESET_B $end +$var wire 1 ]B buf_Q $end +$var wire 1 ^B RESET $end +$upscope $end +$upscope $end + +$scope module sky130_fd_sc_hd__dfrtp_1_1_ $end +$var wire 1 x! Q $end +$var wire 1 Y! CLK $end +$var wire 1 w! D $end +$var wire 1 ( RESET_B $end +$var supply1 1 _B VPWR $end +$var supply0 1 `B VGND $end +$var supply1 1 aB VPB $end +$var supply0 1 bB VNB $end + +$scope module base $end +$var wire 1 x! Q $end +$var wire 1 Y! CLK $end +$var wire 1 w! D $end +$var wire 1 ( RESET_B $end +$var wire 1 cB buf_Q $end +$var wire 1 dB RESET $end +$upscope $end +$upscope $end + +$scope module FTB_59__58 $end +$var wire 1 U" X $end +$var wire 1 x! A $end +$var supply1 1 eB VPWR $end +$var supply0 1 fB VGND $end +$var supply1 1 gB VPB $end +$var supply0 1 hB VNB $end + +$scope module base $end +$var wire 1 U" X $end +$var wire 1 x! A $end +$var wire 1 iB buf0_out_X $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mem_left_track_31 $end +$var wire 1 ( pReset [0] $end +$var wire 1 Y! prog_clk [0] $end +$var wire 1 u" ccff_head [0] $end +$var wire 1 V" ccff_tail [0] $end +$var wire 1 y! mem_out [0] $end +$var wire 1 z! mem_out [1] $end + +$scope module sky130_fd_sc_hd__dfrtp_1_0_ $end +$var wire 1 y! Q $end +$var wire 1 Y! CLK $end +$var wire 1 u" D $end +$var wire 1 ( RESET_B $end +$var supply1 1 jB VPWR $end +$var supply0 1 kB VGND $end +$var supply1 1 lB VPB $end +$var supply0 1 mB VNB $end + +$scope module base $end +$var wire 1 y! Q $end +$var wire 1 Y! CLK $end +$var wire 1 u" D $end +$var wire 1 ( RESET_B $end +$var wire 1 nB buf_Q $end +$var wire 1 oB RESET $end +$upscope $end +$upscope $end + +$scope module sky130_fd_sc_hd__dfrtp_1_1_ $end +$var wire 1 z! Q $end +$var wire 1 Y! CLK $end +$var wire 1 y! D $end +$var wire 1 ( RESET_B $end +$var supply1 1 pB VPWR $end +$var supply0 1 qB VGND $end +$var supply1 1 rB VPB $end +$var supply0 1 sB VNB $end + +$scope module base $end +$var wire 1 z! Q $end +$var wire 1 Y! CLK $end +$var wire 1 y! D $end +$var wire 1 ( RESET_B $end +$var wire 1 tB buf_Q $end +$var wire 1 uB RESET $end +$upscope $end +$upscope $end + +$scope module FTB_60__59 $end +$var wire 1 V" X $end +$var wire 1 z! A $end +$var supply1 1 vB VPWR $end +$var supply0 1 wB VGND $end +$var supply1 1 xB VPB $end +$var supply0 1 yB VNB $end + +$scope module base $end +$var wire 1 V" X $end +$var wire 1 z! A $end +$var wire 1 zB buf0_out_X $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mem_left_track_33 $end +$var wire 1 ( pReset [0] $end +$var wire 1 Y! prog_clk [0] $end +$var wire 1 V" ccff_head [0] $end +$var wire 1 W" ccff_tail [0] $end +$var wire 1 {! mem_out [0] $end +$var wire 1 |! mem_out [1] $end + +$scope module sky130_fd_sc_hd__dfrtp_1_0_ $end +$var wire 1 {! Q $end +$var wire 1 Y! CLK $end +$var wire 1 V" D $end +$var wire 1 ( RESET_B $end +$var supply1 1 {B VPWR $end +$var supply0 1 |B VGND $end +$var supply1 1 }B VPB $end +$var supply0 1 ~B VNB $end + +$scope module base $end +$var wire 1 {! Q $end +$var wire 1 Y! CLK $end +$var wire 1 V" D $end +$var wire 1 ( RESET_B $end +$var wire 1 !C buf_Q $end +$var wire 1 "C RESET $end +$upscope $end +$upscope $end + +$scope module sky130_fd_sc_hd__dfrtp_1_1_ $end +$var wire 1 |! Q $end +$var wire 1 Y! CLK $end +$var wire 1 {! D $end +$var wire 1 ( RESET_B $end +$var supply1 1 #C VPWR $end +$var supply0 1 $C VGND $end +$var supply1 1 %C VPB $end +$var supply0 1 &C VNB $end + +$scope module base $end +$var wire 1 |! Q $end +$var wire 1 Y! CLK $end +$var wire 1 {! D $end +$var wire 1 ( RESET_B $end +$var wire 1 'C buf_Q $end +$var wire 1 (C RESET $end +$upscope $end +$upscope $end + +$scope module FTB_61__60 $end +$var wire 1 W" X $end +$var wire 1 |! A $end +$var supply1 1 )C VPWR $end +$var supply0 1 *C VGND $end +$var supply1 1 +C VPB $end +$var supply0 1 ,C VNB $end + +$scope module base $end +$var wire 1 W" X $end +$var wire 1 |! A $end +$var wire 1 -C buf0_out_X $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mem_left_track_35 $end +$var wire 1 ( pReset [0] $end +$var wire 1 Y! prog_clk [0] $end +$var wire 1 W" ccff_head [0] $end +$var wire 1 X" ccff_tail [0] $end +$var wire 1 }! mem_out [0] $end +$var wire 1 ~! mem_out [1] $end + +$scope module sky130_fd_sc_hd__dfrtp_1_0_ $end +$var wire 1 }! Q $end +$var wire 1 Y! CLK $end +$var wire 1 W" D $end +$var wire 1 ( RESET_B $end +$var supply1 1 .C VPWR $end +$var supply0 1 /C VGND $end +$var supply1 1 0C VPB $end +$var supply0 1 1C VNB $end + +$scope module base $end +$var wire 1 }! Q $end +$var wire 1 Y! CLK $end +$var wire 1 W" D $end +$var wire 1 ( RESET_B $end +$var wire 1 2C buf_Q $end +$var wire 1 3C RESET $end +$upscope $end +$upscope $end + +$scope module sky130_fd_sc_hd__dfrtp_1_1_ $end +$var wire 1 ~! Q $end +$var wire 1 Y! CLK $end +$var wire 1 }! D $end +$var wire 1 ( RESET_B $end +$var supply1 1 4C VPWR $end +$var supply0 1 5C VGND $end +$var supply1 1 6C VPB $end +$var supply0 1 7C VNB $end + +$scope module base $end +$var wire 1 ~! Q $end +$var wire 1 Y! CLK $end +$var wire 1 }! D $end +$var wire 1 ( RESET_B $end +$var wire 1 8C buf_Q $end +$var wire 1 9C RESET $end +$upscope $end +$upscope $end + +$scope module FTB_62__61 $end +$var wire 1 X" X $end +$var wire 1 ~! A $end +$var supply1 1 :C VPWR $end +$var supply0 1 ;C VGND $end +$var supply1 1 C buf0_out_X $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mem_left_track_37 $end +$var wire 1 ( pReset [0] $end +$var wire 1 Y! prog_clk [0] $end +$var wire 1 X" ccff_head [0] $end +$var wire 1 Y" ccff_tail [0] $end +$var wire 1 !" mem_out [0] $end +$var wire 1 "" mem_out [1] $end + +$scope module sky130_fd_sc_hd__dfrtp_1_0_ $end +$var wire 1 !" Q $end +$var wire 1 Y! CLK $end +$var wire 1 X" D $end +$var wire 1 ( RESET_B $end +$var supply1 1 ?C VPWR $end +$var supply0 1 @C VGND $end +$var supply1 1 AC VPB $end +$var supply0 1 BC VNB $end + +$scope module base $end +$var wire 1 !" Q $end +$var wire 1 Y! CLK $end +$var wire 1 X" D $end +$var wire 1 ( RESET_B $end +$var wire 1 CC buf_Q $end +$var wire 1 DC RESET $end +$upscope $end +$upscope $end + +$scope module sky130_fd_sc_hd__dfrtp_1_1_ $end +$var wire 1 "" Q $end +$var wire 1 Y! CLK $end +$var wire 1 !" D $end +$var wire 1 ( RESET_B $end +$var supply1 1 EC VPWR $end +$var supply0 1 FC VGND $end +$var supply1 1 GC VPB $end +$var supply0 1 HC VNB $end + +$scope module base $end +$var wire 1 "" Q $end +$var wire 1 Y! CLK $end +$var wire 1 !" D $end +$var wire 1 ( RESET_B $end +$var wire 1 IC buf_Q $end +$var wire 1 JC RESET $end +$upscope $end +$upscope $end + +$scope module FTB_63__62 $end +$var wire 1 Y" X $end +$var wire 1 "" A $end +$var supply1 1 KC VPWR $end +$var supply0 1 LC VGND $end +$var supply1 1 MC VPB $end +$var supply0 1 NC VNB $end + +$scope module base $end +$var wire 1 Y" X $end +$var wire 1 "" A $end +$var wire 1 OC buf0_out_X $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mem_left_track_39 $end +$var wire 1 ( pReset [0] $end +$var wire 1 Y! prog_clk [0] $end +$var wire 1 Y" ccff_head [0] $end +$var wire 1 Z" ccff_tail [0] $end +$var wire 1 #" mem_out [0] $end +$var wire 1 $" mem_out [1] $end + +$scope module sky130_fd_sc_hd__dfrtp_1_0_ $end +$var wire 1 #" Q $end +$var wire 1 Y! CLK $end +$var wire 1 Y" D $end +$var wire 1 ( RESET_B $end +$var supply1 1 PC VPWR $end +$var supply0 1 QC VGND $end +$var supply1 1 RC VPB $end +$var supply0 1 SC VNB $end + +$scope module base $end +$var wire 1 #" Q $end +$var wire 1 Y! CLK $end +$var wire 1 Y" D $end +$var wire 1 ( RESET_B $end +$var wire 1 TC buf_Q $end +$var wire 1 UC RESET $end +$upscope $end +$upscope $end + +$scope module sky130_fd_sc_hd__dfrtp_1_1_ $end +$var wire 1 $" Q $end +$var wire 1 Y! CLK $end +$var wire 1 #" D $end +$var wire 1 ( RESET_B $end +$var supply1 1 VC VPWR $end +$var supply0 1 WC VGND $end +$var supply1 1 XC VPB $end +$var supply0 1 YC VNB $end + +$scope module base $end +$var wire 1 $" Q $end +$var wire 1 Y! CLK $end +$var wire 1 #" D $end +$var wire 1 ( RESET_B $end +$var wire 1 ZC buf_Q $end +$var wire 1 [C RESET $end +$upscope $end +$upscope $end + +$scope module FTB_64__63 $end +$var wire 1 Z" X $end +$var wire 1 $" A $end +$var supply1 1 \C VPWR $end +$var supply0 1 ]C VGND $end +$var supply1 1 ^C VPB $end +$var supply0 1 _C VNB $end + +$scope module base $end +$var wire 1 Z" X $end +$var wire 1 $" A $end +$var wire 1 `C buf0_out_X $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mem_left_track_41 $end +$var wire 1 ( pReset [0] $end +$var wire 1 Y! prog_clk [0] $end +$var wire 1 Z" ccff_head [0] $end +$var wire 1 [" ccff_tail [0] $end +$var wire 1 %" mem_out [0] $end +$var wire 1 &" mem_out [1] $end + +$scope module sky130_fd_sc_hd__dfrtp_1_0_ $end +$var wire 1 %" Q $end +$var wire 1 Y! CLK $end +$var wire 1 Z" D $end +$var wire 1 ( RESET_B $end +$var supply1 1 aC VPWR $end +$var supply0 1 bC VGND $end +$var supply1 1 cC VPB $end +$var supply0 1 dC VNB $end + +$scope module base $end +$var wire 1 %" Q $end +$var wire 1 Y! CLK $end +$var wire 1 Z" D $end +$var wire 1 ( RESET_B $end +$var wire 1 eC buf_Q $end +$var wire 1 fC RESET $end +$upscope $end +$upscope $end + +$scope module sky130_fd_sc_hd__dfrtp_1_1_ $end +$var wire 1 &" Q $end +$var wire 1 Y! CLK $end +$var wire 1 %" D $end +$var wire 1 ( RESET_B $end +$var supply1 1 gC VPWR $end +$var supply0 1 hC VGND $end +$var supply1 1 iC VPB $end +$var supply0 1 jC VNB $end + +$scope module base $end +$var wire 1 &" Q $end +$var wire 1 Y! CLK $end +$var wire 1 %" D $end +$var wire 1 ( RESET_B $end +$var wire 1 kC buf_Q $end +$var wire 1 lC RESET $end +$upscope $end +$upscope $end + +$scope module FTB_65__64 $end +$var wire 1 [" X $end +$var wire 1 &" A $end +$var supply1 1 mC VPWR $end +$var supply0 1 nC VGND $end +$var supply1 1 oC VPB $end +$var supply0 1 pC VNB $end + +$scope module base $end +$var wire 1 [" X $end +$var wire 1 &" A $end +$var wire 1 qC buf0_out_X $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mem_left_track_43 $end +$var wire 1 ( pReset [0] $end +$var wire 1 Y! prog_clk [0] $end +$var wire 1 [" ccff_head [0] $end +$var wire 1 \" ccff_tail [0] $end +$var wire 1 '" mem_out [0] $end +$var wire 1 (" mem_out [1] $end + +$scope module sky130_fd_sc_hd__dfrtp_1_0_ $end +$var wire 1 '" Q $end +$var wire 1 Y! CLK $end +$var wire 1 [" D $end +$var wire 1 ( RESET_B $end +$var supply1 1 rC VPWR $end +$var supply0 1 sC VGND $end +$var supply1 1 tC VPB $end +$var supply0 1 uC VNB $end + +$scope module base $end +$var wire 1 '" Q $end +$var wire 1 Y! CLK $end +$var wire 1 [" D $end +$var wire 1 ( RESET_B $end +$var wire 1 vC buf_Q $end +$var wire 1 wC RESET $end +$upscope $end +$upscope $end + +$scope module sky130_fd_sc_hd__dfrtp_1_1_ $end +$var wire 1 (" Q $end +$var wire 1 Y! CLK $end +$var wire 1 '" D $end +$var wire 1 ( RESET_B $end +$var supply1 1 xC VPWR $end +$var supply0 1 yC VGND $end +$var supply1 1 zC VPB $end +$var supply0 1 {C VNB $end + +$scope module base $end +$var wire 1 (" Q $end +$var wire 1 Y! CLK $end +$var wire 1 '" D $end +$var wire 1 ( RESET_B $end +$var wire 1 |C buf_Q $end +$var wire 1 }C RESET $end +$upscope $end +$upscope $end + +$scope module FTB_66__65 $end +$var wire 1 \" X $end +$var wire 1 (" A $end +$var supply1 1 ~C VPWR $end +$var supply0 1 !D VGND $end +$var supply1 1 "D VPB $end +$var supply0 1 #D VNB $end + +$scope module base $end +$var wire 1 \" X $end +$var wire 1 (" A $end +$var wire 1 $D buf0_out_X $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mem_left_track_45 $end +$var wire 1 ( pReset [0] $end +$var wire 1 Y! prog_clk [0] $end +$var wire 1 \" ccff_head [0] $end +$var wire 1 ^" ccff_tail [0] $end +$var wire 1 +" mem_out [0] $end +$var wire 1 ," mem_out [1] $end + +$scope module sky130_fd_sc_hd__dfrtp_1_0_ $end +$var wire 1 +" Q $end +$var wire 1 Y! CLK $end +$var wire 1 \" D $end +$var wire 1 ( RESET_B $end +$var supply1 1 %D VPWR $end +$var supply0 1 &D VGND $end +$var supply1 1 'D VPB $end +$var supply0 1 (D VNB $end + +$scope module base $end +$var wire 1 +" Q $end +$var wire 1 Y! CLK $end +$var wire 1 \" D $end +$var wire 1 ( RESET_B $end +$var wire 1 )D buf_Q $end +$var wire 1 *D RESET $end +$upscope $end +$upscope $end + +$scope module sky130_fd_sc_hd__dfrtp_1_1_ $end +$var wire 1 ," Q $end +$var wire 1 Y! CLK $end +$var wire 1 +" D $end +$var wire 1 ( RESET_B $end +$var supply1 1 +D VPWR $end +$var supply0 1 ,D VGND $end +$var supply1 1 -D VPB $end +$var supply0 1 .D VNB $end + +$scope module base $end +$var wire 1 ," Q $end +$var wire 1 Y! CLK $end +$var wire 1 +" D $end +$var wire 1 ( RESET_B $end +$var wire 1 /D buf_Q $end +$var wire 1 0D RESET $end +$upscope $end +$upscope $end + +$scope module FTB_67__66 $end +$var wire 1 ^" X $end +$var wire 1 ," A $end +$var supply1 1 1D VPWR $end +$var supply0 1 2D VGND $end +$var supply1 1 3D VPB $end +$var supply0 1 4D VNB $end + +$scope module base $end +$var wire 1 ^" X $end +$var wire 1 ," A $end +$var wire 1 5D buf0_out_X $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mem_left_track_47 $end +$var wire 1 ( pReset [0] $end +$var wire 1 Y! prog_clk [0] $end +$var wire 1 ^" ccff_head [0] $end +$var wire 1 _" ccff_tail [0] $end +$var wire 1 -" mem_out [0] $end +$var wire 1 ." mem_out [1] $end + +$scope module sky130_fd_sc_hd__dfrtp_1_0_ $end +$var wire 1 -" Q $end +$var wire 1 Y! CLK $end +$var wire 1 ^" D $end +$var wire 1 ( RESET_B $end +$var supply1 1 6D VPWR $end +$var supply0 1 7D VGND $end +$var supply1 1 8D VPB $end +$var supply0 1 9D VNB $end + +$scope module base $end +$var wire 1 -" Q $end +$var wire 1 Y! CLK $end +$var wire 1 ^" D $end +$var wire 1 ( RESET_B $end +$var wire 1 :D buf_Q $end +$var wire 1 ;D RESET $end +$upscope $end +$upscope $end + +$scope module sky130_fd_sc_hd__dfrtp_1_1_ $end +$var wire 1 ." Q $end +$var wire 1 Y! CLK $end +$var wire 1 -" D $end +$var wire 1 ( RESET_B $end +$var supply1 1 D VPB $end +$var supply0 1 ?D VNB $end + +$scope module base $end +$var wire 1 ." Q $end +$var wire 1 Y! CLK $end +$var wire 1 -" D $end +$var wire 1 ( RESET_B $end +$var wire 1 @D buf_Q $end +$var wire 1 AD RESET $end +$upscope $end +$upscope $end + +$scope module FTB_68__67 $end +$var wire 1 _" X $end +$var wire 1 ." A $end +$var supply1 1 BD VPWR $end +$var supply0 1 CD VGND $end +$var supply1 1 DD VPB $end +$var supply0 1 ED VNB $end + +$scope module base $end +$var wire 1 _" X $end +$var wire 1 ." A $end +$var wire 1 FD buf0_out_X $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mem_left_track_49 $end +$var wire 1 ( pReset [0] $end +$var wire 1 Y! prog_clk [0] $end +$var wire 1 _" ccff_head [0] $end +$var wire 1 `" ccff_tail [0] $end +$var wire 1 /" mem_out [0] $end +$var wire 1 0" mem_out [1] $end + +$scope module sky130_fd_sc_hd__dfrtp_1_0_ $end +$var wire 1 /" Q $end +$var wire 1 Y! CLK $end +$var wire 1 _" D $end +$var wire 1 ( RESET_B $end +$var supply1 1 GD VPWR $end +$var supply0 1 HD VGND $end +$var supply1 1 ID VPB $end +$var supply0 1 JD VNB $end + +$scope module base $end +$var wire 1 /" Q $end +$var wire 1 Y! CLK $end +$var wire 1 _" D $end +$var wire 1 ( RESET_B $end +$var wire 1 KD buf_Q $end +$var wire 1 LD RESET $end +$upscope $end +$upscope $end + +$scope module sky130_fd_sc_hd__dfrtp_1_1_ $end +$var wire 1 0" Q $end +$var wire 1 Y! CLK $end +$var wire 1 /" D $end +$var wire 1 ( RESET_B $end +$var supply1 1 MD VPWR $end +$var supply0 1 ND VGND $end +$var supply1 1 OD VPB $end +$var supply0 1 PD VNB $end + +$scope module base $end +$var wire 1 0" Q $end +$var wire 1 Y! CLK $end +$var wire 1 /" D $end +$var wire 1 ( RESET_B $end +$var wire 1 QD buf_Q $end +$var wire 1 RD RESET $end +$upscope $end +$upscope $end + +$scope module FTB_69__68 $end +$var wire 1 `" X $end +$var wire 1 0" A $end +$var supply1 1 SD VPWR $end +$var supply0 1 TD VGND $end +$var supply1 1 UD VPB $end +$var supply0 1 VD VNB $end + +$scope module base $end +$var wire 1 `" X $end +$var wire 1 0" A $end +$var wire 1 WD buf0_out_X $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mem_left_track_51 $end +$var wire 1 ( pReset [0] $end +$var wire 1 Y! prog_clk [0] $end +$var wire 1 `" ccff_head [0] $end +$var wire 1 a" ccff_tail [0] $end +$var wire 1 1" mem_out [0] $end +$var wire 1 2" mem_out [1] $end + +$scope module sky130_fd_sc_hd__dfrtp_1_0_ $end +$var wire 1 1" Q $end +$var wire 1 Y! CLK $end +$var wire 1 `" D $end +$var wire 1 ( RESET_B $end +$var supply1 1 XD VPWR $end +$var supply0 1 YD VGND $end +$var supply1 1 ZD VPB $end +$var supply0 1 [D VNB $end + +$scope module base $end +$var wire 1 1" Q $end +$var wire 1 Y! CLK $end +$var wire 1 `" D $end +$var wire 1 ( RESET_B $end +$var wire 1 \D buf_Q $end +$var wire 1 ]D RESET $end +$upscope $end +$upscope $end + +$scope module sky130_fd_sc_hd__dfrtp_1_1_ $end +$var wire 1 2" Q $end +$var wire 1 Y! CLK $end +$var wire 1 1" D $end +$var wire 1 ( RESET_B $end +$var supply1 1 ^D VPWR $end +$var supply0 1 _D VGND $end +$var supply1 1 `D VPB $end +$var supply0 1 aD VNB $end + +$scope module base $end +$var wire 1 2" Q $end +$var wire 1 Y! CLK $end +$var wire 1 1" D $end +$var wire 1 ( RESET_B $end +$var wire 1 bD buf_Q $end +$var wire 1 cD RESET $end +$upscope $end +$upscope $end + +$scope module FTB_70__69 $end +$var wire 1 a" X $end +$var wire 1 2" A $end +$var supply1 1 dD VPWR $end +$var supply0 1 eD VGND $end +$var supply1 1 fD VPB $end +$var supply0 1 gD VNB $end + +$scope module base $end +$var wire 1 a" X $end +$var wire 1 2" A $end +$var wire 1 hD buf0_out_X $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mem_left_track_55 $end +$var wire 1 ( pReset [0] $end +$var wire 1 Y! prog_clk [0] $end +$var wire 1 v" ccff_head [0] $end +$var wire 1 b" ccff_tail [0] $end +$var wire 1 3" mem_out [0] $end +$var wire 1 4" mem_out [1] $end + +$scope module sky130_fd_sc_hd__dfrtp_1_0_ $end +$var wire 1 3" Q $end +$var wire 1 Y! CLK $end +$var wire 1 v" D $end +$var wire 1 ( RESET_B $end +$var supply1 1 iD VPWR $end +$var supply0 1 jD VGND $end +$var supply1 1 kD VPB $end +$var supply0 1 lD VNB $end + +$scope module base $end +$var wire 1 3" Q $end +$var wire 1 Y! CLK $end +$var wire 1 v" D $end +$var wire 1 ( RESET_B $end +$var wire 1 mD buf_Q $end +$var wire 1 nD RESET $end +$upscope $end +$upscope $end + +$scope module sky130_fd_sc_hd__dfrtp_1_1_ $end +$var wire 1 4" Q $end +$var wire 1 Y! CLK $end +$var wire 1 3" D $end +$var wire 1 ( RESET_B $end +$var supply1 1 oD VPWR $end +$var supply0 1 pD VGND $end +$var supply1 1 qD VPB $end +$var supply0 1 rD VNB $end + +$scope module base $end +$var wire 1 4" Q $end +$var wire 1 Y! CLK $end +$var wire 1 3" D $end +$var wire 1 ( RESET_B $end +$var wire 1 sD buf_Q $end +$var wire 1 tD RESET $end +$upscope $end +$upscope $end + +$scope module FTB_71__70 $end +$var wire 1 b" X $end +$var wire 1 4" A $end +$var supply1 1 uD VPWR $end +$var supply0 1 vD VGND $end +$var supply1 1 wD VPB $end +$var supply0 1 xD VNB $end + +$scope module base $end +$var wire 1 b" X $end +$var wire 1 4" A $end +$var wire 1 yD buf0_out_X $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mem_left_track_57 $end +$var wire 1 ( pReset [0] $end +$var wire 1 Y! prog_clk [0] $end +$var wire 1 b" ccff_head [0] $end +$var wire 1 c" ccff_tail [0] $end +$var wire 1 5" mem_out [0] $end +$var wire 1 6" mem_out [1] $end + +$scope module sky130_fd_sc_hd__dfrtp_1_0_ $end +$var wire 1 5" Q $end +$var wire 1 Y! CLK $end +$var wire 1 b" D $end +$var wire 1 ( RESET_B $end +$var supply1 1 zD VPWR $end +$var supply0 1 {D VGND $end +$var supply1 1 |D VPB $end +$var supply0 1 }D VNB $end + +$scope module base $end +$var wire 1 5" Q $end +$var wire 1 Y! CLK $end +$var wire 1 b" D $end +$var wire 1 ( RESET_B $end +$var wire 1 ~D buf_Q $end +$var wire 1 !E RESET $end +$upscope $end +$upscope $end + +$scope module sky130_fd_sc_hd__dfrtp_1_1_ $end +$var wire 1 6" Q $end +$var wire 1 Y! CLK $end +$var wire 1 5" D $end +$var wire 1 ( RESET_B $end +$var supply1 1 "E VPWR $end +$var supply0 1 #E VGND $end +$var supply1 1 $E VPB $end +$var supply0 1 %E VNB $end + +$scope module base $end +$var wire 1 6" Q $end +$var wire 1 Y! CLK $end +$var wire 1 5" D $end +$var wire 1 ( RESET_B $end +$var wire 1 &E buf_Q $end +$var wire 1 'E RESET $end +$upscope $end +$upscope $end + +$scope module FTB_72__71 $end +$var wire 1 c" X $end +$var wire 1 6" A $end +$var supply1 1 (E VPWR $end +$var supply0 1 )E VGND $end +$var supply1 1 *E VPB $end +$var supply0 1 +E VNB $end + +$scope module base $end +$var wire 1 c" X $end +$var wire 1 6" A $end +$var wire 1 ,E buf0_out_X $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mem_left_track_59 $end +$var wire 1 ( pReset [0] $end +$var wire 1 Y! prog_clk [0] $end +$var wire 1 c" ccff_head [0] $end +$var wire 1 & ccff_tail [0] $end +$var wire 1 7" mem_out [0] $end +$var wire 1 8" mem_out [1] $end +$var wire 1 -E copt_net_180 $end +$var wire 1 .E copt_net_182 $end +$var wire 1 /E copt_net_181 $end +$var wire 1 0E copt_net_185 $end +$var wire 1 1E copt_net_184 $end +$var wire 1 2E copt_net_183 $end + +$scope module sky130_fd_sc_hd__dfrtp_1_0_ $end +$var wire 1 7" Q $end +$var wire 1 Y! CLK $end +$var wire 1 c" D $end +$var wire 1 ( RESET_B $end +$var supply1 1 3E VPWR $end +$var supply0 1 4E VGND $end +$var supply1 1 5E VPB $end +$var supply0 1 6E VNB $end + +$scope module base $end +$var wire 1 7" Q $end +$var wire 1 Y! CLK $end +$var wire 1 c" D $end +$var wire 1 ( RESET_B $end +$var wire 1 7E buf_Q $end +$var wire 1 8E RESET $end +$upscope $end +$upscope $end + +$scope module sky130_fd_sc_hd__dfrtp_1_1_ $end +$var wire 1 -E Q $end +$var wire 1 Y! CLK $end +$var wire 1 7" D $end +$var wire 1 ( RESET_B $end +$var supply1 1 9E VPWR $end +$var supply0 1 :E VGND $end +$var supply1 1 ;E VPB $end +$var supply0 1 E RESET $end +$upscope $end +$upscope $end + +$scope module FTB_73__72 $end +$var wire 1 & X $end +$var wire 1 8" A $end +$var supply1 1 ?E VPWR $end +$var supply0 1 @E VGND $end +$var supply1 1 AE VPB $end +$var supply0 1 BE VNB $end + +$scope module base $end +$var wire 1 & X $end +$var wire 1 8" A $end +$var wire 1 CE buf0_out_X $end +$upscope $end +$upscope $end + +$scope module copt_h_inst_1376 $end +$var wire 1 8" X $end +$var wire 1 .E A $end +$var supply1 1 DE VPWR $end +$var supply0 1 EE VGND $end +$var supply1 1 FE VPB $end +$var supply0 1 GE VNB $end + +$scope module base $end +$var wire 1 8" X $end +$var wire 1 .E A $end +$var wire 1 HE buf0_out_X $end +$upscope $end +$upscope $end + +$scope module copt_h_inst_1377 $end +$var wire 1 /E X $end +$var wire 1 -E A $end +$var supply1 1 IE VPWR $end +$var supply0 1 JE VGND $end +$var supply1 1 KE VPB $end +$var supply0 1 LE VNB $end + +$scope module base $end +$var wire 1 /E X $end +$var wire 1 -E A $end +$var wire 1 ME buf0_out_X $end +$upscope $end +$upscope $end + +$scope module copt_h_inst_1378 $end +$var wire 1 .E X $end +$var wire 1 0E A $end +$var supply1 1 NE VPWR $end +$var supply0 1 OE VGND $end +$var supply1 1 PE VPB $end +$var supply0 1 QE VNB $end + +$scope module base $end +$var wire 1 .E X $end +$var wire 1 0E A $end +$var wire 1 RE buf0_out_X $end +$upscope $end +$upscope $end + +$scope module copt_h_inst_1379 $end +$var wire 1 2E X $end +$var wire 1 1E A $end +$var supply1 1 SE VPWR $end +$var supply0 1 TE VGND $end +$var supply1 1 UE VPB $end +$var supply0 1 VE VNB $end + +$scope module base $end +$var wire 1 2E X $end +$var wire 1 1E A $end +$var wire 1 WE buf0_out_X $end +$upscope $end +$upscope $end + +$scope module copt_h_inst_1380 $end +$var wire 1 1E X $end +$var wire 1 /E A $end +$var supply1 1 XE VPWR $end +$var supply0 1 YE VGND $end +$var supply1 1 ZE VPB $end +$var supply0 1 [E VNB $end + +$scope module base $end +$var wire 1 1E X $end +$var wire 1 /E A $end +$var wire 1 \E buf0_out_X $end +$upscope $end +$upscope $end + +$scope module copt_h_inst_1381 $end +$var wire 1 0E X $end +$var wire 1 2E A $end +$var supply1 1 ]E VPWR $end +$var supply0 1 ^E VGND $end +$var supply1 1 _E VPB $end +$var supply0 1 `E VNB $end + +$scope module base $end +$var wire 1 0E X $end +$var wire 1 2E A $end +$var wire 1 aE buf0_out_X $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mux_bottom_track_29 $end +$var wire 1 G in [0] $end +$var wire 1 O in [1] $end +$var wire 1 _ in [2] $end +$var wire 1 k" sram [0] $end +$var wire 1 l" sram [1] $end +$var wire 1 w$ sram_inv [0] $end +$var wire 1 x$ sram_inv [1] $end +$var wire 1 '! out [0] $end +$var wire 1 k# p0 $end +$var wire 1 bE mux_2level_tapbuf_basis_input2_mem1_0_out [0] $end +$var wire 1 cE mux_2level_tapbuf_basis_input2_mem1_1_out [0] $end +$var wire 1 dE mux_2level_tapbuf_basis_input2_mem1_2_out [0] $end +$var wire 1 eE SYNOPSYS_UNCONNECTED_1 $end +$var wire 1 fE SYNOPSYS_UNCONNECTED_2 $end +$var wire 1 gE SYNOPSYS_UNCONNECTED_3 $end +$var wire 1 hE SYNOPSYS_UNCONNECTED_4 $end +$var wire 1 iE BUF_net_171 $end + +$scope module mux_l1_in_0_ $end +$var wire 1 G in [0] $end +$var wire 1 O in [1] $end +$var wire 1 k" mem [0] $end +$var wire 1 eE mem_inv [0] $end +$var wire 1 bE out [0] $end + +$scope module sky130_fd_sc_hd__mux2_1_0 $end +$var wire 1 bE X $end +$var wire 1 O A0 $end +$var wire 1 G A1 $end +$var wire 1 k" S $end +$var supply1 1 jE VPWR $end +$var supply0 1 kE VGND $end +$var supply1 1 lE VPB $end +$var supply0 1 mE VNB $end + +$scope module base $end +$var wire 1 bE X $end +$var wire 1 O A0 $end +$var wire 1 G A1 $end +$var wire 1 k" S $end +$var wire 1 nE mux_2to10_out_X $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mux_l1_in_1_ $end +$var wire 1 _ in [0] $end +$var wire 1 fE in [1] $end +$var wire 1 k" mem [0] $end +$var wire 1 gE mem_inv [0] $end +$var wire 1 cE out [0] $end +$var wire 1 k# p0 $end + +$scope module sky130_fd_sc_hd__mux2_1_0 $end +$var wire 1 cE X $end +$var wire 1 k# A0 $end +$var wire 1 _ A1 $end +$var wire 1 k" S $end +$var supply1 1 oE VPWR $end +$var supply0 1 pE VGND $end +$var supply1 1 qE VPB $end +$var supply0 1 rE VNB $end + +$scope module base $end +$var wire 1 cE X $end +$var wire 1 k# A0 $end +$var wire 1 _ A1 $end +$var wire 1 k" S $end +$var wire 1 sE mux_2to10_out_X $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mux_l2_in_0_ $end +$var wire 1 bE in [0] $end +$var wire 1 cE in [1] $end +$var wire 1 l" mem [0] $end +$var wire 1 hE mem_inv [0] $end +$var wire 1 dE out [0] $end + +$scope module sky130_fd_sc_hd__mux2_1_0 $end +$var wire 1 dE X $end +$var wire 1 cE A0 $end +$var wire 1 bE A1 $end +$var wire 1 l" S $end +$var supply1 1 tE VPWR $end +$var supply0 1 uE VGND $end +$var supply1 1 vE VPB $end +$var supply0 1 wE VNB $end + +$scope module base $end +$var wire 1 dE X $end +$var wire 1 cE A0 $end +$var wire 1 bE A1 $end +$var wire 1 l" S $end +$var wire 1 xE mux_2to10_out_X $end +$upscope $end +$upscope $end +$upscope $end + +$scope module BINV_R_170 $end +$var wire 1 '! Y $end +$var wire 1 iE A $end +$var supply1 1 yE VPWR $end +$var supply0 1 zE VGND $end +$var supply1 1 {E VPB $end +$var supply0 1 |E VNB $end + +$scope module base $end +$var wire 1 '! Y $end +$var wire 1 iE A $end +$var wire 1 }E not0_out_Y $end +$upscope $end +$upscope $end + +$scope module BINV_R_171 $end +$var wire 1 iE Y $end +$var wire 1 dE A $end +$var supply1 1 ~E VPWR $end +$var supply0 1 !F VGND $end +$var supply1 1 "F VPB $end +$var supply0 1 #F VNB $end + +$scope module base $end +$var wire 1 iE Y $end +$var wire 1 dE A $end +$var wire 1 $F not0_out_Y $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mux_bottom_track_45 $end +$var wire 1 G in [0] $end +$var wire 1 K in [1] $end +$var wire 1 g in [2] $end +$var wire 1 m" sram [0] $end +$var wire 1 n" sram [1] $end +$var wire 1 y$ sram_inv [0] $end +$var wire 1 z$ sram_inv [1] $end +$var wire 1 /! out [0] $end +$var wire 1 .$ p0 $end +$var wire 1 %F mux_2level_tapbuf_basis_input2_mem1_0_out [0] $end +$var wire 1 &F mux_2level_tapbuf_basis_input2_mem1_1_out [0] $end +$var wire 1 'F mux_2level_tapbuf_basis_input2_mem1_2_out [0] $end +$var wire 1 (F SYNOPSYS_UNCONNECTED_1 $end +$var wire 1 )F SYNOPSYS_UNCONNECTED_2 $end +$var wire 1 *F SYNOPSYS_UNCONNECTED_3 $end +$var wire 1 +F SYNOPSYS_UNCONNECTED_4 $end + +$scope module sky130_fd_sc_hd__buf_4_0_ $end +$var wire 1 /! X $end +$var wire 1 'F A $end +$var supply1 1 ,F VPWR $end +$var supply0 1 -F VGND $end +$var supply1 1 .F VPB $end +$var supply0 1 /F VNB $end + +$scope module base $end +$var wire 1 /! X $end +$var wire 1 'F A $end +$var wire 1 0F buf0_out_X $end +$upscope $end +$upscope $end + +$scope module mux_l1_in_0_ $end +$var wire 1 G in [0] $end +$var wire 1 K in [1] $end +$var wire 1 m" mem [0] $end +$var wire 1 (F mem_inv [0] $end +$var wire 1 %F out [0] $end + +$scope module sky130_fd_sc_hd__mux2_1_0 $end +$var wire 1 %F X $end +$var wire 1 K A0 $end +$var wire 1 G A1 $end +$var wire 1 m" S $end +$var supply1 1 1F VPWR $end +$var supply0 1 2F VGND $end +$var supply1 1 3F VPB $end +$var supply0 1 4F VNB $end + +$scope module base $end +$var wire 1 %F X $end +$var wire 1 K A0 $end +$var wire 1 G A1 $end +$var wire 1 m" S $end +$var wire 1 5F mux_2to10_out_X $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mux_l1_in_1_ $end +$var wire 1 g in [0] $end +$var wire 1 )F in [1] $end +$var wire 1 m" mem [0] $end +$var wire 1 *F mem_inv [0] $end +$var wire 1 &F out [0] $end +$var wire 1 .$ p0 $end + +$scope module sky130_fd_sc_hd__mux2_1_0 $end +$var wire 1 &F X $end +$var wire 1 .$ A0 $end +$var wire 1 g A1 $end +$var wire 1 m" S $end +$var supply1 1 6F VPWR $end +$var supply0 1 7F VGND $end +$var supply1 1 8F VPB $end +$var supply0 1 9F VNB $end + +$scope module base $end +$var wire 1 &F X $end +$var wire 1 .$ A0 $end +$var wire 1 g A1 $end +$var wire 1 m" S $end +$var wire 1 :F mux_2to10_out_X $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mux_l2_in_0_ $end +$var wire 1 %F in [0] $end +$var wire 1 &F in [1] $end +$var wire 1 n" mem [0] $end +$var wire 1 +F mem_inv [0] $end +$var wire 1 'F out [0] $end + +$scope module sky130_fd_sc_hd__mux2_1_0 $end +$var wire 1 'F X $end +$var wire 1 &F A0 $end +$var wire 1 %F A1 $end +$var wire 1 n" S $end +$var supply1 1 ;F VPWR $end +$var supply0 1 F VNB $end + +$scope module base $end +$var wire 1 'F X $end +$var wire 1 &F A0 $end +$var wire 1 %F A1 $end +$var wire 1 n" S $end +$var wire 1 ?F mux_2to10_out_X $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mux_left_track_29 $end +$var wire 1 6 in [0] $end +$var wire 1 n in [1] $end +$var wire 1 v in [2] $end +$var wire 1 o" sram [0] $end +$var wire 1 p" sram [1] $end +$var wire 1 {$ sram_inv [0] $end +$var wire 1 |$ sram_inv [1] $end +$var wire 1 E! out [0] $end +$var wire 1 L$ p0 $end +$var wire 1 @F mux_2level_tapbuf_basis_input2_mem1_0_out [0] $end +$var wire 1 AF mux_2level_tapbuf_basis_input2_mem1_1_out [0] $end +$var wire 1 BF mux_2level_tapbuf_basis_input2_mem1_2_out [0] $end +$var wire 1 CF SYNOPSYS_UNCONNECTED_1 $end +$var wire 1 DF SYNOPSYS_UNCONNECTED_2 $end +$var wire 1 EF SYNOPSYS_UNCONNECTED_3 $end +$var wire 1 FF SYNOPSYS_UNCONNECTED_4 $end +$var wire 1 GF BUF_net_173 $end + +$scope module mux_l1_in_0_ $end +$var wire 1 6 in [0] $end +$var wire 1 n in [1] $end +$var wire 1 o" mem [0] $end +$var wire 1 CF mem_inv [0] $end +$var wire 1 @F out [0] $end + +$scope module sky130_fd_sc_hd__mux2_1_0 $end +$var wire 1 @F X $end +$var wire 1 n A0 $end +$var wire 1 6 A1 $end +$var wire 1 o" S $end +$var supply1 1 HF VPWR $end +$var supply0 1 IF VGND $end +$var supply1 1 JF VPB $end +$var supply0 1 KF VNB $end + +$scope module base $end +$var wire 1 @F X $end +$var wire 1 n A0 $end +$var wire 1 6 A1 $end +$var wire 1 o" S $end +$var wire 1 LF mux_2to10_out_X $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mux_l1_in_1_ $end +$var wire 1 v in [0] $end +$var wire 1 DF in [1] $end +$var wire 1 o" mem [0] $end +$var wire 1 EF mem_inv [0] $end +$var wire 1 AF out [0] $end +$var wire 1 L$ p0 $end + +$scope module sky130_fd_sc_hd__mux2_1_0 $end +$var wire 1 AF X $end +$var wire 1 L$ A0 $end +$var wire 1 v A1 $end +$var wire 1 o" S $end +$var supply1 1 MF VPWR $end +$var supply0 1 NF VGND $end +$var supply1 1 OF VPB $end +$var supply0 1 PF VNB $end + +$scope module base $end +$var wire 1 AF X $end +$var wire 1 L$ A0 $end +$var wire 1 v A1 $end +$var wire 1 o" S $end +$var wire 1 QF mux_2to10_out_X $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mux_l2_in_0_ $end +$var wire 1 @F in [0] $end +$var wire 1 AF in [1] $end +$var wire 1 p" mem [0] $end +$var wire 1 FF mem_inv [0] $end +$var wire 1 BF out [0] $end + +$scope module sky130_fd_sc_hd__mux2_1_0 $end +$var wire 1 BF X $end +$var wire 1 AF A0 $end +$var wire 1 @F A1 $end +$var wire 1 p" S $end +$var supply1 1 RF VPWR $end +$var supply0 1 SF VGND $end +$var supply1 1 TF VPB $end +$var supply0 1 UF VNB $end + +$scope module base $end +$var wire 1 BF X $end +$var wire 1 AF A0 $end +$var wire 1 @F A1 $end +$var wire 1 p" S $end +$var wire 1 VF mux_2to10_out_X $end +$upscope $end +$upscope $end +$upscope $end + +$scope module BINV_R_172 $end +$var wire 1 E! Y $end +$var wire 1 GF A $end +$var supply1 1 WF VPWR $end +$var supply0 1 XF VGND $end +$var supply1 1 YF VPB $end +$var supply0 1 ZF VNB $end + +$scope module base $end +$var wire 1 E! Y $end +$var wire 1 GF A $end +$var wire 1 [F not0_out_Y $end +$upscope $end +$upscope $end + +$scope module BINV_R_173 $end +$var wire 1 GF Y $end +$var wire 1 BF A $end +$var supply1 1 \F VPWR $end +$var supply0 1 ]F VGND $end +$var supply1 1 ^F VPB $end +$var supply0 1 _F VNB $end + +$scope module base $end +$var wire 1 GF Y $end +$var wire 1 BF A $end +$var wire 1 `F not0_out_Y $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mux_left_track_53 $end +$var wire 1 B in [0] $end +$var wire 1 r in [1] $end +$var wire 1 v in [2] $end +$var wire 1 q" sram [0] $end +$var wire 1 r" sram [1] $end +$var wire 1 }$ sram_inv [0] $end +$var wire 1 ~$ sram_inv [1] $end +$var wire 1 Q! out [0] $end +$var wire 1 L$ p0 $end +$var wire 1 aF mux_2level_tapbuf_basis_input2_mem1_0_out [0] $end +$var wire 1 bF mux_2level_tapbuf_basis_input2_mem1_1_out [0] $end +$var wire 1 cF mux_2level_tapbuf_basis_input2_mem1_2_out [0] $end +$var wire 1 dF SYNOPSYS_UNCONNECTED_1 $end +$var wire 1 eF SYNOPSYS_UNCONNECTED_2 $end +$var wire 1 fF SYNOPSYS_UNCONNECTED_3 $end +$var wire 1 gF SYNOPSYS_UNCONNECTED_4 $end + +$scope module sky130_fd_sc_hd__buf_4_0_ $end +$var wire 1 Q! X $end +$var wire 1 cF A $end +$var supply1 1 hF VPWR $end +$var supply0 1 iF VGND $end +$var supply1 1 jF VPB $end +$var supply0 1 kF VNB $end + +$scope module base $end +$var wire 1 Q! X $end +$var wire 1 cF A $end +$var wire 1 lF buf0_out_X $end +$upscope $end +$upscope $end + +$scope module mux_l1_in_0_ $end +$var wire 1 B in [0] $end +$var wire 1 r in [1] $end +$var wire 1 q" mem [0] $end +$var wire 1 dF mem_inv [0] $end +$var wire 1 aF out [0] $end + +$scope module sky130_fd_sc_hd__mux2_1_0 $end +$var wire 1 aF X $end +$var wire 1 r A0 $end +$var wire 1 B A1 $end +$var wire 1 q" S $end +$var supply1 1 mF VPWR $end +$var supply0 1 nF VGND $end +$var supply1 1 oF VPB $end +$var supply0 1 pF VNB $end + +$scope module base $end +$var wire 1 aF X $end +$var wire 1 r A0 $end +$var wire 1 B A1 $end +$var wire 1 q" S $end +$var wire 1 qF mux_2to10_out_X $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mux_l1_in_1_ $end +$var wire 1 v in [0] $end +$var wire 1 eF in [1] $end +$var wire 1 q" mem [0] $end +$var wire 1 fF mem_inv [0] $end +$var wire 1 bF out [0] $end +$var wire 1 L$ p0 $end + +$scope module sky130_fd_sc_hd__mux2_1_0 $end +$var wire 1 bF X $end +$var wire 1 L$ A0 $end +$var wire 1 v A1 $end +$var wire 1 q" S $end +$var supply1 1 rF VPWR $end +$var supply0 1 sF VGND $end +$var supply1 1 tF VPB $end +$var supply0 1 uF VNB $end + +$scope module base $end +$var wire 1 bF X $end +$var wire 1 L$ A0 $end +$var wire 1 v A1 $end +$var wire 1 q" S $end +$var wire 1 vF mux_2to10_out_X $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mux_l2_in_0_ $end +$var wire 1 aF in [0] $end +$var wire 1 bF in [1] $end +$var wire 1 r" mem [0] $end +$var wire 1 gF mem_inv [0] $end +$var wire 1 cF out [0] $end + +$scope module sky130_fd_sc_hd__mux2_1_0 $end +$var wire 1 cF X $end +$var wire 1 bF A0 $end +$var wire 1 aF A1 $end +$var wire 1 r" S $end +$var supply1 1 wF VPWR $end +$var supply0 1 xF VGND $end +$var supply1 1 yF VPB $end +$var supply0 1 zF VNB $end + +$scope module base $end +$var wire 1 cF X $end +$var wire 1 bF A0 $end +$var wire 1 aF A1 $end +$var wire 1 r" S $end +$var wire 1 {F mux_2to10_out_X $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mem_bottom_track_29 $end +$var wire 1 ( pReset [0] $end +$var wire 1 Y! prog_clk [0] $end +$var wire 1 h" ccff_head [0] $end +$var wire 1 s" ccff_tail [0] $end +$var wire 1 k" mem_out [0] $end +$var wire 1 l" mem_out [1] $end + +$scope module sky130_fd_sc_hd__dfrtp_1_0_ $end +$var wire 1 k" Q $end +$var wire 1 Y! CLK $end +$var wire 1 h" D $end +$var wire 1 ( RESET_B $end +$var supply1 1 |F VPWR $end +$var supply0 1 }F VGND $end +$var supply1 1 ~F VPB $end +$var supply0 1 !G VNB $end + +$scope module base $end +$var wire 1 k" Q $end +$var wire 1 Y! CLK $end +$var wire 1 h" D $end +$var wire 1 ( RESET_B $end +$var wire 1 "G buf_Q $end +$var wire 1 #G RESET $end +$upscope $end +$upscope $end + +$scope module sky130_fd_sc_hd__dfrtp_1_1_ $end +$var wire 1 l" Q $end +$var wire 1 Y! CLK $end +$var wire 1 k" D $end +$var wire 1 ( RESET_B $end +$var supply1 1 $G VPWR $end +$var supply0 1 %G VGND $end +$var supply1 1 &G VPB $end +$var supply0 1 'G VNB $end + +$scope module base $end +$var wire 1 l" Q $end +$var wire 1 Y! CLK $end +$var wire 1 k" D $end +$var wire 1 ( RESET_B $end +$var wire 1 (G buf_Q $end +$var wire 1 )G RESET $end +$upscope $end +$upscope $end + +$scope module FTB_74__73 $end +$var wire 1 s" X $end +$var wire 1 l" A $end +$var supply1 1 *G VPWR $end +$var supply0 1 +G VGND $end +$var supply1 1 ,G VPB $end +$var supply0 1 -G VNB $end + +$scope module base $end +$var wire 1 s" X $end +$var wire 1 l" A $end +$var wire 1 .G buf0_out_X $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mem_bottom_track_45 $end +$var wire 1 ( pReset [0] $end +$var wire 1 Y! prog_clk [0] $end +$var wire 1 H" ccff_head [0] $end +$var wire 1 t" ccff_tail [0] $end +$var wire 1 m" mem_out [0] $end +$var wire 1 n" mem_out [1] $end + +$scope module sky130_fd_sc_hd__dfrtp_1_0_ $end +$var wire 1 m" Q $end +$var wire 1 Y! CLK $end +$var wire 1 H" D $end +$var wire 1 ( RESET_B $end +$var supply1 1 /G VPWR $end +$var supply0 1 0G VGND $end +$var supply1 1 1G VPB $end +$var supply0 1 2G VNB $end + +$scope module base $end +$var wire 1 m" Q $end +$var wire 1 Y! CLK $end +$var wire 1 H" D $end +$var wire 1 ( RESET_B $end +$var wire 1 3G buf_Q $end +$var wire 1 4G RESET $end +$upscope $end +$upscope $end + +$scope module sky130_fd_sc_hd__dfrtp_1_1_ $end +$var wire 1 n" Q $end +$var wire 1 Y! CLK $end +$var wire 1 m" D $end +$var wire 1 ( RESET_B $end +$var supply1 1 5G VPWR $end +$var supply0 1 6G VGND $end +$var supply1 1 7G VPB $end +$var supply0 1 8G VNB $end + +$scope module base $end +$var wire 1 n" Q $end +$var wire 1 Y! CLK $end +$var wire 1 m" D $end +$var wire 1 ( RESET_B $end +$var wire 1 9G buf_Q $end +$var wire 1 :G RESET $end +$upscope $end +$upscope $end + +$scope module FTB_75__74 $end +$var wire 1 t" X $end +$var wire 1 n" A $end +$var supply1 1 ;G VPWR $end +$var supply0 1 G VNB $end + +$scope module base $end +$var wire 1 t" X $end +$var wire 1 n" A $end +$var wire 1 ?G buf0_out_X $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mem_left_track_29 $end +$var wire 1 ( pReset [0] $end +$var wire 1 Y! prog_clk [0] $end +$var wire 1 U" ccff_head [0] $end +$var wire 1 u" ccff_tail [0] $end +$var wire 1 o" mem_out [0] $end +$var wire 1 p" mem_out [1] $end + +$scope module sky130_fd_sc_hd__dfrtp_1_0_ $end +$var wire 1 o" Q $end +$var wire 1 Y! CLK $end +$var wire 1 U" D $end +$var wire 1 ( RESET_B $end +$var supply1 1 @G VPWR $end +$var supply0 1 AG VGND $end +$var supply1 1 BG VPB $end +$var supply0 1 CG VNB $end + +$scope module base $end +$var wire 1 o" Q $end +$var wire 1 Y! CLK $end +$var wire 1 U" D $end +$var wire 1 ( RESET_B $end +$var wire 1 DG buf_Q $end +$var wire 1 EG RESET $end +$upscope $end +$upscope $end + +$scope module sky130_fd_sc_hd__dfrtp_1_1_ $end +$var wire 1 p" Q $end +$var wire 1 Y! CLK $end +$var wire 1 o" D $end +$var wire 1 ( RESET_B $end +$var supply1 1 FG VPWR $end +$var supply0 1 GG VGND $end +$var supply1 1 HG VPB $end +$var supply0 1 IG VNB $end + +$scope module base $end +$var wire 1 p" Q $end +$var wire 1 Y! CLK $end +$var wire 1 o" D $end +$var wire 1 ( RESET_B $end +$var wire 1 JG buf_Q $end +$var wire 1 KG RESET $end +$upscope $end +$upscope $end + +$scope module FTB_76__75 $end +$var wire 1 u" X $end +$var wire 1 p" A $end +$var supply1 1 LG VPWR $end +$var supply0 1 MG VGND $end +$var supply1 1 NG VPB $end +$var supply0 1 OG VNB $end + +$scope module base $end +$var wire 1 u" X $end +$var wire 1 p" A $end +$var wire 1 PG buf0_out_X $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mem_left_track_53 $end +$var wire 1 ( pReset [0] $end +$var wire 1 Y! prog_clk [0] $end +$var wire 1 a" ccff_head [0] $end +$var wire 1 v" ccff_tail [0] $end +$var wire 1 q" mem_out [0] $end +$var wire 1 r" mem_out [1] $end + +$scope module sky130_fd_sc_hd__dfrtp_1_0_ $end +$var wire 1 q" Q $end +$var wire 1 Y! CLK $end +$var wire 1 a" D $end +$var wire 1 ( RESET_B $end +$var supply1 1 QG VPWR $end +$var supply0 1 RG VGND $end +$var supply1 1 SG VPB $end +$var supply0 1 TG VNB $end + +$scope module base $end +$var wire 1 q" Q $end +$var wire 1 Y! CLK $end +$var wire 1 a" D $end +$var wire 1 ( RESET_B $end +$var wire 1 UG buf_Q $end +$var wire 1 VG RESET $end +$upscope $end +$upscope $end + +$scope module sky130_fd_sc_hd__dfrtp_1_1_ $end +$var wire 1 r" Q $end +$var wire 1 Y! CLK $end +$var wire 1 q" D $end +$var wire 1 ( RESET_B $end +$var supply1 1 WG VPWR $end +$var supply0 1 XG VGND $end +$var supply1 1 YG VPB $end +$var supply0 1 ZG VNB $end + +$scope module base $end +$var wire 1 r" Q $end +$var wire 1 Y! CLK $end +$var wire 1 q" D $end +$var wire 1 ( RESET_B $end +$var wire 1 [G buf_Q $end +$var wire 1 \G RESET $end +$upscope $end +$upscope $end + +$scope module FTB_77__76 $end +$var wire 1 v" X $end +$var wire 1 r" A $end +$var supply1 1 ]G VPWR $end +$var supply0 1 ^G VGND $end +$var supply1 1 _G VPB $end +$var supply0 1 `G VNB $end + +$scope module base $end +$var wire 1 v" X $end +$var wire 1 r" A $end +$var wire 1 aG buf0_out_X $end +$upscope $end +$upscope $end +$upscope $end + +$scope module pReset_FTB00 $end +$var wire 1 ( X $end +$var wire 1 W! A $end +$var supply1 1 bG VPWR $end +$var supply0 1 cG VGND $end +$var supply1 1 dG VPB $end +$var supply0 1 eG VNB $end + +$scope module base $end +$var wire 1 ( X $end +$var wire 1 W! A $end +$var wire 1 fG buf0_out_X $end +$upscope $end +$upscope $end + +$scope module prog_clk_0_FTB00 $end +$var wire 1 Y! X $end +$var wire 1 X! A $end +$var supply1 1 gG VPWR $end +$var supply0 1 hG VGND $end +$var supply1 1 iG VPB $end +$var supply0 1 jG VNB $end + +$scope module base $end +$var wire 1 Y! X $end +$var wire 1 X! A $end +$var wire 1 kG buf0_out_X $end +$upscope $end +$upscope $end + +$scope module FTB_78__77 $end +$var wire 1 6! X $end +$var wire 1 P A $end +$var supply1 1 lG VPWR $end +$var supply0 1 mG VGND $end +$var supply1 1 nG VPB $end +$var supply0 1 oG VNB $end + +$scope module base $end +$var wire 1 6! X $end +$var wire 1 P A $end +$var wire 1 pG buf0_out_X $end +$upscope $end +$upscope $end + +$scope module FTB_79__78 $end +$var wire 1 (! X $end +$var wire 1 ` A $end +$var supply1 1 qG VPWR $end +$var supply0 1 rG VGND $end +$var supply1 1 sG VPB $end +$var supply0 1 tG VNB $end + +$scope module base $end +$var wire 1 (! X $end +$var wire 1 ` A $end +$var wire 1 uG buf0_out_X $end +$upscope $end +$upscope $end + +$scope module FTB_80__79 $end +$var wire 1 )! X $end +$var wire 1 a A $end +$var supply1 1 vG VPWR $end +$var supply0 1 wG VGND $end +$var supply1 1 xG VPB $end +$var supply0 1 yG VNB $end + +$scope module base $end +$var wire 1 )! X $end +$var wire 1 a A $end +$var wire 1 zG buf0_out_X $end +$upscope $end +$upscope $end + +$scope module FTB_81__80 $end +$var wire 1 *! X $end +$var wire 1 b A $end +$var supply1 1 {G VPWR $end +$var supply0 1 |G VGND $end +$var supply1 1 }G VPB $end +$var supply0 1 ~G VNB $end + +$scope module base $end +$var wire 1 *! X $end +$var wire 1 b A $end +$var wire 1 !H buf0_out_X $end +$upscope $end +$upscope $end + +$scope module FTB_82__81 $end +$var wire 1 +! X $end +$var wire 1 c A $end +$var supply1 1 "H VPWR $end +$var supply0 1 #H VGND $end +$var supply1 1 $H VPB $end +$var supply0 1 %H VNB $end + +$scope module base $end +$var wire 1 +! X $end +$var wire 1 c A $end +$var wire 1 &H buf0_out_X $end +$upscope $end +$upscope $end + +$scope module FTB_83__82 $end +$var wire 1 4! X $end +$var wire 1 l A $end +$var supply1 1 'H VPWR $end +$var supply0 1 (H VGND $end +$var supply1 1 )H VPB $end +$var supply0 1 *H VNB $end + +$scope module base $end +$var wire 1 4! X $end +$var wire 1 l A $end +$var wire 1 +H buf0_out_X $end +$upscope $end +$upscope $end + +$scope module FTB_84__83 $end +$var wire 1 5! X $end +$var wire 1 m A $end +$var supply1 1 ,H VPWR $end +$var supply0 1 -H VGND $end +$var supply1 1 .H VPB $end +$var supply0 1 /H VNB $end + +$scope module base $end +$var wire 1 5! X $end +$var wire 1 m A $end +$var wire 1 0H buf0_out_X $end +$upscope $end +$upscope $end + +$scope module FTB_85__84 $end +$var wire 1 V! X $end +$var wire 1 U! A $end +$var supply1 1 1H VPWR $end +$var supply0 1 2H VGND $end +$var supply1 1 3H VPB $end +$var supply0 1 4H VNB $end + +$scope module base $end +$var wire 1 V! X $end +$var wire 1 U! A $end +$var wire 1 5H buf0_out_X $end +$upscope $end +$upscope $end + +$scope module optlc_176 $end +$var wire 1 b# HI $end +$var wire 1 !% LO $end +$var supply1 1 6H VPWR $end +$var supply0 1 7H VGND $end +$var supply1 1 8H VPB $end +$var supply0 1 9H VNB $end + +$scope module base $end +$var wire 1 b# HI $end +$var wire 1 !% LO $end +$upscope $end +$upscope $end + +$scope module optlc_178 $end +$var wire 1 .$ HI $end +$var wire 1 "% LO $end +$var supply1 1 :H VPWR $end +$var supply0 1 ;H VGND $end +$var supply1 1 H VPWR $end +$var supply0 1 ?H VGND $end +$var supply1 1 @H VPB $end +$var supply0 1 AH VNB $end + +$scope module base $end +$var wire 1 L$ HI $end +$var wire 1 #% LO $end +$upscope $end +$upscope $end + +$scope module optlc_184 $end +$var wire 1 k# HI $end +$var wire 1 $% LO $end +$var supply1 1 BH VPWR $end +$var supply0 1 CH VGND $end +$var supply1 1 DH VPB $end +$var supply0 1 EH VNB $end + +$scope module base $end +$var wire 1 k# HI $end +$var wire 1 $% LO $end +$upscope $end +$upscope $end + +$scope module optlc_186 $end +$var wire 1 Y# HI $end +$var wire 1 %% LO $end +$var supply1 1 FH VPWR $end +$var supply0 1 GH VGND $end +$var supply1 1 HH VPB $end +$var supply0 1 IH VNB $end + +$scope module base $end +$var wire 1 Y# HI $end +$var wire 1 %% LO $end +$upscope $end +$upscope $end + +$scope module optlc_188 $end +$var wire 1 5$ HI $end +$var wire 1 &% LO $end +$var supply1 1 JH VPWR $end +$var supply0 1 KH VGND $end +$var supply1 1 LH VPB $end +$var supply0 1 MH VNB $end + +$scope module base $end +$var wire 1 5$ HI $end +$var wire 1 &% LO $end +$upscope $end +$upscope $end +$upscope $end + +$scope module sb_6__0_ $end +$var wire 1 NH pReset [0] $end +$var wire 1 OH chany_top_in [0] $end +$var wire 1 PH chany_top_in [1] $end +$var wire 1 QH chany_top_in [2] $end +$var wire 1 RH chany_top_in [3] $end +$var wire 1 SH chany_top_in [4] $end +$var wire 1 TH chany_top_in [5] $end +$var wire 1 UH chany_top_in [6] $end +$var wire 1 VH chany_top_in [7] $end +$var wire 1 WH chany_top_in [8] $end +$var wire 1 XH chany_top_in [9] $end +$var wire 1 YH chany_top_in [10] $end +$var wire 1 ZH chany_top_in [11] $end +$var wire 1 [H chany_top_in [12] $end +$var wire 1 \H chany_top_in [13] $end +$var wire 1 ]H chany_top_in [14] $end +$var wire 1 ^H chany_top_in [15] $end +$var wire 1 _H chany_top_in [16] $end +$var wire 1 `H chany_top_in [17] $end +$var wire 1 aH chany_top_in [18] $end +$var wire 1 bH chany_top_in [19] $end +$var wire 1 cH chany_top_in [20] $end +$var wire 1 dH chany_top_in [21] $end +$var wire 1 eH chany_top_in [22] $end +$var wire 1 fH chany_top_in [23] $end +$var wire 1 gH chany_top_in [24] $end +$var wire 1 hH chany_top_in [25] $end +$var wire 1 iH chany_top_in [26] $end +$var wire 1 jH chany_top_in [27] $end +$var wire 1 kH chany_top_in [28] $end +$var wire 1 lH chany_top_in [29] $end +$var wire 1 mH top_left_grid_pin_44_ [0] $end +$var wire 1 nH top_left_grid_pin_45_ [0] $end +$var wire 1 oH top_left_grid_pin_46_ [0] $end +$var wire 1 pH top_left_grid_pin_47_ [0] $end +$var wire 1 qH top_left_grid_pin_48_ [0] $end +$var wire 1 rH top_left_grid_pin_49_ [0] $end +$var wire 1 sH top_left_grid_pin_50_ [0] $end +$var wire 1 tH top_left_grid_pin_51_ [0] $end +$var wire 1 uH chanx_right_in [0] $end +$var wire 1 vH chanx_right_in [1] $end +$var wire 1 wH chanx_right_in [2] $end +$var wire 1 xH chanx_right_in [3] $end +$var wire 1 yH chanx_right_in [4] $end +$var wire 1 zH chanx_right_in [5] $end +$var wire 1 {H chanx_right_in [6] $end +$var wire 1 |H chanx_right_in [7] $end +$var wire 1 }H chanx_right_in [8] $end +$var wire 1 ~H chanx_right_in [9] $end +$var wire 1 !I chanx_right_in [10] $end +$var wire 1 "I chanx_right_in [11] $end +$var wire 1 #I chanx_right_in [12] $end +$var wire 1 $I chanx_right_in [13] $end +$var wire 1 %I chanx_right_in [14] $end +$var wire 1 &I chanx_right_in [15] $end +$var wire 1 'I chanx_right_in [16] $end +$var wire 1 (I chanx_right_in [17] $end +$var wire 1 )I chanx_right_in [18] $end +$var wire 1 *I chanx_right_in [19] $end +$var wire 1 +I chanx_right_in [20] $end +$var wire 1 ,I chanx_right_in [21] $end +$var wire 1 -I chanx_right_in [22] $end +$var wire 1 .I chanx_right_in [23] $end +$var wire 1 /I chanx_right_in [24] $end +$var wire 1 0I chanx_right_in [25] $end +$var wire 1 1I chanx_right_in [26] $end +$var wire 1 2I chanx_right_in [27] $end +$var wire 1 3I chanx_right_in [28] $end +$var wire 1 4I chanx_right_in [29] $end +$var wire 1 5I right_bottom_grid_pin_1_ [0] $end +$var wire 1 6I right_bottom_grid_pin_3_ [0] $end +$var wire 1 7I right_bottom_grid_pin_5_ [0] $end +$var wire 1 8I right_bottom_grid_pin_7_ [0] $end +$var wire 1 9I right_bottom_grid_pin_9_ [0] $end +$var wire 1 :I right_bottom_grid_pin_11_ [0] $end +$var wire 1 ;I right_bottom_grid_pin_13_ [0] $end +$var wire 1 I chanx_left_in [0] $end +$var wire 1 ?I chanx_left_in [1] $end +$var wire 1 @I chanx_left_in [2] $end +$var wire 1 AI chanx_left_in [3] $end +$var wire 1 BI chanx_left_in [4] $end +$var wire 1 CI chanx_left_in [5] $end +$var wire 1 DI chanx_left_in [6] $end +$var wire 1 EI chanx_left_in [7] $end +$var wire 1 FI chanx_left_in [8] $end +$var wire 1 GI chanx_left_in [9] $end +$var wire 1 HI chanx_left_in [10] $end +$var wire 1 II chanx_left_in [11] $end +$var wire 1 JI chanx_left_in [12] $end +$var wire 1 KI chanx_left_in [13] $end +$var wire 1 LI chanx_left_in [14] $end +$var wire 1 MI chanx_left_in [15] $end +$var wire 1 NI chanx_left_in [16] $end +$var wire 1 OI chanx_left_in [17] $end +$var wire 1 PI chanx_left_in [18] $end +$var wire 1 QI chanx_left_in [19] $end +$var wire 1 RI chanx_left_in [20] $end +$var wire 1 SI chanx_left_in [21] $end +$var wire 1 TI chanx_left_in [22] $end +$var wire 1 UI chanx_left_in [23] $end +$var wire 1 VI chanx_left_in [24] $end +$var wire 1 WI chanx_left_in [25] $end +$var wire 1 XI chanx_left_in [26] $end +$var wire 1 YI chanx_left_in [27] $end +$var wire 1 ZI chanx_left_in [28] $end +$var wire 1 [I chanx_left_in [29] $end +$var wire 1 \I left_bottom_grid_pin_1_ [0] $end +$var wire 1 ]I left_bottom_grid_pin_3_ [0] $end +$var wire 1 ^I left_bottom_grid_pin_5_ [0] $end +$var wire 1 _I left_bottom_grid_pin_7_ [0] $end +$var wire 1 `I left_bottom_grid_pin_9_ [0] $end +$var wire 1 aI left_bottom_grid_pin_11_ [0] $end +$var wire 1 bI left_bottom_grid_pin_13_ [0] $end +$var wire 1 cI left_bottom_grid_pin_15_ [0] $end +$var wire 1 dI left_bottom_grid_pin_17_ [0] $end +$var wire 1 eI ccff_head [0] $end +$var wire 1 fI chany_top_out [0] $end +$var wire 1 gI chany_top_out [1] $end +$var wire 1 hI chany_top_out [2] $end +$var wire 1 iI chany_top_out [3] $end +$var wire 1 jI chany_top_out [4] $end +$var wire 1 kI chany_top_out [5] $end +$var wire 1 lI chany_top_out [6] $end +$var wire 1 mI chany_top_out [7] $end +$var wire 1 nI chany_top_out [8] $end +$var wire 1 oI chany_top_out [9] $end +$var wire 1 pI chany_top_out [10] $end +$var wire 1 qI chany_top_out [11] $end +$var wire 1 rI chany_top_out [12] $end +$var wire 1 sI chany_top_out [13] $end +$var wire 1 tI chany_top_out [14] $end +$var wire 1 uI chany_top_out [15] $end +$var wire 1 vI chany_top_out [16] $end +$var wire 1 wI chany_top_out [17] $end +$var wire 1 xI chany_top_out [18] $end +$var wire 1 yI chany_top_out [19] $end +$var wire 1 zI chany_top_out [20] $end +$var wire 1 {I chany_top_out [21] $end +$var wire 1 |I chany_top_out [22] $end +$var wire 1 }I chany_top_out [23] $end +$var wire 1 ~I chany_top_out [24] $end +$var wire 1 !J chany_top_out [25] $end +$var wire 1 "J chany_top_out [26] $end +$var wire 1 #J chany_top_out [27] $end +$var wire 1 $J chany_top_out [28] $end +$var wire 1 %J chany_top_out [29] $end +$var wire 1 &J chanx_right_out [0] $end +$var wire 1 'J chanx_right_out [1] $end +$var wire 1 (J chanx_right_out [2] $end +$var wire 1 )J chanx_right_out [3] $end +$var wire 1 *J chanx_right_out [4] $end +$var wire 1 +J chanx_right_out [5] $end +$var wire 1 ,J chanx_right_out [6] $end +$var wire 1 -J chanx_right_out [7] $end +$var wire 1 .J chanx_right_out [8] $end +$var wire 1 /J chanx_right_out [9] $end +$var wire 1 0J chanx_right_out [10] $end +$var wire 1 1J chanx_right_out [11] $end +$var wire 1 2J chanx_right_out [12] $end +$var wire 1 3J chanx_right_out [13] $end +$var wire 1 4J chanx_right_out [14] $end +$var wire 1 5J chanx_right_out [15] $end +$var wire 1 6J chanx_right_out [16] $end +$var wire 1 7J chanx_right_out [17] $end +$var wire 1 8J chanx_right_out [18] $end +$var wire 1 9J chanx_right_out [19] $end +$var wire 1 :J chanx_right_out [20] $end +$var wire 1 ;J chanx_right_out [21] $end +$var wire 1 J chanx_right_out [24] $end +$var wire 1 ?J chanx_right_out [25] $end +$var wire 1 @J chanx_right_out [26] $end +$var wire 1 AJ chanx_right_out [27] $end +$var wire 1 BJ chanx_right_out [28] $end +$var wire 1 CJ chanx_right_out [29] $end +$var wire 1 DJ chanx_left_out [0] $end +$var wire 1 EJ chanx_left_out [1] $end +$var wire 1 FJ chanx_left_out [2] $end +$var wire 1 GJ chanx_left_out [3] $end +$var wire 1 HJ chanx_left_out [4] $end +$var wire 1 IJ chanx_left_out [5] $end +$var wire 1 JJ chanx_left_out [6] $end +$var wire 1 KJ chanx_left_out [7] $end +$var wire 1 LJ chanx_left_out [8] $end +$var wire 1 MJ chanx_left_out [9] $end +$var wire 1 NJ chanx_left_out [10] $end +$var wire 1 OJ chanx_left_out [11] $end +$var wire 1 PJ chanx_left_out [12] $end +$var wire 1 QJ chanx_left_out [13] $end +$var wire 1 RJ chanx_left_out [14] $end +$var wire 1 SJ chanx_left_out [15] $end +$var wire 1 TJ chanx_left_out [16] $end +$var wire 1 UJ chanx_left_out [17] $end +$var wire 1 VJ chanx_left_out [18] $end +$var wire 1 WJ chanx_left_out [19] $end +$var wire 1 XJ chanx_left_out [20] $end +$var wire 1 YJ chanx_left_out [21] $end +$var wire 1 ZJ chanx_left_out [22] $end +$var wire 1 [J chanx_left_out [23] $end +$var wire 1 \J chanx_left_out [24] $end +$var wire 1 ]J chanx_left_out [25] $end +$var wire 1 ^J chanx_left_out [26] $end +$var wire 1 _J chanx_left_out [27] $end +$var wire 1 `J chanx_left_out [28] $end +$var wire 1 aJ chanx_left_out [29] $end +$var wire 1 bJ ccff_tail [0] $end +$var wire 1 cJ SC_IN_TOP $end +$var wire 1 dJ SC_OUT_TOP $end +$var wire 1 eJ Test_en_S_in $end +$var wire 1 fJ Test_en_N_out $end +$var wire 1 $ pReset_S_in $end +$var wire 1 gJ pReset_E_in $end +$var wire 1 hJ pReset_W_in $end +$var wire 1 iJ pReset_N_out $end +$var wire 1 jJ pReset_W_out $end +$var wire 1 kJ pReset_E_out $end +$var wire 1 # Reset_S_in $end +$var wire 1 lJ Reset_N_out $end +$var wire 1 mJ prog_clk_0_N_in $end +$var wire 1 ! prog_clk_3_S_in $end +$var wire 1 nJ prog_clk_3_N_out $end +$var wire 1 " clk_3_S_in $end +$var wire 1 oJ clk_3_N_out $end +$var wire 1 pJ ropt_net_229 $end +$var wire 1 qJ prog_clk [0] $end +$var wire 1 rJ prog_clk_0 $end +$var wire 1 sJ mux_2level_tapbuf_size10_0_sram [0] $end +$var wire 1 tJ mux_2level_tapbuf_size10_0_sram [1] $end +$var wire 1 uJ mux_2level_tapbuf_size10_0_sram [2] $end +$var wire 1 vJ mux_2level_tapbuf_size10_0_sram [3] $end +$var wire 1 wJ mux_2level_tapbuf_size10_mem_0_ccff_tail [0] $end +$var wire 1 xJ mux_2level_tapbuf_size2_0_sram [0] $end +$var wire 1 yJ mux_2level_tapbuf_size2_0_sram [1] $end +$var wire 1 zJ mux_2level_tapbuf_size2_10_sram [0] $end +$var wire 1 {J mux_2level_tapbuf_size2_10_sram [1] $end +$var wire 1 |J mux_2level_tapbuf_size2_1_sram [0] $end +$var wire 1 }J mux_2level_tapbuf_size2_1_sram [1] $end +$var wire 1 ~J mux_2level_tapbuf_size2_2_sram [0] $end +$var wire 1 !K mux_2level_tapbuf_size2_2_sram [1] $end +$var wire 1 "K mux_2level_tapbuf_size2_3_sram [0] $end +$var wire 1 #K mux_2level_tapbuf_size2_3_sram [1] $end +$var wire 1 $K mux_2level_tapbuf_size2_4_sram [0] $end +$var wire 1 %K mux_2level_tapbuf_size2_4_sram [1] $end +$var wire 1 &K mux_2level_tapbuf_size2_5_sram [0] $end +$var wire 1 'K mux_2level_tapbuf_size2_5_sram [1] $end +$var wire 1 (K mux_2level_tapbuf_size2_6_sram [0] $end +$var wire 1 )K mux_2level_tapbuf_size2_6_sram [1] $end +$var wire 1 *K mux_2level_tapbuf_size2_7_sram [0] $end +$var wire 1 +K mux_2level_tapbuf_size2_7_sram [1] $end +$var wire 1 ,K mux_2level_tapbuf_size2_8_sram [0] $end +$var wire 1 -K mux_2level_tapbuf_size2_8_sram [1] $end +$var wire 1 .K mux_2level_tapbuf_size2_9_sram [0] $end +$var wire 1 /K mux_2level_tapbuf_size2_9_sram [1] $end +$var wire 1 0K mux_2level_tapbuf_size2_mem_0_ccff_tail [0] $end +$var wire 1 1K mux_2level_tapbuf_size2_mem_10_ccff_tail [0] $end +$var wire 1 2K mux_2level_tapbuf_size2_mem_1_ccff_tail [0] $end +$var wire 1 3K mux_2level_tapbuf_size2_mem_2_ccff_tail [0] $end +$var wire 1 4K mux_2level_tapbuf_size2_mem_3_ccff_tail [0] $end +$var wire 1 5K mux_2level_tapbuf_size2_mem_4_ccff_tail [0] $end +$var wire 1 6K mux_2level_tapbuf_size2_mem_5_ccff_tail [0] $end +$var wire 1 7K mux_2level_tapbuf_size2_mem_6_ccff_tail [0] $end +$var wire 1 8K mux_2level_tapbuf_size2_mem_7_ccff_tail [0] $end +$var wire 1 9K mux_2level_tapbuf_size2_mem_8_ccff_tail [0] $end +$var wire 1 :K mux_2level_tapbuf_size2_mem_9_ccff_tail [0] $end +$var wire 1 ;K mux_2level_tapbuf_size3_0_sram [0] $end +$var wire 1 K mux_2level_tapbuf_size3_1_sram [1] $end +$var wire 1 ?K mux_2level_tapbuf_size3_2_sram [0] $end +$var wire 1 @K mux_2level_tapbuf_size3_2_sram [1] $end +$var wire 1 AK mux_2level_tapbuf_size3_3_sram [0] $end +$var wire 1 BK mux_2level_tapbuf_size3_3_sram [1] $end +$var wire 1 CK mux_2level_tapbuf_size3_4_sram [0] $end +$var wire 1 DK mux_2level_tapbuf_size3_4_sram [1] $end +$var wire 1 EK mux_2level_tapbuf_size3_mem_0_ccff_tail [0] $end +$var wire 1 FK mux_2level_tapbuf_size3_mem_1_ccff_tail [0] $end +$var wire 1 GK mux_2level_tapbuf_size3_mem_2_ccff_tail [0] $end +$var wire 1 HK mux_2level_tapbuf_size3_mem_3_ccff_tail [0] $end +$var wire 1 IK mux_2level_tapbuf_size3_mem_4_ccff_tail [0] $end +$var wire 1 JK mux_2level_tapbuf_size4_0_sram [0] $end +$var wire 1 KK mux_2level_tapbuf_size4_0_sram [1] $end +$var wire 1 LK mux_2level_tapbuf_size4_0_sram [2] $end +$var wire 1 MK mux_2level_tapbuf_size4_0_sram [3] $end +$var wire 1 NK mux_2level_tapbuf_size4_1_sram [0] $end +$var wire 1 OK mux_2level_tapbuf_size4_1_sram [1] $end +$var wire 1 PK mux_2level_tapbuf_size4_1_sram [2] $end +$var wire 1 QK mux_2level_tapbuf_size4_1_sram [3] $end +$var wire 1 RK mux_2level_tapbuf_size4_2_sram [0] $end +$var wire 1 SK mux_2level_tapbuf_size4_2_sram [1] $end +$var wire 1 TK mux_2level_tapbuf_size4_2_sram [2] $end +$var wire 1 UK mux_2level_tapbuf_size4_2_sram [3] $end +$var wire 1 VK mux_2level_tapbuf_size4_3_sram [0] $end +$var wire 1 WK mux_2level_tapbuf_size4_3_sram [1] $end +$var wire 1 XK mux_2level_tapbuf_size4_3_sram [2] $end +$var wire 1 YK mux_2level_tapbuf_size4_3_sram [3] $end +$var wire 1 ZK mux_2level_tapbuf_size4_4_sram [0] $end +$var wire 1 [K mux_2level_tapbuf_size4_4_sram [1] $end +$var wire 1 \K mux_2level_tapbuf_size4_4_sram [2] $end +$var wire 1 ]K mux_2level_tapbuf_size4_4_sram [3] $end +$var wire 1 ^K mux_2level_tapbuf_size4_5_sram [0] $end +$var wire 1 _K mux_2level_tapbuf_size4_5_sram [1] $end +$var wire 1 `K mux_2level_tapbuf_size4_5_sram [2] $end +$var wire 1 aK mux_2level_tapbuf_size4_5_sram [3] $end +$var wire 1 bK mux_2level_tapbuf_size4_mem_0_ccff_tail [0] $end +$var wire 1 cK mux_2level_tapbuf_size4_mem_1_ccff_tail [0] $end +$var wire 1 dK mux_2level_tapbuf_size4_mem_2_ccff_tail [0] $end +$var wire 1 eK mux_2level_tapbuf_size4_mem_3_ccff_tail [0] $end +$var wire 1 fK mux_2level_tapbuf_size4_mem_4_ccff_tail [0] $end +$var wire 1 gK mux_2level_tapbuf_size4_mem_5_ccff_tail [0] $end +$var wire 1 hK mux_2level_tapbuf_size5_0_sram [0] $end +$var wire 1 iK mux_2level_tapbuf_size5_0_sram [1] $end +$var wire 1 jK mux_2level_tapbuf_size5_0_sram [2] $end +$var wire 1 kK mux_2level_tapbuf_size5_0_sram [3] $end +$var wire 1 lK mux_2level_tapbuf_size5_1_sram [0] $end +$var wire 1 mK mux_2level_tapbuf_size5_1_sram [1] $end +$var wire 1 nK mux_2level_tapbuf_size5_1_sram [2] $end +$var wire 1 oK mux_2level_tapbuf_size5_1_sram [3] $end +$var wire 1 pK mux_2level_tapbuf_size5_2_sram [0] $end +$var wire 1 qK mux_2level_tapbuf_size5_2_sram [1] $end +$var wire 1 rK mux_2level_tapbuf_size5_2_sram [2] $end +$var wire 1 sK mux_2level_tapbuf_size5_2_sram [3] $end +$var wire 1 tK mux_2level_tapbuf_size5_3_sram [0] $end +$var wire 1 uK mux_2level_tapbuf_size5_3_sram [1] $end +$var wire 1 vK mux_2level_tapbuf_size5_3_sram [2] $end +$var wire 1 wK mux_2level_tapbuf_size5_3_sram [3] $end +$var wire 1 xK mux_2level_tapbuf_size5_4_sram [0] $end +$var wire 1 yK mux_2level_tapbuf_size5_4_sram [1] $end +$var wire 1 zK mux_2level_tapbuf_size5_4_sram [2] $end +$var wire 1 {K mux_2level_tapbuf_size5_4_sram [3] $end +$var wire 1 |K mux_2level_tapbuf_size5_5_sram [0] $end +$var wire 1 }K mux_2level_tapbuf_size5_5_sram [1] $end +$var wire 1 ~K mux_2level_tapbuf_size5_5_sram [2] $end +$var wire 1 !L mux_2level_tapbuf_size5_5_sram [3] $end +$var wire 1 "L mux_2level_tapbuf_size5_mem_0_ccff_tail [0] $end +$var wire 1 #L mux_2level_tapbuf_size5_mem_1_ccff_tail [0] $end +$var wire 1 $L mux_2level_tapbuf_size5_mem_2_ccff_tail [0] $end +$var wire 1 %L mux_2level_tapbuf_size5_mem_3_ccff_tail [0] $end +$var wire 1 &L mux_2level_tapbuf_size5_mem_4_ccff_tail [0] $end +$var wire 1 'L mux_2level_tapbuf_size6_0_sram [0] $end +$var wire 1 (L mux_2level_tapbuf_size6_0_sram [1] $end +$var wire 1 )L mux_2level_tapbuf_size6_0_sram [2] $end +$var wire 1 *L mux_2level_tapbuf_size6_0_sram [3] $end +$var wire 1 +L mux_2level_tapbuf_size6_1_sram [0] $end +$var wire 1 ,L mux_2level_tapbuf_size6_1_sram [1] $end +$var wire 1 -L mux_2level_tapbuf_size6_1_sram [2] $end +$var wire 1 .L mux_2level_tapbuf_size6_1_sram [3] $end +$var wire 1 /L mux_2level_tapbuf_size6_2_sram [0] $end +$var wire 1 0L mux_2level_tapbuf_size6_2_sram [1] $end +$var wire 1 1L mux_2level_tapbuf_size6_2_sram [2] $end +$var wire 1 2L mux_2level_tapbuf_size6_2_sram [3] $end +$var wire 1 3L mux_2level_tapbuf_size6_mem_0_ccff_tail [0] $end +$var wire 1 4L mux_2level_tapbuf_size6_mem_1_ccff_tail [0] $end +$var wire 1 5L mux_2level_tapbuf_size6_mem_2_ccff_tail [0] $end +$var wire 1 6L mux_2level_tapbuf_size7_0_sram [0] $end +$var wire 1 7L mux_2level_tapbuf_size7_0_sram [1] $end +$var wire 1 8L mux_2level_tapbuf_size7_0_sram [2] $end +$var wire 1 9L mux_2level_tapbuf_size7_0_sram [3] $end +$var wire 1 :L mux_2level_tapbuf_size7_1_sram [0] $end +$var wire 1 ;L mux_2level_tapbuf_size7_1_sram [1] $end +$var wire 1 L mux_2level_tapbuf_size7_2_sram [0] $end +$var wire 1 ?L mux_2level_tapbuf_size7_2_sram [1] $end +$var wire 1 @L mux_2level_tapbuf_size7_2_sram [2] $end +$var wire 1 AL mux_2level_tapbuf_size7_2_sram [3] $end +$var wire 1 BL mux_2level_tapbuf_size7_3_sram [0] $end +$var wire 1 CL mux_2level_tapbuf_size7_3_sram [1] $end +$var wire 1 DL mux_2level_tapbuf_size7_3_sram [2] $end +$var wire 1 EL mux_2level_tapbuf_size7_3_sram [3] $end +$var wire 1 FL mux_2level_tapbuf_size7_4_sram [0] $end +$var wire 1 GL mux_2level_tapbuf_size7_4_sram [1] $end +$var wire 1 HL mux_2level_tapbuf_size7_4_sram [2] $end +$var wire 1 IL mux_2level_tapbuf_size7_4_sram [3] $end +$var wire 1 JL mux_2level_tapbuf_size7_5_sram [0] $end +$var wire 1 KL mux_2level_tapbuf_size7_5_sram [1] $end +$var wire 1 LL mux_2level_tapbuf_size7_5_sram [2] $end +$var wire 1 ML mux_2level_tapbuf_size7_5_sram [3] $end +$var wire 1 NL mux_2level_tapbuf_size7_6_sram [0] $end +$var wire 1 OL mux_2level_tapbuf_size7_6_sram [1] $end +$var wire 1 PL mux_2level_tapbuf_size7_6_sram [2] $end +$var wire 1 QL mux_2level_tapbuf_size7_6_sram [3] $end +$var wire 1 RL mux_2level_tapbuf_size7_7_sram [0] $end +$var wire 1 SL mux_2level_tapbuf_size7_7_sram [1] $end +$var wire 1 TL mux_2level_tapbuf_size7_7_sram [2] $end +$var wire 1 UL mux_2level_tapbuf_size7_7_sram [3] $end +$var wire 1 VL mux_2level_tapbuf_size7_8_sram [0] $end +$var wire 1 WL mux_2level_tapbuf_size7_8_sram [1] $end +$var wire 1 XL mux_2level_tapbuf_size7_8_sram [2] $end +$var wire 1 YL mux_2level_tapbuf_size7_8_sram [3] $end +$var wire 1 ZL mux_2level_tapbuf_size7_9_sram [0] $end +$var wire 1 [L mux_2level_tapbuf_size7_9_sram [1] $end +$var wire 1 \L mux_2level_tapbuf_size7_9_sram [2] $end +$var wire 1 ]L mux_2level_tapbuf_size7_9_sram [3] $end +$var wire 1 ^L mux_2level_tapbuf_size7_mem_0_ccff_tail [0] $end +$var wire 1 _L mux_2level_tapbuf_size7_mem_1_ccff_tail [0] $end +$var wire 1 `L mux_2level_tapbuf_size7_mem_2_ccff_tail [0] $end +$var wire 1 aL mux_2level_tapbuf_size7_mem_3_ccff_tail [0] $end +$var wire 1 bL mux_2level_tapbuf_size7_mem_4_ccff_tail [0] $end +$var wire 1 cL mux_2level_tapbuf_size7_mem_5_ccff_tail [0] $end +$var wire 1 dL mux_2level_tapbuf_size7_mem_6_ccff_tail [0] $end +$var wire 1 eL mux_2level_tapbuf_size7_mem_7_ccff_tail [0] $end +$var wire 1 fL mux_2level_tapbuf_size7_mem_8_ccff_tail [0] $end +$var wire 1 gL mux_2level_tapbuf_size7_mem_9_ccff_tail [0] $end +$var wire 1 hL mux_2level_tapbuf_size8_0_sram [0] $end +$var wire 1 iL mux_2level_tapbuf_size8_0_sram [1] $end +$var wire 1 jL mux_2level_tapbuf_size8_0_sram [2] $end +$var wire 1 kL mux_2level_tapbuf_size8_0_sram [3] $end +$var wire 1 lL mux_2level_tapbuf_size8_1_sram [0] $end +$var wire 1 mL mux_2level_tapbuf_size8_1_sram [1] $end +$var wire 1 nL mux_2level_tapbuf_size8_1_sram [2] $end +$var wire 1 oL mux_2level_tapbuf_size8_1_sram [3] $end +$var wire 1 pL mux_2level_tapbuf_size8_2_sram [0] $end +$var wire 1 qL mux_2level_tapbuf_size8_2_sram [1] $end +$var wire 1 rL mux_2level_tapbuf_size8_2_sram [2] $end +$var wire 1 sL mux_2level_tapbuf_size8_2_sram [3] $end +$var wire 1 tL mux_2level_tapbuf_size8_mem_0_ccff_tail [0] $end +$var wire 1 uL mux_2level_tapbuf_size8_mem_1_ccff_tail [0] $end +$var wire 1 vL mux_2level_tapbuf_size8_mem_2_ccff_tail [0] $end +$var wire 1 wL mux_2level_tapbuf_size9_0_sram [0] $end +$var wire 1 xL mux_2level_tapbuf_size9_0_sram [1] $end +$var wire 1 yL mux_2level_tapbuf_size9_0_sram [2] $end +$var wire 1 zL mux_2level_tapbuf_size9_0_sram [3] $end +$var wire 1 {L mux_2level_tapbuf_size9_1_sram [0] $end +$var wire 1 |L mux_2level_tapbuf_size9_1_sram [1] $end +$var wire 1 }L mux_2level_tapbuf_size9_1_sram [2] $end +$var wire 1 ~L mux_2level_tapbuf_size9_1_sram [3] $end +$var wire 1 !M mux_2level_tapbuf_size9_2_sram [0] $end +$var wire 1 "M mux_2level_tapbuf_size9_2_sram [1] $end +$var wire 1 #M mux_2level_tapbuf_size9_2_sram [2] $end +$var wire 1 $M mux_2level_tapbuf_size9_2_sram [3] $end +$var wire 1 %M mux_2level_tapbuf_size9_mem_0_ccff_tail [0] $end +$var wire 1 &M mux_2level_tapbuf_size9_mem_1_ccff_tail [0] $end +$var wire 1 'M mux_2level_tapbuf_size9_mem_2_ccff_tail [0] $end +$var wire 1 (M SYNOPSYS_UNCONNECTED_1 $end +$var wire 1 )M SYNOPSYS_UNCONNECTED_2 $end +$var wire 1 *M SYNOPSYS_UNCONNECTED_3 $end +$var wire 1 +M SYNOPSYS_UNCONNECTED_4 $end +$var wire 1 ,M optlc_net_212 $end +$var wire 1 -M SYNOPSYS_UNCONNECTED_5 $end +$var wire 1 .M SYNOPSYS_UNCONNECTED_6 $end +$var wire 1 /M SYNOPSYS_UNCONNECTED_7 $end +$var wire 1 0M SYNOPSYS_UNCONNECTED_8 $end +$var wire 1 1M SYNOPSYS_UNCONNECTED_9 $end +$var wire 1 2M SYNOPSYS_UNCONNECTED_10 $end +$var wire 1 3M SYNOPSYS_UNCONNECTED_11 $end +$var wire 1 4M SYNOPSYS_UNCONNECTED_12 $end +$var wire 1 5M SYNOPSYS_UNCONNECTED_13 $end +$var wire 1 6M SYNOPSYS_UNCONNECTED_14 $end +$var wire 1 7M SYNOPSYS_UNCONNECTED_15 $end +$var wire 1 8M SYNOPSYS_UNCONNECTED_16 $end +$var wire 1 9M optlc_net_209 $end +$var wire 1 :M SYNOPSYS_UNCONNECTED_17 $end +$var wire 1 ;M SYNOPSYS_UNCONNECTED_18 $end +$var wire 1 M SYNOPSYS_UNCONNECTED_21 $end +$var wire 1 ?M SYNOPSYS_UNCONNECTED_22 $end +$var wire 1 @M SYNOPSYS_UNCONNECTED_23 $end +$var wire 1 AM SYNOPSYS_UNCONNECTED_24 $end +$var wire 1 BM optlc_net_207 $end +$var wire 1 CM SYNOPSYS_UNCONNECTED_25 $end +$var wire 1 DM SYNOPSYS_UNCONNECTED_26 $end +$var wire 1 EM SYNOPSYS_UNCONNECTED_27 $end +$var wire 1 FM SYNOPSYS_UNCONNECTED_28 $end +$var wire 1 GM optlc_net_210 $end +$var wire 1 HM SYNOPSYS_UNCONNECTED_29 $end +$var wire 1 IM SYNOPSYS_UNCONNECTED_30 $end +$var wire 1 JM SYNOPSYS_UNCONNECTED_31 $end +$var wire 1 KM SYNOPSYS_UNCONNECTED_32 $end +$var wire 1 LM optlc_net_211 $end +$var wire 1 MM SYNOPSYS_UNCONNECTED_33 $end +$var wire 1 NM SYNOPSYS_UNCONNECTED_34 $end +$var wire 1 OM SYNOPSYS_UNCONNECTED_35 $end +$var wire 1 PM SYNOPSYS_UNCONNECTED_36 $end +$var wire 1 QM SYNOPSYS_UNCONNECTED_37 $end +$var wire 1 RM SYNOPSYS_UNCONNECTED_38 $end +$var wire 1 SM SYNOPSYS_UNCONNECTED_39 $end +$var wire 1 TM SYNOPSYS_UNCONNECTED_40 $end +$var wire 1 UM SYNOPSYS_UNCONNECTED_41 $end +$var wire 1 VM SYNOPSYS_UNCONNECTED_42 $end +$var wire 1 WM SYNOPSYS_UNCONNECTED_43 $end +$var wire 1 XM SYNOPSYS_UNCONNECTED_44 $end +$var wire 1 YM SYNOPSYS_UNCONNECTED_45 $end +$var wire 1 ZM SYNOPSYS_UNCONNECTED_46 $end +$var wire 1 [M SYNOPSYS_UNCONNECTED_47 $end +$var wire 1 \M SYNOPSYS_UNCONNECTED_48 $end +$var wire 1 ]M SYNOPSYS_UNCONNECTED_49 $end +$var wire 1 ^M SYNOPSYS_UNCONNECTED_50 $end +$var wire 1 _M SYNOPSYS_UNCONNECTED_51 $end +$var wire 1 `M SYNOPSYS_UNCONNECTED_52 $end +$var wire 1 aM optlc_net_208 $end +$var wire 1 bM SYNOPSYS_UNCONNECTED_53 $end +$var wire 1 cM SYNOPSYS_UNCONNECTED_54 $end +$var wire 1 dM SYNOPSYS_UNCONNECTED_55 $end +$var wire 1 eM SYNOPSYS_UNCONNECTED_56 $end +$var wire 1 fM SYNOPSYS_UNCONNECTED_57 $end +$var wire 1 gM SYNOPSYS_UNCONNECTED_58 $end +$var wire 1 hM SYNOPSYS_UNCONNECTED_59 $end +$var wire 1 iM SYNOPSYS_UNCONNECTED_60 $end +$var wire 1 jM SYNOPSYS_UNCONNECTED_61 $end +$var wire 1 kM SYNOPSYS_UNCONNECTED_62 $end +$var wire 1 lM SYNOPSYS_UNCONNECTED_63 $end +$var wire 1 mM SYNOPSYS_UNCONNECTED_64 $end +$var wire 1 nM SYNOPSYS_UNCONNECTED_65 $end +$var wire 1 oM SYNOPSYS_UNCONNECTED_66 $end +$var wire 1 pM SYNOPSYS_UNCONNECTED_67 $end +$var wire 1 qM SYNOPSYS_UNCONNECTED_68 $end +$var wire 1 rM SYNOPSYS_UNCONNECTED_69 $end +$var wire 1 sM SYNOPSYS_UNCONNECTED_70 $end +$var wire 1 tM SYNOPSYS_UNCONNECTED_71 $end +$var wire 1 uM SYNOPSYS_UNCONNECTED_72 $end +$var wire 1 vM SYNOPSYS_UNCONNECTED_73 $end +$var wire 1 wM SYNOPSYS_UNCONNECTED_74 $end +$var wire 1 xM SYNOPSYS_UNCONNECTED_75 $end +$var wire 1 yM SYNOPSYS_UNCONNECTED_76 $end +$var wire 1 zM SYNOPSYS_UNCONNECTED_77 $end +$var wire 1 {M SYNOPSYS_UNCONNECTED_78 $end +$var wire 1 |M SYNOPSYS_UNCONNECTED_79 $end +$var wire 1 }M SYNOPSYS_UNCONNECTED_80 $end +$var wire 1 ~M SYNOPSYS_UNCONNECTED_81 $end +$var wire 1 !N SYNOPSYS_UNCONNECTED_82 $end +$var wire 1 "N SYNOPSYS_UNCONNECTED_83 $end +$var wire 1 #N SYNOPSYS_UNCONNECTED_84 $end +$var wire 1 $N SYNOPSYS_UNCONNECTED_85 $end +$var wire 1 %N SYNOPSYS_UNCONNECTED_86 $end +$var wire 1 &N SYNOPSYS_UNCONNECTED_87 $end +$var wire 1 'N SYNOPSYS_UNCONNECTED_88 $end +$var wire 1 (N SYNOPSYS_UNCONNECTED_89 $end +$var wire 1 )N SYNOPSYS_UNCONNECTED_90 $end +$var wire 1 *N SYNOPSYS_UNCONNECTED_91 $end +$var wire 1 +N SYNOPSYS_UNCONNECTED_92 $end +$var wire 1 ,N SYNOPSYS_UNCONNECTED_93 $end +$var wire 1 -N SYNOPSYS_UNCONNECTED_94 $end +$var wire 1 .N SYNOPSYS_UNCONNECTED_95 $end +$var wire 1 /N SYNOPSYS_UNCONNECTED_96 $end +$var wire 1 0N SYNOPSYS_UNCONNECTED_97 $end +$var wire 1 1N SYNOPSYS_UNCONNECTED_98 $end +$var wire 1 2N SYNOPSYS_UNCONNECTED_99 $end +$var wire 1 3N SYNOPSYS_UNCONNECTED_100 $end +$var wire 1 4N SYNOPSYS_UNCONNECTED_101 $end +$var wire 1 5N SYNOPSYS_UNCONNECTED_102 $end +$var wire 1 6N SYNOPSYS_UNCONNECTED_103 $end +$var wire 1 7N SYNOPSYS_UNCONNECTED_104 $end +$var wire 1 8N SYNOPSYS_UNCONNECTED_105 $end +$var wire 1 9N SYNOPSYS_UNCONNECTED_106 $end +$var wire 1 :N SYNOPSYS_UNCONNECTED_107 $end +$var wire 1 ;N SYNOPSYS_UNCONNECTED_108 $end +$var wire 1 N SYNOPSYS_UNCONNECTED_111 $end +$var wire 1 ?N SYNOPSYS_UNCONNECTED_112 $end +$var wire 1 @N SYNOPSYS_UNCONNECTED_113 $end +$var wire 1 AN SYNOPSYS_UNCONNECTED_114 $end +$var wire 1 BN SYNOPSYS_UNCONNECTED_115 $end +$var wire 1 CN SYNOPSYS_UNCONNECTED_116 $end +$var wire 1 DN SYNOPSYS_UNCONNECTED_117 $end +$var wire 1 EN SYNOPSYS_UNCONNECTED_118 $end +$var wire 1 FN SYNOPSYS_UNCONNECTED_119 $end +$var wire 1 GN SYNOPSYS_UNCONNECTED_120 $end +$var wire 1 HN SYNOPSYS_UNCONNECTED_121 $end +$var wire 1 IN SYNOPSYS_UNCONNECTED_122 $end +$var wire 1 JN SYNOPSYS_UNCONNECTED_123 $end +$var wire 1 KN SYNOPSYS_UNCONNECTED_124 $end +$var wire 1 LN SYNOPSYS_UNCONNECTED_125 $end +$var wire 1 MN SYNOPSYS_UNCONNECTED_126 $end +$var wire 1 NN SYNOPSYS_UNCONNECTED_127 $end +$var wire 1 ON SYNOPSYS_UNCONNECTED_128 $end +$var wire 1 PN SYNOPSYS_UNCONNECTED_129 $end +$var wire 1 QN SYNOPSYS_UNCONNECTED_130 $end +$var wire 1 RN SYNOPSYS_UNCONNECTED_131 $end +$var wire 1 SN SYNOPSYS_UNCONNECTED_132 $end +$var wire 1 TN SYNOPSYS_UNCONNECTED_133 $end +$var wire 1 UN SYNOPSYS_UNCONNECTED_134 $end +$var wire 1 VN SYNOPSYS_UNCONNECTED_135 $end +$var wire 1 WN SYNOPSYS_UNCONNECTED_136 $end +$var wire 1 XN SYNOPSYS_UNCONNECTED_137 $end +$var wire 1 YN SYNOPSYS_UNCONNECTED_138 $end +$var wire 1 ZN SYNOPSYS_UNCONNECTED_139 $end +$var wire 1 [N SYNOPSYS_UNCONNECTED_140 $end +$var wire 1 \N SYNOPSYS_UNCONNECTED_141 $end +$var wire 1 ]N SYNOPSYS_UNCONNECTED_142 $end +$var wire 1 ^N SYNOPSYS_UNCONNECTED_143 $end +$var wire 1 _N SYNOPSYS_UNCONNECTED_144 $end +$var wire 1 `N SYNOPSYS_UNCONNECTED_145 $end +$var wire 1 aN SYNOPSYS_UNCONNECTED_146 $end +$var wire 1 bN SYNOPSYS_UNCONNECTED_147 $end +$var wire 1 cN SYNOPSYS_UNCONNECTED_148 $end +$var wire 1 dN aps_rename_505_ $end +$var wire 1 eN SYNOPSYS_UNCONNECTED_149 $end +$var wire 1 fN SYNOPSYS_UNCONNECTED_150 $end +$var wire 1 gN SYNOPSYS_UNCONNECTED_151 $end +$var wire 1 hN SYNOPSYS_UNCONNECTED_152 $end +$var wire 1 iN SYNOPSYS_UNCONNECTED_153 $end +$var wire 1 jN SYNOPSYS_UNCONNECTED_154 $end +$var wire 1 kN SYNOPSYS_UNCONNECTED_155 $end +$var wire 1 lN SYNOPSYS_UNCONNECTED_156 $end +$var wire 1 mN aps_rename_506_ $end +$var wire 1 nN SYNOPSYS_UNCONNECTED_157 $end +$var wire 1 oN SYNOPSYS_UNCONNECTED_158 $end +$var wire 1 pN SYNOPSYS_UNCONNECTED_159 $end +$var wire 1 qN SYNOPSYS_UNCONNECTED_160 $end +$var wire 1 rN SYNOPSYS_UNCONNECTED_161 $end +$var wire 1 sN aps_rename_507_ $end +$var wire 1 tN aps_rename_508_ $end +$var wire 1 uN SYNOPSYS_UNCONNECTED_162 $end +$var wire 1 vN aps_rename_509_ $end +$var wire 1 wN aps_rename_510_ $end +$var wire 1 xN BUF_net_196 $end +$var wire 1 yN BUF_net_198 $end +$var wire 1 zN BUF_net_200 $end +$var wire 1 {N BUF_net_202 $end +$var wire 1 |N BUF_net_204 $end +$var wire 1 }N SYNOPSYS_UNCONNECTED_163 $end +$var wire 1 ~N SYNOPSYS_UNCONNECTED_164 $end +$var wire 1 !O SYNOPSYS_UNCONNECTED_165 $end +$var wire 1 "O SYNOPSYS_UNCONNECTED_166 $end + +$scope module mux_top_track_0 $end +$var wire 1 mH in [0] $end +$var wire 1 pH in [1] $end +$var wire 1 sH in [2] $end +$var wire 1 vH in [3] $end +$var wire 1 HJ in [4] $end +$var wire 1 >I in [5] $end +$var wire 1 *J in [6] $end +$var wire 1 6L sram [0] $end +$var wire 1 7L sram [1] $end +$var wire 1 8L sram [2] $end +$var wire 1 9L sram [3] $end +$var wire 1 (M sram_inv [0] $end +$var wire 1 )M sram_inv [1] $end +$var wire 1 *M sram_inv [2] $end +$var wire 1 +M sram_inv [3] $end +$var wire 1 fI out [0] $end +$var wire 1 ,M p0 $end +$var wire 1 #O local_encoder2to3_0_data [0] $end +$var wire 1 $O local_encoder2to3_0_data [1] $end +$var wire 1 %O local_encoder2to3_0_data [2] $end +$var wire 1 &O local_encoder2to3_0_data_inv [0] $end +$var wire 1 'O local_encoder2to3_0_data_inv [1] $end +$var wire 1 (O local_encoder2to3_0_data_inv [2] $end +$var wire 1 )O local_encoder2to3_1_data [0] $end +$var wire 1 *O local_encoder2to3_1_data [1] $end +$var wire 1 +O local_encoder2to3_1_data [2] $end +$var wire 1 ,O local_encoder2to3_1_data_inv [0] $end +$var wire 1 -O local_encoder2to3_1_data_inv [1] $end +$var wire 1 .O local_encoder2to3_1_data_inv [2] $end +$var wire 1 /O mux_2level_tapbuf_basis_input2_mem2_0_out [0] $end +$var wire 1 0O mux_2level_tapbuf_basis_input3_mem3_0_out [0] $end +$var wire 1 1O mux_2level_tapbuf_basis_input3_mem3_1_out [0] $end +$var wire 1 2O mux_2level_tapbuf_basis_input3_mem3_2_out [0] $end +$var wire 1 3O SYNOPSYS_UNCONNECTED_1 $end + +$scope module sky130_fd_sc_hd__buf_4_0_ $end +$var wire 1 fI X $end +$var wire 1 2O A $end +$var supply1 1 4O VPWR $end +$var supply0 1 5O VGND $end +$var supply1 1 6O VPB $end +$var supply0 1 7O VNB $end + +$scope module base $end +$var wire 1 fI X $end +$var wire 1 2O A $end +$var wire 1 8O buf0_out_X $end +$upscope $end +$upscope $end + +$scope module local_encoder2to3_0_ $end +$var wire 1 6L addr [0] $end +$var wire 1 7L addr [1] $end +$var wire 1 #O data [0] $end +$var wire 1 $O data [1] $end +$var wire 1 %O data [2] $end +$var wire 1 &O data_inv [0] $end +$var wire 1 'O data_inv [1] $end +$var wire 1 (O data_inv [2] $end + +$scope module U8 $end +$var wire 1 &O Y $end +$var wire 1 #O A $end +$var supply1 1 9O VPWR $end +$var supply0 1 :O VGND $end +$var supply1 1 ;O VPB $end +$var supply0 1 O VPWR $end +$var supply0 1 ?O VGND $end +$var supply1 1 @O VPB $end +$var supply0 1 AO VNB $end + +$scope module base $end +$var wire 1 $O Y $end +$var wire 1 'O A $end +$var wire 1 BO not0_out_Y $end +$upscope $end +$upscope $end + +$scope module U10 $end +$var wire 1 'O Y $end +$var wire 1 6L A $end +$var wire 1 (O B $end +$var supply1 1 CO VPWR $end +$var supply0 1 DO VGND $end +$var supply1 1 EO VPB $end +$var supply0 1 FO VNB $end + +$scope module base $end +$var wire 1 'O Y $end +$var wire 1 6L A $end +$var wire 1 (O B $end +$var wire 1 GO nand0_out_Y $end +$upscope $end +$upscope $end + +$scope module U11 $end +$var wire 1 (O Y $end +$var wire 1 %O A $end +$var supply1 1 HO VPWR $end +$var supply0 1 IO VGND $end +$var supply1 1 JO VPB $end +$var supply0 1 KO VNB $end + +$scope module base $end +$var wire 1 (O Y $end +$var wire 1 %O A $end +$var wire 1 LO not0_out_Y $end +$upscope $end +$upscope $end + +$scope module U12 $end +$var wire 1 #O Y $end +$var wire 1 %O A $end +$var wire 1 6L B $end +$var supply1 1 MO VPWR $end +$var supply0 1 NO VGND $end +$var supply1 1 OO VPB $end +$var supply0 1 PO VNB $end + +$scope module base $end +$var wire 1 #O Y $end +$var wire 1 %O A $end +$var wire 1 6L B $end +$var wire 1 QO nor0_out_Y $end +$upscope $end +$upscope $end + +$scope module FTB_1__0 $end +$var wire 1 %O X $end +$var wire 1 7L A $end +$var supply1 1 RO VPWR $end +$var supply0 1 SO VGND $end +$var supply1 1 TO VPB $end +$var supply0 1 UO VNB $end + +$scope module base $end +$var wire 1 %O X $end +$var wire 1 7L A $end +$var wire 1 VO buf0_out_X $end +$upscope $end +$upscope $end +$upscope $end + +$scope module local_encoder2to3_1_ $end +$var wire 1 8L addr [0] $end +$var wire 1 9L addr [1] $end +$var wire 1 )O data [0] $end +$var wire 1 *O data [1] $end +$var wire 1 +O data [2] $end +$var wire 1 ,O data_inv [0] $end +$var wire 1 -O data_inv [1] $end +$var wire 1 .O data_inv [2] $end + +$scope module U8 $end +$var wire 1 ,O Y $end +$var wire 1 )O A $end +$var supply1 1 WO VPWR $end +$var supply0 1 XO VGND $end +$var supply1 1 YO VPB $end +$var supply0 1 ZO VNB $end + +$scope module base $end +$var wire 1 ,O Y $end +$var wire 1 )O A $end +$var wire 1 [O not0_out_Y $end +$upscope $end +$upscope $end + +$scope module U9 $end +$var wire 1 *O Y $end +$var wire 1 -O A $end +$var supply1 1 \O VPWR $end +$var supply0 1 ]O VGND $end +$var supply1 1 ^O VPB $end +$var supply0 1 _O VNB $end + +$scope module base $end +$var wire 1 *O Y $end +$var wire 1 -O A $end +$var wire 1 `O not0_out_Y $end +$upscope $end +$upscope $end + +$scope module U10 $end +$var wire 1 -O Y $end +$var wire 1 8L A $end +$var wire 1 .O B $end +$var supply1 1 aO VPWR $end +$var supply0 1 bO VGND $end +$var supply1 1 cO VPB $end +$var supply0 1 dO VNB $end + +$scope module base $end +$var wire 1 -O Y $end +$var wire 1 8L A $end +$var wire 1 .O B $end +$var wire 1 eO nand0_out_Y $end +$upscope $end +$upscope $end + +$scope module U11 $end +$var wire 1 .O Y $end +$var wire 1 +O A $end +$var supply1 1 fO VPWR $end +$var supply0 1 gO VGND $end +$var supply1 1 hO VPB $end +$var supply0 1 iO VNB $end + +$scope module base $end +$var wire 1 .O Y $end +$var wire 1 +O A $end +$var wire 1 jO not0_out_Y $end +$upscope $end +$upscope $end + +$scope module U12 $end +$var wire 1 )O Y $end +$var wire 1 +O A $end +$var wire 1 8L B $end +$var supply1 1 kO VPWR $end +$var supply0 1 lO VGND $end +$var supply1 1 mO VPB $end +$var supply0 1 nO VNB $end + +$scope module base $end +$var wire 1 )O Y $end +$var wire 1 +O A $end +$var wire 1 8L B $end +$var wire 1 oO nor0_out_Y $end +$upscope $end +$upscope $end + +$scope module FTB_2__1 $end +$var wire 1 +O X $end +$var wire 1 9L A $end +$var supply1 1 pO VPWR $end +$var supply0 1 qO VGND $end +$var supply1 1 rO VPB $end +$var supply0 1 sO VNB $end + +$scope module base $end +$var wire 1 +O X $end +$var wire 1 9L A $end +$var wire 1 tO buf0_out_X $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mux_l1_in_0_ $end +$var wire 1 mH in [0] $end +$var wire 1 pH in [1] $end +$var wire 1 sH in [2] $end +$var wire 1 #O mem [0] $end +$var wire 1 $O mem [1] $end +$var wire 1 %O mem [2] $end +$var wire 1 &O mem_inv [0] $end +$var wire 1 'O mem_inv [1] $end +$var wire 1 (O mem_inv [2] $end +$var wire 1 0O out [0] $end + +$scope module scs8hd_muxinv3_1_0 $end +$var wire 1 0O Z $end +$var wire 1 mH Q1 $end +$var wire 1 pH Q2 $end +$var wire 1 sH Q3 $end +$var wire 1 #O S0 $end +$var wire 1 &O S0B $end +$var wire 1 $O S1 $end +$var wire 1 'O S1B $end +$var wire 1 %O S2 $end +$var wire 1 (O S2B $end +$var wire 1 uO Q1__bar $end +$var wire 1 vO Q2__bar $end +$var wire 1 wO Q3__bar $end +$upscope $end +$upscope $end + +$scope module mux_l1_in_1_ $end +$var wire 1 vH in [0] $end +$var wire 1 HJ in [1] $end +$var wire 1 >I in [2] $end +$var wire 1 #O mem [0] $end +$var wire 1 $O mem [1] $end +$var wire 1 %O mem [2] $end +$var wire 1 &O mem_inv [0] $end +$var wire 1 'O mem_inv [1] $end +$var wire 1 (O mem_inv [2] $end +$var wire 1 1O out [0] $end + +$scope module scs8hd_muxinv3_1_0 $end +$var wire 1 1O Z $end +$var wire 1 vH Q1 $end +$var wire 1 HJ Q2 $end +$var wire 1 >I Q3 $end +$var wire 1 #O S0 $end +$var wire 1 &O S0B $end +$var wire 1 $O S1 $end +$var wire 1 'O S1B $end +$var wire 1 %O S2 $end +$var wire 1 (O S2B $end +$var wire 1 xO Q1__bar $end +$var wire 1 yO Q2__bar $end +$var wire 1 zO Q3__bar $end +$upscope $end +$upscope $end + +$scope module mux_l2_in_0_ $end +$var wire 1 0O in [0] $end +$var wire 1 1O in [1] $end +$var wire 1 /O in [2] $end +$var wire 1 )O mem [0] $end +$var wire 1 *O mem [1] $end +$var wire 1 +O mem [2] $end +$var wire 1 ,O mem_inv [0] $end +$var wire 1 -O mem_inv [1] $end +$var wire 1 .O mem_inv [2] $end +$var wire 1 2O out [0] $end + +$scope module scs8hd_muxinv3_1_0 $end +$var wire 1 2O Z $end +$var wire 1 0O Q1 $end +$var wire 1 1O Q2 $end +$var wire 1 /O Q3 $end +$var wire 1 )O S0 $end +$var wire 1 ,O S0B $end +$var wire 1 *O S1 $end +$var wire 1 -O S1B $end +$var wire 1 +O S2 $end +$var wire 1 .O S2B $end +$var wire 1 {O Q1__bar $end +$var wire 1 |O Q2__bar $end +$var wire 1 }O Q3__bar $end +$upscope $end +$upscope $end + +$scope module mux_l1_in_2_ $end +$var wire 1 *J in [0] $end +$var wire 1 3O in [1] $end +$var wire 1 #O mem [0] $end +$var wire 1 $O mem [1] $end +$var wire 1 &O mem_inv [0] $end +$var wire 1 'O mem_inv [1] $end +$var wire 1 /O out [0] $end +$var wire 1 ,M p0 $end + +$scope module scs8hd_muxinv2_1_0 $end +$var wire 1 /O Z $end +$var wire 1 *J Q1 $end +$var wire 1 ,M Q2 $end +$var wire 1 #O S0 $end +$var wire 1 &O S0B $end +$var wire 1 $O S1 $end +$var wire 1 'O S1B $end +$var wire 1 ~O Q1__bar $end +$var wire 1 !P Q2__bar $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mux_right_track_0 $end +$var wire 1 YH in [0] $end +$var wire 1 dH in [1] $end +$var wire 1 5I in [2] $end +$var wire 1 8I in [3] $end +$var wire 1 ;I in [4] $end +$var wire 1 *J in [5] $end +$var wire 1 :J in [6] $end +$var wire 1 :L sram [0] $end +$var wire 1 ;L sram [1] $end +$var wire 1 P VGND $end +$var supply1 1 ?P VPB $end +$var supply0 1 @P VNB $end + +$scope module base $end +$var wire 1 #P Y $end +$var wire 1 &P A $end +$var wire 1 AP not0_out_Y $end +$upscope $end +$upscope $end + +$scope module U10 $end +$var wire 1 &P Y $end +$var wire 1 :L A $end +$var wire 1 'P B $end +$var supply1 1 BP VPWR $end +$var supply0 1 CP VGND $end +$var supply1 1 DP VPB $end +$var supply0 1 EP VNB $end + +$scope module base $end +$var wire 1 &P Y $end +$var wire 1 :L A $end +$var wire 1 'P B $end +$var wire 1 FP nand0_out_Y $end +$upscope $end +$upscope $end + +$scope module U11 $end +$var wire 1 'P Y $end +$var wire 1 $P A $end +$var supply1 1 GP VPWR $end +$var supply0 1 HP VGND $end +$var supply1 1 IP VPB $end +$var supply0 1 JP VNB $end + +$scope module base $end +$var wire 1 'P Y $end +$var wire 1 $P A $end +$var wire 1 KP not0_out_Y $end +$upscope $end +$upscope $end + +$scope module U12 $end +$var wire 1 "P Y $end +$var wire 1 $P A $end +$var wire 1 :L B $end +$var supply1 1 LP VPWR $end +$var supply0 1 MP VGND $end +$var supply1 1 NP VPB $end +$var supply0 1 OP VNB $end + +$scope module base $end +$var wire 1 "P Y $end +$var wire 1 $P A $end +$var wire 1 :L B $end +$var wire 1 PP nor0_out_Y $end +$upscope $end +$upscope $end + +$scope module FTB_3__2 $end +$var wire 1 $P X $end +$var wire 1 ;L A $end +$var supply1 1 QP VPWR $end +$var supply0 1 RP VGND $end +$var supply1 1 SP VPB $end +$var supply0 1 TP VNB $end + +$scope module base $end +$var wire 1 $P X $end +$var wire 1 ;L A $end +$var wire 1 UP buf0_out_X $end +$upscope $end +$upscope $end +$upscope $end + +$scope module local_encoder2to3_1_ $end +$var wire 1 L sram [0] $end +$var wire 1 ?L sram [1] $end +$var wire 1 @L sram [2] $end +$var wire 1 AL sram [3] $end +$var wire 1 1M sram_inv [0] $end +$var wire 1 2M sram_inv [1] $end +$var wire 1 3M sram_inv [2] $end +$var wire 1 4M sram_inv [3] $end +$var wire 1 ,J out [0] $end +$var wire 1 ,M p0 $end +$var wire 1 !Q local_encoder2to3_0_data [0] $end +$var wire 1 "Q local_encoder2to3_0_data [1] $end +$var wire 1 #Q local_encoder2to3_0_data [2] $end +$var wire 1 $Q local_encoder2to3_0_data_inv [0] $end +$var wire 1 %Q local_encoder2to3_0_data_inv [1] $end +$var wire 1 &Q local_encoder2to3_0_data_inv [2] $end +$var wire 1 'Q local_encoder2to3_1_data [0] $end +$var wire 1 (Q local_encoder2to3_1_data [1] $end +$var wire 1 )Q local_encoder2to3_1_data [2] $end +$var wire 1 *Q local_encoder2to3_1_data_inv [0] $end +$var wire 1 +Q local_encoder2to3_1_data_inv [1] $end +$var wire 1 ,Q local_encoder2to3_1_data_inv [2] $end +$var wire 1 -Q mux_2level_tapbuf_basis_input2_mem2_0_out [0] $end +$var wire 1 .Q mux_2level_tapbuf_basis_input3_mem3_0_out [0] $end +$var wire 1 /Q mux_2level_tapbuf_basis_input3_mem3_1_out [0] $end +$var wire 1 0Q mux_2level_tapbuf_basis_input3_mem3_2_out [0] $end +$var wire 1 1Q SYNOPSYS_UNCONNECTED_1 $end + +$scope module sky130_fd_sc_hd__buf_4_0_ $end +$var wire 1 ,J X $end +$var wire 1 0Q A $end +$var supply1 1 2Q VPWR $end +$var supply0 1 3Q VGND $end +$var supply1 1 4Q VPB $end +$var supply0 1 5Q VNB $end + +$scope module base $end +$var wire 1 ,J X $end +$var wire 1 0Q A $end +$var wire 1 6Q buf0_out_X $end +$upscope $end +$upscope $end + +$scope module local_encoder2to3_0_ $end +$var wire 1 >L addr [0] $end +$var wire 1 ?L addr [1] $end +$var wire 1 !Q data [0] $end +$var wire 1 "Q data [1] $end +$var wire 1 #Q data [2] $end +$var wire 1 $Q data_inv [0] $end +$var wire 1 %Q data_inv [1] $end +$var wire 1 &Q data_inv [2] $end + +$scope module U8 $end +$var wire 1 $Q Y $end +$var wire 1 !Q A $end +$var supply1 1 7Q VPWR $end +$var supply0 1 8Q VGND $end +$var supply1 1 9Q VPB $end +$var supply0 1 :Q VNB $end + +$scope module base $end +$var wire 1 $Q Y $end +$var wire 1 !Q A $end +$var wire 1 ;Q not0_out_Y $end +$upscope $end +$upscope $end + +$scope module U9 $end +$var wire 1 "Q Y $end +$var wire 1 %Q A $end +$var supply1 1 Q VPB $end +$var supply0 1 ?Q VNB $end + +$scope module base $end +$var wire 1 "Q Y $end +$var wire 1 %Q A $end +$var wire 1 @Q not0_out_Y $end +$upscope $end +$upscope $end + +$scope module U10 $end +$var wire 1 %Q Y $end +$var wire 1 >L A $end +$var wire 1 &Q B $end +$var supply1 1 AQ VPWR $end +$var supply0 1 BQ VGND $end +$var supply1 1 CQ VPB $end +$var supply0 1 DQ VNB $end + +$scope module base $end +$var wire 1 %Q Y $end +$var wire 1 >L A $end +$var wire 1 &Q B $end +$var wire 1 EQ nand0_out_Y $end +$upscope $end +$upscope $end + +$scope module U11 $end +$var wire 1 &Q Y $end +$var wire 1 #Q A $end +$var supply1 1 FQ VPWR $end +$var supply0 1 GQ VGND $end +$var supply1 1 HQ VPB $end +$var supply0 1 IQ VNB $end + +$scope module base $end +$var wire 1 &Q Y $end +$var wire 1 #Q A $end +$var wire 1 JQ not0_out_Y $end +$upscope $end +$upscope $end + +$scope module U12 $end +$var wire 1 !Q Y $end +$var wire 1 #Q A $end +$var wire 1 >L B $end +$var supply1 1 KQ VPWR $end +$var supply0 1 LQ VGND $end +$var supply1 1 MQ VPB $end +$var supply0 1 NQ VNB $end + +$scope module base $end +$var wire 1 !Q Y $end +$var wire 1 #Q A $end +$var wire 1 >L B $end +$var wire 1 OQ nor0_out_Y $end +$upscope $end +$upscope $end + +$scope module FTB_5__4 $end +$var wire 1 #Q X $end +$var wire 1 ?L A $end +$var supply1 1 PQ VPWR $end +$var supply0 1 QQ VGND $end +$var supply1 1 RQ VPB $end +$var supply0 1 SQ VNB $end + +$scope module base $end +$var wire 1 #Q X $end +$var wire 1 ?L A $end +$var wire 1 TQ buf0_out_X $end +$upscope $end +$upscope $end +$upscope $end + +$scope module local_encoder2to3_1_ $end +$var wire 1 @L addr [0] $end +$var wire 1 AL addr [1] $end +$var wire 1 'Q data [0] $end +$var wire 1 (Q data [1] $end +$var wire 1 )Q data [2] $end +$var wire 1 *Q data_inv [0] $end +$var wire 1 +Q data_inv [1] $end +$var wire 1 ,Q data_inv [2] $end + +$scope module U8 $end +$var wire 1 *Q Y $end +$var wire 1 'Q A $end +$var supply1 1 UQ VPWR $end +$var supply0 1 VQ VGND $end +$var supply1 1 WQ VPB $end +$var supply0 1 XQ VNB $end + +$scope module base $end +$var wire 1 *Q Y $end +$var wire 1 'Q A $end +$var wire 1 YQ not0_out_Y $end +$upscope $end +$upscope $end + +$scope module U9 $end +$var wire 1 (Q Y $end +$var wire 1 +Q A $end +$var supply1 1 ZQ VPWR $end +$var supply0 1 [Q VGND $end +$var supply1 1 \Q VPB $end +$var supply0 1 ]Q VNB $end + +$scope module base $end +$var wire 1 (Q Y $end +$var wire 1 +Q A $end +$var wire 1 ^Q not0_out_Y $end +$upscope $end +$upscope $end + +$scope module U10 $end +$var wire 1 +Q Y $end +$var wire 1 @L A $end +$var wire 1 ,Q B $end +$var supply1 1 _Q VPWR $end +$var supply0 1 `Q VGND $end +$var supply1 1 aQ VPB $end +$var supply0 1 bQ VNB $end + +$scope module base $end +$var wire 1 +Q Y $end +$var wire 1 @L A $end +$var wire 1 ,Q B $end +$var wire 1 cQ nand0_out_Y $end +$upscope $end +$upscope $end + +$scope module U11 $end +$var wire 1 ,Q Y $end +$var wire 1 )Q A $end +$var supply1 1 dQ VPWR $end +$var supply0 1 eQ VGND $end +$var supply1 1 fQ VPB $end +$var supply0 1 gQ VNB $end + +$scope module base $end +$var wire 1 ,Q Y $end +$var wire 1 )Q A $end +$var wire 1 hQ not0_out_Y $end +$upscope $end +$upscope $end + +$scope module U12 $end +$var wire 1 'Q Y $end +$var wire 1 )Q A $end +$var wire 1 @L B $end +$var supply1 1 iQ VPWR $end +$var supply0 1 jQ VGND $end +$var supply1 1 kQ VPB $end +$var supply0 1 lQ VNB $end + +$scope module base $end +$var wire 1 'Q Y $end +$var wire 1 )Q A $end +$var wire 1 @L B $end +$var wire 1 mQ nor0_out_Y $end +$upscope $end +$upscope $end + +$scope module FTB_6__5 $end +$var wire 1 )Q X $end +$var wire 1 AL A $end +$var supply1 1 nQ VPWR $end +$var supply0 1 oQ VGND $end +$var supply1 1 pQ VPB $end +$var supply0 1 qQ VNB $end + +$scope module base $end +$var wire 1 )Q X $end +$var wire 1 AL A $end +$var wire 1 rQ buf0_out_X $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mux_l1_in_0_ $end +$var wire 1 SH in [0] $end +$var wire 1 ^H in [1] $end +$var wire 1 iH in [2] $end +$var wire 1 !Q mem [0] $end +$var wire 1 "Q mem [1] $end +$var wire 1 #Q mem [2] $end +$var wire 1 $Q mem_inv [0] $end +$var wire 1 %Q mem_inv [1] $end +$var wire 1 &Q mem_inv [2] $end +$var wire 1 .Q out [0] $end + +$scope module scs8hd_muxinv3_1_0 $end +$var wire 1 .Q Z $end +$var wire 1 SH Q1 $end +$var wire 1 ^H Q2 $end +$var wire 1 iH Q3 $end +$var wire 1 !Q S0 $end +$var wire 1 $Q S0B $end +$var wire 1 "Q S1 $end +$var wire 1 %Q S1B $end +$var wire 1 #Q S2 $end +$var wire 1 &Q S2B $end +$var wire 1 sQ Q1__bar $end +$var wire 1 tQ Q2__bar $end +$var wire 1 uQ Q3__bar $end +$upscope $end +$upscope $end + +$scope module mux_l1_in_1_ $end +$var wire 1 5I in [0] $end +$var wire 1 ;I in [1] $end +$var wire 1 2J in [2] $end +$var wire 1 !Q mem [0] $end +$var wire 1 "Q mem [1] $end +$var wire 1 #Q mem [2] $end +$var wire 1 $Q mem_inv [0] $end +$var wire 1 %Q mem_inv [1] $end +$var wire 1 &Q mem_inv [2] $end +$var wire 1 /Q out [0] $end + +$scope module scs8hd_muxinv3_1_0 $end +$var wire 1 /Q Z $end +$var wire 1 5I Q1 $end +$var wire 1 ;I Q2 $end +$var wire 1 2J Q3 $end +$var wire 1 !Q S0 $end +$var wire 1 $Q S0B $end +$var wire 1 "Q S1 $end +$var wire 1 %Q S1B $end +$var wire 1 #Q S2 $end +$var wire 1 &Q S2B $end +$var wire 1 vQ Q1__bar $end +$var wire 1 wQ Q2__bar $end +$var wire 1 xQ Q3__bar $end +$upscope $end +$upscope $end + +$scope module mux_l2_in_0_ $end +$var wire 1 .Q in [0] $end +$var wire 1 /Q in [1] $end +$var wire 1 -Q in [2] $end +$var wire 1 'Q mem [0] $end +$var wire 1 (Q mem [1] $end +$var wire 1 )Q mem [2] $end +$var wire 1 *Q mem_inv [0] $end +$var wire 1 +Q mem_inv [1] $end +$var wire 1 ,Q mem_inv [2] $end +$var wire 1 0Q out [0] $end + +$scope module scs8hd_muxinv3_1_0 $end +$var wire 1 0Q Z $end +$var wire 1 .Q Q1 $end +$var wire 1 /Q Q2 $end +$var wire 1 -Q Q3 $end +$var wire 1 'Q S0 $end +$var wire 1 *Q S0B $end +$var wire 1 (Q S1 $end +$var wire 1 +Q S1B $end +$var wire 1 )Q S2 $end +$var wire 1 ,Q S2B $end +$var wire 1 yQ Q1__bar $end +$var wire 1 zQ Q2__bar $end +$var wire 1 {Q Q3__bar $end +$upscope $end +$upscope $end + +$scope module mux_l1_in_2_ $end +$var wire 1 AJ in [0] $end +$var wire 1 1Q in [1] $end +$var wire 1 !Q mem [0] $end +$var wire 1 "Q mem [1] $end +$var wire 1 $Q mem_inv [0] $end +$var wire 1 %Q mem_inv [1] $end +$var wire 1 -Q out [0] $end +$var wire 1 ,M p0 $end + +$scope module scs8hd_muxinv2_1_0 $end +$var wire 1 -Q Z $end +$var wire 1 AJ Q1 $end +$var wire 1 ,M Q2 $end +$var wire 1 !Q S0 $end +$var wire 1 $Q S0B $end +$var wire 1 "Q S1 $end +$var wire 1 %Q S1B $end +$var wire 1 |Q Q1__bar $end +$var wire 1 }Q Q2__bar $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mux_right_track_20 $end +$var wire 1 TH in [0] $end +$var wire 1 _H in [1] $end +$var wire 1 jH in [2] $end +$var wire 1 6I in [3] $end +$var wire 1 R VNB $end + +$scope module base $end +$var wire 1 !R Y $end +$var wire 1 $R A $end +$var wire 1 ?R not0_out_Y $end +$upscope $end +$upscope $end + +$scope module U10 $end +$var wire 1 $R Y $end +$var wire 1 BL A $end +$var wire 1 %R B $end +$var supply1 1 @R VPWR $end +$var supply0 1 AR VGND $end +$var supply1 1 BR VPB $end +$var supply0 1 CR VNB $end + +$scope module base $end +$var wire 1 $R Y $end +$var wire 1 BL A $end +$var wire 1 %R B $end +$var wire 1 DR nand0_out_Y $end +$upscope $end +$upscope $end + +$scope module U11 $end +$var wire 1 %R Y $end +$var wire 1 "R A $end +$var supply1 1 ER VPWR $end +$var supply0 1 FR VGND $end +$var supply1 1 GR VPB $end +$var supply0 1 HR VNB $end + +$scope module base $end +$var wire 1 %R Y $end +$var wire 1 "R A $end +$var wire 1 IR not0_out_Y $end +$upscope $end +$upscope $end + +$scope module U12 $end +$var wire 1 ~Q Y $end +$var wire 1 "R A $end +$var wire 1 BL B $end +$var supply1 1 JR VPWR $end +$var supply0 1 KR VGND $end +$var supply1 1 LR VPB $end +$var supply0 1 MR VNB $end + +$scope module base $end +$var wire 1 ~Q Y $end +$var wire 1 "R A $end +$var wire 1 BL B $end +$var wire 1 NR nor0_out_Y $end +$upscope $end +$upscope $end + +$scope module FTB_7__6 $end +$var wire 1 "R X $end +$var wire 1 CL A $end +$var supply1 1 OR VPWR $end +$var supply0 1 PR VGND $end +$var supply1 1 QR VPB $end +$var supply0 1 RR VNB $end + +$scope module base $end +$var wire 1 "R X $end +$var wire 1 CL A $end +$var wire 1 SR buf0_out_X $end +$upscope $end +$upscope $end +$upscope $end + +$scope module local_encoder2to3_1_ $end +$var wire 1 DL addr [0] $end +$var wire 1 EL addr [1] $end +$var wire 1 &R data [0] $end +$var wire 1 'R data [1] $end +$var wire 1 (R data [2] $end +$var wire 1 )R data_inv [0] $end +$var wire 1 *R data_inv [1] $end +$var wire 1 +R data_inv [2] $end + +$scope module U8 $end +$var wire 1 )R Y $end +$var wire 1 &R A $end +$var supply1 1 TR VPWR $end +$var supply0 1 UR VGND $end +$var supply1 1 VR VPB $end +$var supply0 1 WR VNB $end + +$scope module base $end +$var wire 1 )R Y $end +$var wire 1 &R A $end +$var wire 1 XR not0_out_Y $end +$upscope $end +$upscope $end + +$scope module U9 $end +$var wire 1 'R Y $end +$var wire 1 *R A $end +$var supply1 1 YR VPWR $end +$var supply0 1 ZR VGND $end +$var supply1 1 [R VPB $end +$var supply0 1 \R VNB $end + +$scope module base $end +$var wire 1 'R Y $end +$var wire 1 *R A $end +$var wire 1 ]R not0_out_Y $end +$upscope $end +$upscope $end + +$scope module U10 $end +$var wire 1 *R Y $end +$var wire 1 DL A $end +$var wire 1 +R B $end +$var supply1 1 ^R VPWR $end +$var supply0 1 _R VGND $end +$var supply1 1 `R VPB $end +$var supply0 1 aR VNB $end + +$scope module base $end +$var wire 1 *R Y $end +$var wire 1 DL A $end +$var wire 1 +R B $end +$var wire 1 bR nand0_out_Y $end +$upscope $end +$upscope $end + +$scope module U11 $end +$var wire 1 +R Y $end +$var wire 1 (R A $end +$var supply1 1 cR VPWR $end +$var supply0 1 dR VGND $end +$var supply1 1 eR VPB $end +$var supply0 1 fR VNB $end + +$scope module base $end +$var wire 1 +R Y $end +$var wire 1 (R A $end +$var wire 1 gR not0_out_Y $end +$upscope $end +$upscope $end + +$scope module U12 $end +$var wire 1 &R Y $end +$var wire 1 (R A $end +$var wire 1 DL B $end +$var supply1 1 hR VPWR $end +$var supply0 1 iR VGND $end +$var supply1 1 jR VPB $end +$var supply0 1 kR VNB $end + +$scope module base $end +$var wire 1 &R Y $end +$var wire 1 (R A $end +$var wire 1 DL B $end +$var wire 1 lR nor0_out_Y $end +$upscope $end +$upscope $end + +$scope module FTB_8__7 $end +$var wire 1 (R X $end +$var wire 1 EL A $end +$var supply1 1 mR VPWR $end +$var supply0 1 nR VGND $end +$var supply1 1 oR VPB $end +$var supply0 1 pR VNB $end + +$scope module base $end +$var wire 1 (R X $end +$var wire 1 EL A $end +$var wire 1 qR buf0_out_X $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mux_l1_in_0_ $end +$var wire 1 TH in [0] $end +$var wire 1 _H in [1] $end +$var wire 1 jH in [2] $end +$var wire 1 ~Q mem [0] $end +$var wire 1 !R mem [1] $end +$var wire 1 "R mem [2] $end +$var wire 1 #R mem_inv [0] $end +$var wire 1 $R mem_inv [1] $end +$var wire 1 %R mem_inv [2] $end +$var wire 1 -R out [0] $end + +$scope module scs8hd_muxinv3_1_0 $end +$var wire 1 -R Z $end +$var wire 1 TH Q1 $end +$var wire 1 _H Q2 $end +$var wire 1 jH Q3 $end +$var wire 1 ~Q S0 $end +$var wire 1 #R S0B $end +$var wire 1 !R S1 $end +$var wire 1 $R S1B $end +$var wire 1 "R S2 $end +$var wire 1 %R S2B $end +$var wire 1 rR Q1__bar $end +$var wire 1 sR Q2__bar $end +$var wire 1 tR Q3__bar $end +$upscope $end +$upscope $end + +$scope module mux_l1_in_1_ $end +$var wire 1 6I in [0] $end +$var wire 1 S VNB $end + +$scope module base $end +$var wire 1 #S Y $end +$var wire 1 FL A $end +$var wire 1 $S B $end +$var wire 1 ?S nand0_out_Y $end +$upscope $end +$upscope $end + +$scope module U11 $end +$var wire 1 $S Y $end +$var wire 1 !S A $end +$var supply1 1 @S VPWR $end +$var supply0 1 AS VGND $end +$var supply1 1 BS VPB $end +$var supply0 1 CS VNB $end + +$scope module base $end +$var wire 1 $S Y $end +$var wire 1 !S A $end +$var wire 1 DS not0_out_Y $end +$upscope $end +$upscope $end + +$scope module U12 $end +$var wire 1 }R Y $end +$var wire 1 !S A $end +$var wire 1 FL B $end +$var supply1 1 ES VPWR $end +$var supply0 1 FS VGND $end +$var supply1 1 GS VPB $end +$var supply0 1 HS VNB $end + +$scope module base $end +$var wire 1 }R Y $end +$var wire 1 !S A $end +$var wire 1 FL B $end +$var wire 1 IS nor0_out_Y $end +$upscope $end +$upscope $end + +$scope module FTB_9__8 $end +$var wire 1 !S X $end +$var wire 1 GL A $end +$var supply1 1 JS VPWR $end +$var supply0 1 KS VGND $end +$var supply1 1 LS VPB $end +$var supply0 1 MS VNB $end + +$scope module base $end +$var wire 1 !S X $end +$var wire 1 GL A $end +$var wire 1 NS buf0_out_X $end +$upscope $end +$upscope $end +$upscope $end + +$scope module local_encoder2to3_1_ $end +$var wire 1 HL addr [0] $end +$var wire 1 IL addr [1] $end +$var wire 1 %S data [0] $end +$var wire 1 &S data [1] $end +$var wire 1 'S data [2] $end +$var wire 1 (S data_inv [0] $end +$var wire 1 )S data_inv [1] $end +$var wire 1 *S data_inv [2] $end + +$scope module U8 $end +$var wire 1 (S Y $end +$var wire 1 %S A $end +$var supply1 1 OS VPWR $end +$var supply0 1 PS VGND $end +$var supply1 1 QS VPB $end +$var supply0 1 RS VNB $end + +$scope module base $end +$var wire 1 (S Y $end +$var wire 1 %S A $end +$var wire 1 SS not0_out_Y $end +$upscope $end +$upscope $end + +$scope module U9 $end +$var wire 1 &S Y $end +$var wire 1 )S A $end +$var supply1 1 TS VPWR $end +$var supply0 1 US VGND $end +$var supply1 1 VS VPB $end +$var supply0 1 WS VNB $end + +$scope module base $end +$var wire 1 &S Y $end +$var wire 1 )S A $end +$var wire 1 XS not0_out_Y $end +$upscope $end +$upscope $end + +$scope module U10 $end +$var wire 1 )S Y $end +$var wire 1 HL A $end +$var wire 1 *S B $end +$var supply1 1 YS VPWR $end +$var supply0 1 ZS VGND $end +$var supply1 1 [S VPB $end +$var supply0 1 \S VNB $end + +$scope module base $end +$var wire 1 )S Y $end +$var wire 1 HL A $end +$var wire 1 *S B $end +$var wire 1 ]S nand0_out_Y $end +$upscope $end +$upscope $end + +$scope module U11 $end +$var wire 1 *S Y $end +$var wire 1 'S A $end +$var supply1 1 ^S VPWR $end +$var supply0 1 _S VGND $end +$var supply1 1 `S VPB $end +$var supply0 1 aS VNB $end + +$scope module base $end +$var wire 1 *S Y $end +$var wire 1 'S A $end +$var wire 1 bS not0_out_Y $end +$upscope $end +$upscope $end + +$scope module U12 $end +$var wire 1 %S Y $end +$var wire 1 'S A $end +$var wire 1 HL B $end +$var supply1 1 cS VPWR $end +$var supply0 1 dS VGND $end +$var supply1 1 eS VPB $end +$var supply0 1 fS VNB $end + +$scope module base $end +$var wire 1 %S Y $end +$var wire 1 'S A $end +$var wire 1 HL B $end +$var wire 1 gS nor0_out_Y $end +$upscope $end +$upscope $end + +$scope module FTB_10__9 $end +$var wire 1 'S X $end +$var wire 1 IL A $end +$var supply1 1 hS VPWR $end +$var supply0 1 iS VGND $end +$var supply1 1 jS VPB $end +$var supply0 1 kS VNB $end + +$scope module base $end +$var wire 1 'S X $end +$var wire 1 IL A $end +$var wire 1 lS buf0_out_X $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mux_l1_in_0_ $end +$var wire 1 UH in [0] $end +$var wire 1 `H in [1] $end +$var wire 1 kH in [2] $end +$var wire 1 }R mem [0] $end +$var wire 1 ~R mem [1] $end +$var wire 1 !S mem [2] $end +$var wire 1 "S mem_inv [0] $end +$var wire 1 #S mem_inv [1] $end +$var wire 1 $S mem_inv [2] $end +$var wire 1 ,S out [0] $end + +$scope module scs8hd_muxinv3_1_0 $end +$var wire 1 ,S Z $end +$var wire 1 UH Q1 $end +$var wire 1 `H Q2 $end +$var wire 1 kH Q3 $end +$var wire 1 }R S0 $end +$var wire 1 "S S0B $end +$var wire 1 ~R S1 $end +$var wire 1 #S S1B $end +$var wire 1 !S S2 $end +$var wire 1 $S S2B $end +$var wire 1 mS Q1__bar $end +$var wire 1 nS Q2__bar $end +$var wire 1 oS Q3__bar $end +$upscope $end +$upscope $end + +$scope module mux_l1_in_1_ $end +$var wire 1 7I in [0] $end +$var wire 1 =I in [1] $end +$var wire 1 5J in [2] $end +$var wire 1 }R mem [0] $end +$var wire 1 ~R mem [1] $end +$var wire 1 !S mem [2] $end +$var wire 1 "S mem_inv [0] $end +$var wire 1 #S mem_inv [1] $end +$var wire 1 $S mem_inv [2] $end +$var wire 1 -S out [0] $end + +$scope module scs8hd_muxinv3_1_0 $end +$var wire 1 -S Z $end +$var wire 1 7I Q1 $end +$var wire 1 =I Q2 $end +$var wire 1 5J Q3 $end +$var wire 1 }R S0 $end +$var wire 1 "S S0B $end +$var wire 1 ~R S1 $end +$var wire 1 #S S1B $end +$var wire 1 !S S2 $end +$var wire 1 $S S2B $end +$var wire 1 pS Q1__bar $end +$var wire 1 qS Q2__bar $end +$var wire 1 rS Q3__bar $end +$upscope $end +$upscope $end + +$scope module mux_l2_in_0_ $end +$var wire 1 ,S in [0] $end +$var wire 1 -S in [1] $end +$var wire 1 +S in [2] $end +$var wire 1 %S mem [0] $end +$var wire 1 &S mem [1] $end +$var wire 1 'S mem [2] $end +$var wire 1 (S mem_inv [0] $end +$var wire 1 )S mem_inv [1] $end +$var wire 1 *S mem_inv [2] $end +$var wire 1 .S out [0] $end + +$scope module scs8hd_muxinv3_1_0 $end +$var wire 1 .S Z $end +$var wire 1 ,S Q1 $end +$var wire 1 -S Q2 $end +$var wire 1 +S Q3 $end +$var wire 1 %S S0 $end +$var wire 1 (S S0B $end +$var wire 1 &S S1 $end +$var wire 1 )S S1B $end +$var wire 1 'S S2 $end +$var wire 1 *S S2B $end +$var wire 1 sS Q1__bar $end +$var wire 1 tS Q2__bar $end +$var wire 1 uS Q3__bar $end +$upscope $end +$upscope $end + +$scope module mux_l1_in_2_ $end +$var wire 1 CJ in [0] $end +$var wire 1 /S in [1] $end +$var wire 1 }R mem [0] $end +$var wire 1 ~R mem [1] $end +$var wire 1 "S mem_inv [0] $end +$var wire 1 #S mem_inv [1] $end +$var wire 1 +S out [0] $end +$var wire 1 9M p0 $end + +$scope module scs8hd_muxinv2_1_0 $end +$var wire 1 +S Z $end +$var wire 1 CJ Q1 $end +$var wire 1 9M Q2 $end +$var wire 1 }R S0 $end +$var wire 1 "S S0B $end +$var wire 1 ~R S1 $end +$var wire 1 #S S1B $end +$var wire 1 vS Q1__bar $end +$var wire 1 wS Q2__bar $end +$upscope $end +$upscope $end + +$scope module BINV_R_147 $end +$var wire 1 4J Y $end +$var wire 1 0S A $end +$var supply1 1 xS VPWR $end +$var supply0 1 yS VGND $end +$var supply1 1 zS VPB $end +$var supply0 1 {S VNB $end + +$scope module base $end +$var wire 1 4J Y $end +$var wire 1 0S A $end +$var wire 1 |S not0_out_Y $end +$upscope $end +$upscope $end + +$scope module BINV_R_148 $end +$var wire 1 0S Y $end +$var wire 1 .S A $end +$var supply1 1 }S VPWR $end +$var supply0 1 ~S VGND $end +$var supply1 1 !T VPB $end +$var supply0 1 "T VNB $end + +$scope module base $end +$var wire 1 0S Y $end +$var wire 1 .S A $end +$var wire 1 #T not0_out_Y $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mux_left_track_3 $end +$var wire 1 YH in [0] $end +$var wire 1 dH in [1] $end +$var wire 1 KJ in [2] $end +$var wire 1 YJ in [3] $end +$var wire 1 ]I in [4] $end +$var wire 1 `I in [5] $end +$var wire 1 cI in [6] $end +$var wire 1 JL sram [0] $end +$var wire 1 KL sram [1] $end +$var wire 1 LL sram [2] $end +$var wire 1 ML sram [3] $end +$var wire 1 >M sram_inv [0] $end +$var wire 1 ?M sram_inv [1] $end +$var wire 1 @M sram_inv [2] $end +$var wire 1 AM sram_inv [3] $end +$var wire 1 EJ out [0] $end +$var wire 1 BM p0 $end +$var wire 1 $T local_encoder2to3_0_data [0] $end +$var wire 1 %T local_encoder2to3_0_data [1] $end +$var wire 1 &T local_encoder2to3_0_data [2] $end +$var wire 1 'T local_encoder2to3_0_data_inv [0] $end +$var wire 1 (T local_encoder2to3_0_data_inv [1] $end +$var wire 1 )T local_encoder2to3_0_data_inv [2] $end +$var wire 1 *T local_encoder2to3_1_data [0] $end +$var wire 1 +T local_encoder2to3_1_data [1] $end +$var wire 1 ,T local_encoder2to3_1_data [2] $end +$var wire 1 -T local_encoder2to3_1_data_inv [0] $end +$var wire 1 .T local_encoder2to3_1_data_inv [1] $end +$var wire 1 /T local_encoder2to3_1_data_inv [2] $end +$var wire 1 0T mux_2level_tapbuf_basis_input2_mem2_0_out [0] $end +$var wire 1 1T mux_2level_tapbuf_basis_input3_mem3_0_out [0] $end +$var wire 1 2T mux_2level_tapbuf_basis_input3_mem3_1_out [0] $end +$var wire 1 3T mux_2level_tapbuf_basis_input3_mem3_2_out [0] $end +$var wire 1 4T SYNOPSYS_UNCONNECTED_1 $end + +$scope module sky130_fd_sc_hd__buf_4_0_ $end +$var wire 1 EJ X $end +$var wire 1 3T A $end +$var supply1 1 5T VPWR $end +$var supply0 1 6T VGND $end +$var supply1 1 7T VPB $end +$var supply0 1 8T VNB $end + +$scope module base $end +$var wire 1 EJ X $end +$var wire 1 3T A $end +$var wire 1 9T buf0_out_X $end +$upscope $end +$upscope $end + +$scope module local_encoder2to3_0_ $end +$var wire 1 JL addr [0] $end +$var wire 1 KL addr [1] $end +$var wire 1 $T data [0] $end +$var wire 1 %T data [1] $end +$var wire 1 &T data [2] $end +$var wire 1 'T data_inv [0] $end +$var wire 1 (T data_inv [1] $end +$var wire 1 )T data_inv [2] $end + +$scope module U8 $end +$var wire 1 'T Y $end +$var wire 1 $T A $end +$var supply1 1 :T VPWR $end +$var supply0 1 ;T VGND $end +$var supply1 1 T not0_out_Y $end +$upscope $end +$upscope $end + +$scope module U9 $end +$var wire 1 %T Y $end +$var wire 1 (T A $end +$var supply1 1 ?T VPWR $end +$var supply0 1 @T VGND $end +$var supply1 1 AT VPB $end +$var supply0 1 BT VNB $end + +$scope module base $end +$var wire 1 %T Y $end +$var wire 1 (T A $end +$var wire 1 CT not0_out_Y $end +$upscope $end +$upscope $end + +$scope module U10 $end +$var wire 1 (T Y $end +$var wire 1 JL A $end +$var wire 1 )T B $end +$var supply1 1 DT VPWR $end +$var supply0 1 ET VGND $end +$var supply1 1 FT VPB $end +$var supply0 1 GT VNB $end + +$scope module base $end +$var wire 1 (T Y $end +$var wire 1 JL A $end +$var wire 1 )T B $end +$var wire 1 HT nand0_out_Y $end +$upscope $end +$upscope $end + +$scope module U11 $end +$var wire 1 )T Y $end +$var wire 1 &T A $end +$var supply1 1 IT VPWR $end +$var supply0 1 JT VGND $end +$var supply1 1 KT VPB $end +$var supply0 1 LT VNB $end + +$scope module base $end +$var wire 1 )T Y $end +$var wire 1 &T A $end +$var wire 1 MT not0_out_Y $end +$upscope $end +$upscope $end + +$scope module U12 $end +$var wire 1 $T Y $end +$var wire 1 &T A $end +$var wire 1 JL B $end +$var supply1 1 NT VPWR $end +$var supply0 1 OT VGND $end +$var supply1 1 PT VPB $end +$var supply0 1 QT VNB $end + +$scope module base $end +$var wire 1 $T Y $end +$var wire 1 &T A $end +$var wire 1 JL B $end +$var wire 1 RT nor0_out_Y $end +$upscope $end +$upscope $end + +$scope module FTB_11__10 $end +$var wire 1 &T X $end +$var wire 1 KL A $end +$var supply1 1 ST VPWR $end +$var supply0 1 TT VGND $end +$var supply1 1 UT VPB $end +$var supply0 1 VT VNB $end + +$scope module base $end +$var wire 1 &T X $end +$var wire 1 KL A $end +$var wire 1 WT buf0_out_X $end +$upscope $end +$upscope $end +$upscope $end + +$scope module local_encoder2to3_1_ $end +$var wire 1 LL addr [0] $end +$var wire 1 ML addr [1] $end +$var wire 1 *T data [0] $end +$var wire 1 +T data [1] $end +$var wire 1 ,T data [2] $end +$var wire 1 -T data_inv [0] $end +$var wire 1 .T data_inv [1] $end +$var wire 1 /T data_inv [2] $end + +$scope module U8 $end +$var wire 1 -T Y $end +$var wire 1 *T A $end +$var supply1 1 XT VPWR $end +$var supply0 1 YT VGND $end +$var supply1 1 ZT VPB $end +$var supply0 1 [T VNB $end + +$scope module base $end +$var wire 1 -T Y $end +$var wire 1 *T A $end +$var wire 1 \T not0_out_Y $end +$upscope $end +$upscope $end + +$scope module U9 $end +$var wire 1 +T Y $end +$var wire 1 .T A $end +$var supply1 1 ]T VPWR $end +$var supply0 1 ^T VGND $end +$var supply1 1 _T VPB $end +$var supply0 1 `T VNB $end + +$scope module base $end +$var wire 1 +T Y $end +$var wire 1 .T A $end +$var wire 1 aT not0_out_Y $end +$upscope $end +$upscope $end + +$scope module U10 $end +$var wire 1 .T Y $end +$var wire 1 LL A $end +$var wire 1 /T B $end +$var supply1 1 bT VPWR $end +$var supply0 1 cT VGND $end +$var supply1 1 dT VPB $end +$var supply0 1 eT VNB $end + +$scope module base $end +$var wire 1 .T Y $end +$var wire 1 LL A $end +$var wire 1 /T B $end +$var wire 1 fT nand0_out_Y $end +$upscope $end +$upscope $end + +$scope module U11 $end +$var wire 1 /T Y $end +$var wire 1 ,T A $end +$var supply1 1 gT VPWR $end +$var supply0 1 hT VGND $end +$var supply1 1 iT VPB $end +$var supply0 1 jT VNB $end + +$scope module base $end +$var wire 1 /T Y $end +$var wire 1 ,T A $end +$var wire 1 kT not0_out_Y $end +$upscope $end +$upscope $end + +$scope module U12 $end +$var wire 1 *T Y $end +$var wire 1 ,T A $end +$var wire 1 LL B $end +$var supply1 1 lT VPWR $end +$var supply0 1 mT VGND $end +$var supply1 1 nT VPB $end +$var supply0 1 oT VNB $end + +$scope module base $end +$var wire 1 *T Y $end +$var wire 1 ,T A $end +$var wire 1 LL B $end +$var wire 1 pT nor0_out_Y $end +$upscope $end +$upscope $end + +$scope module FTB_12__11 $end +$var wire 1 ,T X $end +$var wire 1 ML A $end +$var supply1 1 qT VPWR $end +$var supply0 1 rT VGND $end +$var supply1 1 sT VPB $end +$var supply0 1 tT VNB $end + +$scope module base $end +$var wire 1 ,T X $end +$var wire 1 ML A $end +$var wire 1 uT buf0_out_X $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mux_l1_in_0_ $end +$var wire 1 YH in [0] $end +$var wire 1 dH in [1] $end +$var wire 1 KJ in [2] $end +$var wire 1 $T mem [0] $end +$var wire 1 %T mem [1] $end +$var wire 1 &T mem [2] $end +$var wire 1 'T mem_inv [0] $end +$var wire 1 (T mem_inv [1] $end +$var wire 1 )T mem_inv [2] $end +$var wire 1 1T out [0] $end + +$scope module scs8hd_muxinv3_1_0 $end +$var wire 1 1T Z $end +$var wire 1 YH Q1 $end +$var wire 1 dH Q2 $end +$var wire 1 KJ Q3 $end +$var wire 1 $T S0 $end +$var wire 1 'T S0B $end +$var wire 1 %T S1 $end +$var wire 1 (T S1B $end +$var wire 1 &T S2 $end +$var wire 1 )T S2B $end +$var wire 1 vT Q1__bar $end +$var wire 1 wT Q2__bar $end +$var wire 1 xT Q3__bar $end +$upscope $end +$upscope $end + +$scope module mux_l1_in_1_ $end +$var wire 1 YJ in [0] $end +$var wire 1 ]I in [1] $end +$var wire 1 `I in [2] $end +$var wire 1 $T mem [0] $end +$var wire 1 %T mem [1] $end +$var wire 1 &T mem [2] $end +$var wire 1 'T mem_inv [0] $end +$var wire 1 (T mem_inv [1] $end +$var wire 1 )T mem_inv [2] $end +$var wire 1 2T out [0] $end + +$scope module scs8hd_muxinv3_1_0 $end +$var wire 1 2T Z $end +$var wire 1 YJ Q1 $end +$var wire 1 ]I Q2 $end +$var wire 1 `I Q3 $end +$var wire 1 $T S0 $end +$var wire 1 'T S0B $end +$var wire 1 %T S1 $end +$var wire 1 (T S1B $end +$var wire 1 &T S2 $end +$var wire 1 )T S2B $end +$var wire 1 yT Q1__bar $end +$var wire 1 zT Q2__bar $end +$var wire 1 {T Q3__bar $end +$upscope $end +$upscope $end + +$scope module mux_l2_in_0_ $end +$var wire 1 1T in [0] $end +$var wire 1 2T in [1] $end +$var wire 1 0T in [2] $end +$var wire 1 *T mem [0] $end +$var wire 1 +T mem [1] $end +$var wire 1 ,T mem [2] $end +$var wire 1 -T mem_inv [0] $end +$var wire 1 .T mem_inv [1] $end +$var wire 1 /T mem_inv [2] $end +$var wire 1 3T out [0] $end + +$scope module scs8hd_muxinv3_1_0 $end +$var wire 1 3T Z $end +$var wire 1 1T Q1 $end +$var wire 1 2T Q2 $end +$var wire 1 0T Q3 $end +$var wire 1 *T S0 $end +$var wire 1 -T S0B $end +$var wire 1 +T S1 $end +$var wire 1 .T S1B $end +$var wire 1 ,T S2 $end +$var wire 1 /T S2B $end +$var wire 1 |T Q1__bar $end +$var wire 1 }T Q2__bar $end +$var wire 1 ~T Q3__bar $end +$upscope $end +$upscope $end + +$scope module mux_l1_in_2_ $end +$var wire 1 cI in [0] $end +$var wire 1 4T in [1] $end +$var wire 1 $T mem [0] $end +$var wire 1 %T mem [1] $end +$var wire 1 'T mem_inv [0] $end +$var wire 1 (T mem_inv [1] $end +$var wire 1 0T out [0] $end +$var wire 1 BM p0 $end + +$scope module scs8hd_muxinv2_1_0 $end +$var wire 1 0T Z $end +$var wire 1 cI Q1 $end +$var wire 1 BM Q2 $end +$var wire 1 $T S0 $end +$var wire 1 'T S0B $end +$var wire 1 %T S1 $end +$var wire 1 (T S1B $end +$var wire 1 !U Q1__bar $end +$var wire 1 "U Q2__bar $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mux_left_track_5 $end +$var wire 1 XH in [0] $end +$var wire 1 cH in [1] $end +$var wire 1 LJ in [2] $end +$var wire 1 [J in [3] $end +$var wire 1 ^I in [4] $end +$var wire 1 aI in [5] $end +$var wire 1 dI in [6] $end +$var wire 1 NL sram [0] $end +$var wire 1 OL sram [1] $end +$var wire 1 PL sram [2] $end +$var wire 1 QL sram [3] $end +$var wire 1 CM sram_inv [0] $end +$var wire 1 DM sram_inv [1] $end +$var wire 1 EM sram_inv [2] $end +$var wire 1 FM sram_inv [3] $end +$var wire 1 FJ out [0] $end +$var wire 1 GM p0 $end +$var wire 1 #U local_encoder2to3_0_data [0] $end +$var wire 1 $U local_encoder2to3_0_data [1] $end +$var wire 1 %U local_encoder2to3_0_data [2] $end +$var wire 1 &U local_encoder2to3_0_data_inv [0] $end +$var wire 1 'U local_encoder2to3_0_data_inv [1] $end +$var wire 1 (U local_encoder2to3_0_data_inv [2] $end +$var wire 1 )U local_encoder2to3_1_data [0] $end +$var wire 1 *U local_encoder2to3_1_data [1] $end +$var wire 1 +U local_encoder2to3_1_data [2] $end +$var wire 1 ,U local_encoder2to3_1_data_inv [0] $end +$var wire 1 -U local_encoder2to3_1_data_inv [1] $end +$var wire 1 .U local_encoder2to3_1_data_inv [2] $end +$var wire 1 /U mux_2level_tapbuf_basis_input2_mem2_0_out [0] $end +$var wire 1 0U mux_2level_tapbuf_basis_input3_mem3_0_out [0] $end +$var wire 1 1U mux_2level_tapbuf_basis_input3_mem3_1_out [0] $end +$var wire 1 2U mux_2level_tapbuf_basis_input3_mem3_2_out [0] $end +$var wire 1 3U SYNOPSYS_UNCONNECTED_1 $end + +$scope module sky130_fd_sc_hd__buf_4_0_ $end +$var wire 1 FJ X $end +$var wire 1 2U A $end +$var supply1 1 4U VPWR $end +$var supply0 1 5U VGND $end +$var supply1 1 6U VPB $end +$var supply0 1 7U VNB $end + +$scope module base $end +$var wire 1 FJ X $end +$var wire 1 2U A $end +$var wire 1 8U buf0_out_X $end +$upscope $end +$upscope $end + +$scope module local_encoder2to3_0_ $end +$var wire 1 NL addr [0] $end +$var wire 1 OL addr [1] $end +$var wire 1 #U data [0] $end +$var wire 1 $U data [1] $end +$var wire 1 %U data [2] $end +$var wire 1 &U data_inv [0] $end +$var wire 1 'U data_inv [1] $end +$var wire 1 (U data_inv [2] $end + +$scope module U8 $end +$var wire 1 &U Y $end +$var wire 1 #U A $end +$var supply1 1 9U VPWR $end +$var supply0 1 :U VGND $end +$var supply1 1 ;U VPB $end +$var supply0 1 U VPWR $end +$var supply0 1 ?U VGND $end +$var supply1 1 @U VPB $end +$var supply0 1 AU VNB $end + +$scope module base $end +$var wire 1 $U Y $end +$var wire 1 'U A $end +$var wire 1 BU not0_out_Y $end +$upscope $end +$upscope $end + +$scope module U10 $end +$var wire 1 'U Y $end +$var wire 1 NL A $end +$var wire 1 (U B $end +$var supply1 1 CU VPWR $end +$var supply0 1 DU VGND $end +$var supply1 1 EU VPB $end +$var supply0 1 FU VNB $end + +$scope module base $end +$var wire 1 'U Y $end +$var wire 1 NL A $end +$var wire 1 (U B $end +$var wire 1 GU nand0_out_Y $end +$upscope $end +$upscope $end + +$scope module U11 $end +$var wire 1 (U Y $end +$var wire 1 %U A $end +$var supply1 1 HU VPWR $end +$var supply0 1 IU VGND $end +$var supply1 1 JU VPB $end +$var supply0 1 KU VNB $end + +$scope module base $end +$var wire 1 (U Y $end +$var wire 1 %U A $end +$var wire 1 LU not0_out_Y $end +$upscope $end +$upscope $end + +$scope module U12 $end +$var wire 1 #U Y $end +$var wire 1 %U A $end +$var wire 1 NL B $end +$var supply1 1 MU VPWR $end +$var supply0 1 NU VGND $end +$var supply1 1 OU VPB $end +$var supply0 1 PU VNB $end + +$scope module base $end +$var wire 1 #U Y $end +$var wire 1 %U A $end +$var wire 1 NL B $end +$var wire 1 QU nor0_out_Y $end +$upscope $end +$upscope $end + +$scope module FTB_13__12 $end +$var wire 1 %U X $end +$var wire 1 OL A $end +$var supply1 1 RU VPWR $end +$var supply0 1 SU VGND $end +$var supply1 1 TU VPB $end +$var supply0 1 UU VNB $end + +$scope module base $end +$var wire 1 %U X $end +$var wire 1 OL A $end +$var wire 1 VU buf0_out_X $end +$upscope $end +$upscope $end +$upscope $end + +$scope module local_encoder2to3_1_ $end +$var wire 1 PL addr [0] $end +$var wire 1 QL addr [1] $end +$var wire 1 )U data [0] $end +$var wire 1 *U data [1] $end +$var wire 1 +U data [2] $end +$var wire 1 ,U data_inv [0] $end +$var wire 1 -U data_inv [1] $end +$var wire 1 .U data_inv [2] $end + +$scope module U8 $end +$var wire 1 ,U Y $end +$var wire 1 )U A $end +$var supply1 1 WU VPWR $end +$var supply0 1 XU VGND $end +$var supply1 1 YU VPB $end +$var supply0 1 ZU VNB $end + +$scope module base $end +$var wire 1 ,U Y $end +$var wire 1 )U A $end +$var wire 1 [U not0_out_Y $end +$upscope $end +$upscope $end + +$scope module U9 $end +$var wire 1 *U Y $end +$var wire 1 -U A $end +$var supply1 1 \U VPWR $end +$var supply0 1 ]U VGND $end +$var supply1 1 ^U VPB $end +$var supply0 1 _U VNB $end + +$scope module base $end +$var wire 1 *U Y $end +$var wire 1 -U A $end +$var wire 1 `U not0_out_Y $end +$upscope $end +$upscope $end + +$scope module U10 $end +$var wire 1 -U Y $end +$var wire 1 PL A $end +$var wire 1 .U B $end +$var supply1 1 aU VPWR $end +$var supply0 1 bU VGND $end +$var supply1 1 cU VPB $end +$var supply0 1 dU VNB $end + +$scope module base $end +$var wire 1 -U Y $end +$var wire 1 PL A $end +$var wire 1 .U B $end +$var wire 1 eU nand0_out_Y $end +$upscope $end +$upscope $end + +$scope module U11 $end +$var wire 1 .U Y $end +$var wire 1 +U A $end +$var supply1 1 fU VPWR $end +$var supply0 1 gU VGND $end +$var supply1 1 hU VPB $end +$var supply0 1 iU VNB $end + +$scope module base $end +$var wire 1 .U Y $end +$var wire 1 +U A $end +$var wire 1 jU not0_out_Y $end +$upscope $end +$upscope $end + +$scope module U12 $end +$var wire 1 )U Y $end +$var wire 1 +U A $end +$var wire 1 PL B $end +$var supply1 1 kU VPWR $end +$var supply0 1 lU VGND $end +$var supply1 1 mU VPB $end +$var supply0 1 nU VNB $end + +$scope module base $end +$var wire 1 )U Y $end +$var wire 1 +U A $end +$var wire 1 PL B $end +$var wire 1 oU nor0_out_Y $end +$upscope $end +$upscope $end + +$scope module FTB_14__13 $end +$var wire 1 +U X $end +$var wire 1 QL A $end +$var supply1 1 pU VPWR $end +$var supply0 1 qU VGND $end +$var supply1 1 rU VPB $end +$var supply0 1 sU VNB $end + +$scope module base $end +$var wire 1 +U X $end +$var wire 1 QL A $end +$var wire 1 tU buf0_out_X $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mux_l1_in_0_ $end +$var wire 1 XH in [0] $end +$var wire 1 cH in [1] $end +$var wire 1 LJ in [2] $end +$var wire 1 #U mem [0] $end +$var wire 1 $U mem [1] $end +$var wire 1 %U mem [2] $end +$var wire 1 &U mem_inv [0] $end +$var wire 1 'U mem_inv [1] $end +$var wire 1 (U mem_inv [2] $end +$var wire 1 0U out [0] $end + +$scope module scs8hd_muxinv3_1_0 $end +$var wire 1 0U Z $end +$var wire 1 XH Q1 $end +$var wire 1 cH Q2 $end +$var wire 1 LJ Q3 $end +$var wire 1 #U S0 $end +$var wire 1 &U S0B $end +$var wire 1 $U S1 $end +$var wire 1 'U S1B $end +$var wire 1 %U S2 $end +$var wire 1 (U S2B $end +$var wire 1 uU Q1__bar $end +$var wire 1 vU Q2__bar $end +$var wire 1 wU Q3__bar $end +$upscope $end +$upscope $end + +$scope module mux_l1_in_1_ $end +$var wire 1 [J in [0] $end +$var wire 1 ^I in [1] $end +$var wire 1 aI in [2] $end +$var wire 1 #U mem [0] $end +$var wire 1 $U mem [1] $end +$var wire 1 %U mem [2] $end +$var wire 1 &U mem_inv [0] $end +$var wire 1 'U mem_inv [1] $end +$var wire 1 (U mem_inv [2] $end +$var wire 1 1U out [0] $end + +$scope module scs8hd_muxinv3_1_0 $end +$var wire 1 1U Z $end +$var wire 1 [J Q1 $end +$var wire 1 ^I Q2 $end +$var wire 1 aI Q3 $end +$var wire 1 #U S0 $end +$var wire 1 &U S0B $end +$var wire 1 $U S1 $end +$var wire 1 'U S1B $end +$var wire 1 %U S2 $end +$var wire 1 (U S2B $end +$var wire 1 xU Q1__bar $end +$var wire 1 yU Q2__bar $end +$var wire 1 zU Q3__bar $end +$upscope $end +$upscope $end + +$scope module mux_l2_in_0_ $end +$var wire 1 0U in [0] $end +$var wire 1 1U in [1] $end +$var wire 1 /U in [2] $end +$var wire 1 )U mem [0] $end +$var wire 1 *U mem [1] $end +$var wire 1 +U mem [2] $end +$var wire 1 ,U mem_inv [0] $end +$var wire 1 -U mem_inv [1] $end +$var wire 1 .U mem_inv [2] $end +$var wire 1 2U out [0] $end + +$scope module scs8hd_muxinv3_1_0 $end +$var wire 1 2U Z $end +$var wire 1 0U Q1 $end +$var wire 1 1U Q2 $end +$var wire 1 /U Q3 $end +$var wire 1 )U S0 $end +$var wire 1 ,U S0B $end +$var wire 1 *U S1 $end +$var wire 1 -U S1B $end +$var wire 1 +U S2 $end +$var wire 1 .U S2B $end +$var wire 1 {U Q1__bar $end +$var wire 1 |U Q2__bar $end +$var wire 1 }U Q3__bar $end +$upscope $end +$upscope $end + +$scope module mux_l1_in_2_ $end +$var wire 1 dI in [0] $end +$var wire 1 3U in [1] $end +$var wire 1 #U mem [0] $end +$var wire 1 $U mem [1] $end +$var wire 1 &U mem_inv [0] $end +$var wire 1 'U mem_inv [1] $end +$var wire 1 /U out [0] $end +$var wire 1 GM p0 $end + +$scope module scs8hd_muxinv2_1_0 $end +$var wire 1 /U Z $end +$var wire 1 dI Q1 $end +$var wire 1 GM Q2 $end +$var wire 1 #U S0 $end +$var wire 1 &U S0B $end +$var wire 1 $U S1 $end +$var wire 1 'U S1B $end +$var wire 1 ~U Q1__bar $end +$var wire 1 !V Q2__bar $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mux_left_track_13 $end +$var wire 1 UH in [0] $end +$var wire 1 `H in [1] $end +$var wire 1 kH in [2] $end +$var wire 1 PJ in [3] $end +$var wire 1 _J in [4] $end +$var wire 1 \I in [5] $end +$var wire 1 bI in [6] $end +$var wire 1 RL sram [0] $end +$var wire 1 SL sram [1] $end +$var wire 1 TL sram [2] $end +$var wire 1 UL sram [3] $end +$var wire 1 HM sram_inv [0] $end +$var wire 1 IM sram_inv [1] $end +$var wire 1 JM sram_inv [2] $end +$var wire 1 KM sram_inv [3] $end +$var wire 1 JJ out [0] $end +$var wire 1 LM p0 $end +$var wire 1 "V local_encoder2to3_0_data [0] $end +$var wire 1 #V local_encoder2to3_0_data [1] $end +$var wire 1 $V local_encoder2to3_0_data [2] $end +$var wire 1 %V local_encoder2to3_0_data_inv [0] $end +$var wire 1 &V local_encoder2to3_0_data_inv [1] $end +$var wire 1 'V local_encoder2to3_0_data_inv [2] $end +$var wire 1 (V local_encoder2to3_1_data [0] $end +$var wire 1 )V local_encoder2to3_1_data [1] $end +$var wire 1 *V local_encoder2to3_1_data [2] $end +$var wire 1 +V local_encoder2to3_1_data_inv [0] $end +$var wire 1 ,V local_encoder2to3_1_data_inv [1] $end +$var wire 1 -V local_encoder2to3_1_data_inv [2] $end +$var wire 1 .V mux_2level_tapbuf_basis_input2_mem2_0_out [0] $end +$var wire 1 /V mux_2level_tapbuf_basis_input3_mem3_0_out [0] $end +$var wire 1 0V mux_2level_tapbuf_basis_input3_mem3_1_out [0] $end +$var wire 1 1V mux_2level_tapbuf_basis_input3_mem3_2_out [0] $end +$var wire 1 2V SYNOPSYS_UNCONNECTED_1 $end + +$scope module sky130_fd_sc_hd__buf_4_0_ $end +$var wire 1 JJ X $end +$var wire 1 1V A $end +$var supply1 1 3V VPWR $end +$var supply0 1 4V VGND $end +$var supply1 1 5V VPB $end +$var supply0 1 6V VNB $end + +$scope module base $end +$var wire 1 JJ X $end +$var wire 1 1V A $end +$var wire 1 7V buf0_out_X $end +$upscope $end +$upscope $end + +$scope module local_encoder2to3_0_ $end +$var wire 1 RL addr [0] $end +$var wire 1 SL addr [1] $end +$var wire 1 "V data [0] $end +$var wire 1 #V data [1] $end +$var wire 1 $V data [2] $end +$var wire 1 %V data_inv [0] $end +$var wire 1 &V data_inv [1] $end +$var wire 1 'V data_inv [2] $end + +$scope module U8 $end +$var wire 1 %V Y $end +$var wire 1 "V A $end +$var supply1 1 8V VPWR $end +$var supply0 1 9V VGND $end +$var supply1 1 :V VPB $end +$var supply0 1 ;V VNB $end + +$scope module base $end +$var wire 1 %V Y $end +$var wire 1 "V A $end +$var wire 1 V VGND $end +$var supply1 1 ?V VPB $end +$var supply0 1 @V VNB $end + +$scope module base $end +$var wire 1 #V Y $end +$var wire 1 &V A $end +$var wire 1 AV not0_out_Y $end +$upscope $end +$upscope $end + +$scope module U10 $end +$var wire 1 &V Y $end +$var wire 1 RL A $end +$var wire 1 'V B $end +$var supply1 1 BV VPWR $end +$var supply0 1 CV VGND $end +$var supply1 1 DV VPB $end +$var supply0 1 EV VNB $end + +$scope module base $end +$var wire 1 &V Y $end +$var wire 1 RL A $end +$var wire 1 'V B $end +$var wire 1 FV nand0_out_Y $end +$upscope $end +$upscope $end + +$scope module U11 $end +$var wire 1 'V Y $end +$var wire 1 $V A $end +$var supply1 1 GV VPWR $end +$var supply0 1 HV VGND $end +$var supply1 1 IV VPB $end +$var supply0 1 JV VNB $end + +$scope module base $end +$var wire 1 'V Y $end +$var wire 1 $V A $end +$var wire 1 KV not0_out_Y $end +$upscope $end +$upscope $end + +$scope module U12 $end +$var wire 1 "V Y $end +$var wire 1 $V A $end +$var wire 1 RL B $end +$var supply1 1 LV VPWR $end +$var supply0 1 MV VGND $end +$var supply1 1 NV VPB $end +$var supply0 1 OV VNB $end + +$scope module base $end +$var wire 1 "V Y $end +$var wire 1 $V A $end +$var wire 1 RL B $end +$var wire 1 PV nor0_out_Y $end +$upscope $end +$upscope $end + +$scope module FTB_15__14 $end +$var wire 1 $V X $end +$var wire 1 SL A $end +$var supply1 1 QV VPWR $end +$var supply0 1 RV VGND $end +$var supply1 1 SV VPB $end +$var supply0 1 TV VNB $end + +$scope module base $end +$var wire 1 $V X $end +$var wire 1 SL A $end +$var wire 1 UV buf0_out_X $end +$upscope $end +$upscope $end +$upscope $end + +$scope module local_encoder2to3_1_ $end +$var wire 1 TL addr [0] $end +$var wire 1 UL addr [1] $end +$var wire 1 (V data [0] $end +$var wire 1 )V data [1] $end +$var wire 1 *V data [2] $end +$var wire 1 +V data_inv [0] $end +$var wire 1 ,V data_inv [1] $end +$var wire 1 -V data_inv [2] $end + +$scope module U8 $end +$var wire 1 +V Y $end +$var wire 1 (V A $end +$var supply1 1 VV VPWR $end +$var supply0 1 WV VGND $end +$var supply1 1 XV VPB $end +$var supply0 1 YV VNB $end + +$scope module base $end +$var wire 1 +V Y $end +$var wire 1 (V A $end +$var wire 1 ZV not0_out_Y $end +$upscope $end +$upscope $end + +$scope module U9 $end +$var wire 1 )V Y $end +$var wire 1 ,V A $end +$var supply1 1 [V VPWR $end +$var supply0 1 \V VGND $end +$var supply1 1 ]V VPB $end +$var supply0 1 ^V VNB $end + +$scope module base $end +$var wire 1 )V Y $end +$var wire 1 ,V A $end +$var wire 1 _V not0_out_Y $end +$upscope $end +$upscope $end + +$scope module U10 $end +$var wire 1 ,V Y $end +$var wire 1 TL A $end +$var wire 1 -V B $end +$var supply1 1 `V VPWR $end +$var supply0 1 aV VGND $end +$var supply1 1 bV VPB $end +$var supply0 1 cV VNB $end + +$scope module base $end +$var wire 1 ,V Y $end +$var wire 1 TL A $end +$var wire 1 -V B $end +$var wire 1 dV nand0_out_Y $end +$upscope $end +$upscope $end + +$scope module U11 $end +$var wire 1 -V Y $end +$var wire 1 *V A $end +$var supply1 1 eV VPWR $end +$var supply0 1 fV VGND $end +$var supply1 1 gV VPB $end +$var supply0 1 hV VNB $end + +$scope module base $end +$var wire 1 -V Y $end +$var wire 1 *V A $end +$var wire 1 iV not0_out_Y $end +$upscope $end +$upscope $end + +$scope module U12 $end +$var wire 1 (V Y $end +$var wire 1 *V A $end +$var wire 1 TL B $end +$var supply1 1 jV VPWR $end +$var supply0 1 kV VGND $end +$var supply1 1 lV VPB $end +$var supply0 1 mV VNB $end + +$scope module base $end +$var wire 1 (V Y $end +$var wire 1 *V A $end +$var wire 1 TL B $end +$var wire 1 nV nor0_out_Y $end +$upscope $end +$upscope $end + +$scope module FTB_16__15 $end +$var wire 1 *V X $end +$var wire 1 UL A $end +$var supply1 1 oV VPWR $end +$var supply0 1 pV VGND $end +$var supply1 1 qV VPB $end +$var supply0 1 rV VNB $end + +$scope module base $end +$var wire 1 *V X $end +$var wire 1 UL A $end +$var wire 1 sV buf0_out_X $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mux_l1_in_0_ $end +$var wire 1 UH in [0] $end +$var wire 1 `H in [1] $end +$var wire 1 kH in [2] $end +$var wire 1 "V mem [0] $end +$var wire 1 #V mem [1] $end +$var wire 1 $V mem [2] $end +$var wire 1 %V mem_inv [0] $end +$var wire 1 &V mem_inv [1] $end +$var wire 1 'V mem_inv [2] $end +$var wire 1 /V out [0] $end + +$scope module scs8hd_muxinv3_1_0 $end +$var wire 1 /V Z $end +$var wire 1 UH Q1 $end +$var wire 1 `H Q2 $end +$var wire 1 kH Q3 $end +$var wire 1 "V S0 $end +$var wire 1 %V S0B $end +$var wire 1 #V S1 $end +$var wire 1 &V S1B $end +$var wire 1 $V S2 $end +$var wire 1 'V S2B $end +$var wire 1 tV Q1__bar $end +$var wire 1 uV Q2__bar $end +$var wire 1 vV Q3__bar $end +$upscope $end +$upscope $end + +$scope module mux_l1_in_1_ $end +$var wire 1 PJ in [0] $end +$var wire 1 _J in [1] $end +$var wire 1 \I in [2] $end +$var wire 1 "V mem [0] $end +$var wire 1 #V mem [1] $end +$var wire 1 $V mem [2] $end +$var wire 1 %V mem_inv [0] $end +$var wire 1 &V mem_inv [1] $end +$var wire 1 'V mem_inv [2] $end +$var wire 1 0V out [0] $end + +$scope module scs8hd_muxinv3_1_0 $end +$var wire 1 0V Z $end +$var wire 1 PJ Q1 $end +$var wire 1 _J Q2 $end +$var wire 1 \I Q3 $end +$var wire 1 "V S0 $end +$var wire 1 %V S0B $end +$var wire 1 #V S1 $end +$var wire 1 &V S1B $end +$var wire 1 $V S2 $end +$var wire 1 'V S2B $end +$var wire 1 wV Q1__bar $end +$var wire 1 xV Q2__bar $end +$var wire 1 yV Q3__bar $end +$upscope $end +$upscope $end + +$scope module mux_l2_in_0_ $end +$var wire 1 /V in [0] $end +$var wire 1 0V in [1] $end +$var wire 1 .V in [2] $end +$var wire 1 (V mem [0] $end +$var wire 1 )V mem [1] $end +$var wire 1 *V mem [2] $end +$var wire 1 +V mem_inv [0] $end +$var wire 1 ,V mem_inv [1] $end +$var wire 1 -V mem_inv [2] $end +$var wire 1 1V out [0] $end + +$scope module scs8hd_muxinv3_1_0 $end +$var wire 1 1V Z $end +$var wire 1 /V Q1 $end +$var wire 1 0V Q2 $end +$var wire 1 .V Q3 $end +$var wire 1 (V S0 $end +$var wire 1 +V S0B $end +$var wire 1 )V S1 $end +$var wire 1 ,V S1B $end +$var wire 1 *V S2 $end +$var wire 1 -V S2B $end +$var wire 1 zV Q1__bar $end +$var wire 1 {V Q2__bar $end +$var wire 1 |V Q3__bar $end +$upscope $end +$upscope $end + +$scope module mux_l1_in_2_ $end +$var wire 1 bI in [0] $end +$var wire 1 2V in [1] $end +$var wire 1 "V mem [0] $end +$var wire 1 #V mem [1] $end +$var wire 1 %V mem_inv [0] $end +$var wire 1 &V mem_inv [1] $end +$var wire 1 .V out [0] $end +$var wire 1 LM p0 $end + +$scope module scs8hd_muxinv2_1_0 $end +$var wire 1 .V Z $end +$var wire 1 bI Q1 $end +$var wire 1 LM Q2 $end +$var wire 1 "V S0 $end +$var wire 1 %V S0B $end +$var wire 1 #V S1 $end +$var wire 1 &V S1B $end +$var wire 1 }V Q1__bar $end +$var wire 1 ~V Q2__bar $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mux_left_track_21 $end +$var wire 1 TH in [0] $end +$var wire 1 _H in [1] $end +$var wire 1 jH in [2] $end +$var wire 1 QJ in [3] $end +$var wire 1 `J in [4] $end +$var wire 1 ]I in [5] $end +$var wire 1 cI in [6] $end +$var wire 1 VL sram [0] $end +$var wire 1 WL sram [1] $end +$var wire 1 XL sram [2] $end +$var wire 1 YL sram [3] $end +$var wire 1 MM sram_inv [0] $end +$var wire 1 NM sram_inv [1] $end +$var wire 1 OM sram_inv [2] $end +$var wire 1 PM sram_inv [3] $end +$var wire 1 NJ out [0] $end +$var wire 1 BM p0 $end +$var wire 1 !W local_encoder2to3_0_data [0] $end +$var wire 1 "W local_encoder2to3_0_data [1] $end +$var wire 1 #W local_encoder2to3_0_data [2] $end +$var wire 1 $W local_encoder2to3_0_data_inv [0] $end +$var wire 1 %W local_encoder2to3_0_data_inv [1] $end +$var wire 1 &W local_encoder2to3_0_data_inv [2] $end +$var wire 1 'W local_encoder2to3_1_data [0] $end +$var wire 1 (W local_encoder2to3_1_data [1] $end +$var wire 1 )W local_encoder2to3_1_data [2] $end +$var wire 1 *W local_encoder2to3_1_data_inv [0] $end +$var wire 1 +W local_encoder2to3_1_data_inv [1] $end +$var wire 1 ,W local_encoder2to3_1_data_inv [2] $end +$var wire 1 -W mux_2level_tapbuf_basis_input2_mem2_0_out [0] $end +$var wire 1 .W mux_2level_tapbuf_basis_input3_mem3_0_out [0] $end +$var wire 1 /W mux_2level_tapbuf_basis_input3_mem3_1_out [0] $end +$var wire 1 0W mux_2level_tapbuf_basis_input3_mem3_2_out [0] $end +$var wire 1 1W SYNOPSYS_UNCONNECTED_1 $end + +$scope module sky130_fd_sc_hd__buf_4_0_ $end +$var wire 1 NJ X $end +$var wire 1 0W A $end +$var supply1 1 2W VPWR $end +$var supply0 1 3W VGND $end +$var supply1 1 4W VPB $end +$var supply0 1 5W VNB $end + +$scope module base $end +$var wire 1 NJ X $end +$var wire 1 0W A $end +$var wire 1 6W buf0_out_X $end +$upscope $end +$upscope $end + +$scope module local_encoder2to3_0_ $end +$var wire 1 VL addr [0] $end +$var wire 1 WL addr [1] $end +$var wire 1 !W data [0] $end +$var wire 1 "W data [1] $end +$var wire 1 #W data [2] $end +$var wire 1 $W data_inv [0] $end +$var wire 1 %W data_inv [1] $end +$var wire 1 &W data_inv [2] $end + +$scope module U8 $end +$var wire 1 $W Y $end +$var wire 1 !W A $end +$var supply1 1 7W VPWR $end +$var supply0 1 8W VGND $end +$var supply1 1 9W VPB $end +$var supply0 1 :W VNB $end + +$scope module base $end +$var wire 1 $W Y $end +$var wire 1 !W A $end +$var wire 1 ;W not0_out_Y $end +$upscope $end +$upscope $end + +$scope module U9 $end +$var wire 1 "W Y $end +$var wire 1 %W A $end +$var supply1 1 W VPB $end +$var supply0 1 ?W VNB $end + +$scope module base $end +$var wire 1 "W Y $end +$var wire 1 %W A $end +$var wire 1 @W not0_out_Y $end +$upscope $end +$upscope $end + +$scope module U10 $end +$var wire 1 %W Y $end +$var wire 1 VL A $end +$var wire 1 &W B $end +$var supply1 1 AW VPWR $end +$var supply0 1 BW VGND $end +$var supply1 1 CW VPB $end +$var supply0 1 DW VNB $end + +$scope module base $end +$var wire 1 %W Y $end +$var wire 1 VL A $end +$var wire 1 &W B $end +$var wire 1 EW nand0_out_Y $end +$upscope $end +$upscope $end + +$scope module U11 $end +$var wire 1 &W Y $end +$var wire 1 #W A $end +$var supply1 1 FW VPWR $end +$var supply0 1 GW VGND $end +$var supply1 1 HW VPB $end +$var supply0 1 IW VNB $end + +$scope module base $end +$var wire 1 &W Y $end +$var wire 1 #W A $end +$var wire 1 JW not0_out_Y $end +$upscope $end +$upscope $end + +$scope module U12 $end +$var wire 1 !W Y $end +$var wire 1 #W A $end +$var wire 1 VL B $end +$var supply1 1 KW VPWR $end +$var supply0 1 LW VGND $end +$var supply1 1 MW VPB $end +$var supply0 1 NW VNB $end + +$scope module base $end +$var wire 1 !W Y $end +$var wire 1 #W A $end +$var wire 1 VL B $end +$var wire 1 OW nor0_out_Y $end +$upscope $end +$upscope $end + +$scope module FTB_17__16 $end +$var wire 1 #W X $end +$var wire 1 WL A $end +$var supply1 1 PW VPWR $end +$var supply0 1 QW VGND $end +$var supply1 1 RW VPB $end +$var supply0 1 SW VNB $end + +$scope module base $end +$var wire 1 #W X $end +$var wire 1 WL A $end +$var wire 1 TW buf0_out_X $end +$upscope $end +$upscope $end +$upscope $end + +$scope module local_encoder2to3_1_ $end +$var wire 1 XL addr [0] $end +$var wire 1 YL addr [1] $end +$var wire 1 'W data [0] $end +$var wire 1 (W data [1] $end +$var wire 1 )W data [2] $end +$var wire 1 *W data_inv [0] $end +$var wire 1 +W data_inv [1] $end +$var wire 1 ,W data_inv [2] $end + +$scope module U8 $end +$var wire 1 *W Y $end +$var wire 1 'W A $end +$var supply1 1 UW VPWR $end +$var supply0 1 VW VGND $end +$var supply1 1 WW VPB $end +$var supply0 1 XW VNB $end + +$scope module base $end +$var wire 1 *W Y $end +$var wire 1 'W A $end +$var wire 1 YW not0_out_Y $end +$upscope $end +$upscope $end + +$scope module U9 $end +$var wire 1 (W Y $end +$var wire 1 +W A $end +$var supply1 1 ZW VPWR $end +$var supply0 1 [W VGND $end +$var supply1 1 \W VPB $end +$var supply0 1 ]W VNB $end + +$scope module base $end +$var wire 1 (W Y $end +$var wire 1 +W A $end +$var wire 1 ^W not0_out_Y $end +$upscope $end +$upscope $end + +$scope module U10 $end +$var wire 1 +W Y $end +$var wire 1 XL A $end +$var wire 1 ,W B $end +$var supply1 1 _W VPWR $end +$var supply0 1 `W VGND $end +$var supply1 1 aW VPB $end +$var supply0 1 bW VNB $end + +$scope module base $end +$var wire 1 +W Y $end +$var wire 1 XL A $end +$var wire 1 ,W B $end +$var wire 1 cW nand0_out_Y $end +$upscope $end +$upscope $end + +$scope module U11 $end +$var wire 1 ,W Y $end +$var wire 1 )W A $end +$var supply1 1 dW VPWR $end +$var supply0 1 eW VGND $end +$var supply1 1 fW VPB $end +$var supply0 1 gW VNB $end + +$scope module base $end +$var wire 1 ,W Y $end +$var wire 1 )W A $end +$var wire 1 hW not0_out_Y $end +$upscope $end +$upscope $end + +$scope module U12 $end +$var wire 1 'W Y $end +$var wire 1 )W A $end +$var wire 1 XL B $end +$var supply1 1 iW VPWR $end +$var supply0 1 jW VGND $end +$var supply1 1 kW VPB $end +$var supply0 1 lW VNB $end + +$scope module base $end +$var wire 1 'W Y $end +$var wire 1 )W A $end +$var wire 1 XL B $end +$var wire 1 mW nor0_out_Y $end +$upscope $end +$upscope $end + +$scope module FTB_18__17 $end +$var wire 1 )W X $end +$var wire 1 YL A $end +$var supply1 1 nW VPWR $end +$var supply0 1 oW VGND $end +$var supply1 1 pW VPB $end +$var supply0 1 qW VNB $end + +$scope module base $end +$var wire 1 )W X $end +$var wire 1 YL A $end +$var wire 1 rW buf0_out_X $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mux_l1_in_0_ $end +$var wire 1 TH in [0] $end +$var wire 1 _H in [1] $end +$var wire 1 jH in [2] $end +$var wire 1 !W mem [0] $end +$var wire 1 "W mem [1] $end +$var wire 1 #W mem [2] $end +$var wire 1 $W mem_inv [0] $end +$var wire 1 %W mem_inv [1] $end +$var wire 1 &W mem_inv [2] $end +$var wire 1 .W out [0] $end + +$scope module scs8hd_muxinv3_1_0 $end +$var wire 1 .W Z $end +$var wire 1 TH Q1 $end +$var wire 1 _H Q2 $end +$var wire 1 jH Q3 $end +$var wire 1 !W S0 $end +$var wire 1 $W S0B $end +$var wire 1 "W S1 $end +$var wire 1 %W S1B $end +$var wire 1 #W S2 $end +$var wire 1 &W S2B $end +$var wire 1 sW Q1__bar $end +$var wire 1 tW Q2__bar $end +$var wire 1 uW Q3__bar $end +$upscope $end +$upscope $end + +$scope module mux_l1_in_1_ $end +$var wire 1 QJ in [0] $end +$var wire 1 `J in [1] $end +$var wire 1 ]I in [2] $end +$var wire 1 !W mem [0] $end +$var wire 1 "W mem [1] $end +$var wire 1 #W mem [2] $end +$var wire 1 $W mem_inv [0] $end +$var wire 1 %W mem_inv [1] $end +$var wire 1 &W mem_inv [2] $end +$var wire 1 /W out [0] $end + +$scope module scs8hd_muxinv3_1_0 $end +$var wire 1 /W Z $end +$var wire 1 QJ Q1 $end +$var wire 1 `J Q2 $end +$var wire 1 ]I Q3 $end +$var wire 1 !W S0 $end +$var wire 1 $W S0B $end +$var wire 1 "W S1 $end +$var wire 1 %W S1B $end +$var wire 1 #W S2 $end +$var wire 1 &W S2B $end +$var wire 1 vW Q1__bar $end +$var wire 1 wW Q2__bar $end +$var wire 1 xW Q3__bar $end +$upscope $end +$upscope $end + +$scope module mux_l2_in_0_ $end +$var wire 1 .W in [0] $end +$var wire 1 /W in [1] $end +$var wire 1 -W in [2] $end +$var wire 1 'W mem [0] $end +$var wire 1 (W mem [1] $end +$var wire 1 )W mem [2] $end +$var wire 1 *W mem_inv [0] $end +$var wire 1 +W mem_inv [1] $end +$var wire 1 ,W mem_inv [2] $end +$var wire 1 0W out [0] $end + +$scope module scs8hd_muxinv3_1_0 $end +$var wire 1 0W Z $end +$var wire 1 .W Q1 $end +$var wire 1 /W Q2 $end +$var wire 1 -W Q3 $end +$var wire 1 'W S0 $end +$var wire 1 *W S0B $end +$var wire 1 (W S1 $end +$var wire 1 +W S1B $end +$var wire 1 )W S2 $end +$var wire 1 ,W S2B $end +$var wire 1 yW Q1__bar $end +$var wire 1 zW Q2__bar $end +$var wire 1 {W Q3__bar $end +$upscope $end +$upscope $end + +$scope module mux_l1_in_2_ $end +$var wire 1 cI in [0] $end +$var wire 1 1W in [1] $end +$var wire 1 !W mem [0] $end +$var wire 1 "W mem [1] $end +$var wire 1 $W mem_inv [0] $end +$var wire 1 %W mem_inv [1] $end +$var wire 1 -W out [0] $end +$var wire 1 BM p0 $end + +$scope module scs8hd_muxinv2_1_0 $end +$var wire 1 -W Z $end +$var wire 1 cI Q1 $end +$var wire 1 BM Q2 $end +$var wire 1 !W S0 $end +$var wire 1 $W S0B $end +$var wire 1 "W S1 $end +$var wire 1 %W S1B $end +$var wire 1 |W Q1__bar $end +$var wire 1 }W Q2__bar $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mux_left_track_29 $end +$var wire 1 SH in [0] $end +$var wire 1 ^H in [1] $end +$var wire 1 iH in [2] $end +$var wire 1 SJ in [3] $end +$var wire 1 aJ in [4] $end +$var wire 1 ^I in [5] $end +$var wire 1 dI in [6] $end +$var wire 1 ZL sram [0] $end +$var wire 1 [L sram [1] $end +$var wire 1 \L sram [2] $end +$var wire 1 ]L sram [3] $end +$var wire 1 QM sram_inv [0] $end +$var wire 1 RM sram_inv [1] $end +$var wire 1 SM sram_inv [2] $end +$var wire 1 TM sram_inv [3] $end +$var wire 1 RJ out [0] $end +$var wire 1 GM p0 $end +$var wire 1 ~W local_encoder2to3_0_data [0] $end +$var wire 1 !X local_encoder2to3_0_data [1] $end +$var wire 1 "X local_encoder2to3_0_data [2] $end +$var wire 1 #X local_encoder2to3_0_data_inv [0] $end +$var wire 1 $X local_encoder2to3_0_data_inv [1] $end +$var wire 1 %X local_encoder2to3_0_data_inv [2] $end +$var wire 1 &X local_encoder2to3_1_data [0] $end +$var wire 1 'X local_encoder2to3_1_data [1] $end +$var wire 1 (X local_encoder2to3_1_data [2] $end +$var wire 1 )X local_encoder2to3_1_data_inv [0] $end +$var wire 1 *X local_encoder2to3_1_data_inv [1] $end +$var wire 1 +X local_encoder2to3_1_data_inv [2] $end +$var wire 1 ,X mux_2level_tapbuf_basis_input2_mem2_0_out [0] $end +$var wire 1 -X mux_2level_tapbuf_basis_input3_mem3_0_out [0] $end +$var wire 1 .X mux_2level_tapbuf_basis_input3_mem3_1_out [0] $end +$var wire 1 /X mux_2level_tapbuf_basis_input3_mem3_2_out [0] $end +$var wire 1 0X SYNOPSYS_UNCONNECTED_1 $end + +$scope module sky130_fd_sc_hd__buf_4_0_ $end +$var wire 1 RJ X $end +$var wire 1 /X A $end +$var supply1 1 1X VPWR $end +$var supply0 1 2X VGND $end +$var supply1 1 3X VPB $end +$var supply0 1 4X VNB $end + +$scope module base $end +$var wire 1 RJ X $end +$var wire 1 /X A $end +$var wire 1 5X buf0_out_X $end +$upscope $end +$upscope $end + +$scope module local_encoder2to3_0_ $end +$var wire 1 ZL addr [0] $end +$var wire 1 [L addr [1] $end +$var wire 1 ~W data [0] $end +$var wire 1 !X data [1] $end +$var wire 1 "X data [2] $end +$var wire 1 #X data_inv [0] $end +$var wire 1 $X data_inv [1] $end +$var wire 1 %X data_inv [2] $end + +$scope module U8 $end +$var wire 1 #X Y $end +$var wire 1 ~W A $end +$var supply1 1 6X VPWR $end +$var supply0 1 7X VGND $end +$var supply1 1 8X VPB $end +$var supply0 1 9X VNB $end + +$scope module base $end +$var wire 1 #X Y $end +$var wire 1 ~W A $end +$var wire 1 :X not0_out_Y $end +$upscope $end +$upscope $end + +$scope module U9 $end +$var wire 1 !X Y $end +$var wire 1 $X A $end +$var supply1 1 ;X VPWR $end +$var supply0 1 X VNB $end + +$scope module base $end +$var wire 1 !X Y $end +$var wire 1 $X A $end +$var wire 1 ?X not0_out_Y $end +$upscope $end +$upscope $end + +$scope module U10 $end +$var wire 1 $X Y $end +$var wire 1 ZL A $end +$var wire 1 %X B $end +$var supply1 1 @X VPWR $end +$var supply0 1 AX VGND $end +$var supply1 1 BX VPB $end +$var supply0 1 CX VNB $end + +$scope module base $end +$var wire 1 $X Y $end +$var wire 1 ZL A $end +$var wire 1 %X B $end +$var wire 1 DX nand0_out_Y $end +$upscope $end +$upscope $end + +$scope module U11 $end +$var wire 1 %X Y $end +$var wire 1 "X A $end +$var supply1 1 EX VPWR $end +$var supply0 1 FX VGND $end +$var supply1 1 GX VPB $end +$var supply0 1 HX VNB $end + +$scope module base $end +$var wire 1 %X Y $end +$var wire 1 "X A $end +$var wire 1 IX not0_out_Y $end +$upscope $end +$upscope $end + +$scope module U12 $end +$var wire 1 ~W Y $end +$var wire 1 "X A $end +$var wire 1 ZL B $end +$var supply1 1 JX VPWR $end +$var supply0 1 KX VGND $end +$var supply1 1 LX VPB $end +$var supply0 1 MX VNB $end + +$scope module base $end +$var wire 1 ~W Y $end +$var wire 1 "X A $end +$var wire 1 ZL B $end +$var wire 1 NX nor0_out_Y $end +$upscope $end +$upscope $end + +$scope module FTB_19__18 $end +$var wire 1 "X X $end +$var wire 1 [L A $end +$var supply1 1 OX VPWR $end +$var supply0 1 PX VGND $end +$var supply1 1 QX VPB $end +$var supply0 1 RX VNB $end + +$scope module base $end +$var wire 1 "X X $end +$var wire 1 [L A $end +$var wire 1 SX buf0_out_X $end +$upscope $end +$upscope $end +$upscope $end + +$scope module local_encoder2to3_1_ $end +$var wire 1 \L addr [0] $end +$var wire 1 ]L addr [1] $end +$var wire 1 &X data [0] $end +$var wire 1 'X data [1] $end +$var wire 1 (X data [2] $end +$var wire 1 )X data_inv [0] $end +$var wire 1 *X data_inv [1] $end +$var wire 1 +X data_inv [2] $end + +$scope module U8 $end +$var wire 1 )X Y $end +$var wire 1 &X A $end +$var supply1 1 TX VPWR $end +$var supply0 1 UX VGND $end +$var supply1 1 VX VPB $end +$var supply0 1 WX VNB $end + +$scope module base $end +$var wire 1 )X Y $end +$var wire 1 &X A $end +$var wire 1 XX not0_out_Y $end +$upscope $end +$upscope $end + +$scope module U9 $end +$var wire 1 'X Y $end +$var wire 1 *X A $end +$var supply1 1 YX VPWR $end +$var supply0 1 ZX VGND $end +$var supply1 1 [X VPB $end +$var supply0 1 \X VNB $end + +$scope module base $end +$var wire 1 'X Y $end +$var wire 1 *X A $end +$var wire 1 ]X not0_out_Y $end +$upscope $end +$upscope $end + +$scope module U10 $end +$var wire 1 *X Y $end +$var wire 1 \L A $end +$var wire 1 +X B $end +$var supply1 1 ^X VPWR $end +$var supply0 1 _X VGND $end +$var supply1 1 `X VPB $end +$var supply0 1 aX VNB $end + +$scope module base $end +$var wire 1 *X Y $end +$var wire 1 \L A $end +$var wire 1 +X B $end +$var wire 1 bX nand0_out_Y $end +$upscope $end +$upscope $end + +$scope module U11 $end +$var wire 1 +X Y $end +$var wire 1 (X A $end +$var supply1 1 cX VPWR $end +$var supply0 1 dX VGND $end +$var supply1 1 eX VPB $end +$var supply0 1 fX VNB $end + +$scope module base $end +$var wire 1 +X Y $end +$var wire 1 (X A $end +$var wire 1 gX not0_out_Y $end +$upscope $end +$upscope $end + +$scope module U12 $end +$var wire 1 &X Y $end +$var wire 1 (X A $end +$var wire 1 \L B $end +$var supply1 1 hX VPWR $end +$var supply0 1 iX VGND $end +$var supply1 1 jX VPB $end +$var supply0 1 kX VNB $end + +$scope module base $end +$var wire 1 &X Y $end +$var wire 1 (X A $end +$var wire 1 \L B $end +$var wire 1 lX nor0_out_Y $end +$upscope $end +$upscope $end + +$scope module FTB_20__19 $end +$var wire 1 (X X $end +$var wire 1 ]L A $end +$var supply1 1 mX VPWR $end +$var supply0 1 nX VGND $end +$var supply1 1 oX VPB $end +$var supply0 1 pX VNB $end + +$scope module base $end +$var wire 1 (X X $end +$var wire 1 ]L A $end +$var wire 1 qX buf0_out_X $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mux_l1_in_0_ $end +$var wire 1 SH in [0] $end +$var wire 1 ^H in [1] $end +$var wire 1 iH in [2] $end +$var wire 1 ~W mem [0] $end +$var wire 1 !X mem [1] $end +$var wire 1 "X mem [2] $end +$var wire 1 #X mem_inv [0] $end +$var wire 1 $X mem_inv [1] $end +$var wire 1 %X mem_inv [2] $end +$var wire 1 -X out [0] $end + +$scope module scs8hd_muxinv3_1_0 $end +$var wire 1 -X Z $end +$var wire 1 SH Q1 $end +$var wire 1 ^H Q2 $end +$var wire 1 iH Q3 $end +$var wire 1 ~W S0 $end +$var wire 1 #X S0B $end +$var wire 1 !X S1 $end +$var wire 1 $X S1B $end +$var wire 1 "X S2 $end +$var wire 1 %X S2B $end +$var wire 1 rX Q1__bar $end +$var wire 1 sX Q2__bar $end +$var wire 1 tX Q3__bar $end +$upscope $end +$upscope $end + +$scope module mux_l1_in_1_ $end +$var wire 1 SJ in [0] $end +$var wire 1 aJ in [1] $end +$var wire 1 ^I in [2] $end +$var wire 1 ~W mem [0] $end +$var wire 1 !X mem [1] $end +$var wire 1 "X mem [2] $end +$var wire 1 #X mem_inv [0] $end +$var wire 1 $X mem_inv [1] $end +$var wire 1 %X mem_inv [2] $end +$var wire 1 .X out [0] $end + +$scope module scs8hd_muxinv3_1_0 $end +$var wire 1 .X Z $end +$var wire 1 SJ Q1 $end +$var wire 1 aJ Q2 $end +$var wire 1 ^I Q3 $end +$var wire 1 ~W S0 $end +$var wire 1 #X S0B $end +$var wire 1 !X S1 $end +$var wire 1 $X S1B $end +$var wire 1 "X S2 $end +$var wire 1 %X S2B $end +$var wire 1 uX Q1__bar $end +$var wire 1 vX Q2__bar $end +$var wire 1 wX Q3__bar $end +$upscope $end +$upscope $end + +$scope module mux_l2_in_0_ $end +$var wire 1 -X in [0] $end +$var wire 1 .X in [1] $end +$var wire 1 ,X in [2] $end +$var wire 1 &X mem [0] $end +$var wire 1 'X mem [1] $end +$var wire 1 (X mem [2] $end +$var wire 1 )X mem_inv [0] $end +$var wire 1 *X mem_inv [1] $end +$var wire 1 +X mem_inv [2] $end +$var wire 1 /X out [0] $end + +$scope module scs8hd_muxinv3_1_0 $end +$var wire 1 /X Z $end +$var wire 1 -X Q1 $end +$var wire 1 .X Q2 $end +$var wire 1 ,X Q3 $end +$var wire 1 &X S0 $end +$var wire 1 )X S0B $end +$var wire 1 'X S1 $end +$var wire 1 *X S1B $end +$var wire 1 (X S2 $end +$var wire 1 +X S2B $end +$var wire 1 xX Q1__bar $end +$var wire 1 yX Q2__bar $end +$var wire 1 zX Q3__bar $end +$upscope $end +$upscope $end + +$scope module mux_l1_in_2_ $end +$var wire 1 dI in [0] $end +$var wire 1 0X in [1] $end +$var wire 1 ~W mem [0] $end +$var wire 1 !X mem [1] $end +$var wire 1 #X mem_inv [0] $end +$var wire 1 $X mem_inv [1] $end +$var wire 1 ,X out [0] $end +$var wire 1 GM p0 $end + +$scope module scs8hd_muxinv2_1_0 $end +$var wire 1 ,X Z $end +$var wire 1 dI Q1 $end +$var wire 1 GM Q2 $end +$var wire 1 ~W S0 $end +$var wire 1 #X S0B $end +$var wire 1 !X S1 $end +$var wire 1 $X S1B $end +$var wire 1 {X Q1__bar $end +$var wire 1 |X Q2__bar $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mem_top_track_0 $end +$var wire 1 NH pReset [0] $end +$var wire 1 qJ prog_clk [0] $end +$var wire 1 eI ccff_head [0] $end +$var wire 1 ^L ccff_tail [0] $end +$var wire 1 6L mem_out [0] $end +$var wire 1 7L mem_out [1] $end +$var wire 1 8L mem_out [2] $end +$var wire 1 9L mem_out [3] $end +$var wire 1 }X ropt_net_249 $end +$var wire 1 ~X ropt_net_250 $end +$var wire 1 !Y copt_net_213 $end +$var wire 1 "Y copt_net_214 $end +$var wire 1 #Y copt_net_215 $end +$var wire 1 $Y copt_net_218 $end +$var wire 1 %Y copt_net_216 $end +$var wire 1 &Y copt_net_217 $end +$var wire 1 'Y ropt_net_243 $end +$var wire 1 (Y ropt_net_244 $end +$var wire 1 )Y ropt_net_245 $end +$var wire 1 *Y ropt_net_246 $end +$var wire 1 +Y ropt_net_247 $end +$var wire 1 ,Y ropt_net_248 $end + +$scope module sky130_fd_sc_hd__dfrtp_1_0_ $end +$var wire 1 6L Q $end +$var wire 1 qJ CLK $end +$var wire 1 }X D $end +$var wire 1 NH RESET_B $end +$var supply1 1 -Y VPWR $end +$var supply0 1 .Y VGND $end +$var supply1 1 /Y VPB $end +$var supply0 1 0Y VNB $end + +$scope module base $end +$var wire 1 6L Q $end +$var wire 1 qJ CLK $end +$var wire 1 }X D $end +$var wire 1 NH RESET_B $end +$var wire 1 1Y buf_Q $end +$var wire 1 2Y RESET $end +$upscope $end +$upscope $end + +$scope module sky130_fd_sc_hd__dfrtp_1_1_ $end +$var wire 1 7L Q $end +$var wire 1 qJ CLK $end +$var wire 1 6L D $end +$var wire 1 NH RESET_B $end +$var supply1 1 3Y VPWR $end +$var supply0 1 4Y VGND $end +$var supply1 1 5Y VPB $end +$var supply0 1 6Y VNB $end + +$scope module base $end +$var wire 1 7L Q $end +$var wire 1 qJ CLK $end +$var wire 1 6L D $end +$var wire 1 NH RESET_B $end +$var wire 1 7Y buf_Q $end +$var wire 1 8Y RESET $end +$upscope $end +$upscope $end + +$scope module sky130_fd_sc_hd__dfrtp_1_2_ $end +$var wire 1 8L Q $end +$var wire 1 qJ CLK $end +$var wire 1 7L D $end +$var wire 1 NH RESET_B $end +$var supply1 1 9Y VPWR $end +$var supply0 1 :Y VGND $end +$var supply1 1 ;Y VPB $end +$var supply0 1 Y RESET $end +$upscope $end +$upscope $end + +$scope module sky130_fd_sc_hd__dfrtp_1_3_ $end +$var wire 1 9L Q $end +$var wire 1 qJ CLK $end +$var wire 1 8L D $end +$var wire 1 NH RESET_B $end +$var supply1 1 ?Y VPWR $end +$var supply0 1 @Y VGND $end +$var supply1 1 AY VPB $end +$var supply0 1 BY VNB $end + +$scope module base $end +$var wire 1 9L Q $end +$var wire 1 qJ CLK $end +$var wire 1 8L D $end +$var wire 1 NH RESET_B $end +$var wire 1 CY buf_Q $end +$var wire 1 DY RESET $end +$upscope $end +$upscope $end + +$scope module FTB_21__20 $end +$var wire 1 ^L X $end +$var wire 1 9L A $end +$var supply1 1 EY VPWR $end +$var supply0 1 FY VGND $end +$var supply1 1 GY VPB $end +$var supply0 1 HY VNB $end + +$scope module base $end +$var wire 1 ^L X $end +$var wire 1 9L A $end +$var wire 1 IY buf0_out_X $end +$upscope $end +$upscope $end + +$scope module copt_h_inst_1414 $end +$var wire 1 !Y X $end +$var wire 1 ~X A $end +$var supply1 1 JY VPWR $end +$var supply0 1 KY VGND $end +$var supply1 1 LY VPB $end +$var supply0 1 MY VNB $end + +$scope module base $end +$var wire 1 !Y X $end +$var wire 1 ~X A $end +$var wire 1 NY buf0_out_X $end +$upscope $end +$upscope $end + +$scope module copt_h_inst_1415 $end +$var wire 1 "Y X $end +$var wire 1 !Y A $end +$var supply1 1 OY VPWR $end +$var supply0 1 PY VGND $end +$var supply1 1 QY VPB $end +$var supply0 1 RY VNB $end + +$scope module base $end +$var wire 1 "Y X $end +$var wire 1 !Y A $end +$var wire 1 SY buf0_out_X $end +$upscope $end +$upscope $end + +$scope module copt_h_inst_1416 $end +$var wire 1 #Y X $end +$var wire 1 "Y A $end +$var supply1 1 TY VPWR $end +$var supply0 1 UY VGND $end +$var supply1 1 VY VPB $end +$var supply0 1 WY VNB $end + +$scope module base $end +$var wire 1 #Y X $end +$var wire 1 "Y A $end +$var wire 1 XY buf0_out_X $end +$upscope $end +$upscope $end + +$scope module copt_h_inst_1417 $end +$var wire 1 %Y X $end +$var wire 1 $Y A $end +$var supply1 1 YY VPWR $end +$var supply0 1 ZY VGND $end +$var supply1 1 [Y VPB $end +$var supply0 1 \Y VNB $end + +$scope module base $end +$var wire 1 %Y X $end +$var wire 1 $Y A $end +$var wire 1 ]Y buf0_out_X $end +$upscope $end +$upscope $end + +$scope module copt_h_inst_1418 $end +$var wire 1 &Y X $end +$var wire 1 eI A $end +$var supply1 1 ^Y VPWR $end +$var supply0 1 _Y VGND $end +$var supply1 1 `Y VPB $end +$var supply0 1 aY VNB $end + +$scope module base $end +$var wire 1 &Y X $end +$var wire 1 eI A $end +$var wire 1 bY buf0_out_X $end +$upscope $end +$upscope $end + +$scope module copt_h_inst_1419 $end +$var wire 1 $Y X $end +$var wire 1 #Y A $end +$var supply1 1 cY VPWR $end +$var supply0 1 dY VGND $end +$var supply1 1 eY VPB $end +$var supply0 1 fY VNB $end + +$scope module base $end +$var wire 1 $Y X $end +$var wire 1 #Y A $end +$var wire 1 gY buf0_out_X $end +$upscope $end +$upscope $end + +$scope module ropt_h_inst_1444 $end +$var wire 1 'Y X $end +$var wire 1 %Y A $end +$var supply1 1 hY VPWR $end +$var supply0 1 iY VGND $end +$var supply1 1 jY VPB $end +$var supply0 1 kY VNB $end + +$scope module base $end +$var wire 1 'Y X $end +$var wire 1 %Y A $end +$var wire 1 lY buf0_out_X $end +$upscope $end +$upscope $end + +$scope module ropt_h_inst_1445 $end +$var wire 1 (Y X $end +$var wire 1 'Y A $end +$var supply1 1 mY VPWR $end +$var supply0 1 nY VGND $end +$var supply1 1 oY VPB $end +$var supply0 1 pY VNB $end + +$scope module base $end +$var wire 1 (Y X $end +$var wire 1 'Y A $end +$var wire 1 qY buf0_out_X $end +$upscope $end +$upscope $end + +$scope module ropt_h_inst_1446 $end +$var wire 1 )Y X $end +$var wire 1 (Y A $end +$var supply1 1 rY VPWR $end +$var supply0 1 sY VGND $end +$var supply1 1 tY VPB $end +$var supply0 1 uY VNB $end + +$scope module base $end +$var wire 1 )Y X $end +$var wire 1 (Y A $end +$var wire 1 vY buf0_out_X $end +$upscope $end +$upscope $end + +$scope module ropt_h_inst_1447 $end +$var wire 1 *Y X $end +$var wire 1 )Y A $end +$var supply1 1 wY VPWR $end +$var supply0 1 xY VGND $end +$var supply1 1 yY VPB $end +$var supply0 1 zY VNB $end + +$scope module base $end +$var wire 1 *Y X $end +$var wire 1 )Y A $end +$var wire 1 {Y buf0_out_X $end +$upscope $end +$upscope $end + +$scope module ropt_h_inst_1448 $end +$var wire 1 +Y X $end +$var wire 1 *Y A $end +$var supply1 1 |Y VPWR $end +$var supply0 1 }Y VGND $end +$var supply1 1 ~Y VPB $end +$var supply0 1 !Z VNB $end + +$scope module base $end +$var wire 1 +Y X $end +$var wire 1 *Y A $end +$var wire 1 "Z buf0_out_X $end +$upscope $end +$upscope $end + +$scope module ropt_h_inst_1449 $end +$var wire 1 ,Y X $end +$var wire 1 +Y A $end +$var supply1 1 #Z VPWR $end +$var supply0 1 $Z VGND $end +$var supply1 1 %Z VPB $end +$var supply0 1 &Z VNB $end + +$scope module base $end +$var wire 1 ,Y X $end +$var wire 1 +Y A $end +$var wire 1 'Z buf0_out_X $end +$upscope $end +$upscope $end + +$scope module ropt_h_inst_1450 $end +$var wire 1 }X X $end +$var wire 1 ,Y A $end +$var supply1 1 (Z VPWR $end +$var supply0 1 )Z VGND $end +$var supply1 1 *Z VPB $end +$var supply0 1 +Z VNB $end + +$scope module base $end +$var wire 1 }X X $end +$var wire 1 ,Y A $end +$var wire 1 ,Z buf0_out_X $end +$upscope $end +$upscope $end + +$scope module ropt_h_inst_1451 $end +$var wire 1 ~X X $end +$var wire 1 &Y A $end +$var supply1 1 -Z VPWR $end +$var supply0 1 .Z VGND $end +$var supply1 1 /Z VPB $end +$var supply0 1 0Z VNB $end + +$scope module base $end +$var wire 1 ~X X $end +$var wire 1 &Y A $end +$var wire 1 1Z buf0_out_X $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mem_right_track_0 $end +$var wire 1 NH pReset [0] $end +$var wire 1 qJ prog_clk [0] $end +$var wire 1 1K ccff_head [0] $end +$var wire 1 _L ccff_tail [0] $end +$var wire 1 :L mem_out [0] $end +$var wire 1 ;L mem_out [1] $end +$var wire 1 Z VPWR $end +$var supply0 1 ?Z VGND $end +$var supply1 1 @Z VPB $end +$var supply0 1 AZ VNB $end + +$scope module base $end +$var wire 1 L mem_out [0] $end +$var wire 1 ?L mem_out [1] $end +$var wire 1 @L mem_out [2] $end +$var wire 1 AL mem_out [3] $end + +$scope module sky130_fd_sc_hd__dfrtp_1_0_ $end +$var wire 1 >L Q $end +$var wire 1 qJ CLK $end +$var wire 1 %M D $end +$var wire 1 NH RESET_B $end +$var supply1 1 OZ VPWR $end +$var supply0 1 PZ VGND $end +$var supply1 1 QZ VPB $end +$var supply0 1 RZ VNB $end + +$scope module base $end +$var wire 1 >L Q $end +$var wire 1 qJ CLK $end +$var wire 1 %M D $end +$var wire 1 NH RESET_B $end +$var wire 1 SZ buf_Q $end +$var wire 1 TZ RESET $end +$upscope $end +$upscope $end + +$scope module sky130_fd_sc_hd__dfrtp_1_1_ $end +$var wire 1 ?L Q $end +$var wire 1 qJ CLK $end +$var wire 1 >L D $end +$var wire 1 NH RESET_B $end +$var supply1 1 UZ VPWR $end +$var supply0 1 VZ VGND $end +$var supply1 1 WZ VPB $end +$var supply0 1 XZ VNB $end + +$scope module base $end +$var wire 1 ?L Q $end +$var wire 1 qJ CLK $end +$var wire 1 >L D $end +$var wire 1 NH RESET_B $end +$var wire 1 YZ buf_Q $end +$var wire 1 ZZ RESET $end +$upscope $end +$upscope $end + +$scope module sky130_fd_sc_hd__dfrtp_1_2_ $end +$var wire 1 @L Q $end +$var wire 1 qJ CLK $end +$var wire 1 ?L D $end +$var wire 1 NH RESET_B $end +$var supply1 1 [Z VPWR $end +$var supply0 1 \Z VGND $end +$var supply1 1 ]Z VPB $end +$var supply0 1 ^Z VNB $end + +$scope module base $end +$var wire 1 @L Q $end +$var wire 1 qJ CLK $end +$var wire 1 ?L D $end +$var wire 1 NH RESET_B $end +$var wire 1 _Z buf_Q $end +$var wire 1 `Z RESET $end +$upscope $end +$upscope $end + +$scope module sky130_fd_sc_hd__dfrtp_1_3_ $end +$var wire 1 AL Q $end +$var wire 1 qJ CLK $end +$var wire 1 @L D $end +$var wire 1 NH RESET_B $end +$var supply1 1 aZ VPWR $end +$var supply0 1 bZ VGND $end +$var supply1 1 cZ VPB $end +$var supply0 1 dZ VNB $end + +$scope module base $end +$var wire 1 AL Q $end +$var wire 1 qJ CLK $end +$var wire 1 @L D $end +$var wire 1 NH RESET_B $end +$var wire 1 eZ buf_Q $end +$var wire 1 fZ RESET $end +$upscope $end +$upscope $end + +$scope module FTB_23__22 $end +$var wire 1 `L X $end +$var wire 1 AL A $end +$var supply1 1 gZ VPWR $end +$var supply0 1 hZ VGND $end +$var supply1 1 iZ VPB $end +$var supply0 1 jZ VNB $end + +$scope module base $end +$var wire 1 `L X $end +$var wire 1 AL A $end +$var wire 1 kZ buf0_out_X $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mem_right_track_20 $end +$var wire 1 NH pReset [0] $end +$var wire 1 qJ prog_clk [0] $end +$var wire 1 `L ccff_head [0] $end +$var wire 1 aL ccff_tail [0] $end +$var wire 1 BL mem_out [0] $end +$var wire 1 CL mem_out [1] $end +$var wire 1 DL mem_out [2] $end +$var wire 1 EL mem_out [3] $end + +$scope module sky130_fd_sc_hd__dfrtp_1_0_ $end +$var wire 1 BL Q $end +$var wire 1 qJ CLK $end +$var wire 1 `L D $end +$var wire 1 NH RESET_B $end +$var supply1 1 lZ VPWR $end +$var supply0 1 mZ VGND $end +$var supply1 1 nZ VPB $end +$var supply0 1 oZ VNB $end + +$scope module base $end +$var wire 1 BL Q $end +$var wire 1 qJ CLK $end +$var wire 1 `L D $end +$var wire 1 NH RESET_B $end +$var wire 1 pZ buf_Q $end +$var wire 1 qZ RESET $end +$upscope $end +$upscope $end + +$scope module sky130_fd_sc_hd__dfrtp_1_1_ $end +$var wire 1 CL Q $end +$var wire 1 qJ CLK $end +$var wire 1 BL D $end +$var wire 1 NH RESET_B $end +$var supply1 1 rZ VPWR $end +$var supply0 1 sZ VGND $end +$var supply1 1 tZ VPB $end +$var supply0 1 uZ VNB $end + +$scope module base $end +$var wire 1 CL Q $end +$var wire 1 qJ CLK $end +$var wire 1 BL D $end +$var wire 1 NH RESET_B $end +$var wire 1 vZ buf_Q $end +$var wire 1 wZ RESET $end +$upscope $end +$upscope $end + +$scope module sky130_fd_sc_hd__dfrtp_1_2_ $end +$var wire 1 DL Q $end +$var wire 1 qJ CLK $end +$var wire 1 CL D $end +$var wire 1 NH RESET_B $end +$var supply1 1 xZ VPWR $end +$var supply0 1 yZ VGND $end +$var supply1 1 zZ VPB $end +$var supply0 1 {Z VNB $end + +$scope module base $end +$var wire 1 DL Q $end +$var wire 1 qJ CLK $end +$var wire 1 CL D $end +$var wire 1 NH RESET_B $end +$var wire 1 |Z buf_Q $end +$var wire 1 }Z RESET $end +$upscope $end +$upscope $end + +$scope module sky130_fd_sc_hd__dfrtp_1_3_ $end +$var wire 1 EL Q $end +$var wire 1 qJ CLK $end +$var wire 1 DL D $end +$var wire 1 NH RESET_B $end +$var supply1 1 ~Z VPWR $end +$var supply0 1 ![ VGND $end +$var supply1 1 "[ VPB $end +$var supply0 1 #[ VNB $end + +$scope module base $end +$var wire 1 EL Q $end +$var wire 1 qJ CLK $end +$var wire 1 DL D $end +$var wire 1 NH RESET_B $end +$var wire 1 $[ buf_Q $end +$var wire 1 %[ RESET $end +$upscope $end +$upscope $end + +$scope module FTB_24__23 $end +$var wire 1 aL X $end +$var wire 1 EL A $end +$var supply1 1 &[ VPWR $end +$var supply0 1 '[ VGND $end +$var supply1 1 ([ VPB $end +$var supply0 1 )[ VNB $end + +$scope module base $end +$var wire 1 aL X $end +$var wire 1 EL A $end +$var wire 1 *[ buf0_out_X $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mem_right_track_28 $end +$var wire 1 NH pReset [0] $end +$var wire 1 qJ prog_clk [0] $end +$var wire 1 aL ccff_head [0] $end +$var wire 1 bL ccff_tail [0] $end +$var wire 1 FL mem_out [0] $end +$var wire 1 GL mem_out [1] $end +$var wire 1 HL mem_out [2] $end +$var wire 1 IL mem_out [3] $end + +$scope module sky130_fd_sc_hd__dfrtp_1_0_ $end +$var wire 1 FL Q $end +$var wire 1 qJ CLK $end +$var wire 1 aL D $end +$var wire 1 NH RESET_B $end +$var supply1 1 +[ VPWR $end +$var supply0 1 ,[ VGND $end +$var supply1 1 -[ VPB $end +$var supply0 1 .[ VNB $end + +$scope module base $end +$var wire 1 FL Q $end +$var wire 1 qJ CLK $end +$var wire 1 aL D $end +$var wire 1 NH RESET_B $end +$var wire 1 /[ buf_Q $end +$var wire 1 0[ RESET $end +$upscope $end +$upscope $end + +$scope module sky130_fd_sc_hd__dfrtp_1_1_ $end +$var wire 1 GL Q $end +$var wire 1 qJ CLK $end +$var wire 1 FL D $end +$var wire 1 NH RESET_B $end +$var supply1 1 1[ VPWR $end +$var supply0 1 2[ VGND $end +$var supply1 1 3[ VPB $end +$var supply0 1 4[ VNB $end + +$scope module base $end +$var wire 1 GL Q $end +$var wire 1 qJ CLK $end +$var wire 1 FL D $end +$var wire 1 NH RESET_B $end +$var wire 1 5[ buf_Q $end +$var wire 1 6[ RESET $end +$upscope $end +$upscope $end + +$scope module sky130_fd_sc_hd__dfrtp_1_2_ $end +$var wire 1 HL Q $end +$var wire 1 qJ CLK $end +$var wire 1 GL D $end +$var wire 1 NH RESET_B $end +$var supply1 1 7[ VPWR $end +$var supply0 1 8[ VGND $end +$var supply1 1 9[ VPB $end +$var supply0 1 :[ VNB $end + +$scope module base $end +$var wire 1 HL Q $end +$var wire 1 qJ CLK $end +$var wire 1 GL D $end +$var wire 1 NH RESET_B $end +$var wire 1 ;[ buf_Q $end +$var wire 1 <[ RESET $end +$upscope $end +$upscope $end + +$scope module sky130_fd_sc_hd__dfrtp_1_3_ $end +$var wire 1 IL Q $end +$var wire 1 qJ CLK $end +$var wire 1 HL D $end +$var wire 1 NH RESET_B $end +$var supply1 1 =[ VPWR $end +$var supply0 1 >[ VGND $end +$var supply1 1 ?[ VPB $end +$var supply0 1 @[ VNB $end + +$scope module base $end +$var wire 1 IL Q $end +$var wire 1 qJ CLK $end +$var wire 1 HL D $end +$var wire 1 NH RESET_B $end +$var wire 1 A[ buf_Q $end +$var wire 1 B[ RESET $end +$upscope $end +$upscope $end + +$scope module FTB_25__24 $end +$var wire 1 bL X $end +$var wire 1 IL A $end +$var supply1 1 C[ VPWR $end +$var supply0 1 D[ VGND $end +$var supply1 1 E[ VPB $end +$var supply0 1 F[ VNB $end + +$scope module base $end +$var wire 1 bL X $end +$var wire 1 IL A $end +$var wire 1 G[ buf0_out_X $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mem_left_track_3 $end +$var wire 1 NH pReset [0] $end +$var wire 1 qJ prog_clk [0] $end +$var wire 1 vL ccff_head [0] $end +$var wire 1 cL ccff_tail [0] $end +$var wire 1 JL mem_out [0] $end +$var wire 1 KL mem_out [1] $end +$var wire 1 LL mem_out [2] $end +$var wire 1 ML mem_out [3] $end + +$scope module sky130_fd_sc_hd__dfrtp_1_0_ $end +$var wire 1 JL Q $end +$var wire 1 qJ CLK $end +$var wire 1 vL D $end +$var wire 1 NH RESET_B $end +$var supply1 1 H[ VPWR $end +$var supply0 1 I[ VGND $end +$var supply1 1 J[ VPB $end +$var supply0 1 K[ VNB $end + +$scope module base $end +$var wire 1 JL Q $end +$var wire 1 qJ CLK $end +$var wire 1 vL D $end +$var wire 1 NH RESET_B $end +$var wire 1 L[ buf_Q $end +$var wire 1 M[ RESET $end +$upscope $end +$upscope $end + +$scope module sky130_fd_sc_hd__dfrtp_1_1_ $end +$var wire 1 KL Q $end +$var wire 1 qJ CLK $end +$var wire 1 JL D $end +$var wire 1 NH RESET_B $end +$var supply1 1 N[ VPWR $end +$var supply0 1 O[ VGND $end +$var supply1 1 P[ VPB $end +$var supply0 1 Q[ VNB $end + +$scope module base $end +$var wire 1 KL Q $end +$var wire 1 qJ CLK $end +$var wire 1 JL D $end +$var wire 1 NH RESET_B $end +$var wire 1 R[ buf_Q $end +$var wire 1 S[ RESET $end +$upscope $end +$upscope $end + +$scope module sky130_fd_sc_hd__dfrtp_1_2_ $end +$var wire 1 LL Q $end +$var wire 1 qJ CLK $end +$var wire 1 KL D $end +$var wire 1 NH RESET_B $end +$var supply1 1 T[ VPWR $end +$var supply0 1 U[ VGND $end +$var supply1 1 V[ VPB $end +$var supply0 1 W[ VNB $end + +$scope module base $end +$var wire 1 LL Q $end +$var wire 1 qJ CLK $end +$var wire 1 KL D $end +$var wire 1 NH RESET_B $end +$var wire 1 X[ buf_Q $end +$var wire 1 Y[ RESET $end +$upscope $end +$upscope $end + +$scope module sky130_fd_sc_hd__dfrtp_1_3_ $end +$var wire 1 ML Q $end +$var wire 1 qJ CLK $end +$var wire 1 LL D $end +$var wire 1 NH RESET_B $end +$var supply1 1 Z[ VPWR $end +$var supply0 1 [[ VGND $end +$var supply1 1 \[ VPB $end +$var supply0 1 ][ VNB $end + +$scope module base $end +$var wire 1 ML Q $end +$var wire 1 qJ CLK $end +$var wire 1 LL D $end +$var wire 1 NH RESET_B $end +$var wire 1 ^[ buf_Q $end +$var wire 1 _[ RESET $end +$upscope $end +$upscope $end + +$scope module FTB_26__25 $end +$var wire 1 cL X $end +$var wire 1 ML A $end +$var supply1 1 `[ VPWR $end +$var supply0 1 a[ VGND $end +$var supply1 1 b[ VPB $end +$var supply0 1 c[ VNB $end + +$scope module base $end +$var wire 1 cL X $end +$var wire 1 ML A $end +$var wire 1 d[ buf0_out_X $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mem_left_track_5 $end +$var wire 1 NH pReset [0] $end +$var wire 1 qJ prog_clk [0] $end +$var wire 1 cL ccff_head [0] $end +$var wire 1 dL ccff_tail [0] $end +$var wire 1 NL mem_out [0] $end +$var wire 1 OL mem_out [1] $end +$var wire 1 PL mem_out [2] $end +$var wire 1 QL mem_out [3] $end + +$scope module sky130_fd_sc_hd__dfrtp_1_0_ $end +$var wire 1 NL Q $end +$var wire 1 qJ CLK $end +$var wire 1 cL D $end +$var wire 1 NH RESET_B $end +$var supply1 1 e[ VPWR $end +$var supply0 1 f[ VGND $end +$var supply1 1 g[ VPB $end +$var supply0 1 h[ VNB $end + +$scope module base $end +$var wire 1 NL Q $end +$var wire 1 qJ CLK $end +$var wire 1 cL D $end +$var wire 1 NH RESET_B $end +$var wire 1 i[ buf_Q $end +$var wire 1 j[ RESET $end +$upscope $end +$upscope $end + +$scope module sky130_fd_sc_hd__dfrtp_1_1_ $end +$var wire 1 OL Q $end +$var wire 1 qJ CLK $end +$var wire 1 NL D $end +$var wire 1 NH RESET_B $end +$var supply1 1 k[ VPWR $end +$var supply0 1 l[ VGND $end +$var supply1 1 m[ VPB $end +$var supply0 1 n[ VNB $end + +$scope module base $end +$var wire 1 OL Q $end +$var wire 1 qJ CLK $end +$var wire 1 NL D $end +$var wire 1 NH RESET_B $end +$var wire 1 o[ buf_Q $end +$var wire 1 p[ RESET $end +$upscope $end +$upscope $end + +$scope module sky130_fd_sc_hd__dfrtp_1_2_ $end +$var wire 1 PL Q $end +$var wire 1 qJ CLK $end +$var wire 1 OL D $end +$var wire 1 NH RESET_B $end +$var supply1 1 q[ VPWR $end +$var supply0 1 r[ VGND $end +$var supply1 1 s[ VPB $end +$var supply0 1 t[ VNB $end + +$scope module base $end +$var wire 1 PL Q $end +$var wire 1 qJ CLK $end +$var wire 1 OL D $end +$var wire 1 NH RESET_B $end +$var wire 1 u[ buf_Q $end +$var wire 1 v[ RESET $end +$upscope $end +$upscope $end + +$scope module sky130_fd_sc_hd__dfrtp_1_3_ $end +$var wire 1 QL Q $end +$var wire 1 qJ CLK $end +$var wire 1 PL D $end +$var wire 1 NH RESET_B $end +$var supply1 1 w[ VPWR $end +$var supply0 1 x[ VGND $end +$var supply1 1 y[ VPB $end +$var supply0 1 z[ VNB $end + +$scope module base $end +$var wire 1 QL Q $end +$var wire 1 qJ CLK $end +$var wire 1 PL D $end +$var wire 1 NH RESET_B $end +$var wire 1 {[ buf_Q $end +$var wire 1 |[ RESET $end +$upscope $end +$upscope $end + +$scope module FTB_27__26 $end +$var wire 1 dL X $end +$var wire 1 QL A $end +$var supply1 1 }[ VPWR $end +$var supply0 1 ~[ VGND $end +$var supply1 1 !\ VPB $end +$var supply0 1 "\ VNB $end + +$scope module base $end +$var wire 1 dL X $end +$var wire 1 QL A $end +$var wire 1 #\ buf0_out_X $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mem_left_track_13 $end +$var wire 1 NH pReset [0] $end +$var wire 1 qJ prog_clk [0] $end +$var wire 1 'M ccff_head [0] $end +$var wire 1 eL ccff_tail [0] $end +$var wire 1 RL mem_out [0] $end +$var wire 1 SL mem_out [1] $end +$var wire 1 TL mem_out [2] $end +$var wire 1 UL mem_out [3] $end + +$scope module sky130_fd_sc_hd__dfrtp_1_0_ $end +$var wire 1 RL Q $end +$var wire 1 qJ CLK $end +$var wire 1 'M D $end +$var wire 1 NH RESET_B $end +$var supply1 1 $\ VPWR $end +$var supply0 1 %\ VGND $end +$var supply1 1 &\ VPB $end +$var supply0 1 '\ VNB $end + +$scope module base $end +$var wire 1 RL Q $end +$var wire 1 qJ CLK $end +$var wire 1 'M D $end +$var wire 1 NH RESET_B $end +$var wire 1 (\ buf_Q $end +$var wire 1 )\ RESET $end +$upscope $end +$upscope $end + +$scope module sky130_fd_sc_hd__dfrtp_1_1_ $end +$var wire 1 SL Q $end +$var wire 1 qJ CLK $end +$var wire 1 RL D $end +$var wire 1 NH RESET_B $end +$var supply1 1 *\ VPWR $end +$var supply0 1 +\ VGND $end +$var supply1 1 ,\ VPB $end +$var supply0 1 -\ VNB $end + +$scope module base $end +$var wire 1 SL Q $end +$var wire 1 qJ CLK $end +$var wire 1 RL D $end +$var wire 1 NH RESET_B $end +$var wire 1 .\ buf_Q $end +$var wire 1 /\ RESET $end +$upscope $end +$upscope $end + +$scope module sky130_fd_sc_hd__dfrtp_1_2_ $end +$var wire 1 TL Q $end +$var wire 1 qJ CLK $end +$var wire 1 SL D $end +$var wire 1 NH RESET_B $end +$var supply1 1 0\ VPWR $end +$var supply0 1 1\ VGND $end +$var supply1 1 2\ VPB $end +$var supply0 1 3\ VNB $end + +$scope module base $end +$var wire 1 TL Q $end +$var wire 1 qJ CLK $end +$var wire 1 SL D $end +$var wire 1 NH RESET_B $end +$var wire 1 4\ buf_Q $end +$var wire 1 5\ RESET $end +$upscope $end +$upscope $end + +$scope module sky130_fd_sc_hd__dfrtp_1_3_ $end +$var wire 1 UL Q $end +$var wire 1 qJ CLK $end +$var wire 1 TL D $end +$var wire 1 NH RESET_B $end +$var supply1 1 6\ VPWR $end +$var supply0 1 7\ VGND $end +$var supply1 1 8\ VPB $end +$var supply0 1 9\ VNB $end + +$scope module base $end +$var wire 1 UL Q $end +$var wire 1 qJ CLK $end +$var wire 1 TL D $end +$var wire 1 NH RESET_B $end +$var wire 1 :\ buf_Q $end +$var wire 1 ;\ RESET $end +$upscope $end +$upscope $end + +$scope module FTB_28__27 $end +$var wire 1 eL X $end +$var wire 1 UL A $end +$var supply1 1 <\ VPWR $end +$var supply0 1 =\ VGND $end +$var supply1 1 >\ VPB $end +$var supply0 1 ?\ VNB $end + +$scope module base $end +$var wire 1 eL X $end +$var wire 1 UL A $end +$var wire 1 @\ buf0_out_X $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mem_left_track_21 $end +$var wire 1 NH pReset [0] $end +$var wire 1 qJ prog_clk [0] $end +$var wire 1 eL ccff_head [0] $end +$var wire 1 fL ccff_tail [0] $end +$var wire 1 VL mem_out [0] $end +$var wire 1 WL mem_out [1] $end +$var wire 1 XL mem_out [2] $end +$var wire 1 YL mem_out [3] $end + +$scope module sky130_fd_sc_hd__dfrtp_1_0_ $end +$var wire 1 VL Q $end +$var wire 1 qJ CLK $end +$var wire 1 eL D $end +$var wire 1 NH RESET_B $end +$var supply1 1 A\ VPWR $end +$var supply0 1 B\ VGND $end +$var supply1 1 C\ VPB $end +$var supply0 1 D\ VNB $end + +$scope module base $end +$var wire 1 VL Q $end +$var wire 1 qJ CLK $end +$var wire 1 eL D $end +$var wire 1 NH RESET_B $end +$var wire 1 E\ buf_Q $end +$var wire 1 F\ RESET $end +$upscope $end +$upscope $end + +$scope module sky130_fd_sc_hd__dfrtp_1_1_ $end +$var wire 1 WL Q $end +$var wire 1 qJ CLK $end +$var wire 1 VL D $end +$var wire 1 NH RESET_B $end +$var supply1 1 G\ VPWR $end +$var supply0 1 H\ VGND $end +$var supply1 1 I\ VPB $end +$var supply0 1 J\ VNB $end + +$scope module base $end +$var wire 1 WL Q $end +$var wire 1 qJ CLK $end +$var wire 1 VL D $end +$var wire 1 NH RESET_B $end +$var wire 1 K\ buf_Q $end +$var wire 1 L\ RESET $end +$upscope $end +$upscope $end + +$scope module sky130_fd_sc_hd__dfrtp_1_2_ $end +$var wire 1 XL Q $end +$var wire 1 qJ CLK $end +$var wire 1 WL D $end +$var wire 1 NH RESET_B $end +$var supply1 1 M\ VPWR $end +$var supply0 1 N\ VGND $end +$var supply1 1 O\ VPB $end +$var supply0 1 P\ VNB $end + +$scope module base $end +$var wire 1 XL Q $end +$var wire 1 qJ CLK $end +$var wire 1 WL D $end +$var wire 1 NH RESET_B $end +$var wire 1 Q\ buf_Q $end +$var wire 1 R\ RESET $end +$upscope $end +$upscope $end + +$scope module sky130_fd_sc_hd__dfrtp_1_3_ $end +$var wire 1 YL Q $end +$var wire 1 qJ CLK $end +$var wire 1 XL D $end +$var wire 1 NH RESET_B $end +$var supply1 1 S\ VPWR $end +$var supply0 1 T\ VGND $end +$var supply1 1 U\ VPB $end +$var supply0 1 V\ VNB $end + +$scope module base $end +$var wire 1 YL Q $end +$var wire 1 qJ CLK $end +$var wire 1 XL D $end +$var wire 1 NH RESET_B $end +$var wire 1 W\ buf_Q $end +$var wire 1 X\ RESET $end +$upscope $end +$upscope $end + +$scope module FTB_29__28 $end +$var wire 1 fL X $end +$var wire 1 YL A $end +$var supply1 1 Y\ VPWR $end +$var supply0 1 Z\ VGND $end +$var supply1 1 [\ VPB $end +$var supply0 1 \\ VNB $end + +$scope module base $end +$var wire 1 fL X $end +$var wire 1 YL A $end +$var wire 1 ]\ buf0_out_X $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mem_left_track_29 $end +$var wire 1 NH pReset [0] $end +$var wire 1 qJ prog_clk [0] $end +$var wire 1 fL ccff_head [0] $end +$var wire 1 gL ccff_tail [0] $end +$var wire 1 ZL mem_out [0] $end +$var wire 1 [L mem_out [1] $end +$var wire 1 \L mem_out [2] $end +$var wire 1 ]L mem_out [3] $end + +$scope module sky130_fd_sc_hd__dfrtp_1_0_ $end +$var wire 1 ZL Q $end +$var wire 1 qJ CLK $end +$var wire 1 fL D $end +$var wire 1 NH RESET_B $end +$var supply1 1 ^\ VPWR $end +$var supply0 1 _\ VGND $end +$var supply1 1 `\ VPB $end +$var supply0 1 a\ VNB $end + +$scope module base $end +$var wire 1 ZL Q $end +$var wire 1 qJ CLK $end +$var wire 1 fL D $end +$var wire 1 NH RESET_B $end +$var wire 1 b\ buf_Q $end +$var wire 1 c\ RESET $end +$upscope $end +$upscope $end + +$scope module sky130_fd_sc_hd__dfrtp_1_1_ $end +$var wire 1 [L Q $end +$var wire 1 qJ CLK $end +$var wire 1 ZL D $end +$var wire 1 NH RESET_B $end +$var supply1 1 d\ VPWR $end +$var supply0 1 e\ VGND $end +$var supply1 1 f\ VPB $end +$var supply0 1 g\ VNB $end + +$scope module base $end +$var wire 1 [L Q $end +$var wire 1 qJ CLK $end +$var wire 1 ZL D $end +$var wire 1 NH RESET_B $end +$var wire 1 h\ buf_Q $end +$var wire 1 i\ RESET $end +$upscope $end +$upscope $end + +$scope module sky130_fd_sc_hd__dfrtp_1_2_ $end +$var wire 1 \L Q $end +$var wire 1 qJ CLK $end +$var wire 1 [L D $end +$var wire 1 NH RESET_B $end +$var supply1 1 j\ VPWR $end +$var supply0 1 k\ VGND $end +$var supply1 1 l\ VPB $end +$var supply0 1 m\ VNB $end + +$scope module base $end +$var wire 1 \L Q $end +$var wire 1 qJ CLK $end +$var wire 1 [L D $end +$var wire 1 NH RESET_B $end +$var wire 1 n\ buf_Q $end +$var wire 1 o\ RESET $end +$upscope $end +$upscope $end + +$scope module sky130_fd_sc_hd__dfrtp_1_3_ $end +$var wire 1 ]L Q $end +$var wire 1 qJ CLK $end +$var wire 1 \L D $end +$var wire 1 NH RESET_B $end +$var supply1 1 p\ VPWR $end +$var supply0 1 q\ VGND $end +$var supply1 1 r\ VPB $end +$var supply0 1 s\ VNB $end + +$scope module base $end +$var wire 1 ]L Q $end +$var wire 1 qJ CLK $end +$var wire 1 \L D $end +$var wire 1 NH RESET_B $end +$var wire 1 t\ buf_Q $end +$var wire 1 u\ RESET $end +$upscope $end +$upscope $end + +$scope module FTB_30__29 $end +$var wire 1 gL X $end +$var wire 1 ]L A $end +$var supply1 1 v\ VPWR $end +$var supply0 1 w\ VGND $end +$var supply1 1 x\ VPB $end +$var supply0 1 y\ VNB $end + +$scope module base $end +$var wire 1 gL X $end +$var wire 1 ]L A $end +$var wire 1 z\ buf0_out_X $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mux_top_track_2 $end +$var wire 1 yI in [0] $end +$var wire 1 qH in [1] $end +$var wire 1 tH in [2] $end +$var wire 1 wH in [3] $end +$var wire 1 KJ in [4] $end +$var wire 1 -J in [5] $end +$var wire 1 'L sram [0] $end +$var wire 1 (L sram [1] $end +$var wire 1 )L sram [2] $end +$var wire 1 *L sram [3] $end +$var wire 1 UM sram_inv [0] $end +$var wire 1 VM sram_inv [1] $end +$var wire 1 WM sram_inv [2] $end +$var wire 1 XM sram_inv [3] $end +$var wire 1 gI out [0] $end +$var wire 1 GM p0 $end +$var wire 1 {\ local_encoder2to3_0_data [0] $end +$var wire 1 |\ local_encoder2to3_0_data [1] $end +$var wire 1 }\ local_encoder2to3_0_data [2] $end +$var wire 1 ~\ local_encoder2to3_0_data_inv [0] $end +$var wire 1 !] local_encoder2to3_0_data_inv [1] $end +$var wire 1 "] local_encoder2to3_0_data_inv [2] $end +$var wire 1 #] local_encoder2to3_1_data [0] $end +$var wire 1 $] local_encoder2to3_1_data [1] $end +$var wire 1 %] local_encoder2to3_1_data [2] $end +$var wire 1 &] local_encoder2to3_1_data_inv [0] $end +$var wire 1 '] local_encoder2to3_1_data_inv [1] $end +$var wire 1 (] local_encoder2to3_1_data_inv [2] $end +$var wire 1 )] mux_2level_tapbuf_basis_input3_mem3_0_out [0] $end +$var wire 1 *] mux_2level_tapbuf_basis_input3_mem3_1_out [0] $end +$var wire 1 +] mux_2level_tapbuf_basis_input3_mem3_2_out [0] $end +$var wire 1 ,] SYNOPSYS_UNCONNECTED_1 $end +$var wire 1 -] BUF_net_150 $end + +$scope module local_encoder2to3_0_ $end +$var wire 1 'L addr [0] $end +$var wire 1 (L addr [1] $end +$var wire 1 {\ data [0] $end +$var wire 1 |\ data [1] $end +$var wire 1 }\ data [2] $end +$var wire 1 ~\ data_inv [0] $end +$var wire 1 !] data_inv [1] $end +$var wire 1 "] data_inv [2] $end + +$scope module U8 $end +$var wire 1 ~\ Y $end +$var wire 1 {\ A $end +$var supply1 1 .] VPWR $end +$var supply0 1 /] VGND $end +$var supply1 1 0] VPB $end +$var supply0 1 1] VNB $end + +$scope module base $end +$var wire 1 ~\ Y $end +$var wire 1 {\ A $end +$var wire 1 2] not0_out_Y $end +$upscope $end +$upscope $end + +$scope module U9 $end +$var wire 1 |\ Y $end +$var wire 1 !] A $end +$var supply1 1 3] VPWR $end +$var supply0 1 4] VGND $end +$var supply1 1 5] VPB $end +$var supply0 1 6] VNB $end + +$scope module base $end +$var wire 1 |\ Y $end +$var wire 1 !] A $end +$var wire 1 7] not0_out_Y $end +$upscope $end +$upscope $end + +$scope module U10 $end +$var wire 1 !] Y $end +$var wire 1 'L A $end +$var wire 1 "] B $end +$var supply1 1 8] VPWR $end +$var supply0 1 9] VGND $end +$var supply1 1 :] VPB $end +$var supply0 1 ;] VNB $end + +$scope module base $end +$var wire 1 !] Y $end +$var wire 1 'L A $end +$var wire 1 "] B $end +$var wire 1 <] nand0_out_Y $end +$upscope $end +$upscope $end + +$scope module U11 $end +$var wire 1 "] Y $end +$var wire 1 }\ A $end +$var supply1 1 =] VPWR $end +$var supply0 1 >] VGND $end +$var supply1 1 ?] VPB $end +$var supply0 1 @] VNB $end + +$scope module base $end +$var wire 1 "] Y $end +$var wire 1 }\ A $end +$var wire 1 A] not0_out_Y $end +$upscope $end +$upscope $end + +$scope module U12 $end +$var wire 1 {\ Y $end +$var wire 1 }\ A $end +$var wire 1 'L B $end +$var supply1 1 B] VPWR $end +$var supply0 1 C] VGND $end +$var supply1 1 D] VPB $end +$var supply0 1 E] VNB $end + +$scope module base $end +$var wire 1 {\ Y $end +$var wire 1 }\ A $end +$var wire 1 'L B $end +$var wire 1 F] nor0_out_Y $end +$upscope $end +$upscope $end + +$scope module FTB_31__30 $end +$var wire 1 }\ X $end +$var wire 1 (L A $end +$var supply1 1 G] VPWR $end +$var supply0 1 H] VGND $end +$var supply1 1 I] VPB $end +$var supply0 1 J] VNB $end + +$scope module base $end +$var wire 1 }\ X $end +$var wire 1 (L A $end +$var wire 1 K] buf0_out_X $end +$upscope $end +$upscope $end +$upscope $end + +$scope module local_encoder2to3_1_ $end +$var wire 1 )L addr [0] $end +$var wire 1 *L addr [1] $end +$var wire 1 #] data [0] $end +$var wire 1 $] data [1] $end +$var wire 1 %] data [2] $end +$var wire 1 &] data_inv [0] $end +$var wire 1 '] data_inv [1] $end +$var wire 1 (] data_inv [2] $end + +$scope module U8 $end +$var wire 1 &] Y $end +$var wire 1 #] A $end +$var supply1 1 L] VPWR $end +$var supply0 1 M] VGND $end +$var supply1 1 N] VPB $end +$var supply0 1 O] VNB $end + +$scope module base $end +$var wire 1 &] Y $end +$var wire 1 #] A $end +$var wire 1 P] not0_out_Y $end +$upscope $end +$upscope $end + +$scope module U9 $end +$var wire 1 $] Y $end +$var wire 1 '] A $end +$var supply1 1 Q] VPWR $end +$var supply0 1 R] VGND $end +$var supply1 1 S] VPB $end +$var supply0 1 T] VNB $end + +$scope module base $end +$var wire 1 $] Y $end +$var wire 1 '] A $end +$var wire 1 U] not0_out_Y $end +$upscope $end +$upscope $end + +$scope module U10 $end +$var wire 1 '] Y $end +$var wire 1 )L A $end +$var wire 1 (] B $end +$var supply1 1 V] VPWR $end +$var supply0 1 W] VGND $end +$var supply1 1 X] VPB $end +$var supply0 1 Y] VNB $end + +$scope module base $end +$var wire 1 '] Y $end +$var wire 1 )L A $end +$var wire 1 (] B $end +$var wire 1 Z] nand0_out_Y $end +$upscope $end +$upscope $end + +$scope module U11 $end +$var wire 1 (] Y $end +$var wire 1 %] A $end +$var supply1 1 [] VPWR $end +$var supply0 1 \] VGND $end +$var supply1 1 ]] VPB $end +$var supply0 1 ^] VNB $end + +$scope module base $end +$var wire 1 (] Y $end +$var wire 1 %] A $end +$var wire 1 _] not0_out_Y $end +$upscope $end +$upscope $end + +$scope module U12 $end +$var wire 1 #] Y $end +$var wire 1 %] A $end +$var wire 1 )L B $end +$var supply1 1 `] VPWR $end +$var supply0 1 a] VGND $end +$var supply1 1 b] VPB $end +$var supply0 1 c] VNB $end + +$scope module base $end +$var wire 1 #] Y $end +$var wire 1 %] A $end +$var wire 1 )L B $end +$var wire 1 d] nor0_out_Y $end +$upscope $end +$upscope $end + +$scope module FTB_32__31 $end +$var wire 1 %] X $end +$var wire 1 *L A $end +$var supply1 1 e] VPWR $end +$var supply0 1 f] VGND $end +$var supply1 1 g] VPB $end +$var supply0 1 h] VNB $end + +$scope module base $end +$var wire 1 %] X $end +$var wire 1 *L A $end +$var wire 1 i] buf0_out_X $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mux_l1_in_0_ $end +$var wire 1 yI in [0] $end +$var wire 1 qH in [1] $end +$var wire 1 tH in [2] $end +$var wire 1 {\ mem [0] $end +$var wire 1 |\ mem [1] $end +$var wire 1 }\ mem [2] $end +$var wire 1 ~\ mem_inv [0] $end +$var wire 1 !] mem_inv [1] $end +$var wire 1 "] mem_inv [2] $end +$var wire 1 )] out [0] $end + +$scope module scs8hd_muxinv3_1_0 $end +$var wire 1 )] Z $end +$var wire 1 yI Q1 $end +$var wire 1 qH Q2 $end +$var wire 1 tH Q3 $end +$var wire 1 {\ S0 $end +$var wire 1 ~\ S0B $end +$var wire 1 |\ S1 $end +$var wire 1 !] S1B $end +$var wire 1 }\ S2 $end +$var wire 1 "] S2B $end +$var wire 1 j] Q1__bar $end +$var wire 1 k] Q2__bar $end +$var wire 1 l] Q3__bar $end +$upscope $end +$upscope $end + +$scope module mux_l1_in_1_ $end +$var wire 1 wH in [0] $end +$var wire 1 KJ in [1] $end +$var wire 1 -J in [2] $end +$var wire 1 {\ mem [0] $end +$var wire 1 |\ mem [1] $end +$var wire 1 }\ mem [2] $end +$var wire 1 ~\ mem_inv [0] $end +$var wire 1 !] mem_inv [1] $end +$var wire 1 "] mem_inv [2] $end +$var wire 1 *] out [0] $end + +$scope module scs8hd_muxinv3_1_0 $end +$var wire 1 *] Z $end +$var wire 1 wH Q1 $end +$var wire 1 KJ Q2 $end +$var wire 1 -J Q3 $end +$var wire 1 {\ S0 $end +$var wire 1 ~\ S0B $end +$var wire 1 |\ S1 $end +$var wire 1 !] S1B $end +$var wire 1 }\ S2 $end +$var wire 1 "] S2B $end +$var wire 1 m] Q1__bar $end +$var wire 1 n] Q2__bar $end +$var wire 1 o] Q3__bar $end +$upscope $end +$upscope $end + +$scope module mux_l2_in_0_ $end +$var wire 1 )] in [0] $end +$var wire 1 *] in [1] $end +$var wire 1 ,] in [2] $end +$var wire 1 #] mem [0] $end +$var wire 1 $] mem [1] $end +$var wire 1 %] mem [2] $end +$var wire 1 &] mem_inv [0] $end +$var wire 1 '] mem_inv [1] $end +$var wire 1 (] mem_inv [2] $end +$var wire 1 +] out [0] $end +$var wire 1 GM p0 $end + +$scope module scs8hd_muxinv3_1_0 $end +$var wire 1 +] Z $end +$var wire 1 )] Q1 $end +$var wire 1 *] Q2 $end +$var wire 1 GM Q3 $end +$var wire 1 #] S0 $end +$var wire 1 &] S0B $end +$var wire 1 $] S1 $end +$var wire 1 '] S1B $end +$var wire 1 %] S2 $end +$var wire 1 (] S2B $end +$var wire 1 p] Q1__bar $end +$var wire 1 q] Q2__bar $end +$var wire 1 r] Q3__bar $end +$upscope $end +$upscope $end + +$scope module BINV_R_149 $end +$var wire 1 gI Y $end +$var wire 1 -] A $end +$var supply1 1 s] VPWR $end +$var supply0 1 t] VGND $end +$var supply1 1 u] VPB $end +$var supply0 1 v] VNB $end + +$scope module base $end +$var wire 1 gI Y $end +$var wire 1 -] A $end +$var wire 1 w] not0_out_Y $end +$upscope $end +$upscope $end + +$scope module BINV_R_150 $end +$var wire 1 -] Y $end +$var wire 1 +] A $end +$var supply1 1 x] VPWR $end +$var supply0 1 y] VGND $end +$var supply1 1 z] VPB $end +$var supply0 1 {] VNB $end + +$scope module base $end +$var wire 1 -] Y $end +$var wire 1 +] A $end +$var wire 1 |] not0_out_Y $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mux_top_track_6 $end +$var wire 1 mH in [0] $end +$var wire 1 pH in [1] $end +$var wire 1 sH in [2] $end +$var wire 1 zH in [3] $end +$var wire 1 MJ in [4] $end +$var wire 1 /J in [5] $end +$var wire 1 +L sram [0] $end +$var wire 1 ,L sram [1] $end +$var wire 1 -L sram [2] $end +$var wire 1 .L sram [3] $end +$var wire 1 YM sram_inv [0] $end +$var wire 1 ZM sram_inv [1] $end +$var wire 1 [M sram_inv [2] $end +$var wire 1 \M sram_inv [3] $end +$var wire 1 iI out [0] $end +$var wire 1 ,M p0 $end +$var wire 1 }] local_encoder2to3_0_data [0] $end +$var wire 1 ~] local_encoder2to3_0_data [1] $end +$var wire 1 !^ local_encoder2to3_0_data [2] $end +$var wire 1 "^ local_encoder2to3_0_data_inv [0] $end +$var wire 1 #^ local_encoder2to3_0_data_inv [1] $end +$var wire 1 $^ local_encoder2to3_0_data_inv [2] $end +$var wire 1 %^ local_encoder2to3_1_data [0] $end +$var wire 1 &^ local_encoder2to3_1_data [1] $end +$var wire 1 '^ local_encoder2to3_1_data [2] $end +$var wire 1 (^ local_encoder2to3_1_data_inv [0] $end +$var wire 1 )^ local_encoder2to3_1_data_inv [1] $end +$var wire 1 *^ local_encoder2to3_1_data_inv [2] $end +$var wire 1 +^ mux_2level_tapbuf_basis_input3_mem3_0_out [0] $end +$var wire 1 ,^ mux_2level_tapbuf_basis_input3_mem3_1_out [0] $end +$var wire 1 -^ mux_2level_tapbuf_basis_input3_mem3_2_out [0] $end +$var wire 1 .^ SYNOPSYS_UNCONNECTED_1 $end +$var wire 1 /^ BUF_net_152 $end + +$scope module local_encoder2to3_0_ $end +$var wire 1 +L addr [0] $end +$var wire 1 ,L addr [1] $end +$var wire 1 }] data [0] $end +$var wire 1 ~] data [1] $end +$var wire 1 !^ data [2] $end +$var wire 1 "^ data_inv [0] $end +$var wire 1 #^ data_inv [1] $end +$var wire 1 $^ data_inv [2] $end + +$scope module U8 $end +$var wire 1 "^ Y $end +$var wire 1 }] A $end +$var supply1 1 0^ VPWR $end +$var supply0 1 1^ VGND $end +$var supply1 1 2^ VPB $end +$var supply0 1 3^ VNB $end + +$scope module base $end +$var wire 1 "^ Y $end +$var wire 1 }] A $end +$var wire 1 4^ not0_out_Y $end +$upscope $end +$upscope $end + +$scope module U9 $end +$var wire 1 ~] Y $end +$var wire 1 #^ A $end +$var supply1 1 5^ VPWR $end +$var supply0 1 6^ VGND $end +$var supply1 1 7^ VPB $end +$var supply0 1 8^ VNB $end + +$scope module base $end +$var wire 1 ~] Y $end +$var wire 1 #^ A $end +$var wire 1 9^ not0_out_Y $end +$upscope $end +$upscope $end + +$scope module U10 $end +$var wire 1 #^ Y $end +$var wire 1 +L A $end +$var wire 1 $^ B $end +$var supply1 1 :^ VPWR $end +$var supply0 1 ;^ VGND $end +$var supply1 1 <^ VPB $end +$var supply0 1 =^ VNB $end + +$scope module base $end +$var wire 1 #^ Y $end +$var wire 1 +L A $end +$var wire 1 $^ B $end +$var wire 1 >^ nand0_out_Y $end +$upscope $end +$upscope $end + +$scope module U11 $end +$var wire 1 $^ Y $end +$var wire 1 !^ A $end +$var supply1 1 ?^ VPWR $end +$var supply0 1 @^ VGND $end +$var supply1 1 A^ VPB $end +$var supply0 1 B^ VNB $end + +$scope module base $end +$var wire 1 $^ Y $end +$var wire 1 !^ A $end +$var wire 1 C^ not0_out_Y $end +$upscope $end +$upscope $end + +$scope module U12 $end +$var wire 1 }] Y $end +$var wire 1 !^ A $end +$var wire 1 +L B $end +$var supply1 1 D^ VPWR $end +$var supply0 1 E^ VGND $end +$var supply1 1 F^ VPB $end +$var supply0 1 G^ VNB $end + +$scope module base $end +$var wire 1 }] Y $end +$var wire 1 !^ A $end +$var wire 1 +L B $end +$var wire 1 H^ nor0_out_Y $end +$upscope $end +$upscope $end + +$scope module FTB_33__32 $end +$var wire 1 !^ X $end +$var wire 1 ,L A $end +$var supply1 1 I^ VPWR $end +$var supply0 1 J^ VGND $end +$var supply1 1 K^ VPB $end +$var supply0 1 L^ VNB $end + +$scope module base $end +$var wire 1 !^ X $end +$var wire 1 ,L A $end +$var wire 1 M^ buf0_out_X $end +$upscope $end +$upscope $end +$upscope $end + +$scope module local_encoder2to3_1_ $end +$var wire 1 -L addr [0] $end +$var wire 1 .L addr [1] $end +$var wire 1 %^ data [0] $end +$var wire 1 &^ data [1] $end +$var wire 1 '^ data [2] $end +$var wire 1 (^ data_inv [0] $end +$var wire 1 )^ data_inv [1] $end +$var wire 1 *^ data_inv [2] $end + +$scope module U8 $end +$var wire 1 (^ Y $end +$var wire 1 %^ A $end +$var supply1 1 N^ VPWR $end +$var supply0 1 O^ VGND $end +$var supply1 1 P^ VPB $end +$var supply0 1 Q^ VNB $end + +$scope module base $end +$var wire 1 (^ Y $end +$var wire 1 %^ A $end +$var wire 1 R^ not0_out_Y $end +$upscope $end +$upscope $end + +$scope module U9 $end +$var wire 1 &^ Y $end +$var wire 1 )^ A $end +$var supply1 1 S^ VPWR $end +$var supply0 1 T^ VGND $end +$var supply1 1 U^ VPB $end +$var supply0 1 V^ VNB $end + +$scope module base $end +$var wire 1 &^ Y $end +$var wire 1 )^ A $end +$var wire 1 W^ not0_out_Y $end +$upscope $end +$upscope $end + +$scope module U10 $end +$var wire 1 )^ Y $end +$var wire 1 -L A $end +$var wire 1 *^ B $end +$var supply1 1 X^ VPWR $end +$var supply0 1 Y^ VGND $end +$var supply1 1 Z^ VPB $end +$var supply0 1 [^ VNB $end + +$scope module base $end +$var wire 1 )^ Y $end +$var wire 1 -L A $end +$var wire 1 *^ B $end +$var wire 1 \^ nand0_out_Y $end +$upscope $end +$upscope $end + +$scope module U11 $end +$var wire 1 *^ Y $end +$var wire 1 '^ A $end +$var supply1 1 ]^ VPWR $end +$var supply0 1 ^^ VGND $end +$var supply1 1 _^ VPB $end +$var supply0 1 `^ VNB $end + +$scope module base $end +$var wire 1 *^ Y $end +$var wire 1 '^ A $end +$var wire 1 a^ not0_out_Y $end +$upscope $end +$upscope $end + +$scope module U12 $end +$var wire 1 %^ Y $end +$var wire 1 '^ A $end +$var wire 1 -L B $end +$var supply1 1 b^ VPWR $end +$var supply0 1 c^ VGND $end +$var supply1 1 d^ VPB $end +$var supply0 1 e^ VNB $end + +$scope module base $end +$var wire 1 %^ Y $end +$var wire 1 '^ A $end +$var wire 1 -L B $end +$var wire 1 f^ nor0_out_Y $end +$upscope $end +$upscope $end + +$scope module FTB_34__33 $end +$var wire 1 '^ X $end +$var wire 1 .L A $end +$var supply1 1 g^ VPWR $end +$var supply0 1 h^ VGND $end +$var supply1 1 i^ VPB $end +$var supply0 1 j^ VNB $end + +$scope module base $end +$var wire 1 '^ X $end +$var wire 1 .L A $end +$var wire 1 k^ buf0_out_X $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mux_l1_in_0_ $end +$var wire 1 mH in [0] $end +$var wire 1 pH in [1] $end +$var wire 1 sH in [2] $end +$var wire 1 }] mem [0] $end +$var wire 1 ~] mem [1] $end +$var wire 1 !^ mem [2] $end +$var wire 1 "^ mem_inv [0] $end +$var wire 1 #^ mem_inv [1] $end +$var wire 1 $^ mem_inv [2] $end +$var wire 1 +^ out [0] $end + +$scope module scs8hd_muxinv3_1_0 $end +$var wire 1 +^ Z $end +$var wire 1 mH Q1 $end +$var wire 1 pH Q2 $end +$var wire 1 sH Q3 $end +$var wire 1 }] S0 $end +$var wire 1 "^ S0B $end +$var wire 1 ~] S1 $end +$var wire 1 #^ S1B $end +$var wire 1 !^ S2 $end +$var wire 1 $^ S2B $end +$var wire 1 l^ Q1__bar $end +$var wire 1 m^ Q2__bar $end +$var wire 1 n^ Q3__bar $end +$upscope $end +$upscope $end + +$scope module mux_l1_in_1_ $end +$var wire 1 zH in [0] $end +$var wire 1 MJ in [1] $end +$var wire 1 /J in [2] $end +$var wire 1 }] mem [0] $end +$var wire 1 ~] mem [1] $end +$var wire 1 !^ mem [2] $end +$var wire 1 "^ mem_inv [0] $end +$var wire 1 #^ mem_inv [1] $end +$var wire 1 $^ mem_inv [2] $end +$var wire 1 ,^ out [0] $end + +$scope module scs8hd_muxinv3_1_0 $end +$var wire 1 ,^ Z $end +$var wire 1 zH Q1 $end +$var wire 1 MJ Q2 $end +$var wire 1 /J Q3 $end +$var wire 1 }] S0 $end +$var wire 1 "^ S0B $end +$var wire 1 ~] S1 $end +$var wire 1 #^ S1B $end +$var wire 1 !^ S2 $end +$var wire 1 $^ S2B $end +$var wire 1 o^ Q1__bar $end +$var wire 1 p^ Q2__bar $end +$var wire 1 q^ Q3__bar $end +$upscope $end +$upscope $end + +$scope module mux_l2_in_0_ $end +$var wire 1 +^ in [0] $end +$var wire 1 ,^ in [1] $end +$var wire 1 .^ in [2] $end +$var wire 1 %^ mem [0] $end +$var wire 1 &^ mem [1] $end +$var wire 1 '^ mem [2] $end +$var wire 1 (^ mem_inv [0] $end +$var wire 1 )^ mem_inv [1] $end +$var wire 1 *^ mem_inv [2] $end +$var wire 1 -^ out [0] $end +$var wire 1 ,M p0 $end + +$scope module scs8hd_muxinv3_1_0 $end +$var wire 1 -^ Z $end +$var wire 1 +^ Q1 $end +$var wire 1 ,^ Q2 $end +$var wire 1 ,M Q3 $end +$var wire 1 %^ S0 $end +$var wire 1 (^ S0B $end +$var wire 1 &^ S1 $end +$var wire 1 )^ S1B $end +$var wire 1 '^ S2 $end +$var wire 1 *^ S2B $end +$var wire 1 r^ Q1__bar $end +$var wire 1 s^ Q2__bar $end +$var wire 1 t^ Q3__bar $end +$upscope $end +$upscope $end + +$scope module BINV_R_151 $end +$var wire 1 iI Y $end +$var wire 1 /^ A $end +$var supply1 1 u^ VPWR $end +$var supply0 1 v^ VGND $end +$var supply1 1 w^ VPB $end +$var supply0 1 x^ VNB $end + +$scope module base $end +$var wire 1 iI Y $end +$var wire 1 /^ A $end +$var wire 1 y^ not0_out_Y $end +$upscope $end +$upscope $end + +$scope module BINV_R_152 $end +$var wire 1 /^ Y $end +$var wire 1 -^ A $end +$var supply1 1 z^ VPWR $end +$var supply0 1 {^ VGND $end +$var supply1 1 |^ VPB $end +$var supply0 1 }^ VNB $end + +$scope module base $end +$var wire 1 /^ Y $end +$var wire 1 -^ A $end +$var wire 1 ~^ not0_out_Y $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mux_top_track_8 $end +$var wire 1 yI in [0] $end +$var wire 1 qH in [1] $end +$var wire 1 tH in [2] $end +$var wire 1 ~H in [3] $end +$var wire 1 OJ in [4] $end +$var wire 1 1J in [5] $end +$var wire 1 /L sram [0] $end +$var wire 1 0L sram [1] $end +$var wire 1 1L sram [2] $end +$var wire 1 2L sram [3] $end +$var wire 1 ]M sram_inv [0] $end +$var wire 1 ^M sram_inv [1] $end +$var wire 1 _M sram_inv [2] $end +$var wire 1 `M sram_inv [3] $end +$var wire 1 jI out [0] $end +$var wire 1 aM p0 $end +$var wire 1 !_ local_encoder2to3_0_data [0] $end +$var wire 1 "_ local_encoder2to3_0_data [1] $end +$var wire 1 #_ local_encoder2to3_0_data [2] $end +$var wire 1 $_ local_encoder2to3_0_data_inv [0] $end +$var wire 1 %_ local_encoder2to3_0_data_inv [1] $end +$var wire 1 &_ local_encoder2to3_0_data_inv [2] $end +$var wire 1 '_ local_encoder2to3_1_data [0] $end +$var wire 1 (_ local_encoder2to3_1_data [1] $end +$var wire 1 )_ local_encoder2to3_1_data [2] $end +$var wire 1 *_ local_encoder2to3_1_data_inv [0] $end +$var wire 1 +_ local_encoder2to3_1_data_inv [1] $end +$var wire 1 ,_ local_encoder2to3_1_data_inv [2] $end +$var wire 1 -_ mux_2level_tapbuf_basis_input3_mem3_0_out [0] $end +$var wire 1 ._ mux_2level_tapbuf_basis_input3_mem3_1_out [0] $end +$var wire 1 /_ mux_2level_tapbuf_basis_input3_mem3_2_out [0] $end +$var wire 1 0_ SYNOPSYS_UNCONNECTED_1 $end + +$scope module sky130_fd_sc_hd__buf_4_0_ $end +$var wire 1 jI X $end +$var wire 1 /_ A $end +$var supply1 1 1_ VPWR $end +$var supply0 1 2_ VGND $end +$var supply1 1 3_ VPB $end +$var supply0 1 4_ VNB $end + +$scope module base $end +$var wire 1 jI X $end +$var wire 1 /_ A $end +$var wire 1 5_ buf0_out_X $end +$upscope $end +$upscope $end + +$scope module local_encoder2to3_0_ $end +$var wire 1 /L addr [0] $end +$var wire 1 0L addr [1] $end +$var wire 1 !_ data [0] $end +$var wire 1 "_ data [1] $end +$var wire 1 #_ data [2] $end +$var wire 1 $_ data_inv [0] $end +$var wire 1 %_ data_inv [1] $end +$var wire 1 &_ data_inv [2] $end + +$scope module U8 $end +$var wire 1 $_ Y $end +$var wire 1 !_ A $end +$var supply1 1 6_ VPWR $end +$var supply0 1 7_ VGND $end +$var supply1 1 8_ VPB $end +$var supply0 1 9_ VNB $end + +$scope module base $end +$var wire 1 $_ Y $end +$var wire 1 !_ A $end +$var wire 1 :_ not0_out_Y $end +$upscope $end +$upscope $end + +$scope module U9 $end +$var wire 1 "_ Y $end +$var wire 1 %_ A $end +$var supply1 1 ;_ VPWR $end +$var supply0 1 <_ VGND $end +$var supply1 1 =_ VPB $end +$var supply0 1 >_ VNB $end + +$scope module base $end +$var wire 1 "_ Y $end +$var wire 1 %_ A $end +$var wire 1 ?_ not0_out_Y $end +$upscope $end +$upscope $end + +$scope module U10 $end +$var wire 1 %_ Y $end +$var wire 1 /L A $end +$var wire 1 &_ B $end +$var supply1 1 @_ VPWR $end +$var supply0 1 A_ VGND $end +$var supply1 1 B_ VPB $end +$var supply0 1 C_ VNB $end + +$scope module base $end +$var wire 1 %_ Y $end +$var wire 1 /L A $end +$var wire 1 &_ B $end +$var wire 1 D_ nand0_out_Y $end +$upscope $end +$upscope $end + +$scope module U11 $end +$var wire 1 &_ Y $end +$var wire 1 #_ A $end +$var supply1 1 E_ VPWR $end +$var supply0 1 F_ VGND $end +$var supply1 1 G_ VPB $end +$var supply0 1 H_ VNB $end + +$scope module base $end +$var wire 1 &_ Y $end +$var wire 1 #_ A $end +$var wire 1 I_ not0_out_Y $end +$upscope $end +$upscope $end + +$scope module U12 $end +$var wire 1 !_ Y $end +$var wire 1 #_ A $end +$var wire 1 /L B $end +$var supply1 1 J_ VPWR $end +$var supply0 1 K_ VGND $end +$var supply1 1 L_ VPB $end +$var supply0 1 M_ VNB $end + +$scope module base $end +$var wire 1 !_ Y $end +$var wire 1 #_ A $end +$var wire 1 /L B $end +$var wire 1 N_ nor0_out_Y $end +$upscope $end +$upscope $end + +$scope module FTB_35__34 $end +$var wire 1 #_ X $end +$var wire 1 0L A $end +$var supply1 1 O_ VPWR $end +$var supply0 1 P_ VGND $end +$var supply1 1 Q_ VPB $end +$var supply0 1 R_ VNB $end + +$scope module base $end +$var wire 1 #_ X $end +$var wire 1 0L A $end +$var wire 1 S_ buf0_out_X $end +$upscope $end +$upscope $end +$upscope $end + +$scope module local_encoder2to3_1_ $end +$var wire 1 1L addr [0] $end +$var wire 1 2L addr [1] $end +$var wire 1 '_ data [0] $end +$var wire 1 (_ data [1] $end +$var wire 1 )_ data [2] $end +$var wire 1 *_ data_inv [0] $end +$var wire 1 +_ data_inv [1] $end +$var wire 1 ,_ data_inv [2] $end + +$scope module U8 $end +$var wire 1 *_ Y $end +$var wire 1 '_ A $end +$var supply1 1 T_ VPWR $end +$var supply0 1 U_ VGND $end +$var supply1 1 V_ VPB $end +$var supply0 1 W_ VNB $end + +$scope module base $end +$var wire 1 *_ Y $end +$var wire 1 '_ A $end +$var wire 1 X_ not0_out_Y $end +$upscope $end +$upscope $end + +$scope module U9 $end +$var wire 1 (_ Y $end +$var wire 1 +_ A $end +$var supply1 1 Y_ VPWR $end +$var supply0 1 Z_ VGND $end +$var supply1 1 [_ VPB $end +$var supply0 1 \_ VNB $end + +$scope module base $end +$var wire 1 (_ Y $end +$var wire 1 +_ A $end +$var wire 1 ]_ not0_out_Y $end +$upscope $end +$upscope $end + +$scope module U10 $end +$var wire 1 +_ Y $end +$var wire 1 1L A $end +$var wire 1 ,_ B $end +$var supply1 1 ^_ VPWR $end +$var supply0 1 __ VGND $end +$var supply1 1 `_ VPB $end +$var supply0 1 a_ VNB $end + +$scope module base $end +$var wire 1 +_ Y $end +$var wire 1 1L A $end +$var wire 1 ,_ B $end +$var wire 1 b_ nand0_out_Y $end +$upscope $end +$upscope $end + +$scope module U11 $end +$var wire 1 ,_ Y $end +$var wire 1 )_ A $end +$var supply1 1 c_ VPWR $end +$var supply0 1 d_ VGND $end +$var supply1 1 e_ VPB $end +$var supply0 1 f_ VNB $end + +$scope module base $end +$var wire 1 ,_ Y $end +$var wire 1 )_ A $end +$var wire 1 g_ not0_out_Y $end +$upscope $end +$upscope $end + +$scope module U12 $end +$var wire 1 '_ Y $end +$var wire 1 )_ A $end +$var wire 1 1L B $end +$var supply1 1 h_ VPWR $end +$var supply0 1 i_ VGND $end +$var supply1 1 j_ VPB $end +$var supply0 1 k_ VNB $end + +$scope module base $end +$var wire 1 '_ Y $end +$var wire 1 )_ A $end +$var wire 1 1L B $end +$var wire 1 l_ nor0_out_Y $end +$upscope $end +$upscope $end + +$scope module FTB_36__35 $end +$var wire 1 )_ X $end +$var wire 1 2L A $end +$var supply1 1 m_ VPWR $end +$var supply0 1 n_ VGND $end +$var supply1 1 o_ VPB $end +$var supply0 1 p_ VNB $end + +$scope module base $end +$var wire 1 )_ X $end +$var wire 1 2L A $end +$var wire 1 q_ buf0_out_X $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mux_l1_in_0_ $end +$var wire 1 yI in [0] $end +$var wire 1 qH in [1] $end +$var wire 1 tH in [2] $end +$var wire 1 !_ mem [0] $end +$var wire 1 "_ mem [1] $end +$var wire 1 #_ mem [2] $end +$var wire 1 $_ mem_inv [0] $end +$var wire 1 %_ mem_inv [1] $end +$var wire 1 &_ mem_inv [2] $end +$var wire 1 -_ out [0] $end + +$scope module scs8hd_muxinv3_1_0 $end +$var wire 1 -_ Z $end +$var wire 1 yI Q1 $end +$var wire 1 qH Q2 $end +$var wire 1 tH Q3 $end +$var wire 1 !_ S0 $end +$var wire 1 $_ S0B $end +$var wire 1 "_ S1 $end +$var wire 1 %_ S1B $end +$var wire 1 #_ S2 $end +$var wire 1 &_ S2B $end +$var wire 1 r_ Q1__bar $end +$var wire 1 s_ Q2__bar $end +$var wire 1 t_ Q3__bar $end +$upscope $end +$upscope $end + +$scope module mux_l1_in_1_ $end +$var wire 1 ~H in [0] $end +$var wire 1 OJ in [1] $end +$var wire 1 1J in [2] $end +$var wire 1 !_ mem [0] $end +$var wire 1 "_ mem [1] $end +$var wire 1 #_ mem [2] $end +$var wire 1 $_ mem_inv [0] $end +$var wire 1 %_ mem_inv [1] $end +$var wire 1 &_ mem_inv [2] $end +$var wire 1 ._ out [0] $end + +$scope module scs8hd_muxinv3_1_0 $end +$var wire 1 ._ Z $end +$var wire 1 ~H Q1 $end +$var wire 1 OJ Q2 $end +$var wire 1 1J Q3 $end +$var wire 1 !_ S0 $end +$var wire 1 $_ S0B $end +$var wire 1 "_ S1 $end +$var wire 1 %_ S1B $end +$var wire 1 #_ S2 $end +$var wire 1 &_ S2B $end +$var wire 1 u_ Q1__bar $end +$var wire 1 v_ Q2__bar $end +$var wire 1 w_ Q3__bar $end +$upscope $end +$upscope $end + +$scope module mux_l2_in_0_ $end +$var wire 1 -_ in [0] $end +$var wire 1 ._ in [1] $end +$var wire 1 0_ in [2] $end +$var wire 1 '_ mem [0] $end +$var wire 1 (_ mem [1] $end +$var wire 1 )_ mem [2] $end +$var wire 1 *_ mem_inv [0] $end +$var wire 1 +_ mem_inv [1] $end +$var wire 1 ,_ mem_inv [2] $end +$var wire 1 /_ out [0] $end +$var wire 1 aM p0 $end + +$scope module scs8hd_muxinv3_1_0 $end +$var wire 1 /_ Z $end +$var wire 1 -_ Q1 $end +$var wire 1 ._ Q2 $end +$var wire 1 aM Q3 $end +$var wire 1 '_ S0 $end +$var wire 1 *_ S0B $end +$var wire 1 (_ S1 $end +$var wire 1 +_ S1B $end +$var wire 1 )_ S2 $end +$var wire 1 ,_ S2B $end +$var wire 1 x_ Q1__bar $end +$var wire 1 y_ Q2__bar $end +$var wire 1 z_ Q3__bar $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mem_top_track_2 $end +$var wire 1 NH pReset [0] $end +$var wire 1 qJ prog_clk [0] $end +$var wire 1 ^L ccff_head [0] $end +$var wire 1 3L ccff_tail [0] $end +$var wire 1 'L mem_out [0] $end +$var wire 1 (L mem_out [1] $end +$var wire 1 )L mem_out [2] $end +$var wire 1 *L mem_out [3] $end + +$scope module sky130_fd_sc_hd__dfrtp_1_0_ $end +$var wire 1 'L Q $end +$var wire 1 qJ CLK $end +$var wire 1 ^L D $end +$var wire 1 NH RESET_B $end +$var supply1 1 {_ VPWR $end +$var supply0 1 |_ VGND $end +$var supply1 1 }_ VPB $end +$var supply0 1 ~_ VNB $end + +$scope module base $end +$var wire 1 'L Q $end +$var wire 1 qJ CLK $end +$var wire 1 ^L D $end +$var wire 1 NH RESET_B $end +$var wire 1 !` buf_Q $end +$var wire 1 "` RESET $end +$upscope $end +$upscope $end + +$scope module sky130_fd_sc_hd__dfrtp_1_1_ $end +$var wire 1 (L Q $end +$var wire 1 qJ CLK $end +$var wire 1 'L D $end +$var wire 1 NH RESET_B $end +$var supply1 1 #` VPWR $end +$var supply0 1 $` VGND $end +$var supply1 1 %` VPB $end +$var supply0 1 &` VNB $end + +$scope module base $end +$var wire 1 (L Q $end +$var wire 1 qJ CLK $end +$var wire 1 'L D $end +$var wire 1 NH RESET_B $end +$var wire 1 '` buf_Q $end +$var wire 1 (` RESET $end +$upscope $end +$upscope $end + +$scope module sky130_fd_sc_hd__dfrtp_1_2_ $end +$var wire 1 )L Q $end +$var wire 1 qJ CLK $end +$var wire 1 (L D $end +$var wire 1 NH RESET_B $end +$var supply1 1 )` VPWR $end +$var supply0 1 *` VGND $end +$var supply1 1 +` VPB $end +$var supply0 1 ,` VNB $end + +$scope module base $end +$var wire 1 )L Q $end +$var wire 1 qJ CLK $end +$var wire 1 (L D $end +$var wire 1 NH RESET_B $end +$var wire 1 -` buf_Q $end +$var wire 1 .` RESET $end +$upscope $end +$upscope $end + +$scope module sky130_fd_sc_hd__dfrtp_1_3_ $end +$var wire 1 *L Q $end +$var wire 1 qJ CLK $end +$var wire 1 )L D $end +$var wire 1 NH RESET_B $end +$var supply1 1 /` VPWR $end +$var supply0 1 0` VGND $end +$var supply1 1 1` VPB $end +$var supply0 1 2` VNB $end + +$scope module base $end +$var wire 1 *L Q $end +$var wire 1 qJ CLK $end +$var wire 1 )L D $end +$var wire 1 NH RESET_B $end +$var wire 1 3` buf_Q $end +$var wire 1 4` RESET $end +$upscope $end +$upscope $end + +$scope module FTB_37__36 $end +$var wire 1 3L X $end +$var wire 1 *L A $end +$var supply1 1 5` VPWR $end +$var supply0 1 6` VGND $end +$var supply1 1 7` VPB $end +$var supply0 1 8` VNB $end + +$scope module base $end +$var wire 1 3L X $end +$var wire 1 *L A $end +$var wire 1 9` buf0_out_X $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mem_top_track_6 $end +$var wire 1 NH pReset [0] $end +$var wire 1 qJ prog_clk [0] $end +$var wire 1 "L ccff_head [0] $end +$var wire 1 4L ccff_tail [0] $end +$var wire 1 +L mem_out [0] $end +$var wire 1 ,L mem_out [1] $end +$var wire 1 -L mem_out [2] $end +$var wire 1 .L mem_out [3] $end + +$scope module sky130_fd_sc_hd__dfrtp_1_0_ $end +$var wire 1 +L Q $end +$var wire 1 qJ CLK $end +$var wire 1 "L D $end +$var wire 1 NH RESET_B $end +$var supply1 1 :` VPWR $end +$var supply0 1 ;` VGND $end +$var supply1 1 <` VPB $end +$var supply0 1 =` VNB $end + +$scope module base $end +$var wire 1 +L Q $end +$var wire 1 qJ CLK $end +$var wire 1 "L D $end +$var wire 1 NH RESET_B $end +$var wire 1 >` buf_Q $end +$var wire 1 ?` RESET $end +$upscope $end +$upscope $end + +$scope module sky130_fd_sc_hd__dfrtp_1_1_ $end +$var wire 1 ,L Q $end +$var wire 1 qJ CLK $end +$var wire 1 +L D $end +$var wire 1 NH RESET_B $end +$var supply1 1 @` VPWR $end +$var supply0 1 A` VGND $end +$var supply1 1 B` VPB $end +$var supply0 1 C` VNB $end + +$scope module base $end +$var wire 1 ,L Q $end +$var wire 1 qJ CLK $end +$var wire 1 +L D $end +$var wire 1 NH RESET_B $end +$var wire 1 D` buf_Q $end +$var wire 1 E` RESET $end +$upscope $end +$upscope $end + +$scope module sky130_fd_sc_hd__dfrtp_1_2_ $end +$var wire 1 -L Q $end +$var wire 1 qJ CLK $end +$var wire 1 ,L D $end +$var wire 1 NH RESET_B $end +$var supply1 1 F` VPWR $end +$var supply0 1 G` VGND $end +$var supply1 1 H` VPB $end +$var supply0 1 I` VNB $end + +$scope module base $end +$var wire 1 -L Q $end +$var wire 1 qJ CLK $end +$var wire 1 ,L D $end +$var wire 1 NH RESET_B $end +$var wire 1 J` buf_Q $end +$var wire 1 K` RESET $end +$upscope $end +$upscope $end + +$scope module sky130_fd_sc_hd__dfrtp_1_3_ $end +$var wire 1 .L Q $end +$var wire 1 qJ CLK $end +$var wire 1 -L D $end +$var wire 1 NH RESET_B $end +$var supply1 1 L` VPWR $end +$var supply0 1 M` VGND $end +$var supply1 1 N` VPB $end +$var supply0 1 O` VNB $end + +$scope module base $end +$var wire 1 .L Q $end +$var wire 1 qJ CLK $end +$var wire 1 -L D $end +$var wire 1 NH RESET_B $end +$var wire 1 P` buf_Q $end +$var wire 1 Q` RESET $end +$upscope $end +$upscope $end + +$scope module FTB_38__37 $end +$var wire 1 4L X $end +$var wire 1 .L A $end +$var supply1 1 R` VPWR $end +$var supply0 1 S` VGND $end +$var supply1 1 T` VPB $end +$var supply0 1 U` VNB $end + +$scope module base $end +$var wire 1 4L X $end +$var wire 1 .L A $end +$var wire 1 V` buf0_out_X $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mem_top_track_8 $end +$var wire 1 NH pReset [0] $end +$var wire 1 qJ prog_clk [0] $end +$var wire 1 4L ccff_head [0] $end +$var wire 1 5L ccff_tail [0] $end +$var wire 1 /L mem_out [0] $end +$var wire 1 0L mem_out [1] $end +$var wire 1 1L mem_out [2] $end +$var wire 1 2L mem_out [3] $end + +$scope module sky130_fd_sc_hd__dfrtp_1_0_ $end +$var wire 1 /L Q $end +$var wire 1 qJ CLK $end +$var wire 1 4L D $end +$var wire 1 NH RESET_B $end +$var supply1 1 W` VPWR $end +$var supply0 1 X` VGND $end +$var supply1 1 Y` VPB $end +$var supply0 1 Z` VNB $end + +$scope module base $end +$var wire 1 /L Q $end +$var wire 1 qJ CLK $end +$var wire 1 4L D $end +$var wire 1 NH RESET_B $end +$var wire 1 [` buf_Q $end +$var wire 1 \` RESET $end +$upscope $end +$upscope $end + +$scope module sky130_fd_sc_hd__dfrtp_1_1_ $end +$var wire 1 0L Q $end +$var wire 1 qJ CLK $end +$var wire 1 /L D $end +$var wire 1 NH RESET_B $end +$var supply1 1 ]` VPWR $end +$var supply0 1 ^` VGND $end +$var supply1 1 _` VPB $end +$var supply0 1 `` VNB $end + +$scope module base $end +$var wire 1 0L Q $end +$var wire 1 qJ CLK $end +$var wire 1 /L D $end +$var wire 1 NH RESET_B $end +$var wire 1 a` buf_Q $end +$var wire 1 b` RESET $end +$upscope $end +$upscope $end + +$scope module sky130_fd_sc_hd__dfrtp_1_2_ $end +$var wire 1 1L Q $end +$var wire 1 qJ CLK $end +$var wire 1 0L D $end +$var wire 1 NH RESET_B $end +$var supply1 1 c` VPWR $end +$var supply0 1 d` VGND $end +$var supply1 1 e` VPB $end +$var supply0 1 f` VNB $end + +$scope module base $end +$var wire 1 1L Q $end +$var wire 1 qJ CLK $end +$var wire 1 0L D $end +$var wire 1 NH RESET_B $end +$var wire 1 g` buf_Q $end +$var wire 1 h` RESET $end +$upscope $end +$upscope $end + +$scope module sky130_fd_sc_hd__dfrtp_1_3_ $end +$var wire 1 2L Q $end +$var wire 1 qJ CLK $end +$var wire 1 1L D $end +$var wire 1 NH RESET_B $end +$var supply1 1 i` VPWR $end +$var supply0 1 j` VGND $end +$var supply1 1 k` VPB $end +$var supply0 1 l` VNB $end + +$scope module base $end +$var wire 1 2L Q $end +$var wire 1 qJ CLK $end +$var wire 1 1L D $end +$var wire 1 NH RESET_B $end +$var wire 1 m` buf_Q $end +$var wire 1 n` RESET $end +$upscope $end +$upscope $end + +$scope module FTB_39__38 $end +$var wire 1 5L X $end +$var wire 1 2L A $end +$var supply1 1 o` VPWR $end +$var supply0 1 p` VGND $end +$var supply1 1 q` VPB $end +$var supply0 1 r` VNB $end + +$scope module base $end +$var wire 1 5L X $end +$var wire 1 2L A $end +$var wire 1 s` buf0_out_X $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mux_top_track_4 $end +$var wire 1 oH in [0] $end +$var wire 1 rH in [1] $end +$var wire 1 yH in [2] $end +$var wire 1 LJ in [3] $end +$var wire 1 .J in [4] $end +$var wire 1 hK sram [0] $end +$var wire 1 iK sram [1] $end +$var wire 1 jK sram [2] $end +$var wire 1 kK sram [3] $end +$var wire 1 bM sram_inv [0] $end +$var wire 1 cM sram_inv [1] $end +$var wire 1 dM sram_inv [2] $end +$var wire 1 eM sram_inv [3] $end +$var wire 1 hI out [0] $end +$var wire 1 GM p0 $end +$var wire 1 t` local_encoder2to3_0_data [0] $end +$var wire 1 u` local_encoder2to3_0_data [1] $end +$var wire 1 v` local_encoder2to3_0_data [2] $end +$var wire 1 w` local_encoder2to3_0_data_inv [0] $end +$var wire 1 x` local_encoder2to3_0_data_inv [1] $end +$var wire 1 y` local_encoder2to3_0_data_inv [2] $end +$var wire 1 z` local_encoder2to3_1_data [0] $end +$var wire 1 {` local_encoder2to3_1_data [1] $end +$var wire 1 |` local_encoder2to3_1_data [2] $end +$var wire 1 }` local_encoder2to3_1_data_inv [0] $end +$var wire 1 ~` local_encoder2to3_1_data_inv [1] $end +$var wire 1 !a local_encoder2to3_1_data_inv [2] $end +$var wire 1 "a mux_2level_tapbuf_basis_input2_mem2_0_out [0] $end +$var wire 1 #a mux_2level_tapbuf_basis_input3_mem3_0_out [0] $end +$var wire 1 $a mux_2level_tapbuf_basis_input3_mem3_1_out [0] $end +$var wire 1 %a SYNOPSYS_UNCONNECTED_1 $end +$var wire 1 &a BUF_net_154 $end + +$scope module local_encoder2to3_0_ $end +$var wire 1 hK addr [0] $end +$var wire 1 iK addr [1] $end +$var wire 1 t` data [0] $end +$var wire 1 u` data [1] $end +$var wire 1 v` data [2] $end +$var wire 1 w` data_inv [0] $end +$var wire 1 x` data_inv [1] $end +$var wire 1 y` data_inv [2] $end + +$scope module U8 $end +$var wire 1 w` Y $end +$var wire 1 t` A $end +$var supply1 1 'a VPWR $end +$var supply0 1 (a VGND $end +$var supply1 1 )a VPB $end +$var supply0 1 *a VNB $end + +$scope module base $end +$var wire 1 w` Y $end +$var wire 1 t` A $end +$var wire 1 +a not0_out_Y $end +$upscope $end +$upscope $end + +$scope module U9 $end +$var wire 1 u` Y $end +$var wire 1 x` A $end +$var supply1 1 ,a VPWR $end +$var supply0 1 -a VGND $end +$var supply1 1 .a VPB $end +$var supply0 1 /a VNB $end + +$scope module base $end +$var wire 1 u` Y $end +$var wire 1 x` A $end +$var wire 1 0a not0_out_Y $end +$upscope $end +$upscope $end + +$scope module U10 $end +$var wire 1 x` Y $end +$var wire 1 hK A $end +$var wire 1 y` B $end +$var supply1 1 1a VPWR $end +$var supply0 1 2a VGND $end +$var supply1 1 3a VPB $end +$var supply0 1 4a VNB $end + +$scope module base $end +$var wire 1 x` Y $end +$var wire 1 hK A $end +$var wire 1 y` B $end +$var wire 1 5a nand0_out_Y $end +$upscope $end +$upscope $end + +$scope module U11 $end +$var wire 1 y` Y $end +$var wire 1 v` A $end +$var supply1 1 6a VPWR $end +$var supply0 1 7a VGND $end +$var supply1 1 8a VPB $end +$var supply0 1 9a VNB $end + +$scope module base $end +$var wire 1 y` Y $end +$var wire 1 v` A $end +$var wire 1 :a not0_out_Y $end +$upscope $end +$upscope $end + +$scope module U12 $end +$var wire 1 t` Y $end +$var wire 1 v` A $end +$var wire 1 hK B $end +$var supply1 1 ;a VPWR $end +$var supply0 1 a VNB $end + +$scope module base $end +$var wire 1 t` Y $end +$var wire 1 v` A $end +$var wire 1 hK B $end +$var wire 1 ?a nor0_out_Y $end +$upscope $end +$upscope $end + +$scope module FTB_40__39 $end +$var wire 1 v` X $end +$var wire 1 iK A $end +$var supply1 1 @a VPWR $end +$var supply0 1 Aa VGND $end +$var supply1 1 Ba VPB $end +$var supply0 1 Ca VNB $end + +$scope module base $end +$var wire 1 v` X $end +$var wire 1 iK A $end +$var wire 1 Da buf0_out_X $end +$upscope $end +$upscope $end +$upscope $end + +$scope module local_encoder2to3_1_ $end +$var wire 1 jK addr [0] $end +$var wire 1 kK addr [1] $end +$var wire 1 z` data [0] $end +$var wire 1 {` data [1] $end +$var wire 1 |` data [2] $end +$var wire 1 }` data_inv [0] $end +$var wire 1 ~` data_inv [1] $end +$var wire 1 !a data_inv [2] $end + +$scope module U8 $end +$var wire 1 }` Y $end +$var wire 1 z` A $end +$var supply1 1 Ea VPWR $end +$var supply0 1 Fa VGND $end +$var supply1 1 Ga VPB $end +$var supply0 1 Ha VNB $end + +$scope module base $end +$var wire 1 }` Y $end +$var wire 1 z` A $end +$var wire 1 Ia not0_out_Y $end +$upscope $end +$upscope $end + +$scope module U9 $end +$var wire 1 {` Y $end +$var wire 1 ~` A $end +$var supply1 1 Ja VPWR $end +$var supply0 1 Ka VGND $end +$var supply1 1 La VPB $end +$var supply0 1 Ma VNB $end + +$scope module base $end +$var wire 1 {` Y $end +$var wire 1 ~` A $end +$var wire 1 Na not0_out_Y $end +$upscope $end +$upscope $end + +$scope module U10 $end +$var wire 1 ~` Y $end +$var wire 1 jK A $end +$var wire 1 !a B $end +$var supply1 1 Oa VPWR $end +$var supply0 1 Pa VGND $end +$var supply1 1 Qa VPB $end +$var supply0 1 Ra VNB $end + +$scope module base $end +$var wire 1 ~` Y $end +$var wire 1 jK A $end +$var wire 1 !a B $end +$var wire 1 Sa nand0_out_Y $end +$upscope $end +$upscope $end + +$scope module U11 $end +$var wire 1 !a Y $end +$var wire 1 |` A $end +$var supply1 1 Ta VPWR $end +$var supply0 1 Ua VGND $end +$var supply1 1 Va VPB $end +$var supply0 1 Wa VNB $end + +$scope module base $end +$var wire 1 !a Y $end +$var wire 1 |` A $end +$var wire 1 Xa not0_out_Y $end +$upscope $end +$upscope $end + +$scope module U12 $end +$var wire 1 z` Y $end +$var wire 1 |` A $end +$var wire 1 jK B $end +$var supply1 1 Ya VPWR $end +$var supply0 1 Za VGND $end +$var supply1 1 [a VPB $end +$var supply0 1 \a VNB $end + +$scope module base $end +$var wire 1 z` Y $end +$var wire 1 |` A $end +$var wire 1 jK B $end +$var wire 1 ]a nor0_out_Y $end +$upscope $end +$upscope $end + +$scope module FTB_41__40 $end +$var wire 1 |` X $end +$var wire 1 kK A $end +$var supply1 1 ^a VPWR $end +$var supply0 1 _a VGND $end +$var supply1 1 `a VPB $end +$var supply0 1 aa VNB $end + +$scope module base $end +$var wire 1 |` X $end +$var wire 1 kK A $end +$var wire 1 ba buf0_out_X $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mux_l1_in_0_ $end +$var wire 1 oH in [0] $end +$var wire 1 rH in [1] $end +$var wire 1 yH in [2] $end +$var wire 1 t` mem [0] $end +$var wire 1 u` mem [1] $end +$var wire 1 v` mem [2] $end +$var wire 1 w` mem_inv [0] $end +$var wire 1 x` mem_inv [1] $end +$var wire 1 y` mem_inv [2] $end +$var wire 1 #a out [0] $end + +$scope module scs8hd_muxinv3_1_0 $end +$var wire 1 #a Z $end +$var wire 1 oH Q1 $end +$var wire 1 rH Q2 $end +$var wire 1 yH Q3 $end +$var wire 1 t` S0 $end +$var wire 1 w` S0B $end +$var wire 1 u` S1 $end +$var wire 1 x` S1B $end +$var wire 1 v` S2 $end +$var wire 1 y` S2B $end +$var wire 1 ca Q1__bar $end +$var wire 1 da Q2__bar $end +$var wire 1 ea Q3__bar $end +$upscope $end +$upscope $end + +$scope module mux_l2_in_0_ $end +$var wire 1 #a in [0] $end +$var wire 1 "a in [1] $end +$var wire 1 %a in [2] $end +$var wire 1 z` mem [0] $end +$var wire 1 {` mem [1] $end +$var wire 1 |` mem [2] $end +$var wire 1 }` mem_inv [0] $end +$var wire 1 ~` mem_inv [1] $end +$var wire 1 !a mem_inv [2] $end +$var wire 1 $a out [0] $end +$var wire 1 GM p0 $end + +$scope module scs8hd_muxinv3_1_0 $end +$var wire 1 $a Z $end +$var wire 1 #a Q1 $end +$var wire 1 "a Q2 $end +$var wire 1 GM Q3 $end +$var wire 1 z` S0 $end +$var wire 1 }` S0B $end +$var wire 1 {` S1 $end +$var wire 1 ~` S1B $end +$var wire 1 |` S2 $end +$var wire 1 !a S2B $end +$var wire 1 fa Q1__bar $end +$var wire 1 ga Q2__bar $end +$var wire 1 ha Q3__bar $end +$upscope $end +$upscope $end + +$scope module mux_l1_in_1_ $end +$var wire 1 LJ in [0] $end +$var wire 1 .J in [1] $end +$var wire 1 t` mem [0] $end +$var wire 1 u` mem [1] $end +$var wire 1 w` mem_inv [0] $end +$var wire 1 x` mem_inv [1] $end +$var wire 1 "a out [0] $end + +$scope module scs8hd_muxinv2_1_0 $end +$var wire 1 "a Z $end +$var wire 1 LJ Q1 $end +$var wire 1 .J Q2 $end +$var wire 1 t` S0 $end +$var wire 1 w` S0B $end +$var wire 1 u` S1 $end +$var wire 1 x` S1B $end +$var wire 1 ia Q1__bar $end +$var wire 1 ja Q2__bar $end +$upscope $end +$upscope $end + +$scope module BINV_R_153 $end +$var wire 1 hI Y $end +$var wire 1 &a A $end +$var supply1 1 ka VPWR $end +$var supply0 1 la VGND $end +$var supply1 1 ma VPB $end +$var supply0 1 na VNB $end + +$scope module base $end +$var wire 1 hI Y $end +$var wire 1 &a A $end +$var wire 1 oa not0_out_Y $end +$upscope $end +$upscope $end + +$scope module BINV_R_154 $end +$var wire 1 &a Y $end +$var wire 1 $a A $end +$var supply1 1 pa VPWR $end +$var supply0 1 qa VGND $end +$var supply1 1 ra VPB $end +$var supply0 1 sa VNB $end + +$scope module base $end +$var wire 1 &a Y $end +$var wire 1 $a A $end +$var wire 1 ta not0_out_Y $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mux_top_track_10 $end +$var wire 1 oH in [0] $end +$var wire 1 rH in [1] $end +$var wire 1 PJ in [2] $end +$var wire 1 $I in [3] $end +$var wire 1 2J in [4] $end +$var wire 1 lK sram [0] $end +$var wire 1 mK sram [1] $end +$var wire 1 nK sram [2] $end +$var wire 1 oK sram [3] $end +$var wire 1 fM sram_inv [0] $end +$var wire 1 gM sram_inv [1] $end +$var wire 1 hM sram_inv [2] $end +$var wire 1 iM sram_inv [3] $end +$var wire 1 kI out [0] $end +$var wire 1 GM p0 $end +$var wire 1 ua local_encoder2to3_0_data [0] $end +$var wire 1 va local_encoder2to3_0_data [1] $end +$var wire 1 wa local_encoder2to3_0_data [2] $end +$var wire 1 xa local_encoder2to3_0_data_inv [0] $end +$var wire 1 ya local_encoder2to3_0_data_inv [1] $end +$var wire 1 za local_encoder2to3_0_data_inv [2] $end +$var wire 1 {a local_encoder2to3_1_data [0] $end +$var wire 1 |a local_encoder2to3_1_data [1] $end +$var wire 1 }a local_encoder2to3_1_data [2] $end +$var wire 1 ~a local_encoder2to3_1_data_inv [0] $end +$var wire 1 !b local_encoder2to3_1_data_inv [1] $end +$var wire 1 "b local_encoder2to3_1_data_inv [2] $end +$var wire 1 #b mux_2level_tapbuf_basis_input2_mem2_0_out [0] $end +$var wire 1 $b mux_2level_tapbuf_basis_input3_mem3_0_out [0] $end +$var wire 1 %b mux_2level_tapbuf_basis_input3_mem3_1_out [0] $end +$var wire 1 &b SYNOPSYS_UNCONNECTED_1 $end +$var wire 1 'b BUF_net_156 $end + +$scope module local_encoder2to3_0_ $end +$var wire 1 lK addr [0] $end +$var wire 1 mK addr [1] $end +$var wire 1 ua data [0] $end +$var wire 1 va data [1] $end +$var wire 1 wa data [2] $end +$var wire 1 xa data_inv [0] $end +$var wire 1 ya data_inv [1] $end +$var wire 1 za data_inv [2] $end + +$scope module U8 $end +$var wire 1 xa Y $end +$var wire 1 ua A $end +$var supply1 1 (b VPWR $end +$var supply0 1 )b VGND $end +$var supply1 1 *b VPB $end +$var supply0 1 +b VNB $end + +$scope module base $end +$var wire 1 xa Y $end +$var wire 1 ua A $end +$var wire 1 ,b not0_out_Y $end +$upscope $end +$upscope $end + +$scope module U9 $end +$var wire 1 va Y $end +$var wire 1 ya A $end +$var supply1 1 -b VPWR $end +$var supply0 1 .b VGND $end +$var supply1 1 /b VPB $end +$var supply0 1 0b VNB $end + +$scope module base $end +$var wire 1 va Y $end +$var wire 1 ya A $end +$var wire 1 1b not0_out_Y $end +$upscope $end +$upscope $end + +$scope module U10 $end +$var wire 1 ya Y $end +$var wire 1 lK A $end +$var wire 1 za B $end +$var supply1 1 2b VPWR $end +$var supply0 1 3b VGND $end +$var supply1 1 4b VPB $end +$var supply0 1 5b VNB $end + +$scope module base $end +$var wire 1 ya Y $end +$var wire 1 lK A $end +$var wire 1 za B $end +$var wire 1 6b nand0_out_Y $end +$upscope $end +$upscope $end + +$scope module U11 $end +$var wire 1 za Y $end +$var wire 1 wa A $end +$var supply1 1 7b VPWR $end +$var supply0 1 8b VGND $end +$var supply1 1 9b VPB $end +$var supply0 1 :b VNB $end + +$scope module base $end +$var wire 1 za Y $end +$var wire 1 wa A $end +$var wire 1 ;b not0_out_Y $end +$upscope $end +$upscope $end + +$scope module U12 $end +$var wire 1 ua Y $end +$var wire 1 wa A $end +$var wire 1 lK B $end +$var supply1 1 b VPB $end +$var supply0 1 ?b VNB $end + +$scope module base $end +$var wire 1 ua Y $end +$var wire 1 wa A $end +$var wire 1 lK B $end +$var wire 1 @b nor0_out_Y $end +$upscope $end +$upscope $end + +$scope module FTB_42__41 $end +$var wire 1 wa X $end +$var wire 1 mK A $end +$var supply1 1 Ab VPWR $end +$var supply0 1 Bb VGND $end +$var supply1 1 Cb VPB $end +$var supply0 1 Db VNB $end + +$scope module base $end +$var wire 1 wa X $end +$var wire 1 mK A $end +$var wire 1 Eb buf0_out_X $end +$upscope $end +$upscope $end +$upscope $end + +$scope module local_encoder2to3_1_ $end +$var wire 1 nK addr [0] $end +$var wire 1 oK addr [1] $end +$var wire 1 {a data [0] $end +$var wire 1 |a data [1] $end +$var wire 1 }a data [2] $end +$var wire 1 ~a data_inv [0] $end +$var wire 1 !b data_inv [1] $end +$var wire 1 "b data_inv [2] $end + +$scope module U8 $end +$var wire 1 ~a Y $end +$var wire 1 {a A $end +$var supply1 1 Fb VPWR $end +$var supply0 1 Gb VGND $end +$var supply1 1 Hb VPB $end +$var supply0 1 Ib VNB $end + +$scope module base $end +$var wire 1 ~a Y $end +$var wire 1 {a A $end +$var wire 1 Jb not0_out_Y $end +$upscope $end +$upscope $end + +$scope module U9 $end +$var wire 1 |a Y $end +$var wire 1 !b A $end +$var supply1 1 Kb VPWR $end +$var supply0 1 Lb VGND $end +$var supply1 1 Mb VPB $end +$var supply0 1 Nb VNB $end + +$scope module base $end +$var wire 1 |a Y $end +$var wire 1 !b A $end +$var wire 1 Ob not0_out_Y $end +$upscope $end +$upscope $end + +$scope module U10 $end +$var wire 1 !b Y $end +$var wire 1 nK A $end +$var wire 1 "b B $end +$var supply1 1 Pb VPWR $end +$var supply0 1 Qb VGND $end +$var supply1 1 Rb VPB $end +$var supply0 1 Sb VNB $end + +$scope module base $end +$var wire 1 !b Y $end +$var wire 1 nK A $end +$var wire 1 "b B $end +$var wire 1 Tb nand0_out_Y $end +$upscope $end +$upscope $end + +$scope module U11 $end +$var wire 1 "b Y $end +$var wire 1 }a A $end +$var supply1 1 Ub VPWR $end +$var supply0 1 Vb VGND $end +$var supply1 1 Wb VPB $end +$var supply0 1 Xb VNB $end + +$scope module base $end +$var wire 1 "b Y $end +$var wire 1 }a A $end +$var wire 1 Yb not0_out_Y $end +$upscope $end +$upscope $end + +$scope module U12 $end +$var wire 1 {a Y $end +$var wire 1 }a A $end +$var wire 1 nK B $end +$var supply1 1 Zb VPWR $end +$var supply0 1 [b VGND $end +$var supply1 1 \b VPB $end +$var supply0 1 ]b VNB $end + +$scope module base $end +$var wire 1 {a Y $end +$var wire 1 }a A $end +$var wire 1 nK B $end +$var wire 1 ^b nor0_out_Y $end +$upscope $end +$upscope $end + +$scope module FTB_43__42 $end +$var wire 1 }a X $end +$var wire 1 oK A $end +$var supply1 1 _b VPWR $end +$var supply0 1 `b VGND $end +$var supply1 1 ab VPB $end +$var supply0 1 bb VNB $end + +$scope module base $end +$var wire 1 }a X $end +$var wire 1 oK A $end +$var wire 1 cb buf0_out_X $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mux_l1_in_0_ $end +$var wire 1 oH in [0] $end +$var wire 1 rH in [1] $end +$var wire 1 PJ in [2] $end +$var wire 1 ua mem [0] $end +$var wire 1 va mem [1] $end +$var wire 1 wa mem [2] $end +$var wire 1 xa mem_inv [0] $end +$var wire 1 ya mem_inv [1] $end +$var wire 1 za mem_inv [2] $end +$var wire 1 $b out [0] $end + +$scope module scs8hd_muxinv3_1_0 $end +$var wire 1 $b Z $end +$var wire 1 oH Q1 $end +$var wire 1 rH Q2 $end +$var wire 1 PJ Q3 $end +$var wire 1 ua S0 $end +$var wire 1 xa S0B $end +$var wire 1 va S1 $end +$var wire 1 ya S1B $end +$var wire 1 wa S2 $end +$var wire 1 za S2B $end +$var wire 1 db Q1__bar $end +$var wire 1 eb Q2__bar $end +$var wire 1 fb Q3__bar $end +$upscope $end +$upscope $end + +$scope module mux_l2_in_0_ $end +$var wire 1 $b in [0] $end +$var wire 1 #b in [1] $end +$var wire 1 &b in [2] $end +$var wire 1 {a mem [0] $end +$var wire 1 |a mem [1] $end +$var wire 1 }a mem [2] $end +$var wire 1 ~a mem_inv [0] $end +$var wire 1 !b mem_inv [1] $end +$var wire 1 "b mem_inv [2] $end +$var wire 1 %b out [0] $end +$var wire 1 GM p0 $end + +$scope module scs8hd_muxinv3_1_0 $end +$var wire 1 %b Z $end +$var wire 1 $b Q1 $end +$var wire 1 #b Q2 $end +$var wire 1 GM Q3 $end +$var wire 1 {a S0 $end +$var wire 1 ~a S0B $end +$var wire 1 |a S1 $end +$var wire 1 !b S1B $end +$var wire 1 }a S2 $end +$var wire 1 "b S2B $end +$var wire 1 gb Q1__bar $end +$var wire 1 hb Q2__bar $end +$var wire 1 ib Q3__bar $end +$upscope $end +$upscope $end + +$scope module mux_l1_in_1_ $end +$var wire 1 $I in [0] $end +$var wire 1 2J in [1] $end +$var wire 1 ua mem [0] $end +$var wire 1 va mem [1] $end +$var wire 1 xa mem_inv [0] $end +$var wire 1 ya mem_inv [1] $end +$var wire 1 #b out [0] $end + +$scope module scs8hd_muxinv2_1_0 $end +$var wire 1 #b Z $end +$var wire 1 $I Q1 $end +$var wire 1 2J Q2 $end +$var wire 1 ua S0 $end +$var wire 1 xa S0B $end +$var wire 1 va S1 $end +$var wire 1 ya S1B $end +$var wire 1 jb Q1__bar $end +$var wire 1 kb Q2__bar $end +$upscope $end +$upscope $end + +$scope module BINV_R_155 $end +$var wire 1 kI Y $end +$var wire 1 'b A $end +$var supply1 1 lb VPWR $end +$var supply0 1 mb VGND $end +$var supply1 1 nb VPB $end +$var supply0 1 ob VNB $end + +$scope module base $end +$var wire 1 kI Y $end +$var wire 1 'b A $end +$var wire 1 pb not0_out_Y $end +$upscope $end +$upscope $end + +$scope module BINV_R_156 $end +$var wire 1 'b Y $end +$var wire 1 %b A $end +$var supply1 1 qb VPWR $end +$var supply0 1 rb VGND $end +$var supply1 1 sb VPB $end +$var supply0 1 tb VNB $end + +$scope module base $end +$var wire 1 'b Y $end +$var wire 1 %b A $end +$var wire 1 ub not0_out_Y $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mux_right_track_36 $end +$var wire 1 VH in [0] $end +$var wire 1 aH in [1] $end +$var wire 1 lH in [2] $end +$var wire 1 8I in [3] $end +$var wire 1 6J in [4] $end +$var wire 1 pK sram [0] $end +$var wire 1 qK sram [1] $end +$var wire 1 rK sram [2] $end +$var wire 1 sK sram [3] $end +$var wire 1 jM sram_inv [0] $end +$var wire 1 kM sram_inv [1] $end +$var wire 1 lM sram_inv [2] $end +$var wire 1 mM sram_inv [3] $end +$var wire 1 8J out [0] $end +$var wire 1 9M p0 $end +$var wire 1 vb local_encoder2to3_0_data [0] $end +$var wire 1 wb local_encoder2to3_0_data [1] $end +$var wire 1 xb local_encoder2to3_0_data [2] $end +$var wire 1 yb local_encoder2to3_0_data_inv [0] $end +$var wire 1 zb local_encoder2to3_0_data_inv [1] $end +$var wire 1 {b local_encoder2to3_0_data_inv [2] $end +$var wire 1 |b local_encoder2to3_1_data [0] $end +$var wire 1 }b local_encoder2to3_1_data [1] $end +$var wire 1 ~b local_encoder2to3_1_data [2] $end +$var wire 1 !c local_encoder2to3_1_data_inv [0] $end +$var wire 1 "c local_encoder2to3_1_data_inv [1] $end +$var wire 1 #c local_encoder2to3_1_data_inv [2] $end +$var wire 1 $c mux_2level_tapbuf_basis_input2_mem2_0_out [0] $end +$var wire 1 %c mux_2level_tapbuf_basis_input3_mem3_0_out [0] $end +$var wire 1 &c mux_2level_tapbuf_basis_input3_mem3_1_out [0] $end +$var wire 1 'c SYNOPSYS_UNCONNECTED_1 $end +$var wire 1 (c BUF_net_206 $end + +$scope module local_encoder2to3_0_ $end +$var wire 1 pK addr [0] $end +$var wire 1 qK addr [1] $end +$var wire 1 vb data [0] $end +$var wire 1 wb data [1] $end +$var wire 1 xb data [2] $end +$var wire 1 yb data_inv [0] $end +$var wire 1 zb data_inv [1] $end +$var wire 1 {b data_inv [2] $end + +$scope module U8 $end +$var wire 1 yb Y $end +$var wire 1 vb A $end +$var supply1 1 )c VPWR $end +$var supply0 1 *c VGND $end +$var supply1 1 +c VPB $end +$var supply0 1 ,c VNB $end + +$scope module base $end +$var wire 1 yb Y $end +$var wire 1 vb A $end +$var wire 1 -c not0_out_Y $end +$upscope $end +$upscope $end + +$scope module U9 $end +$var wire 1 wb Y $end +$var wire 1 zb A $end +$var supply1 1 .c VPWR $end +$var supply0 1 /c VGND $end +$var supply1 1 0c VPB $end +$var supply0 1 1c VNB $end + +$scope module base $end +$var wire 1 wb Y $end +$var wire 1 zb A $end +$var wire 1 2c not0_out_Y $end +$upscope $end +$upscope $end + +$scope module U10 $end +$var wire 1 zb Y $end +$var wire 1 pK A $end +$var wire 1 {b B $end +$var supply1 1 3c VPWR $end +$var supply0 1 4c VGND $end +$var supply1 1 5c VPB $end +$var supply0 1 6c VNB $end + +$scope module base $end +$var wire 1 zb Y $end +$var wire 1 pK A $end +$var wire 1 {b B $end +$var wire 1 7c nand0_out_Y $end +$upscope $end +$upscope $end + +$scope module U11 $end +$var wire 1 {b Y $end +$var wire 1 xb A $end +$var supply1 1 8c VPWR $end +$var supply0 1 9c VGND $end +$var supply1 1 :c VPB $end +$var supply0 1 ;c VNB $end + +$scope module base $end +$var wire 1 {b Y $end +$var wire 1 xb A $end +$var wire 1 c VGND $end +$var supply1 1 ?c VPB $end +$var supply0 1 @c VNB $end + +$scope module base $end +$var wire 1 vb Y $end +$var wire 1 xb A $end +$var wire 1 pK B $end +$var wire 1 Ac nor0_out_Y $end +$upscope $end +$upscope $end + +$scope module FTB_44__43 $end +$var wire 1 xb X $end +$var wire 1 qK A $end +$var supply1 1 Bc VPWR $end +$var supply0 1 Cc VGND $end +$var supply1 1 Dc VPB $end +$var supply0 1 Ec VNB $end + +$scope module base $end +$var wire 1 xb X $end +$var wire 1 qK A $end +$var wire 1 Fc buf0_out_X $end +$upscope $end +$upscope $end +$upscope $end + +$scope module local_encoder2to3_1_ $end +$var wire 1 rK addr [0] $end +$var wire 1 sK addr [1] $end +$var wire 1 |b data [0] $end +$var wire 1 }b data [1] $end +$var wire 1 ~b data [2] $end +$var wire 1 !c data_inv [0] $end +$var wire 1 "c data_inv [1] $end +$var wire 1 #c data_inv [2] $end + +$scope module U8 $end +$var wire 1 !c Y $end +$var wire 1 |b A $end +$var supply1 1 Gc VPWR $end +$var supply0 1 Hc VGND $end +$var supply1 1 Ic VPB $end +$var supply0 1 Jc VNB $end + +$scope module base $end +$var wire 1 !c Y $end +$var wire 1 |b A $end +$var wire 1 Kc not0_out_Y $end +$upscope $end +$upscope $end + +$scope module U9 $end +$var wire 1 }b Y $end +$var wire 1 "c A $end +$var supply1 1 Lc VPWR $end +$var supply0 1 Mc VGND $end +$var supply1 1 Nc VPB $end +$var supply0 1 Oc VNB $end + +$scope module base $end +$var wire 1 }b Y $end +$var wire 1 "c A $end +$var wire 1 Pc not0_out_Y $end +$upscope $end +$upscope $end + +$scope module U10 $end +$var wire 1 "c Y $end +$var wire 1 rK A $end +$var wire 1 #c B $end +$var supply1 1 Qc VPWR $end +$var supply0 1 Rc VGND $end +$var supply1 1 Sc VPB $end +$var supply0 1 Tc VNB $end + +$scope module base $end +$var wire 1 "c Y $end +$var wire 1 rK A $end +$var wire 1 #c B $end +$var wire 1 Uc nand0_out_Y $end +$upscope $end +$upscope $end + +$scope module U11 $end +$var wire 1 #c Y $end +$var wire 1 ~b A $end +$var supply1 1 Vc VPWR $end +$var supply0 1 Wc VGND $end +$var supply1 1 Xc VPB $end +$var supply0 1 Yc VNB $end + +$scope module base $end +$var wire 1 #c Y $end +$var wire 1 ~b A $end +$var wire 1 Zc not0_out_Y $end +$upscope $end +$upscope $end + +$scope module U12 $end +$var wire 1 |b Y $end +$var wire 1 ~b A $end +$var wire 1 rK B $end +$var supply1 1 [c VPWR $end +$var supply0 1 \c VGND $end +$var supply1 1 ]c VPB $end +$var supply0 1 ^c VNB $end + +$scope module base $end +$var wire 1 |b Y $end +$var wire 1 ~b A $end +$var wire 1 rK B $end +$var wire 1 _c nor0_out_Y $end +$upscope $end +$upscope $end + +$scope module FTB_45__44 $end +$var wire 1 ~b X $end +$var wire 1 sK A $end +$var supply1 1 `c VPWR $end +$var supply0 1 ac VGND $end +$var supply1 1 bc VPB $end +$var supply0 1 cc VNB $end + +$scope module base $end +$var wire 1 ~b X $end +$var wire 1 sK A $end +$var wire 1 dc buf0_out_X $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mux_l1_in_0_ $end +$var wire 1 VH in [0] $end +$var wire 1 aH in [1] $end +$var wire 1 lH in [2] $end +$var wire 1 vb mem [0] $end +$var wire 1 wb mem [1] $end +$var wire 1 xb mem [2] $end +$var wire 1 yb mem_inv [0] $end +$var wire 1 zb mem_inv [1] $end +$var wire 1 {b mem_inv [2] $end +$var wire 1 %c out [0] $end + +$scope module scs8hd_muxinv3_1_0 $end +$var wire 1 %c Z $end +$var wire 1 VH Q1 $end +$var wire 1 aH Q2 $end +$var wire 1 lH Q3 $end +$var wire 1 vb S0 $end +$var wire 1 yb S0B $end +$var wire 1 wb S1 $end +$var wire 1 zb S1B $end +$var wire 1 xb S2 $end +$var wire 1 {b S2B $end +$var wire 1 ec Q1__bar $end +$var wire 1 fc Q2__bar $end +$var wire 1 gc Q3__bar $end +$upscope $end +$upscope $end + +$scope module mux_l2_in_0_ $end +$var wire 1 %c in [0] $end +$var wire 1 $c in [1] $end +$var wire 1 'c in [2] $end +$var wire 1 |b mem [0] $end +$var wire 1 }b mem [1] $end +$var wire 1 ~b mem [2] $end +$var wire 1 !c mem_inv [0] $end +$var wire 1 "c mem_inv [1] $end +$var wire 1 #c mem_inv [2] $end +$var wire 1 &c out [0] $end +$var wire 1 9M p0 $end + +$scope module scs8hd_muxinv3_1_0 $end +$var wire 1 &c Z $end +$var wire 1 %c Q1 $end +$var wire 1 $c Q2 $end +$var wire 1 9M Q3 $end +$var wire 1 |b S0 $end +$var wire 1 !c S0B $end +$var wire 1 }b S1 $end +$var wire 1 "c S1B $end +$var wire 1 ~b S2 $end +$var wire 1 #c S2B $end +$var wire 1 hc Q1__bar $end +$var wire 1 ic Q2__bar $end +$var wire 1 jc Q3__bar $end +$upscope $end +$upscope $end + +$scope module mux_l1_in_1_ $end +$var wire 1 8I in [0] $end +$var wire 1 6J in [1] $end +$var wire 1 vb mem [0] $end +$var wire 1 wb mem [1] $end +$var wire 1 yb mem_inv [0] $end +$var wire 1 zb mem_inv [1] $end +$var wire 1 $c out [0] $end + +$scope module scs8hd_muxinv2_1_0 $end +$var wire 1 $c Z $end +$var wire 1 8I Q1 $end +$var wire 1 6J Q2 $end +$var wire 1 vb S0 $end +$var wire 1 yb S0B $end +$var wire 1 wb S1 $end +$var wire 1 zb S1B $end +$var wire 1 kc Q1__bar $end +$var wire 1 lc Q2__bar $end +$upscope $end +$upscope $end + +$scope module BINV_R_205 $end +$var wire 1 8J Y $end +$var wire 1 (c A $end +$var supply1 1 mc VPWR $end +$var supply0 1 nc VGND $end +$var supply1 1 oc VPB $end +$var supply0 1 pc VNB $end + +$scope module base $end +$var wire 1 8J Y $end +$var wire 1 (c A $end +$var wire 1 qc not0_out_Y $end +$upscope $end +$upscope $end + +$scope module BINV_R_206 $end +$var wire 1 (c Y $end +$var wire 1 &c A $end +$var supply1 1 rc VPWR $end +$var supply0 1 sc VGND $end +$var supply1 1 tc VPB $end +$var supply0 1 uc VNB $end + +$scope module base $end +$var wire 1 (c Y $end +$var wire 1 &c A $end +$var wire 1 vc not0_out_Y $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mux_left_track_37 $end +$var wire 1 RH in [0] $end +$var wire 1 ]H in [1] $end +$var wire 1 hH in [2] $end +$var wire 1 TJ in [3] $end +$var wire 1 _I in [4] $end +$var wire 1 tK sram [0] $end +$var wire 1 uK sram [1] $end +$var wire 1 vK sram [2] $end +$var wire 1 wK sram [3] $end +$var wire 1 nM sram_inv [0] $end +$var wire 1 oM sram_inv [1] $end +$var wire 1 pM sram_inv [2] $end +$var wire 1 qM sram_inv [3] $end +$var wire 1 VJ out [0] $end +$var wire 1 GM p0 $end +$var wire 1 wc local_encoder2to3_0_data [0] $end +$var wire 1 xc local_encoder2to3_0_data [1] $end +$var wire 1 yc local_encoder2to3_0_data [2] $end +$var wire 1 zc local_encoder2to3_0_data_inv [0] $end +$var wire 1 {c local_encoder2to3_0_data_inv [1] $end +$var wire 1 |c local_encoder2to3_0_data_inv [2] $end +$var wire 1 }c local_encoder2to3_1_data [0] $end +$var wire 1 ~c local_encoder2to3_1_data [1] $end +$var wire 1 !d local_encoder2to3_1_data [2] $end +$var wire 1 "d local_encoder2to3_1_data_inv [0] $end +$var wire 1 #d local_encoder2to3_1_data_inv [1] $end +$var wire 1 $d local_encoder2to3_1_data_inv [2] $end +$var wire 1 %d mux_2level_tapbuf_basis_input2_mem2_0_out [0] $end +$var wire 1 &d mux_2level_tapbuf_basis_input3_mem3_0_out [0] $end +$var wire 1 'd mux_2level_tapbuf_basis_input3_mem3_1_out [0] $end +$var wire 1 (d SYNOPSYS_UNCONNECTED_1 $end +$var wire 1 )d BUF_net_158 $end + +$scope module local_encoder2to3_0_ $end +$var wire 1 tK addr [0] $end +$var wire 1 uK addr [1] $end +$var wire 1 wc data [0] $end +$var wire 1 xc data [1] $end +$var wire 1 yc data [2] $end +$var wire 1 zc data_inv [0] $end +$var wire 1 {c data_inv [1] $end +$var wire 1 |c data_inv [2] $end + +$scope module U8 $end +$var wire 1 zc Y $end +$var wire 1 wc A $end +$var supply1 1 *d VPWR $end +$var supply0 1 +d VGND $end +$var supply1 1 ,d VPB $end +$var supply0 1 -d VNB $end + +$scope module base $end +$var wire 1 zc Y $end +$var wire 1 wc A $end +$var wire 1 .d not0_out_Y $end +$upscope $end +$upscope $end + +$scope module U9 $end +$var wire 1 xc Y $end +$var wire 1 {c A $end +$var supply1 1 /d VPWR $end +$var supply0 1 0d VGND $end +$var supply1 1 1d VPB $end +$var supply0 1 2d VNB $end + +$scope module base $end +$var wire 1 xc Y $end +$var wire 1 {c A $end +$var wire 1 3d not0_out_Y $end +$upscope $end +$upscope $end + +$scope module U10 $end +$var wire 1 {c Y $end +$var wire 1 tK A $end +$var wire 1 |c B $end +$var supply1 1 4d VPWR $end +$var supply0 1 5d VGND $end +$var supply1 1 6d VPB $end +$var supply0 1 7d VNB $end + +$scope module base $end +$var wire 1 {c Y $end +$var wire 1 tK A $end +$var wire 1 |c B $end +$var wire 1 8d nand0_out_Y $end +$upscope $end +$upscope $end + +$scope module U11 $end +$var wire 1 |c Y $end +$var wire 1 yc A $end +$var supply1 1 9d VPWR $end +$var supply0 1 :d VGND $end +$var supply1 1 ;d VPB $end +$var supply0 1 d VPWR $end +$var supply0 1 ?d VGND $end +$var supply1 1 @d VPB $end +$var supply0 1 Ad VNB $end + +$scope module base $end +$var wire 1 wc Y $end +$var wire 1 yc A $end +$var wire 1 tK B $end +$var wire 1 Bd nor0_out_Y $end +$upscope $end +$upscope $end + +$scope module FTB_46__45 $end +$var wire 1 yc X $end +$var wire 1 uK A $end +$var supply1 1 Cd VPWR $end +$var supply0 1 Dd VGND $end +$var supply1 1 Ed VPB $end +$var supply0 1 Fd VNB $end + +$scope module base $end +$var wire 1 yc X $end +$var wire 1 uK A $end +$var wire 1 Gd buf0_out_X $end +$upscope $end +$upscope $end +$upscope $end + +$scope module local_encoder2to3_1_ $end +$var wire 1 vK addr [0] $end +$var wire 1 wK addr [1] $end +$var wire 1 }c data [0] $end +$var wire 1 ~c data [1] $end +$var wire 1 !d data [2] $end +$var wire 1 "d data_inv [0] $end +$var wire 1 #d data_inv [1] $end +$var wire 1 $d data_inv [2] $end + +$scope module U8 $end +$var wire 1 "d Y $end +$var wire 1 }c A $end +$var supply1 1 Hd VPWR $end +$var supply0 1 Id VGND $end +$var supply1 1 Jd VPB $end +$var supply0 1 Kd VNB $end + +$scope module base $end +$var wire 1 "d Y $end +$var wire 1 }c A $end +$var wire 1 Ld not0_out_Y $end +$upscope $end +$upscope $end + +$scope module U9 $end +$var wire 1 ~c Y $end +$var wire 1 #d A $end +$var supply1 1 Md VPWR $end +$var supply0 1 Nd VGND $end +$var supply1 1 Od VPB $end +$var supply0 1 Pd VNB $end + +$scope module base $end +$var wire 1 ~c Y $end +$var wire 1 #d A $end +$var wire 1 Qd not0_out_Y $end +$upscope $end +$upscope $end + +$scope module U10 $end +$var wire 1 #d Y $end +$var wire 1 vK A $end +$var wire 1 $d B $end +$var supply1 1 Rd VPWR $end +$var supply0 1 Sd VGND $end +$var supply1 1 Td VPB $end +$var supply0 1 Ud VNB $end + +$scope module base $end +$var wire 1 #d Y $end +$var wire 1 vK A $end +$var wire 1 $d B $end +$var wire 1 Vd nand0_out_Y $end +$upscope $end +$upscope $end + +$scope module U11 $end +$var wire 1 $d Y $end +$var wire 1 !d A $end +$var supply1 1 Wd VPWR $end +$var supply0 1 Xd VGND $end +$var supply1 1 Yd VPB $end +$var supply0 1 Zd VNB $end + +$scope module base $end +$var wire 1 $d Y $end +$var wire 1 !d A $end +$var wire 1 [d not0_out_Y $end +$upscope $end +$upscope $end + +$scope module U12 $end +$var wire 1 }c Y $end +$var wire 1 !d A $end +$var wire 1 vK B $end +$var supply1 1 \d VPWR $end +$var supply0 1 ]d VGND $end +$var supply1 1 ^d VPB $end +$var supply0 1 _d VNB $end + +$scope module base $end +$var wire 1 }c Y $end +$var wire 1 !d A $end +$var wire 1 vK B $end +$var wire 1 `d nor0_out_Y $end +$upscope $end +$upscope $end + +$scope module FTB_47__46 $end +$var wire 1 !d X $end +$var wire 1 wK A $end +$var supply1 1 ad VPWR $end +$var supply0 1 bd VGND $end +$var supply1 1 cd VPB $end +$var supply0 1 dd VNB $end + +$scope module base $end +$var wire 1 !d X $end +$var wire 1 wK A $end +$var wire 1 ed buf0_out_X $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mux_l1_in_0_ $end +$var wire 1 RH in [0] $end +$var wire 1 ]H in [1] $end +$var wire 1 hH in [2] $end +$var wire 1 wc mem [0] $end +$var wire 1 xc mem [1] $end +$var wire 1 yc mem [2] $end +$var wire 1 zc mem_inv [0] $end +$var wire 1 {c mem_inv [1] $end +$var wire 1 |c mem_inv [2] $end +$var wire 1 &d out [0] $end + +$scope module scs8hd_muxinv3_1_0 $end +$var wire 1 &d Z $end +$var wire 1 RH Q1 $end +$var wire 1 ]H Q2 $end +$var wire 1 hH Q3 $end +$var wire 1 wc S0 $end +$var wire 1 zc S0B $end +$var wire 1 xc S1 $end +$var wire 1 {c S1B $end +$var wire 1 yc S2 $end +$var wire 1 |c S2B $end +$var wire 1 fd Q1__bar $end +$var wire 1 gd Q2__bar $end +$var wire 1 hd Q3__bar $end +$upscope $end +$upscope $end + +$scope module mux_l2_in_0_ $end +$var wire 1 &d in [0] $end +$var wire 1 %d in [1] $end +$var wire 1 (d in [2] $end +$var wire 1 }c mem [0] $end +$var wire 1 ~c mem [1] $end +$var wire 1 !d mem [2] $end +$var wire 1 "d mem_inv [0] $end +$var wire 1 #d mem_inv [1] $end +$var wire 1 $d mem_inv [2] $end +$var wire 1 'd out [0] $end +$var wire 1 GM p0 $end + +$scope module scs8hd_muxinv3_1_0 $end +$var wire 1 'd Z $end +$var wire 1 &d Q1 $end +$var wire 1 %d Q2 $end +$var wire 1 GM Q3 $end +$var wire 1 }c S0 $end +$var wire 1 "d S0B $end +$var wire 1 ~c S1 $end +$var wire 1 #d S1B $end +$var wire 1 !d S2 $end +$var wire 1 $d S2B $end +$var wire 1 id Q1__bar $end +$var wire 1 jd Q2__bar $end +$var wire 1 kd Q3__bar $end +$upscope $end +$upscope $end + +$scope module mux_l1_in_1_ $end +$var wire 1 TJ in [0] $end +$var wire 1 _I in [1] $end +$var wire 1 wc mem [0] $end +$var wire 1 xc mem [1] $end +$var wire 1 zc mem_inv [0] $end +$var wire 1 {c mem_inv [1] $end +$var wire 1 %d out [0] $end + +$scope module scs8hd_muxinv2_1_0 $end +$var wire 1 %d Z $end +$var wire 1 TJ Q1 $end +$var wire 1 _I Q2 $end +$var wire 1 wc S0 $end +$var wire 1 zc S0B $end +$var wire 1 xc S1 $end +$var wire 1 {c S1B $end +$var wire 1 ld Q1__bar $end +$var wire 1 md Q2__bar $end +$upscope $end +$upscope $end + +$scope module BINV_R_157 $end +$var wire 1 VJ Y $end +$var wire 1 )d A $end +$var supply1 1 nd VPWR $end +$var supply0 1 od VGND $end +$var supply1 1 pd VPB $end +$var supply0 1 qd VNB $end + +$scope module base $end +$var wire 1 VJ Y $end +$var wire 1 )d A $end +$var wire 1 rd not0_out_Y $end +$upscope $end +$upscope $end + +$scope module BINV_R_158 $end +$var wire 1 )d Y $end +$var wire 1 'd A $end +$var supply1 1 sd VPWR $end +$var supply0 1 td VGND $end +$var supply1 1 ud VPB $end +$var supply0 1 vd VNB $end + +$scope module base $end +$var wire 1 )d Y $end +$var wire 1 'd A $end +$var wire 1 wd not0_out_Y $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mux_left_track_45 $end +$var wire 1 QH in [0] $end +$var wire 1 \H in [1] $end +$var wire 1 gH in [2] $end +$var wire 1 UJ in [3] $end +$var wire 1 `I in [4] $end +$var wire 1 xK sram [0] $end +$var wire 1 yK sram [1] $end +$var wire 1 zK sram [2] $end +$var wire 1 {K sram [3] $end +$var wire 1 rM sram_inv [0] $end +$var wire 1 sM sram_inv [1] $end +$var wire 1 tM sram_inv [2] $end +$var wire 1 uM sram_inv [3] $end +$var wire 1 ZJ out [0] $end +$var wire 1 GM p0 $end +$var wire 1 xd local_encoder2to3_0_data [0] $end +$var wire 1 yd local_encoder2to3_0_data [1] $end +$var wire 1 zd local_encoder2to3_0_data [2] $end +$var wire 1 {d local_encoder2to3_0_data_inv [0] $end +$var wire 1 |d local_encoder2to3_0_data_inv [1] $end +$var wire 1 }d local_encoder2to3_0_data_inv [2] $end +$var wire 1 ~d local_encoder2to3_1_data [0] $end +$var wire 1 !e local_encoder2to3_1_data [1] $end +$var wire 1 "e local_encoder2to3_1_data [2] $end +$var wire 1 #e local_encoder2to3_1_data_inv [0] $end +$var wire 1 $e local_encoder2to3_1_data_inv [1] $end +$var wire 1 %e local_encoder2to3_1_data_inv [2] $end +$var wire 1 &e mux_2level_tapbuf_basis_input2_mem2_0_out [0] $end +$var wire 1 'e mux_2level_tapbuf_basis_input3_mem3_0_out [0] $end +$var wire 1 (e mux_2level_tapbuf_basis_input3_mem3_1_out [0] $end +$var wire 1 )e SYNOPSYS_UNCONNECTED_1 $end +$var wire 1 *e BUF_net_160 $end + +$scope module local_encoder2to3_0_ $end +$var wire 1 xK addr [0] $end +$var wire 1 yK addr [1] $end +$var wire 1 xd data [0] $end +$var wire 1 yd data [1] $end +$var wire 1 zd data [2] $end +$var wire 1 {d data_inv [0] $end +$var wire 1 |d data_inv [1] $end +$var wire 1 }d data_inv [2] $end + +$scope module U8 $end +$var wire 1 {d Y $end +$var wire 1 xd A $end +$var supply1 1 +e VPWR $end +$var supply0 1 ,e VGND $end +$var supply1 1 -e VPB $end +$var supply0 1 .e VNB $end + +$scope module base $end +$var wire 1 {d Y $end +$var wire 1 xd A $end +$var wire 1 /e not0_out_Y $end +$upscope $end +$upscope $end + +$scope module U9 $end +$var wire 1 yd Y $end +$var wire 1 |d A $end +$var supply1 1 0e VPWR $end +$var supply0 1 1e VGND $end +$var supply1 1 2e VPB $end +$var supply0 1 3e VNB $end + +$scope module base $end +$var wire 1 yd Y $end +$var wire 1 |d A $end +$var wire 1 4e not0_out_Y $end +$upscope $end +$upscope $end + +$scope module U10 $end +$var wire 1 |d Y $end +$var wire 1 xK A $end +$var wire 1 }d B $end +$var supply1 1 5e VPWR $end +$var supply0 1 6e VGND $end +$var supply1 1 7e VPB $end +$var supply0 1 8e VNB $end + +$scope module base $end +$var wire 1 |d Y $end +$var wire 1 xK A $end +$var wire 1 }d B $end +$var wire 1 9e nand0_out_Y $end +$upscope $end +$upscope $end + +$scope module U11 $end +$var wire 1 }d Y $end +$var wire 1 zd A $end +$var supply1 1 :e VPWR $end +$var supply0 1 ;e VGND $end +$var supply1 1 e not0_out_Y $end +$upscope $end +$upscope $end + +$scope module U12 $end +$var wire 1 xd Y $end +$var wire 1 zd A $end +$var wire 1 xK B $end +$var supply1 1 ?e VPWR $end +$var supply0 1 @e VGND $end +$var supply1 1 Ae VPB $end +$var supply0 1 Be VNB $end + +$scope module base $end +$var wire 1 xd Y $end +$var wire 1 zd A $end +$var wire 1 xK B $end +$var wire 1 Ce nor0_out_Y $end +$upscope $end +$upscope $end + +$scope module FTB_48__47 $end +$var wire 1 zd X $end +$var wire 1 yK A $end +$var supply1 1 De VPWR $end +$var supply0 1 Ee VGND $end +$var supply1 1 Fe VPB $end +$var supply0 1 Ge VNB $end + +$scope module base $end +$var wire 1 zd X $end +$var wire 1 yK A $end +$var wire 1 He buf0_out_X $end +$upscope $end +$upscope $end +$upscope $end + +$scope module local_encoder2to3_1_ $end +$var wire 1 zK addr [0] $end +$var wire 1 {K addr [1] $end +$var wire 1 ~d data [0] $end +$var wire 1 !e data [1] $end +$var wire 1 "e data [2] $end +$var wire 1 #e data_inv [0] $end +$var wire 1 $e data_inv [1] $end +$var wire 1 %e data_inv [2] $end + +$scope module U8 $end +$var wire 1 #e Y $end +$var wire 1 ~d A $end +$var supply1 1 Ie VPWR $end +$var supply0 1 Je VGND $end +$var supply1 1 Ke VPB $end +$var supply0 1 Le VNB $end + +$scope module base $end +$var wire 1 #e Y $end +$var wire 1 ~d A $end +$var wire 1 Me not0_out_Y $end +$upscope $end +$upscope $end + +$scope module U9 $end +$var wire 1 !e Y $end +$var wire 1 $e A $end +$var supply1 1 Ne VPWR $end +$var supply0 1 Oe VGND $end +$var supply1 1 Pe VPB $end +$var supply0 1 Qe VNB $end + +$scope module base $end +$var wire 1 !e Y $end +$var wire 1 $e A $end +$var wire 1 Re not0_out_Y $end +$upscope $end +$upscope $end + +$scope module U10 $end +$var wire 1 $e Y $end +$var wire 1 zK A $end +$var wire 1 %e B $end +$var supply1 1 Se VPWR $end +$var supply0 1 Te VGND $end +$var supply1 1 Ue VPB $end +$var supply0 1 Ve VNB $end + +$scope module base $end +$var wire 1 $e Y $end +$var wire 1 zK A $end +$var wire 1 %e B $end +$var wire 1 We nand0_out_Y $end +$upscope $end +$upscope $end + +$scope module U11 $end +$var wire 1 %e Y $end +$var wire 1 "e A $end +$var supply1 1 Xe VPWR $end +$var supply0 1 Ye VGND $end +$var supply1 1 Ze VPB $end +$var supply0 1 [e VNB $end + +$scope module base $end +$var wire 1 %e Y $end +$var wire 1 "e A $end +$var wire 1 \e not0_out_Y $end +$upscope $end +$upscope $end + +$scope module U12 $end +$var wire 1 ~d Y $end +$var wire 1 "e A $end +$var wire 1 zK B $end +$var supply1 1 ]e VPWR $end +$var supply0 1 ^e VGND $end +$var supply1 1 _e VPB $end +$var supply0 1 `e VNB $end + +$scope module base $end +$var wire 1 ~d Y $end +$var wire 1 "e A $end +$var wire 1 zK B $end +$var wire 1 ae nor0_out_Y $end +$upscope $end +$upscope $end + +$scope module FTB_49__48 $end +$var wire 1 "e X $end +$var wire 1 {K A $end +$var supply1 1 be VPWR $end +$var supply0 1 ce VGND $end +$var supply1 1 de VPB $end +$var supply0 1 ee VNB $end + +$scope module base $end +$var wire 1 "e X $end +$var wire 1 {K A $end +$var wire 1 fe buf0_out_X $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mux_l1_in_0_ $end +$var wire 1 QH in [0] $end +$var wire 1 \H in [1] $end +$var wire 1 gH in [2] $end +$var wire 1 xd mem [0] $end +$var wire 1 yd mem [1] $end +$var wire 1 zd mem [2] $end +$var wire 1 {d mem_inv [0] $end +$var wire 1 |d mem_inv [1] $end +$var wire 1 }d mem_inv [2] $end +$var wire 1 'e out [0] $end + +$scope module scs8hd_muxinv3_1_0 $end +$var wire 1 'e Z $end +$var wire 1 QH Q1 $end +$var wire 1 \H Q2 $end +$var wire 1 gH Q3 $end +$var wire 1 xd S0 $end +$var wire 1 {d S0B $end +$var wire 1 yd S1 $end +$var wire 1 |d S1B $end +$var wire 1 zd S2 $end +$var wire 1 }d S2B $end +$var wire 1 ge Q1__bar $end +$var wire 1 he Q2__bar $end +$var wire 1 ie Q3__bar $end +$upscope $end +$upscope $end + +$scope module mux_l2_in_0_ $end +$var wire 1 'e in [0] $end +$var wire 1 &e in [1] $end +$var wire 1 )e in [2] $end +$var wire 1 ~d mem [0] $end +$var wire 1 !e mem [1] $end +$var wire 1 "e mem [2] $end +$var wire 1 #e mem_inv [0] $end +$var wire 1 $e mem_inv [1] $end +$var wire 1 %e mem_inv [2] $end +$var wire 1 (e out [0] $end +$var wire 1 GM p0 $end + +$scope module scs8hd_muxinv3_1_0 $end +$var wire 1 (e Z $end +$var wire 1 'e Q1 $end +$var wire 1 &e Q2 $end +$var wire 1 GM Q3 $end +$var wire 1 ~d S0 $end +$var wire 1 #e S0B $end +$var wire 1 !e S1 $end +$var wire 1 $e S1B $end +$var wire 1 "e S2 $end +$var wire 1 %e S2B $end +$var wire 1 je Q1__bar $end +$var wire 1 ke Q2__bar $end +$var wire 1 le Q3__bar $end +$upscope $end +$upscope $end + +$scope module mux_l1_in_1_ $end +$var wire 1 UJ in [0] $end +$var wire 1 `I in [1] $end +$var wire 1 xd mem [0] $end +$var wire 1 yd mem [1] $end +$var wire 1 {d mem_inv [0] $end +$var wire 1 |d mem_inv [1] $end +$var wire 1 &e out [0] $end + +$scope module scs8hd_muxinv2_1_0 $end +$var wire 1 &e Z $end +$var wire 1 UJ Q1 $end +$var wire 1 `I Q2 $end +$var wire 1 xd S0 $end +$var wire 1 {d S0B $end +$var wire 1 yd S1 $end +$var wire 1 |d S1B $end +$var wire 1 me Q1__bar $end +$var wire 1 ne Q2__bar $end +$upscope $end +$upscope $end + +$scope module BINV_R_159 $end +$var wire 1 ZJ Y $end +$var wire 1 *e A $end +$var supply1 1 oe VPWR $end +$var supply0 1 pe VGND $end +$var supply1 1 qe VPB $end +$var supply0 1 re VNB $end + +$scope module base $end +$var wire 1 ZJ Y $end +$var wire 1 *e A $end +$var wire 1 se not0_out_Y $end +$upscope $end +$upscope $end + +$scope module BINV_R_160 $end +$var wire 1 *e Y $end +$var wire 1 (e A $end +$var supply1 1 te VPWR $end +$var supply0 1 ue VGND $end +$var supply1 1 ve VPB $end +$var supply0 1 we VNB $end + +$scope module base $end +$var wire 1 *e Y $end +$var wire 1 (e A $end +$var wire 1 xe not0_out_Y $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mux_left_track_53 $end +$var wire 1 PH in [0] $end +$var wire 1 [H in [1] $end +$var wire 1 fH in [2] $end +$var wire 1 WJ in [3] $end +$var wire 1 aI in [4] $end +$var wire 1 |K sram [0] $end +$var wire 1 }K sram [1] $end +$var wire 1 ~K sram [2] $end +$var wire 1 !L sram [3] $end +$var wire 1 vM sram_inv [0] $end +$var wire 1 wM sram_inv [1] $end +$var wire 1 xM sram_inv [2] $end +$var wire 1 yM sram_inv [3] $end +$var wire 1 ^J out [0] $end +$var wire 1 GM p0 $end +$var wire 1 ye local_encoder2to3_0_data [0] $end +$var wire 1 ze local_encoder2to3_0_data [1] $end +$var wire 1 {e local_encoder2to3_0_data [2] $end +$var wire 1 |e local_encoder2to3_0_data_inv [0] $end +$var wire 1 }e local_encoder2to3_0_data_inv [1] $end +$var wire 1 ~e local_encoder2to3_0_data_inv [2] $end +$var wire 1 !f local_encoder2to3_1_data [0] $end +$var wire 1 "f local_encoder2to3_1_data [1] $end +$var wire 1 #f local_encoder2to3_1_data [2] $end +$var wire 1 $f local_encoder2to3_1_data_inv [0] $end +$var wire 1 %f local_encoder2to3_1_data_inv [1] $end +$var wire 1 &f local_encoder2to3_1_data_inv [2] $end +$var wire 1 'f mux_2level_tapbuf_basis_input2_mem2_0_out [0] $end +$var wire 1 (f mux_2level_tapbuf_basis_input3_mem3_0_out [0] $end +$var wire 1 )f mux_2level_tapbuf_basis_input3_mem3_1_out [0] $end +$var wire 1 *f SYNOPSYS_UNCONNECTED_1 $end +$var wire 1 +f BUF_net_162 $end + +$scope module local_encoder2to3_0_ $end +$var wire 1 |K addr [0] $end +$var wire 1 }K addr [1] $end +$var wire 1 ye data [0] $end +$var wire 1 ze data [1] $end +$var wire 1 {e data [2] $end +$var wire 1 |e data_inv [0] $end +$var wire 1 }e data_inv [1] $end +$var wire 1 ~e data_inv [2] $end + +$scope module U8 $end +$var wire 1 |e Y $end +$var wire 1 ye A $end +$var supply1 1 ,f VPWR $end +$var supply0 1 -f VGND $end +$var supply1 1 .f VPB $end +$var supply0 1 /f VNB $end + +$scope module base $end +$var wire 1 |e Y $end +$var wire 1 ye A $end +$var wire 1 0f not0_out_Y $end +$upscope $end +$upscope $end + +$scope module U9 $end +$var wire 1 ze Y $end +$var wire 1 }e A $end +$var supply1 1 1f VPWR $end +$var supply0 1 2f VGND $end +$var supply1 1 3f VPB $end +$var supply0 1 4f VNB $end + +$scope module base $end +$var wire 1 ze Y $end +$var wire 1 }e A $end +$var wire 1 5f not0_out_Y $end +$upscope $end +$upscope $end + +$scope module U10 $end +$var wire 1 }e Y $end +$var wire 1 |K A $end +$var wire 1 ~e B $end +$var supply1 1 6f VPWR $end +$var supply0 1 7f VGND $end +$var supply1 1 8f VPB $end +$var supply0 1 9f VNB $end + +$scope module base $end +$var wire 1 }e Y $end +$var wire 1 |K A $end +$var wire 1 ~e B $end +$var wire 1 :f nand0_out_Y $end +$upscope $end +$upscope $end + +$scope module U11 $end +$var wire 1 ~e Y $end +$var wire 1 {e A $end +$var supply1 1 ;f VPWR $end +$var supply0 1 f VNB $end + +$scope module base $end +$var wire 1 ~e Y $end +$var wire 1 {e A $end +$var wire 1 ?f not0_out_Y $end +$upscope $end +$upscope $end + +$scope module U12 $end +$var wire 1 ye Y $end +$var wire 1 {e A $end +$var wire 1 |K B $end +$var supply1 1 @f VPWR $end +$var supply0 1 Af VGND $end +$var supply1 1 Bf VPB $end +$var supply0 1 Cf VNB $end + +$scope module base $end +$var wire 1 ye Y $end +$var wire 1 {e A $end +$var wire 1 |K B $end +$var wire 1 Df nor0_out_Y $end +$upscope $end +$upscope $end + +$scope module FTB_50__49 $end +$var wire 1 {e X $end +$var wire 1 }K A $end +$var supply1 1 Ef VPWR $end +$var supply0 1 Ff VGND $end +$var supply1 1 Gf VPB $end +$var supply0 1 Hf VNB $end + +$scope module base $end +$var wire 1 {e X $end +$var wire 1 }K A $end +$var wire 1 If buf0_out_X $end +$upscope $end +$upscope $end +$upscope $end + +$scope module local_encoder2to3_1_ $end +$var wire 1 ~K addr [0] $end +$var wire 1 !L addr [1] $end +$var wire 1 !f data [0] $end +$var wire 1 "f data [1] $end +$var wire 1 #f data [2] $end +$var wire 1 $f data_inv [0] $end +$var wire 1 %f data_inv [1] $end +$var wire 1 &f data_inv [2] $end + +$scope module U8 $end +$var wire 1 $f Y $end +$var wire 1 !f A $end +$var supply1 1 Jf VPWR $end +$var supply0 1 Kf VGND $end +$var supply1 1 Lf VPB $end +$var supply0 1 Mf VNB $end + +$scope module base $end +$var wire 1 $f Y $end +$var wire 1 !f A $end +$var wire 1 Nf not0_out_Y $end +$upscope $end +$upscope $end + +$scope module U9 $end +$var wire 1 "f Y $end +$var wire 1 %f A $end +$var supply1 1 Of VPWR $end +$var supply0 1 Pf VGND $end +$var supply1 1 Qf VPB $end +$var supply0 1 Rf VNB $end + +$scope module base $end +$var wire 1 "f Y $end +$var wire 1 %f A $end +$var wire 1 Sf not0_out_Y $end +$upscope $end +$upscope $end + +$scope module U10 $end +$var wire 1 %f Y $end +$var wire 1 ~K A $end +$var wire 1 &f B $end +$var supply1 1 Tf VPWR $end +$var supply0 1 Uf VGND $end +$var supply1 1 Vf VPB $end +$var supply0 1 Wf VNB $end + +$scope module base $end +$var wire 1 %f Y $end +$var wire 1 ~K A $end +$var wire 1 &f B $end +$var wire 1 Xf nand0_out_Y $end +$upscope $end +$upscope $end + +$scope module U11 $end +$var wire 1 &f Y $end +$var wire 1 #f A $end +$var supply1 1 Yf VPWR $end +$var supply0 1 Zf VGND $end +$var supply1 1 [f VPB $end +$var supply0 1 \f VNB $end + +$scope module base $end +$var wire 1 &f Y $end +$var wire 1 #f A $end +$var wire 1 ]f not0_out_Y $end +$upscope $end +$upscope $end + +$scope module U12 $end +$var wire 1 !f Y $end +$var wire 1 #f A $end +$var wire 1 ~K B $end +$var supply1 1 ^f VPWR $end +$var supply0 1 _f VGND $end +$var supply1 1 `f VPB $end +$var supply0 1 af VNB $end + +$scope module base $end +$var wire 1 !f Y $end +$var wire 1 #f A $end +$var wire 1 ~K B $end +$var wire 1 bf nor0_out_Y $end +$upscope $end +$upscope $end + +$scope module FTB_51__50 $end +$var wire 1 #f X $end +$var wire 1 !L A $end +$var supply1 1 cf VPWR $end +$var supply0 1 df VGND $end +$var supply1 1 ef VPB $end +$var supply0 1 ff VNB $end + +$scope module base $end +$var wire 1 #f X $end +$var wire 1 !L A $end +$var wire 1 gf buf0_out_X $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mux_l1_in_0_ $end +$var wire 1 PH in [0] $end +$var wire 1 [H in [1] $end +$var wire 1 fH in [2] $end +$var wire 1 ye mem [0] $end +$var wire 1 ze mem [1] $end +$var wire 1 {e mem [2] $end +$var wire 1 |e mem_inv [0] $end +$var wire 1 }e mem_inv [1] $end +$var wire 1 ~e mem_inv [2] $end +$var wire 1 (f out [0] $end + +$scope module scs8hd_muxinv3_1_0 $end +$var wire 1 (f Z $end +$var wire 1 PH Q1 $end +$var wire 1 [H Q2 $end +$var wire 1 fH Q3 $end +$var wire 1 ye S0 $end +$var wire 1 |e S0B $end +$var wire 1 ze S1 $end +$var wire 1 }e S1B $end +$var wire 1 {e S2 $end +$var wire 1 ~e S2B $end +$var wire 1 hf Q1__bar $end +$var wire 1 if Q2__bar $end +$var wire 1 jf Q3__bar $end +$upscope $end +$upscope $end + +$scope module mux_l2_in_0_ $end +$var wire 1 (f in [0] $end +$var wire 1 'f in [1] $end +$var wire 1 *f in [2] $end +$var wire 1 !f mem [0] $end +$var wire 1 "f mem [1] $end +$var wire 1 #f mem [2] $end +$var wire 1 $f mem_inv [0] $end +$var wire 1 %f mem_inv [1] $end +$var wire 1 &f mem_inv [2] $end +$var wire 1 )f out [0] $end +$var wire 1 GM p0 $end + +$scope module scs8hd_muxinv3_1_0 $end +$var wire 1 )f Z $end +$var wire 1 (f Q1 $end +$var wire 1 'f Q2 $end +$var wire 1 GM Q3 $end +$var wire 1 !f S0 $end +$var wire 1 $f S0B $end +$var wire 1 "f S1 $end +$var wire 1 %f S1B $end +$var wire 1 #f S2 $end +$var wire 1 &f S2B $end +$var wire 1 kf Q1__bar $end +$var wire 1 lf Q2__bar $end +$var wire 1 mf Q3__bar $end +$upscope $end +$upscope $end + +$scope module mux_l1_in_1_ $end +$var wire 1 WJ in [0] $end +$var wire 1 aI in [1] $end +$var wire 1 ye mem [0] $end +$var wire 1 ze mem [1] $end +$var wire 1 |e mem_inv [0] $end +$var wire 1 }e mem_inv [1] $end +$var wire 1 'f out [0] $end + +$scope module scs8hd_muxinv2_1_0 $end +$var wire 1 'f Z $end +$var wire 1 WJ Q1 $end +$var wire 1 aI Q2 $end +$var wire 1 ye S0 $end +$var wire 1 |e S0B $end +$var wire 1 ze S1 $end +$var wire 1 }e S1B $end +$var wire 1 nf Q1__bar $end +$var wire 1 of Q2__bar $end +$upscope $end +$upscope $end + +$scope module BINV_R_161 $end +$var wire 1 ^J Y $end +$var wire 1 +f A $end +$var supply1 1 pf VPWR $end +$var supply0 1 qf VGND $end +$var supply1 1 rf VPB $end +$var supply0 1 sf VNB $end + +$scope module base $end +$var wire 1 ^J Y $end +$var wire 1 +f A $end +$var wire 1 tf not0_out_Y $end +$upscope $end +$upscope $end + +$scope module BINV_R_162 $end +$var wire 1 +f Y $end +$var wire 1 )f A $end +$var supply1 1 uf VPWR $end +$var supply0 1 vf VGND $end +$var supply1 1 wf VPB $end +$var supply0 1 xf VNB $end + +$scope module base $end +$var wire 1 +f Y $end +$var wire 1 )f A $end +$var wire 1 yf not0_out_Y $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mem_top_track_4 $end +$var wire 1 NH pReset [0] $end +$var wire 1 qJ prog_clk [0] $end +$var wire 1 3L ccff_head [0] $end +$var wire 1 "L ccff_tail [0] $end +$var wire 1 hK mem_out [0] $end +$var wire 1 iK mem_out [1] $end +$var wire 1 jK mem_out [2] $end +$var wire 1 kK mem_out [3] $end + +$scope module sky130_fd_sc_hd__dfrtp_1_0_ $end +$var wire 1 hK Q $end +$var wire 1 qJ CLK $end +$var wire 1 3L D $end +$var wire 1 NH RESET_B $end +$var supply1 1 zf VPWR $end +$var supply0 1 {f VGND $end +$var supply1 1 |f VPB $end +$var supply0 1 }f VNB $end + +$scope module base $end +$var wire 1 hK Q $end +$var wire 1 qJ CLK $end +$var wire 1 3L D $end +$var wire 1 NH RESET_B $end +$var wire 1 ~f buf_Q $end +$var wire 1 !g RESET $end +$upscope $end +$upscope $end + +$scope module sky130_fd_sc_hd__dfrtp_1_1_ $end +$var wire 1 iK Q $end +$var wire 1 qJ CLK $end +$var wire 1 hK D $end +$var wire 1 NH RESET_B $end +$var supply1 1 "g VPWR $end +$var supply0 1 #g VGND $end +$var supply1 1 $g VPB $end +$var supply0 1 %g VNB $end + +$scope module base $end +$var wire 1 iK Q $end +$var wire 1 qJ CLK $end +$var wire 1 hK D $end +$var wire 1 NH RESET_B $end +$var wire 1 &g buf_Q $end +$var wire 1 'g RESET $end +$upscope $end +$upscope $end + +$scope module sky130_fd_sc_hd__dfrtp_1_2_ $end +$var wire 1 jK Q $end +$var wire 1 qJ CLK $end +$var wire 1 iK D $end +$var wire 1 NH RESET_B $end +$var supply1 1 (g VPWR $end +$var supply0 1 )g VGND $end +$var supply1 1 *g VPB $end +$var supply0 1 +g VNB $end + +$scope module base $end +$var wire 1 jK Q $end +$var wire 1 qJ CLK $end +$var wire 1 iK D $end +$var wire 1 NH RESET_B $end +$var wire 1 ,g buf_Q $end +$var wire 1 -g RESET $end +$upscope $end +$upscope $end + +$scope module sky130_fd_sc_hd__dfrtp_1_3_ $end +$var wire 1 kK Q $end +$var wire 1 qJ CLK $end +$var wire 1 jK D $end +$var wire 1 NH RESET_B $end +$var supply1 1 .g VPWR $end +$var supply0 1 /g VGND $end +$var supply1 1 0g VPB $end +$var supply0 1 1g VNB $end + +$scope module base $end +$var wire 1 kK Q $end +$var wire 1 qJ CLK $end +$var wire 1 jK D $end +$var wire 1 NH RESET_B $end +$var wire 1 2g buf_Q $end +$var wire 1 3g RESET $end +$upscope $end +$upscope $end + +$scope module FTB_52__51 $end +$var wire 1 "L X $end +$var wire 1 kK A $end +$var supply1 1 4g VPWR $end +$var supply0 1 5g VGND $end +$var supply1 1 6g VPB $end +$var supply0 1 7g VNB $end + +$scope module base $end +$var wire 1 "L X $end +$var wire 1 kK A $end +$var wire 1 8g buf0_out_X $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mem_top_track_10 $end +$var wire 1 NH pReset [0] $end +$var wire 1 qJ prog_clk [0] $end +$var wire 1 5L ccff_head [0] $end +$var wire 1 #L ccff_tail [0] $end +$var wire 1 lK mem_out [0] $end +$var wire 1 mK mem_out [1] $end +$var wire 1 nK mem_out [2] $end +$var wire 1 oK mem_out [3] $end + +$scope module sky130_fd_sc_hd__dfrtp_1_0_ $end +$var wire 1 lK Q $end +$var wire 1 qJ CLK $end +$var wire 1 5L D $end +$var wire 1 NH RESET_B $end +$var supply1 1 9g VPWR $end +$var supply0 1 :g VGND $end +$var supply1 1 ;g VPB $end +$var supply0 1 g RESET $end +$upscope $end +$upscope $end + +$scope module sky130_fd_sc_hd__dfrtp_1_1_ $end +$var wire 1 mK Q $end +$var wire 1 qJ CLK $end +$var wire 1 lK D $end +$var wire 1 NH RESET_B $end +$var supply1 1 ?g VPWR $end +$var supply0 1 @g VGND $end +$var supply1 1 Ag VPB $end +$var supply0 1 Bg VNB $end + +$scope module base $end +$var wire 1 mK Q $end +$var wire 1 qJ CLK $end +$var wire 1 lK D $end +$var wire 1 NH RESET_B $end +$var wire 1 Cg buf_Q $end +$var wire 1 Dg RESET $end +$upscope $end +$upscope $end + +$scope module sky130_fd_sc_hd__dfrtp_1_2_ $end +$var wire 1 nK Q $end +$var wire 1 qJ CLK $end +$var wire 1 mK D $end +$var wire 1 NH RESET_B $end +$var supply1 1 Eg VPWR $end +$var supply0 1 Fg VGND $end +$var supply1 1 Gg VPB $end +$var supply0 1 Hg VNB $end + +$scope module base $end +$var wire 1 nK Q $end +$var wire 1 qJ CLK $end +$var wire 1 mK D $end +$var wire 1 NH RESET_B $end +$var wire 1 Ig buf_Q $end +$var wire 1 Jg RESET $end +$upscope $end +$upscope $end + +$scope module sky130_fd_sc_hd__dfrtp_1_3_ $end +$var wire 1 oK Q $end +$var wire 1 qJ CLK $end +$var wire 1 nK D $end +$var wire 1 NH RESET_B $end +$var supply1 1 Kg VPWR $end +$var supply0 1 Lg VGND $end +$var supply1 1 Mg VPB $end +$var supply0 1 Ng VNB $end + +$scope module base $end +$var wire 1 oK Q $end +$var wire 1 qJ CLK $end +$var wire 1 nK D $end +$var wire 1 NH RESET_B $end +$var wire 1 Og buf_Q $end +$var wire 1 Pg RESET $end +$upscope $end +$upscope $end + +$scope module FTB_53__52 $end +$var wire 1 #L X $end +$var wire 1 oK A $end +$var supply1 1 Qg VPWR $end +$var supply0 1 Rg VGND $end +$var supply1 1 Sg VPB $end +$var supply0 1 Tg VNB $end + +$scope module base $end +$var wire 1 #L X $end +$var wire 1 oK A $end +$var wire 1 Ug buf0_out_X $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mem_right_track_36 $end +$var wire 1 NH pReset [0] $end +$var wire 1 qJ prog_clk [0] $end +$var wire 1 bL ccff_head [0] $end +$var wire 1 $L ccff_tail [0] $end +$var wire 1 pK mem_out [0] $end +$var wire 1 qK mem_out [1] $end +$var wire 1 rK mem_out [2] $end +$var wire 1 sK mem_out [3] $end + +$scope module sky130_fd_sc_hd__dfrtp_1_0_ $end +$var wire 1 pK Q $end +$var wire 1 qJ CLK $end +$var wire 1 bL D $end +$var wire 1 NH RESET_B $end +$var supply1 1 Vg VPWR $end +$var supply0 1 Wg VGND $end +$var supply1 1 Xg VPB $end +$var supply0 1 Yg VNB $end + +$scope module base $end +$var wire 1 pK Q $end +$var wire 1 qJ CLK $end +$var wire 1 bL D $end +$var wire 1 NH RESET_B $end +$var wire 1 Zg buf_Q $end +$var wire 1 [g RESET $end +$upscope $end +$upscope $end + +$scope module sky130_fd_sc_hd__dfrtp_1_1_ $end +$var wire 1 qK Q $end +$var wire 1 qJ CLK $end +$var wire 1 pK D $end +$var wire 1 NH RESET_B $end +$var supply1 1 \g VPWR $end +$var supply0 1 ]g VGND $end +$var supply1 1 ^g VPB $end +$var supply0 1 _g VNB $end + +$scope module base $end +$var wire 1 qK Q $end +$var wire 1 qJ CLK $end +$var wire 1 pK D $end +$var wire 1 NH RESET_B $end +$var wire 1 `g buf_Q $end +$var wire 1 ag RESET $end +$upscope $end +$upscope $end + +$scope module sky130_fd_sc_hd__dfrtp_1_2_ $end +$var wire 1 rK Q $end +$var wire 1 qJ CLK $end +$var wire 1 qK D $end +$var wire 1 NH RESET_B $end +$var supply1 1 bg VPWR $end +$var supply0 1 cg VGND $end +$var supply1 1 dg VPB $end +$var supply0 1 eg VNB $end + +$scope module base $end +$var wire 1 rK Q $end +$var wire 1 qJ CLK $end +$var wire 1 qK D $end +$var wire 1 NH RESET_B $end +$var wire 1 fg buf_Q $end +$var wire 1 gg RESET $end +$upscope $end +$upscope $end + +$scope module sky130_fd_sc_hd__dfrtp_1_3_ $end +$var wire 1 sK Q $end +$var wire 1 qJ CLK $end +$var wire 1 rK D $end +$var wire 1 NH RESET_B $end +$var supply1 1 hg VPWR $end +$var supply0 1 ig VGND $end +$var supply1 1 jg VPB $end +$var supply0 1 kg VNB $end + +$scope module base $end +$var wire 1 sK Q $end +$var wire 1 qJ CLK $end +$var wire 1 rK D $end +$var wire 1 NH RESET_B $end +$var wire 1 lg buf_Q $end +$var wire 1 mg RESET $end +$upscope $end +$upscope $end + +$scope module FTB_54__53 $end +$var wire 1 $L X $end +$var wire 1 sK A $end +$var supply1 1 ng VPWR $end +$var supply0 1 og VGND $end +$var supply1 1 pg VPB $end +$var supply0 1 qg VNB $end + +$scope module base $end +$var wire 1 $L X $end +$var wire 1 sK A $end +$var wire 1 rg buf0_out_X $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mem_left_track_37 $end +$var wire 1 NH pReset [0] $end +$var wire 1 qJ prog_clk [0] $end +$var wire 1 gL ccff_head [0] $end +$var wire 1 %L ccff_tail [0] $end +$var wire 1 tK mem_out [0] $end +$var wire 1 uK mem_out [1] $end +$var wire 1 vK mem_out [2] $end +$var wire 1 wK mem_out [3] $end + +$scope module sky130_fd_sc_hd__dfrtp_1_0_ $end +$var wire 1 tK Q $end +$var wire 1 qJ CLK $end +$var wire 1 gL D $end +$var wire 1 NH RESET_B $end +$var supply1 1 sg VPWR $end +$var supply0 1 tg VGND $end +$var supply1 1 ug VPB $end +$var supply0 1 vg VNB $end + +$scope module base $end +$var wire 1 tK Q $end +$var wire 1 qJ CLK $end +$var wire 1 gL D $end +$var wire 1 NH RESET_B $end +$var wire 1 wg buf_Q $end +$var wire 1 xg RESET $end +$upscope $end +$upscope $end + +$scope module sky130_fd_sc_hd__dfrtp_1_1_ $end +$var wire 1 uK Q $end +$var wire 1 qJ CLK $end +$var wire 1 tK D $end +$var wire 1 NH RESET_B $end +$var supply1 1 yg VPWR $end +$var supply0 1 zg VGND $end +$var supply1 1 {g VPB $end +$var supply0 1 |g VNB $end + +$scope module base $end +$var wire 1 uK Q $end +$var wire 1 qJ CLK $end +$var wire 1 tK D $end +$var wire 1 NH RESET_B $end +$var wire 1 }g buf_Q $end +$var wire 1 ~g RESET $end +$upscope $end +$upscope $end + +$scope module sky130_fd_sc_hd__dfrtp_1_2_ $end +$var wire 1 vK Q $end +$var wire 1 qJ CLK $end +$var wire 1 uK D $end +$var wire 1 NH RESET_B $end +$var supply1 1 !h VPWR $end +$var supply0 1 "h VGND $end +$var supply1 1 #h VPB $end +$var supply0 1 $h VNB $end + +$scope module base $end +$var wire 1 vK Q $end +$var wire 1 qJ CLK $end +$var wire 1 uK D $end +$var wire 1 NH RESET_B $end +$var wire 1 %h buf_Q $end +$var wire 1 &h RESET $end +$upscope $end +$upscope $end + +$scope module sky130_fd_sc_hd__dfrtp_1_3_ $end +$var wire 1 wK Q $end +$var wire 1 qJ CLK $end +$var wire 1 vK D $end +$var wire 1 NH RESET_B $end +$var supply1 1 'h VPWR $end +$var supply0 1 (h VGND $end +$var supply1 1 )h VPB $end +$var supply0 1 *h VNB $end + +$scope module base $end +$var wire 1 wK Q $end +$var wire 1 qJ CLK $end +$var wire 1 vK D $end +$var wire 1 NH RESET_B $end +$var wire 1 +h buf_Q $end +$var wire 1 ,h RESET $end +$upscope $end +$upscope $end + +$scope module FTB_55__54 $end +$var wire 1 %L X $end +$var wire 1 wK A $end +$var supply1 1 -h VPWR $end +$var supply0 1 .h VGND $end +$var supply1 1 /h VPB $end +$var supply0 1 0h VNB $end + +$scope module base $end +$var wire 1 %L X $end +$var wire 1 wK A $end +$var wire 1 1h buf0_out_X $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mem_left_track_45 $end +$var wire 1 NH pReset [0] $end +$var wire 1 qJ prog_clk [0] $end +$var wire 1 %L ccff_head [0] $end +$var wire 1 &L ccff_tail [0] $end +$var wire 1 xK mem_out [0] $end +$var wire 1 yK mem_out [1] $end +$var wire 1 zK mem_out [2] $end +$var wire 1 {K mem_out [3] $end + +$scope module sky130_fd_sc_hd__dfrtp_1_0_ $end +$var wire 1 xK Q $end +$var wire 1 qJ CLK $end +$var wire 1 %L D $end +$var wire 1 NH RESET_B $end +$var supply1 1 2h VPWR $end +$var supply0 1 3h VGND $end +$var supply1 1 4h VPB $end +$var supply0 1 5h VNB $end + +$scope module base $end +$var wire 1 xK Q $end +$var wire 1 qJ CLK $end +$var wire 1 %L D $end +$var wire 1 NH RESET_B $end +$var wire 1 6h buf_Q $end +$var wire 1 7h RESET $end +$upscope $end +$upscope $end + +$scope module sky130_fd_sc_hd__dfrtp_1_1_ $end +$var wire 1 yK Q $end +$var wire 1 qJ CLK $end +$var wire 1 xK D $end +$var wire 1 NH RESET_B $end +$var supply1 1 8h VPWR $end +$var supply0 1 9h VGND $end +$var supply1 1 :h VPB $end +$var supply0 1 ;h VNB $end + +$scope module base $end +$var wire 1 yK Q $end +$var wire 1 qJ CLK $end +$var wire 1 xK D $end +$var wire 1 NH RESET_B $end +$var wire 1 h VPWR $end +$var supply0 1 ?h VGND $end +$var supply1 1 @h VPB $end +$var supply0 1 Ah VNB $end + +$scope module base $end +$var wire 1 zK Q $end +$var wire 1 qJ CLK $end +$var wire 1 yK D $end +$var wire 1 NH RESET_B $end +$var wire 1 Bh buf_Q $end +$var wire 1 Ch RESET $end +$upscope $end +$upscope $end + +$scope module sky130_fd_sc_hd__dfrtp_1_3_ $end +$var wire 1 {K Q $end +$var wire 1 qJ CLK $end +$var wire 1 zK D $end +$var wire 1 NH RESET_B $end +$var supply1 1 Dh VPWR $end +$var supply0 1 Eh VGND $end +$var supply1 1 Fh VPB $end +$var supply0 1 Gh VNB $end + +$scope module base $end +$var wire 1 {K Q $end +$var wire 1 qJ CLK $end +$var wire 1 zK D $end +$var wire 1 NH RESET_B $end +$var wire 1 Hh buf_Q $end +$var wire 1 Ih RESET $end +$upscope $end +$upscope $end + +$scope module FTB_56__55 $end +$var wire 1 &L X $end +$var wire 1 {K A $end +$var supply1 1 Jh VPWR $end +$var supply0 1 Kh VGND $end +$var supply1 1 Lh VPB $end +$var supply0 1 Mh VNB $end + +$scope module base $end +$var wire 1 &L X $end +$var wire 1 {K A $end +$var wire 1 Nh buf0_out_X $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mem_left_track_53 $end +$var wire 1 NH pReset [0] $end +$var wire 1 qJ prog_clk [0] $end +$var wire 1 &L ccff_head [0] $end +$var wire 1 bJ ccff_tail [0] $end +$var wire 1 |K mem_out [0] $end +$var wire 1 }K mem_out [1] $end +$var wire 1 ~K mem_out [2] $end +$var wire 1 !L mem_out [3] $end + +$scope module sky130_fd_sc_hd__dfrtp_1_0_ $end +$var wire 1 |K Q $end +$var wire 1 qJ CLK $end +$var wire 1 &L D $end +$var wire 1 NH RESET_B $end +$var supply1 1 Oh VPWR $end +$var supply0 1 Ph VGND $end +$var supply1 1 Qh VPB $end +$var supply0 1 Rh VNB $end + +$scope module base $end +$var wire 1 |K Q $end +$var wire 1 qJ CLK $end +$var wire 1 &L D $end +$var wire 1 NH RESET_B $end +$var wire 1 Sh buf_Q $end +$var wire 1 Th RESET $end +$upscope $end +$upscope $end + +$scope module sky130_fd_sc_hd__dfrtp_1_1_ $end +$var wire 1 }K Q $end +$var wire 1 qJ CLK $end +$var wire 1 |K D $end +$var wire 1 NH RESET_B $end +$var supply1 1 Uh VPWR $end +$var supply0 1 Vh VGND $end +$var supply1 1 Wh VPB $end +$var supply0 1 Xh VNB $end + +$scope module base $end +$var wire 1 }K Q $end +$var wire 1 qJ CLK $end +$var wire 1 |K D $end +$var wire 1 NH RESET_B $end +$var wire 1 Yh buf_Q $end +$var wire 1 Zh RESET $end +$upscope $end +$upscope $end + +$scope module sky130_fd_sc_hd__dfrtp_1_2_ $end +$var wire 1 ~K Q $end +$var wire 1 qJ CLK $end +$var wire 1 }K D $end +$var wire 1 NH RESET_B $end +$var supply1 1 [h VPWR $end +$var supply0 1 \h VGND $end +$var supply1 1 ]h VPB $end +$var supply0 1 ^h VNB $end + +$scope module base $end +$var wire 1 ~K Q $end +$var wire 1 qJ CLK $end +$var wire 1 }K D $end +$var wire 1 NH RESET_B $end +$var wire 1 _h buf_Q $end +$var wire 1 `h RESET $end +$upscope $end +$upscope $end + +$scope module sky130_fd_sc_hd__dfrtp_1_3_ $end +$var wire 1 !L Q $end +$var wire 1 qJ CLK $end +$var wire 1 ~K D $end +$var wire 1 NH RESET_B $end +$var supply1 1 ah VPWR $end +$var supply0 1 bh VGND $end +$var supply1 1 ch VPB $end +$var supply0 1 dh VNB $end + +$scope module base $end +$var wire 1 !L Q $end +$var wire 1 qJ CLK $end +$var wire 1 ~K D $end +$var wire 1 NH RESET_B $end +$var wire 1 eh buf_Q $end +$var wire 1 fh RESET $end +$upscope $end +$upscope $end + +$scope module FTB_57__56 $end +$var wire 1 bJ X $end +$var wire 1 !L A $end +$var supply1 1 gh VPWR $end +$var supply0 1 hh VGND $end +$var supply1 1 ih VPB $end +$var supply0 1 jh VNB $end + +$scope module base $end +$var wire 1 bJ X $end +$var wire 1 !L A $end +$var wire 1 kh buf0_out_X $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mux_top_track_12 $end +$var wire 1 mH in [0] $end +$var wire 1 QJ in [1] $end +$var wire 1 (I in [2] $end +$var wire 1 3J in [3] $end +$var wire 1 JK sram [0] $end +$var wire 1 KK sram [1] $end +$var wire 1 LK sram [2] $end +$var wire 1 MK sram [3] $end +$var wire 1 zM sram_inv [0] $end +$var wire 1 {M sram_inv [1] $end +$var wire 1 |M sram_inv [2] $end +$var wire 1 }M sram_inv [3] $end +$var wire 1 lI out [0] $end +$var wire 1 aM p0 $end +$var wire 1 lh local_encoder2to3_0_data [0] $end +$var wire 1 mh local_encoder2to3_0_data [1] $end +$var wire 1 nh local_encoder2to3_0_data [2] $end +$var wire 1 oh local_encoder2to3_0_data_inv [0] $end +$var wire 1 ph local_encoder2to3_0_data_inv [1] $end +$var wire 1 qh local_encoder2to3_0_data_inv [2] $end +$var wire 1 rh local_encoder2to3_1_data [0] $end +$var wire 1 sh local_encoder2to3_1_data [1] $end +$var wire 1 th local_encoder2to3_1_data [2] $end +$var wire 1 uh local_encoder2to3_1_data_inv [0] $end +$var wire 1 vh local_encoder2to3_1_data_inv [1] $end +$var wire 1 wh local_encoder2to3_1_data_inv [2] $end +$var wire 1 xh mux_2level_tapbuf_basis_input3_mem3_0_out [0] $end +$var wire 1 yh mux_2level_tapbuf_basis_input3_mem3_1_out [0] $end +$var wire 1 zh SYNOPSYS_UNCONNECTED_1 $end +$var wire 1 {h BUF_net_164 $end + +$scope module local_encoder2to3_0_ $end +$var wire 1 JK addr [0] $end +$var wire 1 KK addr [1] $end +$var wire 1 lh data [0] $end +$var wire 1 mh data [1] $end +$var wire 1 nh data [2] $end +$var wire 1 oh data_inv [0] $end +$var wire 1 ph data_inv [1] $end +$var wire 1 qh data_inv [2] $end + +$scope module U8 $end +$var wire 1 oh Y $end +$var wire 1 lh A $end +$var supply1 1 |h VPWR $end +$var supply0 1 }h VGND $end +$var supply1 1 ~h VPB $end +$var supply0 1 !i VNB $end + +$scope module base $end +$var wire 1 oh Y $end +$var wire 1 lh A $end +$var wire 1 "i not0_out_Y $end +$upscope $end +$upscope $end + +$scope module U9 $end +$var wire 1 mh Y $end +$var wire 1 ph A $end +$var supply1 1 #i VPWR $end +$var supply0 1 $i VGND $end +$var supply1 1 %i VPB $end +$var supply0 1 &i VNB $end + +$scope module base $end +$var wire 1 mh Y $end +$var wire 1 ph A $end +$var wire 1 'i not0_out_Y $end +$upscope $end +$upscope $end + +$scope module U10 $end +$var wire 1 ph Y $end +$var wire 1 JK A $end +$var wire 1 qh B $end +$var supply1 1 (i VPWR $end +$var supply0 1 )i VGND $end +$var supply1 1 *i VPB $end +$var supply0 1 +i VNB $end + +$scope module base $end +$var wire 1 ph Y $end +$var wire 1 JK A $end +$var wire 1 qh B $end +$var wire 1 ,i nand0_out_Y $end +$upscope $end +$upscope $end + +$scope module U11 $end +$var wire 1 qh Y $end +$var wire 1 nh A $end +$var supply1 1 -i VPWR $end +$var supply0 1 .i VGND $end +$var supply1 1 /i VPB $end +$var supply0 1 0i VNB $end + +$scope module base $end +$var wire 1 qh Y $end +$var wire 1 nh A $end +$var wire 1 1i not0_out_Y $end +$upscope $end +$upscope $end + +$scope module U12 $end +$var wire 1 lh Y $end +$var wire 1 nh A $end +$var wire 1 JK B $end +$var supply1 1 2i VPWR $end +$var supply0 1 3i VGND $end +$var supply1 1 4i VPB $end +$var supply0 1 5i VNB $end + +$scope module base $end +$var wire 1 lh Y $end +$var wire 1 nh A $end +$var wire 1 JK B $end +$var wire 1 6i nor0_out_Y $end +$upscope $end +$upscope $end + +$scope module FTB_58__57 $end +$var wire 1 nh X $end +$var wire 1 KK A $end +$var supply1 1 7i VPWR $end +$var supply0 1 8i VGND $end +$var supply1 1 9i VPB $end +$var supply0 1 :i VNB $end + +$scope module base $end +$var wire 1 nh X $end +$var wire 1 KK A $end +$var wire 1 ;i buf0_out_X $end +$upscope $end +$upscope $end +$upscope $end + +$scope module local_encoder2to3_1_ $end +$var wire 1 LK addr [0] $end +$var wire 1 MK addr [1] $end +$var wire 1 rh data [0] $end +$var wire 1 sh data [1] $end +$var wire 1 th data [2] $end +$var wire 1 uh data_inv [0] $end +$var wire 1 vh data_inv [1] $end +$var wire 1 wh data_inv [2] $end + +$scope module U8 $end +$var wire 1 uh Y $end +$var wire 1 rh A $end +$var supply1 1 i VPB $end +$var supply0 1 ?i VNB $end + +$scope module base $end +$var wire 1 uh Y $end +$var wire 1 rh A $end +$var wire 1 @i not0_out_Y $end +$upscope $end +$upscope $end + +$scope module U9 $end +$var wire 1 sh Y $end +$var wire 1 vh A $end +$var supply1 1 Ai VPWR $end +$var supply0 1 Bi VGND $end +$var supply1 1 Ci VPB $end +$var supply0 1 Di VNB $end + +$scope module base $end +$var wire 1 sh Y $end +$var wire 1 vh A $end +$var wire 1 Ei not0_out_Y $end +$upscope $end +$upscope $end + +$scope module U10 $end +$var wire 1 vh Y $end +$var wire 1 LK A $end +$var wire 1 wh B $end +$var supply1 1 Fi VPWR $end +$var supply0 1 Gi VGND $end +$var supply1 1 Hi VPB $end +$var supply0 1 Ii VNB $end + +$scope module base $end +$var wire 1 vh Y $end +$var wire 1 LK A $end +$var wire 1 wh B $end +$var wire 1 Ji nand0_out_Y $end +$upscope $end +$upscope $end + +$scope module U11 $end +$var wire 1 wh Y $end +$var wire 1 th A $end +$var supply1 1 Ki VPWR $end +$var supply0 1 Li VGND $end +$var supply1 1 Mi VPB $end +$var supply0 1 Ni VNB $end + +$scope module base $end +$var wire 1 wh Y $end +$var wire 1 th A $end +$var wire 1 Oi not0_out_Y $end +$upscope $end +$upscope $end + +$scope module U12 $end +$var wire 1 rh Y $end +$var wire 1 th A $end +$var wire 1 LK B $end +$var supply1 1 Pi VPWR $end +$var supply0 1 Qi VGND $end +$var supply1 1 Ri VPB $end +$var supply0 1 Si VNB $end + +$scope module base $end +$var wire 1 rh Y $end +$var wire 1 th A $end +$var wire 1 LK B $end +$var wire 1 Ti nor0_out_Y $end +$upscope $end +$upscope $end + +$scope module FTB_59__58 $end +$var wire 1 th X $end +$var wire 1 MK A $end +$var supply1 1 Ui VPWR $end +$var supply0 1 Vi VGND $end +$var supply1 1 Wi VPB $end +$var supply0 1 Xi VNB $end + +$scope module base $end +$var wire 1 th X $end +$var wire 1 MK A $end +$var wire 1 Yi buf0_out_X $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mux_l1_in_0_ $end +$var wire 1 mH in [0] $end +$var wire 1 QJ in [1] $end +$var wire 1 (I in [2] $end +$var wire 1 lh mem [0] $end +$var wire 1 mh mem [1] $end +$var wire 1 nh mem [2] $end +$var wire 1 oh mem_inv [0] $end +$var wire 1 ph mem_inv [1] $end +$var wire 1 qh mem_inv [2] $end +$var wire 1 xh out [0] $end + +$scope module scs8hd_muxinv3_1_0 $end +$var wire 1 xh Z $end +$var wire 1 mH Q1 $end +$var wire 1 QJ Q2 $end +$var wire 1 (I Q3 $end +$var wire 1 lh S0 $end +$var wire 1 oh S0B $end +$var wire 1 mh S1 $end +$var wire 1 ph S1B $end +$var wire 1 nh S2 $end +$var wire 1 qh S2B $end +$var wire 1 Zi Q1__bar $end +$var wire 1 [i Q2__bar $end +$var wire 1 \i Q3__bar $end +$upscope $end +$upscope $end + +$scope module mux_l2_in_0_ $end +$var wire 1 xh in [0] $end +$var wire 1 3J in [1] $end +$var wire 1 zh in [2] $end +$var wire 1 rh mem [0] $end +$var wire 1 sh mem [1] $end +$var wire 1 th mem [2] $end +$var wire 1 uh mem_inv [0] $end +$var wire 1 vh mem_inv [1] $end +$var wire 1 wh mem_inv [2] $end +$var wire 1 yh out [0] $end +$var wire 1 aM p0 $end + +$scope module scs8hd_muxinv3_1_0 $end +$var wire 1 yh Z $end +$var wire 1 xh Q1 $end +$var wire 1 3J Q2 $end +$var wire 1 aM Q3 $end +$var wire 1 rh S0 $end +$var wire 1 uh S0B $end +$var wire 1 sh S1 $end +$var wire 1 vh S1B $end +$var wire 1 th S2 $end +$var wire 1 wh S2B $end +$var wire 1 ]i Q1__bar $end +$var wire 1 ^i Q2__bar $end +$var wire 1 _i Q3__bar $end +$upscope $end +$upscope $end + +$scope module BINV_R_163 $end +$var wire 1 lI Y $end +$var wire 1 {h A $end +$var supply1 1 `i VPWR $end +$var supply0 1 ai VGND $end +$var supply1 1 bi VPB $end +$var supply0 1 ci VNB $end + +$scope module base $end +$var wire 1 lI Y $end +$var wire 1 {h A $end +$var wire 1 di not0_out_Y $end +$upscope $end +$upscope $end + +$scope module BINV_R_164 $end +$var wire 1 {h Y $end +$var wire 1 yh A $end +$var supply1 1 ei VPWR $end +$var supply0 1 fi VGND $end +$var supply1 1 gi VPB $end +$var supply0 1 hi VNB $end + +$scope module base $end +$var wire 1 {h Y $end +$var wire 1 yh A $end +$var wire 1 ii not0_out_Y $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mux_top_track_14 $end +$var wire 1 yI in [0] $end +$var wire 1 SJ in [1] $end +$var wire 1 ,I in [2] $end +$var wire 1 5J in [3] $end +$var wire 1 NK sram [0] $end +$var wire 1 OK sram [1] $end +$var wire 1 PK sram [2] $end +$var wire 1 QK sram [3] $end +$var wire 1 ~M sram_inv [0] $end +$var wire 1 !N sram_inv [1] $end +$var wire 1 "N sram_inv [2] $end +$var wire 1 #N sram_inv [3] $end +$var wire 1 mI out [0] $end +$var wire 1 aM p0 $end +$var wire 1 ji local_encoder2to3_0_data [0] $end +$var wire 1 ki local_encoder2to3_0_data [1] $end +$var wire 1 li local_encoder2to3_0_data [2] $end +$var wire 1 mi local_encoder2to3_0_data_inv [0] $end +$var wire 1 ni local_encoder2to3_0_data_inv [1] $end +$var wire 1 oi local_encoder2to3_0_data_inv [2] $end +$var wire 1 pi local_encoder2to3_1_data [0] $end +$var wire 1 qi local_encoder2to3_1_data [1] $end +$var wire 1 ri local_encoder2to3_1_data [2] $end +$var wire 1 si local_encoder2to3_1_data_inv [0] $end +$var wire 1 ti local_encoder2to3_1_data_inv [1] $end +$var wire 1 ui local_encoder2to3_1_data_inv [2] $end +$var wire 1 vi mux_2level_tapbuf_basis_input3_mem3_0_out [0] $end +$var wire 1 wi mux_2level_tapbuf_basis_input3_mem3_1_out [0] $end +$var wire 1 xi SYNOPSYS_UNCONNECTED_1 $end +$var wire 1 yi BUF_net_166 $end + +$scope module local_encoder2to3_0_ $end +$var wire 1 NK addr [0] $end +$var wire 1 OK addr [1] $end +$var wire 1 ji data [0] $end +$var wire 1 ki data [1] $end +$var wire 1 li data [2] $end +$var wire 1 mi data_inv [0] $end +$var wire 1 ni data_inv [1] $end +$var wire 1 oi data_inv [2] $end + +$scope module U8 $end +$var wire 1 mi Y $end +$var wire 1 ji A $end +$var supply1 1 zi VPWR $end +$var supply0 1 {i VGND $end +$var supply1 1 |i VPB $end +$var supply0 1 }i VNB $end + +$scope module base $end +$var wire 1 mi Y $end +$var wire 1 ji A $end +$var wire 1 ~i not0_out_Y $end +$upscope $end +$upscope $end + +$scope module U9 $end +$var wire 1 ki Y $end +$var wire 1 ni A $end +$var supply1 1 !j VPWR $end +$var supply0 1 "j VGND $end +$var supply1 1 #j VPB $end +$var supply0 1 $j VNB $end + +$scope module base $end +$var wire 1 ki Y $end +$var wire 1 ni A $end +$var wire 1 %j not0_out_Y $end +$upscope $end +$upscope $end + +$scope module U10 $end +$var wire 1 ni Y $end +$var wire 1 NK A $end +$var wire 1 oi B $end +$var supply1 1 &j VPWR $end +$var supply0 1 'j VGND $end +$var supply1 1 (j VPB $end +$var supply0 1 )j VNB $end + +$scope module base $end +$var wire 1 ni Y $end +$var wire 1 NK A $end +$var wire 1 oi B $end +$var wire 1 *j nand0_out_Y $end +$upscope $end +$upscope $end + +$scope module U11 $end +$var wire 1 oi Y $end +$var wire 1 li A $end +$var supply1 1 +j VPWR $end +$var supply0 1 ,j VGND $end +$var supply1 1 -j VPB $end +$var supply0 1 .j VNB $end + +$scope module base $end +$var wire 1 oi Y $end +$var wire 1 li A $end +$var wire 1 /j not0_out_Y $end +$upscope $end +$upscope $end + +$scope module U12 $end +$var wire 1 ji Y $end +$var wire 1 li A $end +$var wire 1 NK B $end +$var supply1 1 0j VPWR $end +$var supply0 1 1j VGND $end +$var supply1 1 2j VPB $end +$var supply0 1 3j VNB $end + +$scope module base $end +$var wire 1 ji Y $end +$var wire 1 li A $end +$var wire 1 NK B $end +$var wire 1 4j nor0_out_Y $end +$upscope $end +$upscope $end + +$scope module FTB_60__59 $end +$var wire 1 li X $end +$var wire 1 OK A $end +$var supply1 1 5j VPWR $end +$var supply0 1 6j VGND $end +$var supply1 1 7j VPB $end +$var supply0 1 8j VNB $end + +$scope module base $end +$var wire 1 li X $end +$var wire 1 OK A $end +$var wire 1 9j buf0_out_X $end +$upscope $end +$upscope $end +$upscope $end + +$scope module local_encoder2to3_1_ $end +$var wire 1 PK addr [0] $end +$var wire 1 QK addr [1] $end +$var wire 1 pi data [0] $end +$var wire 1 qi data [1] $end +$var wire 1 ri data [2] $end +$var wire 1 si data_inv [0] $end +$var wire 1 ti data_inv [1] $end +$var wire 1 ui data_inv [2] $end + +$scope module U8 $end +$var wire 1 si Y $end +$var wire 1 pi A $end +$var supply1 1 :j VPWR $end +$var supply0 1 ;j VGND $end +$var supply1 1 j not0_out_Y $end +$upscope $end +$upscope $end + +$scope module U9 $end +$var wire 1 qi Y $end +$var wire 1 ti A $end +$var supply1 1 ?j VPWR $end +$var supply0 1 @j VGND $end +$var supply1 1 Aj VPB $end +$var supply0 1 Bj VNB $end + +$scope module base $end +$var wire 1 qi Y $end +$var wire 1 ti A $end +$var wire 1 Cj not0_out_Y $end +$upscope $end +$upscope $end + +$scope module U10 $end +$var wire 1 ti Y $end +$var wire 1 PK A $end +$var wire 1 ui B $end +$var supply1 1 Dj VPWR $end +$var supply0 1 Ej VGND $end +$var supply1 1 Fj VPB $end +$var supply0 1 Gj VNB $end + +$scope module base $end +$var wire 1 ti Y $end +$var wire 1 PK A $end +$var wire 1 ui B $end +$var wire 1 Hj nand0_out_Y $end +$upscope $end +$upscope $end + +$scope module U11 $end +$var wire 1 ui Y $end +$var wire 1 ri A $end +$var supply1 1 Ij VPWR $end +$var supply0 1 Jj VGND $end +$var supply1 1 Kj VPB $end +$var supply0 1 Lj VNB $end + +$scope module base $end +$var wire 1 ui Y $end +$var wire 1 ri A $end +$var wire 1 Mj not0_out_Y $end +$upscope $end +$upscope $end + +$scope module U12 $end +$var wire 1 pi Y $end +$var wire 1 ri A $end +$var wire 1 PK B $end +$var supply1 1 Nj VPWR $end +$var supply0 1 Oj VGND $end +$var supply1 1 Pj VPB $end +$var supply0 1 Qj VNB $end + +$scope module base $end +$var wire 1 pi Y $end +$var wire 1 ri A $end +$var wire 1 PK B $end +$var wire 1 Rj nor0_out_Y $end +$upscope $end +$upscope $end + +$scope module FTB_61__60 $end +$var wire 1 ri X $end +$var wire 1 QK A $end +$var supply1 1 Sj VPWR $end +$var supply0 1 Tj VGND $end +$var supply1 1 Uj VPB $end +$var supply0 1 Vj VNB $end + +$scope module base $end +$var wire 1 ri X $end +$var wire 1 QK A $end +$var wire 1 Wj buf0_out_X $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mux_l1_in_0_ $end +$var wire 1 yI in [0] $end +$var wire 1 SJ in [1] $end +$var wire 1 ,I in [2] $end +$var wire 1 ji mem [0] $end +$var wire 1 ki mem [1] $end +$var wire 1 li mem [2] $end +$var wire 1 mi mem_inv [0] $end +$var wire 1 ni mem_inv [1] $end +$var wire 1 oi mem_inv [2] $end +$var wire 1 vi out [0] $end + +$scope module scs8hd_muxinv3_1_0 $end +$var wire 1 vi Z $end +$var wire 1 yI Q1 $end +$var wire 1 SJ Q2 $end +$var wire 1 ,I Q3 $end +$var wire 1 ji S0 $end +$var wire 1 mi S0B $end +$var wire 1 ki S1 $end +$var wire 1 ni S1B $end +$var wire 1 li S2 $end +$var wire 1 oi S2B $end +$var wire 1 Xj Q1__bar $end +$var wire 1 Yj Q2__bar $end +$var wire 1 Zj Q3__bar $end +$upscope $end +$upscope $end + +$scope module mux_l2_in_0_ $end +$var wire 1 vi in [0] $end +$var wire 1 5J in [1] $end +$var wire 1 xi in [2] $end +$var wire 1 pi mem [0] $end +$var wire 1 qi mem [1] $end +$var wire 1 ri mem [2] $end +$var wire 1 si mem_inv [0] $end +$var wire 1 ti mem_inv [1] $end +$var wire 1 ui mem_inv [2] $end +$var wire 1 wi out [0] $end +$var wire 1 aM p0 $end + +$scope module scs8hd_muxinv3_1_0 $end +$var wire 1 wi Z $end +$var wire 1 vi Q1 $end +$var wire 1 5J Q2 $end +$var wire 1 aM Q3 $end +$var wire 1 pi S0 $end +$var wire 1 si S0B $end +$var wire 1 qi S1 $end +$var wire 1 ti S1B $end +$var wire 1 ri S2 $end +$var wire 1 ui S2B $end +$var wire 1 [j Q1__bar $end +$var wire 1 \j Q2__bar $end +$var wire 1 ]j Q3__bar $end +$upscope $end +$upscope $end + +$scope module BINV_R_165 $end +$var wire 1 mI Y $end +$var wire 1 yi A $end +$var supply1 1 ^j VPWR $end +$var supply0 1 _j VGND $end +$var supply1 1 `j VPB $end +$var supply0 1 aj VNB $end + +$scope module base $end +$var wire 1 mI Y $end +$var wire 1 yi A $end +$var wire 1 bj not0_out_Y $end +$upscope $end +$upscope $end + +$scope module BINV_R_166 $end +$var wire 1 yi Y $end +$var wire 1 wi A $end +$var supply1 1 cj VPWR $end +$var supply0 1 dj VGND $end +$var supply1 1 ej VPB $end +$var supply0 1 fj VNB $end + +$scope module base $end +$var wire 1 yi Y $end +$var wire 1 wi A $end +$var wire 1 gj not0_out_Y $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mux_top_track_16 $end +$var wire 1 oH in [0] $end +$var wire 1 TJ in [1] $end +$var wire 1 0I in [2] $end +$var wire 1 6J in [3] $end +$var wire 1 RK sram [0] $end +$var wire 1 SK sram [1] $end +$var wire 1 TK sram [2] $end +$var wire 1 UK sram [3] $end +$var wire 1 $N sram_inv [0] $end +$var wire 1 %N sram_inv [1] $end +$var wire 1 &N sram_inv [2] $end +$var wire 1 'N sram_inv [3] $end +$var wire 1 nI out [0] $end +$var wire 1 aM p0 $end +$var wire 1 hj local_encoder2to3_0_data [0] $end +$var wire 1 ij local_encoder2to3_0_data [1] $end +$var wire 1 jj local_encoder2to3_0_data [2] $end +$var wire 1 kj local_encoder2to3_0_data_inv [0] $end +$var wire 1 lj local_encoder2to3_0_data_inv [1] $end +$var wire 1 mj local_encoder2to3_0_data_inv [2] $end +$var wire 1 nj local_encoder2to3_1_data [0] $end +$var wire 1 oj local_encoder2to3_1_data [1] $end +$var wire 1 pj local_encoder2to3_1_data [2] $end +$var wire 1 qj local_encoder2to3_1_data_inv [0] $end +$var wire 1 rj local_encoder2to3_1_data_inv [1] $end +$var wire 1 sj local_encoder2to3_1_data_inv [2] $end +$var wire 1 tj mux_2level_tapbuf_basis_input3_mem3_0_out [0] $end +$var wire 1 uj mux_2level_tapbuf_basis_input3_mem3_1_out [0] $end +$var wire 1 vj SYNOPSYS_UNCONNECTED_1 $end +$var wire 1 wj BUF_net_168 $end + +$scope module local_encoder2to3_0_ $end +$var wire 1 RK addr [0] $end +$var wire 1 SK addr [1] $end +$var wire 1 hj data [0] $end +$var wire 1 ij data [1] $end +$var wire 1 jj data [2] $end +$var wire 1 kj data_inv [0] $end +$var wire 1 lj data_inv [1] $end +$var wire 1 mj data_inv [2] $end + +$scope module U8 $end +$var wire 1 kj Y $end +$var wire 1 hj A $end +$var supply1 1 xj VPWR $end +$var supply0 1 yj VGND $end +$var supply1 1 zj VPB $end +$var supply0 1 {j VNB $end + +$scope module base $end +$var wire 1 kj Y $end +$var wire 1 hj A $end +$var wire 1 |j not0_out_Y $end +$upscope $end +$upscope $end + +$scope module U9 $end +$var wire 1 ij Y $end +$var wire 1 lj A $end +$var supply1 1 }j VPWR $end +$var supply0 1 ~j VGND $end +$var supply1 1 !k VPB $end +$var supply0 1 "k VNB $end + +$scope module base $end +$var wire 1 ij Y $end +$var wire 1 lj A $end +$var wire 1 #k not0_out_Y $end +$upscope $end +$upscope $end + +$scope module U10 $end +$var wire 1 lj Y $end +$var wire 1 RK A $end +$var wire 1 mj B $end +$var supply1 1 $k VPWR $end +$var supply0 1 %k VGND $end +$var supply1 1 &k VPB $end +$var supply0 1 'k VNB $end + +$scope module base $end +$var wire 1 lj Y $end +$var wire 1 RK A $end +$var wire 1 mj B $end +$var wire 1 (k nand0_out_Y $end +$upscope $end +$upscope $end + +$scope module U11 $end +$var wire 1 mj Y $end +$var wire 1 jj A $end +$var supply1 1 )k VPWR $end +$var supply0 1 *k VGND $end +$var supply1 1 +k VPB $end +$var supply0 1 ,k VNB $end + +$scope module base $end +$var wire 1 mj Y $end +$var wire 1 jj A $end +$var wire 1 -k not0_out_Y $end +$upscope $end +$upscope $end + +$scope module U12 $end +$var wire 1 hj Y $end +$var wire 1 jj A $end +$var wire 1 RK B $end +$var supply1 1 .k VPWR $end +$var supply0 1 /k VGND $end +$var supply1 1 0k VPB $end +$var supply0 1 1k VNB $end + +$scope module base $end +$var wire 1 hj Y $end +$var wire 1 jj A $end +$var wire 1 RK B $end +$var wire 1 2k nor0_out_Y $end +$upscope $end +$upscope $end + +$scope module FTB_62__61 $end +$var wire 1 jj X $end +$var wire 1 SK A $end +$var supply1 1 3k VPWR $end +$var supply0 1 4k VGND $end +$var supply1 1 5k VPB $end +$var supply0 1 6k VNB $end + +$scope module base $end +$var wire 1 jj X $end +$var wire 1 SK A $end +$var wire 1 7k buf0_out_X $end +$upscope $end +$upscope $end +$upscope $end + +$scope module local_encoder2to3_1_ $end +$var wire 1 TK addr [0] $end +$var wire 1 UK addr [1] $end +$var wire 1 nj data [0] $end +$var wire 1 oj data [1] $end +$var wire 1 pj data [2] $end +$var wire 1 qj data_inv [0] $end +$var wire 1 rj data_inv [1] $end +$var wire 1 sj data_inv [2] $end + +$scope module U8 $end +$var wire 1 qj Y $end +$var wire 1 nj A $end +$var supply1 1 8k VPWR $end +$var supply0 1 9k VGND $end +$var supply1 1 :k VPB $end +$var supply0 1 ;k VNB $end + +$scope module base $end +$var wire 1 qj Y $end +$var wire 1 nj A $end +$var wire 1 k VGND $end +$var supply1 1 ?k VPB $end +$var supply0 1 @k VNB $end + +$scope module base $end +$var wire 1 oj Y $end +$var wire 1 rj A $end +$var wire 1 Ak not0_out_Y $end +$upscope $end +$upscope $end + +$scope module U10 $end +$var wire 1 rj Y $end +$var wire 1 TK A $end +$var wire 1 sj B $end +$var supply1 1 Bk VPWR $end +$var supply0 1 Ck VGND $end +$var supply1 1 Dk VPB $end +$var supply0 1 Ek VNB $end + +$scope module base $end +$var wire 1 rj Y $end +$var wire 1 TK A $end +$var wire 1 sj B $end +$var wire 1 Fk nand0_out_Y $end +$upscope $end +$upscope $end + +$scope module U11 $end +$var wire 1 sj Y $end +$var wire 1 pj A $end +$var supply1 1 Gk VPWR $end +$var supply0 1 Hk VGND $end +$var supply1 1 Ik VPB $end +$var supply0 1 Jk VNB $end + +$scope module base $end +$var wire 1 sj Y $end +$var wire 1 pj A $end +$var wire 1 Kk not0_out_Y $end +$upscope $end +$upscope $end + +$scope module U12 $end +$var wire 1 nj Y $end +$var wire 1 pj A $end +$var wire 1 TK B $end +$var supply1 1 Lk VPWR $end +$var supply0 1 Mk VGND $end +$var supply1 1 Nk VPB $end +$var supply0 1 Ok VNB $end + +$scope module base $end +$var wire 1 nj Y $end +$var wire 1 pj A $end +$var wire 1 TK B $end +$var wire 1 Pk nor0_out_Y $end +$upscope $end +$upscope $end + +$scope module FTB_63__62 $end +$var wire 1 pj X $end +$var wire 1 UK A $end +$var supply1 1 Qk VPWR $end +$var supply0 1 Rk VGND $end +$var supply1 1 Sk VPB $end +$var supply0 1 Tk VNB $end + +$scope module base $end +$var wire 1 pj X $end +$var wire 1 UK A $end +$var wire 1 Uk buf0_out_X $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mux_l1_in_0_ $end +$var wire 1 oH in [0] $end +$var wire 1 TJ in [1] $end +$var wire 1 0I in [2] $end +$var wire 1 hj mem [0] $end +$var wire 1 ij mem [1] $end +$var wire 1 jj mem [2] $end +$var wire 1 kj mem_inv [0] $end +$var wire 1 lj mem_inv [1] $end +$var wire 1 mj mem_inv [2] $end +$var wire 1 tj out [0] $end + +$scope module scs8hd_muxinv3_1_0 $end +$var wire 1 tj Z $end +$var wire 1 oH Q1 $end +$var wire 1 TJ Q2 $end +$var wire 1 0I Q3 $end +$var wire 1 hj S0 $end +$var wire 1 kj S0B $end +$var wire 1 ij S1 $end +$var wire 1 lj S1B $end +$var wire 1 jj S2 $end +$var wire 1 mj S2B $end +$var wire 1 Vk Q1__bar $end +$var wire 1 Wk Q2__bar $end +$var wire 1 Xk Q3__bar $end +$upscope $end +$upscope $end + +$scope module mux_l2_in_0_ $end +$var wire 1 tj in [0] $end +$var wire 1 6J in [1] $end +$var wire 1 vj in [2] $end +$var wire 1 nj mem [0] $end +$var wire 1 oj mem [1] $end +$var wire 1 pj mem [2] $end +$var wire 1 qj mem_inv [0] $end +$var wire 1 rj mem_inv [1] $end +$var wire 1 sj mem_inv [2] $end +$var wire 1 uj out [0] $end +$var wire 1 aM p0 $end + +$scope module scs8hd_muxinv3_1_0 $end +$var wire 1 uj Z $end +$var wire 1 tj Q1 $end +$var wire 1 6J Q2 $end +$var wire 1 aM Q3 $end +$var wire 1 nj S0 $end +$var wire 1 qj S0B $end +$var wire 1 oj S1 $end +$var wire 1 rj S1B $end +$var wire 1 pj S2 $end +$var wire 1 sj S2B $end +$var wire 1 Yk Q1__bar $end +$var wire 1 Zk Q2__bar $end +$var wire 1 [k Q3__bar $end +$upscope $end +$upscope $end + +$scope module BINV_R_167 $end +$var wire 1 nI Y $end +$var wire 1 wj A $end +$var supply1 1 \k VPWR $end +$var supply0 1 ]k VGND $end +$var supply1 1 ^k VPB $end +$var supply0 1 _k VNB $end + +$scope module base $end +$var wire 1 nI Y $end +$var wire 1 wj A $end +$var wire 1 `k not0_out_Y $end +$upscope $end +$upscope $end + +$scope module BINV_R_168 $end +$var wire 1 wj Y $end +$var wire 1 uj A $end +$var supply1 1 ak VPWR $end +$var supply0 1 bk VGND $end +$var supply1 1 ck VPB $end +$var supply0 1 dk VNB $end + +$scope module base $end +$var wire 1 wj Y $end +$var wire 1 uj A $end +$var wire 1 ek not0_out_Y $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mux_top_track_18 $end +$var wire 1 pH in [0] $end +$var wire 1 UJ in [1] $end +$var wire 1 4I in [2] $end +$var wire 1 7J in [3] $end +$var wire 1 VK sram [0] $end +$var wire 1 WK sram [1] $end +$var wire 1 XK sram [2] $end +$var wire 1 YK sram [3] $end +$var wire 1 (N sram_inv [0] $end +$var wire 1 )N sram_inv [1] $end +$var wire 1 *N sram_inv [2] $end +$var wire 1 +N sram_inv [3] $end +$var wire 1 oI out [0] $end +$var wire 1 aM p0 $end +$var wire 1 fk local_encoder2to3_0_data [0] $end +$var wire 1 gk local_encoder2to3_0_data [1] $end +$var wire 1 hk local_encoder2to3_0_data [2] $end +$var wire 1 ik local_encoder2to3_0_data_inv [0] $end +$var wire 1 jk local_encoder2to3_0_data_inv [1] $end +$var wire 1 kk local_encoder2to3_0_data_inv [2] $end +$var wire 1 lk local_encoder2to3_1_data [0] $end +$var wire 1 mk local_encoder2to3_1_data [1] $end +$var wire 1 nk local_encoder2to3_1_data [2] $end +$var wire 1 ok local_encoder2to3_1_data_inv [0] $end +$var wire 1 pk local_encoder2to3_1_data_inv [1] $end +$var wire 1 qk local_encoder2to3_1_data_inv [2] $end +$var wire 1 rk mux_2level_tapbuf_basis_input3_mem3_0_out [0] $end +$var wire 1 sk mux_2level_tapbuf_basis_input3_mem3_1_out [0] $end +$var wire 1 tk SYNOPSYS_UNCONNECTED_1 $end +$var wire 1 uk BUF_net_170 $end + +$scope module local_encoder2to3_0_ $end +$var wire 1 VK addr [0] $end +$var wire 1 WK addr [1] $end +$var wire 1 fk data [0] $end +$var wire 1 gk data [1] $end +$var wire 1 hk data [2] $end +$var wire 1 ik data_inv [0] $end +$var wire 1 jk data_inv [1] $end +$var wire 1 kk data_inv [2] $end + +$scope module U8 $end +$var wire 1 ik Y $end +$var wire 1 fk A $end +$var supply1 1 vk VPWR $end +$var supply0 1 wk VGND $end +$var supply1 1 xk VPB $end +$var supply0 1 yk VNB $end + +$scope module base $end +$var wire 1 ik Y $end +$var wire 1 fk A $end +$var wire 1 zk not0_out_Y $end +$upscope $end +$upscope $end + +$scope module U9 $end +$var wire 1 gk Y $end +$var wire 1 jk A $end +$var supply1 1 {k VPWR $end +$var supply0 1 |k VGND $end +$var supply1 1 }k VPB $end +$var supply0 1 ~k VNB $end + +$scope module base $end +$var wire 1 gk Y $end +$var wire 1 jk A $end +$var wire 1 !l not0_out_Y $end +$upscope $end +$upscope $end + +$scope module U10 $end +$var wire 1 jk Y $end +$var wire 1 VK A $end +$var wire 1 kk B $end +$var supply1 1 "l VPWR $end +$var supply0 1 #l VGND $end +$var supply1 1 $l VPB $end +$var supply0 1 %l VNB $end + +$scope module base $end +$var wire 1 jk Y $end +$var wire 1 VK A $end +$var wire 1 kk B $end +$var wire 1 &l nand0_out_Y $end +$upscope $end +$upscope $end + +$scope module U11 $end +$var wire 1 kk Y $end +$var wire 1 hk A $end +$var supply1 1 'l VPWR $end +$var supply0 1 (l VGND $end +$var supply1 1 )l VPB $end +$var supply0 1 *l VNB $end + +$scope module base $end +$var wire 1 kk Y $end +$var wire 1 hk A $end +$var wire 1 +l not0_out_Y $end +$upscope $end +$upscope $end + +$scope module U12 $end +$var wire 1 fk Y $end +$var wire 1 hk A $end +$var wire 1 VK B $end +$var supply1 1 ,l VPWR $end +$var supply0 1 -l VGND $end +$var supply1 1 .l VPB $end +$var supply0 1 /l VNB $end + +$scope module base $end +$var wire 1 fk Y $end +$var wire 1 hk A $end +$var wire 1 VK B $end +$var wire 1 0l nor0_out_Y $end +$upscope $end +$upscope $end + +$scope module FTB_64__63 $end +$var wire 1 hk X $end +$var wire 1 WK A $end +$var supply1 1 1l VPWR $end +$var supply0 1 2l VGND $end +$var supply1 1 3l VPB $end +$var supply0 1 4l VNB $end + +$scope module base $end +$var wire 1 hk X $end +$var wire 1 WK A $end +$var wire 1 5l buf0_out_X $end +$upscope $end +$upscope $end +$upscope $end + +$scope module local_encoder2to3_1_ $end +$var wire 1 XK addr [0] $end +$var wire 1 YK addr [1] $end +$var wire 1 lk data [0] $end +$var wire 1 mk data [1] $end +$var wire 1 nk data [2] $end +$var wire 1 ok data_inv [0] $end +$var wire 1 pk data_inv [1] $end +$var wire 1 qk data_inv [2] $end + +$scope module U8 $end +$var wire 1 ok Y $end +$var wire 1 lk A $end +$var supply1 1 6l VPWR $end +$var supply0 1 7l VGND $end +$var supply1 1 8l VPB $end +$var supply0 1 9l VNB $end + +$scope module base $end +$var wire 1 ok Y $end +$var wire 1 lk A $end +$var wire 1 :l not0_out_Y $end +$upscope $end +$upscope $end + +$scope module U9 $end +$var wire 1 mk Y $end +$var wire 1 pk A $end +$var supply1 1 ;l VPWR $end +$var supply0 1 l VNB $end + +$scope module base $end +$var wire 1 mk Y $end +$var wire 1 pk A $end +$var wire 1 ?l not0_out_Y $end +$upscope $end +$upscope $end + +$scope module U10 $end +$var wire 1 pk Y $end +$var wire 1 XK A $end +$var wire 1 qk B $end +$var supply1 1 @l VPWR $end +$var supply0 1 Al VGND $end +$var supply1 1 Bl VPB $end +$var supply0 1 Cl VNB $end + +$scope module base $end +$var wire 1 pk Y $end +$var wire 1 XK A $end +$var wire 1 qk B $end +$var wire 1 Dl nand0_out_Y $end +$upscope $end +$upscope $end + +$scope module U11 $end +$var wire 1 qk Y $end +$var wire 1 nk A $end +$var supply1 1 El VPWR $end +$var supply0 1 Fl VGND $end +$var supply1 1 Gl VPB $end +$var supply0 1 Hl VNB $end + +$scope module base $end +$var wire 1 qk Y $end +$var wire 1 nk A $end +$var wire 1 Il not0_out_Y $end +$upscope $end +$upscope $end + +$scope module U12 $end +$var wire 1 lk Y $end +$var wire 1 nk A $end +$var wire 1 XK B $end +$var supply1 1 Jl VPWR $end +$var supply0 1 Kl VGND $end +$var supply1 1 Ll VPB $end +$var supply0 1 Ml VNB $end + +$scope module base $end +$var wire 1 lk Y $end +$var wire 1 nk A $end +$var wire 1 XK B $end +$var wire 1 Nl nor0_out_Y $end +$upscope $end +$upscope $end + +$scope module FTB_65__64 $end +$var wire 1 nk X $end +$var wire 1 YK A $end +$var supply1 1 Ol VPWR $end +$var supply0 1 Pl VGND $end +$var supply1 1 Ql VPB $end +$var supply0 1 Rl VNB $end + +$scope module base $end +$var wire 1 nk X $end +$var wire 1 YK A $end +$var wire 1 Sl buf0_out_X $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mux_l1_in_0_ $end +$var wire 1 pH in [0] $end +$var wire 1 UJ in [1] $end +$var wire 1 4I in [2] $end +$var wire 1 fk mem [0] $end +$var wire 1 gk mem [1] $end +$var wire 1 hk mem [2] $end +$var wire 1 ik mem_inv [0] $end +$var wire 1 jk mem_inv [1] $end +$var wire 1 kk mem_inv [2] $end +$var wire 1 rk out [0] $end + +$scope module scs8hd_muxinv3_1_0 $end +$var wire 1 rk Z $end +$var wire 1 pH Q1 $end +$var wire 1 UJ Q2 $end +$var wire 1 4I Q3 $end +$var wire 1 fk S0 $end +$var wire 1 ik S0B $end +$var wire 1 gk S1 $end +$var wire 1 jk S1B $end +$var wire 1 hk S2 $end +$var wire 1 kk S2B $end +$var wire 1 Tl Q1__bar $end +$var wire 1 Ul Q2__bar $end +$var wire 1 Vl Q3__bar $end +$upscope $end +$upscope $end + +$scope module mux_l2_in_0_ $end +$var wire 1 rk in [0] $end +$var wire 1 7J in [1] $end +$var wire 1 tk in [2] $end +$var wire 1 lk mem [0] $end +$var wire 1 mk mem [1] $end +$var wire 1 nk mem [2] $end +$var wire 1 ok mem_inv [0] $end +$var wire 1 pk mem_inv [1] $end +$var wire 1 qk mem_inv [2] $end +$var wire 1 sk out [0] $end +$var wire 1 aM p0 $end + +$scope module scs8hd_muxinv3_1_0 $end +$var wire 1 sk Z $end +$var wire 1 rk Q1 $end +$var wire 1 7J Q2 $end +$var wire 1 aM Q3 $end +$var wire 1 lk S0 $end +$var wire 1 ok S0B $end +$var wire 1 mk S1 $end +$var wire 1 pk S1B $end +$var wire 1 nk S2 $end +$var wire 1 qk S2B $end +$var wire 1 Wl Q1__bar $end +$var wire 1 Xl Q2__bar $end +$var wire 1 Yl Q3__bar $end +$upscope $end +$upscope $end + +$scope module BINV_R_169 $end +$var wire 1 oI Y $end +$var wire 1 uk A $end +$var supply1 1 Zl VPWR $end +$var supply0 1 [l VGND $end +$var supply1 1 \l VPB $end +$var supply0 1 ]l VNB $end + +$scope module base $end +$var wire 1 oI Y $end +$var wire 1 uk A $end +$var wire 1 ^l not0_out_Y $end +$upscope $end +$upscope $end + +$scope module BINV_R_170 $end +$var wire 1 uk Y $end +$var wire 1 sk A $end +$var supply1 1 _l VPWR $end +$var supply0 1 `l VGND $end +$var supply1 1 al VPB $end +$var supply0 1 bl VNB $end + +$scope module base $end +$var wire 1 uk Y $end +$var wire 1 sk A $end +$var wire 1 cl not0_out_Y $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mux_right_track_44 $end +$var wire 1 WH in [0] $end +$var wire 1 bH in [1] $end +$var wire 1 9I in [2] $end +$var wire 1 7J in [3] $end +$var wire 1 ZK sram [0] $end +$var wire 1 [K sram [1] $end +$var wire 1 \K sram [2] $end +$var wire 1 ]K sram [3] $end +$var wire 1 ,N sram_inv [0] $end +$var wire 1 -N sram_inv [1] $end +$var wire 1 .N sram_inv [2] $end +$var wire 1 /N sram_inv [3] $end +$var wire 1 m VGND $end +$var supply1 1 ?m VPB $end +$var supply0 1 @m VNB $end + +$scope module base $end +$var wire 1 nl Y $end +$var wire 1 \K A $end +$var wire 1 ol B $end +$var wire 1 Am nand0_out_Y $end +$upscope $end +$upscope $end + +$scope module U11 $end +$var wire 1 ol Y $end +$var wire 1 ll A $end +$var supply1 1 Bm VPWR $end +$var supply0 1 Cm VGND $end +$var supply1 1 Dm VPB $end +$var supply0 1 Em VNB $end + +$scope module base $end +$var wire 1 ol Y $end +$var wire 1 ll A $end +$var wire 1 Fm not0_out_Y $end +$upscope $end +$upscope $end + +$scope module U12 $end +$var wire 1 jl Y $end +$var wire 1 ll A $end +$var wire 1 \K B $end +$var supply1 1 Gm VPWR $end +$var supply0 1 Hm VGND $end +$var supply1 1 Im VPB $end +$var supply0 1 Jm VNB $end + +$scope module base $end +$var wire 1 jl Y $end +$var wire 1 ll A $end +$var wire 1 \K B $end +$var wire 1 Km nor0_out_Y $end +$upscope $end +$upscope $end + +$scope module FTB_67__66 $end +$var wire 1 ll X $end +$var wire 1 ]K A $end +$var supply1 1 Lm VPWR $end +$var supply0 1 Mm VGND $end +$var supply1 1 Nm VPB $end +$var supply0 1 Om VNB $end + +$scope module base $end +$var wire 1 ll X $end +$var wire 1 ]K A $end +$var wire 1 Pm buf0_out_X $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mux_l1_in_0_ $end +$var wire 1 WH in [0] $end +$var wire 1 bH in [1] $end +$var wire 1 9I in [2] $end +$var wire 1 dl mem [0] $end +$var wire 1 el mem [1] $end +$var wire 1 fl mem [2] $end +$var wire 1 gl mem_inv [0] $end +$var wire 1 hl mem_inv [1] $end +$var wire 1 il mem_inv [2] $end +$var wire 1 pl out [0] $end + +$scope module scs8hd_muxinv3_1_0 $end +$var wire 1 pl Z $end +$var wire 1 WH Q1 $end +$var wire 1 bH Q2 $end +$var wire 1 9I Q3 $end +$var wire 1 dl S0 $end +$var wire 1 gl S0B $end +$var wire 1 el S1 $end +$var wire 1 hl S1B $end +$var wire 1 fl S2 $end +$var wire 1 il S2B $end +$var wire 1 Qm Q1__bar $end +$var wire 1 Rm Q2__bar $end +$var wire 1 Sm Q3__bar $end +$upscope $end +$upscope $end + +$scope module mux_l2_in_0_ $end +$var wire 1 pl in [0] $end +$var wire 1 7J in [1] $end +$var wire 1 rl in [2] $end +$var wire 1 jl mem [0] $end +$var wire 1 kl mem [1] $end +$var wire 1 ll mem [2] $end +$var wire 1 ml mem_inv [0] $end +$var wire 1 nl mem_inv [1] $end +$var wire 1 ol mem_inv [2] $end +$var wire 1 ql out [0] $end +$var wire 1 9M p0 $end + +$scope module scs8hd_muxinv3_1_0 $end +$var wire 1 ql Z $end +$var wire 1 pl Q1 $end +$var wire 1 7J Q2 $end +$var wire 1 9M Q3 $end +$var wire 1 jl S0 $end +$var wire 1 ml S0B $end +$var wire 1 kl S1 $end +$var wire 1 nl S1B $end +$var wire 1 ll S2 $end +$var wire 1 ol S2B $end +$var wire 1 Tm Q1__bar $end +$var wire 1 Um Q2__bar $end +$var wire 1 Vm Q3__bar $end +$upscope $end +$upscope $end + +$scope module BUFT_RR_171 $end +$var wire 1 n not0_out_Y $end +$upscope $end +$upscope $end + +$scope module U12 $end +$var wire 1 bm Y $end +$var wire 1 dm A $end +$var wire 1 `K B $end +$var supply1 1 ?n VPWR $end +$var supply0 1 @n VGND $end +$var supply1 1 An VPB $end +$var supply0 1 Bn VNB $end + +$scope module base $end +$var wire 1 bm Y $end +$var wire 1 dm A $end +$var wire 1 `K B $end +$var wire 1 Cn nor0_out_Y $end +$upscope $end +$upscope $end + +$scope module FTB_69__68 $end +$var wire 1 dm X $end +$var wire 1 aK A $end +$var supply1 1 Dn VPWR $end +$var supply0 1 En VGND $end +$var supply1 1 Fn VPB $end +$var supply0 1 Gn VNB $end + +$scope module base $end +$var wire 1 dm X $end +$var wire 1 aK A $end +$var wire 1 Hn buf0_out_X $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mux_l1_in_0_ $end +$var wire 1 XH in [0] $end +$var wire 1 cH in [1] $end +$var wire 1 :I in [2] $end +$var wire 1 \m mem [0] $end +$var wire 1 ]m mem [1] $end +$var wire 1 ^m mem [2] $end +$var wire 1 _m mem_inv [0] $end +$var wire 1 `m mem_inv [1] $end +$var wire 1 am mem_inv [2] $end +$var wire 1 hm out [0] $end + +$scope module scs8hd_muxinv3_1_0 $end +$var wire 1 hm Z $end +$var wire 1 XH Q1 $end +$var wire 1 cH Q2 $end +$var wire 1 :I Q3 $end +$var wire 1 \m S0 $end +$var wire 1 _m S0B $end +$var wire 1 ]m S1 $end +$var wire 1 `m S1B $end +$var wire 1 ^m S2 $end +$var wire 1 am S2B $end +$var wire 1 In Q1__bar $end +$var wire 1 Jn Q2__bar $end +$var wire 1 Kn Q3__bar $end +$upscope $end +$upscope $end + +$scope module mux_l2_in_0_ $end +$var wire 1 hm in [0] $end +$var wire 1 9J in [1] $end +$var wire 1 jm in [2] $end +$var wire 1 bm mem [0] $end +$var wire 1 cm mem [1] $end +$var wire 1 dm mem [2] $end +$var wire 1 em mem_inv [0] $end +$var wire 1 fm mem_inv [1] $end +$var wire 1 gm mem_inv [2] $end +$var wire 1 im out [0] $end +$var wire 1 aM p0 $end + +$scope module scs8hd_muxinv3_1_0 $end +$var wire 1 im Z $end +$var wire 1 hm Q1 $end +$var wire 1 9J Q2 $end +$var wire 1 aM Q3 $end +$var wire 1 bm S0 $end +$var wire 1 em S0B $end +$var wire 1 cm S1 $end +$var wire 1 fm S1B $end +$var wire 1 dm S2 $end +$var wire 1 gm S2B $end +$var wire 1 Ln Q1__bar $end +$var wire 1 Mn Q2__bar $end +$var wire 1 Nn Q3__bar $end +$upscope $end +$upscope $end + +$scope module BUFT_RR_172 $end +$var wire 1 @J X $end +$var wire 1 im A $end +$var supply1 1 On VPWR $end +$var supply0 1 Pn VGND $end +$var supply1 1 Qn VPB $end +$var supply0 1 Rn VNB $end + +$scope module base $end +$var wire 1 @J X $end +$var wire 1 im A $end +$var wire 1 Sn buf0_out_X $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mem_top_track_12 $end +$var wire 1 NH pReset [0] $end +$var wire 1 qJ prog_clk [0] $end +$var wire 1 #L ccff_head [0] $end +$var wire 1 bK ccff_tail [0] $end +$var wire 1 JK mem_out [0] $end +$var wire 1 KK mem_out [1] $end +$var wire 1 LK mem_out [2] $end +$var wire 1 MK mem_out [3] $end + +$scope module sky130_fd_sc_hd__dfrtp_1_0_ $end +$var wire 1 JK Q $end +$var wire 1 qJ CLK $end +$var wire 1 #L D $end +$var wire 1 NH RESET_B $end +$var supply1 1 Tn VPWR $end +$var supply0 1 Un VGND $end +$var supply1 1 Vn VPB $end +$var supply0 1 Wn VNB $end + +$scope module base $end +$var wire 1 JK Q $end +$var wire 1 qJ CLK $end +$var wire 1 #L D $end +$var wire 1 NH RESET_B $end +$var wire 1 Xn buf_Q $end +$var wire 1 Yn RESET $end +$upscope $end +$upscope $end + +$scope module sky130_fd_sc_hd__dfrtp_1_1_ $end +$var wire 1 KK Q $end +$var wire 1 qJ CLK $end +$var wire 1 JK D $end +$var wire 1 NH RESET_B $end +$var supply1 1 Zn VPWR $end +$var supply0 1 [n VGND $end +$var supply1 1 \n VPB $end +$var supply0 1 ]n VNB $end + +$scope module base $end +$var wire 1 KK Q $end +$var wire 1 qJ CLK $end +$var wire 1 JK D $end +$var wire 1 NH RESET_B $end +$var wire 1 ^n buf_Q $end +$var wire 1 _n RESET $end +$upscope $end +$upscope $end + +$scope module sky130_fd_sc_hd__dfrtp_1_2_ $end +$var wire 1 LK Q $end +$var wire 1 qJ CLK $end +$var wire 1 KK D $end +$var wire 1 NH RESET_B $end +$var supply1 1 `n VPWR $end +$var supply0 1 an VGND $end +$var supply1 1 bn VPB $end +$var supply0 1 cn VNB $end + +$scope module base $end +$var wire 1 LK Q $end +$var wire 1 qJ CLK $end +$var wire 1 KK D $end +$var wire 1 NH RESET_B $end +$var wire 1 dn buf_Q $end +$var wire 1 en RESET $end +$upscope $end +$upscope $end + +$scope module sky130_fd_sc_hd__dfrtp_1_3_ $end +$var wire 1 MK Q $end +$var wire 1 qJ CLK $end +$var wire 1 LK D $end +$var wire 1 NH RESET_B $end +$var supply1 1 fn VPWR $end +$var supply0 1 gn VGND $end +$var supply1 1 hn VPB $end +$var supply0 1 in VNB $end + +$scope module base $end +$var wire 1 MK Q $end +$var wire 1 qJ CLK $end +$var wire 1 LK D $end +$var wire 1 NH RESET_B $end +$var wire 1 jn buf_Q $end +$var wire 1 kn RESET $end +$upscope $end +$upscope $end + +$scope module FTB_70__69 $end +$var wire 1 bK X $end +$var wire 1 MK A $end +$var supply1 1 ln VPWR $end +$var supply0 1 mn VGND $end +$var supply1 1 nn VPB $end +$var supply0 1 on VNB $end + +$scope module base $end +$var wire 1 bK X $end +$var wire 1 MK A $end +$var wire 1 pn buf0_out_X $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mem_top_track_14 $end +$var wire 1 NH pReset [0] $end +$var wire 1 qJ prog_clk [0] $end +$var wire 1 bK ccff_head [0] $end +$var wire 1 cK ccff_tail [0] $end +$var wire 1 NK mem_out [0] $end +$var wire 1 OK mem_out [1] $end +$var wire 1 PK mem_out [2] $end +$var wire 1 QK mem_out [3] $end + +$scope module sky130_fd_sc_hd__dfrtp_1_0_ $end +$var wire 1 NK Q $end +$var wire 1 qJ CLK $end +$var wire 1 bK D $end +$var wire 1 NH RESET_B $end +$var supply1 1 qn VPWR $end +$var supply0 1 rn VGND $end +$var supply1 1 sn VPB $end +$var supply0 1 tn VNB $end + +$scope module base $end +$var wire 1 NK Q $end +$var wire 1 qJ CLK $end +$var wire 1 bK D $end +$var wire 1 NH RESET_B $end +$var wire 1 un buf_Q $end +$var wire 1 vn RESET $end +$upscope $end +$upscope $end + +$scope module sky130_fd_sc_hd__dfrtp_1_1_ $end +$var wire 1 OK Q $end +$var wire 1 qJ CLK $end +$var wire 1 NK D $end +$var wire 1 NH RESET_B $end +$var supply1 1 wn VPWR $end +$var supply0 1 xn VGND $end +$var supply1 1 yn VPB $end +$var supply0 1 zn VNB $end + +$scope module base $end +$var wire 1 OK Q $end +$var wire 1 qJ CLK $end +$var wire 1 NK D $end +$var wire 1 NH RESET_B $end +$var wire 1 {n buf_Q $end +$var wire 1 |n RESET $end +$upscope $end +$upscope $end + +$scope module sky130_fd_sc_hd__dfrtp_1_2_ $end +$var wire 1 PK Q $end +$var wire 1 qJ CLK $end +$var wire 1 OK D $end +$var wire 1 NH RESET_B $end +$var supply1 1 }n VPWR $end +$var supply0 1 ~n VGND $end +$var supply1 1 !o VPB $end +$var supply0 1 "o VNB $end + +$scope module base $end +$var wire 1 PK Q $end +$var wire 1 qJ CLK $end +$var wire 1 OK D $end +$var wire 1 NH RESET_B $end +$var wire 1 #o buf_Q $end +$var wire 1 $o RESET $end +$upscope $end +$upscope $end + +$scope module sky130_fd_sc_hd__dfrtp_1_3_ $end +$var wire 1 QK Q $end +$var wire 1 qJ CLK $end +$var wire 1 PK D $end +$var wire 1 NH RESET_B $end +$var supply1 1 %o VPWR $end +$var supply0 1 &o VGND $end +$var supply1 1 'o VPB $end +$var supply0 1 (o VNB $end + +$scope module base $end +$var wire 1 QK Q $end +$var wire 1 qJ CLK $end +$var wire 1 PK D $end +$var wire 1 NH RESET_B $end +$var wire 1 )o buf_Q $end +$var wire 1 *o RESET $end +$upscope $end +$upscope $end + +$scope module FTB_71__70 $end +$var wire 1 cK X $end +$var wire 1 QK A $end +$var supply1 1 +o VPWR $end +$var supply0 1 ,o VGND $end +$var supply1 1 -o VPB $end +$var supply0 1 .o VNB $end + +$scope module base $end +$var wire 1 cK X $end +$var wire 1 QK A $end +$var wire 1 /o buf0_out_X $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mem_top_track_16 $end +$var wire 1 NH pReset [0] $end +$var wire 1 qJ prog_clk [0] $end +$var wire 1 cK ccff_head [0] $end +$var wire 1 dK ccff_tail [0] $end +$var wire 1 RK mem_out [0] $end +$var wire 1 SK mem_out [1] $end +$var wire 1 TK mem_out [2] $end +$var wire 1 UK mem_out [3] $end + +$scope module sky130_fd_sc_hd__dfrtp_1_0_ $end +$var wire 1 RK Q $end +$var wire 1 qJ CLK $end +$var wire 1 cK D $end +$var wire 1 NH RESET_B $end +$var supply1 1 0o VPWR $end +$var supply0 1 1o VGND $end +$var supply1 1 2o VPB $end +$var supply0 1 3o VNB $end + +$scope module base $end +$var wire 1 RK Q $end +$var wire 1 qJ CLK $end +$var wire 1 cK D $end +$var wire 1 NH RESET_B $end +$var wire 1 4o buf_Q $end +$var wire 1 5o RESET $end +$upscope $end +$upscope $end + +$scope module sky130_fd_sc_hd__dfrtp_1_1_ $end +$var wire 1 SK Q $end +$var wire 1 qJ CLK $end +$var wire 1 RK D $end +$var wire 1 NH RESET_B $end +$var supply1 1 6o VPWR $end +$var supply0 1 7o VGND $end +$var supply1 1 8o VPB $end +$var supply0 1 9o VNB $end + +$scope module base $end +$var wire 1 SK Q $end +$var wire 1 qJ CLK $end +$var wire 1 RK D $end +$var wire 1 NH RESET_B $end +$var wire 1 :o buf_Q $end +$var wire 1 ;o RESET $end +$upscope $end +$upscope $end + +$scope module sky130_fd_sc_hd__dfrtp_1_2_ $end +$var wire 1 TK Q $end +$var wire 1 qJ CLK $end +$var wire 1 SK D $end +$var wire 1 NH RESET_B $end +$var supply1 1 o VPB $end +$var supply0 1 ?o VNB $end + +$scope module base $end +$var wire 1 TK Q $end +$var wire 1 qJ CLK $end +$var wire 1 SK D $end +$var wire 1 NH RESET_B $end +$var wire 1 @o buf_Q $end +$var wire 1 Ao RESET $end +$upscope $end +$upscope $end + +$scope module sky130_fd_sc_hd__dfrtp_1_3_ $end +$var wire 1 UK Q $end +$var wire 1 qJ CLK $end +$var wire 1 TK D $end +$var wire 1 NH RESET_B $end +$var supply1 1 Bo VPWR $end +$var supply0 1 Co VGND $end +$var supply1 1 Do VPB $end +$var supply0 1 Eo VNB $end + +$scope module base $end +$var wire 1 UK Q $end +$var wire 1 qJ CLK $end +$var wire 1 TK D $end +$var wire 1 NH RESET_B $end +$var wire 1 Fo buf_Q $end +$var wire 1 Go RESET $end +$upscope $end +$upscope $end + +$scope module FTB_72__71 $end +$var wire 1 dK X $end +$var wire 1 UK A $end +$var supply1 1 Ho VPWR $end +$var supply0 1 Io VGND $end +$var supply1 1 Jo VPB $end +$var supply0 1 Ko VNB $end + +$scope module base $end +$var wire 1 dK X $end +$var wire 1 UK A $end +$var wire 1 Lo buf0_out_X $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mem_top_track_18 $end +$var wire 1 NH pReset [0] $end +$var wire 1 qJ prog_clk [0] $end +$var wire 1 dK ccff_head [0] $end +$var wire 1 eK ccff_tail [0] $end +$var wire 1 VK mem_out [0] $end +$var wire 1 WK mem_out [1] $end +$var wire 1 XK mem_out [2] $end +$var wire 1 YK mem_out [3] $end + +$scope module sky130_fd_sc_hd__dfrtp_1_0_ $end +$var wire 1 VK Q $end +$var wire 1 qJ CLK $end +$var wire 1 dK D $end +$var wire 1 NH RESET_B $end +$var supply1 1 Mo VPWR $end +$var supply0 1 No VGND $end +$var supply1 1 Oo VPB $end +$var supply0 1 Po VNB $end + +$scope module base $end +$var wire 1 VK Q $end +$var wire 1 qJ CLK $end +$var wire 1 dK D $end +$var wire 1 NH RESET_B $end +$var wire 1 Qo buf_Q $end +$var wire 1 Ro RESET $end +$upscope $end +$upscope $end + +$scope module sky130_fd_sc_hd__dfrtp_1_1_ $end +$var wire 1 WK Q $end +$var wire 1 qJ CLK $end +$var wire 1 VK D $end +$var wire 1 NH RESET_B $end +$var supply1 1 So VPWR $end +$var supply0 1 To VGND $end +$var supply1 1 Uo VPB $end +$var supply0 1 Vo VNB $end + +$scope module base $end +$var wire 1 WK Q $end +$var wire 1 qJ CLK $end +$var wire 1 VK D $end +$var wire 1 NH RESET_B $end +$var wire 1 Wo buf_Q $end +$var wire 1 Xo RESET $end +$upscope $end +$upscope $end + +$scope module sky130_fd_sc_hd__dfrtp_1_2_ $end +$var wire 1 XK Q $end +$var wire 1 qJ CLK $end +$var wire 1 WK D $end +$var wire 1 NH RESET_B $end +$var supply1 1 Yo VPWR $end +$var supply0 1 Zo VGND $end +$var supply1 1 [o VPB $end +$var supply0 1 \o VNB $end + +$scope module base $end +$var wire 1 XK Q $end +$var wire 1 qJ CLK $end +$var wire 1 WK D $end +$var wire 1 NH RESET_B $end +$var wire 1 ]o buf_Q $end +$var wire 1 ^o RESET $end +$upscope $end +$upscope $end + +$scope module sky130_fd_sc_hd__dfrtp_1_3_ $end +$var wire 1 YK Q $end +$var wire 1 qJ CLK $end +$var wire 1 XK D $end +$var wire 1 NH RESET_B $end +$var supply1 1 _o VPWR $end +$var supply0 1 `o VGND $end +$var supply1 1 ao VPB $end +$var supply0 1 bo VNB $end + +$scope module base $end +$var wire 1 YK Q $end +$var wire 1 qJ CLK $end +$var wire 1 XK D $end +$var wire 1 NH RESET_B $end +$var wire 1 co buf_Q $end +$var wire 1 do RESET $end +$upscope $end +$upscope $end + +$scope module FTB_73__72 $end +$var wire 1 eK X $end +$var wire 1 YK A $end +$var supply1 1 eo VPWR $end +$var supply0 1 fo VGND $end +$var supply1 1 go VPB $end +$var supply0 1 ho VNB $end + +$scope module base $end +$var wire 1 eK X $end +$var wire 1 YK A $end +$var wire 1 io buf0_out_X $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mem_right_track_44 $end +$var wire 1 NH pReset [0] $end +$var wire 1 qJ prog_clk [0] $end +$var wire 1 $L ccff_head [0] $end +$var wire 1 fK ccff_tail [0] $end +$var wire 1 ZK mem_out [0] $end +$var wire 1 [K mem_out [1] $end +$var wire 1 \K mem_out [2] $end +$var wire 1 ]K mem_out [3] $end + +$scope module sky130_fd_sc_hd__dfrtp_1_0_ $end +$var wire 1 ZK Q $end +$var wire 1 qJ CLK $end +$var wire 1 $L D $end +$var wire 1 NH RESET_B $end +$var supply1 1 jo VPWR $end +$var supply0 1 ko VGND $end +$var supply1 1 lo VPB $end +$var supply0 1 mo VNB $end + +$scope module base $end +$var wire 1 ZK Q $end +$var wire 1 qJ CLK $end +$var wire 1 $L D $end +$var wire 1 NH RESET_B $end +$var wire 1 no buf_Q $end +$var wire 1 oo RESET $end +$upscope $end +$upscope $end + +$scope module sky130_fd_sc_hd__dfrtp_1_1_ $end +$var wire 1 [K Q $end +$var wire 1 qJ CLK $end +$var wire 1 ZK D $end +$var wire 1 NH RESET_B $end +$var supply1 1 po VPWR $end +$var supply0 1 qo VGND $end +$var supply1 1 ro VPB $end +$var supply0 1 so VNB $end + +$scope module base $end +$var wire 1 [K Q $end +$var wire 1 qJ CLK $end +$var wire 1 ZK D $end +$var wire 1 NH RESET_B $end +$var wire 1 to buf_Q $end +$var wire 1 uo RESET $end +$upscope $end +$upscope $end + +$scope module sky130_fd_sc_hd__dfrtp_1_2_ $end +$var wire 1 \K Q $end +$var wire 1 qJ CLK $end +$var wire 1 [K D $end +$var wire 1 NH RESET_B $end +$var supply1 1 vo VPWR $end +$var supply0 1 wo VGND $end +$var supply1 1 xo VPB $end +$var supply0 1 yo VNB $end + +$scope module base $end +$var wire 1 \K Q $end +$var wire 1 qJ CLK $end +$var wire 1 [K D $end +$var wire 1 NH RESET_B $end +$var wire 1 zo buf_Q $end +$var wire 1 {o RESET $end +$upscope $end +$upscope $end + +$scope module sky130_fd_sc_hd__dfrtp_1_3_ $end +$var wire 1 ]K Q $end +$var wire 1 qJ CLK $end +$var wire 1 \K D $end +$var wire 1 NH RESET_B $end +$var supply1 1 |o VPWR $end +$var supply0 1 }o VGND $end +$var supply1 1 ~o VPB $end +$var supply0 1 !p VNB $end + +$scope module base $end +$var wire 1 ]K Q $end +$var wire 1 qJ CLK $end +$var wire 1 \K D $end +$var wire 1 NH RESET_B $end +$var wire 1 "p buf_Q $end +$var wire 1 #p RESET $end +$upscope $end +$upscope $end + +$scope module FTB_74__73 $end +$var wire 1 fK X $end +$var wire 1 ]K A $end +$var supply1 1 $p VPWR $end +$var supply0 1 %p VGND $end +$var supply1 1 &p VPB $end +$var supply0 1 'p VNB $end + +$scope module base $end +$var wire 1 fK X $end +$var wire 1 ]K A $end +$var wire 1 (p buf0_out_X $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mem_right_track_52 $end +$var wire 1 NH pReset [0] $end +$var wire 1 qJ prog_clk [0] $end +$var wire 1 fK ccff_head [0] $end +$var wire 1 gK ccff_tail [0] $end +$var wire 1 ^K mem_out [0] $end +$var wire 1 _K mem_out [1] $end +$var wire 1 `K mem_out [2] $end +$var wire 1 aK mem_out [3] $end + +$scope module sky130_fd_sc_hd__dfrtp_1_0_ $end +$var wire 1 ^K Q $end +$var wire 1 qJ CLK $end +$var wire 1 fK D $end +$var wire 1 NH RESET_B $end +$var supply1 1 )p VPWR $end +$var supply0 1 *p VGND $end +$var supply1 1 +p VPB $end +$var supply0 1 ,p VNB $end + +$scope module base $end +$var wire 1 ^K Q $end +$var wire 1 qJ CLK $end +$var wire 1 fK D $end +$var wire 1 NH RESET_B $end +$var wire 1 -p buf_Q $end +$var wire 1 .p RESET $end +$upscope $end +$upscope $end + +$scope module sky130_fd_sc_hd__dfrtp_1_1_ $end +$var wire 1 _K Q $end +$var wire 1 qJ CLK $end +$var wire 1 ^K D $end +$var wire 1 NH RESET_B $end +$var supply1 1 /p VPWR $end +$var supply0 1 0p VGND $end +$var supply1 1 1p VPB $end +$var supply0 1 2p VNB $end + +$scope module base $end +$var wire 1 _K Q $end +$var wire 1 qJ CLK $end +$var wire 1 ^K D $end +$var wire 1 NH RESET_B $end +$var wire 1 3p buf_Q $end +$var wire 1 4p RESET $end +$upscope $end +$upscope $end + +$scope module sky130_fd_sc_hd__dfrtp_1_2_ $end +$var wire 1 `K Q $end +$var wire 1 qJ CLK $end +$var wire 1 _K D $end +$var wire 1 NH RESET_B $end +$var supply1 1 5p VPWR $end +$var supply0 1 6p VGND $end +$var supply1 1 7p VPB $end +$var supply0 1 8p VNB $end + +$scope module base $end +$var wire 1 `K Q $end +$var wire 1 qJ CLK $end +$var wire 1 _K D $end +$var wire 1 NH RESET_B $end +$var wire 1 9p buf_Q $end +$var wire 1 :p RESET $end +$upscope $end +$upscope $end + +$scope module sky130_fd_sc_hd__dfrtp_1_3_ $end +$var wire 1 aK Q $end +$var wire 1 qJ CLK $end +$var wire 1 `K D $end +$var wire 1 NH RESET_B $end +$var supply1 1 ;p VPWR $end +$var supply0 1

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+0Y! +0Z! +0rJ +#407320000 +1! +1j$! +1vN +0T'! +0{N +1O'! +1nJ +1mJ +1e$! +1X! +1kG +1qJ +1Y! +1Z! +1rJ diff --git a/FPGA1212_SOFA_CHD_PNR/Verification/ConfigChainTestFull_run/run.log b/FPGA1212_SOFA_CHD_PNR/Verification/ConfigChainTestFull_run/run.log new file mode 100644 index 0000000..c7e1a28 --- /dev/null +++ b/FPGA1212_SOFA_CHD_PNR/Verification/ConfigChainTestFull_run/run.log @@ -0,0 +1,647 @@ +Found test fpga_reset_hd_sky_pnr.ConfigChainTestFull +Running test 1/1: ConfigChainTestFull +Starting test: "ConfigChainTestFull" +Description: None +Signal received at sb_12__12_ at 65 +Signal received at cbx_12__12_ at 35 +Signal received at sb_11__12_ at 81 +Signal received at cbx_11__12_ at 35 +Signal received at sb_10__12_ at 81 +Signal received at cbx_10__12_ at 35 +Signal received at sb_9__12_ at 81 +Signal received at cbx_9__12_ at 35 +Signal received at sb_8__12_ at 81 +Signal received at cbx_8__12_ at 35 +Signal received at sb_7__12_ at 81 +Signal received at cbx_7__12_ at 35 +Signal received at sb_6__12_ at 81 +Signal received at cbx_6__12_ at 35 +Signal received at sb_5__12_ at 81 +Signal received at cbx_5__12_ at 35 +Signal received at sb_4__12_ at 81 +Signal received at cbx_4__12_ at 35 +Signal received at sb_3__12_ at 81 +Signal received at cbx_3__12_ at 35 +Signal received at sb_2__12_ at 81 +Signal received at cbx_2__12_ at 35 +Signal received at sb_1__12_ at 81 +Signal received at cbx_1__12_ at 35 +Signal received at sb_0__12_ at 41 +Signal received at cby_0__12_ at 3 +Signal received at grid_clb_1__12_ at 116 +Signal received at cby_1__12_ at 32 +Signal received at grid_clb_2__12_ at 116 +Signal received at cby_2__12_ at 32 +Signal received at grid_clb_3__12_ at 116 +Signal received at cby_3__12_ at 32 +Signal received at grid_clb_4__12_ at 116 +Signal received at cby_4__12_ at 32 +Signal received at grid_clb_5__12_ at 116 +Signal received at cby_5__12_ at 32 +Signal received at grid_clb_6__12_ at 116 +Signal received at cby_6__12_ at 32 +Signal received at grid_clb_7__12_ at 116 +Signal received at cby_7__12_ at 32 +Signal received at grid_clb_8__12_ at 116 +Signal received at cby_8__12_ at 32 +Signal received at grid_clb_9__12_ at 116 +Signal received at cby_9__12_ at 32 +Signal received at grid_clb_10__12_ at 116 +Signal received at cby_10__12_ at 32 +Signal received at grid_clb_11__12_ at 116 +Signal received at cby_11__12_ at 32 +Signal received at grid_clb_12__12_ at 116 +Signal received at cby_12__12_ at 35 +Signal received at sb_12__11_ at 83 +Signal received at cbx_12__11_ at 33 +Signal received at sb_11__11_ at 88 +Signal received at cbx_11__11_ at 32 +Signal received at sb_10__11_ at 88 +Signal received at cbx_10__11_ at 32 +Signal received at sb_9__11_ at 88 +Signal received at cbx_9__11_ at 32 +Signal received at sb_8__11_ at 88 +Signal received at cbx_8__11_ at 32 +Signal received at sb_7__11_ at 88 +Signal received at cbx_7__11_ at 32 +Signal received at sb_6__11_ at 88 +Signal received at cbx_6__11_ at 32 +Signal received at sb_5__11_ at 88 +Signal received at cbx_5__11_ at 32 +Signal received at sb_4__11_ at 88 +Signal received at cbx_4__11_ at 32 +Signal received at sb_3__11_ at 88 +Signal received at cbx_3__11_ at 32 +Signal received at sb_2__11_ at 88 +Signal received at cbx_2__11_ at 32 +Signal received at sb_1__11_ at 88 +Signal received at cbx_1__11_ at 32 +Signal received at sb_0__11_ at 82 +Signal received at cby_0__11_ at 3 +Signal received at grid_clb_1__11_ at 116 +Signal received at cby_1__11_ at 32 +Signal received at grid_clb_2__11_ at 116 +Signal received at cby_2__11_ at 32 +Signal received at grid_clb_3__11_ at 116 +Signal received at cby_3__11_ at 32 +Signal received at grid_clb_4__11_ at 116 +Signal received at cby_4__11_ at 32 +Signal received at grid_clb_5__11_ at 116 +Signal received at cby_5__11_ at 32 +Signal received at grid_clb_6__11_ at 116 +Signal received at cby_6__11_ at 32 +Signal received at grid_clb_7__11_ at 116 +Signal received at cby_7__11_ at 32 +Signal received at grid_clb_8__11_ at 116 +Signal received at cby_8__11_ at 32 +Signal received at grid_clb_9__11_ at 116 +Signal received at cby_9__11_ at 32 +Signal received at grid_clb_10__11_ at 116 +Signal received at cby_10__11_ at 32 +Signal received at grid_clb_11__11_ at 116 +Signal received at cby_11__11_ at 32 +Signal received at grid_clb_12__11_ at 116 +Signal received at cby_12__11_ at 35 +Signal received at sb_12__10_ at 83 +Signal received at cbx_12__10_ at 32 +Signal received at sb_11__10_ at 88 +Signal received at cbx_11__10_ at 32 +Signal received at sb_10__10_ at 88 +Signal received at cbx_10__10_ at 32 +Signal received at sb_9__10_ at 88 +Signal received at cbx_9__10_ at 32 +Signal received at sb_8__10_ at 88 +Signal received at cbx_8__10_ at 32 +Signal received at sb_7__10_ at 88 +Signal received at cbx_7__10_ at 32 +Signal received at sb_6__10_ at 88 +Signal received at cbx_6__10_ at 32 +Signal received at sb_5__10_ at 88 +Signal received at cbx_5__10_ at 32 +Signal received at sb_4__10_ at 88 +Signal received at cbx_4__10_ at 32 +Signal received at sb_3__10_ at 88 +Signal received at cbx_3__10_ at 32 +Signal received at sb_2__10_ at 88 +Signal received at cbx_2__10_ at 32 +Signal received at sb_1__10_ at 88 +Signal received at cbx_1__10_ at 32 +Signal received at sb_0__10_ at 82 +Signal received at cby_0__10_ at 3 +Signal received at grid_clb_1__10_ at 116 +Signal received at cby_1__10_ at 32 +Signal received at grid_clb_2__10_ at 116 +Signal received at cby_2__10_ at 32 +Signal received at grid_clb_3__10_ at 116 +Signal received at cby_3__10_ at 32 +Signal received at grid_clb_4__10_ at 116 +Signal received at cby_4__10_ at 32 +Signal received at grid_clb_5__10_ at 116 +Signal received at cby_5__10_ at 32 +Signal received at grid_clb_6__10_ at 116 +Signal received at cby_6__10_ at 32 +Signal received at grid_clb_7__10_ at 116 +Signal received at cby_7__10_ at 32 +Signal received at grid_clb_8__10_ at 116 +Signal received at cby_8__10_ at 32 +Signal received at grid_clb_9__10_ at 116 +Signal received at cby_9__10_ at 32 +Signal received at grid_clb_10__10_ at 116 +Signal received at cby_10__10_ at 32 +Signal received at grid_clb_11__10_ at 116 +Signal received at cby_11__10_ at 32 +Signal received at grid_clb_12__10_ at 116 +Signal received at cby_12__10_ at 35 +Signal received at sb_12__9_ at 83 +Signal received at cbx_12__9_ at 32 +Signal received at sb_11__9_ at 88 +Signal received at cbx_11__9_ at 32 +Signal received at sb_10__9_ at 88 +Signal received at cbx_10__9_ at 32 +Signal received at sb_9__9_ at 88 +Signal received at cbx_9__9_ at 32 +Signal received at sb_8__9_ at 88 +Signal received at cbx_8__9_ at 32 +Signal received at sb_7__9_ at 88 +Signal received at cbx_7__9_ at 32 +Signal received at sb_6__9_ at 88 +Signal received at cbx_6__9_ at 32 +Signal received at sb_5__9_ at 88 +Signal received at cbx_5__9_ at 32 +Signal received at sb_4__9_ at 88 +Signal received at cbx_4__9_ at 32 +Signal received at sb_3__9_ at 88 +Signal received at cbx_3__9_ at 32 +Signal received at sb_2__9_ at 88 +Signal received at cbx_2__9_ at 32 +Signal received at sb_1__9_ at 88 +Signal received at cbx_1__9_ at 32 +Signal received at sb_0__9_ at 82 +Signal received at cby_0__9_ at 3 +Signal received at grid_clb_1__9_ at 116 +Signal received at cby_1__9_ at 32 +Signal received at grid_clb_2__9_ at 116 +Signal received at cby_2__9_ at 32 +Signal received at grid_clb_3__9_ at 116 +Signal received at cby_3__9_ at 32 +Signal received at grid_clb_4__9_ at 116 +Signal received at cby_4__9_ at 32 +Signal received at grid_clb_5__9_ at 116 +Signal received at cby_5__9_ at 32 +Signal received at grid_clb_6__9_ at 116 +Signal received at cby_6__9_ at 32 +Signal received at grid_clb_7__9_ at 116 +Signal received at cby_7__9_ at 32 +Signal received at grid_clb_8__9_ at 116 +Signal received at cby_8__9_ at 32 +Signal received at grid_clb_9__9_ at 116 +Signal received at cby_9__9_ at 32 +Signal received at grid_clb_10__9_ at 116 +Signal received at cby_10__9_ at 32 +Signal received at grid_clb_11__9_ at 116 +Signal received at cby_11__9_ at 32 +Signal received at grid_clb_12__9_ at 116 +Signal received at cby_12__9_ at 35 +Signal received at sb_12__8_ at 84 +Signal received at cbx_12__8_ at 32 +Signal received at sb_11__8_ at 88 +Signal received at cbx_11__8_ at 32 +Signal received at sb_10__8_ at 88 +Signal received at cbx_10__8_ at 32 +Signal received at sb_9__8_ at 88 +Signal received at cbx_9__8_ at 32 +Signal received at sb_8__8_ at 88 +Signal received at cbx_8__8_ at 32 +Signal received at sb_7__8_ at 88 +Signal received at cbx_7__8_ at 32 +Signal received at sb_6__8_ at 88 +Signal received at cbx_6__8_ at 32 +Signal received at sb_5__8_ at 88 +Signal received at cbx_5__8_ at 32 +Signal received at sb_4__8_ at 88 +Signal received at cbx_4__8_ at 32 +Signal received at sb_3__8_ at 88 +Signal received at cbx_3__8_ at 32 +Signal received at sb_2__8_ at 88 +Signal received at cbx_2__8_ at 32 +Signal received at sb_1__8_ at 88 +Signal received at cbx_1__8_ at 32 +Signal received at sb_0__8_ at 82 +Signal received at cby_0__8_ at 3 +Signal received at grid_clb_1__8_ at 116 +Signal received at cby_1__8_ at 32 +Signal received at grid_clb_2__8_ at 116 +Signal received at cby_2__8_ at 32 +Signal received at grid_clb_3__8_ at 116 +Signal received at cby_3__8_ at 32 +Signal received at grid_clb_4__8_ at 116 +Signal received at cby_4__8_ at 32 +Signal received at grid_clb_5__8_ at 116 +Signal received at cby_5__8_ at 32 +Signal received at grid_clb_6__8_ at 116 +Signal received at cby_6__8_ at 32 +Signal received at grid_clb_7__8_ at 116 +Signal received at cby_7__8_ at 32 +Signal received at grid_clb_8__8_ at 116 +Signal received at cby_8__8_ at 32 +Signal received at grid_clb_9__8_ at 116 +Signal received at cby_9__8_ at 32 +Signal received at grid_clb_10__8_ at 116 +Signal received at cby_10__8_ at 32 +Signal received at grid_clb_11__8_ at 116 +Signal received at cby_11__8_ at 32 +Signal received at grid_clb_12__8_ at 116 +Signal received at cby_12__8_ at 35 +Signal received at sb_12__7_ at 83 +Signal received at cbx_12__7_ at 32 +Signal received at sb_11__7_ at 88 +Signal received at cbx_11__7_ at 32 +Signal received at sb_10__7_ at 88 +Signal received at cbx_10__7_ at 32 +Signal received at sb_9__7_ at 88 +Signal received at cbx_9__7_ at 32 +Signal received at sb_8__7_ at 88 +Signal received at cbx_8__7_ at 32 +Signal received at sb_7__7_ at 88 +Signal received at cbx_7__7_ at 32 +Signal received at sb_6__7_ at 88 +Signal received at cbx_6__7_ at 32 +Signal received at sb_5__7_ at 88 +Signal received at cbx_5__7_ at 32 +Signal received at sb_4__7_ at 88 +Signal received at cbx_4__7_ at 32 +Signal received at sb_3__7_ at 88 +Signal received at cbx_3__7_ at 32 +Signal received at sb_2__7_ at 88 +Signal received at cbx_2__7_ at 32 +Signal received at sb_1__7_ at 88 +Signal received at cbx_1__7_ at 32 +Signal received at sb_0__7_ at 82 +Signal received at cby_0__7_ at 3 +Signal received at grid_clb_1__7_ at 116 +Signal received at cby_1__7_ at 32 +Signal received at grid_clb_2__7_ at 116 +Signal received at cby_2__7_ at 32 +Signal received at grid_clb_3__7_ at 116 +Signal received at cby_3__7_ at 32 +Signal received at grid_clb_4__7_ at 116 +Signal received at cby_4__7_ at 32 +Signal received at grid_clb_5__7_ at 116 +Signal received at cby_5__7_ at 32 +Signal received at grid_clb_6__7_ at 116 +Signal received at cby_6__7_ at 32 +Signal received at grid_clb_7__7_ at 116 +Signal received at cby_7__7_ at 32 +Signal received at grid_clb_8__7_ at 116 +Signal received at cby_8__7_ at 32 +Signal received at grid_clb_9__7_ at 116 +Signal received at cby_9__7_ at 32 +Signal received at grid_clb_10__7_ at 116 +Signal received at cby_10__7_ at 32 +Signal received at grid_clb_11__7_ at 116 +Signal received at cby_11__7_ at 32 +Signal received at grid_clb_12__7_ at 116 +Signal received at cby_12__7_ at 35 +Signal received at sb_12__6_ at 83 +Signal received at cbx_12__6_ at 32 +Signal received at sb_11__6_ at 88 +Signal received at cbx_11__6_ at 32 +Signal received at sb_10__6_ at 88 +Signal received at cbx_10__6_ at 32 +Signal received at sb_9__6_ at 88 +Signal received at cbx_9__6_ at 32 +Signal received at sb_8__6_ at 88 +Signal received at cbx_8__6_ at 32 +Signal received at sb_7__6_ at 88 +Signal received at cbx_7__6_ at 32 +Signal received at sb_6__6_ at 88 +Signal received at cbx_6__6_ at 32 +Signal received at sb_5__6_ at 88 +Signal received at cbx_5__6_ at 32 +Signal received at sb_4__6_ at 88 +Signal received at cbx_4__6_ at 32 +Signal received at sb_3__6_ at 88 +Signal received at cbx_3__6_ at 32 +Signal received at sb_2__6_ at 88 +Signal received at cbx_2__6_ at 32 +Signal received at sb_1__6_ at 88 +Signal received at cbx_1__6_ at 32 +Signal received at sb_0__6_ at 82 +Signal received at cby_0__6_ at 3 +Signal received at grid_clb_1__6_ at 116 +Signal received at cby_1__6_ at 32 +Signal received at grid_clb_2__6_ at 116 +Signal received at cby_2__6_ at 32 +Signal received at grid_clb_3__6_ at 116 +Signal received at cby_3__6_ at 32 +Signal received at grid_clb_4__6_ at 116 +Signal received at cby_4__6_ at 32 +Signal received at grid_clb_5__6_ at 116 +Signal received at cby_5__6_ at 32 +Signal received at grid_clb_6__6_ at 116 +Signal received at cby_6__6_ at 32 +Signal received at grid_clb_7__6_ at 116 +Signal received at cby_7__6_ at 32 +Signal received at grid_clb_8__6_ at 116 +Signal received at cby_8__6_ at 32 +Signal received at grid_clb_9__6_ at 116 +Signal received at cby_9__6_ at 32 +Signal received at grid_clb_10__6_ at 116 +Signal received at cby_10__6_ at 32 +Signal received at grid_clb_11__6_ at 116 +Signal received at cby_11__6_ at 32 +Signal received at grid_clb_12__6_ at 116 +Signal received at cby_12__6_ at 35 +Signal received at sb_12__5_ at 83 +Signal received at cbx_12__5_ at 32 +Signal received at sb_11__5_ at 88 +Signal received at cbx_11__5_ at 32 +Signal received at sb_10__5_ at 88 +Signal received at cbx_10__5_ at 32 +Signal received at sb_9__5_ at 88 +Signal received at cbx_9__5_ at 32 +Signal received at sb_8__5_ at 88 +Signal received at cbx_8__5_ at 32 +Signal received at sb_7__5_ at 88 +Signal received at cbx_7__5_ at 32 +Signal received at sb_6__5_ at 88 +Signal received at cbx_6__5_ at 32 +Signal received at sb_5__5_ at 88 +Signal received at cbx_5__5_ at 32 +Signal received at sb_4__5_ at 88 +Signal received at cbx_4__5_ at 32 +Signal received at sb_3__5_ at 88 +Signal received at cbx_3__5_ at 32 +Signal received at sb_2__5_ at 88 +Signal received at cbx_2__5_ at 32 +Signal received at sb_1__5_ at 88 +Signal received at cbx_1__5_ at 32 +Signal received at sb_0__5_ at 82 +Signal received at cby_0__5_ at 3 +Signal received at grid_clb_1__5_ at 116 +Signal received at cby_1__5_ at 32 +Signal received at grid_clb_2__5_ at 116 +Signal received at cby_2__5_ at 32 +Signal received at grid_clb_3__5_ at 116 +Signal received at cby_3__5_ at 32 +Signal received at grid_clb_4__5_ at 116 +Signal received at cby_4__5_ at 32 +Signal received at grid_clb_5__5_ at 116 +Signal received at cby_5__5_ at 32 +Signal received at grid_clb_6__5_ at 116 +Signal received at cby_6__5_ at 32 +Signal received at grid_clb_7__5_ at 116 +Signal received at cby_7__5_ at 32 +Signal received at grid_clb_8__5_ at 116 +Signal received at cby_8__5_ at 32 +Signal received at grid_clb_9__5_ at 116 +Signal received at cby_9__5_ at 32 +Signal received at grid_clb_10__5_ at 116 +Signal received at cby_10__5_ at 32 +Signal received at grid_clb_11__5_ at 116 +Signal received at cby_11__5_ at 32 +Signal received at grid_clb_12__5_ at 116 +Signal received at cby_12__5_ at 35 +Signal received at sb_12__4_ at 83 +Signal received at cbx_12__4_ at 32 +Signal received at sb_11__4_ at 88 +Signal received at cbx_11__4_ at 32 +Signal received at sb_10__4_ at 88 +Signal received at cbx_10__4_ at 32 +Signal received at sb_9__4_ at 88 +Signal received at cbx_9__4_ at 32 +Signal received at sb_8__4_ at 88 +Signal received at cbx_8__4_ at 32 +Signal received at sb_7__4_ at 88 +Signal received at cbx_7__4_ at 32 +Signal received at sb_6__4_ at 88 +Signal received at cbx_6__4_ at 32 +Signal received at sb_5__4_ at 88 +Signal received at cbx_5__4_ at 32 +Signal received at sb_4__4_ at 88 +Signal received at cbx_4__4_ at 32 +Signal received at sb_3__4_ at 88 +Signal received at cbx_3__4_ at 32 +Signal received at sb_2__4_ at 88 +Signal received at cbx_2__4_ at 32 +Signal received at sb_1__4_ at 88 +Signal received at cbx_1__4_ at 32 +Signal received at sb_0__4_ at 82 +Signal received at cby_0__4_ at 3 +Signal received at grid_clb_1__4_ at 116 +Signal received at cby_1__4_ at 32 +Signal received at grid_clb_2__4_ at 116 +Signal received at cby_2__4_ at 32 +Signal received at grid_clb_3__4_ at 116 +Signal received at cby_3__4_ at 32 +Signal received at grid_clb_4__4_ at 116 +Signal received at cby_4__4_ at 32 +Signal received at grid_clb_5__4_ at 116 +Signal received at cby_5__4_ at 32 +Signal received at grid_clb_6__4_ at 116 +Signal received at cby_6__4_ at 32 +Signal received at grid_clb_7__4_ at 116 +Signal received at cby_7__4_ at 32 +Signal received at grid_clb_8__4_ at 116 +Signal received at cby_8__4_ at 32 +Signal received at grid_clb_9__4_ at 116 +Signal received at cby_9__4_ at 32 +Signal received at grid_clb_10__4_ at 116 +Signal received at cby_10__4_ at 32 +Signal received at grid_clb_11__4_ at 116 +Signal received at cby_11__4_ at 32 +Signal received at grid_clb_12__4_ at 116 +Signal received at cby_12__4_ at 35 +Signal received at sb_12__3_ at 83 +Signal received at cbx_12__3_ at 32 +Signal received at sb_11__3_ at 88 +Signal received at cbx_11__3_ at 32 +Signal received at sb_10__3_ at 88 +Signal received at cbx_10__3_ at 32 +Signal received at sb_9__3_ at 88 +Signal received at cbx_9__3_ at 32 +Signal received at sb_8__3_ at 88 +Signal received at cbx_8__3_ at 32 +Signal received at sb_7__3_ at 88 +Signal received at cbx_7__3_ at 32 +Signal received at sb_6__3_ at 88 +Signal received at cbx_6__3_ at 32 +Signal received at sb_5__3_ at 88 +Signal received at cbx_5__3_ at 32 +Signal received at sb_4__3_ at 88 +Signal received at cbx_4__3_ at 32 +Signal received at sb_3__3_ at 88 +Signal received at cbx_3__3_ at 32 +Signal received at sb_2__3_ at 88 +Signal received at cbx_2__3_ at 32 +Signal received at sb_1__3_ at 88 +Signal received at cbx_1__3_ at 32 +Signal received at sb_0__3_ at 82 +Signal received at cby_0__3_ at 3 +Signal received at grid_clb_1__3_ at 116 +Signal received at cby_1__3_ at 32 +Signal received at grid_clb_2__3_ at 116 +Signal received at cby_2__3_ at 32 +Signal received at grid_clb_3__3_ at 116 +Signal received at cby_3__3_ at 32 +Signal received at grid_clb_4__3_ at 116 +Signal received at cby_4__3_ at 32 +Signal received at grid_clb_5__3_ at 116 +Signal received at cby_5__3_ at 32 +Signal received at grid_clb_6__3_ at 116 +Signal received at cby_6__3_ at 32 +Signal received at grid_clb_7__3_ at 116 +Signal received at cby_7__3_ at 32 +Signal received at grid_clb_8__3_ at 116 +Signal received at cby_8__3_ at 32 +Signal received at grid_clb_9__3_ at 116 +Signal received at cby_9__3_ at 32 +Signal received at grid_clb_10__3_ at 116 +Signal received at cby_10__3_ at 32 +Signal received at grid_clb_11__3_ at 116 +Signal received at cby_11__3_ at 32 +Signal received at grid_clb_12__3_ at 116 +Signal received at cby_12__3_ at 35 +Signal received at sb_12__2_ at 83 +Signal received at cbx_12__2_ at 32 +Signal received at sb_11__2_ at 88 +Signal received at cbx_11__2_ at 32 +Signal received at sb_10__2_ at 88 +Signal received at cbx_10__2_ at 32 +Signal received at sb_9__2_ at 88 +Signal received at cbx_9__2_ at 32 +Signal received at sb_8__2_ at 88 +Signal received at cbx_8__2_ at 32 +Signal received at sb_7__2_ at 88 +Signal received at cbx_7__2_ at 32 +Signal received at sb_6__2_ at 88 +Signal received at cbx_6__2_ at 32 +Signal received at sb_5__2_ at 88 +Signal received at cbx_5__2_ at 32 +Signal received at sb_4__2_ at 88 +Signal received at cbx_4__2_ at 32 +Signal received at sb_3__2_ at 88 +Signal received at cbx_3__2_ at 32 +Signal received at sb_2__2_ at 88 +Signal received at cbx_2__2_ at 32 +Signal received at sb_1__2_ at 88 +Signal received at cbx_1__2_ at 32 +Signal received at sb_0__2_ at 82 +Signal received at cby_0__2_ at 3 +Signal received at grid_clb_1__2_ at 116 +Signal received at cby_1__2_ at 32 +Signal received at grid_clb_2__2_ at 116 +Signal received at cby_2__2_ at 32 +Signal received at grid_clb_3__2_ at 116 +Signal received at cby_3__2_ at 32 +Signal received at grid_clb_4__2_ at 116 +Signal received at cby_4__2_ at 32 +Signal received at grid_clb_5__2_ at 116 +Signal received at cby_5__2_ at 32 +Signal received at grid_clb_6__2_ at 116 +Signal received at cby_6__2_ at 32 +Signal received at grid_clb_7__2_ at 116 +Signal received at cby_7__2_ at 32 +Signal received at grid_clb_8__2_ at 116 +Signal received at cby_8__2_ at 32 +Signal received at grid_clb_9__2_ at 116 +Signal received at cby_9__2_ at 32 +Signal received at grid_clb_10__2_ at 116 +Signal received at cby_10__2_ at 32 +Signal received at grid_clb_11__2_ at 116 +Signal received at cby_11__2_ at 32 +Signal received at grid_clb_12__2_ at 116 +Signal received at cby_12__2_ at 35 +Signal received at sb_12__1_ at 83 +Signal received at cbx_12__1_ at 32 +Signal received at sb_11__1_ at 88 +Signal received at cbx_11__1_ at 32 +Signal received at sb_10__1_ at 88 +Signal received at cbx_10__1_ at 32 +Signal received at sb_9__1_ at 88 +Signal received at cbx_9__1_ at 32 +Signal received at sb_8__1_ at 88 +Signal received at cbx_8__1_ at 32 +Signal received at sb_7__1_ at 88 +Signal received at cbx_7__1_ at 32 +Signal received at sb_6__1_ at 88 +Signal received at cbx_6__1_ at 32 +Signal received at sb_5__1_ at 88 +Signal received at cbx_5__1_ at 32 +Signal received at sb_4__1_ at 88 +Signal received at cbx_4__1_ at 32 +Signal received at sb_3__1_ at 88 +Signal received at cbx_3__1_ at 32 +Signal received at sb_2__1_ at 88 +Signal received at cbx_2__1_ at 32 +Signal received at sb_1__1_ at 88 +Signal received at cbx_1__1_ at 32 +Signal received at sb_0__1_ at 82 +Signal received at cby_0__1_ at 3 +Signal received at grid_clb_1__1_ at 116 +Signal received at cby_1__1_ at 32 +Signal received at grid_clb_2__1_ at 116 +Signal received at cby_2__1_ at 32 +Signal received at grid_clb_3__1_ at 116 +Signal received at cby_3__1_ at 32 +Signal received at grid_clb_4__1_ at 116 +Signal received at cby_4__1_ at 32 +Signal received at grid_clb_5__1_ at 116 +Signal received at cby_5__1_ at 32 +Signal received at grid_clb_6__1_ at 116 +Signal received at cby_6__1_ at 32 +Signal received at grid_clb_7__1_ at 116 +Signal received at cby_7__1_ at 32 +Signal received at grid_clb_8__1_ at 116 +Signal received at cby_8__1_ at 32 +Signal received at grid_clb_9__1_ at 116 +Signal received at cby_9__1_ at 32 +Signal received at grid_clb_10__1_ at 116 +Signal received at cby_10__1_ at 32 +Signal received at grid_clb_11__1_ at 116 +Signal received at cby_11__1_ at 32 +Signal received at grid_clb_12__1_ at 116 +Signal received at cby_12__1_ at 35 +Signal received at sb_12__0_ at 65 +Signal received at cbx_12__0_ at 23 +Signal received at sb_11__0_ at 80 +Signal received at cbx_11__0_ at 23 +Signal received at sb_10__0_ at 80 +Signal received at cbx_10__0_ at 23 +Signal received at sb_9__0_ at 80 +Signal received at cbx_9__0_ at 23 +Signal received at sb_8__0_ at 80 +Signal received at cbx_8__0_ at 23 +Signal received at sb_7__0_ at 80 +Signal received at cbx_7__0_ at 23 +Signal received at sb_6__0_ at 80 +Signal received at cbx_6__0_ at 23 +Signal received at sb_5__0_ at 80 +Signal received at cbx_5__0_ at 23 +Signal received at sb_4__0_ at 80 +Signal received at cbx_4__0_ at 23 +Signal received at sb_3__0_ at 80 +Signal received at cbx_3__0_ at 23 +Signal received at sb_2__0_ at 80 +Signal received at cbx_2__0_ at 23 +Signal received at sb_1__0_ at 80 +Signal received at cbx_1__0_ at 23 +Signal received at sb_0__0_ at 41 +Simulation Finished in clocks 40726 +Test Passed: ConfigChainTestFull +Passed 1 tests (0 skipped) +*************************************************************************************************** +** TEST PASS/FAIL SIM TIME(NS) REAL TIME(S) RATIO(NS/S) ** +*************************************************************************************************** +** fpga_reset_hd_sky_pnr.ConfigChainTestFull PASS 407320.00 96.06 4240.25 ** +*************************************************************************************************** + +************************************************************************************* +** ERRORS : 0 ** +************************************************************************************* +** SIM TIME : 407320.00 NS ** +** REAL TIME : 96.11 S ** +** SIM / REAL TIME : 4237.94 NS/S ** +************************************************************************************* + +Shutting down... diff --git a/FPGA1212_SOFA_CHD_PNR/Verification/INIT/INIT/ConfigChainTestFull_init.v b/FPGA1212_SOFA_CHD_PNR/Verification/INIT/INIT/ConfigChainTestFull_init.v new file mode 100644 index 0000000..2c2ab83 --- /dev/null +++ b/FPGA1212_SOFA_CHD_PNR/Verification/INIT/INIT/ConfigChainTestFull_init.v @@ -0,0 +1,22 @@ + +initial begin + $dumpfile ("ccff_test.vcd"); + $dumpvars (1, + io_in[37], + io_in[36], + fpga_core_uut.prog_clk, + fpga_core_uut.Reset, + fpga_core_uut.pReset, + fpga_core_uut.sb_12__12_.ccff_head, + fpga_core_uut.sb_12__12_.ccff_tail, + fpga_core_uut.ccff_head, + fpga_core_uut.ccff_tail + ); +end + +initial begin + $dumpvars (0, + fpga_core_uut.sb_12__12_, + fpga_core_uut.sb_6__0_ + ); +end diff --git a/FPGA1212_SOFA_CHD_PNR/Verification/INIT/INIT/ScanChainTestFull_init.v b/FPGA1212_SOFA_CHD_PNR/Verification/INIT/INIT/ScanChainTestFull_init.v new file mode 100644 index 0000000..b38af20 --- /dev/null +++ b/FPGA1212_SOFA_CHD_PNR/Verification/INIT/INIT/ScanChainTestFull_init.v @@ -0,0 +1,23 @@ + +initial begin + $dumpfile ("scff_test.vcd"); + $dumpvars (1, + io_in[37], + io_in[36], + io_in[0], + fpga_core_uut.scff_Wires, + fpga_core_uut.Test_en, + + fpga_core_uut.sb_0__12_.SC_IN_TOP, + fpga_core_uut.sb_0__12_.SC_OUT_BOT, + fpga_core_uut.grid_clb_1__12_.SC_IN_TOP, + fpga_core_uut.grid_clb_1__12_.SC_OUT_BOT, + sc_head, + sc_tail + ); +end + +initial begin + $dumpvars (0, + fpga_core_uut.sb_12__12_); +end diff --git a/FPGA1212_SOFA_CHD_PNR/Verification/INIT/INIT/include_postpnr.v b/FPGA1212_SOFA_CHD_PNR/Verification/INIT/INIT/include_postpnr.v new file mode 100644 index 0000000..0f2fc34 --- /dev/null +++ b/FPGA1212_SOFA_CHD_PNR/Verification/INIT/INIT/include_postpnr.v @@ -0,0 +1,617 @@ +// +// +// +// +// +// +// +// +`timescale 1ns / 1ps +`define FUNCTIONAL 1 +`define UNIT_DELAY #0.01 + +`include "./TaskConfigCopy/FPGA1212_SOFA_CHD_task/sc_verilog/fd_hd_mux_custom_cells_tt.v" + +`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/and2b/sky130_fd_sc_hd__and2b_1.v" +`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/and2b/sky130_fd_sc_hd__and2b_2.v" +`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/and2b/sky130_fd_sc_hd__and2b_4.v" +`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/and2b/sky130_fd_sc_hd__and2b.v" +`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/and2/sky130_fd_sc_hd__and2_0.v" +`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/and2/sky130_fd_sc_hd__and2_1.v" +`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/and2/sky130_fd_sc_hd__and2_2.v" +`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/and2/sky130_fd_sc_hd__and2_4.v" +`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/and2/sky130_fd_sc_hd__and2.v" +`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/and3/sky130_fd_sc_hd__and3_1.v" +`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/and3/sky130_fd_sc_hd__and3_2.v" +`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/and3/sky130_fd_sc_hd__and3_4.v" +`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/and3/sky130_fd_sc_hd__and3.v" +`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/and4b/sky130_fd_sc_hd__and4b_1.v" +`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/and4b/sky130_fd_sc_hd__and4b_2.v" +`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/and4b/sky130_fd_sc_hd__and4b_4.v" +`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/and4b/sky130_fd_sc_hd__and4b.v" +`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/and4/sky130_fd_sc_hd__and4_1.v" +`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/and4/sky130_fd_sc_hd__and4_2.v" +`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/and4/sky130_fd_sc_hd__and4_4.v" +`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/and4/sky130_fd_sc_hd__and4.v" +`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/bufbuf/sky130_fd_sc_hd__bufbuf_16.v" +`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/bufbuf/sky130_fd_sc_hd__bufbuf_8.v" +`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/bufbuf/sky130_fd_sc_hd__bufbuf.v" +`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/bufinv/sky130_fd_sc_hd__bufinv_16.v" +`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/bufinv/sky130_fd_sc_hd__bufinv_8.v" +`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/bufinv/sky130_fd_sc_hd__bufinv.v" +`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/buf/sky130_fd_sc_hd__buf_12.v" +`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/buf/sky130_fd_sc_hd__buf_16.v" +`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/buf/sky130_fd_sc_hd__buf_1.v" +`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/buf/sky130_fd_sc_hd__buf_2.v" +`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/buf/sky130_fd_sc_hd__buf_4.v" +`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/buf/sky130_fd_sc_hd__buf_6.v" +`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/buf/sky130_fd_sc_hd__buf_8.v" +`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/buf/sky130_fd_sc_hd__buf.v" +`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/clkbuf/sky130_fd_sc_hd__clkbuf_16.v" +`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/clkbuf/sky130_fd_sc_hd__clkbuf_1.v" +`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/clkbuf/sky130_fd_sc_hd__clkbuf_2.v" +`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/clkbuf/sky130_fd_sc_hd__clkbuf_4.v" +`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/clkbuf/sky130_fd_sc_hd__clkbuf_8.v" +`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/clkbuf/sky130_fd_sc_hd__clkbuf.v" +`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/clkdlybuf4s15/sky130_fd_sc_hd__clkdlybuf4s15_1.v" +`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/clkdlybuf4s15/sky130_fd_sc_hd__clkdlybuf4s15_2.v" +`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/clkdlybuf4s15/sky130_fd_sc_hd__clkdlybuf4s15.v" +`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/clkdlybuf4s18/sky130_fd_sc_hd__clkdlybuf4s18_1.v" +`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/clkdlybuf4s18/sky130_fd_sc_hd__clkdlybuf4s18_2.v" +`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/clkdlybuf4s18/sky130_fd_sc_hd__clkdlybuf4s18.v" +`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/clkdlybuf4s25/sky130_fd_sc_hd__clkdlybuf4s25_1.v" +`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/clkdlybuf4s25/sky130_fd_sc_hd__clkdlybuf4s25_2.v" +`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/clkdlybuf4s25/sky130_fd_sc_hd__clkdlybuf4s25.v" +`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/clkdlybuf4s50/sky130_fd_sc_hd__clkdlybuf4s50_1.v" +`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/clkdlybuf4s50/sky130_fd_sc_hd__clkdlybuf4s50_2.v" +`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/clkdlybuf4s50/sky130_fd_sc_hd__clkdlybuf4s50.v" +`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/clkinvlp/sky130_fd_sc_hd__clkinvlp_2.v" +`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/clkinvlp/sky130_fd_sc_hd__clkinvlp_4.v" +`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/clkinvlp/sky130_fd_sc_hd__clkinvlp.v" +`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/clkinv/sky130_fd_sc_hd__clkinv_16.v" +`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/clkinv/sky130_fd_sc_hd__clkinv_1.v" +`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/clkinv/sky130_fd_sc_hd__clkinv_2.v" +`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/clkinv/sky130_fd_sc_hd__clkinv_4.v" +`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/clkinv/sky130_fd_sc_hd__clkinv_8.v" +`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/clkinv/sky130_fd_sc_hd__clkinv.v" +`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/conb/sky130_fd_sc_hd__conb_1.v" +`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/conb/sky130_fd_sc_hd__conb.v" +`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/decap/sky130_fd_sc_hd__decap_12.v" +`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/decap/sky130_fd_sc_hd__decap_3.v" +`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/decap/sky130_fd_sc_hd__decap_4.v" +`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/decap/sky130_fd_sc_hd__decap_6.v" +`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/decap/sky130_fd_sc_hd__decap_8.v" +`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/decap/sky130_fd_sc_hd__decap.v" +// +// +// +// +// +// +// +// +// +// +`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/dfrtp/sky130_fd_sc_hd__dfrtp_1.v" +`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/dfrtp/sky130_fd_sc_hd__dfrtp_2.v" +`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/dfrtp/sky130_fd_sc_hd__dfrtp_4.v" +`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/dfrtp/sky130_fd_sc_hd__dfrtp.v" +`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/dfsbp/sky130_fd_sc_hd__dfsbp_1.v" +`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/dfsbp/sky130_fd_sc_hd__dfsbp_2.v" +`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/dfsbp/sky130_fd_sc_hd__dfsbp.v" +`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/dfstp/sky130_fd_sc_hd__dfstp_1.v" +`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/dfstp/sky130_fd_sc_hd__dfstp_2.v" +`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/dfstp/sky130_fd_sc_hd__dfstp_4.v" +`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/dfstp/sky130_fd_sc_hd__dfstp.v" +`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/dfxbp/sky130_fd_sc_hd__dfxbp_1.v" +`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/dfxbp/sky130_fd_sc_hd__dfxbp_2.v" +`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/dfxbp/sky130_fd_sc_hd__dfxbp.v" +`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/dfxtp/sky130_fd_sc_hd__dfxtp_1.v" +`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/dfxtp/sky130_fd_sc_hd__dfxtp_2.v" +`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/dfxtp/sky130_fd_sc_hd__dfxtp_4.v" +`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/dfxtp/sky130_fd_sc_hd__dfxtp.v" +`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/diode/sky130_fd_sc_hd__diode_2.v" +`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/diode/sky130_fd_sc_hd__diode.v" +`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/dlclkp/sky130_fd_sc_hd__dlclkp_1.v" +`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/dlclkp/sky130_fd_sc_hd__dlclkp_2.v" +`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/dlclkp/sky130_fd_sc_hd__dlclkp_4.v" +`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/dlclkp/sky130_fd_sc_hd__dlclkp.v" +`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/dlrbn/sky130_fd_sc_hd__dlrbn_1.v" +`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/dlrbn/sky130_fd_sc_hd__dlrbn_2.v" +`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/dlrbn/sky130_fd_sc_hd__dlrbn.v" +`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/dlrbp/sky130_fd_sc_hd__dlrbp_1.v" +`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/dlrbp/sky130_fd_sc_hd__dlrbp_2.v" +`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/dlrbp/sky130_fd_sc_hd__dlrbp.v" +`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/dlrtn/sky130_fd_sc_hd__dlrtn_1.v" +`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/dlrtn/sky130_fd_sc_hd__dlrtn_2.v" +`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/dlrtn/sky130_fd_sc_hd__dlrtn_4.v" +`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/dlrtn/sky130_fd_sc_hd__dlrtn.v" +`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/dlrtp/sky130_fd_sc_hd__dlrtp_1.v" +`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/dlrtp/sky130_fd_sc_hd__dlrtp_2.v" +`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/dlrtp/sky130_fd_sc_hd__dlrtp_4.v" +`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/dlrtp/sky130_fd_sc_hd__dlrtp.v" +`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/dlxbn/sky130_fd_sc_hd__dlxbn_1.v" +`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/dlxbn/sky130_fd_sc_hd__dlxbn_2.v" +`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/dlxbn/sky130_fd_sc_hd__dlxbn.v" +`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/dlxbp/sky130_fd_sc_hd__dlxbp_1.v" +`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/dlxbp/sky130_fd_sc_hd__dlxbp.v" +`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/dlxtn/sky130_fd_sc_hd__dlxtn_1.v" +`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/dlxtn/sky130_fd_sc_hd__dlxtn_2.v" +`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/dlxtn/sky130_fd_sc_hd__dlxtn_4.v" +`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/dlxtn/sky130_fd_sc_hd__dlxtn.v" +`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/dlxtp/sky130_fd_sc_hd__dlxtp_1.v" +`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/dlxtp/sky130_fd_sc_hd__dlxtp.v" +`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/dlygate4sd1/sky130_fd_sc_hd__dlygate4sd1_1.v" +`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/dlygate4sd1/sky130_fd_sc_hd__dlygate4sd1.v" +`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/dlygate4sd2/sky130_fd_sc_hd__dlygate4sd2_1.v" +`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/dlygate4sd2/sky130_fd_sc_hd__dlygate4sd2.v" +`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/dlygate4sd3/sky130_fd_sc_hd__dlygate4sd3_1.v" +`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/dlygate4sd3/sky130_fd_sc_hd__dlygate4sd3.v" +`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/dlymetal6s2s/sky130_fd_sc_hd__dlymetal6s2s_1.v" +`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/dlymetal6s2s/sky130_fd_sc_hd__dlymetal6s2s.v" +`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/dlymetal6s4s/sky130_fd_sc_hd__dlymetal6s4s_1.v" +`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/dlymetal6s4s/sky130_fd_sc_hd__dlymetal6s4s.v" +`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/dlymetal6s6s/sky130_fd_sc_hd__dlymetal6s6s_1.v" +`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/dlymetal6s6s/sky130_fd_sc_hd__dlymetal6s6s.v" +`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/ebufn/sky130_fd_sc_hd__ebufn_1.v" +`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/ebufn/sky130_fd_sc_hd__ebufn_2.v" +`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/ebufn/sky130_fd_sc_hd__ebufn_4.v" +`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/ebufn/sky130_fd_sc_hd__ebufn_8.v" +`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/ebufn/sky130_fd_sc_hd__ebufn.v" +`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/edfxbp/sky130_fd_sc_hd__edfxbp_1.v" +`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/edfxbp/sky130_fd_sc_hd__edfxbp.v" +`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/edfxtp/sky130_fd_sc_hd__edfxtp_1.v" +`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/edfxtp/sky130_fd_sc_hd__edfxtp.v" +`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/einvn/sky130_fd_sc_hd__einvn_0.v" +`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/einvn/sky130_fd_sc_hd__einvn_1.v" +`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/einvn/sky130_fd_sc_hd__einvn_2.v" +`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/einvn/sky130_fd_sc_hd__einvn_4.v" +`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/einvn/sky130_fd_sc_hd__einvn_8.v" +`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/einvn/sky130_fd_sc_hd__einvn.v" +`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/einvp/sky130_fd_sc_hd__einvp_1.v" +`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/einvp/sky130_fd_sc_hd__einvp_2.v" +`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/einvp/sky130_fd_sc_hd__einvp_4.v" +`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/einvp/sky130_fd_sc_hd__einvp_8.v" +`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/einvp/sky130_fd_sc_hd__einvp.v" +`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/fahcin/sky130_fd_sc_hd__fahcin_1.v" +`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/fahcin/sky130_fd_sc_hd__fahcin.v" +`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/fahcon/sky130_fd_sc_hd__fahcon_1.v" +`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/fahcon/sky130_fd_sc_hd__fahcon.v" +`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/fah/sky130_fd_sc_hd__fah_1.v" +`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/fah/sky130_fd_sc_hd__fah.v" +`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/fa/sky130_fd_sc_hd__fa_1.v" +`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/fa/sky130_fd_sc_hd__fa_2.v" +`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/fa/sky130_fd_sc_hd__fa_4.v" +`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/fa/sky130_fd_sc_hd__fa.v" +`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/fill/sky130_fd_sc_hd__fill_1.v" +`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/fill/sky130_fd_sc_hd__fill_2.v" +`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/fill/sky130_fd_sc_hd__fill_4.v" +`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/fill/sky130_fd_sc_hd__fill_8.v" +`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/fill/sky130_fd_sc_hd__fill.v" +`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/ha/sky130_fd_sc_hd__ha_1.v" +`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/ha/sky130_fd_sc_hd__ha_2.v" +`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/ha/sky130_fd_sc_hd__ha_4.v" +`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/ha/sky130_fd_sc_hd__ha.v" +`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/inv/sky130_fd_sc_hd__inv_12.v" +`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/inv/sky130_fd_sc_hd__inv_16.v" +`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/inv/sky130_fd_sc_hd__inv_1.v" +`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/inv/sky130_fd_sc_hd__inv_2.v" +`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/inv/sky130_fd_sc_hd__inv_4.v" +`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/inv/sky130_fd_sc_hd__inv_6.v" +`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/inv/sky130_fd_sc_hd__inv_8.v" +`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/inv/sky130_fd_sc_hd__inv.v" +// +// +// +// +// +// +// +// +// +// +// +// +// +// +// +// +// +// +// +// +// +// +// +// +// +// +// +// +// +// +// +// +// +// +// +// +// +// +// +// +`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/macro_sparecell/sky130_fd_sc_hd__macro_sparecell.v" +`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/maj3/sky130_fd_sc_hd__maj3_1.v" +`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/maj3/sky130_fd_sc_hd__maj3_2.v" +`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/maj3/sky130_fd_sc_hd__maj3_4.v" +`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/maj3/sky130_fd_sc_hd__maj3.v" +`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/mux2i/sky130_fd_sc_hd__mux2i_1.v" +`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/mux2i/sky130_fd_sc_hd__mux2i_2.v" +`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/mux2i/sky130_fd_sc_hd__mux2i_4.v" +`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/mux2i/sky130_fd_sc_hd__mux2i.v" +`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/mux2/sky130_fd_sc_hd__mux2_1.v" +`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/mux2/sky130_fd_sc_hd__mux2_2.v" +`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/mux2/sky130_fd_sc_hd__mux2_4.v" +`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/mux2/sky130_fd_sc_hd__mux2_8.v" +`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/mux2/sky130_fd_sc_hd__mux2.v" +`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/mux4/sky130_fd_sc_hd__mux4_1.v" +`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/mux4/sky130_fd_sc_hd__mux4_2.v" +`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/mux4/sky130_fd_sc_hd__mux4_4.v" +`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/mux4/sky130_fd_sc_hd__mux4.v" +`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/nand2b/sky130_fd_sc_hd__nand2b_1.v" +`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/nand2b/sky130_fd_sc_hd__nand2b_2.v" +`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/nand2b/sky130_fd_sc_hd__nand2b_4.v" +`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/nand2b/sky130_fd_sc_hd__nand2b.v" +`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/nand2/sky130_fd_sc_hd__nand2_1.v" +`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/nand2/sky130_fd_sc_hd__nand2_2.v" +`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/nand2/sky130_fd_sc_hd__nand2_4.v" +`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/nand2/sky130_fd_sc_hd__nand2_8.v" +`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/nand2/sky130_fd_sc_hd__nand2.v" +`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/nand3/sky130_fd_sc_hd__nand3_1.v" +`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/nand3/sky130_fd_sc_hd__nand3_2.v" +`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/nand3/sky130_fd_sc_hd__nand3_4.v" +`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/nand3/sky130_fd_sc_hd__nand3.v" +`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/nand4b/sky130_fd_sc_hd__nand4b_1.v" +`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/nand4b/sky130_fd_sc_hd__nand4b_2.v" +`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/nand4b/sky130_fd_sc_hd__nand4b_4.v" +`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/nand4b/sky130_fd_sc_hd__nand4b.v" +`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/nand4/sky130_fd_sc_hd__nand4_1.v" +`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/nand4/sky130_fd_sc_hd__nand4_2.v" +`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/nand4/sky130_fd_sc_hd__nand4_4.v" +`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/nand4/sky130_fd_sc_hd__nand4.v" +`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/nor2b/sky130_fd_sc_hd__nor2b_1.v" +`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/nor2b/sky130_fd_sc_hd__nor2b_2.v" +`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/nor2b/sky130_fd_sc_hd__nor2b_4.v" +`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/nor2b/sky130_fd_sc_hd__nor2b.v" +`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/nor2/sky130_fd_sc_hd__nor2_1.v" +`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/nor2/sky130_fd_sc_hd__nor2_2.v" +`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/nor2/sky130_fd_sc_hd__nor2_4.v" +`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/nor2/sky130_fd_sc_hd__nor2_8.v" +`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/nor2/sky130_fd_sc_hd__nor2.v" +`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/nor3/sky130_fd_sc_hd__nor3_1.v" +`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/nor3/sky130_fd_sc_hd__nor3_2.v" +`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/nor3/sky130_fd_sc_hd__nor3_4.v" +`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/nor3/sky130_fd_sc_hd__nor3.v" +`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/nor4b/sky130_fd_sc_hd__nor4b_1.v" +`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/nor4b/sky130_fd_sc_hd__nor4b_2.v" +`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/nor4b/sky130_fd_sc_hd__nor4b_4.v" +`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/nor4b/sky130_fd_sc_hd__nor4b.v" +`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/nor4/sky130_fd_sc_hd__nor4_1.v" +`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/nor4/sky130_fd_sc_hd__nor4_2.v" +`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/nor4/sky130_fd_sc_hd__nor4_4.v" +`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/nor4/sky130_fd_sc_hd__nor4.v" +// +// +// +// +// +// +// +// +// +// +// +// +// +// +`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/sdfrtp/sky130_fd_sc_hd__sdfrtp_1.v" +`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/sdfrtp/sky130_fd_sc_hd__sdfrtp_2.v" +`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/sdfrtp/sky130_fd_sc_hd__sdfrtp_4.v" +`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/sdfrtp/sky130_fd_sc_hd__sdfrtp.v" +`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/sdfsbp/sky130_fd_sc_hd__sdfsbp_1.v" +`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/sdfsbp/sky130_fd_sc_hd__sdfsbp_2.v" +`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/sdfsbp/sky130_fd_sc_hd__sdfsbp.v" +`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/sdfstp/sky130_fd_sc_hd__sdfstp_1.v" +`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/sdfstp/sky130_fd_sc_hd__sdfstp_2.v" +`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/sdfstp/sky130_fd_sc_hd__sdfstp_4.v" +`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/sdfstp/sky130_fd_sc_hd__sdfstp.v" +`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/sdfxbp/sky130_fd_sc_hd__sdfxbp_1.v" +`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/sdfxbp/sky130_fd_sc_hd__sdfxbp_2.v" +`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/sdfxbp/sky130_fd_sc_hd__sdfxbp.v" +`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/sdfxtp/sky130_fd_sc_hd__sdfxtp_1.v" +`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/sdfxtp/sky130_fd_sc_hd__sdfxtp_2.v" +`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/sdfxtp/sky130_fd_sc_hd__sdfxtp_4.v" +`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/sdfxtp/sky130_fd_sc_hd__sdfxtp.v" +`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/sdlclkp/sky130_fd_sc_hd__sdlclkp_1.v" +`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/sdlclkp/sky130_fd_sc_hd__sdlclkp_2.v" +`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/sdlclkp/sky130_fd_sc_hd__sdlclkp_4.v" +`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/sdlclkp/sky130_fd_sc_hd__sdlclkp.v" +`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/sedfxbp/sky130_fd_sc_hd__sedfxbp_1.v" +`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/sedfxbp/sky130_fd_sc_hd__sedfxbp_2.v" +`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/sedfxbp/sky130_fd_sc_hd__sedfxbp.v" +`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/sedfxtp/sky130_fd_sc_hd__sedfxtp_1.v" +`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/sedfxtp/sky130_fd_sc_hd__sedfxtp_2.v" +`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/sedfxtp/sky130_fd_sc_hd__sedfxtp_4.v" +`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/sedfxtp/sky130_fd_sc_hd__sedfxtp.v" +`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/tap/sky130_fd_sc_hd__tap_1.v" +`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/tap/sky130_fd_sc_hd__tap_2.v" +`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/tap/sky130_fd_sc_hd__tap.v" +`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/tapvgnd2/sky130_fd_sc_hd__tapvgnd2_1.v" +`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/tapvgnd2/sky130_fd_sc_hd__tapvgnd2.v" +`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/tapvgnd/sky130_fd_sc_hd__tapvgnd_1.v" +`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/tapvgnd/sky130_fd_sc_hd__tapvgnd.v" +`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/tapvpwrvgnd/sky130_fd_sc_hd__tapvpwrvgnd_1.v" +`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/tapvpwrvgnd/sky130_fd_sc_hd__tapvpwrvgnd.v" +// +// +// +// +// +// +// +// +// +// +// +// +// +// +// +// + + + +// +// +// +// +// +// +// +// +// +// +// +// +// +// +// +// +// +// +// +// +// +// +// +// +// +// +// +// +// +// +// +// +// +// +// +// +// +// +// +// +// +// +// +// +// +// +// +// +// +// +// +// +// +// +// +// +// +// +// +// +// +// +// +// +// +// +// +// +// +// +// +// +// +// +// +// +// +// +// +// +// +// +// +// +// +// +// +// +// +// +// +// +// +// +// +// +// +// +// +// +// +// +// +// +// +`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/or4bb/sky130_fd_sc_hd__or4bb_1.v" +`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/or4bb/sky130_fd_sc_hd__or4bb_2.v" +`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/or4bb/sky130_fd_sc_hd__or4bb_4.v" +`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/or4bb/sky130_fd_sc_hd__or4bb.v" +// +// +// +// +// +// +// +// +// +// +// +// +// +// +// +// +// +// +// +// +`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/or3b/sky130_fd_sc_hd__or3b_1.v" +`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/or3b/sky130_fd_sc_hd__or3b_2.v" +`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/or3b/sky130_fd_sc_hd__or3b_4.v" +`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/or3b/sky130_fd_sc_hd__or3b.v" +// +// +// +// +// +// +// +// +// +// +// +// +// +// +// +// +// +// +// +// +// +// +// +// +// +// +// +// +// +// +// +// +// +// +// +// +// +// +// +// +// +// +// +// +// +// +// +// +// +// +// +// +// +// +// +// +// +// +// +// +// +// +// +// +// +// +// +// +// +// +// +// +// +// +// +// +// +// +// +// +// +// +// +// +// +// +// +// +// +// +`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/or2b/sky130_fd_sc_hd__or2b_1.v" +`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/or2b/sky130_fd_sc_hd__or2b_2.v" +`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/or2b/sky130_fd_sc_hd__or2b_4.v" +`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/or2b/sky130_fd_sc_hd__or2b.v" +`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/or2/sky130_fd_sc_hd__or2_0.v" +`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/or2/sky130_fd_sc_hd__or2_1.v" +`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/or2/sky130_fd_sc_hd__or2_2.v" +`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/or2/sky130_fd_sc_hd__or2_4.v" +`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/or2/sky130_fd_sc_hd__or2.v" +`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/or3/sky130_fd_sc_hd__or3_1.v" +`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/or3/sky130_fd_sc_hd__or3_2.v" +`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/or3/sky130_fd_sc_hd__or3_4.v" +`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/or3/sky130_fd_sc_hd__or3.v" +`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/or4b/sky130_fd_sc_hd__or4b_1.v" +`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/or4b/sky130_fd_sc_hd__or4b_2.v" +`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/or4b/sky130_fd_sc_hd__or4b_4.v" +`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/or4b/sky130_fd_sc_hd__or4b.v" +`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/or4/sky130_fd_sc_hd__or4_1.v" +`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/or4/sky130_fd_sc_hd__or4_2.v" +`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/or4/sky130_fd_sc_hd__or4_4.v" +`include "/research/ece/lnis/USERS/ggore/PDKs/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/or4/sky130_fd_sc_hd__or4.v" diff --git a/FPGA1212_SOFA_CHD_PNR/Verification/INIT/INIT/sample_init.v b/FPGA1212_SOFA_CHD_PNR/Verification/INIT/INIT/sample_init.v new file mode 100644 index 0000000..592a0e4 --- /dev/null +++ b/FPGA1212_SOFA_CHD_PNR/Verification/INIT/INIT/sample_init.v @@ -0,0 +1,45 @@ + +initial begin + $dumpfile ("ccff_test.vcd"); + $dumpvars (1, prog_clk_pad, + prog_clk, + ccff_head_pad, + ccff_head, + fpga_core_uut.sb_2__2_.ccff_tail, + fpga_core_uut.cbx_2__2_.ccff_tail, + fpga_core_uut.grid_io_top_2__3_.ccff_tail, + fpga_core_uut.sb_1__2_.ccff_tail, + fpga_core_uut.cbx_1__2_.ccff_tail, + fpga_core_uut.grid_io_top_1__3_.ccff_tail, + fpga_core_uut.sb_0__2_.ccff_tail, + fpga_core_uut.cby_0__2_.ccff_tail, + fpga_core_uut.grid_io_left_0__2_.ccff_tail, + fpga_core_uut.grid_clb_1__2_.ccff_tail, + fpga_core_uut.cby_1__2_.ccff_tail, + fpga_core_uut.grid_clb_2__2_.ccff_tail, + fpga_core_uut.cby_2__2_.ccff_tail, + fpga_core_uut.grid_io_right_3__2_.ccff_tail, + fpga_core_uut.sb_2__1_.ccff_tail, + fpga_core_uut.cbx_2__1_.ccff_tail, + fpga_core_uut.sb_1__1_.ccff_tail, + fpga_core_uut.cbx_1__1_.ccff_tail, + fpga_core_uut.sb_0__1_.ccff_tail, + fpga_core_uut.cby_0__1_.ccff_tail, + fpga_core_uut.grid_io_left_0__1_.ccff_tail, + fpga_core_uut.grid_clb_1__1_.ccff_tail, + fpga_core_uut.cby_1__1_.ccff_tail, + fpga_core_uut.grid_clb_2__1_.ccff_tail, + fpga_core_uut.cby_2__1_.ccff_tail, + fpga_core_uut.grid_io_right_3__1_.ccff_tail, + fpga_core_uut.sb_2__0_.ccff_tail, + fpga_core_uut.cbx_2__0_.ccff_tail, + fpga_core_uut.grid_io_bottom_2__0_.ccff_tail, + fpga_core_uut.sb_1__0_.ccff_tail, + fpga_core_uut.cbx_1__0_.ccff_tail, + fpga_core_uut.grid_io_bottom_1__0_.ccff_tail, + fpga_core_uut.sb_0__0_.ccff_tail, + ccff_tail_pad, + ccff_tail); +end + + diff --git a/FPGA1212_SOFA_CHD_PNR/Verification/Makefile b/FPGA1212_SOFA_CHD_PNR/Verification/Makefile new file mode 100644 index 0000000..d01e6dd --- /dev/null +++ b/FPGA1212_SOFA_CHD_PNR/Verification/Makefile @@ -0,0 +1,95 @@ + +## = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +## Verification makefile for FPGA1212_RESET_HD_SKY_PNR (Caravel-QLSOFA-HD) +## = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = + +SHELL=bash +PYTHON_EXEC=python3.8 +RERUN = 0 +TB = top +OPTIONS = +SIM = modelsim +TEST_FILE = fpga_reset_hd_sky_pnr + +.SILENT: +.ONESHELL: + +## Copy all the POSTPnR files from realease directory +UpdatePostPnRNetlist: + source ../config.sh + DESIGN_NAME=$${TOP_MODULE:-$${DESIGN_NAME}} + echo "Collecting files $${DESIGN_NAME}" + cp ../pnr/$${DESIGN_NAME}/outputs_icc2/$${DESIGN_NAME}_icv_in_design.pt.v . || \ + cp ../$${DESIGN_NAME}/outputs_icc2/$${DESIGN_NAME}_icv_in_design.pt.v . || : + + +## Create symbolic links and run test +RunPostPnRTest: + source ../config.sh + INCLUDE_POSTPNR=$${INCLUDE_POSTPNR:-include_postpnr} + DESIGN_NAME=$${TOP_MODULE:-$${DESIGN_NAME}} + VerificationFile=$${TEST_FILE:-${TEST_FILE}} + # = = = = = = = = = = = = = = Log Information = = = = = = = = = = = = + echo "DESIGN_NAME = $${DESIGN_NAME}" + echo "VerificationFile = $${DESIGN_NAME}" + echo "INCLUDE_FILE = $${INCLUDE_POSTPNR}" + # = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = + echo $${VerificationFile} + if [ ! -f "./$${VerificationFile}.py" ]; then + echo "Test file not found $${VerificationFile}.py" + fi + echo "Using test file $${VerificationFile}.py" + Tests=`grep -A 1 "^@cocotb.test" ./$${VerificationFile}.py | grep "def" | sed "s/.*def \(.*\)(.*/\1/g"` + select RUN_TB in $${Tests} + do + echo "Running $${RUN_TB} Test" + if [[ -d "$${RUN_TB}_run" ]] && [[ -z "$${RERUN}" ]]; then + echo "Skipping copying source, which will skip the compilations"; + cp *_tests.py ./$${RUN_TB}_run; + cd $${RUN_TB}_run; break; + fi + + # = = = = = = = = = = = Prepare Netlist = = = = = = = = = = = = = = + # = = = = = = = = = = = Copy python test = = = = = = = = = = = = = + mkdir -p "$${RUN_TB}_run" + cp $${VerificationFile}.py ./$${RUN_TB}_run + cp $${DESIGN_NAME}_icv_in_design.pt.v ./$${RUN_TB}_run/$${DESIGN_NAME}_cocosim.v + + TaskDir=`readlink -f ../*_Verilog/TaskConfigCopy` + TaskDir2=`readlink -f ../*_task` + if [ -d "$$TaskDir" ]; then + rm -rf ./$${RUN_TB}_run/TaskConfigCopy && ln -s $${TaskDir} ./$${RUN_TB}_run + elif [ -d "$$TaskDir2" ]; then + TaskDir=`readlink -f ../*_task` + rm -rf ./$${RUN_TB}_run/TaskConfigCopy && ln -s $${TaskDir} ./$${RUN_TB}_run/TaskConfigCopy + else + echo "Task configuration directory not found" + fi + # = = = = = = = = = = = Enter Run Directory = = = = = = = = = = = = = + cd $${RUN_TB}_run + cp ../INIT/$${INCLUDE_POSTPNR}.v ./fabric_netlists_cocosim.v + echo "\`include \"$$(readlink -f $${DESIGN_NAME}_cocosim.v)\"" >> ./fabric_netlists_cocosim.v + + # = = = = = = = = = = = Insert Init Signals = = = = = = = = = = = = + if test -f "../INIT/$${RUN_TB}_init.v"; then + echo "Found Initialization file [../INIT/$${RUN_TB}_init.v]" + modLineNo=$$(grep -n "module fpga_top" $${DESIGN_NAME}_cocosim.v | cut -f1 -d:) + echo $${modLineNo} + sed -i "$${modLineNo},\$${/endmodule/d}" $${DESIGN_NAME}_cocosim.v + cat ../INIT/$${RUN_TB}_init.v >> $${DESIGN_NAME}_cocosim.v + printf "\nendmodule" >> $${DESIGN_NAME}_cocosim.v + else + echo "No Initialization file found [../INIT/$${RUN_TB}_init.v]" + fi + + # = = = = = = = = Create Makefile to run = = = = = = = = = = = = = = + echo "TOPLEVEL_LANG = verilog" > Makefile + echo "VERILOG_SOURCES = fabric_netlists_cocosim.v" >> Makefile + echo "TOPLEVEL = $${DESIGN_NAME}" >> Makefile + echo "MODULE = $${VerificationFile}" >> Makefile + echo "TESTCASE = $${RUN_TB}" >> Makefile + echo "" >> Makefile + echo "include $(shell cocotb-config --makefiles)/Makefile.sim" >> Makefile + break + done + if [ -z "$$DRY_RUN" ]; then make SIM=$${SIM:-${SIM}}; fi \ No newline at end of file diff --git a/FPGA1212_SOFA_CHD_PNR/Verification/ScanChainTestFull_run/run.log b/FPGA1212_SOFA_CHD_PNR/Verification/ScanChainTestFull_run/run.log new file mode 100644 index 0000000..7554182 --- /dev/null +++ b/FPGA1212_SOFA_CHD_PNR/Verification/ScanChainTestFull_run/run.log @@ -0,0 +1,167 @@ +Found test fpga_reset_hd_sky_pnr.ScanChainTestFull +Running test 1/1: ScanChainTestFull +Starting test: "ScanChainTestFull" +Description: None +Signal received at grid_clb_1__12_ at 8 +Signal received at grid_clb_1__11_ at 8 +Signal received at grid_clb_1__10_ at 8 +Signal received at grid_clb_1__9_ at 8 +Signal received at grid_clb_1__8_ at 8 +Signal received at grid_clb_1__7_ at 8 +Signal received at grid_clb_1__6_ at 8 +Signal received at grid_clb_1__5_ at 8 +Signal received at grid_clb_1__4_ at 8 +Signal received at grid_clb_1__3_ at 8 +Signal received at grid_clb_1__2_ at 8 +Signal received at grid_clb_1__1_ at 8 +Signal received at grid_clb_2__1_ at 8 +Signal received at grid_clb_2__2_ at 8 +Signal received at grid_clb_2__3_ at 8 +Signal received at grid_clb_2__4_ at 8 +Signal received at grid_clb_2__5_ at 8 +Signal received at grid_clb_2__6_ at 8 +Signal received at grid_clb_2__7_ at 8 +Signal received at grid_clb_2__8_ at 8 +Signal received at grid_clb_2__9_ at 8 +Signal received at grid_clb_2__10_ at 8 +Signal received at grid_clb_2__11_ at 8 +Signal received at grid_clb_2__12_ at 8 +Signal received at grid_clb_3__12_ at 8 +Signal received at grid_clb_3__11_ at 9 +Signal received at grid_clb_3__10_ at 8 +Signal received at grid_clb_3__9_ at 8 +Signal received at grid_clb_3__8_ at 8 +Signal received at grid_clb_3__7_ at 8 +Signal received at grid_clb_3__6_ at 8 +Signal received at grid_clb_3__5_ at 8 +Signal received at grid_clb_3__4_ at 8 +Signal received at grid_clb_3__3_ at 8 +Signal received at grid_clb_3__2_ at 8 +Signal received at grid_clb_3__1_ at 8 +Signal received at grid_clb_4__1_ at 8 +Signal received at grid_clb_4__2_ at 8 +Signal received at grid_clb_4__3_ at 8 +Signal received at grid_clb_4__4_ at 8 +Signal received at grid_clb_4__5_ at 8 +Signal received at grid_clb_4__6_ at 8 +Signal received at grid_clb_4__7_ at 8 +Signal received at grid_clb_4__8_ at 8 +Signal received at grid_clb_4__9_ at 8 +Signal received at grid_clb_4__10_ at 8 +Signal received at grid_clb_4__11_ at 8 +Signal received at grid_clb_4__12_ at 8 +Signal received at grid_clb_5__12_ at 8 +Signal received at grid_clb_5__11_ at 8 +Signal received at grid_clb_5__10_ at 8 +Signal received at grid_clb_5__9_ at 8 +Signal received at grid_clb_5__8_ at 8 +Signal received at grid_clb_5__7_ at 8 +Signal received at grid_clb_5__6_ at 8 +Signal received at grid_clb_5__5_ at 8 +Signal received at grid_clb_5__4_ at 8 +Signal received at grid_clb_5__3_ at 8 +Signal received at grid_clb_5__2_ at 8 +Signal received at grid_clb_5__1_ at 8 +Signal received at grid_clb_6__1_ at 8 +Signal received at grid_clb_6__2_ at 8 +Signal received at grid_clb_6__3_ at 8 +Signal received at grid_clb_6__4_ at 8 +Signal received at grid_clb_6__5_ at 8 +Signal received at grid_clb_6__6_ at 8 +Signal received at grid_clb_6__7_ at 8 +Signal received at grid_clb_6__8_ at 8 +Signal received at grid_clb_6__9_ at 8 +Signal received at grid_clb_6__10_ at 8 +Signal received at grid_clb_6__11_ at 8 +Signal received at grid_clb_6__12_ at 8 +Signal received at grid_clb_7__12_ at 8 +Signal received at grid_clb_7__11_ at 8 +Signal received at grid_clb_7__10_ at 8 +Signal received at grid_clb_7__9_ at 8 +Signal received at grid_clb_7__8_ at 8 +Signal received at grid_clb_7__7_ at 8 +Signal received at grid_clb_7__6_ at 8 +Signal received at grid_clb_7__5_ at 8 +Signal received at grid_clb_7__4_ at 8 +Signal received at grid_clb_7__3_ at 8 +Signal received at grid_clb_7__2_ at 8 +Signal received at grid_clb_7__1_ at 8 +Signal received at grid_clb_8__1_ at 8 +Signal received at grid_clb_8__2_ at 8 +Signal received at grid_clb_8__3_ at 8 +Signal received at grid_clb_8__4_ at 8 +Signal received at grid_clb_8__5_ at 8 +Signal received at grid_clb_8__6_ at 8 +Signal received at grid_clb_8__7_ at 8 +Signal received at grid_clb_8__8_ at 8 +Signal received at grid_clb_8__9_ at 8 +Signal received at grid_clb_8__10_ at 8 +Signal received at grid_clb_8__11_ at 8 +Signal received at grid_clb_8__12_ at 8 +Signal received at grid_clb_9__12_ at 8 +Signal received at grid_clb_9__11_ at 8 +Signal received at grid_clb_9__10_ at 8 +Signal received at grid_clb_9__9_ at 8 +Signal received at grid_clb_9__8_ at 8 +Signal received at grid_clb_9__7_ at 8 +Signal received at grid_clb_9__6_ at 8 +Signal received at grid_clb_9__5_ at 8 +Signal received at grid_clb_9__4_ at 8 +Signal received at grid_clb_9__3_ at 8 +Signal received at grid_clb_9__2_ at 8 +Signal received at grid_clb_9__1_ at 8 +Signal received at grid_clb_10__1_ at 8 +Signal received at grid_clb_10__2_ at 8 +Signal received at grid_clb_10__3_ at 8 +Signal received at grid_clb_10__4_ at 8 +Signal received at grid_clb_10__5_ at 8 +Signal received at grid_clb_10__6_ at 8 +Signal received at grid_clb_10__7_ at 8 +Signal received at grid_clb_10__8_ at 8 +Signal received at grid_clb_10__9_ at 8 +Signal received at grid_clb_10__10_ at 8 +Signal received at grid_clb_10__11_ at 8 +Signal received at grid_clb_10__12_ at 8 +Signal received at grid_clb_11__12_ at 8 +Signal received at grid_clb_11__11_ at 8 +Signal received at grid_clb_11__10_ at 8 +Signal received at grid_clb_11__9_ at 8 +Signal received at grid_clb_11__8_ at 8 +Signal received at grid_clb_11__7_ at 8 +Signal received at grid_clb_11__6_ at 8 +Signal received at grid_clb_11__5_ at 8 +Signal received at grid_clb_11__4_ at 8 +Signal received at grid_clb_11__3_ at 8 +Signal received at grid_clb_11__2_ at 8 +Signal received at grid_clb_11__1_ at 8 +Signal received at grid_clb_12__1_ at 8 +Signal received at grid_clb_12__2_ at 8 +Signal received at grid_clb_12__3_ at 8 +Signal received at grid_clb_12__4_ at 8 +Signal received at grid_clb_12__5_ at 8 +Signal received at grid_clb_12__6_ at 8 +Signal received at grid_clb_12__7_ at 8 +Signal received at grid_clb_12__8_ at 8 +Signal received at grid_clb_12__9_ at 8 +Signal received at grid_clb_12__10_ at 8 +Signal received at grid_clb_12__11_ at 8 +Signal received at grid_clb_12__12_ at 8 +Simulation Finished in clocks 1152 +Per Grid 8.0 +Test Passed: ScanChainTestFull +Passed 1 tests (0 skipped) +************************************************************************************************* +** TEST PASS/FAIL SIM TIME(NS) REAL TIME(S) RATIO(NS/S) ** +************************************************************************************************* +** fpga_reset_hd_sky_pnr.ScanChainTestFull PASS 11580.00 2.35 4936.74 ** +************************************************************************************************* + +************************************************************************************* +** ERRORS : 0 ** +************************************************************************************* +** SIM TIME : 11580.00 NS ** +** REAL TIME : 2.39 S ** +** SIM / REAL TIME : 4848.92 NS/S ** +************************************************************************************* + +Shutting down... diff --git a/FPGA1212_SOFA_CHD_PNR/Verification/ScanChainTestFull_run/scff_test.vcd b/FPGA1212_SOFA_CHD_PNR/Verification/ScanChainTestFull_run/scff_test.vcd new file mode 100644 index 0000000..6fc4bcf --- /dev/null +++ b/FPGA1212_SOFA_CHD_PNR/Verification/ScanChainTestFull_run/scff_test.vcd @@ -0,0 +1,29683 @@ +$date + Tue Dec 8 15:56:21 2020 +$end +$version + QuestaSim Version 2019.4 +$end +$timescale + 1ps +$end + +$scope module fpga_top $end +$var wire 1 ! io_in [37] $end +$var wire 1 " io_in [36] $end +$var wire 1 # io_in [0] $end + +$scope module fpga_core_uut $end +$var wire 1 $ scff_Wires [317] $end +$var wire 1 % scff_Wires [316] $end +$var wire 1 & scff_Wires [315] $end +$var wire 1 ' scff_Wires [314] $end +$var wire 1 ( scff_Wires [313] $end +$var wire 1 ) scff_Wires [312] $end +$var wire 1 * scff_Wires [311] $end +$var wire 1 + scff_Wires [310] $end +$var wire 1 , scff_Wires [309] $end +$var wire 1 - scff_Wires [308] $end +$var wire 1 . scff_Wires [307] $end +$var wire 1 / scff_Wires [306] $end +$var wire 1 0 scff_Wires [305] $end +$var wire 1 1 scff_Wires [304] $end +$var wire 1 2 scff_Wires [303] $end +$var wire 1 3 scff_Wires [302] $end +$var wire 1 4 scff_Wires [301] $end +$var wire 1 5 scff_Wires [300] $end +$var wire 1 6 scff_Wires [299] $end +$var wire 1 7 scff_Wires [298] $end +$var wire 1 8 scff_Wires [297] $end +$var wire 1 9 scff_Wires [296] $end +$var wire 1 : scff_Wires [295] $end +$var wire 1 ; scff_Wires [294] $end +$var wire 1 < scff_Wires [293] $end +$var wire 1 = scff_Wires [292] $end +$var wire 1 > scff_Wires [291] $end +$var wire 1 ? scff_Wires [290] $end +$var wire 1 @ scff_Wires [289] $end +$var wire 1 A scff_Wires [288] $end +$var wire 1 B scff_Wires [287] $end +$var wire 1 C scff_Wires [286] $end +$var wire 1 D scff_Wires [285] $end +$var wire 1 E scff_Wires [284] $end +$var wire 1 F scff_Wires [283] $end +$var wire 1 G scff_Wires [282] $end +$var wire 1 H scff_Wires [281] $end +$var wire 1 I scff_Wires [280] $end +$var wire 1 J scff_Wires [279] $end +$var wire 1 K scff_Wires [278] $end +$var wire 1 L scff_Wires [277] $end +$var wire 1 M scff_Wires [276] $end +$var wire 1 N scff_Wires [275] $end +$var wire 1 O scff_Wires [274] $end +$var wire 1 P scff_Wires [273] $end +$var wire 1 Q scff_Wires [272] $end +$var wire 1 R scff_Wires [271] $end +$var wire 1 S scff_Wires [270] $end +$var wire 1 T scff_Wires [269] $end +$var wire 1 U scff_Wires [268] $end +$var wire 1 V scff_Wires [267] $end +$var wire 1 W scff_Wires [266] $end +$var wire 1 X scff_Wires [265] $end +$var wire 1 Y scff_Wires [264] $end +$var wire 1 Z scff_Wires [263] $end +$var wire 1 [ scff_Wires [262] $end +$var wire 1 \ scff_Wires [261] $end +$var wire 1 ] scff_Wires [260] $end +$var wire 1 ^ scff_Wires [259] $end +$var wire 1 _ scff_Wires [258] $end +$var wire 1 ` scff_Wires [257] $end +$var wire 1 a scff_Wires [256] $end +$var wire 1 b scff_Wires [255] $end +$var wire 1 c scff_Wires [254] $end +$var wire 1 d scff_Wires [253] $end +$var wire 1 e scff_Wires [252] $end +$var wire 1 f scff_Wires [251] $end +$var wire 1 g scff_Wires [250] $end +$var wire 1 h scff_Wires [249] $end +$var wire 1 i scff_Wires [248] $end +$var wire 1 j scff_Wires [247] $end +$var wire 1 k scff_Wires [246] $end +$var wire 1 l scff_Wires [245] $end +$var wire 1 m scff_Wires [244] $end +$var wire 1 n scff_Wires [243] $end +$var wire 1 o scff_Wires [242] $end +$var wire 1 p scff_Wires [241] $end +$var wire 1 q scff_Wires [240] $end +$var wire 1 r scff_Wires [239] $end +$var wire 1 s scff_Wires [238] $end +$var wire 1 t scff_Wires [237] $end +$var wire 1 u scff_Wires [236] $end +$var wire 1 v scff_Wires [235] $end +$var wire 1 w scff_Wires [234] $end +$var wire 1 x scff_Wires [233] $end +$var wire 1 y scff_Wires [232] $end +$var wire 1 z scff_Wires [231] $end +$var wire 1 { scff_Wires [230] $end +$var wire 1 | scff_Wires [229] $end +$var wire 1 } scff_Wires [228] $end +$var wire 1 ~ scff_Wires [227] $end +$var wire 1 !! scff_Wires [226] $end +$var wire 1 "! scff_Wires [225] $end +$var wire 1 #! scff_Wires [224] $end +$var wire 1 $! scff_Wires [223] $end +$var wire 1 %! scff_Wires [222] $end +$var wire 1 &! scff_Wires [221] $end +$var wire 1 '! scff_Wires [220] $end +$var wire 1 (! scff_Wires [219] $end +$var wire 1 )! scff_Wires [218] $end +$var wire 1 *! scff_Wires [217] $end +$var wire 1 +! scff_Wires [216] $end +$var wire 1 ,! scff_Wires [215] $end +$var wire 1 -! scff_Wires [214] $end +$var wire 1 .! scff_Wires [213] $end +$var wire 1 /! scff_Wires [212] $end +$var wire 1 0! scff_Wires [211] $end +$var wire 1 1! scff_Wires [210] $end +$var wire 1 2! scff_Wires [209] $end +$var wire 1 3! scff_Wires [208] $end +$var wire 1 4! scff_Wires [207] $end +$var wire 1 5! scff_Wires [206] $end +$var wire 1 6! scff_Wires [205] $end +$var wire 1 7! scff_Wires [204] $end +$var wire 1 8! scff_Wires [203] $end +$var wire 1 9! scff_Wires [202] $end +$var wire 1 :! scff_Wires [201] $end +$var wire 1 ;! scff_Wires [200] $end +$var wire 1 ! scff_Wires [197] $end +$var wire 1 ?! scff_Wires [196] $end +$var wire 1 @! scff_Wires [195] $end +$var wire 1 A! scff_Wires [194] $end +$var wire 1 B! scff_Wires [193] $end +$var wire 1 C! scff_Wires [192] $end +$var wire 1 D! scff_Wires [191] $end +$var wire 1 E! scff_Wires [190] $end +$var wire 1 F! scff_Wires [189] $end +$var wire 1 G! scff_Wires [188] $end +$var wire 1 H! scff_Wires [187] $end +$var wire 1 I! scff_Wires [186] $end +$var wire 1 J! scff_Wires [185] $end +$var wire 1 K! scff_Wires [184] $end +$var wire 1 L! scff_Wires [183] $end +$var wire 1 M! scff_Wires [182] $end +$var wire 1 N! scff_Wires [181] $end +$var wire 1 O! scff_Wires [180] $end +$var wire 1 P! scff_Wires [179] $end +$var wire 1 Q! scff_Wires [178] $end +$var wire 1 R! scff_Wires [177] $end +$var wire 1 S! scff_Wires [176] $end +$var wire 1 T! scff_Wires [175] $end +$var wire 1 U! scff_Wires [174] $end +$var wire 1 V! scff_Wires [173] $end +$var wire 1 W! scff_Wires [172] $end +$var wire 1 X! scff_Wires [171] $end +$var wire 1 Y! scff_Wires [170] $end +$var wire 1 Z! scff_Wires [169] $end +$var wire 1 [! scff_Wires [168] $end +$var wire 1 \! scff_Wires [167] $end +$var wire 1 ]! scff_Wires [166] $end +$var wire 1 ^! scff_Wires [165] $end +$var wire 1 _! scff_Wires [164] $end +$var wire 1 `! scff_Wires [163] $end +$var wire 1 a! scff_Wires [162] $end +$var wire 1 b! scff_Wires [161] $end +$var wire 1 c! scff_Wires [160] $end +$var wire 1 d! scff_Wires [159] $end +$var wire 1 e! scff_Wires [158] $end +$var wire 1 f! scff_Wires [157] $end +$var wire 1 g! scff_Wires [156] $end +$var wire 1 h! scff_Wires [155] $end +$var wire 1 i! scff_Wires [154] $end +$var wire 1 j! scff_Wires [153] $end +$var wire 1 k! scff_Wires [152] $end +$var wire 1 l! scff_Wires [151] $end +$var wire 1 m! scff_Wires [150] $end +$var wire 1 n! scff_Wires [149] $end +$var wire 1 o! scff_Wires [148] $end +$var wire 1 p! scff_Wires [147] $end +$var wire 1 q! scff_Wires [146] $end +$var wire 1 r! scff_Wires [145] $end +$var wire 1 s! scff_Wires [144] $end +$var wire 1 t! scff_Wires [143] $end +$var wire 1 u! scff_Wires [142] $end +$var wire 1 v! scff_Wires [141] $end +$var wire 1 w! scff_Wires [140] $end +$var wire 1 x! scff_Wires [139] $end +$var wire 1 y! scff_Wires [138] $end +$var wire 1 z! scff_Wires [137] $end +$var wire 1 {! scff_Wires [136] $end +$var wire 1 |! scff_Wires [135] $end +$var wire 1 }! scff_Wires [134] $end +$var wire 1 ~! scff_Wires [133] $end +$var wire 1 !" scff_Wires [132] $end +$var wire 1 "" scff_Wires [131] $end +$var wire 1 #" scff_Wires [130] $end +$var wire 1 $" scff_Wires [129] $end +$var wire 1 %" scff_Wires [128] $end +$var wire 1 &" scff_Wires [127] $end +$var wire 1 '" scff_Wires [126] $end +$var wire 1 (" scff_Wires [125] $end +$var wire 1 )" scff_Wires [124] $end +$var wire 1 *" scff_Wires [123] $end +$var wire 1 +" scff_Wires [122] $end +$var wire 1 ," scff_Wires [121] $end +$var wire 1 -" scff_Wires [120] $end +$var wire 1 ." scff_Wires [119] $end +$var wire 1 /" scff_Wires [118] $end +$var wire 1 0" scff_Wires [117] $end +$var wire 1 1" scff_Wires [116] $end +$var wire 1 2" scff_Wires [115] $end +$var wire 1 3" scff_Wires [114] $end +$var wire 1 4" scff_Wires [113] $end +$var wire 1 5" scff_Wires [112] $end +$var wire 1 6" scff_Wires [111] $end +$var wire 1 7" scff_Wires [110] $end +$var wire 1 8" scff_Wires [109] $end +$var wire 1 9" scff_Wires [108] $end +$var wire 1 :" scff_Wires [107] $end +$var wire 1 ;" scff_Wires [106] $end +$var wire 1 <" scff_Wires [105] $end +$var wire 1 =" scff_Wires [104] $end +$var wire 1 >" scff_Wires [103] $end +$var wire 1 ?" scff_Wires [102] $end +$var wire 1 @" scff_Wires [101] $end +$var wire 1 A" scff_Wires [100] $end +$var wire 1 B" scff_Wires [99] $end +$var wire 1 C" scff_Wires [98] $end +$var wire 1 D" scff_Wires [97] $end +$var wire 1 E" scff_Wires [96] $end +$var wire 1 F" scff_Wires [95] $end +$var wire 1 G" scff_Wires [94] $end +$var wire 1 H" scff_Wires [93] $end +$var wire 1 I" scff_Wires [92] $end +$var wire 1 J" scff_Wires [91] $end +$var wire 1 K" scff_Wires [90] $end +$var wire 1 L" scff_Wires [89] $end +$var wire 1 M" scff_Wires [88] $end +$var wire 1 N" scff_Wires [87] $end +$var wire 1 O" scff_Wires [86] $end +$var wire 1 P" scff_Wires [85] $end +$var wire 1 Q" scff_Wires [84] $end +$var wire 1 R" scff_Wires [83] $end +$var wire 1 S" scff_Wires [82] $end +$var wire 1 T" scff_Wires [81] $end +$var wire 1 U" scff_Wires [80] $end +$var wire 1 V" scff_Wires [79] $end +$var wire 1 W" scff_Wires [78] $end +$var wire 1 X" scff_Wires [77] $end +$var wire 1 Y" scff_Wires [76] $end +$var wire 1 Z" scff_Wires [75] $end +$var wire 1 [" scff_Wires [74] $end +$var wire 1 \" scff_Wires [73] $end +$var wire 1 ]" scff_Wires [72] $end +$var wire 1 ^" scff_Wires [71] $end +$var wire 1 _" scff_Wires [70] $end +$var wire 1 `" scff_Wires [69] $end +$var wire 1 a" scff_Wires [68] $end +$var wire 1 b" scff_Wires [67] $end +$var wire 1 c" scff_Wires [66] $end +$var wire 1 d" scff_Wires [65] $end +$var wire 1 e" scff_Wires [64] $end +$var wire 1 f" scff_Wires [63] $end +$var wire 1 g" scff_Wires [62] $end +$var wire 1 h" scff_Wires [61] $end +$var wire 1 i" scff_Wires [60] $end +$var wire 1 j" scff_Wires [59] $end +$var wire 1 k" scff_Wires [58] $end +$var wire 1 l" scff_Wires [57] $end +$var wire 1 m" scff_Wires [56] $end +$var wire 1 n" scff_Wires [55] $end +$var wire 1 o" scff_Wires [54] $end +$var wire 1 p" scff_Wires [53] $end +$var wire 1 q" scff_Wires [52] $end +$var wire 1 r" scff_Wires [51] $end +$var wire 1 s" scff_Wires [50] $end +$var wire 1 t" scff_Wires [49] $end +$var wire 1 u" scff_Wires [48] $end +$var wire 1 v" scff_Wires [47] $end +$var wire 1 w" scff_Wires [46] $end +$var wire 1 x" scff_Wires [45] $end +$var wire 1 y" scff_Wires [44] $end +$var wire 1 z" scff_Wires [43] $end +$var wire 1 {" scff_Wires [42] $end +$var wire 1 |" scff_Wires [41] $end +$var wire 1 }" scff_Wires [40] $end +$var wire 1 ~" scff_Wires [39] $end +$var wire 1 !# scff_Wires [38] $end +$var wire 1 "# scff_Wires [37] $end +$var wire 1 ## scff_Wires [36] $end +$var wire 1 $# scff_Wires [35] $end +$var wire 1 %# scff_Wires [34] $end +$var wire 1 &# scff_Wires [33] $end +$var wire 1 '# scff_Wires [32] $end +$var wire 1 (# scff_Wires [31] $end +$var wire 1 )# scff_Wires [30] $end +$var wire 1 *# scff_Wires [29] $end +$var wire 1 +# scff_Wires [28] $end +$var wire 1 ,# scff_Wires [27] $end +$var wire 1 -# scff_Wires [26] $end +$var wire 1 .# scff_Wires [25] $end +$var wire 1 /# scff_Wires [24] $end +$var wire 1 0# scff_Wires [23] $end +$var wire 1 1# scff_Wires [22] $end +$var wire 1 2# scff_Wires [21] $end +$var wire 1 3# scff_Wires [20] $end +$var wire 1 4# scff_Wires [19] $end +$var wire 1 5# scff_Wires [18] $end +$var wire 1 6# scff_Wires [17] $end +$var wire 1 7# scff_Wires [16] $end +$var wire 1 8# scff_Wires [15] $end +$var wire 1 9# scff_Wires [14] $end +$var wire 1 :# scff_Wires [13] $end +$var wire 1 ;# scff_Wires [12] $end +$var wire 1 <# scff_Wires [11] $end +$var wire 1 =# scff_Wires [10] $end +$var wire 1 ># scff_Wires [9] $end +$var wire 1 ?# scff_Wires [8] $end +$var wire 1 @# scff_Wires [7] $end +$var wire 1 A# scff_Wires [6] $end +$var wire 1 B# scff_Wires [5] $end +$var wire 1 C# scff_Wires [4] $end +$var wire 1 D# scff_Wires [3] $end +$var wire 1 E# scff_Wires [2] $end +$var wire 1 F# scff_Wires [1] $end +$var wire 1 G# scff_Wires [0] $end +$var wire 1 # Test_en [0] $end + +$scope module sb_0__12_ $end +$var wire 1 H# SC_IN_TOP $end +$var wire 1 G# SC_OUT_BOT $end +$upscope $end + +$scope module grid_clb_1__12_ $end +$var wire 1 F# SC_IN_TOP $end +$var wire 1 E# SC_OUT_BOT $end +$upscope $end +$upscope $end +$var wire 1 I# sc_head $end +$var wire 1 J# sc_tail $end + +$scope module fpga_core_uut $end + +$scope module sb_12__12_ $end +$var wire 1 K# pReset [0] $end +$var wire 1 L# chany_bottom_in [0] $end +$var wire 1 M# chany_bottom_in [1] $end +$var wire 1 N# chany_bottom_in [2] $end +$var wire 1 O# chany_bottom_in [3] $end +$var wire 1 P# chany_bottom_in [4] $end +$var wire 1 Q# chany_bottom_in [5] $end +$var wire 1 R# chany_bottom_in [6] $end +$var wire 1 S# chany_bottom_in [7] $end +$var wire 1 T# chany_bottom_in [8] $end +$var wire 1 U# chany_bottom_in [9] $end +$var wire 1 V# chany_bottom_in [10] $end +$var wire 1 W# chany_bottom_in [11] $end +$var wire 1 X# chany_bottom_in [12] $end +$var wire 1 Y# chany_bottom_in [13] $end +$var wire 1 Z# chany_bottom_in [14] $end +$var wire 1 [# chany_bottom_in [15] $end +$var wire 1 \# chany_bottom_in [16] $end +$var wire 1 ]# chany_bottom_in [17] $end +$var wire 1 ^# chany_bottom_in [18] $end +$var wire 1 _# chany_bottom_in [19] $end +$var wire 1 `# chany_bottom_in [20] $end +$var wire 1 a# chany_bottom_in [21] $end +$var wire 1 b# chany_bottom_in [22] $end +$var wire 1 c# chany_bottom_in [23] $end +$var wire 1 d# chany_bottom_in [24] $end +$var wire 1 e# chany_bottom_in [25] $end +$var wire 1 f# chany_bottom_in [26] $end +$var wire 1 g# chany_bottom_in [27] $end +$var wire 1 h# chany_bottom_in [28] $end +$var wire 1 i# chany_bottom_in [29] $end +$var wire 1 j# bottom_right_grid_pin_1_ [0] $end +$var wire 1 k# bottom_left_grid_pin_44_ [0] $end +$var wire 1 l# bottom_left_grid_pin_45_ [0] $end +$var wire 1 m# bottom_left_grid_pin_46_ [0] $end +$var wire 1 n# bottom_left_grid_pin_47_ [0] $end +$var wire 1 o# bottom_left_grid_pin_48_ [0] $end +$var wire 1 p# bottom_left_grid_pin_49_ [0] $end +$var wire 1 q# bottom_left_grid_pin_50_ [0] $end +$var wire 1 r# bottom_left_grid_pin_51_ [0] $end +$var wire 1 s# chanx_left_in [0] $end +$var wire 1 t# chanx_left_in [1] $end +$var wire 1 u# chanx_left_in [2] $end +$var wire 1 v# chanx_left_in [3] $end +$var wire 1 w# chanx_left_in [4] $end +$var wire 1 x# chanx_left_in [5] $end +$var wire 1 y# chanx_left_in [6] $end +$var wire 1 z# chanx_left_in [7] $end +$var wire 1 {# chanx_left_in [8] $end +$var wire 1 |# chanx_left_in [9] $end +$var wire 1 }# chanx_left_in [10] $end +$var wire 1 ~# chanx_left_in [11] $end +$var wire 1 !$ chanx_left_in [12] $end +$var wire 1 "$ chanx_left_in [13] $end +$var wire 1 #$ chanx_left_in [14] $end +$var wire 1 $$ chanx_left_in [15] $end +$var wire 1 %$ chanx_left_in [16] $end +$var wire 1 &$ chanx_left_in [17] $end +$var wire 1 '$ chanx_left_in [18] $end +$var wire 1 ($ chanx_left_in [19] $end +$var wire 1 )$ chanx_left_in [20] $end +$var wire 1 *$ chanx_left_in [21] $end +$var wire 1 +$ chanx_left_in [22] $end +$var wire 1 ,$ chanx_left_in [23] $end +$var wire 1 -$ chanx_left_in [24] $end +$var wire 1 .$ chanx_left_in [25] $end +$var wire 1 /$ chanx_left_in [26] $end +$var wire 1 0$ chanx_left_in [27] $end +$var wire 1 1$ chanx_left_in [28] $end +$var wire 1 2$ chanx_left_in [29] $end +$var wire 1 3$ left_top_grid_pin_1_ [0] $end +$var wire 1 4$ left_bottom_grid_pin_36_ [0] $end +$var wire 1 5$ left_bottom_grid_pin_37_ [0] $end +$var wire 1 6$ left_bottom_grid_pin_38_ [0] $end +$var wire 1 7$ left_bottom_grid_pin_39_ [0] $end +$var wire 1 8$ left_bottom_grid_pin_40_ [0] $end +$var wire 1 9$ left_bottom_grid_pin_41_ [0] $end +$var wire 1 :$ left_bottom_grid_pin_42_ [0] $end +$var wire 1 ;$ left_bottom_grid_pin_43_ [0] $end +$var wire 1 <$ ccff_head [0] $end +$var wire 1 =$ chany_bottom_out [0] $end +$var wire 1 >$ chany_bottom_out [1] $end +$var wire 1 ?$ chany_bottom_out [2] $end +$var wire 1 @$ chany_bottom_out [3] $end +$var wire 1 A$ chany_bottom_out [4] $end +$var wire 1 B$ chany_bottom_out [5] $end +$var wire 1 C$ chany_bottom_out [6] $end +$var wire 1 D$ chany_bottom_out [7] $end +$var wire 1 E$ chany_bottom_out [8] $end +$var wire 1 F$ chany_bottom_out [9] $end +$var wire 1 G$ chany_bottom_out [10] $end +$var wire 1 H$ chany_bottom_out [11] $end +$var wire 1 I$ chany_bottom_out [12] $end +$var wire 1 J$ chany_bottom_out [13] $end +$var wire 1 K$ chany_bottom_out [14] $end +$var wire 1 L$ chany_bottom_out [15] $end +$var wire 1 M$ chany_bottom_out [16] $end +$var wire 1 N$ chany_bottom_out [17] $end +$var wire 1 O$ chany_bottom_out [18] $end +$var wire 1 P$ chany_bottom_out [19] $end +$var wire 1 Q$ chany_bottom_out [20] $end +$var wire 1 R$ chany_bottom_out [21] $end +$var wire 1 S$ chany_bottom_out [22] $end +$var wire 1 T$ chany_bottom_out [23] $end +$var wire 1 U$ chany_bottom_out [24] $end +$var wire 1 V$ chany_bottom_out [25] $end +$var wire 1 W$ chany_bottom_out [26] $end +$var wire 1 X$ chany_bottom_out [27] $end +$var wire 1 Y$ chany_bottom_out [28] $end +$var wire 1 Z$ chany_bottom_out [29] $end +$var wire 1 [$ chanx_left_out [0] $end +$var wire 1 \$ chanx_left_out [1] $end +$var wire 1 ]$ chanx_left_out [2] $end +$var wire 1 ^$ chanx_left_out [3] $end +$var wire 1 _$ chanx_left_out [4] $end +$var wire 1 `$ chanx_left_out [5] $end +$var wire 1 a$ chanx_left_out [6] $end +$var wire 1 b$ chanx_left_out [7] $end +$var wire 1 c$ chanx_left_out [8] $end +$var wire 1 d$ chanx_left_out [9] $end +$var wire 1 e$ chanx_left_out [10] $end +$var wire 1 f$ chanx_left_out [11] $end +$var wire 1 g$ chanx_left_out [12] $end +$var wire 1 h$ chanx_left_out [13] $end +$var wire 1 i$ chanx_left_out [14] $end +$var wire 1 j$ chanx_left_out [15] $end +$var wire 1 k$ chanx_left_out [16] $end +$var wire 1 l$ chanx_left_out [17] $end +$var wire 1 m$ chanx_left_out [18] $end +$var wire 1 n$ chanx_left_out [19] $end +$var wire 1 o$ chanx_left_out [20] $end +$var wire 1 p$ chanx_left_out [21] $end +$var wire 1 q$ chanx_left_out [22] $end +$var wire 1 r$ chanx_left_out [23] $end +$var wire 1 s$ chanx_left_out [24] $end +$var wire 1 t$ chanx_left_out [25] $end +$var wire 1 u$ chanx_left_out [26] $end +$var wire 1 v$ chanx_left_out [27] $end +$var wire 1 w$ chanx_left_out [28] $end +$var wire 1 x$ chanx_left_out [29] $end +$var wire 1 y$ ccff_tail [0] $end +$var wire 1 $ SC_IN_BOT $end +$var wire 1 z$ SC_OUT_BOT $end +$var wire 1 {$ pReset_W_in $end +$var wire 1 |$ prog_clk_0_S_in $end +$var wire 1 }$ prog_clk [0] $end +$var wire 1 ~$ prog_clk_0 $end +$var wire 1 !% mux_2level_tapbuf_size2_0_sram [0] $end +$var wire 1 "% mux_2level_tapbuf_size2_0_sram [1] $end +$var wire 1 #% mux_2level_tapbuf_size2_10_sram [0] $end +$var wire 1 $% mux_2level_tapbuf_size2_10_sram [1] $end +$var wire 1 %% mux_2level_tapbuf_size2_11_sram [0] $end +$var wire 1 &% mux_2level_tapbuf_size2_11_sram [1] $end +$var wire 1 '% mux_2level_tapbuf_size2_12_sram [0] $end +$var wire 1 (% mux_2level_tapbuf_size2_12_sram [1] $end +$var wire 1 )% mux_2level_tapbuf_size2_13_sram [0] $end +$var wire 1 *% mux_2level_tapbuf_size2_13_sram [1] $end +$var wire 1 +% mux_2level_tapbuf_size2_14_sram [0] $end +$var wire 1 ,% mux_2level_tapbuf_size2_14_sram [1] $end +$var wire 1 -% mux_2level_tapbuf_size2_15_sram [0] $end +$var wire 1 .% mux_2level_tapbuf_size2_15_sram [1] $end +$var wire 1 /% mux_2level_tapbuf_size2_16_sram [0] $end +$var wire 1 0% mux_2level_tapbuf_size2_16_sram [1] $end +$var wire 1 1% mux_2level_tapbuf_size2_17_sram [0] $end +$var wire 1 2% mux_2level_tapbuf_size2_17_sram [1] $end +$var wire 1 3% mux_2level_tapbuf_size2_18_sram [0] $end +$var wire 1 4% mux_2level_tapbuf_size2_18_sram [1] $end +$var wire 1 5% mux_2level_tapbuf_size2_19_sram [0] $end +$var wire 1 6% mux_2level_tapbuf_size2_19_sram [1] $end +$var wire 1 7% mux_2level_tapbuf_size2_1_sram [0] $end +$var wire 1 8% mux_2level_tapbuf_size2_1_sram [1] $end +$var wire 1 9% mux_2level_tapbuf_size2_20_sram [0] $end +$var wire 1 :% mux_2level_tapbuf_size2_20_sram [1] $end +$var wire 1 ;% mux_2level_tapbuf_size2_21_sram [0] $end +$var wire 1 <% mux_2level_tapbuf_size2_21_sram [1] $end +$var wire 1 =% mux_2level_tapbuf_size2_22_sram [0] $end +$var wire 1 >% mux_2level_tapbuf_size2_22_sram [1] $end +$var wire 1 ?% mux_2level_tapbuf_size2_23_sram [0] $end +$var wire 1 @% mux_2level_tapbuf_size2_23_sram [1] $end +$var wire 1 A% mux_2level_tapbuf_size2_24_sram [0] $end +$var wire 1 B% mux_2level_tapbuf_size2_24_sram [1] $end +$var wire 1 C% mux_2level_tapbuf_size2_25_sram [0] $end +$var wire 1 D% mux_2level_tapbuf_size2_25_sram [1] $end +$var wire 1 E% mux_2level_tapbuf_size2_26_sram [0] $end +$var wire 1 F% mux_2level_tapbuf_size2_26_sram [1] $end +$var wire 1 G% mux_2level_tapbuf_size2_27_sram [0] $end +$var wire 1 H% mux_2level_tapbuf_size2_27_sram [1] $end +$var wire 1 I% mux_2level_tapbuf_size2_28_sram [0] $end +$var wire 1 J% mux_2level_tapbuf_size2_28_sram [1] $end +$var wire 1 K% mux_2level_tapbuf_size2_29_sram [0] $end +$var wire 1 L% mux_2level_tapbuf_size2_29_sram [1] $end +$var wire 1 M% mux_2level_tapbuf_size2_2_sram [0] $end +$var wire 1 N% mux_2level_tapbuf_size2_2_sram [1] $end +$var wire 1 O% mux_2level_tapbuf_size2_30_sram [0] $end +$var wire 1 P% mux_2level_tapbuf_size2_30_sram [1] $end +$var wire 1 Q% mux_2level_tapbuf_size2_31_sram [0] $end +$var wire 1 R% mux_2level_tapbuf_size2_31_sram [1] $end +$var wire 1 S% mux_2level_tapbuf_size2_32_sram [0] $end +$var wire 1 T% mux_2level_tapbuf_size2_32_sram [1] $end +$var wire 1 U% mux_2level_tapbuf_size2_33_sram [0] $end +$var wire 1 V% mux_2level_tapbuf_size2_33_sram [1] $end +$var wire 1 W% mux_2level_tapbuf_size2_34_sram [0] $end +$var wire 1 X% mux_2level_tapbuf_size2_34_sram [1] $end +$var wire 1 Y% mux_2level_tapbuf_size2_35_sram [0] $end +$var wire 1 Z% mux_2level_tapbuf_size2_35_sram [1] $end +$var wire 1 [% mux_2level_tapbuf_size2_36_sram [0] $end +$var wire 1 \% mux_2level_tapbuf_size2_36_sram [1] $end +$var wire 1 ]% mux_2level_tapbuf_size2_3_sram [0] $end +$var wire 1 ^% mux_2level_tapbuf_size2_3_sram [1] $end +$var wire 1 _% mux_2level_tapbuf_size2_4_sram [0] $end +$var wire 1 `% mux_2level_tapbuf_size2_4_sram [1] $end +$var wire 1 a% mux_2level_tapbuf_size2_5_sram [0] $end +$var wire 1 b% mux_2level_tapbuf_size2_5_sram [1] $end +$var wire 1 c% mux_2level_tapbuf_size2_6_sram [0] $end +$var wire 1 d% mux_2level_tapbuf_size2_6_sram [1] $end +$var wire 1 e% mux_2level_tapbuf_size2_7_sram [0] $end +$var wire 1 f% mux_2level_tapbuf_size2_7_sram [1] $end +$var wire 1 g% mux_2level_tapbuf_size2_8_sram [0] $end +$var wire 1 h% mux_2level_tapbuf_size2_8_sram [1] $end +$var wire 1 i% mux_2level_tapbuf_size2_9_sram [0] $end +$var wire 1 j% mux_2level_tapbuf_size2_9_sram [1] $end +$var wire 1 k% mux_2level_tapbuf_size2_mem_0_ccff_tail [0] $end +$var wire 1 l% mux_2level_tapbuf_size2_mem_10_ccff_tail [0] $end +$var wire 1 m% mux_2level_tapbuf_size2_mem_11_ccff_tail [0] $end +$var wire 1 n% mux_2level_tapbuf_size2_mem_12_ccff_tail [0] $end +$var wire 1 o% mux_2level_tapbuf_size2_mem_13_ccff_tail [0] $end +$var wire 1 p% mux_2level_tapbuf_size2_mem_14_ccff_tail [0] $end +$var wire 1 q% mux_2level_tapbuf_size2_mem_15_ccff_tail [0] $end +$var wire 1 r% mux_2level_tapbuf_size2_mem_16_ccff_tail [0] $end +$var wire 1 s% mux_2level_tapbuf_size2_mem_17_ccff_tail [0] $end +$var wire 1 t% mux_2level_tapbuf_size2_mem_18_ccff_tail [0] $end +$var wire 1 u% mux_2level_tapbuf_size2_mem_19_ccff_tail [0] $end +$var wire 1 v% mux_2level_tapbuf_size2_mem_1_ccff_tail [0] $end +$var wire 1 w% mux_2level_tapbuf_size2_mem_20_ccff_tail [0] $end +$var wire 1 x% mux_2level_tapbuf_size2_mem_21_ccff_tail [0] $end +$var wire 1 y% mux_2level_tapbuf_size2_mem_22_ccff_tail [0] $end +$var wire 1 z% mux_2level_tapbuf_size2_mem_23_ccff_tail [0] $end +$var wire 1 {% mux_2level_tapbuf_size2_mem_24_ccff_tail [0] $end +$var wire 1 |% mux_2level_tapbuf_size2_mem_25_ccff_tail [0] $end +$var wire 1 }% mux_2level_tapbuf_size2_mem_26_ccff_tail [0] $end +$var wire 1 ~% mux_2level_tapbuf_size2_mem_27_ccff_tail [0] $end +$var wire 1 !& mux_2level_tapbuf_size2_mem_28_ccff_tail [0] $end +$var wire 1 "& mux_2level_tapbuf_size2_mem_29_ccff_tail [0] $end +$var wire 1 #& mux_2level_tapbuf_size2_mem_2_ccff_tail [0] $end +$var wire 1 $& mux_2level_tapbuf_size2_mem_30_ccff_tail [0] $end +$var wire 1 %& mux_2level_tapbuf_size2_mem_31_ccff_tail [0] $end +$var wire 1 && mux_2level_tapbuf_size2_mem_32_ccff_tail [0] $end +$var wire 1 '& mux_2level_tapbuf_size2_mem_33_ccff_tail [0] $end +$var wire 1 (& mux_2level_tapbuf_size2_mem_34_ccff_tail [0] $end +$var wire 1 )& mux_2level_tapbuf_size2_mem_35_ccff_tail [0] $end +$var wire 1 *& mux_2level_tapbuf_size2_mem_3_ccff_tail [0] $end +$var wire 1 +& mux_2level_tapbuf_size2_mem_4_ccff_tail [0] $end +$var wire 1 ,& mux_2level_tapbuf_size2_mem_5_ccff_tail [0] $end +$var wire 1 -& mux_2level_tapbuf_size2_mem_6_ccff_tail [0] $end +$var wire 1 .& mux_2level_tapbuf_size2_mem_7_ccff_tail [0] $end +$var wire 1 /& mux_2level_tapbuf_size2_mem_8_ccff_tail [0] $end +$var wire 1 0& mux_2level_tapbuf_size2_mem_9_ccff_tail [0] $end +$var wire 1 1& mux_2level_tapbuf_size3_0_sram [0] $end +$var wire 1 2& mux_2level_tapbuf_size3_0_sram [1] $end +$var wire 1 3& mux_2level_tapbuf_size3_1_sram [0] $end +$var wire 1 4& mux_2level_tapbuf_size3_1_sram [1] $end +$var wire 1 5& mux_2level_tapbuf_size3_2_sram [0] $end +$var wire 1 6& mux_2level_tapbuf_size3_2_sram [1] $end +$var wire 1 7& mux_2level_tapbuf_size3_3_sram [0] $end +$var wire 1 8& mux_2level_tapbuf_size3_3_sram [1] $end +$var wire 1 9& mux_2level_tapbuf_size3_mem_0_ccff_tail [0] $end +$var wire 1 :& mux_2level_tapbuf_size3_mem_1_ccff_tail [0] $end +$var wire 1 ;& mux_2level_tapbuf_size3_mem_2_ccff_tail [0] $end +$var wire 1 <& mux_2level_tapbuf_size3_mem_3_ccff_tail [0] $end +$var wire 1 =& mux_2level_tapbuf_size4_0_sram [0] $end +$var wire 1 >& mux_2level_tapbuf_size4_0_sram [1] $end +$var wire 1 ?& mux_2level_tapbuf_size4_0_sram [2] $end +$var wire 1 @& mux_2level_tapbuf_size4_0_sram [3] $end +$var wire 1 A& mux_2level_tapbuf_size4_10_sram [0] $end +$var wire 1 B& mux_2level_tapbuf_size4_10_sram [1] $end +$var wire 1 C& mux_2level_tapbuf_size4_10_sram [2] $end +$var wire 1 D& mux_2level_tapbuf_size4_10_sram [3] $end +$var wire 1 E& mux_2level_tapbuf_size4_11_sram [0] $end +$var wire 1 F& mux_2level_tapbuf_size4_11_sram [1] $end +$var wire 1 G& mux_2level_tapbuf_size4_11_sram [2] $end +$var wire 1 H& mux_2level_tapbuf_size4_11_sram [3] $end +$var wire 1 I& mux_2level_tapbuf_size4_1_sram [0] $end +$var wire 1 J& mux_2level_tapbuf_size4_1_sram [1] $end +$var wire 1 K& mux_2level_tapbuf_size4_1_sram [2] $end +$var wire 1 L& mux_2level_tapbuf_size4_1_sram [3] $end +$var wire 1 M& mux_2level_tapbuf_size4_2_sram [0] $end +$var wire 1 N& mux_2level_tapbuf_size4_2_sram [1] $end +$var wire 1 O& mux_2level_tapbuf_size4_2_sram [2] $end +$var wire 1 P& mux_2level_tapbuf_size4_2_sram [3] $end +$var wire 1 Q& mux_2level_tapbuf_size4_3_sram [0] $end +$var wire 1 R& mux_2level_tapbuf_size4_3_sram [1] $end +$var wire 1 S& mux_2level_tapbuf_size4_3_sram [2] $end +$var wire 1 T& mux_2level_tapbuf_size4_3_sram [3] $end +$var wire 1 U& mux_2level_tapbuf_size4_4_sram [0] $end +$var wire 1 V& mux_2level_tapbuf_size4_4_sram [1] $end +$var wire 1 W& mux_2level_tapbuf_size4_4_sram [2] $end +$var wire 1 X& mux_2level_tapbuf_size4_4_sram [3] $end +$var wire 1 Y& mux_2level_tapbuf_size4_5_sram [0] $end +$var wire 1 Z& mux_2level_tapbuf_size4_5_sram [1] $end +$var wire 1 [& mux_2level_tapbuf_size4_5_sram [2] $end +$var wire 1 \& mux_2level_tapbuf_size4_5_sram [3] $end +$var wire 1 ]& mux_2level_tapbuf_size4_6_sram [0] $end +$var wire 1 ^& mux_2level_tapbuf_size4_6_sram [1] $end +$var wire 1 _& mux_2level_tapbuf_size4_6_sram [2] $end +$var wire 1 `& mux_2level_tapbuf_size4_6_sram [3] $end +$var wire 1 a& mux_2level_tapbuf_size4_7_sram [0] $end +$var wire 1 b& mux_2level_tapbuf_size4_7_sram [1] $end +$var wire 1 c& mux_2level_tapbuf_size4_7_sram [2] $end +$var wire 1 d& mux_2level_tapbuf_size4_7_sram [3] $end +$var wire 1 e& mux_2level_tapbuf_size4_8_sram [0] $end +$var wire 1 f& mux_2level_tapbuf_size4_8_sram [1] $end +$var wire 1 g& mux_2level_tapbuf_size4_8_sram [2] $end +$var wire 1 h& mux_2level_tapbuf_size4_8_sram [3] $end +$var wire 1 i& mux_2level_tapbuf_size4_9_sram [0] $end +$var wire 1 j& mux_2level_tapbuf_size4_9_sram [1] $end +$var wire 1 k& mux_2level_tapbuf_size4_9_sram [2] $end +$var wire 1 l& mux_2level_tapbuf_size4_9_sram [3] $end +$var wire 1 m& mux_2level_tapbuf_size4_mem_0_ccff_tail [0] $end +$var wire 1 n& mux_2level_tapbuf_size4_mem_10_ccff_tail [0] $end +$var wire 1 o& mux_2level_tapbuf_size4_mem_11_ccff_tail [0] $end +$var wire 1 p& mux_2level_tapbuf_size4_mem_1_ccff_tail [0] $end +$var wire 1 q& mux_2level_tapbuf_size4_mem_2_ccff_tail [0] $end +$var wire 1 r& mux_2level_tapbuf_size4_mem_3_ccff_tail [0] $end +$var wire 1 s& mux_2level_tapbuf_size4_mem_4_ccff_tail [0] $end +$var wire 1 t& mux_2level_tapbuf_size4_mem_5_ccff_tail [0] $end +$var wire 1 u& mux_2level_tapbuf_size4_mem_6_ccff_tail [0] $end +$var wire 1 v& mux_2level_tapbuf_size4_mem_7_ccff_tail [0] $end +$var wire 1 w& mux_2level_tapbuf_size4_mem_8_ccff_tail [0] $end +$var wire 1 x& mux_2level_tapbuf_size4_mem_9_ccff_tail [0] $end +$var wire 1 y& SYNOPSYS_UNCONNECTED_1 $end +$var wire 1 z& SYNOPSYS_UNCONNECTED_2 $end +$var wire 1 {& SYNOPSYS_UNCONNECTED_3 $end +$var wire 1 |& SYNOPSYS_UNCONNECTED_4 $end +$var wire 1 }& optlc_net_178 $end +$var wire 1 ~& SYNOPSYS_UNCONNECTED_5 $end +$var wire 1 !' SYNOPSYS_UNCONNECTED_6 $end +$var wire 1 "' SYNOPSYS_UNCONNECTED_7 $end +$var wire 1 #' SYNOPSYS_UNCONNECTED_8 $end +$var wire 1 $' SYNOPSYS_UNCONNECTED_9 $end +$var wire 1 %' SYNOPSYS_UNCONNECTED_10 $end +$var wire 1 &' SYNOPSYS_UNCONNECTED_11 $end +$var wire 1 '' SYNOPSYS_UNCONNECTED_12 $end +$var wire 1 (' optlc_net_174 $end +$var wire 1 )' SYNOPSYS_UNCONNECTED_13 $end +$var wire 1 *' SYNOPSYS_UNCONNECTED_14 $end +$var wire 1 +' SYNOPSYS_UNCONNECTED_15 $end +$var wire 1 ,' SYNOPSYS_UNCONNECTED_16 $end +$var wire 1 -' SYNOPSYS_UNCONNECTED_17 $end +$var wire 1 .' SYNOPSYS_UNCONNECTED_18 $end +$var wire 1 /' SYNOPSYS_UNCONNECTED_19 $end +$var wire 1 0' SYNOPSYS_UNCONNECTED_20 $end +$var wire 1 1' optlc_net_177 $end +$var wire 1 2' SYNOPSYS_UNCONNECTED_21 $end +$var wire 1 3' SYNOPSYS_UNCONNECTED_22 $end +$var wire 1 4' SYNOPSYS_UNCONNECTED_23 $end +$var wire 1 5' SYNOPSYS_UNCONNECTED_24 $end +$var wire 1 6' SYNOPSYS_UNCONNECTED_25 $end +$var wire 1 7' SYNOPSYS_UNCONNECTED_26 $end +$var wire 1 8' SYNOPSYS_UNCONNECTED_27 $end +$var wire 1 9' SYNOPSYS_UNCONNECTED_28 $end +$var wire 1 :' SYNOPSYS_UNCONNECTED_29 $end +$var wire 1 ;' SYNOPSYS_UNCONNECTED_30 $end +$var wire 1 <' SYNOPSYS_UNCONNECTED_31 $end +$var wire 1 =' SYNOPSYS_UNCONNECTED_32 $end +$var wire 1 >' SYNOPSYS_UNCONNECTED_33 $end +$var wire 1 ?' SYNOPSYS_UNCONNECTED_34 $end +$var wire 1 @' SYNOPSYS_UNCONNECTED_35 $end +$var wire 1 A' SYNOPSYS_UNCONNECTED_36 $end +$var wire 1 B' SYNOPSYS_UNCONNECTED_37 $end +$var wire 1 C' SYNOPSYS_UNCONNECTED_38 $end +$var wire 1 D' SYNOPSYS_UNCONNECTED_39 $end +$var wire 1 E' SYNOPSYS_UNCONNECTED_40 $end +$var wire 1 F' SYNOPSYS_UNCONNECTED_41 $end +$var wire 1 G' SYNOPSYS_UNCONNECTED_42 $end +$var wire 1 H' SYNOPSYS_UNCONNECTED_43 $end +$var wire 1 I' SYNOPSYS_UNCONNECTED_44 $end +$var wire 1 J' SYNOPSYS_UNCONNECTED_45 $end +$var wire 1 K' SYNOPSYS_UNCONNECTED_46 $end +$var wire 1 L' SYNOPSYS_UNCONNECTED_47 $end +$var wire 1 M' SYNOPSYS_UNCONNECTED_48 $end +$var wire 1 N' SYNOPSYS_UNCONNECTED_49 $end +$var wire 1 O' SYNOPSYS_UNCONNECTED_50 $end +$var wire 1 P' SYNOPSYS_UNCONNECTED_51 $end +$var wire 1 Q' SYNOPSYS_UNCONNECTED_52 $end +$var wire 1 R' optlc_net_175 $end +$var wire 1 S' SYNOPSYS_UNCONNECTED_53 $end +$var wire 1 T' SYNOPSYS_UNCONNECTED_54 $end +$var wire 1 U' SYNOPSYS_UNCONNECTED_55 $end +$var wire 1 V' SYNOPSYS_UNCONNECTED_56 $end +$var wire 1 W' SYNOPSYS_UNCONNECTED_57 $end +$var wire 1 X' SYNOPSYS_UNCONNECTED_58 $end +$var wire 1 Y' optlc_net_179 $end +$var wire 1 Z' SYNOPSYS_UNCONNECTED_59 $end +$var wire 1 [' SYNOPSYS_UNCONNECTED_60 $end +$var wire 1 \' SYNOPSYS_UNCONNECTED_61 $end +$var wire 1 ]' SYNOPSYS_UNCONNECTED_62 $end +$var wire 1 ^' SYNOPSYS_UNCONNECTED_63 $end +$var wire 1 _' SYNOPSYS_UNCONNECTED_64 $end +$var wire 1 `' SYNOPSYS_UNCONNECTED_65 $end +$var wire 1 a' SYNOPSYS_UNCONNECTED_66 $end +$var wire 1 b' SYNOPSYS_UNCONNECTED_67 $end +$var wire 1 c' SYNOPSYS_UNCONNECTED_68 $end +$var wire 1 d' SYNOPSYS_UNCONNECTED_69 $end +$var wire 1 e' SYNOPSYS_UNCONNECTED_70 $end +$var wire 1 f' SYNOPSYS_UNCONNECTED_71 $end +$var wire 1 g' SYNOPSYS_UNCONNECTED_72 $end +$var wire 1 h' SYNOPSYS_UNCONNECTED_73 $end +$var wire 1 i' SYNOPSYS_UNCONNECTED_74 $end +$var wire 1 j' SYNOPSYS_UNCONNECTED_75 $end +$var wire 1 k' SYNOPSYS_UNCONNECTED_76 $end +$var wire 1 l' SYNOPSYS_UNCONNECTED_77 $end +$var wire 1 m' SYNOPSYS_UNCONNECTED_78 $end +$var wire 1 n' SYNOPSYS_UNCONNECTED_79 $end +$var wire 1 o' SYNOPSYS_UNCONNECTED_80 $end +$var wire 1 p' optlc_net_176 $end +$var wire 1 q' SYNOPSYS_UNCONNECTED_81 $end +$var wire 1 r' SYNOPSYS_UNCONNECTED_82 $end +$var wire 1 s' SYNOPSYS_UNCONNECTED_83 $end +$var wire 1 t' SYNOPSYS_UNCONNECTED_84 $end +$var wire 1 u' SYNOPSYS_UNCONNECTED_85 $end +$var wire 1 v' SYNOPSYS_UNCONNECTED_86 $end +$var wire 1 w' SYNOPSYS_UNCONNECTED_87 $end +$var wire 1 x' SYNOPSYS_UNCONNECTED_88 $end +$var wire 1 y' SYNOPSYS_UNCONNECTED_89 $end +$var wire 1 z' SYNOPSYS_UNCONNECTED_90 $end +$var wire 1 {' SYNOPSYS_UNCONNECTED_91 $end +$var wire 1 |' SYNOPSYS_UNCONNECTED_92 $end +$var wire 1 }' SYNOPSYS_UNCONNECTED_93 $end +$var wire 1 ~' SYNOPSYS_UNCONNECTED_94 $end +$var wire 1 !( SYNOPSYS_UNCONNECTED_95 $end +$var wire 1 "( SYNOPSYS_UNCONNECTED_96 $end +$var wire 1 #( SYNOPSYS_UNCONNECTED_97 $end +$var wire 1 $( SYNOPSYS_UNCONNECTED_98 $end +$var wire 1 %( SYNOPSYS_UNCONNECTED_99 $end +$var wire 1 &( SYNOPSYS_UNCONNECTED_100 $end +$var wire 1 '( SYNOPSYS_UNCONNECTED_101 $end +$var wire 1 (( SYNOPSYS_UNCONNECTED_102 $end +$var wire 1 )( SYNOPSYS_UNCONNECTED_103 $end +$var wire 1 *( SYNOPSYS_UNCONNECTED_104 $end +$var wire 1 +( SYNOPSYS_UNCONNECTED_105 $end +$var wire 1 ,( SYNOPSYS_UNCONNECTED_106 $end +$var wire 1 -( SYNOPSYS_UNCONNECTED_107 $end +$var wire 1 .( SYNOPSYS_UNCONNECTED_108 $end +$var wire 1 /( SYNOPSYS_UNCONNECTED_109 $end +$var wire 1 0( SYNOPSYS_UNCONNECTED_110 $end +$var wire 1 1( SYNOPSYS_UNCONNECTED_111 $end +$var wire 1 2( SYNOPSYS_UNCONNECTED_112 $end +$var wire 1 3( SYNOPSYS_UNCONNECTED_113 $end +$var wire 1 4( SYNOPSYS_UNCONNECTED_114 $end +$var wire 1 5( SYNOPSYS_UNCONNECTED_115 $end +$var wire 1 6( SYNOPSYS_UNCONNECTED_116 $end +$var wire 1 7( SYNOPSYS_UNCONNECTED_117 $end +$var wire 1 8( SYNOPSYS_UNCONNECTED_118 $end +$var wire 1 9( SYNOPSYS_UNCONNECTED_119 $end +$var wire 1 :( SYNOPSYS_UNCONNECTED_120 $end +$var wire 1 ;( SYNOPSYS_UNCONNECTED_121 $end +$var wire 1 <( SYNOPSYS_UNCONNECTED_122 $end +$var wire 1 =( SYNOPSYS_UNCONNECTED_123 $end +$var wire 1 >( SYNOPSYS_UNCONNECTED_124 $end +$var wire 1 ?( SYNOPSYS_UNCONNECTED_125 $end +$var wire 1 @( SYNOPSYS_UNCONNECTED_126 $end +$var wire 1 A( SYNOPSYS_UNCONNECTED_127 $end +$var wire 1 B( SYNOPSYS_UNCONNECTED_128 $end +$var wire 1 C( SYNOPSYS_UNCONNECTED_129 $end +$var wire 1 D( SYNOPSYS_UNCONNECTED_130 $end +$var wire 1 E( SYNOPSYS_UNCONNECTED_131 $end +$var wire 1 F( SYNOPSYS_UNCONNECTED_132 $end +$var wire 1 G( SYNOPSYS_UNCONNECTED_133 $end +$var wire 1 H( SYNOPSYS_UNCONNECTED_134 $end +$var wire 1 I( SYNOPSYS_UNCONNECTED_135 $end +$var wire 1 J( SYNOPSYS_UNCONNECTED_136 $end + +$scope module mux_bottom_track_1 $end +$var wire 1 j# in [0] $end +$var wire 1 m# in [1] $end +$var wire 1 p# in [2] $end +$var wire 1 t# in [3] $end +$var wire 1 =& sram [0] $end +$var wire 1 >& sram [1] $end +$var wire 1 ?& sram [2] $end +$var wire 1 @& sram [3] $end +$var wire 1 y& sram_inv [0] $end +$var wire 1 z& sram_inv [1] $end +$var wire 1 {& sram_inv [2] $end +$var wire 1 |& sram_inv [3] $end +$var wire 1 =$ out [0] $end +$var wire 1 }& p0 $end +$var wire 1 K( local_encoder2to3_0_data [0] $end +$var wire 1 L( local_encoder2to3_0_data [1] $end +$var wire 1 M( local_encoder2to3_0_data [2] $end +$var wire 1 N( local_encoder2to3_0_data_inv [0] $end +$var wire 1 O( local_encoder2to3_0_data_inv [1] $end +$var wire 1 P( local_encoder2to3_0_data_inv [2] $end +$var wire 1 Q( local_encoder2to3_1_data [0] $end +$var wire 1 R( local_encoder2to3_1_data [1] $end +$var wire 1 S( local_encoder2to3_1_data [2] $end +$var wire 1 T( local_encoder2to3_1_data_inv [0] $end +$var wire 1 U( local_encoder2to3_1_data_inv [1] $end +$var wire 1 V( local_encoder2to3_1_data_inv [2] $end +$var wire 1 W( mux_2level_tapbuf_basis_input3_mem3_0_out [0] $end +$var wire 1 X( mux_2level_tapbuf_basis_input3_mem3_1_out [0] $end +$var wire 1 Y( SYNOPSYS_UNCONNECTED_1 $end +$var wire 1 Z( BUF_net_86 $end + +$scope module local_encoder2to3_0_ $end +$var wire 1 =& addr [0] $end +$var wire 1 >& addr [1] $end +$var wire 1 K( data [0] $end +$var wire 1 L( data [1] $end +$var wire 1 M( data [2] $end +$var wire 1 N( data_inv [0] $end +$var wire 1 O( data_inv [1] $end +$var wire 1 P( data_inv [2] $end + +$scope module U8 $end +$var wire 1 N( Y $end +$var wire 1 K( A $end +$var supply1 1 [( VPWR $end +$var supply0 1 \( VGND $end +$var supply1 1 ]( VPB $end +$var supply0 1 ^( VNB $end + +$scope module base $end +$var wire 1 N( Y $end +$var wire 1 K( A $end +$var wire 1 _( not0_out_Y $end +$upscope $end +$upscope $end + +$scope module U9 $end +$var wire 1 L( Y $end +$var wire 1 O( A $end +$var supply1 1 `( VPWR $end +$var supply0 1 a( VGND $end +$var supply1 1 b( VPB $end +$var supply0 1 c( VNB $end + +$scope module base $end +$var wire 1 L( Y $end +$var wire 1 O( A $end +$var wire 1 d( not0_out_Y $end +$upscope $end +$upscope $end + +$scope module U10 $end +$var wire 1 O( Y $end +$var wire 1 =& A $end +$var wire 1 P( B $end +$var supply1 1 e( VPWR $end +$var supply0 1 f( VGND $end +$var supply1 1 g( VPB $end +$var supply0 1 h( VNB $end + +$scope module base $end +$var wire 1 O( Y $end +$var wire 1 =& A $end +$var wire 1 P( B $end +$var wire 1 i( nand0_out_Y $end +$upscope $end +$upscope $end + +$scope module U11 $end +$var wire 1 P( Y $end +$var wire 1 M( A $end +$var supply1 1 j( VPWR $end +$var supply0 1 k( VGND $end +$var supply1 1 l( VPB $end +$var supply0 1 m( VNB $end + +$scope module base $end +$var wire 1 P( Y $end +$var wire 1 M( A $end +$var wire 1 n( not0_out_Y $end +$upscope $end +$upscope $end + +$scope module U12 $end +$var wire 1 K( Y $end +$var wire 1 M( A $end +$var wire 1 =& B $end +$var supply1 1 o( VPWR $end +$var supply0 1 p( VGND $end +$var supply1 1 q( VPB $end +$var supply0 1 r( VNB $end + +$scope module base $end +$var wire 1 K( Y $end +$var wire 1 M( A $end +$var wire 1 =& B $end +$var wire 1 s( nor0_out_Y $end +$upscope $end +$upscope $end + +$scope module FTB_1__0 $end +$var wire 1 M( X $end +$var wire 1 >& A $end +$var supply1 1 t( VPWR $end +$var supply0 1 u( VGND $end +$var supply1 1 v( VPB $end +$var supply0 1 w( VNB $end + +$scope module base $end +$var wire 1 M( X $end +$var wire 1 >& A $end +$var wire 1 x( buf0_out_X $end +$upscope $end +$upscope $end +$upscope $end + +$scope module local_encoder2to3_1_ $end +$var wire 1 ?& addr [0] $end +$var wire 1 @& addr [1] $end +$var wire 1 Q( data [0] $end +$var wire 1 R( data [1] $end +$var wire 1 S( data [2] $end +$var wire 1 T( data_inv [0] $end +$var wire 1 U( data_inv [1] $end +$var wire 1 V( data_inv [2] $end + +$scope module U8 $end +$var wire 1 T( Y $end +$var wire 1 Q( A $end +$var supply1 1 y( VPWR $end +$var supply0 1 z( VGND $end +$var supply1 1 {( VPB $end +$var supply0 1 |( VNB $end + +$scope module base $end +$var wire 1 T( Y $end +$var wire 1 Q( A $end +$var wire 1 }( not0_out_Y $end +$upscope $end +$upscope $end + +$scope module U9 $end +$var wire 1 R( Y $end +$var wire 1 U( A $end +$var supply1 1 ~( VPWR $end +$var supply0 1 !) VGND $end +$var supply1 1 ") VPB $end +$var supply0 1 #) VNB $end + +$scope module base $end +$var wire 1 R( Y $end +$var wire 1 U( A $end +$var wire 1 $) not0_out_Y $end +$upscope $end +$upscope $end + +$scope module U10 $end +$var wire 1 U( Y $end +$var wire 1 ?& A $end +$var wire 1 V( B $end +$var supply1 1 %) VPWR $end +$var supply0 1 &) VGND $end +$var supply1 1 ') VPB $end +$var supply0 1 () VNB $end + +$scope module base $end +$var wire 1 U( Y $end +$var wire 1 ?& A $end +$var wire 1 V( B $end +$var wire 1 )) nand0_out_Y $end +$upscope $end +$upscope $end + +$scope module U11 $end +$var wire 1 V( Y $end +$var wire 1 S( A $end +$var supply1 1 *) VPWR $end +$var supply0 1 +) VGND $end +$var supply1 1 ,) VPB $end +$var supply0 1 -) VNB $end + +$scope module base $end +$var wire 1 V( Y $end +$var wire 1 S( A $end +$var wire 1 .) not0_out_Y $end +$upscope $end +$upscope $end + +$scope module U12 $end +$var wire 1 Q( Y $end +$var wire 1 S( A $end +$var wire 1 ?& B $end +$var supply1 1 /) VPWR $end +$var supply0 1 0) VGND $end +$var supply1 1 1) VPB $end +$var supply0 1 2) VNB $end + +$scope module base $end +$var wire 1 Q( Y $end +$var wire 1 S( A $end +$var wire 1 ?& B $end +$var wire 1 3) nor0_out_Y $end +$upscope $end +$upscope $end + +$scope module FTB_2__1 $end +$var wire 1 S( X $end +$var wire 1 @& A $end +$var supply1 1 4) VPWR $end +$var supply0 1 5) VGND $end +$var supply1 1 6) VPB $end +$var supply0 1 7) VNB $end + +$scope module base $end +$var wire 1 S( X $end +$var wire 1 @& A $end +$var wire 1 8) buf0_out_X $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mux_l1_in_0_ $end +$var wire 1 j# in [0] $end +$var wire 1 m# in [1] $end +$var wire 1 p# in [2] $end +$var wire 1 K( mem [0] $end +$var wire 1 L( mem [1] $end +$var wire 1 M( mem [2] $end +$var wire 1 N( mem_inv [0] $end +$var wire 1 O( mem_inv [1] $end +$var wire 1 P( mem_inv [2] $end +$var wire 1 W( out [0] $end + +$scope module scs8hd_muxinv3_1_0 $end +$var wire 1 W( Z $end +$var wire 1 j# Q1 $end +$var wire 1 m# Q2 $end +$var wire 1 p# Q3 $end +$var wire 1 K( S0 $end +$var wire 1 N( S0B $end +$var wire 1 L( S1 $end +$var wire 1 O( S1B $end +$var wire 1 M( S2 $end +$var wire 1 P( S2B $end +$var wire 1 9) Q1__bar $end +$var wire 1 :) Q2__bar $end +$var wire 1 ;) Q3__bar $end +$upscope $end +$upscope $end + +$scope module mux_l2_in_0_ $end +$var wire 1 W( in [0] $end +$var wire 1 t# in [1] $end +$var wire 1 Y( in [2] $end +$var wire 1 Q( mem [0] $end +$var wire 1 R( mem [1] $end +$var wire 1 S( mem [2] $end +$var wire 1 T( mem_inv [0] $end +$var wire 1 U( mem_inv [1] $end +$var wire 1 V( mem_inv [2] $end +$var wire 1 X( out [0] $end +$var wire 1 }& p0 $end + +$scope module scs8hd_muxinv3_1_0 $end +$var wire 1 X( Z $end +$var wire 1 W( Q1 $end +$var wire 1 t# Q2 $end +$var wire 1 }& Q3 $end +$var wire 1 Q( S0 $end +$var wire 1 T( S0B $end +$var wire 1 R( S1 $end +$var wire 1 U( S1B $end +$var wire 1 S( S2 $end +$var wire 1 V( S2B $end +$var wire 1 <) Q1__bar $end +$var wire 1 =) Q2__bar $end +$var wire 1 >) Q3__bar $end +$upscope $end +$upscope $end + +$scope module BINV_R_85 $end +$var wire 1 =$ Y $end +$var wire 1 Z( A $end +$var supply1 1 ?) VPWR $end +$var supply0 1 @) VGND $end +$var supply1 1 A) VPB $end +$var supply0 1 B) VNB $end + +$scope module base $end +$var wire 1 =$ Y $end +$var wire 1 Z( A $end +$var wire 1 C) not0_out_Y $end +$upscope $end +$upscope $end + +$scope module BINV_R_86 $end +$var wire 1 Z( Y $end +$var wire 1 X( A $end +$var supply1 1 D) VPWR $end +$var supply0 1 E) VGND $end +$var supply1 1 F) VPB $end +$var supply0 1 G) VNB $end + +$scope module base $end +$var wire 1 Z( Y $end +$var wire 1 X( A $end +$var wire 1 H) not0_out_Y $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mux_bottom_track_3 $end +$var wire 1 k# in [0] $end +$var wire 1 n# in [1] $end +$var wire 1 q# in [2] $end +$var wire 1 u# in [3] $end +$var wire 1 I& sram [0] $end +$var wire 1 J& sram [1] $end +$var wire 1 K& sram [2] $end +$var wire 1 L& sram [3] $end +$var wire 1 ~& sram_inv [0] $end +$var wire 1 !' sram_inv [1] $end +$var wire 1 "' sram_inv [2] $end +$var wire 1 #' sram_inv [3] $end +$var wire 1 >$ out [0] $end +$var wire 1 }& p0 $end +$var wire 1 I) local_encoder2to3_0_data [0] $end +$var wire 1 J) local_encoder2to3_0_data [1] $end +$var wire 1 K) local_encoder2to3_0_data [2] $end +$var wire 1 L) local_encoder2to3_0_data_inv [0] $end +$var wire 1 M) local_encoder2to3_0_data_inv [1] $end +$var wire 1 N) local_encoder2to3_0_data_inv [2] $end +$var wire 1 O) local_encoder2to3_1_data [0] $end +$var wire 1 P) local_encoder2to3_1_data [1] $end +$var wire 1 Q) local_encoder2to3_1_data [2] $end +$var wire 1 R) local_encoder2to3_1_data_inv [0] $end +$var wire 1 S) local_encoder2to3_1_data_inv [1] $end +$var wire 1 T) local_encoder2to3_1_data_inv [2] $end +$var wire 1 U) mux_2level_tapbuf_basis_input3_mem3_0_out [0] $end +$var wire 1 V) mux_2level_tapbuf_basis_input3_mem3_1_out [0] $end +$var wire 1 W) SYNOPSYS_UNCONNECTED_1 $end +$var wire 1 X) BUF_net_88 $end + +$scope module local_encoder2to3_0_ $end +$var wire 1 I& addr [0] $end +$var wire 1 J& addr [1] $end +$var wire 1 I) data [0] $end +$var wire 1 J) data [1] $end +$var wire 1 K) data [2] $end +$var wire 1 L) data_inv [0] $end +$var wire 1 M) data_inv [1] $end +$var wire 1 N) data_inv [2] $end + +$scope module U8 $end +$var wire 1 L) Y $end +$var wire 1 I) A $end +$var supply1 1 Y) VPWR $end +$var supply0 1 Z) VGND $end +$var supply1 1 [) VPB $end +$var supply0 1 \) VNB $end + +$scope module base $end +$var wire 1 L) Y $end +$var wire 1 I) A $end +$var wire 1 ]) not0_out_Y $end +$upscope $end +$upscope $end + +$scope module U9 $end +$var wire 1 J) Y $end +$var wire 1 M) A $end +$var supply1 1 ^) VPWR $end +$var supply0 1 _) VGND $end +$var supply1 1 `) VPB $end +$var supply0 1 a) VNB $end + +$scope module base $end +$var wire 1 J) Y $end +$var wire 1 M) A $end +$var wire 1 b) not0_out_Y $end +$upscope $end +$upscope $end + +$scope module U10 $end +$var wire 1 M) Y $end +$var wire 1 I& A $end +$var wire 1 N) B $end +$var supply1 1 c) VPWR $end +$var supply0 1 d) VGND $end +$var supply1 1 e) VPB $end +$var supply0 1 f) VNB $end + +$scope module base $end +$var wire 1 M) Y $end +$var wire 1 I& A $end +$var wire 1 N) B $end +$var wire 1 g) nand0_out_Y $end +$upscope $end +$upscope $end + +$scope module U11 $end +$var wire 1 N) Y $end +$var wire 1 K) A $end +$var supply1 1 h) VPWR $end +$var supply0 1 i) VGND $end +$var supply1 1 j) VPB $end +$var supply0 1 k) VNB $end + +$scope module base $end +$var wire 1 N) Y $end +$var wire 1 K) A $end +$var wire 1 l) not0_out_Y $end +$upscope $end +$upscope $end + +$scope module U12 $end +$var wire 1 I) Y $end +$var wire 1 K) A $end +$var wire 1 I& B $end +$var supply1 1 m) VPWR $end +$var supply0 1 n) VGND $end +$var supply1 1 o) VPB $end +$var supply0 1 p) VNB $end + +$scope module base $end +$var wire 1 I) Y $end +$var wire 1 K) A $end +$var wire 1 I& B $end +$var wire 1 q) nor0_out_Y $end +$upscope $end +$upscope $end + +$scope module FTB_3__2 $end +$var wire 1 K) X $end +$var wire 1 J& A $end +$var supply1 1 r) VPWR $end +$var supply0 1 s) VGND $end +$var supply1 1 t) VPB $end +$var supply0 1 u) VNB $end + +$scope module base $end +$var wire 1 K) X $end +$var wire 1 J& A $end +$var wire 1 v) buf0_out_X $end +$upscope $end +$upscope $end +$upscope $end + +$scope module local_encoder2to3_1_ $end +$var wire 1 K& addr [0] $end +$var wire 1 L& addr [1] $end +$var wire 1 O) data [0] $end +$var wire 1 P) data [1] $end +$var wire 1 Q) data [2] $end +$var wire 1 R) data_inv [0] $end +$var wire 1 S) data_inv [1] $end +$var wire 1 T) data_inv [2] $end + +$scope module U8 $end +$var wire 1 R) Y $end +$var wire 1 O) A $end +$var supply1 1 w) VPWR $end +$var supply0 1 x) VGND $end +$var supply1 1 y) VPB $end +$var supply0 1 z) VNB $end + +$scope module base $end +$var wire 1 R) Y $end +$var wire 1 O) A $end +$var wire 1 {) not0_out_Y $end +$upscope $end +$upscope $end + +$scope module U9 $end +$var wire 1 P) Y $end +$var wire 1 S) A $end +$var supply1 1 |) VPWR $end +$var supply0 1 }) VGND $end +$var supply1 1 ~) VPB $end +$var supply0 1 !* VNB $end + +$scope module base $end +$var wire 1 P) Y $end +$var wire 1 S) A $end +$var wire 1 "* not0_out_Y $end +$upscope $end +$upscope $end + +$scope module U10 $end +$var wire 1 S) Y $end +$var wire 1 K& A $end +$var wire 1 T) B $end +$var supply1 1 #* VPWR $end +$var supply0 1 $* VGND $end +$var supply1 1 %* VPB $end +$var supply0 1 &* VNB $end + +$scope module base $end +$var wire 1 S) Y $end +$var wire 1 K& A $end +$var wire 1 T) B $end +$var wire 1 '* nand0_out_Y $end +$upscope $end +$upscope $end + +$scope module U11 $end +$var wire 1 T) Y $end +$var wire 1 Q) A $end +$var supply1 1 (* VPWR $end +$var supply0 1 )* VGND $end +$var supply1 1 ** VPB $end +$var supply0 1 +* VNB $end + +$scope module base $end +$var wire 1 T) Y $end +$var wire 1 Q) A $end +$var wire 1 ,* not0_out_Y $end +$upscope $end +$upscope $end + +$scope module U12 $end +$var wire 1 O) Y $end +$var wire 1 Q) A $end +$var wire 1 K& B $end +$var supply1 1 -* VPWR $end +$var supply0 1 .* VGND $end +$var supply1 1 /* VPB $end +$var supply0 1 0* VNB $end + +$scope module base $end +$var wire 1 O) Y $end +$var wire 1 Q) A $end +$var wire 1 K& B $end +$var wire 1 1* nor0_out_Y $end +$upscope $end +$upscope $end + +$scope module FTB_4__3 $end +$var wire 1 Q) X $end +$var wire 1 L& A $end +$var supply1 1 2* VPWR $end +$var supply0 1 3* VGND $end +$var supply1 1 4* VPB $end +$var supply0 1 5* VNB $end + +$scope module base $end +$var wire 1 Q) X $end +$var wire 1 L& A $end +$var wire 1 6* buf0_out_X $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mux_l1_in_0_ $end +$var wire 1 k# in [0] $end +$var wire 1 n# in [1] $end +$var wire 1 q# in [2] $end +$var wire 1 I) mem [0] $end +$var wire 1 J) mem [1] $end +$var wire 1 K) mem [2] $end +$var wire 1 L) mem_inv [0] $end +$var wire 1 M) mem_inv [1] $end +$var wire 1 N) mem_inv [2] $end +$var wire 1 U) out [0] $end + +$scope module scs8hd_muxinv3_1_0 $end +$var wire 1 U) Z $end +$var wire 1 k# Q1 $end +$var wire 1 n# Q2 $end +$var wire 1 q# Q3 $end +$var wire 1 I) S0 $end +$var wire 1 L) S0B $end +$var wire 1 J) S1 $end +$var wire 1 M) S1B $end +$var wire 1 K) S2 $end +$var wire 1 N) S2B $end +$var wire 1 7* Q1__bar $end +$var wire 1 8* Q2__bar $end +$var wire 1 9* Q3__bar $end +$upscope $end +$upscope $end + +$scope module mux_l2_in_0_ $end +$var wire 1 U) in [0] $end +$var wire 1 u# in [1] $end +$var wire 1 W) in [2] $end +$var wire 1 O) mem [0] $end +$var wire 1 P) mem [1] $end +$var wire 1 Q) mem [2] $end +$var wire 1 R) mem_inv [0] $end +$var wire 1 S) mem_inv [1] $end +$var wire 1 T) mem_inv [2] $end +$var wire 1 V) out [0] $end +$var wire 1 }& p0 $end + +$scope module scs8hd_muxinv3_1_0 $end +$var wire 1 V) Z $end +$var wire 1 U) Q1 $end +$var wire 1 u# Q2 $end +$var wire 1 }& Q3 $end +$var wire 1 O) S0 $end +$var wire 1 R) S0B $end +$var wire 1 P) S1 $end +$var wire 1 S) S1B $end +$var wire 1 Q) S2 $end +$var wire 1 T) S2B $end +$var wire 1 :* Q1__bar $end +$var wire 1 ;* Q2__bar $end +$var wire 1 <* Q3__bar $end +$upscope $end +$upscope $end + +$scope module BINV_R_87 $end +$var wire 1 >$ Y $end +$var wire 1 X) A $end +$var supply1 1 =* VPWR $end +$var supply0 1 >* VGND $end +$var supply1 1 ?* VPB $end +$var supply0 1 @* VNB $end + +$scope module base $end +$var wire 1 >$ Y $end +$var wire 1 X) A $end +$var wire 1 A* not0_out_Y $end +$upscope $end +$upscope $end + +$scope module BINV_R_88 $end +$var wire 1 X) Y $end +$var wire 1 V) A $end +$var supply1 1 B* VPWR $end +$var supply0 1 C* VGND $end +$var supply1 1 D* VPB $end +$var supply0 1 E* VNB $end + +$scope module base $end +$var wire 1 X) Y $end +$var wire 1 V) A $end +$var wire 1 F* not0_out_Y $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mux_bottom_track_5 $end +$var wire 1 l# in [0] $end +$var wire 1 o# in [1] $end +$var wire 1 r# in [2] $end +$var wire 1 v# in [3] $end +$var wire 1 M& sram [0] $end +$var wire 1 N& sram [1] $end +$var wire 1 O& sram [2] $end +$var wire 1 P& sram [3] $end +$var wire 1 $' sram_inv [0] $end +$var wire 1 %' sram_inv [1] $end +$var wire 1 &' sram_inv [2] $end +$var wire 1 '' sram_inv [3] $end +$var wire 1 ?$ out [0] $end +$var wire 1 (' p0 $end +$var wire 1 G* local_encoder2to3_0_data [0] $end +$var wire 1 H* local_encoder2to3_0_data [1] $end +$var wire 1 I* local_encoder2to3_0_data [2] $end +$var wire 1 J* local_encoder2to3_0_data_inv [0] $end +$var wire 1 K* local_encoder2to3_0_data_inv [1] $end +$var wire 1 L* local_encoder2to3_0_data_inv [2] $end +$var wire 1 M* local_encoder2to3_1_data [0] $end +$var wire 1 N* local_encoder2to3_1_data [1] $end +$var wire 1 O* local_encoder2to3_1_data [2] $end +$var wire 1 P* local_encoder2to3_1_data_inv [0] $end +$var wire 1 Q* local_encoder2to3_1_data_inv [1] $end +$var wire 1 R* local_encoder2to3_1_data_inv [2] $end +$var wire 1 S* mux_2level_tapbuf_basis_input3_mem3_0_out [0] $end +$var wire 1 T* mux_2level_tapbuf_basis_input3_mem3_1_out [0] $end +$var wire 1 U* SYNOPSYS_UNCONNECTED_1 $end + +$scope module local_encoder2to3_0_ $end +$var wire 1 M& addr [0] $end +$var wire 1 N& addr [1] $end +$var wire 1 G* data [0] $end +$var wire 1 H* data [1] $end +$var wire 1 I* data [2] $end +$var wire 1 J* data_inv [0] $end +$var wire 1 K* data_inv [1] $end +$var wire 1 L* data_inv [2] $end + +$scope module U8 $end +$var wire 1 J* Y $end +$var wire 1 G* A $end +$var supply1 1 V* VPWR $end +$var supply0 1 W* VGND $end +$var supply1 1 X* VPB $end +$var supply0 1 Y* VNB $end + +$scope module base $end +$var wire 1 J* Y $end +$var wire 1 G* A $end +$var wire 1 Z* not0_out_Y $end +$upscope $end +$upscope $end + +$scope module U9 $end +$var wire 1 H* Y $end +$var wire 1 K* A $end +$var supply1 1 [* VPWR $end +$var supply0 1 \* VGND $end +$var supply1 1 ]* VPB $end +$var supply0 1 ^* VNB $end + +$scope module base $end +$var wire 1 H* Y $end +$var wire 1 K* A $end +$var wire 1 _* not0_out_Y $end +$upscope $end +$upscope $end + +$scope module U10 $end +$var wire 1 K* Y $end +$var wire 1 M& A $end +$var wire 1 L* B $end +$var supply1 1 `* VPWR $end +$var supply0 1 a* VGND $end +$var supply1 1 b* VPB $end +$var supply0 1 c* VNB $end + +$scope module base $end +$var wire 1 K* Y $end +$var wire 1 M& A $end +$var wire 1 L* B $end +$var wire 1 d* nand0_out_Y $end +$upscope $end +$upscope $end + +$scope module U11 $end +$var wire 1 L* Y $end +$var wire 1 I* A $end +$var supply1 1 e* VPWR $end +$var supply0 1 f* VGND $end +$var supply1 1 g* VPB $end +$var supply0 1 h* VNB $end + +$scope module base $end +$var wire 1 L* Y $end +$var wire 1 I* A $end +$var wire 1 i* not0_out_Y $end +$upscope $end +$upscope $end + +$scope module U12 $end +$var wire 1 G* Y $end +$var wire 1 I* A $end +$var wire 1 M& B $end +$var supply1 1 j* VPWR $end +$var supply0 1 k* VGND $end +$var supply1 1 l* VPB $end +$var supply0 1 m* VNB $end + +$scope module base $end +$var wire 1 G* Y $end +$var wire 1 I* A $end +$var wire 1 M& B $end +$var wire 1 n* nor0_out_Y $end +$upscope $end +$upscope $end + +$scope module FTB_5__4 $end +$var wire 1 I* X $end +$var wire 1 N& A $end +$var supply1 1 o* VPWR $end +$var supply0 1 p* VGND $end +$var supply1 1 q* VPB $end +$var supply0 1 r* VNB $end + +$scope module base $end +$var wire 1 I* X $end +$var wire 1 N& A $end +$var wire 1 s* buf0_out_X $end +$upscope $end +$upscope $end +$upscope $end + +$scope module local_encoder2to3_1_ $end +$var wire 1 O& addr [0] $end +$var wire 1 P& addr [1] $end +$var wire 1 M* data [0] $end +$var wire 1 N* data [1] $end +$var wire 1 O* data [2] $end +$var wire 1 P* data_inv [0] $end +$var wire 1 Q* data_inv [1] $end +$var wire 1 R* data_inv [2] $end + +$scope module U8 $end +$var wire 1 P* Y $end +$var wire 1 M* A $end +$var supply1 1 t* VPWR $end +$var supply0 1 u* VGND $end +$var supply1 1 v* VPB $end +$var supply0 1 w* VNB $end + +$scope module base $end +$var wire 1 P* Y $end +$var wire 1 M* A $end +$var wire 1 x* not0_out_Y $end +$upscope $end +$upscope $end + +$scope module U9 $end +$var wire 1 N* Y $end +$var wire 1 Q* A $end +$var supply1 1 y* VPWR $end +$var supply0 1 z* VGND $end +$var supply1 1 {* VPB $end +$var supply0 1 |* VNB $end + +$scope module base $end +$var wire 1 N* Y $end +$var wire 1 Q* A $end +$var wire 1 }* not0_out_Y $end +$upscope $end +$upscope $end + +$scope module U10 $end +$var wire 1 Q* Y $end +$var wire 1 O& A $end +$var wire 1 R* B $end +$var supply1 1 ~* VPWR $end +$var supply0 1 !+ VGND $end +$var supply1 1 "+ VPB $end +$var supply0 1 #+ VNB $end + +$scope module base $end +$var wire 1 Q* Y $end +$var wire 1 O& A $end +$var wire 1 R* B $end +$var wire 1 $+ nand0_out_Y $end +$upscope $end +$upscope $end + +$scope module U11 $end +$var wire 1 R* Y $end +$var wire 1 O* A $end +$var supply1 1 %+ VPWR $end +$var supply0 1 &+ VGND $end +$var supply1 1 '+ VPB $end +$var supply0 1 (+ VNB $end + +$scope module base $end +$var wire 1 R* Y $end +$var wire 1 O* A $end +$var wire 1 )+ not0_out_Y $end +$upscope $end +$upscope $end + +$scope module U12 $end +$var wire 1 M* Y $end +$var wire 1 O* A $end +$var wire 1 O& B $end +$var supply1 1 *+ VPWR $end +$var supply0 1 ++ VGND $end +$var supply1 1 ,+ VPB $end +$var supply0 1 -+ VNB $end + +$scope module base $end +$var wire 1 M* Y $end +$var wire 1 O* A $end +$var wire 1 O& B $end +$var wire 1 .+ nor0_out_Y $end +$upscope $end +$upscope $end + +$scope module FTB_6__5 $end +$var wire 1 O* X $end +$var wire 1 P& A $end +$var supply1 1 /+ VPWR $end +$var supply0 1 0+ VGND $end +$var supply1 1 1+ VPB $end +$var supply0 1 2+ VNB $end + +$scope module base $end +$var wire 1 O* X $end +$var wire 1 P& A $end +$var wire 1 3+ buf0_out_X $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mux_l1_in_0_ $end +$var wire 1 l# in [0] $end +$var wire 1 o# in [1] $end +$var wire 1 r# in [2] $end +$var wire 1 G* mem [0] $end +$var wire 1 H* mem [1] $end +$var wire 1 I* mem [2] $end +$var wire 1 J* mem_inv [0] $end +$var wire 1 K* mem_inv [1] $end +$var wire 1 L* mem_inv [2] $end +$var wire 1 S* out [0] $end + +$scope module scs8hd_muxinv3_1_0 $end +$var wire 1 S* Z $end +$var wire 1 l# Q1 $end +$var wire 1 o# Q2 $end +$var wire 1 r# Q3 $end +$var wire 1 G* S0 $end +$var wire 1 J* S0B $end +$var wire 1 H* S1 $end +$var wire 1 K* S1B $end +$var wire 1 I* S2 $end +$var wire 1 L* S2B $end +$var wire 1 4+ Q1__bar $end +$var wire 1 5+ Q2__bar $end +$var wire 1 6+ Q3__bar $end +$upscope $end +$upscope $end + +$scope module mux_l2_in_0_ $end +$var wire 1 S* in [0] $end +$var wire 1 v# in [1] $end +$var wire 1 U* in [2] $end +$var wire 1 M* mem [0] $end +$var wire 1 N* mem [1] $end +$var wire 1 O* mem [2] $end +$var wire 1 P* mem_inv [0] $end +$var wire 1 Q* mem_inv [1] $end +$var wire 1 R* mem_inv [2] $end +$var wire 1 T* out [0] $end +$var wire 1 (' p0 $end + +$scope module scs8hd_muxinv3_1_0 $end +$var wire 1 T* Z $end +$var wire 1 S* Q1 $end +$var wire 1 v# Q2 $end +$var wire 1 (' Q3 $end +$var wire 1 M* S0 $end +$var wire 1 P* S0B $end +$var wire 1 N* S1 $end +$var wire 1 Q* S1B $end +$var wire 1 O* S2 $end +$var wire 1 R* S2B $end +$var wire 1 7+ Q1__bar $end +$var wire 1 8+ Q2__bar $end +$var wire 1 9+ Q3__bar $end +$upscope $end +$upscope $end + +$scope module BUFT_RR_89 $end +$var wire 1 ?$ X $end +$var wire 1 T* A $end +$var supply1 1 :+ VPWR $end +$var supply0 1 ;+ VGND $end +$var supply1 1 <+ VPB $end +$var supply0 1 =+ VNB $end + +$scope module base $end +$var wire 1 ?$ X $end +$var wire 1 T* A $end +$var wire 1 >+ buf0_out_X $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mux_bottom_track_7 $end +$var wire 1 j# in [0] $end +$var wire 1 m# in [1] $end +$var wire 1 p# in [2] $end +$var wire 1 w# in [3] $end +$var wire 1 Q& sram [0] $end +$var wire 1 R& sram [1] $end +$var wire 1 S& sram [2] $end +$var wire 1 T& sram [3] $end +$var wire 1 )' sram_inv [0] $end +$var wire 1 *' sram_inv [1] $end +$var wire 1 +' sram_inv [2] $end +$var wire 1 ,' sram_inv [3] $end +$var wire 1 @$ out [0] $end +$var wire 1 }& p0 $end +$var wire 1 ?+ local_encoder2to3_0_data [0] $end +$var wire 1 @+ local_encoder2to3_0_data [1] $end +$var wire 1 A+ local_encoder2to3_0_data [2] $end +$var wire 1 B+ local_encoder2to3_0_data_inv [0] $end +$var wire 1 C+ local_encoder2to3_0_data_inv [1] $end +$var wire 1 D+ local_encoder2to3_0_data_inv [2] $end +$var wire 1 E+ local_encoder2to3_1_data [0] $end +$var wire 1 F+ local_encoder2to3_1_data [1] $end +$var wire 1 G+ local_encoder2to3_1_data [2] $end +$var wire 1 H+ local_encoder2to3_1_data_inv [0] $end +$var wire 1 I+ local_encoder2to3_1_data_inv [1] $end +$var wire 1 J+ local_encoder2to3_1_data_inv [2] $end +$var wire 1 K+ mux_2level_tapbuf_basis_input3_mem3_0_out [0] $end +$var wire 1 L+ mux_2level_tapbuf_basis_input3_mem3_1_out [0] $end +$var wire 1 M+ SYNOPSYS_UNCONNECTED_1 $end +$var wire 1 N+ BUF_net_91 $end + +$scope module local_encoder2to3_0_ $end +$var wire 1 Q& addr [0] $end +$var wire 1 R& addr [1] $end +$var wire 1 ?+ data [0] $end +$var wire 1 @+ data [1] $end +$var wire 1 A+ data [2] $end +$var wire 1 B+ data_inv [0] $end +$var wire 1 C+ data_inv [1] $end +$var wire 1 D+ data_inv [2] $end + +$scope module U8 $end +$var wire 1 B+ Y $end +$var wire 1 ?+ A $end +$var supply1 1 O+ VPWR $end +$var supply0 1 P+ VGND $end +$var supply1 1 Q+ VPB $end +$var supply0 1 R+ VNB $end + +$scope module base $end +$var wire 1 B+ Y $end +$var wire 1 ?+ A $end +$var wire 1 S+ not0_out_Y $end +$upscope $end +$upscope $end + +$scope module U9 $end +$var wire 1 @+ Y $end +$var wire 1 C+ A $end +$var supply1 1 T+ VPWR $end +$var supply0 1 U+ VGND $end +$var supply1 1 V+ VPB $end +$var supply0 1 W+ VNB $end + +$scope module base $end +$var wire 1 @+ Y $end +$var wire 1 C+ A $end +$var wire 1 X+ not0_out_Y $end +$upscope $end +$upscope $end + +$scope module U10 $end +$var wire 1 C+ Y $end +$var wire 1 Q& A $end +$var wire 1 D+ B $end +$var supply1 1 Y+ VPWR $end +$var supply0 1 Z+ VGND $end +$var supply1 1 [+ VPB $end +$var supply0 1 \+ VNB $end + +$scope module base $end +$var wire 1 C+ Y $end +$var wire 1 Q& A $end +$var wire 1 D+ B $end +$var wire 1 ]+ nand0_out_Y $end +$upscope $end +$upscope $end + +$scope module U11 $end +$var wire 1 D+ Y $end +$var wire 1 A+ A $end +$var supply1 1 ^+ VPWR $end +$var supply0 1 _+ VGND $end +$var supply1 1 `+ VPB $end +$var supply0 1 a+ VNB $end + +$scope module base $end +$var wire 1 D+ Y $end +$var wire 1 A+ A $end +$var wire 1 b+ not0_out_Y $end +$upscope $end +$upscope $end + +$scope module U12 $end +$var wire 1 ?+ Y $end +$var wire 1 A+ A $end +$var wire 1 Q& B $end +$var supply1 1 c+ VPWR $end +$var supply0 1 d+ VGND $end +$var supply1 1 e+ VPB $end +$var supply0 1 f+ VNB $end + +$scope module base $end +$var wire 1 ?+ Y $end +$var wire 1 A+ A $end +$var wire 1 Q& B $end +$var wire 1 g+ nor0_out_Y $end +$upscope $end +$upscope $end + +$scope module FTB_7__6 $end +$var wire 1 A+ X $end +$var wire 1 R& A $end +$var supply1 1 h+ VPWR $end +$var supply0 1 i+ VGND $end +$var supply1 1 j+ VPB $end +$var supply0 1 k+ VNB $end + +$scope module base $end +$var wire 1 A+ X $end +$var wire 1 R& A $end +$var wire 1 l+ buf0_out_X $end +$upscope $end +$upscope $end +$upscope $end + +$scope module local_encoder2to3_1_ $end +$var wire 1 S& addr [0] $end +$var wire 1 T& addr [1] $end +$var wire 1 E+ data [0] $end +$var wire 1 F+ data [1] $end +$var wire 1 G+ data [2] $end +$var wire 1 H+ data_inv [0] $end +$var wire 1 I+ data_inv [1] $end +$var wire 1 J+ data_inv [2] $end + +$scope module U8 $end +$var wire 1 H+ Y $end +$var wire 1 E+ A $end +$var supply1 1 m+ VPWR $end +$var supply0 1 n+ VGND $end +$var supply1 1 o+ VPB $end +$var supply0 1 p+ VNB $end + +$scope module base $end +$var wire 1 H+ Y $end +$var wire 1 E+ A $end +$var wire 1 q+ not0_out_Y $end +$upscope $end +$upscope $end + +$scope module U9 $end +$var wire 1 F+ Y $end +$var wire 1 I+ A $end +$var supply1 1 r+ VPWR $end +$var supply0 1 s+ VGND $end +$var supply1 1 t+ VPB $end +$var supply0 1 u+ VNB $end + +$scope module base $end +$var wire 1 F+ Y $end +$var wire 1 I+ A $end +$var wire 1 v+ not0_out_Y $end +$upscope $end +$upscope $end + +$scope module U10 $end +$var wire 1 I+ Y $end +$var wire 1 S& A $end +$var wire 1 J+ B $end +$var supply1 1 w+ VPWR $end +$var supply0 1 x+ VGND $end +$var supply1 1 y+ VPB $end +$var supply0 1 z+ VNB $end + +$scope module base $end +$var wire 1 I+ Y $end +$var wire 1 S& A $end +$var wire 1 J+ B $end +$var wire 1 {+ nand0_out_Y $end +$upscope $end +$upscope $end + +$scope module U11 $end +$var wire 1 J+ Y $end +$var wire 1 G+ A $end +$var supply1 1 |+ VPWR $end +$var supply0 1 }+ VGND $end +$var supply1 1 ~+ VPB $end +$var supply0 1 !, VNB $end + +$scope module base $end +$var wire 1 J+ Y $end +$var wire 1 G+ A $end +$var wire 1 ", not0_out_Y $end +$upscope $end +$upscope $end + +$scope module U12 $end +$var wire 1 E+ Y $end +$var wire 1 G+ A $end +$var wire 1 S& B $end +$var supply1 1 #, VPWR $end +$var supply0 1 $, VGND $end +$var supply1 1 %, VPB $end +$var supply0 1 &, VNB $end + +$scope module base $end +$var wire 1 E+ Y $end +$var wire 1 G+ A $end +$var wire 1 S& B $end +$var wire 1 ', nor0_out_Y $end +$upscope $end +$upscope $end + +$scope module FTB_8__7 $end +$var wire 1 G+ X $end +$var wire 1 T& A $end +$var supply1 1 (, VPWR $end +$var supply0 1 ), VGND $end +$var supply1 1 *, VPB $end +$var supply0 1 +, VNB $end + +$scope module base $end +$var wire 1 G+ X $end +$var wire 1 T& A $end +$var wire 1 ,, buf0_out_X $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mux_l1_in_0_ $end +$var wire 1 j# in [0] $end +$var wire 1 m# in [1] $end +$var wire 1 p# in [2] $end +$var wire 1 ?+ mem [0] $end +$var wire 1 @+ mem [1] $end +$var wire 1 A+ mem [2] $end +$var wire 1 B+ mem_inv [0] $end +$var wire 1 C+ mem_inv [1] $end +$var wire 1 D+ mem_inv [2] $end +$var wire 1 K+ out [0] $end + +$scope module scs8hd_muxinv3_1_0 $end +$var wire 1 K+ Z $end +$var wire 1 j# Q1 $end +$var wire 1 m# Q2 $end +$var wire 1 p# Q3 $end +$var wire 1 ?+ S0 $end +$var wire 1 B+ S0B $end +$var wire 1 @+ S1 $end +$var wire 1 C+ S1B $end +$var wire 1 A+ S2 $end +$var wire 1 D+ S2B $end +$var wire 1 -, Q1__bar $end +$var wire 1 ., Q2__bar $end +$var wire 1 /, Q3__bar $end +$upscope $end +$upscope $end + +$scope module mux_l2_in_0_ $end +$var wire 1 K+ in [0] $end +$var wire 1 w# in [1] $end +$var wire 1 M+ in [2] $end +$var wire 1 E+ mem [0] $end +$var wire 1 F+ mem [1] $end +$var wire 1 G+ mem [2] $end +$var wire 1 H+ mem_inv [0] $end +$var wire 1 I+ mem_inv [1] $end +$var wire 1 J+ mem_inv [2] $end +$var wire 1 L+ out [0] $end +$var wire 1 }& p0 $end + +$scope module scs8hd_muxinv3_1_0 $end +$var wire 1 L+ Z $end +$var wire 1 K+ Q1 $end +$var wire 1 w# Q2 $end +$var wire 1 }& Q3 $end +$var wire 1 E+ S0 $end +$var wire 1 H+ S0B $end +$var wire 1 F+ S1 $end +$var wire 1 I+ S1B $end +$var wire 1 G+ S2 $end +$var wire 1 J+ S2B $end +$var wire 1 0, Q1__bar $end +$var wire 1 1, Q2__bar $end +$var wire 1 2, Q3__bar $end +$upscope $end +$upscope $end + +$scope module BINV_R_90 $end +$var wire 1 @$ Y $end +$var wire 1 N+ A $end +$var supply1 1 3, VPWR $end +$var supply0 1 4, VGND $end +$var supply1 1 5, VPB $end +$var supply0 1 6, VNB $end + +$scope module base $end +$var wire 1 @$ Y $end +$var wire 1 N+ A $end +$var wire 1 7, not0_out_Y $end +$upscope $end +$upscope $end + +$scope module BINV_R_91 $end +$var wire 1 N+ Y $end +$var wire 1 L+ A $end +$var supply1 1 8, VPWR $end +$var supply0 1 9, VGND $end +$var supply1 1 :, VPB $end +$var supply0 1 ;, VNB $end + +$scope module base $end +$var wire 1 N+ Y $end +$var wire 1 L+ A $end +$var wire 1 <, not0_out_Y $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mux_bottom_track_9 $end +$var wire 1 k# in [0] $end +$var wire 1 n# in [1] $end +$var wire 1 q# in [2] $end +$var wire 1 x# in [3] $end +$var wire 1 U& sram [0] $end +$var wire 1 V& sram [1] $end +$var wire 1 W& sram [2] $end +$var wire 1 X& sram [3] $end +$var wire 1 -' sram_inv [0] $end +$var wire 1 .' sram_inv [1] $end +$var wire 1 /' sram_inv [2] $end +$var wire 1 0' sram_inv [3] $end +$var wire 1 A$ out [0] $end +$var wire 1 1' p0 $end +$var wire 1 =, local_encoder2to3_0_data [0] $end +$var wire 1 >, local_encoder2to3_0_data [1] $end +$var wire 1 ?, local_encoder2to3_0_data [2] $end +$var wire 1 @, local_encoder2to3_0_data_inv [0] $end +$var wire 1 A, local_encoder2to3_0_data_inv [1] $end +$var wire 1 B, local_encoder2to3_0_data_inv [2] $end +$var wire 1 C, local_encoder2to3_1_data [0] $end +$var wire 1 D, local_encoder2to3_1_data [1] $end +$var wire 1 E, local_encoder2to3_1_data [2] $end +$var wire 1 F, local_encoder2to3_1_data_inv [0] $end +$var wire 1 G, local_encoder2to3_1_data_inv [1] $end +$var wire 1 H, local_encoder2to3_1_data_inv [2] $end +$var wire 1 I, mux_2level_tapbuf_basis_input3_mem3_0_out [0] $end +$var wire 1 J, mux_2level_tapbuf_basis_input3_mem3_1_out [0] $end +$var wire 1 K, SYNOPSYS_UNCONNECTED_1 $end +$var wire 1 L, BUF_net_93 $end + +$scope module local_encoder2to3_0_ $end +$var wire 1 U& addr [0] $end +$var wire 1 V& addr [1] $end +$var wire 1 =, data [0] $end +$var wire 1 >, data [1] $end +$var wire 1 ?, data [2] $end +$var wire 1 @, data_inv [0] $end +$var wire 1 A, data_inv [1] $end +$var wire 1 B, data_inv [2] $end + +$scope module U8 $end +$var wire 1 @, Y $end +$var wire 1 =, A $end +$var supply1 1 M, VPWR $end +$var supply0 1 N, VGND $end +$var supply1 1 O, VPB $end +$var supply0 1 P, VNB $end + +$scope module base $end +$var wire 1 @, Y $end +$var wire 1 =, A $end +$var wire 1 Q, not0_out_Y $end +$upscope $end +$upscope $end + +$scope module U9 $end +$var wire 1 >, Y $end +$var wire 1 A, A $end +$var supply1 1 R, VPWR $end +$var supply0 1 S, VGND $end +$var supply1 1 T, VPB $end +$var supply0 1 U, VNB $end + +$scope module base $end +$var wire 1 >, Y $end +$var wire 1 A, A $end +$var wire 1 V, not0_out_Y $end +$upscope $end +$upscope $end + +$scope module U10 $end +$var wire 1 A, Y $end +$var wire 1 U& A $end +$var wire 1 B, B $end +$var supply1 1 W, VPWR $end +$var supply0 1 X, VGND $end +$var supply1 1 Y, VPB $end +$var supply0 1 Z, VNB $end + +$scope module base $end +$var wire 1 A, Y $end +$var wire 1 U& A $end +$var wire 1 B, B $end +$var wire 1 [, nand0_out_Y $end +$upscope $end +$upscope $end + +$scope module U11 $end +$var wire 1 B, Y $end +$var wire 1 ?, A $end +$var supply1 1 \, VPWR $end +$var supply0 1 ], VGND $end +$var supply1 1 ^, VPB $end +$var supply0 1 _, VNB $end + +$scope module base $end +$var wire 1 B, Y $end +$var wire 1 ?, A $end +$var wire 1 `, not0_out_Y $end +$upscope $end +$upscope $end + +$scope module U12 $end +$var wire 1 =, Y $end +$var wire 1 ?, A $end +$var wire 1 U& B $end +$var supply1 1 a, VPWR $end +$var supply0 1 b, VGND $end +$var supply1 1 c, VPB $end +$var supply0 1 d, VNB $end + +$scope module base $end +$var wire 1 =, Y $end +$var wire 1 ?, A $end +$var wire 1 U& B $end +$var wire 1 e, nor0_out_Y $end +$upscope $end +$upscope $end + +$scope module FTB_9__8 $end +$var wire 1 ?, X $end +$var wire 1 V& A $end +$var supply1 1 f, VPWR $end +$var supply0 1 g, VGND $end +$var supply1 1 h, VPB $end +$var supply0 1 i, VNB $end + +$scope module base $end +$var wire 1 ?, X $end +$var wire 1 V& A $end +$var wire 1 j, buf0_out_X $end +$upscope $end +$upscope $end +$upscope $end + +$scope module local_encoder2to3_1_ $end +$var wire 1 W& addr [0] $end +$var wire 1 X& addr [1] $end +$var wire 1 C, data [0] $end +$var wire 1 D, data [1] $end +$var wire 1 E, data [2] $end +$var wire 1 F, data_inv [0] $end +$var wire 1 G, data_inv [1] $end +$var wire 1 H, data_inv [2] $end + +$scope module U8 $end +$var wire 1 F, Y $end +$var wire 1 C, A $end +$var supply1 1 k, VPWR $end +$var supply0 1 l, VGND $end +$var supply1 1 m, VPB $end +$var supply0 1 n, VNB $end + +$scope module base $end +$var wire 1 F, Y $end +$var wire 1 C, A $end +$var wire 1 o, not0_out_Y $end +$upscope $end +$upscope $end + +$scope module U9 $end +$var wire 1 D, Y $end +$var wire 1 G, A $end +$var supply1 1 p, VPWR $end +$var supply0 1 q, VGND $end +$var supply1 1 r, VPB $end +$var supply0 1 s, VNB $end + +$scope module base $end +$var wire 1 D, Y $end +$var wire 1 G, A $end +$var wire 1 t, not0_out_Y $end +$upscope $end +$upscope $end + +$scope module U10 $end +$var wire 1 G, Y $end +$var wire 1 W& A $end +$var wire 1 H, B $end +$var supply1 1 u, VPWR $end +$var supply0 1 v, VGND $end +$var supply1 1 w, VPB $end +$var supply0 1 x, VNB $end + +$scope module base $end +$var wire 1 G, Y $end +$var wire 1 W& A $end +$var wire 1 H, B $end +$var wire 1 y, nand0_out_Y $end +$upscope $end +$upscope $end + +$scope module U11 $end +$var wire 1 H, Y $end +$var wire 1 E, A $end +$var supply1 1 z, VPWR $end +$var supply0 1 {, VGND $end +$var supply1 1 |, VPB $end +$var supply0 1 }, VNB $end + +$scope module base $end +$var wire 1 H, Y $end +$var wire 1 E, A $end +$var wire 1 ~, not0_out_Y $end +$upscope $end +$upscope $end + +$scope module U12 $end +$var wire 1 C, Y $end +$var wire 1 E, A $end +$var wire 1 W& B $end +$var supply1 1 !- VPWR $end +$var supply0 1 "- VGND $end +$var supply1 1 #- VPB $end +$var supply0 1 $- VNB $end + +$scope module base $end +$var wire 1 C, Y $end +$var wire 1 E, A $end +$var wire 1 W& B $end +$var wire 1 %- nor0_out_Y $end +$upscope $end +$upscope $end + +$scope module FTB_10__9 $end +$var wire 1 E, X $end +$var wire 1 X& A $end +$var supply1 1 &- VPWR $end +$var supply0 1 '- VGND $end +$var supply1 1 (- VPB $end +$var supply0 1 )- VNB $end + +$scope module base $end +$var wire 1 E, X $end +$var wire 1 X& A $end +$var wire 1 *- buf0_out_X $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mux_l1_in_0_ $end +$var wire 1 k# in [0] $end +$var wire 1 n# in [1] $end +$var wire 1 q# in [2] $end +$var wire 1 =, mem [0] $end +$var wire 1 >, mem [1] $end +$var wire 1 ?, mem [2] $end +$var wire 1 @, mem_inv [0] $end +$var wire 1 A, mem_inv [1] $end +$var wire 1 B, mem_inv [2] $end +$var wire 1 I, out [0] $end + +$scope module scs8hd_muxinv3_1_0 $end +$var wire 1 I, Z $end +$var wire 1 k# Q1 $end +$var wire 1 n# Q2 $end +$var wire 1 q# Q3 $end +$var wire 1 =, S0 $end +$var wire 1 @, S0B $end +$var wire 1 >, S1 $end +$var wire 1 A, S1B $end +$var wire 1 ?, S2 $end +$var wire 1 B, S2B $end +$var wire 1 +- Q1__bar $end +$var wire 1 ,- Q2__bar $end +$var wire 1 -- Q3__bar $end +$upscope $end +$upscope $end + +$scope module mux_l2_in_0_ $end +$var wire 1 I, in [0] $end +$var wire 1 x# in [1] $end +$var wire 1 K, in [2] $end +$var wire 1 C, mem [0] $end +$var wire 1 D, mem [1] $end +$var wire 1 E, mem [2] $end +$var wire 1 F, mem_inv [0] $end +$var wire 1 G, mem_inv [1] $end +$var wire 1 H, mem_inv [2] $end +$var wire 1 J, out [0] $end +$var wire 1 1' p0 $end + +$scope module scs8hd_muxinv3_1_0 $end +$var wire 1 J, Z $end +$var wire 1 I, Q1 $end +$var wire 1 x# Q2 $end +$var wire 1 1' Q3 $end +$var wire 1 C, S0 $end +$var wire 1 F, S0B $end +$var wire 1 D, S1 $end +$var wire 1 G, S1B $end +$var wire 1 E, S2 $end +$var wire 1 H, S2B $end +$var wire 1 .- Q1__bar $end +$var wire 1 /- Q2__bar $end +$var wire 1 0- Q3__bar $end +$upscope $end +$upscope $end + +$scope module BINV_R_92 $end +$var wire 1 A$ Y $end +$var wire 1 L, A $end +$var supply1 1 1- VPWR $end +$var supply0 1 2- VGND $end +$var supply1 1 3- VPB $end +$var supply0 1 4- VNB $end + +$scope module base $end +$var wire 1 A$ Y $end +$var wire 1 L, A $end +$var wire 1 5- not0_out_Y $end +$upscope $end +$upscope $end + +$scope module BINV_R_93 $end +$var wire 1 L, Y $end +$var wire 1 J, A $end +$var supply1 1 6- VPWR $end +$var supply0 1 7- VGND $end +$var supply1 1 8- VPB $end +$var supply0 1 9- VNB $end + +$scope module base $end +$var wire 1 L, Y $end +$var wire 1 J, A $end +$var wire 1 :- not0_out_Y $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mux_bottom_track_11 $end +$var wire 1 l# in [0] $end +$var wire 1 o# in [1] $end +$var wire 1 r# in [2] $end +$var wire 1 y# in [3] $end +$var wire 1 Y& sram [0] $end +$var wire 1 Z& sram [1] $end +$var wire 1 [& sram [2] $end +$var wire 1 \& sram [3] $end +$var wire 1 2' sram_inv [0] $end +$var wire 1 3' sram_inv [1] $end +$var wire 1 4' sram_inv [2] $end +$var wire 1 5' sram_inv [3] $end +$var wire 1 B$ out [0] $end +$var wire 1 (' p0 $end +$var wire 1 ;- local_encoder2to3_0_data [0] $end +$var wire 1 <- local_encoder2to3_0_data [1] $end +$var wire 1 =- local_encoder2to3_0_data [2] $end +$var wire 1 >- local_encoder2to3_0_data_inv [0] $end +$var wire 1 ?- local_encoder2to3_0_data_inv [1] $end +$var wire 1 @- local_encoder2to3_0_data_inv [2] $end +$var wire 1 A- local_encoder2to3_1_data [0] $end +$var wire 1 B- local_encoder2to3_1_data [1] $end +$var wire 1 C- local_encoder2to3_1_data [2] $end +$var wire 1 D- local_encoder2to3_1_data_inv [0] $end +$var wire 1 E- local_encoder2to3_1_data_inv [1] $end +$var wire 1 F- local_encoder2to3_1_data_inv [2] $end +$var wire 1 G- mux_2level_tapbuf_basis_input3_mem3_0_out [0] $end +$var wire 1 H- mux_2level_tapbuf_basis_input3_mem3_1_out [0] $end +$var wire 1 I- SYNOPSYS_UNCONNECTED_1 $end +$var wire 1 J- BUF_net_95 $end + +$scope module local_encoder2to3_0_ $end +$var wire 1 Y& addr [0] $end +$var wire 1 Z& addr [1] $end +$var wire 1 ;- data [0] $end +$var wire 1 <- data [1] $end +$var wire 1 =- data [2] $end +$var wire 1 >- data_inv [0] $end +$var wire 1 ?- data_inv [1] $end +$var wire 1 @- data_inv [2] $end + +$scope module U8 $end +$var wire 1 >- Y $end +$var wire 1 ;- A $end +$var supply1 1 K- VPWR $end +$var supply0 1 L- VGND $end +$var supply1 1 M- VPB $end +$var supply0 1 N- VNB $end + +$scope module base $end +$var wire 1 >- Y $end +$var wire 1 ;- A $end +$var wire 1 O- not0_out_Y $end +$upscope $end +$upscope $end + +$scope module U9 $end +$var wire 1 <- Y $end +$var wire 1 ?- A $end +$var supply1 1 P- VPWR $end +$var supply0 1 Q- VGND $end +$var supply1 1 R- VPB $end +$var supply0 1 S- VNB $end + +$scope module base $end +$var wire 1 <- Y $end +$var wire 1 ?- A $end +$var wire 1 T- not0_out_Y $end +$upscope $end +$upscope $end + +$scope module U10 $end +$var wire 1 ?- Y $end +$var wire 1 Y& A $end +$var wire 1 @- B $end +$var supply1 1 U- VPWR $end +$var supply0 1 V- VGND $end +$var supply1 1 W- VPB $end +$var supply0 1 X- VNB $end + +$scope module base $end +$var wire 1 ?- Y $end +$var wire 1 Y& A $end +$var wire 1 @- B $end +$var wire 1 Y- nand0_out_Y $end +$upscope $end +$upscope $end + +$scope module U11 $end +$var wire 1 @- Y $end +$var wire 1 =- A $end +$var supply1 1 Z- VPWR $end +$var supply0 1 [- VGND $end +$var supply1 1 \- VPB $end +$var supply0 1 ]- VNB $end + +$scope module base $end +$var wire 1 @- Y $end +$var wire 1 =- A $end +$var wire 1 ^- not0_out_Y $end +$upscope $end +$upscope $end + +$scope module U12 $end +$var wire 1 ;- Y $end +$var wire 1 =- A $end +$var wire 1 Y& B $end +$var supply1 1 _- VPWR $end +$var supply0 1 `- VGND $end +$var supply1 1 a- VPB $end +$var supply0 1 b- VNB $end + +$scope module base $end +$var wire 1 ;- Y $end +$var wire 1 =- A $end +$var wire 1 Y& B $end +$var wire 1 c- nor0_out_Y $end +$upscope $end +$upscope $end + +$scope module FTB_11__10 $end +$var wire 1 =- X $end +$var wire 1 Z& A $end +$var supply1 1 d- VPWR $end +$var supply0 1 e- VGND $end +$var supply1 1 f- VPB $end +$var supply0 1 g- VNB $end + +$scope module base $end +$var wire 1 =- X $end +$var wire 1 Z& A $end +$var wire 1 h- buf0_out_X $end +$upscope $end +$upscope $end +$upscope $end + +$scope module local_encoder2to3_1_ $end +$var wire 1 [& addr [0] $end +$var wire 1 \& addr [1] $end +$var wire 1 A- data [0] $end +$var wire 1 B- data [1] $end +$var wire 1 C- data [2] $end +$var wire 1 D- data_inv [0] $end +$var wire 1 E- data_inv [1] $end +$var wire 1 F- data_inv [2] $end + +$scope module U8 $end +$var wire 1 D- Y $end +$var wire 1 A- A $end +$var supply1 1 i- VPWR $end +$var supply0 1 j- VGND $end +$var supply1 1 k- VPB $end +$var supply0 1 l- VNB $end + +$scope module base $end +$var wire 1 D- Y $end +$var wire 1 A- A $end +$var wire 1 m- not0_out_Y $end +$upscope $end +$upscope $end + +$scope module U9 $end +$var wire 1 B- Y $end +$var wire 1 E- A $end +$var supply1 1 n- VPWR $end +$var supply0 1 o- VGND $end +$var supply1 1 p- VPB $end +$var supply0 1 q- VNB $end + +$scope module base $end +$var wire 1 B- Y $end +$var wire 1 E- A $end +$var wire 1 r- not0_out_Y $end +$upscope $end +$upscope $end + +$scope module U10 $end +$var wire 1 E- Y $end +$var wire 1 [& A $end +$var wire 1 F- B $end +$var supply1 1 s- VPWR $end +$var supply0 1 t- VGND $end +$var supply1 1 u- VPB $end +$var supply0 1 v- VNB $end + +$scope module base $end +$var wire 1 E- Y $end +$var wire 1 [& A $end +$var wire 1 F- B $end +$var wire 1 w- nand0_out_Y $end +$upscope $end +$upscope $end + +$scope module U11 $end +$var wire 1 F- Y $end +$var wire 1 C- A $end +$var supply1 1 x- VPWR $end +$var supply0 1 y- VGND $end +$var supply1 1 z- VPB $end +$var supply0 1 {- VNB $end + +$scope module base $end +$var wire 1 F- Y $end +$var wire 1 C- A $end +$var wire 1 |- not0_out_Y $end +$upscope $end +$upscope $end + +$scope module U12 $end +$var wire 1 A- Y $end +$var wire 1 C- A $end +$var wire 1 [& B $end +$var supply1 1 }- VPWR $end +$var supply0 1 ~- VGND $end +$var supply1 1 !. VPB $end +$var supply0 1 ". VNB $end + +$scope module base $end +$var wire 1 A- Y $end +$var wire 1 C- A $end +$var wire 1 [& B $end +$var wire 1 #. nor0_out_Y $end +$upscope $end +$upscope $end + +$scope module FTB_12__11 $end +$var wire 1 C- X $end +$var wire 1 \& A $end +$var supply1 1 $. VPWR $end +$var supply0 1 %. VGND $end +$var supply1 1 &. VPB $end +$var supply0 1 '. VNB $end + +$scope module base $end +$var wire 1 C- X $end +$var wire 1 \& A $end +$var wire 1 (. buf0_out_X $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mux_l1_in_0_ $end +$var wire 1 l# in [0] $end +$var wire 1 o# in [1] $end +$var wire 1 r# in [2] $end +$var wire 1 ;- mem [0] $end +$var wire 1 <- mem [1] $end +$var wire 1 =- mem [2] $end +$var wire 1 >- mem_inv [0] $end +$var wire 1 ?- mem_inv [1] $end +$var wire 1 @- mem_inv [2] $end +$var wire 1 G- out [0] $end + +$scope module scs8hd_muxinv3_1_0 $end +$var wire 1 G- Z $end +$var wire 1 l# Q1 $end +$var wire 1 o# Q2 $end +$var wire 1 r# Q3 $end +$var wire 1 ;- S0 $end +$var wire 1 >- S0B $end +$var wire 1 <- S1 $end +$var wire 1 ?- S1B $end +$var wire 1 =- S2 $end +$var wire 1 @- S2B $end +$var wire 1 ). Q1__bar $end +$var wire 1 *. Q2__bar $end +$var wire 1 +. Q3__bar $end +$upscope $end +$upscope $end + +$scope module mux_l2_in_0_ $end +$var wire 1 G- in [0] $end +$var wire 1 y# in [1] $end +$var wire 1 I- in [2] $end +$var wire 1 A- mem [0] $end +$var wire 1 B- mem [1] $end +$var wire 1 C- mem [2] $end +$var wire 1 D- mem_inv [0] $end +$var wire 1 E- mem_inv [1] $end +$var wire 1 F- mem_inv [2] $end +$var wire 1 H- out [0] $end +$var wire 1 (' p0 $end + +$scope module scs8hd_muxinv3_1_0 $end +$var wire 1 H- Z $end +$var wire 1 G- Q1 $end +$var wire 1 y# Q2 $end +$var wire 1 (' Q3 $end +$var wire 1 A- S0 $end +$var wire 1 D- S0B $end +$var wire 1 B- S1 $end +$var wire 1 E- S1B $end +$var wire 1 C- S2 $end +$var wire 1 F- S2B $end +$var wire 1 ,. Q1__bar $end +$var wire 1 -. Q2__bar $end +$var wire 1 .. Q3__bar $end +$upscope $end +$upscope $end + +$scope module BINV_R_94 $end +$var wire 1 B$ Y $end +$var wire 1 J- A $end +$var supply1 1 /. VPWR $end +$var supply0 1 0. VGND $end +$var supply1 1 1. VPB $end +$var supply0 1 2. VNB $end + +$scope module base $end +$var wire 1 B$ Y $end +$var wire 1 J- A $end +$var wire 1 3. not0_out_Y $end +$upscope $end +$upscope $end + +$scope module BINV_R_95 $end +$var wire 1 J- Y $end +$var wire 1 H- A $end +$var supply1 1 4. VPWR $end +$var supply0 1 5. VGND $end +$var supply1 1 6. VPB $end +$var supply0 1 7. VNB $end + +$scope module base $end +$var wire 1 J- Y $end +$var wire 1 H- A $end +$var wire 1 8. not0_out_Y $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mux_left_track_1 $end +$var wire 1 i# in [0] $end +$var wire 1 3$ in [1] $end +$var wire 1 6$ in [2] $end +$var wire 1 9$ in [3] $end +$var wire 1 ]& sram [0] $end +$var wire 1 ^& sram [1] $end +$var wire 1 _& sram [2] $end +$var wire 1 `& sram [3] $end +$var wire 1 6' sram_inv [0] $end +$var wire 1 7' sram_inv [1] $end +$var wire 1 8' sram_inv [2] $end +$var wire 1 9' sram_inv [3] $end +$var wire 1 [$ out [0] $end +$var wire 1 (' p0 $end +$var wire 1 9. local_encoder2to3_0_data [0] $end +$var wire 1 :. local_encoder2to3_0_data [1] $end +$var wire 1 ;. local_encoder2to3_0_data [2] $end +$var wire 1 <. local_encoder2to3_0_data_inv [0] $end +$var wire 1 =. local_encoder2to3_0_data_inv [1] $end +$var wire 1 >. local_encoder2to3_0_data_inv [2] $end +$var wire 1 ?. local_encoder2to3_1_data [0] $end +$var wire 1 @. local_encoder2to3_1_data [1] $end +$var wire 1 A. local_encoder2to3_1_data [2] $end +$var wire 1 B. local_encoder2to3_1_data_inv [0] $end +$var wire 1 C. local_encoder2to3_1_data_inv [1] $end +$var wire 1 D. local_encoder2to3_1_data_inv [2] $end +$var wire 1 E. mux_2level_tapbuf_basis_input3_mem3_0_out [0] $end +$var wire 1 F. mux_2level_tapbuf_basis_input3_mem3_1_out [0] $end +$var wire 1 G. SYNOPSYS_UNCONNECTED_1 $end +$var wire 1 H. BUF_net_97 $end + +$scope module local_encoder2to3_0_ $end +$var wire 1 ]& addr [0] $end +$var wire 1 ^& addr [1] $end +$var wire 1 9. data [0] $end +$var wire 1 :. data [1] $end +$var wire 1 ;. data [2] $end +$var wire 1 <. data_inv [0] $end +$var wire 1 =. data_inv [1] $end +$var wire 1 >. data_inv [2] $end + +$scope module U8 $end +$var wire 1 <. Y $end +$var wire 1 9. A $end +$var supply1 1 I. VPWR $end +$var supply0 1 J. VGND $end +$var supply1 1 K. VPB $end +$var supply0 1 L. VNB $end + +$scope module base $end +$var wire 1 <. Y $end +$var wire 1 9. A $end +$var wire 1 M. not0_out_Y $end +$upscope $end +$upscope $end + +$scope module U9 $end +$var wire 1 :. Y $end +$var wire 1 =. A $end +$var supply1 1 N. VPWR $end +$var supply0 1 O. VGND $end +$var supply1 1 P. VPB $end +$var supply0 1 Q. VNB $end + +$scope module base $end +$var wire 1 :. Y $end +$var wire 1 =. A $end +$var wire 1 R. not0_out_Y $end +$upscope $end +$upscope $end + +$scope module U10 $end +$var wire 1 =. Y $end +$var wire 1 ]& A $end +$var wire 1 >. B $end +$var supply1 1 S. VPWR $end +$var supply0 1 T. VGND $end +$var supply1 1 U. VPB $end +$var supply0 1 V. VNB $end + +$scope module base $end +$var wire 1 =. Y $end +$var wire 1 ]& A $end +$var wire 1 >. B $end +$var wire 1 W. nand0_out_Y $end +$upscope $end +$upscope $end + +$scope module U11 $end +$var wire 1 >. Y $end +$var wire 1 ;. A $end +$var supply1 1 X. VPWR $end +$var supply0 1 Y. VGND $end +$var supply1 1 Z. VPB $end +$var supply0 1 [. VNB $end + +$scope module base $end +$var wire 1 >. Y $end +$var wire 1 ;. A $end +$var wire 1 \. not0_out_Y $end +$upscope $end +$upscope $end + +$scope module U12 $end +$var wire 1 9. Y $end +$var wire 1 ;. A $end +$var wire 1 ]& B $end +$var supply1 1 ]. VPWR $end +$var supply0 1 ^. VGND $end +$var supply1 1 _. VPB $end +$var supply0 1 `. VNB $end + +$scope module base $end +$var wire 1 9. Y $end +$var wire 1 ;. A $end +$var wire 1 ]& B $end +$var wire 1 a. nor0_out_Y $end +$upscope $end +$upscope $end + +$scope module FTB_13__12 $end +$var wire 1 ;. X $end +$var wire 1 ^& A $end +$var supply1 1 b. VPWR $end +$var supply0 1 c. VGND $end +$var supply1 1 d. VPB $end +$var supply0 1 e. VNB $end + +$scope module base $end +$var wire 1 ;. X $end +$var wire 1 ^& A $end +$var wire 1 f. buf0_out_X $end +$upscope $end +$upscope $end +$upscope $end + +$scope module local_encoder2to3_1_ $end +$var wire 1 _& addr [0] $end +$var wire 1 `& addr [1] $end +$var wire 1 ?. data [0] $end +$var wire 1 @. data [1] $end +$var wire 1 A. data [2] $end +$var wire 1 B. data_inv [0] $end +$var wire 1 C. data_inv [1] $end +$var wire 1 D. data_inv [2] $end + +$scope module U8 $end +$var wire 1 B. Y $end +$var wire 1 ?. A $end +$var supply1 1 g. VPWR $end +$var supply0 1 h. VGND $end +$var supply1 1 i. VPB $end +$var supply0 1 j. VNB $end + +$scope module base $end +$var wire 1 B. Y $end +$var wire 1 ?. A $end +$var wire 1 k. not0_out_Y $end +$upscope $end +$upscope $end + +$scope module U9 $end +$var wire 1 @. Y $end +$var wire 1 C. A $end +$var supply1 1 l. VPWR $end +$var supply0 1 m. VGND $end +$var supply1 1 n. VPB $end +$var supply0 1 o. VNB $end + +$scope module base $end +$var wire 1 @. Y $end +$var wire 1 C. A $end +$var wire 1 p. not0_out_Y $end +$upscope $end +$upscope $end + +$scope module U10 $end +$var wire 1 C. Y $end +$var wire 1 _& A $end +$var wire 1 D. B $end +$var supply1 1 q. VPWR $end +$var supply0 1 r. VGND $end +$var supply1 1 s. VPB $end +$var supply0 1 t. VNB $end + +$scope module base $end +$var wire 1 C. Y $end +$var wire 1 _& A $end +$var wire 1 D. B $end +$var wire 1 u. nand0_out_Y $end +$upscope $end +$upscope $end + +$scope module U11 $end +$var wire 1 D. Y $end +$var wire 1 A. A $end +$var supply1 1 v. VPWR $end +$var supply0 1 w. VGND $end +$var supply1 1 x. VPB $end +$var supply0 1 y. VNB $end + +$scope module base $end +$var wire 1 D. Y $end +$var wire 1 A. A $end +$var wire 1 z. not0_out_Y $end +$upscope $end +$upscope $end + +$scope module U12 $end +$var wire 1 ?. Y $end +$var wire 1 A. A $end +$var wire 1 _& B $end +$var supply1 1 {. VPWR $end +$var supply0 1 |. VGND $end +$var supply1 1 }. VPB $end +$var supply0 1 ~. VNB $end + +$scope module base $end +$var wire 1 ?. Y $end +$var wire 1 A. A $end +$var wire 1 _& B $end +$var wire 1 !/ nor0_out_Y $end +$upscope $end +$upscope $end + +$scope module FTB_14__13 $end +$var wire 1 A. X $end +$var wire 1 `& A $end +$var supply1 1 "/ VPWR $end +$var supply0 1 #/ VGND $end +$var supply1 1 $/ VPB $end +$var supply0 1 %/ VNB $end + +$scope module base $end +$var wire 1 A. X $end +$var wire 1 `& A $end +$var wire 1 &/ buf0_out_X $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mux_l1_in_0_ $end +$var wire 1 i# in [0] $end +$var wire 1 3$ in [1] $end +$var wire 1 6$ in [2] $end +$var wire 1 9. mem [0] $end +$var wire 1 :. mem [1] $end +$var wire 1 ;. mem [2] $end +$var wire 1 <. mem_inv [0] $end +$var wire 1 =. mem_inv [1] $end +$var wire 1 >. mem_inv [2] $end +$var wire 1 E. out [0] $end + +$scope module scs8hd_muxinv3_1_0 $end +$var wire 1 E. Z $end +$var wire 1 i# Q1 $end +$var wire 1 3$ Q2 $end +$var wire 1 6$ Q3 $end +$var wire 1 9. S0 $end +$var wire 1 <. S0B $end +$var wire 1 :. S1 $end +$var wire 1 =. S1B $end +$var wire 1 ;. S2 $end +$var wire 1 >. S2B $end +$var wire 1 '/ Q1__bar $end +$var wire 1 (/ Q2__bar $end +$var wire 1 )/ Q3__bar $end +$upscope $end +$upscope $end + +$scope module mux_l2_in_0_ $end +$var wire 1 E. in [0] $end +$var wire 1 9$ in [1] $end +$var wire 1 G. in [2] $end +$var wire 1 ?. mem [0] $end +$var wire 1 @. mem [1] $end +$var wire 1 A. mem [2] $end +$var wire 1 B. mem_inv [0] $end +$var wire 1 C. mem_inv [1] $end +$var wire 1 D. mem_inv [2] $end +$var wire 1 F. out [0] $end +$var wire 1 (' p0 $end + +$scope module scs8hd_muxinv3_1_0 $end +$var wire 1 F. Z $end +$var wire 1 E. Q1 $end +$var wire 1 9$ Q2 $end +$var wire 1 (' Q3 $end +$var wire 1 ?. S0 $end +$var wire 1 B. S0B $end +$var wire 1 @. S1 $end +$var wire 1 C. S1B $end +$var wire 1 A. S2 $end +$var wire 1 D. S2B $end +$var wire 1 */ Q1__bar $end +$var wire 1 +/ Q2__bar $end +$var wire 1 ,/ Q3__bar $end +$upscope $end +$upscope $end + +$scope module BINV_R_96 $end +$var wire 1 [$ Y $end +$var wire 1 H. A $end +$var supply1 1 -/ VPWR $end +$var supply0 1 ./ VGND $end +$var supply1 1 // VPB $end +$var supply0 1 0/ VNB $end + +$scope module base $end +$var wire 1 [$ Y $end +$var wire 1 H. A $end +$var wire 1 1/ not0_out_Y $end +$upscope $end +$upscope $end + +$scope module BINV_R_97 $end +$var wire 1 H. Y $end +$var wire 1 F. A $end +$var supply1 1 2/ VPWR $end +$var supply0 1 3/ VGND $end +$var supply1 1 4/ VPB $end +$var supply0 1 5/ VNB $end + +$scope module base $end +$var wire 1 H. Y $end +$var wire 1 F. A $end +$var wire 1 6/ not0_out_Y $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mux_left_track_3 $end +$var wire 1 L# in [0] $end +$var wire 1 4$ in [1] $end +$var wire 1 7$ in [2] $end +$var wire 1 :$ in [3] $end +$var wire 1 a& sram [0] $end +$var wire 1 b& sram [1] $end +$var wire 1 c& sram [2] $end +$var wire 1 d& sram [3] $end +$var wire 1 :' sram_inv [0] $end +$var wire 1 ;' sram_inv [1] $end +$var wire 1 <' sram_inv [2] $end +$var wire 1 =' sram_inv [3] $end +$var wire 1 \$ out [0] $end +$var wire 1 (' p0 $end +$var wire 1 7/ local_encoder2to3_0_data [0] $end +$var wire 1 8/ local_encoder2to3_0_data [1] $end +$var wire 1 9/ local_encoder2to3_0_data [2] $end +$var wire 1 :/ local_encoder2to3_0_data_inv [0] $end +$var wire 1 ;/ local_encoder2to3_0_data_inv [1] $end +$var wire 1 / local_encoder2to3_1_data [1] $end +$var wire 1 ?/ local_encoder2to3_1_data [2] $end +$var wire 1 @/ local_encoder2to3_1_data_inv [0] $end +$var wire 1 A/ local_encoder2to3_1_data_inv [1] $end +$var wire 1 B/ local_encoder2to3_1_data_inv [2] $end +$var wire 1 C/ mux_2level_tapbuf_basis_input3_mem3_0_out [0] $end +$var wire 1 D/ mux_2level_tapbuf_basis_input3_mem3_1_out [0] $end +$var wire 1 E/ SYNOPSYS_UNCONNECTED_1 $end +$var wire 1 F/ BUF_net_99 $end + +$scope module local_encoder2to3_0_ $end +$var wire 1 a& addr [0] $end +$var wire 1 b& addr [1] $end +$var wire 1 7/ data [0] $end +$var wire 1 8/ data [1] $end +$var wire 1 9/ data [2] $end +$var wire 1 :/ data_inv [0] $end +$var wire 1 ;/ data_inv [1] $end +$var wire 1 / data [1] $end +$var wire 1 ?/ data [2] $end +$var wire 1 @/ data_inv [0] $end +$var wire 1 A/ data_inv [1] $end +$var wire 1 B/ data_inv [2] $end + +$scope module U8 $end +$var wire 1 @/ Y $end +$var wire 1 =/ A $end +$var supply1 1 e/ VPWR $end +$var supply0 1 f/ VGND $end +$var supply1 1 g/ VPB $end +$var supply0 1 h/ VNB $end + +$scope module base $end +$var wire 1 @/ Y $end +$var wire 1 =/ A $end +$var wire 1 i/ not0_out_Y $end +$upscope $end +$upscope $end + +$scope module U9 $end +$var wire 1 >/ Y $end +$var wire 1 A/ A $end +$var supply1 1 j/ VPWR $end +$var supply0 1 k/ VGND $end +$var supply1 1 l/ VPB $end +$var supply0 1 m/ VNB $end + +$scope module base $end +$var wire 1 >/ Y $end +$var wire 1 A/ A $end +$var wire 1 n/ not0_out_Y $end +$upscope $end +$upscope $end + +$scope module U10 $end +$var wire 1 A/ Y $end +$var wire 1 c& A $end +$var wire 1 B/ B $end +$var supply1 1 o/ VPWR $end +$var supply0 1 p/ VGND $end +$var supply1 1 q/ VPB $end +$var supply0 1 r/ VNB $end + +$scope module base $end +$var wire 1 A/ Y $end +$var wire 1 c& A $end +$var wire 1 B/ B $end +$var wire 1 s/ nand0_out_Y $end +$upscope $end +$upscope $end + +$scope module U11 $end +$var wire 1 B/ Y $end +$var wire 1 ?/ A $end +$var supply1 1 t/ VPWR $end +$var supply0 1 u/ VGND $end +$var supply1 1 v/ VPB $end +$var supply0 1 w/ VNB $end + +$scope module base $end +$var wire 1 B/ Y $end +$var wire 1 ?/ A $end +$var wire 1 x/ not0_out_Y $end +$upscope $end +$upscope $end + +$scope module U12 $end +$var wire 1 =/ Y $end +$var wire 1 ?/ A $end +$var wire 1 c& B $end +$var supply1 1 y/ VPWR $end +$var supply0 1 z/ VGND $end +$var supply1 1 {/ VPB $end +$var supply0 1 |/ VNB $end + +$scope module base $end +$var wire 1 =/ Y $end +$var wire 1 ?/ A $end +$var wire 1 c& B $end +$var wire 1 }/ nor0_out_Y $end +$upscope $end +$upscope $end + +$scope module FTB_16__15 $end +$var wire 1 ?/ X $end +$var wire 1 d& A $end +$var supply1 1 ~/ VPWR $end +$var supply0 1 !0 VGND $end +$var supply1 1 "0 VPB $end +$var supply0 1 #0 VNB $end + +$scope module base $end +$var wire 1 ?/ X $end +$var wire 1 d& A $end +$var wire 1 $0 buf0_out_X $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mux_l1_in_0_ $end +$var wire 1 L# in [0] $end +$var wire 1 4$ in [1] $end +$var wire 1 7$ in [2] $end +$var wire 1 7/ mem [0] $end +$var wire 1 8/ mem [1] $end +$var wire 1 9/ mem [2] $end +$var wire 1 :/ mem_inv [0] $end +$var wire 1 ;/ mem_inv [1] $end +$var wire 1 / mem [1] $end +$var wire 1 ?/ mem [2] $end +$var wire 1 @/ mem_inv [0] $end +$var wire 1 A/ mem_inv [1] $end +$var wire 1 B/ mem_inv [2] $end +$var wire 1 D/ out [0] $end +$var wire 1 (' p0 $end + +$scope module scs8hd_muxinv3_1_0 $end +$var wire 1 D/ Z $end +$var wire 1 C/ Q1 $end +$var wire 1 :$ Q2 $end +$var wire 1 (' Q3 $end +$var wire 1 =/ S0 $end +$var wire 1 @/ S0B $end +$var wire 1 >/ S1 $end +$var wire 1 A/ S1B $end +$var wire 1 ?/ S2 $end +$var wire 1 B/ S2B $end +$var wire 1 (0 Q1__bar $end +$var wire 1 )0 Q2__bar $end +$var wire 1 *0 Q3__bar $end +$upscope $end +$upscope $end + +$scope module BINV_R_98 $end +$var wire 1 \$ Y $end +$var wire 1 F/ A $end +$var supply1 1 +0 VPWR $end +$var supply0 1 ,0 VGND $end +$var supply1 1 -0 VPB $end +$var supply0 1 .0 VNB $end + +$scope module base $end +$var wire 1 \$ Y $end +$var wire 1 F/ A $end +$var wire 1 /0 not0_out_Y $end +$upscope $end +$upscope $end + +$scope module BINV_R_99 $end +$var wire 1 F/ Y $end +$var wire 1 D/ A $end +$var supply1 1 00 VPWR $end +$var supply0 1 10 VGND $end +$var supply1 1 20 VPB $end +$var supply0 1 30 VNB $end + +$scope module base $end +$var wire 1 F/ Y $end +$var wire 1 D/ A $end +$var wire 1 40 not0_out_Y $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mux_left_track_5 $end +$var wire 1 M# in [0] $end +$var wire 1 5$ in [1] $end +$var wire 1 8$ in [2] $end +$var wire 1 ;$ in [3] $end +$var wire 1 e& sram [0] $end +$var wire 1 f& sram [1] $end +$var wire 1 g& sram [2] $end +$var wire 1 h& sram [3] $end +$var wire 1 >' sram_inv [0] $end +$var wire 1 ?' sram_inv [1] $end +$var wire 1 @' sram_inv [2] $end +$var wire 1 A' sram_inv [3] $end +$var wire 1 ]$ out [0] $end +$var wire 1 (' p0 $end +$var wire 1 50 local_encoder2to3_0_data [0] $end +$var wire 1 60 local_encoder2to3_0_data [1] $end +$var wire 1 70 local_encoder2to3_0_data [2] $end +$var wire 1 80 local_encoder2to3_0_data_inv [0] $end +$var wire 1 90 local_encoder2to3_0_data_inv [1] $end +$var wire 1 :0 local_encoder2to3_0_data_inv [2] $end +$var wire 1 ;0 local_encoder2to3_1_data [0] $end +$var wire 1 <0 local_encoder2to3_1_data [1] $end +$var wire 1 =0 local_encoder2to3_1_data [2] $end +$var wire 1 >0 local_encoder2to3_1_data_inv [0] $end +$var wire 1 ?0 local_encoder2to3_1_data_inv [1] $end +$var wire 1 @0 local_encoder2to3_1_data_inv [2] $end +$var wire 1 A0 mux_2level_tapbuf_basis_input3_mem3_0_out [0] $end +$var wire 1 B0 mux_2level_tapbuf_basis_input3_mem3_1_out [0] $end +$var wire 1 C0 SYNOPSYS_UNCONNECTED_1 $end +$var wire 1 D0 BUF_net_101 $end + +$scope module local_encoder2to3_0_ $end +$var wire 1 e& addr [0] $end +$var wire 1 f& addr [1] $end +$var wire 1 50 data [0] $end +$var wire 1 60 data [1] $end +$var wire 1 70 data [2] $end +$var wire 1 80 data_inv [0] $end +$var wire 1 90 data_inv [1] $end +$var wire 1 :0 data_inv [2] $end + +$scope module U8 $end +$var wire 1 80 Y $end +$var wire 1 50 A $end +$var supply1 1 E0 VPWR $end +$var supply0 1 F0 VGND $end +$var supply1 1 G0 VPB $end +$var supply0 1 H0 VNB $end + +$scope module base $end +$var wire 1 80 Y $end +$var wire 1 50 A $end +$var wire 1 I0 not0_out_Y $end +$upscope $end +$upscope $end + +$scope module U9 $end +$var wire 1 60 Y $end +$var wire 1 90 A $end +$var supply1 1 J0 VPWR $end +$var supply0 1 K0 VGND $end +$var supply1 1 L0 VPB $end +$var supply0 1 M0 VNB $end + +$scope module base $end +$var wire 1 60 Y $end +$var wire 1 90 A $end +$var wire 1 N0 not0_out_Y $end +$upscope $end +$upscope $end + +$scope module U10 $end +$var wire 1 90 Y $end +$var wire 1 e& A $end +$var wire 1 :0 B $end +$var supply1 1 O0 VPWR $end +$var supply0 1 P0 VGND $end +$var supply1 1 Q0 VPB $end +$var supply0 1 R0 VNB $end + +$scope module base $end +$var wire 1 90 Y $end +$var wire 1 e& A $end +$var wire 1 :0 B $end +$var wire 1 S0 nand0_out_Y $end +$upscope $end +$upscope $end + +$scope module U11 $end +$var wire 1 :0 Y $end +$var wire 1 70 A $end +$var supply1 1 T0 VPWR $end +$var supply0 1 U0 VGND $end +$var supply1 1 V0 VPB $end +$var supply0 1 W0 VNB $end + +$scope module base $end +$var wire 1 :0 Y $end +$var wire 1 70 A $end +$var wire 1 X0 not0_out_Y $end +$upscope $end +$upscope $end + +$scope module U12 $end +$var wire 1 50 Y $end +$var wire 1 70 A $end +$var wire 1 e& B $end +$var supply1 1 Y0 VPWR $end +$var supply0 1 Z0 VGND $end +$var supply1 1 [0 VPB $end +$var supply0 1 \0 VNB $end + +$scope module base $end +$var wire 1 50 Y $end +$var wire 1 70 A $end +$var wire 1 e& B $end +$var wire 1 ]0 nor0_out_Y $end +$upscope $end +$upscope $end + +$scope module FTB_17__16 $end +$var wire 1 70 X $end +$var wire 1 f& A $end +$var supply1 1 ^0 VPWR $end +$var supply0 1 _0 VGND $end +$var supply1 1 `0 VPB $end +$var supply0 1 a0 VNB $end + +$scope module base $end +$var wire 1 70 X $end +$var wire 1 f& A $end +$var wire 1 b0 buf0_out_X $end +$upscope $end +$upscope $end +$upscope $end + +$scope module local_encoder2to3_1_ $end +$var wire 1 g& addr [0] $end +$var wire 1 h& addr [1] $end +$var wire 1 ;0 data [0] $end +$var wire 1 <0 data [1] $end +$var wire 1 =0 data [2] $end +$var wire 1 >0 data_inv [0] $end +$var wire 1 ?0 data_inv [1] $end +$var wire 1 @0 data_inv [2] $end + +$scope module U8 $end +$var wire 1 >0 Y $end +$var wire 1 ;0 A $end +$var supply1 1 c0 VPWR $end +$var supply0 1 d0 VGND $end +$var supply1 1 e0 VPB $end +$var supply0 1 f0 VNB $end + +$scope module base $end +$var wire 1 >0 Y $end +$var wire 1 ;0 A $end +$var wire 1 g0 not0_out_Y $end +$upscope $end +$upscope $end + +$scope module U9 $end +$var wire 1 <0 Y $end +$var wire 1 ?0 A $end +$var supply1 1 h0 VPWR $end +$var supply0 1 i0 VGND $end +$var supply1 1 j0 VPB $end +$var supply0 1 k0 VNB $end + +$scope module base $end +$var wire 1 <0 Y $end +$var wire 1 ?0 A $end +$var wire 1 l0 not0_out_Y $end +$upscope $end +$upscope $end + +$scope module U10 $end +$var wire 1 ?0 Y $end +$var wire 1 g& A $end +$var wire 1 @0 B $end +$var supply1 1 m0 VPWR $end +$var supply0 1 n0 VGND $end +$var supply1 1 o0 VPB $end +$var supply0 1 p0 VNB $end + +$scope module base $end +$var wire 1 ?0 Y $end +$var wire 1 g& A $end +$var wire 1 @0 B $end +$var wire 1 q0 nand0_out_Y $end +$upscope $end +$upscope $end + +$scope module U11 $end +$var wire 1 @0 Y $end +$var wire 1 =0 A $end +$var supply1 1 r0 VPWR $end +$var supply0 1 s0 VGND $end +$var supply1 1 t0 VPB $end +$var supply0 1 u0 VNB $end + +$scope module base $end +$var wire 1 @0 Y $end +$var wire 1 =0 A $end +$var wire 1 v0 not0_out_Y $end +$upscope $end +$upscope $end + +$scope module U12 $end +$var wire 1 ;0 Y $end +$var wire 1 =0 A $end +$var wire 1 g& B $end +$var supply1 1 w0 VPWR $end +$var supply0 1 x0 VGND $end +$var supply1 1 y0 VPB $end +$var supply0 1 z0 VNB $end + +$scope module base $end +$var wire 1 ;0 Y $end +$var wire 1 =0 A $end +$var wire 1 g& B $end +$var wire 1 {0 nor0_out_Y $end +$upscope $end +$upscope $end + +$scope module FTB_18__17 $end +$var wire 1 =0 X $end +$var wire 1 h& A $end +$var supply1 1 |0 VPWR $end +$var supply0 1 }0 VGND $end +$var supply1 1 ~0 VPB $end +$var supply0 1 !1 VNB $end + +$scope module base $end +$var wire 1 =0 X $end +$var wire 1 h& A $end +$var wire 1 "1 buf0_out_X $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mux_l1_in_0_ $end +$var wire 1 M# in [0] $end +$var wire 1 5$ in [1] $end +$var wire 1 8$ in [2] $end +$var wire 1 50 mem [0] $end +$var wire 1 60 mem [1] $end +$var wire 1 70 mem [2] $end +$var wire 1 80 mem_inv [0] $end +$var wire 1 90 mem_inv [1] $end +$var wire 1 :0 mem_inv [2] $end +$var wire 1 A0 out [0] $end + +$scope module scs8hd_muxinv3_1_0 $end +$var wire 1 A0 Z $end +$var wire 1 M# Q1 $end +$var wire 1 5$ Q2 $end +$var wire 1 8$ Q3 $end +$var wire 1 50 S0 $end +$var wire 1 80 S0B $end +$var wire 1 60 S1 $end +$var wire 1 90 S1B $end +$var wire 1 70 S2 $end +$var wire 1 :0 S2B $end +$var wire 1 #1 Q1__bar $end +$var wire 1 $1 Q2__bar $end +$var wire 1 %1 Q3__bar $end +$upscope $end +$upscope $end + +$scope module mux_l2_in_0_ $end +$var wire 1 A0 in [0] $end +$var wire 1 ;$ in [1] $end +$var wire 1 C0 in [2] $end +$var wire 1 ;0 mem [0] $end +$var wire 1 <0 mem [1] $end +$var wire 1 =0 mem [2] $end +$var wire 1 >0 mem_inv [0] $end +$var wire 1 ?0 mem_inv [1] $end +$var wire 1 @0 mem_inv [2] $end +$var wire 1 B0 out [0] $end +$var wire 1 (' p0 $end + +$scope module scs8hd_muxinv3_1_0 $end +$var wire 1 B0 Z $end +$var wire 1 A0 Q1 $end +$var wire 1 ;$ Q2 $end +$var wire 1 (' Q3 $end +$var wire 1 ;0 S0 $end +$var wire 1 >0 S0B $end +$var wire 1 <0 S1 $end +$var wire 1 ?0 S1B $end +$var wire 1 =0 S2 $end +$var wire 1 @0 S2B $end +$var wire 1 &1 Q1__bar $end +$var wire 1 '1 Q2__bar $end +$var wire 1 (1 Q3__bar $end +$upscope $end +$upscope $end + +$scope module BINV_R_100 $end +$var wire 1 ]$ Y $end +$var wire 1 D0 A $end +$var supply1 1 )1 VPWR $end +$var supply0 1 *1 VGND $end +$var supply1 1 +1 VPB $end +$var supply0 1 ,1 VNB $end + +$scope module base $end +$var wire 1 ]$ Y $end +$var wire 1 D0 A $end +$var wire 1 -1 not0_out_Y $end +$upscope $end +$upscope $end + +$scope module BINV_R_101 $end +$var wire 1 D0 Y $end +$var wire 1 B0 A $end +$var supply1 1 .1 VPWR $end +$var supply0 1 /1 VGND $end +$var supply1 1 01 VPB $end +$var supply0 1 11 VNB $end + +$scope module base $end +$var wire 1 D0 Y $end +$var wire 1 B0 A $end +$var wire 1 21 not0_out_Y $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mux_left_track_7 $end +$var wire 1 N# in [0] $end +$var wire 1 3$ in [1] $end +$var wire 1 6$ in [2] $end +$var wire 1 9$ in [3] $end +$var wire 1 i& sram [0] $end +$var wire 1 j& sram [1] $end +$var wire 1 k& sram [2] $end +$var wire 1 l& sram [3] $end +$var wire 1 B' sram_inv [0] $end +$var wire 1 C' sram_inv [1] $end +$var wire 1 D' sram_inv [2] $end +$var wire 1 E' sram_inv [3] $end +$var wire 1 ^$ out [0] $end +$var wire 1 (' p0 $end +$var wire 1 31 local_encoder2to3_0_data [0] $end +$var wire 1 41 local_encoder2to3_0_data [1] $end +$var wire 1 51 local_encoder2to3_0_data [2] $end +$var wire 1 61 local_encoder2to3_0_data_inv [0] $end +$var wire 1 71 local_encoder2to3_0_data_inv [1] $end +$var wire 1 81 local_encoder2to3_0_data_inv [2] $end +$var wire 1 91 local_encoder2to3_1_data [0] $end +$var wire 1 :1 local_encoder2to3_1_data [1] $end +$var wire 1 ;1 local_encoder2to3_1_data [2] $end +$var wire 1 <1 local_encoder2to3_1_data_inv [0] $end +$var wire 1 =1 local_encoder2to3_1_data_inv [1] $end +$var wire 1 >1 local_encoder2to3_1_data_inv [2] $end +$var wire 1 ?1 mux_2level_tapbuf_basis_input3_mem3_0_out [0] $end +$var wire 1 @1 mux_2level_tapbuf_basis_input3_mem3_1_out [0] $end +$var wire 1 A1 SYNOPSYS_UNCONNECTED_1 $end +$var wire 1 B1 BUF_net_103 $end + +$scope module local_encoder2to3_0_ $end +$var wire 1 i& addr [0] $end +$var wire 1 j& addr [1] $end +$var wire 1 31 data [0] $end +$var wire 1 41 data [1] $end +$var wire 1 51 data [2] $end +$var wire 1 61 data_inv [0] $end +$var wire 1 71 data_inv [1] $end +$var wire 1 81 data_inv [2] $end + +$scope module U8 $end +$var wire 1 61 Y $end +$var wire 1 31 A $end +$var supply1 1 C1 VPWR $end +$var supply0 1 D1 VGND $end +$var supply1 1 E1 VPB $end +$var supply0 1 F1 VNB $end + +$scope module base $end +$var wire 1 61 Y $end +$var wire 1 31 A $end +$var wire 1 G1 not0_out_Y $end +$upscope $end +$upscope $end + +$scope module U9 $end +$var wire 1 41 Y $end +$var wire 1 71 A $end +$var supply1 1 H1 VPWR $end +$var supply0 1 I1 VGND $end +$var supply1 1 J1 VPB $end +$var supply0 1 K1 VNB $end + +$scope module base $end +$var wire 1 41 Y $end +$var wire 1 71 A $end +$var wire 1 L1 not0_out_Y $end +$upscope $end +$upscope $end + +$scope module U10 $end +$var wire 1 71 Y $end +$var wire 1 i& A $end +$var wire 1 81 B $end +$var supply1 1 M1 VPWR $end +$var supply0 1 N1 VGND $end +$var supply1 1 O1 VPB $end +$var supply0 1 P1 VNB $end + +$scope module base $end +$var wire 1 71 Y $end +$var wire 1 i& A $end +$var wire 1 81 B $end +$var wire 1 Q1 nand0_out_Y $end +$upscope $end +$upscope $end + +$scope module U11 $end +$var wire 1 81 Y $end +$var wire 1 51 A $end +$var supply1 1 R1 VPWR $end +$var supply0 1 S1 VGND $end +$var supply1 1 T1 VPB $end +$var supply0 1 U1 VNB $end + +$scope module base $end +$var wire 1 81 Y $end +$var wire 1 51 A $end +$var wire 1 V1 not0_out_Y $end +$upscope $end +$upscope $end + +$scope module U12 $end +$var wire 1 31 Y $end +$var wire 1 51 A $end +$var wire 1 i& B $end +$var supply1 1 W1 VPWR $end +$var supply0 1 X1 VGND $end +$var supply1 1 Y1 VPB $end +$var supply0 1 Z1 VNB $end + +$scope module base $end +$var wire 1 31 Y $end +$var wire 1 51 A $end +$var wire 1 i& B $end +$var wire 1 [1 nor0_out_Y $end +$upscope $end +$upscope $end + +$scope module FTB_19__18 $end +$var wire 1 51 X $end +$var wire 1 j& A $end +$var supply1 1 \1 VPWR $end +$var supply0 1 ]1 VGND $end +$var supply1 1 ^1 VPB $end +$var supply0 1 _1 VNB $end + +$scope module base $end +$var wire 1 51 X $end +$var wire 1 j& A $end +$var wire 1 `1 buf0_out_X $end +$upscope $end +$upscope $end +$upscope $end + +$scope module local_encoder2to3_1_ $end +$var wire 1 k& addr [0] $end +$var wire 1 l& addr [1] $end +$var wire 1 91 data [0] $end +$var wire 1 :1 data [1] $end +$var wire 1 ;1 data [2] $end +$var wire 1 <1 data_inv [0] $end +$var wire 1 =1 data_inv [1] $end +$var wire 1 >1 data_inv [2] $end + +$scope module U8 $end +$var wire 1 <1 Y $end +$var wire 1 91 A $end +$var supply1 1 a1 VPWR $end +$var supply0 1 b1 VGND $end +$var supply1 1 c1 VPB $end +$var supply0 1 d1 VNB $end + +$scope module base $end +$var wire 1 <1 Y $end +$var wire 1 91 A $end +$var wire 1 e1 not0_out_Y $end +$upscope $end +$upscope $end + +$scope module U9 $end +$var wire 1 :1 Y $end +$var wire 1 =1 A $end +$var supply1 1 f1 VPWR $end +$var supply0 1 g1 VGND $end +$var supply1 1 h1 VPB $end +$var supply0 1 i1 VNB $end + +$scope module base $end +$var wire 1 :1 Y $end +$var wire 1 =1 A $end +$var wire 1 j1 not0_out_Y $end +$upscope $end +$upscope $end + +$scope module U10 $end +$var wire 1 =1 Y $end +$var wire 1 k& A $end +$var wire 1 >1 B $end +$var supply1 1 k1 VPWR $end +$var supply0 1 l1 VGND $end +$var supply1 1 m1 VPB $end +$var supply0 1 n1 VNB $end + +$scope module base $end +$var wire 1 =1 Y $end +$var wire 1 k& A $end +$var wire 1 >1 B $end +$var wire 1 o1 nand0_out_Y $end +$upscope $end +$upscope $end + +$scope module U11 $end +$var wire 1 >1 Y $end +$var wire 1 ;1 A $end +$var supply1 1 p1 VPWR $end +$var supply0 1 q1 VGND $end +$var supply1 1 r1 VPB $end +$var supply0 1 s1 VNB $end + +$scope module base $end +$var wire 1 >1 Y $end +$var wire 1 ;1 A $end +$var wire 1 t1 not0_out_Y $end +$upscope $end +$upscope $end + +$scope module U12 $end +$var wire 1 91 Y $end +$var wire 1 ;1 A $end +$var wire 1 k& B $end +$var supply1 1 u1 VPWR $end +$var supply0 1 v1 VGND $end +$var supply1 1 w1 VPB $end +$var supply0 1 x1 VNB $end + +$scope module base $end +$var wire 1 91 Y $end +$var wire 1 ;1 A $end +$var wire 1 k& B $end +$var wire 1 y1 nor0_out_Y $end +$upscope $end +$upscope $end + +$scope module FTB_20__19 $end +$var wire 1 ;1 X $end +$var wire 1 l& A $end +$var supply1 1 z1 VPWR $end +$var supply0 1 {1 VGND $end +$var supply1 1 |1 VPB $end +$var supply0 1 }1 VNB $end + +$scope module base $end +$var wire 1 ;1 X $end +$var wire 1 l& A $end +$var wire 1 ~1 buf0_out_X $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mux_l1_in_0_ $end +$var wire 1 N# in [0] $end +$var wire 1 3$ in [1] $end +$var wire 1 6$ in [2] $end +$var wire 1 31 mem [0] $end +$var wire 1 41 mem [1] $end +$var wire 1 51 mem [2] $end +$var wire 1 61 mem_inv [0] $end +$var wire 1 71 mem_inv [1] $end +$var wire 1 81 mem_inv [2] $end +$var wire 1 ?1 out [0] $end + +$scope module scs8hd_muxinv3_1_0 $end +$var wire 1 ?1 Z $end +$var wire 1 N# Q1 $end +$var wire 1 3$ Q2 $end +$var wire 1 6$ Q3 $end +$var wire 1 31 S0 $end +$var wire 1 61 S0B $end +$var wire 1 41 S1 $end +$var wire 1 71 S1B $end +$var wire 1 51 S2 $end +$var wire 1 81 S2B $end +$var wire 1 !2 Q1__bar $end +$var wire 1 "2 Q2__bar $end +$var wire 1 #2 Q3__bar $end +$upscope $end +$upscope $end + +$scope module mux_l2_in_0_ $end +$var wire 1 ?1 in [0] $end +$var wire 1 9$ in [1] $end +$var wire 1 A1 in [2] $end +$var wire 1 91 mem [0] $end +$var wire 1 :1 mem [1] $end +$var wire 1 ;1 mem [2] $end +$var wire 1 <1 mem_inv [0] $end +$var wire 1 =1 mem_inv [1] $end +$var wire 1 >1 mem_inv [2] $end +$var wire 1 @1 out [0] $end +$var wire 1 (' p0 $end + +$scope module scs8hd_muxinv3_1_0 $end +$var wire 1 @1 Z $end +$var wire 1 ?1 Q1 $end +$var wire 1 9$ Q2 $end +$var wire 1 (' Q3 $end +$var wire 1 91 S0 $end +$var wire 1 <1 S0B $end +$var wire 1 :1 S1 $end +$var wire 1 =1 S1B $end +$var wire 1 ;1 S2 $end +$var wire 1 >1 S2B $end +$var wire 1 $2 Q1__bar $end +$var wire 1 %2 Q2__bar $end +$var wire 1 &2 Q3__bar $end +$upscope $end +$upscope $end + +$scope module BINV_R_102 $end +$var wire 1 ^$ Y $end +$var wire 1 B1 A $end +$var supply1 1 '2 VPWR $end +$var supply0 1 (2 VGND $end +$var supply1 1 )2 VPB $end +$var supply0 1 *2 VNB $end + +$scope module base $end +$var wire 1 ^$ Y $end +$var wire 1 B1 A $end +$var wire 1 +2 not0_out_Y $end +$upscope $end +$upscope $end + +$scope module BINV_R_103 $end +$var wire 1 B1 Y $end +$var wire 1 @1 A $end +$var supply1 1 ,2 VPWR $end +$var supply0 1 -2 VGND $end +$var supply1 1 .2 VPB $end +$var supply0 1 /2 VNB $end + +$scope module base $end +$var wire 1 B1 Y $end +$var wire 1 @1 A $end +$var wire 1 02 not0_out_Y $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mux_left_track_9 $end +$var wire 1 O# in [0] $end +$var wire 1 4$ in [1] $end +$var wire 1 7$ in [2] $end +$var wire 1 :$ in [3] $end +$var wire 1 A& sram [0] $end +$var wire 1 B& sram [1] $end +$var wire 1 C& sram [2] $end +$var wire 1 D& sram [3] $end +$var wire 1 F' sram_inv [0] $end +$var wire 1 G' sram_inv [1] $end +$var wire 1 H' sram_inv [2] $end +$var wire 1 I' sram_inv [3] $end +$var wire 1 _$ out [0] $end +$var wire 1 (' p0 $end +$var wire 1 12 local_encoder2to3_0_data [0] $end +$var wire 1 22 local_encoder2to3_0_data [1] $end +$var wire 1 32 local_encoder2to3_0_data [2] $end +$var wire 1 42 local_encoder2to3_0_data_inv [0] $end +$var wire 1 52 local_encoder2to3_0_data_inv [1] $end +$var wire 1 62 local_encoder2to3_0_data_inv [2] $end +$var wire 1 72 local_encoder2to3_1_data [0] $end +$var wire 1 82 local_encoder2to3_1_data [1] $end +$var wire 1 92 local_encoder2to3_1_data [2] $end +$var wire 1 :2 local_encoder2to3_1_data_inv [0] $end +$var wire 1 ;2 local_encoder2to3_1_data_inv [1] $end +$var wire 1 <2 local_encoder2to3_1_data_inv [2] $end +$var wire 1 =2 mux_2level_tapbuf_basis_input3_mem3_0_out [0] $end +$var wire 1 >2 mux_2level_tapbuf_basis_input3_mem3_1_out [0] $end +$var wire 1 ?2 SYNOPSYS_UNCONNECTED_1 $end +$var wire 1 @2 BUF_net_105 $end + +$scope module local_encoder2to3_0_ $end +$var wire 1 A& addr [0] $end +$var wire 1 B& addr [1] $end +$var wire 1 12 data [0] $end +$var wire 1 22 data [1] $end +$var wire 1 32 data [2] $end +$var wire 1 42 data_inv [0] $end +$var wire 1 52 data_inv [1] $end +$var wire 1 62 data_inv [2] $end + +$scope module U8 $end +$var wire 1 42 Y $end +$var wire 1 12 A $end +$var supply1 1 A2 VPWR $end +$var supply0 1 B2 VGND $end +$var supply1 1 C2 VPB $end +$var supply0 1 D2 VNB $end + +$scope module base $end +$var wire 1 42 Y $end +$var wire 1 12 A $end +$var wire 1 E2 not0_out_Y $end +$upscope $end +$upscope $end + +$scope module U9 $end +$var wire 1 22 Y $end +$var wire 1 52 A $end +$var supply1 1 F2 VPWR $end +$var supply0 1 G2 VGND $end +$var supply1 1 H2 VPB $end +$var supply0 1 I2 VNB $end + +$scope module base $end +$var wire 1 22 Y $end +$var wire 1 52 A $end +$var wire 1 J2 not0_out_Y $end +$upscope $end +$upscope $end + +$scope module U10 $end +$var wire 1 52 Y $end +$var wire 1 A& A $end +$var wire 1 62 B $end +$var supply1 1 K2 VPWR $end +$var supply0 1 L2 VGND $end +$var supply1 1 M2 VPB $end +$var supply0 1 N2 VNB $end + +$scope module base $end +$var wire 1 52 Y $end +$var wire 1 A& A $end +$var wire 1 62 B $end +$var wire 1 O2 nand0_out_Y $end +$upscope $end +$upscope $end + +$scope module U11 $end +$var wire 1 62 Y $end +$var wire 1 32 A $end +$var supply1 1 P2 VPWR $end +$var supply0 1 Q2 VGND $end +$var supply1 1 R2 VPB $end +$var supply0 1 S2 VNB $end + +$scope module base $end +$var wire 1 62 Y $end +$var wire 1 32 A $end +$var wire 1 T2 not0_out_Y $end +$upscope $end +$upscope $end + +$scope module U12 $end +$var wire 1 12 Y $end +$var wire 1 32 A $end +$var wire 1 A& B $end +$var supply1 1 U2 VPWR $end +$var supply0 1 V2 VGND $end +$var supply1 1 W2 VPB $end +$var supply0 1 X2 VNB $end + +$scope module base $end +$var wire 1 12 Y $end +$var wire 1 32 A $end +$var wire 1 A& B $end +$var wire 1 Y2 nor0_out_Y $end +$upscope $end +$upscope $end + +$scope module FTB_21__20 $end +$var wire 1 32 X $end +$var wire 1 B& A $end +$var supply1 1 Z2 VPWR $end +$var supply0 1 [2 VGND $end +$var supply1 1 \2 VPB $end +$var supply0 1 ]2 VNB $end + +$scope module base $end +$var wire 1 32 X $end +$var wire 1 B& A $end +$var wire 1 ^2 buf0_out_X $end +$upscope $end +$upscope $end +$upscope $end + +$scope module local_encoder2to3_1_ $end +$var wire 1 C& addr [0] $end +$var wire 1 D& addr [1] $end +$var wire 1 72 data [0] $end +$var wire 1 82 data [1] $end +$var wire 1 92 data [2] $end +$var wire 1 :2 data_inv [0] $end +$var wire 1 ;2 data_inv [1] $end +$var wire 1 <2 data_inv [2] $end + +$scope module U8 $end +$var wire 1 :2 Y $end +$var wire 1 72 A $end +$var supply1 1 _2 VPWR $end +$var supply0 1 `2 VGND $end +$var supply1 1 a2 VPB $end +$var supply0 1 b2 VNB $end + +$scope module base $end +$var wire 1 :2 Y $end +$var wire 1 72 A $end +$var wire 1 c2 not0_out_Y $end +$upscope $end +$upscope $end + +$scope module U9 $end +$var wire 1 82 Y $end +$var wire 1 ;2 A $end +$var supply1 1 d2 VPWR $end +$var supply0 1 e2 VGND $end +$var supply1 1 f2 VPB $end +$var supply0 1 g2 VNB $end + +$scope module base $end +$var wire 1 82 Y $end +$var wire 1 ;2 A $end +$var wire 1 h2 not0_out_Y $end +$upscope $end +$upscope $end + +$scope module U10 $end +$var wire 1 ;2 Y $end +$var wire 1 C& A $end +$var wire 1 <2 B $end +$var supply1 1 i2 VPWR $end +$var supply0 1 j2 VGND $end +$var supply1 1 k2 VPB $end +$var supply0 1 l2 VNB $end + +$scope module base $end +$var wire 1 ;2 Y $end +$var wire 1 C& A $end +$var wire 1 <2 B $end +$var wire 1 m2 nand0_out_Y $end +$upscope $end +$upscope $end + +$scope module U11 $end +$var wire 1 <2 Y $end +$var wire 1 92 A $end +$var supply1 1 n2 VPWR $end +$var supply0 1 o2 VGND $end +$var supply1 1 p2 VPB $end +$var supply0 1 q2 VNB $end + +$scope module base $end +$var wire 1 <2 Y $end +$var wire 1 92 A $end +$var wire 1 r2 not0_out_Y $end +$upscope $end +$upscope $end + +$scope module U12 $end +$var wire 1 72 Y $end +$var wire 1 92 A $end +$var wire 1 C& B $end +$var supply1 1 s2 VPWR $end +$var supply0 1 t2 VGND $end +$var supply1 1 u2 VPB $end +$var supply0 1 v2 VNB $end + +$scope module base $end +$var wire 1 72 Y $end +$var wire 1 92 A $end +$var wire 1 C& B $end +$var wire 1 w2 nor0_out_Y $end +$upscope $end +$upscope $end + +$scope module FTB_22__21 $end +$var wire 1 92 X $end +$var wire 1 D& A $end +$var supply1 1 x2 VPWR $end +$var supply0 1 y2 VGND $end +$var supply1 1 z2 VPB $end +$var supply0 1 {2 VNB $end + +$scope module base $end +$var wire 1 92 X $end +$var wire 1 D& A $end +$var wire 1 |2 buf0_out_X $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mux_l1_in_0_ $end +$var wire 1 O# in [0] $end +$var wire 1 4$ in [1] $end +$var wire 1 7$ in [2] $end +$var wire 1 12 mem [0] $end +$var wire 1 22 mem [1] $end +$var wire 1 32 mem [2] $end +$var wire 1 42 mem_inv [0] $end +$var wire 1 52 mem_inv [1] $end +$var wire 1 62 mem_inv [2] $end +$var wire 1 =2 out [0] $end + +$scope module scs8hd_muxinv3_1_0 $end +$var wire 1 =2 Z $end +$var wire 1 O# Q1 $end +$var wire 1 4$ Q2 $end +$var wire 1 7$ Q3 $end +$var wire 1 12 S0 $end +$var wire 1 42 S0B $end +$var wire 1 22 S1 $end +$var wire 1 52 S1B $end +$var wire 1 32 S2 $end +$var wire 1 62 S2B $end +$var wire 1 }2 Q1__bar $end +$var wire 1 ~2 Q2__bar $end +$var wire 1 !3 Q3__bar $end +$upscope $end +$upscope $end + +$scope module mux_l2_in_0_ $end +$var wire 1 =2 in [0] $end +$var wire 1 :$ in [1] $end +$var wire 1 ?2 in [2] $end +$var wire 1 72 mem [0] $end +$var wire 1 82 mem [1] $end +$var wire 1 92 mem [2] $end +$var wire 1 :2 mem_inv [0] $end +$var wire 1 ;2 mem_inv [1] $end +$var wire 1 <2 mem_inv [2] $end +$var wire 1 >2 out [0] $end +$var wire 1 (' p0 $end + +$scope module scs8hd_muxinv3_1_0 $end +$var wire 1 >2 Z $end +$var wire 1 =2 Q1 $end +$var wire 1 :$ Q2 $end +$var wire 1 (' Q3 $end +$var wire 1 72 S0 $end +$var wire 1 :2 S0B $end +$var wire 1 82 S1 $end +$var wire 1 ;2 S1B $end +$var wire 1 92 S2 $end +$var wire 1 <2 S2B $end +$var wire 1 "3 Q1__bar $end +$var wire 1 #3 Q2__bar $end +$var wire 1 $3 Q3__bar $end +$upscope $end +$upscope $end + +$scope module BINV_R_104 $end +$var wire 1 _$ Y $end +$var wire 1 @2 A $end +$var supply1 1 %3 VPWR $end +$var supply0 1 &3 VGND $end +$var supply1 1 '3 VPB $end +$var supply0 1 (3 VNB $end + +$scope module base $end +$var wire 1 _$ Y $end +$var wire 1 @2 A $end +$var wire 1 )3 not0_out_Y $end +$upscope $end +$upscope $end + +$scope module BINV_R_105 $end +$var wire 1 @2 Y $end +$var wire 1 >2 A $end +$var supply1 1 *3 VPWR $end +$var supply0 1 +3 VGND $end +$var supply1 1 ,3 VPB $end +$var supply0 1 -3 VNB $end + +$scope module base $end +$var wire 1 @2 Y $end +$var wire 1 >2 A $end +$var wire 1 .3 not0_out_Y $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mux_left_track_11 $end +$var wire 1 P# in [0] $end +$var wire 1 5$ in [1] $end +$var wire 1 8$ in [2] $end +$var wire 1 ;$ in [3] $end +$var wire 1 E& sram [0] $end +$var wire 1 F& sram [1] $end +$var wire 1 G& sram [2] $end +$var wire 1 H& sram [3] $end +$var wire 1 J' sram_inv [0] $end +$var wire 1 K' sram_inv [1] $end +$var wire 1 L' sram_inv [2] $end +$var wire 1 M' sram_inv [3] $end +$var wire 1 `$ out [0] $end +$var wire 1 (' p0 $end +$var wire 1 /3 local_encoder2to3_0_data [0] $end +$var wire 1 03 local_encoder2to3_0_data [1] $end +$var wire 1 13 local_encoder2to3_0_data [2] $end +$var wire 1 23 local_encoder2to3_0_data_inv [0] $end +$var wire 1 33 local_encoder2to3_0_data_inv [1] $end +$var wire 1 43 local_encoder2to3_0_data_inv [2] $end +$var wire 1 53 local_encoder2to3_1_data [0] $end +$var wire 1 63 local_encoder2to3_1_data [1] $end +$var wire 1 73 local_encoder2to3_1_data [2] $end +$var wire 1 83 local_encoder2to3_1_data_inv [0] $end +$var wire 1 93 local_encoder2to3_1_data_inv [1] $end +$var wire 1 :3 local_encoder2to3_1_data_inv [2] $end +$var wire 1 ;3 mux_2level_tapbuf_basis_input3_mem3_0_out [0] $end +$var wire 1 <3 mux_2level_tapbuf_basis_input3_mem3_1_out [0] $end +$var wire 1 =3 SYNOPSYS_UNCONNECTED_1 $end +$var wire 1 >3 BUF_net_107 $end + +$scope module local_encoder2to3_0_ $end +$var wire 1 E& addr [0] $end +$var wire 1 F& addr [1] $end +$var wire 1 /3 data [0] $end +$var wire 1 03 data [1] $end +$var wire 1 13 data [2] $end +$var wire 1 23 data_inv [0] $end +$var wire 1 33 data_inv [1] $end +$var wire 1 43 data_inv [2] $end + +$scope module U8 $end +$var wire 1 23 Y $end +$var wire 1 /3 A $end +$var supply1 1 ?3 VPWR $end +$var supply0 1 @3 VGND $end +$var supply1 1 A3 VPB $end +$var supply0 1 B3 VNB $end + +$scope module base $end +$var wire 1 23 Y $end +$var wire 1 /3 A $end +$var wire 1 C3 not0_out_Y $end +$upscope $end +$upscope $end + +$scope module U9 $end +$var wire 1 03 Y $end +$var wire 1 33 A $end +$var supply1 1 D3 VPWR $end +$var supply0 1 E3 VGND $end +$var supply1 1 F3 VPB $end +$var supply0 1 G3 VNB $end + +$scope module base $end +$var wire 1 03 Y $end +$var wire 1 33 A $end +$var wire 1 H3 not0_out_Y $end +$upscope $end +$upscope $end + +$scope module U10 $end +$var wire 1 33 Y $end +$var wire 1 E& A $end +$var wire 1 43 B $end +$var supply1 1 I3 VPWR $end +$var supply0 1 J3 VGND $end +$var supply1 1 K3 VPB $end +$var supply0 1 L3 VNB $end + +$scope module base $end +$var wire 1 33 Y $end +$var wire 1 E& A $end +$var wire 1 43 B $end +$var wire 1 M3 nand0_out_Y $end +$upscope $end +$upscope $end + +$scope module U11 $end +$var wire 1 43 Y $end +$var wire 1 13 A $end +$var supply1 1 N3 VPWR $end +$var supply0 1 O3 VGND $end +$var supply1 1 P3 VPB $end +$var supply0 1 Q3 VNB $end + +$scope module base $end +$var wire 1 43 Y $end +$var wire 1 13 A $end +$var wire 1 R3 not0_out_Y $end +$upscope $end +$upscope $end + +$scope module U12 $end +$var wire 1 /3 Y $end +$var wire 1 13 A $end +$var wire 1 E& B $end +$var supply1 1 S3 VPWR $end +$var supply0 1 T3 VGND $end +$var supply1 1 U3 VPB $end +$var supply0 1 V3 VNB $end + +$scope module base $end +$var wire 1 /3 Y $end +$var wire 1 13 A $end +$var wire 1 E& B $end +$var wire 1 W3 nor0_out_Y $end +$upscope $end +$upscope $end + +$scope module FTB_23__22 $end +$var wire 1 13 X $end +$var wire 1 F& A $end +$var supply1 1 X3 VPWR $end +$var supply0 1 Y3 VGND $end +$var supply1 1 Z3 VPB $end +$var supply0 1 [3 VNB $end + +$scope module base $end +$var wire 1 13 X $end +$var wire 1 F& A $end +$var wire 1 \3 buf0_out_X $end +$upscope $end +$upscope $end +$upscope $end + +$scope module local_encoder2to3_1_ $end +$var wire 1 G& addr [0] $end +$var wire 1 H& addr [1] $end +$var wire 1 53 data [0] $end +$var wire 1 63 data [1] $end +$var wire 1 73 data [2] $end +$var wire 1 83 data_inv [0] $end +$var wire 1 93 data_inv [1] $end +$var wire 1 :3 data_inv [2] $end + +$scope module U8 $end +$var wire 1 83 Y $end +$var wire 1 53 A $end +$var supply1 1 ]3 VPWR $end +$var supply0 1 ^3 VGND $end +$var supply1 1 _3 VPB $end +$var supply0 1 `3 VNB $end + +$scope module base $end +$var wire 1 83 Y $end +$var wire 1 53 A $end +$var wire 1 a3 not0_out_Y $end +$upscope $end +$upscope $end + +$scope module U9 $end +$var wire 1 63 Y $end +$var wire 1 93 A $end +$var supply1 1 b3 VPWR $end +$var supply0 1 c3 VGND $end +$var supply1 1 d3 VPB $end +$var supply0 1 e3 VNB $end + +$scope module base $end +$var wire 1 63 Y $end +$var wire 1 93 A $end +$var wire 1 f3 not0_out_Y $end +$upscope $end +$upscope $end + +$scope module U10 $end +$var wire 1 93 Y $end +$var wire 1 G& A $end +$var wire 1 :3 B $end +$var supply1 1 g3 VPWR $end +$var supply0 1 h3 VGND $end +$var supply1 1 i3 VPB $end +$var supply0 1 j3 VNB $end + +$scope module base $end +$var wire 1 93 Y $end +$var wire 1 G& A $end +$var wire 1 :3 B $end +$var wire 1 k3 nand0_out_Y $end +$upscope $end +$upscope $end + +$scope module U11 $end +$var wire 1 :3 Y $end +$var wire 1 73 A $end +$var supply1 1 l3 VPWR $end +$var supply0 1 m3 VGND $end +$var supply1 1 n3 VPB $end +$var supply0 1 o3 VNB $end + +$scope module base $end +$var wire 1 :3 Y $end +$var wire 1 73 A $end +$var wire 1 p3 not0_out_Y $end +$upscope $end +$upscope $end + +$scope module U12 $end +$var wire 1 53 Y $end +$var wire 1 73 A $end +$var wire 1 G& B $end +$var supply1 1 q3 VPWR $end +$var supply0 1 r3 VGND $end +$var supply1 1 s3 VPB $end +$var supply0 1 t3 VNB $end + +$scope module base $end +$var wire 1 53 Y $end +$var wire 1 73 A $end +$var wire 1 G& B $end +$var wire 1 u3 nor0_out_Y $end +$upscope $end +$upscope $end + +$scope module FTB_24__23 $end +$var wire 1 73 X $end +$var wire 1 H& A $end +$var supply1 1 v3 VPWR $end +$var supply0 1 w3 VGND $end +$var supply1 1 x3 VPB $end +$var supply0 1 y3 VNB $end + +$scope module base $end +$var wire 1 73 X $end +$var wire 1 H& A $end +$var wire 1 z3 buf0_out_X $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mux_l1_in_0_ $end +$var wire 1 P# in [0] $end +$var wire 1 5$ in [1] $end +$var wire 1 8$ in [2] $end +$var wire 1 /3 mem [0] $end +$var wire 1 03 mem [1] $end +$var wire 1 13 mem [2] $end +$var wire 1 23 mem_inv [0] $end +$var wire 1 33 mem_inv [1] $end +$var wire 1 43 mem_inv [2] $end +$var wire 1 ;3 out [0] $end + +$scope module scs8hd_muxinv3_1_0 $end +$var wire 1 ;3 Z $end +$var wire 1 P# Q1 $end +$var wire 1 5$ Q2 $end +$var wire 1 8$ Q3 $end +$var wire 1 /3 S0 $end +$var wire 1 23 S0B $end +$var wire 1 03 S1 $end +$var wire 1 33 S1B $end +$var wire 1 13 S2 $end +$var wire 1 43 S2B $end +$var wire 1 {3 Q1__bar $end +$var wire 1 |3 Q2__bar $end +$var wire 1 }3 Q3__bar $end +$upscope $end +$upscope $end + +$scope module mux_l2_in_0_ $end +$var wire 1 ;3 in [0] $end +$var wire 1 ;$ in [1] $end +$var wire 1 =3 in [2] $end +$var wire 1 53 mem [0] $end +$var wire 1 63 mem [1] $end +$var wire 1 73 mem [2] $end +$var wire 1 83 mem_inv [0] $end +$var wire 1 93 mem_inv [1] $end +$var wire 1 :3 mem_inv [2] $end +$var wire 1 <3 out [0] $end +$var wire 1 (' p0 $end + +$scope module scs8hd_muxinv3_1_0 $end +$var wire 1 <3 Z $end +$var wire 1 ;3 Q1 $end +$var wire 1 ;$ Q2 $end +$var wire 1 (' Q3 $end +$var wire 1 53 S0 $end +$var wire 1 83 S0B $end +$var wire 1 63 S1 $end +$var wire 1 93 S1B $end +$var wire 1 73 S2 $end +$var wire 1 :3 S2B $end +$var wire 1 ~3 Q1__bar $end +$var wire 1 !4 Q2__bar $end +$var wire 1 "4 Q3__bar $end +$upscope $end +$upscope $end + +$scope module BINV_R_106 $end +$var wire 1 `$ Y $end +$var wire 1 >3 A $end +$var supply1 1 #4 VPWR $end +$var supply0 1 $4 VGND $end +$var supply1 1 %4 VPB $end +$var supply0 1 &4 VNB $end + +$scope module base $end +$var wire 1 `$ Y $end +$var wire 1 >3 A $end +$var wire 1 '4 not0_out_Y $end +$upscope $end +$upscope $end + +$scope module BINV_R_107 $end +$var wire 1 >3 Y $end +$var wire 1 <3 A $end +$var supply1 1 (4 VPWR $end +$var supply0 1 )4 VGND $end +$var supply1 1 *4 VPB $end +$var supply0 1 +4 VNB $end + +$scope module base $end +$var wire 1 >3 Y $end +$var wire 1 <3 A $end +$var wire 1 ,4 not0_out_Y $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mem_bottom_track_1 $end +$var wire 1 K# pReset [0] $end +$var wire 1 }$ prog_clk [0] $end +$var wire 1 <$ ccff_head [0] $end +$var wire 1 m& ccff_tail [0] $end +$var wire 1 =& mem_out [0] $end +$var wire 1 >& mem_out [1] $end +$var wire 1 ?& mem_out [2] $end +$var wire 1 @& mem_out [3] $end +$var wire 1 -4 ropt_net_200 $end +$var wire 1 .4 ropt_net_197 $end +$var wire 1 /4 ropt_net_201 $end +$var wire 1 04 ropt_net_198 $end +$var wire 1 14 ropt_net_199 $end +$var wire 1 24 ropt_net_202 $end + +$scope module sky130_fd_sc_hd__dfrtp_1_0_ $end +$var wire 1 =& Q $end +$var wire 1 }$ CLK $end +$var wire 1 -4 D $end +$var wire 1 K# RESET_B $end +$var supply1 1 34 VPWR $end +$var supply0 1 44 VGND $end +$var supply1 1 54 VPB $end +$var supply0 1 64 VNB $end + +$scope module base $end +$var wire 1 =& Q $end +$var wire 1 }$ CLK $end +$var wire 1 -4 D $end +$var wire 1 K# RESET_B $end +$var wire 1 74 buf_Q $end +$var wire 1 84 RESET $end +$upscope $end +$upscope $end + +$scope module sky130_fd_sc_hd__dfrtp_1_1_ $end +$var wire 1 >& Q $end +$var wire 1 }$ CLK $end +$var wire 1 =& D $end +$var wire 1 K# RESET_B $end +$var supply1 1 94 VPWR $end +$var supply0 1 :4 VGND $end +$var supply1 1 ;4 VPB $end +$var supply0 1 <4 VNB $end + +$scope module base $end +$var wire 1 >& Q $end +$var wire 1 }$ CLK $end +$var wire 1 =& D $end +$var wire 1 K# RESET_B $end +$var wire 1 =4 buf_Q $end +$var wire 1 >4 RESET $end +$upscope $end +$upscope $end + +$scope module sky130_fd_sc_hd__dfrtp_1_2_ $end +$var wire 1 ?& Q $end +$var wire 1 }$ CLK $end +$var wire 1 >& D $end +$var wire 1 K# RESET_B $end +$var supply1 1 ?4 VPWR $end +$var supply0 1 @4 VGND $end +$var supply1 1 A4 VPB $end +$var supply0 1 B4 VNB $end + +$scope module base $end +$var wire 1 ?& Q $end +$var wire 1 }$ CLK $end +$var wire 1 >& D $end +$var wire 1 K# RESET_B $end +$var wire 1 C4 buf_Q $end +$var wire 1 D4 RESET $end +$upscope $end +$upscope $end + +$scope module sky130_fd_sc_hd__dfrtp_1_3_ $end +$var wire 1 @& Q $end +$var wire 1 }$ CLK $end +$var wire 1 ?& D $end +$var wire 1 K# RESET_B $end +$var supply1 1 E4 VPWR $end +$var supply0 1 F4 VGND $end +$var supply1 1 G4 VPB $end +$var supply0 1 H4 VNB $end + +$scope module base $end +$var wire 1 @& Q $end +$var wire 1 }$ CLK $end +$var wire 1 ?& D $end +$var wire 1 K# RESET_B $end +$var wire 1 I4 buf_Q $end +$var wire 1 J4 RESET $end +$upscope $end +$upscope $end + +$scope module FTB_25__24 $end +$var wire 1 m& X $end +$var wire 1 @& A $end +$var supply1 1 K4 VPWR $end +$var supply0 1 L4 VGND $end +$var supply1 1 M4 VPB $end +$var supply0 1 N4 VNB $end + +$scope module base $end +$var wire 1 m& X $end +$var wire 1 @& A $end +$var wire 1 O4 buf0_out_X $end +$upscope $end +$upscope $end + +$scope module ropt_h_inst_1429 $end +$var wire 1 .4 X $end +$var wire 1 <$ A $end +$var supply1 1 P4 VPWR $end +$var supply0 1 Q4 VGND $end +$var supply1 1 R4 VPB $end +$var supply0 1 S4 VNB $end + +$scope module base $end +$var wire 1 .4 X $end +$var wire 1 <$ A $end +$var wire 1 T4 buf0_out_X $end +$upscope $end +$upscope $end + +$scope module ropt_h_inst_1430 $end +$var wire 1 04 X $end +$var wire 1 /4 A $end +$var supply1 1 U4 VPWR $end +$var supply0 1 V4 VGND $end +$var supply1 1 W4 VPB $end +$var supply0 1 X4 VNB $end + +$scope module base $end +$var wire 1 04 X $end +$var wire 1 /4 A $end +$var wire 1 Y4 buf0_out_X $end +$upscope $end +$upscope $end + +$scope module ropt_h_inst_1431 $end +$var wire 1 14 X $end +$var wire 1 04 A $end +$var supply1 1 Z4 VPWR $end +$var supply0 1 [4 VGND $end +$var supply1 1 \4 VPB $end +$var supply0 1 ]4 VNB $end + +$scope module base $end +$var wire 1 14 X $end +$var wire 1 04 A $end +$var wire 1 ^4 buf0_out_X $end +$upscope $end +$upscope $end + +$scope module ropt_h_inst_1432 $end +$var wire 1 -4 X $end +$var wire 1 14 A $end +$var supply1 1 _4 VPWR $end +$var supply0 1 `4 VGND $end +$var supply1 1 a4 VPB $end +$var supply0 1 b4 VNB $end + +$scope module base $end +$var wire 1 -4 X $end +$var wire 1 14 A $end +$var wire 1 c4 buf0_out_X $end +$upscope $end +$upscope $end + +$scope module ropt_h_inst_1433 $end +$var wire 1 /4 X $end +$var wire 1 24 A $end +$var supply1 1 d4 VPWR $end +$var supply0 1 e4 VGND $end +$var supply1 1 f4 VPB $end +$var supply0 1 g4 VNB $end + +$scope module base $end +$var wire 1 /4 X $end +$var wire 1 24 A $end +$var wire 1 h4 buf0_out_X $end +$upscope $end +$upscope $end + +$scope module ropt_h_inst_1434 $end +$var wire 1 24 X $end +$var wire 1 .4 A $end +$var supply1 1 i4 VPWR $end +$var supply0 1 j4 VGND $end +$var supply1 1 k4 VPB $end +$var supply0 1 l4 VNB $end + +$scope module base $end +$var wire 1 24 X $end +$var wire 1 .4 A $end +$var wire 1 m4 buf0_out_X $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mem_bottom_track_3 $end +$var wire 1 K# pReset [0] $end +$var wire 1 }$ prog_clk [0] $end +$var wire 1 m& ccff_head [0] $end +$var wire 1 p& ccff_tail [0] $end +$var wire 1 I& mem_out [0] $end +$var wire 1 J& mem_out [1] $end +$var wire 1 K& mem_out [2] $end +$var wire 1 L& mem_out [3] $end + +$scope module sky130_fd_sc_hd__dfrtp_1_0_ $end +$var wire 1 I& Q $end +$var wire 1 }$ CLK $end +$var wire 1 m& D $end +$var wire 1 K# RESET_B $end +$var supply1 1 n4 VPWR $end +$var supply0 1 o4 VGND $end +$var supply1 1 p4 VPB $end +$var supply0 1 q4 VNB $end + +$scope module base $end +$var wire 1 I& Q $end +$var wire 1 }$ CLK $end +$var wire 1 m& D $end +$var wire 1 K# RESET_B $end +$var wire 1 r4 buf_Q $end +$var wire 1 s4 RESET $end +$upscope $end +$upscope $end + +$scope module sky130_fd_sc_hd__dfrtp_1_1_ $end +$var wire 1 J& Q $end +$var wire 1 }$ CLK $end +$var wire 1 I& D $end +$var wire 1 K# RESET_B $end +$var supply1 1 t4 VPWR $end +$var supply0 1 u4 VGND $end +$var supply1 1 v4 VPB $end +$var supply0 1 w4 VNB $end + +$scope module base $end +$var wire 1 J& Q $end +$var wire 1 }$ CLK $end +$var wire 1 I& D $end +$var wire 1 K# RESET_B $end +$var wire 1 x4 buf_Q $end +$var wire 1 y4 RESET $end +$upscope $end +$upscope $end + +$scope module sky130_fd_sc_hd__dfrtp_1_2_ $end +$var wire 1 K& Q $end +$var wire 1 }$ CLK $end +$var wire 1 J& D $end +$var wire 1 K# RESET_B $end +$var supply1 1 z4 VPWR $end +$var supply0 1 {4 VGND $end +$var supply1 1 |4 VPB $end +$var supply0 1 }4 VNB $end + +$scope module base $end +$var wire 1 K& Q $end +$var wire 1 }$ CLK $end +$var wire 1 J& D $end +$var wire 1 K# RESET_B $end +$var wire 1 ~4 buf_Q $end +$var wire 1 !5 RESET $end +$upscope $end +$upscope $end + +$scope module sky130_fd_sc_hd__dfrtp_1_3_ $end +$var wire 1 L& Q $end +$var wire 1 }$ CLK $end +$var wire 1 K& D $end +$var wire 1 K# RESET_B $end +$var supply1 1 "5 VPWR $end +$var supply0 1 #5 VGND $end +$var supply1 1 $5 VPB $end +$var supply0 1 %5 VNB $end + +$scope module base $end +$var wire 1 L& Q $end +$var wire 1 }$ CLK $end +$var wire 1 K& D $end +$var wire 1 K# RESET_B $end +$var wire 1 &5 buf_Q $end +$var wire 1 '5 RESET $end +$upscope $end +$upscope $end + +$scope module FTB_26__25 $end +$var wire 1 p& X $end +$var wire 1 L& A $end +$var supply1 1 (5 VPWR $end +$var supply0 1 )5 VGND $end +$var supply1 1 *5 VPB $end +$var supply0 1 +5 VNB $end + +$scope module base $end +$var wire 1 p& X $end +$var wire 1 L& A $end +$var wire 1 ,5 buf0_out_X $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mem_bottom_track_5 $end +$var wire 1 K# pReset [0] $end +$var wire 1 }$ prog_clk [0] $end +$var wire 1 p& ccff_head [0] $end +$var wire 1 q& ccff_tail [0] $end +$var wire 1 M& mem_out [0] $end +$var wire 1 N& mem_out [1] $end +$var wire 1 O& mem_out [2] $end +$var wire 1 P& mem_out [3] $end + +$scope module sky130_fd_sc_hd__dfrtp_1_0_ $end +$var wire 1 M& Q $end +$var wire 1 }$ CLK $end +$var wire 1 p& D $end +$var wire 1 K# RESET_B $end +$var supply1 1 -5 VPWR $end +$var supply0 1 .5 VGND $end +$var supply1 1 /5 VPB $end +$var supply0 1 05 VNB $end + +$scope module base $end +$var wire 1 M& Q $end +$var wire 1 }$ CLK $end +$var wire 1 p& D $end +$var wire 1 K# RESET_B $end +$var wire 1 15 buf_Q $end +$var wire 1 25 RESET $end +$upscope $end +$upscope $end + +$scope module sky130_fd_sc_hd__dfrtp_1_1_ $end +$var wire 1 N& Q $end +$var wire 1 }$ CLK $end +$var wire 1 M& D $end +$var wire 1 K# RESET_B $end +$var supply1 1 35 VPWR $end +$var supply0 1 45 VGND $end +$var supply1 1 55 VPB $end +$var supply0 1 65 VNB $end + +$scope module base $end +$var wire 1 N& Q $end +$var wire 1 }$ CLK $end +$var wire 1 M& D $end +$var wire 1 K# RESET_B $end +$var wire 1 75 buf_Q $end +$var wire 1 85 RESET $end +$upscope $end +$upscope $end + +$scope module sky130_fd_sc_hd__dfrtp_1_2_ $end +$var wire 1 O& Q $end +$var wire 1 }$ CLK $end +$var wire 1 N& D $end +$var wire 1 K# RESET_B $end +$var supply1 1 95 VPWR $end +$var supply0 1 :5 VGND $end +$var supply1 1 ;5 VPB $end +$var supply0 1 <5 VNB $end + +$scope module base $end +$var wire 1 O& Q $end +$var wire 1 }$ CLK $end +$var wire 1 N& D $end +$var wire 1 K# RESET_B $end +$var wire 1 =5 buf_Q $end +$var wire 1 >5 RESET $end +$upscope $end +$upscope $end + +$scope module sky130_fd_sc_hd__dfrtp_1_3_ $end +$var wire 1 P& Q $end +$var wire 1 }$ CLK $end +$var wire 1 O& D $end +$var wire 1 K# RESET_B $end +$var supply1 1 ?5 VPWR $end +$var supply0 1 @5 VGND $end +$var supply1 1 A5 VPB $end +$var supply0 1 B5 VNB $end + +$scope module base $end +$var wire 1 P& Q $end +$var wire 1 }$ CLK $end +$var wire 1 O& D $end +$var wire 1 K# RESET_B $end +$var wire 1 C5 buf_Q $end +$var wire 1 D5 RESET $end +$upscope $end +$upscope $end + +$scope module FTB_27__26 $end +$var wire 1 q& X $end +$var wire 1 P& A $end +$var supply1 1 E5 VPWR $end +$var supply0 1 F5 VGND $end +$var supply1 1 G5 VPB $end +$var supply0 1 H5 VNB $end + +$scope module base $end +$var wire 1 q& X $end +$var wire 1 P& A $end +$var wire 1 I5 buf0_out_X $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mem_bottom_track_7 $end +$var wire 1 K# pReset [0] $end +$var wire 1 }$ prog_clk [0] $end +$var wire 1 q& ccff_head [0] $end +$var wire 1 r& ccff_tail [0] $end +$var wire 1 Q& mem_out [0] $end +$var wire 1 R& mem_out [1] $end +$var wire 1 S& mem_out [2] $end +$var wire 1 T& mem_out [3] $end + +$scope module sky130_fd_sc_hd__dfrtp_1_0_ $end +$var wire 1 Q& Q $end +$var wire 1 }$ CLK $end +$var wire 1 q& D $end +$var wire 1 K# RESET_B $end +$var supply1 1 J5 VPWR $end +$var supply0 1 K5 VGND $end +$var supply1 1 L5 VPB $end +$var supply0 1 M5 VNB $end + +$scope module base $end +$var wire 1 Q& Q $end +$var wire 1 }$ CLK $end +$var wire 1 q& D $end +$var wire 1 K# RESET_B $end +$var wire 1 N5 buf_Q $end +$var wire 1 O5 RESET $end +$upscope $end +$upscope $end + +$scope module sky130_fd_sc_hd__dfrtp_1_1_ $end +$var wire 1 R& Q $end +$var wire 1 }$ CLK $end +$var wire 1 Q& D $end +$var wire 1 K# RESET_B $end +$var supply1 1 P5 VPWR $end +$var supply0 1 Q5 VGND $end +$var supply1 1 R5 VPB $end +$var supply0 1 S5 VNB $end + +$scope module base $end +$var wire 1 R& Q $end +$var wire 1 }$ CLK $end +$var wire 1 Q& D $end +$var wire 1 K# RESET_B $end +$var wire 1 T5 buf_Q $end +$var wire 1 U5 RESET $end +$upscope $end +$upscope $end + +$scope module sky130_fd_sc_hd__dfrtp_1_2_ $end +$var wire 1 S& Q $end +$var wire 1 }$ CLK $end +$var wire 1 R& D $end +$var wire 1 K# RESET_B $end +$var supply1 1 V5 VPWR $end +$var supply0 1 W5 VGND $end +$var supply1 1 X5 VPB $end +$var supply0 1 Y5 VNB $end + +$scope module base $end +$var wire 1 S& Q $end +$var wire 1 }$ CLK $end +$var wire 1 R& D $end +$var wire 1 K# RESET_B $end +$var wire 1 Z5 buf_Q $end +$var wire 1 [5 RESET $end +$upscope $end +$upscope $end + +$scope module sky130_fd_sc_hd__dfrtp_1_3_ $end +$var wire 1 T& Q $end +$var wire 1 }$ CLK $end +$var wire 1 S& D $end +$var wire 1 K# RESET_B $end +$var supply1 1 \5 VPWR $end +$var supply0 1 ]5 VGND $end +$var supply1 1 ^5 VPB $end +$var supply0 1 _5 VNB $end + +$scope module base $end +$var wire 1 T& Q $end +$var wire 1 }$ CLK $end +$var wire 1 S& D $end +$var wire 1 K# RESET_B $end +$var wire 1 `5 buf_Q $end +$var wire 1 a5 RESET $end +$upscope $end +$upscope $end + +$scope module FTB_28__27 $end +$var wire 1 r& X $end +$var wire 1 T& A $end +$var supply1 1 b5 VPWR $end +$var supply0 1 c5 VGND $end +$var supply1 1 d5 VPB $end +$var supply0 1 e5 VNB $end + +$scope module base $end +$var wire 1 r& X $end +$var wire 1 T& A $end +$var wire 1 f5 buf0_out_X $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mem_bottom_track_9 $end +$var wire 1 K# pReset [0] $end +$var wire 1 }$ prog_clk [0] $end +$var wire 1 r& ccff_head [0] $end +$var wire 1 s& ccff_tail [0] $end +$var wire 1 U& mem_out [0] $end +$var wire 1 V& mem_out [1] $end +$var wire 1 W& mem_out [2] $end +$var wire 1 X& mem_out [3] $end + +$scope module sky130_fd_sc_hd__dfrtp_1_0_ $end +$var wire 1 U& Q $end +$var wire 1 }$ CLK $end +$var wire 1 r& D $end +$var wire 1 K# RESET_B $end +$var supply1 1 g5 VPWR $end +$var supply0 1 h5 VGND $end +$var supply1 1 i5 VPB $end +$var supply0 1 j5 VNB $end + +$scope module base $end +$var wire 1 U& Q $end +$var wire 1 }$ CLK $end +$var wire 1 r& D $end +$var wire 1 K# RESET_B $end +$var wire 1 k5 buf_Q $end +$var wire 1 l5 RESET $end +$upscope $end +$upscope $end + +$scope module sky130_fd_sc_hd__dfrtp_1_1_ $end +$var wire 1 V& Q $end +$var wire 1 }$ CLK $end +$var wire 1 U& D $end +$var wire 1 K# RESET_B $end +$var supply1 1 m5 VPWR $end +$var supply0 1 n5 VGND $end +$var supply1 1 o5 VPB $end +$var supply0 1 p5 VNB $end + +$scope module base $end +$var wire 1 V& Q $end +$var wire 1 }$ CLK $end +$var wire 1 U& D $end +$var wire 1 K# RESET_B $end +$var wire 1 q5 buf_Q $end +$var wire 1 r5 RESET $end +$upscope $end +$upscope $end + +$scope module sky130_fd_sc_hd__dfrtp_1_2_ $end +$var wire 1 W& Q $end +$var wire 1 }$ CLK $end +$var wire 1 V& D $end +$var wire 1 K# RESET_B $end +$var supply1 1 s5 VPWR $end +$var supply0 1 t5 VGND $end +$var supply1 1 u5 VPB $end +$var supply0 1 v5 VNB $end + +$scope module base $end +$var wire 1 W& Q $end +$var wire 1 }$ CLK $end +$var wire 1 V& D $end +$var wire 1 K# RESET_B $end +$var wire 1 w5 buf_Q $end +$var wire 1 x5 RESET $end +$upscope $end +$upscope $end + +$scope module sky130_fd_sc_hd__dfrtp_1_3_ $end +$var wire 1 X& Q $end +$var wire 1 }$ CLK $end +$var wire 1 W& D $end +$var wire 1 K# RESET_B $end +$var supply1 1 y5 VPWR $end +$var supply0 1 z5 VGND $end +$var supply1 1 {5 VPB $end +$var supply0 1 |5 VNB $end + +$scope module base $end +$var wire 1 X& Q $end +$var wire 1 }$ CLK $end +$var wire 1 W& D $end +$var wire 1 K# RESET_B $end +$var wire 1 }5 buf_Q $end +$var wire 1 ~5 RESET $end +$upscope $end +$upscope $end + +$scope module FTB_29__28 $end +$var wire 1 s& X $end +$var wire 1 X& A $end +$var supply1 1 !6 VPWR $end +$var supply0 1 "6 VGND $end +$var supply1 1 #6 VPB $end +$var supply0 1 $6 VNB $end + +$scope module base $end +$var wire 1 s& X $end +$var wire 1 X& A $end +$var wire 1 %6 buf0_out_X $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mem_bottom_track_11 $end +$var wire 1 K# pReset [0] $end +$var wire 1 }$ prog_clk [0] $end +$var wire 1 s& ccff_head [0] $end +$var wire 1 t& ccff_tail [0] $end +$var wire 1 Y& mem_out [0] $end +$var wire 1 Z& mem_out [1] $end +$var wire 1 [& mem_out [2] $end +$var wire 1 \& mem_out [3] $end + +$scope module sky130_fd_sc_hd__dfrtp_1_0_ $end +$var wire 1 Y& Q $end +$var wire 1 }$ CLK $end +$var wire 1 s& D $end +$var wire 1 K# RESET_B $end +$var supply1 1 &6 VPWR $end +$var supply0 1 '6 VGND $end +$var supply1 1 (6 VPB $end +$var supply0 1 )6 VNB $end + +$scope module base $end +$var wire 1 Y& Q $end +$var wire 1 }$ CLK $end +$var wire 1 s& D $end +$var wire 1 K# RESET_B $end +$var wire 1 *6 buf_Q $end +$var wire 1 +6 RESET $end +$upscope $end +$upscope $end + +$scope module sky130_fd_sc_hd__dfrtp_1_1_ $end +$var wire 1 Z& Q $end +$var wire 1 }$ CLK $end +$var wire 1 Y& D $end +$var wire 1 K# RESET_B $end +$var supply1 1 ,6 VPWR $end +$var supply0 1 -6 VGND $end +$var supply1 1 .6 VPB $end +$var supply0 1 /6 VNB $end + +$scope module base $end +$var wire 1 Z& Q $end +$var wire 1 }$ CLK $end +$var wire 1 Y& D $end +$var wire 1 K# RESET_B $end +$var wire 1 06 buf_Q $end +$var wire 1 16 RESET $end +$upscope $end +$upscope $end + +$scope module sky130_fd_sc_hd__dfrtp_1_2_ $end +$var wire 1 [& Q $end +$var wire 1 }$ CLK $end +$var wire 1 Z& D $end +$var wire 1 K# RESET_B $end +$var supply1 1 26 VPWR $end +$var supply0 1 36 VGND $end +$var supply1 1 46 VPB $end +$var supply0 1 56 VNB $end + +$scope module base $end +$var wire 1 [& Q $end +$var wire 1 }$ CLK $end +$var wire 1 Z& D $end +$var wire 1 K# RESET_B $end +$var wire 1 66 buf_Q $end +$var wire 1 76 RESET $end +$upscope $end +$upscope $end + +$scope module sky130_fd_sc_hd__dfrtp_1_3_ $end +$var wire 1 \& Q $end +$var wire 1 }$ CLK $end +$var wire 1 [& D $end +$var wire 1 K# RESET_B $end +$var supply1 1 86 VPWR $end +$var supply0 1 96 VGND $end +$var supply1 1 :6 VPB $end +$var supply0 1 ;6 VNB $end + +$scope module base $end +$var wire 1 \& Q $end +$var wire 1 }$ CLK $end +$var wire 1 [& D $end +$var wire 1 K# RESET_B $end +$var wire 1 <6 buf_Q $end +$var wire 1 =6 RESET $end +$upscope $end +$upscope $end + +$scope module FTB_30__29 $end +$var wire 1 t& X $end +$var wire 1 \& A $end +$var supply1 1 >6 VPWR $end +$var supply0 1 ?6 VGND $end +$var supply1 1 @6 VPB $end +$var supply0 1 A6 VNB $end + +$scope module base $end +$var wire 1 t& X $end +$var wire 1 \& A $end +$var wire 1 B6 buf0_out_X $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mem_left_track_1 $end +$var wire 1 K# pReset [0] $end +$var wire 1 }$ prog_clk [0] $end +$var wire 1 p% ccff_head [0] $end +$var wire 1 u& ccff_tail [0] $end +$var wire 1 ]& mem_out [0] $end +$var wire 1 ^& mem_out [1] $end +$var wire 1 _& mem_out [2] $end +$var wire 1 `& mem_out [3] $end + +$scope module sky130_fd_sc_hd__dfrtp_1_0_ $end +$var wire 1 ]& Q $end +$var wire 1 }$ CLK $end +$var wire 1 p% D $end +$var wire 1 K# RESET_B $end +$var supply1 1 C6 VPWR $end +$var supply0 1 D6 VGND $end +$var supply1 1 E6 VPB $end +$var supply0 1 F6 VNB $end + +$scope module base $end +$var wire 1 ]& Q $end +$var wire 1 }$ CLK $end +$var wire 1 p% D $end +$var wire 1 K# RESET_B $end +$var wire 1 G6 buf_Q $end +$var wire 1 H6 RESET $end +$upscope $end +$upscope $end + +$scope module sky130_fd_sc_hd__dfrtp_1_1_ $end +$var wire 1 ^& Q $end +$var wire 1 }$ CLK $end +$var wire 1 ]& D $end +$var wire 1 K# RESET_B $end +$var supply1 1 I6 VPWR $end +$var supply0 1 J6 VGND $end +$var supply1 1 K6 VPB $end +$var supply0 1 L6 VNB $end + +$scope module base $end +$var wire 1 ^& Q $end +$var wire 1 }$ CLK $end +$var wire 1 ]& D $end +$var wire 1 K# RESET_B $end +$var wire 1 M6 buf_Q $end +$var wire 1 N6 RESET $end +$upscope $end +$upscope $end + +$scope module sky130_fd_sc_hd__dfrtp_1_2_ $end +$var wire 1 _& Q $end +$var wire 1 }$ CLK $end +$var wire 1 ^& D $end +$var wire 1 K# RESET_B $end +$var supply1 1 O6 VPWR $end +$var supply0 1 P6 VGND $end +$var supply1 1 Q6 VPB $end +$var supply0 1 R6 VNB $end + +$scope module base $end +$var wire 1 _& Q $end +$var wire 1 }$ CLK $end +$var wire 1 ^& D $end +$var wire 1 K# RESET_B $end +$var wire 1 S6 buf_Q $end +$var wire 1 T6 RESET $end +$upscope $end +$upscope $end + +$scope module sky130_fd_sc_hd__dfrtp_1_3_ $end +$var wire 1 `& Q $end +$var wire 1 }$ CLK $end +$var wire 1 _& D $end +$var wire 1 K# RESET_B $end +$var supply1 1 U6 VPWR $end +$var supply0 1 V6 VGND $end +$var supply1 1 W6 VPB $end +$var supply0 1 X6 VNB $end + +$scope module base $end +$var wire 1 `& Q $end +$var wire 1 }$ CLK $end +$var wire 1 _& D $end +$var wire 1 K# RESET_B $end +$var wire 1 Y6 buf_Q $end +$var wire 1 Z6 RESET $end +$upscope $end +$upscope $end + +$scope module FTB_31__30 $end +$var wire 1 u& X $end +$var wire 1 `& A $end +$var supply1 1 [6 VPWR $end +$var supply0 1 \6 VGND $end +$var supply1 1 ]6 VPB $end +$var supply0 1 ^6 VNB $end + +$scope module base $end +$var wire 1 u& X $end +$var wire 1 `& A $end +$var wire 1 _6 buf0_out_X $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mem_left_track_3 $end +$var wire 1 K# pReset [0] $end +$var wire 1 }$ prog_clk [0] $end +$var wire 1 u& ccff_head [0] $end +$var wire 1 v& ccff_tail [0] $end +$var wire 1 a& mem_out [0] $end +$var wire 1 b& mem_out [1] $end +$var wire 1 c& mem_out [2] $end +$var wire 1 d& mem_out [3] $end + +$scope module sky130_fd_sc_hd__dfrtp_1_0_ $end +$var wire 1 a& Q $end +$var wire 1 }$ CLK $end +$var wire 1 u& D $end +$var wire 1 K# RESET_B $end +$var supply1 1 `6 VPWR $end +$var supply0 1 a6 VGND $end +$var supply1 1 b6 VPB $end +$var supply0 1 c6 VNB $end + +$scope module base $end +$var wire 1 a& Q $end +$var wire 1 }$ CLK $end +$var wire 1 u& D $end +$var wire 1 K# RESET_B $end +$var wire 1 d6 buf_Q $end +$var wire 1 e6 RESET $end +$upscope $end +$upscope $end + +$scope module sky130_fd_sc_hd__dfrtp_1_1_ $end +$var wire 1 b& Q $end +$var wire 1 }$ CLK $end +$var wire 1 a& D $end +$var wire 1 K# RESET_B $end +$var supply1 1 f6 VPWR $end +$var supply0 1 g6 VGND $end +$var supply1 1 h6 VPB $end +$var supply0 1 i6 VNB $end + +$scope module base $end +$var wire 1 b& Q $end +$var wire 1 }$ CLK $end +$var wire 1 a& D $end +$var wire 1 K# RESET_B $end +$var wire 1 j6 buf_Q $end +$var wire 1 k6 RESET $end +$upscope $end +$upscope $end + +$scope module sky130_fd_sc_hd__dfrtp_1_2_ $end +$var wire 1 c& Q $end +$var wire 1 }$ CLK $end +$var wire 1 b& D $end +$var wire 1 K# RESET_B $end +$var supply1 1 l6 VPWR $end +$var supply0 1 m6 VGND $end +$var supply1 1 n6 VPB $end +$var supply0 1 o6 VNB $end + +$scope module base $end +$var wire 1 c& Q $end +$var wire 1 }$ CLK $end +$var wire 1 b& D $end +$var wire 1 K# RESET_B $end +$var wire 1 p6 buf_Q $end +$var wire 1 q6 RESET $end +$upscope $end +$upscope $end + +$scope module sky130_fd_sc_hd__dfrtp_1_3_ $end +$var wire 1 d& Q $end +$var wire 1 }$ CLK $end +$var wire 1 c& D $end +$var wire 1 K# RESET_B $end +$var supply1 1 r6 VPWR $end +$var supply0 1 s6 VGND $end +$var supply1 1 t6 VPB $end +$var supply0 1 u6 VNB $end + +$scope module base $end +$var wire 1 d& Q $end +$var wire 1 }$ CLK $end +$var wire 1 c& D $end +$var wire 1 K# RESET_B $end +$var wire 1 v6 buf_Q $end +$var wire 1 w6 RESET $end +$upscope $end +$upscope $end + +$scope module FTB_32__31 $end +$var wire 1 v& X $end +$var wire 1 d& A $end +$var supply1 1 x6 VPWR $end +$var supply0 1 y6 VGND $end +$var supply1 1 z6 VPB $end +$var supply0 1 {6 VNB $end + +$scope module base $end +$var wire 1 v& X $end +$var wire 1 d& A $end +$var wire 1 |6 buf0_out_X $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mem_left_track_5 $end +$var wire 1 K# pReset [0] $end +$var wire 1 }$ prog_clk [0] $end +$var wire 1 v& ccff_head [0] $end +$var wire 1 w& ccff_tail [0] $end +$var wire 1 e& mem_out [0] $end +$var wire 1 f& mem_out [1] $end +$var wire 1 g& mem_out [2] $end +$var wire 1 h& mem_out [3] $end + +$scope module sky130_fd_sc_hd__dfrtp_1_0_ $end +$var wire 1 e& Q $end +$var wire 1 }$ CLK $end +$var wire 1 v& D $end +$var wire 1 K# RESET_B $end +$var supply1 1 }6 VPWR $end +$var supply0 1 ~6 VGND $end +$var supply1 1 !7 VPB $end +$var supply0 1 "7 VNB $end + +$scope module base $end +$var wire 1 e& Q $end +$var wire 1 }$ CLK $end +$var wire 1 v& D $end +$var wire 1 K# RESET_B $end +$var wire 1 #7 buf_Q $end +$var wire 1 $7 RESET $end +$upscope $end +$upscope $end + +$scope module sky130_fd_sc_hd__dfrtp_1_1_ $end +$var wire 1 f& Q $end +$var wire 1 }$ CLK $end +$var wire 1 e& D $end +$var wire 1 K# RESET_B $end +$var supply1 1 %7 VPWR $end +$var supply0 1 &7 VGND $end +$var supply1 1 '7 VPB $end +$var supply0 1 (7 VNB $end + +$scope module base $end +$var wire 1 f& Q $end +$var wire 1 }$ CLK $end +$var wire 1 e& D $end +$var wire 1 K# RESET_B $end +$var wire 1 )7 buf_Q $end +$var wire 1 *7 RESET $end +$upscope $end +$upscope $end + +$scope module sky130_fd_sc_hd__dfrtp_1_2_ $end +$var wire 1 g& Q $end +$var wire 1 }$ CLK $end +$var wire 1 f& D $end +$var wire 1 K# RESET_B $end +$var supply1 1 +7 VPWR $end +$var supply0 1 ,7 VGND $end +$var supply1 1 -7 VPB $end +$var supply0 1 .7 VNB $end + +$scope module base $end +$var wire 1 g& Q $end +$var wire 1 }$ CLK $end +$var wire 1 f& D $end +$var wire 1 K# RESET_B $end +$var wire 1 /7 buf_Q $end +$var wire 1 07 RESET $end +$upscope $end +$upscope $end + +$scope module sky130_fd_sc_hd__dfrtp_1_3_ $end +$var wire 1 h& Q $end +$var wire 1 }$ CLK $end +$var wire 1 g& D $end +$var wire 1 K# RESET_B $end +$var supply1 1 17 VPWR $end +$var supply0 1 27 VGND $end +$var supply1 1 37 VPB $end +$var supply0 1 47 VNB $end + +$scope module base $end +$var wire 1 h& Q $end +$var wire 1 }$ CLK $end +$var wire 1 g& D $end +$var wire 1 K# RESET_B $end +$var wire 1 57 buf_Q $end +$var wire 1 67 RESET $end +$upscope $end +$upscope $end + +$scope module FTB_33__32 $end +$var wire 1 w& X $end +$var wire 1 h& A $end +$var supply1 1 77 VPWR $end +$var supply0 1 87 VGND $end +$var supply1 1 97 VPB $end +$var supply0 1 :7 VNB $end + +$scope module base $end +$var wire 1 w& X $end +$var wire 1 h& A $end +$var wire 1 ;7 buf0_out_X $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mem_left_track_7 $end +$var wire 1 K# pReset [0] $end +$var wire 1 }$ prog_clk [0] $end +$var wire 1 w& ccff_head [0] $end +$var wire 1 x& ccff_tail [0] $end +$var wire 1 i& mem_out [0] $end +$var wire 1 j& mem_out [1] $end +$var wire 1 k& mem_out [2] $end +$var wire 1 l& mem_out [3] $end + +$scope module sky130_fd_sc_hd__dfrtp_1_0_ $end +$var wire 1 i& Q $end +$var wire 1 }$ CLK $end +$var wire 1 w& D $end +$var wire 1 K# RESET_B $end +$var supply1 1 <7 VPWR $end +$var supply0 1 =7 VGND $end +$var supply1 1 >7 VPB $end +$var supply0 1 ?7 VNB $end + +$scope module base $end +$var wire 1 i& Q $end +$var wire 1 }$ CLK $end +$var wire 1 w& D $end +$var wire 1 K# RESET_B $end +$var wire 1 @7 buf_Q $end +$var wire 1 A7 RESET $end +$upscope $end +$upscope $end + +$scope module sky130_fd_sc_hd__dfrtp_1_1_ $end +$var wire 1 j& Q $end +$var wire 1 }$ CLK $end +$var wire 1 i& D $end +$var wire 1 K# RESET_B $end +$var supply1 1 B7 VPWR $end +$var supply0 1 C7 VGND $end +$var supply1 1 D7 VPB $end +$var supply0 1 E7 VNB $end + +$scope module base $end +$var wire 1 j& Q $end +$var wire 1 }$ CLK $end +$var wire 1 i& D $end +$var wire 1 K# RESET_B $end +$var wire 1 F7 buf_Q $end +$var wire 1 G7 RESET $end +$upscope $end +$upscope $end + +$scope module sky130_fd_sc_hd__dfrtp_1_2_ $end +$var wire 1 k& Q $end +$var wire 1 }$ CLK $end +$var wire 1 j& D $end +$var wire 1 K# RESET_B $end +$var supply1 1 H7 VPWR $end +$var supply0 1 I7 VGND $end +$var supply1 1 J7 VPB $end +$var supply0 1 K7 VNB $end + +$scope module base $end +$var wire 1 k& Q $end +$var wire 1 }$ CLK $end +$var wire 1 j& D $end +$var wire 1 K# RESET_B $end +$var wire 1 L7 buf_Q $end +$var wire 1 M7 RESET $end +$upscope $end +$upscope $end + +$scope module sky130_fd_sc_hd__dfrtp_1_3_ $end +$var wire 1 l& Q $end +$var wire 1 }$ CLK $end +$var wire 1 k& D $end +$var wire 1 K# RESET_B $end +$var supply1 1 N7 VPWR $end +$var supply0 1 O7 VGND $end +$var supply1 1 P7 VPB $end +$var supply0 1 Q7 VNB $end + +$scope module base $end +$var wire 1 l& Q $end +$var wire 1 }$ CLK $end +$var wire 1 k& D $end +$var wire 1 K# RESET_B $end +$var wire 1 R7 buf_Q $end +$var wire 1 S7 RESET $end +$upscope $end +$upscope $end + +$scope module FTB_34__33 $end +$var wire 1 x& X $end +$var wire 1 l& A $end +$var supply1 1 T7 VPWR $end +$var supply0 1 U7 VGND $end +$var supply1 1 V7 VPB $end +$var supply0 1 W7 VNB $end + +$scope module base $end +$var wire 1 x& X $end +$var wire 1 l& A $end +$var wire 1 X7 buf0_out_X $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mem_left_track_9 $end +$var wire 1 K# pReset [0] $end +$var wire 1 }$ prog_clk [0] $end +$var wire 1 x& ccff_head [0] $end +$var wire 1 n& ccff_tail [0] $end +$var wire 1 A& mem_out [0] $end +$var wire 1 B& mem_out [1] $end +$var wire 1 C& mem_out [2] $end +$var wire 1 D& mem_out [3] $end + +$scope module sky130_fd_sc_hd__dfrtp_1_0_ $end +$var wire 1 A& Q $end +$var wire 1 }$ CLK $end +$var wire 1 x& D $end +$var wire 1 K# RESET_B $end +$var supply1 1 Y7 VPWR $end +$var supply0 1 Z7 VGND $end +$var supply1 1 [7 VPB $end +$var supply0 1 \7 VNB $end + +$scope module base $end +$var wire 1 A& Q $end +$var wire 1 }$ CLK $end +$var wire 1 x& D $end +$var wire 1 K# RESET_B $end +$var wire 1 ]7 buf_Q $end +$var wire 1 ^7 RESET $end +$upscope $end +$upscope $end + +$scope module sky130_fd_sc_hd__dfrtp_1_1_ $end +$var wire 1 B& Q $end +$var wire 1 }$ CLK $end +$var wire 1 A& D $end +$var wire 1 K# RESET_B $end +$var supply1 1 _7 VPWR $end +$var supply0 1 `7 VGND $end +$var supply1 1 a7 VPB $end +$var supply0 1 b7 VNB $end + +$scope module base $end +$var wire 1 B& Q $end +$var wire 1 }$ CLK $end +$var wire 1 A& D $end +$var wire 1 K# RESET_B $end +$var wire 1 c7 buf_Q $end +$var wire 1 d7 RESET $end +$upscope $end +$upscope $end + +$scope module sky130_fd_sc_hd__dfrtp_1_2_ $end +$var wire 1 C& Q $end +$var wire 1 }$ CLK $end +$var wire 1 B& D $end +$var wire 1 K# RESET_B $end +$var supply1 1 e7 VPWR $end +$var supply0 1 f7 VGND $end +$var supply1 1 g7 VPB $end +$var supply0 1 h7 VNB $end + +$scope module base $end +$var wire 1 C& Q $end +$var wire 1 }$ CLK $end +$var wire 1 B& D $end +$var wire 1 K# RESET_B $end +$var wire 1 i7 buf_Q $end +$var wire 1 j7 RESET $end +$upscope $end +$upscope $end + +$scope module sky130_fd_sc_hd__dfrtp_1_3_ $end +$var wire 1 D& Q $end +$var wire 1 }$ CLK $end +$var wire 1 C& D $end +$var wire 1 K# RESET_B $end +$var supply1 1 k7 VPWR $end +$var supply0 1 l7 VGND $end +$var supply1 1 m7 VPB $end +$var supply0 1 n7 VNB $end + +$scope module base $end +$var wire 1 D& Q $end +$var wire 1 }$ CLK $end +$var wire 1 C& D $end +$var wire 1 K# RESET_B $end +$var wire 1 o7 buf_Q $end +$var wire 1 p7 RESET $end +$upscope $end +$upscope $end + +$scope module FTB_35__34 $end +$var wire 1 n& X $end +$var wire 1 D& A $end +$var supply1 1 q7 VPWR $end +$var supply0 1 r7 VGND $end +$var supply1 1 s7 VPB $end +$var supply0 1 t7 VNB $end + +$scope module base $end +$var wire 1 n& X $end +$var wire 1 D& A $end +$var wire 1 u7 buf0_out_X $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mem_left_track_11 $end +$var wire 1 K# pReset [0] $end +$var wire 1 }$ prog_clk [0] $end +$var wire 1 n& ccff_head [0] $end +$var wire 1 o& ccff_tail [0] $end +$var wire 1 E& mem_out [0] $end +$var wire 1 F& mem_out [1] $end +$var wire 1 G& mem_out [2] $end +$var wire 1 H& mem_out [3] $end + +$scope module sky130_fd_sc_hd__dfrtp_1_0_ $end +$var wire 1 E& Q $end +$var wire 1 }$ CLK $end +$var wire 1 n& D $end +$var wire 1 K# RESET_B $end +$var supply1 1 v7 VPWR $end +$var supply0 1 w7 VGND $end +$var supply1 1 x7 VPB $end +$var supply0 1 y7 VNB $end + +$scope module base $end +$var wire 1 E& Q $end +$var wire 1 }$ CLK $end +$var wire 1 n& D $end +$var wire 1 K# RESET_B $end +$var wire 1 z7 buf_Q $end +$var wire 1 {7 RESET $end +$upscope $end +$upscope $end + +$scope module sky130_fd_sc_hd__dfrtp_1_1_ $end +$var wire 1 F& Q $end +$var wire 1 }$ CLK $end +$var wire 1 E& D $end +$var wire 1 K# RESET_B $end +$var supply1 1 |7 VPWR $end +$var supply0 1 }7 VGND $end +$var supply1 1 ~7 VPB $end +$var supply0 1 !8 VNB $end + +$scope module base $end +$var wire 1 F& Q $end +$var wire 1 }$ CLK $end +$var wire 1 E& D $end +$var wire 1 K# RESET_B $end +$var wire 1 "8 buf_Q $end +$var wire 1 #8 RESET $end +$upscope $end +$upscope $end + +$scope module sky130_fd_sc_hd__dfrtp_1_2_ $end +$var wire 1 G& Q $end +$var wire 1 }$ CLK $end +$var wire 1 F& D $end +$var wire 1 K# RESET_B $end +$var supply1 1 $8 VPWR $end +$var supply0 1 %8 VGND $end +$var supply1 1 &8 VPB $end +$var supply0 1 '8 VNB $end + +$scope module base $end +$var wire 1 G& Q $end +$var wire 1 }$ CLK $end +$var wire 1 F& D $end +$var wire 1 K# RESET_B $end +$var wire 1 (8 buf_Q $end +$var wire 1 )8 RESET $end +$upscope $end +$upscope $end + +$scope module sky130_fd_sc_hd__dfrtp_1_3_ $end +$var wire 1 H& Q $end +$var wire 1 }$ CLK $end +$var wire 1 G& D $end +$var wire 1 K# RESET_B $end +$var supply1 1 *8 VPWR $end +$var supply0 1 +8 VGND $end +$var supply1 1 ,8 VPB $end +$var supply0 1 -8 VNB $end + +$scope module base $end +$var wire 1 H& Q $end +$var wire 1 }$ CLK $end +$var wire 1 G& D $end +$var wire 1 K# RESET_B $end +$var wire 1 .8 buf_Q $end +$var wire 1 /8 RESET $end +$upscope $end +$upscope $end + +$scope module FTB_36__35 $end +$var wire 1 o& X $end +$var wire 1 H& A $end +$var supply1 1 08 VPWR $end +$var supply0 1 18 VGND $end +$var supply1 1 28 VPB $end +$var supply0 1 38 VNB $end + +$scope module base $end +$var wire 1 o& X $end +$var wire 1 H& A $end +$var wire 1 48 buf0_out_X $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mux_bottom_track_13 $end +$var wire 1 j# in [0] $end +$var wire 1 z# in [1] $end +$var wire 1 !% sram [0] $end +$var wire 1 "% sram [1] $end +$var wire 1 N' sram_inv [0] $end +$var wire 1 O' sram_inv [1] $end +$var wire 1 C$ out [0] $end +$var wire 1 1' p0 $end +$var wire 1 58 mux_2level_tapbuf_basis_input2_mem1_0_out [0] $end +$var wire 1 68 mux_2level_tapbuf_basis_input2_mem1_1_out [0] $end +$var wire 1 78 SYNOPSYS_UNCONNECTED_1 $end +$var wire 1 88 SYNOPSYS_UNCONNECTED_2 $end +$var wire 1 98 SYNOPSYS_UNCONNECTED_3 $end + +$scope module mux_l1_in_0_ $end +$var wire 1 j# in [0] $end +$var wire 1 z# in [1] $end +$var wire 1 !% mem [0] $end +$var wire 1 78 mem_inv [0] $end +$var wire 1 58 out [0] $end + +$scope module sky130_fd_sc_hd__mux2_1_0 $end +$var wire 1 58 X $end +$var wire 1 z# A0 $end +$var wire 1 j# A1 $end +$var wire 1 !% S $end +$var supply1 1 :8 VPWR $end +$var supply0 1 ;8 VGND $end +$var supply1 1 <8 VPB $end +$var supply0 1 =8 VNB $end + +$scope module base $end +$var wire 1 58 X $end +$var wire 1 z# A0 $end +$var wire 1 j# A1 $end +$var wire 1 !% S $end +$var wire 1 >8 mux_2to10_out_X $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mux_l2_in_0_ $end +$var wire 1 58 in [0] $end +$var wire 1 88 in [1] $end +$var wire 1 "% mem [0] $end +$var wire 1 98 mem_inv [0] $end +$var wire 1 68 out [0] $end +$var wire 1 1' p0 $end + +$scope module sky130_fd_sc_hd__mux2_1_0 $end +$var wire 1 68 X $end +$var wire 1 1' A0 $end +$var wire 1 58 A1 $end +$var wire 1 "% S $end +$var supply1 1 ?8 VPWR $end +$var supply0 1 @8 VGND $end +$var supply1 1 A8 VPB $end +$var supply0 1 B8 VNB $end + +$scope module base $end +$var wire 1 68 X $end +$var wire 1 1' A0 $end +$var wire 1 58 A1 $end +$var wire 1 "% S $end +$var wire 1 C8 mux_2to10_out_X $end +$upscope $end +$upscope $end +$upscope $end + +$scope module BUFT_RR_108 $end +$var wire 1 C$ X $end +$var wire 1 68 A $end +$var supply1 1 D8 VPWR $end +$var supply0 1 E8 VGND $end +$var supply1 1 F8 VPB $end +$var supply0 1 G8 VNB $end + +$scope module base $end +$var wire 1 C$ X $end +$var wire 1 68 A $end +$var wire 1 H8 buf0_out_X $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mux_bottom_track_15 $end +$var wire 1 k# in [0] $end +$var wire 1 {# in [1] $end +$var wire 1 7% sram [0] $end +$var wire 1 8% sram [1] $end +$var wire 1 P' sram_inv [0] $end +$var wire 1 Q' sram_inv [1] $end +$var wire 1 D$ out [0] $end +$var wire 1 R' p0 $end +$var wire 1 I8 mux_2level_tapbuf_basis_input2_mem1_0_out [0] $end +$var wire 1 J8 mux_2level_tapbuf_basis_input2_mem1_1_out [0] $end +$var wire 1 K8 SYNOPSYS_UNCONNECTED_1 $end +$var wire 1 L8 SYNOPSYS_UNCONNECTED_2 $end +$var wire 1 M8 SYNOPSYS_UNCONNECTED_3 $end + +$scope module mux_l1_in_0_ $end +$var wire 1 k# in [0] $end +$var wire 1 {# in [1] $end +$var wire 1 7% mem [0] $end +$var wire 1 K8 mem_inv [0] $end +$var wire 1 I8 out [0] $end + +$scope module sky130_fd_sc_hd__mux2_1_0 $end +$var wire 1 I8 X $end +$var wire 1 {# A0 $end +$var wire 1 k# A1 $end +$var wire 1 7% S $end +$var supply1 1 N8 VPWR $end +$var supply0 1 O8 VGND $end +$var supply1 1 P8 VPB $end +$var supply0 1 Q8 VNB $end + +$scope module base $end +$var wire 1 I8 X $end +$var wire 1 {# A0 $end +$var wire 1 k# A1 $end +$var wire 1 7% S $end +$var wire 1 R8 mux_2to10_out_X $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mux_l2_in_0_ $end +$var wire 1 I8 in [0] $end +$var wire 1 L8 in [1] $end +$var wire 1 8% mem [0] $end +$var wire 1 M8 mem_inv [0] $end +$var wire 1 J8 out [0] $end +$var wire 1 R' p0 $end + +$scope module sky130_fd_sc_hd__mux2_1_0 $end +$var wire 1 J8 X $end +$var wire 1 R' A0 $end +$var wire 1 I8 A1 $end +$var wire 1 8% S $end +$var supply1 1 S8 VPWR $end +$var supply0 1 T8 VGND $end +$var supply1 1 U8 VPB $end +$var supply0 1 V8 VNB $end + +$scope module base $end +$var wire 1 J8 X $end +$var wire 1 R' A0 $end +$var wire 1 I8 A1 $end +$var wire 1 8% S $end +$var wire 1 W8 mux_2to10_out_X $end +$upscope $end +$upscope $end +$upscope $end + +$scope module BUFT_RR_109 $end +$var wire 1 D$ X $end +$var wire 1 J8 A $end +$var supply1 1 X8 VPWR $end +$var supply0 1 Y8 VGND $end +$var supply1 1 Z8 VPB $end +$var supply0 1 [8 VNB $end + +$scope module base $end +$var wire 1 D$ X $end +$var wire 1 J8 A $end +$var wire 1 \8 buf0_out_X $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mux_bottom_track_17 $end +$var wire 1 l# in [0] $end +$var wire 1 |# in [1] $end +$var wire 1 M% sram [0] $end +$var wire 1 N% sram [1] $end +$var wire 1 S' sram_inv [0] $end +$var wire 1 T' sram_inv [1] $end +$var wire 1 E$ out [0] $end +$var wire 1 R' p0 $end +$var wire 1 ]8 mux_2level_tapbuf_basis_input2_mem1_0_out [0] $end +$var wire 1 ^8 mux_2level_tapbuf_basis_input2_mem1_1_out [0] $end +$var wire 1 _8 SYNOPSYS_UNCONNECTED_1 $end +$var wire 1 `8 SYNOPSYS_UNCONNECTED_2 $end +$var wire 1 a8 SYNOPSYS_UNCONNECTED_3 $end +$var wire 1 b8 BUF_net_111 $end + +$scope module mux_l1_in_0_ $end +$var wire 1 l# in [0] $end +$var wire 1 |# in [1] $end +$var wire 1 M% mem [0] $end +$var wire 1 _8 mem_inv [0] $end +$var wire 1 ]8 out [0] $end + +$scope module sky130_fd_sc_hd__mux2_1_0 $end +$var wire 1 ]8 X $end +$var wire 1 |# A0 $end +$var wire 1 l# A1 $end +$var wire 1 M% S $end +$var supply1 1 c8 VPWR $end +$var supply0 1 d8 VGND $end +$var supply1 1 e8 VPB $end +$var supply0 1 f8 VNB $end + +$scope module base $end +$var wire 1 ]8 X $end +$var wire 1 |# A0 $end +$var wire 1 l# A1 $end +$var wire 1 M% S $end +$var wire 1 g8 mux_2to10_out_X $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mux_l2_in_0_ $end +$var wire 1 ]8 in [0] $end +$var wire 1 `8 in [1] $end +$var wire 1 N% mem [0] $end +$var wire 1 a8 mem_inv [0] $end +$var wire 1 ^8 out [0] $end +$var wire 1 R' p0 $end + +$scope module sky130_fd_sc_hd__mux2_1_0 $end +$var wire 1 ^8 X $end +$var wire 1 R' A0 $end +$var wire 1 ]8 A1 $end +$var wire 1 N% S $end +$var supply1 1 h8 VPWR $end +$var supply0 1 i8 VGND $end +$var supply1 1 j8 VPB $end +$var supply0 1 k8 VNB $end + +$scope module base $end +$var wire 1 ^8 X $end +$var wire 1 R' A0 $end +$var wire 1 ]8 A1 $end +$var wire 1 N% S $end +$var wire 1 l8 mux_2to10_out_X $end +$upscope $end +$upscope $end +$upscope $end + +$scope module BINV_R_110 $end +$var wire 1 E$ Y $end +$var wire 1 b8 A $end +$var supply1 1 m8 VPWR $end +$var supply0 1 n8 VGND $end +$var supply1 1 o8 VPB $end +$var supply0 1 p8 VNB $end + +$scope module base $end +$var wire 1 E$ Y $end +$var wire 1 b8 A $end +$var wire 1 q8 not0_out_Y $end +$upscope $end +$upscope $end + +$scope module BINV_R_111 $end +$var wire 1 b8 Y $end +$var wire 1 ^8 A $end +$var supply1 1 r8 VPWR $end +$var supply0 1 s8 VGND $end +$var supply1 1 t8 VPB $end +$var supply0 1 u8 VNB $end + +$scope module base $end +$var wire 1 b8 Y $end +$var wire 1 ^8 A $end +$var wire 1 v8 not0_out_Y $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mux_bottom_track_19 $end +$var wire 1 m# in [0] $end +$var wire 1 }# in [1] $end +$var wire 1 ]% sram [0] $end +$var wire 1 ^% sram [1] $end +$var wire 1 U' sram_inv [0] $end +$var wire 1 V' sram_inv [1] $end +$var wire 1 F$ out [0] $end +$var wire 1 R' p0 $end +$var wire 1 w8 mux_2level_tapbuf_basis_input2_mem1_0_out [0] $end +$var wire 1 x8 mux_2level_tapbuf_basis_input2_mem1_1_out [0] $end +$var wire 1 y8 SYNOPSYS_UNCONNECTED_1 $end +$var wire 1 z8 SYNOPSYS_UNCONNECTED_2 $end +$var wire 1 {8 SYNOPSYS_UNCONNECTED_3 $end + +$scope module sky130_fd_sc_hd__buf_4_0_ $end +$var wire 1 F$ X $end +$var wire 1 x8 A $end +$var supply1 1 |8 VPWR $end +$var supply0 1 }8 VGND $end +$var supply1 1 ~8 VPB $end +$var supply0 1 !9 VNB $end + +$scope module base $end +$var wire 1 F$ X $end +$var wire 1 x8 A $end +$var wire 1 "9 buf0_out_X $end +$upscope $end +$upscope $end + +$scope module mux_l1_in_0_ $end +$var wire 1 m# in [0] $end +$var wire 1 }# in [1] $end +$var wire 1 ]% mem [0] $end +$var wire 1 y8 mem_inv [0] $end +$var wire 1 w8 out [0] $end + +$scope module sky130_fd_sc_hd__mux2_1_0 $end +$var wire 1 w8 X $end +$var wire 1 }# A0 $end +$var wire 1 m# A1 $end +$var wire 1 ]% S $end +$var supply1 1 #9 VPWR $end +$var supply0 1 $9 VGND $end +$var supply1 1 %9 VPB $end +$var supply0 1 &9 VNB $end + +$scope module base $end +$var wire 1 w8 X $end +$var wire 1 }# A0 $end +$var wire 1 m# A1 $end +$var wire 1 ]% S $end +$var wire 1 '9 mux_2to10_out_X $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mux_l2_in_0_ $end +$var wire 1 w8 in [0] $end +$var wire 1 z8 in [1] $end +$var wire 1 ^% mem [0] $end +$var wire 1 {8 mem_inv [0] $end +$var wire 1 x8 out [0] $end +$var wire 1 R' p0 $end + +$scope module sky130_fd_sc_hd__mux2_1_0 $end +$var wire 1 x8 X $end +$var wire 1 R' A0 $end +$var wire 1 w8 A1 $end +$var wire 1 ^% S $end +$var supply1 1 (9 VPWR $end +$var supply0 1 )9 VGND $end +$var supply1 1 *9 VPB $end +$var supply0 1 +9 VNB $end + +$scope module base $end +$var wire 1 x8 X $end +$var wire 1 R' A0 $end +$var wire 1 w8 A1 $end +$var wire 1 ^% S $end +$var wire 1 ,9 mux_2to10_out_X $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mux_bottom_track_21 $end +$var wire 1 n# in [0] $end +$var wire 1 ~# in [1] $end +$var wire 1 _% sram [0] $end +$var wire 1 `% sram [1] $end +$var wire 1 W' sram_inv [0] $end +$var wire 1 X' sram_inv [1] $end +$var wire 1 G$ out [0] $end +$var wire 1 Y' p0 $end +$var wire 1 -9 mux_2level_tapbuf_basis_input2_mem1_0_out [0] $end +$var wire 1 .9 mux_2level_tapbuf_basis_input2_mem1_1_out [0] $end +$var wire 1 /9 SYNOPSYS_UNCONNECTED_1 $end +$var wire 1 09 SYNOPSYS_UNCONNECTED_2 $end +$var wire 1 19 SYNOPSYS_UNCONNECTED_3 $end +$var wire 1 29 BUF_net_113 $end + +$scope module mux_l1_in_0_ $end +$var wire 1 n# in [0] $end +$var wire 1 ~# in [1] $end +$var wire 1 _% mem [0] $end +$var wire 1 /9 mem_inv [0] $end +$var wire 1 -9 out [0] $end + +$scope module sky130_fd_sc_hd__mux2_1_0 $end +$var wire 1 -9 X $end +$var wire 1 ~# A0 $end +$var wire 1 n# A1 $end +$var wire 1 _% S $end +$var supply1 1 39 VPWR $end +$var supply0 1 49 VGND $end +$var supply1 1 59 VPB $end +$var supply0 1 69 VNB $end + +$scope module base $end +$var wire 1 -9 X $end +$var wire 1 ~# A0 $end +$var wire 1 n# A1 $end +$var wire 1 _% S $end +$var wire 1 79 mux_2to10_out_X $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mux_l2_in_0_ $end +$var wire 1 -9 in [0] $end +$var wire 1 09 in [1] $end +$var wire 1 `% mem [0] $end +$var wire 1 19 mem_inv [0] $end +$var wire 1 .9 out [0] $end +$var wire 1 Y' p0 $end + +$scope module sky130_fd_sc_hd__mux2_1_0 $end +$var wire 1 .9 X $end +$var wire 1 Y' A0 $end +$var wire 1 -9 A1 $end +$var wire 1 `% S $end +$var supply1 1 89 VPWR $end +$var supply0 1 99 VGND $end +$var supply1 1 :9 VPB $end +$var supply0 1 ;9 VNB $end + +$scope module base $end +$var wire 1 .9 X $end +$var wire 1 Y' A0 $end +$var wire 1 -9 A1 $end +$var wire 1 `% S $end +$var wire 1 <9 mux_2to10_out_X $end +$upscope $end +$upscope $end +$upscope $end + +$scope module BINV_R_112 $end +$var wire 1 G$ Y $end +$var wire 1 29 A $end +$var supply1 1 =9 VPWR $end +$var supply0 1 >9 VGND $end +$var supply1 1 ?9 VPB $end +$var supply0 1 @9 VNB $end + +$scope module base $end +$var wire 1 G$ Y $end +$var wire 1 29 A $end +$var wire 1 A9 not0_out_Y $end +$upscope $end +$upscope $end + +$scope module BINV_R_113 $end +$var wire 1 29 Y $end +$var wire 1 .9 A $end +$var supply1 1 B9 VPWR $end +$var supply0 1 C9 VGND $end +$var supply1 1 D9 VPB $end +$var supply0 1 E9 VNB $end + +$scope module base $end +$var wire 1 29 Y $end +$var wire 1 .9 A $end +$var wire 1 F9 not0_out_Y $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mux_bottom_track_23 $end +$var wire 1 o# in [0] $end +$var wire 1 !$ in [1] $end +$var wire 1 a% sram [0] $end +$var wire 1 b% sram [1] $end +$var wire 1 Z' sram_inv [0] $end +$var wire 1 [' sram_inv [1] $end +$var wire 1 H$ out [0] $end +$var wire 1 Y' p0 $end +$var wire 1 G9 mux_2level_tapbuf_basis_input2_mem1_0_out [0] $end +$var wire 1 H9 mux_2level_tapbuf_basis_input2_mem1_1_out [0] $end +$var wire 1 I9 SYNOPSYS_UNCONNECTED_1 $end +$var wire 1 J9 SYNOPSYS_UNCONNECTED_2 $end +$var wire 1 K9 SYNOPSYS_UNCONNECTED_3 $end +$var wire 1 L9 BUF_net_115 $end + +$scope module mux_l1_in_0_ $end +$var wire 1 o# in [0] $end +$var wire 1 !$ in [1] $end +$var wire 1 a% mem [0] $end +$var wire 1 I9 mem_inv [0] $end +$var wire 1 G9 out [0] $end + +$scope module sky130_fd_sc_hd__mux2_1_0 $end +$var wire 1 G9 X $end +$var wire 1 !$ A0 $end +$var wire 1 o# A1 $end +$var wire 1 a% S $end +$var supply1 1 M9 VPWR $end +$var supply0 1 N9 VGND $end +$var supply1 1 O9 VPB $end +$var supply0 1 P9 VNB $end + +$scope module base $end +$var wire 1 G9 X $end +$var wire 1 !$ A0 $end +$var wire 1 o# A1 $end +$var wire 1 a% S $end +$var wire 1 Q9 mux_2to10_out_X $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mux_l2_in_0_ $end +$var wire 1 G9 in [0] $end +$var wire 1 J9 in [1] $end +$var wire 1 b% mem [0] $end +$var wire 1 K9 mem_inv [0] $end +$var wire 1 H9 out [0] $end +$var wire 1 Y' p0 $end + +$scope module sky130_fd_sc_hd__mux2_1_0 $end +$var wire 1 H9 X $end +$var wire 1 Y' A0 $end +$var wire 1 G9 A1 $end +$var wire 1 b% S $end +$var supply1 1 R9 VPWR $end +$var supply0 1 S9 VGND $end +$var supply1 1 T9 VPB $end +$var supply0 1 U9 VNB $end + +$scope module base $end +$var wire 1 H9 X $end +$var wire 1 Y' A0 $end +$var wire 1 G9 A1 $end +$var wire 1 b% S $end +$var wire 1 V9 mux_2to10_out_X $end +$upscope $end +$upscope $end +$upscope $end + +$scope module BINV_R_114 $end +$var wire 1 H$ Y $end +$var wire 1 L9 A $end +$var supply1 1 W9 VPWR $end +$var supply0 1 X9 VGND $end +$var supply1 1 Y9 VPB $end +$var supply0 1 Z9 VNB $end + +$scope module base $end +$var wire 1 H$ Y $end +$var wire 1 L9 A $end +$var wire 1 [9 not0_out_Y $end +$upscope $end +$upscope $end + +$scope module BINV_R_115 $end +$var wire 1 L9 Y $end +$var wire 1 H9 A $end +$var supply1 1 \9 VPWR $end +$var supply0 1 ]9 VGND $end +$var supply1 1 ^9 VPB $end +$var supply0 1 _9 VNB $end + +$scope module base $end +$var wire 1 L9 Y $end +$var wire 1 H9 A $end +$var wire 1 `9 not0_out_Y $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mux_bottom_track_25 $end +$var wire 1 p# in [0] $end +$var wire 1 "$ in [1] $end +$var wire 1 c% sram [0] $end +$var wire 1 d% sram [1] $end +$var wire 1 \' sram_inv [0] $end +$var wire 1 ]' sram_inv [1] $end +$var wire 1 I$ out [0] $end +$var wire 1 }& p0 $end +$var wire 1 a9 mux_2level_tapbuf_basis_input2_mem1_0_out [0] $end +$var wire 1 b9 mux_2level_tapbuf_basis_input2_mem1_1_out [0] $end +$var wire 1 c9 SYNOPSYS_UNCONNECTED_1 $end +$var wire 1 d9 SYNOPSYS_UNCONNECTED_2 $end +$var wire 1 e9 SYNOPSYS_UNCONNECTED_3 $end +$var wire 1 f9 BUF_net_117 $end + +$scope module mux_l1_in_0_ $end +$var wire 1 p# in [0] $end +$var wire 1 "$ in [1] $end +$var wire 1 c% mem [0] $end +$var wire 1 c9 mem_inv [0] $end +$var wire 1 a9 out [0] $end + +$scope module sky130_fd_sc_hd__mux2_1_0 $end +$var wire 1 a9 X $end +$var wire 1 "$ A0 $end +$var wire 1 p# A1 $end +$var wire 1 c% S $end +$var supply1 1 g9 VPWR $end +$var supply0 1 h9 VGND $end +$var supply1 1 i9 VPB $end +$var supply0 1 j9 VNB $end + +$scope module base $end +$var wire 1 a9 X $end +$var wire 1 "$ A0 $end +$var wire 1 p# A1 $end +$var wire 1 c% S $end +$var wire 1 k9 mux_2to10_out_X $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mux_l2_in_0_ $end +$var wire 1 a9 in [0] $end +$var wire 1 d9 in [1] $end +$var wire 1 d% mem [0] $end +$var wire 1 e9 mem_inv [0] $end +$var wire 1 b9 out [0] $end +$var wire 1 }& p0 $end + +$scope module sky130_fd_sc_hd__mux2_1_0 $end +$var wire 1 b9 X $end +$var wire 1 }& A0 $end +$var wire 1 a9 A1 $end +$var wire 1 d% S $end +$var supply1 1 l9 VPWR $end +$var supply0 1 m9 VGND $end +$var supply1 1 n9 VPB $end +$var supply0 1 o9 VNB $end + +$scope module base $end +$var wire 1 b9 X $end +$var wire 1 }& A0 $end +$var wire 1 a9 A1 $end +$var wire 1 d% S $end +$var wire 1 p9 mux_2to10_out_X $end +$upscope $end +$upscope $end +$upscope $end + +$scope module BINV_R_116 $end +$var wire 1 I$ Y $end +$var wire 1 f9 A $end +$var supply1 1 q9 VPWR $end +$var supply0 1 r9 VGND $end +$var supply1 1 s9 VPB $end +$var supply0 1 t9 VNB $end + +$scope module base $end +$var wire 1 I$ Y $end +$var wire 1 f9 A $end +$var wire 1 u9 not0_out_Y $end +$upscope $end +$upscope $end + +$scope module BINV_R_117 $end +$var wire 1 f9 Y $end +$var wire 1 b9 A $end +$var supply1 1 v9 VPWR $end +$var supply0 1 w9 VGND $end +$var supply1 1 x9 VPB $end +$var supply0 1 y9 VNB $end + +$scope module base $end +$var wire 1 f9 Y $end +$var wire 1 b9 A $end +$var wire 1 z9 not0_out_Y $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mux_bottom_track_27 $end +$var wire 1 q# in [0] $end +$var wire 1 #$ in [1] $end +$var wire 1 e% sram [0] $end +$var wire 1 f% sram [1] $end +$var wire 1 ^' sram_inv [0] $end +$var wire 1 _' sram_inv [1] $end +$var wire 1 J$ out [0] $end +$var wire 1 1' p0 $end +$var wire 1 {9 mux_2level_tapbuf_basis_input2_mem1_0_out [0] $end +$var wire 1 |9 mux_2level_tapbuf_basis_input2_mem1_1_out [0] $end +$var wire 1 }9 SYNOPSYS_UNCONNECTED_1 $end +$var wire 1 ~9 SYNOPSYS_UNCONNECTED_2 $end +$var wire 1 !: SYNOPSYS_UNCONNECTED_3 $end +$var wire 1 ": BUF_net_119 $end + +$scope module mux_l1_in_0_ $end +$var wire 1 q# in [0] $end +$var wire 1 #$ in [1] $end +$var wire 1 e% mem [0] $end +$var wire 1 }9 mem_inv [0] $end +$var wire 1 {9 out [0] $end + +$scope module sky130_fd_sc_hd__mux2_1_0 $end +$var wire 1 {9 X $end +$var wire 1 #$ A0 $end +$var wire 1 q# A1 $end +$var wire 1 e% S $end +$var supply1 1 #: VPWR $end +$var supply0 1 $: VGND $end +$var supply1 1 %: VPB $end +$var supply0 1 &: VNB $end + +$scope module base $end +$var wire 1 {9 X $end +$var wire 1 #$ A0 $end +$var wire 1 q# A1 $end +$var wire 1 e% S $end +$var wire 1 ': mux_2to10_out_X $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mux_l2_in_0_ $end +$var wire 1 {9 in [0] $end +$var wire 1 ~9 in [1] $end +$var wire 1 f% mem [0] $end +$var wire 1 !: mem_inv [0] $end +$var wire 1 |9 out [0] $end +$var wire 1 1' p0 $end + +$scope module sky130_fd_sc_hd__mux2_1_0 $end +$var wire 1 |9 X $end +$var wire 1 1' A0 $end +$var wire 1 {9 A1 $end +$var wire 1 f% S $end +$var supply1 1 (: VPWR $end +$var supply0 1 ): VGND $end +$var supply1 1 *: VPB $end +$var supply0 1 +: VNB $end + +$scope module base $end +$var wire 1 |9 X $end +$var wire 1 1' A0 $end +$var wire 1 {9 A1 $end +$var wire 1 f% S $end +$var wire 1 ,: mux_2to10_out_X $end +$upscope $end +$upscope $end +$upscope $end + +$scope module BINV_R_118 $end +$var wire 1 J$ Y $end +$var wire 1 ": A $end +$var supply1 1 -: VPWR $end +$var supply0 1 .: VGND $end +$var supply1 1 /: VPB $end +$var supply0 1 0: VNB $end + +$scope module base $end +$var wire 1 J$ Y $end +$var wire 1 ": A $end +$var wire 1 1: not0_out_Y $end +$upscope $end +$upscope $end + +$scope module BINV_R_119 $end +$var wire 1 ": Y $end +$var wire 1 |9 A $end +$var supply1 1 2: VPWR $end +$var supply0 1 3: VGND $end +$var supply1 1 4: VPB $end +$var supply0 1 5: VNB $end + +$scope module base $end +$var wire 1 ": Y $end +$var wire 1 |9 A $end +$var wire 1 6: not0_out_Y $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mux_bottom_track_39 $end +$var wire 1 k# in [0] $end +$var wire 1 )$ in [1] $end +$var wire 1 g% sram [0] $end +$var wire 1 h% sram [1] $end +$var wire 1 `' sram_inv [0] $end +$var wire 1 a' sram_inv [1] $end +$var wire 1 P$ out [0] $end +$var wire 1 Y' p0 $end +$var wire 1 7: mux_2level_tapbuf_basis_input2_mem1_0_out [0] $end +$var wire 1 8: mux_2level_tapbuf_basis_input2_mem1_1_out [0] $end +$var wire 1 9: SYNOPSYS_UNCONNECTED_1 $end +$var wire 1 :: SYNOPSYS_UNCONNECTED_2 $end +$var wire 1 ;: SYNOPSYS_UNCONNECTED_3 $end +$var wire 1 <: BUF_net_121 $end + +$scope module mux_l1_in_0_ $end +$var wire 1 k# in [0] $end +$var wire 1 )$ in [1] $end +$var wire 1 g% mem [0] $end +$var wire 1 9: mem_inv [0] $end +$var wire 1 7: out [0] $end + +$scope module sky130_fd_sc_hd__mux2_1_0 $end +$var wire 1 7: X $end +$var wire 1 )$ A0 $end +$var wire 1 k# A1 $end +$var wire 1 g% S $end +$var supply1 1 =: VPWR $end +$var supply0 1 >: VGND $end +$var supply1 1 ?: VPB $end +$var supply0 1 @: VNB $end + +$scope module base $end +$var wire 1 7: X $end +$var wire 1 )$ A0 $end +$var wire 1 k# A1 $end +$var wire 1 g% S $end +$var wire 1 A: mux_2to10_out_X $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mux_l2_in_0_ $end +$var wire 1 7: in [0] $end +$var wire 1 :: in [1] $end +$var wire 1 h% mem [0] $end +$var wire 1 ;: mem_inv [0] $end +$var wire 1 8: out [0] $end +$var wire 1 Y' p0 $end + +$scope module sky130_fd_sc_hd__mux2_1_0 $end +$var wire 1 8: X $end +$var wire 1 Y' A0 $end +$var wire 1 7: A1 $end +$var wire 1 h% S $end +$var supply1 1 B: VPWR $end +$var supply0 1 C: VGND $end +$var supply1 1 D: VPB $end +$var supply0 1 E: VNB $end + +$scope module base $end +$var wire 1 8: X $end +$var wire 1 Y' A0 $end +$var wire 1 7: A1 $end +$var wire 1 h% S $end +$var wire 1 F: mux_2to10_out_X $end +$upscope $end +$upscope $end +$upscope $end + +$scope module BINV_R_120 $end +$var wire 1 P$ Y $end +$var wire 1 <: A $end +$var supply1 1 G: VPWR $end +$var supply0 1 H: VGND $end +$var supply1 1 I: VPB $end +$var supply0 1 J: VNB $end + +$scope module base $end +$var wire 1 P$ Y $end +$var wire 1 <: A $end +$var wire 1 K: not0_out_Y $end +$upscope $end +$upscope $end + +$scope module BINV_R_121 $end +$var wire 1 <: Y $end +$var wire 1 8: A $end +$var supply1 1 L: VPWR $end +$var supply0 1 M: VGND $end +$var supply1 1 N: VPB $end +$var supply0 1 O: VNB $end + +$scope module base $end +$var wire 1 <: Y $end +$var wire 1 8: A $end +$var wire 1 P: not0_out_Y $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mux_bottom_track_41 $end +$var wire 1 l# in [0] $end +$var wire 1 *$ in [1] $end +$var wire 1 i% sram [0] $end +$var wire 1 j% sram [1] $end +$var wire 1 b' sram_inv [0] $end +$var wire 1 c' sram_inv [1] $end +$var wire 1 Q$ out [0] $end +$var wire 1 R' p0 $end +$var wire 1 Q: mux_2level_tapbuf_basis_input2_mem1_0_out [0] $end +$var wire 1 R: mux_2level_tapbuf_basis_input2_mem1_1_out [0] $end +$var wire 1 S: SYNOPSYS_UNCONNECTED_1 $end +$var wire 1 T: SYNOPSYS_UNCONNECTED_2 $end +$var wire 1 U: SYNOPSYS_UNCONNECTED_3 $end + +$scope module sky130_fd_sc_hd__buf_4_0_ $end +$var wire 1 Q$ X $end +$var wire 1 R: A $end +$var supply1 1 V: VPWR $end +$var supply0 1 W: VGND $end +$var supply1 1 X: VPB $end +$var supply0 1 Y: VNB $end + +$scope module base $end +$var wire 1 Q$ X $end +$var wire 1 R: A $end +$var wire 1 Z: buf0_out_X $end +$upscope $end +$upscope $end + +$scope module mux_l1_in_0_ $end +$var wire 1 l# in [0] $end +$var wire 1 *$ in [1] $end +$var wire 1 i% mem [0] $end +$var wire 1 S: mem_inv [0] $end +$var wire 1 Q: out [0] $end + +$scope module sky130_fd_sc_hd__mux2_1_0 $end +$var wire 1 Q: X $end +$var wire 1 *$ A0 $end +$var wire 1 l# A1 $end +$var wire 1 i% S $end +$var supply1 1 [: VPWR $end +$var supply0 1 \: VGND $end +$var supply1 1 ]: VPB $end +$var supply0 1 ^: VNB $end + +$scope module base $end +$var wire 1 Q: X $end +$var wire 1 *$ A0 $end +$var wire 1 l# A1 $end +$var wire 1 i% S $end +$var wire 1 _: mux_2to10_out_X $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mux_l2_in_0_ $end +$var wire 1 Q: in [0] $end +$var wire 1 T: in [1] $end +$var wire 1 j% mem [0] $end +$var wire 1 U: mem_inv [0] $end +$var wire 1 R: out [0] $end +$var wire 1 R' p0 $end + +$scope module sky130_fd_sc_hd__mux2_1_0 $end +$var wire 1 R: X $end +$var wire 1 R' A0 $end +$var wire 1 Q: A1 $end +$var wire 1 j% S $end +$var supply1 1 `: VPWR $end +$var supply0 1 a: VGND $end +$var supply1 1 b: VPB $end +$var supply0 1 c: VNB $end + +$scope module base $end +$var wire 1 R: X $end +$var wire 1 R' A0 $end +$var wire 1 Q: A1 $end +$var wire 1 j% S $end +$var wire 1 d: mux_2to10_out_X $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mux_bottom_track_43 $end +$var wire 1 m# in [0] $end +$var wire 1 +$ in [1] $end +$var wire 1 #% sram [0] $end +$var wire 1 $% sram [1] $end +$var wire 1 d' sram_inv [0] $end +$var wire 1 e' sram_inv [1] $end +$var wire 1 R$ out [0] $end +$var wire 1 R' p0 $end +$var wire 1 e: mux_2level_tapbuf_basis_input2_mem1_0_out [0] $end +$var wire 1 f: mux_2level_tapbuf_basis_input2_mem1_1_out [0] $end +$var wire 1 g: SYNOPSYS_UNCONNECTED_1 $end +$var wire 1 h: SYNOPSYS_UNCONNECTED_2 $end +$var wire 1 i: SYNOPSYS_UNCONNECTED_3 $end +$var wire 1 j: BUF_net_123 $end + +$scope module mux_l1_in_0_ $end +$var wire 1 m# in [0] $end +$var wire 1 +$ in [1] $end +$var wire 1 #% mem [0] $end +$var wire 1 g: mem_inv [0] $end +$var wire 1 e: out [0] $end + +$scope module sky130_fd_sc_hd__mux2_1_0 $end +$var wire 1 e: X $end +$var wire 1 +$ A0 $end +$var wire 1 m# A1 $end +$var wire 1 #% S $end +$var supply1 1 k: VPWR $end +$var supply0 1 l: VGND $end +$var supply1 1 m: VPB $end +$var supply0 1 n: VNB $end + +$scope module base $end +$var wire 1 e: X $end +$var wire 1 +$ A0 $end +$var wire 1 m# A1 $end +$var wire 1 #% S $end +$var wire 1 o: mux_2to10_out_X $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mux_l2_in_0_ $end +$var wire 1 e: in [0] $end +$var wire 1 h: in [1] $end +$var wire 1 $% mem [0] $end +$var wire 1 i: mem_inv [0] $end +$var wire 1 f: out [0] $end +$var wire 1 R' p0 $end + +$scope module sky130_fd_sc_hd__mux2_1_0 $end +$var wire 1 f: X $end +$var wire 1 R' A0 $end +$var wire 1 e: A1 $end +$var wire 1 $% S $end +$var supply1 1 p: VPWR $end +$var supply0 1 q: VGND $end +$var supply1 1 r: VPB $end +$var supply0 1 s: VNB $end + +$scope module base $end +$var wire 1 f: X $end +$var wire 1 R' A0 $end +$var wire 1 e: A1 $end +$var wire 1 $% S $end +$var wire 1 t: mux_2to10_out_X $end +$upscope $end +$upscope $end +$upscope $end + +$scope module BINV_R_122 $end +$var wire 1 R$ Y $end +$var wire 1 j: A $end +$var supply1 1 u: VPWR $end +$var supply0 1 v: VGND $end +$var supply1 1 w: VPB $end +$var supply0 1 x: VNB $end + +$scope module base $end +$var wire 1 R$ Y $end +$var wire 1 j: A $end +$var wire 1 y: not0_out_Y $end +$upscope $end +$upscope $end + +$scope module BINV_R_123 $end +$var wire 1 j: Y $end +$var wire 1 f: A $end +$var supply1 1 z: VPWR $end +$var supply0 1 {: VGND $end +$var supply1 1 |: VPB $end +$var supply0 1 }: VNB $end + +$scope module base $end +$var wire 1 j: Y $end +$var wire 1 f: A $end +$var wire 1 ~: not0_out_Y $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mux_bottom_track_47 $end +$var wire 1 o# in [0] $end +$var wire 1 -$ in [1] $end +$var wire 1 %% sram [0] $end +$var wire 1 &% sram [1] $end +$var wire 1 f' sram_inv [0] $end +$var wire 1 g' sram_inv [1] $end +$var wire 1 T$ out [0] $end +$var wire 1 R' p0 $end +$var wire 1 !; mux_2level_tapbuf_basis_input2_mem1_0_out [0] $end +$var wire 1 "; mux_2level_tapbuf_basis_input2_mem1_1_out [0] $end +$var wire 1 #; SYNOPSYS_UNCONNECTED_1 $end +$var wire 1 $; SYNOPSYS_UNCONNECTED_2 $end +$var wire 1 %; SYNOPSYS_UNCONNECTED_3 $end +$var wire 1 &; BUF_net_125 $end + +$scope module mux_l1_in_0_ $end +$var wire 1 o# in [0] $end +$var wire 1 -$ in [1] $end +$var wire 1 %% mem [0] $end +$var wire 1 #; mem_inv [0] $end +$var wire 1 !; out [0] $end + +$scope module sky130_fd_sc_hd__mux2_1_0 $end +$var wire 1 !; X $end +$var wire 1 -$ A0 $end +$var wire 1 o# A1 $end +$var wire 1 %% S $end +$var supply1 1 '; VPWR $end +$var supply0 1 (; VGND $end +$var supply1 1 ); VPB $end +$var supply0 1 *; VNB $end + +$scope module base $end +$var wire 1 !; X $end +$var wire 1 -$ A0 $end +$var wire 1 o# A1 $end +$var wire 1 %% S $end +$var wire 1 +; mux_2to10_out_X $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mux_l2_in_0_ $end +$var wire 1 !; in [0] $end +$var wire 1 $; in [1] $end +$var wire 1 &% mem [0] $end +$var wire 1 %; mem_inv [0] $end +$var wire 1 "; out [0] $end +$var wire 1 R' p0 $end + +$scope module sky130_fd_sc_hd__mux2_1_0 $end +$var wire 1 "; X $end +$var wire 1 R' A0 $end +$var wire 1 !; A1 $end +$var wire 1 &% S $end +$var supply1 1 ,; VPWR $end +$var supply0 1 -; VGND $end +$var supply1 1 .; VPB $end +$var supply0 1 /; VNB $end + +$scope module base $end +$var wire 1 "; X $end +$var wire 1 R' A0 $end +$var wire 1 !; A1 $end +$var wire 1 &% S $end +$var wire 1 0; mux_2to10_out_X $end +$upscope $end +$upscope $end +$upscope $end + +$scope module BINV_R_124 $end +$var wire 1 T$ Y $end +$var wire 1 &; A $end +$var supply1 1 1; VPWR $end +$var supply0 1 2; VGND $end +$var supply1 1 3; VPB $end +$var supply0 1 4; VNB $end + +$scope module base $end +$var wire 1 T$ Y $end +$var wire 1 &; A $end +$var wire 1 5; not0_out_Y $end +$upscope $end +$upscope $end + +$scope module BINV_R_125 $end +$var wire 1 &; Y $end +$var wire 1 "; A $end +$var supply1 1 6; VPWR $end +$var supply0 1 7; VGND $end +$var supply1 1 8; VPB $end +$var supply0 1 9; VNB $end + +$scope module base $end +$var wire 1 &; Y $end +$var wire 1 "; A $end +$var wire 1 :; not0_out_Y $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mux_bottom_track_49 $end +$var wire 1 p# in [0] $end +$var wire 1 .$ in [1] $end +$var wire 1 '% sram [0] $end +$var wire 1 (% sram [1] $end +$var wire 1 h' sram_inv [0] $end +$var wire 1 i' sram_inv [1] $end +$var wire 1 U$ out [0] $end +$var wire 1 1' p0 $end +$var wire 1 ;; mux_2level_tapbuf_basis_input2_mem1_0_out [0] $end +$var wire 1 <; mux_2level_tapbuf_basis_input2_mem1_1_out [0] $end +$var wire 1 =; SYNOPSYS_UNCONNECTED_1 $end +$var wire 1 >; SYNOPSYS_UNCONNECTED_2 $end +$var wire 1 ?; SYNOPSYS_UNCONNECTED_3 $end +$var wire 1 @; BUF_net_127 $end + +$scope module mux_l1_in_0_ $end +$var wire 1 p# in [0] $end +$var wire 1 .$ in [1] $end +$var wire 1 '% mem [0] $end +$var wire 1 =; mem_inv [0] $end +$var wire 1 ;; out [0] $end + +$scope module sky130_fd_sc_hd__mux2_1_0 $end +$var wire 1 ;; X $end +$var wire 1 .$ A0 $end +$var wire 1 p# A1 $end +$var wire 1 '% S $end +$var supply1 1 A; VPWR $end +$var supply0 1 B; VGND $end +$var supply1 1 C; VPB $end +$var supply0 1 D; VNB $end + +$scope module base $end +$var wire 1 ;; X $end +$var wire 1 .$ A0 $end +$var wire 1 p# A1 $end +$var wire 1 '% S $end +$var wire 1 E; mux_2to10_out_X $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mux_l2_in_0_ $end +$var wire 1 ;; in [0] $end +$var wire 1 >; in [1] $end +$var wire 1 (% mem [0] $end +$var wire 1 ?; mem_inv [0] $end +$var wire 1 <; out [0] $end +$var wire 1 1' p0 $end + +$scope module sky130_fd_sc_hd__mux2_1_0 $end +$var wire 1 <; X $end +$var wire 1 1' A0 $end +$var wire 1 ;; A1 $end +$var wire 1 (% S $end +$var supply1 1 F; VPWR $end +$var supply0 1 G; VGND $end +$var supply1 1 H; VPB $end +$var supply0 1 I; VNB $end + +$scope module base $end +$var wire 1 <; X $end +$var wire 1 1' A0 $end +$var wire 1 ;; A1 $end +$var wire 1 (% S $end +$var wire 1 J; mux_2to10_out_X $end +$upscope $end +$upscope $end +$upscope $end + +$scope module BINV_R_126 $end +$var wire 1 U$ Y $end +$var wire 1 @; A $end +$var supply1 1 K; VPWR $end +$var supply0 1 L; VGND $end +$var supply1 1 M; VPB $end +$var supply0 1 N; VNB $end + +$scope module base $end +$var wire 1 U$ Y $end +$var wire 1 @; A $end +$var wire 1 O; not0_out_Y $end +$upscope $end +$upscope $end + +$scope module BINV_R_127 $end +$var wire 1 @; Y $end +$var wire 1 <; A $end +$var supply1 1 P; VPWR $end +$var supply0 1 Q; VGND $end +$var supply1 1 R; VPB $end +$var supply0 1 S; VNB $end + +$scope module base $end +$var wire 1 @; Y $end +$var wire 1 <; A $end +$var wire 1 T; not0_out_Y $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mux_bottom_track_51 $end +$var wire 1 q# in [0] $end +$var wire 1 /$ in [1] $end +$var wire 1 )% sram [0] $end +$var wire 1 *% sram [1] $end +$var wire 1 j' sram_inv [0] $end +$var wire 1 k' sram_inv [1] $end +$var wire 1 V$ out [0] $end +$var wire 1 1' p0 $end +$var wire 1 U; mux_2level_tapbuf_basis_input2_mem1_0_out [0] $end +$var wire 1 V; mux_2level_tapbuf_basis_input2_mem1_1_out [0] $end +$var wire 1 W; SYNOPSYS_UNCONNECTED_1 $end +$var wire 1 X; SYNOPSYS_UNCONNECTED_2 $end +$var wire 1 Y; SYNOPSYS_UNCONNECTED_3 $end +$var wire 1 Z; BUF_net_129 $end + +$scope module mux_l1_in_0_ $end +$var wire 1 q# in [0] $end +$var wire 1 /$ in [1] $end +$var wire 1 )% mem [0] $end +$var wire 1 W; mem_inv [0] $end +$var wire 1 U; out [0] $end + +$scope module sky130_fd_sc_hd__mux2_1_0 $end +$var wire 1 U; X $end +$var wire 1 /$ A0 $end +$var wire 1 q# A1 $end +$var wire 1 )% S $end +$var supply1 1 [; VPWR $end +$var supply0 1 \; VGND $end +$var supply1 1 ]; VPB $end +$var supply0 1 ^; VNB $end + +$scope module base $end +$var wire 1 U; X $end +$var wire 1 /$ A0 $end +$var wire 1 q# A1 $end +$var wire 1 )% S $end +$var wire 1 _; mux_2to10_out_X $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mux_l2_in_0_ $end +$var wire 1 U; in [0] $end +$var wire 1 X; in [1] $end +$var wire 1 *% mem [0] $end +$var wire 1 Y; mem_inv [0] $end +$var wire 1 V; out [0] $end +$var wire 1 1' p0 $end + +$scope module sky130_fd_sc_hd__mux2_1_0 $end +$var wire 1 V; X $end +$var wire 1 1' A0 $end +$var wire 1 U; A1 $end +$var wire 1 *% S $end +$var supply1 1 `; VPWR $end +$var supply0 1 a; VGND $end +$var supply1 1 b; VPB $end +$var supply0 1 c; VNB $end + +$scope module base $end +$var wire 1 V; X $end +$var wire 1 1' A0 $end +$var wire 1 U; A1 $end +$var wire 1 *% S $end +$var wire 1 d; mux_2to10_out_X $end +$upscope $end +$upscope $end +$upscope $end + +$scope module BINV_R_128 $end +$var wire 1 V$ Y $end +$var wire 1 Z; A $end +$var supply1 1 e; VPWR $end +$var supply0 1 f; VGND $end +$var supply1 1 g; VPB $end +$var supply0 1 h; VNB $end + +$scope module base $end +$var wire 1 V$ Y $end +$var wire 1 Z; A $end +$var wire 1 i; not0_out_Y $end +$upscope $end +$upscope $end + +$scope module BINV_R_129 $end +$var wire 1 Z; Y $end +$var wire 1 V; A $end +$var supply1 1 j; VPWR $end +$var supply0 1 k; VGND $end +$var supply1 1 l; VPB $end +$var supply0 1 m; VNB $end + +$scope module base $end +$var wire 1 Z; Y $end +$var wire 1 V; A $end +$var wire 1 n; not0_out_Y $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mux_bottom_track_53 $end +$var wire 1 r# in [0] $end +$var wire 1 0$ in [1] $end +$var wire 1 +% sram [0] $end +$var wire 1 ,% sram [1] $end +$var wire 1 l' sram_inv [0] $end +$var wire 1 m' sram_inv [1] $end +$var wire 1 W$ out [0] $end +$var wire 1 (' p0 $end +$var wire 1 o; mux_2level_tapbuf_basis_input2_mem1_0_out [0] $end +$var wire 1 p; mux_2level_tapbuf_basis_input2_mem1_1_out [0] $end +$var wire 1 q; SYNOPSYS_UNCONNECTED_1 $end +$var wire 1 r; SYNOPSYS_UNCONNECTED_2 $end +$var wire 1 s; SYNOPSYS_UNCONNECTED_3 $end +$var wire 1 t; BUF_net_131 $end + +$scope module mux_l1_in_0_ $end +$var wire 1 r# in [0] $end +$var wire 1 0$ in [1] $end +$var wire 1 +% mem [0] $end +$var wire 1 q; mem_inv [0] $end +$var wire 1 o; out [0] $end + +$scope module sky130_fd_sc_hd__mux2_1_0 $end +$var wire 1 o; X $end +$var wire 1 0$ A0 $end +$var wire 1 r# A1 $end +$var wire 1 +% S $end +$var supply1 1 u; VPWR $end +$var supply0 1 v; VGND $end +$var supply1 1 w; VPB $end +$var supply0 1 x; VNB $end + +$scope module base $end +$var wire 1 o; X $end +$var wire 1 0$ A0 $end +$var wire 1 r# A1 $end +$var wire 1 +% S $end +$var wire 1 y; mux_2to10_out_X $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mux_l2_in_0_ $end +$var wire 1 o; in [0] $end +$var wire 1 r; in [1] $end +$var wire 1 ,% mem [0] $end +$var wire 1 s; mem_inv [0] $end +$var wire 1 p; out [0] $end +$var wire 1 (' p0 $end + +$scope module sky130_fd_sc_hd__mux2_1_0 $end +$var wire 1 p; X $end +$var wire 1 (' A0 $end +$var wire 1 o; A1 $end +$var wire 1 ,% S $end +$var supply1 1 z; VPWR $end +$var supply0 1 {; VGND $end +$var supply1 1 |; VPB $end +$var supply0 1 }; VNB $end + +$scope module base $end +$var wire 1 p; X $end +$var wire 1 (' A0 $end +$var wire 1 o; A1 $end +$var wire 1 ,% S $end +$var wire 1 ~; mux_2to10_out_X $end +$upscope $end +$upscope $end +$upscope $end + +$scope module BINV_R_130 $end +$var wire 1 W$ Y $end +$var wire 1 t; A $end +$var supply1 1 !< VPWR $end +$var supply0 1 "< VGND $end +$var supply1 1 #< VPB $end +$var supply0 1 $< VNB $end + +$scope module base $end +$var wire 1 W$ Y $end +$var wire 1 t; A $end +$var wire 1 %< not0_out_Y $end +$upscope $end +$upscope $end + +$scope module BINV_R_131 $end +$var wire 1 t; Y $end +$var wire 1 p; A $end +$var supply1 1 &< VPWR $end +$var supply0 1 '< VGND $end +$var supply1 1 (< VPB $end +$var supply0 1 )< VNB $end + +$scope module base $end +$var wire 1 t; Y $end +$var wire 1 p; A $end +$var wire 1 *< not0_out_Y $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mux_left_track_13 $end +$var wire 1 Q# in [0] $end +$var wire 1 3$ in [1] $end +$var wire 1 -% sram [0] $end +$var wire 1 .% sram [1] $end +$var wire 1 n' sram_inv [0] $end +$var wire 1 o' sram_inv [1] $end +$var wire 1 a$ out [0] $end +$var wire 1 p' p0 $end +$var wire 1 +< mux_2level_tapbuf_basis_input2_mem1_0_out [0] $end +$var wire 1 ,< mux_2level_tapbuf_basis_input2_mem1_1_out [0] $end +$var wire 1 -< SYNOPSYS_UNCONNECTED_1 $end +$var wire 1 .< SYNOPSYS_UNCONNECTED_2 $end +$var wire 1 /< SYNOPSYS_UNCONNECTED_3 $end +$var wire 1 0< BUF_net_133 $end + +$scope module mux_l1_in_0_ $end +$var wire 1 Q# in [0] $end +$var wire 1 3$ in [1] $end +$var wire 1 -% mem [0] $end +$var wire 1 -< mem_inv [0] $end +$var wire 1 +< out [0] $end + +$scope module sky130_fd_sc_hd__mux2_1_0 $end +$var wire 1 +< X $end +$var wire 1 3$ A0 $end +$var wire 1 Q# A1 $end +$var wire 1 -% S $end +$var supply1 1 1< VPWR $end +$var supply0 1 2< VGND $end +$var supply1 1 3< VPB $end +$var supply0 1 4< VNB $end + +$scope module base $end +$var wire 1 +< X $end +$var wire 1 3$ A0 $end +$var wire 1 Q# A1 $end +$var wire 1 -% S $end +$var wire 1 5< mux_2to10_out_X $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mux_l2_in_0_ $end +$var wire 1 +< in [0] $end +$var wire 1 .< in [1] $end +$var wire 1 .% mem [0] $end +$var wire 1 /< mem_inv [0] $end +$var wire 1 ,< out [0] $end +$var wire 1 p' p0 $end + +$scope module sky130_fd_sc_hd__mux2_1_0 $end +$var wire 1 ,< X $end +$var wire 1 p' A0 $end +$var wire 1 +< A1 $end +$var wire 1 .% S $end +$var supply1 1 6< VPWR $end +$var supply0 1 7< VGND $end +$var supply1 1 8< VPB $end +$var supply0 1 9< VNB $end + +$scope module base $end +$var wire 1 ,< X $end +$var wire 1 p' A0 $end +$var wire 1 +< A1 $end +$var wire 1 .% S $end +$var wire 1 :< mux_2to10_out_X $end +$upscope $end +$upscope $end +$upscope $end + +$scope module BINV_R_132 $end +$var wire 1 a$ Y $end +$var wire 1 0< A $end +$var supply1 1 ;< VPWR $end +$var supply0 1 << VGND $end +$var supply1 1 =< VPB $end +$var supply0 1 >< VNB $end + +$scope module base $end +$var wire 1 a$ Y $end +$var wire 1 0< A $end +$var wire 1 ?< not0_out_Y $end +$upscope $end +$upscope $end + +$scope module BINV_R_133 $end +$var wire 1 0< Y $end +$var wire 1 ,< A $end +$var supply1 1 @< VPWR $end +$var supply0 1 A< VGND $end +$var supply1 1 B< VPB $end +$var supply0 1 C< VNB $end + +$scope module base $end +$var wire 1 0< Y $end +$var wire 1 ,< A $end +$var wire 1 D< not0_out_Y $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mux_left_track_15 $end +$var wire 1 R# in [0] $end +$var wire 1 4$ in [1] $end +$var wire 1 /% sram [0] $end +$var wire 1 0% sram [1] $end +$var wire 1 q' sram_inv [0] $end +$var wire 1 r' sram_inv [1] $end +$var wire 1 b$ out [0] $end +$var wire 1 p' p0 $end +$var wire 1 E< mux_2level_tapbuf_basis_input2_mem1_0_out [0] $end +$var wire 1 F< mux_2level_tapbuf_basis_input2_mem1_1_out [0] $end +$var wire 1 G< SYNOPSYS_UNCONNECTED_1 $end +$var wire 1 H< SYNOPSYS_UNCONNECTED_2 $end +$var wire 1 I< SYNOPSYS_UNCONNECTED_3 $end +$var wire 1 J< BUF_net_135 $end + +$scope module mux_l1_in_0_ $end +$var wire 1 R# in [0] $end +$var wire 1 4$ in [1] $end +$var wire 1 /% mem [0] $end +$var wire 1 G< mem_inv [0] $end +$var wire 1 E< out [0] $end + +$scope module sky130_fd_sc_hd__mux2_1_0 $end +$var wire 1 E< X $end +$var wire 1 4$ A0 $end +$var wire 1 R# A1 $end +$var wire 1 /% S $end +$var supply1 1 K< VPWR $end +$var supply0 1 L< VGND $end +$var supply1 1 M< VPB $end +$var supply0 1 N< VNB $end + +$scope module base $end +$var wire 1 E< X $end +$var wire 1 4$ A0 $end +$var wire 1 R# A1 $end +$var wire 1 /% S $end +$var wire 1 O< mux_2to10_out_X $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mux_l2_in_0_ $end +$var wire 1 E< in [0] $end +$var wire 1 H< in [1] $end +$var wire 1 0% mem [0] $end +$var wire 1 I< mem_inv [0] $end +$var wire 1 F< out [0] $end +$var wire 1 p' p0 $end + +$scope module sky130_fd_sc_hd__mux2_1_0 $end +$var wire 1 F< X $end +$var wire 1 p' A0 $end +$var wire 1 E< A1 $end +$var wire 1 0% S $end +$var supply1 1 P< VPWR $end +$var supply0 1 Q< VGND $end +$var supply1 1 R< VPB $end +$var supply0 1 S< VNB $end + +$scope module base $end +$var wire 1 F< X $end +$var wire 1 p' A0 $end +$var wire 1 E< A1 $end +$var wire 1 0% S $end +$var wire 1 T< mux_2to10_out_X $end +$upscope $end +$upscope $end +$upscope $end + +$scope module BINV_R_134 $end +$var wire 1 b$ Y $end +$var wire 1 J< A $end +$var supply1 1 U< VPWR $end +$var supply0 1 V< VGND $end +$var supply1 1 W< VPB $end +$var supply0 1 X< VNB $end + +$scope module base $end +$var wire 1 b$ Y $end +$var wire 1 J< A $end +$var wire 1 Y< not0_out_Y $end +$upscope $end +$upscope $end + +$scope module BINV_R_135 $end +$var wire 1 J< Y $end +$var wire 1 F< A $end +$var supply1 1 Z< VPWR $end +$var supply0 1 [< VGND $end +$var supply1 1 \< VPB $end +$var supply0 1 ]< VNB $end + +$scope module base $end +$var wire 1 J< Y $end +$var wire 1 F< A $end +$var wire 1 ^< not0_out_Y $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mux_left_track_17 $end +$var wire 1 S# in [0] $end +$var wire 1 5$ in [1] $end +$var wire 1 1% sram [0] $end +$var wire 1 2% sram [1] $end +$var wire 1 s' sram_inv [0] $end +$var wire 1 t' sram_inv [1] $end +$var wire 1 c$ out [0] $end +$var wire 1 p' p0 $end +$var wire 1 _< mux_2level_tapbuf_basis_input2_mem1_0_out [0] $end +$var wire 1 `< mux_2level_tapbuf_basis_input2_mem1_1_out [0] $end +$var wire 1 a< SYNOPSYS_UNCONNECTED_1 $end +$var wire 1 b< SYNOPSYS_UNCONNECTED_2 $end +$var wire 1 c< SYNOPSYS_UNCONNECTED_3 $end +$var wire 1 d< BUF_net_137 $end + +$scope module mux_l1_in_0_ $end +$var wire 1 S# in [0] $end +$var wire 1 5$ in [1] $end +$var wire 1 1% mem [0] $end +$var wire 1 a< mem_inv [0] $end +$var wire 1 _< out [0] $end + +$scope module sky130_fd_sc_hd__mux2_1_0 $end +$var wire 1 _< X $end +$var wire 1 5$ A0 $end +$var wire 1 S# A1 $end +$var wire 1 1% S $end +$var supply1 1 e< VPWR $end +$var supply0 1 f< VGND $end +$var supply1 1 g< VPB $end +$var supply0 1 h< VNB $end + +$scope module base $end +$var wire 1 _< X $end +$var wire 1 5$ A0 $end +$var wire 1 S# A1 $end +$var wire 1 1% S $end +$var wire 1 i< mux_2to10_out_X $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mux_l2_in_0_ $end +$var wire 1 _< in [0] $end +$var wire 1 b< in [1] $end +$var wire 1 2% mem [0] $end +$var wire 1 c< mem_inv [0] $end +$var wire 1 `< out [0] $end +$var wire 1 p' p0 $end + +$scope module sky130_fd_sc_hd__mux2_1_0 $end +$var wire 1 `< X $end +$var wire 1 p' A0 $end +$var wire 1 _< A1 $end +$var wire 1 2% S $end +$var supply1 1 j< VPWR $end +$var supply0 1 k< VGND $end +$var supply1 1 l< VPB $end +$var supply0 1 m< VNB $end + +$scope module base $end +$var wire 1 `< X $end +$var wire 1 p' A0 $end +$var wire 1 _< A1 $end +$var wire 1 2% S $end +$var wire 1 n< mux_2to10_out_X $end +$upscope $end +$upscope $end +$upscope $end + +$scope module BINV_R_136 $end +$var wire 1 c$ Y $end +$var wire 1 d< A $end +$var supply1 1 o< VPWR $end +$var supply0 1 p< VGND $end +$var supply1 1 q< VPB $end +$var supply0 1 r< VNB $end + +$scope module base $end +$var wire 1 c$ Y $end +$var wire 1 d< A $end +$var wire 1 s< not0_out_Y $end +$upscope $end +$upscope $end + +$scope module BINV_R_137 $end +$var wire 1 d< Y $end +$var wire 1 `< A $end +$var supply1 1 t< VPWR $end +$var supply0 1 u< VGND $end +$var supply1 1 v< VPB $end +$var supply0 1 w< VNB $end + +$scope module base $end +$var wire 1 d< Y $end +$var wire 1 `< A $end +$var wire 1 x< not0_out_Y $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mux_left_track_19 $end +$var wire 1 T# in [0] $end +$var wire 1 6$ in [1] $end +$var wire 1 3% sram [0] $end +$var wire 1 4% sram [1] $end +$var wire 1 u' sram_inv [0] $end +$var wire 1 v' sram_inv [1] $end +$var wire 1 d$ out [0] $end +$var wire 1 p' p0 $end +$var wire 1 y< mux_2level_tapbuf_basis_input2_mem1_0_out [0] $end +$var wire 1 z< mux_2level_tapbuf_basis_input2_mem1_1_out [0] $end +$var wire 1 {< SYNOPSYS_UNCONNECTED_1 $end +$var wire 1 |< SYNOPSYS_UNCONNECTED_2 $end +$var wire 1 }< SYNOPSYS_UNCONNECTED_3 $end +$var wire 1 ~< BUF_net_139 $end + +$scope module mux_l1_in_0_ $end +$var wire 1 T# in [0] $end +$var wire 1 6$ in [1] $end +$var wire 1 3% mem [0] $end +$var wire 1 {< mem_inv [0] $end +$var wire 1 y< out [0] $end + +$scope module sky130_fd_sc_hd__mux2_1_0 $end +$var wire 1 y< X $end +$var wire 1 6$ A0 $end +$var wire 1 T# A1 $end +$var wire 1 3% S $end +$var supply1 1 != VPWR $end +$var supply0 1 "= VGND $end +$var supply1 1 #= VPB $end +$var supply0 1 $= VNB $end + +$scope module base $end +$var wire 1 y< X $end +$var wire 1 6$ A0 $end +$var wire 1 T# A1 $end +$var wire 1 3% S $end +$var wire 1 %= mux_2to10_out_X $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mux_l2_in_0_ $end +$var wire 1 y< in [0] $end +$var wire 1 |< in [1] $end +$var wire 1 4% mem [0] $end +$var wire 1 }< mem_inv [0] $end +$var wire 1 z< out [0] $end +$var wire 1 p' p0 $end + +$scope module sky130_fd_sc_hd__mux2_1_0 $end +$var wire 1 z< X $end +$var wire 1 p' A0 $end +$var wire 1 y< A1 $end +$var wire 1 4% S $end +$var supply1 1 &= VPWR $end +$var supply0 1 '= VGND $end +$var supply1 1 (= VPB $end +$var supply0 1 )= VNB $end + +$scope module base $end +$var wire 1 z< X $end +$var wire 1 p' A0 $end +$var wire 1 y< A1 $end +$var wire 1 4% S $end +$var wire 1 *= mux_2to10_out_X $end +$upscope $end +$upscope $end +$upscope $end + +$scope module BINV_R_138 $end +$var wire 1 d$ Y $end +$var wire 1 ~< A $end +$var supply1 1 += VPWR $end +$var supply0 1 ,= VGND $end +$var supply1 1 -= VPB $end +$var supply0 1 .= VNB $end + +$scope module base $end +$var wire 1 d$ Y $end +$var wire 1 ~< A $end +$var wire 1 /= not0_out_Y $end +$upscope $end +$upscope $end + +$scope module BINV_R_139 $end +$var wire 1 ~< Y $end +$var wire 1 z< A $end +$var supply1 1 0= VPWR $end +$var supply0 1 1= VGND $end +$var supply1 1 2= VPB $end +$var supply0 1 3= VNB $end + +$scope module base $end +$var wire 1 ~< Y $end +$var wire 1 z< A $end +$var wire 1 4= not0_out_Y $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mux_left_track_21 $end +$var wire 1 U# in [0] $end +$var wire 1 7$ in [1] $end +$var wire 1 5% sram [0] $end +$var wire 1 6% sram [1] $end +$var wire 1 w' sram_inv [0] $end +$var wire 1 x' sram_inv [1] $end +$var wire 1 e$ out [0] $end +$var wire 1 R' p0 $end +$var wire 1 5= mux_2level_tapbuf_basis_input2_mem1_0_out [0] $end +$var wire 1 6= mux_2level_tapbuf_basis_input2_mem1_1_out [0] $end +$var wire 1 7= SYNOPSYS_UNCONNECTED_1 $end +$var wire 1 8= SYNOPSYS_UNCONNECTED_2 $end +$var wire 1 9= SYNOPSYS_UNCONNECTED_3 $end +$var wire 1 := BUF_net_141 $end + +$scope module mux_l1_in_0_ $end +$var wire 1 U# in [0] $end +$var wire 1 7$ in [1] $end +$var wire 1 5% mem [0] $end +$var wire 1 7= mem_inv [0] $end +$var wire 1 5= out [0] $end + +$scope module sky130_fd_sc_hd__mux2_1_0 $end +$var wire 1 5= X $end +$var wire 1 7$ A0 $end +$var wire 1 U# A1 $end +$var wire 1 5% S $end +$var supply1 1 ;= VPWR $end +$var supply0 1 <= VGND $end +$var supply1 1 == VPB $end +$var supply0 1 >= VNB $end + +$scope module base $end +$var wire 1 5= X $end +$var wire 1 7$ A0 $end +$var wire 1 U# A1 $end +$var wire 1 5% S $end +$var wire 1 ?= mux_2to10_out_X $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mux_l2_in_0_ $end +$var wire 1 5= in [0] $end +$var wire 1 8= in [1] $end +$var wire 1 6% mem [0] $end +$var wire 1 9= mem_inv [0] $end +$var wire 1 6= out [0] $end +$var wire 1 R' p0 $end + +$scope module sky130_fd_sc_hd__mux2_1_0 $end +$var wire 1 6= X $end +$var wire 1 R' A0 $end +$var wire 1 5= A1 $end +$var wire 1 6% S $end +$var supply1 1 @= VPWR $end +$var supply0 1 A= VGND $end +$var supply1 1 B= VPB $end +$var supply0 1 C= VNB $end + +$scope module base $end +$var wire 1 6= X $end +$var wire 1 R' A0 $end +$var wire 1 5= A1 $end +$var wire 1 6% S $end +$var wire 1 D= mux_2to10_out_X $end +$upscope $end +$upscope $end +$upscope $end + +$scope module BINV_R_140 $end +$var wire 1 e$ Y $end +$var wire 1 := A $end +$var supply1 1 E= VPWR $end +$var supply0 1 F= VGND $end +$var supply1 1 G= VPB $end +$var supply0 1 H= VNB $end + +$scope module base $end +$var wire 1 e$ Y $end +$var wire 1 := A $end +$var wire 1 I= not0_out_Y $end +$upscope $end +$upscope $end + +$scope module BINV_R_141 $end +$var wire 1 := Y $end +$var wire 1 6= A $end +$var supply1 1 J= VPWR $end +$var supply0 1 K= VGND $end +$var supply1 1 L= VPB $end +$var supply0 1 M= VNB $end + +$scope module base $end +$var wire 1 := Y $end +$var wire 1 6= A $end +$var wire 1 N= not0_out_Y $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mux_left_track_23 $end +$var wire 1 V# in [0] $end +$var wire 1 8$ in [1] $end +$var wire 1 9% sram [0] $end +$var wire 1 :% sram [1] $end +$var wire 1 y' sram_inv [0] $end +$var wire 1 z' sram_inv [1] $end +$var wire 1 f$ out [0] $end +$var wire 1 R' p0 $end +$var wire 1 O= mux_2level_tapbuf_basis_input2_mem1_0_out [0] $end +$var wire 1 P= mux_2level_tapbuf_basis_input2_mem1_1_out [0] $end +$var wire 1 Q= SYNOPSYS_UNCONNECTED_1 $end +$var wire 1 R= SYNOPSYS_UNCONNECTED_2 $end +$var wire 1 S= SYNOPSYS_UNCONNECTED_3 $end + +$scope module sky130_fd_sc_hd__buf_4_0_ $end +$var wire 1 f$ X $end +$var wire 1 P= A $end +$var supply1 1 T= VPWR $end +$var supply0 1 U= VGND $end +$var supply1 1 V= VPB $end +$var supply0 1 W= VNB $end + +$scope module base $end +$var wire 1 f$ X $end +$var wire 1 P= A $end +$var wire 1 X= buf0_out_X $end +$upscope $end +$upscope $end + +$scope module mux_l1_in_0_ $end +$var wire 1 V# in [0] $end +$var wire 1 8$ in [1] $end +$var wire 1 9% mem [0] $end +$var wire 1 Q= mem_inv [0] $end +$var wire 1 O= out [0] $end + +$scope module sky130_fd_sc_hd__mux2_1_0 $end +$var wire 1 O= X $end +$var wire 1 8$ A0 $end +$var wire 1 V# A1 $end +$var wire 1 9% S $end +$var supply1 1 Y= VPWR $end +$var supply0 1 Z= VGND $end +$var supply1 1 [= VPB $end +$var supply0 1 \= VNB $end + +$scope module base $end +$var wire 1 O= X $end +$var wire 1 8$ A0 $end +$var wire 1 V# A1 $end +$var wire 1 9% S $end +$var wire 1 ]= mux_2to10_out_X $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mux_l2_in_0_ $end +$var wire 1 O= in [0] $end +$var wire 1 R= in [1] $end +$var wire 1 :% mem [0] $end +$var wire 1 S= mem_inv [0] $end +$var wire 1 P= out [0] $end +$var wire 1 R' p0 $end + +$scope module sky130_fd_sc_hd__mux2_1_0 $end +$var wire 1 P= X $end +$var wire 1 R' A0 $end +$var wire 1 O= A1 $end +$var wire 1 :% S $end +$var supply1 1 ^= VPWR $end +$var supply0 1 _= VGND $end +$var supply1 1 `= VPB $end +$var supply0 1 a= VNB $end + +$scope module base $end +$var wire 1 P= X $end +$var wire 1 R' A0 $end +$var wire 1 O= A1 $end +$var wire 1 :% S $end +$var wire 1 b= mux_2to10_out_X $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mux_left_track_25 $end +$var wire 1 W# in [0] $end +$var wire 1 9$ in [1] $end +$var wire 1 ;% sram [0] $end +$var wire 1 <% sram [1] $end +$var wire 1 {' sram_inv [0] $end +$var wire 1 |' sram_inv [1] $end +$var wire 1 g$ out [0] $end +$var wire 1 R' p0 $end +$var wire 1 c= mux_2level_tapbuf_basis_input2_mem1_0_out [0] $end +$var wire 1 d= mux_2level_tapbuf_basis_input2_mem1_1_out [0] $end +$var wire 1 e= SYNOPSYS_UNCONNECTED_1 $end +$var wire 1 f= SYNOPSYS_UNCONNECTED_2 $end +$var wire 1 g= SYNOPSYS_UNCONNECTED_3 $end +$var wire 1 h= BUF_net_143 $end + +$scope module mux_l1_in_0_ $end +$var wire 1 W# in [0] $end +$var wire 1 9$ in [1] $end +$var wire 1 ;% mem [0] $end +$var wire 1 e= mem_inv [0] $end +$var wire 1 c= out [0] $end + +$scope module sky130_fd_sc_hd__mux2_1_0 $end +$var wire 1 c= X $end +$var wire 1 9$ A0 $end +$var wire 1 W# A1 $end +$var wire 1 ;% S $end +$var supply1 1 i= VPWR $end +$var supply0 1 j= VGND $end +$var supply1 1 k= VPB $end +$var supply0 1 l= VNB $end + +$scope module base $end +$var wire 1 c= X $end +$var wire 1 9$ A0 $end +$var wire 1 W# A1 $end +$var wire 1 ;% S $end +$var wire 1 m= mux_2to10_out_X $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mux_l2_in_0_ $end +$var wire 1 c= in [0] $end +$var wire 1 f= in [1] $end +$var wire 1 <% mem [0] $end +$var wire 1 g= mem_inv [0] $end +$var wire 1 d= out [0] $end +$var wire 1 R' p0 $end + +$scope module sky130_fd_sc_hd__mux2_1_0 $end +$var wire 1 d= X $end +$var wire 1 R' A0 $end +$var wire 1 c= A1 $end +$var wire 1 <% S $end +$var supply1 1 n= VPWR $end +$var supply0 1 o= VGND $end +$var supply1 1 p= VPB $end +$var supply0 1 q= VNB $end + +$scope module base $end +$var wire 1 d= X $end +$var wire 1 R' A0 $end +$var wire 1 c= A1 $end +$var wire 1 <% S $end +$var wire 1 r= mux_2to10_out_X $end +$upscope $end +$upscope $end +$upscope $end + +$scope module BINV_R_142 $end +$var wire 1 g$ Y $end +$var wire 1 h= A $end +$var supply1 1 s= VPWR $end +$var supply0 1 t= VGND $end +$var supply1 1 u= VPB $end +$var supply0 1 v= VNB $end + +$scope module base $end +$var wire 1 g$ Y $end +$var wire 1 h= A $end +$var wire 1 w= not0_out_Y $end +$upscope $end +$upscope $end + +$scope module BINV_R_143 $end +$var wire 1 h= Y $end +$var wire 1 d= A $end +$var supply1 1 x= VPWR $end +$var supply0 1 y= VGND $end +$var supply1 1 z= VPB $end +$var supply0 1 {= VNB $end + +$scope module base $end +$var wire 1 h= Y $end +$var wire 1 d= A $end +$var wire 1 |= not0_out_Y $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mux_left_track_27 $end +$var wire 1 X# in [0] $end +$var wire 1 :$ in [1] $end +$var wire 1 =% sram [0] $end +$var wire 1 >% sram [1] $end +$var wire 1 }' sram_inv [0] $end +$var wire 1 ~' sram_inv [1] $end +$var wire 1 h$ out [0] $end +$var wire 1 R' p0 $end +$var wire 1 }= mux_2level_tapbuf_basis_input2_mem1_0_out [0] $end +$var wire 1 ~= mux_2level_tapbuf_basis_input2_mem1_1_out [0] $end +$var wire 1 !> SYNOPSYS_UNCONNECTED_1 $end +$var wire 1 "> SYNOPSYS_UNCONNECTED_2 $end +$var wire 1 #> SYNOPSYS_UNCONNECTED_3 $end + +$scope module sky130_fd_sc_hd__buf_4_0_ $end +$var wire 1 h$ X $end +$var wire 1 ~= A $end +$var supply1 1 $> VPWR $end +$var supply0 1 %> VGND $end +$var supply1 1 &> VPB $end +$var supply0 1 '> VNB $end + +$scope module base $end +$var wire 1 h$ X $end +$var wire 1 ~= A $end +$var wire 1 (> buf0_out_X $end +$upscope $end +$upscope $end + +$scope module mux_l1_in_0_ $end +$var wire 1 X# in [0] $end +$var wire 1 :$ in [1] $end +$var wire 1 =% mem [0] $end +$var wire 1 !> mem_inv [0] $end +$var wire 1 }= out [0] $end + +$scope module sky130_fd_sc_hd__mux2_1_0 $end +$var wire 1 }= X $end +$var wire 1 :$ A0 $end +$var wire 1 X# A1 $end +$var wire 1 =% S $end +$var supply1 1 )> VPWR $end +$var supply0 1 *> VGND $end +$var supply1 1 +> VPB $end +$var supply0 1 ,> VNB $end + +$scope module base $end +$var wire 1 }= X $end +$var wire 1 :$ A0 $end +$var wire 1 X# A1 $end +$var wire 1 =% S $end +$var wire 1 -> mux_2to10_out_X $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mux_l2_in_0_ $end +$var wire 1 }= in [0] $end +$var wire 1 "> in [1] $end +$var wire 1 >% mem [0] $end +$var wire 1 #> mem_inv [0] $end +$var wire 1 ~= out [0] $end +$var wire 1 R' p0 $end + +$scope module sky130_fd_sc_hd__mux2_1_0 $end +$var wire 1 ~= X $end +$var wire 1 R' A0 $end +$var wire 1 }= A1 $end +$var wire 1 >% S $end +$var supply1 1 .> VPWR $end +$var supply0 1 /> VGND $end +$var supply1 1 0> VPB $end +$var supply0 1 1> VNB $end + +$scope module base $end +$var wire 1 ~= X $end +$var wire 1 R' A0 $end +$var wire 1 }= A1 $end +$var wire 1 >% S $end +$var wire 1 2> mux_2to10_out_X $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mux_left_track_31 $end +$var wire 1 Z# in [0] $end +$var wire 1 4$ in [1] $end +$var wire 1 ?% sram [0] $end +$var wire 1 @% sram [1] $end +$var wire 1 !( sram_inv [0] $end +$var wire 1 "( sram_inv [1] $end +$var wire 1 j$ out [0] $end +$var wire 1 p' p0 $end +$var wire 1 3> mux_2level_tapbuf_basis_input2_mem1_0_out [0] $end +$var wire 1 4> mux_2level_tapbuf_basis_input2_mem1_1_out [0] $end +$var wire 1 5> SYNOPSYS_UNCONNECTED_1 $end +$var wire 1 6> SYNOPSYS_UNCONNECTED_2 $end +$var wire 1 7> SYNOPSYS_UNCONNECTED_3 $end +$var wire 1 8> BUF_net_145 $end + +$scope module mux_l1_in_0_ $end +$var wire 1 Z# in [0] $end +$var wire 1 4$ in [1] $end +$var wire 1 ?% mem [0] $end +$var wire 1 5> mem_inv [0] $end +$var wire 1 3> out [0] $end + +$scope module sky130_fd_sc_hd__mux2_1_0 $end +$var wire 1 3> X $end +$var wire 1 4$ A0 $end +$var wire 1 Z# A1 $end +$var wire 1 ?% S $end +$var supply1 1 9> VPWR $end +$var supply0 1 :> VGND $end +$var supply1 1 ;> VPB $end +$var supply0 1 <> VNB $end + +$scope module base $end +$var wire 1 3> X $end +$var wire 1 4$ A0 $end +$var wire 1 Z# A1 $end +$var wire 1 ?% S $end +$var wire 1 => mux_2to10_out_X $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mux_l2_in_0_ $end +$var wire 1 3> in [0] $end +$var wire 1 6> in [1] $end +$var wire 1 @% mem [0] $end +$var wire 1 7> mem_inv [0] $end +$var wire 1 4> out [0] $end +$var wire 1 p' p0 $end + +$scope module sky130_fd_sc_hd__mux2_1_0 $end +$var wire 1 4> X $end +$var wire 1 p' A0 $end +$var wire 1 3> A1 $end +$var wire 1 @% S $end +$var supply1 1 >> VPWR $end +$var supply0 1 ?> VGND $end +$var supply1 1 @> VPB $end +$var supply0 1 A> VNB $end + +$scope module base $end +$var wire 1 4> X $end +$var wire 1 p' A0 $end +$var wire 1 3> A1 $end +$var wire 1 @% S $end +$var wire 1 B> mux_2to10_out_X $end +$upscope $end +$upscope $end +$upscope $end + +$scope module BINV_R_144 $end +$var wire 1 j$ Y $end +$var wire 1 8> A $end +$var supply1 1 C> VPWR $end +$var supply0 1 D> VGND $end +$var supply1 1 E> VPB $end +$var supply0 1 F> VNB $end + +$scope module base $end +$var wire 1 j$ Y $end +$var wire 1 8> A $end +$var wire 1 G> not0_out_Y $end +$upscope $end +$upscope $end + +$scope module BINV_R_145 $end +$var wire 1 8> Y $end +$var wire 1 4> A $end +$var supply1 1 H> VPWR $end +$var supply0 1 I> VGND $end +$var supply1 1 J> VPB $end +$var supply0 1 K> VNB $end + +$scope module base $end +$var wire 1 8> Y $end +$var wire 1 4> A $end +$var wire 1 L> not0_out_Y $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mux_left_track_33 $end +$var wire 1 [# in [0] $end +$var wire 1 5$ in [1] $end +$var wire 1 A% sram [0] $end +$var wire 1 B% sram [1] $end +$var wire 1 #( sram_inv [0] $end +$var wire 1 $( sram_inv [1] $end +$var wire 1 k$ out [0] $end +$var wire 1 p' p0 $end +$var wire 1 M> mux_2level_tapbuf_basis_input2_mem1_0_out [0] $end +$var wire 1 N> mux_2level_tapbuf_basis_input2_mem1_1_out [0] $end +$var wire 1 O> SYNOPSYS_UNCONNECTED_1 $end +$var wire 1 P> SYNOPSYS_UNCONNECTED_2 $end +$var wire 1 Q> SYNOPSYS_UNCONNECTED_3 $end +$var wire 1 R> BUF_net_147 $end + +$scope module mux_l1_in_0_ $end +$var wire 1 [# in [0] $end +$var wire 1 5$ in [1] $end +$var wire 1 A% mem [0] $end +$var wire 1 O> mem_inv [0] $end +$var wire 1 M> out [0] $end + +$scope module sky130_fd_sc_hd__mux2_1_0 $end +$var wire 1 M> X $end +$var wire 1 5$ A0 $end +$var wire 1 [# A1 $end +$var wire 1 A% S $end +$var supply1 1 S> VPWR $end +$var supply0 1 T> VGND $end +$var supply1 1 U> VPB $end +$var supply0 1 V> VNB $end + +$scope module base $end +$var wire 1 M> X $end +$var wire 1 5$ A0 $end +$var wire 1 [# A1 $end +$var wire 1 A% S $end +$var wire 1 W> mux_2to10_out_X $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mux_l2_in_0_ $end +$var wire 1 M> in [0] $end +$var wire 1 P> in [1] $end +$var wire 1 B% mem [0] $end +$var wire 1 Q> mem_inv [0] $end +$var wire 1 N> out [0] $end +$var wire 1 p' p0 $end + +$scope module sky130_fd_sc_hd__mux2_1_0 $end +$var wire 1 N> X $end +$var wire 1 p' A0 $end +$var wire 1 M> A1 $end +$var wire 1 B% S $end +$var supply1 1 X> VPWR $end +$var supply0 1 Y> VGND $end +$var supply1 1 Z> VPB $end +$var supply0 1 [> VNB $end + +$scope module base $end +$var wire 1 N> X $end +$var wire 1 p' A0 $end +$var wire 1 M> A1 $end +$var wire 1 B% S $end +$var wire 1 \> mux_2to10_out_X $end +$upscope $end +$upscope $end +$upscope $end + +$scope module BINV_R_146 $end +$var wire 1 k$ Y $end +$var wire 1 R> A $end +$var supply1 1 ]> VPWR $end +$var supply0 1 ^> VGND $end +$var supply1 1 _> VPB $end +$var supply0 1 `> VNB $end + +$scope module base $end +$var wire 1 k$ Y $end +$var wire 1 R> A $end +$var wire 1 a> not0_out_Y $end +$upscope $end +$upscope $end + +$scope module BINV_R_147 $end +$var wire 1 R> Y $end +$var wire 1 N> A $end +$var supply1 1 b> VPWR $end +$var supply0 1 c> VGND $end +$var supply1 1 d> VPB $end +$var supply0 1 e> VNB $end + +$scope module base $end +$var wire 1 R> Y $end +$var wire 1 N> A $end +$var wire 1 f> not0_out_Y $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mux_left_track_35 $end +$var wire 1 \# in [0] $end +$var wire 1 6$ in [1] $end +$var wire 1 C% sram [0] $end +$var wire 1 D% sram [1] $end +$var wire 1 %( sram_inv [0] $end +$var wire 1 &( sram_inv [1] $end +$var wire 1 l$ out [0] $end +$var wire 1 p' p0 $end +$var wire 1 g> mux_2level_tapbuf_basis_input2_mem1_0_out [0] $end +$var wire 1 h> mux_2level_tapbuf_basis_input2_mem1_1_out [0] $end +$var wire 1 i> SYNOPSYS_UNCONNECTED_1 $end +$var wire 1 j> SYNOPSYS_UNCONNECTED_2 $end +$var wire 1 k> SYNOPSYS_UNCONNECTED_3 $end +$var wire 1 l> BUF_net_149 $end + +$scope module mux_l1_in_0_ $end +$var wire 1 \# in [0] $end +$var wire 1 6$ in [1] $end +$var wire 1 C% mem [0] $end +$var wire 1 i> mem_inv [0] $end +$var wire 1 g> out [0] $end + +$scope module sky130_fd_sc_hd__mux2_1_0 $end +$var wire 1 g> X $end +$var wire 1 6$ A0 $end +$var wire 1 \# A1 $end +$var wire 1 C% S $end +$var supply1 1 m> VPWR $end +$var supply0 1 n> VGND $end +$var supply1 1 o> VPB $end +$var supply0 1 p> VNB $end + +$scope module base $end +$var wire 1 g> X $end +$var wire 1 6$ A0 $end +$var wire 1 \# A1 $end +$var wire 1 C% S $end +$var wire 1 q> mux_2to10_out_X $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mux_l2_in_0_ $end +$var wire 1 g> in [0] $end +$var wire 1 j> in [1] $end +$var wire 1 D% mem [0] $end +$var wire 1 k> mem_inv [0] $end +$var wire 1 h> out [0] $end +$var wire 1 p' p0 $end + +$scope module sky130_fd_sc_hd__mux2_1_0 $end +$var wire 1 h> X $end +$var wire 1 p' A0 $end +$var wire 1 g> A1 $end +$var wire 1 D% S $end +$var supply1 1 r> VPWR $end +$var supply0 1 s> VGND $end +$var supply1 1 t> VPB $end +$var supply0 1 u> VNB $end + +$scope module base $end +$var wire 1 h> X $end +$var wire 1 p' A0 $end +$var wire 1 g> A1 $end +$var wire 1 D% S $end +$var wire 1 v> mux_2to10_out_X $end +$upscope $end +$upscope $end +$upscope $end + +$scope module BINV_R_148 $end +$var wire 1 l$ Y $end +$var wire 1 l> A $end +$var supply1 1 w> VPWR $end +$var supply0 1 x> VGND $end +$var supply1 1 y> VPB $end +$var supply0 1 z> VNB $end + +$scope module base $end +$var wire 1 l$ Y $end +$var wire 1 l> A $end +$var wire 1 {> not0_out_Y $end +$upscope $end +$upscope $end + +$scope module BINV_R_149 $end +$var wire 1 l> Y $end +$var wire 1 h> A $end +$var supply1 1 |> VPWR $end +$var supply0 1 }> VGND $end +$var supply1 1 ~> VPB $end +$var supply0 1 !? VNB $end + +$scope module base $end +$var wire 1 l> Y $end +$var wire 1 h> A $end +$var wire 1 "? not0_out_Y $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mux_left_track_37 $end +$var wire 1 ]# in [0] $end +$var wire 1 7$ in [1] $end +$var wire 1 E% sram [0] $end +$var wire 1 F% sram [1] $end +$var wire 1 '( sram_inv [0] $end +$var wire 1 (( sram_inv [1] $end +$var wire 1 m$ out [0] $end +$var wire 1 p' p0 $end +$var wire 1 #? mux_2level_tapbuf_basis_input2_mem1_0_out [0] $end +$var wire 1 $? mux_2level_tapbuf_basis_input2_mem1_1_out [0] $end +$var wire 1 %? SYNOPSYS_UNCONNECTED_1 $end +$var wire 1 &? SYNOPSYS_UNCONNECTED_2 $end +$var wire 1 '? SYNOPSYS_UNCONNECTED_3 $end +$var wire 1 (? BUF_net_151 $end + +$scope module mux_l1_in_0_ $end +$var wire 1 ]# in [0] $end +$var wire 1 7$ in [1] $end +$var wire 1 E% mem [0] $end +$var wire 1 %? mem_inv [0] $end +$var wire 1 #? out [0] $end + +$scope module sky130_fd_sc_hd__mux2_1_0 $end +$var wire 1 #? X $end +$var wire 1 7$ A0 $end +$var wire 1 ]# A1 $end +$var wire 1 E% S $end +$var supply1 1 )? VPWR $end +$var supply0 1 *? VGND $end +$var supply1 1 +? VPB $end +$var supply0 1 ,? VNB $end + +$scope module base $end +$var wire 1 #? X $end +$var wire 1 7$ A0 $end +$var wire 1 ]# A1 $end +$var wire 1 E% S $end +$var wire 1 -? mux_2to10_out_X $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mux_l2_in_0_ $end +$var wire 1 #? in [0] $end +$var wire 1 &? in [1] $end +$var wire 1 F% mem [0] $end +$var wire 1 '? mem_inv [0] $end +$var wire 1 $? out [0] $end +$var wire 1 p' p0 $end + +$scope module sky130_fd_sc_hd__mux2_1_0 $end +$var wire 1 $? X $end +$var wire 1 p' A0 $end +$var wire 1 #? A1 $end +$var wire 1 F% S $end +$var supply1 1 .? VPWR $end +$var supply0 1 /? VGND $end +$var supply1 1 0? VPB $end +$var supply0 1 1? VNB $end + +$scope module base $end +$var wire 1 $? X $end +$var wire 1 p' A0 $end +$var wire 1 #? A1 $end +$var wire 1 F% S $end +$var wire 1 2? mux_2to10_out_X $end +$upscope $end +$upscope $end +$upscope $end + +$scope module BINV_R_150 $end +$var wire 1 m$ Y $end +$var wire 1 (? A $end +$var supply1 1 3? VPWR $end +$var supply0 1 4? VGND $end +$var supply1 1 5? VPB $end +$var supply0 1 6? VNB $end + +$scope module base $end +$var wire 1 m$ Y $end +$var wire 1 (? A $end +$var wire 1 7? not0_out_Y $end +$upscope $end +$upscope $end + +$scope module BINV_R_151 $end +$var wire 1 (? Y $end +$var wire 1 $? A $end +$var supply1 1 8? VPWR $end +$var supply0 1 9? VGND $end +$var supply1 1 :? VPB $end +$var supply0 1 ;? VNB $end + +$scope module base $end +$var wire 1 (? Y $end +$var wire 1 $? A $end +$var wire 1 ? mux_2level_tapbuf_basis_input2_mem1_1_out [0] $end +$var wire 1 ?? SYNOPSYS_UNCONNECTED_1 $end +$var wire 1 @? SYNOPSYS_UNCONNECTED_2 $end +$var wire 1 A? SYNOPSYS_UNCONNECTED_3 $end +$var wire 1 B? BUF_net_153 $end + +$scope module mux_l1_in_0_ $end +$var wire 1 ^# in [0] $end +$var wire 1 8$ in [1] $end +$var wire 1 G% mem [0] $end +$var wire 1 ?? mem_inv [0] $end +$var wire 1 =? out [0] $end + +$scope module sky130_fd_sc_hd__mux2_1_0 $end +$var wire 1 =? X $end +$var wire 1 8$ A0 $end +$var wire 1 ^# A1 $end +$var wire 1 G% S $end +$var supply1 1 C? VPWR $end +$var supply0 1 D? VGND $end +$var supply1 1 E? VPB $end +$var supply0 1 F? VNB $end + +$scope module base $end +$var wire 1 =? X $end +$var wire 1 8$ A0 $end +$var wire 1 ^# A1 $end +$var wire 1 G% S $end +$var wire 1 G? mux_2to10_out_X $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mux_l2_in_0_ $end +$var wire 1 =? in [0] $end +$var wire 1 @? in [1] $end +$var wire 1 H% mem [0] $end +$var wire 1 A? mem_inv [0] $end +$var wire 1 >? out [0] $end +$var wire 1 p' p0 $end + +$scope module sky130_fd_sc_hd__mux2_1_0 $end +$var wire 1 >? X $end +$var wire 1 p' A0 $end +$var wire 1 =? A1 $end +$var wire 1 H% S $end +$var supply1 1 H? VPWR $end +$var supply0 1 I? VGND $end +$var supply1 1 J? VPB $end +$var supply0 1 K? VNB $end + +$scope module base $end +$var wire 1 >? X $end +$var wire 1 p' A0 $end +$var wire 1 =? A1 $end +$var wire 1 H% S $end +$var wire 1 L? mux_2to10_out_X $end +$upscope $end +$upscope $end +$upscope $end + +$scope module BINV_R_152 $end +$var wire 1 n$ Y $end +$var wire 1 B? A $end +$var supply1 1 M? VPWR $end +$var supply0 1 N? VGND $end +$var supply1 1 O? VPB $end +$var supply0 1 P? VNB $end + +$scope module base $end +$var wire 1 n$ Y $end +$var wire 1 B? A $end +$var wire 1 Q? not0_out_Y $end +$upscope $end +$upscope $end + +$scope module BINV_R_153 $end +$var wire 1 B? Y $end +$var wire 1 >? A $end +$var supply1 1 R? VPWR $end +$var supply0 1 S? VGND $end +$var supply1 1 T? VPB $end +$var supply0 1 U? VNB $end + +$scope module base $end +$var wire 1 B? Y $end +$var wire 1 >? A $end +$var wire 1 V? not0_out_Y $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mux_left_track_41 $end +$var wire 1 _# in [0] $end +$var wire 1 9$ in [1] $end +$var wire 1 I% sram [0] $end +$var wire 1 J% sram [1] $end +$var wire 1 +( sram_inv [0] $end +$var wire 1 ,( sram_inv [1] $end +$var wire 1 o$ out [0] $end +$var wire 1 p' p0 $end +$var wire 1 W? mux_2level_tapbuf_basis_input2_mem1_0_out [0] $end +$var wire 1 X? mux_2level_tapbuf_basis_input2_mem1_1_out [0] $end +$var wire 1 Y? SYNOPSYS_UNCONNECTED_1 $end +$var wire 1 Z? SYNOPSYS_UNCONNECTED_2 $end +$var wire 1 [? SYNOPSYS_UNCONNECTED_3 $end +$var wire 1 \? BUF_net_155 $end + +$scope module mux_l1_in_0_ $end +$var wire 1 _# in [0] $end +$var wire 1 9$ in [1] $end +$var wire 1 I% mem [0] $end +$var wire 1 Y? mem_inv [0] $end +$var wire 1 W? out [0] $end + +$scope module sky130_fd_sc_hd__mux2_1_0 $end +$var wire 1 W? X $end +$var wire 1 9$ A0 $end +$var wire 1 _# A1 $end +$var wire 1 I% S $end +$var supply1 1 ]? VPWR $end +$var supply0 1 ^? VGND $end +$var supply1 1 _? VPB $end +$var supply0 1 `? VNB $end + +$scope module base $end +$var wire 1 W? X $end +$var wire 1 9$ A0 $end +$var wire 1 _# A1 $end +$var wire 1 I% S $end +$var wire 1 a? mux_2to10_out_X $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mux_l2_in_0_ $end +$var wire 1 W? in [0] $end +$var wire 1 Z? in [1] $end +$var wire 1 J% mem [0] $end +$var wire 1 [? mem_inv [0] $end +$var wire 1 X? out [0] $end +$var wire 1 p' p0 $end + +$scope module sky130_fd_sc_hd__mux2_1_0 $end +$var wire 1 X? X $end +$var wire 1 p' A0 $end +$var wire 1 W? A1 $end +$var wire 1 J% S $end +$var supply1 1 b? VPWR $end +$var supply0 1 c? VGND $end +$var supply1 1 d? VPB $end +$var supply0 1 e? VNB $end + +$scope module base $end +$var wire 1 X? X $end +$var wire 1 p' A0 $end +$var wire 1 W? A1 $end +$var wire 1 J% S $end +$var wire 1 f? mux_2to10_out_X $end +$upscope $end +$upscope $end +$upscope $end + +$scope module BINV_R_154 $end +$var wire 1 o$ Y $end +$var wire 1 \? A $end +$var supply1 1 g? VPWR $end +$var supply0 1 h? VGND $end +$var supply1 1 i? VPB $end +$var supply0 1 j? VNB $end + +$scope module base $end +$var wire 1 o$ Y $end +$var wire 1 \? A $end +$var wire 1 k? not0_out_Y $end +$upscope $end +$upscope $end + +$scope module BINV_R_155 $end +$var wire 1 \? Y $end +$var wire 1 X? A $end +$var supply1 1 l? VPWR $end +$var supply0 1 m? VGND $end +$var supply1 1 n? VPB $end +$var supply0 1 o? VNB $end + +$scope module base $end +$var wire 1 \? Y $end +$var wire 1 X? A $end +$var wire 1 p? not0_out_Y $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mux_left_track_43 $end +$var wire 1 `# in [0] $end +$var wire 1 :$ in [1] $end +$var wire 1 K% sram [0] $end +$var wire 1 L% sram [1] $end +$var wire 1 -( sram_inv [0] $end +$var wire 1 .( sram_inv [1] $end +$var wire 1 p$ out [0] $end +$var wire 1 p' p0 $end +$var wire 1 q? mux_2level_tapbuf_basis_input2_mem1_0_out [0] $end +$var wire 1 r? mux_2level_tapbuf_basis_input2_mem1_1_out [0] $end +$var wire 1 s? SYNOPSYS_UNCONNECTED_1 $end +$var wire 1 t? SYNOPSYS_UNCONNECTED_2 $end +$var wire 1 u? SYNOPSYS_UNCONNECTED_3 $end +$var wire 1 v? BUF_net_157 $end + +$scope module mux_l1_in_0_ $end +$var wire 1 `# in [0] $end +$var wire 1 :$ in [1] $end +$var wire 1 K% mem [0] $end +$var wire 1 s? mem_inv [0] $end +$var wire 1 q? out [0] $end + +$scope module sky130_fd_sc_hd__mux2_1_0 $end +$var wire 1 q? X $end +$var wire 1 :$ A0 $end +$var wire 1 `# A1 $end +$var wire 1 K% S $end +$var supply1 1 w? VPWR $end +$var supply0 1 x? VGND $end +$var supply1 1 y? VPB $end +$var supply0 1 z? VNB $end + +$scope module base $end +$var wire 1 q? X $end +$var wire 1 :$ A0 $end +$var wire 1 `# A1 $end +$var wire 1 K% S $end +$var wire 1 {? mux_2to10_out_X $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mux_l2_in_0_ $end +$var wire 1 q? in [0] $end +$var wire 1 t? in [1] $end +$var wire 1 L% mem [0] $end +$var wire 1 u? mem_inv [0] $end +$var wire 1 r? out [0] $end +$var wire 1 p' p0 $end + +$scope module sky130_fd_sc_hd__mux2_1_0 $end +$var wire 1 r? X $end +$var wire 1 p' A0 $end +$var wire 1 q? A1 $end +$var wire 1 L% S $end +$var supply1 1 |? VPWR $end +$var supply0 1 }? VGND $end +$var supply1 1 ~? VPB $end +$var supply0 1 !@ VNB $end + +$scope module base $end +$var wire 1 r? X $end +$var wire 1 p' A0 $end +$var wire 1 q? A1 $end +$var wire 1 L% S $end +$var wire 1 "@ mux_2to10_out_X $end +$upscope $end +$upscope $end +$upscope $end + +$scope module BINV_R_156 $end +$var wire 1 p$ Y $end +$var wire 1 v? A $end +$var supply1 1 #@ VPWR $end +$var supply0 1 $@ VGND $end +$var supply1 1 %@ VPB $end +$var supply0 1 &@ VNB $end + +$scope module base $end +$var wire 1 p$ Y $end +$var wire 1 v? A $end +$var wire 1 '@ not0_out_Y $end +$upscope $end +$upscope $end + +$scope module BINV_R_157 $end +$var wire 1 v? Y $end +$var wire 1 r? A $end +$var supply1 1 (@ VPWR $end +$var supply0 1 )@ VGND $end +$var supply1 1 *@ VPB $end +$var supply0 1 +@ VNB $end + +$scope module base $end +$var wire 1 v? Y $end +$var wire 1 r? A $end +$var wire 1 ,@ not0_out_Y $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mux_left_track_45 $end +$var wire 1 a# in [0] $end +$var wire 1 3$ in [1] $end +$var wire 1 O% sram [0] $end +$var wire 1 P% sram [1] $end +$var wire 1 /( sram_inv [0] $end +$var wire 1 0( sram_inv [1] $end +$var wire 1 q$ out [0] $end +$var wire 1 p' p0 $end +$var wire 1 -@ mux_2level_tapbuf_basis_input2_mem1_0_out [0] $end +$var wire 1 .@ mux_2level_tapbuf_basis_input2_mem1_1_out [0] $end +$var wire 1 /@ SYNOPSYS_UNCONNECTED_1 $end +$var wire 1 0@ SYNOPSYS_UNCONNECTED_2 $end +$var wire 1 1@ SYNOPSYS_UNCONNECTED_3 $end +$var wire 1 2@ BUF_net_159 $end + +$scope module mux_l1_in_0_ $end +$var wire 1 a# in [0] $end +$var wire 1 3$ in [1] $end +$var wire 1 O% mem [0] $end +$var wire 1 /@ mem_inv [0] $end +$var wire 1 -@ out [0] $end + +$scope module sky130_fd_sc_hd__mux2_1_0 $end +$var wire 1 -@ X $end +$var wire 1 3$ A0 $end +$var wire 1 a# A1 $end +$var wire 1 O% S $end +$var supply1 1 3@ VPWR $end +$var supply0 1 4@ VGND $end +$var supply1 1 5@ VPB $end +$var supply0 1 6@ VNB $end + +$scope module base $end +$var wire 1 -@ X $end +$var wire 1 3$ A0 $end +$var wire 1 a# A1 $end +$var wire 1 O% S $end +$var wire 1 7@ mux_2to10_out_X $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mux_l2_in_0_ $end +$var wire 1 -@ in [0] $end +$var wire 1 0@ in [1] $end +$var wire 1 P% mem [0] $end +$var wire 1 1@ mem_inv [0] $end +$var wire 1 .@ out [0] $end +$var wire 1 p' p0 $end + +$scope module sky130_fd_sc_hd__mux2_1_0 $end +$var wire 1 .@ X $end +$var wire 1 p' A0 $end +$var wire 1 -@ A1 $end +$var wire 1 P% S $end +$var supply1 1 8@ VPWR $end +$var supply0 1 9@ VGND $end +$var supply1 1 :@ VPB $end +$var supply0 1 ;@ VNB $end + +$scope module base $end +$var wire 1 .@ X $end +$var wire 1 p' A0 $end +$var wire 1 -@ A1 $end +$var wire 1 P% S $end +$var wire 1 <@ mux_2to10_out_X $end +$upscope $end +$upscope $end +$upscope $end + +$scope module BINV_R_158 $end +$var wire 1 q$ Y $end +$var wire 1 2@ A $end +$var supply1 1 =@ VPWR $end +$var supply0 1 >@ VGND $end +$var supply1 1 ?@ VPB $end +$var supply0 1 @@ VNB $end + +$scope module base $end +$var wire 1 q$ Y $end +$var wire 1 2@ A $end +$var wire 1 A@ not0_out_Y $end +$upscope $end +$upscope $end + +$scope module BINV_R_159 $end +$var wire 1 2@ Y $end +$var wire 1 .@ A $end +$var supply1 1 B@ VPWR $end +$var supply0 1 C@ VGND $end +$var supply1 1 D@ VPB $end +$var supply0 1 E@ VNB $end + +$scope module base $end +$var wire 1 2@ Y $end +$var wire 1 .@ A $end +$var wire 1 F@ not0_out_Y $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mux_left_track_47 $end +$var wire 1 b# in [0] $end +$var wire 1 4$ in [1] $end +$var wire 1 Q% sram [0] $end +$var wire 1 R% sram [1] $end +$var wire 1 1( sram_inv [0] $end +$var wire 1 2( sram_inv [1] $end +$var wire 1 r$ out [0] $end +$var wire 1 p' p0 $end +$var wire 1 G@ mux_2level_tapbuf_basis_input2_mem1_0_out [0] $end +$var wire 1 H@ mux_2level_tapbuf_basis_input2_mem1_1_out [0] $end +$var wire 1 I@ SYNOPSYS_UNCONNECTED_1 $end +$var wire 1 J@ SYNOPSYS_UNCONNECTED_2 $end +$var wire 1 K@ SYNOPSYS_UNCONNECTED_3 $end +$var wire 1 L@ BUF_net_161 $end + +$scope module mux_l1_in_0_ $end +$var wire 1 b# in [0] $end +$var wire 1 4$ in [1] $end +$var wire 1 Q% mem [0] $end +$var wire 1 I@ mem_inv [0] $end +$var wire 1 G@ out [0] $end + +$scope module sky130_fd_sc_hd__mux2_1_0 $end +$var wire 1 G@ X $end +$var wire 1 4$ A0 $end +$var wire 1 b# A1 $end +$var wire 1 Q% S $end +$var supply1 1 M@ VPWR $end +$var supply0 1 N@ VGND $end +$var supply1 1 O@ VPB $end +$var supply0 1 P@ VNB $end + +$scope module base $end +$var wire 1 G@ X $end +$var wire 1 4$ A0 $end +$var wire 1 b# A1 $end +$var wire 1 Q% S $end +$var wire 1 Q@ mux_2to10_out_X $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mux_l2_in_0_ $end +$var wire 1 G@ in [0] $end +$var wire 1 J@ in [1] $end +$var wire 1 R% mem [0] $end +$var wire 1 K@ mem_inv [0] $end +$var wire 1 H@ out [0] $end +$var wire 1 p' p0 $end + +$scope module sky130_fd_sc_hd__mux2_1_0 $end +$var wire 1 H@ X $end +$var wire 1 p' A0 $end +$var wire 1 G@ A1 $end +$var wire 1 R% S $end +$var supply1 1 R@ VPWR $end +$var supply0 1 S@ VGND $end +$var supply1 1 T@ VPB $end +$var supply0 1 U@ VNB $end + +$scope module base $end +$var wire 1 H@ X $end +$var wire 1 p' A0 $end +$var wire 1 G@ A1 $end +$var wire 1 R% S $end +$var wire 1 V@ mux_2to10_out_X $end +$upscope $end +$upscope $end +$upscope $end + +$scope module BINV_R_160 $end +$var wire 1 r$ Y $end +$var wire 1 L@ A $end +$var supply1 1 W@ VPWR $end +$var supply0 1 X@ VGND $end +$var supply1 1 Y@ VPB $end +$var supply0 1 Z@ VNB $end + +$scope module base $end +$var wire 1 r$ Y $end +$var wire 1 L@ A $end +$var wire 1 [@ not0_out_Y $end +$upscope $end +$upscope $end + +$scope module BINV_R_161 $end +$var wire 1 L@ Y $end +$var wire 1 H@ A $end +$var supply1 1 \@ VPWR $end +$var supply0 1 ]@ VGND $end +$var supply1 1 ^@ VPB $end +$var supply0 1 _@ VNB $end + +$scope module base $end +$var wire 1 L@ Y $end +$var wire 1 H@ A $end +$var wire 1 `@ not0_out_Y $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mux_left_track_49 $end +$var wire 1 c# in [0] $end +$var wire 1 5$ in [1] $end +$var wire 1 S% sram [0] $end +$var wire 1 T% sram [1] $end +$var wire 1 3( sram_inv [0] $end +$var wire 1 4( sram_inv [1] $end +$var wire 1 s$ out [0] $end +$var wire 1 p' p0 $end +$var wire 1 a@ mux_2level_tapbuf_basis_input2_mem1_0_out [0] $end +$var wire 1 b@ mux_2level_tapbuf_basis_input2_mem1_1_out [0] $end +$var wire 1 c@ SYNOPSYS_UNCONNECTED_1 $end +$var wire 1 d@ SYNOPSYS_UNCONNECTED_2 $end +$var wire 1 e@ SYNOPSYS_UNCONNECTED_3 $end +$var wire 1 f@ BUF_net_163 $end + +$scope module mux_l1_in_0_ $end +$var wire 1 c# in [0] $end +$var wire 1 5$ in [1] $end +$var wire 1 S% mem [0] $end +$var wire 1 c@ mem_inv [0] $end +$var wire 1 a@ out [0] $end + +$scope module sky130_fd_sc_hd__mux2_1_0 $end +$var wire 1 a@ X $end +$var wire 1 5$ A0 $end +$var wire 1 c# A1 $end +$var wire 1 S% S $end +$var supply1 1 g@ VPWR $end +$var supply0 1 h@ VGND $end +$var supply1 1 i@ VPB $end +$var supply0 1 j@ VNB $end + +$scope module base $end +$var wire 1 a@ X $end +$var wire 1 5$ A0 $end +$var wire 1 c# A1 $end +$var wire 1 S% S $end +$var wire 1 k@ mux_2to10_out_X $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mux_l2_in_0_ $end +$var wire 1 a@ in [0] $end +$var wire 1 d@ in [1] $end +$var wire 1 T% mem [0] $end +$var wire 1 e@ mem_inv [0] $end +$var wire 1 b@ out [0] $end +$var wire 1 p' p0 $end + +$scope module sky130_fd_sc_hd__mux2_1_0 $end +$var wire 1 b@ X $end +$var wire 1 p' A0 $end +$var wire 1 a@ A1 $end +$var wire 1 T% S $end +$var supply1 1 l@ VPWR $end +$var supply0 1 m@ VGND $end +$var supply1 1 n@ VPB $end +$var supply0 1 o@ VNB $end + +$scope module base $end +$var wire 1 b@ X $end +$var wire 1 p' A0 $end +$var wire 1 a@ A1 $end +$var wire 1 T% S $end +$var wire 1 p@ mux_2to10_out_X $end +$upscope $end +$upscope $end +$upscope $end + +$scope module BINV_R_162 $end +$var wire 1 s$ Y $end +$var wire 1 f@ A $end +$var supply1 1 q@ VPWR $end +$var supply0 1 r@ VGND $end +$var supply1 1 s@ VPB $end +$var supply0 1 t@ VNB $end + +$scope module base $end +$var wire 1 s$ Y $end +$var wire 1 f@ A $end +$var wire 1 u@ not0_out_Y $end +$upscope $end +$upscope $end + +$scope module BINV_R_163 $end +$var wire 1 f@ Y $end +$var wire 1 b@ A $end +$var supply1 1 v@ VPWR $end +$var supply0 1 w@ VGND $end +$var supply1 1 x@ VPB $end +$var supply0 1 y@ VNB $end + +$scope module base $end +$var wire 1 f@ Y $end +$var wire 1 b@ A $end +$var wire 1 z@ not0_out_Y $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mux_left_track_51 $end +$var wire 1 d# in [0] $end +$var wire 1 6$ in [1] $end +$var wire 1 U% sram [0] $end +$var wire 1 V% sram [1] $end +$var wire 1 5( sram_inv [0] $end +$var wire 1 6( sram_inv [1] $end +$var wire 1 t$ out [0] $end +$var wire 1 p' p0 $end +$var wire 1 {@ mux_2level_tapbuf_basis_input2_mem1_0_out [0] $end +$var wire 1 |@ mux_2level_tapbuf_basis_input2_mem1_1_out [0] $end +$var wire 1 }@ SYNOPSYS_UNCONNECTED_1 $end +$var wire 1 ~@ SYNOPSYS_UNCONNECTED_2 $end +$var wire 1 !A SYNOPSYS_UNCONNECTED_3 $end +$var wire 1 "A BUF_net_165 $end + +$scope module mux_l1_in_0_ $end +$var wire 1 d# in [0] $end +$var wire 1 6$ in [1] $end +$var wire 1 U% mem [0] $end +$var wire 1 }@ mem_inv [0] $end +$var wire 1 {@ out [0] $end + +$scope module sky130_fd_sc_hd__mux2_1_0 $end +$var wire 1 {@ X $end +$var wire 1 6$ A0 $end +$var wire 1 d# A1 $end +$var wire 1 U% S $end +$var supply1 1 #A VPWR $end +$var supply0 1 $A VGND $end +$var supply1 1 %A VPB $end +$var supply0 1 &A VNB $end + +$scope module base $end +$var wire 1 {@ X $end +$var wire 1 6$ A0 $end +$var wire 1 d# A1 $end +$var wire 1 U% S $end +$var wire 1 'A mux_2to10_out_X $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mux_l2_in_0_ $end +$var wire 1 {@ in [0] $end +$var wire 1 ~@ in [1] $end +$var wire 1 V% mem [0] $end +$var wire 1 !A mem_inv [0] $end +$var wire 1 |@ out [0] $end +$var wire 1 p' p0 $end + +$scope module sky130_fd_sc_hd__mux2_1_0 $end +$var wire 1 |@ X $end +$var wire 1 p' A0 $end +$var wire 1 {@ A1 $end +$var wire 1 V% S $end +$var supply1 1 (A VPWR $end +$var supply0 1 )A VGND $end +$var supply1 1 *A VPB $end +$var supply0 1 +A VNB $end + +$scope module base $end +$var wire 1 |@ X $end +$var wire 1 p' A0 $end +$var wire 1 {@ A1 $end +$var wire 1 V% S $end +$var wire 1 ,A mux_2to10_out_X $end +$upscope $end +$upscope $end +$upscope $end + +$scope module BINV_R_164 $end +$var wire 1 t$ Y $end +$var wire 1 "A A $end +$var supply1 1 -A VPWR $end +$var supply0 1 .A VGND $end +$var supply1 1 /A VPB $end +$var supply0 1 0A VNB $end + +$scope module base $end +$var wire 1 t$ Y $end +$var wire 1 "A A $end +$var wire 1 1A not0_out_Y $end +$upscope $end +$upscope $end + +$scope module BINV_R_165 $end +$var wire 1 "A Y $end +$var wire 1 |@ A $end +$var supply1 1 2A VPWR $end +$var supply0 1 3A VGND $end +$var supply1 1 4A VPB $end +$var supply0 1 5A VNB $end + +$scope module base $end +$var wire 1 "A Y $end +$var wire 1 |@ A $end +$var wire 1 6A not0_out_Y $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mux_left_track_55 $end +$var wire 1 f# in [0] $end +$var wire 1 8$ in [1] $end +$var wire 1 W% sram [0] $end +$var wire 1 X% sram [1] $end +$var wire 1 7( sram_inv [0] $end +$var wire 1 8( sram_inv [1] $end +$var wire 1 v$ out [0] $end +$var wire 1 R' p0 $end +$var wire 1 7A mux_2level_tapbuf_basis_input2_mem1_0_out [0] $end +$var wire 1 8A mux_2level_tapbuf_basis_input2_mem1_1_out [0] $end +$var wire 1 9A SYNOPSYS_UNCONNECTED_1 $end +$var wire 1 :A SYNOPSYS_UNCONNECTED_2 $end +$var wire 1 ;A SYNOPSYS_UNCONNECTED_3 $end +$var wire 1 A VGND $end +$var supply1 1 ?A VPB $end +$var supply0 1 @A VNB $end + +$scope module base $end +$var wire 1 7A X $end +$var wire 1 8$ A0 $end +$var wire 1 f# A1 $end +$var wire 1 W% S $end +$var wire 1 AA mux_2to10_out_X $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mux_l2_in_0_ $end +$var wire 1 7A in [0] $end +$var wire 1 :A in [1] $end +$var wire 1 X% mem [0] $end +$var wire 1 ;A mem_inv [0] $end +$var wire 1 8A out [0] $end +$var wire 1 R' p0 $end + +$scope module sky130_fd_sc_hd__mux2_1_0 $end +$var wire 1 8A X $end +$var wire 1 R' A0 $end +$var wire 1 7A A1 $end +$var wire 1 X% S $end +$var supply1 1 BA VPWR $end +$var supply0 1 CA VGND $end +$var supply1 1 DA VPB $end +$var supply0 1 EA VNB $end + +$scope module base $end +$var wire 1 8A X $end +$var wire 1 R' A0 $end +$var wire 1 7A A1 $end +$var wire 1 X% S $end +$var wire 1 FA mux_2to10_out_X $end +$upscope $end +$upscope $end +$upscope $end + +$scope module BINV_R_166 $end +$var wire 1 v$ Y $end +$var wire 1 B VPWR $end +$var supply0 1 ?B VGND $end +$var supply1 1 @B VPB $end +$var supply0 1 AB VNB $end + +$scope module base $end +$var wire 1 v% X $end +$var wire 1 8% A $end +$var wire 1 BB buf0_out_X $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mem_bottom_track_17 $end +$var wire 1 K# pReset [0] $end +$var wire 1 }$ prog_clk [0] $end +$var wire 1 v% ccff_head [0] $end +$var wire 1 #& ccff_tail [0] $end +$var wire 1 M% mem_out [0] $end +$var wire 1 N% mem_out [1] $end + +$scope module sky130_fd_sc_hd__dfrtp_1_0_ $end +$var wire 1 M% Q $end +$var wire 1 }$ CLK $end +$var wire 1 v% D $end +$var wire 1 K# RESET_B $end +$var supply1 1 CB VPWR $end +$var supply0 1 DB VGND $end +$var supply1 1 EB VPB $end +$var supply0 1 FB VNB $end + +$scope module base $end +$var wire 1 M% Q $end +$var wire 1 }$ CLK $end +$var wire 1 v% D $end +$var wire 1 K# RESET_B $end +$var wire 1 GB buf_Q $end +$var wire 1 HB RESET $end +$upscope $end +$upscope $end + +$scope module sky130_fd_sc_hd__dfrtp_1_1_ $end +$var wire 1 N% Q $end +$var wire 1 }$ CLK $end +$var wire 1 M% D $end +$var wire 1 K# RESET_B $end +$var supply1 1 IB VPWR $end +$var supply0 1 JB VGND $end +$var supply1 1 KB VPB $end +$var supply0 1 LB VNB $end + +$scope module base $end +$var wire 1 N% Q $end +$var wire 1 }$ CLK $end +$var wire 1 M% D $end +$var wire 1 K# RESET_B $end +$var wire 1 MB buf_Q $end +$var wire 1 NB RESET $end +$upscope $end +$upscope $end + +$scope module FTB_39__38 $end +$var wire 1 #& X $end +$var wire 1 N% A $end +$var supply1 1 OB VPWR $end +$var supply0 1 PB VGND $end +$var supply1 1 QB VPB $end +$var supply0 1 RB VNB $end + +$scope module base $end +$var wire 1 #& X $end +$var wire 1 N% A $end +$var wire 1 SB buf0_out_X $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mem_bottom_track_19 $end +$var wire 1 K# pReset [0] $end +$var wire 1 }$ prog_clk [0] $end +$var wire 1 #& ccff_head [0] $end +$var wire 1 *& ccff_tail [0] $end +$var wire 1 ]% mem_out [0] $end +$var wire 1 ^% mem_out [1] $end + +$scope module sky130_fd_sc_hd__dfrtp_1_0_ $end +$var wire 1 ]% Q $end +$var wire 1 }$ CLK $end +$var wire 1 #& D $end +$var wire 1 K# RESET_B $end +$var supply1 1 TB VPWR $end +$var supply0 1 UB VGND $end +$var supply1 1 VB VPB $end +$var supply0 1 WB VNB $end + +$scope module base $end +$var wire 1 ]% Q $end +$var wire 1 }$ CLK $end +$var wire 1 #& D $end +$var wire 1 K# RESET_B $end +$var wire 1 XB buf_Q $end +$var wire 1 YB RESET $end +$upscope $end +$upscope $end + +$scope module sky130_fd_sc_hd__dfrtp_1_1_ $end +$var wire 1 ^% Q $end +$var wire 1 }$ CLK $end +$var wire 1 ]% D $end +$var wire 1 K# RESET_B $end +$var supply1 1 ZB VPWR $end +$var supply0 1 [B VGND $end +$var supply1 1 \B VPB $end +$var supply0 1 ]B VNB $end + +$scope module base $end +$var wire 1 ^% Q $end +$var wire 1 }$ CLK $end +$var wire 1 ]% D $end +$var wire 1 K# RESET_B $end +$var wire 1 ^B buf_Q $end +$var wire 1 _B RESET $end +$upscope $end +$upscope $end + +$scope module FTB_40__39 $end +$var wire 1 *& X $end +$var wire 1 ^% A $end +$var supply1 1 `B VPWR $end +$var supply0 1 aB VGND $end +$var supply1 1 bB VPB $end +$var supply0 1 cB VNB $end + +$scope module base $end +$var wire 1 *& X $end +$var wire 1 ^% A $end +$var wire 1 dB buf0_out_X $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mem_bottom_track_21 $end +$var wire 1 K# pReset [0] $end +$var wire 1 }$ prog_clk [0] $end +$var wire 1 *& ccff_head [0] $end +$var wire 1 +& ccff_tail [0] $end +$var wire 1 _% mem_out [0] $end +$var wire 1 `% mem_out [1] $end + +$scope module sky130_fd_sc_hd__dfrtp_1_0_ $end +$var wire 1 _% Q $end +$var wire 1 }$ CLK $end +$var wire 1 *& D $end +$var wire 1 K# RESET_B $end +$var supply1 1 eB VPWR $end +$var supply0 1 fB VGND $end +$var supply1 1 gB VPB $end +$var supply0 1 hB VNB $end + +$scope module base $end +$var wire 1 _% Q $end +$var wire 1 }$ CLK $end +$var wire 1 *& D $end +$var wire 1 K# RESET_B $end +$var wire 1 iB buf_Q $end +$var wire 1 jB RESET $end +$upscope $end +$upscope $end + +$scope module sky130_fd_sc_hd__dfrtp_1_1_ $end +$var wire 1 `% Q $end +$var wire 1 }$ CLK $end +$var wire 1 _% D $end +$var wire 1 K# RESET_B $end +$var supply1 1 kB VPWR $end +$var supply0 1 lB VGND $end +$var supply1 1 mB VPB $end +$var supply0 1 nB VNB $end + +$scope module base $end +$var wire 1 `% Q $end +$var wire 1 }$ CLK $end +$var wire 1 _% D $end +$var wire 1 K# RESET_B $end +$var wire 1 oB buf_Q $end +$var wire 1 pB RESET $end +$upscope $end +$upscope $end + +$scope module FTB_41__40 $end +$var wire 1 +& X $end +$var wire 1 `% A $end +$var supply1 1 qB VPWR $end +$var supply0 1 rB VGND $end +$var supply1 1 sB VPB $end +$var supply0 1 tB VNB $end + +$scope module base $end +$var wire 1 +& X $end +$var wire 1 `% A $end +$var wire 1 uB buf0_out_X $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mem_bottom_track_23 $end +$var wire 1 K# pReset [0] $end +$var wire 1 }$ prog_clk [0] $end +$var wire 1 +& ccff_head [0] $end +$var wire 1 ,& ccff_tail [0] $end +$var wire 1 a% mem_out [0] $end +$var wire 1 b% mem_out [1] $end + +$scope module sky130_fd_sc_hd__dfrtp_1_0_ $end +$var wire 1 a% Q $end +$var wire 1 }$ CLK $end +$var wire 1 +& D $end +$var wire 1 K# RESET_B $end +$var supply1 1 vB VPWR $end +$var supply0 1 wB VGND $end +$var supply1 1 xB VPB $end +$var supply0 1 yB VNB $end + +$scope module base $end +$var wire 1 a% Q $end +$var wire 1 }$ CLK $end +$var wire 1 +& D $end +$var wire 1 K# RESET_B $end +$var wire 1 zB buf_Q $end +$var wire 1 {B RESET $end +$upscope $end +$upscope $end + +$scope module sky130_fd_sc_hd__dfrtp_1_1_ $end +$var wire 1 b% Q $end +$var wire 1 }$ CLK $end +$var wire 1 a% D $end +$var wire 1 K# RESET_B $end +$var supply1 1 |B VPWR $end +$var supply0 1 }B VGND $end +$var supply1 1 ~B VPB $end +$var supply0 1 !C VNB $end + +$scope module base $end +$var wire 1 b% Q $end +$var wire 1 }$ CLK $end +$var wire 1 a% D $end +$var wire 1 K# RESET_B $end +$var wire 1 "C buf_Q $end +$var wire 1 #C RESET $end +$upscope $end +$upscope $end + +$scope module FTB_42__41 $end +$var wire 1 ,& X $end +$var wire 1 b% A $end +$var supply1 1 $C VPWR $end +$var supply0 1 %C VGND $end +$var supply1 1 &C VPB $end +$var supply0 1 'C VNB $end + +$scope module base $end +$var wire 1 ,& X $end +$var wire 1 b% A $end +$var wire 1 (C buf0_out_X $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mem_bottom_track_25 $end +$var wire 1 K# pReset [0] $end +$var wire 1 }$ prog_clk [0] $end +$var wire 1 ,& ccff_head [0] $end +$var wire 1 -& ccff_tail [0] $end +$var wire 1 c% mem_out [0] $end +$var wire 1 d% mem_out [1] $end + +$scope module sky130_fd_sc_hd__dfrtp_1_0_ $end +$var wire 1 c% Q $end +$var wire 1 }$ CLK $end +$var wire 1 ,& D $end +$var wire 1 K# RESET_B $end +$var supply1 1 )C VPWR $end +$var supply0 1 *C VGND $end +$var supply1 1 +C VPB $end +$var supply0 1 ,C VNB $end + +$scope module base $end +$var wire 1 c% Q $end +$var wire 1 }$ CLK $end +$var wire 1 ,& D $end +$var wire 1 K# RESET_B $end +$var wire 1 -C buf_Q $end +$var wire 1 .C RESET $end +$upscope $end +$upscope $end + +$scope module sky130_fd_sc_hd__dfrtp_1_1_ $end +$var wire 1 d% Q $end +$var wire 1 }$ CLK $end +$var wire 1 c% D $end +$var wire 1 K# RESET_B $end +$var supply1 1 /C VPWR $end +$var supply0 1 0C VGND $end +$var supply1 1 1C VPB $end +$var supply0 1 2C VNB $end + +$scope module base $end +$var wire 1 d% Q $end +$var wire 1 }$ CLK $end +$var wire 1 c% D $end +$var wire 1 K# RESET_B $end +$var wire 1 3C buf_Q $end +$var wire 1 4C RESET $end +$upscope $end +$upscope $end + +$scope module FTB_43__42 $end +$var wire 1 -& X $end +$var wire 1 d% A $end +$var supply1 1 5C VPWR $end +$var supply0 1 6C VGND $end +$var supply1 1 7C VPB $end +$var supply0 1 8C VNB $end + +$scope module base $end +$var wire 1 -& X $end +$var wire 1 d% A $end +$var wire 1 9C buf0_out_X $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mem_bottom_track_27 $end +$var wire 1 K# pReset [0] $end +$var wire 1 }$ prog_clk [0] $end +$var wire 1 -& ccff_head [0] $end +$var wire 1 .& ccff_tail [0] $end +$var wire 1 e% mem_out [0] $end +$var wire 1 f% mem_out [1] $end + +$scope module sky130_fd_sc_hd__dfrtp_1_0_ $end +$var wire 1 e% Q $end +$var wire 1 }$ CLK $end +$var wire 1 -& D $end +$var wire 1 K# RESET_B $end +$var supply1 1 :C VPWR $end +$var supply0 1 ;C VGND $end +$var supply1 1 C buf_Q $end +$var wire 1 ?C RESET $end +$upscope $end +$upscope $end + +$scope module sky130_fd_sc_hd__dfrtp_1_1_ $end +$var wire 1 f% Q $end +$var wire 1 }$ CLK $end +$var wire 1 e% D $end +$var wire 1 K# RESET_B $end +$var supply1 1 @C VPWR $end +$var supply0 1 AC VGND $end +$var supply1 1 BC VPB $end +$var supply0 1 CC VNB $end + +$scope module base $end +$var wire 1 f% Q $end +$var wire 1 }$ CLK $end +$var wire 1 e% D $end +$var wire 1 K# RESET_B $end +$var wire 1 DC buf_Q $end +$var wire 1 EC RESET $end +$upscope $end +$upscope $end + +$scope module FTB_44__43 $end +$var wire 1 .& X $end +$var wire 1 f% A $end +$var supply1 1 FC VPWR $end +$var supply0 1 GC VGND $end +$var supply1 1 HC VPB $end +$var supply0 1 IC VNB $end + +$scope module base $end +$var wire 1 .& X $end +$var wire 1 f% A $end +$var wire 1 JC buf0_out_X $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mem_bottom_track_39 $end +$var wire 1 K# pReset [0] $end +$var wire 1 }$ prog_clk [0] $end +$var wire 1 9& ccff_head [0] $end +$var wire 1 /& ccff_tail [0] $end +$var wire 1 g% mem_out [0] $end +$var wire 1 h% mem_out [1] $end + +$scope module sky130_fd_sc_hd__dfrtp_1_0_ $end +$var wire 1 g% Q $end +$var wire 1 }$ CLK $end +$var wire 1 9& D $end +$var wire 1 K# RESET_B $end +$var supply1 1 KC VPWR $end +$var supply0 1 LC VGND $end +$var supply1 1 MC VPB $end +$var supply0 1 NC VNB $end + +$scope module base $end +$var wire 1 g% Q $end +$var wire 1 }$ CLK $end +$var wire 1 9& D $end +$var wire 1 K# RESET_B $end +$var wire 1 OC buf_Q $end +$var wire 1 PC RESET $end +$upscope $end +$upscope $end + +$scope module sky130_fd_sc_hd__dfrtp_1_1_ $end +$var wire 1 h% Q $end +$var wire 1 }$ CLK $end +$var wire 1 g% D $end +$var wire 1 K# RESET_B $end +$var supply1 1 QC VPWR $end +$var supply0 1 RC VGND $end +$var supply1 1 SC VPB $end +$var supply0 1 TC VNB $end + +$scope module base $end +$var wire 1 h% Q $end +$var wire 1 }$ CLK $end +$var wire 1 g% D $end +$var wire 1 K# RESET_B $end +$var wire 1 UC buf_Q $end +$var wire 1 VC RESET $end +$upscope $end +$upscope $end + +$scope module FTB_45__44 $end +$var wire 1 /& X $end +$var wire 1 h% A $end +$var supply1 1 WC VPWR $end +$var supply0 1 XC VGND $end +$var supply1 1 YC VPB $end +$var supply0 1 ZC VNB $end + +$scope module base $end +$var wire 1 /& X $end +$var wire 1 h% A $end +$var wire 1 [C buf0_out_X $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mem_bottom_track_41 $end +$var wire 1 K# pReset [0] $end +$var wire 1 }$ prog_clk [0] $end +$var wire 1 /& ccff_head [0] $end +$var wire 1 0& ccff_tail [0] $end +$var wire 1 i% mem_out [0] $end +$var wire 1 j% mem_out [1] $end + +$scope module sky130_fd_sc_hd__dfrtp_1_0_ $end +$var wire 1 i% Q $end +$var wire 1 }$ CLK $end +$var wire 1 /& D $end +$var wire 1 K# RESET_B $end +$var supply1 1 \C VPWR $end +$var supply0 1 ]C VGND $end +$var supply1 1 ^C VPB $end +$var supply0 1 _C VNB $end + +$scope module base $end +$var wire 1 i% Q $end +$var wire 1 }$ CLK $end +$var wire 1 /& D $end +$var wire 1 K# RESET_B $end +$var wire 1 `C buf_Q $end +$var wire 1 aC RESET $end +$upscope $end +$upscope $end + +$scope module sky130_fd_sc_hd__dfrtp_1_1_ $end +$var wire 1 j% Q $end +$var wire 1 }$ CLK $end +$var wire 1 i% D $end +$var wire 1 K# RESET_B $end +$var supply1 1 bC VPWR $end +$var supply0 1 cC VGND $end +$var supply1 1 dC VPB $end +$var supply0 1 eC VNB $end + +$scope module base $end +$var wire 1 j% Q $end +$var wire 1 }$ CLK $end +$var wire 1 i% D $end +$var wire 1 K# RESET_B $end +$var wire 1 fC buf_Q $end +$var wire 1 gC RESET $end +$upscope $end +$upscope $end + +$scope module FTB_46__45 $end +$var wire 1 0& X $end +$var wire 1 j% A $end +$var supply1 1 hC VPWR $end +$var supply0 1 iC VGND $end +$var supply1 1 jC VPB $end +$var supply0 1 kC VNB $end + +$scope module base $end +$var wire 1 0& X $end +$var wire 1 j% A $end +$var wire 1 lC buf0_out_X $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mem_bottom_track_43 $end +$var wire 1 K# pReset [0] $end +$var wire 1 }$ prog_clk [0] $end +$var wire 1 0& ccff_head [0] $end +$var wire 1 l% ccff_tail [0] $end +$var wire 1 #% mem_out [0] $end +$var wire 1 $% mem_out [1] $end + +$scope module sky130_fd_sc_hd__dfrtp_1_0_ $end +$var wire 1 #% Q $end +$var wire 1 }$ CLK $end +$var wire 1 0& D $end +$var wire 1 K# RESET_B $end +$var supply1 1 mC VPWR $end +$var supply0 1 nC VGND $end +$var supply1 1 oC VPB $end +$var supply0 1 pC VNB $end + +$scope module base $end +$var wire 1 #% Q $end +$var wire 1 }$ CLK $end +$var wire 1 0& D $end +$var wire 1 K# RESET_B $end +$var wire 1 qC buf_Q $end +$var wire 1 rC RESET $end +$upscope $end +$upscope $end + +$scope module sky130_fd_sc_hd__dfrtp_1_1_ $end +$var wire 1 $% Q $end +$var wire 1 }$ CLK $end +$var wire 1 #% D $end +$var wire 1 K# RESET_B $end +$var supply1 1 sC VPWR $end +$var supply0 1 tC VGND $end +$var supply1 1 uC VPB $end +$var supply0 1 vC VNB $end + +$scope module base $end +$var wire 1 $% Q $end +$var wire 1 }$ CLK $end +$var wire 1 #% D $end +$var wire 1 K# RESET_B $end +$var wire 1 wC buf_Q $end +$var wire 1 xC RESET $end +$upscope $end +$upscope $end + +$scope module FTB_47__46 $end +$var wire 1 l% X $end +$var wire 1 $% A $end +$var supply1 1 yC VPWR $end +$var supply0 1 zC VGND $end +$var supply1 1 {C VPB $end +$var supply0 1 |C VNB $end + +$scope module base $end +$var wire 1 l% X $end +$var wire 1 $% A $end +$var wire 1 }C buf0_out_X $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mem_bottom_track_47 $end +$var wire 1 K# pReset [0] $end +$var wire 1 }$ prog_clk [0] $end +$var wire 1 :& ccff_head [0] $end +$var wire 1 m% ccff_tail [0] $end +$var wire 1 %% mem_out [0] $end +$var wire 1 &% mem_out [1] $end + +$scope module sky130_fd_sc_hd__dfrtp_1_0_ $end +$var wire 1 %% Q $end +$var wire 1 }$ CLK $end +$var wire 1 :& D $end +$var wire 1 K# RESET_B $end +$var supply1 1 ~C VPWR $end +$var supply0 1 !D VGND $end +$var supply1 1 "D VPB $end +$var supply0 1 #D VNB $end + +$scope module base $end +$var wire 1 %% Q $end +$var wire 1 }$ CLK $end +$var wire 1 :& D $end +$var wire 1 K# RESET_B $end +$var wire 1 $D buf_Q $end +$var wire 1 %D RESET $end +$upscope $end +$upscope $end + +$scope module sky130_fd_sc_hd__dfrtp_1_1_ $end +$var wire 1 &% Q $end +$var wire 1 }$ CLK $end +$var wire 1 %% D $end +$var wire 1 K# RESET_B $end +$var supply1 1 &D VPWR $end +$var supply0 1 'D VGND $end +$var supply1 1 (D VPB $end +$var supply0 1 )D VNB $end + +$scope module base $end +$var wire 1 &% Q $end +$var wire 1 }$ CLK $end +$var wire 1 %% D $end +$var wire 1 K# RESET_B $end +$var wire 1 *D buf_Q $end +$var wire 1 +D RESET $end +$upscope $end +$upscope $end + +$scope module FTB_48__47 $end +$var wire 1 m% X $end +$var wire 1 &% A $end +$var supply1 1 ,D VPWR $end +$var supply0 1 -D VGND $end +$var supply1 1 .D VPB $end +$var supply0 1 /D VNB $end + +$scope module base $end +$var wire 1 m% X $end +$var wire 1 &% A $end +$var wire 1 0D buf0_out_X $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mem_bottom_track_49 $end +$var wire 1 K# pReset [0] $end +$var wire 1 }$ prog_clk [0] $end +$var wire 1 m% ccff_head [0] $end +$var wire 1 n% ccff_tail [0] $end +$var wire 1 '% mem_out [0] $end +$var wire 1 (% mem_out [1] $end + +$scope module sky130_fd_sc_hd__dfrtp_1_0_ $end +$var wire 1 '% Q $end +$var wire 1 }$ CLK $end +$var wire 1 m% D $end +$var wire 1 K# RESET_B $end +$var supply1 1 1D VPWR $end +$var supply0 1 2D VGND $end +$var supply1 1 3D VPB $end +$var supply0 1 4D VNB $end + +$scope module base $end +$var wire 1 '% Q $end +$var wire 1 }$ CLK $end +$var wire 1 m% D $end +$var wire 1 K# RESET_B $end +$var wire 1 5D buf_Q $end +$var wire 1 6D RESET $end +$upscope $end +$upscope $end + +$scope module sky130_fd_sc_hd__dfrtp_1_1_ $end +$var wire 1 (% Q $end +$var wire 1 }$ CLK $end +$var wire 1 '% D $end +$var wire 1 K# RESET_B $end +$var supply1 1 7D VPWR $end +$var supply0 1 8D VGND $end +$var supply1 1 9D VPB $end +$var supply0 1 :D VNB $end + +$scope module base $end +$var wire 1 (% Q $end +$var wire 1 }$ CLK $end +$var wire 1 '% D $end +$var wire 1 K# RESET_B $end +$var wire 1 ;D buf_Q $end +$var wire 1 D VGND $end +$var supply1 1 ?D VPB $end +$var supply0 1 @D VNB $end + +$scope module base $end +$var wire 1 n% X $end +$var wire 1 (% A $end +$var wire 1 AD buf0_out_X $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mem_bottom_track_51 $end +$var wire 1 K# pReset [0] $end +$var wire 1 }$ prog_clk [0] $end +$var wire 1 n% ccff_head [0] $end +$var wire 1 o% ccff_tail [0] $end +$var wire 1 )% mem_out [0] $end +$var wire 1 *% mem_out [1] $end + +$scope module sky130_fd_sc_hd__dfrtp_1_0_ $end +$var wire 1 )% Q $end +$var wire 1 }$ CLK $end +$var wire 1 n% D $end +$var wire 1 K# RESET_B $end +$var supply1 1 BD VPWR $end +$var supply0 1 CD VGND $end +$var supply1 1 DD VPB $end +$var supply0 1 ED VNB $end + +$scope module base $end +$var wire 1 )% Q $end +$var wire 1 }$ CLK $end +$var wire 1 n% D $end +$var wire 1 K# RESET_B $end +$var wire 1 FD buf_Q $end +$var wire 1 GD RESET $end +$upscope $end +$upscope $end + +$scope module sky130_fd_sc_hd__dfrtp_1_1_ $end +$var wire 1 *% Q $end +$var wire 1 }$ CLK $end +$var wire 1 )% D $end +$var wire 1 K# RESET_B $end +$var supply1 1 HD VPWR $end +$var supply0 1 ID VGND $end +$var supply1 1 JD VPB $end +$var supply0 1 KD VNB $end + +$scope module base $end +$var wire 1 *% Q $end +$var wire 1 }$ CLK $end +$var wire 1 )% D $end +$var wire 1 K# RESET_B $end +$var wire 1 LD buf_Q $end +$var wire 1 MD RESET $end +$upscope $end +$upscope $end + +$scope module FTB_50__49 $end +$var wire 1 o% X $end +$var wire 1 *% A $end +$var supply1 1 ND VPWR $end +$var supply0 1 OD VGND $end +$var supply1 1 PD VPB $end +$var supply0 1 QD VNB $end + +$scope module base $end +$var wire 1 o% X $end +$var wire 1 *% A $end +$var wire 1 RD buf0_out_X $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mem_bottom_track_53 $end +$var wire 1 K# pReset [0] $end +$var wire 1 }$ prog_clk [0] $end +$var wire 1 o% ccff_head [0] $end +$var wire 1 p% ccff_tail [0] $end +$var wire 1 +% mem_out [0] $end +$var wire 1 ,% mem_out [1] $end + +$scope module sky130_fd_sc_hd__dfrtp_1_0_ $end +$var wire 1 +% Q $end +$var wire 1 }$ CLK $end +$var wire 1 o% D $end +$var wire 1 K# RESET_B $end +$var supply1 1 SD VPWR $end +$var supply0 1 TD VGND $end +$var supply1 1 UD VPB $end +$var supply0 1 VD VNB $end + +$scope module base $end +$var wire 1 +% Q $end +$var wire 1 }$ CLK $end +$var wire 1 o% D $end +$var wire 1 K# RESET_B $end +$var wire 1 WD buf_Q $end +$var wire 1 XD RESET $end +$upscope $end +$upscope $end + +$scope module sky130_fd_sc_hd__dfrtp_1_1_ $end +$var wire 1 ,% Q $end +$var wire 1 }$ CLK $end +$var wire 1 +% D $end +$var wire 1 K# RESET_B $end +$var supply1 1 YD VPWR $end +$var supply0 1 ZD VGND $end +$var supply1 1 [D VPB $end +$var supply0 1 \D VNB $end + +$scope module base $end +$var wire 1 ,% Q $end +$var wire 1 }$ CLK $end +$var wire 1 +% D $end +$var wire 1 K# RESET_B $end +$var wire 1 ]D buf_Q $end +$var wire 1 ^D RESET $end +$upscope $end +$upscope $end + +$scope module FTB_51__50 $end +$var wire 1 p% X $end +$var wire 1 ,% A $end +$var supply1 1 _D VPWR $end +$var supply0 1 `D VGND $end +$var supply1 1 aD VPB $end +$var supply0 1 bD VNB $end + +$scope module base $end +$var wire 1 p% X $end +$var wire 1 ,% A $end +$var wire 1 cD buf0_out_X $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mem_left_track_13 $end +$var wire 1 K# pReset [0] $end +$var wire 1 }$ prog_clk [0] $end +$var wire 1 o& ccff_head [0] $end +$var wire 1 q% ccff_tail [0] $end +$var wire 1 -% mem_out [0] $end +$var wire 1 .% mem_out [1] $end + +$scope module sky130_fd_sc_hd__dfrtp_1_0_ $end +$var wire 1 -% Q $end +$var wire 1 }$ CLK $end +$var wire 1 o& D $end +$var wire 1 K# RESET_B $end +$var supply1 1 dD VPWR $end +$var supply0 1 eD VGND $end +$var supply1 1 fD VPB $end +$var supply0 1 gD VNB $end + +$scope module base $end +$var wire 1 -% Q $end +$var wire 1 }$ CLK $end +$var wire 1 o& D $end +$var wire 1 K# RESET_B $end +$var wire 1 hD buf_Q $end +$var wire 1 iD RESET $end +$upscope $end +$upscope $end + +$scope module sky130_fd_sc_hd__dfrtp_1_1_ $end +$var wire 1 .% Q $end +$var wire 1 }$ CLK $end +$var wire 1 -% D $end +$var wire 1 K# RESET_B $end +$var supply1 1 jD VPWR $end +$var supply0 1 kD VGND $end +$var supply1 1 lD VPB $end +$var supply0 1 mD VNB $end + +$scope module base $end +$var wire 1 .% Q $end +$var wire 1 }$ CLK $end +$var wire 1 -% D $end +$var wire 1 K# RESET_B $end +$var wire 1 nD buf_Q $end +$var wire 1 oD RESET $end +$upscope $end +$upscope $end + +$scope module FTB_52__51 $end +$var wire 1 q% X $end +$var wire 1 .% A $end +$var supply1 1 pD VPWR $end +$var supply0 1 qD VGND $end +$var supply1 1 rD VPB $end +$var supply0 1 sD VNB $end + +$scope module base $end +$var wire 1 q% X $end +$var wire 1 .% A $end +$var wire 1 tD buf0_out_X $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mem_left_track_15 $end +$var wire 1 K# pReset [0] $end +$var wire 1 }$ prog_clk [0] $end +$var wire 1 q% ccff_head [0] $end +$var wire 1 r% ccff_tail [0] $end +$var wire 1 /% mem_out [0] $end +$var wire 1 0% mem_out [1] $end + +$scope module sky130_fd_sc_hd__dfrtp_1_0_ $end +$var wire 1 /% Q $end +$var wire 1 }$ CLK $end +$var wire 1 q% D $end +$var wire 1 K# RESET_B $end +$var supply1 1 uD VPWR $end +$var supply0 1 vD VGND $end +$var supply1 1 wD VPB $end +$var supply0 1 xD VNB $end + +$scope module base $end +$var wire 1 /% Q $end +$var wire 1 }$ CLK $end +$var wire 1 q% D $end +$var wire 1 K# RESET_B $end +$var wire 1 yD buf_Q $end +$var wire 1 zD RESET $end +$upscope $end +$upscope $end + +$scope module sky130_fd_sc_hd__dfrtp_1_1_ $end +$var wire 1 0% Q $end +$var wire 1 }$ CLK $end +$var wire 1 /% D $end +$var wire 1 K# RESET_B $end +$var supply1 1 {D VPWR $end +$var supply0 1 |D VGND $end +$var supply1 1 }D VPB $end +$var supply0 1 ~D VNB $end + +$scope module base $end +$var wire 1 0% Q $end +$var wire 1 }$ CLK $end +$var wire 1 /% D $end +$var wire 1 K# RESET_B $end +$var wire 1 !E buf_Q $end +$var wire 1 "E RESET $end +$upscope $end +$upscope $end + +$scope module FTB_53__52 $end +$var wire 1 r% X $end +$var wire 1 0% A $end +$var supply1 1 #E VPWR $end +$var supply0 1 $E VGND $end +$var supply1 1 %E VPB $end +$var supply0 1 &E VNB $end + +$scope module base $end +$var wire 1 r% X $end +$var wire 1 0% A $end +$var wire 1 'E buf0_out_X $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mem_left_track_17 $end +$var wire 1 K# pReset [0] $end +$var wire 1 }$ prog_clk [0] $end +$var wire 1 r% ccff_head [0] $end +$var wire 1 s% ccff_tail [0] $end +$var wire 1 1% mem_out [0] $end +$var wire 1 2% mem_out [1] $end + +$scope module sky130_fd_sc_hd__dfrtp_1_0_ $end +$var wire 1 1% Q $end +$var wire 1 }$ CLK $end +$var wire 1 r% D $end +$var wire 1 K# RESET_B $end +$var supply1 1 (E VPWR $end +$var supply0 1 )E VGND $end +$var supply1 1 *E VPB $end +$var supply0 1 +E VNB $end + +$scope module base $end +$var wire 1 1% Q $end +$var wire 1 }$ CLK $end +$var wire 1 r% D $end +$var wire 1 K# RESET_B $end +$var wire 1 ,E buf_Q $end +$var wire 1 -E RESET $end +$upscope $end +$upscope $end + +$scope module sky130_fd_sc_hd__dfrtp_1_1_ $end +$var wire 1 2% Q $end +$var wire 1 }$ CLK $end +$var wire 1 1% D $end +$var wire 1 K# RESET_B $end +$var supply1 1 .E VPWR $end +$var supply0 1 /E VGND $end +$var supply1 1 0E VPB $end +$var supply0 1 1E VNB $end + +$scope module base $end +$var wire 1 2% Q $end +$var wire 1 }$ CLK $end +$var wire 1 1% D $end +$var wire 1 K# RESET_B $end +$var wire 1 2E buf_Q $end +$var wire 1 3E RESET $end +$upscope $end +$upscope $end + +$scope module FTB_54__53 $end +$var wire 1 s% X $end +$var wire 1 2% A $end +$var supply1 1 4E VPWR $end +$var supply0 1 5E VGND $end +$var supply1 1 6E VPB $end +$var supply0 1 7E VNB $end + +$scope module base $end +$var wire 1 s% X $end +$var wire 1 2% A $end +$var wire 1 8E buf0_out_X $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mem_left_track_19 $end +$var wire 1 K# pReset [0] $end +$var wire 1 }$ prog_clk [0] $end +$var wire 1 s% ccff_head [0] $end +$var wire 1 t% ccff_tail [0] $end +$var wire 1 3% mem_out [0] $end +$var wire 1 4% mem_out [1] $end + +$scope module sky130_fd_sc_hd__dfrtp_1_0_ $end +$var wire 1 3% Q $end +$var wire 1 }$ CLK $end +$var wire 1 s% D $end +$var wire 1 K# RESET_B $end +$var supply1 1 9E VPWR $end +$var supply0 1 :E VGND $end +$var supply1 1 ;E VPB $end +$var supply0 1 E RESET $end +$upscope $end +$upscope $end + +$scope module sky130_fd_sc_hd__dfrtp_1_1_ $end +$var wire 1 4% Q $end +$var wire 1 }$ CLK $end +$var wire 1 3% D $end +$var wire 1 K# RESET_B $end +$var supply1 1 ?E VPWR $end +$var supply0 1 @E VGND $end +$var supply1 1 AE VPB $end +$var supply0 1 BE VNB $end + +$scope module base $end +$var wire 1 4% Q $end +$var wire 1 }$ CLK $end +$var wire 1 3% D $end +$var wire 1 K# RESET_B $end +$var wire 1 CE buf_Q $end +$var wire 1 DE RESET $end +$upscope $end +$upscope $end + +$scope module FTB_55__54 $end +$var wire 1 t% X $end +$var wire 1 4% A $end +$var supply1 1 EE VPWR $end +$var supply0 1 FE VGND $end +$var supply1 1 GE VPB $end +$var supply0 1 HE VNB $end + +$scope module base $end +$var wire 1 t% X $end +$var wire 1 4% A $end +$var wire 1 IE buf0_out_X $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mem_left_track_21 $end +$var wire 1 K# pReset [0] $end +$var wire 1 }$ prog_clk [0] $end +$var wire 1 t% ccff_head [0] $end +$var wire 1 u% ccff_tail [0] $end +$var wire 1 5% mem_out [0] $end +$var wire 1 6% mem_out [1] $end + +$scope module sky130_fd_sc_hd__dfrtp_1_0_ $end +$var wire 1 5% Q $end +$var wire 1 }$ CLK $end +$var wire 1 t% D $end +$var wire 1 K# RESET_B $end +$var supply1 1 JE VPWR $end +$var supply0 1 KE VGND $end +$var supply1 1 LE VPB $end +$var supply0 1 ME VNB $end + +$scope module base $end +$var wire 1 5% Q $end +$var wire 1 }$ CLK $end +$var wire 1 t% D $end +$var wire 1 K# RESET_B $end +$var wire 1 NE buf_Q $end +$var wire 1 OE RESET $end +$upscope $end +$upscope $end + +$scope module sky130_fd_sc_hd__dfrtp_1_1_ $end +$var wire 1 6% Q $end +$var wire 1 }$ CLK $end +$var wire 1 5% D $end +$var wire 1 K# RESET_B $end +$var supply1 1 PE VPWR $end +$var supply0 1 QE VGND $end +$var supply1 1 RE VPB $end +$var supply0 1 SE VNB $end + +$scope module base $end +$var wire 1 6% Q $end +$var wire 1 }$ CLK $end +$var wire 1 5% D $end +$var wire 1 K# RESET_B $end +$var wire 1 TE buf_Q $end +$var wire 1 UE RESET $end +$upscope $end +$upscope $end + +$scope module FTB_56__55 $end +$var wire 1 u% X $end +$var wire 1 6% A $end +$var supply1 1 VE VPWR $end +$var supply0 1 WE VGND $end +$var supply1 1 XE VPB $end +$var supply0 1 YE VNB $end + +$scope module base $end +$var wire 1 u% X $end +$var wire 1 6% A $end +$var wire 1 ZE buf0_out_X $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mem_left_track_23 $end +$var wire 1 K# pReset [0] $end +$var wire 1 }$ prog_clk [0] $end +$var wire 1 u% ccff_head [0] $end +$var wire 1 w% ccff_tail [0] $end +$var wire 1 9% mem_out [0] $end +$var wire 1 :% mem_out [1] $end + +$scope module sky130_fd_sc_hd__dfrtp_1_0_ $end +$var wire 1 9% Q $end +$var wire 1 }$ CLK $end +$var wire 1 u% D $end +$var wire 1 K# RESET_B $end +$var supply1 1 [E VPWR $end +$var supply0 1 \E VGND $end +$var supply1 1 ]E VPB $end +$var supply0 1 ^E VNB $end + +$scope module base $end +$var wire 1 9% Q $end +$var wire 1 }$ CLK $end +$var wire 1 u% D $end +$var wire 1 K# RESET_B $end +$var wire 1 _E buf_Q $end +$var wire 1 `E RESET $end +$upscope $end +$upscope $end + +$scope module sky130_fd_sc_hd__dfrtp_1_1_ $end +$var wire 1 :% Q $end +$var wire 1 }$ CLK $end +$var wire 1 9% D $end +$var wire 1 K# RESET_B $end +$var supply1 1 aE VPWR $end +$var supply0 1 bE VGND $end +$var supply1 1 cE VPB $end +$var supply0 1 dE VNB $end + +$scope module base $end +$var wire 1 :% Q $end +$var wire 1 }$ CLK $end +$var wire 1 9% D $end +$var wire 1 K# RESET_B $end +$var wire 1 eE buf_Q $end +$var wire 1 fE RESET $end +$upscope $end +$upscope $end + +$scope module FTB_57__56 $end +$var wire 1 w% X $end +$var wire 1 :% A $end +$var supply1 1 gE VPWR $end +$var supply0 1 hE VGND $end +$var supply1 1 iE VPB $end +$var supply0 1 jE VNB $end + +$scope module base $end +$var wire 1 w% X $end +$var wire 1 :% A $end +$var wire 1 kE buf0_out_X $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mem_left_track_25 $end +$var wire 1 K# pReset [0] $end +$var wire 1 }$ prog_clk [0] $end +$var wire 1 w% ccff_head [0] $end +$var wire 1 x% ccff_tail [0] $end +$var wire 1 ;% mem_out [0] $end +$var wire 1 <% mem_out [1] $end + +$scope module sky130_fd_sc_hd__dfrtp_1_0_ $end +$var wire 1 ;% Q $end +$var wire 1 }$ CLK $end +$var wire 1 w% D $end +$var wire 1 K# RESET_B $end +$var supply1 1 lE VPWR $end +$var supply0 1 mE VGND $end +$var supply1 1 nE VPB $end +$var supply0 1 oE VNB $end + +$scope module base $end +$var wire 1 ;% Q $end +$var wire 1 }$ CLK $end +$var wire 1 w% D $end +$var wire 1 K# RESET_B $end +$var wire 1 pE buf_Q $end +$var wire 1 qE RESET $end +$upscope $end +$upscope $end + +$scope module sky130_fd_sc_hd__dfrtp_1_1_ $end +$var wire 1 <% Q $end +$var wire 1 }$ CLK $end +$var wire 1 ;% D $end +$var wire 1 K# RESET_B $end +$var supply1 1 rE VPWR $end +$var supply0 1 sE VGND $end +$var supply1 1 tE VPB $end +$var supply0 1 uE VNB $end + +$scope module base $end +$var wire 1 <% Q $end +$var wire 1 }$ CLK $end +$var wire 1 ;% D $end +$var wire 1 K# RESET_B $end +$var wire 1 vE buf_Q $end +$var wire 1 wE RESET $end +$upscope $end +$upscope $end + +$scope module FTB_58__57 $end +$var wire 1 x% X $end +$var wire 1 <% A $end +$var supply1 1 xE VPWR $end +$var supply0 1 yE VGND $end +$var supply1 1 zE VPB $end +$var supply0 1 {E VNB $end + +$scope module base $end +$var wire 1 x% X $end +$var wire 1 <% A $end +$var wire 1 |E buf0_out_X $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mem_left_track_27 $end +$var wire 1 K# pReset [0] $end +$var wire 1 }$ prog_clk [0] $end +$var wire 1 x% ccff_head [0] $end +$var wire 1 y% ccff_tail [0] $end +$var wire 1 =% mem_out [0] $end +$var wire 1 >% mem_out [1] $end + +$scope module sky130_fd_sc_hd__dfrtp_1_0_ $end +$var wire 1 =% Q $end +$var wire 1 }$ CLK $end +$var wire 1 x% D $end +$var wire 1 K# RESET_B $end +$var supply1 1 }E VPWR $end +$var supply0 1 ~E VGND $end +$var supply1 1 !F VPB $end +$var supply0 1 "F VNB $end + +$scope module base $end +$var wire 1 =% Q $end +$var wire 1 }$ CLK $end +$var wire 1 x% D $end +$var wire 1 K# RESET_B $end +$var wire 1 #F buf_Q $end +$var wire 1 $F RESET $end +$upscope $end +$upscope $end + +$scope module sky130_fd_sc_hd__dfrtp_1_1_ $end +$var wire 1 >% Q $end +$var wire 1 }$ CLK $end +$var wire 1 =% D $end +$var wire 1 K# RESET_B $end +$var supply1 1 %F VPWR $end +$var supply0 1 &F VGND $end +$var supply1 1 'F VPB $end +$var supply0 1 (F VNB $end + +$scope module base $end +$var wire 1 >% Q $end +$var wire 1 }$ CLK $end +$var wire 1 =% D $end +$var wire 1 K# RESET_B $end +$var wire 1 )F buf_Q $end +$var wire 1 *F RESET $end +$upscope $end +$upscope $end + +$scope module FTB_59__58 $end +$var wire 1 y% X $end +$var wire 1 >% A $end +$var supply1 1 +F VPWR $end +$var supply0 1 ,F VGND $end +$var supply1 1 -F VPB $end +$var supply0 1 .F VNB $end + +$scope module base $end +$var wire 1 y% X $end +$var wire 1 >% A $end +$var wire 1 /F buf0_out_X $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mem_left_track_31 $end +$var wire 1 K# pReset [0] $end +$var wire 1 }$ prog_clk [0] $end +$var wire 1 ;& ccff_head [0] $end +$var wire 1 z% ccff_tail [0] $end +$var wire 1 ?% mem_out [0] $end +$var wire 1 @% mem_out [1] $end + +$scope module sky130_fd_sc_hd__dfrtp_1_0_ $end +$var wire 1 ?% Q $end +$var wire 1 }$ CLK $end +$var wire 1 ;& D $end +$var wire 1 K# RESET_B $end +$var supply1 1 0F VPWR $end +$var supply0 1 1F VGND $end +$var supply1 1 2F VPB $end +$var supply0 1 3F VNB $end + +$scope module base $end +$var wire 1 ?% Q $end +$var wire 1 }$ CLK $end +$var wire 1 ;& D $end +$var wire 1 K# RESET_B $end +$var wire 1 4F buf_Q $end +$var wire 1 5F RESET $end +$upscope $end +$upscope $end + +$scope module sky130_fd_sc_hd__dfrtp_1_1_ $end +$var wire 1 @% Q $end +$var wire 1 }$ CLK $end +$var wire 1 ?% D $end +$var wire 1 K# RESET_B $end +$var supply1 1 6F VPWR $end +$var supply0 1 7F VGND $end +$var supply1 1 8F VPB $end +$var supply0 1 9F VNB $end + +$scope module base $end +$var wire 1 @% Q $end +$var wire 1 }$ CLK $end +$var wire 1 ?% D $end +$var wire 1 K# RESET_B $end +$var wire 1 :F buf_Q $end +$var wire 1 ;F RESET $end +$upscope $end +$upscope $end + +$scope module FTB_60__59 $end +$var wire 1 z% X $end +$var wire 1 @% A $end +$var supply1 1 F VPB $end +$var supply0 1 ?F VNB $end + +$scope module base $end +$var wire 1 z% X $end +$var wire 1 @% A $end +$var wire 1 @F buf0_out_X $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mem_left_track_33 $end +$var wire 1 K# pReset [0] $end +$var wire 1 }$ prog_clk [0] $end +$var wire 1 z% ccff_head [0] $end +$var wire 1 {% ccff_tail [0] $end +$var wire 1 A% mem_out [0] $end +$var wire 1 B% mem_out [1] $end + +$scope module sky130_fd_sc_hd__dfrtp_1_0_ $end +$var wire 1 A% Q $end +$var wire 1 }$ CLK $end +$var wire 1 z% D $end +$var wire 1 K# RESET_B $end +$var supply1 1 AF VPWR $end +$var supply0 1 BF VGND $end +$var supply1 1 CF VPB $end +$var supply0 1 DF VNB $end + +$scope module base $end +$var wire 1 A% Q $end +$var wire 1 }$ CLK $end +$var wire 1 z% D $end +$var wire 1 K# RESET_B $end +$var wire 1 EF buf_Q $end +$var wire 1 FF RESET $end +$upscope $end +$upscope $end + +$scope module sky130_fd_sc_hd__dfrtp_1_1_ $end +$var wire 1 B% Q $end +$var wire 1 }$ CLK $end +$var wire 1 A% D $end +$var wire 1 K# RESET_B $end +$var supply1 1 GF VPWR $end +$var supply0 1 HF VGND $end +$var supply1 1 IF VPB $end +$var supply0 1 JF VNB $end + +$scope module base $end +$var wire 1 B% Q $end +$var wire 1 }$ CLK $end +$var wire 1 A% D $end +$var wire 1 K# RESET_B $end +$var wire 1 KF buf_Q $end +$var wire 1 LF RESET $end +$upscope $end +$upscope $end + +$scope module FTB_61__60 $end +$var wire 1 {% X $end +$var wire 1 B% A $end +$var supply1 1 MF VPWR $end +$var supply0 1 NF VGND $end +$var supply1 1 OF VPB $end +$var supply0 1 PF VNB $end + +$scope module base $end +$var wire 1 {% X $end +$var wire 1 B% A $end +$var wire 1 QF buf0_out_X $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mem_left_track_35 $end +$var wire 1 K# pReset [0] $end +$var wire 1 }$ prog_clk [0] $end +$var wire 1 {% ccff_head [0] $end +$var wire 1 |% ccff_tail [0] $end +$var wire 1 C% mem_out [0] $end +$var wire 1 D% mem_out [1] $end + +$scope module sky130_fd_sc_hd__dfrtp_1_0_ $end +$var wire 1 C% Q $end +$var wire 1 }$ CLK $end +$var wire 1 {% D $end +$var wire 1 K# RESET_B $end +$var supply1 1 RF VPWR $end +$var supply0 1 SF VGND $end +$var supply1 1 TF VPB $end +$var supply0 1 UF VNB $end + +$scope module base $end +$var wire 1 C% Q $end +$var wire 1 }$ CLK $end +$var wire 1 {% D $end +$var wire 1 K# RESET_B $end +$var wire 1 VF buf_Q $end +$var wire 1 WF RESET $end +$upscope $end +$upscope $end + +$scope module sky130_fd_sc_hd__dfrtp_1_1_ $end +$var wire 1 D% Q $end +$var wire 1 }$ CLK $end +$var wire 1 C% D $end +$var wire 1 K# RESET_B $end +$var supply1 1 XF VPWR $end +$var supply0 1 YF VGND $end +$var supply1 1 ZF VPB $end +$var supply0 1 [F VNB $end + +$scope module base $end +$var wire 1 D% Q $end +$var wire 1 }$ CLK $end +$var wire 1 C% D $end +$var wire 1 K# RESET_B $end +$var wire 1 \F buf_Q $end +$var wire 1 ]F RESET $end +$upscope $end +$upscope $end + +$scope module FTB_62__61 $end +$var wire 1 |% X $end +$var wire 1 D% A $end +$var supply1 1 ^F VPWR $end +$var supply0 1 _F VGND $end +$var supply1 1 `F VPB $end +$var supply0 1 aF VNB $end + +$scope module base $end +$var wire 1 |% X $end +$var wire 1 D% A $end +$var wire 1 bF buf0_out_X $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mem_left_track_37 $end +$var wire 1 K# pReset [0] $end +$var wire 1 }$ prog_clk [0] $end +$var wire 1 |% ccff_head [0] $end +$var wire 1 }% ccff_tail [0] $end +$var wire 1 E% mem_out [0] $end +$var wire 1 F% mem_out [1] $end + +$scope module sky130_fd_sc_hd__dfrtp_1_0_ $end +$var wire 1 E% Q $end +$var wire 1 }$ CLK $end +$var wire 1 |% D $end +$var wire 1 K# RESET_B $end +$var supply1 1 cF VPWR $end +$var supply0 1 dF VGND $end +$var supply1 1 eF VPB $end +$var supply0 1 fF VNB $end + +$scope module base $end +$var wire 1 E% Q $end +$var wire 1 }$ CLK $end +$var wire 1 |% D $end +$var wire 1 K# RESET_B $end +$var wire 1 gF buf_Q $end +$var wire 1 hF RESET $end +$upscope $end +$upscope $end + +$scope module sky130_fd_sc_hd__dfrtp_1_1_ $end +$var wire 1 F% Q $end +$var wire 1 }$ CLK $end +$var wire 1 E% D $end +$var wire 1 K# RESET_B $end +$var supply1 1 iF VPWR $end +$var supply0 1 jF VGND $end +$var supply1 1 kF VPB $end +$var supply0 1 lF VNB $end + +$scope module base $end +$var wire 1 F% Q $end +$var wire 1 }$ CLK $end +$var wire 1 E% D $end +$var wire 1 K# RESET_B $end +$var wire 1 mF buf_Q $end +$var wire 1 nF RESET $end +$upscope $end +$upscope $end + +$scope module FTB_63__62 $end +$var wire 1 }% X $end +$var wire 1 F% A $end +$var supply1 1 oF VPWR $end +$var supply0 1 pF VGND $end +$var supply1 1 qF VPB $end +$var supply0 1 rF VNB $end + +$scope module base $end +$var wire 1 }% X $end +$var wire 1 F% A $end +$var wire 1 sF buf0_out_X $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mem_left_track_39 $end +$var wire 1 K# pReset [0] $end +$var wire 1 }$ prog_clk [0] $end +$var wire 1 }% ccff_head [0] $end +$var wire 1 ~% ccff_tail [0] $end +$var wire 1 G% mem_out [0] $end +$var wire 1 H% mem_out [1] $end + +$scope module sky130_fd_sc_hd__dfrtp_1_0_ $end +$var wire 1 G% Q $end +$var wire 1 }$ CLK $end +$var wire 1 }% D $end +$var wire 1 K# RESET_B $end +$var supply1 1 tF VPWR $end +$var supply0 1 uF VGND $end +$var supply1 1 vF VPB $end +$var supply0 1 wF VNB $end + +$scope module base $end +$var wire 1 G% Q $end +$var wire 1 }$ CLK $end +$var wire 1 }% D $end +$var wire 1 K# RESET_B $end +$var wire 1 xF buf_Q $end +$var wire 1 yF RESET $end +$upscope $end +$upscope $end + +$scope module sky130_fd_sc_hd__dfrtp_1_1_ $end +$var wire 1 H% Q $end +$var wire 1 }$ CLK $end +$var wire 1 G% D $end +$var wire 1 K# RESET_B $end +$var supply1 1 zF VPWR $end +$var supply0 1 {F VGND $end +$var supply1 1 |F VPB $end +$var supply0 1 }F VNB $end + +$scope module base $end +$var wire 1 H% Q $end +$var wire 1 }$ CLK $end +$var wire 1 G% D $end +$var wire 1 K# RESET_B $end +$var wire 1 ~F buf_Q $end +$var wire 1 !G RESET $end +$upscope $end +$upscope $end + +$scope module FTB_64__63 $end +$var wire 1 ~% X $end +$var wire 1 H% A $end +$var supply1 1 "G VPWR $end +$var supply0 1 #G VGND $end +$var supply1 1 $G VPB $end +$var supply0 1 %G VNB $end + +$scope module base $end +$var wire 1 ~% X $end +$var wire 1 H% A $end +$var wire 1 &G buf0_out_X $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mem_left_track_41 $end +$var wire 1 K# pReset [0] $end +$var wire 1 }$ prog_clk [0] $end +$var wire 1 ~% ccff_head [0] $end +$var wire 1 !& ccff_tail [0] $end +$var wire 1 I% mem_out [0] $end +$var wire 1 J% mem_out [1] $end + +$scope module sky130_fd_sc_hd__dfrtp_1_0_ $end +$var wire 1 I% Q $end +$var wire 1 }$ CLK $end +$var wire 1 ~% D $end +$var wire 1 K# RESET_B $end +$var supply1 1 'G VPWR $end +$var supply0 1 (G VGND $end +$var supply1 1 )G VPB $end +$var supply0 1 *G VNB $end + +$scope module base $end +$var wire 1 I% Q $end +$var wire 1 }$ CLK $end +$var wire 1 ~% D $end +$var wire 1 K# RESET_B $end +$var wire 1 +G buf_Q $end +$var wire 1 ,G RESET $end +$upscope $end +$upscope $end + +$scope module sky130_fd_sc_hd__dfrtp_1_1_ $end +$var wire 1 J% Q $end +$var wire 1 }$ CLK $end +$var wire 1 I% D $end +$var wire 1 K# RESET_B $end +$var supply1 1 -G VPWR $end +$var supply0 1 .G VGND $end +$var supply1 1 /G VPB $end +$var supply0 1 0G VNB $end + +$scope module base $end +$var wire 1 J% Q $end +$var wire 1 }$ CLK $end +$var wire 1 I% D $end +$var wire 1 K# RESET_B $end +$var wire 1 1G buf_Q $end +$var wire 1 2G RESET $end +$upscope $end +$upscope $end + +$scope module FTB_65__64 $end +$var wire 1 !& X $end +$var wire 1 J% A $end +$var supply1 1 3G VPWR $end +$var supply0 1 4G VGND $end +$var supply1 1 5G VPB $end +$var supply0 1 6G VNB $end + +$scope module base $end +$var wire 1 !& X $end +$var wire 1 J% A $end +$var wire 1 7G buf0_out_X $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mem_left_track_43 $end +$var wire 1 K# pReset [0] $end +$var wire 1 }$ prog_clk [0] $end +$var wire 1 !& ccff_head [0] $end +$var wire 1 "& ccff_tail [0] $end +$var wire 1 K% mem_out [0] $end +$var wire 1 L% mem_out [1] $end + +$scope module sky130_fd_sc_hd__dfrtp_1_0_ $end +$var wire 1 K% Q $end +$var wire 1 }$ CLK $end +$var wire 1 !& D $end +$var wire 1 K# RESET_B $end +$var supply1 1 8G VPWR $end +$var supply0 1 9G VGND $end +$var supply1 1 :G VPB $end +$var supply0 1 ;G VNB $end + +$scope module base $end +$var wire 1 K% Q $end +$var wire 1 }$ CLK $end +$var wire 1 !& D $end +$var wire 1 K# RESET_B $end +$var wire 1 G VPWR $end +$var supply0 1 ?G VGND $end +$var supply1 1 @G VPB $end +$var supply0 1 AG VNB $end + +$scope module base $end +$var wire 1 L% Q $end +$var wire 1 }$ CLK $end +$var wire 1 K% D $end +$var wire 1 K# RESET_B $end +$var wire 1 BG buf_Q $end +$var wire 1 CG RESET $end +$upscope $end +$upscope $end + +$scope module FTB_66__65 $end +$var wire 1 "& X $end +$var wire 1 L% A $end +$var supply1 1 DG VPWR $end +$var supply0 1 EG VGND $end +$var supply1 1 FG VPB $end +$var supply0 1 GG VNB $end + +$scope module base $end +$var wire 1 "& X $end +$var wire 1 L% A $end +$var wire 1 HG buf0_out_X $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mem_left_track_45 $end +$var wire 1 K# pReset [0] $end +$var wire 1 }$ prog_clk [0] $end +$var wire 1 "& ccff_head [0] $end +$var wire 1 $& ccff_tail [0] $end +$var wire 1 O% mem_out [0] $end +$var wire 1 P% mem_out [1] $end + +$scope module sky130_fd_sc_hd__dfrtp_1_0_ $end +$var wire 1 O% Q $end +$var wire 1 }$ CLK $end +$var wire 1 "& D $end +$var wire 1 K# RESET_B $end +$var supply1 1 IG VPWR $end +$var supply0 1 JG VGND $end +$var supply1 1 KG VPB $end +$var supply0 1 LG VNB $end + +$scope module base $end +$var wire 1 O% Q $end +$var wire 1 }$ CLK $end +$var wire 1 "& D $end +$var wire 1 K# RESET_B $end +$var wire 1 MG buf_Q $end +$var wire 1 NG RESET $end +$upscope $end +$upscope $end + +$scope module sky130_fd_sc_hd__dfrtp_1_1_ $end +$var wire 1 P% Q $end +$var wire 1 }$ CLK $end +$var wire 1 O% D $end +$var wire 1 K# RESET_B $end +$var supply1 1 OG VPWR $end +$var supply0 1 PG VGND $end +$var supply1 1 QG VPB $end +$var supply0 1 RG VNB $end + +$scope module base $end +$var wire 1 P% Q $end +$var wire 1 }$ CLK $end +$var wire 1 O% D $end +$var wire 1 K# RESET_B $end +$var wire 1 SG buf_Q $end +$var wire 1 TG RESET $end +$upscope $end +$upscope $end + +$scope module FTB_67__66 $end +$var wire 1 $& X $end +$var wire 1 P% A $end +$var supply1 1 UG VPWR $end +$var supply0 1 VG VGND $end +$var supply1 1 WG VPB $end +$var supply0 1 XG VNB $end + +$scope module base $end +$var wire 1 $& X $end +$var wire 1 P% A $end +$var wire 1 YG buf0_out_X $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mem_left_track_47 $end +$var wire 1 K# pReset [0] $end +$var wire 1 }$ prog_clk [0] $end +$var wire 1 $& ccff_head [0] $end +$var wire 1 %& ccff_tail [0] $end +$var wire 1 Q% mem_out [0] $end +$var wire 1 R% mem_out [1] $end + +$scope module sky130_fd_sc_hd__dfrtp_1_0_ $end +$var wire 1 Q% Q $end +$var wire 1 }$ CLK $end +$var wire 1 $& D $end +$var wire 1 K# RESET_B $end +$var supply1 1 ZG VPWR $end +$var supply0 1 [G VGND $end +$var supply1 1 \G VPB $end +$var supply0 1 ]G VNB $end + +$scope module base $end +$var wire 1 Q% Q $end +$var wire 1 }$ CLK $end +$var wire 1 $& D $end +$var wire 1 K# RESET_B $end +$var wire 1 ^G buf_Q $end +$var wire 1 _G RESET $end +$upscope $end +$upscope $end + +$scope module sky130_fd_sc_hd__dfrtp_1_1_ $end +$var wire 1 R% Q $end +$var wire 1 }$ CLK $end +$var wire 1 Q% D $end +$var wire 1 K# RESET_B $end +$var supply1 1 `G VPWR $end +$var supply0 1 aG VGND $end +$var supply1 1 bG VPB $end +$var supply0 1 cG VNB $end + +$scope module base $end +$var wire 1 R% Q $end +$var wire 1 }$ CLK $end +$var wire 1 Q% D $end +$var wire 1 K# RESET_B $end +$var wire 1 dG buf_Q $end +$var wire 1 eG RESET $end +$upscope $end +$upscope $end + +$scope module FTB_68__67 $end +$var wire 1 %& X $end +$var wire 1 R% A $end +$var supply1 1 fG VPWR $end +$var supply0 1 gG VGND $end +$var supply1 1 hG VPB $end +$var supply0 1 iG VNB $end + +$scope module base $end +$var wire 1 %& X $end +$var wire 1 R% A $end +$var wire 1 jG buf0_out_X $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mem_left_track_49 $end +$var wire 1 K# pReset [0] $end +$var wire 1 }$ prog_clk [0] $end +$var wire 1 %& ccff_head [0] $end +$var wire 1 && ccff_tail [0] $end +$var wire 1 S% mem_out [0] $end +$var wire 1 T% mem_out [1] $end + +$scope module sky130_fd_sc_hd__dfrtp_1_0_ $end +$var wire 1 S% Q $end +$var wire 1 }$ CLK $end +$var wire 1 %& D $end +$var wire 1 K# RESET_B $end +$var supply1 1 kG VPWR $end +$var supply0 1 lG VGND $end +$var supply1 1 mG VPB $end +$var supply0 1 nG VNB $end + +$scope module base $end +$var wire 1 S% Q $end +$var wire 1 }$ CLK $end +$var wire 1 %& D $end +$var wire 1 K# RESET_B $end +$var wire 1 oG buf_Q $end +$var wire 1 pG RESET $end +$upscope $end +$upscope $end + +$scope module sky130_fd_sc_hd__dfrtp_1_1_ $end +$var wire 1 T% Q $end +$var wire 1 }$ CLK $end +$var wire 1 S% D $end +$var wire 1 K# RESET_B $end +$var supply1 1 qG VPWR $end +$var supply0 1 rG VGND $end +$var supply1 1 sG VPB $end +$var supply0 1 tG VNB $end + +$scope module base $end +$var wire 1 T% Q $end +$var wire 1 }$ CLK $end +$var wire 1 S% D $end +$var wire 1 K# RESET_B $end +$var wire 1 uG buf_Q $end +$var wire 1 vG RESET $end +$upscope $end +$upscope $end + +$scope module FTB_69__68 $end +$var wire 1 && X $end +$var wire 1 T% A $end +$var supply1 1 wG VPWR $end +$var supply0 1 xG VGND $end +$var supply1 1 yG VPB $end +$var supply0 1 zG VNB $end + +$scope module base $end +$var wire 1 && X $end +$var wire 1 T% A $end +$var wire 1 {G buf0_out_X $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mem_left_track_51 $end +$var wire 1 K# pReset [0] $end +$var wire 1 }$ prog_clk [0] $end +$var wire 1 && ccff_head [0] $end +$var wire 1 '& ccff_tail [0] $end +$var wire 1 U% mem_out [0] $end +$var wire 1 V% mem_out [1] $end + +$scope module sky130_fd_sc_hd__dfrtp_1_0_ $end +$var wire 1 U% Q $end +$var wire 1 }$ CLK $end +$var wire 1 && D $end +$var wire 1 K# RESET_B $end +$var supply1 1 |G VPWR $end +$var supply0 1 }G VGND $end +$var supply1 1 ~G VPB $end +$var supply0 1 !H VNB $end + +$scope module base $end +$var wire 1 U% Q $end +$var wire 1 }$ CLK $end +$var wire 1 && D $end +$var wire 1 K# RESET_B $end +$var wire 1 "H buf_Q $end +$var wire 1 #H RESET $end +$upscope $end +$upscope $end + +$scope module sky130_fd_sc_hd__dfrtp_1_1_ $end +$var wire 1 V% Q $end +$var wire 1 }$ CLK $end +$var wire 1 U% D $end +$var wire 1 K# RESET_B $end +$var supply1 1 $H VPWR $end +$var supply0 1 %H VGND $end +$var supply1 1 &H VPB $end +$var supply0 1 'H VNB $end + +$scope module base $end +$var wire 1 V% Q $end +$var wire 1 }$ CLK $end +$var wire 1 U% D $end +$var wire 1 K# RESET_B $end +$var wire 1 (H buf_Q $end +$var wire 1 )H RESET $end +$upscope $end +$upscope $end + +$scope module FTB_70__69 $end +$var wire 1 '& X $end +$var wire 1 V% A $end +$var supply1 1 *H VPWR $end +$var supply0 1 +H VGND $end +$var supply1 1 ,H VPB $end +$var supply0 1 -H VNB $end + +$scope module base $end +$var wire 1 '& X $end +$var wire 1 V% A $end +$var wire 1 .H buf0_out_X $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mem_left_track_55 $end +$var wire 1 K# pReset [0] $end +$var wire 1 }$ prog_clk [0] $end +$var wire 1 <& ccff_head [0] $end +$var wire 1 (& ccff_tail [0] $end +$var wire 1 W% mem_out [0] $end +$var wire 1 X% mem_out [1] $end + +$scope module sky130_fd_sc_hd__dfrtp_1_0_ $end +$var wire 1 W% Q $end +$var wire 1 }$ CLK $end +$var wire 1 <& D $end +$var wire 1 K# RESET_B $end +$var supply1 1 /H VPWR $end +$var supply0 1 0H VGND $end +$var supply1 1 1H VPB $end +$var supply0 1 2H VNB $end + +$scope module base $end +$var wire 1 W% Q $end +$var wire 1 }$ CLK $end +$var wire 1 <& D $end +$var wire 1 K# RESET_B $end +$var wire 1 3H buf_Q $end +$var wire 1 4H RESET $end +$upscope $end +$upscope $end + +$scope module sky130_fd_sc_hd__dfrtp_1_1_ $end +$var wire 1 X% Q $end +$var wire 1 }$ CLK $end +$var wire 1 W% D $end +$var wire 1 K# RESET_B $end +$var supply1 1 5H VPWR $end +$var supply0 1 6H VGND $end +$var supply1 1 7H VPB $end +$var supply0 1 8H VNB $end + +$scope module base $end +$var wire 1 X% Q $end +$var wire 1 }$ CLK $end +$var wire 1 W% D $end +$var wire 1 K# RESET_B $end +$var wire 1 9H buf_Q $end +$var wire 1 :H RESET $end +$upscope $end +$upscope $end + +$scope module FTB_71__70 $end +$var wire 1 (& X $end +$var wire 1 X% A $end +$var supply1 1 ;H VPWR $end +$var supply0 1 H VNB $end + +$scope module base $end +$var wire 1 (& X $end +$var wire 1 X% A $end +$var wire 1 ?H buf0_out_X $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mem_left_track_57 $end +$var wire 1 K# pReset [0] $end +$var wire 1 }$ prog_clk [0] $end +$var wire 1 (& ccff_head [0] $end +$var wire 1 )& ccff_tail [0] $end +$var wire 1 Y% mem_out [0] $end +$var wire 1 Z% mem_out [1] $end + +$scope module sky130_fd_sc_hd__dfrtp_1_0_ $end +$var wire 1 Y% Q $end +$var wire 1 }$ CLK $end +$var wire 1 (& D $end +$var wire 1 K# RESET_B $end +$var supply1 1 @H VPWR $end +$var supply0 1 AH VGND $end +$var supply1 1 BH VPB $end +$var supply0 1 CH VNB $end + +$scope module base $end +$var wire 1 Y% Q $end +$var wire 1 }$ CLK $end +$var wire 1 (& D $end +$var wire 1 K# RESET_B $end +$var wire 1 DH buf_Q $end +$var wire 1 EH RESET $end +$upscope $end +$upscope $end + +$scope module sky130_fd_sc_hd__dfrtp_1_1_ $end +$var wire 1 Z% Q $end +$var wire 1 }$ CLK $end +$var wire 1 Y% D $end +$var wire 1 K# RESET_B $end +$var supply1 1 FH VPWR $end +$var supply0 1 GH VGND $end +$var supply1 1 HH VPB $end +$var supply0 1 IH VNB $end + +$scope module base $end +$var wire 1 Z% Q $end +$var wire 1 }$ CLK $end +$var wire 1 Y% D $end +$var wire 1 K# RESET_B $end +$var wire 1 JH buf_Q $end +$var wire 1 KH RESET $end +$upscope $end +$upscope $end + +$scope module FTB_72__71 $end +$var wire 1 )& X $end +$var wire 1 Z% A $end +$var supply1 1 LH VPWR $end +$var supply0 1 MH VGND $end +$var supply1 1 NH VPB $end +$var supply0 1 OH VNB $end + +$scope module base $end +$var wire 1 )& X $end +$var wire 1 Z% A $end +$var wire 1 PH buf0_out_X $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mem_left_track_59 $end +$var wire 1 K# pReset [0] $end +$var wire 1 }$ prog_clk [0] $end +$var wire 1 )& ccff_head [0] $end +$var wire 1 y$ ccff_tail [0] $end +$var wire 1 [% mem_out [0] $end +$var wire 1 \% mem_out [1] $end +$var wire 1 QH copt_net_180 $end +$var wire 1 RH copt_net_182 $end +$var wire 1 SH copt_net_181 $end +$var wire 1 TH copt_net_185 $end +$var wire 1 UH copt_net_184 $end +$var wire 1 VH copt_net_183 $end + +$scope module sky130_fd_sc_hd__dfrtp_1_0_ $end +$var wire 1 [% Q $end +$var wire 1 }$ CLK $end +$var wire 1 )& D $end +$var wire 1 K# RESET_B $end +$var supply1 1 WH VPWR $end +$var supply0 1 XH VGND $end +$var supply1 1 YH VPB $end +$var supply0 1 ZH VNB $end + +$scope module base $end +$var wire 1 [% Q $end +$var wire 1 }$ CLK $end +$var wire 1 )& D $end +$var wire 1 K# RESET_B $end +$var wire 1 [H buf_Q $end +$var wire 1 \H RESET $end +$upscope $end +$upscope $end + +$scope module sky130_fd_sc_hd__dfrtp_1_1_ $end +$var wire 1 QH Q $end +$var wire 1 }$ CLK $end +$var wire 1 [% D $end +$var wire 1 K# RESET_B $end +$var supply1 1 ]H VPWR $end +$var supply0 1 ^H VGND $end +$var supply1 1 _H VPB $end +$var supply0 1 `H VNB $end + +$scope module base $end +$var wire 1 QH Q $end +$var wire 1 }$ CLK $end +$var wire 1 [% D $end +$var wire 1 K# RESET_B $end +$var wire 1 aH buf_Q $end +$var wire 1 bH RESET $end +$upscope $end +$upscope $end + +$scope module FTB_73__72 $end +$var wire 1 y$ X $end +$var wire 1 \% A $end +$var supply1 1 cH VPWR $end +$var supply0 1 dH VGND $end +$var supply1 1 eH VPB $end +$var supply0 1 fH VNB $end + +$scope module base $end +$var wire 1 y$ X $end +$var wire 1 \% A $end +$var wire 1 gH buf0_out_X $end +$upscope $end +$upscope $end + +$scope module copt_h_inst_1376 $end +$var wire 1 \% X $end +$var wire 1 RH A $end +$var supply1 1 hH VPWR $end +$var supply0 1 iH VGND $end +$var supply1 1 jH VPB $end +$var supply0 1 kH VNB $end + +$scope module base $end +$var wire 1 \% X $end +$var wire 1 RH A $end +$var wire 1 lH buf0_out_X $end +$upscope $end +$upscope $end + +$scope module copt_h_inst_1377 $end +$var wire 1 SH X $end +$var wire 1 QH A $end +$var supply1 1 mH VPWR $end +$var supply0 1 nH VGND $end +$var supply1 1 oH VPB $end +$var supply0 1 pH VNB $end + +$scope module base $end +$var wire 1 SH X $end +$var wire 1 QH A $end +$var wire 1 qH buf0_out_X $end +$upscope $end +$upscope $end + +$scope module copt_h_inst_1378 $end +$var wire 1 RH X $end +$var wire 1 TH A $end +$var supply1 1 rH VPWR $end +$var supply0 1 sH VGND $end +$var supply1 1 tH VPB $end +$var supply0 1 uH VNB $end + +$scope module base $end +$var wire 1 RH X $end +$var wire 1 TH A $end +$var wire 1 vH buf0_out_X $end +$upscope $end +$upscope $end + +$scope module copt_h_inst_1379 $end +$var wire 1 VH X $end +$var wire 1 UH A $end +$var supply1 1 wH VPWR $end +$var supply0 1 xH VGND $end +$var supply1 1 yH VPB $end +$var supply0 1 zH VNB $end + +$scope module base $end +$var wire 1 VH X $end +$var wire 1 UH A $end +$var wire 1 {H buf0_out_X $end +$upscope $end +$upscope $end + +$scope module copt_h_inst_1380 $end +$var wire 1 UH X $end +$var wire 1 SH A $end +$var supply1 1 |H VPWR $end +$var supply0 1 }H VGND $end +$var supply1 1 ~H VPB $end +$var supply0 1 !I VNB $end + +$scope module base $end +$var wire 1 UH X $end +$var wire 1 SH A $end +$var wire 1 "I buf0_out_X $end +$upscope $end +$upscope $end + +$scope module copt_h_inst_1381 $end +$var wire 1 TH X $end +$var wire 1 VH A $end +$var supply1 1 #I VPWR $end +$var supply0 1 $I VGND $end +$var supply1 1 %I VPB $end +$var supply0 1 &I VNB $end + +$scope module base $end +$var wire 1 TH X $end +$var wire 1 VH A $end +$var wire 1 'I buf0_out_X $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mux_bottom_track_29 $end +$var wire 1 j# in [0] $end +$var wire 1 r# in [1] $end +$var wire 1 $$ in [2] $end +$var wire 1 1& sram [0] $end +$var wire 1 2& sram [1] $end +$var wire 1 =( sram_inv [0] $end +$var wire 1 >( sram_inv [1] $end +$var wire 1 K$ out [0] $end +$var wire 1 1' p0 $end +$var wire 1 (I mux_2level_tapbuf_basis_input2_mem1_0_out [0] $end +$var wire 1 )I mux_2level_tapbuf_basis_input2_mem1_1_out [0] $end +$var wire 1 *I mux_2level_tapbuf_basis_input2_mem1_2_out [0] $end +$var wire 1 +I SYNOPSYS_UNCONNECTED_1 $end +$var wire 1 ,I SYNOPSYS_UNCONNECTED_2 $end +$var wire 1 -I SYNOPSYS_UNCONNECTED_3 $end +$var wire 1 .I SYNOPSYS_UNCONNECTED_4 $end +$var wire 1 /I BUF_net_171 $end + +$scope module mux_l1_in_0_ $end +$var wire 1 j# in [0] $end +$var wire 1 r# in [1] $end +$var wire 1 1& mem [0] $end +$var wire 1 +I mem_inv [0] $end +$var wire 1 (I out [0] $end + +$scope module sky130_fd_sc_hd__mux2_1_0 $end +$var wire 1 (I X $end +$var wire 1 r# A0 $end +$var wire 1 j# A1 $end +$var wire 1 1& S $end +$var supply1 1 0I VPWR $end +$var supply0 1 1I VGND $end +$var supply1 1 2I VPB $end +$var supply0 1 3I VNB $end + +$scope module base $end +$var wire 1 (I X $end +$var wire 1 r# A0 $end +$var wire 1 j# A1 $end +$var wire 1 1& S $end +$var wire 1 4I mux_2to10_out_X $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mux_l1_in_1_ $end +$var wire 1 $$ in [0] $end +$var wire 1 ,I in [1] $end +$var wire 1 1& mem [0] $end +$var wire 1 -I mem_inv [0] $end +$var wire 1 )I out [0] $end +$var wire 1 1' p0 $end + +$scope module sky130_fd_sc_hd__mux2_1_0 $end +$var wire 1 )I X $end +$var wire 1 1' A0 $end +$var wire 1 $$ A1 $end +$var wire 1 1& S $end +$var supply1 1 5I VPWR $end +$var supply0 1 6I VGND $end +$var supply1 1 7I VPB $end +$var supply0 1 8I VNB $end + +$scope module base $end +$var wire 1 )I X $end +$var wire 1 1' A0 $end +$var wire 1 $$ A1 $end +$var wire 1 1& S $end +$var wire 1 9I mux_2to10_out_X $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mux_l2_in_0_ $end +$var wire 1 (I in [0] $end +$var wire 1 )I in [1] $end +$var wire 1 2& mem [0] $end +$var wire 1 .I mem_inv [0] $end +$var wire 1 *I out [0] $end + +$scope module sky130_fd_sc_hd__mux2_1_0 $end +$var wire 1 *I X $end +$var wire 1 )I A0 $end +$var wire 1 (I A1 $end +$var wire 1 2& S $end +$var supply1 1 :I VPWR $end +$var supply0 1 ;I VGND $end +$var supply1 1 I mux_2to10_out_X $end +$upscope $end +$upscope $end +$upscope $end + +$scope module BINV_R_170 $end +$var wire 1 K$ Y $end +$var wire 1 /I A $end +$var supply1 1 ?I VPWR $end +$var supply0 1 @I VGND $end +$var supply1 1 AI VPB $end +$var supply0 1 BI VNB $end + +$scope module base $end +$var wire 1 K$ Y $end +$var wire 1 /I A $end +$var wire 1 CI not0_out_Y $end +$upscope $end +$upscope $end + +$scope module BINV_R_171 $end +$var wire 1 /I Y $end +$var wire 1 *I A $end +$var supply1 1 DI VPWR $end +$var supply0 1 EI VGND $end +$var supply1 1 FI VPB $end +$var supply0 1 GI VNB $end + +$scope module base $end +$var wire 1 /I Y $end +$var wire 1 *I A $end +$var wire 1 HI not0_out_Y $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mux_bottom_track_45 $end +$var wire 1 j# in [0] $end +$var wire 1 n# in [1] $end +$var wire 1 ,$ in [2] $end +$var wire 1 3& sram [0] $end +$var wire 1 4& sram [1] $end +$var wire 1 ?( sram_inv [0] $end +$var wire 1 @( sram_inv [1] $end +$var wire 1 S$ out [0] $end +$var wire 1 R' p0 $end +$var wire 1 II mux_2level_tapbuf_basis_input2_mem1_0_out [0] $end +$var wire 1 JI mux_2level_tapbuf_basis_input2_mem1_1_out [0] $end +$var wire 1 KI mux_2level_tapbuf_basis_input2_mem1_2_out [0] $end +$var wire 1 LI SYNOPSYS_UNCONNECTED_1 $end +$var wire 1 MI SYNOPSYS_UNCONNECTED_2 $end +$var wire 1 NI SYNOPSYS_UNCONNECTED_3 $end +$var wire 1 OI SYNOPSYS_UNCONNECTED_4 $end + +$scope module sky130_fd_sc_hd__buf_4_0_ $end +$var wire 1 S$ X $end +$var wire 1 KI A $end +$var supply1 1 PI VPWR $end +$var supply0 1 QI VGND $end +$var supply1 1 RI VPB $end +$var supply0 1 SI VNB $end + +$scope module base $end +$var wire 1 S$ X $end +$var wire 1 KI A $end +$var wire 1 TI buf0_out_X $end +$upscope $end +$upscope $end + +$scope module mux_l1_in_0_ $end +$var wire 1 j# in [0] $end +$var wire 1 n# in [1] $end +$var wire 1 3& mem [0] $end +$var wire 1 LI mem_inv [0] $end +$var wire 1 II out [0] $end + +$scope module sky130_fd_sc_hd__mux2_1_0 $end +$var wire 1 II X $end +$var wire 1 n# A0 $end +$var wire 1 j# A1 $end +$var wire 1 3& S $end +$var supply1 1 UI VPWR $end +$var supply0 1 VI VGND $end +$var supply1 1 WI VPB $end +$var supply0 1 XI VNB $end + +$scope module base $end +$var wire 1 II X $end +$var wire 1 n# A0 $end +$var wire 1 j# A1 $end +$var wire 1 3& S $end +$var wire 1 YI mux_2to10_out_X $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mux_l1_in_1_ $end +$var wire 1 ,$ in [0] $end +$var wire 1 MI in [1] $end +$var wire 1 3& mem [0] $end +$var wire 1 NI mem_inv [0] $end +$var wire 1 JI out [0] $end +$var wire 1 R' p0 $end + +$scope module sky130_fd_sc_hd__mux2_1_0 $end +$var wire 1 JI X $end +$var wire 1 R' A0 $end +$var wire 1 ,$ A1 $end +$var wire 1 3& S $end +$var supply1 1 ZI VPWR $end +$var supply0 1 [I VGND $end +$var supply1 1 \I VPB $end +$var supply0 1 ]I VNB $end + +$scope module base $end +$var wire 1 JI X $end +$var wire 1 R' A0 $end +$var wire 1 ,$ A1 $end +$var wire 1 3& S $end +$var wire 1 ^I mux_2to10_out_X $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mux_l2_in_0_ $end +$var wire 1 II in [0] $end +$var wire 1 JI in [1] $end +$var wire 1 4& mem [0] $end +$var wire 1 OI mem_inv [0] $end +$var wire 1 KI out [0] $end + +$scope module sky130_fd_sc_hd__mux2_1_0 $end +$var wire 1 KI X $end +$var wire 1 JI A0 $end +$var wire 1 II A1 $end +$var wire 1 4& S $end +$var supply1 1 _I VPWR $end +$var supply0 1 `I VGND $end +$var supply1 1 aI VPB $end +$var supply0 1 bI VNB $end + +$scope module base $end +$var wire 1 KI X $end +$var wire 1 JI A0 $end +$var wire 1 II A1 $end +$var wire 1 4& S $end +$var wire 1 cI mux_2to10_out_X $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mux_left_track_29 $end +$var wire 1 Y# in [0] $end +$var wire 1 3$ in [1] $end +$var wire 1 ;$ in [2] $end +$var wire 1 5& sram [0] $end +$var wire 1 6& sram [1] $end +$var wire 1 A( sram_inv [0] $end +$var wire 1 B( sram_inv [1] $end +$var wire 1 i$ out [0] $end +$var wire 1 p' p0 $end +$var wire 1 dI mux_2level_tapbuf_basis_input2_mem1_0_out [0] $end +$var wire 1 eI mux_2level_tapbuf_basis_input2_mem1_1_out [0] $end +$var wire 1 fI mux_2level_tapbuf_basis_input2_mem1_2_out [0] $end +$var wire 1 gI SYNOPSYS_UNCONNECTED_1 $end +$var wire 1 hI SYNOPSYS_UNCONNECTED_2 $end +$var wire 1 iI SYNOPSYS_UNCONNECTED_3 $end +$var wire 1 jI SYNOPSYS_UNCONNECTED_4 $end +$var wire 1 kI BUF_net_173 $end + +$scope module mux_l1_in_0_ $end +$var wire 1 Y# in [0] $end +$var wire 1 3$ in [1] $end +$var wire 1 5& mem [0] $end +$var wire 1 gI mem_inv [0] $end +$var wire 1 dI out [0] $end + +$scope module sky130_fd_sc_hd__mux2_1_0 $end +$var wire 1 dI X $end +$var wire 1 3$ A0 $end +$var wire 1 Y# A1 $end +$var wire 1 5& S $end +$var supply1 1 lI VPWR $end +$var supply0 1 mI VGND $end +$var supply1 1 nI VPB $end +$var supply0 1 oI VNB $end + +$scope module base $end +$var wire 1 dI X $end +$var wire 1 3$ A0 $end +$var wire 1 Y# A1 $end +$var wire 1 5& S $end +$var wire 1 pI mux_2to10_out_X $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mux_l1_in_1_ $end +$var wire 1 ;$ in [0] $end +$var wire 1 hI in [1] $end +$var wire 1 5& mem [0] $end +$var wire 1 iI mem_inv [0] $end +$var wire 1 eI out [0] $end +$var wire 1 p' p0 $end + +$scope module sky130_fd_sc_hd__mux2_1_0 $end +$var wire 1 eI X $end +$var wire 1 p' A0 $end +$var wire 1 ;$ A1 $end +$var wire 1 5& S $end +$var supply1 1 qI VPWR $end +$var supply0 1 rI VGND $end +$var supply1 1 sI VPB $end +$var supply0 1 tI VNB $end + +$scope module base $end +$var wire 1 eI X $end +$var wire 1 p' A0 $end +$var wire 1 ;$ A1 $end +$var wire 1 5& S $end +$var wire 1 uI mux_2to10_out_X $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mux_l2_in_0_ $end +$var wire 1 dI in [0] $end +$var wire 1 eI in [1] $end +$var wire 1 6& mem [0] $end +$var wire 1 jI mem_inv [0] $end +$var wire 1 fI out [0] $end + +$scope module sky130_fd_sc_hd__mux2_1_0 $end +$var wire 1 fI X $end +$var wire 1 eI A0 $end +$var wire 1 dI A1 $end +$var wire 1 6& S $end +$var supply1 1 vI VPWR $end +$var supply0 1 wI VGND $end +$var supply1 1 xI VPB $end +$var supply0 1 yI VNB $end + +$scope module base $end +$var wire 1 fI X $end +$var wire 1 eI A0 $end +$var wire 1 dI A1 $end +$var wire 1 6& S $end +$var wire 1 zI mux_2to10_out_X $end +$upscope $end +$upscope $end +$upscope $end + +$scope module BINV_R_172 $end +$var wire 1 i$ Y $end +$var wire 1 kI A $end +$var supply1 1 {I VPWR $end +$var supply0 1 |I VGND $end +$var supply1 1 }I VPB $end +$var supply0 1 ~I VNB $end + +$scope module base $end +$var wire 1 i$ Y $end +$var wire 1 kI A $end +$var wire 1 !J not0_out_Y $end +$upscope $end +$upscope $end + +$scope module BINV_R_173 $end +$var wire 1 kI Y $end +$var wire 1 fI A $end +$var supply1 1 "J VPWR $end +$var supply0 1 #J VGND $end +$var supply1 1 $J VPB $end +$var supply0 1 %J VNB $end + +$scope module base $end +$var wire 1 kI Y $end +$var wire 1 fI A $end +$var wire 1 &J not0_out_Y $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mux_left_track_53 $end +$var wire 1 e# in [0] $end +$var wire 1 7$ in [1] $end +$var wire 1 ;$ in [2] $end +$var wire 1 7& sram [0] $end +$var wire 1 8& sram [1] $end +$var wire 1 C( sram_inv [0] $end +$var wire 1 D( sram_inv [1] $end +$var wire 1 u$ out [0] $end +$var wire 1 p' p0 $end +$var wire 1 'J mux_2level_tapbuf_basis_input2_mem1_0_out [0] $end +$var wire 1 (J mux_2level_tapbuf_basis_input2_mem1_1_out [0] $end +$var wire 1 )J mux_2level_tapbuf_basis_input2_mem1_2_out [0] $end +$var wire 1 *J SYNOPSYS_UNCONNECTED_1 $end +$var wire 1 +J SYNOPSYS_UNCONNECTED_2 $end +$var wire 1 ,J SYNOPSYS_UNCONNECTED_3 $end +$var wire 1 -J SYNOPSYS_UNCONNECTED_4 $end + +$scope module sky130_fd_sc_hd__buf_4_0_ $end +$var wire 1 u$ X $end +$var wire 1 )J A $end +$var supply1 1 .J VPWR $end +$var supply0 1 /J VGND $end +$var supply1 1 0J VPB $end +$var supply0 1 1J VNB $end + +$scope module base $end +$var wire 1 u$ X $end +$var wire 1 )J A $end +$var wire 1 2J buf0_out_X $end +$upscope $end +$upscope $end + +$scope module mux_l1_in_0_ $end +$var wire 1 e# in [0] $end +$var wire 1 7$ in [1] $end +$var wire 1 7& mem [0] $end +$var wire 1 *J mem_inv [0] $end +$var wire 1 'J out [0] $end + +$scope module sky130_fd_sc_hd__mux2_1_0 $end +$var wire 1 'J X $end +$var wire 1 7$ A0 $end +$var wire 1 e# A1 $end +$var wire 1 7& S $end +$var supply1 1 3J VPWR $end +$var supply0 1 4J VGND $end +$var supply1 1 5J VPB $end +$var supply0 1 6J VNB $end + +$scope module base $end +$var wire 1 'J X $end +$var wire 1 7$ A0 $end +$var wire 1 e# A1 $end +$var wire 1 7& S $end +$var wire 1 7J mux_2to10_out_X $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mux_l1_in_1_ $end +$var wire 1 ;$ in [0] $end +$var wire 1 +J in [1] $end +$var wire 1 7& mem [0] $end +$var wire 1 ,J mem_inv [0] $end +$var wire 1 (J out [0] $end +$var wire 1 p' p0 $end + +$scope module sky130_fd_sc_hd__mux2_1_0 $end +$var wire 1 (J X $end +$var wire 1 p' A0 $end +$var wire 1 ;$ A1 $end +$var wire 1 7& S $end +$var supply1 1 8J VPWR $end +$var supply0 1 9J VGND $end +$var supply1 1 :J VPB $end +$var supply0 1 ;J VNB $end + +$scope module base $end +$var wire 1 (J X $end +$var wire 1 p' A0 $end +$var wire 1 ;$ A1 $end +$var wire 1 7& S $end +$var wire 1 J VGND $end +$var supply1 1 ?J VPB $end +$var supply0 1 @J VNB $end + +$scope module base $end +$var wire 1 )J X $end +$var wire 1 (J A0 $end +$var wire 1 'J A1 $end +$var wire 1 8& S $end +$var wire 1 AJ mux_2to10_out_X $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mem_bottom_track_29 $end +$var wire 1 K# pReset [0] $end +$var wire 1 }$ prog_clk [0] $end +$var wire 1 .& ccff_head [0] $end +$var wire 1 9& ccff_tail [0] $end +$var wire 1 1& mem_out [0] $end +$var wire 1 2& mem_out [1] $end + +$scope module sky130_fd_sc_hd__dfrtp_1_0_ $end +$var wire 1 1& Q $end +$var wire 1 }$ CLK $end +$var wire 1 .& D $end +$var wire 1 K# RESET_B $end +$var supply1 1 BJ VPWR $end +$var supply0 1 CJ VGND $end +$var supply1 1 DJ VPB $end +$var supply0 1 EJ VNB $end + +$scope module base $end +$var wire 1 1& Q $end +$var wire 1 }$ CLK $end +$var wire 1 .& D $end +$var wire 1 K# RESET_B $end +$var wire 1 FJ buf_Q $end +$var wire 1 GJ RESET $end +$upscope $end +$upscope $end + +$scope module sky130_fd_sc_hd__dfrtp_1_1_ $end +$var wire 1 2& Q $end +$var wire 1 }$ CLK $end +$var wire 1 1& D $end +$var wire 1 K# RESET_B $end +$var supply1 1 HJ VPWR $end +$var supply0 1 IJ VGND $end +$var supply1 1 JJ VPB $end +$var supply0 1 KJ VNB $end + +$scope module base $end +$var wire 1 2& Q $end +$var wire 1 }$ CLK $end +$var wire 1 1& D $end +$var wire 1 K# RESET_B $end +$var wire 1 LJ buf_Q $end +$var wire 1 MJ RESET $end +$upscope $end +$upscope $end + +$scope module FTB_74__73 $end +$var wire 1 9& X $end +$var wire 1 2& A $end +$var supply1 1 NJ VPWR $end +$var supply0 1 OJ VGND $end +$var supply1 1 PJ VPB $end +$var supply0 1 QJ VNB $end + +$scope module base $end +$var wire 1 9& X $end +$var wire 1 2& A $end +$var wire 1 RJ buf0_out_X $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mem_bottom_track_45 $end +$var wire 1 K# pReset [0] $end +$var wire 1 }$ prog_clk [0] $end +$var wire 1 l% ccff_head [0] $end +$var wire 1 :& ccff_tail [0] $end +$var wire 1 3& mem_out [0] $end +$var wire 1 4& mem_out [1] $end + +$scope module sky130_fd_sc_hd__dfrtp_1_0_ $end +$var wire 1 3& Q $end +$var wire 1 }$ CLK $end +$var wire 1 l% D $end +$var wire 1 K# RESET_B $end +$var supply1 1 SJ VPWR $end +$var supply0 1 TJ VGND $end +$var supply1 1 UJ VPB $end +$var supply0 1 VJ VNB $end + +$scope module base $end +$var wire 1 3& Q $end +$var wire 1 }$ CLK $end +$var wire 1 l% D $end +$var wire 1 K# RESET_B $end +$var wire 1 WJ buf_Q $end +$var wire 1 XJ RESET $end +$upscope $end +$upscope $end + +$scope module sky130_fd_sc_hd__dfrtp_1_1_ $end +$var wire 1 4& Q $end +$var wire 1 }$ CLK $end +$var wire 1 3& D $end +$var wire 1 K# RESET_B $end +$var supply1 1 YJ VPWR $end +$var supply0 1 ZJ VGND $end +$var supply1 1 [J VPB $end +$var supply0 1 \J VNB $end + +$scope module base $end +$var wire 1 4& Q $end +$var wire 1 }$ CLK $end +$var wire 1 3& D $end +$var wire 1 K# RESET_B $end +$var wire 1 ]J buf_Q $end +$var wire 1 ^J RESET $end +$upscope $end +$upscope $end + +$scope module FTB_75__74 $end +$var wire 1 :& X $end +$var wire 1 4& A $end +$var supply1 1 _J VPWR $end +$var supply0 1 `J VGND $end +$var supply1 1 aJ VPB $end +$var supply0 1 bJ VNB $end + +$scope module base $end +$var wire 1 :& X $end +$var wire 1 4& A $end +$var wire 1 cJ buf0_out_X $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mem_left_track_29 $end +$var wire 1 K# pReset [0] $end +$var wire 1 }$ prog_clk [0] $end +$var wire 1 y% ccff_head [0] $end +$var wire 1 ;& ccff_tail [0] $end +$var wire 1 5& mem_out [0] $end +$var wire 1 6& mem_out [1] $end + +$scope module sky130_fd_sc_hd__dfrtp_1_0_ $end +$var wire 1 5& Q $end +$var wire 1 }$ CLK $end +$var wire 1 y% D $end +$var wire 1 K# RESET_B $end +$var supply1 1 dJ VPWR $end +$var supply0 1 eJ VGND $end +$var supply1 1 fJ VPB $end +$var supply0 1 gJ VNB $end + +$scope module base $end +$var wire 1 5& Q $end +$var wire 1 }$ CLK $end +$var wire 1 y% D $end +$var wire 1 K# RESET_B $end +$var wire 1 hJ buf_Q $end +$var wire 1 iJ RESET $end +$upscope $end +$upscope $end + +$scope module sky130_fd_sc_hd__dfrtp_1_1_ $end +$var wire 1 6& Q $end +$var wire 1 }$ CLK $end +$var wire 1 5& D $end +$var wire 1 K# RESET_B $end +$var supply1 1 jJ VPWR $end +$var supply0 1 kJ VGND $end +$var supply1 1 lJ VPB $end +$var supply0 1 mJ VNB $end + +$scope module base $end +$var wire 1 6& Q $end +$var wire 1 }$ CLK $end +$var wire 1 5& D $end +$var wire 1 K# RESET_B $end +$var wire 1 nJ buf_Q $end +$var wire 1 oJ RESET $end +$upscope $end +$upscope $end + +$scope module FTB_76__75 $end +$var wire 1 ;& X $end +$var wire 1 6& A $end +$var supply1 1 pJ VPWR $end +$var supply0 1 qJ VGND $end +$var supply1 1 rJ VPB $end +$var supply0 1 sJ VNB $end + +$scope module base $end +$var wire 1 ;& X $end +$var wire 1 6& A $end +$var wire 1 tJ buf0_out_X $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mem_left_track_53 $end +$var wire 1 K# pReset [0] $end +$var wire 1 }$ prog_clk [0] $end +$var wire 1 '& ccff_head [0] $end +$var wire 1 <& ccff_tail [0] $end +$var wire 1 7& mem_out [0] $end +$var wire 1 8& mem_out [1] $end + +$scope module sky130_fd_sc_hd__dfrtp_1_0_ $end +$var wire 1 7& Q $end +$var wire 1 }$ CLK $end +$var wire 1 '& D $end +$var wire 1 K# RESET_B $end +$var supply1 1 uJ VPWR $end +$var supply0 1 vJ VGND $end +$var supply1 1 wJ VPB $end +$var supply0 1 xJ VNB $end + +$scope module base $end +$var wire 1 7& Q $end +$var wire 1 }$ CLK $end +$var wire 1 '& D $end +$var wire 1 K# RESET_B $end +$var wire 1 yJ buf_Q $end +$var wire 1 zJ RESET $end +$upscope $end +$upscope $end + +$scope module sky130_fd_sc_hd__dfrtp_1_1_ $end +$var wire 1 8& Q $end +$var wire 1 }$ CLK $end +$var wire 1 7& D $end +$var wire 1 K# RESET_B $end +$var supply1 1 {J VPWR $end +$var supply0 1 |J VGND $end +$var supply1 1 }J VPB $end +$var supply0 1 ~J VNB $end + +$scope module base $end +$var wire 1 8& Q $end +$var wire 1 }$ CLK $end +$var wire 1 7& D $end +$var wire 1 K# RESET_B $end +$var wire 1 !K buf_Q $end +$var wire 1 "K RESET $end +$upscope $end +$upscope $end + +$scope module FTB_77__76 $end +$var wire 1 <& X $end +$var wire 1 8& A $end +$var supply1 1 #K VPWR $end +$var supply0 1 $K VGND $end +$var supply1 1 %K VPB $end +$var supply0 1 &K VNB $end + +$scope module base $end +$var wire 1 <& X $end +$var wire 1 8& A $end +$var wire 1 'K buf0_out_X $end +$upscope $end +$upscope $end +$upscope $end + +$scope module pReset_FTB00 $end +$var wire 1 K# X $end +$var wire 1 {$ A $end +$var supply1 1 (K VPWR $end +$var supply0 1 )K VGND $end +$var supply1 1 *K VPB $end +$var supply0 1 +K VNB $end + +$scope module base $end +$var wire 1 K# X $end +$var wire 1 {$ A $end +$var wire 1 ,K buf0_out_X $end +$upscope $end +$upscope $end + +$scope module prog_clk_0_FTB00 $end +$var wire 1 }$ X $end +$var wire 1 |$ A $end +$var supply1 1 -K VPWR $end +$var supply0 1 .K VGND $end +$var supply1 1 /K VPB $end +$var supply0 1 0K VNB $end + +$scope module base $end +$var wire 1 }$ X $end +$var wire 1 |$ A $end +$var wire 1 1K buf0_out_X $end +$upscope $end +$upscope $end + +$scope module FTB_78__77 $end +$var wire 1 Z$ X $end +$var wire 1 s# A $end +$var supply1 1 2K VPWR $end +$var supply0 1 3K VGND $end +$var supply1 1 4K VPB $end +$var supply0 1 5K VNB $end + +$scope module base $end +$var wire 1 Z$ X $end +$var wire 1 s# A $end +$var wire 1 6K buf0_out_X $end +$upscope $end +$upscope $end + +$scope module FTB_79__78 $end +$var wire 1 L$ X $end +$var wire 1 %$ A $end +$var supply1 1 7K VPWR $end +$var supply0 1 8K VGND $end +$var supply1 1 9K VPB $end +$var supply0 1 :K VNB $end + +$scope module base $end +$var wire 1 L$ X $end +$var wire 1 %$ A $end +$var wire 1 ;K buf0_out_X $end +$upscope $end +$upscope $end + +$scope module FTB_80__79 $end +$var wire 1 M$ X $end +$var wire 1 &$ A $end +$var supply1 1 K VPB $end +$var supply0 1 ?K VNB $end + +$scope module base $end +$var wire 1 M$ X $end +$var wire 1 &$ A $end +$var wire 1 @K buf0_out_X $end +$upscope $end +$upscope $end + +$scope module FTB_81__80 $end +$var wire 1 N$ X $end +$var wire 1 '$ A $end +$var supply1 1 AK VPWR $end +$var supply0 1 BK VGND $end +$var supply1 1 CK VPB $end +$var supply0 1 DK VNB $end + +$scope module base $end +$var wire 1 N$ X $end +$var wire 1 '$ A $end +$var wire 1 EK buf0_out_X $end +$upscope $end +$upscope $end + +$scope module FTB_82__81 $end +$var wire 1 O$ X $end +$var wire 1 ($ A $end +$var supply1 1 FK VPWR $end +$var supply0 1 GK VGND $end +$var supply1 1 HK VPB $end +$var supply0 1 IK VNB $end + +$scope module base $end +$var wire 1 O$ X $end +$var wire 1 ($ A $end +$var wire 1 JK buf0_out_X $end +$upscope $end +$upscope $end + +$scope module FTB_83__82 $end +$var wire 1 X$ X $end +$var wire 1 1$ A $end +$var supply1 1 KK VPWR $end +$var supply0 1 LK VGND $end +$var supply1 1 MK VPB $end +$var supply0 1 NK VNB $end + +$scope module base $end +$var wire 1 X$ X $end +$var wire 1 1$ A $end +$var wire 1 OK buf0_out_X $end +$upscope $end +$upscope $end + +$scope module FTB_84__83 $end +$var wire 1 Y$ X $end +$var wire 1 2$ A $end +$var supply1 1 PK VPWR $end +$var supply0 1 QK VGND $end +$var supply1 1 RK VPB $end +$var supply0 1 SK VNB $end + +$scope module base $end +$var wire 1 Y$ X $end +$var wire 1 2$ A $end +$var wire 1 TK buf0_out_X $end +$upscope $end +$upscope $end + +$scope module FTB_85__84 $end +$var wire 1 z$ X $end +$var wire 1 $ A $end +$var supply1 1 UK VPWR $end +$var supply0 1 VK VGND $end +$var supply1 1 WK VPB $end +$var supply0 1 XK VNB $end + +$scope module base $end +$var wire 1 z$ X $end +$var wire 1 $ A $end +$var wire 1 YK buf0_out_X $end +$upscope $end +$upscope $end + +$scope module optlc_176 $end +$var wire 1 (' HI $end +$var wire 1 E( LO $end +$var supply1 1 ZK VPWR $end +$var supply0 1 [K VGND $end +$var supply1 1 \K VPB $end +$var supply0 1 ]K VNB $end + +$scope module base $end +$var wire 1 (' HI $end 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a/FPGA1212_SOFA_CHD_PNR/Verification/fpga_reset_hd_sky_pnr.py b/FPGA1212_SOFA_CHD_PNR/Verification/fpga_reset_hd_sky_pnr.py new file mode 100644 index 0000000..3ee7abe --- /dev/null +++ b/FPGA1212_SOFA_CHD_PNR/Verification/fpga_reset_hd_sky_pnr.py @@ -0,0 +1,349 @@ +import random +import os +import sys +import glob +import math +import cocotb +import logging +import filecmp +from logging.handlers import RotatingFileHandler +from collections import OrderedDict +from pprint import pprint +from xml.dom import minidom +from cocotb.binary import BinaryValue +from cocotb.log import SimLogFormatter +from cocotb.clock import Clock +from cocotb import wavedrom +from cocotb.utils import get_sim_time +from cocotb.handle import Force, Release, Deposit +from cocotb.monitors import Monitor +from cocotb.scoreboard import Scoreboard +from cocotb.result import SimTimeoutError, TestFailure, SimTimeoutError, TestSuccess +from cocotb.triggers import FallingEdge, RisingEdge, Timer, ClockCycles, with_timeout, First + +root_logger = logging.getLogger() + + +file_handler = RotatingFileHandler( + "run.log", maxBytes=(5 * 1024 * 1024), backupCount=2) +root_logger.addHandler(file_handler) + +# Caravel interface pin mapping +FromPinAlias = { + "prog_clk": "io_in[37]", + "clk": "io_in[36]", + "pReset": "io_in[3]", + "Reset": "io_in[2]", + "test_en": "io_in[0]", + "sc_head": "io_in[26]", + "sc_tail": "io_in[11]", + "ccff_head": "io_in[12]", + "ccff_tail": "io_in[35]", +} + + +def getFromPinAlias(dut, pinName): + ''' Get DUT pin from alias ''' + return eval(f"dut.{FromPinAlias[pinName]}") + + +@cocotb.test() +async def ConfigChainTestFull(dut): + # = = = = = = = Get Design Variable = = = = = = = = = = = = = = = = = + PConf = getConfig() + clk = getFromPinAlias(dut, "clk") + prog_clk = getFromPinAlias(dut, "prog_clk") + test_en = getFromPinAlias(dut, "test_en") + pReset = getFromPinAlias(dut, "pReset") + Reset = getFromPinAlias(dut, "Reset") + ccff_head = getFromPinAlias(dut, "ccff_head") + ccff_tail = getFromPinAlias(dut, "ccff_tail") + PCLK_PERIOD = 10 # in nanoseconds + # = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = + + clk <= 0 # Disable prog clock + Reset <= 0 # Disable reset + pReset <= 0 # Reset all configuration FF + pclock = Clock(prog_clk, PCLK_PERIOD*0.5, units="ns") + cocotb.fork(pclock.start()) # Start the clock + + # Clock Preamble Ticks 2 + await ClockCycles(prog_clk, 2) + await FallingEdge(prog_clk) + pReset <= 1 + + # Pass 1 bit logic to CCFF chain + ccff_head <= 1 + await FallingEdge(prog_clk) + ccff_head <= 0 + + # Check CCFF_tail of each module in sequence + CCFFChain = filter(lambda x: not "grid_io" in x, CreateCCFFChain()) + try: + start_ccff_time = get_sim_time(units='ns') + for ModuleName in CCFFChain: + InstPtr = eval(f"dut.fpga_core_uut.{ModuleName}.ccff_tail") + + # Wait for tick + start_time_ns = get_sim_time(units='ns') + await with_timeout(FallingEdge(InstPtr), 200*PCLK_PERIOD, 'ns') + edge_time_ns = get_sim_time(units='ns') + + # Verify + CLKTick = math.ceil((edge_time_ns-start_time_ns)/PCLK_PERIOD) + dut._log.info( + f"Signal received at {ModuleName} at {CLKTick}") + if (CLKTick != 8): + TestFailure( + f"Expected 8 ticks on module {ModuleName} received {CLKTick}") + end_ccff_time = get_sim_time(units='ns') + await ClockCycles(prog_clk, 10) + TotalClock = math.ceil((end_ccff_time-start_ccff_time)/PCLK_PERIOD) + dut._log.info(f"Simulation Finished in clocks {TotalClock}") + except SimTimeoutError: + raise TestFailure(f"Failed to receive signal on {ModuleName}") + + +@cocotb.test() +async def ScanChainTestFull(dut): + # = = = = = = = Get Design Variable = = = = = = = = = = = = = = = = = + PConf = getConfig() + clk = getFromPinAlias(dut, "clk") + prog_clk = getFromPinAlias(dut, "prog_clk") + pReset = getFromPinAlias(dut, "pReset") + Reset = getFromPinAlias(dut, "Reset") + test_en = getFromPinAlias(dut, "test_en") + sc_head = getFromPinAlias(dut, "sc_head") + sc_tail = getFromPinAlias(dut, "sc_tail") + CLK_PERIOD = 10 # in nanoseconds + # = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = + + prog_clk <= 0 # Disable prog clock + pReset <= 0 # Disable programming reset + Reset <= 0 # Disable reset + clock = Clock(clk, CLK_PERIOD*0.5, units="ns") + cocotb.fork(clock.start()) # Start the clock + + # Clock Preamble Ticks 2 + await ClockCycles(clk, 2) + + # Setup control signals + await FallingEdge(clk) + test_en <= 1 + Reset <= 1 + + # Pass 1 bit logic to SCFF chain + sc_head <= 1 + await FallingEdge(clk) + sc_head <= 0 + + try: + start_scff_time = get_sim_time(units='ns') + for X in range(1, 1+PConf["FPGA_SIZE_X"]): + Yrange = range(1, 1+PConf["FPGA_SIZE_X"]) + Yrange = reversed(Yrange) if (X % 2) else Yrange + for Y in Yrange: + ModuleName = f"grid_clb_{X}__{Y}_" + PinName = "SC_OUT_BOT" if (X % 2) else "SC_OUT_TOP" + InstPtr = eval(f"dut.fpga_core_uut.{ModuleName}.{PinName}") + # Wait for tick + start_time_ns = get_sim_time(units='ns') + await with_timeout(FallingEdge(InstPtr), 50*CLK_PERIOD, 'ns') + edge_time_ns = get_sim_time(units='ns') + + # Verify + CLKTick = math.ceil((edge_time_ns-start_time_ns)/CLK_PERIOD) + dut._log.info( + f"Signal received at {ModuleName} at {CLKTick}") + if (CLKTick != 8): + TestFailure( + f"Expected 8 ticks on module {ModuleName} received {CLKTick}") + end_scff_time = get_sim_time(units='ns') + TotalClock = math.ceil((end_scff_time-start_scff_time)/CLK_PERIOD) + await ClockCycles(clk, 10) + dut._log.info(f"Simulation Finished in clocks {TotalClock}") + dut._log.info(f"Per Grid {TotalClock/(PConf['FPGA_SIZE_X']**2)}") + except SimTimeoutError: + raise TestFailure(f"Failed to receive signal on {ModuleName}") + + +# ###================================================================ +# = = = = = = = = = = Utils Functions = = = = = = = = = = = = = = = = +# ###================================================================ + + +def getConfig(): + """ + return config.sh varaibles with default values + """ + return { + "TECHNOLOGY": os.environ.get('TECHNOLOGY', 'skywater'), + "PROJ_NAME": os.environ.get('PROJ_NAME', None), + "DESIGN_STYLE": os.environ.get('DESIGN_STYLE', "hier"), + "FPGA_SIZE_X": int(os.environ.get('FPGA_SIZE_X', 0)), + "FPGA_SIZE_Y": int(os.environ.get('FPGA_SIZE_Y', 0)), + } + + +@cocotb.coroutine +async def ProgramPhase(dut, BitFile, maxCycles=sys.maxsize): + dut.pReset_pad = 0 + bitCount = 0 + with open(BitFile, "r") as fp: + dut._log.info(f"Bitfile opened : {BitFile}") + while bitCount < maxCycles: + c = fp.read(1) + if not c in ["0", "1"]: + dut._log.info(f"Configured device with {bitCount} bits") + break + bitCount += 1 + if (bitCount % 50) == 0: + dut._log.info(f"Writen {bitCount} bits") + dut.ccff_head_pad = int(c) + await FallingEdge(dut.prog_clk_pad) + + +@cocotb.coroutine +async def AutoConfigure(dut, BitFile, ccPaths, BitstreamLen): + TotalBitsCount = 0 + PreviousSync = 0 + # Locking Signal + with open(BitFile, "r") as fp: + dut._log.info(f"Bitfile opened {BitFile}") + syncPts = math.ceil(BitstreamLen/4800) + InitialBits = [int(i) for i in list(fp.read(syncPts+1))] + dut._log.info(f"Will make total {syncPts} sync {InitialBits}") + for inst, eachModule in ccPaths.items(): + BitsCount = 0 + for eachPath in eachModule: + size = eachPath["width"] + BitsCount += size + try: + Stream = fp.read(size) + bits = int(Stream, 2) + except: + dut._log.info(f"Padding Zero") + bits = 0 + eachPath["obj"] <= Force(bits) + TotalBitsCount += BitsCount + dut._log.info(f"Configured {inst} with {BitsCount} bits ") + dut.ccff_head_pad <= InitialBits.pop() + await FallingEdge(dut.prog_clk_pad) + + # Releasing Signals + PreviousSync = 0 + TotalBitsCount = 0 + for inst, eachModule in ccPaths.items(): + for eachPath in eachModule: + eachPath["obj"] <= Release() + TotalBitsCount += eachPath["width"] + if (TotalBitsCount-PreviousSync) > 4800: + dut.ccff_head_pad <= InitialBits.pop() + await FallingEdge(dut.prog_clk_pad) + PreviousSync = TotalBitsCount + dut._log.info(f"Releasing config of {inst}") + dut.ccff_head_pad <= InitialBits.pop() + await FallingEdge(dut.prog_clk_pad) + dut._log.info(f"Configured {TotalBitsCount} bits") + + +def SaveConfiguration(CFFPaths, filename, style="default"): + lineW = 0 + with open(filename, "w") as fp: + for _, eachModule in CFFPaths.items(): + for eachPath in eachModule: + val = eachPath["obj"].value.binstr + if style == 'default': + val = "\n".join(list(val)) + fp.write(val+"\n") + elif style == "bitstream": + fp.write(val) + elif style == "detailed": + fp.write(f"{eachPath['name']} {val}\n") + elif style == "adjusted": + for eachC in val: + fp.write(eachC) + lineW += 1 + if (lineW == 32): + fp.write("\n") + lineW = 0 + + +def CreateCCFFChain(): + CCFFChain = [] + mydoc = minidom.parse( + glob.glob("./TaskConfigCopy/*_task/arch/fabric_key.xml")[0]) + items = mydoc.getElementsByTagName('key') + for elem in items: + CCFFChain.append(elem.attributes['alias'].value) + return CCFFChain + + +def returnPaths(Node, PathList): + Nodes = [e for e in Node.childNodes if not isinstance(e, minidom.Text)] + # pprint(Nodes) + for eachN in Nodes: + eachNChild = [ + e for e in eachN.childNodes if not isinstance(e, minidom.Text)] + Bitstream = [e for e in eachNChild if e.tagName == "bitstream"] + if Bitstream: + Hier = eachN.getElementsByTagName("hierarchy")[0] + path = [each.attributes["name"].value + for each in Hier.getElementsByTagName("instance")] + path = ".".join(path).replace('fpga_top', 'dut.fpga_core_uut') + + bitEles = Bitstream[0].getElementsByTagName("bit") + ports = [path + "." + each.attributes["memory_port"].value.split("[")[0] + for each in bitEles[:1]] + length = len(bitEles) + value = "".join([e.attributes["value"].value for e in bitEles]) + PathList.append({ + "name": ports[0], + "width": length, + "value": value + }) + elif eachN.tagName == "bitstream_block": + returnPaths(eachN, PathList) + + +def get_modules(): + FabricKey = minidom.parse( + glob.glob("./TaskConfigCopy/*_task/arch/fabric_key.xml")[0]) + items = FabricKey.getElementsByTagName('key') + return [elem.attributes['alias'].value for elem in items] + + +def CreateCCFFChainPaths(dut): + BitstreamXML = minidom.parse( + glob.glob("./TESTBENCH/top/fabric_indepenent_bitstream.xml")[0]) + + ModulesDict = {} + BT_BLocks = BitstreamXML.getElementsByTagName('bitstream_block') + for element in BT_BLocks: + if element.getAttribute('hierarchy_level') == "1": + ModulesDict[element.attributes['name'].value] = element + + FabricKey = minidom.parse( + glob.glob("./TaskConfigCopy/*_task/arch/fabric_key.xml")[0]) + items = FabricKey.getElementsByTagName('key') + + pathList = OrderedDict() + chainLength = 0 + + for elem in items: + modulePaths = [] + moduleLen = 0 + inst = elem.attributes['alias'].value + returnPaths(ModulesDict[inst], modulePaths) + for eachEle in modulePaths: + eachEle["obj"] = eval(eachEle["name"]) + moduleLen += eachEle["width"] + pathList[inst] = modulePaths + chainLength += moduleLen + return (chainLength, pathList) + + +if __name__ == "__main__": + CC = CreateCCFFChainPaths(None) + pprint(CC["grid_clb_1__2_"][:5]) + pprint(len(CC["grid_clb_1__2_"])) diff --git a/FPGA1212_SOFA_CHD_PNR/config.sh b/FPGA1212_SOFA_CHD_PNR/config.sh new file mode 100644 index 0000000..2343f84 --- /dev/null +++ b/FPGA1212_SOFA_CHD_PNR/config.sh @@ -0,0 +1,50 @@ +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# = = = = = = = = = = = = = = Variables Sections = = = = = = = = = = = = = = = +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = + +export PROJ_NAME=FPGA1212_SOFA_CHD # Project Name +export FPGA_SIZE_X=12 # Grid X Size +export FPGA_SIZE_Y=12 # Grid Y Size +# Design Style [hier/flat], mostly hier +export DESIGN_STYLE=hier +export TECHNOLOGY="skywater" + +# Complete Chip (fpga_top) or eFPGA (fpga_core) +export DESIGN_NAME=fpga_core + +# Pin Information Source Automatic or Sheet +export PIN_MAP=Automatic +export PIN_MAP_CSV_SPREADSHEET_LINK="" # Required only if PIN_MAP==Sheet + +# Core Dimension, requires if DESIGN_NAME=fpga_core +# if DESIGN_NAME=fpga_top its Optional if defined it overrides the +# Calculated DIE_DIMENSION +export DIE_DIMENSION=3200 + +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# Derived Or Fixed Variables +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +export OPENFPGA_ENGINE_PATH=/research/ece/lnis/USERS/DARPA_ERI/Tapeout/May2020/OpenFPGA_for_Chip +export TASK_DIR_NAME=${PROJ_NAME}_task +export VERILOG_PROJ_DIR=${PROJ_NAME}_Verilog +export SPY_HACK_FILE=${TASK_DIR_NAME}/spy_hack.txt +export POST_OPENFPGA_SCRIPT=./PostOpenFPGAScript.sh +export RESTRUCT_NETLIST=../utils/RestructureNetlistSkywater.py +export POST_GENERATION_SCRIPT=./generate_scandef_and_case_analysis.sh +export MODULE_ADJUST=./adjust_module.sh + +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# Restructure Netlist Varaibles +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# export RESTRUCTURE_skipClockRestructure="" +# export RESTRUCTURE_Skeleton="" + +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# PNR RELATED FLOW +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +export INIT_DESIGN_INPUT="ASCII" + +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# Extra variables availble during flow (suuffix FLOWVAR_) +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +export FLOWVAR_STANDARD_CELLS="sc_hd" \ No newline at end of file diff --git a/FPGA1212_SOFA_CHD_PNR/fpga_top/fpga_top_icv_in_design.fm.v b/FPGA1212_SOFA_CHD_PNR/fpga_top/fpga_top_icv_in_design.fm.v index 8d14ee8..34c5ad9 100644 --- a/FPGA1212_SOFA_CHD_PNR/fpga_top/fpga_top_icv_in_design.fm.v +++ b/FPGA1212_SOFA_CHD_PNR/fpga_top/fpga_top_icv_in_design.fm.v @@ -12,18 +12,10 @@ input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:0] mem_out ; -wire copt_net_114 ; +assign ccff_tail[0] = mem_out[0] ; sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( copt_net_114 ) ) ; -sky130_fd_sc_hd__buf_6 FTB_18__17 ( .A ( copt_net_116 ) , - .X ( ccff_tail[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1354 ( .A ( copt_net_114 ) , - .X ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1355 ( .A ( mem_out[0] ) , - .X ( copt_net_115 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1356 ( .A ( copt_net_115 ) , - .X ( copt_net_116 ) ) ; + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; endmodule @@ -38,16 +30,12 @@ input FPGA_DIR ; input IO_ISOL_N ; sky130_fd_sc_hd__or2b_4 ISOL_EN_GATE ( .A ( FPGA_DIR ) , .B_N ( IO_ISOL_N ) , - .X ( aps_rename_510_ ) ) ; -sky130_fd_sc_hd__inv_1 INV_SOC_DIR ( .A ( aps_rename_510_ ) , - .Y ( SOC_DIR_N ) ) ; + .X ( SOC_DIR ) ) ; +sky130_fd_sc_hd__inv_1 INV_SOC_DIR ( .A ( SOC_DIR ) , .Y ( SOC_DIR_N ) ) ; sky130_fd_sc_hd__ebufn_4 IN_PROTECT_GATE ( .A ( SOC_IN ) , .TE_B ( SOC_DIR_N ) , .Z ( FPGA_IN ) ) ; sky130_fd_sc_hd__ebufn_4 OUT_PROTECT_GATE ( .A ( FPGA_OUT ) , - .TE_B ( aps_rename_510_ ) , .Z ( SOC_OUT ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_81 ( .A ( aps_rename_510_ ) , - .Y ( BUF_net_81 ) ) ; -sky130_fd_sc_hd__inv_6 BINV_R_80 ( .A ( BUF_net_81 ) , .Y ( SOC_DIR ) ) ; + .TE_B ( SOC_DIR ) , .Z ( SOC_OUT ) ) ; endmodule @@ -113,6 +101,8 @@ input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; +assign ccff_tail[0] = mem_out[3] ; + sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , @@ -121,7 +111,6 @@ sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__buf_1 FTB_17__16 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -133,6 +122,8 @@ input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; +assign ccff_tail[0] = mem_out[3] ; + sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , @@ -141,7 +132,6 @@ sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__buf_1 FTB_16__15 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -153,6 +143,8 @@ input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; +assign ccff_tail[0] = mem_out[3] ; + sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , @@ -161,7 +153,6 @@ sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__buf_1 FTB_15__14 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -173,6 +164,8 @@ input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; +assign ccff_tail[0] = mem_out[3] ; + sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , @@ -181,7 +174,6 @@ sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__buf_1 FTB_14__13 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -193,6 +185,8 @@ input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; +assign ccff_tail[0] = mem_out[3] ; + sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , @@ -201,7 +195,6 @@ sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__buf_1 FTB_13__12 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -213,6 +206,8 @@ input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; +assign ccff_tail[0] = mem_out[3] ; + sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , @@ -221,7 +216,6 @@ sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__buf_1 FTB_12__11 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -233,6 +227,8 @@ input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; +assign ccff_tail[0] = mem_out[3] ; + sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , @@ -241,7 +237,6 @@ sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__buf_1 FTB_11__10 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -253,6 +248,8 @@ input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; +assign ccff_tail[0] = mem_out[3] ; + sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , @@ -261,7 +258,6 @@ sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__buf_1 FTB_10__9 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -271,26 +267,34 @@ input [0:1] mem ; input [0:1] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule -module cby_2__1__mux_2level_basis_input4_mem4 ( in , mem , mem_inv , out , - p0 ) ; +module cby_2__1__mux_2level_basis_input4_mem4 ( in , mem , mem_inv , out ) ; input [0:3] in ; input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; -input p0 ; + +wire [0:0] out_inv ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; -scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( p0 ) , + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; +scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -300,12 +304,20 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; -scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; +scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( ZINV_1377_17 ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; +sky130_fd_sc_hd__clkinv_1 ZINV_1377_inst_1023 ( .A ( in[2] ) , + .Y ( ZINV_1377_17 ) ) ; endmodule @@ -315,12 +327,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -337,7 +355,7 @@ sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ; sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , .Y ( data_inv[2] ) ) ; sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ; -sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ; +sky130_fd_sc_hd__clkinv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ; sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ; sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , .Y ( data_inv[3] ) ) ; @@ -357,7 +375,7 @@ sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ; sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , .Y ( data_inv[2] ) ) ; sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ; -sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ; +sky130_fd_sc_hd__clkinv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ; sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ; sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , .Y ( data_inv[3] ) ) ; @@ -366,16 +384,18 @@ endmodule module cby_2__1__const1 ( const1 ) ; output [0:0] const1 ; + +assign const1[0] = 1'b1 ; endmodule -module cby_2__1__mux_2level_size10 ( in , sram , sram_inv , out , p0 ) ; +module cby_2__1__mux_2level_size10 ( in , sram , sram_inv , out ) ; input [0:9] in ; input [0:3] sram ; input [0:3] sram_inv ; output [0:0] out ; -input p0 ; +wire [0:0] const1_0_const1 ; wire [0:3] local_encoder2to4_0_data ; wire [0:3] local_encoder2to4_0_data_inv ; wire [0:3] local_encoder2to4_1_data ; @@ -385,10 +405,9 @@ wire [0:0] mux_2level_basis_input4_mem4_0_out ; wire [0:0] mux_2level_basis_input4_mem4_1_out ; wire [0:0] mux_2level_basis_input4_mem4_2_out ; -cby_2__1__const1 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +cby_2__1__const1 const1_0_ ( .const1 ( const1_0_const1 ) ) ; sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_1_0_ ( - .A ( mux_2level_basis_input4_mem4_2_out[0] ) , .X ( net_net_95 ) ) ; + .A ( mux_2level_basis_input4_mem4_2_out[0] ) , .X ( out[0] ) ) ; cby_2__1__local_encoder2to4_32 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , .data ( local_encoder2to4_0_data ) , .data_inv ( local_encoder2to4_0_data_inv ) ) ; @@ -406,15 +425,14 @@ cby_2__1__mux_2level_basis_input4_mem4_58 mux_l1_in_1_ ( .in ( in[4:7] ) , cby_2__1__mux_2level_basis_input4_mem4 mux_l2_in_0_ ( .in ( { mux_2level_basis_input4_mem4_0_out[0] , mux_2level_basis_input4_mem4_1_out[0] , - mux_2level_basis_input2_mem2_0_out[0] , SYNOPSYS_UNCONNECTED_2 } ) , + mux_2level_basis_input2_mem2_0_out[0] , const1_0_const1[0] } ) , .mem ( local_encoder2to4_1_data ) , .mem_inv ( local_encoder2to4_1_data_inv ) , - .out ( mux_2level_basis_input4_mem4_2_out ) , .p0 ( p0 ) ) ; + .out ( mux_2level_basis_input4_mem4_2_out ) ) ; cby_2__1__mux_2level_basis_input2_mem2 mux_l1_in_2_ ( .in ( in[8:9] ) , .mem ( local_encoder2to4_0_data[0:1] ) , .mem_inv ( local_encoder2to4_0_data_inv[0:1] ) , .out ( mux_2level_basis_input2_mem2_0_out ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_95 ( .A ( net_net_95 ) , .X ( out[0] ) ) ; endmodule @@ -424,26 +442,34 @@ input [0:1] mem ; input [0:1] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule -module cby_2__1__mux_2level_basis_input4_mem4_56 ( in , mem , mem_inv , out , - p0 ) ; +module cby_2__1__mux_2level_basis_input4_mem4_56 ( in , mem , mem_inv , out ) ; input [0:3] in ; input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; -input p0 ; + +wire [0:0] out_inv ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; -scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( p0 ) , + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; +scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -453,12 +479,19 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; -scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; +scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( ZINV_4_16 ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; +sky130_fd_sc_hd__clkinv_1 ZINV_4_inst_1004 ( .A ( in[3] ) , .Y ( ZINV_4_16 ) ) ; endmodule @@ -468,12 +501,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -490,7 +529,7 @@ sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ; sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , .Y ( data_inv[2] ) ) ; sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ; -sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ; +sky130_fd_sc_hd__clkinv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ; sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ; sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , .Y ( data_inv[3] ) ) ; @@ -510,7 +549,7 @@ sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ; sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , .Y ( data_inv[2] ) ) ; sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ; -sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ; +sky130_fd_sc_hd__clkinv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ; sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ; sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , .Y ( data_inv[3] ) ) ; @@ -519,16 +558,18 @@ endmodule module cby_2__1__const1_15 ( const1 ) ; output [0:0] const1 ; + +assign const1[0] = 1'b1 ; endmodule -module cby_2__1__mux_2level_size10_6 ( in , sram , sram_inv , out , p0 ) ; +module cby_2__1__mux_2level_size10_6 ( in , sram , sram_inv , out ) ; input [0:9] in ; input [0:3] sram ; input [0:3] sram_inv ; output [0:0] out ; -input p0 ; +wire [0:0] const1_0_const1 ; wire [0:3] local_encoder2to4_0_data ; wire [0:3] local_encoder2to4_0_data_inv ; wire [0:3] local_encoder2to4_1_data ; @@ -538,10 +579,9 @@ wire [0:0] mux_2level_basis_input4_mem4_0_out ; wire [0:0] mux_2level_basis_input4_mem4_1_out ; wire [0:0] mux_2level_basis_input4_mem4_2_out ; -cby_2__1__const1_15 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +cby_2__1__const1_15 const1_0_ ( .const1 ( const1_0_const1 ) ) ; sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_1_0_ ( - .A ( mux_2level_basis_input4_mem4_2_out[0] ) , .X ( net_net_94 ) ) ; + .A ( mux_2level_basis_input4_mem4_2_out[0] ) , .X ( out[0] ) ) ; cby_2__1__local_encoder2to4_30 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , .data ( local_encoder2to4_0_data ) , .data_inv ( local_encoder2to4_0_data_inv ) ) ; @@ -559,15 +599,14 @@ cby_2__1__mux_2level_basis_input4_mem4_55 mux_l1_in_1_ ( .in ( in[4:7] ) , cby_2__1__mux_2level_basis_input4_mem4_56 mux_l2_in_0_ ( .in ( { mux_2level_basis_input4_mem4_0_out[0] , mux_2level_basis_input4_mem4_1_out[0] , - mux_2level_basis_input2_mem2_0_out[0] , SYNOPSYS_UNCONNECTED_2 } ) , + mux_2level_basis_input2_mem2_0_out[0] , const1_0_const1[0] } ) , .mem ( local_encoder2to4_1_data ) , .mem_inv ( local_encoder2to4_1_data_inv ) , - .out ( mux_2level_basis_input4_mem4_2_out ) , .p0 ( p0 ) ) ; + .out ( mux_2level_basis_input4_mem4_2_out ) ) ; cby_2__1__mux_2level_basis_input2_mem2_6 mux_l1_in_2_ ( .in ( in[8:9] ) , .mem ( local_encoder2to4_0_data[0:1] ) , .mem_inv ( local_encoder2to4_0_data_inv[0:1] ) , .out ( mux_2level_basis_input2_mem2_0_out ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_94 ( .A ( net_net_94 ) , .X ( out[0] ) ) ; endmodule @@ -577,26 +616,34 @@ input [0:1] mem ; input [0:1] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule -module cby_2__1__mux_2level_basis_input4_mem4_53 ( in , mem , mem_inv , out , - p0 ) ; +module cby_2__1__mux_2level_basis_input4_mem4_53 ( in , mem , mem_inv , out ) ; input [0:3] in ; input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; -input p0 ; + +wire [0:0] out_inv ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; -scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( p0 ) , + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; +scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -606,12 +653,20 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; -scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; +scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( ZINV_24_11 ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; +sky130_fd_sc_hd__clkinv_1 ZINV_24_inst_961 ( .A ( in[2] ) , + .Y ( ZINV_24_11 ) ) ; endmodule @@ -621,12 +676,19 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; -scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , +wire [0:0] out_inv ; + +scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( ZINV_17_3 ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; +sky130_fd_sc_hd__clkinv_1 ZINV_17_inst_910 ( .A ( in[0] ) , .Y ( ZINV_17_3 ) ) ; endmodule @@ -643,7 +705,7 @@ sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ; sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , .Y ( data_inv[2] ) ) ; sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ; -sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ; +sky130_fd_sc_hd__clkinv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ; sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ; sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , .Y ( data_inv[3] ) ) ; @@ -663,7 +725,7 @@ sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ; sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , .Y ( data_inv[2] ) ) ; sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ; -sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ; +sky130_fd_sc_hd__clkinv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ; sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ; sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , .Y ( data_inv[3] ) ) ; @@ -672,16 +734,18 @@ endmodule module cby_2__1__const1_14 ( const1 ) ; output [0:0] const1 ; + +assign const1[0] = 1'b1 ; endmodule -module cby_2__1__mux_2level_size10_5 ( in , sram , sram_inv , out , p0 ) ; +module cby_2__1__mux_2level_size10_5 ( in , sram , sram_inv , out ) ; input [0:9] in ; input [0:3] sram ; input [0:3] sram_inv ; output [0:0] out ; -input p0 ; +wire [0:0] const1_0_const1 ; wire [0:3] local_encoder2to4_0_data ; wire [0:3] local_encoder2to4_0_data_inv ; wire [0:3] local_encoder2to4_1_data ; @@ -691,10 +755,9 @@ wire [0:0] mux_2level_basis_input4_mem4_0_out ; wire [0:0] mux_2level_basis_input4_mem4_1_out ; wire [0:0] mux_2level_basis_input4_mem4_2_out ; -cby_2__1__const1_14 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +cby_2__1__const1_14 const1_0_ ( .const1 ( const1_0_const1 ) ) ; sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_1_0_ ( - .A ( mux_2level_basis_input4_mem4_2_out[0] ) , .X ( aps_rename_509_ ) ) ; + .A ( mux_2level_basis_input4_mem4_2_out[0] ) , .X ( out[0] ) ) ; cby_2__1__local_encoder2to4_28 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , .data ( local_encoder2to4_0_data ) , .data_inv ( local_encoder2to4_0_data_inv ) ) ; @@ -712,17 +775,14 @@ cby_2__1__mux_2level_basis_input4_mem4_52 mux_l1_in_1_ ( .in ( in[4:7] ) , cby_2__1__mux_2level_basis_input4_mem4_53 mux_l2_in_0_ ( .in ( { mux_2level_basis_input4_mem4_0_out[0] , mux_2level_basis_input4_mem4_1_out[0] , - mux_2level_basis_input2_mem2_0_out[0] , SYNOPSYS_UNCONNECTED_2 } ) , + mux_2level_basis_input2_mem2_0_out[0] , const1_0_const1[0] } ) , .mem ( local_encoder2to4_1_data ) , .mem_inv ( local_encoder2to4_1_data_inv ) , - .out ( mux_2level_basis_input4_mem4_2_out ) , .p0 ( p0 ) ) ; + .out ( mux_2level_basis_input4_mem4_2_out ) ) ; cby_2__1__mux_2level_basis_input2_mem2_5 mux_l1_in_2_ ( .in ( in[8:9] ) , .mem ( local_encoder2to4_0_data[0:1] ) , .mem_inv ( local_encoder2to4_0_data_inv[0:1] ) , .out ( mux_2level_basis_input2_mem2_0_out ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_92 ( .A ( BUF_net_93 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_93 ( .A ( aps_rename_509_ ) , - .Y ( BUF_net_93 ) ) ; endmodule @@ -732,26 +792,34 @@ input [0:1] mem ; input [0:1] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule -module cby_2__1__mux_2level_basis_input4_mem4_50 ( in , mem , mem_inv , out , - p0 ) ; +module cby_2__1__mux_2level_basis_input4_mem4_50 ( in , mem , mem_inv , out ) ; input [0:3] in ; input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; -input p0 ; + +wire [0:0] out_inv ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; -scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( p0 ) , + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; +scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -761,12 +829,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -776,12 +850,20 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; -scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , +wire [0:0] out_inv ; + +scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( ZINV_10_0 ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; -scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; +scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( ZINV_10_1 ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; +sky130_fd_sc_hd__clkinv_1 ZINV_10_inst_883 ( .A ( in[1] ) , .Y ( ZINV_10_0 ) ) ; +sky130_fd_sc_hd__clkinv_1 ZINV_10_inst_895 ( .A ( in[3] ) , .Y ( ZINV_10_1 ) ) ; endmodule @@ -798,7 +880,7 @@ sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ; sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , .Y ( data_inv[2] ) ) ; sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ; -sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ; +sky130_fd_sc_hd__clkinv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ; sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ; sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , .Y ( data_inv[3] ) ) ; @@ -818,7 +900,7 @@ sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ; sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , .Y ( data_inv[2] ) ) ; sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ; -sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ; +sky130_fd_sc_hd__clkinv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ; sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ; sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , .Y ( data_inv[3] ) ) ; @@ -827,16 +909,18 @@ endmodule module cby_2__1__const1_13 ( const1 ) ; output [0:0] const1 ; + +assign const1[0] = 1'b1 ; endmodule -module cby_2__1__mux_2level_size10_4 ( in , sram , sram_inv , out , p0 ) ; +module cby_2__1__mux_2level_size10_4 ( in , sram , sram_inv , out ) ; input [0:9] in ; input [0:3] sram ; input [0:3] sram_inv ; output [0:0] out ; -input p0 ; +wire [0:0] const1_0_const1 ; wire [0:3] local_encoder2to4_0_data ; wire [0:3] local_encoder2to4_0_data_inv ; wire [0:3] local_encoder2to4_1_data ; @@ -846,9 +930,8 @@ wire [0:0] mux_2level_basis_input4_mem4_0_out ; wire [0:0] mux_2level_basis_input4_mem4_1_out ; wire [0:0] mux_2level_basis_input4_mem4_2_out ; -cby_2__1__const1_13 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__bufbuf_16 sky130_fd_sc_hd__buf_1_0_ ( +cby_2__1__const1_13 const1_0_ ( .const1 ( const1_0_const1 ) ) ; +sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_1_0_ ( .A ( mux_2level_basis_input4_mem4_2_out[0] ) , .X ( out[0] ) ) ; cby_2__1__local_encoder2to4_26 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , .data ( local_encoder2to4_0_data ) , @@ -867,10 +950,10 @@ cby_2__1__mux_2level_basis_input4_mem4_49 mux_l1_in_1_ ( .in ( in[4:7] ) , cby_2__1__mux_2level_basis_input4_mem4_50 mux_l2_in_0_ ( .in ( { mux_2level_basis_input4_mem4_0_out[0] , mux_2level_basis_input4_mem4_1_out[0] , - mux_2level_basis_input2_mem2_0_out[0] , SYNOPSYS_UNCONNECTED_2 } ) , + mux_2level_basis_input2_mem2_0_out[0] , const1_0_const1[0] } ) , .mem ( local_encoder2to4_1_data ) , .mem_inv ( local_encoder2to4_1_data_inv ) , - .out ( mux_2level_basis_input4_mem4_2_out ) , .p0 ( p0 ) ) ; + .out ( mux_2level_basis_input4_mem4_2_out ) ) ; cby_2__1__mux_2level_basis_input2_mem2_4 mux_l1_in_2_ ( .in ( in[8:9] ) , .mem ( local_encoder2to4_0_data[0:1] ) , .mem_inv ( local_encoder2to4_0_data_inv[0:1] ) , @@ -884,26 +967,35 @@ input [0:1] mem ; input [0:1] mem_inv ; output [0:0] out ; -scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , +wire [0:0] out_inv ; + +scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( ZINV_7_5 ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; +sky130_fd_sc_hd__clkinv_1 ZINV_7_inst_932 ( .A ( in[1] ) , .Y ( ZINV_7_5 ) ) ; endmodule -module cby_2__1__mux_2level_basis_input4_mem4_47 ( in , mem , mem_inv , out , - p0 ) ; +module cby_2__1__mux_2level_basis_input4_mem4_47 ( in , mem , mem_inv , out ) ; input [0:3] in ; input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; -input p0 ; + +wire [0:0] out_inv ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; -scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( p0 ) , + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; +scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -913,12 +1005,19 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; -scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; +scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( ZINV_4_9 ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; +sky130_fd_sc_hd__clkinv_1 ZINV_4_inst_949 ( .A ( in[3] ) , .Y ( ZINV_4_9 ) ) ; endmodule @@ -928,12 +1027,19 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; -scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , +wire [0:0] out_inv ; + +scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( ZINV_10_2 ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; +sky130_fd_sc_hd__clkinv_1 ZINV_10_inst_904 ( .A ( in[1] ) , .Y ( ZINV_10_2 ) ) ; endmodule @@ -950,7 +1056,7 @@ sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ; sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , .Y ( data_inv[2] ) ) ; sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ; -sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ; +sky130_fd_sc_hd__clkinv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ; sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ; sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , .Y ( data_inv[3] ) ) ; @@ -970,7 +1076,7 @@ sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ; sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , .Y ( data_inv[2] ) ) ; sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ; -sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ; +sky130_fd_sc_hd__clkinv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ; sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ; sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , .Y ( data_inv[3] ) ) ; @@ -979,16 +1085,18 @@ endmodule module cby_2__1__const1_12 ( const1 ) ; output [0:0] const1 ; + +assign const1[0] = 1'b1 ; endmodule -module cby_2__1__mux_2level_size10_3 ( in , sram , sram_inv , out , p0 ) ; +module cby_2__1__mux_2level_size10_3 ( in , sram , sram_inv , out ) ; input [0:9] in ; input [0:3] sram ; input [0:3] sram_inv ; output [0:0] out ; -input p0 ; +wire [0:0] const1_0_const1 ; wire [0:3] local_encoder2to4_0_data ; wire [0:3] local_encoder2to4_0_data_inv ; wire [0:3] local_encoder2to4_1_data ; @@ -998,9 +1106,8 @@ wire [0:0] mux_2level_basis_input4_mem4_0_out ; wire [0:0] mux_2level_basis_input4_mem4_1_out ; wire [0:0] mux_2level_basis_input4_mem4_2_out ; -cby_2__1__const1_12 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__bufbuf_16 sky130_fd_sc_hd__buf_1_0_ ( +cby_2__1__const1_12 const1_0_ ( .const1 ( const1_0_const1 ) ) ; +sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_1_0_ ( .A ( mux_2level_basis_input4_mem4_2_out[0] ) , .X ( out[0] ) ) ; cby_2__1__local_encoder2to4_24 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , .data ( local_encoder2to4_0_data ) , @@ -1019,10 +1126,10 @@ cby_2__1__mux_2level_basis_input4_mem4_46 mux_l1_in_1_ ( .in ( in[4:7] ) , cby_2__1__mux_2level_basis_input4_mem4_47 mux_l2_in_0_ ( .in ( { mux_2level_basis_input4_mem4_0_out[0] , mux_2level_basis_input4_mem4_1_out[0] , - mux_2level_basis_input2_mem2_0_out[0] , SYNOPSYS_UNCONNECTED_2 } ) , + mux_2level_basis_input2_mem2_0_out[0] , const1_0_const1[0] } ) , .mem ( local_encoder2to4_1_data ) , .mem_inv ( local_encoder2to4_1_data_inv ) , - .out ( mux_2level_basis_input4_mem4_2_out ) , .p0 ( p0 ) ) ; + .out ( mux_2level_basis_input4_mem4_2_out ) ) ; cby_2__1__mux_2level_basis_input2_mem2_3 mux_l1_in_2_ ( .in ( in[8:9] ) , .mem ( local_encoder2to4_0_data[0:1] ) , .mem_inv ( local_encoder2to4_0_data_inv[0:1] ) , @@ -1036,26 +1143,36 @@ input [0:1] mem ; input [0:1] mem_inv ; output [0:0] out ; -scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , +wire [0:0] out_inv ; + +scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( ZINV_368_3 ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; +sky130_fd_sc_hd__clkinv_1 ZINV_368_inst_912 ( .A ( in[1] ) , + .Y ( ZINV_368_3 ) ) ; endmodule -module cby_2__1__mux_2level_basis_input4_mem4_44 ( in , mem , mem_inv , out , - p0 ) ; +module cby_2__1__mux_2level_basis_input4_mem4_44 ( in , mem , mem_inv , out ) ; input [0:3] in ; input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; -input p0 ; + +wire [0:0] out_inv ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; -scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( p0 ) , + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; +scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -1065,12 +1182,21 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; -scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , - .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; +scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( ZINV_200_17 ) , + .Q2 ( ZINV_4_10 ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , + .S0 ( mem[2] ) , .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; +sky130_fd_sc_hd__clkinv_1 ZINV_4_inst_952 ( .A ( in[3] ) , .Y ( ZINV_4_10 ) ) ; +sky130_fd_sc_hd__clkinv_1 ZINV_200_inst_1016 ( .A ( in[2] ) , + .Y ( ZINV_200_17 ) ) ; endmodule @@ -1080,12 +1206,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -1102,7 +1234,7 @@ sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ; sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , .Y ( data_inv[2] ) ) ; sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ; -sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ; +sky130_fd_sc_hd__clkinv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ; sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ; sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , .Y ( data_inv[3] ) ) ; @@ -1122,7 +1254,7 @@ sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ; sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , .Y ( data_inv[2] ) ) ; sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ; -sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ; +sky130_fd_sc_hd__clkinv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ; sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ; sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , .Y ( data_inv[3] ) ) ; @@ -1131,16 +1263,18 @@ endmodule module cby_2__1__const1_11 ( const1 ) ; output [0:0] const1 ; + +assign const1[0] = 1'b1 ; endmodule -module cby_2__1__mux_2level_size10_2 ( in , sram , sram_inv , out , p0 ) ; +module cby_2__1__mux_2level_size10_2 ( in , sram , sram_inv , out ) ; input [0:9] in ; input [0:3] sram ; input [0:3] sram_inv ; output [0:0] out ; -input p0 ; +wire [0:0] const1_0_const1 ; wire [0:3] local_encoder2to4_0_data ; wire [0:3] local_encoder2to4_0_data_inv ; wire [0:3] local_encoder2to4_1_data ; @@ -1150,9 +1284,8 @@ wire [0:0] mux_2level_basis_input4_mem4_0_out ; wire [0:0] mux_2level_basis_input4_mem4_1_out ; wire [0:0] mux_2level_basis_input4_mem4_2_out ; -cby_2__1__const1_11 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__bufbuf_16 sky130_fd_sc_hd__buf_1_0_ ( +cby_2__1__const1_11 const1_0_ ( .const1 ( const1_0_const1 ) ) ; +sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_1_0_ ( .A ( mux_2level_basis_input4_mem4_2_out[0] ) , .X ( out[0] ) ) ; cby_2__1__local_encoder2to4_22 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , .data ( local_encoder2to4_0_data ) , @@ -1171,10 +1304,10 @@ cby_2__1__mux_2level_basis_input4_mem4_43 mux_l1_in_1_ ( .in ( in[4:7] ) , cby_2__1__mux_2level_basis_input4_mem4_44 mux_l2_in_0_ ( .in ( { mux_2level_basis_input4_mem4_0_out[0] , mux_2level_basis_input4_mem4_1_out[0] , - mux_2level_basis_input2_mem2_0_out[0] , SYNOPSYS_UNCONNECTED_2 } ) , + mux_2level_basis_input2_mem2_0_out[0] , const1_0_const1[0] } ) , .mem ( local_encoder2to4_1_data ) , .mem_inv ( local_encoder2to4_1_data_inv ) , - .out ( mux_2level_basis_input4_mem4_2_out ) , .p0 ( p0 ) ) ; + .out ( mux_2level_basis_input4_mem4_2_out ) ) ; cby_2__1__mux_2level_basis_input2_mem2_2 mux_l1_in_2_ ( .in ( in[8:9] ) , .mem ( local_encoder2to4_0_data[0:1] ) , .mem_inv ( local_encoder2to4_0_data_inv[0:1] ) , @@ -1188,26 +1321,34 @@ input [0:1] mem ; input [0:1] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule -module cby_2__1__mux_2level_basis_input4_mem4_41 ( in , mem , mem_inv , out , - p0 ) ; +module cby_2__1__mux_2level_basis_input4_mem4_41 ( in , mem , mem_inv , out ) ; input [0:3] in ; input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; -input p0 ; + +wire [0:0] out_inv ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; -scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( p0 ) , + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; +scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -1217,12 +1358,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -1232,12 +1379,20 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; -scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , +wire [0:0] out_inv ; + +scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( ZINV_4_0 ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; -scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; +scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( ZINV_14_0 ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; +sky130_fd_sc_hd__clkinv_1 ZINV_4_inst_878 ( .A ( in[0] ) , .Y ( ZINV_4_0 ) ) ; +sky130_fd_sc_hd__clkinv_1 ZINV_14_inst_886 ( .A ( in[2] ) , .Y ( ZINV_14_0 ) ) ; endmodule @@ -1254,7 +1409,7 @@ sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ; sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , .Y ( data_inv[2] ) ) ; sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ; -sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ; +sky130_fd_sc_hd__clkinv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ; sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ; sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , .Y ( data_inv[3] ) ) ; @@ -1274,7 +1429,7 @@ sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ; sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , .Y ( data_inv[2] ) ) ; sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ; -sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ; +sky130_fd_sc_hd__clkinv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ; sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ; sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , .Y ( data_inv[3] ) ) ; @@ -1283,16 +1438,18 @@ endmodule module cby_2__1__const1_10 ( const1 ) ; output [0:0] const1 ; + +assign const1[0] = 1'b1 ; endmodule -module cby_2__1__mux_2level_size10_1 ( in , sram , sram_inv , out , p0 ) ; +module cby_2__1__mux_2level_size10_1 ( in , sram , sram_inv , out ) ; input [0:9] in ; input [0:3] sram ; input [0:3] sram_inv ; output [0:0] out ; -input p0 ; +wire [0:0] const1_0_const1 ; wire [0:3] local_encoder2to4_0_data ; wire [0:3] local_encoder2to4_0_data_inv ; wire [0:3] local_encoder2to4_1_data ; @@ -1302,9 +1459,8 @@ wire [0:0] mux_2level_basis_input4_mem4_0_out ; wire [0:0] mux_2level_basis_input4_mem4_1_out ; wire [0:0] mux_2level_basis_input4_mem4_2_out ; -cby_2__1__const1_10 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__bufbuf_16 sky130_fd_sc_hd__buf_1_0_ ( +cby_2__1__const1_10 const1_0_ ( .const1 ( const1_0_const1 ) ) ; +sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_1_0_ ( .A ( mux_2level_basis_input4_mem4_2_out[0] ) , .X ( out[0] ) ) ; cby_2__1__local_encoder2to4_20 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , .data ( local_encoder2to4_0_data ) , @@ -1323,10 +1479,10 @@ cby_2__1__mux_2level_basis_input4_mem4_40 mux_l1_in_1_ ( .in ( in[4:7] ) , cby_2__1__mux_2level_basis_input4_mem4_41 mux_l2_in_0_ ( .in ( { mux_2level_basis_input4_mem4_0_out[0] , mux_2level_basis_input4_mem4_1_out[0] , - mux_2level_basis_input2_mem2_0_out[0] , SYNOPSYS_UNCONNECTED_2 } ) , + mux_2level_basis_input2_mem2_0_out[0] , const1_0_const1[0] } ) , .mem ( local_encoder2to4_1_data ) , .mem_inv ( local_encoder2to4_1_data_inv ) , - .out ( mux_2level_basis_input4_mem4_2_out ) , .p0 ( p0 ) ) ; + .out ( mux_2level_basis_input4_mem4_2_out ) ) ; cby_2__1__mux_2level_basis_input2_mem2_1 mux_l1_in_2_ ( .in ( in[8:9] ) , .mem ( local_encoder2to4_0_data[0:1] ) , .mem_inv ( local_encoder2to4_0_data_inv[0:1] ) , @@ -1340,26 +1496,37 @@ input [0:1] mem ; input [0:1] mem_inv ; output [0:0] out ; -scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , - .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; +wire [0:0] out_inv ; + +scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( ZINV_4_14 ) , + .Q2 ( ZINV_810_17 ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , + .S0 ( mem[0] ) , .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; +sky130_fd_sc_hd__clkinv_1 ZINV_4_inst_978 ( .A ( in[0] ) , .Y ( ZINV_4_14 ) ) ; +sky130_fd_sc_hd__clkinv_1 ZINV_810_inst_1034 ( .A ( in[1] ) , + .Y ( ZINV_810_17 ) ) ; endmodule -module cby_2__1__mux_2level_basis_input4_mem4_38 ( in , mem , mem_inv , out , - p0 ) ; +module cby_2__1__mux_2level_basis_input4_mem4_38 ( in , mem , mem_inv , out ) ; input [0:3] in ; input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; -input p0 ; + +wire [0:0] out_inv ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; -scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( p0 ) , + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; +scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -1369,12 +1536,19 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; -scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , +wire [0:0] out_inv ; + +scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( ZINV_4_15 ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; +sky130_fd_sc_hd__clkinv_1 ZINV_4_inst_994 ( .A ( in[0] ) , .Y ( ZINV_4_15 ) ) ; endmodule @@ -1384,12 +1558,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -1406,7 +1586,7 @@ sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ; sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , .Y ( data_inv[2] ) ) ; sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ; -sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ; +sky130_fd_sc_hd__clkinv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ; sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ; sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , .Y ( data_inv[3] ) ) ; @@ -1426,7 +1606,7 @@ sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ; sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , .Y ( data_inv[2] ) ) ; sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ; -sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ; +sky130_fd_sc_hd__clkinv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ; sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ; sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , .Y ( data_inv[3] ) ) ; @@ -1435,16 +1615,18 @@ endmodule module cby_2__1__const1_9 ( const1 ) ; output [0:0] const1 ; + +assign const1[0] = 1'b1 ; endmodule -module cby_2__1__mux_2level_size10_0 ( in , sram , sram_inv , out , p0 ) ; +module cby_2__1__mux_2level_size10_0 ( in , sram , sram_inv , out ) ; input [0:9] in ; input [0:3] sram ; input [0:3] sram_inv ; output [0:0] out ; -input p0 ; +wire [0:0] const1_0_const1 ; wire [0:3] local_encoder2to4_0_data ; wire [0:3] local_encoder2to4_0_data_inv ; wire [0:3] local_encoder2to4_1_data ; @@ -1454,9 +1636,8 @@ wire [0:0] mux_2level_basis_input4_mem4_0_out ; wire [0:0] mux_2level_basis_input4_mem4_1_out ; wire [0:0] mux_2level_basis_input4_mem4_2_out ; -cby_2__1__const1_9 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__bufbuf_16 sky130_fd_sc_hd__buf_1_0_ ( +cby_2__1__const1_9 const1_0_ ( .const1 ( const1_0_const1 ) ) ; +sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_1_0_ ( .A ( mux_2level_basis_input4_mem4_2_out[0] ) , .X ( out[0] ) ) ; cby_2__1__local_encoder2to4_18 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , .data ( local_encoder2to4_0_data ) , @@ -1475,10 +1656,10 @@ cby_2__1__mux_2level_basis_input4_mem4_37 mux_l1_in_1_ ( .in ( in[4:7] ) , cby_2__1__mux_2level_basis_input4_mem4_38 mux_l2_in_0_ ( .in ( { mux_2level_basis_input4_mem4_0_out[0] , mux_2level_basis_input4_mem4_1_out[0] , - mux_2level_basis_input2_mem2_0_out[0] , SYNOPSYS_UNCONNECTED_2 } ) , + mux_2level_basis_input2_mem2_0_out[0] , const1_0_const1[0] } ) , .mem ( local_encoder2to4_1_data ) , .mem_inv ( local_encoder2to4_1_data_inv ) , - .out ( mux_2level_basis_input4_mem4_2_out ) , .p0 ( p0 ) ) ; + .out ( mux_2level_basis_input4_mem4_2_out ) ) ; cby_2__1__mux_2level_basis_input2_mem2_0 mux_l1_in_2_ ( .in ( in[8:9] ) , .mem ( local_encoder2to4_0_data[0:1] ) , .mem_inv ( local_encoder2to4_0_data_inv[0:1] ) , @@ -1494,6 +1675,8 @@ input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; +assign ccff_tail[0] = mem_out[3] ; + sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , @@ -1502,7 +1685,6 @@ sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__buf_1 FTB_9__8 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -1514,6 +1696,8 @@ input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; +assign ccff_tail[0] = mem_out[3] ; + sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , @@ -1522,7 +1706,6 @@ sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__buf_1 FTB_8__7 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -1534,6 +1717,8 @@ input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; +assign ccff_tail[0] = mem_out[3] ; + sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , @@ -1542,7 +1727,6 @@ sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__buf_1 FTB_7__6 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -1554,6 +1738,8 @@ input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; +assign ccff_tail[0] = mem_out[3] ; + sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , @@ -1562,7 +1748,6 @@ sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__buf_1 FTB_6__5 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -1574,6 +1759,8 @@ input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; +assign ccff_tail[0] = mem_out[3] ; + sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , @@ -1582,7 +1769,6 @@ sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__buf_1 FTB_5__4 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -1594,6 +1780,8 @@ input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; +assign ccff_tail[0] = mem_out[3] ; + sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , @@ -1602,7 +1790,6 @@ sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__buf_1 FTB_4__3 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -1614,6 +1801,8 @@ input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; +assign ccff_tail[0] = mem_out[3] ; + sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , @@ -1622,7 +1811,6 @@ sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__buf_1 FTB_3__2 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -1634,6 +1822,8 @@ input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; +assign ccff_tail[0] = mem_out[3] ; + sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , @@ -1642,7 +1832,6 @@ sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__buf_1 FTB_2__1 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -1654,7 +1843,9 @@ input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( copt_net_106 ) , +assign ccff_tail[0] = mem_out[3] ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ropt_net_6 ) , .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; @@ -1662,44 +1853,31 @@ sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__buf_1 FTB_1__0 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1346 ( .A ( copt_net_117 ) , - .X ( copt_net_106 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1347 ( .A ( ccff_head[0] ) , - .X ( copt_net_107 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1348 ( .A ( copt_net_107 ) , - .X ( copt_net_108 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1349 ( .A ( ropt_net_121 ) , - .X ( copt_net_109 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1350 ( .A ( copt_net_108 ) , - .X ( copt_net_110 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 copt_h_inst_1357 ( .A ( ropt_net_119 ) , - .X ( copt_net_117 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1358 ( .A ( copt_net_109 ) , - .X ( ropt_net_118 ) ) ; -sky130_fd_sc_hd__buf_2 ropt_h_inst_1359 ( .A ( ropt_net_118 ) , - .X ( ropt_net_119 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1360 ( .A ( copt_net_110 ) , - .X ( ropt_net_120 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1361 ( .A ( ropt_net_120 ) , - .X ( ropt_net_121 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1044 ( .A ( ccff_head[0] ) , + .X ( ropt_net_5 ) ) ; +sky130_fd_sc_hd__clkbuf_2 ropt_h_inst_1045 ( .A ( ropt_net_5 ) , + .X ( ropt_net_6 ) ) ; endmodule -module cby_2__1__mux_2level_basis_input4_mem4_35 ( in , mem , mem_inv , out , - p0 ) ; +module cby_2__1__mux_2level_basis_input4_mem4_35 ( in , mem , mem_inv , out ) ; input [0:3] in ; input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; -input p0 ; + +wire [0:0] out_inv ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; -scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( p0 ) , + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; +scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -1709,12 +1887,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -1724,12 +1908,20 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; -scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; +scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( ZINV_11_12 ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; +sky130_fd_sc_hd__clkinv_1 ZINV_11_inst_968 ( .A ( in[2] ) , + .Y ( ZINV_11_12 ) ) ; endmodule @@ -1739,12 +1931,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -1761,7 +1959,7 @@ sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ; sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , .Y ( data_inv[2] ) ) ; sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ; -sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ; +sky130_fd_sc_hd__clkinv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ; sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ; sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , .Y ( data_inv[3] ) ) ; @@ -1781,7 +1979,7 @@ sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ; sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , .Y ( data_inv[2] ) ) ; sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ; -sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ; +sky130_fd_sc_hd__clkinv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ; sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ; sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , .Y ( data_inv[3] ) ) ; @@ -1790,16 +1988,18 @@ endmodule module cby_2__1__const1_8 ( const1 ) ; output [0:0] const1 ; + +assign const1[0] = 1'b1 ; endmodule -module cby_2__1__mux_2level_size12 ( in , sram , sram_inv , out , p0 ) ; +module cby_2__1__mux_2level_size12 ( in , sram , sram_inv , out ) ; input [0:11] in ; input [0:3] sram ; input [0:3] sram_inv ; output [0:0] out ; -input p0 ; +wire [0:0] const1_0_const1 ; wire [0:3] local_encoder2to4_0_data ; wire [0:3] local_encoder2to4_0_data_inv ; wire [0:3] local_encoder2to4_1_data ; @@ -1809,10 +2009,9 @@ wire [0:0] mux_2level_basis_input4_mem4_1_out ; wire [0:0] mux_2level_basis_input4_mem4_2_out ; wire [0:0] mux_2level_basis_input4_mem4_3_out ; -cby_2__1__const1_8 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +cby_2__1__const1_8 const1_0_ ( .const1 ( const1_0_const1 ) ) ; sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_1_0_ ( - .A ( mux_2level_basis_input4_mem4_3_out[0] ) , .X ( aps_rename_508_ ) ) ; + .A ( mux_2level_basis_input4_mem4_3_out[0] ) , .X ( out[0] ) ) ; cby_2__1__local_encoder2to4_16 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , .data ( local_encoder2to4_0_data ) , .data_inv ( local_encoder2to4_0_data_inv ) ) ; @@ -1834,30 +2033,31 @@ cby_2__1__mux_2level_basis_input4_mem4_34 mux_l1_in_2_ ( .in ( in[8:11] ) , cby_2__1__mux_2level_basis_input4_mem4_35 mux_l2_in_0_ ( .in ( { mux_2level_basis_input4_mem4_0_out[0] , mux_2level_basis_input4_mem4_1_out[0] , - mux_2level_basis_input4_mem4_2_out[0] , SYNOPSYS_UNCONNECTED_2 } ) , + mux_2level_basis_input4_mem4_2_out[0] , const1_0_const1[0] } ) , .mem ( local_encoder2to4_1_data ) , .mem_inv ( local_encoder2to4_1_data_inv ) , - .out ( mux_2level_basis_input4_mem4_3_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_90 ( .A ( BUF_net_91 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_91 ( .A ( aps_rename_508_ ) , - .Y ( BUF_net_91 ) ) ; + .out ( mux_2level_basis_input4_mem4_3_out ) ) ; endmodule -module cby_2__1__mux_2level_basis_input4_mem4_31 ( in , mem , mem_inv , out , - p0 ) ; +module cby_2__1__mux_2level_basis_input4_mem4_31 ( in , mem , mem_inv , out ) ; input [0:3] in ; input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; -input p0 ; + +wire [0:0] out_inv ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; -scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( p0 ) , + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; +scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -1867,12 +2067,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -1882,12 +2088,20 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; -scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , +wire [0:0] out_inv ; + +scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( ZINV_7_4 ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; -scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; +scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( ZINV_7_6 ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; +sky130_fd_sc_hd__clkinv_1 ZINV_7_inst_922 ( .A ( in[0] ) , .Y ( ZINV_7_4 ) ) ; +sky130_fd_sc_hd__clkinv_1 ZINV_7_inst_935 ( .A ( in[2] ) , .Y ( ZINV_7_6 ) ) ; endmodule @@ -1897,12 +2111,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -1919,7 +2139,7 @@ sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ; sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , .Y ( data_inv[2] ) ) ; sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ; -sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ; +sky130_fd_sc_hd__clkinv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ; sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ; sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , .Y ( data_inv[3] ) ) ; @@ -1939,7 +2159,7 @@ sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ; sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , .Y ( data_inv[2] ) ) ; sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ; -sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ; +sky130_fd_sc_hd__clkinv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ; sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ; sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , .Y ( data_inv[3] ) ) ; @@ -1948,16 +2168,18 @@ endmodule module cby_2__1__const1_7 ( const1 ) ; output [0:0] const1 ; + +assign const1[0] = 1'b1 ; endmodule -module cby_2__1__mux_2level_size12_7 ( in , sram , sram_inv , out , p0 ) ; +module cby_2__1__mux_2level_size12_7 ( in , sram , sram_inv , out ) ; input [0:11] in ; input [0:3] sram ; input [0:3] sram_inv ; output [0:0] out ; -input p0 ; +wire [0:0] const1_0_const1 ; wire [0:3] local_encoder2to4_0_data ; wire [0:3] local_encoder2to4_0_data_inv ; wire [0:3] local_encoder2to4_1_data ; @@ -1967,9 +2189,8 @@ wire [0:0] mux_2level_basis_input4_mem4_1_out ; wire [0:0] mux_2level_basis_input4_mem4_2_out ; wire [0:0] mux_2level_basis_input4_mem4_3_out ; -cby_2__1__const1_7 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__bufbuf_16 sky130_fd_sc_hd__buf_1_0_ ( +cby_2__1__const1_7 const1_0_ ( .const1 ( const1_0_const1 ) ) ; +sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_1_0_ ( .A ( mux_2level_basis_input4_mem4_3_out[0] ) , .X ( out[0] ) ) ; cby_2__1__local_encoder2to4_14 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , .data ( local_encoder2to4_0_data ) , @@ -1992,27 +2213,31 @@ cby_2__1__mux_2level_basis_input4_mem4_30 mux_l1_in_2_ ( .in ( in[8:11] ) , cby_2__1__mux_2level_basis_input4_mem4_31 mux_l2_in_0_ ( .in ( { mux_2level_basis_input4_mem4_0_out[0] , mux_2level_basis_input4_mem4_1_out[0] , - mux_2level_basis_input4_mem4_2_out[0] , SYNOPSYS_UNCONNECTED_2 } ) , + mux_2level_basis_input4_mem4_2_out[0] , const1_0_const1[0] } ) , .mem ( local_encoder2to4_1_data ) , .mem_inv ( local_encoder2to4_1_data_inv ) , - .out ( mux_2level_basis_input4_mem4_3_out ) , .p0 ( p0 ) ) ; + .out ( mux_2level_basis_input4_mem4_3_out ) ) ; endmodule -module cby_2__1__mux_2level_basis_input4_mem4_27 ( in , mem , mem_inv , out , - p0 ) ; +module cby_2__1__mux_2level_basis_input4_mem4_27 ( in , mem , mem_inv , out ) ; input [0:3] in ; input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; -input p0 ; + +wire [0:0] out_inv ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; -scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( p0 ) , + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; +scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -2022,12 +2247,19 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; -scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , +wire [0:0] out_inv ; + +scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( ZINV_7_3 ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; +sky130_fd_sc_hd__clkinv_1 ZINV_7_inst_919 ( .A ( in[0] ) , .Y ( ZINV_7_3 ) ) ; endmodule @@ -2037,12 +2269,19 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; -scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , +wire [0:0] out_inv ; + +scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( ZINV_4_3 ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; +sky130_fd_sc_hd__clkinv_1 ZINV_4_inst_916 ( .A ( in[0] ) , .Y ( ZINV_4_3 ) ) ; endmodule @@ -2052,12 +2291,19 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; -scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , +wire [0:0] out_inv ; + +scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( ZINV_10_3 ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; +sky130_fd_sc_hd__clkinv_1 ZINV_10_inst_907 ( .A ( in[0] ) , .Y ( ZINV_10_3 ) ) ; endmodule @@ -2074,7 +2320,7 @@ sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ; sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , .Y ( data_inv[2] ) ) ; sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ; -sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ; +sky130_fd_sc_hd__clkinv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ; sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ; sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , .Y ( data_inv[3] ) ) ; @@ -2094,7 +2340,7 @@ sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ; sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , .Y ( data_inv[2] ) ) ; sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ; -sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ; +sky130_fd_sc_hd__clkinv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ; sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ; sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , .Y ( data_inv[3] ) ) ; @@ -2103,16 +2349,18 @@ endmodule module cby_2__1__const1_6 ( const1 ) ; output [0:0] const1 ; + +assign const1[0] = 1'b1 ; endmodule -module cby_2__1__mux_2level_size12_6 ( in , sram , sram_inv , out , p0 ) ; +module cby_2__1__mux_2level_size12_6 ( in , sram , sram_inv , out ) ; input [0:11] in ; input [0:3] sram ; input [0:3] sram_inv ; output [0:0] out ; -input p0 ; +wire [0:0] const1_0_const1 ; wire [0:3] local_encoder2to4_0_data ; wire [0:3] local_encoder2to4_0_data_inv ; wire [0:3] local_encoder2to4_1_data ; @@ -2122,10 +2370,9 @@ wire [0:0] mux_2level_basis_input4_mem4_1_out ; wire [0:0] mux_2level_basis_input4_mem4_2_out ; wire [0:0] mux_2level_basis_input4_mem4_3_out ; -cby_2__1__const1_6 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +cby_2__1__const1_6 const1_0_ ( .const1 ( const1_0_const1 ) ) ; sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_1_0_ ( - .A ( mux_2level_basis_input4_mem4_3_out[0] ) , .X ( aps_rename_507_ ) ) ; + .A ( mux_2level_basis_input4_mem4_3_out[0] ) , .X ( out[0] ) ) ; cby_2__1__local_encoder2to4_12 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , .data ( local_encoder2to4_0_data ) , .data_inv ( local_encoder2to4_0_data_inv ) ) ; @@ -2147,30 +2394,31 @@ cby_2__1__mux_2level_basis_input4_mem4_26 mux_l1_in_2_ ( .in ( in[8:11] ) , cby_2__1__mux_2level_basis_input4_mem4_27 mux_l2_in_0_ ( .in ( { mux_2level_basis_input4_mem4_0_out[0] , mux_2level_basis_input4_mem4_1_out[0] , - mux_2level_basis_input4_mem4_2_out[0] , SYNOPSYS_UNCONNECTED_2 } ) , + mux_2level_basis_input4_mem4_2_out[0] , const1_0_const1[0] } ) , .mem ( local_encoder2to4_1_data ) , .mem_inv ( local_encoder2to4_1_data_inv ) , - .out ( mux_2level_basis_input4_mem4_3_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_6 BINV_R_88 ( .A ( BUF_net_89 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_89 ( .A ( aps_rename_507_ ) , - .Y ( BUF_net_89 ) ) ; + .out ( mux_2level_basis_input4_mem4_3_out ) ) ; endmodule -module cby_2__1__mux_2level_basis_input4_mem4_23 ( in , mem , mem_inv , out , - p0 ) ; +module cby_2__1__mux_2level_basis_input4_mem4_23 ( in , mem , mem_inv , out ) ; input [0:3] in ; input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; -input p0 ; + +wire [0:0] out_inv ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; -scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( p0 ) , + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; +scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -2180,12 +2428,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -2195,12 +2449,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -2210,12 +2470,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -2232,7 +2498,7 @@ sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ; sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , .Y ( data_inv[2] ) ) ; sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ; -sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ; +sky130_fd_sc_hd__clkinv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ; sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ; sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , .Y ( data_inv[3] ) ) ; @@ -2252,7 +2518,7 @@ sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ; sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , .Y ( data_inv[2] ) ) ; sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ; -sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ; +sky130_fd_sc_hd__clkinv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ; sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ; sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , .Y ( data_inv[3] ) ) ; @@ -2261,16 +2527,18 @@ endmodule module cby_2__1__const1_5 ( const1 ) ; output [0:0] const1 ; + +assign const1[0] = 1'b1 ; endmodule -module cby_2__1__mux_2level_size12_5 ( in , sram , sram_inv , out , p0 ) ; +module cby_2__1__mux_2level_size12_5 ( in , sram , sram_inv , out ) ; input [0:11] in ; input [0:3] sram ; input [0:3] sram_inv ; output [0:0] out ; -input p0 ; +wire [0:0] const1_0_const1 ; wire [0:3] local_encoder2to4_0_data ; wire [0:3] local_encoder2to4_0_data_inv ; wire [0:3] local_encoder2to4_1_data ; @@ -2280,10 +2548,9 @@ wire [0:0] mux_2level_basis_input4_mem4_1_out ; wire [0:0] mux_2level_basis_input4_mem4_2_out ; wire [0:0] mux_2level_basis_input4_mem4_3_out ; -cby_2__1__const1_5 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +cby_2__1__const1_5 const1_0_ ( .const1 ( const1_0_const1 ) ) ; sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_1_0_ ( - .A ( mux_2level_basis_input4_mem4_3_out[0] ) , .X ( aps_rename_506_ ) ) ; + .A ( mux_2level_basis_input4_mem4_3_out[0] ) , .X ( out[0] ) ) ; cby_2__1__local_encoder2to4_10 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , .data ( local_encoder2to4_0_data ) , .data_inv ( local_encoder2to4_0_data_inv ) ) ; @@ -2305,30 +2572,31 @@ cby_2__1__mux_2level_basis_input4_mem4_22 mux_l1_in_2_ ( .in ( in[8:11] ) , cby_2__1__mux_2level_basis_input4_mem4_23 mux_l2_in_0_ ( .in ( { mux_2level_basis_input4_mem4_0_out[0] , mux_2level_basis_input4_mem4_1_out[0] , - mux_2level_basis_input4_mem4_2_out[0] , SYNOPSYS_UNCONNECTED_2 } ) , + mux_2level_basis_input4_mem4_2_out[0] , const1_0_const1[0] } ) , .mem ( local_encoder2to4_1_data ) , .mem_inv ( local_encoder2to4_1_data_inv ) , - .out ( mux_2level_basis_input4_mem4_3_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_86 ( .A ( BUF_net_87 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_87 ( .A ( aps_rename_506_ ) , - .Y ( BUF_net_87 ) ) ; + .out ( mux_2level_basis_input4_mem4_3_out ) ) ; endmodule -module cby_2__1__mux_2level_basis_input4_mem4_19 ( in , mem , mem_inv , out , - p0 ) ; +module cby_2__1__mux_2level_basis_input4_mem4_19 ( in , mem , mem_inv , out ) ; input [0:3] in ; input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; -input p0 ; + +wire [0:0] out_inv ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; -scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( p0 ) , + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; +scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -2338,12 +2606,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -2353,12 +2627,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -2368,12 +2648,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -2390,7 +2676,7 @@ sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ; sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , .Y ( data_inv[2] ) ) ; sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ; -sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ; +sky130_fd_sc_hd__clkinv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ; sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ; sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , .Y ( data_inv[3] ) ) ; @@ -2410,7 +2696,7 @@ sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ; sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , .Y ( data_inv[2] ) ) ; sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ; -sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ; +sky130_fd_sc_hd__clkinv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ; sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ; sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , .Y ( data_inv[3] ) ) ; @@ -2419,16 +2705,18 @@ endmodule module cby_2__1__const1_4 ( const1 ) ; output [0:0] const1 ; + +assign const1[0] = 1'b1 ; endmodule -module cby_2__1__mux_2level_size12_4 ( in , sram , sram_inv , out , p0 ) ; +module cby_2__1__mux_2level_size12_4 ( in , sram , sram_inv , out ) ; input [0:11] in ; input [0:3] sram ; input [0:3] sram_inv ; output [0:0] out ; -input p0 ; +wire [0:0] const1_0_const1 ; wire [0:3] local_encoder2to4_0_data ; wire [0:3] local_encoder2to4_0_data_inv ; wire [0:3] local_encoder2to4_1_data ; @@ -2438,10 +2726,9 @@ wire [0:0] mux_2level_basis_input4_mem4_1_out ; wire [0:0] mux_2level_basis_input4_mem4_2_out ; wire [0:0] mux_2level_basis_input4_mem4_3_out ; -cby_2__1__const1_4 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +cby_2__1__const1_4 const1_0_ ( .const1 ( const1_0_const1 ) ) ; sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_1_0_ ( - .A ( mux_2level_basis_input4_mem4_3_out[0] ) , .X ( aps_rename_505_ ) ) ; + .A ( mux_2level_basis_input4_mem4_3_out[0] ) , .X ( out[0] ) ) ; cby_2__1__local_encoder2to4_8 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , .data ( local_encoder2to4_0_data ) , .data_inv ( local_encoder2to4_0_data_inv ) ) ; @@ -2463,30 +2750,31 @@ cby_2__1__mux_2level_basis_input4_mem4_18 mux_l1_in_2_ ( .in ( in[8:11] ) , cby_2__1__mux_2level_basis_input4_mem4_19 mux_l2_in_0_ ( .in ( { mux_2level_basis_input4_mem4_0_out[0] , mux_2level_basis_input4_mem4_1_out[0] , - mux_2level_basis_input4_mem4_2_out[0] , SYNOPSYS_UNCONNECTED_2 } ) , + mux_2level_basis_input4_mem4_2_out[0] , const1_0_const1[0] } ) , .mem ( local_encoder2to4_1_data ) , .mem_inv ( local_encoder2to4_1_data_inv ) , - .out ( mux_2level_basis_input4_mem4_3_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_84 ( .A ( BUF_net_85 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_85 ( .A ( aps_rename_505_ ) , - .Y ( BUF_net_85 ) ) ; + .out ( mux_2level_basis_input4_mem4_3_out ) ) ; endmodule -module cby_2__1__mux_2level_basis_input4_mem4_15 ( in , mem , mem_inv , out , - p0 ) ; +module cby_2__1__mux_2level_basis_input4_mem4_15 ( in , mem , mem_inv , out ) ; input [0:3] in ; input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; -input p0 ; + +wire [0:0] out_inv ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; -scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( p0 ) , + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; +scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -2496,12 +2784,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -2511,12 +2805,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -2526,12 +2826,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -2548,7 +2854,7 @@ sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ; sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , .Y ( data_inv[2] ) ) ; sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ; -sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ; +sky130_fd_sc_hd__clkinv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ; sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ; sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , .Y ( data_inv[3] ) ) ; @@ -2568,7 +2874,7 @@ sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ; sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , .Y ( data_inv[2] ) ) ; sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ; -sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ; +sky130_fd_sc_hd__clkinv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ; sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ; sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , .Y ( data_inv[3] ) ) ; @@ -2577,16 +2883,18 @@ endmodule module cby_2__1__const1_3 ( const1 ) ; output [0:0] const1 ; + +assign const1[0] = 1'b1 ; endmodule -module cby_2__1__mux_2level_size12_3 ( in , sram , sram_inv , out , p0 ) ; +module cby_2__1__mux_2level_size12_3 ( in , sram , sram_inv , out ) ; input [0:11] in ; input [0:3] sram ; input [0:3] sram_inv ; output [0:0] out ; -input p0 ; +wire [0:0] const1_0_const1 ; wire [0:3] local_encoder2to4_0_data ; wire [0:3] local_encoder2to4_0_data_inv ; wire [0:3] local_encoder2to4_1_data ; @@ -2596,10 +2904,9 @@ wire [0:0] mux_2level_basis_input4_mem4_1_out ; wire [0:0] mux_2level_basis_input4_mem4_2_out ; wire [0:0] mux_2level_basis_input4_mem4_3_out ; -cby_2__1__const1_3 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +cby_2__1__const1_3 const1_0_ ( .const1 ( const1_0_const1 ) ) ; sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_1_0_ ( - .A ( mux_2level_basis_input4_mem4_3_out[0] ) , .X ( net_net_83 ) ) ; + .A ( mux_2level_basis_input4_mem4_3_out[0] ) , .X ( out[0] ) ) ; cby_2__1__local_encoder2to4_6 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , .data ( local_encoder2to4_0_data ) , .data_inv ( local_encoder2to4_0_data_inv ) ) ; @@ -2621,28 +2928,31 @@ cby_2__1__mux_2level_basis_input4_mem4_14 mux_l1_in_2_ ( .in ( in[8:11] ) , cby_2__1__mux_2level_basis_input4_mem4_15 mux_l2_in_0_ ( .in ( { mux_2level_basis_input4_mem4_0_out[0] , mux_2level_basis_input4_mem4_1_out[0] , - mux_2level_basis_input4_mem4_2_out[0] , SYNOPSYS_UNCONNECTED_2 } ) , + mux_2level_basis_input4_mem4_2_out[0] , const1_0_const1[0] } ) , .mem ( local_encoder2to4_1_data ) , .mem_inv ( local_encoder2to4_1_data_inv ) , - .out ( mux_2level_basis_input4_mem4_3_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_83 ( .A ( net_net_83 ) , .X ( out[0] ) ) ; + .out ( mux_2level_basis_input4_mem4_3_out ) ) ; endmodule -module cby_2__1__mux_2level_basis_input4_mem4_11 ( in , mem , mem_inv , out , - p0 ) ; +module cby_2__1__mux_2level_basis_input4_mem4_11 ( in , mem , mem_inv , out ) ; input [0:3] in ; input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; -input p0 ; + +wire [0:0] out_inv ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; -scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( p0 ) , + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; +scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -2652,12 +2962,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -2667,12 +2983,21 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; -scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , +wire [0:0] out_inv ; + +scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( ZINV_7_7 ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; -scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; +scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( ZINV_11_13 ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; +sky130_fd_sc_hd__clkinv_1 ZINV_7_inst_939 ( .A ( in[1] ) , .Y ( ZINV_7_7 ) ) ; +sky130_fd_sc_hd__clkinv_1 ZINV_11_inst_971 ( .A ( in[3] ) , + .Y ( ZINV_11_13 ) ) ; endmodule @@ -2682,12 +3007,19 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; -scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , +wire [0:0] out_inv ; + +scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( ZINV_13_0 ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; +sky130_fd_sc_hd__clkinv_1 ZINV_13_inst_889 ( .A ( in[1] ) , .Y ( ZINV_13_0 ) ) ; endmodule @@ -2704,7 +3036,7 @@ sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ; sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , .Y ( data_inv[2] ) ) ; sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ; -sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ; +sky130_fd_sc_hd__clkinv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ; sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ; sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , .Y ( data_inv[3] ) ) ; @@ -2724,7 +3056,7 @@ sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ; sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , .Y ( data_inv[2] ) ) ; sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ; -sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ; +sky130_fd_sc_hd__clkinv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ; sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ; sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , .Y ( data_inv[3] ) ) ; @@ -2733,16 +3065,18 @@ endmodule module cby_2__1__const1_2 ( const1 ) ; output [0:0] const1 ; + +assign const1[0] = 1'b1 ; endmodule -module cby_2__1__mux_2level_size12_2 ( in , sram , sram_inv , out , p0 ) ; +module cby_2__1__mux_2level_size12_2 ( in , sram , sram_inv , out ) ; input [0:11] in ; input [0:3] sram ; input [0:3] sram_inv ; output [0:0] out ; -input p0 ; +wire [0:0] const1_0_const1 ; wire [0:3] local_encoder2to4_0_data ; wire [0:3] local_encoder2to4_0_data_inv ; wire [0:3] local_encoder2to4_1_data ; @@ -2752,9 +3086,8 @@ wire [0:0] mux_2level_basis_input4_mem4_1_out ; wire [0:0] mux_2level_basis_input4_mem4_2_out ; wire [0:0] mux_2level_basis_input4_mem4_3_out ; -cby_2__1__const1_2 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__bufbuf_16 sky130_fd_sc_hd__buf_1_0_ ( +cby_2__1__const1_2 const1_0_ ( .const1 ( const1_0_const1 ) ) ; +sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_1_0_ ( .A ( mux_2level_basis_input4_mem4_3_out[0] ) , .X ( out[0] ) ) ; cby_2__1__local_encoder2to4_4 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , .data ( local_encoder2to4_0_data ) , @@ -2777,27 +3110,31 @@ cby_2__1__mux_2level_basis_input4_mem4_10 mux_l1_in_2_ ( .in ( in[8:11] ) , cby_2__1__mux_2level_basis_input4_mem4_11 mux_l2_in_0_ ( .in ( { mux_2level_basis_input4_mem4_0_out[0] , mux_2level_basis_input4_mem4_1_out[0] , - mux_2level_basis_input4_mem4_2_out[0] , SYNOPSYS_UNCONNECTED_2 } ) , + mux_2level_basis_input4_mem4_2_out[0] , const1_0_const1[0] } ) , .mem ( local_encoder2to4_1_data ) , .mem_inv ( local_encoder2to4_1_data_inv ) , - .out ( mux_2level_basis_input4_mem4_3_out ) , .p0 ( p0 ) ) ; + .out ( mux_2level_basis_input4_mem4_3_out ) ) ; endmodule -module cby_2__1__mux_2level_basis_input4_mem4_7 ( in , mem , mem_inv , out , - p0 ) ; +module cby_2__1__mux_2level_basis_input4_mem4_7 ( in , mem , mem_inv , out ) ; input [0:3] in ; input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; -input p0 ; + +wire [0:0] out_inv ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; -scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( p0 ) , + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; +scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -2807,12 +3144,22 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; -scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , +wire [0:0] out_inv ; + +scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( ZINV_11_14 ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; -scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; +scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( ZINV_191_1 ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; +sky130_fd_sc_hd__clkinv_1 ZINV_191_inst_898 ( .A ( in[3] ) , + .Y ( ZINV_191_1 ) ) ; +sky130_fd_sc_hd__clkinv_1 ZINV_11_inst_990 ( .A ( in[1] ) , + .Y ( ZINV_11_14 ) ) ; endmodule @@ -2822,12 +3169,19 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; -scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; +scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( ZINV_4_11 ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; +sky130_fd_sc_hd__clkinv_1 ZINV_4_inst_957 ( .A ( in[3] ) , .Y ( ZINV_4_11 ) ) ; endmodule @@ -2837,12 +3191,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -2859,7 +3219,7 @@ sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ; sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , .Y ( data_inv[2] ) ) ; sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ; -sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ; +sky130_fd_sc_hd__clkinv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ; sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ; sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , .Y ( data_inv[3] ) ) ; @@ -2879,7 +3239,7 @@ sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ; sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , .Y ( data_inv[2] ) ) ; sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ; -sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ; +sky130_fd_sc_hd__clkinv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ; sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ; sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , .Y ( data_inv[3] ) ) ; @@ -2888,16 +3248,18 @@ endmodule module cby_2__1__const1_1 ( const1 ) ; output [0:0] const1 ; + +assign const1[0] = 1'b1 ; endmodule -module cby_2__1__mux_2level_size12_1 ( in , sram , sram_inv , out , p0 ) ; +module cby_2__1__mux_2level_size12_1 ( in , sram , sram_inv , out ) ; input [0:11] in ; input [0:3] sram ; input [0:3] sram_inv ; output [0:0] out ; -input p0 ; +wire [0:0] const1_0_const1 ; wire [0:3] local_encoder2to4_0_data ; wire [0:3] local_encoder2to4_0_data_inv ; wire [0:3] local_encoder2to4_1_data ; @@ -2907,9 +3269,8 @@ wire [0:0] mux_2level_basis_input4_mem4_1_out ; wire [0:0] mux_2level_basis_input4_mem4_2_out ; wire [0:0] mux_2level_basis_input4_mem4_3_out ; -cby_2__1__const1_1 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__bufbuf_16 sky130_fd_sc_hd__buf_1_0_ ( +cby_2__1__const1_1 const1_0_ ( .const1 ( const1_0_const1 ) ) ; +sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_1_0_ ( .A ( mux_2level_basis_input4_mem4_3_out[0] ) , .X ( out[0] ) ) ; cby_2__1__local_encoder2to4_2 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , .data ( local_encoder2to4_0_data ) , @@ -2932,27 +3293,31 @@ cby_2__1__mux_2level_basis_input4_mem4_6 mux_l1_in_2_ ( .in ( in[8:11] ) , cby_2__1__mux_2level_basis_input4_mem4_7 mux_l2_in_0_ ( .in ( { mux_2level_basis_input4_mem4_0_out[0] , mux_2level_basis_input4_mem4_1_out[0] , - mux_2level_basis_input4_mem4_2_out[0] , SYNOPSYS_UNCONNECTED_2 } ) , + mux_2level_basis_input4_mem4_2_out[0] , const1_0_const1[0] } ) , .mem ( local_encoder2to4_1_data ) , .mem_inv ( local_encoder2to4_1_data_inv ) , - .out ( mux_2level_basis_input4_mem4_3_out ) , .p0 ( p0 ) ) ; + .out ( mux_2level_basis_input4_mem4_3_out ) ) ; endmodule -module cby_2__1__mux_2level_basis_input4_mem4_3 ( in , mem , mem_inv , out , - p0 ) ; +module cby_2__1__mux_2level_basis_input4_mem4_3 ( in , mem , mem_inv , out ) ; input [0:3] in ; input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; -input p0 ; + +wire [0:0] out_inv ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; -scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( p0 ) , + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; +scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -2962,12 +3327,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -2977,12 +3348,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -2992,12 +3369,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -3014,7 +3397,7 @@ sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ; sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , .Y ( data_inv[2] ) ) ; sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ; -sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ; +sky130_fd_sc_hd__clkinv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ; sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ; sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , .Y ( data_inv[3] ) ) ; @@ -3034,7 +3417,7 @@ sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ; sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , .Y ( data_inv[2] ) ) ; sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ; -sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ; +sky130_fd_sc_hd__clkinv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ; sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ; sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , .Y ( data_inv[3] ) ) ; @@ -3043,16 +3426,18 @@ endmodule module cby_2__1__const1_0 ( const1 ) ; output [0:0] const1 ; + +assign const1[0] = 1'b1 ; endmodule -module cby_2__1__mux_2level_size12_0 ( in , sram , sram_inv , out , p0 ) ; +module cby_2__1__mux_2level_size12_0 ( in , sram , sram_inv , out ) ; input [0:11] in ; input [0:3] sram ; input [0:3] sram_inv ; output [0:0] out ; -input p0 ; +wire [0:0] const1_0_const1 ; wire [0:3] local_encoder2to4_0_data ; wire [0:3] local_encoder2to4_0_data_inv ; wire [0:3] local_encoder2to4_1_data ; @@ -3062,10 +3447,9 @@ wire [0:0] mux_2level_basis_input4_mem4_1_out ; wire [0:0] mux_2level_basis_input4_mem4_2_out ; wire [0:0] mux_2level_basis_input4_mem4_3_out ; -cby_2__1__const1_0 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +cby_2__1__const1_0 const1_0_ ( .const1 ( const1_0_const1 ) ) ; sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_1_0_ ( - .A ( mux_2level_basis_input4_mem4_3_out[0] ) , .X ( net_net_82 ) ) ; + .A ( mux_2level_basis_input4_mem4_3_out[0] ) , .X ( out[0] ) ) ; cby_2__1__local_encoder2to4_0 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , .data ( local_encoder2to4_0_data ) , .data_inv ( local_encoder2to4_0_data_inv ) ) ; @@ -3087,11 +3471,10 @@ cby_2__1__mux_2level_basis_input4_mem4_2 mux_l1_in_2_ ( .in ( in[8:11] ) , cby_2__1__mux_2level_basis_input4_mem4_3 mux_l2_in_0_ ( .in ( { mux_2level_basis_input4_mem4_0_out[0] , mux_2level_basis_input4_mem4_1_out[0] , - mux_2level_basis_input4_mem4_2_out[0] , SYNOPSYS_UNCONNECTED_2 } ) , + mux_2level_basis_input4_mem4_2_out[0] , const1_0_const1[0] } ) , .mem ( local_encoder2to4_1_data ) , .mem_inv ( local_encoder2to4_1_data_inv ) , - .out ( mux_2level_basis_input4_mem4_3_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_82 ( .A ( net_net_82 ) , .X ( out[0] ) ) ; + .out ( mux_2level_basis_input4_mem4_3_out ) ) ; endmodule @@ -3178,90 +3561,99 @@ wire [0:0] mux_2level_size12_mem_5_ccff_tail ; wire [0:0] mux_2level_size12_mem_6_ccff_tail ; wire [0:0] mux_2level_size12_mem_7_ccff_tail ; wire [0:0] mux_2level_size12_mem_8_ccff_tail ; +wire [0:3] mux_left_ipin_0_undriven_sram_inv ; +wire [0:3] mux_right_ipin_0_undriven_sram_inv ; +wire [0:3] mux_right_ipin_10_undriven_sram_inv ; +wire [0:3] mux_right_ipin_11_undriven_sram_inv ; +wire [0:3] mux_right_ipin_12_undriven_sram_inv ; +wire [0:3] mux_right_ipin_13_undriven_sram_inv ; +wire [0:3] mux_right_ipin_14_undriven_sram_inv ; +wire [0:3] mux_right_ipin_15_undriven_sram_inv ; +wire [0:3] mux_right_ipin_1_undriven_sram_inv ; +wire [0:3] mux_right_ipin_2_undriven_sram_inv ; +wire [0:3] mux_right_ipin_3_undriven_sram_inv ; +wire [0:3] mux_right_ipin_4_undriven_sram_inv ; +wire [0:3] mux_right_ipin_5_undriven_sram_inv ; +wire [0:3] mux_right_ipin_6_undriven_sram_inv ; +wire [0:3] mux_right_ipin_7_undriven_sram_inv ; +wire [0:3] mux_right_ipin_8_undriven_sram_inv ; +wire [0:3] mux_right_ipin_9_undriven_sram_inv ; +assign left_width_0_height_0__pin_1_lower[0] = left_width_0_height_0__pin_1_upper[0] ; assign prog_clk_0 = prog_clk[0] ; cby_2__1__mux_2level_size12_0 mux_left_ipin_0 ( - .in ( { chany_top_out[0] , chany_bottom_out[0] , chany_top_out[3] , - chany_bottom_out[3] , chany_top_out[6] , chany_bottom_out[6] , - chany_top_out[12] , chany_bottom_out[12] , chany_top_out[18] , - chany_bottom_out[18] , chany_top_out[24] , chany_bottom_out[24] } ) , - .sram ( mux_2level_size12_0_sram ) , - .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 , - SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) , - .out ( right_grid_pin_0_ ) , .p0 ( optlc_net_101 ) ) ; + .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[3] , + ZINV_195_0 , chany_bottom_in[6] , chany_top_in[6] , + chany_top_out[12] , chany_top_in[12] , chany_bottom_in[18] , + chany_top_in[18] , chany_bottom_in[24] , chany_top_in[24] } ) , + .sram ( mux_2level_size12_0_sram ) , + .sram_inv ( mux_left_ipin_0_undriven_sram_inv ) , + .out ( { ZBUF_660_f_17 } ) ) ; cby_2__1__mux_2level_size12_1 mux_right_ipin_0 ( - .in ( { chany_top_out[1] , chany_bottom_out[1] , chany_top_out[4] , - chany_bottom_out[4] , chany_top_out[7] , chany_bottom_out[7] , - chany_top_out[13] , chany_bottom_out[13] , chany_top_out[19] , - chany_bottom_out[19] , chany_top_out[25] , chany_bottom_out[25] } ) , - .sram ( mux_2level_size12_1_sram ) , - .sram_inv ( { SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 , - SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 } ) , - .out ( left_grid_pin_16_ ) , .p0 ( optlc_net_98 ) ) ; + .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[4] , + chany_top_in[4] , chany_bottom_in[7] , chany_bottom_out[7] , + chany_bottom_in[13] , ZINV_62_11 , chany_bottom_in[19] , ZINV_69_15 , + chany_bottom_in[25] , ZINV_267_1 } ) , + .sram ( mux_2level_size12_1_sram ) , + .sram_inv ( mux_right_ipin_0_undriven_sram_inv ) , + .out ( left_grid_pin_16_ ) ) ; cby_2__1__mux_2level_size12_2 mux_right_ipin_2 ( - .in ( { chany_top_out[0] , chany_bottom_out[0] , chany_top_out[3] , - chany_bottom_out[3] , chany_top_out[9] , chany_bottom_out[9] , - chany_top_out[15] , chany_bottom_out[15] , chany_top_out[21] , - chany_bottom_out[21] , chany_top_out[27] , chany_bottom_out[27] } ) , - .sram ( mux_2level_size12_2_sram ) , - .sram_inv ( { SYNOPSYS_UNCONNECTED_9 , SYNOPSYS_UNCONNECTED_10 , - SYNOPSYS_UNCONNECTED_11 , SYNOPSYS_UNCONNECTED_12 } ) , - .out ( left_grid_pin_18_ ) , .p0 ( optlc_net_99 ) ) ; + .in ( { chany_bottom_in[0] , ZINV_71_0 , chany_bottom_in[3] , ZINV_195_0 , + chany_bottom_in[9] , ZINV_65_7 , chany_bottom_in[15] , ZINV_69_14 , + chany_bottom_in[21] , chany_bottom_out[21] , chany_bottom_in[27] , + chany_top_in[27] } ) , + .sram ( mux_2level_size12_2_sram ) , + .sram_inv ( mux_right_ipin_2_undriven_sram_inv ) , + .out ( left_grid_pin_18_ ) ) ; cby_2__1__mux_2level_size12_3 mux_right_ipin_4 ( - .in ( { chany_top_out[2] , chany_bottom_out[2] , chany_top_out[5] , - chany_bottom_out[5] , chany_top_out[11] , chany_bottom_out[11] , - chany_top_out[17] , chany_bottom_out[17] , chany_top_out[23] , - chany_bottom_out[23] , chany_top_out[29] , chany_bottom_out[29] } ) , - .sram ( mux_2level_size12_3_sram ) , - .sram_inv ( { SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 , - SYNOPSYS_UNCONNECTED_15 , SYNOPSYS_UNCONNECTED_16 } ) , - .out ( left_grid_pin_20_ ) , .p0 ( optlc_net_98 ) ) ; + .in ( { chany_bottom_in[2] , chany_top_in[2] , ZINV_157_1 , + chany_top_in[5] , chany_bottom_in[11] , chany_top_in[11] , + chany_bottom_in[17] , chany_top_in[17] , chany_bottom_in[23] , + chany_top_in[23] , chany_bottom_in[29] , chany_top_in[29] } ) , + .sram ( mux_2level_size12_3_sram ) , + .sram_inv ( mux_right_ipin_4_undriven_sram_inv ) , + .out ( left_grid_pin_20_ ) ) ; cby_2__1__mux_2level_size12_4 mux_right_ipin_6 ( - .in ( { chany_top_out[1] , chany_bottom_out[1] , chany_top_out[4] , - chany_bottom_out[4] , chany_top_out[7] , chany_bottom_out[7] , - chany_top_out[13] , chany_bottom_out[13] , chany_top_out[19] , - chany_bottom_out[19] , chany_top_out[25] , chany_bottom_out[25] } ) , - .sram ( mux_2level_size12_4_sram ) , - .sram_inv ( { SYNOPSYS_UNCONNECTED_17 , SYNOPSYS_UNCONNECTED_18 , - SYNOPSYS_UNCONNECTED_19 , SYNOPSYS_UNCONNECTED_20 } ) , - .out ( left_grid_pin_22_ ) , .p0 ( optlc_net_100 ) ) ; + .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[4] , + chany_top_in[4] , chany_bottom_in[7] , chany_top_in[7] , + chany_bottom_in[13] , chany_top_in[13] , chany_bottom_in[19] , + chany_top_in[19] , chany_bottom_in[25] , chany_top_in[25] } ) , + .sram ( mux_2level_size12_4_sram ) , + .sram_inv ( mux_right_ipin_6_undriven_sram_inv ) , + .out ( left_grid_pin_22_ ) ) ; cby_2__1__mux_2level_size12_5 mux_right_ipin_8 ( - .in ( { chany_top_out[0] , chany_bottom_out[0] , chany_top_out[3] , - chany_bottom_out[3] , chany_top_out[9] , chany_bottom_out[9] , - chany_top_out[15] , chany_bottom_out[15] , chany_top_out[21] , - chany_bottom_out[21] , chany_top_out[27] , chany_bottom_out[27] } ) , - .sram ( mux_2level_size12_5_sram ) , - .sram_inv ( { SYNOPSYS_UNCONNECTED_21 , SYNOPSYS_UNCONNECTED_22 , - SYNOPSYS_UNCONNECTED_23 , SYNOPSYS_UNCONNECTED_24 } ) , - .out ( left_grid_pin_24_ ) , .p0 ( optlc_net_99 ) ) ; + .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[3] , + ZINV_195_0 , chany_bottom_in[9] , chany_top_in[9] , + chany_bottom_in[15] , chany_top_in[15] , chany_bottom_in[21] , + chany_bottom_out[21] , chany_bottom_in[27] , chany_top_in[27] } ) , + .sram ( mux_2level_size12_5_sram ) , + .sram_inv ( mux_right_ipin_8_undriven_sram_inv ) , + .out ( { ZBUF_274_f_16 } ) ) ; cby_2__1__mux_2level_size12_6 mux_right_ipin_10 ( - .in ( { chany_top_out[2] , chany_bottom_out[2] , chany_top_out[5] , - chany_bottom_out[5] , chany_top_out[11] , chany_bottom_out[11] , - chany_top_out[17] , chany_bottom_out[17] , chany_top_out[23] , - chany_bottom_out[23] , chany_top_out[29] , chany_bottom_out[29] } ) , - .sram ( mux_2level_size12_6_sram ) , - .sram_inv ( { SYNOPSYS_UNCONNECTED_25 , SYNOPSYS_UNCONNECTED_26 , - SYNOPSYS_UNCONNECTED_27 , SYNOPSYS_UNCONNECTED_28 } ) , - .out ( left_grid_pin_26_ ) , .p0 ( optlc_net_102 ) ) ; + .in ( { ZINV_68_3 , chany_top_in[2] , ZINV_157_1 , chany_top_in[5] , + ZINV_62_3 , chany_top_in[11] , ZINV_19_4 , chany_top_in[17] , + ZINV_65_3 , chany_top_in[23] , chany_bottom_in[29] , + chany_top_in[29] } ) , + .sram ( mux_2level_size12_6_sram ) , + .sram_inv ( mux_right_ipin_10_undriven_sram_inv ) , + .out ( left_grid_pin_26_ ) ) ; cby_2__1__mux_2level_size12_7 mux_right_ipin_12 ( - .in ( { chany_top_out[1] , chany_bottom_out[1] , chany_top_out[4] , - chany_bottom_out[4] , chany_top_out[7] , chany_bottom_out[7] , - chany_top_out[13] , chany_bottom_out[13] , chany_top_out[19] , - chany_bottom_out[19] , chany_top_out[25] , chany_bottom_out[25] } ) , - .sram ( mux_2level_size12_7_sram ) , - .sram_inv ( { SYNOPSYS_UNCONNECTED_29 , SYNOPSYS_UNCONNECTED_30 , - SYNOPSYS_UNCONNECTED_31 , SYNOPSYS_UNCONNECTED_32 } ) , - .out ( left_grid_pin_28_ ) , .p0 ( optlc_net_100 ) ) ; + .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[4] , + chany_top_in[4] , ZINV_65_4 , chany_top_in[7] , ZINV_65_6 , + chany_top_in[13] , chany_bottom_in[19] , chany_top_in[19] , + chany_bottom_in[25] , chany_top_in[25] } ) , + .sram ( mux_2level_size12_7_sram ) , + .sram_inv ( mux_right_ipin_12_undriven_sram_inv ) , + .out ( { ropt_net_3 } ) ) ; cby_2__1__mux_2level_size12 mux_right_ipin_14 ( - .in ( { chany_top_out[0] , chany_bottom_out[0] , chany_top_out[3] , - chany_bottom_out[3] , chany_top_out[9] , chany_bottom_out[9] , - chany_top_out[15] , chany_bottom_out[15] , chany_top_out[21] , - chany_bottom_out[21] , chany_top_out[27] , chany_bottom_out[27] } ) , - .sram ( mux_2level_size12_8_sram ) , - .sram_inv ( { SYNOPSYS_UNCONNECTED_33 , SYNOPSYS_UNCONNECTED_34 , - SYNOPSYS_UNCONNECTED_35 , SYNOPSYS_UNCONNECTED_36 } ) , - .out ( left_grid_pin_30_ ) , .p0 ( optlc_net_99 ) ) ; + .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[3] , + ZINV_195_0 , chany_bottom_in[9] , chany_top_in[9] , ZINV_69_13 , + chany_top_in[15] , chany_bottom_in[21] , chany_bottom_out[21] , + chany_bottom_in[27] , chany_top_in[27] } ) , + .sram ( mux_2level_size12_8_sram ) , + .sram_inv ( mux_right_ipin_14_undriven_sram_inv ) , + .out ( { ZBUF_7_f_17 } ) ) ; cby_2__1__mux_2level_size12_mem_0 mem_left_ipin_0 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( mux_2level_size12_mem_0_ccff_tail ) , @@ -3307,77 +3699,63 @@ cby_2__1__mux_2level_size12_mem mem_right_ipin_14 ( .pReset ( pReset ) , .ccff_tail ( mux_2level_size12_mem_8_ccff_tail ) , .mem_out ( mux_2level_size12_8_sram ) ) ; cby_2__1__mux_2level_size10_0 mux_right_ipin_1 ( - .in ( { chany_top_out[2] , chany_bottom_out[2] , chany_top_out[5] , - chany_bottom_out[5] , chany_top_out[8] , chany_bottom_out[8] , - chany_top_out[17] , chany_bottom_out[17] , chany_top_out[26] , - chany_bottom_out[26] } ) , - .sram ( mux_2level_size10_0_sram ) , - .sram_inv ( { SYNOPSYS_UNCONNECTED_37 , SYNOPSYS_UNCONNECTED_38 , - SYNOPSYS_UNCONNECTED_39 , SYNOPSYS_UNCONNECTED_40 } ) , - .out ( left_grid_pin_17_ ) , .p0 ( optlc_net_100 ) ) ; + .in ( { chany_bottom_in[2] , chany_top_in[2] , ZINV_157_1 , + chany_top_in[5] , ZINV_62_15 , chany_top_in[8] , ZINV_19_4 , + chany_top_in[17] , ZINV_62_14 , ZINV_892_f_17 } ) , + .sram ( mux_2level_size10_0_sram ) , + .sram_inv ( mux_right_ipin_1_undriven_sram_inv ) , + .out ( left_grid_pin_17_ ) ) ; cby_2__1__mux_2level_size10_1 mux_right_ipin_3 ( - .in ( { chany_top_out[1] , chany_bottom_out[1] , chany_top_out[4] , - chany_bottom_out[4] , chany_top_out[10] , chany_bottom_out[10] , - chany_top_out[19] , chany_bottom_out[19] , chany_top_out[28] , - chany_bottom_out[28] } ) , - .sram ( mux_2level_size10_1_sram ) , - .sram_inv ( { SYNOPSYS_UNCONNECTED_41 , SYNOPSYS_UNCONNECTED_42 , - SYNOPSYS_UNCONNECTED_43 , SYNOPSYS_UNCONNECTED_44 } ) , - .out ( left_grid_pin_19_ ) , .p0 ( optlc_net_100 ) ) ; + .in ( { ZINV_62_0 , chany_top_in[1] , ZINV_72_0 , chany_top_in[4] , + chany_bottom_in[10] , chany_top_in[10] , chany_bottom_in[19] , + chany_top_in[19] , chany_top_out[28] , chany_top_in[28] } ) , + .sram ( mux_2level_size10_1_sram ) , + .sram_inv ( mux_right_ipin_3_undriven_sram_inv ) , + .out ( { ropt_net_2 } ) ) ; cby_2__1__mux_2level_size10_2 mux_right_ipin_5 ( - .in ( { chany_top_out[0] , chany_bottom_out[0] , chany_top_out[3] , - chany_bottom_out[3] , chany_top_out[6] , chany_bottom_out[6] , - chany_top_out[12] , chany_bottom_out[12] , chany_top_out[21] , - chany_bottom_out[21] } ) , - .sram ( mux_2level_size10_2_sram ) , - .sram_inv ( { SYNOPSYS_UNCONNECTED_45 , SYNOPSYS_UNCONNECTED_46 , - SYNOPSYS_UNCONNECTED_47 , SYNOPSYS_UNCONNECTED_48 } ) , - .out ( left_grid_pin_21_ ) , .p0 ( optlc_net_99 ) ) ; + .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[3] , + ZINV_195_0 , chany_bottom_in[6] , chany_top_in[6] , ZINV_241_17 , + ZINV_62_10 , chany_bottom_in[21] , ZINV_423_3 } ) , + .sram ( mux_2level_size10_2_sram ) , + .sram_inv ( mux_right_ipin_5_undriven_sram_inv ) , + .out ( left_grid_pin_21_ ) ) ; cby_2__1__mux_2level_size10_3 mux_right_ipin_7 ( - .in ( { chany_top_out[2] , chany_bottom_out[2] , chany_top_out[5] , - chany_bottom_out[5] , chany_top_out[8] , chany_bottom_out[8] , - chany_top_out[14] , chany_bottom_out[14] , chany_top_out[23] , - chany_bottom_out[23] } ) , - .sram ( mux_2level_size10_3_sram ) , - .sram_inv ( { SYNOPSYS_UNCONNECTED_49 , SYNOPSYS_UNCONNECTED_50 , - SYNOPSYS_UNCONNECTED_51 , SYNOPSYS_UNCONNECTED_52 } ) , - .out ( left_grid_pin_23_ ) , .p0 ( optlc_net_98 ) ) ; + .in ( { chany_bottom_in[2] , ZINV_68_2 , ZINV_157_1 , chany_top_in[5] , + chany_bottom_in[8] , chany_top_in[8] , chany_bottom_in[14] , + ZINV_62_9 , chany_bottom_in[23] , ZINV_65_5 } ) , + .sram ( mux_2level_size10_3_sram ) , + .sram_inv ( mux_right_ipin_7_undriven_sram_inv ) , + .out ( left_grid_pin_23_ ) ) ; cby_2__1__mux_2level_size10_4 mux_right_ipin_9 ( - .in ( { chany_top_out[1] , chany_bottom_out[1] , chany_top_out[4] , - chany_bottom_out[4] , chany_top_out[10] , chany_bottom_out[10] , - chany_top_out[16] , chany_bottom_out[16] , chany_top_out[25] , - chany_bottom_out[25] } ) , - .sram ( mux_2level_size10_4_sram ) , - .sram_inv ( { SYNOPSYS_UNCONNECTED_53 , SYNOPSYS_UNCONNECTED_54 , - SYNOPSYS_UNCONNECTED_55 , SYNOPSYS_UNCONNECTED_56 } ) , - .out ( left_grid_pin_25_ ) , .p0 ( optlc_net_98 ) ) ; + .in ( { chany_bottom_in[1] , ZINV_68_0 , chany_bottom_in[4] , ZINV_68_1 , + chany_bottom_in[10] , chany_bottom_out[10] , chany_bottom_in[16] , + chany_top_in[16] , chany_bottom_in[25] , chany_bottom_out[25] } ) , + .sram ( mux_2level_size10_4_sram ) , + .sram_inv ( mux_right_ipin_9_undriven_sram_inv ) , + .out ( { ZBUF_275_f_17 } ) ) ; cby_2__1__mux_2level_size10_5 mux_right_ipin_11 ( - .in ( { chany_top_out[0] , chany_bottom_out[0] , chany_top_out[3] , - chany_bottom_out[3] , chany_top_out[12] , chany_bottom_out[12] , - chany_top_out[18] , chany_bottom_out[18] , chany_top_out[27] , - chany_bottom_out[27] } ) , - .sram ( mux_2level_size10_5_sram ) , - .sram_inv ( { SYNOPSYS_UNCONNECTED_57 , SYNOPSYS_UNCONNECTED_58 , - SYNOPSYS_UNCONNECTED_59 , SYNOPSYS_UNCONNECTED_60 } ) , - .out ( left_grid_pin_27_ ) , .p0 ( optlc_net_103 ) ) ; + .in ( { ZINV_75_3 , chany_top_in[0] , chany_bottom_in[3] , ZINV_195_0 , + chany_top_out[12] , chany_top_in[12] , ZINV_69_12 , chany_top_in[18] , + chany_bottom_in[27] , chany_top_in[27] } ) , + .sram ( mux_2level_size10_5_sram ) , + .sram_inv ( mux_right_ipin_11_undriven_sram_inv ) , + .out ( { ZBUF_275_f_16 } ) ) ; cby_2__1__mux_2level_size10_6 mux_right_ipin_13 ( - .in ( { chany_top_out[2] , chany_bottom_out[2] , chany_top_out[5] , - chany_bottom_out[5] , chany_top_out[14] , chany_bottom_out[14] , - chany_top_out[20] , chany_bottom_out[20] , chany_top_out[29] , - chany_bottom_out[29] } ) , - .sram ( mux_2level_size10_6_sram ) , - .sram_inv ( { SYNOPSYS_UNCONNECTED_61 , SYNOPSYS_UNCONNECTED_62 , - SYNOPSYS_UNCONNECTED_63 , SYNOPSYS_UNCONNECTED_64 } ) , - .out ( left_grid_pin_29_ ) , .p0 ( optlc_net_100 ) ) ; + .in ( { chany_bottom_in[2] , chany_top_in[2] , ZINV_157_1 , + chany_top_in[5] , chany_bottom_in[14] , chany_top_in[14] , + chany_bottom_in[20] , ZINV_62_16 , chany_bottom_in[29] , + chany_top_in[29] } ) , + .sram ( mux_2level_size10_6_sram ) , + .sram_inv ( mux_right_ipin_13_undriven_sram_inv ) , + .out ( left_grid_pin_29_ ) ) ; cby_2__1__mux_2level_size10 mux_right_ipin_15 ( - .in ( { chany_top_out[1] , chany_bottom_out[1] , chany_top_out[4] , - chany_bottom_out[4] , chany_top_out[7] , chany_bottom_out[7] , - chany_top_out[16] , chany_bottom_out[16] , chany_top_out[22] , - chany_bottom_out[22] } ) , - .sram ( mux_2level_size10_7_sram ) , - .sram_inv ( { SYNOPSYS_UNCONNECTED_65 , SYNOPSYS_UNCONNECTED_66 , - SYNOPSYS_UNCONNECTED_67 , SYNOPSYS_UNCONNECTED_68 } ) , - .out ( left_grid_pin_31_ ) , .p0 ( optlc_net_100 ) ) ; + .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[4] , + chany_top_in[4] , chany_bottom_in[7] , chany_top_in[7] , + ZINV_1458_f_17 , chany_top_in[16] , chany_top_out[22] , + chany_top_in[22] } ) , + .sram ( mux_2level_size10_7_sram ) , + .sram_inv ( mux_right_ipin_15_undriven_sram_inv ) , + .out ( left_grid_pin_31_ ) ) ; cby_2__1__mux_2level_size10_mem_0 mem_right_ipin_1 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( mux_2level_size12_mem_1_ccff_tail ) , @@ -3425,154 +3803,229 @@ cby_2__1__logical_tile_io_mode_io_ logical_tile_io_mode_io__0 ( .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ) , .io_outpad ( left_width_0_height_0__pin_0_ ) , .ccff_head ( { ccff_tail_mid } ) , - .io_inpad ( left_width_0_height_0__pin_1_lower ) , + .io_inpad ( left_width_0_height_0__pin_1_upper ) , .ccff_tail ( ccff_tail ) ) ; sky130_fd_sc_hd__buf_8 pReset_FTB00 ( .A ( pReset_S_in ) , .X ( pReset[0] ) ) ; -sky130_fd_sc_hd__buf_1 prog_clk_0_FTB00 ( .A ( prog_clk_0_W_in ) , +sky130_fd_sc_hd__buf_16 prog_clk_0_FTB00 ( .A ( prog_clk_0_W_in ) , .X ( prog_clk[0] ) ) ; sky130_fd_sc_hd__clkbuf_1 prog_clk_0_S_FTB01 ( .A ( prog_clk_0_W_in ) , - .X ( ctsbuf_net_1104 ) ) ; + .X ( ctsbuf_net_10 ) ) ; sky130_fd_sc_hd__clkbuf_1 prog_clk_0_N_FTB01 ( .A ( prog_clk_0_W_in ) , - .X ( ctsbuf_net_2105 ) ) ; -sky130_fd_sc_hd__buf_8 FTB_19__18 ( .A ( chany_bottom_in[0] ) , - .X ( chany_top_out[0] ) ) ; -sky130_fd_sc_hd__buf_8 FTB_20__19 ( .A ( chany_bottom_in[1] ) , - .X ( chany_top_out[1] ) ) ; -sky130_fd_sc_hd__buf_8 FTB_21__20 ( .A ( chany_bottom_in[2] ) , - .X ( chany_top_out[2] ) ) ; -sky130_fd_sc_hd__buf_8 FTB_22__21 ( .A ( chany_bottom_in[3] ) , - .X ( chany_top_out[3] ) ) ; -sky130_fd_sc_hd__buf_8 FTB_23__22 ( .A ( chany_bottom_in[4] ) , - .X ( chany_top_out[4] ) ) ; -sky130_fd_sc_hd__buf_8 FTB_24__23 ( .A ( chany_bottom_in[5] ) , - .X ( chany_top_out[5] ) ) ; -sky130_fd_sc_hd__buf_8 FTB_25__24 ( .A ( chany_bottom_in[6] ) , - .X ( chany_top_out[6] ) ) ; -sky130_fd_sc_hd__buf_8 FTB_26__25 ( .A ( chany_bottom_in[7] ) , - .X ( chany_top_out[7] ) ) ; -sky130_fd_sc_hd__buf_8 FTB_27__26 ( .A ( chany_bottom_in[8] ) , - .X ( chany_top_out[8] ) ) ; -sky130_fd_sc_hd__buf_8 FTB_28__27 ( .A ( chany_bottom_in[9] ) , - .X ( chany_top_out[9] ) ) ; -sky130_fd_sc_hd__buf_8 FTB_29__28 ( .A ( chany_bottom_in[10] ) , - .X ( chany_top_out[10] ) ) ; -sky130_fd_sc_hd__buf_8 FTB_30__29 ( .A ( chany_bottom_in[11] ) , - .X ( chany_top_out[11] ) ) ; -sky130_fd_sc_hd__buf_8 FTB_31__30 ( .A ( chany_bottom_in[12] ) , - .X ( chany_top_out[12] ) ) ; -sky130_fd_sc_hd__buf_8 FTB_32__31 ( .A ( chany_bottom_in[13] ) , - .X ( chany_top_out[13] ) ) ; -sky130_fd_sc_hd__buf_8 FTB_33__32 ( .A ( chany_bottom_in[14] ) , - .X ( chany_top_out[14] ) ) ; -sky130_fd_sc_hd__buf_8 FTB_34__33 ( .A ( chany_bottom_in[15] ) , - .X ( chany_top_out[15] ) ) ; -sky130_fd_sc_hd__buf_8 FTB_35__34 ( .A ( chany_bottom_in[16] ) , - .X ( chany_top_out[16] ) ) ; -sky130_fd_sc_hd__buf_8 FTB_36__35 ( .A ( chany_bottom_in[17] ) , - .X ( chany_top_out[17] ) ) ; -sky130_fd_sc_hd__buf_8 FTB_37__36 ( .A ( chany_bottom_in[18] ) , - .X ( chany_top_out[18] ) ) ; -sky130_fd_sc_hd__buf_8 FTB_38__37 ( .A ( chany_bottom_in[19] ) , - .X ( chany_top_out[19] ) ) ; -sky130_fd_sc_hd__buf_8 FTB_39__38 ( .A ( chany_bottom_in[20] ) , - .X ( chany_top_out[20] ) ) ; -sky130_fd_sc_hd__buf_8 FTB_40__39 ( .A ( chany_bottom_in[21] ) , - .X ( chany_top_out[21] ) ) ; -sky130_fd_sc_hd__buf_8 FTB_41__40 ( .A ( chany_bottom_in[22] ) , - .X ( chany_top_out[22] ) ) ; -sky130_fd_sc_hd__buf_8 FTB_42__41 ( .A ( chany_bottom_in[23] ) , - .X ( chany_top_out[23] ) ) ; -sky130_fd_sc_hd__buf_8 FTB_43__42 ( .A ( chany_bottom_in[24] ) , - .X ( chany_top_out[24] ) ) ; -sky130_fd_sc_hd__buf_8 FTB_44__43 ( .A ( chany_bottom_in[25] ) , - .X ( chany_top_out[25] ) ) ; -sky130_fd_sc_hd__buf_8 FTB_45__44 ( .A ( chany_bottom_in[26] ) , - .X ( chany_top_out[26] ) ) ; -sky130_fd_sc_hd__buf_8 FTB_46__45 ( .A ( chany_bottom_in[27] ) , - .X ( chany_top_out[27] ) ) ; -sky130_fd_sc_hd__buf_8 FTB_47__46 ( .A ( chany_bottom_in[28] ) , - .X ( chany_top_out[28] ) ) ; -sky130_fd_sc_hd__buf_8 FTB_48__47 ( .A ( chany_bottom_in[29] ) , - .X ( chany_top_out[29] ) ) ; -sky130_fd_sc_hd__buf_8 FTB_49__48 ( .A ( chany_top_in[0] ) , - .X ( chany_bottom_out[0] ) ) ; -sky130_fd_sc_hd__buf_8 FTB_50__49 ( .A ( chany_top_in[1] ) , - .X ( chany_bottom_out[1] ) ) ; -sky130_fd_sc_hd__buf_8 FTB_51__50 ( .A ( chany_top_in[2] ) , - .X ( chany_bottom_out[2] ) ) ; -sky130_fd_sc_hd__buf_8 FTB_52__51 ( .A ( chany_top_in[3] ) , - .X ( chany_bottom_out[3] ) ) ; -sky130_fd_sc_hd__buf_8 FTB_53__52 ( .A ( chany_top_in[4] ) , - .X ( chany_bottom_out[4] ) ) ; -sky130_fd_sc_hd__buf_8 FTB_54__53 ( .A ( chany_top_in[5] ) , - .X ( chany_bottom_out[5] ) ) ; -sky130_fd_sc_hd__buf_8 FTB_55__54 ( .A ( chany_top_in[6] ) , - .X ( chany_bottom_out[6] ) ) ; -sky130_fd_sc_hd__buf_8 FTB_56__55 ( .A ( chany_top_in[7] ) , - .X ( chany_bottom_out[7] ) ) ; -sky130_fd_sc_hd__buf_8 FTB_57__56 ( .A ( chany_top_in[8] ) , - .X ( chany_bottom_out[8] ) ) ; -sky130_fd_sc_hd__buf_8 FTB_58__57 ( .A ( chany_top_in[9] ) , - .X ( chany_bottom_out[9] ) ) ; -sky130_fd_sc_hd__buf_8 FTB_59__58 ( .A ( chany_top_in[10] ) , - .X ( chany_bottom_out[10] ) ) ; -sky130_fd_sc_hd__buf_8 FTB_60__59 ( .A ( chany_top_in[11] ) , - .X ( chany_bottom_out[11] ) ) ; -sky130_fd_sc_hd__buf_8 FTB_61__60 ( .A ( chany_top_in[12] ) , - .X ( chany_bottom_out[12] ) ) ; -sky130_fd_sc_hd__buf_8 FTB_62__61 ( .A ( chany_top_in[13] ) , - .X ( chany_bottom_out[13] ) ) ; -sky130_fd_sc_hd__buf_8 FTB_63__62 ( .A ( chany_top_in[14] ) , - .X ( chany_bottom_out[14] ) ) ; -sky130_fd_sc_hd__buf_8 FTB_64__63 ( .A ( chany_top_in[15] ) , - .X ( chany_bottom_out[15] ) ) ; -sky130_fd_sc_hd__buf_8 FTB_65__64 ( .A ( chany_top_in[16] ) , - .X ( chany_bottom_out[16] ) ) ; -sky130_fd_sc_hd__buf_8 FTB_66__65 ( .A ( chany_top_in[17] ) , - .X ( chany_bottom_out[17] ) ) ; -sky130_fd_sc_hd__buf_8 FTB_67__66 ( .A ( chany_top_in[18] ) , - .X ( chany_bottom_out[18] ) ) ; -sky130_fd_sc_hd__buf_8 FTB_68__67 ( .A ( chany_top_in[19] ) , - .X ( chany_bottom_out[19] ) ) ; -sky130_fd_sc_hd__buf_8 FTB_69__68 ( .A ( chany_top_in[20] ) , - .X ( chany_bottom_out[20] ) ) ; -sky130_fd_sc_hd__buf_8 FTB_70__69 ( .A ( chany_top_in[21] ) , - .X ( chany_bottom_out[21] ) ) ; -sky130_fd_sc_hd__buf_8 FTB_71__70 ( .A ( chany_top_in[22] ) , - .X ( chany_bottom_out[22] ) ) ; -sky130_fd_sc_hd__buf_8 FTB_72__71 ( .A ( chany_top_in[23] ) , - .X ( chany_bottom_out[23] ) ) ; -sky130_fd_sc_hd__buf_8 FTB_73__72 ( .A ( chany_top_in[24] ) , - .X ( chany_bottom_out[24] ) ) ; -sky130_fd_sc_hd__buf_8 FTB_74__73 ( .A ( chany_top_in[25] ) , - .X ( chany_bottom_out[25] ) ) ; -sky130_fd_sc_hd__buf_8 FTB_75__74 ( .A ( chany_top_in[26] ) , - .X ( chany_bottom_out[26] ) ) ; -sky130_fd_sc_hd__buf_8 FTB_76__75 ( .A ( chany_top_in[27] ) , - .X ( chany_bottom_out[27] ) ) ; -sky130_fd_sc_hd__buf_8 FTB_77__76 ( .A ( chany_top_in[28] ) , - .X ( chany_bottom_out[28] ) ) ; -sky130_fd_sc_hd__buf_8 FTB_78__77 ( .A ( chany_top_in[29] ) , - .X ( chany_bottom_out[29] ) ) ; -sky130_fd_sc_hd__buf_6 FTB_79__78 ( - .A ( left_width_0_height_0__pin_1_lower[0] ) , - .X ( left_width_0_height_0__pin_1_upper[0] ) ) ; -sky130_fd_sc_hd__conb_1 optlc_99 ( .LO ( SYNOPSYS_UNCONNECTED_69 ) , - .HI ( optlc_net_98 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_102 ( .LO ( SYNOPSYS_UNCONNECTED_70 ) , - .HI ( optlc_net_99 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_104 ( .LO ( SYNOPSYS_UNCONNECTED_71 ) , - .HI ( optlc_net_100 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_105 ( .LO ( SYNOPSYS_UNCONNECTED_72 ) , - .HI ( optlc_net_101 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_107 ( .LO ( SYNOPSYS_UNCONNECTED_73 ) , - .HI ( optlc_net_102 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_108 ( .LO ( SYNOPSYS_UNCONNECTED_74 ) , - .HI ( optlc_net_103 ) ) ; -sky130_fd_sc_hd__buf_6 cts_buf_3651248 ( .A ( ctsbuf_net_1104 ) , + .X ( ctsbuf_net_21 ) ) ; +sky130_fd_sc_hd__clkinv_4 ZINV_10_inst_877 ( .A ( ZINV_62_0 ) , + .Y ( chany_top_out[1] ) ) ; +sky130_fd_sc_hd__buf_6 cts_buf_429755 ( .A ( ctsbuf_net_10 ) , .X ( prog_clk_0_S_out ) ) ; -sky130_fd_sc_hd__buf_6 cts_buf_3701253 ( .A ( ctsbuf_net_2105 ) , +sky130_fd_sc_hd__clkbuf_8 cts_buf_434760 ( .A ( ctsbuf_net_21 ) , .X ( prog_clk_0_N_out ) ) ; +sky130_fd_sc_hd__clkinv_1 ZINV_62_inst_879 ( .A ( chany_bottom_in[1] ) , + .Y ( ZINV_62_0 ) ) ; +sky130_fd_sc_hd__buf_6 ZBUF_18_f_inst_881 ( .A ( chany_bottom_in[3] ) , + .X ( chany_top_out[3] ) ) ; +sky130_fd_sc_hd__clkinv_4 ZINV_16_inst_882 ( .A ( ZINV_68_0 ) , + .Y ( chany_bottom_out[1] ) ) ; +sky130_fd_sc_hd__clkinv_1 ZINV_68_inst_884 ( .A ( chany_top_in[1] ) , + .Y ( ZINV_68_0 ) ) ; +sky130_fd_sc_hd__clkinv_4 ZINV_20_inst_885 ( .A ( ZINV_72_0 ) , + .Y ( chany_top_out[4] ) ) ; +sky130_fd_sc_hd__clkinv_1 ZINV_72_inst_887 ( .A ( chany_bottom_in[4] ) , + .Y ( ZINV_72_0 ) ) ; +sky130_fd_sc_hd__clkinv_4 ZINV_19_inst_888 ( .A ( ZINV_71_0 ) , + .Y ( chany_bottom_out[0] ) ) ; +sky130_fd_sc_hd__clkinv_1 ZINV_71_inst_890 ( .A ( chany_top_in[0] ) , + .Y ( ZINV_71_0 ) ) ; +sky130_fd_sc_hd__inv_1 ZINV_205_inst_891 ( .A ( ZINV_267_0 ) , + .Y ( ropt_net_4 ) ) ; +sky130_fd_sc_hd__inv_1 ZINV_195_inst_892 ( .A ( ZINV_267_0 ) , + .Y ( ZINV_195_0 ) ) ; +sky130_fd_sc_hd__clkinv_1 ZINV_267_inst_893 ( .A ( chany_top_in[3] ) , + .Y ( ZINV_267_0 ) ) ; +sky130_fd_sc_hd__clkinv_4 ZINV_16_inst_894 ( .A ( ZINV_68_1 ) , + .Y ( chany_bottom_out[4] ) ) ; +sky130_fd_sc_hd__clkinv_1 ZINV_68_inst_896 ( .A ( chany_top_in[4] ) , + .Y ( ZINV_68_1 ) ) ; +sky130_fd_sc_hd__clkinv_4 ZINV_215_inst_897 ( .A ( ZINV_267_1 ) , + .Y ( chany_bottom_out[25] ) ) ; +sky130_fd_sc_hd__clkinv_1 ZINV_267_inst_899 ( .A ( chany_top_in[25] ) , + .Y ( ZINV_267_1 ) ) ; +sky130_fd_sc_hd__clkinv_4 ZINV_166_inst_900 ( .A ( ZINV_252_1 ) , + .Y ( chany_top_out[5] ) ) ; +sky130_fd_sc_hd__inv_1 ZINV_157_inst_901 ( .A ( ZINV_252_1 ) , + .Y ( ZINV_157_1 ) ) ; +sky130_fd_sc_hd__clkinv_1 ZINV_252_inst_902 ( .A ( chany_bottom_in[5] ) , + .Y ( ZINV_252_1 ) ) ; +sky130_fd_sc_hd__clkinv_4 ZINV_16_inst_903 ( .A ( ZINV_68_2 ) , + .Y ( chany_bottom_out[2] ) ) ; +sky130_fd_sc_hd__clkinv_1 ZINV_68_inst_905 ( .A ( chany_top_in[2] ) , + .Y ( ZINV_68_2 ) ) ; +sky130_fd_sc_hd__clkinv_4 ZINV_16_inst_906 ( .A ( ZINV_68_3 ) , + .Y ( chany_top_out[2] ) ) ; +sky130_fd_sc_hd__clkinv_1 ZINV_68_inst_908 ( .A ( chany_bottom_in[2] ) , + .Y ( ZINV_68_3 ) ) ; +sky130_fd_sc_hd__clkinv_4 ZINV_23_inst_909 ( .A ( ZINV_75_3 ) , + .Y ( chany_top_out[0] ) ) ; +sky130_fd_sc_hd__clkinv_1 ZINV_75_inst_911 ( .A ( chany_bottom_in[0] ) , + .Y ( ZINV_75_3 ) ) ; +sky130_fd_sc_hd__inv_8 ZINV_346_inst_913 ( .A ( ZINV_423_3 ) , + .Y ( chany_bottom_out[21] ) ) ; +sky130_fd_sc_hd__clkinv_1 ZINV_423_inst_914 ( .A ( chany_top_in[21] ) , + .Y ( ZINV_423_3 ) ) ; +sky130_fd_sc_hd__clkinv_4 ZINV_10_inst_915 ( .A ( ZINV_62_3 ) , + .Y ( chany_top_out[11] ) ) ; +sky130_fd_sc_hd__clkinv_1 ZINV_62_inst_917 ( .A ( chany_bottom_in[11] ) , + .Y ( ZINV_62_3 ) ) ; +sky130_fd_sc_hd__clkinv_4 ZINV_13_inst_918 ( .A ( ZINV_65_3 ) , + .Y ( chany_top_out[23] ) ) ; +sky130_fd_sc_hd__clkinv_1 ZINV_65_inst_920 ( .A ( chany_bottom_in[23] ) , + .Y ( ZINV_65_3 ) ) ; +sky130_fd_sc_hd__clkinv_4 ZINV_13_inst_921 ( .A ( ZINV_65_4 ) , + .Y ( chany_top_out[7] ) ) ; +sky130_fd_sc_hd__clkinv_1 ZINV_65_inst_923 ( .A ( chany_bottom_in[7] ) , + .Y ( ZINV_65_4 ) ) ; +sky130_fd_sc_hd__buf_6 ZBUF_11_f_inst_924 ( .A ( chany_bottom_in[27] ) , + .X ( chany_top_out[27] ) ) ; +sky130_fd_sc_hd__inv_8 ZINV_25_inst_925 ( .A ( ZINV_77_4 ) , + .Y ( chany_top_out[17] ) ) ; +sky130_fd_sc_hd__clkinv_1 ZINV_19_inst_926 ( .A ( ZINV_77_4 ) , + .Y ( ZINV_19_4 ) ) ; +sky130_fd_sc_hd__clkinv_1 ZINV_77_inst_927 ( .A ( chany_bottom_in[17] ) , + .Y ( ZINV_77_4 ) ) ; +sky130_fd_sc_hd__buf_6 ZBUF_14_f_inst_928 ( .A ( chany_top_in[5] ) , + .X ( chany_bottom_out[5] ) ) ; +sky130_fd_sc_hd__buf_6 ZBUF_18_f_inst_929 ( .A ( chany_top_in[27] ) , + .X ( chany_bottom_out[27] ) ) ; +sky130_fd_sc_hd__buf_6 ZBUF_11_f_inst_930 ( .A ( chany_bottom_in[19] ) , + .X ( chany_top_out[19] ) ) ; +sky130_fd_sc_hd__clkinv_4 ZINV_13_inst_931 ( .A ( ZINV_65_5 ) , + .Y ( chany_bottom_out[23] ) ) ; +sky130_fd_sc_hd__clkinv_1 ZINV_65_inst_933 ( .A ( chany_top_in[23] ) , + .Y ( ZINV_65_5 ) ) ; +sky130_fd_sc_hd__clkinv_4 ZINV_13_inst_934 ( .A ( ZINV_65_6 ) , + .Y ( chany_top_out[13] ) ) ; +sky130_fd_sc_hd__clkinv_1 ZINV_65_inst_936 ( .A ( chany_bottom_in[13] ) , + .Y ( ZINV_65_6 ) ) ; +sky130_fd_sc_hd__buf_6 ZBUF_15_f_inst_937 ( .A ( chany_bottom_in[25] ) , + .X ( chany_top_out[25] ) ) ; +sky130_fd_sc_hd__clkinv_4 ZINV_13_inst_938 ( .A ( ZINV_65_7 ) , + .Y ( chany_bottom_out[9] ) ) ; +sky130_fd_sc_hd__clkinv_1 ZINV_65_inst_940 ( .A ( chany_top_in[9] ) , + .Y ( ZINV_65_7 ) ) ; +sky130_fd_sc_hd__buf_6 ZBUF_11_f_inst_941 ( .A ( chany_bottom_in[6] ) , + .X ( chany_top_out[6] ) ) ; +sky130_fd_sc_hd__buf_6 ZBUF_15_f_inst_942 ( .A ( chany_top_in[11] ) , + .X ( chany_bottom_out[11] ) ) ; +sky130_fd_sc_hd__clkbuf_8 ZBUF_14_f_inst_943 ( .A ( chany_bottom_in[14] ) , + .X ( chany_top_out[14] ) ) ; +sky130_fd_sc_hd__buf_6 ZBUF_14_f_inst_944 ( .A ( chany_bottom_in[21] ) , + .X ( chany_top_out[21] ) ) ; +sky130_fd_sc_hd__buf_6 ZBUF_8_f_inst_945 ( .A ( chany_bottom_in[29] ) , + .X ( chany_top_out[29] ) ) ; +sky130_fd_sc_hd__buf_6 ZBUF_11_f_inst_946 ( .A ( chany_bottom_in[10] ) , + .X ( chany_top_out[10] ) ) ; +sky130_fd_sc_hd__buf_6 ZBUF_8_f_inst_947 ( .A ( chany_top_in[8] ) , + .X ( chany_bottom_out[8] ) ) ; +sky130_fd_sc_hd__clkinv_4 ZINV_10_inst_948 ( .A ( ZINV_62_9 ) , + .Y ( chany_bottom_out[14] ) ) ; +sky130_fd_sc_hd__clkinv_1 ZINV_62_inst_950 ( .A ( chany_top_in[14] ) , + .Y ( ZINV_62_9 ) ) ; +sky130_fd_sc_hd__clkinv_4 ZINV_10_inst_951 ( .A ( ZINV_62_10 ) , + .Y ( chany_bottom_out[12] ) ) ; +sky130_fd_sc_hd__clkinv_1 ZINV_62_inst_953 ( .A ( chany_top_in[12] ) , + .Y ( ZINV_62_10 ) ) ; +sky130_fd_sc_hd__buf_6 ZBUF_8_f_inst_955 ( .A ( chany_top_in[29] ) , + .X ( chany_bottom_out[29] ) ) ; +sky130_fd_sc_hd__clkinv_4 ZINV_10_inst_956 ( .A ( ZINV_62_11 ) , + .Y ( chany_bottom_out[13] ) ) ; +sky130_fd_sc_hd__clkinv_1 ZINV_62_inst_958 ( .A ( chany_top_in[13] ) , + .Y ( ZINV_62_11 ) ) ; +sky130_fd_sc_hd__buf_6 ZBUF_15_f_inst_959 ( .A ( chany_top_in[16] ) , + .X ( chany_bottom_out[16] ) ) ; +sky130_fd_sc_hd__clkinv_4 ZINV_10_inst_962 ( .A ( ZINV_69_12 ) , + .Y ( chany_top_out[18] ) ) ; +sky130_fd_sc_hd__clkinv_1 ZINV_69_inst_963 ( .A ( chany_bottom_in[18] ) , + .Y ( ZINV_69_12 ) ) ; +sky130_fd_sc_hd__clkinv_4 ZINV_17_inst_967 ( .A ( ZINV_69_13 ) , + .Y ( chany_top_out[15] ) ) ; +sky130_fd_sc_hd__clkinv_1 ZINV_69_inst_969 ( .A ( chany_bottom_in[15] ) , + .Y ( ZINV_69_13 ) ) ; +sky130_fd_sc_hd__clkinv_4 ZINV_17_inst_970 ( .A ( ZINV_69_14 ) , + .Y ( chany_bottom_out[15] ) ) ; +sky130_fd_sc_hd__clkinv_1 ZINV_69_inst_972 ( .A ( chany_top_in[15] ) , + .Y ( ZINV_69_14 ) ) ; +sky130_fd_sc_hd__buf_6 ZBUF_9_f_inst_976 ( .A ( chany_top_in[28] ) , + .X ( chany_bottom_out[28] ) ) ; +sky130_fd_sc_hd__inv_8 ZINV_10_inst_977 ( .A ( ZINV_62_14 ) , + .Y ( chany_top_out[26] ) ) ; +sky130_fd_sc_hd__clkinv_1 ZINV_62_inst_979 ( .A ( chany_bottom_in[26] ) , + .Y ( ZINV_62_14 ) ) ; +sky130_fd_sc_hd__clkinv_4 ZINV_824_f_inst_986 ( .A ( ZINV_833_14 ) , + .Y ( chany_bottom_out[22] ) ) ; +sky130_fd_sc_hd__clkinv_1 ZINV_833_inst_987 ( .A ( chany_top_in[22] ) , + .Y ( ZINV_833_14 ) ) ; +sky130_fd_sc_hd__clkinv_4 ZINV_17_inst_989 ( .A ( ZINV_69_15 ) , + .Y ( chany_bottom_out[19] ) ) ; +sky130_fd_sc_hd__clkinv_1 ZINV_69_inst_991 ( .A ( chany_top_in[19] ) , + .Y ( ZINV_69_15 ) ) ; +sky130_fd_sc_hd__clkinv_4 ZINV_10_inst_993 ( .A ( ZINV_62_15 ) , + .Y ( chany_top_out[8] ) ) ; +sky130_fd_sc_hd__clkinv_1 ZINV_62_inst_995 ( .A ( chany_bottom_in[8] ) , + .Y ( ZINV_62_15 ) ) ; +sky130_fd_sc_hd__buf_6 ZBUF_8_f_inst_999 ( .A ( chany_top_in[18] ) , + .X ( chany_bottom_out[18] ) ) ; +sky130_fd_sc_hd__clkinv_4 ZINV_10_inst_1003 ( .A ( ZINV_62_16 ) , + .Y ( chany_bottom_out[20] ) ) ; +sky130_fd_sc_hd__clkinv_1 ZINV_62_inst_1005 ( .A ( chany_top_in[20] ) , + .Y ( ZINV_62_16 ) ) ; +sky130_fd_sc_hd__buf_6 ZBUF_275_f_inst_1009 ( .A ( ZBUF_275_f_16 ) , + .X ( left_grid_pin_27_[0] ) ) ; +sky130_fd_sc_hd__buf_6 ZBUF_274_f_inst_1010 ( .A ( ZBUF_274_f_16 ) , + .X ( left_grid_pin_24_[0] ) ) ; +sky130_fd_sc_hd__buf_6 ZBUF_275_f_inst_1011 ( .A ( ZBUF_275_f_17 ) , + .X ( left_grid_pin_25_[0] ) ) ; +sky130_fd_sc_hd__buf_6 ZBUF_7_f_inst_1013 ( .A ( ZBUF_7_f_17 ) , + .X ( left_grid_pin_30_[0] ) ) ; +sky130_fd_sc_hd__inv_8 ZINV_182_inst_1017 ( .A ( ZINV_241_17 ) , + .Y ( chany_top_out[12] ) ) ; +sky130_fd_sc_hd__clkinv_1 ZINV_241_inst_1018 ( .A ( chany_bottom_in[12] ) , + .Y ( ZINV_241_17 ) ) ; +sky130_fd_sc_hd__buf_6 ZBUF_1030_f_inst_1019 ( .A ( chany_top_in[17] ) , + .X ( chany_bottom_out[17] ) ) ; +sky130_fd_sc_hd__buf_6 ZBUF_815_f_inst_1021 ( .A ( chany_bottom_in[20] ) , + .X ( chany_top_out[20] ) ) ; +sky130_fd_sc_hd__clkinv_4 ZINV_1383_inst_1022 ( .A ( ZINV_1458_f_17 ) , + .Y ( chany_top_out[16] ) ) ; +sky130_fd_sc_hd__clkinv_1 ZINV_1458_f_inst_1024 ( .A ( chany_bottom_in[16] ) , + .Y ( ZINV_1458_f_17 ) ) ; +sky130_fd_sc_hd__buf_6 ZBUF_826_f_inst_1025 ( .A ( chany_top_in[24] ) , + .X ( chany_bottom_out[24] ) ) ; +sky130_fd_sc_hd__buf_6 ZBUF_1105_f_inst_1027 ( .A ( chany_top_in[6] ) , + .X ( chany_bottom_out[6] ) ) ; +sky130_fd_sc_hd__clkinv_4 ZINV_1528_f_inst_1029 ( .A ( ZINV_1537_17 ) , + .Y ( chany_bottom_out[7] ) ) ; +sky130_fd_sc_hd__clkinv_1 ZINV_1537_inst_1030 ( .A ( chany_top_in[7] ) , + .Y ( ZINV_1537_17 ) ) ; +sky130_fd_sc_hd__buf_6 ZBUF_1011_f_inst_1031 ( .A ( chany_bottom_in[9] ) , + .X ( chany_top_out[9] ) ) ; +sky130_fd_sc_hd__buf_6 ZBUF_1267_f_inst_1032 ( .A ( chany_top_in[10] ) , + .X ( chany_bottom_out[10] ) ) ; +sky130_fd_sc_hd__clkinv_4 ZINV_816_inst_1033 ( .A ( ZINV_892_f_17 ) , + .Y ( chany_bottom_out[26] ) ) ; +sky130_fd_sc_hd__clkinv_1 ZINV_892_f_inst_1035 ( .A ( chany_top_in[26] ) , + .Y ( ZINV_892_f_17 ) ) ; +sky130_fd_sc_hd__buf_6 ZBUF_338_f_inst_1036 ( .A ( chany_bottom_in[24] ) , + .X ( chany_top_out[24] ) ) ; +sky130_fd_sc_hd__clkbuf_8 ZBUF_301_f_inst_1037 ( .A ( chany_bottom_in[22] ) , + .X ( chany_top_out[22] ) ) ; +sky130_fd_sc_hd__buf_6 ZBUF_529_f_inst_1038 ( .A ( chany_bottom_in[28] ) , + .X ( chany_top_out[28] ) ) ; +sky130_fd_sc_hd__buf_6 ZBUF_660_f_inst_1039 ( .A ( ZBUF_660_f_17 ) , + .X ( right_grid_pin_0_[0] ) ) ; +sky130_fd_sc_hd__buf_4 ropt_mt_inst_1040 ( .A ( ropt_net_2 ) , + .X ( left_grid_pin_19_[0] ) ) ; +sky130_fd_sc_hd__buf_4 ropt_mt_inst_1041 ( .A ( ropt_net_3 ) , + .X ( left_grid_pin_28_[0] ) ) ; +sky130_fd_sc_hd__buf_6 ropt_mt_inst_1043 ( .A ( ropt_net_4 ) , + .X ( chany_bottom_out[3] ) ) ; endmodule @@ -3584,8 +4037,6 @@ input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -wire copt_net_121 ; - sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , @@ -3593,15 +4044,11 @@ sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( copt_net_121 ) ) ; -sky130_fd_sc_hd__buf_6 FTB_16__15 ( .A ( copt_net_126 ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_6 FTB_16__15 ( .A ( copt_net_105 ) , .X ( ccff_tail[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1371 ( .A ( copt_net_121 ) , - .X ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1372 ( .A ( mem_out[3] ) , - .X ( copt_net_122 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1376 ( .A ( copt_net_122 ) , - .X ( copt_net_126 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1342 ( .A ( mem_out[3] ) , + .X ( copt_net_105 ) ) ; endmodule @@ -3751,9 +4198,13 @@ input [0:1] mem ; input [0:1] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -3765,12 +4216,18 @@ input [0:3] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -3780,12 +4237,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -3795,12 +4258,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -3868,7 +4337,7 @@ wire [0:0] mux_2level_basis_input4_mem4_2_out ; cby_1__1__const1 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_1_0_ ( - .A ( mux_2level_basis_input4_mem4_2_out[0] ) , .X ( aps_rename_512_ ) ) ; + .A ( mux_2level_basis_input4_mem4_2_out[0] ) , .X ( out[0] ) ) ; cby_1__1__local_encoder2to4_30 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , .data ( local_encoder2to4_0_data ) , .data_inv ( local_encoder2to4_0_data_inv ) ) ; @@ -3894,9 +4363,6 @@ cby_1__1__mux_2level_basis_input2_mem2 mux_l1_in_2_ ( .in ( in[8:9] ) , .mem ( local_encoder2to4_0_data[0:1] ) , .mem_inv ( local_encoder2to4_0_data_inv[0:1] ) , .out ( mux_2level_basis_input2_mem2_0_out ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_93 ( .A ( BUF_net_94 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_94 ( .A ( aps_rename_512_ ) , - .Y ( BUF_net_94 ) ) ; endmodule @@ -3906,9 +4372,13 @@ input [0:1] mem ; input [0:1] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -3920,12 +4390,18 @@ input [0:3] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -3935,12 +4411,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -3950,12 +4432,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -4022,7 +4510,7 @@ wire [0:0] mux_2level_basis_input4_mem4_2_out ; cby_1__1__const1_14 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__bufbuf_16 sky130_fd_sc_hd__buf_1_0_ ( +sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_1_0_ ( .A ( mux_2level_basis_input4_mem4_2_out[0] ) , .X ( out[0] ) ) ; cby_1__1__local_encoder2to4_28 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , .data ( local_encoder2to4_0_data ) , @@ -4058,9 +4546,13 @@ input [0:1] mem ; input [0:1] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -4072,12 +4564,18 @@ input [0:3] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -4087,12 +4585,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -4102,12 +4606,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -4175,7 +4685,7 @@ wire [0:0] mux_2level_basis_input4_mem4_2_out ; cby_1__1__const1_13 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_1_0_ ( - .A ( mux_2level_basis_input4_mem4_2_out[0] ) , .X ( out[0] ) ) ; + .A ( mux_2level_basis_input4_mem4_2_out[0] ) , .X ( net_net_88 ) ) ; cby_1__1__local_encoder2to4_26 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , .data ( local_encoder2to4_0_data ) , .data_inv ( local_encoder2to4_0_data_inv ) ) ; @@ -4201,6 +4711,7 @@ cby_1__1__mux_2level_basis_input2_mem2_5 mux_l1_in_2_ ( .in ( in[8:9] ) , .mem ( local_encoder2to4_0_data[0:1] ) , .mem_inv ( local_encoder2to4_0_data_inv[0:1] ) , .out ( mux_2level_basis_input2_mem2_0_out ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_88 ( .A ( net_net_88 ) , .X ( out[0] ) ) ; endmodule @@ -4210,9 +4721,13 @@ input [0:1] mem ; input [0:1] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -4224,12 +4739,18 @@ input [0:3] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -4239,12 +4760,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -4254,12 +4781,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -4327,7 +4860,7 @@ wire [0:0] mux_2level_basis_input4_mem4_2_out ; cby_1__1__const1_12 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_1_0_ ( - .A ( mux_2level_basis_input4_mem4_2_out[0] ) , .X ( aps_rename_511_ ) ) ; + .A ( mux_2level_basis_input4_mem4_2_out[0] ) , .X ( aps_rename_510_ ) ) ; cby_1__1__local_encoder2to4_24 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , .data ( local_encoder2to4_0_data ) , .data_inv ( local_encoder2to4_0_data_inv ) ) ; @@ -4353,9 +4886,9 @@ cby_1__1__mux_2level_basis_input2_mem2_4 mux_l1_in_2_ ( .in ( in[8:9] ) , .mem ( local_encoder2to4_0_data[0:1] ) , .mem_inv ( local_encoder2to4_0_data_inv[0:1] ) , .out ( mux_2level_basis_input2_mem2_0_out ) ) ; -sky130_fd_sc_hd__inv_6 BINV_R_104 ( .A ( BUF_net_105 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_105 ( .A ( aps_rename_511_ ) , - .Y ( BUF_net_105 ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_86 ( .A ( BUF_net_87 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_87 ( .A ( aps_rename_510_ ) , + .Y ( BUF_net_87 ) ) ; endmodule @@ -4365,9 +4898,13 @@ input [0:1] mem ; input [0:1] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -4379,12 +4916,18 @@ input [0:3] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -4394,12 +4937,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -4409,12 +4958,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -4517,9 +5072,13 @@ input [0:1] mem ; input [0:1] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -4531,12 +5090,18 @@ input [0:3] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -4546,12 +5111,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -4561,12 +5132,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -4669,9 +5246,13 @@ input [0:1] mem ; input [0:1] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -4683,12 +5264,18 @@ input [0:3] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -4698,12 +5285,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -4713,12 +5306,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -4786,7 +5385,7 @@ wire [0:0] mux_2level_basis_input4_mem4_2_out ; cby_1__1__const1_9 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_1_0_ ( - .A ( mux_2level_basis_input4_mem4_2_out[0] ) , .X ( aps_rename_510_ ) ) ; + .A ( mux_2level_basis_input4_mem4_2_out[0] ) , .X ( aps_rename_509_ ) ) ; cby_1__1__local_encoder2to4_18 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , .data ( local_encoder2to4_0_data ) , .data_inv ( local_encoder2to4_0_data_inv ) ) ; @@ -4812,9 +5411,9 @@ cby_1__1__mux_2level_basis_input2_mem2_1 mux_l1_in_2_ ( .in ( in[8:9] ) , .mem ( local_encoder2to4_0_data[0:1] ) , .mem_inv ( local_encoder2to4_0_data_inv[0:1] ) , .out ( mux_2level_basis_input2_mem2_0_out ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_89 ( .A ( BUF_net_90 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_90 ( .A ( aps_rename_510_ ) , - .Y ( BUF_net_90 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_84 ( .A ( BUF_net_85 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_85 ( .A ( aps_rename_509_ ) , + .Y ( BUF_net_85 ) ) ; endmodule @@ -4824,9 +5423,13 @@ input [0:1] mem ; input [0:1] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -4838,12 +5441,18 @@ input [0:3] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -4853,12 +5462,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -4868,12 +5483,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -4941,7 +5562,7 @@ wire [0:0] mux_2level_basis_input4_mem4_2_out ; cby_1__1__const1_8 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_1_0_ ( - .A ( mux_2level_basis_input4_mem4_2_out[0] ) , .X ( aps_rename_509_ ) ) ; + .A ( mux_2level_basis_input4_mem4_2_out[0] ) , .X ( aps_rename_508_ ) ) ; cby_1__1__local_encoder2to4_16 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , .data ( local_encoder2to4_0_data ) , .data_inv ( local_encoder2to4_0_data_inv ) ) ; @@ -4967,9 +5588,7 @@ cby_1__1__mux_2level_basis_input2_mem2_0 mux_l1_in_2_ ( .in ( in[8:9] ) , .mem ( local_encoder2to4_0_data[0:1] ) , .mem_inv ( local_encoder2to4_0_data_inv[0:1] ) , .out ( mux_2level_basis_input2_mem2_0_out ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_87 ( .A ( BUF_net_88 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_88 ( .A ( aps_rename_509_ ) , - .Y ( BUF_net_88 ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_94 ( .A ( aps_rename_508_ ) , .X ( out[0] ) ) ; endmodule @@ -5121,7 +5740,7 @@ input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ropt_net_132 ) , +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; @@ -5130,24 +5749,6 @@ sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__buf_1 FTB_1__0 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1364 ( .A ( ropt_net_133 ) , - .X ( copt_net_114 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1365 ( .A ( copt_net_116 ) , - .X ( copt_net_115 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1366 ( .A ( copt_net_114 ) , - .X ( copt_net_116 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1367 ( .A ( ccff_head[0] ) , - .X ( copt_net_117 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1374 ( .A ( copt_net_115 ) , - .X ( copt_net_124 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 copt_h_inst_1375 ( .A ( copt_net_124 ) , - .X ( copt_net_125 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1380 ( .A ( copt_net_125 ) , - .X ( ropt_net_131 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1381 ( .A ( ropt_net_131 ) , - .X ( ropt_net_132 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 ropt_h_inst_1382 ( .A ( copt_net_117 ) , - .X ( ropt_net_133 ) ) ; endmodule @@ -5159,12 +5760,18 @@ input [0:3] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -5174,12 +5781,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -5189,12 +5802,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -5204,12 +5823,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -5276,7 +5901,7 @@ wire [0:0] mux_2level_basis_input4_mem4_3_out ; cby_1__1__const1_7 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__bufbuf_16 sky130_fd_sc_hd__buf_1_0_ ( +sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_1_0_ ( .A ( mux_2level_basis_input4_mem4_3_out[0] ) , .X ( out[0] ) ) ; cby_1__1__local_encoder2to4_14 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , .data ( local_encoder2to4_0_data ) , @@ -5314,12 +5939,18 @@ input [0:3] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -5329,12 +5960,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -5344,12 +5981,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -5359,12 +6002,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -5432,7 +6081,7 @@ wire [0:0] mux_2level_basis_input4_mem4_3_out ; cby_1__1__const1_6 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_1_0_ ( - .A ( mux_2level_basis_input4_mem4_3_out[0] ) , .X ( aps_rename_508_ ) ) ; + .A ( mux_2level_basis_input4_mem4_3_out[0] ) , .X ( out[0] ) ) ; cby_1__1__local_encoder2to4_12 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , .data ( local_encoder2to4_0_data ) , .data_inv ( local_encoder2to4_0_data_inv ) ) ; @@ -5458,9 +6107,6 @@ cby_1__1__mux_2level_basis_input4_mem4_27 mux_l2_in_0_ ( .mem ( local_encoder2to4_1_data ) , .mem_inv ( local_encoder2to4_1_data_inv ) , .out ( mux_2level_basis_input4_mem4_3_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_85 ( .A ( BUF_net_86 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_86 ( .A ( aps_rename_508_ ) , - .Y ( BUF_net_86 ) ) ; endmodule @@ -5472,12 +6118,18 @@ input [0:3] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -5487,12 +6139,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -5502,12 +6160,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -5517,12 +6181,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -5590,7 +6260,7 @@ wire [0:0] mux_2level_basis_input4_mem4_3_out ; cby_1__1__const1_5 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_1_0_ ( - .A ( mux_2level_basis_input4_mem4_3_out[0] ) , .X ( net_net_84 ) ) ; + .A ( mux_2level_basis_input4_mem4_3_out[0] ) , .X ( aps_rename_507_ ) ) ; cby_1__1__local_encoder2to4_10 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , .data ( local_encoder2to4_0_data ) , .data_inv ( local_encoder2to4_0_data_inv ) ) ; @@ -5616,7 +6286,9 @@ cby_1__1__mux_2level_basis_input4_mem4_23 mux_l2_in_0_ ( .mem ( local_encoder2to4_1_data ) , .mem_inv ( local_encoder2to4_1_data_inv ) , .out ( mux_2level_basis_input4_mem4_3_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_84 ( .A ( net_net_84 ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_80 ( .A ( BUF_net_81 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_81 ( .A ( aps_rename_507_ ) , + .Y ( BUF_net_81 ) ) ; endmodule @@ -5628,12 +6300,18 @@ input [0:3] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -5643,12 +6321,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -5658,12 +6342,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -5673,12 +6363,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -5746,7 +6442,7 @@ wire [0:0] mux_2level_basis_input4_mem4_3_out ; cby_1__1__const1_4 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_1_0_ ( - .A ( mux_2level_basis_input4_mem4_3_out[0] ) , .X ( aps_rename_507_ ) ) ; + .A ( mux_2level_basis_input4_mem4_3_out[0] ) , .X ( aps_rename_506_ ) ) ; cby_1__1__local_encoder2to4_8 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , .data ( local_encoder2to4_0_data ) , .data_inv ( local_encoder2to4_0_data_inv ) ) ; @@ -5772,9 +6468,9 @@ cby_1__1__mux_2level_basis_input4_mem4_19 mux_l2_in_0_ ( .mem ( local_encoder2to4_1_data ) , .mem_inv ( local_encoder2to4_1_data_inv ) , .out ( mux_2level_basis_input4_mem4_3_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_82 ( .A ( BUF_net_83 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_83 ( .A ( aps_rename_507_ ) , - .Y ( BUF_net_83 ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_78 ( .A ( BUF_net_79 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_79 ( .A ( aps_rename_506_ ) , + .Y ( BUF_net_79 ) ) ; endmodule @@ -5786,12 +6482,18 @@ input [0:3] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -5801,12 +6503,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -5816,12 +6524,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -5831,12 +6545,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -5903,8 +6623,8 @@ wire [0:0] mux_2level_basis_input4_mem4_3_out ; cby_1__1__const1_3 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_1_0_ ( - .A ( mux_2level_basis_input4_mem4_3_out[0] ) , .X ( net_net_81 ) ) ; +sky130_fd_sc_hd__bufbuf_16 sky130_fd_sc_hd__buf_1_0_ ( + .A ( mux_2level_basis_input4_mem4_3_out[0] ) , .X ( out[0] ) ) ; cby_1__1__local_encoder2to4_6 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , .data ( local_encoder2to4_0_data ) , .data_inv ( local_encoder2to4_0_data_inv ) ) ; @@ -5930,7 +6650,6 @@ cby_1__1__mux_2level_basis_input4_mem4_15 mux_l2_in_0_ ( .mem ( local_encoder2to4_1_data ) , .mem_inv ( local_encoder2to4_1_data_inv ) , .out ( mux_2level_basis_input4_mem4_3_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_81 ( .A ( net_net_81 ) , .X ( out[0] ) ) ; endmodule @@ -5942,12 +6661,18 @@ input [0:3] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -5957,12 +6682,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -5972,12 +6703,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -5987,12 +6724,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -6059,8 +6802,8 @@ wire [0:0] mux_2level_basis_input4_mem4_3_out ; cby_1__1__const1_2 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_1_0_ ( - .A ( mux_2level_basis_input4_mem4_3_out[0] ) , .X ( aps_rename_506_ ) ) ; +sky130_fd_sc_hd__bufbuf_16 sky130_fd_sc_hd__buf_1_0_ ( + .A ( mux_2level_basis_input4_mem4_3_out[0] ) , .X ( out[0] ) ) ; cby_1__1__local_encoder2to4_4 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , .data ( local_encoder2to4_0_data ) , .data_inv ( local_encoder2to4_0_data_inv ) ) ; @@ -6086,9 +6829,6 @@ cby_1__1__mux_2level_basis_input4_mem4_11 mux_l2_in_0_ ( .mem ( local_encoder2to4_1_data ) , .mem_inv ( local_encoder2to4_1_data_inv ) , .out ( mux_2level_basis_input4_mem4_3_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_79 ( .A ( BUF_net_80 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_80 ( .A ( aps_rename_506_ ) , - .Y ( BUF_net_80 ) ) ; endmodule @@ -6100,12 +6840,18 @@ input [0:3] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -6115,12 +6861,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -6130,12 +6882,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -6145,12 +6903,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -6244,7 +7008,9 @@ cby_1__1__mux_2level_basis_input4_mem4_7 mux_l2_in_0_ ( .mem ( local_encoder2to4_1_data ) , .mem_inv ( local_encoder2to4_1_data_inv ) , .out ( mux_2level_basis_input4_mem4_3_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_101 ( .A ( aps_rename_505_ ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_76 ( .A ( BUF_net_77 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_77 ( .A ( aps_rename_505_ ) , + .Y ( BUF_net_77 ) ) ; endmodule @@ -6256,12 +7022,18 @@ input [0:3] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -6271,12 +7043,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -6286,12 +7064,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -6301,12 +7085,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -6374,7 +7164,7 @@ wire [0:0] mux_2level_basis_input4_mem4_3_out ; cby_1__1__const1_0 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_1_0_ ( - .A ( mux_2level_basis_input4_mem4_3_out[0] ) , .X ( net_net_76 ) ) ; + .A ( mux_2level_basis_input4_mem4_3_out[0] ) , .X ( out[0] ) ) ; cby_1__1__local_encoder2to4_0 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , .data ( local_encoder2to4_0_data ) , .data_inv ( local_encoder2to4_0_data_inv ) ) ; @@ -6400,7 +7190,6 @@ cby_1__1__mux_2level_basis_input4_mem4_3 mux_l2_in_0_ ( .mem ( local_encoder2to4_1_data ) , .mem_inv ( local_encoder2to4_1_data_inv ) , .out ( mux_2level_basis_input4_mem4_3_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_76 ( .A ( net_net_76 ) , .X ( out[0] ) ) ; endmodule @@ -6476,8 +7265,6 @@ input clk_3_N_in ; output clk_3_N_out ; output clk_3_S_out ; -wire ropt_net_130 ; -wire ropt_net_129 ; wire [0:0] prog_clk ; wire prog_clk_0 ; wire [0:3] mux_2level_size10_0_sram ; @@ -6530,7 +7317,7 @@ cby_1__1__mux_2level_size12_0 mux_right_ipin_0 ( .sram ( mux_2level_size12_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 , SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) , - .out ( left_grid_pin_16_ ) , .p0 ( optlc_net_110 ) ) ; + .out ( left_grid_pin_16_ ) , .p0 ( optlc_net_99 ) ) ; cby_1__1__mux_2level_size12_1 mux_right_ipin_2 ( .in ( { chany_top_out[2] , chany_bottom_out[2] , chany_top_out[5] , chany_bottom_out[5] , chany_top_out[8] , chany_bottom_out[8] , @@ -6539,7 +7326,7 @@ cby_1__1__mux_2level_size12_1 mux_right_ipin_2 ( .sram ( mux_2level_size12_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 , SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 } ) , - .out ( left_grid_pin_18_ ) , .p0 ( optlc_net_107 ) ) ; + .out ( left_grid_pin_18_ ) , .p0 ( optlc_net_100 ) ) ; cby_1__1__mux_2level_size12_2 mux_right_ipin_4 ( .in ( { chany_top_out[1] , chany_bottom_out[1] , chany_top_out[4] , chany_bottom_out[4] , chany_top_out[10] , chany_bottom_out[10] , @@ -6548,7 +7335,7 @@ cby_1__1__mux_2level_size12_2 mux_right_ipin_4 ( .sram ( mux_2level_size12_2_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_9 , SYNOPSYS_UNCONNECTED_10 , SYNOPSYS_UNCONNECTED_11 , SYNOPSYS_UNCONNECTED_12 } ) , - .out ( left_grid_pin_20_ ) , .p0 ( optlc_net_109 ) ) ; + .out ( left_grid_pin_20_ ) , .p0 ( optlc_net_99 ) ) ; cby_1__1__mux_2level_size12_3 mux_right_ipin_6 ( .in ( { chany_top_out[0] , chany_bottom_out[0] , chany_top_out[3] , chany_bottom_out[3] , chany_top_out[6] , chany_bottom_out[6] , @@ -6557,7 +7344,7 @@ cby_1__1__mux_2level_size12_3 mux_right_ipin_6 ( .sram ( mux_2level_size12_3_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 , SYNOPSYS_UNCONNECTED_15 , SYNOPSYS_UNCONNECTED_16 } ) , - .out ( left_grid_pin_22_ ) , .p0 ( optlc_net_110 ) ) ; + .out ( left_grid_pin_22_ ) , .p0 ( optlc_net_101 ) ) ; cby_1__1__mux_2level_size12_4 mux_right_ipin_8 ( .in ( { chany_top_out[2] , chany_bottom_out[2] , chany_top_out[5] , chany_bottom_out[5] , chany_top_out[8] , chany_bottom_out[8] , @@ -6566,7 +7353,7 @@ cby_1__1__mux_2level_size12_4 mux_right_ipin_8 ( .sram ( mux_2level_size12_4_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_17 , SYNOPSYS_UNCONNECTED_18 , SYNOPSYS_UNCONNECTED_19 , SYNOPSYS_UNCONNECTED_20 } ) , - .out ( left_grid_pin_24_ ) , .p0 ( optlc_net_108 ) ) ; + .out ( left_grid_pin_24_ ) , .p0 ( optlc_net_100 ) ) ; cby_1__1__mux_2level_size12_5 mux_right_ipin_10 ( .in ( { chany_top_out[1] , chany_bottom_out[1] , chany_top_out[4] , chany_bottom_out[4] , chany_top_out[10] , chany_bottom_out[10] , @@ -6575,7 +7362,7 @@ cby_1__1__mux_2level_size12_5 mux_right_ipin_10 ( .sram ( mux_2level_size12_5_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_21 , SYNOPSYS_UNCONNECTED_22 , SYNOPSYS_UNCONNECTED_23 , SYNOPSYS_UNCONNECTED_24 } ) , - .out ( left_grid_pin_26_ ) , .p0 ( optlc_net_106 ) ) ; + .out ( left_grid_pin_26_ ) , .p0 ( optlc_net_102 ) ) ; cby_1__1__mux_2level_size12_6 mux_right_ipin_12 ( .in ( { chany_top_out[0] , chany_bottom_out[0] , chany_top_out[3] , chany_bottom_out[3] , chany_top_out[6] , chany_bottom_out[6] , @@ -6584,7 +7371,7 @@ cby_1__1__mux_2level_size12_6 mux_right_ipin_12 ( .sram ( mux_2level_size12_6_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_25 , SYNOPSYS_UNCONNECTED_26 , SYNOPSYS_UNCONNECTED_27 , SYNOPSYS_UNCONNECTED_28 } ) , - .out ( left_grid_pin_28_ ) , .p0 ( optlc_net_110 ) ) ; + .out ( left_grid_pin_28_ ) , .p0 ( optlc_net_101 ) ) ; cby_1__1__mux_2level_size12 mux_right_ipin_14 ( .in ( { chany_top_out[2] , chany_bottom_out[2] , chany_top_out[5] , chany_bottom_out[5] , chany_top_out[8] , chany_bottom_out[8] , @@ -6593,7 +7380,7 @@ cby_1__1__mux_2level_size12 mux_right_ipin_14 ( .sram ( mux_2level_size12_7_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_29 , SYNOPSYS_UNCONNECTED_30 , SYNOPSYS_UNCONNECTED_31 , SYNOPSYS_UNCONNECTED_32 } ) , - .out ( left_grid_pin_30_ ) , .p0 ( optlc_net_108 ) ) ; + .out ( left_grid_pin_30_ ) , .p0 ( optlc_net_101 ) ) ; cby_1__1__mux_2level_size12_mem_0 mem_right_ipin_0 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( mux_2level_size12_mem_0_ccff_tail ) , @@ -6641,7 +7428,7 @@ cby_1__1__mux_2level_size10_0 mux_right_ipin_1 ( .sram ( mux_2level_size10_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_33 , SYNOPSYS_UNCONNECTED_34 , SYNOPSYS_UNCONNECTED_35 , SYNOPSYS_UNCONNECTED_36 } ) , - .out ( left_grid_pin_17_ ) , .p0 ( optlc_net_108 ) ) ; + .out ( left_grid_pin_17_ ) , .p0 ( optlc_net_101 ) ) ; cby_1__1__mux_2level_size10_1 mux_right_ipin_3 ( .in ( { chany_top_out[0] , chany_bottom_out[0] , chany_top_out[3] , chany_bottom_out[3] , chany_top_out[9] , chany_bottom_out[9] , @@ -6650,7 +7437,7 @@ cby_1__1__mux_2level_size10_1 mux_right_ipin_3 ( .sram ( mux_2level_size10_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_37 , SYNOPSYS_UNCONNECTED_38 , SYNOPSYS_UNCONNECTED_39 , SYNOPSYS_UNCONNECTED_40 } ) , - .out ( left_grid_pin_19_ ) , .p0 ( optlc_net_108 ) ) ; + .out ( left_grid_pin_19_ ) , .p0 ( optlc_net_100 ) ) ; cby_1__1__mux_2level_size10_2 mux_right_ipin_5 ( .in ( { chany_top_out[2] , chany_bottom_out[2] , chany_top_out[5] , chany_bottom_out[5] , chany_top_out[11] , chany_bottom_out[11] , @@ -6659,7 +7446,7 @@ cby_1__1__mux_2level_size10_2 mux_right_ipin_5 ( .sram ( mux_2level_size10_2_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_41 , SYNOPSYS_UNCONNECTED_42 , SYNOPSYS_UNCONNECTED_43 , SYNOPSYS_UNCONNECTED_44 } ) , - .out ( left_grid_pin_21_ ) , .p0 ( optlc_net_109 ) ) ; + .out ( left_grid_pin_21_ ) , .p0 ( optlc_net_99 ) ) ; cby_1__1__mux_2level_size10_3 mux_right_ipin_7 ( .in ( { chany_top_out[1] , chany_bottom_out[1] , chany_top_out[4] , chany_bottom_out[4] , chany_top_out[7] , chany_bottom_out[7] , @@ -6668,7 +7455,7 @@ cby_1__1__mux_2level_size10_3 mux_right_ipin_7 ( .sram ( mux_2level_size10_3_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_45 , SYNOPSYS_UNCONNECTED_46 , SYNOPSYS_UNCONNECTED_47 , SYNOPSYS_UNCONNECTED_48 } ) , - .out ( left_grid_pin_23_ ) , .p0 ( optlc_net_109 ) ) ; + .out ( left_grid_pin_23_ ) , .p0 ( optlc_net_99 ) ) ; cby_1__1__mux_2level_size10_4 mux_right_ipin_9 ( .in ( { chany_top_out[0] , chany_bottom_out[0] , chany_top_out[3] , chany_bottom_out[3] , chany_top_out[9] , chany_bottom_out[9] , @@ -6677,7 +7464,7 @@ cby_1__1__mux_2level_size10_4 mux_right_ipin_9 ( .sram ( mux_2level_size10_4_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_49 , SYNOPSYS_UNCONNECTED_50 , SYNOPSYS_UNCONNECTED_51 , SYNOPSYS_UNCONNECTED_52 } ) , - .out ( left_grid_pin_25_ ) , .p0 ( optlc_net_106 ) ) ; + .out ( left_grid_pin_25_ ) , .p0 ( optlc_net_100 ) ) ; cby_1__1__mux_2level_size10_5 mux_right_ipin_11 ( .in ( { chany_top_out[2] , chany_bottom_out[2] , chany_top_out[5] , chany_bottom_out[5] , chany_top_out[11] , chany_bottom_out[11] , @@ -6686,8 +7473,7 @@ cby_1__1__mux_2level_size10_5 mux_right_ipin_11 ( .sram ( mux_2level_size10_5_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_53 , SYNOPSYS_UNCONNECTED_54 , SYNOPSYS_UNCONNECTED_55 , SYNOPSYS_UNCONNECTED_56 } ) , - .out ( { ropt_net_128 } ) , - .p0 ( optlc_net_109 ) ) ; + .out ( left_grid_pin_27_ ) , .p0 ( optlc_net_101 ) ) ; cby_1__1__mux_2level_size10_6 mux_right_ipin_13 ( .in ( { chany_top_out[1] , chany_bottom_out[1] , chany_top_out[4] , chany_bottom_out[4] , chany_top_out[13] , chany_bottom_out[13] , @@ -6696,7 +7482,7 @@ cby_1__1__mux_2level_size10_6 mux_right_ipin_13 ( .sram ( mux_2level_size10_6_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_57 , SYNOPSYS_UNCONNECTED_58 , SYNOPSYS_UNCONNECTED_59 , SYNOPSYS_UNCONNECTED_60 } ) , - .out ( left_grid_pin_29_ ) , .p0 ( optlc_net_106 ) ) ; + .out ( left_grid_pin_29_ ) , .p0 ( optlc_net_99 ) ) ; cby_1__1__mux_2level_size10 mux_right_ipin_15 ( .in ( { chany_top_out[0] , chany_bottom_out[0] , chany_top_out[3] , chany_bottom_out[3] , chany_top_out[6] , chany_bottom_out[6] , @@ -6705,7 +7491,7 @@ cby_1__1__mux_2level_size10 mux_right_ipin_15 ( .sram ( mux_2level_size10_7_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_61 , SYNOPSYS_UNCONNECTED_62 , SYNOPSYS_UNCONNECTED_63 , SYNOPSYS_UNCONNECTED_64 } ) , - .out ( left_grid_pin_31_ ) , .p0 ( optlc_net_111 ) ) ; + .out ( left_grid_pin_31_ ) , .p0 ( optlc_net_102 ) ) ; cby_1__1__mux_2level_size10_mem_0 mem_right_ipin_1 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( mux_2level_size12_mem_0_ccff_tail ) , @@ -6745,43 +7531,43 @@ cby_1__1__mux_2level_size10_mem mem_right_ipin_15 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( mux_2level_size12_mem_7_ccff_tail ) , .ccff_tail ( ccff_tail ) , .mem_out ( mux_2level_size10_7_sram ) ) ; -sky130_fd_sc_hd__bufbuf_16 Test_en_N_FTB01 ( .A ( Test_en_E_in ) , - .X ( Test_en_N_out ) ) ; -sky130_fd_sc_hd__bufbuf_16 Test_en_W_FTB01 ( .A ( Test_en_E_in ) , +sky130_fd_sc_hd__buf_1 Test_en_N_FTB01 ( .A ( Test_en_E_in ) , + .X ( net_net_89 ) ) ; +sky130_fd_sc_hd__buf_4 Test_en_W_FTB01 ( .A ( Test_en_E_in ) , .X ( Test_en_W_out ) ) ; sky130_fd_sc_hd__bufbuf_16 Test_en_E_FTB01 ( .A ( Test_en_E_in ) , .X ( Test_en_E_out ) ) ; sky130_fd_sc_hd__buf_8 pReset_FTB00 ( .A ( pReset_S_in ) , .X ( pReset[0] ) ) ; -sky130_fd_sc_hd__conb_1 optlc_109 ( .LO ( SYNOPSYS_UNCONNECTED_65 ) , - .HI ( optlc_net_106 ) ) ; -sky130_fd_sc_hd__buf_1 Reset_N_FTB01 ( .A ( Reset_E_in ) , - .X ( aps_rename_513_ ) ) ; -sky130_fd_sc_hd__bufbuf_16 Reset_W_FTB01 ( .A ( Reset_E_in ) , +sky130_fd_sc_hd__conb_1 optlc_98 ( .LO ( SYNOPSYS_UNCONNECTED_65 ) , + .HI ( optlc_net_99 ) ) ; +sky130_fd_sc_hd__bufbuf_16 Reset_N_FTB01 ( .A ( Reset_E_in ) , + .X ( Reset_N_out ) ) ; +sky130_fd_sc_hd__buf_4 Reset_W_FTB01 ( .A ( Reset_E_in ) , .X ( Reset_W_out ) ) ; sky130_fd_sc_hd__bufbuf_16 Reset_E_FTB01 ( .A ( Reset_E_in ) , .X ( Reset_E_out ) ) ; -sky130_fd_sc_hd__buf_1 prog_clk_0_FTB00 ( .A ( prog_clk_0_W_in ) , +sky130_fd_sc_hd__buf_16 prog_clk_0_FTB00 ( .A ( prog_clk_0_W_in ) , .X ( prog_clk[0] ) ) ; sky130_fd_sc_hd__clkbuf_1 prog_clk_0_S_FTB01 ( .A ( prog_clk_0_W_in ) , - .X ( ctsbuf_net_1112 ) ) ; + .X ( ctsbuf_net_1103 ) ) ; sky130_fd_sc_hd__clkbuf_1 prog_clk_0_N_FTB01 ( .A ( prog_clk_0_W_in ) , - .X ( ctsbuf_net_2113 ) ) ; -sky130_fd_sc_hd__buf_1 prog_clk_2_S_FTB01 ( .A ( prog_clk_2_S_in ) , - .X ( aps_rename_514_ ) ) ; -sky130_fd_sc_hd__buf_1 prog_clk_2_N_FTB01 ( .A ( prog_clk_2_S_in ) , - .X ( aps_rename_515_ ) ) ; -sky130_fd_sc_hd__buf_1 prog_clk_3_N_FTB01 ( .A ( prog_clk_3_N_in ) , - .X ( aps_rename_516_ ) ) ; -sky130_fd_sc_hd__buf_1 prog_clk_3_S_FTB01 ( .A ( prog_clk_3_N_in ) , - .X ( aps_rename_517_ ) ) ; -sky130_fd_sc_hd__buf_1 clk_2_S_FTB01 ( .A ( clk_2_S_in ) , - .X ( aps_rename_518_ ) ) ; -sky130_fd_sc_hd__buf_1 clk_2_N_FTB01 ( .A ( clk_2_S_in ) , - .X ( aps_rename_519_ ) ) ; -sky130_fd_sc_hd__buf_1 clk_3_N_FTB01 ( .A ( clk_3_N_in ) , - .X ( aps_rename_520_ ) ) ; -sky130_fd_sc_hd__buf_1 clk_3_S_FTB01 ( .A ( clk_3_N_in ) , - .X ( aps_rename_521_ ) ) ; + .X ( ctsbuf_net_2104 ) ) ; +sky130_fd_sc_hd__buf_4 prog_clk_2_S_FTB01 ( .A ( prog_clk_2_S_in ) , + .X ( prog_clk_2_S_out ) ) ; +sky130_fd_sc_hd__bufbuf_16 prog_clk_2_N_FTB01 ( .A ( prog_clk_2_S_in ) , + .X ( prog_clk_2_N_out ) ) ; +sky130_fd_sc_hd__bufbuf_16 prog_clk_3_N_FTB01 ( .A ( prog_clk_3_N_in ) , + .X ( prog_clk_3_N_out ) ) ; +sky130_fd_sc_hd__buf_4 prog_clk_3_S_FTB01 ( .A ( prog_clk_3_N_in ) , + .X ( prog_clk_3_S_out ) ) ; +sky130_fd_sc_hd__buf_4 clk_2_S_FTB01 ( .A ( clk_2_S_in ) , + .X ( clk_2_S_out ) ) ; +sky130_fd_sc_hd__bufbuf_16 clk_2_N_FTB01 ( .A ( clk_2_S_in ) , + .X ( clk_2_N_out ) ) ; +sky130_fd_sc_hd__bufbuf_16 clk_3_N_FTB01 ( .A ( clk_3_N_in ) , + .X ( clk_3_N_out ) ) ; +sky130_fd_sc_hd__buf_4 clk_3_S_FTB01 ( .A ( clk_3_N_in ) , + .X ( clk_3_S_out ) ) ; sky130_fd_sc_hd__buf_8 FTB_17__16 ( .A ( chany_bottom_in[0] ) , .X ( chany_top_out[0] ) ) ; sky130_fd_sc_hd__buf_8 FTB_18__17 ( .A ( chany_bottom_in[1] ) , @@ -6829,7 +7615,7 @@ sky130_fd_sc_hd__buf_8 FTB_38__37 ( .A ( chany_bottom_in[21] ) , sky130_fd_sc_hd__buf_8 FTB_39__38 ( .A ( chany_bottom_in[22] ) , .X ( chany_top_out[22] ) ) ; sky130_fd_sc_hd__buf_6 FTB_40__39 ( .A ( chany_bottom_in[23] ) , - .X ( ropt_net_130 ) ) ; + .X ( chany_top_out[23] ) ) ; sky130_fd_sc_hd__buf_8 FTB_41__40 ( .A ( chany_bottom_in[24] ) , .X ( chany_top_out[24] ) ) ; sky130_fd_sc_hd__buf_8 FTB_42__41 ( .A ( chany_bottom_in[25] ) , @@ -6889,7 +7675,7 @@ sky130_fd_sc_hd__buf_8 FTB_68__67 ( .A ( chany_top_in[21] ) , sky130_fd_sc_hd__buf_8 FTB_69__68 ( .A ( chany_top_in[22] ) , .X ( chany_bottom_out[22] ) ) ; sky130_fd_sc_hd__buf_6 FTB_70__69 ( .A ( chany_top_in[23] ) , - .X ( ropt_net_129 ) ) ; + .X ( chany_bottom_out[23] ) ) ; sky130_fd_sc_hd__buf_8 FTB_71__70 ( .A ( chany_top_in[24] ) , .X ( chany_bottom_out[24] ) ) ; sky130_fd_sc_hd__buf_8 FTB_72__71 ( .A ( chany_top_in[25] ) , @@ -6902,48 +7688,19 @@ sky130_fd_sc_hd__buf_8 FTB_75__74 ( .A ( chany_top_in[28] ) , .X ( chany_bottom_out[28] ) ) ; sky130_fd_sc_hd__buf_8 FTB_76__75 ( .A ( chany_top_in[29] ) , .X ( chany_bottom_out[29] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_95 ( .A ( BUF_net_96 ) , .Y ( pReset_N_out ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_96 ( .A ( pReset_S_in ) , .Y ( BUF_net_96 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_97 ( .A ( BUF_net_98 ) , .Y ( Reset_N_out ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_98 ( .A ( aps_rename_513_ ) , - .Y ( BUF_net_98 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_99 ( .A ( BUF_net_100 ) , .Y ( clk_3_N_out ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_100 ( .A ( aps_rename_520_ ) , - .Y ( BUF_net_100 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_110 ( .LO ( SYNOPSYS_UNCONNECTED_66 ) , - .HI ( optlc_net_107 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_114 ( .LO ( SYNOPSYS_UNCONNECTED_67 ) , - .HI ( optlc_net_108 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_116 ( .LO ( SYNOPSYS_UNCONNECTED_68 ) , - .HI ( optlc_net_109 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_118 ( .LO ( SYNOPSYS_UNCONNECTED_69 ) , - .HI ( optlc_net_110 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_119 ( .LO ( SYNOPSYS_UNCONNECTED_70 ) , - .HI ( optlc_net_111 ) ) ; -sky130_fd_sc_hd__buf_6 ZBUF_4_f_inst_120 ( .A ( aps_rename_521_ ) , - .X ( clk_3_S_out ) ) ; -sky130_fd_sc_hd__buf_6 ZBUF_4_f_inst_121 ( .A ( aps_rename_517_ ) , - .X ( prog_clk_3_S_out ) ) ; -sky130_fd_sc_hd__buf_6 ZBUF_4_f_inst_122 ( .A ( aps_rename_519_ ) , - .X ( clk_2_N_out ) ) ; -sky130_fd_sc_hd__buf_6 ZBUF_4_f_inst_123 ( .A ( aps_rename_515_ ) , - .X ( prog_clk_2_N_out ) ) ; -sky130_fd_sc_hd__buf_6 ZBUF_4_f_inst_124 ( .A ( aps_rename_516_ ) , - .X ( prog_clk_3_N_out ) ) ; -sky130_fd_sc_hd__buf_6 ZBUF_4_f_inst_125 ( .A ( aps_rename_514_ ) , - .X ( prog_clk_2_S_out ) ) ; -sky130_fd_sc_hd__buf_6 ZBUF_4_f_inst_126 ( .A ( aps_rename_518_ ) , - .X ( clk_2_S_out ) ) ; -sky130_fd_sc_hd__buf_6 ropt_mt_inst_1377 ( .A ( ropt_net_128 ) , - .X ( left_grid_pin_27_[0] ) ) ; -sky130_fd_sc_hd__buf_6 cts_buf_3651266 ( .A ( ctsbuf_net_1112 ) , +sky130_fd_sc_hd__buf_6 BUFT_RR_89 ( .A ( net_net_89 ) , .X ( Test_en_N_out ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_90 ( .A ( BUF_net_91 ) , .Y ( pReset_N_out ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_91 ( .A ( pReset_S_in ) , .Y ( BUF_net_91 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_100 ( .LO ( SYNOPSYS_UNCONNECTED_66 ) , + .HI ( optlc_net_100 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_102 ( .LO ( SYNOPSYS_UNCONNECTED_67 ) , + .HI ( optlc_net_101 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_104 ( .LO ( SYNOPSYS_UNCONNECTED_68 ) , + .HI ( optlc_net_102 ) ) ; +sky130_fd_sc_hd__buf_6 cts_buf_3651244 ( .A ( ctsbuf_net_1103 ) , .X ( prog_clk_0_S_out ) ) ; -sky130_fd_sc_hd__clkbuf_8 cts_buf_3701271 ( .A ( ctsbuf_net_2113 ) , +sky130_fd_sc_hd__clkbuf_8 cts_buf_3701249 ( .A ( ctsbuf_net_2104 ) , .X ( prog_clk_0_N_out ) ) ; -sky130_fd_sc_hd__buf_8 ropt_mt_inst_1378 ( .A ( ropt_net_129 ) , - .X ( chany_bottom_out[23] ) ) ; -sky130_fd_sc_hd__buf_8 ropt_mt_inst_1379 ( .A ( ropt_net_130 ) , - .X ( chany_top_out[23] ) ) ; endmodule @@ -6955,21 +7712,23 @@ input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:0] mem_out ; +wire copt_net_73 ; + sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__buf_6 FTB_2__1 ( .A ( copt_net_78 ) , .X ( ccff_tail[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1224 ( .A ( copt_net_76 ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( copt_net_73 ) ) ; +sky130_fd_sc_hd__buf_6 FTB_2__1 ( .A ( mem_out[0] ) , .X ( ccff_tail[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1223 ( .A ( copt_net_74 ) , + .X ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1224 ( .A ( copt_net_75 ) , .X ( copt_net_74 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1225 ( .A ( copt_net_74 ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1225 ( .A ( copt_net_76 ) , .X ( copt_net_75 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1226 ( .A ( mem_out[0] ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1226 ( .A ( copt_net_78 ) , .X ( copt_net_76 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1227 ( .A ( copt_net_79 ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1227 ( .A ( copt_net_73 ) , .X ( copt_net_77 ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1228 ( .A ( copt_net_77 ) , .X ( copt_net_78 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1229 ( .A ( copt_net_75 ) , - .X ( copt_net_79 ) ) ; endmodule @@ -7059,7 +7818,7 @@ input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( copt_net_73 ) , +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( copt_net_72 ) , .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; @@ -7068,18 +7827,18 @@ sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__buf_1 FTB_1__0 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1218 ( .A ( ccff_head[0] ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1217 ( .A ( ccff_head[0] ) , + .X ( copt_net_67 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1218 ( .A ( copt_net_69 ) , .X ( copt_net_68 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1219 ( .A ( copt_net_68 ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1219 ( .A ( copt_net_71 ) , .X ( copt_net_69 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1220 ( .A ( copt_net_69 ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1220 ( .A ( copt_net_67 ) , .X ( copt_net_70 ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1221 ( .A ( copt_net_70 ) , .X ( copt_net_71 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1222 ( .A ( copt_net_71 ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1222 ( .A ( copt_net_68 ) , .X ( copt_net_72 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1223 ( .A ( copt_net_72 ) , - .X ( copt_net_73 ) ) ; endmodule @@ -7091,12 +7850,18 @@ input [0:3] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -7106,12 +7871,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -7121,12 +7892,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -7136,12 +7913,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -7208,8 +7991,8 @@ wire [0:0] mux_2level_basis_input4_mem4_3_out ; cby_0__1__const1 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_1_0_ ( - .A ( mux_2level_basis_input4_mem4_3_out[0] ) , .X ( net_net_66 ) ) ; +sky130_fd_sc_hd__bufbuf_16 sky130_fd_sc_hd__buf_1_0_ ( + .A ( mux_2level_basis_input4_mem4_3_out[0] ) , .X ( out[0] ) ) ; cby_0__1__local_encoder2to4_0 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , .data ( local_encoder2to4_0_data ) , .data_inv ( local_encoder2to4_0_data_inv ) ) ; @@ -7235,7 +8018,6 @@ cby_0__1__mux_2level_basis_input4_mem4 mux_l2_in_0_ ( .mem ( local_encoder2to4_1_data ) , .mem_inv ( local_encoder2to4_1_data_inv ) , .out ( mux_2level_basis_input4_mem4_3_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_66 ( .A ( net_net_66 ) , .X ( out[0] ) ) ; endmodule @@ -7263,30 +8045,27 @@ output [0:0] right_width_0_height_0__pin_1_lower ; input pReset_N_in ; input prog_clk_0_E_in ; -wire ropt_net_149 ; -wire ropt_net_145 ; -wire ropt_net_129 ; -wire ropt_net_147 ; -wire ropt_net_152 ; -wire ropt_net_151 ; -wire ropt_net_142 ; -wire ropt_net_138 ; -wire ropt_net_133 ; -wire ropt_net_137 ; -wire ropt_net_130 ; -wire ropt_net_134 ; -wire ropt_net_140 ; -wire ropt_net_144 ; +wire ropt_net_122 ; wire ropt_net_135 ; -wire ropt_net_136 ; -wire ropt_net_139 ; -wire ropt_net_132 ; -wire ropt_net_150 ; -wire ropt_net_143 ; -wire ropt_net_131 ; -wire ropt_net_126 ; -wire ropt_net_127 ; wire ropt_net_128 ; +wire ropt_net_121 ; +wire ropt_net_139 ; +wire ropt_net_129 ; +wire ropt_net_134 ; +wire ropt_net_133 ; +wire ropt_net_132 ; +wire ropt_net_138 ; +wire ropt_net_123 ; +wire ropt_net_141 ; +wire ropt_net_126 ; +wire ropt_net_120 ; +wire ropt_net_125 ; +wire ropt_net_130 ; +wire ropt_net_131 ; +wire ropt_net_140 ; +wire ropt_net_137 ; +wire ropt_net_124 ; +wire ropt_net_127 ; wire [0:0] prog_clk ; wire prog_clk_0 ; wire [0:3] mux_2level_size12_0_sram ; @@ -7301,7 +8080,7 @@ cby_0__1__mux_2level_size12 mux_right_ipin_0 ( .sram ( mux_2level_size12_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 , SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) , - .out ( left_grid_pin_0_ ) , .p0 ( optlc_net_67 ) ) ; + .out ( left_grid_pin_0_ ) , .p0 ( optlc_net_66 ) ) ; cby_0__1__mux_2level_size12_mem mem_right_ipin_0 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( { ccff_tail_mid } ) , @@ -7320,177 +8099,171 @@ sky130_fd_sc_hd__buf_1 prog_clk_0_FTB00 ( .A ( prog_clk_0_E_in ) , .X ( prog_clk[0] ) ) ; sky130_fd_sc_hd__buf_8 FTB_3__2 ( .A ( chany_bottom_in[0] ) , .X ( chany_top_out[0] ) ) ; -sky130_fd_sc_hd__buf_6 FTB_4__3 ( .A ( chany_bottom_in[1] ) , - .X ( ropt_net_149 ) ) ; -sky130_fd_sc_hd__buf_8 FTB_5__4 ( .A ( chany_bottom_in[2] ) , - .X ( chany_top_out[2] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_4__3 ( .A ( chany_bottom_in[1] ) , + .X ( chany_top_out[1] ) ) ; +sky130_fd_sc_hd__buf_6 FTB_5__4 ( .A ( chany_bottom_in[2] ) , + .X ( ropt_net_122 ) ) ; sky130_fd_sc_hd__buf_8 FTB_6__5 ( .A ( chany_bottom_in[3] ) , .X ( chany_top_out[3] ) ) ; -sky130_fd_sc_hd__buf_8 FTB_7__6 ( .A ( chany_bottom_in[4] ) , - .X ( chany_top_out[4] ) ) ; -sky130_fd_sc_hd__buf_8 FTB_8__7 ( .A ( chany_bottom_in[5] ) , - .X ( chany_top_out[5] ) ) ; +sky130_fd_sc_hd__buf_6 FTB_7__6 ( .A ( chany_bottom_in[4] ) , + .X ( ropt_net_135 ) ) ; +sky130_fd_sc_hd__buf_6 FTB_8__7 ( .A ( chany_bottom_in[5] ) , + .X ( ropt_net_128 ) ) ; sky130_fd_sc_hd__buf_8 FTB_9__8 ( .A ( chany_bottom_in[6] ) , .X ( chany_top_out[6] ) ) ; -sky130_fd_sc_hd__buf_8 FTB_10__9 ( .A ( chany_bottom_in[7] ) , +sky130_fd_sc_hd__buf_6 FTB_10__9 ( .A ( chany_bottom_in[7] ) , .X ( chany_top_out[7] ) ) ; -sky130_fd_sc_hd__buf_6 FTB_11__10 ( .A ( chany_bottom_in[8] ) , - .X ( ropt_net_145 ) ) ; -sky130_fd_sc_hd__buf_6 FTB_12__11 ( .A ( chany_bottom_in[9] ) , - .X ( ropt_net_129 ) ) ; +sky130_fd_sc_hd__buf_8 FTB_11__10 ( .A ( chany_bottom_in[8] ) , + .X ( chany_top_out[8] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_12__11 ( .A ( chany_bottom_in[9] ) , + .X ( chany_top_out[9] ) ) ; sky130_fd_sc_hd__buf_8 FTB_13__12 ( .A ( chany_bottom_in[10] ) , .X ( chany_top_out[10] ) ) ; sky130_fd_sc_hd__buf_6 FTB_14__13 ( .A ( chany_bottom_in[11] ) , .X ( chany_top_out[11] ) ) ; sky130_fd_sc_hd__buf_8 FTB_15__14 ( .A ( chany_bottom_in[12] ) , .X ( chany_top_out[12] ) ) ; -sky130_fd_sc_hd__buf_8 FTB_16__15 ( .A ( chany_bottom_in[13] ) , - .X ( chany_top_out[13] ) ) ; +sky130_fd_sc_hd__buf_6 FTB_16__15 ( .A ( chany_bottom_in[13] ) , + .X ( ropt_net_121 ) ) ; sky130_fd_sc_hd__buf_8 FTB_17__16 ( .A ( chany_bottom_in[14] ) , .X ( chany_top_out[14] ) ) ; sky130_fd_sc_hd__buf_8 FTB_18__17 ( .A ( chany_bottom_in[15] ) , .X ( chany_top_out[15] ) ) ; -sky130_fd_sc_hd__buf_8 FTB_19__18 ( .A ( chany_bottom_in[16] ) , +sky130_fd_sc_hd__buf_6 FTB_19__18 ( .A ( chany_bottom_in[16] ) , .X ( chany_top_out[16] ) ) ; sky130_fd_sc_hd__buf_6 FTB_20__19 ( .A ( chany_bottom_in[17] ) , - .X ( ropt_net_147 ) ) ; + .X ( ropt_net_139 ) ) ; sky130_fd_sc_hd__buf_8 FTB_21__20 ( .A ( chany_bottom_in[18] ) , .X ( chany_top_out[18] ) ) ; sky130_fd_sc_hd__buf_6 FTB_22__21 ( .A ( chany_bottom_in[19] ) , - .X ( ropt_net_152 ) ) ; + .X ( chany_top_out[19] ) ) ; sky130_fd_sc_hd__buf_6 FTB_23__22 ( .A ( chany_bottom_in[20] ) , - .X ( ropt_net_151 ) ) ; + .X ( chany_top_out[20] ) ) ; sky130_fd_sc_hd__buf_8 FTB_24__23 ( .A ( chany_bottom_in[21] ) , .X ( chany_top_out[21] ) ) ; sky130_fd_sc_hd__buf_6 FTB_25__24 ( .A ( chany_bottom_in[22] ) , - .X ( ropt_net_142 ) ) ; -sky130_fd_sc_hd__buf_6 FTB_26__25 ( .A ( chany_bottom_in[23] ) , - .X ( ropt_net_138 ) ) ; + .X ( ropt_net_129 ) ) ; +sky130_fd_sc_hd__buf_8 FTB_26__25 ( .A ( chany_bottom_in[23] ) , + .X ( chany_top_out[23] ) ) ; sky130_fd_sc_hd__buf_8 FTB_27__26 ( .A ( chany_bottom_in[24] ) , .X ( chany_top_out[24] ) ) ; sky130_fd_sc_hd__buf_6 FTB_28__27 ( .A ( chany_bottom_in[25] ) , - .X ( ropt_net_133 ) ) ; + .X ( ropt_net_134 ) ) ; sky130_fd_sc_hd__buf_6 FTB_29__28 ( .A ( chany_bottom_in[26] ) , - .X ( ropt_net_137 ) ) ; + .X ( ropt_net_133 ) ) ; sky130_fd_sc_hd__buf_8 FTB_30__29 ( .A ( chany_bottom_in[27] ) , .X ( chany_top_out[27] ) ) ; -sky130_fd_sc_hd__buf_8 FTB_31__30 ( .A ( chany_bottom_in[28] ) , +sky130_fd_sc_hd__buf_6 FTB_31__30 ( .A ( chany_bottom_in[28] ) , .X ( chany_top_out[28] ) ) ; -sky130_fd_sc_hd__buf_6 FTB_32__31 ( .A ( chany_bottom_in[29] ) , - .X ( ropt_net_130 ) ) ; +sky130_fd_sc_hd__buf_8 FTB_32__31 ( .A ( chany_bottom_in[29] ) , + .X ( chany_top_out[29] ) ) ; sky130_fd_sc_hd__buf_8 FTB_33__32 ( .A ( chany_top_in[0] ) , .X ( chany_bottom_out[0] ) ) ; -sky130_fd_sc_hd__buf_6 FTB_34__33 ( .A ( chany_top_in[1] ) , - .X ( ropt_net_134 ) ) ; +sky130_fd_sc_hd__buf_8 FTB_34__33 ( .A ( chany_top_in[1] ) , + .X ( chany_bottom_out[1] ) ) ; sky130_fd_sc_hd__buf_6 FTB_35__34 ( .A ( chany_top_in[2] ) , - .X ( ropt_net_140 ) ) ; + .X ( ropt_net_132 ) ) ; sky130_fd_sc_hd__buf_8 FTB_36__35 ( .A ( chany_top_in[3] ) , .X ( chany_bottom_out[3] ) ) ; sky130_fd_sc_hd__buf_8 FTB_37__36 ( .A ( chany_top_in[4] ) , .X ( chany_bottom_out[4] ) ) ; -sky130_fd_sc_hd__buf_8 FTB_38__37 ( .A ( chany_top_in[5] ) , - .X ( chany_bottom_out[5] ) ) ; +sky130_fd_sc_hd__buf_6 FTB_38__37 ( .A ( chany_top_in[5] ) , + .X ( ropt_net_138 ) ) ; sky130_fd_sc_hd__buf_8 FTB_39__38 ( .A ( chany_top_in[6] ) , .X ( chany_bottom_out[6] ) ) ; sky130_fd_sc_hd__buf_6 FTB_40__39 ( .A ( chany_top_in[7] ) , - .X ( ropt_net_144 ) ) ; -sky130_fd_sc_hd__buf_8 FTB_41__40 ( .A ( chany_top_in[8] ) , + .X ( ropt_net_123 ) ) ; +sky130_fd_sc_hd__buf_6 FTB_41__40 ( .A ( chany_top_in[8] ) , .X ( chany_bottom_out[8] ) ) ; -sky130_fd_sc_hd__buf_8 FTB_42__41 ( .A ( chany_top_in[9] ) , - .X ( chany_bottom_out[9] ) ) ; +sky130_fd_sc_hd__buf_6 FTB_42__41 ( .A ( chany_top_in[9] ) , + .X ( ropt_net_141 ) ) ; sky130_fd_sc_hd__buf_6 FTB_43__42 ( .A ( chany_top_in[10] ) , - .X ( ropt_net_135 ) ) ; + .X ( ropt_net_126 ) ) ; sky130_fd_sc_hd__buf_8 FTB_44__43 ( .A ( chany_top_in[11] ) , .X ( chany_bottom_out[11] ) ) ; sky130_fd_sc_hd__buf_8 FTB_45__44 ( .A ( chany_top_in[12] ) , .X ( chany_bottom_out[12] ) ) ; sky130_fd_sc_hd__buf_6 FTB_46__45 ( .A ( chany_top_in[13] ) , - .X ( ropt_net_136 ) ) ; + .X ( ropt_net_120 ) ) ; sky130_fd_sc_hd__buf_6 FTB_47__46 ( .A ( chany_top_in[14] ) , - .X ( ropt_net_139 ) ) ; -sky130_fd_sc_hd__buf_8 FTB_48__47 ( .A ( chany_top_in[15] ) , - .X ( chany_bottom_out[15] ) ) ; + .X ( ropt_net_125 ) ) ; +sky130_fd_sc_hd__buf_6 FTB_48__47 ( .A ( chany_top_in[15] ) , + .X ( ropt_net_130 ) ) ; sky130_fd_sc_hd__buf_6 FTB_49__48 ( .A ( chany_top_in[16] ) , - .X ( chany_bottom_out[16] ) ) ; + .X ( ropt_net_131 ) ) ; sky130_fd_sc_hd__buf_8 FTB_50__49 ( .A ( chany_top_in[17] ) , .X ( chany_bottom_out[17] ) ) ; sky130_fd_sc_hd__buf_8 FTB_51__50 ( .A ( chany_top_in[18] ) , .X ( chany_bottom_out[18] ) ) ; -sky130_fd_sc_hd__buf_6 FTB_52__51 ( .A ( chany_top_in[19] ) , - .X ( ropt_net_132 ) ) ; +sky130_fd_sc_hd__buf_8 FTB_52__51 ( .A ( chany_top_in[19] ) , + .X ( chany_bottom_out[19] ) ) ; sky130_fd_sc_hd__buf_6 FTB_53__52 ( .A ( chany_top_in[20] ) , - .X ( ropt_net_150 ) ) ; + .X ( ropt_net_140 ) ) ; sky130_fd_sc_hd__buf_8 FTB_54__53 ( .A ( chany_top_in[21] ) , .X ( chany_bottom_out[21] ) ) ; sky130_fd_sc_hd__buf_6 FTB_55__54 ( .A ( chany_top_in[22] ) , - .X ( ropt_net_143 ) ) ; -sky130_fd_sc_hd__buf_8 FTB_56__55 ( .A ( chany_top_in[23] ) , - .X ( chany_bottom_out[23] ) ) ; + .X ( ropt_net_137 ) ) ; +sky130_fd_sc_hd__buf_6 FTB_56__55 ( .A ( chany_top_in[23] ) , + .X ( ropt_net_124 ) ) ; sky130_fd_sc_hd__buf_8 FTB_57__56 ( .A ( chany_top_in[24] ) , .X ( chany_bottom_out[24] ) ) ; sky130_fd_sc_hd__buf_6 FTB_58__57 ( .A ( chany_top_in[25] ) , - .X ( ropt_net_131 ) ) ; -sky130_fd_sc_hd__buf_6 FTB_59__58 ( .A ( chany_top_in[26] ) , - .X ( ropt_net_126 ) ) ; -sky130_fd_sc_hd__buf_6 FTB_60__59 ( .A ( chany_top_in[27] ) , .X ( ropt_net_127 ) ) ; +sky130_fd_sc_hd__buf_8 FTB_59__58 ( .A ( chany_top_in[26] ) , + .X ( chany_bottom_out[26] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_60__59 ( .A ( chany_top_in[27] ) , + .X ( chany_bottom_out[27] ) ) ; sky130_fd_sc_hd__buf_8 FTB_61__60 ( .A ( chany_top_in[28] ) , .X ( chany_bottom_out[28] ) ) ; -sky130_fd_sc_hd__buf_6 FTB_62__61 ( .A ( chany_top_in[29] ) , - .X ( ropt_net_128 ) ) ; +sky130_fd_sc_hd__buf_8 FTB_62__61 ( .A ( chany_top_in[29] ) , + .X ( chany_bottom_out[29] ) ) ; sky130_fd_sc_hd__buf_6 FTB_63__62 ( .A ( right_width_0_height_0__pin_1_lower[0] ) , .X ( right_width_0_height_0__pin_1_upper[0] ) ) ; -sky130_fd_sc_hd__conb_1 optlc_68 ( .LO ( SYNOPSYS_UNCONNECTED_5 ) , - .HI ( optlc_net_67 ) ) ; -sky130_fd_sc_hd__buf_8 ropt_mt_inst_1276 ( .A ( ropt_net_126 ) , - .X ( chany_bottom_out[26] ) ) ; -sky130_fd_sc_hd__buf_8 ropt_mt_inst_1277 ( .A ( ropt_net_127 ) , - .X ( chany_bottom_out[27] ) ) ; -sky130_fd_sc_hd__buf_8 ropt_mt_inst_1278 ( .A ( ropt_net_128 ) , - .X ( chany_bottom_out[29] ) ) ; -sky130_fd_sc_hd__buf_8 ropt_mt_inst_1279 ( .A ( ropt_net_129 ) , - .X ( chany_top_out[9] ) ) ; -sky130_fd_sc_hd__buf_8 ropt_mt_inst_1280 ( .A ( ropt_net_130 ) , - .X ( chany_top_out[29] ) ) ; -sky130_fd_sc_hd__buf_8 ropt_mt_inst_1281 ( .A ( ropt_net_131 ) , - .X ( chany_bottom_out[25] ) ) ; -sky130_fd_sc_hd__buf_8 ropt_mt_inst_1282 ( .A ( ropt_net_132 ) , - .X ( chany_bottom_out[19] ) ) ; -sky130_fd_sc_hd__buf_8 ropt_mt_inst_1283 ( .A ( ropt_net_133 ) , - .X ( chany_top_out[25] ) ) ; -sky130_fd_sc_hd__buf_8 ropt_mt_inst_1284 ( .A ( ropt_net_134 ) , - .X ( chany_bottom_out[1] ) ) ; -sky130_fd_sc_hd__buf_8 ropt_mt_inst_1285 ( .A ( ropt_net_135 ) , - .X ( chany_bottom_out[10] ) ) ; -sky130_fd_sc_hd__buf_8 ropt_mt_inst_1286 ( .A ( ropt_net_136 ) , +sky130_fd_sc_hd__conb_1 optlc_67 ( .LO ( SYNOPSYS_UNCONNECTED_5 ) , + .HI ( optlc_net_66 ) ) ; +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1270 ( .A ( ropt_net_120 ) , .X ( chany_bottom_out[13] ) ) ; -sky130_fd_sc_hd__buf_8 ropt_mt_inst_1287 ( .A ( ropt_net_137 ) , - .X ( chany_top_out[26] ) ) ; -sky130_fd_sc_hd__buf_8 ropt_mt_inst_1288 ( .A ( ropt_net_138 ) , - .X ( chany_top_out[23] ) ) ; -sky130_fd_sc_hd__buf_8 ropt_mt_inst_1289 ( .A ( ropt_net_139 ) , - .X ( chany_bottom_out[14] ) ) ; -sky130_fd_sc_hd__buf_8 ropt_mt_inst_1290 ( .A ( ropt_net_140 ) , - .X ( chany_bottom_out[2] ) ) ; -sky130_fd_sc_hd__buf_8 ropt_mt_inst_1292 ( .A ( ropt_net_142 ) , - .X ( chany_top_out[22] ) ) ; -sky130_fd_sc_hd__buf_8 ropt_mt_inst_1293 ( .A ( ropt_net_143 ) , - .X ( chany_bottom_out[22] ) ) ; -sky130_fd_sc_hd__buf_8 ropt_mt_inst_1294 ( .A ( ropt_net_144 ) , +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1271 ( .A ( ropt_net_121 ) , + .X ( chany_top_out[13] ) ) ; +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1272 ( .A ( ropt_net_122 ) , + .X ( chany_top_out[2] ) ) ; +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1273 ( .A ( ropt_net_123 ) , .X ( chany_bottom_out[7] ) ) ; -sky130_fd_sc_hd__buf_8 ropt_mt_inst_1295 ( .A ( ropt_net_145 ) , - .X ( chany_top_out[8] ) ) ; -sky130_fd_sc_hd__buf_8 ropt_mt_inst_1297 ( .A ( ropt_net_147 ) , +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1274 ( .A ( ropt_net_124 ) , + .X ( chany_bottom_out[23] ) ) ; +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1275 ( .A ( ropt_net_125 ) , + .X ( chany_bottom_out[14] ) ) ; +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1276 ( .A ( ropt_net_126 ) , + .X ( chany_bottom_out[10] ) ) ; +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1277 ( .A ( ropt_net_127 ) , + .X ( chany_bottom_out[25] ) ) ; +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1278 ( .A ( ropt_net_128 ) , + .X ( chany_top_out[5] ) ) ; +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1279 ( .A ( ropt_net_129 ) , + .X ( chany_top_out[22] ) ) ; +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1280 ( .A ( ropt_net_130 ) , + .X ( chany_bottom_out[15] ) ) ; +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1281 ( .A ( ropt_net_131 ) , + .X ( chany_bottom_out[16] ) ) ; +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1282 ( .A ( ropt_net_132 ) , + .X ( chany_bottom_out[2] ) ) ; +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1283 ( .A ( ropt_net_133 ) , + .X ( chany_top_out[26] ) ) ; +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1284 ( .A ( ropt_net_134 ) , + .X ( chany_top_out[25] ) ) ; +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1285 ( .A ( ropt_net_135 ) , + .X ( chany_top_out[4] ) ) ; +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1287 ( .A ( ropt_net_137 ) , + .X ( chany_bottom_out[22] ) ) ; +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1288 ( .A ( ropt_net_138 ) , + .X ( chany_bottom_out[5] ) ) ; +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1289 ( .A ( ropt_net_139 ) , .X ( chany_top_out[17] ) ) ; -sky130_fd_sc_hd__buf_8 ropt_mt_inst_1299 ( .A ( ropt_net_149 ) , - .X ( chany_top_out[1] ) ) ; -sky130_fd_sc_hd__buf_8 ropt_mt_inst_1300 ( .A ( ropt_net_150 ) , +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1290 ( .A ( ropt_net_140 ) , .X ( chany_bottom_out[20] ) ) ; -sky130_fd_sc_hd__buf_8 ropt_mt_inst_1301 ( .A ( ropt_net_151 ) , - .X ( chany_top_out[20] ) ) ; -sky130_fd_sc_hd__buf_8 ropt_mt_inst_1302 ( .A ( ropt_net_152 ) , - .X ( chany_top_out[19] ) ) ; +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1291 ( .A ( ropt_net_141 ) , + .X ( chany_bottom_out[9] ) ) ; endmodule @@ -7502,17 +8275,9 @@ input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:0] mem_out ; -wire copt_net_138 ; - sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( copt_net_138 ) ) ; + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; sky130_fd_sc_hd__buf_6 FTB_18__17 ( .A ( mem_out[0] ) , .X ( ccff_tail[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1374 ( .A ( copt_net_138 ) , - .X ( copt_net_137 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1376 ( .A ( copt_net_140 ) , - .X ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1377 ( .A ( copt_net_137 ) , - .X ( copt_net_140 ) ) ; endmodule @@ -7527,15 +8292,16 @@ input FPGA_DIR ; input IO_ISOL_N ; sky130_fd_sc_hd__nand2b_1 ISOL_EN_GATE ( .A_N ( FPGA_DIR ) , - .B ( IO_ISOL_N ) , .Y ( aps_rename_516_ ) ) ; -sky130_fd_sc_hd__inv_1 INV_SOC_DIR ( .A ( BUF_net_81 ) , .Y ( SOC_DIR_N ) ) ; + .B ( IO_ISOL_N ) , .Y ( aps_rename_515_ ) ) ; +sky130_fd_sc_hd__inv_1 INV_SOC_DIR ( .A ( aps_rename_515_ ) , + .Y ( SOC_DIR_N ) ) ; sky130_fd_sc_hd__ebufn_4 IN_PROTECT_GATE ( .A ( SOC_IN ) , .TE_B ( SOC_DIR_N ) , .Z ( FPGA_IN ) ) ; sky130_fd_sc_hd__ebufn_4 OUT_PROTECT_GATE ( .A ( FPGA_OUT ) , - .TE_B ( BUF_net_81 ) , .Z ( SOC_OUT ) ) ; -sky130_fd_sc_hd__inv_4 BINV_R_81 ( .A ( BUF_net_83 ) , .Y ( BUF_net_81 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_82 ( .A ( BUF_net_83 ) , .Y ( SOC_DIR ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_83 ( .A ( aps_rename_516_ ) , + .TE_B ( BUF_net_82 ) , .Z ( SOC_OUT ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_81 ( .A ( BUF_net_83 ) , .Y ( SOC_DIR ) ) ; +sky130_fd_sc_hd__inv_4 BINV_R_82 ( .A ( BUF_net_83 ) , .Y ( BUF_net_82 ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_83 ( .A ( aps_rename_515_ ) , .Y ( BUF_net_83 ) ) ; endmodule @@ -7760,9 +8526,13 @@ input [0:1] mem ; input [0:1] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -7774,12 +8544,18 @@ input [0:3] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -7789,12 +8565,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -7804,12 +8586,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -7877,7 +8665,7 @@ wire [0:0] mux_2level_basis_input4_mem4_2_out ; cbx_1__2__const1 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_1_0_ ( - .A ( mux_2level_basis_input4_mem4_2_out[0] ) , .X ( out[0] ) ) ; + .A ( mux_2level_basis_input4_mem4_2_out[0] ) , .X ( aps_rename_514_ ) ) ; cbx_1__2__local_encoder2to4_32 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , .data ( local_encoder2to4_0_data ) , .data_inv ( local_encoder2to4_0_data_inv ) ) ; @@ -7903,6 +8691,9 @@ cbx_1__2__mux_2level_basis_input2_mem2 mux_l1_in_2_ ( .in ( in[8:9] ) , .mem ( local_encoder2to4_0_data[0:1] ) , .mem_inv ( local_encoder2to4_0_data_inv[0:1] ) , .out ( mux_2level_basis_input2_mem2_0_out ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_95 ( .A ( aps_rename_514_ ) , + .Y ( BUF_net_95 ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_101 ( .A ( BUF_net_95 ) , .Y ( out[0] ) ) ; endmodule @@ -7912,9 +8703,13 @@ input [0:1] mem ; input [0:1] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -7926,12 +8721,18 @@ input [0:3] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -7941,12 +8742,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -7956,12 +8763,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -8029,7 +8842,7 @@ wire [0:0] mux_2level_basis_input4_mem4_2_out ; cbx_1__2__const1_15 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_1_0_ ( - .A ( mux_2level_basis_input4_mem4_2_out[0] ) , .X ( aps_rename_515_ ) ) ; + .A ( mux_2level_basis_input4_mem4_2_out[0] ) , .X ( out[0] ) ) ; cbx_1__2__local_encoder2to4_30 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , .data ( local_encoder2to4_0_data ) , .data_inv ( local_encoder2to4_0_data_inv ) ) ; @@ -8055,9 +8868,6 @@ cbx_1__2__mux_2level_basis_input2_mem2_6 mux_l1_in_2_ ( .in ( in[8:9] ) , .mem ( local_encoder2to4_0_data[0:1] ) , .mem_inv ( local_encoder2to4_0_data_inv[0:1] ) , .out ( mux_2level_basis_input2_mem2_0_out ) ) ; -sky130_fd_sc_hd__inv_2 BINV_R_106 ( .A ( aps_rename_515_ ) , - .Y ( BUF_net_106 ) ) ; -sky130_fd_sc_hd__inv_6 BINV_R_115 ( .A ( BUF_net_106 ) , .Y ( out[0] ) ) ; endmodule @@ -8067,9 +8877,13 @@ input [0:1] mem ; input [0:1] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -8081,12 +8895,18 @@ input [0:3] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -8096,12 +8916,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -8111,12 +8937,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -8184,7 +9016,7 @@ wire [0:0] mux_2level_basis_input4_mem4_2_out ; cbx_1__2__const1_14 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_1_0_ ( - .A ( mux_2level_basis_input4_mem4_2_out[0] ) , .X ( aps_rename_514_ ) ) ; + .A ( mux_2level_basis_input4_mem4_2_out[0] ) , .X ( aps_rename_513_ ) ) ; cbx_1__2__local_encoder2to4_28 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , .data ( local_encoder2to4_0_data ) , .data_inv ( local_encoder2to4_0_data_inv ) ) ; @@ -8210,9 +9042,9 @@ cbx_1__2__mux_2level_basis_input2_mem2_5 mux_l1_in_2_ ( .in ( in[8:9] ) , .mem ( local_encoder2to4_0_data[0:1] ) , .mem_inv ( local_encoder2to4_0_data_inv[0:1] ) , .out ( mux_2level_basis_input2_mem2_0_out ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_103 ( .A ( BUF_net_104 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_4 BINV_R_104 ( .A ( aps_rename_514_ ) , - .Y ( BUF_net_104 ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_92 ( .A ( BUF_net_93 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_93 ( .A ( aps_rename_513_ ) , + .Y ( BUF_net_93 ) ) ; endmodule @@ -8222,9 +9054,13 @@ input [0:1] mem ; input [0:1] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -8236,12 +9072,18 @@ input [0:3] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -8251,12 +9093,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -8266,12 +9114,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -8339,7 +9193,7 @@ wire [0:0] mux_2level_basis_input4_mem4_2_out ; cbx_1__2__const1_13 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_1_0_ ( - .A ( mux_2level_basis_input4_mem4_2_out[0] ) , .X ( aps_rename_513_ ) ) ; + .A ( mux_2level_basis_input4_mem4_2_out[0] ) , .X ( aps_rename_512_ ) ) ; cbx_1__2__local_encoder2to4_26 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , .data ( local_encoder2to4_0_data ) , .data_inv ( local_encoder2to4_0_data_inv ) ) ; @@ -8365,9 +9219,9 @@ cbx_1__2__mux_2level_basis_input2_mem2_4 mux_l1_in_2_ ( .in ( in[8:9] ) , .mem ( local_encoder2to4_0_data[0:1] ) , .mem_inv ( local_encoder2to4_0_data_inv[0:1] ) , .out ( mux_2level_basis_input2_mem2_0_out ) ) ; -sky130_fd_sc_hd__inv_2 BINV_R_102 ( .A ( aps_rename_513_ ) , - .Y ( BUF_net_102 ) ) ; -sky130_fd_sc_hd__inv_6 BINV_R_119 ( .A ( BUF_net_102 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_109 ( .A ( BUF_net_110 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_4 BINV_R_110 ( .A ( aps_rename_512_ ) , + .Y ( BUF_net_110 ) ) ; endmodule @@ -8377,9 +9231,13 @@ input [0:1] mem ; input [0:1] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -8391,12 +9249,18 @@ input [0:3] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -8406,12 +9270,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -8421,12 +9291,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -8529,9 +9405,13 @@ input [0:1] mem ; input [0:1] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -8543,12 +9423,18 @@ input [0:3] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -8558,12 +9444,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -8573,12 +9465,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -8646,7 +9544,7 @@ wire [0:0] mux_2level_basis_input4_mem4_2_out ; cbx_1__2__const1_11 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_1_0_ ( - .A ( mux_2level_basis_input4_mem4_2_out[0] ) , .X ( aps_rename_512_ ) ) ; + .A ( mux_2level_basis_input4_mem4_2_out[0] ) , .X ( out[0] ) ) ; cbx_1__2__local_encoder2to4_22 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , .data ( local_encoder2to4_0_data ) , .data_inv ( local_encoder2to4_0_data_inv ) ) ; @@ -8672,9 +9570,6 @@ cbx_1__2__mux_2level_basis_input2_mem2_2 mux_l1_in_2_ ( .in ( in[8:9] ) , .mem ( local_encoder2to4_0_data[0:1] ) , .mem_inv ( local_encoder2to4_0_data_inv[0:1] ) , .out ( mux_2level_basis_input2_mem2_0_out ) ) ; -sky130_fd_sc_hd__inv_4 BINV_R_123 ( .A ( BUF_net_124 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_4 BINV_R_124 ( .A ( aps_rename_512_ ) , - .Y ( BUF_net_124 ) ) ; endmodule @@ -8684,9 +9579,13 @@ input [0:1] mem ; input [0:1] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -8698,12 +9597,18 @@ input [0:3] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -8713,12 +9618,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -8728,12 +9639,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -8836,9 +9753,13 @@ input [0:1] mem ; input [0:1] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -8850,12 +9771,18 @@ input [0:3] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -8865,12 +9792,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -8880,12 +9813,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -8979,9 +9918,9 @@ cbx_1__2__mux_2level_basis_input2_mem2_0 mux_l1_in_2_ ( .in ( in[8:9] ) , .mem ( local_encoder2to4_0_data[0:1] ) , .mem_inv ( local_encoder2to4_0_data_inv[0:1] ) , .out ( mux_2level_basis_input2_mem2_0_out ) ) ; -sky130_fd_sc_hd__inv_2 BINV_R_98 ( .A ( aps_rename_511_ ) , - .Y ( BUF_net_98 ) ) ; -sky130_fd_sc_hd__inv_4 BINV_R_117 ( .A ( BUF_net_98 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_91 ( .A ( aps_rename_511_ ) , + .Y ( BUF_net_91 ) ) ; +sky130_fd_sc_hd__inv_4 BINV_R_98 ( .A ( BUF_net_91 ) , .Y ( out[0] ) ) ; endmodule @@ -9153,7 +10092,7 @@ input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ropt_net_146 ) , +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( copt_net_122 ) , .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; @@ -9162,26 +10101,8 @@ sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__buf_1 FTB_1__0 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1367 ( .A ( copt_net_133 ) , - .X ( copt_net_130 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1368 ( .A ( ropt_net_147 ) , - .X ( copt_net_131 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1369 ( .A ( copt_net_130 ) , - .X ( copt_net_132 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1370 ( .A ( ccff_head[0] ) , - .X ( copt_net_133 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1371 ( .A ( copt_net_131 ) , - .X ( copt_net_134 ) ) ; -sky130_fd_sc_hd__buf_1 copt_h_inst_1372 ( .A ( copt_net_132 ) , - .X ( copt_net_135 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1379 ( .A ( ropt_net_145 ) , - .X ( ropt_net_144 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1380 ( .A ( copt_net_134 ) , - .X ( ropt_net_145 ) ) ; -sky130_fd_sc_hd__buf_4 ropt_h_inst_1381 ( .A ( ropt_net_144 ) , - .X ( ropt_net_146 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1382 ( .A ( copt_net_135 ) , - .X ( ropt_net_147 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 copt_h_inst_1359 ( .A ( ccff_head[0] ) , + .X ( copt_net_122 ) ) ; endmodule @@ -9193,12 +10114,18 @@ input [0:3] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -9208,12 +10135,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -9223,12 +10156,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -9238,12 +10177,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -9311,7 +10256,7 @@ wire [0:0] mux_2level_basis_input4_mem4_3_out ; cbx_1__2__const1_8 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_1_0_ ( - .A ( mux_2level_basis_input4_mem4_3_out[0] ) , .X ( aps_rename_510_ ) ) ; + .A ( mux_2level_basis_input4_mem4_3_out[0] ) , .X ( out[0] ) ) ; cbx_1__2__local_encoder2to4_16 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , .data ( local_encoder2to4_0_data ) , .data_inv ( local_encoder2to4_0_data_inv ) ) ; @@ -9337,9 +10282,6 @@ cbx_1__2__mux_2level_basis_input4_mem4_35 mux_l2_in_0_ ( .mem ( local_encoder2to4_1_data ) , .mem_inv ( local_encoder2to4_1_data_inv ) , .out ( mux_2level_basis_input4_mem4_3_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_95 ( .A ( BUF_net_96 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_96 ( .A ( aps_rename_510_ ) , - .Y ( BUF_net_96 ) ) ; endmodule @@ -9351,12 +10293,18 @@ input [0:3] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -9366,12 +10314,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -9381,12 +10335,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -9396,12 +10356,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -9469,7 +10435,7 @@ wire [0:0] mux_2level_basis_input4_mem4_3_out ; cbx_1__2__const1_7 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_1_0_ ( - .A ( mux_2level_basis_input4_mem4_3_out[0] ) , .X ( net_net_94 ) ) ; + .A ( mux_2level_basis_input4_mem4_3_out[0] ) , .X ( aps_rename_510_ ) ) ; cbx_1__2__local_encoder2to4_14 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , .data ( local_encoder2to4_0_data ) , .data_inv ( local_encoder2to4_0_data_inv ) ) ; @@ -9495,7 +10461,9 @@ cbx_1__2__mux_2level_basis_input4_mem4_31 mux_l2_in_0_ ( .mem ( local_encoder2to4_1_data ) , .mem_inv ( local_encoder2to4_1_data_inv ) , .out ( mux_2level_basis_input4_mem4_3_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_94 ( .A ( net_net_94 ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_89 ( .A ( aps_rename_510_ ) , + .Y ( BUF_net_89 ) ) ; +sky130_fd_sc_hd__inv_4 BINV_R_113 ( .A ( BUF_net_89 ) , .Y ( out[0] ) ) ; endmodule @@ -9507,12 +10475,18 @@ input [0:3] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -9522,12 +10496,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -9537,12 +10517,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -9552,12 +10538,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -9651,9 +10643,9 @@ cbx_1__2__mux_2level_basis_input4_mem4_27 mux_l2_in_0_ ( .mem ( local_encoder2to4_1_data ) , .mem_inv ( local_encoder2to4_1_data_inv ) , .out ( mux_2level_basis_input4_mem4_3_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_2 BINV_R_93 ( .A ( aps_rename_509_ ) , - .Y ( BUF_net_93 ) ) ; -sky130_fd_sc_hd__inv_6 BINV_R_111 ( .A ( BUF_net_93 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_87 ( .A ( aps_rename_509_ ) , + .Y ( BUF_net_87 ) ) ; +sky130_fd_sc_hd__inv_4 BINV_R_111 ( .A ( BUF_net_87 ) , .Y ( out[0] ) ) ; endmodule @@ -9665,12 +10657,18 @@ input [0:3] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -9680,12 +10678,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -9695,12 +10699,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -9710,12 +10720,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -9809,9 +10825,9 @@ cbx_1__2__mux_2level_basis_input4_mem4_23 mux_l2_in_0_ ( .mem ( local_encoder2to4_1_data ) , .mem_inv ( local_encoder2to4_1_data_inv ) , .out ( mux_2level_basis_input4_mem4_3_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_2 BINV_R_91 ( .A ( aps_rename_508_ ) , - .Y ( BUF_net_91 ) ) ; -sky130_fd_sc_hd__inv_4 BINV_R_109 ( .A ( BUF_net_91 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_107 ( .A ( BUF_net_108 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_4 BINV_R_108 ( .A ( aps_rename_508_ ) , + .Y ( BUF_net_108 ) ) ; endmodule @@ -9823,12 +10839,18 @@ input [0:3] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -9838,12 +10860,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -9853,12 +10881,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -9868,12 +10902,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -9967,9 +11007,9 @@ cbx_1__2__mux_2level_basis_input4_mem4_19 mux_l2_in_0_ ( .mem ( local_encoder2to4_1_data ) , .mem_inv ( local_encoder2to4_1_data_inv ) , .out ( mux_2level_basis_input4_mem4_3_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_4 BINV_R_121 ( .A ( BUF_net_122 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_4 BINV_R_122 ( .A ( aps_rename_507_ ) , - .Y ( BUF_net_122 ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_85 ( .A ( aps_rename_507_ ) , + .Y ( BUF_net_85 ) ) ; +sky130_fd_sc_hd__inv_4 BINV_R_96 ( .A ( BUF_net_85 ) , .Y ( out[0] ) ) ; endmodule @@ -9981,12 +11021,18 @@ input [0:3] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -9996,12 +11042,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -10011,12 +11063,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -10026,12 +11084,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -10136,12 +11200,18 @@ input [0:3] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -10151,12 +11221,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -10166,12 +11242,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -10181,12 +11263,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -10280,9 +11368,9 @@ cbx_1__2__mux_2level_basis_input4_mem4_11 mux_l2_in_0_ ( .mem ( local_encoder2to4_1_data ) , .mem_inv ( local_encoder2to4_1_data_inv ) , .out ( mux_2level_basis_input4_mem4_3_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_86 ( .A ( BUF_net_87 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_87 ( .A ( aps_rename_506_ ) , - .Y ( BUF_net_87 ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_105 ( .A ( BUF_net_106 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_4 BINV_R_106 ( .A ( aps_rename_506_ ) , + .Y ( BUF_net_106 ) ) ; endmodule @@ -10294,12 +11382,18 @@ input [0:3] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -10309,12 +11403,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -10324,12 +11424,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -10339,12 +11445,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -10412,7 +11524,7 @@ wire [0:0] mux_2level_basis_input4_mem4_3_out ; cbx_1__2__const1_1 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_1_0_ ( - .A ( mux_2level_basis_input4_mem4_3_out[0] ) , .X ( out[0] ) ) ; + .A ( mux_2level_basis_input4_mem4_3_out[0] ) , .X ( aps_rename_505_ ) ) ; cbx_1__2__local_encoder2to4_2 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , .data ( local_encoder2to4_0_data ) , .data_inv ( local_encoder2to4_0_data_inv ) ) ; @@ -10438,6 +11550,9 @@ cbx_1__2__mux_2level_basis_input4_mem4_7 mux_l2_in_0_ ( .mem ( local_encoder2to4_1_data ) , .mem_inv ( local_encoder2to4_1_data_inv ) , .out ( mux_2level_basis_input4_mem4_3_out ) , .p0 ( p0 ) ) ; +sky130_fd_sc_hd__inv_12 BINV_R_103 ( .A ( BUF_net_104 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_4 BINV_R_104 ( .A ( aps_rename_505_ ) , + .Y ( BUF_net_104 ) ) ; endmodule @@ -10449,12 +11564,18 @@ input [0:3] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -10464,12 +11585,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -10479,12 +11606,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -10494,12 +11627,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -10567,7 +11706,7 @@ wire [0:0] mux_2level_basis_input4_mem4_3_out ; cbx_1__2__const1_0 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_1_0_ ( - .A ( mux_2level_basis_input4_mem4_3_out[0] ) , .X ( aps_rename_505_ ) ) ; + .A ( mux_2level_basis_input4_mem4_3_out[0] ) , .X ( out[0] ) ) ; cbx_1__2__local_encoder2to4_0 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , .data ( local_encoder2to4_0_data ) , .data_inv ( local_encoder2to4_0_data_inv ) ) ; @@ -10593,9 +11732,6 @@ cbx_1__2__mux_2level_basis_input4_mem4_3 mux_l2_in_0_ ( .mem ( local_encoder2to4_1_data ) , .mem_inv ( local_encoder2to4_1_data_inv ) , .out ( mux_2level_basis_input4_mem4_3_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_84 ( .A ( BUF_net_85 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_85 ( .A ( aps_rename_505_ ) , - .Y ( BUF_net_85 ) ) ; endmodule @@ -10702,7 +11838,7 @@ cbx_1__2__mux_2level_size12_0 mux_bottom_ipin_0 ( .sram ( mux_2level_size12_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 , SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) , - .out ( top_grid_pin_0_ ) , .p0 ( optlc_net_126 ) ) ; + .out ( top_grid_pin_0_ ) , .p0 ( optlc_net_120 ) ) ; cbx_1__2__mux_2level_size12_1 mux_top_ipin_0 ( .in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[4] , chanx_left_out[4] , chanx_right_out[7] , chanx_left_out[7] , @@ -10711,7 +11847,7 @@ cbx_1__2__mux_2level_size12_1 mux_top_ipin_0 ( .sram ( mux_2level_size12_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 , SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 } ) , - .out ( bottom_grid_pin_0_ ) , .p0 ( optlc_net_127 ) ) ; + .out ( bottom_grid_pin_0_ ) , .p0 ( optlc_net_119 ) ) ; cbx_1__2__mux_2level_size12_2 mux_top_ipin_2 ( .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[3] , chanx_left_out[3] , chanx_right_out[9] , chanx_left_out[9] , @@ -10720,7 +11856,7 @@ cbx_1__2__mux_2level_size12_2 mux_top_ipin_2 ( .sram ( mux_2level_size12_2_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_9 , SYNOPSYS_UNCONNECTED_10 , SYNOPSYS_UNCONNECTED_11 , SYNOPSYS_UNCONNECTED_12 } ) , - .out ( bottom_grid_pin_2_ ) , .p0 ( optlc_net_126 ) ) ; + .out ( bottom_grid_pin_2_ ) , .p0 ( optlc_net_118 ) ) ; cbx_1__2__mux_2level_size12_3 mux_top_ipin_4 ( .in ( { chanx_right_out[2] , chanx_left_out[2] , chanx_right_out[5] , chanx_left_out[5] , chanx_right_out[11] , chanx_left_out[11] , @@ -10729,7 +11865,7 @@ cbx_1__2__mux_2level_size12_3 mux_top_ipin_4 ( .sram ( mux_2level_size12_3_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 , SYNOPSYS_UNCONNECTED_15 , SYNOPSYS_UNCONNECTED_16 } ) , - .out ( bottom_grid_pin_4_ ) , .p0 ( optlc_net_125 ) ) ; + .out ( bottom_grid_pin_4_ ) , .p0 ( optlc_net_116 ) ) ; cbx_1__2__mux_2level_size12_4 mux_top_ipin_6 ( .in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[4] , chanx_left_out[4] , chanx_right_out[7] , chanx_left_out[7] , @@ -10738,7 +11874,7 @@ cbx_1__2__mux_2level_size12_4 mux_top_ipin_6 ( .sram ( mux_2level_size12_4_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_17 , SYNOPSYS_UNCONNECTED_18 , SYNOPSYS_UNCONNECTED_19 , SYNOPSYS_UNCONNECTED_20 } ) , - .out ( bottom_grid_pin_6_ ) , .p0 ( optlc_net_128 ) ) ; + .out ( bottom_grid_pin_6_ ) , .p0 ( optlc_net_119 ) ) ; cbx_1__2__mux_2level_size12_5 mux_top_ipin_8 ( .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[3] , chanx_left_out[3] , chanx_right_out[9] , chanx_left_out[9] , @@ -10747,8 +11883,7 @@ cbx_1__2__mux_2level_size12_5 mux_top_ipin_8 ( .sram ( mux_2level_size12_5_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_21 , SYNOPSYS_UNCONNECTED_22 , SYNOPSYS_UNCONNECTED_23 , SYNOPSYS_UNCONNECTED_24 } ) , - .out ( { ropt_net_150 } ) , - .p0 ( optlc_net_126 ) ) ; + .out ( bottom_grid_pin_8_ ) , .p0 ( optlc_net_117 ) ) ; cbx_1__2__mux_2level_size12_6 mux_top_ipin_10 ( .in ( { chanx_right_out[2] , chanx_left_out[2] , chanx_right_out[5] , chanx_left_out[5] , chanx_right_out[11] , chanx_left_out[11] , @@ -10757,7 +11892,7 @@ cbx_1__2__mux_2level_size12_6 mux_top_ipin_10 ( .sram ( mux_2level_size12_6_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_25 , SYNOPSYS_UNCONNECTED_26 , SYNOPSYS_UNCONNECTED_27 , SYNOPSYS_UNCONNECTED_28 } ) , - .out ( bottom_grid_pin_10_ ) , .p0 ( optlc_net_125 ) ) ; + .out ( bottom_grid_pin_10_ ) , .p0 ( optlc_net_116 ) ) ; cbx_1__2__mux_2level_size12_7 mux_top_ipin_12 ( .in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[4] , chanx_left_out[4] , chanx_right_out[7] , chanx_left_out[7] , @@ -10766,7 +11901,7 @@ cbx_1__2__mux_2level_size12_7 mux_top_ipin_12 ( .sram ( mux_2level_size12_7_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_29 , SYNOPSYS_UNCONNECTED_30 , SYNOPSYS_UNCONNECTED_31 , SYNOPSYS_UNCONNECTED_32 } ) , - .out ( bottom_grid_pin_12_ ) , .p0 ( optlc_net_127 ) ) ; + .out ( bottom_grid_pin_12_ ) , .p0 ( optlc_net_120 ) ) ; cbx_1__2__mux_2level_size12 mux_top_ipin_14 ( .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[3] , chanx_left_out[3] , chanx_right_out[9] , chanx_left_out[9] , @@ -10775,7 +11910,8 @@ cbx_1__2__mux_2level_size12 mux_top_ipin_14 ( .sram ( mux_2level_size12_8_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_33 , SYNOPSYS_UNCONNECTED_34 , SYNOPSYS_UNCONNECTED_35 , SYNOPSYS_UNCONNECTED_36 } ) , - .out ( bottom_grid_pin_14_ ) , .p0 ( optlc_net_126 ) ) ; + .out ( { ropt_net_123 } ) , + .p0 ( optlc_net_118 ) ) ; cbx_1__2__mux_2level_size12_mem_0 mem_bottom_ipin_0 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( mux_2level_size12_mem_0_ccff_tail ) , @@ -10828,8 +11964,7 @@ cbx_1__2__mux_2level_size10_0 mux_top_ipin_1 ( .sram ( mux_2level_size10_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_37 , SYNOPSYS_UNCONNECTED_38 , SYNOPSYS_UNCONNECTED_39 , SYNOPSYS_UNCONNECTED_40 } ) , - .out ( { ropt_net_149 } ) , - .p0 ( optlc_net_127 ) ) ; + .out ( bottom_grid_pin_1_ ) , .p0 ( optlc_net_119 ) ) ; cbx_1__2__mux_2level_size10_1 mux_top_ipin_3 ( .in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[4] , chanx_left_out[4] , chanx_right_out[10] , chanx_left_out[10] , @@ -10838,7 +11973,7 @@ cbx_1__2__mux_2level_size10_1 mux_top_ipin_3 ( .sram ( mux_2level_size10_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_41 , SYNOPSYS_UNCONNECTED_42 , SYNOPSYS_UNCONNECTED_43 , SYNOPSYS_UNCONNECTED_44 } ) , - .out ( bottom_grid_pin_3_ ) , .p0 ( optlc_net_125 ) ) ; + .out ( bottom_grid_pin_3_ ) , .p0 ( optlc_net_120 ) ) ; cbx_1__2__mux_2level_size10_2 mux_top_ipin_5 ( .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[3] , chanx_left_out[3] , chanx_right_out[6] , chanx_left_out[6] , @@ -10847,7 +11982,7 @@ cbx_1__2__mux_2level_size10_2 mux_top_ipin_5 ( .sram ( mux_2level_size10_2_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_45 , SYNOPSYS_UNCONNECTED_46 , SYNOPSYS_UNCONNECTED_47 , SYNOPSYS_UNCONNECTED_48 } ) , - .out ( bottom_grid_pin_5_ ) , .p0 ( optlc_net_128 ) ) ; + .out ( bottom_grid_pin_5_ ) , .p0 ( optlc_net_120 ) ) ; cbx_1__2__mux_2level_size10_3 mux_top_ipin_7 ( .in ( { chanx_right_out[2] , chanx_left_out[2] , chanx_right_out[5] , chanx_left_out[5] , chanx_right_out[8] , chanx_left_out[8] , @@ -10856,7 +11991,7 @@ cbx_1__2__mux_2level_size10_3 mux_top_ipin_7 ( .sram ( mux_2level_size10_3_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_49 , SYNOPSYS_UNCONNECTED_50 , SYNOPSYS_UNCONNECTED_51 , SYNOPSYS_UNCONNECTED_52 } ) , - .out ( bottom_grid_pin_7_ ) , .p0 ( optlc_net_127 ) ) ; + .out ( bottom_grid_pin_7_ ) , .p0 ( optlc_net_116 ) ) ; cbx_1__2__mux_2level_size10_4 mux_top_ipin_9 ( .in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[4] , chanx_left_out[4] , chanx_right_out[10] , chanx_left_out[10] , @@ -10865,7 +12000,7 @@ cbx_1__2__mux_2level_size10_4 mux_top_ipin_9 ( .sram ( mux_2level_size10_4_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_53 , SYNOPSYS_UNCONNECTED_54 , SYNOPSYS_UNCONNECTED_55 , SYNOPSYS_UNCONNECTED_56 } ) , - .out ( bottom_grid_pin_9_ ) , .p0 ( optlc_net_125 ) ) ; + .out ( bottom_grid_pin_9_ ) , .p0 ( optlc_net_120 ) ) ; cbx_1__2__mux_2level_size10_5 mux_top_ipin_11 ( .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[3] , chanx_left_out[3] , chanx_right_out[12] , chanx_left_out[12] , @@ -10874,8 +12009,7 @@ cbx_1__2__mux_2level_size10_5 mux_top_ipin_11 ( .sram ( mux_2level_size10_5_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_57 , SYNOPSYS_UNCONNECTED_58 , SYNOPSYS_UNCONNECTED_59 , SYNOPSYS_UNCONNECTED_60 } ) , - .out ( { ropt_net_148 } ) , - .p0 ( optlc_net_126 ) ) ; + .out ( bottom_grid_pin_11_ ) , .p0 ( optlc_net_117 ) ) ; cbx_1__2__mux_2level_size10_6 mux_top_ipin_13 ( .in ( { chanx_right_out[2] , chanx_left_out[2] , chanx_right_out[5] , chanx_left_out[5] , chanx_right_out[14] , chanx_left_out[14] , @@ -10884,7 +12018,7 @@ cbx_1__2__mux_2level_size10_6 mux_top_ipin_13 ( .sram ( mux_2level_size10_6_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_61 , SYNOPSYS_UNCONNECTED_62 , SYNOPSYS_UNCONNECTED_63 , SYNOPSYS_UNCONNECTED_64 } ) , - .out ( bottom_grid_pin_13_ ) , .p0 ( optlc_net_127 ) ) ; + .out ( bottom_grid_pin_13_ ) , .p0 ( optlc_net_119 ) ) ; cbx_1__2__mux_2level_size10 mux_top_ipin_15 ( .in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[4] , chanx_left_out[4] , chanx_right_out[7] , chanx_left_out[7] , @@ -10893,7 +12027,7 @@ cbx_1__2__mux_2level_size10 mux_top_ipin_15 ( .sram ( mux_2level_size10_7_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_65 , SYNOPSYS_UNCONNECTED_66 , SYNOPSYS_UNCONNECTED_67 , SYNOPSYS_UNCONNECTED_68 } ) , - .out ( bottom_grid_pin_15_ ) , .p0 ( optlc_net_125 ) ) ; + .out ( bottom_grid_pin_15_ ) , .p0 ( optlc_net_117 ) ) ; cbx_1__2__mux_2level_size10_mem_0 mem_top_ipin_1 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( mux_2level_size12_mem_1_ccff_tail ) , @@ -10944,16 +12078,16 @@ cbx_1__2__logical_tile_io_mode_io_ logical_tile_io_mode_io__0 ( .io_inpad ( bottom_width_0_height_0__pin_1_lower ) , .ccff_tail ( ccff_tail ) ) ; sky130_fd_sc_hd__buf_8 pReset_FTB00 ( .A ( pReset_W_in ) , .X ( pReset[0] ) ) ; -sky130_fd_sc_hd__buf_4 pReset_W_FTB01 ( .A ( pReset_W_in ) , +sky130_fd_sc_hd__bufbuf_16 pReset_W_FTB01 ( .A ( pReset_W_in ) , .X ( pReset_W_out ) ) ; -sky130_fd_sc_hd__bufbuf_16 pReset_S_FTB01 ( .A ( pReset_W_in ) , +sky130_fd_sc_hd__buf_4 pReset_S_FTB01 ( .A ( pReset_W_in ) , .X ( pReset_S_out ) ) ; -sky130_fd_sc_hd__buf_1 pReset_E_FTB01 ( .A ( pReset_W_in ) , - .X ( aps_rename_517_ ) ) ; -sky130_fd_sc_hd__buf_1 prog_clk_0_FTB00 ( .A ( prog_clk_0_S_in ) , +sky130_fd_sc_hd__buf_4 pReset_E_FTB01 ( .A ( pReset_W_in ) , + .X ( pReset_E_out ) ) ; +sky130_fd_sc_hd__buf_2 prog_clk_0_FTB00 ( .A ( prog_clk_0_S_in ) , .X ( prog_clk[0] ) ) ; sky130_fd_sc_hd__clkbuf_1 prog_clk_0_W_FTB01 ( .A ( prog_clk_0_S_in ) , - .X ( ctsbuf_net_1129 ) ) ; + .X ( ctsbuf_net_1121 ) ) ; sky130_fd_sc_hd__buf_8 FTB_19__18 ( .A ( chanx_left_in[0] ) , .X ( chanx_right_out[0] ) ) ; sky130_fd_sc_hd__buf_8 FTB_20__19 ( .A ( chanx_left_in[1] ) , @@ -11079,24 +12213,20 @@ sky130_fd_sc_hd__buf_6 FTB_79__78 ( .X ( bottom_width_0_height_0__pin_1_upper[0] ) ) ; sky130_fd_sc_hd__buf_6 FTB_80__79 ( .A ( SC_IN_TOP ) , .X ( SC_OUT_BOT ) ) ; sky130_fd_sc_hd__buf_6 FTB_81__80 ( .A ( SC_IN_BOT ) , .X ( SC_OUT_TOP ) ) ; -sky130_fd_sc_hd__conb_1 optlc_127 ( .LO ( SYNOPSYS_UNCONNECTED_69 ) , - .HI ( optlc_net_125 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_129 ( .LO ( SYNOPSYS_UNCONNECTED_70 ) , - .HI ( optlc_net_126 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_131 ( .LO ( SYNOPSYS_UNCONNECTED_71 ) , - .HI ( optlc_net_127 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_133 ( .LO ( SYNOPSYS_UNCONNECTED_72 ) , - .HI ( optlc_net_128 ) ) ; -sky130_fd_sc_hd__buf_6 ZBUF_6_f_inst_134 ( .A ( aps_rename_517_ ) , - .X ( pReset_E_out ) ) ; -sky130_fd_sc_hd__buf_6 ropt_mt_inst_1386 ( .A ( ropt_net_148 ) , - .X ( bottom_grid_pin_11_[0] ) ) ; -sky130_fd_sc_hd__buf_6 cts_buf_3651274 ( .A ( ctsbuf_net_1129 ) , +sky130_fd_sc_hd__conb_1 optlc_117 ( .LO ( SYNOPSYS_UNCONNECTED_69 ) , + .HI ( optlc_net_116 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_119 ( .LO ( SYNOPSYS_UNCONNECTED_70 ) , + .HI ( optlc_net_117 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_122 ( .LO ( SYNOPSYS_UNCONNECTED_71 ) , + .HI ( optlc_net_118 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_124 ( .LO ( SYNOPSYS_UNCONNECTED_72 ) , + .HI ( optlc_net_119 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_126 ( .LO ( SYNOPSYS_UNCONNECTED_73 ) , + .HI ( optlc_net_120 ) ) ; +sky130_fd_sc_hd__buf_6 ropt_mt_inst_1360 ( .A ( ropt_net_123 ) , + .X ( bottom_grid_pin_14_[0] ) ) ; +sky130_fd_sc_hd__buf_6 cts_buf_3651266 ( .A ( ctsbuf_net_1121 ) , .X ( prog_clk_0_W_out ) ) ; -sky130_fd_sc_hd__buf_6 ropt_mt_inst_1387 ( .A ( ropt_net_149 ) , - .X ( bottom_grid_pin_1_[0] ) ) ; -sky130_fd_sc_hd__buf_6 ropt_mt_inst_1388 ( .A ( ropt_net_150 ) , - .X ( bottom_grid_pin_8_[0] ) ) ; endmodule @@ -11108,7 +12238,7 @@ input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -wire copt_net_156 ; +wire copt_net_128 ; sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; @@ -11117,14 +12247,16 @@ sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( copt_net_156 ) ) ; + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( copt_net_128 ) ) ; sky130_fd_sc_hd__buf_6 FTB_16__15 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1394 ( .A ( copt_net_154 ) , - .X ( copt_net_152 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1395 ( .A ( copt_net_152 ) , +sky130_fd_sc_hd__buf_1 copt_h_inst_1361 ( .A ( copt_net_127 ) , .X ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1396 ( .A ( copt_net_156 ) , - .X ( copt_net_154 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1362 ( .A ( copt_net_128 ) , + .X ( copt_net_126 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1363 ( .A ( copt_net_130 ) , + .X ( copt_net_127 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1366 ( .A ( copt_net_126 ) , + .X ( copt_net_130 ) ) ; endmodule @@ -11274,9 +12406,13 @@ input [0:1] mem ; input [0:1] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -11288,12 +12424,18 @@ input [0:3] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -11303,12 +12445,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -11318,12 +12466,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -11426,9 +12580,13 @@ input [0:1] mem ; input [0:1] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -11440,12 +12598,18 @@ input [0:3] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -11455,12 +12619,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -11470,12 +12640,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -11543,7 +12719,7 @@ wire [0:0] mux_2level_basis_input4_mem4_2_out ; cbx_1__1__const1_14 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_1_0_ ( - .A ( mux_2level_basis_input4_mem4_2_out[0] ) , .X ( aps_rename_514_ ) ) ; + .A ( mux_2level_basis_input4_mem4_2_out[0] ) , .X ( net_net_90 ) ) ; cbx_1__1__local_encoder2to4_28 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , .data ( local_encoder2to4_0_data ) , .data_inv ( local_encoder2to4_0_data_inv ) ) ; @@ -11569,9 +12745,7 @@ cbx_1__1__mux_2level_basis_input2_mem2_6 mux_l1_in_2_ ( .in ( in[8:9] ) , .mem ( local_encoder2to4_0_data[0:1] ) , .mem_inv ( local_encoder2to4_0_data_inv[0:1] ) , .out ( mux_2level_basis_input2_mem2_0_out ) ) ; -sky130_fd_sc_hd__inv_6 BINV_R_139 ( .A ( BUF_net_140 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_140 ( .A ( aps_rename_514_ ) , - .Y ( BUF_net_140 ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_90 ( .A ( net_net_90 ) , .X ( out[0] ) ) ; endmodule @@ -11581,9 +12755,13 @@ input [0:1] mem ; input [0:1] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -11595,12 +12773,18 @@ input [0:3] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -11610,12 +12794,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -11625,12 +12815,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -11698,7 +12894,7 @@ wire [0:0] mux_2level_basis_input4_mem4_2_out ; cbx_1__1__const1_13 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_1_0_ ( - .A ( mux_2level_basis_input4_mem4_2_out[0] ) , .X ( aps_rename_513_ ) ) ; + .A ( mux_2level_basis_input4_mem4_2_out[0] ) , .X ( aps_rename_509_ ) ) ; cbx_1__1__local_encoder2to4_26 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , .data ( local_encoder2to4_0_data ) , .data_inv ( local_encoder2to4_0_data_inv ) ) ; @@ -11724,9 +12920,9 @@ cbx_1__1__mux_2level_basis_input2_mem2_5 mux_l1_in_2_ ( .in ( in[8:9] ) , .mem ( local_encoder2to4_0_data[0:1] ) , .mem_inv ( local_encoder2to4_0_data_inv[0:1] ) , .out ( mux_2level_basis_input2_mem2_0_out ) ) ; -sky130_fd_sc_hd__inv_6 BINV_R_137 ( .A ( BUF_net_138 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_138 ( .A ( aps_rename_513_ ) , - .Y ( BUF_net_138 ) ) ; +sky130_fd_sc_hd__inv_4 BINV_R_111 ( .A ( BUF_net_112 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_4 BINV_R_112 ( .A ( aps_rename_509_ ) , + .Y ( BUF_net_112 ) ) ; endmodule @@ -11736,9 +12932,13 @@ input [0:1] mem ; input [0:1] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -11750,12 +12950,18 @@ input [0:3] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -11765,12 +12971,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -11780,12 +12992,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -11888,9 +13106,13 @@ input [0:1] mem ; input [0:1] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -11902,12 +13124,18 @@ input [0:3] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -11917,12 +13145,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -11932,12 +13166,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -12004,7 +13244,7 @@ wire [0:0] mux_2level_basis_input4_mem4_2_out ; cbx_1__1__const1_11 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__bufbuf_16 sky130_fd_sc_hd__buf_1_0_ ( +sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_1_0_ ( .A ( mux_2level_basis_input4_mem4_2_out[0] ) , .X ( out[0] ) ) ; cbx_1__1__local_encoder2to4_22 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , .data ( local_encoder2to4_0_data ) , @@ -12040,9 +13280,13 @@ input [0:1] mem ; input [0:1] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -12054,12 +13298,18 @@ input [0:3] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -12069,12 +13319,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -12084,12 +13340,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -12156,8 +13418,8 @@ wire [0:0] mux_2level_basis_input4_mem4_2_out ; cbx_1__1__const1_10 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__bufbuf_16 sky130_fd_sc_hd__buf_1_0_ ( - .A ( mux_2level_basis_input4_mem4_2_out[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_1_0_ ( + .A ( mux_2level_basis_input4_mem4_2_out[0] ) , .X ( aps_rename_508_ ) ) ; cbx_1__1__local_encoder2to4_20 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , .data ( local_encoder2to4_0_data ) , .data_inv ( local_encoder2to4_0_data_inv ) ) ; @@ -12183,6 +13445,9 @@ cbx_1__1__mux_2level_basis_input2_mem2_2 mux_l1_in_2_ ( .in ( in[8:9] ) , .mem ( local_encoder2to4_0_data[0:1] ) , .mem_inv ( local_encoder2to4_0_data_inv[0:1] ) , .out ( mux_2level_basis_input2_mem2_0_out ) ) ; +sky130_fd_sc_hd__inv_4 BINV_R_109 ( .A ( BUF_net_110 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_4 BINV_R_110 ( .A ( aps_rename_508_ ) , + .Y ( BUF_net_110 ) ) ; endmodule @@ -12192,9 +13457,13 @@ input [0:1] mem ; input [0:1] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -12206,12 +13475,18 @@ input [0:3] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -12221,12 +13496,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -12236,12 +13517,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -12309,7 +13596,7 @@ wire [0:0] mux_2level_basis_input4_mem4_2_out ; cbx_1__1__const1_9 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_1_0_ ( - .A ( mux_2level_basis_input4_mem4_2_out[0] ) , .X ( net_net_97 ) ) ; + .A ( mux_2level_basis_input4_mem4_2_out[0] ) , .X ( out[0] ) ) ; cbx_1__1__local_encoder2to4_18 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , .data ( local_encoder2to4_0_data ) , .data_inv ( local_encoder2to4_0_data_inv ) ) ; @@ -12335,7 +13622,6 @@ cbx_1__1__mux_2level_basis_input2_mem2_1 mux_l1_in_2_ ( .in ( in[8:9] ) , .mem ( local_encoder2to4_0_data[0:1] ) , .mem_inv ( local_encoder2to4_0_data_inv[0:1] ) , .out ( mux_2level_basis_input2_mem2_0_out ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_97 ( .A ( net_net_97 ) , .X ( out[0] ) ) ; endmodule @@ -12345,9 +13631,13 @@ input [0:1] mem ; input [0:1] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -12359,12 +13649,18 @@ input [0:3] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -12374,12 +13670,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -12389,12 +13691,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -12462,7 +13770,7 @@ wire [0:0] mux_2level_basis_input4_mem4_2_out ; cbx_1__1__const1_8 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_1_0_ ( - .A ( mux_2level_basis_input4_mem4_2_out[0] ) , .X ( aps_rename_512_ ) ) ; + .A ( mux_2level_basis_input4_mem4_2_out[0] ) , .X ( out[0] ) ) ; cbx_1__1__local_encoder2to4_16 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , .data ( local_encoder2to4_0_data ) , .data_inv ( local_encoder2to4_0_data_inv ) ) ; @@ -12488,9 +13796,6 @@ cbx_1__1__mux_2level_basis_input2_mem2_0 mux_l1_in_2_ ( .in ( in[8:9] ) , .mem ( local_encoder2to4_0_data[0:1] ) , .mem_inv ( local_encoder2to4_0_data_inv[0:1] ) , .out ( mux_2level_basis_input2_mem2_0_out ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_95 ( .A ( BUF_net_96 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_96 ( .A ( aps_rename_512_ ) , - .Y ( BUF_net_96 ) ) ; endmodule @@ -12642,7 +13947,7 @@ input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ropt_net_179 ) , +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( copt_net_121 ) , .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; @@ -12651,26 +13956,20 @@ sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__buf_1 FTB_1__0 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1388 ( .A ( copt_net_147 ) , - .X ( copt_net_146 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1389 ( .A ( copt_net_149 ) , - .X ( copt_net_147 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1390 ( .A ( ropt_net_182 ) , - .X ( copt_net_148 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1391 ( .A ( ropt_net_181 ) , - .X ( copt_net_149 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1392 ( .A ( ccff_head[0] ) , - .X ( copt_net_150 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 copt_h_inst_1397 ( .A ( copt_net_146 ) , - .X ( copt_net_155 ) ) ; -sky130_fd_sc_hd__buf_1 ropt_h_inst_1420 ( .A ( copt_net_155 ) , - .X ( ropt_net_179 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1421 ( .A ( copt_net_150 ) , - .X ( ropt_net_180 ) ) ; -sky130_fd_sc_hd__buf_1 ropt_h_inst_1422 ( .A ( copt_net_148 ) , - .X ( ropt_net_181 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1423 ( .A ( ropt_net_180 ) , - .X ( ropt_net_182 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1354 ( .A ( copt_net_119 ) , + .X ( copt_net_118 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1355 ( .A ( copt_net_123 ) , + .X ( copt_net_119 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1356 ( .A ( ropt_net_139 ) , + .X ( copt_net_120 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1357 ( .A ( copt_net_122 ) , + .X ( copt_net_121 ) ) ; +sky130_fd_sc_hd__buf_2 copt_h_inst_1358 ( .A ( copt_net_120 ) , + .X ( copt_net_122 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1359 ( .A ( ccff_head[0] ) , + .X ( copt_net_123 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1376 ( .A ( copt_net_118 ) , + .X ( ropt_net_139 ) ) ; endmodule @@ -12682,12 +13981,18 @@ input [0:3] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -12697,12 +14002,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -12712,12 +14023,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -12727,12 +14044,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -12800,7 +14123,7 @@ wire [0:0] mux_2level_basis_input4_mem4_3_out ; cbx_1__1__const1_7 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_1_0_ ( - .A ( mux_2level_basis_input4_mem4_3_out[0] ) , .X ( aps_rename_511_ ) ) ; + .A ( mux_2level_basis_input4_mem4_3_out[0] ) , .X ( aps_rename_507_ ) ) ; cbx_1__1__local_encoder2to4_14 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , .data ( local_encoder2to4_0_data ) , .data_inv ( local_encoder2to4_0_data_inv ) ) ; @@ -12826,9 +14149,9 @@ cbx_1__1__mux_2level_basis_input4_mem4_31 mux_l2_in_0_ ( .mem ( local_encoder2to4_1_data ) , .mem_inv ( local_encoder2to4_1_data_inv ) , .out ( mux_2level_basis_input4_mem4_3_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_6 BINV_R_135 ( .A ( BUF_net_136 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_136 ( .A ( aps_rename_511_ ) , - .Y ( BUF_net_136 ) ) ; +sky130_fd_sc_hd__inv_4 BINV_R_84 ( .A ( BUF_net_85 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_4 BINV_R_85 ( .A ( aps_rename_507_ ) , + .Y ( BUF_net_85 ) ) ; endmodule @@ -12840,12 +14163,18 @@ input [0:3] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -12855,12 +14184,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -12870,12 +14205,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -12885,12 +14226,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -12958,7 +14305,7 @@ wire [0:0] mux_2level_basis_input4_mem4_3_out ; cbx_1__1__const1_6 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_1_0_ ( - .A ( mux_2level_basis_input4_mem4_3_out[0] ) , .X ( aps_rename_510_ ) ) ; + .A ( mux_2level_basis_input4_mem4_3_out[0] ) , .X ( aps_rename_506_ ) ) ; cbx_1__1__local_encoder2to4_12 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , .data ( local_encoder2to4_0_data ) , .data_inv ( local_encoder2to4_0_data_inv ) ) ; @@ -12984,9 +14331,9 @@ cbx_1__1__mux_2level_basis_input4_mem4_27 mux_l2_in_0_ ( .mem ( local_encoder2to4_1_data ) , .mem_inv ( local_encoder2to4_1_data_inv ) , .out ( mux_2level_basis_input4_mem4_3_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_6 BINV_R_133 ( .A ( BUF_net_134 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_134 ( .A ( aps_rename_510_ ) , - .Y ( BUF_net_134 ) ) ; +sky130_fd_sc_hd__inv_4 BINV_R_107 ( .A ( BUF_net_108 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_4 BINV_R_108 ( .A ( aps_rename_506_ ) , + .Y ( BUF_net_108 ) ) ; endmodule @@ -12998,12 +14345,18 @@ input [0:3] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -13013,12 +14366,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -13028,12 +14387,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -13043,12 +14408,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -13116,7 +14487,7 @@ wire [0:0] mux_2level_basis_input4_mem4_3_out ; cbx_1__1__const1_5 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_1_0_ ( - .A ( mux_2level_basis_input4_mem4_3_out[0] ) , .X ( aps_rename_509_ ) ) ; + .A ( mux_2level_basis_input4_mem4_3_out[0] ) , .X ( out[0] ) ) ; cbx_1__1__local_encoder2to4_10 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , .data ( local_encoder2to4_0_data ) , .data_inv ( local_encoder2to4_0_data_inv ) ) ; @@ -13142,9 +14513,6 @@ cbx_1__1__mux_2level_basis_input4_mem4_23 mux_l2_in_0_ ( .mem ( local_encoder2to4_1_data ) , .mem_inv ( local_encoder2to4_1_data_inv ) , .out ( mux_2level_basis_input4_mem4_3_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_6 BINV_R_131 ( .A ( BUF_net_132 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_132 ( .A ( aps_rename_509_ ) , - .Y ( BUF_net_132 ) ) ; endmodule @@ -13156,12 +14524,18 @@ input [0:3] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -13171,12 +14545,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -13186,12 +14566,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -13201,12 +14587,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -13274,7 +14666,7 @@ wire [0:0] mux_2level_basis_input4_mem4_3_out ; cbx_1__1__const1_4 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_1_0_ ( - .A ( mux_2level_basis_input4_mem4_3_out[0] ) , .X ( aps_rename_508_ ) ) ; + .A ( mux_2level_basis_input4_mem4_3_out[0] ) , .X ( aps_rename_505_ ) ) ; cbx_1__1__local_encoder2to4_8 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , .data ( local_encoder2to4_0_data ) , .data_inv ( local_encoder2to4_0_data_inv ) ) ; @@ -13300,9 +14692,9 @@ cbx_1__1__mux_2level_basis_input4_mem4_19 mux_l2_in_0_ ( .mem ( local_encoder2to4_1_data ) , .mem_inv ( local_encoder2to4_1_data_inv ) , .out ( mux_2level_basis_input4_mem4_3_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_6 BINV_R_129 ( .A ( BUF_net_130 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_130 ( .A ( aps_rename_508_ ) , - .Y ( BUF_net_130 ) ) ; +sky130_fd_sc_hd__inv_4 BINV_R_80 ( .A ( BUF_net_81 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_4 BINV_R_81 ( .A ( aps_rename_505_ ) , + .Y ( BUF_net_81 ) ) ; endmodule @@ -13314,12 +14706,18 @@ input [0:3] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -13329,12 +14727,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -13344,12 +14748,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -13359,12 +14769,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -13432,7 +14848,7 @@ wire [0:0] mux_2level_basis_input4_mem4_3_out ; cbx_1__1__const1_3 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_1_0_ ( - .A ( mux_2level_basis_input4_mem4_3_out[0] ) , .X ( aps_rename_507_ ) ) ; + .A ( mux_2level_basis_input4_mem4_3_out[0] ) , .X ( out[0] ) ) ; cbx_1__1__local_encoder2to4_6 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , .data ( local_encoder2to4_0_data ) , .data_inv ( local_encoder2to4_0_data_inv ) ) ; @@ -13458,9 +14874,6 @@ cbx_1__1__mux_2level_basis_input4_mem4_15 mux_l2_in_0_ ( .mem ( local_encoder2to4_1_data ) , .mem_inv ( local_encoder2to4_1_data_inv ) , .out ( mux_2level_basis_input4_mem4_3_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_85 ( .A ( BUF_net_86 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_86 ( .A ( aps_rename_507_ ) , - .Y ( BUF_net_86 ) ) ; endmodule @@ -13472,12 +14885,18 @@ input [0:3] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -13487,12 +14906,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -13502,12 +14927,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -13517,12 +14948,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -13589,8 +15026,8 @@ wire [0:0] mux_2level_basis_input4_mem4_3_out ; cbx_1__1__const1_2 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_1_0_ ( - .A ( mux_2level_basis_input4_mem4_3_out[0] ) , .X ( net_net_84 ) ) ; +sky130_fd_sc_hd__bufbuf_16 sky130_fd_sc_hd__buf_1_0_ ( + .A ( mux_2level_basis_input4_mem4_3_out[0] ) , .X ( out[0] ) ) ; cbx_1__1__local_encoder2to4_4 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , .data ( local_encoder2to4_0_data ) , .data_inv ( local_encoder2to4_0_data_inv ) ) ; @@ -13616,7 +15053,6 @@ cbx_1__1__mux_2level_basis_input4_mem4_11 mux_l2_in_0_ ( .mem ( local_encoder2to4_1_data ) , .mem_inv ( local_encoder2to4_1_data_inv ) , .out ( mux_2level_basis_input4_mem4_3_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_84 ( .A ( net_net_84 ) , .X ( out[0] ) ) ; endmodule @@ -13628,12 +15064,18 @@ input [0:3] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -13643,12 +15085,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -13658,12 +15106,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -13673,12 +15127,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -13746,7 +15206,7 @@ wire [0:0] mux_2level_basis_input4_mem4_3_out ; cbx_1__1__const1_1 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_1_0_ ( - .A ( mux_2level_basis_input4_mem4_3_out[0] ) , .X ( aps_rename_506_ ) ) ; + .A ( mux_2level_basis_input4_mem4_3_out[0] ) , .X ( out[0] ) ) ; cbx_1__1__local_encoder2to4_2 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , .data ( local_encoder2to4_0_data ) , .data_inv ( local_encoder2to4_0_data_inv ) ) ; @@ -13772,9 +15232,6 @@ cbx_1__1__mux_2level_basis_input4_mem4_7 mux_l2_in_0_ ( .mem ( local_encoder2to4_1_data ) , .mem_inv ( local_encoder2to4_1_data_inv ) , .out ( mux_2level_basis_input4_mem4_3_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_82 ( .A ( BUF_net_83 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_83 ( .A ( aps_rename_506_ ) , - .Y ( BUF_net_83 ) ) ; endmodule @@ -13786,12 +15243,18 @@ input [0:3] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -13801,12 +15264,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -13816,12 +15285,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -13831,12 +15306,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -13904,7 +15385,7 @@ wire [0:0] mux_2level_basis_input4_mem4_3_out ; cbx_1__1__const1_0 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_1_0_ ( - .A ( mux_2level_basis_input4_mem4_3_out[0] ) , .X ( aps_rename_505_ ) ) ; + .A ( mux_2level_basis_input4_mem4_3_out[0] ) , .X ( out[0] ) ) ; cbx_1__1__local_encoder2to4_0 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , .data ( local_encoder2to4_0_data ) , .data_inv ( local_encoder2to4_0_data_inv ) ) ; @@ -13930,9 +15411,6 @@ cbx_1__1__mux_2level_basis_input4_mem4_3 mux_l2_in_0_ ( .mem ( local_encoder2to4_1_data ) , .mem_inv ( local_encoder2to4_1_data_inv ) , .out ( mux_2level_basis_input4_mem4_3_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_6 BINV_R_127 ( .A ( BUF_net_128 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_128 ( .A ( aps_rename_505_ ) , - .Y ( BUF_net_128 ) ) ; endmodule @@ -14016,9 +15494,11 @@ input clk_3_E_in ; output clk_3_E_out ; output clk_3_W_out ; -wire ropt_net_175 ; -wire ropt_net_166 ; -wire ropt_net_168 ; +wire ropt_net_132 ; +wire ropt_net_134 ; +wire ropt_net_133 ; +wire ropt_net_135 ; +wire ropt_net_136 ; wire [0:0] prog_clk ; wire prog_clk_0 ; wire [0:3] mux_2level_size10_0_sram ; @@ -14070,7 +15550,8 @@ cbx_1__1__mux_2level_size12_0 mux_top_ipin_0 ( .sram ( mux_2level_size12_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 , SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) , - .out ( bottom_grid_pin_0_ ) , .p0 ( optlc_net_143 ) ) ; + .out ( { ropt_net_140 } ) , + .p0 ( optlc_net_113 ) ) ; cbx_1__1__mux_2level_size12_1 mux_top_ipin_2 ( .in ( { chanx_right_out[2] , chanx_left_out[2] , chanx_right_out[5] , chanx_left_out[5] , chanx_right_out[8] , chanx_left_out[8] , @@ -14079,7 +15560,7 @@ cbx_1__1__mux_2level_size12_1 mux_top_ipin_2 ( .sram ( mux_2level_size12_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 , SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 } ) , - .out ( bottom_grid_pin_2_ ) , .p0 ( optlc_net_144 ) ) ; + .out ( bottom_grid_pin_2_ ) , .p0 ( optlc_net_115 ) ) ; cbx_1__1__mux_2level_size12_2 mux_top_ipin_4 ( .in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[4] , chanx_left_out[4] , chanx_right_out[10] , chanx_left_out[10] , @@ -14088,7 +15569,7 @@ cbx_1__1__mux_2level_size12_2 mux_top_ipin_4 ( .sram ( mux_2level_size12_2_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_9 , SYNOPSYS_UNCONNECTED_10 , SYNOPSYS_UNCONNECTED_11 , SYNOPSYS_UNCONNECTED_12 } ) , - .out ( bottom_grid_pin_4_ ) , .p0 ( optlc_net_141 ) ) ; + .out ( bottom_grid_pin_4_ ) , .p0 ( optlc_net_113 ) ) ; cbx_1__1__mux_2level_size12_3 mux_top_ipin_6 ( .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[3] , chanx_left_out[3] , chanx_right_out[6] , chanx_left_out[6] , @@ -14097,7 +15578,7 @@ cbx_1__1__mux_2level_size12_3 mux_top_ipin_6 ( .sram ( mux_2level_size12_3_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 , SYNOPSYS_UNCONNECTED_15 , SYNOPSYS_UNCONNECTED_16 } ) , - .out ( bottom_grid_pin_6_ ) , .p0 ( optlc_net_143 ) ) ; + .out ( bottom_grid_pin_6_ ) , .p0 ( optlc_net_115 ) ) ; cbx_1__1__mux_2level_size12_4 mux_top_ipin_8 ( .in ( { chanx_right_out[2] , chanx_left_out[2] , chanx_right_out[5] , chanx_left_out[5] , chanx_right_out[8] , chanx_left_out[8] , @@ -14106,7 +15587,7 @@ cbx_1__1__mux_2level_size12_4 mux_top_ipin_8 ( .sram ( mux_2level_size12_4_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_17 , SYNOPSYS_UNCONNECTED_18 , SYNOPSYS_UNCONNECTED_19 , SYNOPSYS_UNCONNECTED_20 } ) , - .out ( bottom_grid_pin_8_ ) , .p0 ( optlc_net_142 ) ) ; + .out ( bottom_grid_pin_8_ ) , .p0 ( optlc_net_116 ) ) ; cbx_1__1__mux_2level_size12_5 mux_top_ipin_10 ( .in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[4] , chanx_left_out[4] , chanx_right_out[10] , chanx_left_out[10] , @@ -14115,7 +15596,7 @@ cbx_1__1__mux_2level_size12_5 mux_top_ipin_10 ( .sram ( mux_2level_size12_5_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_21 , SYNOPSYS_UNCONNECTED_22 , SYNOPSYS_UNCONNECTED_23 , SYNOPSYS_UNCONNECTED_24 } ) , - .out ( bottom_grid_pin_10_ ) , .p0 ( optlc_net_141 ) ) ; + .out ( bottom_grid_pin_10_ ) , .p0 ( optlc_net_116 ) ) ; cbx_1__1__mux_2level_size12_6 mux_top_ipin_12 ( .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[3] , chanx_left_out[3] , chanx_right_out[6] , chanx_left_out[6] , @@ -14124,7 +15605,7 @@ cbx_1__1__mux_2level_size12_6 mux_top_ipin_12 ( .sram ( mux_2level_size12_6_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_25 , SYNOPSYS_UNCONNECTED_26 , SYNOPSYS_UNCONNECTED_27 , SYNOPSYS_UNCONNECTED_28 } ) , - .out ( bottom_grid_pin_12_ ) , .p0 ( optlc_net_141 ) ) ; + .out ( bottom_grid_pin_12_ ) , .p0 ( optlc_net_114 ) ) ; cbx_1__1__mux_2level_size12 mux_top_ipin_14 ( .in ( { chanx_right_out[2] , chanx_left_out[2] , chanx_right_out[5] , chanx_left_out[5] , chanx_right_out[8] , chanx_left_out[8] , @@ -14133,7 +15614,7 @@ cbx_1__1__mux_2level_size12 mux_top_ipin_14 ( .sram ( mux_2level_size12_7_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_29 , SYNOPSYS_UNCONNECTED_30 , SYNOPSYS_UNCONNECTED_31 , SYNOPSYS_UNCONNECTED_32 } ) , - .out ( bottom_grid_pin_14_ ) , .p0 ( optlc_net_144 ) ) ; + .out ( bottom_grid_pin_14_ ) , .p0 ( optlc_net_115 ) ) ; cbx_1__1__mux_2level_size12_mem_0 mem_top_ipin_0 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( mux_2level_size12_mem_0_ccff_tail ) , @@ -14181,7 +15662,7 @@ cbx_1__1__mux_2level_size10_0 mux_top_ipin_1 ( .sram ( mux_2level_size10_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_33 , SYNOPSYS_UNCONNECTED_34 , SYNOPSYS_UNCONNECTED_35 , SYNOPSYS_UNCONNECTED_36 } ) , - .out ( bottom_grid_pin_1_ ) , .p0 ( optlc_net_143 ) ) ; + .out ( bottom_grid_pin_1_ ) , .p0 ( optlc_net_113 ) ) ; cbx_1__1__mux_2level_size10_1 mux_top_ipin_3 ( .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[3] , chanx_left_out[3] , chanx_right_out[9] , chanx_left_out[9] , @@ -14190,7 +15671,8 @@ cbx_1__1__mux_2level_size10_1 mux_top_ipin_3 ( .sram ( mux_2level_size10_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_37 , SYNOPSYS_UNCONNECTED_38 , SYNOPSYS_UNCONNECTED_39 , SYNOPSYS_UNCONNECTED_40 } ) , - .out ( bottom_grid_pin_3_ ) , .p0 ( optlc_net_143 ) ) ; + .out ( { ropt_net_131 } ) , + .p0 ( optlc_net_113 ) ) ; cbx_1__1__mux_2level_size10_2 mux_top_ipin_5 ( .in ( { chanx_right_out[2] , chanx_left_out[2] , chanx_right_out[5] , chanx_left_out[5] , chanx_right_out[11] , chanx_left_out[11] , @@ -14199,7 +15681,7 @@ cbx_1__1__mux_2level_size10_2 mux_top_ipin_5 ( .sram ( mux_2level_size10_2_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_41 , SYNOPSYS_UNCONNECTED_42 , SYNOPSYS_UNCONNECTED_43 , SYNOPSYS_UNCONNECTED_44 } ) , - .out ( bottom_grid_pin_5_ ) , .p0 ( optlc_net_141 ) ) ; + .out ( bottom_grid_pin_5_ ) , .p0 ( optlc_net_115 ) ) ; cbx_1__1__mux_2level_size10_3 mux_top_ipin_7 ( .in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[4] , chanx_left_out[4] , chanx_right_out[7] , chanx_left_out[7] , @@ -14208,7 +15690,7 @@ cbx_1__1__mux_2level_size10_3 mux_top_ipin_7 ( .sram ( mux_2level_size10_3_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_45 , SYNOPSYS_UNCONNECTED_46 , SYNOPSYS_UNCONNECTED_47 , SYNOPSYS_UNCONNECTED_48 } ) , - .out ( bottom_grid_pin_7_ ) , .p0 ( optlc_net_142 ) ) ; + .out ( bottom_grid_pin_7_ ) , .p0 ( optlc_net_116 ) ) ; cbx_1__1__mux_2level_size10_4 mux_top_ipin_9 ( .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[3] , chanx_left_out[3] , chanx_right_out[9] , chanx_left_out[9] , @@ -14217,8 +15699,7 @@ cbx_1__1__mux_2level_size10_4 mux_top_ipin_9 ( .sram ( mux_2level_size10_4_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_49 , SYNOPSYS_UNCONNECTED_50 , SYNOPSYS_UNCONNECTED_51 , SYNOPSYS_UNCONNECTED_52 } ) , - .out ( { ZBUF_4_f_0 } ) , - .p0 ( optlc_net_144 ) ) ; + .out ( bottom_grid_pin_9_ ) , .p0 ( optlc_net_113 ) ) ; cbx_1__1__mux_2level_size10_5 mux_top_ipin_11 ( .in ( { chanx_right_out[2] , chanx_left_out[2] , chanx_right_out[5] , chanx_left_out[5] , chanx_right_out[11] , chanx_left_out[11] , @@ -14227,7 +15708,7 @@ cbx_1__1__mux_2level_size10_5 mux_top_ipin_11 ( .sram ( mux_2level_size10_5_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_53 , SYNOPSYS_UNCONNECTED_54 , SYNOPSYS_UNCONNECTED_55 , SYNOPSYS_UNCONNECTED_56 } ) , - .out ( bottom_grid_pin_11_ ) , .p0 ( optlc_net_142 ) ) ; + .out ( bottom_grid_pin_11_ ) , .p0 ( optlc_net_114 ) ) ; cbx_1__1__mux_2level_size10_6 mux_top_ipin_13 ( .in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[4] , chanx_left_out[4] , chanx_right_out[13] , chanx_left_out[13] , @@ -14236,7 +15717,7 @@ cbx_1__1__mux_2level_size10_6 mux_top_ipin_13 ( .sram ( mux_2level_size10_6_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_57 , SYNOPSYS_UNCONNECTED_58 , SYNOPSYS_UNCONNECTED_59 , SYNOPSYS_UNCONNECTED_60 } ) , - .out ( bottom_grid_pin_13_ ) , .p0 ( optlc_net_142 ) ) ; + .out ( bottom_grid_pin_13_ ) , .p0 ( optlc_net_116 ) ) ; cbx_1__1__mux_2level_size10 mux_top_ipin_15 ( .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[3] , chanx_left_out[3] , chanx_right_out[6] , chanx_left_out[6] , @@ -14245,8 +15726,7 @@ cbx_1__1__mux_2level_size10 mux_top_ipin_15 ( .sram ( mux_2level_size10_7_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_61 , SYNOPSYS_UNCONNECTED_62 , SYNOPSYS_UNCONNECTED_63 , SYNOPSYS_UNCONNECTED_64 } ) , - .out ( { ZBUF_4_f_1 } ) , - .p0 ( optlc_net_143 ) ) ; + .out ( bottom_grid_pin_15_ ) , .p0 ( optlc_net_113 ) ) ; cbx_1__1__mux_2level_size10_mem_0 mem_top_ipin_1 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( mux_2level_size12_mem_0_ccff_tail ) , @@ -14288,37 +15768,36 @@ cbx_1__1__mux_2level_size10_mem mem_top_ipin_15 ( .pReset ( pReset ) , .ccff_tail ( ccff_tail ) , .mem_out ( mux_2level_size10_7_sram ) ) ; sky130_fd_sc_hd__buf_8 pReset_FTB00 ( .A ( pReset_W_in ) , .X ( pReset[0] ) ) ; sky130_fd_sc_hd__buf_4 pReset_W_FTB01 ( .A ( pReset_W_in ) , - .X ( ZBUF_39_1 ) ) ; -sky130_fd_sc_hd__buf_4 pReset_S_FTB01 ( .A ( pReset_W_in ) , - .X ( aps_rename_515_ ) ) ; -sky130_fd_sc_hd__buf_1 pReset_E_FTB01 ( .A ( pReset_W_in ) , - .X ( aps_rename_516_ ) ) ; + .X ( pReset_W_out ) ) ; +sky130_fd_sc_hd__buf_1 pReset_S_FTB01 ( .A ( pReset_W_in ) , + .X ( aps_rename_510_ ) ) ; +sky130_fd_sc_hd__buf_4 pReset_E_FTB01 ( .A ( pReset_W_in ) , + .X ( pReset_E_out ) ) ; sky130_fd_sc_hd__buf_1 prog_clk_0_FTB00 ( .A ( prog_clk_0_N_in ) , .X ( prog_clk[0] ) ) ; sky130_fd_sc_hd__clkbuf_1 prog_clk_0_W_FTB01 ( .A ( prog_clk_0_N_in ) , - .X ( ctsbuf_net_1145 ) ) ; -sky130_fd_sc_hd__bufbuf_16 prog_clk_1_N_FTB01 ( .A ( prog_clk_1_E_in ) , - .X ( prog_clk_1_N_out ) ) ; + .X ( ctsbuf_net_1117 ) ) ; +sky130_fd_sc_hd__buf_1 prog_clk_1_N_FTB01 ( .A ( prog_clk_1_E_in ) , + .X ( aps_rename_511_ ) ) ; sky130_fd_sc_hd__buf_1 prog_clk_1_S_FTB01 ( .A ( prog_clk_1_E_in ) , - .X ( aps_rename_517_ ) ) ; + .X ( net_net_95 ) ) ; sky130_fd_sc_hd__bufbuf_16 prog_clk_2_W_FTB01 ( .A ( prog_clk_2_W_in ) , .X ( prog_clk_2_W_out ) ) ; -sky130_fd_sc_hd__buf_1 prog_clk_2_E_FTB01 ( .A ( prog_clk_2_W_in ) , - .X ( aps_rename_518_ ) ) ; -sky130_fd_sc_hd__buf_1 prog_clk_3_E_FTB01 ( .A ( prog_clk_3_E_in ) , - .X ( aps_rename_519_ ) ) ; +sky130_fd_sc_hd__buf_4 prog_clk_2_E_FTB01 ( .A ( prog_clk_2_W_in ) , + .X ( prog_clk_2_E_out ) ) ; +sky130_fd_sc_hd__buf_4 prog_clk_3_E_FTB01 ( .A ( prog_clk_3_E_in ) , + .X ( prog_clk_3_E_out ) ) ; sky130_fd_sc_hd__bufbuf_16 prog_clk_3_W_FTB01 ( .A ( prog_clk_3_E_in ) , .X ( prog_clk_3_W_out ) ) ; -sky130_fd_sc_hd__buf_1 clk_1_N_FTB01 ( .A ( clk_1_E_in ) , - .X ( aps_rename_520_ ) ) ; +sky130_fd_sc_hd__bufbuf_16 clk_1_N_FTB01 ( .A ( clk_1_E_in ) , + .X ( clk_1_N_out ) ) ; sky130_fd_sc_hd__buf_1 clk_1_S_FTB01 ( .A ( clk_1_E_in ) , - .X ( aps_rename_521_ ) ) ; + .X ( aps_rename_512_ ) ) ; sky130_fd_sc_hd__bufbuf_16 clk_2_W_FTB01 ( .A ( clk_2_W_in ) , .X ( clk_2_W_out ) ) ; -sky130_fd_sc_hd__buf_1 clk_2_E_FTB01 ( .A ( clk_2_W_in ) , - .X ( net_net_112 ) ) ; -sky130_fd_sc_hd__buf_1 clk_3_E_FTB01 ( .A ( clk_3_E_in ) , - .X ( aps_rename_522_ ) ) ; +sky130_fd_sc_hd__buf_4 clk_2_E_FTB01 ( .A ( clk_2_W_in ) , + .X ( clk_2_E_out ) ) ; +sky130_fd_sc_hd__buf_1 clk_3_E_FTB01 ( .A ( clk_3_E_in ) , .X ( net_net_98 ) ) ; sky130_fd_sc_hd__bufbuf_16 clk_3_W_FTB01 ( .A ( clk_3_E_in ) , .X ( clk_3_W_out ) ) ; sky130_fd_sc_hd__buf_8 FTB_17__16 ( .A ( chanx_left_in[0] ) , @@ -14368,7 +15847,7 @@ sky130_fd_sc_hd__buf_8 FTB_38__37 ( .A ( chanx_left_in[21] ) , sky130_fd_sc_hd__buf_8 FTB_39__38 ( .A ( chanx_left_in[22] ) , .X ( chanx_right_out[22] ) ) ; sky130_fd_sc_hd__buf_1 FTB_40__39 ( .A ( chanx_left_in[23] ) , - .X ( ropt_net_175 ) ) ; + .X ( ropt_net_132 ) ) ; sky130_fd_sc_hd__buf_8 FTB_41__40 ( .A ( chanx_left_in[24] ) , .X ( chanx_right_out[24] ) ) ; sky130_fd_sc_hd__buf_8 FTB_42__41 ( .A ( chanx_left_in[25] ) , @@ -14427,8 +15906,8 @@ sky130_fd_sc_hd__buf_8 FTB_68__67 ( .A ( chanx_right_in[21] ) , .X ( chanx_left_out[21] ) ) ; sky130_fd_sc_hd__buf_8 FTB_69__68 ( .A ( chanx_right_in[22] ) , .X ( chanx_left_out[22] ) ) ; -sky130_fd_sc_hd__buf_1 FTB_70__69 ( .A ( chanx_right_in[23] ) , - .X ( ropt_net_166 ) ) ; +sky130_fd_sc_hd__buf_6 FTB_70__69 ( .A ( chanx_right_in[23] ) , + .X ( ropt_net_134 ) ) ; sky130_fd_sc_hd__buf_8 FTB_71__70 ( .A ( chanx_right_in[24] ) , .X ( chanx_left_out[24] ) ) ; sky130_fd_sc_hd__buf_8 FTB_72__71 ( .A ( chanx_right_in[25] ) , @@ -14441,58 +15920,49 @@ sky130_fd_sc_hd__buf_8 FTB_75__74 ( .A ( chanx_right_in[28] ) , .X ( chanx_left_out[28] ) ) ; sky130_fd_sc_hd__buf_8 FTB_76__75 ( .A ( chanx_right_in[29] ) , .X ( chanx_left_out[29] ) ) ; -sky130_fd_sc_hd__buf_8 FTB_77__76 ( .A ( SC_IN_TOP ) , .X ( SC_OUT_BOT ) ) ; -sky130_fd_sc_hd__buf_6 FTB_78__77 ( .A ( SC_IN_BOT ) , .X ( ropt_net_168 ) ) ; -sky130_fd_sc_hd__buf_8 FTB_79__78 ( .A ( REGIN_FEEDTHROUGH ) , - .X ( REGOUT_FEEDTHROUGH ) ) ; -sky130_fd_sc_hd__buf_8 FTB_80__79 ( .A ( CIN_FEEDTHROUGH ) , - .X ( COUT_FEEDTHROUGH ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_102 ( .A ( BUF_net_103 ) , .Y ( pReset_E_out ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_103 ( .A ( aps_rename_516_ ) , - .Y ( BUF_net_103 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_104 ( .A ( BUF_net_105 ) , - .Y ( prog_clk_1_S_out ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_105 ( .A ( aps_rename_517_ ) , - .Y ( BUF_net_105 ) ) ; -sky130_fd_sc_hd__inv_6 BINV_R_106 ( .A ( BUF_net_107 ) , - .Y ( prog_clk_3_E_out ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_107 ( .A ( aps_rename_519_ ) , - .Y ( BUF_net_107 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_108 ( .A ( BUF_net_109 ) , .Y ( clk_1_N_out ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_109 ( .A ( aps_rename_520_ ) , - .Y ( BUF_net_109 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_110 ( .A ( BUF_net_111 ) , .Y ( clk_1_S_out ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_111 ( .A ( aps_rename_521_ ) , - .Y ( BUF_net_111 ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_112 ( .A ( net_net_112 ) , .X ( clk_2_E_out ) ) ; -sky130_fd_sc_hd__conb_1 optlc_143 ( .LO ( SYNOPSYS_UNCONNECTED_65 ) , - .HI ( optlc_net_141 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_145 ( .LO ( SYNOPSYS_UNCONNECTED_66 ) , - .HI ( optlc_net_142 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_147 ( .LO ( SYNOPSYS_UNCONNECTED_67 ) , - .HI ( optlc_net_143 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_149 ( .LO ( SYNOPSYS_UNCONNECTED_68 ) , - .HI ( optlc_net_144 ) ) ; -sky130_fd_sc_hd__buf_6 ZBUF_6_f_inst_150 ( .A ( aps_rename_518_ ) , - .X ( prog_clk_2_E_out ) ) ; -sky130_fd_sc_hd__buf_6 ZBUF_6_f_inst_151 ( .A ( aps_rename_522_ ) , - .X ( clk_3_E_out ) ) ; -sky130_fd_sc_hd__buf_6 ZBUF_6_f_inst_656 ( .A ( aps_rename_515_ ) , - .X ( pReset_S_out ) ) ; -sky130_fd_sc_hd__buf_6 ZBUF_4_f_inst_1385 ( .A ( ZBUF_4_f_0 ) , - .X ( bottom_grid_pin_9_[0] ) ) ; -sky130_fd_sc_hd__clkbuf_8 cts_buf_3651292 ( .A ( ctsbuf_net_1145 ) , +sky130_fd_sc_hd__buf_6 FTB_77__76 ( .A ( SC_IN_TOP ) , .X ( SC_OUT_BOT ) ) ; +sky130_fd_sc_hd__buf_1 FTB_78__77 ( .A ( SC_IN_BOT ) , .X ( ropt_net_133 ) ) ; +sky130_fd_sc_hd__buf_6 FTB_79__78 ( .A ( REGIN_FEEDTHROUGH ) , + .X ( ropt_net_135 ) ) ; +sky130_fd_sc_hd__buf_6 FTB_80__79 ( .A ( CIN_FEEDTHROUGH ) , + .X ( ropt_net_136 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_115 ( .LO ( SYNOPSYS_UNCONNECTED_65 ) , + .HI ( optlc_net_113 ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_92 ( .A ( aps_rename_510_ ) , + .Y ( BUF_net_92 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_93 ( .A ( BUF_net_94 ) , + .Y ( prog_clk_1_N_out ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_94 ( .A ( aps_rename_511_ ) , + .Y ( BUF_net_94 ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_95 ( .A ( net_net_95 ) , + .X ( prog_clk_1_S_out ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_96 ( .A ( BUF_net_97 ) , .Y ( clk_1_S_out ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_97 ( .A ( aps_rename_512_ ) , + .Y ( BUF_net_97 ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_98 ( .A ( net_net_98 ) , .X ( clk_3_E_out ) ) ; +sky130_fd_sc_hd__inv_4 BINV_R_105 ( .A ( BUF_net_92 ) , .Y ( pReset_S_out ) ) ; +sky130_fd_sc_hd__conb_1 optlc_117 ( .LO ( SYNOPSYS_UNCONNECTED_66 ) , + .HI ( optlc_net_114 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_119 ( .LO ( SYNOPSYS_UNCONNECTED_67 ) , + .HI ( optlc_net_115 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_121 ( .LO ( SYNOPSYS_UNCONNECTED_68 ) , + .HI ( optlc_net_116 ) ) ; +sky130_fd_sc_hd__buf_6 ropt_mt_inst_1367 ( .A ( ropt_net_131 ) , + .X ( bottom_grid_pin_3_[0] ) ) ; +sky130_fd_sc_hd__buf_6 cts_buf_3651261 ( .A ( ctsbuf_net_1117 ) , .X ( prog_clk_0_W_out ) ) ; -sky130_fd_sc_hd__buf_6 ZBUF_4_f_inst_1386 ( .A ( ZBUF_4_f_1 ) , - .X ( bottom_grid_pin_15_[0] ) ) ; -sky130_fd_sc_hd__buf_6 ZBUF_39_inst_1387 ( .A ( ZBUF_39_1 ) , - .X ( pReset_W_out ) ) ; -sky130_fd_sc_hd__buf_6 ropt_mt_inst_1417 ( .A ( ropt_net_175 ) , +sky130_fd_sc_hd__buf_6 ropt_mt_inst_1371 ( .A ( ropt_net_132 ) , .X ( chanx_right_out[23] ) ) ; -sky130_fd_sc_hd__buf_6 ropt_mt_inst_1408 ( .A ( ropt_net_166 ) , - .X ( chanx_left_out[23] ) ) ; -sky130_fd_sc_hd__buf_6 ropt_mt_inst_1410 ( .A ( ropt_net_168 ) , +sky130_fd_sc_hd__buf_6 ropt_mt_inst_1372 ( .A ( ropt_net_133 ) , .X ( SC_OUT_TOP ) ) ; +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1373 ( .A ( ropt_net_134 ) , + .X ( chanx_left_out[23] ) ) ; +sky130_fd_sc_hd__buf_6 ropt_mt_inst_1374 ( .A ( ropt_net_135 ) , + .X ( REGOUT_FEEDTHROUGH ) ) ; +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1375 ( .A ( ropt_net_136 ) , + .X ( COUT_FEEDTHROUGH ) ) ; +sky130_fd_sc_hd__buf_6 ropt_mt_inst_1377 ( .A ( ropt_net_140 ) , + .X ( bottom_grid_pin_0_[0] ) ) ; endmodule @@ -14504,21 +15974,21 @@ input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:0] mem_out ; -wire copt_net_156 ; +wire copt_net_148 ; sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( copt_net_156 ) ) ; + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( copt_net_148 ) ) ; sky130_fd_sc_hd__buf_6 FTB_18__17 ( .A ( mem_out[0] ) , .X ( ccff_tail[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1389 ( .A ( copt_net_156 ) , - .X ( copt_net_152 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1390 ( .A ( copt_net_152 ) , - .X ( copt_net_153 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1391 ( .A ( copt_net_153 ) , - .X ( copt_net_154 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1392 ( .A ( copt_net_154 ) , - .X ( copt_net_155 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1393 ( .A ( copt_net_155 ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1383 ( .A ( copt_net_149 ) , .X ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1384 ( .A ( copt_net_150 ) , + .X ( copt_net_149 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1385 ( .A ( copt_net_151 ) , + .X ( copt_net_150 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1386 ( .A ( copt_net_152 ) , + .X ( copt_net_151 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1387 ( .A ( copt_net_148 ) , + .X ( copt_net_152 ) ) ; endmodule @@ -14532,17 +16002,17 @@ input FPGA_OUT ; input FPGA_DIR ; input IO_ISOL_N ; -sky130_fd_sc_hd__nand2b_1 ISOL_EN_GATE ( .A_N ( FPGA_DIR ) , - .B ( IO_ISOL_N ) , .Y ( aps_rename_518_ ) ) ; +sky130_fd_sc_hd__or2b_4 ISOL_EN_GATE ( .A ( FPGA_DIR ) , .B_N ( IO_ISOL_N ) , + .X ( aps_rename_517_ ) ) ; sky130_fd_sc_hd__inv_1 INV_SOC_DIR ( .A ( BUF_net_117 ) , .Y ( SOC_DIR_N ) ) ; sky130_fd_sc_hd__ebufn_4 IN_PROTECT_GATE ( .A ( SOC_IN ) , .TE_B ( SOC_DIR_N ) , .Z ( FPGA_IN ) ) ; sky130_fd_sc_hd__ebufn_4 OUT_PROTECT_GATE ( .A ( FPGA_OUT ) , - .TE_B ( BUF_net_117 ) , .Z ( SOC_OUT ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_116 ( .A ( BUF_net_118 ) , .Y ( SOC_DIR ) ) ; -sky130_fd_sc_hd__inv_4 BINV_R_117 ( .A ( BUF_net_118 ) , .Y ( BUF_net_117 ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_118 ( .A ( aps_rename_518_ ) , + .TE_B ( aps_rename_517_ ) , .Z ( SOC_OUT ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_115 ( .A ( BUF_net_118 ) , .Y ( SOC_DIR ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_118 ( .A ( aps_rename_517_ ) , .Y ( BUF_net_118 ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_117 ( .A ( BUF_net_118 ) , .Y ( BUF_net_117 ) ) ; endmodule @@ -14625,17 +16095,15 @@ input FPGA_DIR ; input IO_ISOL_N ; sky130_fd_sc_hd__nand2b_1 ISOL_EN_GATE ( .A_N ( FPGA_DIR ) , - .B ( IO_ISOL_N ) , .Y ( aps_rename_517_ ) ) ; -sky130_fd_sc_hd__inv_1 INV_SOC_DIR ( .A ( aps_rename_517_ ) , - .Y ( SOC_DIR_N ) ) ; + .B ( IO_ISOL_N ) , .Y ( aps_rename_516_ ) ) ; sky130_fd_sc_hd__ebufn_4 IN_PROTECT_GATE ( .A ( SOC_IN ) , - .TE_B ( SOC_DIR_N ) , .Z ( FPGA_IN ) ) ; + .TE_B ( BUF_net_114 ) , .Z ( FPGA_IN ) ) ; sky130_fd_sc_hd__ebufn_4 OUT_PROTECT_GATE ( .A ( FPGA_OUT ) , - .TE_B ( BUF_net_113 ) , .Z ( SOC_OUT ) ) ; -sky130_fd_sc_hd__inv_4 BINV_R_113 ( .A ( BUF_net_115 ) , .Y ( BUF_net_113 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_114 ( .A ( BUF_net_115 ) , .Y ( SOC_DIR ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_115 ( .A ( aps_rename_517_ ) , - .Y ( BUF_net_115 ) ) ; + .TE_B ( BUF_net_111 ) , .Z ( SOC_OUT ) ) ; +sky130_fd_sc_hd__inv_4 BINV_R_111 ( .A ( BUF_net_114 ) , .Y ( BUF_net_111 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_113 ( .A ( BUF_net_114 ) , .Y ( SOC_DIR ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_114 ( .A ( aps_rename_516_ ) , + .Y ( BUF_net_114 ) ) ; endmodule @@ -14718,19 +16186,16 @@ input FPGA_DIR ; input IO_ISOL_N ; sky130_fd_sc_hd__nand2b_1 ISOL_EN_GATE ( .A_N ( FPGA_DIR ) , - .B ( IO_ISOL_N ) , .Y ( aps_rename_516_ ) ) ; -sky130_fd_sc_hd__inv_1 INV_SOC_DIR ( .A ( aps_rename_516_ ) , - .Y ( SOC_DIR_N ) ) ; + .B ( IO_ISOL_N ) , .Y ( aps_rename_515_ ) ) ; +sky130_fd_sc_hd__inv_1 INV_SOC_DIR ( .A ( BUF_net_108 ) , .Y ( SOC_DIR_N ) ) ; sky130_fd_sc_hd__ebufn_4 IN_PROTECT_GATE ( .A ( SOC_IN ) , .TE_B ( SOC_DIR_N ) , .Z ( FPGA_IN ) ) ; sky130_fd_sc_hd__ebufn_4 OUT_PROTECT_GATE ( .A ( FPGA_OUT ) , - .TE_B ( BUF_net_110 ) , .Z ( SOC_OUT ) ) ; -sky130_fd_sc_hd__inv_4 BINV_R_110 ( .A ( BUF_net_112 ) , .Y ( BUF_net_110 ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_112 ( .A ( aps_rename_516_ ) , - .Y ( BUF_net_112 ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_131 ( .A ( BUF_net_112 ) , .Y ( BUF_net_131 ) ) ; -sky130_fd_sc_hd__inv_6 BINV_R_137 ( .A ( BUF_net_138 ) , .Y ( SOC_DIR ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_138 ( .A ( BUF_net_131 ) , .Y ( BUF_net_138 ) ) ; + .TE_B ( BUF_net_108 ) , .Z ( SOC_OUT ) ) ; +sky130_fd_sc_hd__inv_4 BINV_R_108 ( .A ( BUF_net_110 ) , .Y ( BUF_net_108 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_109 ( .A ( BUF_net_110 ) , .Y ( SOC_DIR ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_110 ( .A ( aps_rename_515_ ) , + .Y ( BUF_net_110 ) ) ; endmodule @@ -14813,14 +16278,16 @@ input FPGA_DIR ; input IO_ISOL_N ; sky130_fd_sc_hd__or2b_4 ISOL_EN_GATE ( .A ( FPGA_DIR ) , .B_N ( IO_ISOL_N ) , - .X ( aps_rename_515_ ) ) ; + .X ( aps_rename_514_ ) ) ; +sky130_fd_sc_hd__inv_1 INV_SOC_DIR ( .A ( aps_rename_514_ ) , + .Y ( SOC_DIR_N ) ) ; sky130_fd_sc_hd__ebufn_4 IN_PROTECT_GATE ( .A ( SOC_IN ) , - .TE_B ( BUF_net_109 ) , .Z ( FPGA_IN ) ) ; + .TE_B ( SOC_DIR_N ) , .Z ( FPGA_IN ) ) ; sky130_fd_sc_hd__ebufn_4 OUT_PROTECT_GATE ( .A ( FPGA_OUT ) , - .TE_B ( aps_rename_515_ ) , .Z ( SOC_OUT ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_107 ( .A ( BUF_net_109 ) , .Y ( SOC_DIR ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_109 ( .A ( aps_rename_515_ ) , - .Y ( BUF_net_109 ) ) ; + .TE_B ( aps_rename_514_ ) , .Z ( SOC_OUT ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_106 ( .A ( BUF_net_107 ) , .Y ( SOC_DIR ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_107 ( .A ( aps_rename_514_ ) , + .Y ( BUF_net_107 ) ) ; endmodule @@ -14902,17 +16369,16 @@ input FPGA_OUT ; input FPGA_DIR ; input IO_ISOL_N ; -sky130_fd_sc_hd__or2b_4 ISOL_EN_GATE ( .A ( FPGA_DIR ) , .B_N ( IO_ISOL_N ) , - .X ( aps_rename_514_ ) ) ; -sky130_fd_sc_hd__inv_1 INV_SOC_DIR ( .A ( aps_rename_514_ ) , - .Y ( SOC_DIR_N ) ) ; +sky130_fd_sc_hd__nand2b_1 ISOL_EN_GATE ( .A_N ( FPGA_DIR ) , + .B ( IO_ISOL_N ) , .Y ( aps_rename_513_ ) ) ; sky130_fd_sc_hd__ebufn_4 IN_PROTECT_GATE ( .A ( SOC_IN ) , - .TE_B ( SOC_DIR_N ) , .Z ( FPGA_IN ) ) ; + .TE_B ( BUF_net_105 ) , .Z ( FPGA_IN ) ) ; sky130_fd_sc_hd__ebufn_4 OUT_PROTECT_GATE ( .A ( FPGA_OUT ) , - .TE_B ( aps_rename_514_ ) , .Z ( SOC_OUT ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_103 ( .A ( BUF_net_106 ) , .Y ( SOC_DIR ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_106 ( .A ( aps_rename_514_ ) , - .Y ( BUF_net_106 ) ) ; + .TE_B ( BUF_net_103 ) , .Z ( SOC_OUT ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_102 ( .A ( BUF_net_105 ) , .Y ( SOC_DIR ) ) ; +sky130_fd_sc_hd__inv_4 BINV_R_103 ( .A ( BUF_net_105 ) , .Y ( BUF_net_103 ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_105 ( .A ( aps_rename_513_ ) , + .Y ( BUF_net_105 ) ) ; endmodule @@ -14995,15 +16461,17 @@ input FPGA_DIR ; input IO_ISOL_N ; sky130_fd_sc_hd__nand2b_1 ISOL_EN_GATE ( .A_N ( FPGA_DIR ) , - .B ( IO_ISOL_N ) , .Y ( aps_rename_513_ ) ) ; + .B ( IO_ISOL_N ) , .Y ( aps_rename_512_ ) ) ; +sky130_fd_sc_hd__inv_1 INV_SOC_DIR ( .A ( aps_rename_512_ ) , + .Y ( SOC_DIR_N ) ) ; sky130_fd_sc_hd__ebufn_4 IN_PROTECT_GATE ( .A ( SOC_IN ) , - .TE_B ( BUF_net_102 ) , .Z ( FPGA_IN ) ) ; + .TE_B ( SOC_DIR_N ) , .Z ( FPGA_IN ) ) ; sky130_fd_sc_hd__ebufn_4 OUT_PROTECT_GATE ( .A ( FPGA_OUT ) , - .TE_B ( BUF_net_99 ) , .Z ( SOC_OUT ) ) ; -sky130_fd_sc_hd__inv_4 BINV_R_99 ( .A ( BUF_net_102 ) , .Y ( BUF_net_99 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_101 ( .A ( BUF_net_102 ) , .Y ( SOC_DIR ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_102 ( .A ( aps_rename_513_ ) , - .Y ( BUF_net_102 ) ) ; + .TE_B ( BUF_net_100 ) , .Z ( SOC_OUT ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_98 ( .A ( BUF_net_101 ) , .Y ( SOC_DIR ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_101 ( .A ( aps_rename_512_ ) , + .Y ( BUF_net_101 ) ) ; +sky130_fd_sc_hd__inv_4 BINV_R_100 ( .A ( BUF_net_101 ) , .Y ( BUF_net_100 ) ) ; endmodule @@ -15085,18 +16553,17 @@ input FPGA_OUT ; input FPGA_DIR ; input IO_ISOL_N ; -sky130_fd_sc_hd__nand2b_1 ISOL_EN_GATE ( .A_N ( FPGA_DIR ) , - .B ( IO_ISOL_N ) , .Y ( aps_rename_512_ ) ) ; -sky130_fd_sc_hd__inv_1 INV_SOC_DIR ( .A ( aps_rename_512_ ) , - .Y ( SOC_DIR_N ) ) ; +sky130_fd_sc_hd__or2b_4 ISOL_EN_GATE ( .A ( FPGA_DIR ) , .B_N ( IO_ISOL_N ) , + .X ( aps_rename_511_ ) ) ; +sky130_fd_sc_hd__inv_1 INV_SOC_DIR ( .A ( BUF_net_95 ) , .Y ( SOC_DIR_N ) ) ; sky130_fd_sc_hd__ebufn_4 IN_PROTECT_GATE ( .A ( SOC_IN ) , .TE_B ( SOC_DIR_N ) , .Z ( FPGA_IN ) ) ; sky130_fd_sc_hd__ebufn_4 OUT_PROTECT_GATE ( .A ( FPGA_OUT ) , - .TE_B ( BUF_net_96 ) , .Z ( SOC_OUT ) ) ; -sky130_fd_sc_hd__inv_4 BINV_R_96 ( .A ( BUF_net_98 ) , .Y ( BUF_net_96 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_97 ( .A ( BUF_net_98 ) , .Y ( SOC_DIR ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_98 ( .A ( aps_rename_512_ ) , - .Y ( BUF_net_98 ) ) ; + .TE_B ( aps_rename_511_ ) , .Z ( SOC_OUT ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_95 ( .A ( BUF_net_97 ) , .Y ( BUF_net_95 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_96 ( .A ( BUF_net_97 ) , .Y ( SOC_DIR ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_97 ( .A ( aps_rename_511_ ) , + .Y ( BUF_net_97 ) ) ; endmodule @@ -15179,16 +16646,16 @@ input FPGA_DIR ; input IO_ISOL_N ; sky130_fd_sc_hd__nand2b_1 ISOL_EN_GATE ( .A_N ( FPGA_DIR ) , - .B ( IO_ISOL_N ) , .Y ( aps_rename_511_ ) ) ; + .B ( IO_ISOL_N ) , .Y ( aps_rename_510_ ) ) ; sky130_fd_sc_hd__inv_1 INV_SOC_DIR ( .A ( BUF_net_93 ) , .Y ( SOC_DIR_N ) ) ; sky130_fd_sc_hd__ebufn_4 IN_PROTECT_GATE ( .A ( SOC_IN ) , .TE_B ( SOC_DIR_N ) , .Z ( FPGA_IN ) ) ; sky130_fd_sc_hd__ebufn_4 OUT_PROTECT_GATE ( .A ( FPGA_OUT ) , .TE_B ( BUF_net_93 ) , .Z ( SOC_OUT ) ) ; -sky130_fd_sc_hd__inv_4 BINV_R_93 ( .A ( BUF_net_95 ) , .Y ( BUF_net_93 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_94 ( .A ( BUF_net_95 ) , .Y ( SOC_DIR ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_95 ( .A ( aps_rename_511_ ) , - .Y ( BUF_net_95 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_92 ( .A ( BUF_net_94 ) , .Y ( SOC_DIR ) ) ; +sky130_fd_sc_hd__inv_4 BINV_R_93 ( .A ( BUF_net_94 ) , .Y ( BUF_net_93 ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_94 ( .A ( aps_rename_510_ ) , + .Y ( BUF_net_94 ) ) ; endmodule @@ -15271,14 +16738,14 @@ input FPGA_DIR ; input IO_ISOL_N ; sky130_fd_sc_hd__or2b_4 ISOL_EN_GATE ( .A ( FPGA_DIR ) , .B_N ( IO_ISOL_N ) , - .X ( aps_rename_510_ ) ) ; + .X ( aps_rename_509_ ) ) ; sky130_fd_sc_hd__ebufn_4 IN_PROTECT_GATE ( .A ( SOC_IN ) , - .TE_B ( BUF_net_92 ) , .Z ( FPGA_IN ) ) ; + .TE_B ( BUF_net_91 ) , .Z ( FPGA_IN ) ) ; sky130_fd_sc_hd__ebufn_4 OUT_PROTECT_GATE ( .A ( FPGA_OUT ) , - .TE_B ( aps_rename_510_ ) , .Z ( SOC_OUT ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_89 ( .A ( BUF_net_92 ) , .Y ( SOC_DIR ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_92 ( .A ( aps_rename_510_ ) , - .Y ( BUF_net_92 ) ) ; + .TE_B ( aps_rename_509_ ) , .Z ( SOC_OUT ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_90 ( .A ( BUF_net_91 ) , .Y ( SOC_DIR ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_91 ( .A ( aps_rename_509_ ) , + .Y ( BUF_net_91 ) ) ; endmodule @@ -15504,7 +16971,7 @@ input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ropt_net_160 ) , +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ropt_net_155 ) , .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; @@ -15513,20 +16980,20 @@ sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__buf_1 FTB_1__0 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1382 ( .A ( ccff_head[0] ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1376 ( .A ( copt_net_142 ) , + .X ( copt_net_141 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1377 ( .A ( copt_net_143 ) , + .X ( copt_net_142 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1378 ( .A ( ccff_head[0] ) , + .X ( copt_net_143 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1379 ( .A ( copt_net_141 ) , + .X ( copt_net_144 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1380 ( .A ( copt_net_146 ) , .X ( copt_net_145 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1383 ( .A ( copt_net_145 ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1381 ( .A ( copt_net_144 ) , .X ( copt_net_146 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1384 ( .A ( copt_net_146 ) , - .X ( copt_net_147 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1385 ( .A ( copt_net_147 ) , - .X ( copt_net_148 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1386 ( .A ( copt_net_148 ) , - .X ( copt_net_149 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1387 ( .A ( copt_net_149 ) , - .X ( copt_net_150 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1395 ( .A ( copt_net_150 ) , - .X ( ropt_net_160 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1389 ( .A ( copt_net_145 ) , + .X ( ropt_net_155 ) ) ; endmodule @@ -15538,12 +17005,18 @@ input [0:3] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -15553,12 +17026,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -15568,12 +17047,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -15583,12 +17068,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -15693,12 +17184,18 @@ input [0:3] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -15708,12 +17205,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -15723,12 +17226,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -15738,12 +17247,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -15811,7 +17326,7 @@ wire [0:0] mux_2level_basis_input4_mem4_3_out ; cbx_1__0__const1_7 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_1_0_ ( - .A ( mux_2level_basis_input4_mem4_3_out[0] ) , .X ( aps_rename_509_ ) ) ; + .A ( mux_2level_basis_input4_mem4_3_out[0] ) , .X ( out[0] ) ) ; cbx_1__0__local_encoder2to4_14 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , .data ( local_encoder2to4_0_data ) , .data_inv ( local_encoder2to4_0_data_inv ) ) ; @@ -15837,9 +17352,6 @@ cbx_1__0__mux_2level_basis_input4_mem4_31 mux_l2_in_0_ ( .mem ( local_encoder2to4_1_data ) , .mem_inv ( local_encoder2to4_1_data_inv ) , .out ( mux_2level_basis_input4_mem4_3_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_127 ( .A ( BUF_net_128 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_128 ( .A ( aps_rename_509_ ) , - .Y ( BUF_net_128 ) ) ; endmodule @@ -15851,12 +17363,18 @@ input [0:3] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -15866,12 +17384,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -15881,12 +17405,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -15896,12 +17426,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -15969,7 +17505,7 @@ wire [0:0] mux_2level_basis_input4_mem4_3_out ; cbx_1__0__const1_6 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_1_0_ ( - .A ( mux_2level_basis_input4_mem4_3_out[0] ) , .X ( out[0] ) ) ; + .A ( mux_2level_basis_input4_mem4_3_out[0] ) , .X ( aps_rename_508_ ) ) ; cbx_1__0__local_encoder2to4_12 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , .data ( local_encoder2to4_0_data ) , .data_inv ( local_encoder2to4_0_data_inv ) ) ; @@ -15995,6 +17531,9 @@ cbx_1__0__mux_2level_basis_input4_mem4_27 mux_l2_in_0_ ( .mem ( local_encoder2to4_1_data ) , .mem_inv ( local_encoder2to4_1_data_inv ) , .out ( mux_2level_basis_input4_mem4_3_out ) , .p0 ( p0 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_125 ( .A ( BUF_net_126 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_126 ( .A ( aps_rename_508_ ) , + .Y ( BUF_net_126 ) ) ; endmodule @@ -16006,12 +17545,18 @@ input [0:3] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -16021,12 +17566,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -16036,12 +17587,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -16051,12 +17608,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -16124,7 +17687,7 @@ wire [0:0] mux_2level_basis_input4_mem4_3_out ; cbx_1__0__const1_5 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_1_0_ ( - .A ( mux_2level_basis_input4_mem4_3_out[0] ) , .X ( out[0] ) ) ; + .A ( mux_2level_basis_input4_mem4_3_out[0] ) , .X ( aps_rename_507_ ) ) ; cbx_1__0__local_encoder2to4_10 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , .data ( local_encoder2to4_0_data ) , .data_inv ( local_encoder2to4_0_data_inv ) ) ; @@ -16150,6 +17713,9 @@ cbx_1__0__mux_2level_basis_input4_mem4_23 mux_l2_in_0_ ( .mem ( local_encoder2to4_1_data ) , .mem_inv ( local_encoder2to4_1_data_inv ) , .out ( mux_2level_basis_input4_mem4_3_out ) , .p0 ( p0 ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_123 ( .A ( BUF_net_124 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_124 ( .A ( aps_rename_507_ ) , + .Y ( BUF_net_124 ) ) ; endmodule @@ -16161,12 +17727,18 @@ input [0:3] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -16176,12 +17748,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -16191,12 +17769,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -16206,12 +17790,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -16278,8 +17868,8 @@ wire [0:0] mux_2level_basis_input4_mem4_3_out ; cbx_1__0__const1_4 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_1_0_ ( - .A ( mux_2level_basis_input4_mem4_3_out[0] ) , .X ( aps_rename_508_ ) ) ; +sky130_fd_sc_hd__bufbuf_16 sky130_fd_sc_hd__buf_1_0_ ( + .A ( mux_2level_basis_input4_mem4_3_out[0] ) , .X ( out[0] ) ) ; cbx_1__0__local_encoder2to4_8 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , .data ( local_encoder2to4_0_data ) , .data_inv ( local_encoder2to4_0_data_inv ) ) ; @@ -16305,9 +17895,6 @@ cbx_1__0__mux_2level_basis_input4_mem4_19 mux_l2_in_0_ ( .mem ( local_encoder2to4_1_data ) , .mem_inv ( local_encoder2to4_1_data_inv ) , .out ( mux_2level_basis_input4_mem4_3_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_125 ( .A ( BUF_net_126 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_126 ( .A ( aps_rename_508_ ) , - .Y ( BUF_net_126 ) ) ; endmodule @@ -16319,12 +17906,18 @@ input [0:3] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -16334,12 +17927,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -16349,12 +17948,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -16364,12 +17969,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -16437,7 +18048,7 @@ wire [0:0] mux_2level_basis_input4_mem4_3_out ; cbx_1__0__const1_3 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_1_0_ ( - .A ( mux_2level_basis_input4_mem4_3_out[0] ) , .X ( out[0] ) ) ; + .A ( mux_2level_basis_input4_mem4_3_out[0] ) , .X ( aps_rename_506_ ) ) ; cbx_1__0__local_encoder2to4_6 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , .data ( local_encoder2to4_0_data ) , .data_inv ( local_encoder2to4_0_data_inv ) ) ; @@ -16463,6 +18074,9 @@ cbx_1__0__mux_2level_basis_input4_mem4_15 mux_l2_in_0_ ( .mem ( local_encoder2to4_1_data ) , .mem_inv ( local_encoder2to4_1_data_inv ) , .out ( mux_2level_basis_input4_mem4_3_out ) , .p0 ( p0 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_121 ( .A ( BUF_net_122 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_122 ( .A ( aps_rename_506_ ) , + .Y ( BUF_net_122 ) ) ; endmodule @@ -16474,12 +18088,18 @@ input [0:3] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -16489,12 +18109,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -16504,12 +18130,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -16519,12 +18151,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -16591,8 +18229,8 @@ wire [0:0] mux_2level_basis_input4_mem4_3_out ; cbx_1__0__const1_2 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_1_0_ ( - .A ( mux_2level_basis_input4_mem4_3_out[0] ) , .X ( aps_rename_507_ ) ) ; +sky130_fd_sc_hd__bufbuf_16 sky130_fd_sc_hd__buf_1_0_ ( + .A ( mux_2level_basis_input4_mem4_3_out[0] ) , .X ( out[0] ) ) ; cbx_1__0__local_encoder2to4_4 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , .data ( local_encoder2to4_0_data ) , .data_inv ( local_encoder2to4_0_data_inv ) ) ; @@ -16618,9 +18256,6 @@ cbx_1__0__mux_2level_basis_input4_mem4_11 mux_l2_in_0_ ( .mem ( local_encoder2to4_1_data ) , .mem_inv ( local_encoder2to4_1_data_inv ) , .out ( mux_2level_basis_input4_mem4_3_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_124 ( .A ( aps_rename_507_ ) , - .Y ( BUF_net_124 ) ) ; -sky130_fd_sc_hd__inv_6 BINV_R_133 ( .A ( BUF_net_124 ) , .Y ( out[0] ) ) ; endmodule @@ -16632,12 +18267,18 @@ input [0:3] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -16647,12 +18288,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -16662,12 +18309,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -16677,12 +18330,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -16750,7 +18409,7 @@ wire [0:0] mux_2level_basis_input4_mem4_3_out ; cbx_1__0__const1_1 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_1_0_ ( - .A ( mux_2level_basis_input4_mem4_3_out[0] ) , .X ( aps_rename_506_ ) ) ; + .A ( mux_2level_basis_input4_mem4_3_out[0] ) , .X ( aps_rename_505_ ) ) ; cbx_1__0__local_encoder2to4_2 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , .data ( local_encoder2to4_0_data ) , .data_inv ( local_encoder2to4_0_data_inv ) ) ; @@ -16776,9 +18435,9 @@ cbx_1__0__mux_2level_basis_input4_mem4_7 mux_l2_in_0_ ( .mem ( local_encoder2to4_1_data ) , .mem_inv ( local_encoder2to4_1_data_inv ) , .out ( mux_2level_basis_input4_mem4_3_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_6 BINV_R_121 ( .A ( BUF_net_122 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_122 ( .A ( aps_rename_506_ ) , - .Y ( BUF_net_122 ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_120 ( .A ( aps_rename_505_ ) , + .Y ( BUF_net_120 ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_130 ( .A ( BUF_net_120 ) , .Y ( out[0] ) ) ; endmodule @@ -16790,12 +18449,18 @@ input [0:3] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -16805,12 +18470,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -16820,12 +18491,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -16835,12 +18512,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -16907,8 +18590,8 @@ wire [0:0] mux_2level_basis_input4_mem4_3_out ; cbx_1__0__const1_0 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_1_0_ ( - .A ( mux_2level_basis_input4_mem4_3_out[0] ) , .X ( aps_rename_505_ ) ) ; +sky130_fd_sc_hd__bufbuf_16 sky130_fd_sc_hd__buf_1_0_ ( + .A ( mux_2level_basis_input4_mem4_3_out[0] ) , .X ( out[0] ) ) ; cbx_1__0__local_encoder2to4_0 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , .data ( local_encoder2to4_0_data ) , .data_inv ( local_encoder2to4_0_data_inv ) ) ; @@ -16934,9 +18617,6 @@ cbx_1__0__mux_2level_basis_input4_mem4_3 mux_l2_in_0_ ( .mem ( local_encoder2to4_1_data ) , .mem_inv ( local_encoder2to4_1_data_inv ) , .out ( mux_2level_basis_input4_mem4_3_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_119 ( .A ( BUF_net_120 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_120 ( .A ( aps_rename_505_ ) , - .Y ( BUF_net_120 ) ) ; endmodule @@ -17060,7 +18740,7 @@ cbx_1__0__mux_2level_size12_0 mux_top_ipin_0 ( .sram ( mux_2level_size12_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 , SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) , - .out ( bottom_grid_pin_0_ ) , .p0 ( optlc_net_142 ) ) ; + .out ( bottom_grid_pin_0_ ) , .p0 ( optlc_net_136 ) ) ; cbx_1__0__mux_2level_size12_1 mux_top_ipin_1 ( .in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[4] , chanx_left_out[4] , chanx_right_out[7] , chanx_left_out[7] , @@ -17069,7 +18749,7 @@ cbx_1__0__mux_2level_size12_1 mux_top_ipin_1 ( .sram ( mux_2level_size12_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 , SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 } ) , - .out ( bottom_grid_pin_2_ ) , .p0 ( optlc_net_143 ) ) ; + .out ( bottom_grid_pin_2_ ) , .p0 ( optlc_net_136 ) ) ; cbx_1__0__mux_2level_size12_2 mux_top_ipin_2 ( .in ( { chanx_right_out[2] , chanx_left_out[2] , chanx_right_out[5] , chanx_left_out[5] , chanx_right_out[8] , chanx_left_out[8] , @@ -17078,7 +18758,7 @@ cbx_1__0__mux_2level_size12_2 mux_top_ipin_2 ( .sram ( mux_2level_size12_2_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_9 , SYNOPSYS_UNCONNECTED_10 , SYNOPSYS_UNCONNECTED_11 , SYNOPSYS_UNCONNECTED_12 } ) , - .out ( bottom_grid_pin_4_ ) , .p0 ( optlc_net_143 ) ) ; + .out ( bottom_grid_pin_4_ ) , .p0 ( optlc_net_138 ) ) ; cbx_1__0__mux_2level_size12_3 mux_top_ipin_3 ( .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[3] , chanx_left_out[3] , chanx_right_out[9] , chanx_left_out[9] , @@ -17087,8 +18767,7 @@ cbx_1__0__mux_2level_size12_3 mux_top_ipin_3 ( .sram ( mux_2level_size12_3_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 , SYNOPSYS_UNCONNECTED_15 , SYNOPSYS_UNCONNECTED_16 } ) , - .out ( { aps_rename_519_ } ) , - .p0 ( optlc_net_141 ) ) ; + .out ( bottom_grid_pin_6_ ) , .p0 ( optlc_net_139 ) ) ; cbx_1__0__mux_2level_size12_4 mux_top_ipin_4 ( .in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[4] , chanx_left_out[4] , chanx_right_out[10] , chanx_left_out[10] , @@ -17097,7 +18776,7 @@ cbx_1__0__mux_2level_size12_4 mux_top_ipin_4 ( .sram ( mux_2level_size12_4_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_17 , SYNOPSYS_UNCONNECTED_18 , SYNOPSYS_UNCONNECTED_19 , SYNOPSYS_UNCONNECTED_20 } ) , - .out ( bottom_grid_pin_8_ ) , .p0 ( optlc_net_141 ) ) ; + .out ( bottom_grid_pin_8_ ) , .p0 ( optlc_net_138 ) ) ; cbx_1__0__mux_2level_size12_5 mux_top_ipin_5 ( .in ( { chanx_right_out[2] , chanx_left_out[2] , chanx_right_out[5] , chanx_left_out[5] , chanx_right_out[11] , chanx_left_out[11] , @@ -17106,8 +18785,7 @@ cbx_1__0__mux_2level_size12_5 mux_top_ipin_5 ( .sram ( mux_2level_size12_5_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_21 , SYNOPSYS_UNCONNECTED_22 , SYNOPSYS_UNCONNECTED_23 , SYNOPSYS_UNCONNECTED_24 } ) , - .out ( { aps_rename_520_ } ) , - .p0 ( optlc_net_142 ) ) ; + .out ( bottom_grid_pin_10_ ) , .p0 ( optlc_net_138 ) ) ; cbx_1__0__mux_2level_size12_6 mux_top_ipin_6 ( .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[3] , chanx_left_out[3] , chanx_right_out[6] , chanx_left_out[6] , @@ -17116,8 +18794,7 @@ cbx_1__0__mux_2level_size12_6 mux_top_ipin_6 ( .sram ( mux_2level_size12_6_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_25 , SYNOPSYS_UNCONNECTED_26 , SYNOPSYS_UNCONNECTED_27 , SYNOPSYS_UNCONNECTED_28 } ) , - .out ( { aps_rename_521_ } ) , - .p0 ( optlc_net_143 ) ) ; + .out ( bottom_grid_pin_12_ ) , .p0 ( optlc_net_138 ) ) ; cbx_1__0__mux_2level_size12_7 mux_top_ipin_7 ( .in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[4] , chanx_left_out[4] , chanx_right_out[7] , chanx_left_out[7] , @@ -17126,7 +18803,8 @@ cbx_1__0__mux_2level_size12_7 mux_top_ipin_7 ( .sram ( mux_2level_size12_7_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_29 , SYNOPSYS_UNCONNECTED_30 , SYNOPSYS_UNCONNECTED_31 , SYNOPSYS_UNCONNECTED_32 } ) , - .out ( bottom_grid_pin_14_ ) , .p0 ( optlc_net_141 ) ) ; + .out ( { aps_rename_518_ } ) , + .p0 ( optlc_net_136 ) ) ; cbx_1__0__mux_2level_size12 mux_top_ipin_8 ( .in ( { chanx_right_out[2] , chanx_left_out[2] , chanx_right_out[5] , chanx_left_out[5] , chanx_right_out[8] , chanx_left_out[8] , @@ -17135,7 +18813,7 @@ cbx_1__0__mux_2level_size12 mux_top_ipin_8 ( .sram ( mux_2level_size12_8_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_33 , SYNOPSYS_UNCONNECTED_34 , SYNOPSYS_UNCONNECTED_35 , SYNOPSYS_UNCONNECTED_36 } ) , - .out ( bottom_grid_pin_16_ ) , .p0 ( optlc_net_142 ) ) ; + .out ( bottom_grid_pin_16_ ) , .p0 ( optlc_net_137 ) ) ; cbx_1__0__mux_2level_size12_mem_0 mem_top_ipin_0 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( mux_2level_size12_mem_0_ccff_tail ) , @@ -17263,13 +18941,13 @@ cbx_1__0__logical_tile_io_mode_io_ logical_tile_io_mode_io__8 ( .ccff_tail ( ccff_tail ) ) ; sky130_fd_sc_hd__buf_8 pReset_FTB00 ( .A ( pReset_W_in ) , .X ( pReset[0] ) ) ; sky130_fd_sc_hd__buf_1 pReset_W_FTB01 ( .A ( pReset_W_in ) , - .X ( aps_rename_522_ ) ) ; -sky130_fd_sc_hd__bufbuf_16 pReset_E_FTB01 ( .A ( pReset_W_in ) , - .X ( pReset_E_out ) ) ; + .X ( aps_rename_519_ ) ) ; +sky130_fd_sc_hd__buf_1 pReset_E_FTB01 ( .A ( pReset_W_in ) , + .X ( net_net_129 ) ) ; sky130_fd_sc_hd__buf_1 prog_clk_0_FTB00 ( .A ( prog_clk_0_N_in ) , .X ( prog_clk[0] ) ) ; sky130_fd_sc_hd__clkbuf_1 prog_clk_0_W_FTB01 ( .A ( prog_clk_0_N_in ) , - .X ( ctsbuf_net_1144 ) ) ; + .X ( ctsbuf_net_1140 ) ) ; sky130_fd_sc_hd__buf_8 FTB_19__18 ( .A ( chanx_left_in[0] ) , .X ( chanx_right_out[0] ) ) ; sky130_fd_sc_hd__buf_8 FTB_20__19 ( .A ( chanx_left_in[1] ) , @@ -17419,22 +19097,22 @@ sky130_fd_sc_hd__buf_6 FTB_87__86 ( .X ( top_width_0_height_0__pin_17_upper[0] ) ) ; sky130_fd_sc_hd__buf_6 FTB_88__87 ( .A ( SC_IN_TOP ) , .X ( SC_OUT_BOT ) ) ; sky130_fd_sc_hd__buf_6 FTB_89__88 ( .A ( SC_IN_BOT ) , .X ( SC_OUT_TOP ) ) ; -sky130_fd_sc_hd__conb_1 optlc_142 ( .LO ( SYNOPSYS_UNCONNECTED_37 ) , - .HI ( optlc_net_141 ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_130 ( .A ( aps_rename_522_ ) , - .Y ( BUF_net_130 ) ) ; -sky130_fd_sc_hd__inv_6 BINV_R_135 ( .A ( BUF_net_130 ) , .Y ( pReset_W_out ) ) ; -sky130_fd_sc_hd__conb_1 optlc_144 ( .LO ( SYNOPSYS_UNCONNECTED_38 ) , - .HI ( optlc_net_142 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_146 ( .LO ( SYNOPSYS_UNCONNECTED_39 ) , - .HI ( optlc_net_143 ) ) ; -sky130_fd_sc_hd__buf_6 ZBUF_6_f_inst_147 ( .A ( aps_rename_521_ ) , - .X ( bottom_grid_pin_12_[0] ) ) ; -sky130_fd_sc_hd__buf_6 ZBUF_6_f_inst_148 ( .A ( aps_rename_519_ ) , - .X ( bottom_grid_pin_6_[0] ) ) ; -sky130_fd_sc_hd__buf_6 ZBUF_6_f_inst_149 ( .A ( aps_rename_520_ ) , - .X ( bottom_grid_pin_10_[0] ) ) ; -sky130_fd_sc_hd__buf_6 cts_buf_3651289 ( .A ( ctsbuf_net_1144 ) , +sky130_fd_sc_hd__conb_1 optlc_138 ( .LO ( SYNOPSYS_UNCONNECTED_37 ) , + .HI ( optlc_net_136 ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_128 ( .A ( aps_rename_519_ ) , + .Y ( BUF_net_128 ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_129 ( .A ( net_net_129 ) , + .X ( pReset_E_out ) ) ; +sky130_fd_sc_hd__conb_1 optlc_139 ( .LO ( SYNOPSYS_UNCONNECTED_38 ) , + .HI ( optlc_net_137 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_141 ( .LO ( SYNOPSYS_UNCONNECTED_39 ) , + .HI ( optlc_net_138 ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_134 ( .A ( BUF_net_128 ) , .Y ( pReset_W_out ) ) ; +sky130_fd_sc_hd__conb_1 optlc_142 ( .LO ( SYNOPSYS_UNCONNECTED_40 ) , + .HI ( optlc_net_139 ) ) ; +sky130_fd_sc_hd__buf_6 ZBUF_6_f_inst_143 ( .A ( aps_rename_518_ ) , + .X ( bottom_grid_pin_14_[0] ) ) ; +sky130_fd_sc_hd__clkbuf_8 cts_buf_3651283 ( .A ( ctsbuf_net_1140 ) , .X ( prog_clk_0_W_out ) ) ; endmodule @@ -17510,7 +19188,7 @@ input [0:0] mem ; input [0:0] mem_inv ; output [0:0] out ; -sky130_fd_sc_hd__mux2_2 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) , +sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ; endmodule @@ -17558,8 +19236,6 @@ wire [0:0] mux_2level_tapbuf_basis_input2_mem1_2_out ; sb_2__2__const1 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( mux_2level_tapbuf_basis_input2_mem1_2_out[0] ) , .X ( out[0] ) ) ; sb_2__2__mux_2level_tapbuf_basis_input2_mem1_83 mux_l1_in_0_ ( .in ( in[0:1] ) , .mem ( sram[0] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_2 } ) , @@ -17575,6 +19251,9 @@ sb_2__2__mux_2level_tapbuf_basis_input2_mem1 mux_l2_in_0_ ( .mem ( sram[1] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_5 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_2_out ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_158 ( .A ( BUF_net_159 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_159 ( + .A ( mux_2level_tapbuf_basis_input2_mem1_2_out[0] ) , .Y ( BUF_net_159 ) ) ; endmodule @@ -17585,7 +19264,7 @@ input [0:0] mem ; input [0:0] mem_inv ; output [0:0] out ; -sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) , +sky130_fd_sc_hd__mux2_2 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ; endmodule @@ -17633,6 +19312,8 @@ wire [0:0] mux_2level_tapbuf_basis_input2_mem1_2_out ; sb_2__2__const1_51 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( mux_2level_tapbuf_basis_input2_mem1_2_out[0] ) , .X ( out[0] ) ) ; sb_2__2__mux_2level_tapbuf_basis_input2_mem1_80 mux_l1_in_0_ ( .in ( in[0:1] ) , .mem ( sram[0] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_2 } ) , @@ -17648,9 +19329,6 @@ sb_2__2__mux_2level_tapbuf_basis_input2_mem1_82 mux_l2_in_0_ ( .mem ( sram[1] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_5 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_2_out ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_172 ( .A ( BUF_net_173 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_173 ( - .A ( mux_2level_tapbuf_basis_input2_mem1_2_out[0] ) , .Y ( BUF_net_173 ) ) ; endmodule @@ -17799,9 +19477,9 @@ sb_2__2__mux_2level_tapbuf_basis_input2_mem1_76 mux_l2_in_0_ ( .mem ( sram[1] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_5 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_2_out ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_170 ( .A ( BUF_net_171 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_171 ( - .A ( mux_2level_tapbuf_basis_input2_mem1_2_out[0] ) , .Y ( BUF_net_171 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_156 ( .A ( BUF_net_157 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_157 ( + .A ( mux_2level_tapbuf_basis_input2_mem1_2_out[0] ) , .Y ( BUF_net_157 ) ) ; endmodule @@ -17813,25 +19491,11 @@ input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -wire copt_net_180 ; - sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( copt_net_180 ) ) ; + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__buf_6 FTB_73__72 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1376 ( .A ( copt_net_182 ) , - .X ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1377 ( .A ( copt_net_180 ) , - .X ( copt_net_181 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1378 ( .A ( copt_net_185 ) , - .X ( copt_net_182 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1379 ( .A ( copt_net_184 ) , - .X ( copt_net_183 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1380 ( .A ( copt_net_181 ) , - .X ( copt_net_184 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1381 ( .A ( copt_net_183 ) , - .X ( copt_net_185 ) ) ; endmodule @@ -18520,9 +20184,9 @@ sb_2__2__mux_2level_tapbuf_basis_input2_mem1_71 mux_l2_in_0_ ( .mem ( sram[1] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_4 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_168 ( .A ( BUF_net_169 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_169 ( - .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_169 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_154 ( .A ( BUF_net_155 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_155 ( + .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_155 ) ) ; endmodule @@ -18578,9 +20242,9 @@ sb_2__2__mux_2level_tapbuf_basis_input2_mem1_69 mux_l2_in_0_ ( .mem ( sram[1] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_4 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_166 ( .A ( BUF_net_167 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_167 ( - .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_167 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_152 ( .A ( BUF_net_153 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_153 ( + .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_153 ) ) ; endmodule @@ -18636,9 +20300,9 @@ sb_2__2__mux_2level_tapbuf_basis_input2_mem1_67 mux_l2_in_0_ ( .mem ( sram[1] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_4 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_164 ( .A ( BUF_net_165 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_165 ( - .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_165 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_150 ( .A ( BUF_net_151 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_151 ( + .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_151 ) ) ; endmodule @@ -18650,7 +20314,7 @@ input [0:0] mem_inv ; output [0:0] out ; input p0 ; -sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , +sky130_fd_sc_hd__mux2_2 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ; endmodule @@ -18684,6 +20348,8 @@ wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ; sb_2__2__const1_44 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) ) ; sb_2__2__mux_2level_tapbuf_basis_input2_mem1_64 mux_l1_in_0_ ( .in ( in ) , .mem ( sram[0] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_2 } ) , @@ -18694,9 +20360,6 @@ sb_2__2__mux_2level_tapbuf_basis_input2_mem1_65 mux_l2_in_0_ ( .mem ( sram[1] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_4 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_162 ( .A ( BUF_net_163 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_163 ( - .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_163 ) ) ; endmodule @@ -18752,9 +20415,9 @@ sb_2__2__mux_2level_tapbuf_basis_input2_mem1_63 mux_l2_in_0_ ( .mem ( sram[1] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_4 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_160 ( .A ( BUF_net_161 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_161 ( - .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_161 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_148 ( .A ( BUF_net_149 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_149 ( + .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_149 ) ) ; endmodule @@ -18810,9 +20473,9 @@ sb_2__2__mux_2level_tapbuf_basis_input2_mem1_61 mux_l2_in_0_ ( .mem ( sram[1] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_4 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_158 ( .A ( BUF_net_159 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_159 ( - .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_159 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_146 ( .A ( BUF_net_147 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_147 ( + .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_147 ) ) ; endmodule @@ -18868,9 +20531,9 @@ sb_2__2__mux_2level_tapbuf_basis_input2_mem1_59 mux_l2_in_0_ ( .mem ( sram[1] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_4 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_156 ( .A ( BUF_net_157 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_157 ( - .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_157 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_144 ( .A ( BUF_net_145 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_145 ( + .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_145 ) ) ; endmodule @@ -18926,9 +20589,9 @@ sb_2__2__mux_2level_tapbuf_basis_input2_mem1_57 mux_l2_in_0_ ( .mem ( sram[1] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_4 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_154 ( .A ( BUF_net_155 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_155 ( - .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_155 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_142 ( .A ( BUF_net_143 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_143 ( + .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_143 ) ) ; endmodule @@ -18984,9 +20647,9 @@ sb_2__2__mux_2level_tapbuf_basis_input2_mem1_55 mux_l2_in_0_ ( .mem ( sram[1] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_4 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_152 ( .A ( BUF_net_153 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_153 ( - .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_153 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_140 ( .A ( BUF_net_141 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_141 ( + .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_141 ) ) ; endmodule @@ -19042,9 +20705,9 @@ sb_2__2__mux_2level_tapbuf_basis_input2_mem1_53 mux_l2_in_0_ ( .mem ( sram[1] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_4 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_150 ( .A ( BUF_net_151 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_151 ( - .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_151 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_138 ( .A ( BUF_net_139 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_139 ( + .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_139 ) ) ; endmodule @@ -19100,9 +20763,9 @@ sb_2__2__mux_2level_tapbuf_basis_input2_mem1_51 mux_l2_in_0_ ( .mem ( sram[1] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_4 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_148 ( .A ( BUF_net_149 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_149 ( - .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_149 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_136 ( .A ( BUF_net_137 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_137 ( + .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_137 ) ) ; endmodule @@ -19114,7 +20777,7 @@ input [0:0] mem_inv ; output [0:0] out ; input p0 ; -sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , +sky130_fd_sc_hd__mux2_2 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ; endmodule @@ -19158,9 +20821,8 @@ sb_2__2__mux_2level_tapbuf_basis_input2_mem1_49 mux_l2_in_0_ ( .mem ( sram[1] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_4 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_146 ( .A ( BUF_net_147 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_147 ( - .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_147 ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_135 ( + .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) ) ; endmodule @@ -19172,7 +20834,7 @@ input [0:0] mem_inv ; output [0:0] out ; input p0 ; -sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , +sky130_fd_sc_hd__mux2_2 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ; endmodule @@ -19216,9 +20878,8 @@ sb_2__2__mux_2level_tapbuf_basis_input2_mem1_47 mux_l2_in_0_ ( .mem ( sram[1] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_4 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_144 ( .A ( BUF_net_145 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_145 ( - .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_145 ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_134 ( + .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) ) ; endmodule @@ -19264,8 +20925,6 @@ wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ; sb_2__2__const1_34 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) ) ; sb_2__2__mux_2level_tapbuf_basis_input2_mem1_44 mux_l1_in_0_ ( .in ( in ) , .mem ( sram[0] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_2 } ) , @@ -19276,6 +20935,8 @@ sb_2__2__mux_2level_tapbuf_basis_input2_mem1_45 mux_l2_in_0_ ( .mem ( sram[1] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_4 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_133 ( + .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) ) ; endmodule @@ -19331,9 +20992,9 @@ sb_2__2__mux_2level_tapbuf_basis_input2_mem1_43 mux_l2_in_0_ ( .mem ( sram[1] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_4 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_142 ( .A ( BUF_net_143 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_143 ( - .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_143 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_131 ( .A ( BUF_net_132 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_132 ( + .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_132 ) ) ; endmodule @@ -19379,8 +21040,6 @@ wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ; sb_2__2__const1_32 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) ) ; sb_2__2__mux_2level_tapbuf_basis_input2_mem1_40 mux_l1_in_0_ ( .in ( in ) , .mem ( sram[0] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_2 } ) , @@ -19391,6 +21050,8 @@ sb_2__2__mux_2level_tapbuf_basis_input2_mem1_41 mux_l2_in_0_ ( .mem ( sram[1] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_4 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_130 ( + .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) ) ; endmodule @@ -19446,9 +21107,9 @@ sb_2__2__mux_2level_tapbuf_basis_input2_mem1_39 mux_l2_in_0_ ( .mem ( sram[1] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_4 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_140 ( .A ( BUF_net_141 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_141 ( - .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_141 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_128 ( .A ( BUF_net_129 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_129 ( + .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_129 ) ) ; endmodule @@ -19504,9 +21165,9 @@ sb_2__2__mux_2level_tapbuf_basis_input2_mem1_37 mux_l2_in_0_ ( .mem ( sram[1] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_4 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_138 ( .A ( BUF_net_139 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_139 ( - .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_139 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_126 ( .A ( BUF_net_127 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_127 ( + .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_127 ) ) ; endmodule @@ -19562,9 +21223,9 @@ sb_2__2__mux_2level_tapbuf_basis_input2_mem1_35 mux_l2_in_0_ ( .mem ( sram[1] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_4 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_136 ( .A ( BUF_net_137 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_137 ( - .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_137 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_124 ( .A ( BUF_net_125 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_125 ( + .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_125 ) ) ; endmodule @@ -19620,9 +21281,9 @@ sb_2__2__mux_2level_tapbuf_basis_input2_mem1_33 mux_l2_in_0_ ( .mem ( sram[1] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_4 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_134 ( .A ( BUF_net_135 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_135 ( - .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_135 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_122 ( .A ( BUF_net_123 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_123 ( + .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_123 ) ) ; endmodule @@ -19678,9 +21339,9 @@ sb_2__2__mux_2level_tapbuf_basis_input2_mem1_31 mux_l2_in_0_ ( .mem ( sram[1] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_4 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_132 ( .A ( BUF_net_133 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_133 ( - .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_133 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_120 ( .A ( BUF_net_121 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_121 ( + .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_121 ) ) ; endmodule @@ -19736,9 +21397,9 @@ sb_2__2__mux_2level_tapbuf_basis_input2_mem1_29 mux_l2_in_0_ ( .mem ( sram[1] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_4 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_130 ( .A ( BUF_net_131 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_131 ( - .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_131 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_118 ( .A ( BUF_net_119 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_119 ( + .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_119 ) ) ; endmodule @@ -19750,7 +21411,7 @@ input [0:0] mem_inv ; output [0:0] out ; input p0 ; -sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , +sky130_fd_sc_hd__mux2_2 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ; endmodule @@ -19784,6 +21445,8 @@ wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ; sb_2__2__const1_25 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) ) ; sb_2__2__mux_2level_tapbuf_basis_input2_mem1_26 mux_l1_in_0_ ( .in ( in ) , .mem ( sram[0] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_2 } ) , @@ -19794,9 +21457,6 @@ sb_2__2__mux_2level_tapbuf_basis_input2_mem1_27 mux_l2_in_0_ ( .mem ( sram[1] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_4 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_128 ( .A ( BUF_net_129 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_129 ( - .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_129 ) ) ; endmodule @@ -19852,9 +21512,9 @@ sb_2__2__mux_2level_tapbuf_basis_input2_mem1_25 mux_l2_in_0_ ( .mem ( sram[1] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_4 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_126 ( .A ( BUF_net_127 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_127 ( - .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_127 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_116 ( .A ( BUF_net_117 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_117 ( + .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_117 ) ) ; endmodule @@ -19866,7 +21526,7 @@ input [0:0] mem_inv ; output [0:0] out ; input p0 ; -sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , +sky130_fd_sc_hd__mux2_2 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ; endmodule @@ -19910,9 +21570,8 @@ sb_2__2__mux_2level_tapbuf_basis_input2_mem1_23 mux_l2_in_0_ ( .mem ( sram[1] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_4 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_124 ( .A ( BUF_net_125 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_125 ( - .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_125 ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_115 ( + .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) ) ; endmodule @@ -19958,6 +21617,8 @@ wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ; sb_2__2__const1_22 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) ) ; sb_2__2__mux_2level_tapbuf_basis_input2_mem1_20 mux_l1_in_0_ ( .in ( in ) , .mem ( sram[0] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_2 } ) , @@ -19968,9 +21629,6 @@ sb_2__2__mux_2level_tapbuf_basis_input2_mem1_21 mux_l2_in_0_ ( .mem ( sram[1] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_4 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_122 ( .A ( BUF_net_123 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_123 ( - .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_123 ) ) ; endmodule @@ -19982,7 +21640,7 @@ input [0:0] mem_inv ; output [0:0] out ; input p0 ; -sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , +sky130_fd_sc_hd__mux2_2 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ; endmodule @@ -20016,8 +21674,6 @@ wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ; sb_2__2__const1_21 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) ) ; sb_2__2__mux_2level_tapbuf_basis_input2_mem1_18 mux_l1_in_0_ ( .in ( in ) , .mem ( sram[0] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_2 } ) , @@ -20028,6 +21684,8 @@ sb_2__2__mux_2level_tapbuf_basis_input2_mem1_19 mux_l2_in_0_ ( .mem ( sram[1] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_4 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_114 ( + .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) ) ; endmodule @@ -20083,9 +21741,9 @@ sb_2__2__mux_2level_tapbuf_basis_input2_mem1_17 mux_l2_in_0_ ( .mem ( sram[1] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_4 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_120 ( .A ( BUF_net_121 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_121 ( - .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_121 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_112 ( .A ( BUF_net_113 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_113 ( + .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_113 ) ) ; endmodule @@ -20141,9 +21799,9 @@ sb_2__2__mux_2level_tapbuf_basis_input2_mem1_15 mux_l2_in_0_ ( .mem ( sram[1] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_4 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_118 ( .A ( BUF_net_119 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_119 ( - .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_119 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_110 ( .A ( BUF_net_111 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_111 ( + .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_111 ) ) ; endmodule @@ -20189,6 +21847,8 @@ wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ; sb_2__2__const1_18 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) ) ; sb_2__2__mux_2level_tapbuf_basis_input2_mem1_12 mux_l1_in_0_ ( .in ( in ) , .mem ( sram[0] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_2 } ) , @@ -20199,9 +21859,6 @@ sb_2__2__mux_2level_tapbuf_basis_input2_mem1_13 mux_l2_in_0_ ( .mem ( sram[1] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_4 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_116 ( .A ( BUF_net_117 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_117 ( - .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_117 ) ) ; endmodule @@ -20257,9 +21914,9 @@ sb_2__2__mux_2level_tapbuf_basis_input2_mem1_11 mux_l2_in_0_ ( .mem ( sram[1] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_4 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_114 ( .A ( BUF_net_115 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_115 ( - .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_115 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_108 ( .A ( BUF_net_109 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_109 ( + .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_109 ) ) ; endmodule @@ -20305,6 +21962,8 @@ wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ; sb_2__2__const1_16 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) ) ; sb_2__2__mux_2level_tapbuf_basis_input2_mem1_8 mux_l1_in_0_ ( .in ( in ) , .mem ( sram[0] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_2 } ) , @@ -20315,9 +21974,6 @@ sb_2__2__mux_2level_tapbuf_basis_input2_mem1_9 mux_l2_in_0_ ( .mem ( sram[1] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_4 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_112 ( .A ( BUF_net_113 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_113 ( - .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_113 ) ) ; endmodule @@ -20363,8 +22019,6 @@ wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ; sb_2__2__const1_15 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) ) ; sb_2__2__mux_2level_tapbuf_basis_input2_mem1_6 mux_l1_in_0_ ( .in ( in ) , .mem ( sram[0] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_2 } ) , @@ -20375,6 +22029,8 @@ sb_2__2__mux_2level_tapbuf_basis_input2_mem1_7 mux_l2_in_0_ ( .mem ( sram[1] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_4 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_107 ( + .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) ) ; endmodule @@ -20430,9 +22086,9 @@ sb_2__2__mux_2level_tapbuf_basis_input2_mem1_5 mux_l2_in_0_ ( .mem ( sram[1] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_4 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_110 ( .A ( BUF_net_111 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_111 ( - .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_111 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_105 ( .A ( BUF_net_106 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_106 ( + .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_106 ) ) ; endmodule @@ -20478,6 +22134,8 @@ wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ; sb_2__2__const1_13 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) ) ; sb_2__2__mux_2level_tapbuf_basis_input2_mem1_2 mux_l1_in_0_ ( .in ( in ) , .mem ( sram[0] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_2 } ) , @@ -20488,8 +22146,6 @@ sb_2__2__mux_2level_tapbuf_basis_input2_mem1_3 mux_l2_in_0_ ( .mem ( sram[1] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_4 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_109 ( - .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) ) ; endmodule @@ -20545,7 +22201,7 @@ sb_2__2__mux_2level_tapbuf_basis_input2_mem1_1 mux_l2_in_0_ ( .mem ( sram[1] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_4 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_108 ( +sky130_fd_sc_hd__buf_6 BUFT_RR_104 ( .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) ) ; endmodule @@ -20778,7 +22434,7 @@ input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ropt_net_200 ) , +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ropt_net_191 ) , .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; @@ -20787,18 +22443,30 @@ sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__buf_1 FTB_25__24 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1429 ( .A ( ccff_head[0] ) , - .X ( ropt_net_197 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1430 ( .A ( ropt_net_201 ) , - .X ( ropt_net_198 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1431 ( .A ( ropt_net_198 ) , - .X ( ropt_net_199 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1432 ( .A ( ropt_net_199 ) , - .X ( ropt_net_200 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1433 ( .A ( ropt_net_202 ) , - .X ( ropt_net_201 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1434 ( .A ( ropt_net_197 ) , - .X ( ropt_net_202 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1344 ( .A ( ccff_head[0] ) , + .X ( copt_net_164 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1345 ( .A ( copt_net_164 ) , + .X ( copt_net_165 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1346 ( .A ( copt_net_165 ) , + .X ( copt_net_166 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1347 ( .A ( copt_net_166 ) , + .X ( copt_net_167 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1348 ( .A ( copt_net_167 ) , + .X ( copt_net_168 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1349 ( .A ( ropt_net_195 ) , + .X ( copt_net_169 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1367 ( .A ( copt_net_169 ) , + .X ( ropt_net_190 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1368 ( .A ( ropt_net_192 ) , + .X ( ropt_net_191 ) ) ; +sky130_fd_sc_hd__buf_2 ropt_h_inst_1369 ( .A ( ropt_net_190 ) , + .X ( ropt_net_192 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1370 ( .A ( copt_net_168 ) , + .X ( ropt_net_193 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1371 ( .A ( ropt_net_193 ) , + .X ( ropt_net_194 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1372 ( .A ( ropt_net_194 ) , + .X ( ropt_net_195 ) ) ; endmodule @@ -20810,10 +22478,14 @@ input [0:2] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -20824,10 +22496,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -20900,9 +22576,9 @@ sb_2__2__mux_2level_tapbuf_basis_input3_mem3 mux_l2_in_0_ ( .mem ( local_encoder2to3_1_data ) , .mem_inv ( local_encoder2to3_1_data_inv ) , .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_106 ( .A ( BUF_net_107 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_107 ( - .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_107 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_102 ( .A ( BUF_net_103 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_103 ( + .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_103 ) ) ; endmodule @@ -20914,10 +22590,14 @@ input [0:2] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -20928,10 +22608,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -21004,9 +22688,9 @@ sb_2__2__mux_2level_tapbuf_basis_input3_mem3_21 mux_l2_in_0_ ( .mem ( local_encoder2to3_1_data ) , .mem_inv ( local_encoder2to3_1_data_inv ) , .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_104 ( .A ( BUF_net_105 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_105 ( - .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_105 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_100 ( .A ( BUF_net_101 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_101 ( + .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_101 ) ) ; endmodule @@ -21018,10 +22702,14 @@ input [0:2] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -21032,10 +22720,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -21108,9 +22800,9 @@ sb_2__2__mux_2level_tapbuf_basis_input3_mem3_19 mux_l2_in_0_ ( .mem ( local_encoder2to3_1_data ) , .mem_inv ( local_encoder2to3_1_data_inv ) , .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_102 ( .A ( BUF_net_103 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_103 ( - .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_103 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_98 ( .A ( BUF_net_99 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_99 ( + .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_99 ) ) ; endmodule @@ -21122,10 +22814,14 @@ input [0:2] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -21136,10 +22832,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -21212,9 +22912,9 @@ sb_2__2__mux_2level_tapbuf_basis_input3_mem3_17 mux_l2_in_0_ ( .mem ( local_encoder2to3_1_data ) , .mem_inv ( local_encoder2to3_1_data_inv ) , .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_100 ( .A ( BUF_net_101 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_101 ( - .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_101 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_96 ( .A ( BUF_net_97 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_97 ( + .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_97 ) ) ; endmodule @@ -21226,10 +22926,14 @@ input [0:2] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -21240,10 +22944,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -21316,9 +23024,9 @@ sb_2__2__mux_2level_tapbuf_basis_input3_mem3_15 mux_l2_in_0_ ( .mem ( local_encoder2to3_1_data ) , .mem_inv ( local_encoder2to3_1_data_inv ) , .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_98 ( .A ( BUF_net_99 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_99 ( - .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_99 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_94 ( .A ( BUF_net_95 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_95 ( + .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_95 ) ) ; endmodule @@ -21330,10 +23038,14 @@ input [0:2] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -21344,10 +23056,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -21420,9 +23136,9 @@ sb_2__2__mux_2level_tapbuf_basis_input3_mem3_13 mux_l2_in_0_ ( .mem ( local_encoder2to3_1_data ) , .mem_inv ( local_encoder2to3_1_data_inv ) , .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_96 ( .A ( BUF_net_97 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_97 ( - .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_97 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_92 ( .A ( BUF_net_93 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_93 ( + .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_93 ) ) ; endmodule @@ -21434,10 +23150,14 @@ input [0:2] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -21448,10 +23168,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -21524,9 +23248,9 @@ sb_2__2__mux_2level_tapbuf_basis_input3_mem3_11 mux_l2_in_0_ ( .mem ( local_encoder2to3_1_data ) , .mem_inv ( local_encoder2to3_1_data_inv ) , .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_94 ( .A ( BUF_net_95 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_95 ( - .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_95 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_90 ( .A ( BUF_net_91 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_91 ( + .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_91 ) ) ; endmodule @@ -21538,10 +23262,14 @@ input [0:2] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -21552,10 +23280,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -21628,9 +23360,9 @@ sb_2__2__mux_2level_tapbuf_basis_input3_mem3_9 mux_l2_in_0_ ( .mem ( local_encoder2to3_1_data ) , .mem_inv ( local_encoder2to3_1_data_inv ) , .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_92 ( .A ( BUF_net_93 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_93 ( - .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_93 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_88 ( .A ( BUF_net_89 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_89 ( + .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_89 ) ) ; endmodule @@ -21642,10 +23374,14 @@ input [0:2] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -21656,10 +23392,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -21732,9 +23472,9 @@ sb_2__2__mux_2level_tapbuf_basis_input3_mem3_7 mux_l2_in_0_ ( .mem ( local_encoder2to3_1_data ) , .mem_inv ( local_encoder2to3_1_data_inv ) , .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_90 ( .A ( BUF_net_91 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_91 ( - .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_91 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_86 ( .A ( BUF_net_87 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_87 ( + .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_87 ) ) ; endmodule @@ -21746,10 +23486,14 @@ input [0:2] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -21760,10 +23504,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -21836,7 +23584,7 @@ sb_2__2__mux_2level_tapbuf_basis_input3_mem3_5 mux_l2_in_0_ ( .mem ( local_encoder2to3_1_data ) , .mem_inv ( local_encoder2to3_1_data_inv ) , .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_89 ( +sky130_fd_sc_hd__buf_6 BUFT_RR_85 ( .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .X ( out[0] ) ) ; endmodule @@ -21849,10 +23597,14 @@ input [0:2] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -21863,10 +23615,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -21923,6 +23679,8 @@ wire [0:0] mux_2level_tapbuf_basis_input3_mem3_1_out ; sb_2__2__const1_1 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .X ( out[0] ) ) ; sb_2__2__local_encoder2to3_2 local_encoder2to3_0_ ( .addr ( sram[0:1] ) , .data ( local_encoder2to3_0_data ) , .data_inv ( local_encoder2to3_0_data_inv ) ) ; @@ -21939,9 +23697,6 @@ sb_2__2__mux_2level_tapbuf_basis_input3_mem3_3 mux_l2_in_0_ ( .mem ( local_encoder2to3_1_data ) , .mem_inv ( local_encoder2to3_1_data_inv ) , .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_87 ( .A ( BUF_net_88 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_88 ( - .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_88 ) ) ; endmodule @@ -21953,10 +23708,14 @@ input [0:2] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -21967,10 +23726,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -22027,6 +23790,8 @@ wire [0:0] mux_2level_tapbuf_basis_input3_mem3_1_out ; sb_2__2__const1_0 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .X ( out[0] ) ) ; sb_2__2__local_encoder2to3_0 local_encoder2to3_0_ ( .addr ( sram[0:1] ) , .data ( local_encoder2to3_0_data ) , .data_inv ( local_encoder2to3_0_data_inv ) ) ; @@ -22043,9 +23808,6 @@ sb_2__2__mux_2level_tapbuf_basis_input3_mem3_1 mux_l2_in_0_ ( .mem ( local_encoder2to3_1_data ) , .mem_inv ( local_encoder2to3_1_data_inv ) , .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_85 ( .A ( BUF_net_86 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_86 ( - .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_86 ) ) ; endmodule @@ -22206,84 +23968,84 @@ sb_2__2__mux_2level_tapbuf_size4_0 mux_bottom_track_1 ( .sram ( mux_2level_tapbuf_size4_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 , SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) , - .out ( chany_bottom_out[0] ) , .p0 ( optlc_net_178 ) ) ; + .out ( chany_bottom_out[0] ) , .p0 ( optlc_net_162 ) ) ; sb_2__2__mux_2level_tapbuf_size4_1 mux_bottom_track_3 ( .in ( { bottom_left_grid_pin_44_[0] , bottom_left_grid_pin_47_[0] , bottom_left_grid_pin_50_[0] , chanx_left_in[2] } ) , .sram ( mux_2level_tapbuf_size4_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 , SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 } ) , - .out ( chany_bottom_out[1] ) , .p0 ( optlc_net_178 ) ) ; + .out ( chany_bottom_out[1] ) , .p0 ( optlc_net_162 ) ) ; sb_2__2__mux_2level_tapbuf_size4_2 mux_bottom_track_5 ( .in ( { bottom_left_grid_pin_45_[0] , bottom_left_grid_pin_48_[0] , bottom_left_grid_pin_51_[0] , chanx_left_in[3] } ) , .sram ( mux_2level_tapbuf_size4_2_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_9 , SYNOPSYS_UNCONNECTED_10 , SYNOPSYS_UNCONNECTED_11 , SYNOPSYS_UNCONNECTED_12 } ) , - .out ( chany_bottom_out[2] ) , .p0 ( optlc_net_174 ) ) ; + .out ( chany_bottom_out[2] ) , .p0 ( optlc_net_162 ) ) ; sb_2__2__mux_2level_tapbuf_size4_3 mux_bottom_track_7 ( .in ( { bottom_right_grid_pin_1_[0] , bottom_left_grid_pin_46_[0] , bottom_left_grid_pin_49_[0] , chanx_left_in[4] } ) , .sram ( mux_2level_tapbuf_size4_3_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 , SYNOPSYS_UNCONNECTED_15 , SYNOPSYS_UNCONNECTED_16 } ) , - .out ( chany_bottom_out[3] ) , .p0 ( optlc_net_178 ) ) ; + .out ( chany_bottom_out[3] ) , .p0 ( optlc_net_162 ) ) ; sb_2__2__mux_2level_tapbuf_size4_4 mux_bottom_track_9 ( .in ( { bottom_left_grid_pin_44_[0] , bottom_left_grid_pin_47_[0] , bottom_left_grid_pin_50_[0] , chanx_left_in[5] } ) , .sram ( mux_2level_tapbuf_size4_4_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_17 , SYNOPSYS_UNCONNECTED_18 , SYNOPSYS_UNCONNECTED_19 , SYNOPSYS_UNCONNECTED_20 } ) , - .out ( chany_bottom_out[4] ) , .p0 ( optlc_net_177 ) ) ; + .out ( chany_bottom_out[4] ) , .p0 ( optlc_net_160 ) ) ; sb_2__2__mux_2level_tapbuf_size4_5 mux_bottom_track_11 ( .in ( { bottom_left_grid_pin_45_[0] , bottom_left_grid_pin_48_[0] , bottom_left_grid_pin_51_[0] , chanx_left_in[6] } ) , .sram ( mux_2level_tapbuf_size4_5_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_21 , SYNOPSYS_UNCONNECTED_22 , SYNOPSYS_UNCONNECTED_23 , SYNOPSYS_UNCONNECTED_24 } ) , - .out ( chany_bottom_out[5] ) , .p0 ( optlc_net_174 ) ) ; + .out ( chany_bottom_out[5] ) , .p0 ( optlc_net_162 ) ) ; sb_2__2__mux_2level_tapbuf_size4_6 mux_left_track_1 ( .in ( { chany_bottom_in[29] , left_top_grid_pin_1_[0] , left_bottom_grid_pin_38_[0] , left_bottom_grid_pin_41_[0] } ) , .sram ( mux_2level_tapbuf_size4_6_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_25 , SYNOPSYS_UNCONNECTED_26 , SYNOPSYS_UNCONNECTED_27 , SYNOPSYS_UNCONNECTED_28 } ) , - .out ( chanx_left_out[0] ) , .p0 ( optlc_net_174 ) ) ; + .out ( chanx_left_out[0] ) , .p0 ( optlc_net_160 ) ) ; sb_2__2__mux_2level_tapbuf_size4_7 mux_left_track_3 ( .in ( { chany_bottom_in[0] , left_bottom_grid_pin_36_[0] , left_bottom_grid_pin_39_[0] , left_bottom_grid_pin_42_[0] } ) , .sram ( mux_2level_tapbuf_size4_7_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_29 , SYNOPSYS_UNCONNECTED_30 , SYNOPSYS_UNCONNECTED_31 , SYNOPSYS_UNCONNECTED_32 } ) , - .out ( chanx_left_out[1] ) , .p0 ( optlc_net_174 ) ) ; + .out ( chanx_left_out[1] ) , .p0 ( optlc_net_160 ) ) ; sb_2__2__mux_2level_tapbuf_size4_8 mux_left_track_5 ( .in ( { chany_bottom_in[1] , left_bottom_grid_pin_37_[0] , left_bottom_grid_pin_40_[0] , left_bottom_grid_pin_43_[0] } ) , .sram ( mux_2level_tapbuf_size4_8_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_33 , SYNOPSYS_UNCONNECTED_34 , SYNOPSYS_UNCONNECTED_35 , SYNOPSYS_UNCONNECTED_36 } ) , - .out ( chanx_left_out[2] ) , .p0 ( optlc_net_174 ) ) ; + .out ( chanx_left_out[2] ) , .p0 ( optlc_net_160 ) ) ; sb_2__2__mux_2level_tapbuf_size4_9 mux_left_track_7 ( .in ( { chany_bottom_in[2] , left_top_grid_pin_1_[0] , left_bottom_grid_pin_38_[0] , left_bottom_grid_pin_41_[0] } ) , .sram ( mux_2level_tapbuf_size4_9_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_37 , SYNOPSYS_UNCONNECTED_38 , SYNOPSYS_UNCONNECTED_39 , SYNOPSYS_UNCONNECTED_40 } ) , - .out ( chanx_left_out[3] ) , .p0 ( optlc_net_174 ) ) ; + .out ( chanx_left_out[3] ) , .p0 ( optlc_net_160 ) ) ; sb_2__2__mux_2level_tapbuf_size4_10 mux_left_track_9 ( .in ( { chany_bottom_in[3] , left_bottom_grid_pin_36_[0] , left_bottom_grid_pin_39_[0] , left_bottom_grid_pin_42_[0] } ) , .sram ( mux_2level_tapbuf_size4_10_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_41 , SYNOPSYS_UNCONNECTED_42 , SYNOPSYS_UNCONNECTED_43 , SYNOPSYS_UNCONNECTED_44 } ) , - .out ( chanx_left_out[4] ) , .p0 ( optlc_net_174 ) ) ; + .out ( chanx_left_out[4] ) , .p0 ( optlc_net_160 ) ) ; sb_2__2__mux_2level_tapbuf_size4 mux_left_track_11 ( .in ( { chany_bottom_in[4] , left_bottom_grid_pin_37_[0] , left_bottom_grid_pin_40_[0] , left_bottom_grid_pin_43_[0] } ) , .sram ( mux_2level_tapbuf_size4_11_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_45 , SYNOPSYS_UNCONNECTED_46 , SYNOPSYS_UNCONNECTED_47 , SYNOPSYS_UNCONNECTED_48 } ) , - .out ( chanx_left_out[5] ) , .p0 ( optlc_net_174 ) ) ; + .out ( chanx_left_out[5] ) , .p0 ( optlc_net_160 ) ) ; sb_2__2__mux_2level_tapbuf_size4_mem_0 mem_bottom_track_1 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( mux_2level_tapbuf_size4_mem_0_ccff_tail ) , @@ -22347,187 +24109,187 @@ sb_2__2__mux_2level_tapbuf_size2_0 mux_bottom_track_13 ( .in ( { bottom_right_grid_pin_1_[0] , chanx_left_in[7] } ) , .sram ( mux_2level_tapbuf_size2_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_49 , SYNOPSYS_UNCONNECTED_50 } ) , - .out ( chany_bottom_out[6] ) , .p0 ( optlc_net_177 ) ) ; + .out ( chany_bottom_out[6] ) , .p0 ( optlc_net_162 ) ) ; sb_2__2__mux_2level_tapbuf_size2_1 mux_bottom_track_15 ( .in ( { bottom_left_grid_pin_44_[0] , chanx_left_in[8] } ) , .sram ( mux_2level_tapbuf_size2_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_51 , SYNOPSYS_UNCONNECTED_52 } ) , - .out ( chany_bottom_out[7] ) , .p0 ( optlc_net_175 ) ) ; + .out ( chany_bottom_out[7] ) , .p0 ( optlc_net_163 ) ) ; sb_2__2__mux_2level_tapbuf_size2_2 mux_bottom_track_17 ( .in ( { bottom_left_grid_pin_45_[0] , chanx_left_in[9] } ) , .sram ( mux_2level_tapbuf_size2_2_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_53 , SYNOPSYS_UNCONNECTED_54 } ) , - .out ( chany_bottom_out[8] ) , .p0 ( optlc_net_175 ) ) ; + .out ( chany_bottom_out[8] ) , .p0 ( optlc_net_163 ) ) ; sb_2__2__mux_2level_tapbuf_size2_3 mux_bottom_track_19 ( .in ( { bottom_left_grid_pin_46_[0] , chanx_left_in[10] } ) , .sram ( mux_2level_tapbuf_size2_3_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_55 , SYNOPSYS_UNCONNECTED_56 } ) , - .out ( chany_bottom_out[9] ) , .p0 ( optlc_net_175 ) ) ; + .out ( chany_bottom_out[9] ) , .p0 ( optlc_net_163 ) ) ; sb_2__2__mux_2level_tapbuf_size2_4 mux_bottom_track_21 ( .in ( { bottom_left_grid_pin_47_[0] , chanx_left_in[11] } ) , .sram ( mux_2level_tapbuf_size2_4_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_57 , SYNOPSYS_UNCONNECTED_58 } ) , - .out ( chany_bottom_out[10] ) , .p0 ( optlc_net_179 ) ) ; + .out ( chany_bottom_out[10] ) , .p0 ( optlc_net_163 ) ) ; sb_2__2__mux_2level_tapbuf_size2_5 mux_bottom_track_23 ( .in ( { bottom_left_grid_pin_48_[0] , chanx_left_in[12] } ) , .sram ( mux_2level_tapbuf_size2_5_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_59 , SYNOPSYS_UNCONNECTED_60 } ) , - .out ( chany_bottom_out[11] ) , .p0 ( optlc_net_179 ) ) ; + .out ( chany_bottom_out[11] ) , .p0 ( optlc_net_162 ) ) ; sb_2__2__mux_2level_tapbuf_size2_6 mux_bottom_track_25 ( .in ( { bottom_left_grid_pin_49_[0] , chanx_left_in[13] } ) , .sram ( mux_2level_tapbuf_size2_6_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_61 , SYNOPSYS_UNCONNECTED_62 } ) , - .out ( chany_bottom_out[12] ) , .p0 ( optlc_net_178 ) ) ; + .out ( chany_bottom_out[12] ) , .p0 ( optlc_net_163 ) ) ; sb_2__2__mux_2level_tapbuf_size2_7 mux_bottom_track_27 ( .in ( { bottom_left_grid_pin_50_[0] , chanx_left_in[14] } ) , .sram ( mux_2level_tapbuf_size2_7_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_63 , SYNOPSYS_UNCONNECTED_64 } ) , - .out ( chany_bottom_out[13] ) , .p0 ( optlc_net_177 ) ) ; + .out ( chany_bottom_out[13] ) , .p0 ( optlc_net_162 ) ) ; sb_2__2__mux_2level_tapbuf_size2_8 mux_bottom_track_39 ( .in ( { bottom_left_grid_pin_44_[0] , chanx_left_in[20] } ) , .sram ( mux_2level_tapbuf_size2_8_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_65 , SYNOPSYS_UNCONNECTED_66 } ) , - .out ( chany_bottom_out[19] ) , .p0 ( optlc_net_179 ) ) ; + .out ( chany_bottom_out[19] ) , .p0 ( optlc_net_162 ) ) ; sb_2__2__mux_2level_tapbuf_size2_9 mux_bottom_track_41 ( .in ( { bottom_left_grid_pin_45_[0] , chanx_left_in[21] } ) , .sram ( mux_2level_tapbuf_size2_9_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_67 , SYNOPSYS_UNCONNECTED_68 } ) , - .out ( chany_bottom_out[20] ) , .p0 ( optlc_net_175 ) ) ; + .out ( chany_bottom_out[20] ) , .p0 ( optlc_net_162 ) ) ; sb_2__2__mux_2level_tapbuf_size2_10 mux_bottom_track_43 ( .in ( { bottom_left_grid_pin_46_[0] , chanx_left_in[22] } ) , .sram ( mux_2level_tapbuf_size2_10_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_69 , SYNOPSYS_UNCONNECTED_70 } ) , - .out ( chany_bottom_out[21] ) , .p0 ( optlc_net_175 ) ) ; + .out ( chany_bottom_out[21] ) , .p0 ( optlc_net_163 ) ) ; sb_2__2__mux_2level_tapbuf_size2_11 mux_bottom_track_47 ( .in ( { bottom_left_grid_pin_48_[0] , chanx_left_in[24] } ) , .sram ( mux_2level_tapbuf_size2_11_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_71 , SYNOPSYS_UNCONNECTED_72 } ) , - .out ( chany_bottom_out[23] ) , .p0 ( optlc_net_175 ) ) ; + .out ( chany_bottom_out[23] ) , .p0 ( optlc_net_163 ) ) ; sb_2__2__mux_2level_tapbuf_size2_12 mux_bottom_track_49 ( .in ( { bottom_left_grid_pin_49_[0] , chanx_left_in[25] } ) , .sram ( mux_2level_tapbuf_size2_12_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_73 , SYNOPSYS_UNCONNECTED_74 } ) , - .out ( chany_bottom_out[24] ) , .p0 ( optlc_net_177 ) ) ; + .out ( chany_bottom_out[24] ) , .p0 ( optlc_net_163 ) ) ; sb_2__2__mux_2level_tapbuf_size2_13 mux_bottom_track_51 ( .in ( { bottom_left_grid_pin_50_[0] , chanx_left_in[26] } ) , .sram ( mux_2level_tapbuf_size2_13_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_75 , SYNOPSYS_UNCONNECTED_76 } ) , - .out ( chany_bottom_out[25] ) , .p0 ( optlc_net_177 ) ) ; + .out ( chany_bottom_out[25] ) , .p0 ( optlc_net_163 ) ) ; sb_2__2__mux_2level_tapbuf_size2_14 mux_bottom_track_53 ( .in ( { bottom_left_grid_pin_51_[0] , chanx_left_in[27] } ) , .sram ( mux_2level_tapbuf_size2_14_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_77 , SYNOPSYS_UNCONNECTED_78 } ) , - .out ( chany_bottom_out[26] ) , .p0 ( optlc_net_174 ) ) ; + .out ( chany_bottom_out[26] ) , .p0 ( optlc_net_162 ) ) ; sb_2__2__mux_2level_tapbuf_size2_15 mux_left_track_13 ( .in ( { chany_bottom_in[5] , left_top_grid_pin_1_[0] } ) , .sram ( mux_2level_tapbuf_size2_15_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_79 , SYNOPSYS_UNCONNECTED_80 } ) , - .out ( chanx_left_out[6] ) , .p0 ( optlc_net_176 ) ) ; + .out ( chanx_left_out[6] ) , .p0 ( optlc_net_161 ) ) ; sb_2__2__mux_2level_tapbuf_size2_16 mux_left_track_15 ( .in ( { chany_bottom_in[6] , left_bottom_grid_pin_36_[0] } ) , .sram ( mux_2level_tapbuf_size2_16_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_81 , SYNOPSYS_UNCONNECTED_82 } ) , - .out ( chanx_left_out[7] ) , .p0 ( optlc_net_176 ) ) ; + .out ( chanx_left_out[7] ) , .p0 ( optlc_net_163 ) ) ; sb_2__2__mux_2level_tapbuf_size2_17 mux_left_track_17 ( .in ( { chany_bottom_in[7] , left_bottom_grid_pin_37_[0] } ) , .sram ( mux_2level_tapbuf_size2_17_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_83 , SYNOPSYS_UNCONNECTED_84 } ) , - .out ( chanx_left_out[8] ) , .p0 ( optlc_net_176 ) ) ; + .out ( chanx_left_out[8] ) , .p0 ( optlc_net_161 ) ) ; sb_2__2__mux_2level_tapbuf_size2_18 mux_left_track_19 ( .in ( { chany_bottom_in[8] , left_bottom_grid_pin_38_[0] } ) , .sram ( mux_2level_tapbuf_size2_18_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_85 , SYNOPSYS_UNCONNECTED_86 } ) , - .out ( chanx_left_out[9] ) , .p0 ( optlc_net_176 ) ) ; + .out ( chanx_left_out[9] ) , .p0 ( optlc_net_161 ) ) ; sb_2__2__mux_2level_tapbuf_size2_19 mux_left_track_21 ( .in ( { chany_bottom_in[9] , left_bottom_grid_pin_39_[0] } ) , .sram ( mux_2level_tapbuf_size2_19_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_87 , SYNOPSYS_UNCONNECTED_88 } ) , - .out ( chanx_left_out[10] ) , .p0 ( optlc_net_175 ) ) ; + .out ( chanx_left_out[10] ) , .p0 ( optlc_net_161 ) ) ; sb_2__2__mux_2level_tapbuf_size2_20 mux_left_track_23 ( .in ( { chany_bottom_in[10] , left_bottom_grid_pin_40_[0] } ) , .sram ( mux_2level_tapbuf_size2_20_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_89 , SYNOPSYS_UNCONNECTED_90 } ) , - .out ( chanx_left_out[11] ) , .p0 ( optlc_net_175 ) ) ; + .out ( chanx_left_out[11] ) , .p0 ( optlc_net_163 ) ) ; sb_2__2__mux_2level_tapbuf_size2_21 mux_left_track_25 ( .in ( { chany_bottom_in[11] , left_bottom_grid_pin_41_[0] } ) , .sram ( mux_2level_tapbuf_size2_21_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_91 , SYNOPSYS_UNCONNECTED_92 } ) , - .out ( chanx_left_out[12] ) , .p0 ( optlc_net_175 ) ) ; + .out ( chanx_left_out[12] ) , .p0 ( optlc_net_163 ) ) ; sb_2__2__mux_2level_tapbuf_size2_22 mux_left_track_27 ( .in ( { chany_bottom_in[12] , left_bottom_grid_pin_42_[0] } ) , .sram ( mux_2level_tapbuf_size2_22_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_93 , SYNOPSYS_UNCONNECTED_94 } ) , - .out ( chanx_left_out[13] ) , .p0 ( optlc_net_175 ) ) ; + .out ( chanx_left_out[13] ) , .p0 ( optlc_net_163 ) ) ; sb_2__2__mux_2level_tapbuf_size2_23 mux_left_track_31 ( .in ( { chany_bottom_in[14] , left_bottom_grid_pin_36_[0] } ) , .sram ( mux_2level_tapbuf_size2_23_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_95 , SYNOPSYS_UNCONNECTED_96 } ) , - .out ( chanx_left_out[15] ) , .p0 ( optlc_net_176 ) ) ; + .out ( chanx_left_out[15] ) , .p0 ( optlc_net_163 ) ) ; sb_2__2__mux_2level_tapbuf_size2_24 mux_left_track_33 ( .in ( { chany_bottom_in[15] , left_bottom_grid_pin_37_[0] } ) , .sram ( mux_2level_tapbuf_size2_24_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_97 , SYNOPSYS_UNCONNECTED_98 } ) , - .out ( chanx_left_out[16] ) , .p0 ( optlc_net_176 ) ) ; + .out ( chanx_left_out[16] ) , .p0 ( optlc_net_163 ) ) ; sb_2__2__mux_2level_tapbuf_size2_25 mux_left_track_35 ( .in ( { chany_bottom_in[16] , left_bottom_grid_pin_38_[0] } ) , .sram ( mux_2level_tapbuf_size2_25_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_99 , SYNOPSYS_UNCONNECTED_100 } ) , - .out ( chanx_left_out[17] ) , .p0 ( optlc_net_176 ) ) ; + .out ( chanx_left_out[17] ) , .p0 ( optlc_net_161 ) ) ; sb_2__2__mux_2level_tapbuf_size2_26 mux_left_track_37 ( .in ( { chany_bottom_in[17] , left_bottom_grid_pin_39_[0] } ) , .sram ( mux_2level_tapbuf_size2_26_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_101 , SYNOPSYS_UNCONNECTED_102 } ) , - .out ( chanx_left_out[18] ) , .p0 ( optlc_net_176 ) ) ; + .out ( chanx_left_out[18] ) , .p0 ( optlc_net_161 ) ) ; sb_2__2__mux_2level_tapbuf_size2_27 mux_left_track_39 ( .in ( { chany_bottom_in[18] , left_bottom_grid_pin_40_[0] } ) , .sram ( mux_2level_tapbuf_size2_27_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_103 , SYNOPSYS_UNCONNECTED_104 } ) , - .out ( chanx_left_out[19] ) , .p0 ( optlc_net_176 ) ) ; + .out ( chanx_left_out[19] ) , .p0 ( optlc_net_161 ) ) ; sb_2__2__mux_2level_tapbuf_size2_28 mux_left_track_41 ( .in ( { chany_bottom_in[19] , left_bottom_grid_pin_41_[0] } ) , .sram ( mux_2level_tapbuf_size2_28_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_105 , SYNOPSYS_UNCONNECTED_106 } ) , - .out ( chanx_left_out[20] ) , .p0 ( optlc_net_176 ) ) ; + .out ( chanx_left_out[20] ) , .p0 ( optlc_net_161 ) ) ; sb_2__2__mux_2level_tapbuf_size2_29 mux_left_track_43 ( .in ( { chany_bottom_in[20] , left_bottom_grid_pin_42_[0] } ) , .sram ( mux_2level_tapbuf_size2_29_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_107 , SYNOPSYS_UNCONNECTED_108 } ) , - .out ( chanx_left_out[21] ) , .p0 ( optlc_net_176 ) ) ; + .out ( chanx_left_out[21] ) , .p0 ( optlc_net_161 ) ) ; sb_2__2__mux_2level_tapbuf_size2_30 mux_left_track_45 ( .in ( { chany_bottom_in[21] , left_top_grid_pin_1_[0] } ) , .sram ( mux_2level_tapbuf_size2_30_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_109 , SYNOPSYS_UNCONNECTED_110 } ) , - .out ( chanx_left_out[22] ) , .p0 ( optlc_net_176 ) ) ; + .out ( chanx_left_out[22] ) , .p0 ( optlc_net_161 ) ) ; sb_2__2__mux_2level_tapbuf_size2_31 mux_left_track_47 ( .in ( { chany_bottom_in[22] , left_bottom_grid_pin_36_[0] } ) , .sram ( mux_2level_tapbuf_size2_31_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_111 , SYNOPSYS_UNCONNECTED_112 } ) , - .out ( chanx_left_out[23] ) , .p0 ( optlc_net_176 ) ) ; + .out ( chanx_left_out[23] ) , .p0 ( optlc_net_161 ) ) ; sb_2__2__mux_2level_tapbuf_size2_32 mux_left_track_49 ( .in ( { chany_bottom_in[23] , left_bottom_grid_pin_37_[0] } ) , .sram ( mux_2level_tapbuf_size2_32_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_113 , SYNOPSYS_UNCONNECTED_114 } ) , - .out ( chanx_left_out[24] ) , .p0 ( optlc_net_176 ) ) ; + .out ( chanx_left_out[24] ) , .p0 ( optlc_net_163 ) ) ; sb_2__2__mux_2level_tapbuf_size2_33 mux_left_track_51 ( .in ( { chany_bottom_in[24] , left_bottom_grid_pin_38_[0] } ) , .sram ( mux_2level_tapbuf_size2_33_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_115 , SYNOPSYS_UNCONNECTED_116 } ) , - .out ( chanx_left_out[25] ) , .p0 ( optlc_net_176 ) ) ; + .out ( chanx_left_out[25] ) , .p0 ( optlc_net_161 ) ) ; sb_2__2__mux_2level_tapbuf_size2_34 mux_left_track_55 ( .in ( { chany_bottom_in[26] , left_bottom_grid_pin_40_[0] } ) , .sram ( mux_2level_tapbuf_size2_34_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_117 , SYNOPSYS_UNCONNECTED_118 } ) , - .out ( chanx_left_out[27] ) , .p0 ( optlc_net_175 ) ) ; + .out ( chanx_left_out[27] ) , .p0 ( optlc_net_161 ) ) ; sb_2__2__mux_2level_tapbuf_size2_35 mux_left_track_57 ( .in ( { chany_bottom_in[27] , left_bottom_grid_pin_41_[0] } ) , .sram ( mux_2level_tapbuf_size2_35_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_119 , SYNOPSYS_UNCONNECTED_120 } ) , - .out ( chanx_left_out[28] ) , .p0 ( optlc_net_175 ) ) ; + .out ( chanx_left_out[28] ) , .p0 ( optlc_net_161 ) ) ; sb_2__2__mux_2level_tapbuf_size2 mux_left_track_59 ( .in ( { chany_bottom_in[28] , left_bottom_grid_pin_42_[0] } ) , .sram ( mux_2level_tapbuf_size2_36_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_121 , SYNOPSYS_UNCONNECTED_122 } ) , - .out ( chanx_left_out[29] ) , .p0 ( optlc_net_175 ) ) ; + .out ( chanx_left_out[29] ) , .p0 ( optlc_net_163 ) ) ; sb_2__2__mux_2level_tapbuf_size2_mem_0 mem_bottom_track_13 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( mux_2level_tapbuf_size4_mem_5_ccff_tail ) , @@ -22717,25 +24479,25 @@ sb_2__2__mux_2level_tapbuf_size3_0 mux_bottom_track_29 ( chanx_left_in[15] } ) , .sram ( mux_2level_tapbuf_size3_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_123 , SYNOPSYS_UNCONNECTED_124 } ) , - .out ( chany_bottom_out[14] ) , .p0 ( optlc_net_177 ) ) ; + .out ( chany_bottom_out[14] ) , .p0 ( optlc_net_162 ) ) ; sb_2__2__mux_2level_tapbuf_size3_1 mux_bottom_track_45 ( .in ( { bottom_right_grid_pin_1_[0] , bottom_left_grid_pin_47_[0] , chanx_left_in[23] } ) , .sram ( mux_2level_tapbuf_size3_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_125 , SYNOPSYS_UNCONNECTED_126 } ) , - .out ( chany_bottom_out[22] ) , .p0 ( optlc_net_175 ) ) ; + .out ( chany_bottom_out[22] ) , .p0 ( optlc_net_163 ) ) ; sb_2__2__mux_2level_tapbuf_size3_2 mux_left_track_29 ( .in ( { chany_bottom_in[13] , left_top_grid_pin_1_[0] , left_bottom_grid_pin_43_[0] } ) , .sram ( mux_2level_tapbuf_size3_2_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_127 , SYNOPSYS_UNCONNECTED_128 } ) , - .out ( chanx_left_out[14] ) , .p0 ( optlc_net_176 ) ) ; + .out ( chanx_left_out[14] ) , .p0 ( optlc_net_163 ) ) ; sb_2__2__mux_2level_tapbuf_size3 mux_left_track_53 ( .in ( { chany_bottom_in[25] , left_bottom_grid_pin_39_[0] , left_bottom_grid_pin_43_[0] } ) , .sram ( mux_2level_tapbuf_size3_3_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_129 , SYNOPSYS_UNCONNECTED_130 } ) , - .out ( chanx_left_out[26] ) , .p0 ( optlc_net_176 ) ) ; + .out ( chanx_left_out[26] ) , .p0 ( optlc_net_161 ) ) ; sb_2__2__mux_2level_tapbuf_size3_mem_0 mem_bottom_track_29 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( mux_2level_tapbuf_size2_mem_7_ccff_tail ) , @@ -22757,7 +24519,7 @@ sb_2__2__mux_2level_tapbuf_size3_mem mem_left_track_53 ( .pReset ( pReset ) , .ccff_tail ( mux_2level_tapbuf_size3_mem_3_ccff_tail ) , .mem_out ( mux_2level_tapbuf_size3_3_sram ) ) ; sky130_fd_sc_hd__buf_8 pReset_FTB00 ( .A ( pReset_W_in ) , .X ( pReset[0] ) ) ; -sky130_fd_sc_hd__buf_8 prog_clk_0_FTB00 ( .A ( prog_clk_0_S_in ) , +sky130_fd_sc_hd__buf_1 prog_clk_0_FTB00 ( .A ( prog_clk_0_S_in ) , .X ( prog_clk[0] ) ) ; sky130_fd_sc_hd__buf_8 FTB_78__77 ( .A ( chanx_left_in[0] ) , .X ( chany_bottom_out[29] ) ) ; @@ -22774,18 +24536,14 @@ sky130_fd_sc_hd__buf_8 FTB_83__82 ( .A ( chanx_left_in[28] ) , sky130_fd_sc_hd__buf_8 FTB_84__83 ( .A ( chanx_left_in[29] ) , .X ( chany_bottom_out[28] ) ) ; sky130_fd_sc_hd__buf_6 FTB_85__84 ( .A ( SC_IN_BOT ) , .X ( SC_OUT_BOT ) ) ; -sky130_fd_sc_hd__conb_1 optlc_176 ( .LO ( SYNOPSYS_UNCONNECTED_131 ) , - .HI ( optlc_net_174 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_178 ( .LO ( SYNOPSYS_UNCONNECTED_132 ) , - .HI ( optlc_net_175 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_181 ( .LO ( SYNOPSYS_UNCONNECTED_133 ) , - .HI ( optlc_net_176 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_184 ( .LO ( SYNOPSYS_UNCONNECTED_134 ) , - .HI ( optlc_net_177 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_186 ( .LO ( SYNOPSYS_UNCONNECTED_135 ) , - .HI ( optlc_net_178 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_188 ( .LO ( SYNOPSYS_UNCONNECTED_136 ) , - .HI ( optlc_net_179 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_162 ( .LO ( SYNOPSYS_UNCONNECTED_131 ) , + .HI ( optlc_net_160 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_164 ( .LO ( SYNOPSYS_UNCONNECTED_132 ) , + .HI ( optlc_net_161 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_166 ( .LO ( SYNOPSYS_UNCONNECTED_133 ) , + .HI ( optlc_net_162 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_168 ( .LO ( SYNOPSYS_UNCONNECTED_134 ) , + .HI ( optlc_net_163 ) ) ; endmodule @@ -23030,7 +24788,7 @@ input [0:0] mem_inv ; output [0:0] out ; input p0 ; -sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , +sky130_fd_sc_hd__mux2_2 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ; endmodule @@ -23074,9 +24832,8 @@ sb_2__1__mux_2level_tapbuf_basis_input2_mem1_33 mux_l2_in_0_ ( .mem ( sram[1] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_4 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_194 ( .A ( BUF_net_195 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_195 ( - .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_195 ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_182 ( + .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) ) ; endmodule @@ -23189,7 +24946,7 @@ sb_2__1__mux_2level_tapbuf_basis_input2_mem1_29 mux_l2_in_0_ ( .mem ( sram[1] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_4 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_193 ( +sky130_fd_sc_hd__buf_6 BUFT_RR_181 ( .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) ) ; endmodule @@ -23202,7 +24959,7 @@ input [0:0] mem_inv ; output [0:0] out ; input p0 ; -sky130_fd_sc_hd__mux2_2 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , +sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ; endmodule @@ -23236,6 +24993,8 @@ wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ; sb_2__1__const1_43 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) ) ; sb_2__1__mux_2level_tapbuf_basis_input2_mem1_26 mux_l1_in_0_ ( .in ( in ) , .mem ( sram[0] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_2 } ) , @@ -23246,8 +25005,6 @@ sb_2__1__mux_2level_tapbuf_basis_input2_mem1_27 mux_l2_in_0_ ( .mem ( sram[1] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_4 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_192 ( - .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) ) ; endmodule @@ -23259,7 +25016,7 @@ input [0:0] mem_inv ; output [0:0] out ; input p0 ; -sky130_fd_sc_hd__mux2_2 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , +sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ; endmodule @@ -23293,6 +25050,8 @@ wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ; sb_2__1__const1_42 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) ) ; sb_2__1__mux_2level_tapbuf_basis_input2_mem1_24 mux_l1_in_0_ ( .in ( in ) , .mem ( sram[0] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_2 } ) , @@ -23303,8 +25062,6 @@ sb_2__1__mux_2level_tapbuf_basis_input2_mem1_25 mux_l2_in_0_ ( .mem ( sram[1] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_4 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_191 ( - .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) ) ; endmodule @@ -23445,7 +25202,7 @@ input [0:0] mem ; input [0:0] mem_inv ; output [0:0] out ; -sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) , +sky130_fd_sc_hd__mux2_2 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ; endmodule @@ -23493,8 +25250,6 @@ wire [0:0] mux_2level_tapbuf_basis_input2_mem1_2_out ; sb_2__1__const1_41 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( mux_2level_tapbuf_basis_input2_mem1_2_out[0] ) , .X ( out[0] ) ) ; sb_2__1__mux_2level_tapbuf_basis_input2_mem1_21 mux_l1_in_0_ ( .in ( in[0:1] ) , .mem ( sram[0] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_2 } ) , @@ -23510,6 +25265,8 @@ sb_2__1__mux_2level_tapbuf_basis_input2_mem1_23 mux_l2_in_0_ ( .mem ( sram[1] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_5 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_2_out ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_180 ( + .A ( mux_2level_tapbuf_basis_input2_mem1_2_out[0] ) , .X ( out[0] ) ) ; endmodule @@ -23595,7 +25352,7 @@ input [0:0] mem ; input [0:0] mem_inv ; output [0:0] out ; -sky130_fd_sc_hd__mux2_2 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) , +sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ; endmodule @@ -23658,8 +25415,9 @@ sb_2__1__mux_2level_tapbuf_basis_input2_mem1_17 mux_l2_in_0_ ( .mem ( sram[1] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_5 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_2_out ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_190 ( - .A ( mux_2level_tapbuf_basis_input2_mem1_2_out[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_178 ( .A ( BUF_net_179 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_179 ( + .A ( mux_2level_tapbuf_basis_input2_mem1_2_out[0] ) , .Y ( BUF_net_179 ) ) ; endmodule @@ -23718,8 +25476,6 @@ wire [0:0] mux_2level_tapbuf_basis_input2_mem1_2_out ; sb_2__1__const1_38 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( mux_2level_tapbuf_basis_input2_mem1_2_out[0] ) , .X ( out[0] ) ) ; sb_2__1__mux_2level_tapbuf_basis_input2_mem1_12 mux_l1_in_0_ ( .in ( in[0:1] ) , .mem ( sram[0] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_2 } ) , @@ -23735,6 +25491,8 @@ sb_2__1__mux_2level_tapbuf_basis_input2_mem1_14 mux_l2_in_0_ ( .mem ( sram[1] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_5 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_2_out ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_177 ( + .A ( mux_2level_tapbuf_basis_input2_mem1_2_out[0] ) , .X ( out[0] ) ) ; endmodule @@ -23745,7 +25503,7 @@ input [0:0] mem ; input [0:0] mem_inv ; output [0:0] out ; -sky130_fd_sc_hd__mux2_2 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) , +sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ; endmodule @@ -23793,7 +25551,7 @@ wire [0:0] mux_2level_tapbuf_basis_input2_mem1_2_out ; sb_2__1__const1_37 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( mux_2level_tapbuf_basis_input2_mem1_2_out[0] ) , .X ( out[0] ) ) ; sb_2__1__mux_2level_tapbuf_basis_input2_mem1_9 mux_l1_in_0_ ( .in ( in[0:1] ) , .mem ( sram[0] ) , @@ -23820,7 +25578,7 @@ input [0:0] mem ; input [0:0] mem_inv ; output [0:0] out ; -sky130_fd_sc_hd__mux2_2 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) , +sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ; endmodule @@ -23868,8 +25626,6 @@ wire [0:0] mux_2level_tapbuf_basis_input2_mem1_2_out ; sb_2__1__const1_36 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( mux_2level_tapbuf_basis_input2_mem1_2_out[0] ) , .X ( out[0] ) ) ; sb_2__1__mux_2level_tapbuf_basis_input2_mem1_6 mux_l1_in_0_ ( .in ( in[0:1] ) , .mem ( sram[0] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_2 } ) , @@ -23885,6 +25641,9 @@ sb_2__1__mux_2level_tapbuf_basis_input2_mem1_8 mux_l2_in_0_ ( .mem ( sram[1] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_5 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_2_out ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_175 ( .A ( BUF_net_176 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_176 ( + .A ( mux_2level_tapbuf_basis_input2_mem1_2_out[0] ) , .Y ( BUF_net_176 ) ) ; endmodule @@ -23895,7 +25654,7 @@ input [0:0] mem ; input [0:0] mem_inv ; output [0:0] out ; -sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) , +sky130_fd_sc_hd__mux2_2 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ; endmodule @@ -24206,10 +25965,14 @@ input [0:2] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -24220,10 +25983,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -24296,9 +26063,9 @@ sb_2__1__mux_2level_tapbuf_basis_input3_mem3 mux_l2_in_0_ ( .mem ( local_encoder2to3_1_data ) , .mem_inv ( local_encoder2to3_1_data_inv ) , .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_188 ( .A ( BUF_net_189 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_189 ( - .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_189 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_173 ( .A ( BUF_net_174 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_174 ( + .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_174 ) ) ; endmodule @@ -24310,10 +26077,14 @@ input [0:2] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -24324,10 +26095,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -24384,6 +26159,8 @@ wire [0:0] mux_2level_tapbuf_basis_input3_mem3_1_out ; sb_2__1__const1_32 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .X ( out[0] ) ) ; sb_2__1__local_encoder2to3_56 local_encoder2to3_0_ ( .addr ( sram[0:1] ) , .data ( local_encoder2to3_0_data ) , .data_inv ( local_encoder2to3_0_data_inv ) ) ; @@ -24400,9 +26177,6 @@ sb_2__1__mux_2level_tapbuf_basis_input3_mem3_77 mux_l2_in_0_ ( .mem ( local_encoder2to3_1_data ) , .mem_inv ( local_encoder2to3_1_data_inv ) , .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_186 ( .A ( BUF_net_187 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_187 ( - .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_187 ) ) ; endmodule @@ -24414,10 +26188,14 @@ input [0:2] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -24428,10 +26206,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -24488,8 +26270,6 @@ wire [0:0] mux_2level_tapbuf_basis_input3_mem3_1_out ; sb_2__1__const1_31 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .X ( out[0] ) ) ; sb_2__1__local_encoder2to3_54 local_encoder2to3_0_ ( .addr ( sram[0:1] ) , .data ( local_encoder2to3_0_data ) , .data_inv ( local_encoder2to3_0_data_inv ) ) ; @@ -24506,6 +26286,9 @@ sb_2__1__mux_2level_tapbuf_basis_input3_mem3_75 mux_l2_in_0_ ( .mem ( local_encoder2to3_1_data ) , .mem_inv ( local_encoder2to3_1_data_inv ) , .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .p0 ( p0 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_171 ( .A ( BUF_net_172 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_172 ( + .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_172 ) ) ; endmodule @@ -24517,10 +26300,14 @@ input [0:2] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -24531,10 +26318,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -24607,9 +26398,8 @@ sb_2__1__mux_2level_tapbuf_basis_input3_mem3_73 mux_l2_in_0_ ( .mem ( local_encoder2to3_1_data ) , .mem_inv ( local_encoder2to3_1_data_inv ) , .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_184 ( .A ( BUF_net_185 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_185 ( - .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_185 ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_170 ( + .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .X ( out[0] ) ) ; endmodule @@ -24621,10 +26411,14 @@ input [0:2] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -24635,10 +26429,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -24711,9 +26509,9 @@ sb_2__1__mux_2level_tapbuf_basis_input3_mem3_71 mux_l2_in_0_ ( .mem ( local_encoder2to3_1_data ) , .mem_inv ( local_encoder2to3_1_data_inv ) , .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_182 ( .A ( BUF_net_183 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_183 ( - .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_183 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_168 ( .A ( BUF_net_169 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_169 ( + .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_169 ) ) ; endmodule @@ -24725,10 +26523,14 @@ input [0:2] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -24739,10 +26541,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -24799,6 +26605,8 @@ wire [0:0] mux_2level_tapbuf_basis_input3_mem3_1_out ; sb_2__1__const1_28 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .X ( out[0] ) ) ; sb_2__1__local_encoder2to3_48 local_encoder2to3_0_ ( .addr ( sram[0:1] ) , .data ( local_encoder2to3_0_data ) , .data_inv ( local_encoder2to3_0_data_inv ) ) ; @@ -24815,9 +26623,6 @@ sb_2__1__mux_2level_tapbuf_basis_input3_mem3_69 mux_l2_in_0_ ( .mem ( local_encoder2to3_1_data ) , .mem_inv ( local_encoder2to3_1_data_inv ) , .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_180 ( .A ( BUF_net_181 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_181 ( - .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_181 ) ) ; endmodule @@ -24829,10 +26634,14 @@ input [0:2] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -24843,10 +26652,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -24919,9 +26732,8 @@ sb_2__1__mux_2level_tapbuf_basis_input3_mem3_67 mux_l2_in_0_ ( .mem ( local_encoder2to3_1_data ) , .mem_inv ( local_encoder2to3_1_data_inv ) , .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_178 ( .A ( BUF_net_179 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_179 ( - .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_179 ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_167 ( + .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .X ( out[0] ) ) ; endmodule @@ -24933,10 +26745,14 @@ input [0:2] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -24947,10 +26763,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -25007,6 +26827,8 @@ wire [0:0] mux_2level_tapbuf_basis_input3_mem3_1_out ; sb_2__1__const1_26 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .X ( out[0] ) ) ; sb_2__1__local_encoder2to3_44 local_encoder2to3_0_ ( .addr ( sram[0:1] ) , .data ( local_encoder2to3_0_data ) , .data_inv ( local_encoder2to3_0_data_inv ) ) ; @@ -25023,9 +26845,6 @@ sb_2__1__mux_2level_tapbuf_basis_input3_mem3_65 mux_l2_in_0_ ( .mem ( local_encoder2to3_1_data ) , .mem_inv ( local_encoder2to3_1_data_inv ) , .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_176 ( .A ( BUF_net_177 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_177 ( - .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_177 ) ) ; endmodule @@ -25137,10 +26956,14 @@ input [0:2] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -25151,10 +26974,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -25165,10 +26992,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -25226,8 +27057,6 @@ wire [0:0] mux_2level_tapbuf_basis_input3_mem3_2_out ; sb_2__1__const1_25 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( mux_2level_tapbuf_basis_input3_mem3_2_out[0] ) , .X ( out[0] ) ) ; sb_2__1__local_encoder2to3_42 local_encoder2to3_0_ ( .addr ( sram[0:1] ) , .data ( local_encoder2to3_0_data ) , .data_inv ( local_encoder2to3_0_data_inv ) ) ; @@ -25249,6 +27078,9 @@ sb_2__1__mux_2level_tapbuf_basis_input3_mem3_63 mux_l2_in_0_ ( .mem ( local_encoder2to3_1_data ) , .mem_inv ( local_encoder2to3_1_data_inv ) , .out ( mux_2level_tapbuf_basis_input3_mem3_2_out ) , .p0 ( p0 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_165 ( .A ( BUF_net_166 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_166 ( + .A ( mux_2level_tapbuf_basis_input3_mem3_2_out[0] ) , .Y ( BUF_net_166 ) ) ; endmodule @@ -25260,10 +27092,14 @@ input [0:2] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -25274,10 +27110,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -25288,10 +27128,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -25370,9 +27214,9 @@ sb_2__1__mux_2level_tapbuf_basis_input3_mem3_60 mux_l2_in_0_ ( .mem ( local_encoder2to3_1_data ) , .mem_inv ( local_encoder2to3_1_data_inv ) , .out ( mux_2level_tapbuf_basis_input3_mem3_2_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_174 ( .A ( BUF_net_175 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_175 ( - .A ( mux_2level_tapbuf_basis_input3_mem3_2_out[0] ) , .Y ( BUF_net_175 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_163 ( .A ( BUF_net_164 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_164 ( + .A ( mux_2level_tapbuf_basis_input3_mem3_2_out[0] ) , .Y ( BUF_net_164 ) ) ; endmodule @@ -25384,10 +27228,14 @@ input [0:2] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -25398,10 +27246,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -25412,10 +27264,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -25507,10 +27363,14 @@ input [0:2] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -25521,10 +27381,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -25535,10 +27399,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -25630,10 +27498,14 @@ input [0:2] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -25644,10 +27516,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -25658,10 +27534,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -25740,9 +27620,9 @@ sb_2__1__mux_2level_tapbuf_basis_input3_mem3_51 mux_l2_in_0_ ( .mem ( local_encoder2to3_1_data ) , .mem_inv ( local_encoder2to3_1_data_inv ) , .out ( mux_2level_tapbuf_basis_input3_mem3_2_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_172 ( .A ( BUF_net_173 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_173 ( - .A ( mux_2level_tapbuf_basis_input3_mem3_2_out[0] ) , .Y ( BUF_net_173 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_185 ( .A ( BUF_net_186 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_186 ( + .A ( mux_2level_tapbuf_basis_input3_mem3_2_out[0] ) , .Y ( BUF_net_186 ) ) ; endmodule @@ -25773,9 +27653,13 @@ input [0:1] mem ; input [0:1] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -25787,12 +27671,18 @@ input [0:3] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -25803,12 +27693,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -25819,12 +27715,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -25892,8 +27794,7 @@ wire [0:0] mux_2level_tapbuf_basis_input4_mem4_2_out ; sb_2__1__const1_20 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_4_0_ ( - .A ( mux_2level_tapbuf_basis_input4_mem4_2_out[0] ) , - .X ( aps_rename_507_ ) ) ; + .A ( mux_2level_tapbuf_basis_input4_mem4_2_out[0] ) , .X ( net_net_162 ) ) ; sb_2__1__local_encoder2to4_6 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , .data ( local_encoder2to4_0_data ) , .data_inv ( local_encoder2to4_0_data_inv ) ) ; @@ -25920,9 +27821,7 @@ sb_2__1__mux_2level_tapbuf_basis_input2_mem2 mux_l1_in_2_ ( .in ( in[8:9] ) , .mem ( local_encoder2to4_0_data[0:1] ) , .mem_inv ( local_encoder2to4_0_data_inv[0:1] ) , .out ( mux_2level_tapbuf_basis_input2_mem2_0_out ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_170 ( .A ( BUF_net_171 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_171 ( .A ( aps_rename_507_ ) , - .Y ( BUF_net_171 ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_162 ( .A ( net_net_162 ) , .X ( out[0] ) ) ; endmodule @@ -26053,9 +27952,13 @@ input [0:1] mem ; input [0:1] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -26067,10 +27970,14 @@ input [0:2] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -26081,10 +27988,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -26142,6 +28053,8 @@ wire [0:0] mux_2level_tapbuf_basis_input3_mem3_1_out ; sb_2__1__const1_19 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .X ( out[0] ) ) ; sb_2__1__local_encoder2to3_32 local_encoder2to3_0_ ( .addr ( sram[0:1] ) , .data ( local_encoder2to3_0_data ) , .data_inv ( local_encoder2to3_0_data_inv ) ) ; @@ -26163,8 +28076,6 @@ sb_2__1__mux_2level_tapbuf_basis_input2_mem2_12 mux_l1_in_1_ ( .in ( in[3:4] ) , .mem ( local_encoder2to3_0_data[0:1] ) , .mem_inv ( local_encoder2to3_0_data_inv[0:1] ) , .out ( mux_2level_tapbuf_basis_input2_mem2_0_out ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_169 ( - .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .X ( out[0] ) ) ; endmodule @@ -26175,9 +28086,13 @@ input [0:1] mem ; input [0:1] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -26189,10 +28104,14 @@ input [0:2] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -26203,10 +28122,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -26285,9 +28208,9 @@ sb_2__1__mux_2level_tapbuf_basis_input2_mem2_11 mux_l1_in_1_ ( .in ( in[3:4] ) , .mem ( local_encoder2to3_0_data[0:1] ) , .mem_inv ( local_encoder2to3_0_data_inv[0:1] ) , .out ( mux_2level_tapbuf_basis_input2_mem2_0_out ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_167 ( .A ( BUF_net_168 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_168 ( - .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_168 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_160 ( .A ( BUF_net_161 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_161 ( + .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_161 ) ) ; endmodule @@ -26298,9 +28221,13 @@ input [0:1] mem ; input [0:1] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -26312,10 +28239,14 @@ input [0:2] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -26326,10 +28257,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -26408,9 +28343,9 @@ sb_2__1__mux_2level_tapbuf_basis_input2_mem2_10 mux_l1_in_1_ ( .in ( in[3:4] ) , .mem ( local_encoder2to3_0_data[0:1] ) , .mem_inv ( local_encoder2to3_0_data_inv[0:1] ) , .out ( mux_2level_tapbuf_basis_input2_mem2_0_out ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_165 ( .A ( BUF_net_166 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_166 ( - .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_166 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_158 ( .A ( BUF_net_159 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_159 ( + .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_159 ) ) ; endmodule @@ -26421,9 +28356,13 @@ input [0:1] mem ; input [0:1] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -26435,10 +28374,14 @@ input [0:2] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -26449,10 +28392,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -26510,6 +28457,8 @@ wire [0:0] mux_2level_tapbuf_basis_input3_mem3_1_out ; sb_2__1__const1_16 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .X ( out[0] ) ) ; sb_2__1__local_encoder2to3_26 local_encoder2to3_0_ ( .addr ( sram[0:1] ) , .data ( local_encoder2to3_0_data ) , .data_inv ( local_encoder2to3_0_data_inv ) ) ; @@ -26531,8 +28480,6 @@ sb_2__1__mux_2level_tapbuf_basis_input2_mem2_9 mux_l1_in_1_ ( .in ( in[3:4] ) , .mem ( local_encoder2to3_0_data[0:1] ) , .mem_inv ( local_encoder2to3_0_data_inv[0:1] ) , .out ( mux_2level_tapbuf_basis_input2_mem2_0_out ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_164 ( - .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .X ( out[0] ) ) ; endmodule @@ -26543,9 +28490,13 @@ input [0:1] mem ; input [0:1] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -26557,10 +28508,14 @@ input [0:2] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -26571,10 +28526,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -26653,9 +28612,9 @@ sb_2__1__mux_2level_tapbuf_basis_input2_mem2_8 mux_l1_in_1_ ( .in ( in[3:4] ) , .mem ( local_encoder2to3_0_data[0:1] ) , .mem_inv ( local_encoder2to3_0_data_inv[0:1] ) , .out ( mux_2level_tapbuf_basis_input2_mem2_0_out ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_162 ( .A ( BUF_net_163 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_163 ( - .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_163 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_156 ( .A ( BUF_net_157 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_157 ( + .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_157 ) ) ; endmodule @@ -26666,9 +28625,13 @@ input [0:1] mem ; input [0:1] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -26680,10 +28643,14 @@ input [0:2] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -26694,10 +28661,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -26755,8 +28726,6 @@ wire [0:0] mux_2level_tapbuf_basis_input3_mem3_1_out ; sb_2__1__const1_14 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .X ( out[0] ) ) ; sb_2__1__local_encoder2to3_22 local_encoder2to3_0_ ( .addr ( sram[0:1] ) , .data ( local_encoder2to3_0_data ) , .data_inv ( local_encoder2to3_0_data_inv ) ) ; @@ -26778,6 +28747,9 @@ sb_2__1__mux_2level_tapbuf_basis_input2_mem2_7 mux_l1_in_1_ ( .in ( in[3:4] ) , .mem ( local_encoder2to3_0_data[0:1] ) , .mem_inv ( local_encoder2to3_0_data_inv[0:1] ) , .out ( mux_2level_tapbuf_basis_input2_mem2_0_out ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_154 ( .A ( BUF_net_155 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_155 ( + .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_155 ) ) ; endmodule @@ -26849,12 +28821,18 @@ input [0:3] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -26865,12 +28843,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -26881,12 +28865,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -26952,9 +28942,8 @@ wire [0:0] mux_2level_tapbuf_basis_input4_mem4_2_out ; sb_2__1__const1_13 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_4_0_ ( - .A ( mux_2level_tapbuf_basis_input4_mem4_2_out[0] ) , - .X ( aps_rename_506_ ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( mux_2level_tapbuf_basis_input4_mem4_2_out[0] ) , .X ( out[0] ) ) ; sb_2__1__local_encoder2to4_4 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , .data ( local_encoder2to4_0_data ) , .data_inv ( local_encoder2to4_0_data_inv ) ) ; @@ -26976,9 +28965,6 @@ sb_2__1__mux_2level_tapbuf_basis_input4_mem4_8 mux_l2_in_0_ ( .mem ( local_encoder2to4_1_data ) , .mem_inv ( local_encoder2to4_1_data_inv ) , .out ( mux_2level_tapbuf_basis_input4_mem4_2_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_160 ( .A ( BUF_net_161 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_161 ( .A ( aps_rename_506_ ) , - .Y ( BUF_net_161 ) ) ; endmodule @@ -26990,12 +28976,18 @@ input [0:3] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -27006,12 +28998,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -27022,12 +29020,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -27093,7 +29097,7 @@ wire [0:0] mux_2level_tapbuf_basis_input4_mem4_2_out ; sb_2__1__const1_12 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__bufbuf_16 sky130_fd_sc_hd__buf_4_0_ ( +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( mux_2level_tapbuf_basis_input4_mem4_2_out[0] ) , .X ( out[0] ) ) ; sb_2__1__local_encoder2to4_2 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , .data ( local_encoder2to4_0_data ) , @@ -27127,12 +29131,18 @@ input [0:3] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -27143,12 +29153,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -27159,12 +29175,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -27230,9 +29252,8 @@ wire [0:0] mux_2level_tapbuf_basis_input4_mem4_2_out ; sb_2__1__const1_11 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_4_0_ ( - .A ( mux_2level_tapbuf_basis_input4_mem4_2_out[0] ) , - .X ( aps_rename_505_ ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( mux_2level_tapbuf_basis_input4_mem4_2_out[0] ) , .X ( out[0] ) ) ; sb_2__1__local_encoder2to4_0 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , .data ( local_encoder2to4_0_data ) , .data_inv ( local_encoder2to4_0_data_inv ) ) ; @@ -27254,9 +29275,6 @@ sb_2__1__mux_2level_tapbuf_basis_input4_mem4_2 mux_l2_in_0_ ( .mem ( local_encoder2to4_1_data ) , .mem_inv ( local_encoder2to4_1_data_inv ) , .out ( mux_2level_tapbuf_basis_input4_mem4_2_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_158 ( .A ( BUF_net_159 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_159 ( .A ( aps_rename_505_ ) , - .Y ( BUF_net_159 ) ) ; endmodule @@ -27408,9 +29426,13 @@ input [0:1] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( p0 ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -27421,10 +29443,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -27435,10 +29461,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -27449,10 +29479,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -27507,9 +29541,12 @@ wire [0:2] local_encoder2to3_1_data_inv ; wire [0:0] mux_2level_tapbuf_basis_input2_mem2_0_out ; wire [0:0] mux_2level_tapbuf_basis_input3_mem3_0_out ; wire [0:0] mux_2level_tapbuf_basis_input3_mem3_1_out ; +wire [0:0] mux_2level_tapbuf_basis_input3_mem3_2_out ; sb_2__1__const1_10 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( mux_2level_tapbuf_basis_input3_mem3_2_out[0] ) , .X ( out[0] ) ) ; sb_2__1__local_encoder2to3_20 local_encoder2to3_0_ ( .addr ( sram[0:1] ) , .data ( local_encoder2to3_0_data ) , .data_inv ( local_encoder2to3_0_data_inv ) ) ; @@ -27529,7 +29566,8 @@ sb_2__1__mux_2level_tapbuf_basis_input3_mem3_36 mux_l2_in_0_ ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] , mux_2level_tapbuf_basis_input2_mem2_0_out[0] } ) , .mem ( local_encoder2to3_1_data ) , - .mem_inv ( local_encoder2to3_1_data_inv ) , .out ( out ) ) ; + .mem_inv ( local_encoder2to3_1_data_inv ) , + .out ( mux_2level_tapbuf_basis_input3_mem3_2_out ) ) ; sb_2__1__mux_2level_tapbuf_basis_input2_mem2_6 mux_l1_in_2_ ( .in ( { in[6] , SYNOPSYS_UNCONNECTED_2 } ) , .mem ( local_encoder2to3_0_data[0:1] ) , @@ -27546,9 +29584,13 @@ input [0:1] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( p0 ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -27559,10 +29601,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -27573,10 +29619,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -27587,10 +29637,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -27649,6 +29703,8 @@ wire [0:0] mux_2level_tapbuf_basis_input3_mem3_2_out ; sb_2__1__const1_9 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( mux_2level_tapbuf_basis_input3_mem3_2_out[0] ) , .X ( out[0] ) ) ; sb_2__1__local_encoder2to3_18 local_encoder2to3_0_ ( .addr ( sram[0:1] ) , .data ( local_encoder2to3_0_data ) , .data_inv ( local_encoder2to3_0_data_inv ) ) ; @@ -27675,9 +29731,6 @@ sb_2__1__mux_2level_tapbuf_basis_input2_mem2_5 mux_l1_in_2_ ( .mem ( local_encoder2to3_0_data[0:1] ) , .mem_inv ( local_encoder2to3_0_data_inv[0:1] ) , .out ( mux_2level_tapbuf_basis_input2_mem2_0_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_156 ( .A ( BUF_net_157 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_157 ( - .A ( mux_2level_tapbuf_basis_input3_mem3_2_out[0] ) , .Y ( BUF_net_157 ) ) ; endmodule @@ -27689,9 +29742,13 @@ input [0:1] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( p0 ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -27702,10 +29759,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -27716,10 +29777,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -27730,10 +29795,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -27831,9 +29900,13 @@ input [0:1] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( p0 ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -27844,10 +29917,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -27858,10 +29935,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -27872,10 +29953,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -27973,9 +30058,13 @@ input [0:1] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( p0 ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -27986,10 +30075,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -28000,10 +30093,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -28014,10 +30111,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -28076,8 +30177,6 @@ wire [0:0] mux_2level_tapbuf_basis_input3_mem3_2_out ; sb_2__1__const1_6 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( mux_2level_tapbuf_basis_input3_mem3_2_out[0] ) , .X ( out[0] ) ) ; sb_2__1__local_encoder2to3_12 local_encoder2to3_0_ ( .addr ( sram[0:1] ) , .data ( local_encoder2to3_0_data ) , .data_inv ( local_encoder2to3_0_data_inv ) ) ; @@ -28104,6 +30203,9 @@ sb_2__1__mux_2level_tapbuf_basis_input2_mem2_2 mux_l1_in_2_ ( .mem ( local_encoder2to3_0_data[0:1] ) , .mem_inv ( local_encoder2to3_0_data_inv[0:1] ) , .out ( mux_2level_tapbuf_basis_input2_mem2_0_out ) , .p0 ( p0 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_152 ( .A ( BUF_net_153 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_153 ( + .A ( mux_2level_tapbuf_basis_input3_mem3_2_out[0] ) , .Y ( BUF_net_153 ) ) ; endmodule @@ -28115,9 +30217,13 @@ input [0:1] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( p0 ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -28128,10 +30234,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -28142,10 +30252,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -28156,10 +30270,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -28257,9 +30375,13 @@ input [0:1] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( p0 ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -28270,10 +30392,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -28284,10 +30410,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -28298,10 +30428,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -28459,7 +30593,7 @@ input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ropt_net_226 ) , +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ropt_net_208 ) , .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; @@ -28468,30 +30602,28 @@ sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__buf_1 FTB_9__8 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1392 ( .A ( ccff_head[0] ) , - .X ( copt_net_204 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1393 ( .A ( copt_net_204 ) , - .X ( copt_net_205 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1394 ( .A ( ropt_net_227 ) , - .X ( copt_net_206 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1395 ( .A ( copt_net_205 ) , - .X ( copt_net_207 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1396 ( .A ( copt_net_207 ) , - .X ( copt_net_208 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1397 ( .A ( copt_net_208 ) , - .X ( copt_net_209 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1409 ( .A ( ropt_net_225 ) , - .X ( ropt_net_222 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1410 ( .A ( ropt_net_222 ) , - .X ( ropt_net_223 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1411 ( .A ( ropt_net_223 ) , - .X ( ropt_net_224 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 ropt_h_inst_1412 ( .A ( copt_net_206 ) , - .X ( ropt_net_225 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 ropt_h_inst_1413 ( .A ( ropt_net_224 ) , - .X ( ropt_net_226 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1414 ( .A ( copt_net_209 ) , - .X ( ropt_net_227 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1381 ( .A ( copt_net_195 ) , + .X ( copt_net_193 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1382 ( .A ( copt_net_193 ) , + .X ( copt_net_194 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1383 ( .A ( ccff_head[0] ) , + .X ( copt_net_195 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1384 ( .A ( copt_net_198 ) , + .X ( copt_net_196 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1385 ( .A ( copt_net_194 ) , + .X ( copt_net_197 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 copt_h_inst_1386 ( .A ( ropt_net_210 ) , + .X ( copt_net_198 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1397 ( .A ( copt_net_196 ) , + .X ( ropt_net_206 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1398 ( .A ( ropt_net_206 ) , + .X ( ropt_net_207 ) ) ; +sky130_fd_sc_hd__buf_2 ropt_h_inst_1399 ( .A ( ropt_net_207 ) , + .X ( ropt_net_208 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1400 ( .A ( copt_net_197 ) , + .X ( ropt_net_209 ) ) ; +sky130_fd_sc_hd__buf_1 ropt_h_inst_1401 ( .A ( ropt_net_209 ) , + .X ( ropt_net_210 ) ) ; endmodule @@ -28502,10 +30634,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -28517,10 +30653,14 @@ input [0:2] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -28531,10 +30671,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -28545,10 +30689,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -28607,6 +30755,8 @@ wire [0:0] mux_2level_tapbuf_basis_input3_mem3_3_out ; sb_2__1__const1_3 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( mux_2level_tapbuf_basis_input3_mem3_3_out[0] ) , .X ( out[0] ) ) ; sb_2__1__local_encoder2to3_6 local_encoder2to3_0_ ( .addr ( sram[0:1] ) , .data ( local_encoder2to3_0_data ) , .data_inv ( local_encoder2to3_0_data_inv ) ) ; @@ -28633,9 +30783,6 @@ sb_2__1__mux_2level_tapbuf_basis_input3_mem3_15 mux_l2_in_0_ ( .mem ( local_encoder2to3_1_data ) , .mem_inv ( local_encoder2to3_1_data_inv ) , .out ( mux_2level_tapbuf_basis_input3_mem3_3_out ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_154 ( .A ( BUF_net_155 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_155 ( - .A ( mux_2level_tapbuf_basis_input3_mem3_3_out[0] ) , .Y ( BUF_net_155 ) ) ; endmodule @@ -28646,10 +30793,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -28661,10 +30812,14 @@ input [0:2] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -28675,10 +30830,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -28689,10 +30848,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -28751,6 +30914,8 @@ wire [0:0] mux_2level_tapbuf_basis_input3_mem3_3_out ; sb_2__1__const1_2 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( mux_2level_tapbuf_basis_input3_mem3_3_out[0] ) , .X ( out[0] ) ) ; sb_2__1__local_encoder2to3_4 local_encoder2to3_0_ ( .addr ( sram[0:1] ) , .data ( local_encoder2to3_0_data ) , .data_inv ( local_encoder2to3_0_data_inv ) ) ; @@ -28777,9 +30942,6 @@ sb_2__1__mux_2level_tapbuf_basis_input3_mem3_11 mux_l2_in_0_ ( .mem ( local_encoder2to3_1_data ) , .mem_inv ( local_encoder2to3_1_data_inv ) , .out ( mux_2level_tapbuf_basis_input3_mem3_3_out ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_152 ( .A ( BUF_net_153 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_153 ( - .A ( mux_2level_tapbuf_basis_input3_mem3_3_out[0] ) , .Y ( BUF_net_153 ) ) ; endmodule @@ -28790,10 +30952,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -28805,10 +30971,14 @@ input [0:2] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -28819,10 +30989,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -28833,10 +31007,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -28895,6 +31073,8 @@ wire [0:0] mux_2level_tapbuf_basis_input3_mem3_3_out ; sb_2__1__const1_1 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( mux_2level_tapbuf_basis_input3_mem3_3_out[0] ) , .X ( out[0] ) ) ; sb_2__1__local_encoder2to3_2 local_encoder2to3_0_ ( .addr ( sram[0:1] ) , .data ( local_encoder2to3_0_data ) , .data_inv ( local_encoder2to3_0_data_inv ) ) ; @@ -28921,9 +31101,6 @@ sb_2__1__mux_2level_tapbuf_basis_input3_mem3_7 mux_l2_in_0_ ( .mem ( local_encoder2to3_1_data ) , .mem_inv ( local_encoder2to3_1_data_inv ) , .out ( mux_2level_tapbuf_basis_input3_mem3_3_out ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_150 ( .A ( BUF_net_151 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_151 ( - .A ( mux_2level_tapbuf_basis_input3_mem3_3_out[0] ) , .Y ( BUF_net_151 ) ) ; endmodule @@ -28934,10 +31111,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -28949,10 +31130,14 @@ input [0:2] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -28963,10 +31148,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -28977,10 +31166,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -29039,8 +31232,6 @@ wire [0:0] mux_2level_tapbuf_basis_input3_mem3_3_out ; sb_2__1__const1_0 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( mux_2level_tapbuf_basis_input3_mem3_3_out[0] ) , .X ( out[0] ) ) ; sb_2__1__local_encoder2to3_0 local_encoder2to3_0_ ( .addr ( sram[0:1] ) , .data ( local_encoder2to3_0_data ) , .data_inv ( local_encoder2to3_0_data_inv ) ) ; @@ -29067,6 +31258,9 @@ sb_2__1__mux_2level_tapbuf_basis_input3_mem3_3 mux_l2_in_0_ ( .mem ( local_encoder2to3_1_data ) , .mem_inv ( local_encoder2to3_1_data_inv ) , .out ( mux_2level_tapbuf_basis_input3_mem3_3_out ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_150 ( .A ( BUF_net_151 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_151 ( + .A ( mux_2level_tapbuf_basis_input3_mem3_3_out[0] ) , .Y ( BUF_net_151 ) ) ; endmodule @@ -29124,8 +31318,8 @@ input pReset_W_in ; output pReset_N_out ; input prog_clk_0_N_in ; -wire ropt_net_217 ; -wire ZBUF_74_0 ; +wire ZBUF_250_f_0 ; +wire ZBUF_263_f_0 ; wire [0:0] prog_clk ; wire prog_clk_0 ; wire [0:3] mux_2level_tapbuf_size10_0_sram ; @@ -29235,7 +31429,7 @@ sb_2__1__mux_2level_tapbuf_size8_0 mux_top_track_0 ( .sram ( mux_2level_tapbuf_size8_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 , SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) , - .out ( chany_top_out[0] ) , .p0 ( optlc_net_202 ) ) ; + .out ( chany_top_out[0] ) , .p0 ( optlc_net_192 ) ) ; sb_2__1__mux_2level_tapbuf_size8_1 mux_bottom_track_1 ( .in ( { chany_bottom_out[4] , chany_bottom_out[20] , bottom_right_grid_pin_1_[0] , bottom_left_grid_pin_46_[0] , @@ -29244,7 +31438,7 @@ sb_2__1__mux_2level_tapbuf_size8_1 mux_bottom_track_1 ( .sram ( mux_2level_tapbuf_size8_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 , SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 } ) , - .out ( chany_bottom_out[0] ) , .p0 ( optlc_net_202 ) ) ; + .out ( chany_bottom_out[0] ) , .p0 ( optlc_net_189 ) ) ; sb_2__1__mux_2level_tapbuf_size8_2 mux_bottom_track_3 ( .in ( { chany_bottom_out[7] , chany_bottom_out[21] , bottom_left_grid_pin_44_[0] , bottom_left_grid_pin_47_[0] , @@ -29253,7 +31447,7 @@ sb_2__1__mux_2level_tapbuf_size8_2 mux_bottom_track_3 ( .sram ( mux_2level_tapbuf_size8_2_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_9 , SYNOPSYS_UNCONNECTED_10 , SYNOPSYS_UNCONNECTED_11 , SYNOPSYS_UNCONNECTED_12 } ) , - .out ( chany_bottom_out[1] ) , .p0 ( optlc_net_199 ) ) ; + .out ( chany_bottom_out[1] ) , .p0 ( optlc_net_189 ) ) ; sb_2__1__mux_2level_tapbuf_size8 mux_bottom_track_5 ( .in ( { chany_bottom_out[8] , chany_bottom_out[23] , bottom_left_grid_pin_45_[0] , bottom_left_grid_pin_48_[0] , @@ -29262,7 +31456,7 @@ sb_2__1__mux_2level_tapbuf_size8 mux_bottom_track_5 ( .sram ( mux_2level_tapbuf_size8_3_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 , SYNOPSYS_UNCONNECTED_15 , SYNOPSYS_UNCONNECTED_16 } ) , - .out ( chany_bottom_out[2] ) , .p0 ( optlc_net_202 ) ) ; + .out ( chany_bottom_out[2] ) , .p0 ( optlc_net_189 ) ) ; sb_2__1__mux_2level_tapbuf_size8_mem_0 mem_top_track_0 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( mux_2level_tapbuf_size8_mem_0_ccff_tail ) , @@ -29289,7 +31483,7 @@ sb_2__1__mux_2level_tapbuf_size7_0 mux_top_track_2 ( .sram ( mux_2level_tapbuf_size7_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_17 , SYNOPSYS_UNCONNECTED_18 , SYNOPSYS_UNCONNECTED_19 , SYNOPSYS_UNCONNECTED_20 } ) , - .out ( chany_top_out[1] ) , .p0 ( optlc_net_202 ) ) ; + .out ( chany_top_out[1] ) , .p0 ( optlc_net_192 ) ) ; sb_2__1__mux_2level_tapbuf_size7_1 mux_top_track_4 ( .in ( { top_left_grid_pin_46_[0] , top_left_grid_pin_49_[0] , top_right_grid_pin_1_[0] , chany_top_out[8] , chany_top_out[23] , @@ -29297,7 +31491,7 @@ sb_2__1__mux_2level_tapbuf_size7_1 mux_top_track_4 ( .sram ( mux_2level_tapbuf_size7_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_21 , SYNOPSYS_UNCONNECTED_22 , SYNOPSYS_UNCONNECTED_23 , SYNOPSYS_UNCONNECTED_24 } ) , - .out ( chany_top_out[2] ) , .p0 ( optlc_net_201 ) ) ; + .out ( chany_top_out[2] ) , .p0 ( optlc_net_190 ) ) ; sb_2__1__mux_2level_tapbuf_size7_2 mux_top_track_12 ( .in ( { top_left_grid_pin_44_[0] , top_left_grid_pin_50_[0] , chany_top_out[12] , chany_top_out[27] , chanx_left_in[6] , @@ -29305,7 +31499,7 @@ sb_2__1__mux_2level_tapbuf_size7_2 mux_top_track_12 ( .sram ( mux_2level_tapbuf_size7_2_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_25 , SYNOPSYS_UNCONNECTED_26 , SYNOPSYS_UNCONNECTED_27 , SYNOPSYS_UNCONNECTED_28 } ) , - .out ( chany_top_out[6] ) , .p0 ( optlc_net_201 ) ) ; + .out ( chany_top_out[6] ) , .p0 ( optlc_net_190 ) ) ; sb_2__1__mux_2level_tapbuf_size7_3 mux_top_track_20 ( .in ( { top_left_grid_pin_45_[0] , top_left_grid_pin_51_[0] , chany_top_out[13] , chany_top_out[28] , chanx_left_in[5] , @@ -29313,7 +31507,7 @@ sb_2__1__mux_2level_tapbuf_size7_3 mux_top_track_20 ( .sram ( mux_2level_tapbuf_size7_3_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_29 , SYNOPSYS_UNCONNECTED_30 , SYNOPSYS_UNCONNECTED_31 , SYNOPSYS_UNCONNECTED_32 } ) , - .out ( chany_top_out[10] ) , .p0 ( optlc_net_201 ) ) ; + .out ( chany_top_out[10] ) , .p0 ( optlc_net_190 ) ) ; sb_2__1__mux_2level_tapbuf_size7_4 mux_top_track_28 ( .in ( { top_left_grid_pin_46_[0] , top_right_grid_pin_1_[0] , chany_top_out[15] , chany_top_out[29] , chanx_left_in[4] , @@ -29321,7 +31515,7 @@ sb_2__1__mux_2level_tapbuf_size7_4 mux_top_track_28 ( .sram ( mux_2level_tapbuf_size7_4_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_33 , SYNOPSYS_UNCONNECTED_34 , SYNOPSYS_UNCONNECTED_35 , SYNOPSYS_UNCONNECTED_36 } ) , - .out ( chany_top_out[14] ) , .p0 ( optlc_net_202 ) ) ; + .out ( chany_top_out[14] ) , .p0 ( optlc_net_192 ) ) ; sb_2__1__mux_2level_tapbuf_size7_5 mux_bottom_track_13 ( .in ( { chany_bottom_out[12] , chany_bottom_out[27] , bottom_right_grid_pin_1_[0] , bottom_left_grid_pin_49_[0] , @@ -29329,7 +31523,7 @@ sb_2__1__mux_2level_tapbuf_size7_5 mux_bottom_track_13 ( .sram ( mux_2level_tapbuf_size7_5_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_37 , SYNOPSYS_UNCONNECTED_38 , SYNOPSYS_UNCONNECTED_39 , SYNOPSYS_UNCONNECTED_40 } ) , - .out ( chany_bottom_out[6] ) , .p0 ( optlc_net_198 ) ) ; + .out ( chany_bottom_out[6] ) , .p0 ( optlc_net_187 ) ) ; sb_2__1__mux_2level_tapbuf_size7 mux_bottom_track_21 ( .in ( { chany_bottom_out[13] , chany_bottom_out[28] , bottom_left_grid_pin_44_[0] , bottom_left_grid_pin_50_[0] , @@ -29337,8 +31531,7 @@ sb_2__1__mux_2level_tapbuf_size7 mux_bottom_track_21 ( .sram ( mux_2level_tapbuf_size7_6_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_41 , SYNOPSYS_UNCONNECTED_42 , SYNOPSYS_UNCONNECTED_43 , SYNOPSYS_UNCONNECTED_44 } ) , - .out ( { aps_rename_508_ } ) , - .p0 ( optlc_net_198 ) ) ; + .out ( chany_bottom_out[10] ) , .p0 ( optlc_net_187 ) ) ; sb_2__1__mux_2level_tapbuf_size7_mem_0 mem_top_track_2 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( mux_2level_tapbuf_size8_mem_0_ccff_tail ) , @@ -29382,7 +31575,7 @@ sb_2__1__mux_2level_tapbuf_size9_0 mux_top_track_6 ( .sram ( mux_2level_tapbuf_size9_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_45 , SYNOPSYS_UNCONNECTED_46 , SYNOPSYS_UNCONNECTED_47 , SYNOPSYS_UNCONNECTED_48 } ) , - .out ( chany_top_out[3] ) , .p0 ( optlc_net_201 ) ) ; + .out ( chany_top_out[3] ) , .p0 ( optlc_net_190 ) ) ; sb_2__1__mux_2level_tapbuf_size9_1 mux_top_track_10 ( .in ( { top_left_grid_pin_45_[0] , top_left_grid_pin_47_[0] , top_left_grid_pin_49_[0] , top_left_grid_pin_51_[0] , @@ -29391,7 +31584,7 @@ sb_2__1__mux_2level_tapbuf_size9_1 mux_top_track_10 ( .sram ( mux_2level_tapbuf_size9_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_49 , SYNOPSYS_UNCONNECTED_50 , SYNOPSYS_UNCONNECTED_51 , SYNOPSYS_UNCONNECTED_52 } ) , - .out ( chany_top_out[5] ) , .p0 ( optlc_net_201 ) ) ; + .out ( chany_top_out[5] ) , .p0 ( optlc_net_190 ) ) ; sb_2__1__mux_2level_tapbuf_size9 mux_bottom_track_11 ( .in ( { chany_bottom_out[11] , chany_bottom_out[25] , bottom_left_grid_pin_44_[0] , bottom_left_grid_pin_46_[0] , @@ -29400,7 +31593,7 @@ sb_2__1__mux_2level_tapbuf_size9 mux_bottom_track_11 ( .sram ( mux_2level_tapbuf_size9_2_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_53 , SYNOPSYS_UNCONNECTED_54 , SYNOPSYS_UNCONNECTED_55 , SYNOPSYS_UNCONNECTED_56 } ) , - .out ( chany_bottom_out[5] ) , .p0 ( optlc_net_201 ) ) ; + .out ( chany_bottom_out[5] ) , .p0 ( optlc_net_190 ) ) ; sb_2__1__mux_2level_tapbuf_size9_mem_0 mem_top_track_6 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( mux_2level_tapbuf_size7_mem_1_ccff_tail ) , @@ -29422,42 +31615,42 @@ sb_2__1__mux_2level_tapbuf_size5_0 mux_top_track_36 ( .sram ( mux_2level_tapbuf_size5_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_57 , SYNOPSYS_UNCONNECTED_58 , SYNOPSYS_UNCONNECTED_59 , SYNOPSYS_UNCONNECTED_60 } ) , - .out ( chany_top_out[18] ) , .p0 ( optlc_net_202 ) ) ; + .out ( chany_top_out[18] ) , .p0 ( optlc_net_192 ) ) ; sb_2__1__mux_2level_tapbuf_size5_1 mux_top_track_44 ( .in ( { top_left_grid_pin_48_[0] , chany_top_out[17] , chanx_left_in[2] , chanx_left_in[13] , chanx_left_in[24] } ) , .sram ( mux_2level_tapbuf_size5_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_61 , SYNOPSYS_UNCONNECTED_62 , SYNOPSYS_UNCONNECTED_63 , SYNOPSYS_UNCONNECTED_64 } ) , - .out ( chany_top_out[22] ) , .p0 ( optlc_net_202 ) ) ; + .out ( chany_top_out[22] ) , .p0 ( optlc_net_192 ) ) ; sb_2__1__mux_2level_tapbuf_size5_2 mux_top_track_52 ( .in ( { top_left_grid_pin_49_[0] , chany_top_out[19] , chanx_left_in[1] , chanx_left_in[12] , chanx_left_in[23] } ) , .sram ( mux_2level_tapbuf_size5_2_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_65 , SYNOPSYS_UNCONNECTED_66 , SYNOPSYS_UNCONNECTED_67 , SYNOPSYS_UNCONNECTED_68 } ) , - .out ( chany_top_out[26] ) , .p0 ( optlc_net_202 ) ) ; + .out ( chany_top_out[26] ) , .p0 ( optlc_net_192 ) ) ; sb_2__1__mux_2level_tapbuf_size5_3 mux_bottom_track_53 ( .in ( { chany_bottom_out[19] , bottom_left_grid_pin_48_[0] , chanx_left_in[0] , chanx_left_in[11] , chanx_left_in[22] } ) , .sram ( mux_2level_tapbuf_size5_3_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_69 , SYNOPSYS_UNCONNECTED_70 , SYNOPSYS_UNCONNECTED_71 , SYNOPSYS_UNCONNECTED_72 } ) , - .out ( chany_bottom_out[26] ) , .p0 ( optlc_net_201 ) ) ; + .out ( chany_bottom_out[26] ) , .p0 ( optlc_net_192 ) ) ; sb_2__1__mux_2level_tapbuf_size5_4 mux_left_track_5 ( .in ( { chany_bottom_out[8] , chany_bottom_in[1] , chany_top_out[8] , left_bottom_grid_pin_38_[0] , chanx_left_out[19] } ) , .sram ( mux_2level_tapbuf_size5_4_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_73 , SYNOPSYS_UNCONNECTED_74 , SYNOPSYS_UNCONNECTED_75 , SYNOPSYS_UNCONNECTED_76 } ) , - .out ( chanx_left_out[2] ) , .p0 ( optlc_net_199 ) ) ; + .out ( chanx_left_out[2] ) , .p0 ( optlc_net_188 ) ) ; sb_2__1__mux_2level_tapbuf_size5 mux_left_track_11 ( .in ( { chany_bottom_out[12] , chany_bottom_in[5] , chany_top_out[12] , left_bottom_grid_pin_38_[0] , chanx_left_out[19] } ) , .sram ( mux_2level_tapbuf_size5_5_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_77 , SYNOPSYS_UNCONNECTED_78 , SYNOPSYS_UNCONNECTED_79 , SYNOPSYS_UNCONNECTED_80 } ) , - .out ( chanx_left_out[5] ) , .p0 ( optlc_net_198 ) ) ; + .out ( chanx_left_out[5] ) , .p0 ( optlc_net_191 ) ) ; sb_2__1__mux_2level_tapbuf_size5_mem_0 mem_top_track_36 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( mux_2level_tapbuf_size7_mem_4_ccff_tail ) , @@ -29497,7 +31690,7 @@ sb_2__1__mux_2level_tapbuf_size10 mux_bottom_track_7 ( .sram ( mux_2level_tapbuf_size10_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_81 , SYNOPSYS_UNCONNECTED_82 , SYNOPSYS_UNCONNECTED_83 , SYNOPSYS_UNCONNECTED_84 } ) , - .out ( chany_bottom_out[3] ) , .p0 ( optlc_net_201 ) ) ; + .out ( chany_bottom_out[3] ) , .p0 ( optlc_net_187 ) ) ; sb_2__1__mux_2level_tapbuf_size10_mem mem_bottom_track_7 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( mux_2level_tapbuf_size8_mem_3_ccff_tail ) , @@ -29510,7 +31703,7 @@ sb_2__1__mux_2level_tapbuf_size6_0 mux_bottom_track_29 ( .sram ( mux_2level_tapbuf_size6_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_85 , SYNOPSYS_UNCONNECTED_86 , SYNOPSYS_UNCONNECTED_87 , SYNOPSYS_UNCONNECTED_88 } ) , - .out ( chany_bottom_out[14] ) , .p0 ( optlc_net_198 ) ) ; + .out ( chany_bottom_out[14] ) , .p0 ( optlc_net_187 ) ) ; sb_2__1__mux_2level_tapbuf_size6_1 mux_left_track_1 ( .in ( { chany_top_in[0] , chany_bottom_out[4] , chany_top_out[4] , left_bottom_grid_pin_36_[0] , left_bottom_grid_pin_39_[0] , @@ -29518,7 +31711,7 @@ sb_2__1__mux_2level_tapbuf_size6_1 mux_left_track_1 ( .sram ( mux_2level_tapbuf_size6_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_89 , SYNOPSYS_UNCONNECTED_90 , SYNOPSYS_UNCONNECTED_91 , SYNOPSYS_UNCONNECTED_92 } ) , - .out ( chanx_left_out[0] ) , .p0 ( optlc_net_200 ) ) ; + .out ( chanx_left_out[0] ) , .p0 ( optlc_net_188 ) ) ; sb_2__1__mux_2level_tapbuf_size6_2 mux_left_track_3 ( .in ( { chany_bottom_out[7] , chany_bottom_in[0] , chany_top_out[7] , left_bottom_grid_pin_37_[0] , left_bottom_grid_pin_40_[0] , @@ -29526,7 +31719,7 @@ sb_2__1__mux_2level_tapbuf_size6_2 mux_left_track_3 ( .sram ( mux_2level_tapbuf_size6_2_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_93 , SYNOPSYS_UNCONNECTED_94 , SYNOPSYS_UNCONNECTED_95 , SYNOPSYS_UNCONNECTED_96 } ) , - .out ( chanx_left_out[1] ) , .p0 ( optlc_net_199 ) ) ; + .out ( chanx_left_out[1] ) , .p0 ( optlc_net_188 ) ) ; sb_2__1__mux_2level_tapbuf_size6_3 mux_left_track_7 ( .in ( { chany_bottom_out[9] , chany_bottom_in[2] , chany_top_out[9] , left_bottom_grid_pin_36_[0] , left_bottom_grid_pin_39_[0] , @@ -29534,7 +31727,7 @@ sb_2__1__mux_2level_tapbuf_size6_3 mux_left_track_7 ( .sram ( mux_2level_tapbuf_size6_3_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_97 , SYNOPSYS_UNCONNECTED_98 , SYNOPSYS_UNCONNECTED_99 , SYNOPSYS_UNCONNECTED_100 } ) , - .out ( chanx_left_out[3] ) , .p0 ( optlc_net_200 ) ) ; + .out ( chanx_left_out[3] ) , .p0 ( optlc_net_191 ) ) ; sb_2__1__mux_2level_tapbuf_size6 mux_left_track_9 ( .in ( { chany_bottom_out[11] , chany_bottom_in[4] , chany_top_out[11] , left_bottom_grid_pin_37_[0] , left_bottom_grid_pin_40_[0] , @@ -29542,7 +31735,7 @@ sb_2__1__mux_2level_tapbuf_size6 mux_left_track_9 ( .sram ( mux_2level_tapbuf_size6_4_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_101 , SYNOPSYS_UNCONNECTED_102 , SYNOPSYS_UNCONNECTED_103 , SYNOPSYS_UNCONNECTED_104 } ) , - .out ( chanx_left_out[4] ) , .p0 ( optlc_net_200 ) ) ; + .out ( chanx_left_out[4] ) , .p0 ( optlc_net_191 ) ) ; sb_2__1__mux_2level_tapbuf_size6_mem_0 mem_bottom_track_29 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( mux_2level_tapbuf_size7_mem_6_ccff_tail ) , @@ -29574,56 +31767,56 @@ sb_2__1__mux_2level_tapbuf_size4_0 mux_bottom_track_37 ( .sram ( mux_2level_tapbuf_size4_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_105 , SYNOPSYS_UNCONNECTED_106 , SYNOPSYS_UNCONNECTED_107 , SYNOPSYS_UNCONNECTED_108 } ) , - .out ( chany_bottom_out[18] ) , .p0 ( optlc_net_198 ) ) ; + .out ( chany_bottom_out[18] ) , .p0 ( optlc_net_187 ) ) ; sb_2__1__mux_2level_tapbuf_size4_1 mux_bottom_track_45 ( .in ( { chany_bottom_out[17] , bottom_left_grid_pin_47_[0] , chanx_left_in[10] , chanx_left_in[21] } ) , .sram ( mux_2level_tapbuf_size4_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_109 , SYNOPSYS_UNCONNECTED_110 , SYNOPSYS_UNCONNECTED_111 , SYNOPSYS_UNCONNECTED_112 } ) , - .out ( chany_bottom_out[22] ) , .p0 ( optlc_net_200 ) ) ; + .out ( chany_bottom_out[22] ) , .p0 ( optlc_net_187 ) ) ; sb_2__1__mux_2level_tapbuf_size4_2 mux_left_track_13 ( .in ( { chany_bottom_out[13] , chany_bottom_in[9] , chany_top_out[13] , left_bottom_grid_pin_36_[0] } ) , .sram ( mux_2level_tapbuf_size4_2_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_113 , SYNOPSYS_UNCONNECTED_114 , SYNOPSYS_UNCONNECTED_115 , SYNOPSYS_UNCONNECTED_116 } ) , - .out ( chanx_left_out[6] ) , .p0 ( optlc_net_198 ) ) ; + .out ( chanx_left_out[6] ) , .p0 ( optlc_net_187 ) ) ; sb_2__1__mux_2level_tapbuf_size4_3 mux_left_track_15 ( .in ( { chany_bottom_out[15] , chany_bottom_in[13] , chany_top_out[15] , left_bottom_grid_pin_37_[0] } ) , .sram ( mux_2level_tapbuf_size4_3_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_117 , SYNOPSYS_UNCONNECTED_118 , SYNOPSYS_UNCONNECTED_119 , SYNOPSYS_UNCONNECTED_120 } ) , - .out ( chanx_left_out[7] ) , .p0 ( optlc_net_198 ) ) ; + .out ( chanx_left_out[7] ) , .p0 ( optlc_net_191 ) ) ; sb_2__1__mux_2level_tapbuf_size4_4 mux_left_track_17 ( .in ( { chany_bottom_out[16] , chany_top_out[16] , chany_bottom_in[17] , left_bottom_grid_pin_38_[0] } ) , .sram ( mux_2level_tapbuf_size4_4_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_121 , SYNOPSYS_UNCONNECTED_122 , SYNOPSYS_UNCONNECTED_123 , SYNOPSYS_UNCONNECTED_124 } ) , - .out ( chanx_left_out[8] ) , .p0 ( optlc_net_198 ) ) ; + .out ( chanx_left_out[8] ) , .p0 ( optlc_net_191 ) ) ; sb_2__1__mux_2level_tapbuf_size4_5 mux_left_track_19 ( .in ( { chany_bottom_out[17] , chany_top_out[17] , chany_bottom_in[21] , left_bottom_grid_pin_39_[0] } ) , .sram ( mux_2level_tapbuf_size4_5_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_125 , SYNOPSYS_UNCONNECTED_126 , SYNOPSYS_UNCONNECTED_127 , SYNOPSYS_UNCONNECTED_128 } ) , - .out ( chanx_left_out[9] ) , .p0 ( optlc_net_200 ) ) ; + .out ( chanx_left_out[9] ) , .p0 ( optlc_net_191 ) ) ; sb_2__1__mux_2level_tapbuf_size4_6 mux_left_track_21 ( .in ( { chany_bottom_out[19] , chany_top_out[19] , chany_bottom_in[25] , left_bottom_grid_pin_40_[0] } ) , .sram ( mux_2level_tapbuf_size4_6_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_129 , SYNOPSYS_UNCONNECTED_130 , SYNOPSYS_UNCONNECTED_131 , SYNOPSYS_UNCONNECTED_132 } ) , - .out ( chanx_left_out[10] ) , .p0 ( optlc_net_200 ) ) ; + .out ( chanx_left_out[10] ) , .p0 ( optlc_net_191 ) ) ; sb_2__1__mux_2level_tapbuf_size4 mux_left_track_23 ( .in ( { chany_bottom_out[20] , chany_top_out[20] , chany_bottom_in[29] , chanx_left_out[19] } ) , .sram ( mux_2level_tapbuf_size4_7_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_133 , SYNOPSYS_UNCONNECTED_134 , SYNOPSYS_UNCONNECTED_135 , SYNOPSYS_UNCONNECTED_136 } ) , - .out ( chanx_left_out[11] ) , .p0 ( optlc_net_198 ) ) ; + .out ( chanx_left_out[11] ) , .p0 ( optlc_net_188 ) ) ; sb_2__1__mux_2level_tapbuf_size4_mem_0 mem_bottom_track_37 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( mux_2level_tapbuf_size6_mem_0_ccff_tail ) , @@ -29669,49 +31862,49 @@ sb_2__1__mux_2level_tapbuf_size3_0 mux_left_track_25 ( left_bottom_grid_pin_42_[0] } ) , .sram ( mux_2level_tapbuf_size3_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_137 , SYNOPSYS_UNCONNECTED_138 } ) , - .out ( chanx_left_out[12] ) , .p0 ( optlc_net_200 ) ) ; + .out ( chanx_left_out[12] ) , .p0 ( optlc_net_188 ) ) ; sb_2__1__mux_2level_tapbuf_size3_1 mux_left_track_27 ( .in ( { chany_bottom_out[23] , chany_top_out[23] , left_bottom_grid_pin_43_[0] } ) , .sram ( mux_2level_tapbuf_size3_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_139 , SYNOPSYS_UNCONNECTED_140 } ) , - .out ( chanx_left_out[13] ) , .p0 ( optlc_net_200 ) ) ; + .out ( chanx_left_out[13] ) , .p0 ( optlc_net_188 ) ) ; sb_2__1__mux_2level_tapbuf_size3_2 mux_left_track_29 ( .in ( { chany_bottom_out[24] , chany_top_out[24] , left_bottom_grid_pin_36_[0] } ) , .sram ( mux_2level_tapbuf_size3_2_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_141 , SYNOPSYS_UNCONNECTED_142 } ) , - .out ( chanx_left_out[14] ) , .p0 ( optlc_net_200 ) ) ; + .out ( chanx_left_out[14] ) , .p0 ( optlc_net_188 ) ) ; sb_2__1__mux_2level_tapbuf_size3_3 mux_left_track_31 ( .in ( { chany_bottom_out[25] , chany_top_out[25] , left_bottom_grid_pin_37_[0] } ) , .sram ( mux_2level_tapbuf_size3_3_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_143 , SYNOPSYS_UNCONNECTED_144 } ) , - .out ( chanx_left_out[15] ) , .p0 ( optlc_net_200 ) ) ; + .out ( chanx_left_out[15] ) , .p0 ( optlc_net_191 ) ) ; sb_2__1__mux_2level_tapbuf_size3_4 mux_left_track_33 ( .in ( { chany_bottom_out[27] , chany_top_out[27] , left_bottom_grid_pin_38_[0] } ) , .sram ( mux_2level_tapbuf_size3_4_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_145 , SYNOPSYS_UNCONNECTED_146 } ) , - .out ( chanx_left_out[16] ) , .p0 ( optlc_net_198 ) ) ; + .out ( chanx_left_out[16] ) , .p0 ( optlc_net_191 ) ) ; sb_2__1__mux_2level_tapbuf_size3_5 mux_left_track_35 ( .in ( { chany_bottom_out[28] , chany_top_out[28] , left_bottom_grid_pin_39_[0] } ) , .sram ( mux_2level_tapbuf_size3_5_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_147 , SYNOPSYS_UNCONNECTED_148 } ) , - .out ( chanx_left_out[17] ) , .p0 ( optlc_net_200 ) ) ; + .out ( chanx_left_out[17] ) , .p0 ( optlc_net_191 ) ) ; sb_2__1__mux_2level_tapbuf_size3_6 mux_left_track_37 ( .in ( { chany_bottom_out[29] , chany_top_out[29] , left_bottom_grid_pin_40_[0] } ) , .sram ( mux_2level_tapbuf_size3_6_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_149 , SYNOPSYS_UNCONNECTED_150 } ) , - .out ( chanx_left_out[18] ) , .p0 ( optlc_net_200 ) ) ; + .out ( chanx_left_out[18] ) , .p0 ( optlc_net_188 ) ) ; sb_2__1__mux_2level_tapbuf_size3 mux_left_track_51 ( .in ( { chany_top_in[9] , left_bottom_grid_pin_39_[0] , left_bottom_grid_pin_43_[0] } ) , .sram ( mux_2level_tapbuf_size3_7_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_151 , SYNOPSYS_UNCONNECTED_152 } ) , - .out ( chanx_left_out[25] ) , .p0 ( optlc_net_199 ) ) ; + .out ( chanx_left_out[25] ) , .p0 ( optlc_net_188 ) ) ; sb_2__1__mux_2level_tapbuf_size3_mem_0 mem_left_track_25 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( mux_2level_tapbuf_size4_mem_7_ccff_tail ) , @@ -29756,37 +31949,37 @@ sb_2__1__mux_2level_tapbuf_size2_0 mux_left_track_41 ( .in ( { chany_top_in[29] , left_bottom_grid_pin_42_[0] } ) , .sram ( mux_2level_tapbuf_size2_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_153 , SYNOPSYS_UNCONNECTED_154 } ) , - .out ( chanx_left_out[20] ) , .p0 ( optlc_net_199 ) ) ; + .out ( chanx_left_out[20] ) , .p0 ( optlc_net_189 ) ) ; sb_2__1__mux_2level_tapbuf_size2_1 mux_left_track_45 ( .in ( { chany_top_in[21] , left_bottom_grid_pin_36_[0] } ) , .sram ( mux_2level_tapbuf_size2_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_155 , SYNOPSYS_UNCONNECTED_156 } ) , - .out ( chanx_left_out[22] ) , .p0 ( optlc_net_199 ) ) ; + .out ( chanx_left_out[22] ) , .p0 ( optlc_net_189 ) ) ; sb_2__1__mux_2level_tapbuf_size2_2 mux_left_track_47 ( .in ( { chany_top_in[17] , left_bottom_grid_pin_37_[0] } ) , .sram ( mux_2level_tapbuf_size2_2_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_157 , SYNOPSYS_UNCONNECTED_158 } ) , - .out ( chanx_left_out[23] ) , .p0 ( optlc_net_199 ) ) ; + .out ( chanx_left_out[23] ) , .p0 ( optlc_net_188 ) ) ; sb_2__1__mux_2level_tapbuf_size2_3 mux_left_track_49 ( .in ( { chany_top_in[13] , left_bottom_grid_pin_38_[0] } ) , .sram ( mux_2level_tapbuf_size2_3_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_159 , SYNOPSYS_UNCONNECTED_160 } ) , - .out ( chanx_left_out[24] ) , .p0 ( optlc_net_199 ) ) ; + .out ( chanx_left_out[24] ) , .p0 ( optlc_net_189 ) ) ; sb_2__1__mux_2level_tapbuf_size2_4 mux_left_track_53 ( .in ( { chany_top_in[5] , left_bottom_grid_pin_40_[0] } ) , .sram ( mux_2level_tapbuf_size2_4_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_161 , SYNOPSYS_UNCONNECTED_162 } ) , - .out ( chanx_left_out[26] ) , .p0 ( optlc_net_199 ) ) ; + .out ( chanx_left_out[26] ) , .p0 ( optlc_net_189 ) ) ; sb_2__1__mux_2level_tapbuf_size2_5 mux_left_track_55 ( .in ( { chany_top_in[4] , chanx_left_out[19] } ) , .sram ( mux_2level_tapbuf_size2_5_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_163 , SYNOPSYS_UNCONNECTED_164 } ) , - .out ( chanx_left_out[27] ) , .p0 ( optlc_net_199 ) ) ; + .out ( chanx_left_out[27] ) , .p0 ( optlc_net_188 ) ) ; sb_2__1__mux_2level_tapbuf_size2 mux_left_track_57 ( .in ( { chany_top_in[2] , left_bottom_grid_pin_42_[0] } ) , .sram ( mux_2level_tapbuf_size2_6_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_165 , SYNOPSYS_UNCONNECTED_166 } ) , - .out ( chanx_left_out[28] ) , .p0 ( optlc_net_199 ) ) ; + .out ( chanx_left_out[28] ) , .p0 ( optlc_net_188 ) ) ; sb_2__1__mux_2level_tapbuf_size2_mem_0 mem_left_track_41 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( mux_2level_tapbuf_size3_mem_6_ccff_tail ) , @@ -29822,12 +32015,12 @@ sb_2__1__mux_2level_tapbuf_size2_mem mem_left_track_57 ( .pReset ( pReset ) , .ccff_head ( mux_2level_tapbuf_size2_mem_5_ccff_tail ) , .ccff_tail ( ccff_tail ) , .mem_out ( mux_2level_tapbuf_size2_6_sram ) ) ; sky130_fd_sc_hd__buf_8 pReset_FTB00 ( .A ( pReset_W_in ) , .X ( pReset[0] ) ) ; -sky130_fd_sc_hd__conb_1 optlc_200 ( .LO ( SYNOPSYS_UNCONNECTED_167 ) , - .HI ( optlc_net_198 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_189 ( .LO ( SYNOPSYS_UNCONNECTED_167 ) , + .HI ( optlc_net_187 ) ) ; sky130_fd_sc_hd__buf_1 prog_clk_0_FTB00 ( .A ( prog_clk_0_N_in ) , .X ( prog_clk[0] ) ) ; sky130_fd_sc_hd__buf_1 FTB_110__109 ( .A ( chany_top_in[1] ) , - .X ( ropt_net_217 ) ) ; + .X ( ZBUF_250_f_0 ) ) ; sky130_fd_sc_hd__buf_8 FTB_111__110 ( .A ( chany_top_in[3] ) , .X ( chany_bottom_out[4] ) ) ; sky130_fd_sc_hd__buf_8 FTB_112__111 ( .A ( chany_top_in[6] ) , @@ -29861,7 +32054,7 @@ sky130_fd_sc_hd__buf_8 FTB_125__124 ( .A ( chany_top_in[23] ) , sky130_fd_sc_hd__buf_8 FTB_126__125 ( .A ( chany_top_in[24] ) , .X ( chany_bottom_out[25] ) ) ; sky130_fd_sc_hd__buf_1 FTB_127__126 ( .A ( chany_top_in[25] ) , - .X ( ZBUF_74_0 ) ) ; + .X ( ZBUF_263_f_0 ) ) ; sky130_fd_sc_hd__buf_8 FTB_128__127 ( .A ( chany_top_in[26] ) , .X ( chany_bottom_out[27] ) ) ; sky130_fd_sc_hd__buf_8 FTB_129__128 ( .A ( chany_top_in[27] ) , @@ -29908,21 +32101,21 @@ sky130_fd_sc_hd__buf_8 FTB_149__148 ( .A ( chany_bottom_in[28] ) , .X ( chany_top_out[29] ) ) ; sky130_fd_sc_hd__buf_8 FTB_150__149 ( .A ( left_bottom_grid_pin_41_[0] ) , .X ( chanx_left_out[19] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_196 ( .A ( BUF_net_197 ) , .Y ( pReset_N_out ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_197 ( .A ( pReset_W_in ) , .Y ( BUF_net_197 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_202 ( .LO ( SYNOPSYS_UNCONNECTED_168 ) , - .HI ( optlc_net_199 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_204 ( .LO ( SYNOPSYS_UNCONNECTED_169 ) , - .HI ( optlc_net_200 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_207 ( .LO ( SYNOPSYS_UNCONNECTED_170 ) , - .HI ( optlc_net_201 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_209 ( .LO ( SYNOPSYS_UNCONNECTED_171 ) , - .HI ( optlc_net_202 ) ) ; -sky130_fd_sc_hd__buf_6 ZBUF_214_f_inst_210 ( .A ( aps_rename_508_ ) , - .X ( chany_bottom_out[10] ) ) ; -sky130_fd_sc_hd__buf_6 ropt_mt_inst_1406 ( .A ( ropt_net_217 ) , +sky130_fd_sc_hd__inv_8 BINV_R_183 ( .A ( BUF_net_184 ) , .Y ( pReset_N_out ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_184 ( .A ( pReset_W_in ) , .Y ( BUF_net_184 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_191 ( .LO ( SYNOPSYS_UNCONNECTED_168 ) , + .HI ( optlc_net_188 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_193 ( .LO ( SYNOPSYS_UNCONNECTED_169 ) , + .HI ( optlc_net_189 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_195 ( .LO ( SYNOPSYS_UNCONNECTED_170 ) , + .HI ( optlc_net_190 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_197 ( .LO ( SYNOPSYS_UNCONNECTED_171 ) , + .HI ( optlc_net_191 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_199 ( .LO ( SYNOPSYS_UNCONNECTED_172 ) , + .HI ( optlc_net_192 ) ) ; +sky130_fd_sc_hd__buf_6 ZBUF_250_f_inst_1393 ( .A ( ZBUF_250_f_0 ) , .X ( chanx_left_out[29] ) ) ; -sky130_fd_sc_hd__buf_6 ropt_mt_inst_1408 ( .A ( ZBUF_74_0 ) , +sky130_fd_sc_hd__buf_6 ropt_mt_inst_1396 ( .A ( ZBUF_263_f_0 ) , .X ( chanx_left_out[21] ) ) ; endmodule @@ -29935,17 +32128,17 @@ input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -wire copt_net_169 ; +wire copt_net_159 ; sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( copt_net_169 ) ) ; + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( copt_net_159 ) ) ; sky130_fd_sc_hd__buf_6 FTB_77__76 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; -sky130_fd_sc_hd__buf_1 ropt_h_inst_1366 ( .A ( ropt_net_188 ) , +sky130_fd_sc_hd__buf_1 copt_h_inst_1344 ( .A ( copt_net_163 ) , .X ( mem_out[1] ) ) ; -sky130_fd_sc_hd__buf_1 copt_h_inst_1348 ( .A ( copt_net_169 ) , - .X ( ropt_net_188 ) ) ; +sky130_fd_sc_hd__buf_1 copt_h_inst_1346 ( .A ( copt_net_159 ) , + .X ( copt_net_163 ) ) ; endmodule @@ -30551,8 +32744,6 @@ wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ; sb_2__0__const1 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) ) ; sb_2__0__mux_2level_tapbuf_basis_input2_mem1_85 mux_l1_in_0_ ( .in ( in ) , .mem ( sram[0] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_2 } ) , @@ -30563,6 +32754,8 @@ sb_2__0__mux_2level_tapbuf_basis_input2_mem1 mux_l2_in_0_ ( .mem ( sram[1] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_4 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_142 ( + .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) ) ; endmodule @@ -30608,8 +32801,6 @@ wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ; sb_2__0__const1_51 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) ) ; sb_2__0__mux_2level_tapbuf_basis_input2_mem1_83 mux_l1_in_0_ ( .in ( in ) , .mem ( sram[0] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_2 } ) , @@ -30620,6 +32811,8 @@ sb_2__0__mux_2level_tapbuf_basis_input2_mem1_84 mux_l2_in_0_ ( .mem ( sram[1] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_4 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_141 ( + .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) ) ; endmodule @@ -30688,7 +32881,7 @@ input [0:0] mem_inv ; output [0:0] out ; input p0 ; -sky130_fd_sc_hd__mux2_2 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , +sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ; endmodule @@ -30745,7 +32938,7 @@ input [0:0] mem_inv ; output [0:0] out ; input p0 ; -sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , +sky130_fd_sc_hd__mux2_2 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ; endmodule @@ -30846,9 +33039,9 @@ sb_2__0__mux_2level_tapbuf_basis_input2_mem1_76 mux_l2_in_0_ ( .mem ( sram[1] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_4 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_150 ( .A ( BUF_net_151 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_151 ( - .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_151 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_139 ( .A ( BUF_net_140 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_140 ( + .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_140 ) ) ; endmodule @@ -30904,9 +33097,9 @@ sb_2__0__mux_2level_tapbuf_basis_input2_mem1_74 mux_l2_in_0_ ( .mem ( sram[1] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_4 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_148 ( .A ( BUF_net_149 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_149 ( - .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_149 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_137 ( .A ( BUF_net_138 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_138 ( + .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_138 ) ) ; endmodule @@ -30962,9 +33155,9 @@ sb_2__0__mux_2level_tapbuf_basis_input2_mem1_72 mux_l2_in_0_ ( .mem ( sram[1] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_4 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_146 ( .A ( BUF_net_147 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_147 ( - .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_147 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_145 ( .A ( BUF_net_146 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_146 ( + .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_146 ) ) ; endmodule @@ -30976,7 +33169,7 @@ input [0:0] mem_inv ; output [0:0] out ; input p0 ; -sky130_fd_sc_hd__mux2_2 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , +sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ; endmodule @@ -31010,8 +33203,6 @@ wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ; sb_2__0__const1_44 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) ) ; sb_2__0__mux_2level_tapbuf_basis_input2_mem1_69 mux_l1_in_0_ ( .in ( in ) , .mem ( sram[0] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_2 } ) , @@ -31022,6 +33213,9 @@ sb_2__0__mux_2level_tapbuf_basis_input2_mem1_70 mux_l2_in_0_ ( .mem ( sram[1] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_4 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_135 ( .A ( BUF_net_136 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_136 ( + .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_136 ) ) ; endmodule @@ -31033,7 +33227,7 @@ input [0:0] mem_inv ; output [0:0] out ; input p0 ; -sky130_fd_sc_hd__mux2_2 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , +sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ; endmodule @@ -31067,8 +33261,6 @@ wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ; sb_2__0__const1_43 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) ) ; sb_2__0__mux_2level_tapbuf_basis_input2_mem1_67 mux_l1_in_0_ ( .in ( in ) , .mem ( sram[0] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_2 } ) , @@ -31079,6 +33271,9 @@ sb_2__0__mux_2level_tapbuf_basis_input2_mem1_68 mux_l2_in_0_ ( .mem ( sram[1] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_4 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_133 ( .A ( BUF_net_134 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_134 ( + .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_134 ) ) ; endmodule @@ -31090,7 +33285,7 @@ input [0:0] mem_inv ; output [0:0] out ; input p0 ; -sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , +sky130_fd_sc_hd__mux2_2 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ; endmodule @@ -31124,6 +33319,8 @@ wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ; sb_2__0__const1_42 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) ) ; sb_2__0__mux_2level_tapbuf_basis_input2_mem1_65 mux_l1_in_0_ ( .in ( in ) , .mem ( sram[0] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_2 } ) , @@ -31134,9 +33331,6 @@ sb_2__0__mux_2level_tapbuf_basis_input2_mem1_66 mux_l2_in_0_ ( .mem ( sram[1] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_4 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_144 ( .A ( BUF_net_145 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_145 ( - .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_145 ) ) ; endmodule @@ -31148,7 +33342,7 @@ input [0:0] mem_inv ; output [0:0] out ; input p0 ; -sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , +sky130_fd_sc_hd__mux2_2 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ; endmodule @@ -31182,6 +33376,8 @@ wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ; sb_2__0__const1_41 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) ) ; sb_2__0__mux_2level_tapbuf_basis_input2_mem1_63 mux_l1_in_0_ ( .in ( in ) , .mem ( sram[0] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_2 } ) , @@ -31192,9 +33388,6 @@ sb_2__0__mux_2level_tapbuf_basis_input2_mem1_64 mux_l2_in_0_ ( .mem ( sram[1] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_4 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_142 ( .A ( BUF_net_143 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_143 ( - .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_143 ) ) ; endmodule @@ -31206,7 +33399,7 @@ input [0:0] mem_inv ; output [0:0] out ; input p0 ; -sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , +sky130_fd_sc_hd__mux2_2 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ; endmodule @@ -31240,6 +33433,8 @@ wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ; sb_2__0__const1_40 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) ) ; sb_2__0__mux_2level_tapbuf_basis_input2_mem1_61 mux_l1_in_0_ ( .in ( in ) , .mem ( sram[0] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_2 } ) , @@ -31250,9 +33445,6 @@ sb_2__0__mux_2level_tapbuf_basis_input2_mem1_62 mux_l2_in_0_ ( .mem ( sram[1] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_4 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_140 ( .A ( BUF_net_141 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_141 ( - .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_141 ) ) ; endmodule @@ -31264,7 +33456,7 @@ input [0:0] mem_inv ; output [0:0] out ; input p0 ; -sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , +sky130_fd_sc_hd__mux2_2 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ; endmodule @@ -31298,6 +33490,8 @@ wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ; sb_2__0__const1_39 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) ) ; sb_2__0__mux_2level_tapbuf_basis_input2_mem1_59 mux_l1_in_0_ ( .in ( in ) , .mem ( sram[0] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_2 } ) , @@ -31308,9 +33502,6 @@ sb_2__0__mux_2level_tapbuf_basis_input2_mem1_60 mux_l2_in_0_ ( .mem ( sram[1] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_4 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_138 ( .A ( BUF_net_139 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_139 ( - .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_139 ) ) ; endmodule @@ -31322,7 +33513,7 @@ input [0:0] mem_inv ; output [0:0] out ; input p0 ; -sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , +sky130_fd_sc_hd__mux2_2 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ; endmodule @@ -31356,6 +33547,8 @@ wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ; sb_2__0__const1_38 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) ) ; sb_2__0__mux_2level_tapbuf_basis_input2_mem1_57 mux_l1_in_0_ ( .in ( in ) , .mem ( sram[0] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_2 } ) , @@ -31366,9 +33559,6 @@ sb_2__0__mux_2level_tapbuf_basis_input2_mem1_58 mux_l2_in_0_ ( .mem ( sram[1] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_4 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_136 ( .A ( BUF_net_137 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_137 ( - .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_137 ) ) ; endmodule @@ -31380,7 +33570,7 @@ input [0:0] mem_inv ; output [0:0] out ; input p0 ; -sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , +sky130_fd_sc_hd__mux2_2 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ; endmodule @@ -31424,9 +33614,8 @@ sb_2__0__mux_2level_tapbuf_basis_input2_mem1_56 mux_l2_in_0_ ( .mem ( sram[1] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_4 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_134 ( .A ( BUF_net_135 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_135 ( - .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_135 ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_132 ( + .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) ) ; endmodule @@ -31438,7 +33627,7 @@ input [0:0] mem_inv ; output [0:0] out ; input p0 ; -sky130_fd_sc_hd__mux2_2 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , +sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ; endmodule @@ -31482,8 +33671,9 @@ sb_2__0__mux_2level_tapbuf_basis_input2_mem1_54 mux_l2_in_0_ ( .mem ( sram[1] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_4 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_133 ( - .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_130 ( .A ( BUF_net_131 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_131 ( + .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_131 ) ) ; endmodule @@ -31586,6 +33776,8 @@ wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ; sb_2__0__const1_34 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) ) ; sb_2__0__mux_2level_tapbuf_basis_input2_mem1_49 mux_l1_in_0_ ( .in ( in ) , .mem ( sram[0] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_2 } ) , @@ -31596,8 +33788,6 @@ sb_2__0__mux_2level_tapbuf_basis_input2_mem1_50 mux_l2_in_0_ ( .mem ( sram[1] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_4 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_132 ( - .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) ) ; endmodule @@ -31609,7 +33799,7 @@ input [0:0] mem_inv ; output [0:0] out ; input p0 ; -sky130_fd_sc_hd__mux2_2 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , +sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ; endmodule @@ -31666,7 +33856,7 @@ input [0:0] mem_inv ; output [0:0] out ; input p0 ; -sky130_fd_sc_hd__mux2_2 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , +sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ; endmodule @@ -31757,8 +33947,6 @@ wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ; sb_2__0__const1_31 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) ) ; sb_2__0__mux_2level_tapbuf_basis_input2_mem1_43 mux_l1_in_0_ ( .in ( in ) , .mem ( sram[0] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_2 } ) , @@ -31769,6 +33957,9 @@ sb_2__0__mux_2level_tapbuf_basis_input2_mem1_44 mux_l2_in_0_ ( .mem ( sram[1] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_4 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_128 ( .A ( BUF_net_129 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_129 ( + .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_129 ) ) ; endmodule @@ -31780,7 +33971,7 @@ input [0:0] mem_inv ; output [0:0] out ; input p0 ; -sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , +sky130_fd_sc_hd__mux2_2 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ; endmodule @@ -31824,9 +34015,8 @@ sb_2__0__mux_2level_tapbuf_basis_input2_mem1_42 mux_l2_in_0_ ( .mem ( sram[1] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_4 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_130 ( .A ( BUF_net_131 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_131 ( - .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_131 ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_127 ( + .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) ) ; endmodule @@ -31838,7 +34028,7 @@ input [0:0] mem_inv ; output [0:0] out ; input p0 ; -sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , +sky130_fd_sc_hd__mux2_2 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ; endmodule @@ -31882,9 +34072,8 @@ sb_2__0__mux_2level_tapbuf_basis_input2_mem1_40 mux_l2_in_0_ ( .mem ( sram[1] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_4 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_128 ( .A ( BUF_net_129 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_129 ( - .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_129 ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_126 ( + .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) ) ; endmodule @@ -31940,9 +34129,9 @@ sb_2__0__mux_2level_tapbuf_basis_input2_mem1_38 mux_l2_in_0_ ( .mem ( sram[1] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_4 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_126 ( .A ( BUF_net_127 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_127 ( - .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_127 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_124 ( .A ( BUF_net_125 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_125 ( + .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_125 ) ) ; endmodule @@ -31954,7 +34143,7 @@ input [0:0] mem_inv ; output [0:0] out ; input p0 ; -sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , +sky130_fd_sc_hd__mux2_2 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ; endmodule @@ -31998,9 +34187,8 @@ sb_2__0__mux_2level_tapbuf_basis_input2_mem1_36 mux_l2_in_0_ ( .mem ( sram[1] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_4 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_124 ( .A ( BUF_net_125 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_125 ( - .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_125 ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_123 ( + .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) ) ; endmodule @@ -32012,7 +34200,7 @@ input [0:0] mem_inv ; output [0:0] out ; input p0 ; -sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , +sky130_fd_sc_hd__mux2_2 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ; endmodule @@ -32056,9 +34244,8 @@ sb_2__0__mux_2level_tapbuf_basis_input2_mem1_34 mux_l2_in_0_ ( .mem ( sram[1] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_4 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_122 ( .A ( BUF_net_123 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_123 ( - .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_123 ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_122 ( + .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) ) ; endmodule @@ -32127,7 +34314,7 @@ input [0:0] mem_inv ; output [0:0] out ; input p0 ; -sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , +sky130_fd_sc_hd__mux2_2 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ; endmodule @@ -32171,9 +34358,8 @@ sb_2__0__mux_2level_tapbuf_basis_input2_mem1_30 mux_l2_in_0_ ( .mem ( sram[1] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_4 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_120 ( .A ( BUF_net_121 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_121 ( - .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_121 ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_121 ( + .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) ) ; endmodule @@ -32229,9 +34415,9 @@ sb_2__0__mux_2level_tapbuf_basis_input2_mem1_28 mux_l2_in_0_ ( .mem ( sram[1] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_4 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_118 ( .A ( BUF_net_119 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_119 ( - .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_119 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_119 ( .A ( BUF_net_120 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_120 ( + .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_120 ) ) ; endmodule @@ -32287,9 +34473,9 @@ sb_2__0__mux_2level_tapbuf_basis_input2_mem1_26 mux_l2_in_0_ ( .mem ( sram[1] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_4 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_116 ( .A ( BUF_net_117 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_117 ( - .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_117 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_117 ( .A ( BUF_net_118 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_118 ( + .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_118 ) ) ; endmodule @@ -32335,6 +34521,8 @@ wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ; sb_2__0__const1_21 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) ) ; sb_2__0__mux_2level_tapbuf_basis_input2_mem1_23 mux_l1_in_0_ ( .in ( in ) , .mem ( sram[0] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_2 } ) , @@ -32345,9 +34533,6 @@ sb_2__0__mux_2level_tapbuf_basis_input2_mem1_24 mux_l2_in_0_ ( .mem ( sram[1] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_4 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_114 ( .A ( BUF_net_115 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_115 ( - .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_115 ) ) ; endmodule @@ -32403,8 +34588,9 @@ sb_2__0__mux_2level_tapbuf_basis_input2_mem1_22 mux_l2_in_0_ ( .mem ( sram[1] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_4 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_113 ( - .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_115 ( .A ( BUF_net_116 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_116 ( + .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_116 ) ) ; endmodule @@ -32460,9 +34646,9 @@ sb_2__0__mux_2level_tapbuf_basis_input2_mem1_20 mux_l2_in_0_ ( .mem ( sram[1] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_4 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_111 ( .A ( BUF_net_112 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_112 ( - .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_112 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_113 ( .A ( BUF_net_114 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_114 ( + .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_114 ) ) ; endmodule @@ -32508,6 +34694,8 @@ wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ; sb_2__0__const1_18 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) ) ; sb_2__0__mux_2level_tapbuf_basis_input2_mem1_17 mux_l1_in_0_ ( .in ( in ) , .mem ( sram[0] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_2 } ) , @@ -32518,9 +34706,6 @@ sb_2__0__mux_2level_tapbuf_basis_input2_mem1_18 mux_l2_in_0_ ( .mem ( sram[1] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_4 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_109 ( .A ( BUF_net_110 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_110 ( - .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_110 ) ) ; endmodule @@ -32668,7 +34853,7 @@ input [0:0] mem ; input [0:0] mem_inv ; output [0:0] out ; -sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) , +sky130_fd_sc_hd__mux2_2 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ; endmodule @@ -32731,9 +34916,8 @@ sb_2__0__mux_2level_tapbuf_basis_input2_mem1_14 mux_l2_in_0_ ( .mem ( sram[1] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_5 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_2_out ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_107 ( .A ( BUF_net_108 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_108 ( - .A ( mux_2level_tapbuf_basis_input2_mem1_2_out[0] ) , .Y ( BUF_net_108 ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_112 ( + .A ( mux_2level_tapbuf_basis_input2_mem1_2_out[0] ) , .X ( out[0] ) ) ; endmodule @@ -32744,7 +34928,7 @@ input [0:0] mem ; input [0:0] mem_inv ; output [0:0] out ; -sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) , +sky130_fd_sc_hd__mux2_2 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ; endmodule @@ -32807,9 +34991,8 @@ sb_2__0__mux_2level_tapbuf_basis_input2_mem1_11 mux_l2_in_0_ ( .mem ( sram[1] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_5 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_2_out ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_105 ( .A ( BUF_net_106 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_106 ( - .A ( mux_2level_tapbuf_basis_input2_mem1_2_out[0] ) , .Y ( BUF_net_106 ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_111 ( + .A ( mux_2level_tapbuf_basis_input2_mem1_2_out[0] ) , .X ( out[0] ) ) ; endmodule @@ -32820,7 +35003,7 @@ input [0:0] mem ; input [0:0] mem_inv ; output [0:0] out ; -sky130_fd_sc_hd__mux2_2 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) , +sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ; endmodule @@ -32868,8 +35051,6 @@ wire [0:0] mux_2level_tapbuf_basis_input2_mem1_2_out ; sb_2__0__const1_14 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( mux_2level_tapbuf_basis_input2_mem1_2_out[0] ) , .X ( out[0] ) ) ; sb_2__0__mux_2level_tapbuf_basis_input2_mem1_6 mux_l1_in_0_ ( .in ( in[0:1] ) , .mem ( sram[0] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_2 } ) , @@ -32885,6 +35066,9 @@ sb_2__0__mux_2level_tapbuf_basis_input2_mem1_8 mux_l2_in_0_ ( .mem ( sram[1] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_5 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_2_out ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_109 ( .A ( BUF_net_110 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_110 ( + .A ( mux_2level_tapbuf_basis_input2_mem1_2_out[0] ) , .Y ( BUF_net_110 ) ) ; endmodule @@ -32895,7 +35079,7 @@ input [0:0] mem ; input [0:0] mem_inv ; output [0:0] out ; -sky130_fd_sc_hd__mux2_2 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) , +sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ; endmodule @@ -32943,8 +35127,6 @@ wire [0:0] mux_2level_tapbuf_basis_input2_mem1_2_out ; sb_2__0__const1_13 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( mux_2level_tapbuf_basis_input2_mem1_2_out[0] ) , .X ( out[0] ) ) ; sb_2__0__mux_2level_tapbuf_basis_input2_mem1_3 mux_l1_in_0_ ( .in ( in[0:1] ) , .mem ( sram[0] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_2 } ) , @@ -32960,6 +35142,9 @@ sb_2__0__mux_2level_tapbuf_basis_input2_mem1_5 mux_l2_in_0_ ( .mem ( sram[1] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_5 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_2_out ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_107 ( .A ( BUF_net_108 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_108 ( + .A ( mux_2level_tapbuf_basis_input2_mem1_2_out[0] ) , .Y ( BUF_net_108 ) ) ; endmodule @@ -33018,8 +35203,6 @@ wire [0:0] mux_2level_tapbuf_basis_input2_mem1_2_out ; sb_2__0__const1_12 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( mux_2level_tapbuf_basis_input2_mem1_2_out[0] ) , .X ( out[0] ) ) ; sb_2__0__mux_2level_tapbuf_basis_input2_mem1_0 mux_l1_in_0_ ( .in ( in[0:1] ) , .mem ( sram[0] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_2 } ) , @@ -33035,6 +35218,9 @@ sb_2__0__mux_2level_tapbuf_basis_input2_mem1_2 mux_l2_in_0_ ( .mem ( sram[1] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_5 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_2_out ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_105 ( .A ( BUF_net_106 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_106 ( + .A ( mux_2level_tapbuf_basis_input2_mem1_2_out[0] ) , .Y ( BUF_net_106 ) ) ; endmodule @@ -33266,7 +35452,7 @@ input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ropt_net_186 ) , +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ropt_net_182 ) , .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; @@ -33275,28 +35461,28 @@ sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__buf_1 FTB_25__24 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1338 ( .A ( copt_net_161 ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1336 ( .A ( ccff_head[0] ) , + .X ( copt_net_153 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1337 ( .A ( copt_net_158 ) , + .X ( copt_net_154 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1338 ( .A ( copt_net_156 ) , + .X ( copt_net_155 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1339 ( .A ( copt_net_154 ) , + .X ( copt_net_156 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1340 ( .A ( copt_net_155 ) , + .X ( copt_net_157 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1341 ( .A ( copt_net_153 ) , .X ( copt_net_158 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1339 ( .A ( copt_net_158 ) , - .X ( copt_net_159 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1340 ( .A ( copt_net_163 ) , - .X ( copt_net_160 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1341 ( .A ( ccff_head[0] ) , - .X ( copt_net_161 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1342 ( .A ( copt_net_159 ) , - .X ( copt_net_162 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1343 ( .A ( copt_net_162 ) , - .X ( copt_net_163 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1361 ( .A ( ropt_net_184 ) , - .X ( ropt_net_183 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1362 ( .A ( copt_net_160 ) , - .X ( ropt_net_184 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1363 ( .A ( ropt_net_183 ) , - .X ( ropt_net_185 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1364 ( .A ( ropt_net_187 ) , - .X ( ropt_net_186 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1365 ( .A ( ropt_net_185 ) , - .X ( ropt_net_187 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1359 ( .A ( copt_net_157 ) , + .X ( ropt_net_178 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1360 ( .A ( ropt_net_178 ) , + .X ( ropt_net_179 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1361 ( .A ( ropt_net_179 ) , + .X ( ropt_net_180 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1362 ( .A ( ropt_net_180 ) , + .X ( ropt_net_181 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1363 ( .A ( ropt_net_181 ) , + .X ( ropt_net_182 ) ) ; endmodule @@ -33308,10 +35494,14 @@ input [0:2] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -33322,10 +35512,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -33412,10 +35606,14 @@ input [0:2] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -33426,10 +35624,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -33516,10 +35718,14 @@ input [0:2] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -33530,10 +35736,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -33620,10 +35830,14 @@ input [0:2] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -33634,10 +35848,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -33724,10 +35942,14 @@ input [0:2] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -33738,10 +35960,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -33828,10 +36054,14 @@ input [0:2] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -33842,10 +36072,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -33932,10 +36166,14 @@ input [0:2] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -33946,10 +36184,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -34022,8 +36264,9 @@ sb_2__0__mux_2level_tapbuf_basis_input3_mem3_11 mux_l2_in_0_ ( .mem ( local_encoder2to3_1_data ) , .mem_inv ( local_encoder2to3_1_data_inv ) , .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_92 ( - .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_91 ( .A ( BUF_net_92 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_92 ( + .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_92 ) ) ; endmodule @@ -34035,10 +36278,14 @@ input [0:2] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -34049,10 +36296,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -34125,9 +36376,9 @@ sb_2__0__mux_2level_tapbuf_basis_input3_mem3_9 mux_l2_in_0_ ( .mem ( local_encoder2to3_1_data ) , .mem_inv ( local_encoder2to3_1_data_inv ) , .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_90 ( .A ( BUF_net_91 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_91 ( - .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_91 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_89 ( .A ( BUF_net_90 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_90 ( + .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_90 ) ) ; endmodule @@ -34139,10 +36390,14 @@ input [0:2] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -34153,10 +36408,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -34229,9 +36488,8 @@ sb_2__0__mux_2level_tapbuf_basis_input3_mem3_7 mux_l2_in_0_ ( .mem ( local_encoder2to3_1_data ) , .mem_inv ( local_encoder2to3_1_data_inv ) , .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_88 ( .A ( BUF_net_89 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_89 ( - .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_89 ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_88 ( + .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .X ( out[0] ) ) ; endmodule @@ -34243,10 +36501,14 @@ input [0:2] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -34257,10 +36519,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -34346,10 +36612,14 @@ input [0:2] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -34360,10 +36630,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -34450,10 +36724,14 @@ input [0:2] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -34464,10 +36742,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -34701,84 +36983,84 @@ sb_2__0__mux_2level_tapbuf_size4_0 mux_top_track_0 ( .sram ( mux_2level_tapbuf_size4_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 , SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) , - .out ( chany_top_out[0] ) , .p0 ( optlc_net_156 ) ) ; + .out ( chany_top_out[0] ) , .p0 ( optlc_net_149 ) ) ; sb_2__0__mux_2level_tapbuf_size4_1 mux_top_track_2 ( .in ( { top_left_grid_pin_45_[0] , top_left_grid_pin_48_[0] , top_left_grid_pin_51_[0] , chanx_left_in[29] } ) , .sram ( mux_2level_tapbuf_size4_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 , SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 } ) , - .out ( chany_top_out[1] ) , .p0 ( optlc_net_156 ) ) ; + .out ( chany_top_out[1] ) , .p0 ( optlc_net_149 ) ) ; sb_2__0__mux_2level_tapbuf_size4_2 mux_top_track_4 ( .in ( { top_left_grid_pin_46_[0] , top_left_grid_pin_49_[0] , top_right_grid_pin_1_[0] , chanx_left_in[28] } ) , .sram ( mux_2level_tapbuf_size4_2_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_9 , SYNOPSYS_UNCONNECTED_10 , SYNOPSYS_UNCONNECTED_11 , SYNOPSYS_UNCONNECTED_12 } ) , - .out ( chany_top_out[2] ) , .p0 ( optlc_net_156 ) ) ; + .out ( chany_top_out[2] ) , .p0 ( optlc_net_149 ) ) ; sb_2__0__mux_2level_tapbuf_size4_3 mux_top_track_6 ( .in ( { top_left_grid_pin_44_[0] , top_left_grid_pin_47_[0] , top_left_grid_pin_50_[0] , chanx_left_in[27] } ) , .sram ( mux_2level_tapbuf_size4_3_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 , SYNOPSYS_UNCONNECTED_15 , SYNOPSYS_UNCONNECTED_16 } ) , - .out ( chany_top_out[3] ) , .p0 ( optlc_net_156 ) ) ; + .out ( chany_top_out[3] ) , .p0 ( optlc_net_149 ) ) ; sb_2__0__mux_2level_tapbuf_size4_4 mux_top_track_8 ( .in ( { top_left_grid_pin_45_[0] , top_left_grid_pin_48_[0] , top_left_grid_pin_51_[0] , chanx_left_in[26] } ) , .sram ( mux_2level_tapbuf_size4_4_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_17 , SYNOPSYS_UNCONNECTED_18 , SYNOPSYS_UNCONNECTED_19 , SYNOPSYS_UNCONNECTED_20 } ) , - .out ( chany_top_out[4] ) , .p0 ( optlc_net_156 ) ) ; + .out ( chany_top_out[4] ) , .p0 ( optlc_net_151 ) ) ; sb_2__0__mux_2level_tapbuf_size4_5 mux_top_track_10 ( .in ( { top_left_grid_pin_46_[0] , top_left_grid_pin_49_[0] , top_right_grid_pin_1_[0] , chanx_left_in[25] } ) , .sram ( mux_2level_tapbuf_size4_5_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_21 , SYNOPSYS_UNCONNECTED_22 , SYNOPSYS_UNCONNECTED_23 , SYNOPSYS_UNCONNECTED_24 } ) , - .out ( chany_top_out[5] ) , .p0 ( optlc_net_156 ) ) ; + .out ( chany_top_out[5] ) , .p0 ( optlc_net_152 ) ) ; sb_2__0__mux_2level_tapbuf_size4_6 mux_left_track_1 ( .in ( { chany_top_in[0] , left_bottom_grid_pin_1_[0] , left_bottom_grid_pin_7_[0] , left_bottom_grid_pin_13_[0] } ) , .sram ( mux_2level_tapbuf_size4_6_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_25 , SYNOPSYS_UNCONNECTED_26 , SYNOPSYS_UNCONNECTED_27 , SYNOPSYS_UNCONNECTED_28 } ) , - .out ( chanx_left_out[0] ) , .p0 ( optlc_net_154 ) ) ; + .out ( chanx_left_out[0] ) , .p0 ( optlc_net_147 ) ) ; sb_2__0__mux_2level_tapbuf_size4_7 mux_left_track_3 ( .in ( { chany_top_in[29] , left_bottom_grid_pin_3_[0] , left_bottom_grid_pin_9_[0] , left_bottom_grid_pin_15_[0] } ) , .sram ( mux_2level_tapbuf_size4_7_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_29 , SYNOPSYS_UNCONNECTED_30 , SYNOPSYS_UNCONNECTED_31 , SYNOPSYS_UNCONNECTED_32 } ) , - .out ( chanx_left_out[1] ) , .p0 ( optlc_net_154 ) ) ; + .out ( chanx_left_out[1] ) , .p0 ( optlc_net_147 ) ) ; sb_2__0__mux_2level_tapbuf_size4_8 mux_left_track_5 ( .in ( { chany_top_in[28] , left_bottom_grid_pin_5_[0] , left_bottom_grid_pin_11_[0] , left_bottom_grid_pin_17_[0] } ) , .sram ( mux_2level_tapbuf_size4_8_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_33 , SYNOPSYS_UNCONNECTED_34 , SYNOPSYS_UNCONNECTED_35 , SYNOPSYS_UNCONNECTED_36 } ) , - .out ( chanx_left_out[2] ) , .p0 ( optlc_net_154 ) ) ; + .out ( chanx_left_out[2] ) , .p0 ( optlc_net_147 ) ) ; sb_2__0__mux_2level_tapbuf_size4_9 mux_left_track_7 ( .in ( { chany_top_in[27] , left_bottom_grid_pin_1_[0] , left_bottom_grid_pin_7_[0] , left_bottom_grid_pin_13_[0] } ) , .sram ( mux_2level_tapbuf_size4_9_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_37 , SYNOPSYS_UNCONNECTED_38 , SYNOPSYS_UNCONNECTED_39 , SYNOPSYS_UNCONNECTED_40 } ) , - .out ( chanx_left_out[3] ) , .p0 ( optlc_net_154 ) ) ; + .out ( chanx_left_out[3] ) , .p0 ( optlc_net_147 ) ) ; sb_2__0__mux_2level_tapbuf_size4_10 mux_left_track_9 ( .in ( { chany_top_in[26] , left_bottom_grid_pin_3_[0] , left_bottom_grid_pin_9_[0] , left_bottom_grid_pin_15_[0] } ) , .sram ( mux_2level_tapbuf_size4_10_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_41 , SYNOPSYS_UNCONNECTED_42 , SYNOPSYS_UNCONNECTED_43 , SYNOPSYS_UNCONNECTED_44 } ) , - .out ( chanx_left_out[4] ) , .p0 ( optlc_net_154 ) ) ; + .out ( chanx_left_out[4] ) , .p0 ( optlc_net_149 ) ) ; sb_2__0__mux_2level_tapbuf_size4 mux_left_track_11 ( .in ( { chany_top_in[25] , left_bottom_grid_pin_5_[0] , left_bottom_grid_pin_11_[0] , left_bottom_grid_pin_17_[0] } ) , .sram ( mux_2level_tapbuf_size4_11_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_45 , SYNOPSYS_UNCONNECTED_46 , SYNOPSYS_UNCONNECTED_47 , SYNOPSYS_UNCONNECTED_48 } ) , - .out ( chanx_left_out[5] ) , .p0 ( optlc_net_156 ) ) ; + .out ( chanx_left_out[5] ) , .p0 ( optlc_net_151 ) ) ; sb_2__0__mux_2level_tapbuf_size4_mem_0 mem_top_track_0 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( mux_2level_tapbuf_size4_mem_0_ccff_tail ) , @@ -34843,31 +37125,31 @@ sb_2__0__mux_2level_tapbuf_size3_0 mux_top_track_12 ( chanx_left_in[24] } ) , .sram ( mux_2level_tapbuf_size3_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_49 , SYNOPSYS_UNCONNECTED_50 } ) , - .out ( chany_top_out[6] ) , .p0 ( optlc_net_157 ) ) ; + .out ( chany_top_out[6] ) , .p0 ( optlc_net_148 ) ) ; sb_2__0__mux_2level_tapbuf_size3_1 mux_top_track_44 ( .in ( { top_left_grid_pin_48_[0] , top_right_grid_pin_1_[0] , chanx_left_in[8] } ) , .sram ( mux_2level_tapbuf_size3_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_51 , SYNOPSYS_UNCONNECTED_52 } ) , - .out ( chany_top_out[22] ) , .p0 ( optlc_net_156 ) ) ; + .out ( chany_top_out[22] ) , .p0 ( optlc_net_151 ) ) ; sb_2__0__mux_2level_tapbuf_size3_2 mux_left_track_13 ( .in ( { chany_top_in[24] , left_bottom_grid_pin_1_[0] , left_bottom_grid_pin_17_[0] } ) , .sram ( mux_2level_tapbuf_size3_2_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_53 , SYNOPSYS_UNCONNECTED_54 } ) , - .out ( chanx_left_out[6] ) , .p0 ( optlc_net_157 ) ) ; + .out ( chanx_left_out[6] ) , .p0 ( optlc_net_151 ) ) ; sb_2__0__mux_2level_tapbuf_size3_3 mux_left_track_29 ( .in ( { chany_top_in[16] , left_bottom_grid_pin_1_[0] , left_bottom_grid_pin_17_[0] } ) , .sram ( mux_2level_tapbuf_size3_3_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_55 , SYNOPSYS_UNCONNECTED_56 } ) , - .out ( chanx_left_out[14] ) , .p0 ( optlc_net_155 ) ) ; + .out ( chanx_left_out[14] ) , .p0 ( optlc_net_147 ) ) ; sb_2__0__mux_2level_tapbuf_size3 mux_left_track_45 ( .in ( { chany_top_in[8] , left_bottom_grid_pin_1_[0] , left_bottom_grid_pin_17_[0] } ) , .sram ( mux_2level_tapbuf_size3_4_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_57 , SYNOPSYS_UNCONNECTED_58 } ) , - .out ( chanx_left_out[22] ) , .p0 ( optlc_net_155 ) ) ; + .out ( chanx_left_out[22] ) , .p0 ( optlc_net_147 ) ) ; sb_2__0__mux_2level_tapbuf_size3_mem_0 mem_top_track_12 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( mux_2level_tapbuf_size4_mem_5_ccff_tail ) , @@ -34897,182 +37179,182 @@ sb_2__0__mux_2level_tapbuf_size2_0 mux_top_track_14 ( .in ( { top_left_grid_pin_45_[0] , chanx_left_in[23] } ) , .sram ( mux_2level_tapbuf_size2_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_59 , SYNOPSYS_UNCONNECTED_60 } ) , - .out ( chany_top_out[7] ) , .p0 ( optlc_net_157 ) ) ; + .out ( chany_top_out[7] ) , .p0 ( optlc_net_148 ) ) ; sb_2__0__mux_2level_tapbuf_size2_1 mux_top_track_16 ( .in ( { top_left_grid_pin_46_[0] , chanx_left_in[22] } ) , .sram ( mux_2level_tapbuf_size2_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_61 , SYNOPSYS_UNCONNECTED_62 } ) , - .out ( chany_top_out[8] ) , .p0 ( optlc_net_157 ) ) ; + .out ( chany_top_out[8] ) , .p0 ( optlc_net_152 ) ) ; sb_2__0__mux_2level_tapbuf_size2_2 mux_top_track_18 ( .in ( { top_left_grid_pin_47_[0] , chanx_left_in[21] } ) , .sram ( mux_2level_tapbuf_size2_2_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_63 , SYNOPSYS_UNCONNECTED_64 } ) , - .out ( chany_top_out[9] ) , .p0 ( optlc_net_157 ) ) ; + .out ( chany_top_out[9] ) , .p0 ( optlc_net_148 ) ) ; sb_2__0__mux_2level_tapbuf_size2_3 mux_top_track_20 ( .in ( { top_left_grid_pin_48_[0] , chanx_left_in[20] } ) , .sram ( mux_2level_tapbuf_size2_3_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_65 , SYNOPSYS_UNCONNECTED_66 } ) , - .out ( chany_top_out[10] ) , .p0 ( optlc_net_157 ) ) ; + .out ( chany_top_out[10] ) , .p0 ( optlc_net_150 ) ) ; sb_2__0__mux_2level_tapbuf_size2_4 mux_top_track_22 ( .in ( { top_left_grid_pin_49_[0] , chanx_left_in[19] } ) , .sram ( mux_2level_tapbuf_size2_4_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_67 , SYNOPSYS_UNCONNECTED_68 } ) , - .out ( chany_top_out[11] ) , .p0 ( optlc_net_157 ) ) ; + .out ( chany_top_out[11] ) , .p0 ( optlc_net_150 ) ) ; sb_2__0__mux_2level_tapbuf_size2_5 mux_top_track_24 ( .in ( { top_left_grid_pin_50_[0] , chanx_left_in[18] } ) , .sram ( mux_2level_tapbuf_size2_5_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_69 , SYNOPSYS_UNCONNECTED_70 } ) , - .out ( chany_top_out[12] ) , .p0 ( optlc_net_155 ) ) ; + .out ( chany_top_out[12] ) , .p0 ( optlc_net_148 ) ) ; sb_2__0__mux_2level_tapbuf_size2_6 mux_top_track_26 ( .in ( { top_left_grid_pin_51_[0] , chanx_left_in[17] } ) , .sram ( mux_2level_tapbuf_size2_6_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_71 , SYNOPSYS_UNCONNECTED_72 } ) , - .out ( chany_top_out[13] ) , .p0 ( optlc_net_155 ) ) ; + .out ( chany_top_out[13] ) , .p0 ( optlc_net_150 ) ) ; sb_2__0__mux_2level_tapbuf_size2_7 mux_top_track_28 ( .in ( { top_right_grid_pin_1_[0] , chanx_left_in[16] } ) , .sram ( mux_2level_tapbuf_size2_7_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_73 , SYNOPSYS_UNCONNECTED_74 } ) , - .out ( chany_top_out[14] ) , .p0 ( optlc_net_157 ) ) ; + .out ( chany_top_out[14] ) , .p0 ( optlc_net_148 ) ) ; sb_2__0__mux_2level_tapbuf_size2_8 mux_top_track_36 ( .in ( { top_left_grid_pin_44_[0] , chanx_left_in[12] } ) , .sram ( mux_2level_tapbuf_size2_8_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_75 , SYNOPSYS_UNCONNECTED_76 } ) , - .out ( chany_top_out[18] ) , .p0 ( optlc_net_157 ) ) ; + .out ( chany_top_out[18] ) , .p0 ( optlc_net_148 ) ) ; sb_2__0__mux_2level_tapbuf_size2_9 mux_top_track_38 ( .in ( { top_left_grid_pin_45_[0] , chanx_left_in[11] } ) , .sram ( mux_2level_tapbuf_size2_9_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_77 , SYNOPSYS_UNCONNECTED_78 } ) , - .out ( chany_top_out[19] ) , .p0 ( optlc_net_157 ) ) ; + .out ( chany_top_out[19] ) , .p0 ( optlc_net_148 ) ) ; sb_2__0__mux_2level_tapbuf_size2_10 mux_top_track_40 ( .in ( { top_left_grid_pin_46_[0] , chanx_left_in[10] } ) , .sram ( mux_2level_tapbuf_size2_10_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_79 , SYNOPSYS_UNCONNECTED_80 } ) , - .out ( chany_top_out[20] ) , .p0 ( optlc_net_157 ) ) ; + .out ( chany_top_out[20] ) , .p0 ( optlc_net_148 ) ) ; sb_2__0__mux_2level_tapbuf_size2_11 mux_top_track_42 ( .in ( { top_left_grid_pin_47_[0] , chanx_left_in[9] } ) , .sram ( mux_2level_tapbuf_size2_11_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_81 , SYNOPSYS_UNCONNECTED_82 } ) , - .out ( chany_top_out[21] ) , .p0 ( optlc_net_157 ) ) ; + .out ( chany_top_out[21] ) , .p0 ( optlc_net_148 ) ) ; sb_2__0__mux_2level_tapbuf_size2_12 mux_top_track_46 ( .in ( { top_left_grid_pin_49_[0] , chanx_left_in[7] } ) , .sram ( mux_2level_tapbuf_size2_12_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_83 , SYNOPSYS_UNCONNECTED_84 } ) , - .out ( chany_top_out[23] ) , .p0 ( optlc_net_156 ) ) ; + .out ( chany_top_out[23] ) , .p0 ( optlc_net_149 ) ) ; sb_2__0__mux_2level_tapbuf_size2_13 mux_top_track_48 ( .in ( { top_left_grid_pin_50_[0] , chanx_left_in[6] } ) , .sram ( mux_2level_tapbuf_size2_13_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_85 , SYNOPSYS_UNCONNECTED_86 } ) , - .out ( chany_top_out[24] ) , .p0 ( optlc_net_156 ) ) ; + .out ( chany_top_out[24] ) , .p0 ( optlc_net_152 ) ) ; sb_2__0__mux_2level_tapbuf_size2_14 mux_top_track_50 ( .in ( { top_left_grid_pin_51_[0] , chanx_left_in[5] } ) , .sram ( mux_2level_tapbuf_size2_14_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_87 , SYNOPSYS_UNCONNECTED_88 } ) , - .out ( chany_top_out[25] ) , .p0 ( optlc_net_156 ) ) ; + .out ( chany_top_out[25] ) , .p0 ( optlc_net_149 ) ) ; sb_2__0__mux_2level_tapbuf_size2_15 mux_left_track_15 ( .in ( { chany_top_in[23] , left_bottom_grid_pin_3_[0] } ) , .sram ( mux_2level_tapbuf_size2_15_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_89 , SYNOPSYS_UNCONNECTED_90 } ) , - .out ( chanx_left_out[7] ) , .p0 ( optlc_net_157 ) ) ; + .out ( chanx_left_out[7] ) , .p0 ( optlc_net_152 ) ) ; sb_2__0__mux_2level_tapbuf_size2_16 mux_left_track_17 ( .in ( { chany_top_in[22] , left_bottom_grid_pin_5_[0] } ) , .sram ( mux_2level_tapbuf_size2_16_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_91 , SYNOPSYS_UNCONNECTED_92 } ) , - .out ( chanx_left_out[8] ) , .p0 ( optlc_net_157 ) ) ; + .out ( chanx_left_out[8] ) , .p0 ( optlc_net_152 ) ) ; sb_2__0__mux_2level_tapbuf_size2_17 mux_left_track_19 ( .in ( { chany_top_in[21] , left_bottom_grid_pin_7_[0] } ) , .sram ( mux_2level_tapbuf_size2_17_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_93 , SYNOPSYS_UNCONNECTED_94 } ) , - .out ( chanx_left_out[9] ) , .p0 ( optlc_net_157 ) ) ; + .out ( chanx_left_out[9] ) , .p0 ( optlc_net_148 ) ) ; sb_2__0__mux_2level_tapbuf_size2_18 mux_left_track_21 ( .in ( { chany_top_in[20] , left_bottom_grid_pin_9_[0] } ) , .sram ( mux_2level_tapbuf_size2_18_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_95 , SYNOPSYS_UNCONNECTED_96 } ) , - .out ( chanx_left_out[10] ) , .p0 ( optlc_net_155 ) ) ; + .out ( chanx_left_out[10] ) , .p0 ( optlc_net_148 ) ) ; sb_2__0__mux_2level_tapbuf_size2_19 mux_left_track_23 ( .in ( { chany_top_in[19] , left_bottom_grid_pin_11_[0] } ) , .sram ( mux_2level_tapbuf_size2_19_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_97 , SYNOPSYS_UNCONNECTED_98 } ) , - .out ( chanx_left_out[11] ) , .p0 ( optlc_net_155 ) ) ; + .out ( chanx_left_out[11] ) , .p0 ( optlc_net_150 ) ) ; sb_2__0__mux_2level_tapbuf_size2_20 mux_left_track_25 ( .in ( { chany_top_in[18] , left_bottom_grid_pin_13_[0] } ) , .sram ( mux_2level_tapbuf_size2_20_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_99 , SYNOPSYS_UNCONNECTED_100 } ) , - .out ( chanx_left_out[12] ) , .p0 ( optlc_net_155 ) ) ; + .out ( chanx_left_out[12] ) , .p0 ( optlc_net_148 ) ) ; sb_2__0__mux_2level_tapbuf_size2_21 mux_left_track_27 ( .in ( { chany_top_in[17] , left_bottom_grid_pin_15_[0] } ) , .sram ( mux_2level_tapbuf_size2_21_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_101 , SYNOPSYS_UNCONNECTED_102 } ) , - .out ( chanx_left_out[13] ) , .p0 ( optlc_net_155 ) ) ; + .out ( chanx_left_out[13] ) , .p0 ( optlc_net_150 ) ) ; sb_2__0__mux_2level_tapbuf_size2_22 mux_left_track_31 ( .in ( { chany_top_in[15] , left_bottom_grid_pin_3_[0] } ) , .sram ( mux_2level_tapbuf_size2_22_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_103 , SYNOPSYS_UNCONNECTED_104 } ) , - .out ( chanx_left_out[15] ) , .p0 ( optlc_net_155 ) ) ; + .out ( chanx_left_out[15] ) , .p0 ( optlc_net_150 ) ) ; sb_2__0__mux_2level_tapbuf_size2_23 mux_left_track_33 ( .in ( { chany_top_in[14] , left_bottom_grid_pin_5_[0] } ) , .sram ( mux_2level_tapbuf_size2_23_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_105 , SYNOPSYS_UNCONNECTED_106 } ) , - .out ( chanx_left_out[16] ) , .p0 ( optlc_net_155 ) ) ; + .out ( chanx_left_out[16] ) , .p0 ( optlc_net_150 ) ) ; sb_2__0__mux_2level_tapbuf_size2_24 mux_left_track_35 ( .in ( { chany_top_in[13] , left_bottom_grid_pin_7_[0] } ) , .sram ( mux_2level_tapbuf_size2_24_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_107 , SYNOPSYS_UNCONNECTED_108 } ) , - .out ( chanx_left_out[17] ) , .p0 ( optlc_net_154 ) ) ; + .out ( chanx_left_out[17] ) , .p0 ( optlc_net_150 ) ) ; sb_2__0__mux_2level_tapbuf_size2_25 mux_left_track_37 ( .in ( { chany_top_in[12] , left_bottom_grid_pin_9_[0] } ) , .sram ( mux_2level_tapbuf_size2_25_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_109 , SYNOPSYS_UNCONNECTED_110 } ) , - .out ( chanx_left_out[18] ) , .p0 ( optlc_net_154 ) ) ; + .out ( chanx_left_out[18] ) , .p0 ( optlc_net_150 ) ) ; sb_2__0__mux_2level_tapbuf_size2_26 mux_left_track_39 ( .in ( { chany_top_in[11] , left_bottom_grid_pin_11_[0] } ) , .sram ( mux_2level_tapbuf_size2_26_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_111 , SYNOPSYS_UNCONNECTED_112 } ) , - .out ( chanx_left_out[19] ) , .p0 ( optlc_net_155 ) ) ; + .out ( chanx_left_out[19] ) , .p0 ( optlc_net_150 ) ) ; sb_2__0__mux_2level_tapbuf_size2_27 mux_left_track_41 ( .in ( { chany_top_in[10] , left_bottom_grid_pin_13_[0] } ) , .sram ( mux_2level_tapbuf_size2_27_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_113 , SYNOPSYS_UNCONNECTED_114 } ) , - .out ( chanx_left_out[20] ) , .p0 ( optlc_net_155 ) ) ; + .out ( chanx_left_out[20] ) , .p0 ( optlc_net_150 ) ) ; sb_2__0__mux_2level_tapbuf_size2_28 mux_left_track_43 ( .in ( { chany_top_in[9] , left_bottom_grid_pin_15_[0] } ) , .sram ( mux_2level_tapbuf_size2_28_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_115 , SYNOPSYS_UNCONNECTED_116 } ) , - .out ( chanx_left_out[21] ) , .p0 ( optlc_net_155 ) ) ; + .out ( chanx_left_out[21] ) , .p0 ( optlc_net_150 ) ) ; sb_2__0__mux_2level_tapbuf_size2_29 mux_left_track_47 ( .in ( { chany_top_in[7] , left_bottom_grid_pin_3_[0] } ) , .sram ( mux_2level_tapbuf_size2_29_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_117 , SYNOPSYS_UNCONNECTED_118 } ) , - .out ( chanx_left_out[23] ) , .p0 ( optlc_net_154 ) ) ; + .out ( chanx_left_out[23] ) , .p0 ( optlc_net_150 ) ) ; sb_2__0__mux_2level_tapbuf_size2_30 mux_left_track_49 ( .in ( { chany_top_in[6] , left_bottom_grid_pin_5_[0] } ) , .sram ( mux_2level_tapbuf_size2_30_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_119 , SYNOPSYS_UNCONNECTED_120 } ) , - .out ( chanx_left_out[24] ) , .p0 ( optlc_net_154 ) ) ; + .out ( chanx_left_out[24] ) , .p0 ( optlc_net_147 ) ) ; sb_2__0__mux_2level_tapbuf_size2_31 mux_left_track_51 ( .in ( { chany_top_in[5] , left_bottom_grid_pin_7_[0] } ) , .sram ( mux_2level_tapbuf_size2_31_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_121 , SYNOPSYS_UNCONNECTED_122 } ) , - .out ( chanx_left_out[25] ) , .p0 ( optlc_net_154 ) ) ; + .out ( chanx_left_out[25] ) , .p0 ( optlc_net_148 ) ) ; sb_2__0__mux_2level_tapbuf_size2_32 mux_left_track_53 ( .in ( { chany_top_in[4] , left_bottom_grid_pin_9_[0] } ) , .sram ( mux_2level_tapbuf_size2_32_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_123 , SYNOPSYS_UNCONNECTED_124 } ) , - .out ( chanx_left_out[26] ) , .p0 ( optlc_net_155 ) ) ; + .out ( chanx_left_out[26] ) , .p0 ( optlc_net_152 ) ) ; sb_2__0__mux_2level_tapbuf_size2_33 mux_left_track_55 ( .in ( { chany_top_in[3] , left_bottom_grid_pin_11_[0] } ) , .sram ( mux_2level_tapbuf_size2_33_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_125 , SYNOPSYS_UNCONNECTED_126 } ) , - .out ( chanx_left_out[27] ) , .p0 ( optlc_net_155 ) ) ; + .out ( chanx_left_out[27] ) , .p0 ( optlc_net_148 ) ) ; sb_2__0__mux_2level_tapbuf_size2_34 mux_left_track_57 ( .in ( { chany_top_in[2] , left_bottom_grid_pin_13_[0] } ) , .sram ( mux_2level_tapbuf_size2_34_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_127 , SYNOPSYS_UNCONNECTED_128 } ) , - .out ( chanx_left_out[28] ) , .p0 ( optlc_net_157 ) ) ; + .out ( chanx_left_out[28] ) , .p0 ( optlc_net_148 ) ) ; sb_2__0__mux_2level_tapbuf_size2 mux_left_track_59 ( .in ( { chany_top_in[1] , left_bottom_grid_pin_15_[0] } ) , .sram ( mux_2level_tapbuf_size2_35_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_129 , SYNOPSYS_UNCONNECTED_130 } ) , - .out ( chanx_left_out[29] ) , .p0 ( optlc_net_157 ) ) ; + .out ( chanx_left_out[29] ) , .p0 ( optlc_net_152 ) ) ; sb_2__0__mux_2level_tapbuf_size2_mem_0 mem_top_track_14 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( mux_2level_tapbuf_size3_mem_0_ccff_tail ) , @@ -35253,32 +37535,36 @@ sb_2__0__mux_2level_tapbuf_size2_mem mem_left_track_59 ( .pReset ( pReset ) , .ccff_head ( mux_2level_tapbuf_size2_mem_34_ccff_tail ) , .ccff_tail ( ccff_tail ) , .mem_out ( mux_2level_tapbuf_size2_35_sram ) ) ; sky130_fd_sc_hd__buf_8 pReset_FTB00 ( .A ( pReset_W_in ) , .X ( pReset[0] ) ) ; -sky130_fd_sc_hd__conb_1 optlc_156 ( .LO ( SYNOPSYS_UNCONNECTED_131 ) , - .HI ( optlc_net_154 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_149 ( .LO ( SYNOPSYS_UNCONNECTED_131 ) , + .HI ( optlc_net_147 ) ) ; sky130_fd_sc_hd__buf_1 prog_clk_0_FTB00 ( .A ( prog_clk_0_N_in ) , .X ( prog_clk[0] ) ) ; -sky130_fd_sc_hd__buf_8 FTB_78__77 ( .A ( chanx_left_in[1] ) , +sky130_fd_sc_hd__buf_6 FTB_78__77 ( .A ( chanx_left_in[1] ) , .X ( chany_top_out[29] ) ) ; -sky130_fd_sc_hd__buf_6 FTB_79__78 ( .A ( chanx_left_in[2] ) , +sky130_fd_sc_hd__buf_8 FTB_79__78 ( .A ( chanx_left_in[2] ) , .X ( chany_top_out[28] ) ) ; sky130_fd_sc_hd__buf_8 FTB_80__79 ( .A ( chanx_left_in[3] ) , .X ( chany_top_out[27] ) ) ; sky130_fd_sc_hd__buf_8 FTB_81__80 ( .A ( chanx_left_in[4] ) , .X ( chany_top_out[26] ) ) ; -sky130_fd_sc_hd__buf_8 FTB_82__81 ( .A ( chanx_left_in[13] ) , +sky130_fd_sc_hd__buf_6 FTB_82__81 ( .A ( chanx_left_in[13] ) , .X ( chany_top_out[17] ) ) ; sky130_fd_sc_hd__buf_8 FTB_83__82 ( .A ( chanx_left_in[14] ) , .X ( chany_top_out[16] ) ) ; sky130_fd_sc_hd__buf_8 FTB_84__83 ( .A ( chanx_left_in[15] ) , .X ( chany_top_out[15] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_152 ( .A ( BUF_net_153 ) , .Y ( pReset_N_out ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_153 ( .A ( pReset_W_in ) , .Y ( BUF_net_153 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_158 ( .LO ( SYNOPSYS_UNCONNECTED_132 ) , - .HI ( optlc_net_155 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_160 ( .LO ( SYNOPSYS_UNCONNECTED_133 ) , - .HI ( optlc_net_156 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_162 ( .LO ( SYNOPSYS_UNCONNECTED_134 ) , - .HI ( optlc_net_157 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_143 ( .A ( BUF_net_144 ) , .Y ( pReset_N_out ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_144 ( .A ( pReset_W_in ) , .Y ( BUF_net_144 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_151 ( .LO ( SYNOPSYS_UNCONNECTED_132 ) , + .HI ( optlc_net_148 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_153 ( .LO ( SYNOPSYS_UNCONNECTED_133 ) , + .HI ( optlc_net_149 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_156 ( .LO ( SYNOPSYS_UNCONNECTED_134 ) , + .HI ( optlc_net_150 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_158 ( .LO ( SYNOPSYS_UNCONNECTED_135 ) , + .HI ( optlc_net_151 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_160 ( .LO ( SYNOPSYS_UNCONNECTED_136 ) , + .HI ( optlc_net_152 ) ) ; endmodule @@ -35472,7 +37758,7 @@ input [0:0] mem_inv ; output [0:0] out ; input p0 ; -sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , +sky130_fd_sc_hd__mux2_2 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ; endmodule @@ -35563,8 +37849,6 @@ wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ; sb_1__2__const1_46 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) ) ; sb_1__2__mux_2level_tapbuf_basis_input2_mem1_30 mux_l1_in_0_ ( .in ( in ) , .mem ( sram[0] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_2 } ) , @@ -35575,6 +37859,9 @@ sb_1__2__mux_2level_tapbuf_basis_input2_mem1_31 mux_l2_in_0_ ( .mem ( sram[1] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_4 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_195 ( .A ( BUF_net_196 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_196 ( + .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_196 ) ) ; endmodule @@ -35586,7 +37873,7 @@ input [0:0] mem_inv ; output [0:0] out ; input p0 ; -sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , +sky130_fd_sc_hd__mux2_2 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ; endmodule @@ -35643,7 +37930,7 @@ input [0:0] mem_inv ; output [0:0] out ; input p0 ; -sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , +sky130_fd_sc_hd__mux2_2 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ; endmodule @@ -35734,6 +38021,8 @@ wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ; sb_1__2__const1_43 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) ) ; sb_1__2__mux_2level_tapbuf_basis_input2_mem1_24 mux_l1_in_0_ ( .in ( in ) , .mem ( sram[0] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_2 } ) , @@ -35744,8 +38033,6 @@ sb_1__2__mux_2level_tapbuf_basis_input2_mem1_25 mux_l2_in_0_ ( .mem ( sram[1] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_4 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_197 ( - .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) ) ; endmodule @@ -35791,6 +38078,8 @@ wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ; sb_1__2__const1_42 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) ) ; sb_1__2__mux_2level_tapbuf_basis_input2_mem1_22 mux_l1_in_0_ ( .in ( in ) , .mem ( sram[0] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_2 } ) , @@ -35801,9 +38090,6 @@ sb_1__2__mux_2level_tapbuf_basis_input2_mem1_23 mux_l2_in_0_ ( .mem ( sram[1] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_4 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_195 ( .A ( BUF_net_196 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_196 ( - .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_196 ) ) ; endmodule @@ -35815,7 +38101,7 @@ input [0:0] mem_inv ; output [0:0] out ; input p0 ; -sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , +sky130_fd_sc_hd__mux2_2 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ; endmodule @@ -35849,8 +38135,6 @@ wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ; sb_1__2__const1_41 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) ) ; sb_1__2__mux_2level_tapbuf_basis_input2_mem1_20 mux_l1_in_0_ ( .in ( in ) , .mem ( sram[0] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_2 } ) , @@ -35861,6 +38145,8 @@ sb_1__2__mux_2level_tapbuf_basis_input2_mem1_21 mux_l2_in_0_ ( .mem ( sram[1] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_4 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_194 ( + .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) ) ; endmodule @@ -35872,7 +38158,7 @@ input [0:0] mem_inv ; output [0:0] out ; input p0 ; -sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , +sky130_fd_sc_hd__mux2_2 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ; endmodule @@ -35906,6 +38192,8 @@ wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ; sb_1__2__const1_40 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) ) ; sb_1__2__mux_2level_tapbuf_basis_input2_mem1_18 mux_l1_in_0_ ( .in ( in ) , .mem ( sram[0] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_2 } ) , @@ -35916,9 +38204,6 @@ sb_1__2__mux_2level_tapbuf_basis_input2_mem1_19 mux_l2_in_0_ ( .mem ( sram[1] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_4 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_193 ( .A ( BUF_net_194 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_194 ( - .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_194 ) ) ; endmodule @@ -35930,7 +38215,7 @@ input [0:0] mem_inv ; output [0:0] out ; input p0 ; -sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , +sky130_fd_sc_hd__mux2_2 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ; endmodule @@ -36078,6 +38363,8 @@ wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ; sb_1__2__const1_37 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) ) ; sb_1__2__mux_2level_tapbuf_basis_input2_mem1_12 mux_l1_in_0_ ( .in ( in ) , .mem ( sram[0] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_2 } ) , @@ -36088,8 +38375,6 @@ sb_1__2__mux_2level_tapbuf_basis_input2_mem1_13 mux_l2_in_0_ ( .mem ( sram[1] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_4 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_192 ( - .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) ) ; endmodule @@ -36164,7 +38449,7 @@ input [0:0] mem ; input [0:0] mem_inv ; output [0:0] out ; -sky130_fd_sc_hd__mux2_2 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) , +sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ; endmodule @@ -36212,8 +38497,6 @@ wire [0:0] mux_2level_tapbuf_basis_input2_mem1_2_out ; sb_1__2__const1_36 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( mux_2level_tapbuf_basis_input2_mem1_2_out[0] ) , .X ( out[0] ) ) ; sb_1__2__mux_2level_tapbuf_basis_input2_mem1_9 mux_l1_in_0_ ( .in ( in[0:1] ) , .mem ( sram[0] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_2 } ) , @@ -36229,6 +38512,9 @@ sb_1__2__mux_2level_tapbuf_basis_input2_mem1_11 mux_l2_in_0_ ( .mem ( sram[1] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_5 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_2_out ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_192 ( .A ( BUF_net_193 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_193 ( + .A ( mux_2level_tapbuf_basis_input2_mem1_2_out[0] ) , .Y ( BUF_net_193 ) ) ; endmodule @@ -36362,6 +38648,8 @@ wire [0:0] mux_2level_tapbuf_basis_input2_mem1_2_out ; sb_1__2__const1_34 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( mux_2level_tapbuf_basis_input2_mem1_2_out[0] ) , .X ( out[0] ) ) ; sb_1__2__mux_2level_tapbuf_basis_input2_mem1_3 mux_l1_in_0_ ( .in ( in[0:1] ) , .mem ( sram[0] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_2 } ) , @@ -36377,8 +38665,6 @@ sb_1__2__mux_2level_tapbuf_basis_input2_mem1_5 mux_l2_in_0_ ( .mem ( sram[1] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_5 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_2_out ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_191 ( - .A ( mux_2level_tapbuf_basis_input2_mem1_2_out[0] ) , .X ( out[0] ) ) ; endmodule @@ -36452,9 +38738,9 @@ sb_1__2__mux_2level_tapbuf_basis_input2_mem1_2 mux_l2_in_0_ ( .mem ( sram[1] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_5 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_2_out ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_189 ( .A ( BUF_net_190 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_190 ( - .A ( mux_2level_tapbuf_basis_input2_mem1_2_out[0] ) , .Y ( BUF_net_190 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_190 ( .A ( BUF_net_191 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_191 ( + .A ( mux_2level_tapbuf_basis_input2_mem1_2_out[0] ) , .Y ( BUF_net_191 ) ) ; endmodule @@ -36546,10 +38832,14 @@ input [0:2] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -36560,10 +38850,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -36574,10 +38868,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -36656,9 +38954,9 @@ sb_1__2__mux_2level_tapbuf_basis_input3_mem3 mux_l2_in_0_ ( .mem ( local_encoder2to3_1_data ) , .mem_inv ( local_encoder2to3_1_data_inv ) , .out ( mux_2level_tapbuf_basis_input3_mem3_2_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_187 ( .A ( BUF_net_188 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_188 ( - .A ( mux_2level_tapbuf_basis_input3_mem3_2_out[0] ) , .Y ( BUF_net_188 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_188 ( .A ( BUF_net_189 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_189 ( + .A ( mux_2level_tapbuf_basis_input3_mem3_2_out[0] ) , .Y ( BUF_net_189 ) ) ; endmodule @@ -36670,10 +38968,14 @@ input [0:2] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -36684,10 +38986,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -36698,10 +39004,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -36780,9 +39090,8 @@ sb_1__2__mux_2level_tapbuf_basis_input3_mem3_73 mux_l2_in_0_ ( .mem ( local_encoder2to3_1_data ) , .mem_inv ( local_encoder2to3_1_data_inv ) , .out ( mux_2level_tapbuf_basis_input3_mem3_2_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_185 ( .A ( BUF_net_186 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_186 ( - .A ( mux_2level_tapbuf_basis_input3_mem3_2_out[0] ) , .Y ( BUF_net_186 ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_187 ( + .A ( mux_2level_tapbuf_basis_input3_mem3_2_out[0] ) , .X ( out[0] ) ) ; endmodule @@ -36794,10 +39103,14 @@ input [0:2] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -36808,10 +39121,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -36822,10 +39139,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -36904,7 +39225,7 @@ sb_1__2__mux_2level_tapbuf_basis_input3_mem3_70 mux_l2_in_0_ ( .mem ( local_encoder2to3_1_data ) , .mem_inv ( local_encoder2to3_1_data_inv ) , .out ( mux_2level_tapbuf_basis_input3_mem3_2_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_184 ( +sky130_fd_sc_hd__buf_6 BUFT_RR_186 ( .A ( mux_2level_tapbuf_basis_input3_mem3_2_out[0] ) , .X ( out[0] ) ) ; endmodule @@ -36917,10 +39238,14 @@ input [0:2] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -36931,10 +39256,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -36945,10 +39274,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -37027,9 +39360,9 @@ sb_1__2__mux_2level_tapbuf_basis_input3_mem3_67 mux_l2_in_0_ ( .mem ( local_encoder2to3_1_data ) , .mem_inv ( local_encoder2to3_1_data_inv ) , .out ( mux_2level_tapbuf_basis_input3_mem3_2_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_182 ( .A ( BUF_net_183 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_183 ( - .A ( mux_2level_tapbuf_basis_input3_mem3_2_out[0] ) , .Y ( BUF_net_183 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_184 ( .A ( BUF_net_185 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_185 ( + .A ( mux_2level_tapbuf_basis_input3_mem3_2_out[0] ) , .Y ( BUF_net_185 ) ) ; endmodule @@ -37201,10 +39534,14 @@ input [0:2] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -37215,10 +39552,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -37304,10 +39645,14 @@ input [0:2] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -37318,10 +39663,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -37378,8 +39727,6 @@ wire [0:0] mux_2level_tapbuf_basis_input3_mem3_1_out ; sb_1__2__const1_27 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .X ( out[0] ) ) ; sb_1__2__local_encoder2to3_46 local_encoder2to3_0_ ( .addr ( sram[0:1] ) , .data ( local_encoder2to3_0_data ) , .data_inv ( local_encoder2to3_0_data_inv ) ) ; @@ -37396,6 +39743,8 @@ sb_1__2__mux_2level_tapbuf_basis_input3_mem3_62 mux_l2_in_0_ ( .mem ( local_encoder2to3_1_data ) , .mem_inv ( local_encoder2to3_1_data_inv ) , .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .p0 ( p0 ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_183 ( + .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .X ( out[0] ) ) ; endmodule @@ -37407,10 +39756,14 @@ input [0:2] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -37421,10 +39774,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -37481,6 +39838,8 @@ wire [0:0] mux_2level_tapbuf_basis_input3_mem3_1_out ; sb_1__2__const1_26 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .X ( out[0] ) ) ; sb_1__2__local_encoder2to3_44 local_encoder2to3_0_ ( .addr ( sram[0:1] ) , .data ( local_encoder2to3_0_data ) , .data_inv ( local_encoder2to3_0_data_inv ) ) ; @@ -37497,9 +39856,6 @@ sb_1__2__mux_2level_tapbuf_basis_input3_mem3_60 mux_l2_in_0_ ( .mem ( local_encoder2to3_1_data ) , .mem_inv ( local_encoder2to3_1_data_inv ) , .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_180 ( .A ( BUF_net_181 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_181 ( - .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_181 ) ) ; endmodule @@ -37511,10 +39867,14 @@ input [0:2] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -37525,10 +39885,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -37601,9 +39965,9 @@ sb_1__2__mux_2level_tapbuf_basis_input3_mem3_58 mux_l2_in_0_ ( .mem ( local_encoder2to3_1_data ) , .mem_inv ( local_encoder2to3_1_data_inv ) , .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_178 ( .A ( BUF_net_179 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_179 ( - .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_179 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_181 ( .A ( BUF_net_182 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_182 ( + .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_182 ) ) ; endmodule @@ -37615,10 +39979,14 @@ input [0:2] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -37629,10 +39997,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -37705,9 +40077,9 @@ sb_1__2__mux_2level_tapbuf_basis_input3_mem3_56 mux_l2_in_0_ ( .mem ( local_encoder2to3_1_data ) , .mem_inv ( local_encoder2to3_1_data_inv ) , .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_176 ( .A ( BUF_net_177 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_177 ( - .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_177 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_179 ( .A ( BUF_net_180 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_180 ( + .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_180 ) ) ; endmodule @@ -37719,10 +40091,14 @@ input [0:2] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -37733,10 +40109,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -37809,9 +40189,9 @@ sb_1__2__mux_2level_tapbuf_basis_input3_mem3_54 mux_l2_in_0_ ( .mem ( local_encoder2to3_1_data ) , .mem_inv ( local_encoder2to3_1_data_inv ) , .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_174 ( .A ( BUF_net_175 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_175 ( - .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_175 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_177 ( .A ( BUF_net_178 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_178 ( + .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_178 ) ) ; endmodule @@ -37823,10 +40203,14 @@ input [0:2] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -37837,10 +40221,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -37913,9 +40301,9 @@ sb_1__2__mux_2level_tapbuf_basis_input3_mem3_52 mux_l2_in_0_ ( .mem ( local_encoder2to3_1_data ) , .mem_inv ( local_encoder2to3_1_data_inv ) , .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_172 ( .A ( BUF_net_173 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_173 ( - .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_173 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_175 ( .A ( BUF_net_176 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_176 ( + .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_176 ) ) ; endmodule @@ -37927,10 +40315,14 @@ input [0:2] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -37941,10 +40333,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -38017,9 +40413,8 @@ sb_1__2__mux_2level_tapbuf_basis_input3_mem3_50 mux_l2_in_0_ ( .mem ( local_encoder2to3_1_data ) , .mem_inv ( local_encoder2to3_1_data_inv ) , .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_170 ( .A ( BUF_net_171 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_171 ( - .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_171 ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_174 ( + .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .X ( out[0] ) ) ; endmodule @@ -38130,9 +40525,13 @@ input [0:1] mem ; input [0:1] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -38144,10 +40543,14 @@ input [0:2] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -38158,10 +40561,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -38252,9 +40659,13 @@ input [0:1] mem ; input [0:1] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -38266,10 +40677,14 @@ input [0:2] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -38280,10 +40695,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -38362,8 +40781,9 @@ sb_1__2__mux_2level_tapbuf_basis_input2_mem2_14 mux_l1_in_1_ ( .in ( in[3:4] ) , .mem ( local_encoder2to3_0_data[0:1] ) , .mem_inv ( local_encoder2to3_0_data_inv[0:1] ) , .out ( mux_2level_tapbuf_basis_input2_mem2_0_out ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_169 ( - .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_172 ( .A ( BUF_net_173 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_173 ( + .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_173 ) ) ; endmodule @@ -38374,9 +40794,13 @@ input [0:1] mem ; input [0:1] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -38388,10 +40812,14 @@ input [0:2] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -38402,10 +40830,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -38496,9 +40928,13 @@ input [0:1] mem ; input [0:1] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -38510,10 +40946,14 @@ input [0:2] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -38524,10 +40964,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -38606,9 +41050,9 @@ sb_1__2__mux_2level_tapbuf_basis_input2_mem2_12 mux_l1_in_1_ ( .in ( in[3:4] ) , .mem ( local_encoder2to3_0_data[0:1] ) , .mem_inv ( local_encoder2to3_0_data_inv[0:1] ) , .out ( mux_2level_tapbuf_basis_input2_mem2_0_out ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_167 ( .A ( BUF_net_168 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_168 ( - .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_168 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_170 ( .A ( BUF_net_171 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_171 ( + .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_171 ) ) ; endmodule @@ -38619,9 +41063,13 @@ input [0:1] mem ; input [0:1] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -38633,10 +41081,14 @@ input [0:2] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -38647,10 +41099,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -38729,9 +41185,9 @@ sb_1__2__mux_2level_tapbuf_basis_input2_mem2_11 mux_l1_in_1_ ( .in ( in[3:4] ) , .mem ( local_encoder2to3_0_data[0:1] ) , .mem_inv ( local_encoder2to3_0_data_inv[0:1] ) , .out ( mux_2level_tapbuf_basis_input2_mem2_0_out ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_165 ( .A ( BUF_net_166 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_166 ( - .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_166 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_168 ( .A ( BUF_net_169 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_169 ( + .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_169 ) ) ; endmodule @@ -38783,12 +41239,18 @@ input [0:3] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -38799,12 +41261,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -38815,12 +41283,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -38888,7 +41362,7 @@ sb_1__2__const1_15 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_4_0_ ( .A ( mux_2level_tapbuf_basis_input4_mem4_2_out[0] ) , - .X ( aps_rename_506_ ) ) ; + .X ( aps_rename_507_ ) ) ; sb_1__2__local_encoder2to4_6 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , .data ( local_encoder2to4_0_data ) , .data_inv ( local_encoder2to4_0_data_inv ) ) ; @@ -38910,9 +41384,9 @@ sb_1__2__mux_2level_tapbuf_basis_input4_mem4 mux_l2_in_0_ ( .mem ( local_encoder2to4_1_data ) , .mem_inv ( local_encoder2to4_1_data_inv ) , .out ( mux_2level_tapbuf_basis_input4_mem4_2_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_163 ( .A ( BUF_net_164 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_164 ( .A ( aps_rename_506_ ) , - .Y ( BUF_net_164 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_166 ( .A ( BUF_net_167 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_167 ( .A ( aps_rename_507_ ) , + .Y ( BUF_net_167 ) ) ; endmodule @@ -38924,12 +41398,18 @@ input [0:3] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -38940,12 +41420,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -38956,12 +41442,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -39100,9 +41592,13 @@ input [0:1] mem ; input [0:1] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -39114,12 +41610,18 @@ input [0:3] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -39130,12 +41632,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -39146,12 +41654,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -39219,7 +41733,8 @@ wire [0:0] mux_2level_tapbuf_basis_input4_mem4_2_out ; sb_1__2__const1_13 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_4_0_ ( - .A ( mux_2level_tapbuf_basis_input4_mem4_2_out[0] ) , .X ( net_net_162 ) ) ; + .A ( mux_2level_tapbuf_basis_input4_mem4_2_out[0] ) , + .X ( aps_rename_506_ ) ) ; sb_1__2__local_encoder2to4_2 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , .data ( local_encoder2to4_0_data ) , .data_inv ( local_encoder2to4_0_data_inv ) ) ; @@ -39246,7 +41761,9 @@ sb_1__2__mux_2level_tapbuf_basis_input2_mem2_10 mux_l1_in_2_ ( .in ( in[8:9] ) , .mem ( local_encoder2to4_0_data[0:1] ) , .mem_inv ( local_encoder2to4_0_data_inv[0:1] ) , .out ( mux_2level_tapbuf_basis_input2_mem2_0_out ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_162 ( .A ( net_net_162 ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_164 ( .A ( BUF_net_165 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_165 ( .A ( aps_rename_506_ ) , + .Y ( BUF_net_165 ) ) ; endmodule @@ -39257,9 +41774,13 @@ input [0:1] mem ; input [0:1] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -39271,12 +41792,18 @@ input [0:3] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -39287,12 +41814,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -39303,12 +41836,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -39404,9 +41943,9 @@ sb_1__2__mux_2level_tapbuf_basis_input2_mem2_9 mux_l1_in_2_ ( .in ( in[8:9] ) , .mem ( local_encoder2to4_0_data[0:1] ) , .mem_inv ( local_encoder2to4_0_data_inv[0:1] ) , .out ( mux_2level_tapbuf_basis_input2_mem2_0_out ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_199 ( .A ( BUF_net_200 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_200 ( .A ( aps_rename_505_ ) , - .Y ( BUF_net_200 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_162 ( .A ( BUF_net_163 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_163 ( .A ( aps_rename_505_ ) , + .Y ( BUF_net_163 ) ) ; endmodule @@ -39477,10 +42016,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -39492,10 +42035,14 @@ input [0:2] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -39506,10 +42053,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -39520,10 +42071,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -39621,10 +42176,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -39636,10 +42195,14 @@ input [0:2] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -39650,10 +42213,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -39664,10 +42231,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -39752,8 +42323,9 @@ sb_1__2__mux_2level_tapbuf_basis_input3_mem3_34 mux_l2_in_0_ ( .mem ( local_encoder2to3_1_data ) , .mem_inv ( local_encoder2to3_1_data_inv ) , .out ( mux_2level_tapbuf_basis_input3_mem3_3_out ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_159 ( - .A ( mux_2level_tapbuf_basis_input3_mem3_3_out[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_158 ( .A ( BUF_net_159 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_159 ( + .A ( mux_2level_tapbuf_basis_input3_mem3_3_out[0] ) , .Y ( BUF_net_159 ) ) ; endmodule @@ -39764,10 +42336,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -39779,10 +42355,14 @@ input [0:2] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -39793,10 +42373,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -39807,10 +42391,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -39869,6 +42457,8 @@ wire [0:0] mux_2level_tapbuf_basis_input3_mem3_3_out ; sb_1__2__const1_9 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( mux_2level_tapbuf_basis_input3_mem3_3_out[0] ) , .X ( out[0] ) ) ; sb_1__2__local_encoder2to3_18 local_encoder2to3_0_ ( .addr ( sram[0:1] ) , .data ( local_encoder2to3_0_data ) , .data_inv ( local_encoder2to3_0_data_inv ) ) ; @@ -39895,8 +42485,6 @@ sb_1__2__mux_2level_tapbuf_basis_input3_mem3_30 mux_l2_in_0_ ( .mem ( local_encoder2to3_1_data ) , .mem_inv ( local_encoder2to3_1_data_inv ) , .out ( mux_2level_tapbuf_basis_input3_mem3_3_out ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_158 ( - .A ( mux_2level_tapbuf_basis_input3_mem3_3_out[0] ) , .X ( out[0] ) ) ; endmodule @@ -40068,7 +42656,7 @@ input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( copt_net_216 ) , +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ropt_net_240 ) , .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; @@ -40077,34 +42665,36 @@ sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__buf_1 FTB_19__18 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1420 ( .A ( ccff_head[0] ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1419 ( .A ( ropt_net_244 ) , .X ( copt_net_211 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1421 ( .A ( copt_net_211 ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1420 ( .A ( ropt_net_241 ) , .X ( copt_net_212 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1422 ( .A ( copt_net_212 ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1421 ( .A ( copt_net_215 ) , .X ( copt_net_213 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1423 ( .A ( ropt_net_246 ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1422 ( .A ( copt_net_213 ) , .X ( copt_net_214 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1424 ( .A ( copt_net_213 ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1423 ( .A ( copt_net_211 ) , .X ( copt_net_215 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1425 ( .A ( ropt_net_241 ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1424 ( .A ( copt_net_212 ) , .X ( copt_net_216 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1446 ( .A ( copt_net_214 ) , +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1443 ( .A ( copt_net_216 ) , + .X ( ropt_net_236 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1444 ( .A ( ropt_net_236 ) , + .X ( ropt_net_237 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1445 ( .A ( ropt_net_237 ) , + .X ( ropt_net_238 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1446 ( .A ( ropt_net_238 ) , + .X ( ropt_net_239 ) ) ; +sky130_fd_sc_hd__buf_2 ropt_h_inst_1447 ( .A ( ropt_net_239 ) , .X ( ropt_net_240 ) ) ; -sky130_fd_sc_hd__buf_2 ropt_h_inst_1447 ( .A ( ropt_net_240 ) , +sky130_fd_sc_hd__buf_1 ropt_h_inst_1448 ( .A ( copt_net_214 ) , .X ( ropt_net_241 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1448 ( .A ( copt_net_215 ) , +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1449 ( .A ( ropt_net_243 ) , .X ( ropt_net_242 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1449 ( .A ( ropt_net_247 ) , +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1450 ( .A ( ccff_head[0] ) , .X ( ropt_net_243 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1450 ( .A ( ropt_net_242 ) , +sky130_fd_sc_hd__buf_1 ropt_h_inst_1451 ( .A ( ropt_net_242 ) , .X ( ropt_net_244 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1451 ( .A ( ropt_net_243 ) , - .X ( ropt_net_245 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1452 ( .A ( ropt_net_245 ) , - .X ( ropt_net_246 ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 ropt_h_inst_1453 ( .A ( ropt_net_244 ) , - .X ( ropt_net_247 ) ) ; endmodule @@ -40116,9 +42706,13 @@ input [0:1] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( p0 ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -40129,10 +42723,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -40143,10 +42741,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -40157,10 +42759,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -40258,9 +42864,13 @@ input [0:1] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( p0 ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -40271,10 +42881,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -40285,10 +42899,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -40299,10 +42917,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -40387,8 +43009,9 @@ sb_1__2__mux_2level_tapbuf_basis_input2_mem2_7 mux_l1_in_2_ ( .mem ( local_encoder2to3_0_data[0:1] ) , .mem_inv ( local_encoder2to3_0_data_inv[0:1] ) , .out ( mux_2level_tapbuf_basis_input2_mem2_0_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_157 ( - .A ( mux_2level_tapbuf_basis_input3_mem3_2_out[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_156 ( .A ( BUF_net_157 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_157 ( + .A ( mux_2level_tapbuf_basis_input3_mem3_2_out[0] ) , .Y ( BUF_net_157 ) ) ; endmodule @@ -40400,9 +43023,13 @@ input [0:1] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( p0 ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -40413,10 +43040,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -40427,10 +43058,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -40441,10 +43076,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -40529,9 +43168,9 @@ sb_1__2__mux_2level_tapbuf_basis_input2_mem2_6 mux_l1_in_2_ ( .mem ( local_encoder2to3_0_data[0:1] ) , .mem_inv ( local_encoder2to3_0_data_inv[0:1] ) , .out ( mux_2level_tapbuf_basis_input2_mem2_0_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_155 ( .A ( BUF_net_156 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_156 ( - .A ( mux_2level_tapbuf_basis_input3_mem3_2_out[0] ) , .Y ( BUF_net_156 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_154 ( .A ( BUF_net_155 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_155 ( + .A ( mux_2level_tapbuf_basis_input3_mem3_2_out[0] ) , .Y ( BUF_net_155 ) ) ; endmodule @@ -40543,9 +43182,13 @@ input [0:1] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( p0 ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -40556,10 +43199,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -40570,10 +43217,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -40584,10 +43235,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -40672,9 +43327,9 @@ sb_1__2__mux_2level_tapbuf_basis_input2_mem2_5 mux_l1_in_2_ ( .mem ( local_encoder2to3_0_data[0:1] ) , .mem_inv ( local_encoder2to3_0_data_inv[0:1] ) , .out ( mux_2level_tapbuf_basis_input2_mem2_0_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_153 ( .A ( BUF_net_154 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_154 ( - .A ( mux_2level_tapbuf_basis_input3_mem3_2_out[0] ) , .Y ( BUF_net_154 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_152 ( .A ( BUF_net_153 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_153 ( + .A ( mux_2level_tapbuf_basis_input3_mem3_2_out[0] ) , .Y ( BUF_net_153 ) ) ; endmodule @@ -40686,9 +43341,13 @@ input [0:1] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( p0 ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -40699,10 +43358,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -40713,10 +43376,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -40727,10 +43394,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -40815,9 +43486,8 @@ sb_1__2__mux_2level_tapbuf_basis_input2_mem2_4 mux_l1_in_2_ ( .mem ( local_encoder2to3_0_data[0:1] ) , .mem_inv ( local_encoder2to3_0_data_inv[0:1] ) , .out ( mux_2level_tapbuf_basis_input2_mem2_0_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_151 ( .A ( BUF_net_152 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_152 ( - .A ( mux_2level_tapbuf_basis_input3_mem3_2_out[0] ) , .Y ( BUF_net_152 ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_151 ( + .A ( mux_2level_tapbuf_basis_input3_mem3_2_out[0] ) , .X ( out[0] ) ) ; endmodule @@ -40829,9 +43499,13 @@ input [0:1] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( p0 ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -40842,10 +43516,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -40856,10 +43534,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -40870,10 +43552,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -40958,9 +43644,9 @@ sb_1__2__mux_2level_tapbuf_basis_input2_mem2_3 mux_l1_in_2_ ( .mem ( local_encoder2to3_0_data[0:1] ) , .mem_inv ( local_encoder2to3_0_data_inv[0:1] ) , .out ( mux_2level_tapbuf_basis_input2_mem2_0_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_149 ( .A ( BUF_net_150 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_150 ( - .A ( mux_2level_tapbuf_basis_input3_mem3_2_out[0] ) , .Y ( BUF_net_150 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_199 ( .A ( BUF_net_200 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_200 ( + .A ( mux_2level_tapbuf_basis_input3_mem3_2_out[0] ) , .Y ( BUF_net_200 ) ) ; endmodule @@ -40972,9 +43658,13 @@ input [0:1] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( p0 ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -40985,10 +43675,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -40999,10 +43693,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -41013,10 +43711,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -41114,9 +43816,13 @@ input [0:1] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( p0 ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -41127,10 +43833,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -41141,10 +43851,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -41155,10 +43869,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -41256,9 +43974,13 @@ input [0:1] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( p0 ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -41269,10 +43991,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -41283,10 +44009,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -41297,10 +44027,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -41359,8 +44093,6 @@ wire [0:0] mux_2level_tapbuf_basis_input3_mem3_2_out ; sb_1__2__const1_0 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( mux_2level_tapbuf_basis_input3_mem3_2_out[0] ) , .X ( out[0] ) ) ; sb_1__2__local_encoder2to3_0 local_encoder2to3_0_ ( .addr ( sram[0:1] ) , .data ( local_encoder2to3_0_data ) , .data_inv ( local_encoder2to3_0_data_inv ) ) ; @@ -41387,6 +44119,9 @@ sb_1__2__mux_2level_tapbuf_basis_input2_mem2_0 mux_l1_in_2_ ( .mem ( local_encoder2to3_0_data[0:1] ) , .mem_inv ( local_encoder2to3_0_data_inv[0:1] ) , .out ( mux_2level_tapbuf_basis_input2_mem2_0_out ) , .p0 ( p0 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_149 ( .A ( BUF_net_150 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_150 ( + .A ( mux_2level_tapbuf_basis_input3_mem3_2_out[0] ) , .Y ( BUF_net_150 ) ) ; endmodule @@ -41452,6 +44187,7 @@ output pReset_E_out ; input prog_clk_0_S_in ; wire ropt_net_228 ; +wire ropt_net_227 ; wire [0:0] prog_clk ; wire prog_clk_0 ; wire [0:3] mux_2level_tapbuf_size10_0_sram ; @@ -41561,7 +44297,7 @@ sb_1__2__mux_2level_tapbuf_size7_0 mux_right_track_0 ( .sram ( mux_2level_tapbuf_size7_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 , SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) , - .out ( chanx_right_out[0] ) , .p0 ( optlc_net_204 ) ) ; + .out ( chanx_right_out[0] ) , .p0 ( optlc_net_203 ) ) ; sb_1__2__mux_2level_tapbuf_size7_1 mux_right_track_2 ( .in ( { right_bottom_grid_pin_36_[0] , right_bottom_grid_pin_39_[0] , right_bottom_grid_pin_42_[0] , chany_bottom_in[8] , @@ -41569,7 +44305,7 @@ sb_1__2__mux_2level_tapbuf_size7_1 mux_right_track_2 ( .sram ( mux_2level_tapbuf_size7_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 , SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 } ) , - .out ( chanx_right_out[1] ) , .p0 ( optlc_net_204 ) ) ; + .out ( chanx_right_out[1] ) , .p0 ( optlc_net_203 ) ) ; sb_1__2__mux_2level_tapbuf_size7_2 mux_right_track_12 ( .in ( { right_top_grid_pin_1_[0] , right_bottom_grid_pin_41_[0] , chany_bottom_in[4] , chany_bottom_in[15] , chany_bottom_in[26] , @@ -41577,7 +44313,7 @@ sb_1__2__mux_2level_tapbuf_size7_2 mux_right_track_12 ( .sram ( mux_2level_tapbuf_size7_2_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_9 , SYNOPSYS_UNCONNECTED_10 , SYNOPSYS_UNCONNECTED_11 , SYNOPSYS_UNCONNECTED_12 } ) , - .out ( chanx_right_out[6] ) , .p0 ( optlc_net_204 ) ) ; + .out ( chanx_right_out[6] ) , .p0 ( optlc_net_209 ) ) ; sb_1__2__mux_2level_tapbuf_size7_3 mux_right_track_20 ( .in ( { right_bottom_grid_pin_36_[0] , right_bottom_grid_pin_42_[0] , chany_bottom_in[3] , chany_bottom_in[14] , chany_bottom_in[25] , @@ -41601,7 +44337,7 @@ sb_1__2__mux_2level_tapbuf_size7_5 mux_left_track_1 ( .sram ( mux_2level_tapbuf_size7_5_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_21 , SYNOPSYS_UNCONNECTED_22 , SYNOPSYS_UNCONNECTED_23 , SYNOPSYS_UNCONNECTED_24 } ) , - .out ( chanx_left_out[0] ) , .p0 ( optlc_net_208 ) ) ; + .out ( chanx_left_out[0] ) , .p0 ( optlc_net_202 ) ) ; sb_1__2__mux_2level_tapbuf_size7_6 mux_left_track_13 ( .in ( { chanx_left_out[12] , chanx_left_out[27] , chany_bottom_in[4] , chany_bottom_in[15] , chany_bottom_in[26] , left_top_grid_pin_1_[0] , @@ -41609,7 +44345,7 @@ sb_1__2__mux_2level_tapbuf_size7_6 mux_left_track_13 ( .sram ( mux_2level_tapbuf_size7_6_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_25 , SYNOPSYS_UNCONNECTED_26 , SYNOPSYS_UNCONNECTED_27 , SYNOPSYS_UNCONNECTED_28 } ) , - .out ( chanx_left_out[6] ) , .p0 ( optlc_net_207 ) ) ; + .out ( chanx_left_out[6] ) , .p0 ( optlc_net_208 ) ) ; sb_1__2__mux_2level_tapbuf_size7_7 mux_left_track_21 ( .in ( { chanx_left_out[13] , chanx_left_out[28] , chany_bottom_in[5] , chany_bottom_in[16] , chany_bottom_in[27] , @@ -41617,7 +44353,7 @@ sb_1__2__mux_2level_tapbuf_size7_7 mux_left_track_21 ( .sram ( mux_2level_tapbuf_size7_7_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_29 , SYNOPSYS_UNCONNECTED_30 , SYNOPSYS_UNCONNECTED_31 , SYNOPSYS_UNCONNECTED_32 } ) , - .out ( chanx_left_out[10] ) , .p0 ( optlc_net_206 ) ) ; + .out ( chanx_left_out[10] ) , .p0 ( optlc_net_205 ) ) ; sb_1__2__mux_2level_tapbuf_size7 mux_left_track_29 ( .in ( { chanx_left_out[15] , chanx_left_out[29] , chany_bottom_in[6] , chany_bottom_in[17] , chany_bottom_in[28] , @@ -41625,7 +44361,7 @@ sb_1__2__mux_2level_tapbuf_size7 mux_left_track_29 ( .sram ( mux_2level_tapbuf_size7_8_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_33 , SYNOPSYS_UNCONNECTED_34 , SYNOPSYS_UNCONNECTED_35 , SYNOPSYS_UNCONNECTED_36 } ) , - .out ( chanx_left_out[14] ) , .p0 ( optlc_net_206 ) ) ; + .out ( chanx_left_out[14] ) , .p0 ( optlc_net_201 ) ) ; sb_1__2__mux_2level_tapbuf_size7_mem_0 mem_right_track_0 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( mux_2level_tapbuf_size7_mem_0_ccff_tail ) , @@ -41678,7 +44414,7 @@ sb_1__2__mux_2level_tapbuf_size8_0 mux_right_track_4 ( .sram ( mux_2level_tapbuf_size8_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_37 , SYNOPSYS_UNCONNECTED_38 , SYNOPSYS_UNCONNECTED_39 , SYNOPSYS_UNCONNECTED_40 } ) , - .out ( chanx_right_out[2] ) , .p0 ( optlc_net_205 ) ) ; + .out ( chanx_right_out[2] ) , .p0 ( optlc_net_209 ) ) ; sb_1__2__mux_2level_tapbuf_size8_1 mux_left_track_3 ( .in ( { chanx_left_out[7] , chanx_left_out[21] , chany_bottom_in[0] , chany_bottom_in[11] , chany_bottom_in[22] , @@ -41687,7 +44423,7 @@ sb_1__2__mux_2level_tapbuf_size8_1 mux_left_track_3 ( .sram ( mux_2level_tapbuf_size8_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_41 , SYNOPSYS_UNCONNECTED_42 , SYNOPSYS_UNCONNECTED_43 , SYNOPSYS_UNCONNECTED_44 } ) , - .out ( chanx_left_out[1] ) , .p0 ( optlc_net_209 ) ) ; + .out ( chanx_left_out[1] ) , .p0 ( optlc_net_206 ) ) ; sb_1__2__mux_2level_tapbuf_size8 mux_left_track_5 ( .in ( { chanx_left_out[8] , chanx_left_out[23] , chany_bottom_in[1] , chany_bottom_in[12] , chany_bottom_in[23] , @@ -41696,7 +44432,7 @@ sb_1__2__mux_2level_tapbuf_size8 mux_left_track_5 ( .sram ( mux_2level_tapbuf_size8_2_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_45 , SYNOPSYS_UNCONNECTED_46 , SYNOPSYS_UNCONNECTED_47 , SYNOPSYS_UNCONNECTED_48 } ) , - .out ( chanx_left_out[2] ) , .p0 ( optlc_net_209 ) ) ; + .out ( chanx_left_out[2] ) , .p0 ( optlc_net_206 ) ) ; sb_1__2__mux_2level_tapbuf_size8_mem_0 mem_right_track_4 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( mux_2level_tapbuf_size7_mem_1_ccff_tail ) , @@ -41721,7 +44457,7 @@ sb_1__2__mux_2level_tapbuf_size10_0 mux_right_track_6 ( .sram ( mux_2level_tapbuf_size10_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_49 , SYNOPSYS_UNCONNECTED_50 , SYNOPSYS_UNCONNECTED_51 , SYNOPSYS_UNCONNECTED_52 } ) , - .out ( chanx_right_out[3] ) , .p0 ( optlc_net_204 ) ) ; + .out ( chanx_right_out[3] ) , .p0 ( optlc_net_205 ) ) ; sb_1__2__mux_2level_tapbuf_size10 mux_left_track_7 ( .in ( { chanx_left_out[9] , chanx_left_out[24] , chany_bottom_in[2] , chany_bottom_in[13] , chany_bottom_in[24] , left_top_grid_pin_1_[0] , @@ -41730,7 +44466,7 @@ sb_1__2__mux_2level_tapbuf_size10 mux_left_track_7 ( .sram ( mux_2level_tapbuf_size10_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_53 , SYNOPSYS_UNCONNECTED_54 , SYNOPSYS_UNCONNECTED_55 , SYNOPSYS_UNCONNECTED_56 } ) , - .out ( chanx_left_out[3] ) , .p0 ( optlc_net_203 ) ) ; + .out ( chanx_left_out[3] ) , .p0 ( optlc_net_207 ) ) ; sb_1__2__mux_2level_tapbuf_size10_mem_0 mem_right_track_6 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( mux_2level_tapbuf_size8_mem_0_ccff_tail ) , @@ -41749,8 +44485,8 @@ sb_1__2__mux_2level_tapbuf_size9_0 mux_right_track_10 ( .sram ( mux_2level_tapbuf_size9_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_57 , SYNOPSYS_UNCONNECTED_58 , SYNOPSYS_UNCONNECTED_59 , SYNOPSYS_UNCONNECTED_60 } ) , - .out ( { aps_rename_507_ } ) , - .p0 ( optlc_net_204 ) ) ; + .out ( { aps_rename_508_ } ) , + .p0 ( optlc_net_209 ) ) ; sb_1__2__mux_2level_tapbuf_size9 mux_left_track_11 ( .in ( { chanx_left_out[11] , chanx_left_out[25] , chany_bottom_in[3] , chany_bottom_in[14] , chany_bottom_in[25] , @@ -41759,7 +44495,7 @@ sb_1__2__mux_2level_tapbuf_size9 mux_left_track_11 ( .sram ( mux_2level_tapbuf_size9_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_61 , SYNOPSYS_UNCONNECTED_62 , SYNOPSYS_UNCONNECTED_63 , SYNOPSYS_UNCONNECTED_64 } ) , - .out ( chanx_left_out[5] ) , .p0 ( optlc_net_208 ) ) ; + .out ( chanx_left_out[5] ) , .p0 ( optlc_net_206 ) ) ; sb_1__2__mux_2level_tapbuf_size9_mem_0 mem_right_track_10 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( mux_2level_tapbuf_size10_mem_0_ccff_tail ) , @@ -41776,21 +44512,21 @@ sb_1__2__mux_2level_tapbuf_size5_0 mux_right_track_36 ( .sram ( mux_2level_tapbuf_size5_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_65 , SYNOPSYS_UNCONNECTED_66 , SYNOPSYS_UNCONNECTED_67 , SYNOPSYS_UNCONNECTED_68 } ) , - .out ( chanx_right_out[18] ) , .p0 ( optlc_net_203 ) ) ; + .out ( chanx_right_out[18] ) , .p0 ( optlc_net_204 ) ) ; sb_1__2__mux_2level_tapbuf_size5_1 mux_right_track_44 ( .in ( { right_bottom_grid_pin_39_[0] , chany_bottom_in[0] , chany_bottom_in[11] , chany_bottom_in[22] , chanx_right_out[17] } ) , .sram ( mux_2level_tapbuf_size5_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_69 , SYNOPSYS_UNCONNECTED_70 , SYNOPSYS_UNCONNECTED_71 , SYNOPSYS_UNCONNECTED_72 } ) , - .out ( chanx_right_out[22] ) , .p0 ( optlc_net_203 ) ) ; + .out ( chanx_right_out[22] ) , .p0 ( optlc_net_204 ) ) ; sb_1__2__mux_2level_tapbuf_size5_2 mux_bottom_track_5 ( .in ( { chanx_left_out[8] , bottom_left_grid_pin_46_[0] , bottom_left_grid_pin_49_[0] , chanx_left_in[4] , chanx_right_out[8] } ) , .sram ( mux_2level_tapbuf_size5_2_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_73 , SYNOPSYS_UNCONNECTED_74 , SYNOPSYS_UNCONNECTED_75 , SYNOPSYS_UNCONNECTED_76 } ) , - .out ( chany_bottom_out[2] ) , .p0 ( optlc_net_202 ) ) ; + .out ( chany_bottom_out[2] ) , .p0 ( optlc_net_201 ) ) ; sb_1__2__mux_2level_tapbuf_size5_3 mux_bottom_track_11 ( .in ( { chanx_left_out[12] , bottom_left_grid_pin_46_[0] , bottom_left_grid_pin_49_[0] , chanx_right_out[12] , @@ -41798,7 +44534,7 @@ sb_1__2__mux_2level_tapbuf_size5_3 mux_bottom_track_11 ( .sram ( mux_2level_tapbuf_size5_3_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_77 , SYNOPSYS_UNCONNECTED_78 , SYNOPSYS_UNCONNECTED_79 , SYNOPSYS_UNCONNECTED_80 } ) , - .out ( chany_bottom_out[5] ) , .p0 ( optlc_net_202 ) ) ; + .out ( chany_bottom_out[5] ) , .p0 ( optlc_net_201 ) ) ; sb_1__2__mux_2level_tapbuf_size5 mux_left_track_37 ( .in ( { chanx_left_out[16] , chany_bottom_in[7] , chany_bottom_in[18] , chany_bottom_in[29] , left_bottom_grid_pin_38_[0] } ) , @@ -41837,35 +44573,35 @@ sb_1__2__mux_2level_tapbuf_size4_0 mux_right_track_52 ( .sram ( mux_2level_tapbuf_size4_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_85 , SYNOPSYS_UNCONNECTED_86 , SYNOPSYS_UNCONNECTED_87 , SYNOPSYS_UNCONNECTED_88 } ) , - .out ( chanx_right_out[26] ) , .p0 ( optlc_net_203 ) ) ; + .out ( chanx_right_out[26] ) , .p0 ( optlc_net_204 ) ) ; sb_1__2__mux_2level_tapbuf_size4_1 mux_bottom_track_13 ( .in ( { chanx_left_out[13] , bottom_left_grid_pin_44_[0] , chanx_right_out[13] , chanx_left_in[17] } ) , .sram ( mux_2level_tapbuf_size4_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_89 , SYNOPSYS_UNCONNECTED_90 , SYNOPSYS_UNCONNECTED_91 , SYNOPSYS_UNCONNECTED_92 } ) , - .out ( chany_bottom_out[6] ) , .p0 ( optlc_net_208 ) ) ; + .out ( chany_bottom_out[6] ) , .p0 ( optlc_net_207 ) ) ; sb_1__2__mux_2level_tapbuf_size4_2 mux_bottom_track_15 ( .in ( { chanx_left_out[15] , bottom_left_grid_pin_45_[0] , chanx_right_out[15] , chanx_left_in[21] } ) , .sram ( mux_2level_tapbuf_size4_2_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_93 , SYNOPSYS_UNCONNECTED_94 , SYNOPSYS_UNCONNECTED_95 , SYNOPSYS_UNCONNECTED_96 } ) , - .out ( chany_bottom_out[7] ) , .p0 ( optlc_net_210 ) ) ; + .out ( chany_bottom_out[7] ) , .p0 ( optlc_net_207 ) ) ; sb_1__2__mux_2level_tapbuf_size4_3 mux_bottom_track_17 ( .in ( { chanx_left_out[16] , bottom_left_grid_pin_46_[0] , chanx_right_out[16] , chanx_left_in[25] } ) , .sram ( mux_2level_tapbuf_size4_3_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_97 , SYNOPSYS_UNCONNECTED_98 , SYNOPSYS_UNCONNECTED_99 , SYNOPSYS_UNCONNECTED_100 } ) , - .out ( chany_bottom_out[8] ) , .p0 ( optlc_net_210 ) ) ; + .out ( chany_bottom_out[8] ) , .p0 ( optlc_net_207 ) ) ; sb_1__2__mux_2level_tapbuf_size4_4 mux_bottom_track_19 ( .in ( { chanx_left_out[17] , bottom_left_grid_pin_47_[0] , chanx_right_out[17] , chanx_left_in[29] } ) , .sram ( mux_2level_tapbuf_size4_4_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_101 , SYNOPSYS_UNCONNECTED_102 , SYNOPSYS_UNCONNECTED_103 , SYNOPSYS_UNCONNECTED_104 } ) , - .out ( chany_bottom_out[9] ) , .p0 ( optlc_net_208 ) ) ; + .out ( chany_bottom_out[9] ) , .p0 ( optlc_net_207 ) ) ; sb_1__2__mux_2level_tapbuf_size4_5 mux_bottom_track_37 ( .in ( { chanx_left_out[29] , chanx_right_in[29] , bottom_left_grid_pin_44_[0] , chanx_right_out[29] } ) , @@ -41879,14 +44615,14 @@ sb_1__2__mux_2level_tapbuf_size4_6 mux_left_track_45 ( .sram ( mux_2level_tapbuf_size4_6_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_109 , SYNOPSYS_UNCONNECTED_110 , SYNOPSYS_UNCONNECTED_111 , SYNOPSYS_UNCONNECTED_112 } ) , - .out ( chanx_left_out[22] ) , .p0 ( optlc_net_208 ) ) ; + .out ( chanx_left_out[22] ) , .p0 ( optlc_net_207 ) ) ; sb_1__2__mux_2level_tapbuf_size4 mux_left_track_53 ( .in ( { chanx_left_out[19] , chany_bottom_in[9] , chany_bottom_in[20] , left_bottom_grid_pin_40_[0] } ) , .sram ( mux_2level_tapbuf_size4_7_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_113 , SYNOPSYS_UNCONNECTED_114 , SYNOPSYS_UNCONNECTED_115 , SYNOPSYS_UNCONNECTED_116 } ) , - .out ( chanx_left_out[26] ) , .p0 ( optlc_net_202 ) ) ; + .out ( chanx_left_out[26] ) , .p0 ( optlc_net_201 ) ) ; sb_1__2__mux_2level_tapbuf_size4_mem_0 mem_right_track_52 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( mux_2level_tapbuf_size5_mem_1_ccff_tail ) , @@ -41933,7 +44669,7 @@ sb_1__2__mux_2level_tapbuf_size6_0 mux_bottom_track_1 ( .sram ( mux_2level_tapbuf_size6_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_117 , SYNOPSYS_UNCONNECTED_118 , SYNOPSYS_UNCONNECTED_119 , SYNOPSYS_UNCONNECTED_120 } ) , - .out ( chany_bottom_out[0] ) , .p0 ( optlc_net_202 ) ) ; + .out ( chany_bottom_out[0] ) , .p0 ( optlc_net_207 ) ) ; sb_1__2__mux_2level_tapbuf_size6_1 mux_bottom_track_3 ( .in ( { chanx_left_out[7] , bottom_left_grid_pin_45_[0] , bottom_left_grid_pin_48_[0] , bottom_left_grid_pin_51_[0] , @@ -41941,7 +44677,7 @@ sb_1__2__mux_2level_tapbuf_size6_1 mux_bottom_track_3 ( .sram ( mux_2level_tapbuf_size6_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_121 , SYNOPSYS_UNCONNECTED_122 , SYNOPSYS_UNCONNECTED_123 , SYNOPSYS_UNCONNECTED_124 } ) , - .out ( chany_bottom_out[1] ) , .p0 ( optlc_net_202 ) ) ; + .out ( chany_bottom_out[1] ) , .p0 ( optlc_net_201 ) ) ; sb_1__2__mux_2level_tapbuf_size6_2 mux_bottom_track_7 ( .in ( { chanx_left_out[9] , bottom_left_grid_pin_44_[0] , bottom_left_grid_pin_47_[0] , bottom_left_grid_pin_50_[0] , @@ -41983,7 +44719,7 @@ sb_1__2__mux_2level_tapbuf_size3_0 mux_bottom_track_21 ( chanx_right_out[19] } ) , .sram ( mux_2level_tapbuf_size3_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_133 , SYNOPSYS_UNCONNECTED_134 } ) , - .out ( chany_bottom_out[10] ) , .p0 ( optlc_net_202 ) ) ; + .out ( chany_bottom_out[10] ) , .p0 ( optlc_net_207 ) ) ; sb_1__2__mux_2level_tapbuf_size3_1 mux_bottom_track_23 ( .in ( { chanx_left_out[20] , bottom_left_grid_pin_49_[0] , chanx_right_out[20] } ) , @@ -41995,13 +44731,13 @@ sb_1__2__mux_2level_tapbuf_size3_2 mux_bottom_track_25 ( chanx_right_out[21] } ) , .sram ( mux_2level_tapbuf_size3_2_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_137 , SYNOPSYS_UNCONNECTED_138 } ) , - .out ( chany_bottom_out[12] ) , .p0 ( optlc_net_207 ) ) ; + .out ( chany_bottom_out[12] ) , .p0 ( optlc_net_210 ) ) ; sb_1__2__mux_2level_tapbuf_size3 mux_bottom_track_27 ( .in ( { chanx_left_out[23] , bottom_left_grid_pin_51_[0] , chanx_right_out[23] } ) , .sram ( mux_2level_tapbuf_size3_3_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_139 , SYNOPSYS_UNCONNECTED_140 } ) , - .out ( chany_bottom_out[13] ) , .p0 ( optlc_net_206 ) ) ; + .out ( chany_bottom_out[13] ) , .p0 ( optlc_net_201 ) ) ; sb_1__2__mux_2level_tapbuf_size3_mem_0 mem_bottom_track_21 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( mux_2level_tapbuf_size4_mem_4_ccff_tail ) , @@ -42026,57 +44762,57 @@ sb_1__2__mux_2level_tapbuf_size2_0 mux_bottom_track_29 ( .in ( { chanx_left_out[24] , chanx_right_out[24] } ) , .sram ( mux_2level_tapbuf_size2_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_141 , SYNOPSYS_UNCONNECTED_142 } ) , - .out ( chany_bottom_out[14] ) , .p0 ( optlc_net_207 ) ) ; + .out ( chany_bottom_out[14] ) , .p0 ( optlc_net_208 ) ) ; sb_1__2__mux_2level_tapbuf_size2_1 mux_bottom_track_31 ( .in ( { chanx_left_out[25] , chanx_right_out[25] } ) , .sram ( mux_2level_tapbuf_size2_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_143 , SYNOPSYS_UNCONNECTED_144 } ) , - .out ( chany_bottom_out[15] ) , .p0 ( optlc_net_207 ) ) ; + .out ( chany_bottom_out[15] ) , .p0 ( optlc_net_210 ) ) ; sb_1__2__mux_2level_tapbuf_size2_2 mux_bottom_track_33 ( .in ( { chanx_left_out[27] , chanx_right_out[27] } ) , .sram ( mux_2level_tapbuf_size2_2_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_145 , SYNOPSYS_UNCONNECTED_146 } ) , - .out ( chany_bottom_out[16] ) , .p0 ( optlc_net_204 ) ) ; + .out ( chany_bottom_out[16] ) , .p0 ( optlc_net_210 ) ) ; sb_1__2__mux_2level_tapbuf_size2_3 mux_bottom_track_35 ( .in ( { chanx_left_out[28] , chanx_right_out[28] } ) , .sram ( mux_2level_tapbuf_size2_3_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_147 , SYNOPSYS_UNCONNECTED_148 } ) , - .out ( chany_bottom_out[17] ) , .p0 ( optlc_net_207 ) ) ; + .out ( chany_bottom_out[17] ) , .p0 ( optlc_net_202 ) ) ; sb_1__2__mux_2level_tapbuf_size2_4 mux_bottom_track_39 ( .in ( { chanx_right_in[25] , bottom_left_grid_pin_45_[0] } ) , .sram ( mux_2level_tapbuf_size2_4_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_149 , SYNOPSYS_UNCONNECTED_150 } ) , - .out ( chany_bottom_out[19] ) , .p0 ( optlc_net_205 ) ) ; + .out ( chany_bottom_out[19] ) , .p0 ( optlc_net_203 ) ) ; sb_1__2__mux_2level_tapbuf_size2_5 mux_bottom_track_41 ( .in ( { chanx_right_in[21] , bottom_left_grid_pin_46_[0] } ) , .sram ( mux_2level_tapbuf_size2_5_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_151 , SYNOPSYS_UNCONNECTED_152 } ) , - .out ( chany_bottom_out[20] ) , .p0 ( optlc_net_206 ) ) ; + .out ( chany_bottom_out[20] ) , .p0 ( optlc_net_203 ) ) ; sb_1__2__mux_2level_tapbuf_size2_6 mux_bottom_track_43 ( .in ( { chanx_right_in[17] , bottom_left_grid_pin_47_[0] } ) , .sram ( mux_2level_tapbuf_size2_6_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_153 , SYNOPSYS_UNCONNECTED_154 } ) , - .out ( chany_bottom_out[21] ) , .p0 ( optlc_net_206 ) ) ; + .out ( chany_bottom_out[21] ) , .p0 ( optlc_net_202 ) ) ; sb_1__2__mux_2level_tapbuf_size2_7 mux_bottom_track_45 ( .in ( { chanx_right_in[13] , bottom_left_grid_pin_48_[0] } ) , .sram ( mux_2level_tapbuf_size2_7_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_155 , SYNOPSYS_UNCONNECTED_156 } ) , - .out ( chany_bottom_out[22] ) , .p0 ( optlc_net_201 ) ) ; + .out ( chany_bottom_out[22] ) , .p0 ( optlc_net_202 ) ) ; sb_1__2__mux_2level_tapbuf_size2_8 mux_bottom_track_47 ( .in ( { chanx_right_in[9] , bottom_left_grid_pin_49_[0] } ) , .sram ( mux_2level_tapbuf_size2_8_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_157 , SYNOPSYS_UNCONNECTED_158 } ) , - .out ( chany_bottom_out[23] ) , .p0 ( optlc_net_201 ) ) ; + .out ( chany_bottom_out[23] ) , .p0 ( optlc_net_202 ) ) ; sb_1__2__mux_2level_tapbuf_size2_9 mux_bottom_track_49 ( .in ( { chanx_right_in[5] , bottom_left_grid_pin_50_[0] } ) , .sram ( mux_2level_tapbuf_size2_9_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_159 , SYNOPSYS_UNCONNECTED_160 } ) , - .out ( chany_bottom_out[24] ) , .p0 ( optlc_net_206 ) ) ; + .out ( chany_bottom_out[24] ) , .p0 ( optlc_net_202 ) ) ; sb_1__2__mux_2level_tapbuf_size2 mux_bottom_track_51 ( .in ( { chanx_right_in[4] , bottom_left_grid_pin_51_[0] } ) , .sram ( mux_2level_tapbuf_size2_10_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_161 , SYNOPSYS_UNCONNECTED_162 } ) , - .out ( chany_bottom_out[25] ) , .p0 ( optlc_net_201 ) ) ; + .out ( chany_bottom_out[25] ) , .p0 ( optlc_net_210 ) ) ; sb_1__2__mux_2level_tapbuf_size2_mem_0 mem_bottom_track_29 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( mux_2level_tapbuf_size3_mem_3_ccff_tail ) , @@ -42133,18 +44869,18 @@ sb_1__2__mux_2level_tapbuf_size2_mem mem_bottom_track_51 ( .ccff_tail ( mux_2level_tapbuf_size2_mem_10_ccff_tail ) , .mem_out ( mux_2level_tapbuf_size2_10_sram ) ) ; sky130_fd_sc_hd__buf_8 pReset_FTB00 ( .A ( pReset_E_in ) , .X ( pReset[0] ) ) ; -sky130_fd_sc_hd__bufbuf_16 pReset_W_FTB01 ( .A ( pReset_E_in ) , - .X ( pReset_W_out ) ) ; +sky130_fd_sc_hd__buf_1 pReset_W_FTB01 ( .A ( pReset_E_in ) , + .X ( aps_rename_509_ ) ) ; sky130_fd_sc_hd__buf_1 pReset_E_FTB01 ( .A ( pReset_E_in ) , - .X ( net_net_198 ) ) ; + .X ( aps_rename_510_ ) ) ; sky130_fd_sc_hd__buf_1 prog_clk_0_FTB00 ( .A ( prog_clk_0_S_in ) , .X ( prog_clk[0] ) ) ; -sky130_fd_sc_hd__buf_8 FTB_107__106 ( .A ( chanx_right_in[0] ) , - .X ( chany_bottom_out[28] ) ) ; +sky130_fd_sc_hd__buf_6 FTB_107__106 ( .A ( chanx_right_in[0] ) , + .X ( ropt_net_228 ) ) ; sky130_fd_sc_hd__buf_8 FTB_108__107 ( .A ( chanx_right_in[1] ) , .X ( chany_bottom_out[27] ) ) ; sky130_fd_sc_hd__buf_6 FTB_109__108 ( .A ( chanx_right_in[2] ) , - .X ( ropt_net_228 ) ) ; + .X ( ropt_net_227 ) ) ; sky130_fd_sc_hd__buf_8 FTB_110__109 ( .A ( chanx_right_in[3] ) , .X ( chanx_left_out[4] ) ) ; sky130_fd_sc_hd__buf_8 FTB_111__110 ( .A ( chanx_right_in[6] ) , @@ -42224,8 +44960,9 @@ sky130_fd_sc_hd__buf_8 FTB_147__146 ( .A ( chanx_left_in[27] ) , sky130_fd_sc_hd__buf_8 FTB_148__147 ( .A ( chanx_left_in[28] ) , .X ( chanx_right_out[29] ) ) ; sky130_fd_sc_hd__buf_8 FTB_149__148 ( .A ( SC_IN_BOT ) , .X ( SC_OUT_BOT ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_198 ( .A ( net_net_198 ) , - .X ( pReset_E_out ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_197 ( .A ( BUF_net_198 ) , .Y ( pReset_W_out ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_198 ( .A ( aps_rename_509_ ) , + .Y ( BUF_net_198 ) ) ; sky130_fd_sc_hd__conb_1 optlc_203 ( .LO ( SYNOPSYS_UNCONNECTED_163 ) , .HI ( optlc_net_201 ) ) ; sky130_fd_sc_hd__conb_1 optlc_205 ( .LO ( SYNOPSYS_UNCONNECTED_164 ) , @@ -42236,20 +44973,24 @@ sky130_fd_sc_hd__conb_1 optlc_211 ( .LO ( SYNOPSYS_UNCONNECTED_166 ) , .HI ( optlc_net_204 ) ) ; sky130_fd_sc_hd__conb_1 optlc_213 ( .LO ( SYNOPSYS_UNCONNECTED_167 ) , .HI ( optlc_net_205 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_217 ( .LO ( SYNOPSYS_UNCONNECTED_168 ) , +sky130_fd_sc_hd__conb_1 optlc_215 ( .LO ( SYNOPSYS_UNCONNECTED_168 ) , .HI ( optlc_net_206 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_219 ( .LO ( SYNOPSYS_UNCONNECTED_169 ) , +sky130_fd_sc_hd__conb_1 optlc_218 ( .LO ( SYNOPSYS_UNCONNECTED_169 ) , .HI ( optlc_net_207 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_223 ( .LO ( SYNOPSYS_UNCONNECTED_170 ) , +sky130_fd_sc_hd__conb_1 optlc_220 ( .LO ( SYNOPSYS_UNCONNECTED_170 ) , .HI ( optlc_net_208 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_225 ( .LO ( SYNOPSYS_UNCONNECTED_171 ) , +sky130_fd_sc_hd__conb_1 optlc_223 ( .LO ( SYNOPSYS_UNCONNECTED_171 ) , .HI ( optlc_net_209 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_227 ( .LO ( SYNOPSYS_UNCONNECTED_172 ) , +sky130_fd_sc_hd__conb_1 optlc_225 ( .LO ( SYNOPSYS_UNCONNECTED_172 ) , .HI ( optlc_net_210 ) ) ; -sky130_fd_sc_hd__buf_6 ZBUF_6_f_inst_228 ( .A ( aps_rename_507_ ) , +sky130_fd_sc_hd__buf_6 ZBUF_6_f_inst_226 ( .A ( aps_rename_508_ ) , .X ( chanx_right_out[5] ) ) ; -sky130_fd_sc_hd__buf_8 ropt_mt_inst_1437 ( .A ( ropt_net_228 ) , +sky130_fd_sc_hd__buf_6 ZBUF_6_f_inst_227 ( .A ( aps_rename_510_ ) , + .X ( pReset_E_out ) ) ; +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1435 ( .A ( ropt_net_227 ) , .X ( chany_bottom_out[26] ) ) ; +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1436 ( .A ( ropt_net_228 ) , + .X ( chany_bottom_out[28] ) ) ; endmodule @@ -42261,8 +45002,6 @@ input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -wire copt_net_208 ; - sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , @@ -42270,13 +45009,8 @@ sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( copt_net_208 ) ) ; -sky130_fd_sc_hd__bufbuf_8 FTB_68__67 ( .A ( copt_net_209 ) , - .X ( ccff_tail[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1418 ( .A ( copt_net_208 ) , - .X ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1419 ( .A ( mem_out[3] ) , - .X ( copt_net_209 ) ) ; + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_6 FTB_68__67 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -42508,10 +45242,14 @@ input [0:2] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -42522,10 +45260,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -42536,10 +45278,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -42597,6 +45343,8 @@ wire [0:0] mux_2level_tapbuf_basis_input3_mem3_2_out ; sb_1__1__const1 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( mux_2level_tapbuf_basis_input3_mem3_2_out[0] ) , .X ( out[0] ) ) ; sb_1__1__local_encoder2to3_22 local_encoder2to3_0_ ( .addr ( sram[0:1] ) , .data ( local_encoder2to3_0_data ) , .data_inv ( local_encoder2to3_0_data_inv ) ) ; @@ -42618,8 +45366,6 @@ sb_1__1__mux_2level_tapbuf_basis_input3_mem3 mux_l2_in_0_ ( .mem ( local_encoder2to3_1_data ) , .mem_inv ( local_encoder2to3_1_data_inv ) , .out ( mux_2level_tapbuf_basis_input3_mem3_2_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_190 ( - .A ( mux_2level_tapbuf_basis_input3_mem3_2_out[0] ) , .X ( out[0] ) ) ; endmodule @@ -42631,10 +45377,14 @@ input [0:2] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -42645,10 +45395,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -42659,10 +45413,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -42741,9 +45499,9 @@ sb_1__1__mux_2level_tapbuf_basis_input3_mem3_40 mux_l2_in_0_ ( .mem ( local_encoder2to3_1_data ) , .mem_inv ( local_encoder2to3_1_data_inv ) , .out ( mux_2level_tapbuf_basis_input3_mem3_2_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_188 ( .A ( BUF_net_189 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_189 ( - .A ( mux_2level_tapbuf_basis_input3_mem3_2_out[0] ) , .Y ( BUF_net_189 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_170 ( .A ( BUF_net_171 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_171 ( + .A ( mux_2level_tapbuf_basis_input3_mem3_2_out[0] ) , .Y ( BUF_net_171 ) ) ; endmodule @@ -42755,10 +45513,14 @@ input [0:2] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -42769,10 +45531,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -42783,10 +45549,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -42815,7 +45585,7 @@ sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ; sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ; sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) , .Y ( data_inv[1] ) ) ; -sky130_fd_sc_hd__inv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ; +sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ; sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) , .Y ( data[0] ) ) ; sky130_fd_sc_hd__buf_1 FTB_51__50 ( .A ( addr[1] ) , .X ( data[2] ) ) ; @@ -42865,9 +45635,9 @@ sb_1__1__mux_2level_tapbuf_basis_input3_mem3_37 mux_l2_in_0_ ( .mem ( local_encoder2to3_1_data ) , .mem_inv ( local_encoder2to3_1_data_inv ) , .out ( mux_2level_tapbuf_basis_input3_mem3_2_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_186 ( .A ( BUF_net_187 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_187 ( - .A ( mux_2level_tapbuf_basis_input3_mem3_2_out[0] ) , .Y ( BUF_net_187 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_164 ( .A ( BUF_net_165 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_165 ( + .A ( mux_2level_tapbuf_basis_input3_mem3_2_out[0] ) , .Y ( BUF_net_165 ) ) ; endmodule @@ -42879,10 +45649,14 @@ input [0:2] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -42893,10 +45667,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -42907,10 +45685,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -42968,6 +45750,8 @@ wire [0:0] mux_2level_tapbuf_basis_input3_mem3_2_out ; sb_1__1__const1_40 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( mux_2level_tapbuf_basis_input3_mem3_2_out[0] ) , .X ( out[0] ) ) ; sb_1__1__local_encoder2to3_16 local_encoder2to3_0_ ( .addr ( sram[0:1] ) , .data ( local_encoder2to3_0_data ) , .data_inv ( local_encoder2to3_0_data_inv ) ) ; @@ -42989,9 +45773,6 @@ sb_1__1__mux_2level_tapbuf_basis_input3_mem3_34 mux_l2_in_0_ ( .mem ( local_encoder2to3_1_data ) , .mem_inv ( local_encoder2to3_1_data_inv ) , .out ( mux_2level_tapbuf_basis_input3_mem3_2_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_184 ( .A ( BUF_net_185 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_185 ( - .A ( mux_2level_tapbuf_basis_input3_mem3_2_out[0] ) , .Y ( BUF_net_185 ) ) ; endmodule @@ -43003,10 +45784,14 @@ input [0:2] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -43017,10 +45802,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -43031,10 +45820,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -43126,10 +45919,14 @@ input [0:2] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -43140,10 +45937,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -43154,10 +45955,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -43215,6 +46020,8 @@ wire [0:0] mux_2level_tapbuf_basis_input3_mem3_2_out ; sb_1__1__const1_38 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( mux_2level_tapbuf_basis_input3_mem3_2_out[0] ) , .X ( out[0] ) ) ; sb_1__1__local_encoder2to3_12 local_encoder2to3_0_ ( .addr ( sram[0:1] ) , .data ( local_encoder2to3_0_data ) , .data_inv ( local_encoder2to3_0_data_inv ) ) ; @@ -43236,9 +46043,6 @@ sb_1__1__mux_2level_tapbuf_basis_input3_mem3_28 mux_l2_in_0_ ( .mem ( local_encoder2to3_1_data ) , .mem_inv ( local_encoder2to3_1_data_inv ) , .out ( mux_2level_tapbuf_basis_input3_mem3_2_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_182 ( .A ( BUF_net_183 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_183 ( - .A ( mux_2level_tapbuf_basis_input3_mem3_2_out[0] ) , .Y ( BUF_net_183 ) ) ; endmodule @@ -43250,10 +46054,14 @@ input [0:2] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -43264,10 +46072,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -43278,10 +46090,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -43360,9 +46176,8 @@ sb_1__1__mux_2level_tapbuf_basis_input3_mem3_25 mux_l2_in_0_ ( .mem ( local_encoder2to3_1_data ) , .mem_inv ( local_encoder2to3_1_data_inv ) , .out ( mux_2level_tapbuf_basis_input3_mem3_2_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_180 ( .A ( BUF_net_181 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_181 ( - .A ( mux_2level_tapbuf_basis_input3_mem3_2_out[0] ) , .Y ( BUF_net_181 ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_163 ( + .A ( mux_2level_tapbuf_basis_input3_mem3_2_out[0] ) , .X ( out[0] ) ) ; endmodule @@ -43374,10 +46189,14 @@ input [0:2] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -43388,10 +46207,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -43402,10 +46225,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -43484,9 +46311,8 @@ sb_1__1__mux_2level_tapbuf_basis_input3_mem3_22 mux_l2_in_0_ ( .mem ( local_encoder2to3_1_data ) , .mem_inv ( local_encoder2to3_1_data_inv ) , .out ( mux_2level_tapbuf_basis_input3_mem3_2_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_178 ( .A ( BUF_net_179 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_179 ( - .A ( mux_2level_tapbuf_basis_input3_mem3_2_out[0] ) , .Y ( BUF_net_179 ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_162 ( + .A ( mux_2level_tapbuf_basis_input3_mem3_2_out[0] ) , .X ( out[0] ) ) ; endmodule @@ -43498,10 +46324,14 @@ input [0:2] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -43512,10 +46342,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -43526,10 +46360,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -43587,6 +46425,8 @@ wire [0:0] mux_2level_tapbuf_basis_input3_mem3_2_out ; sb_1__1__const1_35 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( mux_2level_tapbuf_basis_input3_mem3_2_out[0] ) , .X ( out[0] ) ) ; sb_1__1__local_encoder2to3_6 local_encoder2to3_0_ ( .addr ( sram[0:1] ) , .data ( local_encoder2to3_0_data ) , .data_inv ( local_encoder2to3_0_data_inv ) ) ; @@ -43608,9 +46448,6 @@ sb_1__1__mux_2level_tapbuf_basis_input3_mem3_19 mux_l2_in_0_ ( .mem ( local_encoder2to3_1_data ) , .mem_inv ( local_encoder2to3_1_data_inv ) , .out ( mux_2level_tapbuf_basis_input3_mem3_2_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_176 ( .A ( BUF_net_177 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_177 ( - .A ( mux_2level_tapbuf_basis_input3_mem3_2_out[0] ) , .Y ( BUF_net_177 ) ) ; endmodule @@ -43622,10 +46459,14 @@ input [0:2] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -43636,10 +46477,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -43650,10 +46495,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -43711,6 +46560,8 @@ wire [0:0] mux_2level_tapbuf_basis_input3_mem3_2_out ; sb_1__1__const1_34 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( mux_2level_tapbuf_basis_input3_mem3_2_out[0] ) , .X ( out[0] ) ) ; sb_1__1__local_encoder2to3_4 local_encoder2to3_0_ ( .addr ( sram[0:1] ) , .data ( local_encoder2to3_0_data ) , .data_inv ( local_encoder2to3_0_data_inv ) ) ; @@ -43732,9 +46583,6 @@ sb_1__1__mux_2level_tapbuf_basis_input3_mem3_16 mux_l2_in_0_ ( .mem ( local_encoder2to3_1_data ) , .mem_inv ( local_encoder2to3_1_data_inv ) , .out ( mux_2level_tapbuf_basis_input3_mem3_2_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_174 ( .A ( BUF_net_175 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_175 ( - .A ( mux_2level_tapbuf_basis_input3_mem3_2_out[0] ) , .Y ( BUF_net_175 ) ) ; endmodule @@ -43746,10 +46594,14 @@ input [0:2] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -43760,10 +46612,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -43774,10 +46630,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -43835,6 +46695,8 @@ wire [0:0] mux_2level_tapbuf_basis_input3_mem3_2_out ; sb_1__1__const1_33 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( mux_2level_tapbuf_basis_input3_mem3_2_out[0] ) , .X ( out[0] ) ) ; sb_1__1__local_encoder2to3_2 local_encoder2to3_0_ ( .addr ( sram[0:1] ) , .data ( local_encoder2to3_0_data ) , .data_inv ( local_encoder2to3_0_data_inv ) ) ; @@ -43856,9 +46718,6 @@ sb_1__1__mux_2level_tapbuf_basis_input3_mem3_13 mux_l2_in_0_ ( .mem ( local_encoder2to3_1_data ) , .mem_inv ( local_encoder2to3_1_data_inv ) , .out ( mux_2level_tapbuf_basis_input3_mem3_2_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_195 ( .A ( BUF_net_196 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_196 ( - .A ( mux_2level_tapbuf_basis_input3_mem3_2_out[0] ) , .Y ( BUF_net_196 ) ) ; endmodule @@ -43870,10 +46729,14 @@ input [0:2] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -43884,10 +46747,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -43898,10 +46765,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -44073,12 +46944,18 @@ input [0:3] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -44089,12 +46966,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -44105,12 +46988,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -44176,8 +47065,9 @@ wire [0:0] mux_2level_tapbuf_basis_input4_mem4_2_out ; sb_1__1__const1_31 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( mux_2level_tapbuf_basis_input4_mem4_2_out[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_4_0_ ( + .A ( mux_2level_tapbuf_basis_input4_mem4_2_out[0] ) , + .X ( aps_rename_513_ ) ) ; sb_1__1__local_encoder2to4_62 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , .data ( local_encoder2to4_0_data ) , .data_inv ( local_encoder2to4_0_data_inv ) ) ; @@ -44199,6 +47089,9 @@ sb_1__1__mux_2level_tapbuf_basis_input4_mem4 mux_l2_in_0_ ( .mem ( local_encoder2to4_1_data ) , .mem_inv ( local_encoder2to4_1_data_inv ) , .out ( mux_2level_tapbuf_basis_input4_mem4_2_out ) , .p0 ( p0 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_160 ( .A ( BUF_net_161 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_161 ( .A ( aps_rename_513_ ) , + .Y ( BUF_net_161 ) ) ; endmodule @@ -44210,12 +47103,18 @@ input [0:3] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -44226,12 +47125,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -44242,12 +47147,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -44315,7 +47226,7 @@ sb_1__1__const1_30 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_4_0_ ( .A ( mux_2level_tapbuf_basis_input4_mem4_2_out[0] ) , - .X ( aps_rename_520_ ) ) ; + .X ( aps_rename_512_ ) ) ; sb_1__1__local_encoder2to4_60 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , .data ( local_encoder2to4_0_data ) , .data_inv ( local_encoder2to4_0_data_inv ) ) ; @@ -44337,9 +47248,9 @@ sb_1__1__mux_2level_tapbuf_basis_input4_mem4_100 mux_l2_in_0_ ( .mem ( local_encoder2to4_1_data ) , .mem_inv ( local_encoder2to4_1_data_inv ) , .out ( mux_2level_tapbuf_basis_input4_mem4_2_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_172 ( .A ( BUF_net_173 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_173 ( .A ( aps_rename_520_ ) , - .Y ( BUF_net_173 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_158 ( .A ( BUF_net_159 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_159 ( .A ( aps_rename_512_ ) , + .Y ( BUF_net_159 ) ) ; endmodule @@ -44351,12 +47262,18 @@ input [0:3] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -44367,12 +47284,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -44383,12 +47306,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -44454,9 +47383,8 @@ wire [0:0] mux_2level_tapbuf_basis_input4_mem4_2_out ; sb_1__1__const1_29 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_4_0_ ( - .A ( mux_2level_tapbuf_basis_input4_mem4_2_out[0] ) , - .X ( aps_rename_519_ ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( mux_2level_tapbuf_basis_input4_mem4_2_out[0] ) , .X ( out[0] ) ) ; sb_1__1__local_encoder2to4_58 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , .data ( local_encoder2to4_0_data ) , .data_inv ( local_encoder2to4_0_data_inv ) ) ; @@ -44478,9 +47406,6 @@ sb_1__1__mux_2level_tapbuf_basis_input4_mem4_97 mux_l2_in_0_ ( .mem ( local_encoder2to4_1_data ) , .mem_inv ( local_encoder2to4_1_data_inv ) , .out ( mux_2level_tapbuf_basis_input4_mem4_2_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_170 ( .A ( BUF_net_171 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_171 ( .A ( aps_rename_519_ ) , - .Y ( BUF_net_171 ) ) ; endmodule @@ -44492,12 +47417,18 @@ input [0:3] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -44508,12 +47439,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -44524,12 +47461,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -44597,7 +47540,7 @@ sb_1__1__const1_28 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_4_0_ ( .A ( mux_2level_tapbuf_basis_input4_mem4_2_out[0] ) , - .X ( aps_rename_518_ ) ) ; + .X ( aps_rename_511_ ) ) ; sb_1__1__local_encoder2to4_56 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , .data ( local_encoder2to4_0_data ) , .data_inv ( local_encoder2to4_0_data_inv ) ) ; @@ -44619,9 +47562,9 @@ sb_1__1__mux_2level_tapbuf_basis_input4_mem4_94 mux_l2_in_0_ ( .mem ( local_encoder2to4_1_data ) , .mem_inv ( local_encoder2to4_1_data_inv ) , .out ( mux_2level_tapbuf_basis_input4_mem4_2_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_168 ( .A ( BUF_net_169 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_169 ( .A ( aps_rename_518_ ) , - .Y ( BUF_net_169 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_156 ( .A ( BUF_net_157 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_157 ( .A ( aps_rename_511_ ) , + .Y ( BUF_net_157 ) ) ; endmodule @@ -44793,12 +47736,18 @@ input [0:3] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -44809,12 +47758,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -44825,12 +47780,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -44841,12 +47802,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -44913,9 +47880,8 @@ wire [0:0] mux_2level_tapbuf_basis_input4_mem4_3_out ; sb_1__1__const1_27 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_4_0_ ( - .A ( mux_2level_tapbuf_basis_input4_mem4_3_out[0] ) , - .X ( aps_rename_517_ ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( mux_2level_tapbuf_basis_input4_mem4_3_out[0] ) , .X ( out[0] ) ) ; sb_1__1__local_encoder2to4_54 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , .data ( local_encoder2to4_0_data ) , .data_inv ( local_encoder2to4_0_data_inv ) ) ; @@ -44942,9 +47908,6 @@ sb_1__1__mux_2level_tapbuf_basis_input4_mem4_91 mux_l2_in_0_ ( .mem ( local_encoder2to4_1_data ) , .mem_inv ( local_encoder2to4_1_data_inv ) , .out ( mux_2level_tapbuf_basis_input4_mem4_3_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_166 ( .A ( BUF_net_167 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_167 ( .A ( aps_rename_517_ ) , - .Y ( BUF_net_167 ) ) ; endmodule @@ -44956,12 +47919,18 @@ input [0:3] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -44972,12 +47941,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -44988,12 +47963,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -45004,12 +47985,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -45115,12 +48102,18 @@ input [0:3] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -45131,12 +48124,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -45147,12 +48146,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -45163,12 +48168,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -45235,7 +48246,7 @@ wire [0:0] mux_2level_tapbuf_basis_input4_mem4_3_out ; sb_1__1__const1_25 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__bufbuf_16 sky130_fd_sc_hd__buf_4_0_ ( +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( mux_2level_tapbuf_basis_input4_mem4_3_out[0] ) , .X ( out[0] ) ) ; sb_1__1__local_encoder2to4_50 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , .data ( local_encoder2to4_0_data ) , @@ -45274,12 +48285,18 @@ input [0:3] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -45290,12 +48307,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -45306,12 +48329,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -45322,12 +48351,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -45433,12 +48468,18 @@ input [0:3] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -45449,12 +48490,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -45465,12 +48512,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -45481,12 +48534,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -45555,7 +48614,7 @@ sb_1__1__const1_23 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_4_0_ ( .A ( mux_2level_tapbuf_basis_input4_mem4_3_out[0] ) , - .X ( aps_rename_516_ ) ) ; + .X ( aps_rename_510_ ) ) ; sb_1__1__local_encoder2to4_46 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , .data ( local_encoder2to4_0_data ) , .data_inv ( local_encoder2to4_0_data_inv ) ) ; @@ -45582,9 +48641,9 @@ sb_1__1__mux_2level_tapbuf_basis_input4_mem4_75 mux_l2_in_0_ ( .mem ( local_encoder2to4_1_data ) , .mem_inv ( local_encoder2to4_1_data_inv ) , .out ( mux_2level_tapbuf_basis_input4_mem4_3_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_164 ( .A ( BUF_net_165 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_165 ( .A ( aps_rename_516_ ) , - .Y ( BUF_net_165 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_154 ( .A ( BUF_net_155 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_155 ( .A ( aps_rename_510_ ) , + .Y ( BUF_net_155 ) ) ; endmodule @@ -45596,12 +48655,18 @@ input [0:3] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -45612,12 +48677,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -45628,12 +48699,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -45644,12 +48721,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -45716,7 +48799,7 @@ wire [0:0] mux_2level_tapbuf_basis_input4_mem4_3_out ; sb_1__1__const1_22 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_4_0_ ( +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( mux_2level_tapbuf_basis_input4_mem4_3_out[0] ) , .X ( out[0] ) ) ; sb_1__1__local_encoder2to4_44 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , .data ( local_encoder2to4_0_data ) , @@ -45755,12 +48838,18 @@ input [0:3] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -45771,12 +48860,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -45787,12 +48882,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -45803,12 +48904,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -45875,9 +48982,8 @@ wire [0:0] mux_2level_tapbuf_basis_input4_mem4_3_out ; sb_1__1__const1_21 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_4_0_ ( - .A ( mux_2level_tapbuf_basis_input4_mem4_3_out[0] ) , - .X ( aps_rename_515_ ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( mux_2level_tapbuf_basis_input4_mem4_3_out[0] ) , .X ( out[0] ) ) ; sb_1__1__local_encoder2to4_42 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , .data ( local_encoder2to4_0_data ) , .data_inv ( local_encoder2to4_0_data_inv ) ) ; @@ -45904,9 +49010,6 @@ sb_1__1__mux_2level_tapbuf_basis_input4_mem4_67 mux_l2_in_0_ ( .mem ( local_encoder2to4_1_data ) , .mem_inv ( local_encoder2to4_1_data_inv ) , .out ( mux_2level_tapbuf_basis_input4_mem4_3_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_162 ( .A ( BUF_net_163 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_163 ( .A ( aps_rename_515_ ) , - .Y ( BUF_net_163 ) ) ; endmodule @@ -45918,12 +49021,18 @@ input [0:3] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -45934,12 +49043,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -45950,12 +49065,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -45966,12 +49087,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -46038,9 +49165,8 @@ wire [0:0] mux_2level_tapbuf_basis_input4_mem4_3_out ; sb_1__1__const1_20 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_4_0_ ( - .A ( mux_2level_tapbuf_basis_input4_mem4_3_out[0] ) , - .X ( aps_rename_514_ ) ) ; +sky130_fd_sc_hd__bufbuf_16 sky130_fd_sc_hd__buf_4_0_ ( + .A ( mux_2level_tapbuf_basis_input4_mem4_3_out[0] ) , .X ( out[0] ) ) ; sb_1__1__local_encoder2to4_40 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , .data ( local_encoder2to4_0_data ) , .data_inv ( local_encoder2to4_0_data_inv ) ) ; @@ -46067,9 +49193,6 @@ sb_1__1__mux_2level_tapbuf_basis_input4_mem4_63 mux_l2_in_0_ ( .mem ( local_encoder2to4_1_data ) , .mem_inv ( local_encoder2to4_1_data_inv ) , .out ( mux_2level_tapbuf_basis_input4_mem4_3_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_160 ( .A ( BUF_net_161 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_161 ( .A ( aps_rename_514_ ) , - .Y ( BUF_net_161 ) ) ; endmodule @@ -46320,9 +49443,13 @@ input [0:1] mem ; input [0:1] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -46334,12 +49461,18 @@ input [0:3] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -46350,12 +49483,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -46366,12 +49505,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -46476,9 +49621,13 @@ input [0:1] mem ; input [0:1] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -46490,12 +49639,18 @@ input [0:3] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -46506,12 +49661,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -46522,12 +49683,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -46596,8 +49763,7 @@ wire [0:0] mux_2level_tapbuf_basis_input4_mem4_2_out ; sb_1__1__const1_18 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_4_0_ ( - .A ( mux_2level_tapbuf_basis_input4_mem4_2_out[0] ) , - .X ( aps_rename_513_ ) ) ; + .A ( mux_2level_tapbuf_basis_input4_mem4_2_out[0] ) , .X ( net_net_153 ) ) ; sb_1__1__local_encoder2to4_36 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , .data ( local_encoder2to4_0_data ) , .data_inv ( local_encoder2to4_0_data_inv ) ) ; @@ -46624,9 +49790,7 @@ sb_1__1__mux_2level_tapbuf_basis_input2_mem2_10 mux_l1_in_2_ ( .in ( in[8:9] ) , .mem ( local_encoder2to4_0_data[0:1] ) , .mem_inv ( local_encoder2to4_0_data_inv[0:1] ) , .out ( mux_2level_tapbuf_basis_input2_mem2_0_out ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_158 ( .A ( BUF_net_159 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_159 ( .A ( aps_rename_513_ ) , - .Y ( BUF_net_159 ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_153 ( .A ( net_net_153 ) , .X ( out[0] ) ) ; endmodule @@ -46637,9 +49801,13 @@ input [0:1] mem ; input [0:1] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -46651,12 +49819,18 @@ input [0:3] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -46667,12 +49841,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -46683,12 +49863,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -46757,7 +49943,7 @@ sb_1__1__const1_17 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_4_0_ ( .A ( mux_2level_tapbuf_basis_input4_mem4_2_out[0] ) , - .X ( aps_rename_512_ ) ) ; + .X ( aps_rename_509_ ) ) ; sb_1__1__local_encoder2to4_34 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , .data ( local_encoder2to4_0_data ) , .data_inv ( local_encoder2to4_0_data_inv ) ) ; @@ -46784,9 +49970,9 @@ sb_1__1__mux_2level_tapbuf_basis_input2_mem2_9 mux_l1_in_2_ ( .in ( in[8:9] ) , .mem ( local_encoder2to4_0_data[0:1] ) , .mem_inv ( local_encoder2to4_0_data_inv[0:1] ) , .out ( mux_2level_tapbuf_basis_input2_mem2_0_out ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_156 ( .A ( BUF_net_157 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_157 ( .A ( aps_rename_512_ ) , - .Y ( BUF_net_157 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_151 ( .A ( BUF_net_152 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_152 ( .A ( aps_rename_509_ ) , + .Y ( BUF_net_152 ) ) ; endmodule @@ -46797,9 +49983,13 @@ input [0:1] mem ; input [0:1] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -46811,12 +50001,18 @@ input [0:3] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -46827,12 +50023,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -46843,12 +50045,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -46953,9 +50161,13 @@ input [0:1] mem ; input [0:1] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -46967,12 +50179,18 @@ input [0:3] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -46983,12 +50201,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -46999,12 +50223,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -47109,9 +50339,13 @@ input [0:1] mem ; input [0:1] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -47123,12 +50357,18 @@ input [0:3] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -47139,12 +50379,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -47155,12 +50401,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -47265,9 +50517,13 @@ input [0:1] mem ; input [0:1] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -47279,12 +50535,18 @@ input [0:3] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -47295,12 +50557,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -47311,12 +50579,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -47383,9 +50657,8 @@ wire [0:0] mux_2level_tapbuf_basis_input4_mem4_2_out ; sb_1__1__const1_13 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_4_0_ ( - .A ( mux_2level_tapbuf_basis_input4_mem4_2_out[0] ) , - .X ( aps_rename_511_ ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( mux_2level_tapbuf_basis_input4_mem4_2_out[0] ) , .X ( out[0] ) ) ; sb_1__1__local_encoder2to4_26 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , .data ( local_encoder2to4_0_data ) , .data_inv ( local_encoder2to4_0_data_inv ) ) ; @@ -47412,9 +50685,6 @@ sb_1__1__mux_2level_tapbuf_basis_input2_mem2_5 mux_l1_in_2_ ( .in ( in[8:9] ) , .mem ( local_encoder2to4_0_data[0:1] ) , .mem_inv ( local_encoder2to4_0_data_inv[0:1] ) , .out ( mux_2level_tapbuf_basis_input2_mem2_0_out ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_154 ( .A ( BUF_net_155 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_155 ( .A ( aps_rename_511_ ) , - .Y ( BUF_net_155 ) ) ; endmodule @@ -47425,9 +50695,13 @@ input [0:1] mem ; input [0:1] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -47439,12 +50713,18 @@ input [0:3] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -47455,12 +50735,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -47471,12 +50757,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -47545,7 +50837,7 @@ sb_1__1__const1_12 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_4_0_ ( .A ( mux_2level_tapbuf_basis_input4_mem4_2_out[0] ) , - .X ( aps_rename_510_ ) ) ; + .X ( aps_rename_508_ ) ) ; sb_1__1__local_encoder2to4_24 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , .data ( local_encoder2to4_0_data ) , .data_inv ( local_encoder2to4_0_data_inv ) ) ; @@ -47572,9 +50864,9 @@ sb_1__1__mux_2level_tapbuf_basis_input2_mem2_4 mux_l1_in_2_ ( .in ( in[8:9] ) , .mem ( local_encoder2to4_0_data[0:1] ) , .mem_inv ( local_encoder2to4_0_data_inv[0:1] ) , .out ( mux_2level_tapbuf_basis_input2_mem2_0_out ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_152 ( .A ( BUF_net_153 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_153 ( .A ( aps_rename_510_ ) , - .Y ( BUF_net_153 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_149 ( .A ( BUF_net_150 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_150 ( .A ( aps_rename_508_ ) , + .Y ( BUF_net_150 ) ) ; endmodule @@ -47585,9 +50877,13 @@ input [0:1] mem ; input [0:1] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -47599,12 +50895,18 @@ input [0:3] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -47615,12 +50917,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -47631,12 +50939,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -47703,9 +51017,8 @@ wire [0:0] mux_2level_tapbuf_basis_input4_mem4_2_out ; sb_1__1__const1_11 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_4_0_ ( - .A ( mux_2level_tapbuf_basis_input4_mem4_2_out[0] ) , - .X ( aps_rename_509_ ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( mux_2level_tapbuf_basis_input4_mem4_2_out[0] ) , .X ( out[0] ) ) ; sb_1__1__local_encoder2to4_22 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , .data ( local_encoder2to4_0_data ) , .data_inv ( local_encoder2to4_0_data_inv ) ) ; @@ -47732,9 +51045,6 @@ sb_1__1__mux_2level_tapbuf_basis_input2_mem2_3 mux_l1_in_2_ ( .in ( in[8:9] ) , .mem ( local_encoder2to4_0_data[0:1] ) , .mem_inv ( local_encoder2to4_0_data_inv[0:1] ) , .out ( mux_2level_tapbuf_basis_input2_mem2_0_out ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_150 ( .A ( BUF_net_151 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_151 ( .A ( aps_rename_509_ ) , - .Y ( BUF_net_151 ) ) ; endmodule @@ -47745,9 +51055,13 @@ input [0:1] mem ; input [0:1] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -47759,12 +51073,18 @@ input [0:3] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -47775,12 +51095,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -47791,12 +51117,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -47863,7 +51195,7 @@ wire [0:0] mux_2level_tapbuf_basis_input4_mem4_2_out ; sb_1__1__const1_10 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__bufbuf_16 sky130_fd_sc_hd__buf_4_0_ ( +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( mux_2level_tapbuf_basis_input4_mem4_2_out[0] ) , .X ( out[0] ) ) ; sb_1__1__local_encoder2to4_20 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , .data ( local_encoder2to4_0_data ) , @@ -47901,9 +51233,13 @@ input [0:1] mem ; input [0:1] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -47915,12 +51251,18 @@ input [0:3] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -47931,12 +51273,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -47947,12 +51295,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -48019,9 +51373,8 @@ wire [0:0] mux_2level_tapbuf_basis_input4_mem4_2_out ; sb_1__1__const1_9 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_4_0_ ( - .A ( mux_2level_tapbuf_basis_input4_mem4_2_out[0] ) , - .X ( aps_rename_508_ ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( mux_2level_tapbuf_basis_input4_mem4_2_out[0] ) , .X ( out[0] ) ) ; sb_1__1__local_encoder2to4_18 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , .data ( local_encoder2to4_0_data ) , .data_inv ( local_encoder2to4_0_data_inv ) ) ; @@ -48048,9 +51401,6 @@ sb_1__1__mux_2level_tapbuf_basis_input2_mem2_1 mux_l1_in_2_ ( .in ( in[8:9] ) , .mem ( local_encoder2to4_0_data[0:1] ) , .mem_inv ( local_encoder2to4_0_data_inv[0:1] ) , .out ( mux_2level_tapbuf_basis_input2_mem2_0_out ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_193 ( .A ( BUF_net_194 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_194 ( .A ( aps_rename_508_ ) , - .Y ( BUF_net_194 ) ) ; endmodule @@ -48061,9 +51411,13 @@ input [0:1] mem ; input [0:1] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -48075,12 +51429,18 @@ input [0:3] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -48091,12 +51451,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -48107,12 +51473,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -48179,9 +51551,8 @@ wire [0:0] mux_2level_tapbuf_basis_input4_mem4_2_out ; sb_1__1__const1_8 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_4_0_ ( - .A ( mux_2level_tapbuf_basis_input4_mem4_2_out[0] ) , - .X ( aps_rename_507_ ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( mux_2level_tapbuf_basis_input4_mem4_2_out[0] ) , .X ( out[0] ) ) ; sb_1__1__local_encoder2to4_16 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , .data ( local_encoder2to4_0_data ) , .data_inv ( local_encoder2to4_0_data_inv ) ) ; @@ -48208,9 +51579,6 @@ sb_1__1__mux_2level_tapbuf_basis_input2_mem2_0 mux_l1_in_2_ ( .in ( in[8:9] ) , .mem ( local_encoder2to4_0_data[0:1] ) , .mem_inv ( local_encoder2to4_0_data_inv[0:1] ) , .out ( mux_2level_tapbuf_basis_input2_mem2_0_out ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_148 ( .A ( BUF_net_149 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_149 ( .A ( aps_rename_507_ ) , - .Y ( BUF_net_149 ) ) ; endmodule @@ -48362,7 +51730,7 @@ input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( copt_net_207 ) , +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; @@ -48371,10 +51739,6 @@ sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__buf_1 FTB_1__0 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 copt_h_inst_1416 ( .A ( ccff_head[0] ) , - .X ( copt_net_206 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1417 ( .A ( copt_net_206 ) , - .X ( copt_net_207 ) ) ; endmodule @@ -48385,10 +51749,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -48400,12 +51768,18 @@ input [0:3] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -48416,12 +51790,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -48432,12 +51812,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -48504,7 +51890,7 @@ wire [0:0] mux_2level_tapbuf_basis_input4_mem4_2_out ; sb_1__1__const1_7 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__bufbuf_16 sky130_fd_sc_hd__buf_4_0_ ( +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( mux_2level_tapbuf_basis_input4_mem4_2_out[0] ) , .X ( out[0] ) ) ; sb_1__1__local_encoder2to4_14 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , .data ( local_encoder2to4_0_data ) , @@ -48542,10 +51928,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -48557,12 +51947,18 @@ input [0:3] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -48573,12 +51969,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -48589,12 +51991,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -48661,8 +52069,9 @@ wire [0:0] mux_2level_tapbuf_basis_input4_mem4_2_out ; sb_1__1__const1_6 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( mux_2level_tapbuf_basis_input4_mem4_2_out[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_4_0_ ( + .A ( mux_2level_tapbuf_basis_input4_mem4_2_out[0] ) , + .X ( aps_rename_507_ ) ) ; sb_1__1__local_encoder2to4_12 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , .data ( local_encoder2to4_0_data ) , .data_inv ( local_encoder2to4_0_data_inv ) ) ; @@ -48689,6 +52098,9 @@ sb_1__1__mux_2level_tapbuf_basis_input3_mem3_6 mux_l1_in_2_ ( .in ( in[8:10] ) , .mem ( local_encoder2to4_0_data[0:2] ) , .mem_inv ( local_encoder2to4_0_data_inv[0:2] ) , .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_147 ( .A ( BUF_net_148 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_148 ( .A ( aps_rename_507_ ) , + .Y ( BUF_net_148 ) ) ; endmodule @@ -48699,10 +52111,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -48714,12 +52130,18 @@ input [0:3] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -48730,12 +52152,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -48746,12 +52174,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -48818,8 +52252,8 @@ wire [0:0] mux_2level_tapbuf_basis_input4_mem4_2_out ; sb_1__1__const1_5 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__bufbuf_16 sky130_fd_sc_hd__buf_4_0_ ( - .A ( mux_2level_tapbuf_basis_input4_mem4_2_out[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_4_0_ ( + .A ( mux_2level_tapbuf_basis_input4_mem4_2_out[0] ) , .X ( net_net_146 ) ) ; sb_1__1__local_encoder2to4_10 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , .data ( local_encoder2to4_0_data ) , .data_inv ( local_encoder2to4_0_data_inv ) ) ; @@ -48846,6 +52280,7 @@ sb_1__1__mux_2level_tapbuf_basis_input3_mem3_5 mux_l1_in_2_ ( .in ( in[8:10] ) , .mem ( local_encoder2to4_0_data[0:2] ) , .mem_inv ( local_encoder2to4_0_data_inv[0:2] ) , .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_146 ( .A ( net_net_146 ) , .X ( out[0] ) ) ; endmodule @@ -48856,10 +52291,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -48871,12 +52310,18 @@ input [0:3] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -48887,12 +52332,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -48903,12 +52354,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -49004,9 +52461,9 @@ sb_1__1__mux_2level_tapbuf_basis_input3_mem3_4 mux_l1_in_2_ ( .in ( in[8:10] ) , .mem ( local_encoder2to4_0_data[0:2] ) , .mem_inv ( local_encoder2to4_0_data_inv[0:2] ) , .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_146 ( .A ( BUF_net_147 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_147 ( .A ( aps_rename_506_ ) , - .Y ( BUF_net_147 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_144 ( .A ( BUF_net_145 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_145 ( .A ( aps_rename_506_ ) , + .Y ( BUF_net_145 ) ) ; endmodule @@ -49017,10 +52474,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -49032,12 +52493,18 @@ input [0:3] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -49048,12 +52515,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -49064,12 +52537,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -49174,10 +52653,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -49189,12 +52672,18 @@ input [0:3] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -49205,12 +52694,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -49221,12 +52716,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -49293,7 +52794,7 @@ wire [0:0] mux_2level_tapbuf_basis_input4_mem4_2_out ; sb_1__1__const1_2 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_4_0_ ( +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( mux_2level_tapbuf_basis_input4_mem4_2_out[0] ) , .X ( out[0] ) ) ; sb_1__1__local_encoder2to4_4 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , .data ( local_encoder2to4_0_data ) , @@ -49331,10 +52832,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -49346,12 +52851,18 @@ input [0:3] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -49362,12 +52873,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -49378,12 +52895,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -49479,9 +53002,9 @@ sb_1__1__mux_2level_tapbuf_basis_input3_mem3_1 mux_l1_in_2_ ( .in ( in[8:10] ) , .mem ( local_encoder2to4_0_data[0:2] ) , .mem_inv ( local_encoder2to4_0_data_inv[0:2] ) , .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_144 ( .A ( BUF_net_145 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_145 ( .A ( aps_rename_505_ ) , - .Y ( BUF_net_145 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_172 ( .A ( BUF_net_173 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_173 ( .A ( aps_rename_505_ ) , + .Y ( BUF_net_173 ) ) ; endmodule @@ -49492,10 +53015,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -49507,12 +53034,18 @@ input [0:3] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -49523,12 +53056,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -49539,12 +53078,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -49902,7 +53447,7 @@ sb_1__1__mux_2level_tapbuf_size11_0 mux_top_track_0 ( .sram ( mux_2level_tapbuf_size11_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 , SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) , - .out ( chany_top_out[0] ) , .p0 ( optlc_net_200 ) ) ; + .out ( chany_top_out[0] ) , .p0 ( optlc_net_179 ) ) ; sb_1__1__mux_2level_tapbuf_size11_1 mux_top_track_2 ( .in ( { top_left_grid_pin_45_[0] , top_left_grid_pin_48_[0] , top_left_grid_pin_51_[0] , chanx_right_in[2] , chanx_left_out[7] , @@ -49911,7 +53456,7 @@ sb_1__1__mux_2level_tapbuf_size11_1 mux_top_track_2 ( .sram ( mux_2level_tapbuf_size11_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 , SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 } ) , - .out ( chany_top_out[1] ) , .p0 ( optlc_net_201 ) ) ; + .out ( chany_top_out[1] ) , .p0 ( optlc_net_179 ) ) ; sb_1__1__mux_2level_tapbuf_size11_2 mux_right_track_0 ( .in ( { chany_bottom_out[4] , chany_bottom_out[20] , chany_top_in[29] , right_bottom_grid_pin_36_[0] , right_bottom_grid_pin_39_[0] , @@ -49920,8 +53465,7 @@ sb_1__1__mux_2level_tapbuf_size11_2 mux_right_track_0 ( .sram ( mux_2level_tapbuf_size11_2_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_9 , SYNOPSYS_UNCONNECTED_10 , SYNOPSYS_UNCONNECTED_11 , SYNOPSYS_UNCONNECTED_12 } ) , - .out ( { aps_rename_521_ } ) , - .p0 ( optlc_net_198 ) ) ; + .out ( chanx_right_out[0] ) , .p0 ( optlc_net_180 ) ) ; sb_1__1__mux_2level_tapbuf_size11_3 mux_right_track_2 ( .in ( { chany_top_in[0] , chany_bottom_out[7] , chany_bottom_out[21] , right_bottom_grid_pin_37_[0] , right_bottom_grid_pin_40_[0] , @@ -49930,7 +53474,7 @@ sb_1__1__mux_2level_tapbuf_size11_3 mux_right_track_2 ( .sram ( mux_2level_tapbuf_size11_3_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 , SYNOPSYS_UNCONNECTED_15 , SYNOPSYS_UNCONNECTED_16 } ) , - .out ( chanx_right_out[1] ) , .p0 ( optlc_net_202 ) ) ; + .out ( chanx_right_out[1] ) , .p0 ( optlc_net_180 ) ) ; sb_1__1__mux_2level_tapbuf_size11_4 mux_bottom_track_1 ( .in ( { chany_bottom_out[4] , chany_bottom_out[20] , chanx_left_out[4] , chanx_left_out[20] , chanx_right_in[25] , @@ -49940,7 +53484,7 @@ sb_1__1__mux_2level_tapbuf_size11_4 mux_bottom_track_1 ( .sram ( mux_2level_tapbuf_size11_4_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_17 , SYNOPSYS_UNCONNECTED_18 , SYNOPSYS_UNCONNECTED_19 , SYNOPSYS_UNCONNECTED_20 } ) , - .out ( chany_bottom_out[0] ) , .p0 ( optlc_net_204 ) ) ; + .out ( chany_bottom_out[0] ) , .p0 ( optlc_net_176 ) ) ; sb_1__1__mux_2level_tapbuf_size11_5 mux_bottom_track_3 ( .in ( { chany_bottom_out[7] , chany_bottom_out[21] , chanx_left_out[7] , chanx_left_out[21] , chanx_right_in[21] , @@ -49950,7 +53494,7 @@ sb_1__1__mux_2level_tapbuf_size11_5 mux_bottom_track_3 ( .sram ( mux_2level_tapbuf_size11_5_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_21 , SYNOPSYS_UNCONNECTED_22 , SYNOPSYS_UNCONNECTED_23 , SYNOPSYS_UNCONNECTED_24 } ) , - .out ( chany_bottom_out[1] ) , .p0 ( optlc_net_199 ) ) ; + .out ( chany_bottom_out[1] ) , .p0 ( optlc_net_177 ) ) ; sb_1__1__mux_2level_tapbuf_size11_6 mux_left_track_1 ( .in ( { chany_top_in[0] , chany_bottom_out[4] , chany_bottom_out[20] , chanx_left_out[4] , chanx_left_out[20] , chany_top_out[4] , @@ -49960,7 +53504,7 @@ sb_1__1__mux_2level_tapbuf_size11_6 mux_left_track_1 ( .sram ( mux_2level_tapbuf_size11_6_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_25 , SYNOPSYS_UNCONNECTED_26 , SYNOPSYS_UNCONNECTED_27 , SYNOPSYS_UNCONNECTED_28 } ) , - .out ( chanx_left_out[0] ) , .p0 ( optlc_net_204 ) ) ; + .out ( chanx_left_out[0] ) , .p0 ( optlc_net_179 ) ) ; sb_1__1__mux_2level_tapbuf_size11 mux_left_track_3 ( .in ( { chany_bottom_out[7] , chany_bottom_out[21] , chany_top_in[29] , chanx_left_out[7] , chanx_left_out[21] , chany_bottom_in[0] , @@ -49969,7 +53513,7 @@ sb_1__1__mux_2level_tapbuf_size11 mux_left_track_3 ( .sram ( mux_2level_tapbuf_size11_7_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_29 , SYNOPSYS_UNCONNECTED_30 , SYNOPSYS_UNCONNECTED_31 , SYNOPSYS_UNCONNECTED_32 } ) , - .out ( chanx_left_out[1] ) , .p0 ( optlc_net_199 ) ) ; + .out ( chanx_left_out[1] ) , .p0 ( optlc_net_177 ) ) ; sb_1__1__mux_2level_tapbuf_size11_mem_0 mem_top_track_0 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( mux_2level_tapbuf_size11_mem_0_ccff_tail ) , @@ -50017,7 +53561,7 @@ sb_1__1__mux_2level_tapbuf_size10_0 mux_top_track_4 ( .sram ( mux_2level_tapbuf_size10_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_33 , SYNOPSYS_UNCONNECTED_34 , SYNOPSYS_UNCONNECTED_35 , SYNOPSYS_UNCONNECTED_36 } ) , - .out ( chany_top_out[2] ) , .p0 ( optlc_net_197 ) ) ; + .out ( chany_top_out[2] ) , .p0 ( optlc_net_174 ) ) ; sb_1__1__mux_2level_tapbuf_size10_1 mux_top_track_12 ( .in ( { top_left_grid_pin_44_[0] , top_left_grid_pin_50_[0] , chanx_left_out[12] , chanx_right_in[13] , chanx_left_out[27] , @@ -50026,7 +53570,7 @@ sb_1__1__mux_2level_tapbuf_size10_1 mux_top_track_12 ( .sram ( mux_2level_tapbuf_size10_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_37 , SYNOPSYS_UNCONNECTED_38 , SYNOPSYS_UNCONNECTED_39 , SYNOPSYS_UNCONNECTED_40 } ) , - .out ( chany_top_out[6] ) , .p0 ( optlc_net_200 ) ) ; + .out ( chany_top_out[6] ) , .p0 ( optlc_net_175 ) ) ; sb_1__1__mux_2level_tapbuf_size10_2 mux_top_track_20 ( .in ( { top_left_grid_pin_45_[0] , top_left_grid_pin_51_[0] , chanx_left_out[13] , chanx_right_in[17] , chanx_left_out[28] , @@ -50035,7 +53579,7 @@ sb_1__1__mux_2level_tapbuf_size10_2 mux_top_track_20 ( .sram ( mux_2level_tapbuf_size10_2_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_41 , SYNOPSYS_UNCONNECTED_42 , SYNOPSYS_UNCONNECTED_43 , SYNOPSYS_UNCONNECTED_44 } ) , - .out ( chany_top_out[10] ) , .p0 ( optlc_net_203 ) ) ; + .out ( chany_top_out[10] ) , .p0 ( optlc_net_179 ) ) ; sb_1__1__mux_2level_tapbuf_size10_3 mux_right_track_4 ( .in ( { chany_top_in[1] , chany_bottom_out[8] , chany_bottom_out[23] , right_bottom_grid_pin_38_[0] , right_bottom_grid_pin_41_[0] , @@ -50044,7 +53588,7 @@ sb_1__1__mux_2level_tapbuf_size10_3 mux_right_track_4 ( .sram ( mux_2level_tapbuf_size10_3_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_45 , SYNOPSYS_UNCONNECTED_46 , SYNOPSYS_UNCONNECTED_47 , SYNOPSYS_UNCONNECTED_48 } ) , - .out ( chanx_right_out[2] ) , .p0 ( optlc_net_198 ) ) ; + .out ( chanx_right_out[2] ) , .p0 ( optlc_net_175 ) ) ; sb_1__1__mux_2level_tapbuf_size10_4 mux_right_track_12 ( .in ( { chany_top_in[5] , chany_bottom_out[12] , chany_bottom_out[27] , right_bottom_grid_pin_36_[0] , right_bottom_grid_pin_42_[0] , @@ -50053,7 +53597,7 @@ sb_1__1__mux_2level_tapbuf_size10_4 mux_right_track_12 ( .sram ( mux_2level_tapbuf_size10_4_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_49 , SYNOPSYS_UNCONNECTED_50 , SYNOPSYS_UNCONNECTED_51 , SYNOPSYS_UNCONNECTED_52 } ) , - .out ( chanx_right_out[6] ) , .p0 ( optlc_net_202 ) ) ; + .out ( chanx_right_out[6] ) , .p0 ( optlc_net_180 ) ) ; sb_1__1__mux_2level_tapbuf_size10_5 mux_right_track_20 ( .in ( { chany_top_in[9] , chany_bottom_out[13] , chany_bottom_out[28] , right_bottom_grid_pin_37_[0] , right_bottom_grid_pin_43_[0] , @@ -50062,7 +53606,7 @@ sb_1__1__mux_2level_tapbuf_size10_5 mux_right_track_20 ( .sram ( mux_2level_tapbuf_size10_5_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_53 , SYNOPSYS_UNCONNECTED_54 , SYNOPSYS_UNCONNECTED_55 , SYNOPSYS_UNCONNECTED_56 } ) , - .out ( chanx_right_out[10] ) , .p0 ( optlc_net_202 ) ) ; + .out ( chanx_right_out[10] ) , .p0 ( optlc_net_180 ) ) ; sb_1__1__mux_2level_tapbuf_size10_6 mux_bottom_track_5 ( .in ( { chany_bottom_out[8] , chany_bottom_out[23] , chanx_left_out[8] , chanx_right_in[17] , chanx_left_out[23] , @@ -50071,7 +53615,7 @@ sb_1__1__mux_2level_tapbuf_size10_6 mux_bottom_track_5 ( .sram ( mux_2level_tapbuf_size10_6_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_57 , SYNOPSYS_UNCONNECTED_58 , SYNOPSYS_UNCONNECTED_59 , SYNOPSYS_UNCONNECTED_60 } ) , - .out ( chany_bottom_out[2] ) , .p0 ( optlc_net_201 ) ) ; + .out ( chany_bottom_out[2] ) , .p0 ( optlc_net_177 ) ) ; sb_1__1__mux_2level_tapbuf_size10_7 mux_bottom_track_13 ( .in ( { chany_bottom_out[12] , chany_bottom_out[27] , chanx_right_in[5] , chanx_left_out[12] , chanx_left_out[27] , @@ -50080,7 +53624,7 @@ sb_1__1__mux_2level_tapbuf_size10_7 mux_bottom_track_13 ( .sram ( mux_2level_tapbuf_size10_7_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_61 , SYNOPSYS_UNCONNECTED_62 , SYNOPSYS_UNCONNECTED_63 , SYNOPSYS_UNCONNECTED_64 } ) , - .out ( chany_bottom_out[6] ) , .p0 ( optlc_net_204 ) ) ; + .out ( chany_bottom_out[6] ) , .p0 ( optlc_net_176 ) ) ; sb_1__1__mux_2level_tapbuf_size10_8 mux_bottom_track_21 ( .in ( { chany_bottom_out[13] , chany_bottom_out[28] , chanx_right_in[4] , chanx_left_out[13] , chanx_left_out[28] , @@ -50089,7 +53633,7 @@ sb_1__1__mux_2level_tapbuf_size10_8 mux_bottom_track_21 ( .sram ( mux_2level_tapbuf_size10_8_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_65 , SYNOPSYS_UNCONNECTED_66 , SYNOPSYS_UNCONNECTED_67 , SYNOPSYS_UNCONNECTED_68 } ) , - .out ( chany_bottom_out[10] ) , .p0 ( optlc_net_204 ) ) ; + .out ( chany_bottom_out[10] ) , .p0 ( optlc_net_176 ) ) ; sb_1__1__mux_2level_tapbuf_size10_9 mux_left_track_5 ( .in ( { chany_bottom_out[8] , chany_bottom_out[23] , chany_top_in[25] , chanx_left_out[8] , chanx_left_out[23] , chany_bottom_in[1] , @@ -50098,7 +53642,7 @@ sb_1__1__mux_2level_tapbuf_size10_9 mux_left_track_5 ( .sram ( mux_2level_tapbuf_size10_9_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_69 , SYNOPSYS_UNCONNECTED_70 , SYNOPSYS_UNCONNECTED_71 , SYNOPSYS_UNCONNECTED_72 } ) , - .out ( chanx_left_out[2] ) , .p0 ( optlc_net_201 ) ) ; + .out ( chanx_left_out[2] ) , .p0 ( optlc_net_182 ) ) ; sb_1__1__mux_2level_tapbuf_size10_10 mux_left_track_13 ( .in ( { chany_bottom_out[12] , chany_top_in[13] , chany_bottom_out[27] , chanx_left_out[12] , chanx_left_out[27] , chany_bottom_in[5] , @@ -50107,7 +53651,7 @@ sb_1__1__mux_2level_tapbuf_size10_10 mux_left_track_13 ( .sram ( mux_2level_tapbuf_size10_10_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_73 , SYNOPSYS_UNCONNECTED_74 , SYNOPSYS_UNCONNECTED_75 , SYNOPSYS_UNCONNECTED_76 } ) , - .out ( chanx_left_out[6] ) , .p0 ( optlc_net_204 ) ) ; + .out ( chanx_left_out[6] ) , .p0 ( optlc_net_176 ) ) ; sb_1__1__mux_2level_tapbuf_size10 mux_left_track_21 ( .in ( { chany_top_in[9] , chany_bottom_out[13] , chany_bottom_out[28] , chanx_left_out[13] , chanx_left_out[28] , chany_bottom_in[9] , @@ -50116,7 +53660,7 @@ sb_1__1__mux_2level_tapbuf_size10 mux_left_track_21 ( .sram ( mux_2level_tapbuf_size10_11_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_77 , SYNOPSYS_UNCONNECTED_78 , SYNOPSYS_UNCONNECTED_79 , SYNOPSYS_UNCONNECTED_80 } ) , - .out ( chanx_left_out[10] ) , .p0 ( optlc_net_204 ) ) ; + .out ( chanx_left_out[10] ) , .p0 ( optlc_net_176 ) ) ; sb_1__1__mux_2level_tapbuf_size10_mem_0 mem_top_track_4 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( mux_2level_tapbuf_size11_mem_1_ccff_tail ) , @@ -50186,7 +53730,7 @@ sb_1__1__mux_2level_tapbuf_size12_0 mux_top_track_6 ( .sram ( mux_2level_tapbuf_size12_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_81 , SYNOPSYS_UNCONNECTED_82 , SYNOPSYS_UNCONNECTED_83 , SYNOPSYS_UNCONNECTED_84 } ) , - .out ( chany_top_out[3] ) , .p0 ( optlc_net_203 ) ) ; + .out ( chany_top_out[3] ) , .p0 ( optlc_net_182 ) ) ; sb_1__1__mux_2level_tapbuf_size12_1 mux_top_track_10 ( .in ( { top_left_grid_pin_45_[0] , top_left_grid_pin_47_[0] , top_left_grid_pin_49_[0] , top_left_grid_pin_51_[0] , @@ -50196,7 +53740,7 @@ sb_1__1__mux_2level_tapbuf_size12_1 mux_top_track_10 ( .sram ( mux_2level_tapbuf_size12_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_85 , SYNOPSYS_UNCONNECTED_86 , SYNOPSYS_UNCONNECTED_87 , SYNOPSYS_UNCONNECTED_88 } ) , - .out ( chany_top_out[5] ) , .p0 ( optlc_net_201 ) ) ; + .out ( chany_top_out[5] ) , .p0 ( optlc_net_179 ) ) ; sb_1__1__mux_2level_tapbuf_size12_2 mux_right_track_6 ( .in ( { chany_top_in[2] , chany_bottom_out[9] , chany_bottom_out[24] , right_bottom_grid_pin_36_[0] , right_bottom_grid_pin_38_[0] , @@ -50206,8 +53750,7 @@ sb_1__1__mux_2level_tapbuf_size12_2 mux_right_track_6 ( .sram ( mux_2level_tapbuf_size12_2_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_89 , SYNOPSYS_UNCONNECTED_90 , SYNOPSYS_UNCONNECTED_91 , SYNOPSYS_UNCONNECTED_92 } ) , - .out ( { aps_rename_522_ } ) , - .p0 ( optlc_net_202 ) ) ; + .out ( chanx_right_out[3] ) , .p0 ( optlc_net_180 ) ) ; sb_1__1__mux_2level_tapbuf_size12_3 mux_right_track_10 ( .in ( { chany_top_in[4] , chany_bottom_out[11] , chany_bottom_out[25] , right_bottom_grid_pin_37_[0] , right_bottom_grid_pin_39_[0] , @@ -50217,7 +53760,7 @@ sb_1__1__mux_2level_tapbuf_size12_3 mux_right_track_10 ( .sram ( mux_2level_tapbuf_size12_3_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_93 , SYNOPSYS_UNCONNECTED_94 , SYNOPSYS_UNCONNECTED_95 , SYNOPSYS_UNCONNECTED_96 } ) , - .out ( chanx_right_out[5] ) , .p0 ( optlc_net_202 ) ) ; + .out ( chanx_right_out[5] ) , .p0 ( optlc_net_180 ) ) ; sb_1__1__mux_2level_tapbuf_size12_4 mux_bottom_track_7 ( .in ( { chany_bottom_out[9] , chany_bottom_out[24] , chanx_left_out[9] , chanx_right_in[13] , chanx_left_out[24] , @@ -50227,7 +53770,7 @@ sb_1__1__mux_2level_tapbuf_size12_4 mux_bottom_track_7 ( .sram ( mux_2level_tapbuf_size12_4_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_97 , SYNOPSYS_UNCONNECTED_98 , SYNOPSYS_UNCONNECTED_99 , SYNOPSYS_UNCONNECTED_100 } ) , - .out ( chany_bottom_out[3] ) , .p0 ( optlc_net_199 ) ) ; + .out ( chany_bottom_out[3] ) , .p0 ( optlc_net_177 ) ) ; sb_1__1__mux_2level_tapbuf_size12_5 mux_bottom_track_11 ( .in ( { chany_bottom_out[11] , chany_bottom_out[25] , chanx_right_in[9] , chanx_left_out[11] , chanx_left_out[25] , @@ -50237,7 +53780,7 @@ sb_1__1__mux_2level_tapbuf_size12_5 mux_bottom_track_11 ( .sram ( mux_2level_tapbuf_size12_5_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_101 , SYNOPSYS_UNCONNECTED_102 , SYNOPSYS_UNCONNECTED_103 , SYNOPSYS_UNCONNECTED_104 } ) , - .out ( chany_bottom_out[5] ) , .p0 ( optlc_net_199 ) ) ; + .out ( chany_bottom_out[5] ) , .p0 ( optlc_net_176 ) ) ; sb_1__1__mux_2level_tapbuf_size12_6 mux_left_track_7 ( .in ( { chany_bottom_out[9] , chany_top_in[21] , chany_bottom_out[24] , chanx_left_out[9] , chanx_left_out[24] , chany_bottom_in[2] , @@ -50247,7 +53790,7 @@ sb_1__1__mux_2level_tapbuf_size12_6 mux_left_track_7 ( .sram ( mux_2level_tapbuf_size12_6_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_105 , SYNOPSYS_UNCONNECTED_106 , SYNOPSYS_UNCONNECTED_107 , SYNOPSYS_UNCONNECTED_108 } ) , - .out ( chanx_left_out[3] ) , .p0 ( optlc_net_199 ) ) ; + .out ( chanx_left_out[3] ) , .p0 ( optlc_net_182 ) ) ; sb_1__1__mux_2level_tapbuf_size12 mux_left_track_11 ( .in ( { chany_bottom_out[11] , chany_top_in[17] , chany_bottom_out[25] , chanx_left_out[11] , chanx_left_out[25] , chany_bottom_in[4] , @@ -50257,7 +53800,7 @@ sb_1__1__mux_2level_tapbuf_size12 mux_left_track_11 ( .sram ( mux_2level_tapbuf_size12_7_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_109 , SYNOPSYS_UNCONNECTED_110 , SYNOPSYS_UNCONNECTED_111 , SYNOPSYS_UNCONNECTED_112 } ) , - .out ( chanx_left_out[5] ) , .p0 ( optlc_net_204 ) ) ; + .out ( chanx_left_out[5] ) , .p0 ( optlc_net_177 ) ) ; sb_1__1__mux_2level_tapbuf_size12_mem_0 mem_top_track_6 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( mux_2level_tapbuf_size10_mem_0_ccff_tail ) , @@ -50306,7 +53849,7 @@ sb_1__1__mux_2level_tapbuf_size9_0 mux_top_track_28 ( .sram ( mux_2level_tapbuf_size9_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_113 , SYNOPSYS_UNCONNECTED_114 , SYNOPSYS_UNCONNECTED_115 , SYNOPSYS_UNCONNECTED_116 } ) , - .out ( chany_top_out[14] ) , .p0 ( optlc_net_198 ) ) ; + .out ( chany_top_out[14] ) , .p0 ( optlc_net_178 ) ) ; sb_1__1__mux_2level_tapbuf_size9_1 mux_right_track_28 ( .in ( { chany_top_in[13] , chany_bottom_out[15] , chany_bottom_out[29] , right_bottom_grid_pin_38_[0] , chany_bottom_in[2] , @@ -50315,7 +53858,7 @@ sb_1__1__mux_2level_tapbuf_size9_1 mux_right_track_28 ( .sram ( mux_2level_tapbuf_size9_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_117 , SYNOPSYS_UNCONNECTED_118 , SYNOPSYS_UNCONNECTED_119 , SYNOPSYS_UNCONNECTED_120 } ) , - .out ( chanx_right_out[14] ) , .p0 ( optlc_net_202 ) ) ; + .out ( chanx_right_out[14] ) , .p0 ( optlc_net_178 ) ) ; sb_1__1__mux_2level_tapbuf_size9_2 mux_bottom_track_29 ( .in ( { chany_bottom_out[15] , chany_bottom_out[29] , chanx_right_in[2] , chanx_left_out[15] , chanx_left_out[29] , @@ -50324,7 +53867,7 @@ sb_1__1__mux_2level_tapbuf_size9_2 mux_bottom_track_29 ( .sram ( mux_2level_tapbuf_size9_2_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_121 , SYNOPSYS_UNCONNECTED_122 , SYNOPSYS_UNCONNECTED_123 , SYNOPSYS_UNCONNECTED_124 } ) , - .out ( chany_bottom_out[14] ) , .p0 ( optlc_net_202 ) ) ; + .out ( chany_bottom_out[14] ) , .p0 ( optlc_net_180 ) ) ; sb_1__1__mux_2level_tapbuf_size9 mux_left_track_29 ( .in ( { chany_top_in[5] , chany_bottom_out[15] , chany_bottom_out[29] , chanx_left_out[15] , chanx_left_out[29] , chany_bottom_in[13] , @@ -50332,7 +53875,7 @@ sb_1__1__mux_2level_tapbuf_size9 mux_left_track_29 ( .sram ( mux_2level_tapbuf_size9_3_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_125 , SYNOPSYS_UNCONNECTED_126 , SYNOPSYS_UNCONNECTED_127 , SYNOPSYS_UNCONNECTED_128 } ) , - .out ( chanx_left_out[14] ) , .p0 ( optlc_net_204 ) ) ; + .out ( chanx_left_out[14] ) , .p0 ( optlc_net_179 ) ) ; sb_1__1__mux_2level_tapbuf_size9_mem_0 mem_top_track_28 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( mux_2level_tapbuf_size10_mem_2_ccff_tail ) , @@ -50360,7 +53903,7 @@ sb_1__1__mux_2level_tapbuf_size6_0 mux_top_track_36 ( .sram ( mux_2level_tapbuf_size6_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_129 , SYNOPSYS_UNCONNECTED_130 , SYNOPSYS_UNCONNECTED_131 , SYNOPSYS_UNCONNECTED_132 } ) , - .out ( chany_top_out[18] ) , .p0 ( optlc_net_200 ) ) ; + .out ( chany_top_out[18] ) , .p0 ( optlc_net_175 ) ) ; sb_1__1__mux_2level_tapbuf_size6_1 mux_top_track_44 ( .in ( { top_left_grid_pin_48_[0] , chanx_left_out[17] , chanx_right_in[29] , chany_top_out[17] , chanx_left_in[2] , @@ -50368,7 +53911,7 @@ sb_1__1__mux_2level_tapbuf_size6_1 mux_top_track_44 ( .sram ( mux_2level_tapbuf_size6_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_133 , SYNOPSYS_UNCONNECTED_134 , SYNOPSYS_UNCONNECTED_135 , SYNOPSYS_UNCONNECTED_136 } ) , - .out ( chany_top_out[22] ) , .p0 ( optlc_net_203 ) ) ; + .out ( chany_top_out[22] ) , .p0 ( optlc_net_181 ) ) ; sb_1__1__mux_2level_tapbuf_size6_2 mux_top_track_52 ( .in ( { top_left_grid_pin_49_[0] , chanx_right_in[0] , chanx_left_out[19] , chany_top_out[19] , chanx_left_in[1] , @@ -50376,7 +53919,7 @@ sb_1__1__mux_2level_tapbuf_size6_2 mux_top_track_52 ( .sram ( mux_2level_tapbuf_size6_2_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_137 , SYNOPSYS_UNCONNECTED_138 , SYNOPSYS_UNCONNECTED_139 , SYNOPSYS_UNCONNECTED_140 } ) , - .out ( chany_top_out[26] ) , .p0 ( optlc_net_203 ) ) ; + .out ( chany_top_out[26] ) , .p0 ( optlc_net_181 ) ) ; sb_1__1__mux_2level_tapbuf_size6_3 mux_right_track_36 ( .in ( { chany_bottom_out[16] , chany_top_in[17] , right_bottom_grid_pin_39_[0] , chany_bottom_in[1] , @@ -50384,7 +53927,7 @@ sb_1__1__mux_2level_tapbuf_size6_3 mux_right_track_36 ( .sram ( mux_2level_tapbuf_size6_3_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_141 , SYNOPSYS_UNCONNECTED_142 , SYNOPSYS_UNCONNECTED_143 , SYNOPSYS_UNCONNECTED_144 } ) , - .out ( chanx_right_out[18] ) , .p0 ( optlc_net_198 ) ) ; + .out ( chanx_right_out[18] ) , .p0 ( optlc_net_178 ) ) ; sb_1__1__mux_2level_tapbuf_size6_4 mux_right_track_44 ( .in ( { chany_bottom_out[17] , chany_top_in[21] , right_bottom_grid_pin_40_[0] , chany_bottom_in[0] , @@ -50392,7 +53935,7 @@ sb_1__1__mux_2level_tapbuf_size6_4 mux_right_track_44 ( .sram ( mux_2level_tapbuf_size6_4_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_145 , SYNOPSYS_UNCONNECTED_146 , SYNOPSYS_UNCONNECTED_147 , SYNOPSYS_UNCONNECTED_148 } ) , - .out ( chanx_right_out[22] ) , .p0 ( optlc_net_203 ) ) ; + .out ( chanx_right_out[22] ) , .p0 ( optlc_net_175 ) ) ; sb_1__1__mux_2level_tapbuf_size6_5 mux_right_track_52 ( .in ( { chany_bottom_out[19] , chany_top_in[25] , right_bottom_grid_pin_41_[0] , chany_top_out[19] , @@ -50400,7 +53943,7 @@ sb_1__1__mux_2level_tapbuf_size6_5 mux_right_track_52 ( .sram ( mux_2level_tapbuf_size6_5_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_149 , SYNOPSYS_UNCONNECTED_150 , SYNOPSYS_UNCONNECTED_151 , SYNOPSYS_UNCONNECTED_152 } ) , - .out ( chanx_right_out[26] ) , .p0 ( optlc_net_200 ) ) ; + .out ( chanx_right_out[26] ) , .p0 ( optlc_net_178 ) ) ; sb_1__1__mux_2level_tapbuf_size6_6 mux_bottom_track_37 ( .in ( { chany_bottom_out[16] , chanx_right_in[1] , chanx_left_out[16] , bottom_left_grid_pin_47_[0] , chanx_right_out[16] , @@ -50408,7 +53951,7 @@ sb_1__1__mux_2level_tapbuf_size6_6 mux_bottom_track_37 ( .sram ( mux_2level_tapbuf_size6_6_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_153 , SYNOPSYS_UNCONNECTED_154 , SYNOPSYS_UNCONNECTED_155 , SYNOPSYS_UNCONNECTED_156 } ) , - .out ( chany_bottom_out[18] ) , .p0 ( optlc_net_198 ) ) ; + .out ( chany_bottom_out[18] ) , .p0 ( optlc_net_180 ) ) ; sb_1__1__mux_2level_tapbuf_size6_7 mux_bottom_track_45 ( .in ( { chany_bottom_out[17] , chanx_right_in[0] , chanx_left_out[17] , bottom_left_grid_pin_48_[0] , chanx_right_out[17] , @@ -50416,14 +53959,14 @@ sb_1__1__mux_2level_tapbuf_size6_7 mux_bottom_track_45 ( .sram ( mux_2level_tapbuf_size6_7_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_157 , SYNOPSYS_UNCONNECTED_158 , SYNOPSYS_UNCONNECTED_159 , SYNOPSYS_UNCONNECTED_160 } ) , - .out ( chany_bottom_out[22] ) , .p0 ( optlc_net_205 ) ) ; + .out ( chany_bottom_out[22] ) , .p0 ( optlc_net_176 ) ) ; sb_1__1__mux_2level_tapbuf_size6_8 mux_bottom_track_53 ( .in ( { chany_bottom_out[19] , chanx_left_out[19] , chanx_right_in[29] , bottom_left_grid_pin_49_[0] , chanx_left_in[0] , chanx_right_out[19] } ) , .sram ( mux_2level_tapbuf_size6_8_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_161 , SYNOPSYS_UNCONNECTED_162 , SYNOPSYS_UNCONNECTED_163 , SYNOPSYS_UNCONNECTED_164 } ) , - .out ( chany_bottom_out[26] ) , .p0 ( optlc_net_205 ) ) ; + .out ( chany_bottom_out[26] ) , .p0 ( optlc_net_176 ) ) ; sb_1__1__mux_2level_tapbuf_size6_9 mux_left_track_37 ( .in ( { chany_top_in[4] , chany_bottom_out[16] , chanx_left_out[16] , chany_top_out[16] , chany_bottom_in[17] , @@ -50431,7 +53974,7 @@ sb_1__1__mux_2level_tapbuf_size6_9 mux_left_track_37 ( .sram ( mux_2level_tapbuf_size6_9_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_165 , SYNOPSYS_UNCONNECTED_166 , SYNOPSYS_UNCONNECTED_167 , SYNOPSYS_UNCONNECTED_168 } ) , - .out ( chanx_left_out[18] ) , .p0 ( optlc_net_200 ) ) ; + .out ( chanx_left_out[18] ) , .p0 ( optlc_net_181 ) ) ; sb_1__1__mux_2level_tapbuf_size6_10 mux_left_track_45 ( .in ( { chany_top_in[2] , chany_bottom_out[17] , chanx_left_out[17] , chany_top_out[17] , chany_bottom_in[21] , @@ -50439,7 +53982,7 @@ sb_1__1__mux_2level_tapbuf_size6_10 mux_left_track_45 ( .sram ( mux_2level_tapbuf_size6_10_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_169 , SYNOPSYS_UNCONNECTED_170 , SYNOPSYS_UNCONNECTED_171 , SYNOPSYS_UNCONNECTED_172 } ) , - .out ( chanx_left_out[22] ) , .p0 ( optlc_net_197 ) ) ; + .out ( chanx_left_out[22] ) , .p0 ( optlc_net_174 ) ) ; sb_1__1__mux_2level_tapbuf_size6 mux_left_track_53 ( .in ( { chany_top_in[1] , chany_bottom_out[19] , chanx_left_out[19] , chany_top_out[19] , chany_bottom_in[25] , @@ -50447,7 +53990,7 @@ sb_1__1__mux_2level_tapbuf_size6 mux_left_track_53 ( .sram ( mux_2level_tapbuf_size6_11_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_173 , SYNOPSYS_UNCONNECTED_174 , SYNOPSYS_UNCONNECTED_175 , SYNOPSYS_UNCONNECTED_176 } ) , - .out ( chanx_left_out[26] ) , .p0 ( optlc_net_197 ) ) ; + .out ( chanx_left_out[26] ) , .p0 ( optlc_net_174 ) ) ; sb_1__1__mux_2level_tapbuf_size6_mem_0 mem_top_track_36 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( mux_2level_tapbuf_size9_mem_0_ccff_tail ) , @@ -50511,14 +54054,14 @@ sky130_fd_sc_hd__buf_4 Test_en_N_FTB01 ( .A ( Test_en_S_in ) , .X ( Test_en_N_out ) ) ; sky130_fd_sc_hd__buf_8 pReset_FTB00 ( .A ( pReset_E_in ) , .X ( pReset[0] ) ) ; sky130_fd_sc_hd__buf_1 pReset_N_FTB01 ( .A ( pReset_E_in ) , - .X ( aps_rename_523_ ) ) ; -sky130_fd_sc_hd__bufbuf_16 pReset_W_FTB01 ( .A ( pReset_E_in ) , - .X ( pReset_W_out ) ) ; + .X ( aps_rename_514_ ) ) ; +sky130_fd_sc_hd__buf_1 pReset_W_FTB01 ( .A ( pReset_E_in ) , + .X ( aps_rename_515_ ) ) ; sky130_fd_sc_hd__buf_4 pReset_E_FTB01 ( .A ( pReset_E_in ) , .X ( pReset_E_out ) ) ; sky130_fd_sc_hd__buf_4 Reset_N_FTB01 ( .A ( Reset_S_in ) , .X ( Reset_N_out ) ) ; -sky130_fd_sc_hd__buf_16 prog_clk_0_FTB00 ( .A ( prog_clk_0_N_in ) , +sky130_fd_sc_hd__buf_6 prog_clk_0_FTB00 ( .A ( prog_clk_0_N_in ) , .X ( prog_clk[0] ) ) ; sky130_fd_sc_hd__buf_8 FTB_69__68 ( .A ( chany_top_in[3] ) , .X ( chany_bottom_out[4] ) ) ; @@ -50672,31 +54215,30 @@ sky130_fd_sc_hd__buf_8 FTB_143__142 ( .A ( chanx_left_in[27] ) , .X ( chanx_right_out[28] ) ) ; sky130_fd_sc_hd__buf_8 FTB_144__143 ( .A ( chanx_left_in[28] ) , .X ( chanx_right_out[29] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_191 ( .A ( BUF_net_192 ) , .Y ( pReset_N_out ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_192 ( .A ( aps_rename_523_ ) , - .Y ( BUF_net_192 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_199 ( .LO ( SYNOPSYS_UNCONNECTED_177 ) , - .HI ( optlc_net_197 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_201 ( .LO ( SYNOPSYS_UNCONNECTED_178 ) , - .HI ( optlc_net_198 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_204 ( .LO ( SYNOPSYS_UNCONNECTED_179 ) , - .HI ( optlc_net_199 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_206 ( .LO ( SYNOPSYS_UNCONNECTED_180 ) , - .HI ( optlc_net_200 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_208 ( .LO ( SYNOPSYS_UNCONNECTED_181 ) , - .HI ( optlc_net_201 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_210 ( .LO ( SYNOPSYS_UNCONNECTED_182 ) , - .HI ( optlc_net_202 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_212 ( .LO ( SYNOPSYS_UNCONNECTED_183 ) , - .HI ( optlc_net_203 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_214 ( .LO ( SYNOPSYS_UNCONNECTED_184 ) , - .HI ( optlc_net_204 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_216 ( .LO ( SYNOPSYS_UNCONNECTED_185 ) , - .HI ( optlc_net_205 ) ) ; -sky130_fd_sc_hd__buf_6 ZBUF_6_f_inst_217 ( .A ( aps_rename_522_ ) , - .X ( chanx_right_out[3] ) ) ; -sky130_fd_sc_hd__buf_6 ZBUF_6_f_inst_218 ( .A ( aps_rename_521_ ) , - .X ( chanx_right_out[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_166 ( .A ( BUF_net_167 ) , .Y ( pReset_N_out ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_167 ( .A ( aps_rename_514_ ) , + .Y ( BUF_net_167 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_168 ( .A ( BUF_net_169 ) , .Y ( pReset_W_out ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_169 ( .A ( aps_rename_515_ ) , + .Y ( BUF_net_169 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_176 ( .LO ( SYNOPSYS_UNCONNECTED_177 ) , + .HI ( optlc_net_174 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_178 ( .LO ( SYNOPSYS_UNCONNECTED_178 ) , + .HI ( optlc_net_175 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_180 ( .LO ( SYNOPSYS_UNCONNECTED_179 ) , + .HI ( optlc_net_176 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_182 ( .LO ( SYNOPSYS_UNCONNECTED_180 ) , + .HI ( optlc_net_177 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_184 ( .LO ( SYNOPSYS_UNCONNECTED_181 ) , + .HI ( optlc_net_178 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_186 ( .LO ( SYNOPSYS_UNCONNECTED_182 ) , + .HI ( optlc_net_179 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_188 ( .LO ( SYNOPSYS_UNCONNECTED_183 ) , + .HI ( optlc_net_180 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_190 ( .LO ( SYNOPSYS_UNCONNECTED_184 ) , + .HI ( optlc_net_181 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_192 ( .LO ( SYNOPSYS_UNCONNECTED_185 ) , + .HI ( optlc_net_182 ) ) ; endmodule @@ -50771,12 +54313,18 @@ input [0:3] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -50787,12 +54335,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -50803,12 +54357,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -50874,7 +54434,7 @@ wire [0:0] mux_2level_tapbuf_basis_input4_mem4_2_out ; sb_1__0__const1 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__bufbuf_16 sky130_fd_sc_hd__buf_4_0_ ( +sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_4_0_ ( .A ( mux_2level_tapbuf_basis_input4_mem4_2_out[0] ) , .X ( out[0] ) ) ; sb_1__0__local_encoder2to4_6 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , .data ( local_encoder2to4_0_data ) , @@ -50908,12 +54468,18 @@ input [0:3] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -50924,12 +54490,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -50940,12 +54512,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -51012,7 +54590,8 @@ wire [0:0] mux_2level_tapbuf_basis_input4_mem4_2_out ; sb_1__0__const1_46 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_4_0_ ( - .A ( mux_2level_tapbuf_basis_input4_mem4_2_out[0] ) , .X ( out[0] ) ) ; + .A ( mux_2level_tapbuf_basis_input4_mem4_2_out[0] ) , + .X ( aps_rename_505_ ) ) ; sb_1__0__local_encoder2to4_4 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , .data ( local_encoder2to4_0_data ) , .data_inv ( local_encoder2to4_0_data_inv ) ) ; @@ -51034,6 +54613,9 @@ sb_1__0__mux_2level_tapbuf_basis_input4_mem4_8 mux_l2_in_0_ ( .mem ( local_encoder2to4_1_data ) , .mem_inv ( local_encoder2to4_1_data_inv ) , .out ( mux_2level_tapbuf_basis_input4_mem4_2_out ) , .p0 ( p0 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_213 ( .A ( BUF_net_214 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_214 ( .A ( aps_rename_505_ ) , + .Y ( BUF_net_214 ) ) ; endmodule @@ -51045,12 +54627,18 @@ input [0:3] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -51061,12 +54649,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -51077,12 +54671,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -51148,7 +54748,7 @@ wire [0:0] mux_2level_tapbuf_basis_input4_mem4_2_out ; sb_1__0__const1_45 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__bufbuf_16 sky130_fd_sc_hd__buf_4_0_ ( +sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_4_0_ ( .A ( mux_2level_tapbuf_basis_input4_mem4_2_out[0] ) , .X ( out[0] ) ) ; sb_1__0__local_encoder2to4_2 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , .data ( local_encoder2to4_0_data ) , @@ -51202,9 +54802,13 @@ input [0:1] mem ; input [0:1] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -51216,12 +54820,18 @@ input [0:3] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -51232,12 +54842,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -51248,12 +54864,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -51418,10 +55040,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -51433,10 +55059,14 @@ input [0:2] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -51447,10 +55077,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -51461,10 +55095,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -51561,10 +55199,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -51576,10 +55218,14 @@ input [0:2] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -51590,10 +55236,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -51604,10 +55254,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -51705,10 +55359,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -51720,10 +55378,14 @@ input [0:2] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -51734,10 +55396,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -51748,10 +55414,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -51810,8 +55480,6 @@ wire [0:0] mux_2level_tapbuf_basis_input3_mem3_3_out ; sb_1__0__const1_41 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( mux_2level_tapbuf_basis_input3_mem3_3_out[0] ) , .X ( out[0] ) ) ; sb_1__0__local_encoder2to3_50 local_encoder2to3_0_ ( .addr ( sram[0:1] ) , .data ( local_encoder2to3_0_data ) , .data_inv ( local_encoder2to3_0_data_inv ) ) ; @@ -51838,6 +55506,9 @@ sb_1__0__mux_2level_tapbuf_basis_input3_mem3_66 mux_l2_in_0_ ( .mem ( local_encoder2to3_1_data ) , .mem_inv ( local_encoder2to3_1_data_inv ) , .out ( mux_2level_tapbuf_basis_input3_mem3_3_out ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_211 ( .A ( BUF_net_212 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_212 ( + .A ( mux_2level_tapbuf_basis_input3_mem3_3_out[0] ) , .Y ( BUF_net_212 ) ) ; endmodule @@ -52059,8 +55730,6 @@ wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ; sb_1__0__const1_40 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) ) ; sb_1__0__mux_2level_tapbuf_basis_input2_mem1_35 mux_l1_in_0_ ( .in ( in ) , .mem ( sram[0] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_2 } ) , @@ -52071,6 +55740,8 @@ sb_1__0__mux_2level_tapbuf_basis_input2_mem1 mux_l2_in_0_ ( .mem ( sram[1] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_4 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_192 ( + .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) ) ; endmodule @@ -52082,7 +55753,7 @@ input [0:0] mem_inv ; output [0:0] out ; input p0 ; -sky130_fd_sc_hd__mux2_2 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , +sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ; endmodule @@ -52126,8 +55797,9 @@ sb_1__0__mux_2level_tapbuf_basis_input2_mem1_34 mux_l2_in_0_ ( .mem ( sram[1] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_4 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_192 ( - .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_190 ( .A ( BUF_net_191 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_191 ( + .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_191 ) ) ; endmodule @@ -52183,9 +55855,9 @@ sb_1__0__mux_2level_tapbuf_basis_input2_mem1_32 mux_l2_in_0_ ( .mem ( sram[1] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_4 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_190 ( .A ( BUF_net_191 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_191 ( - .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_191 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_188 ( .A ( BUF_net_189 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_189 ( + .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_189 ) ) ; endmodule @@ -52241,9 +55913,9 @@ sb_1__0__mux_2level_tapbuf_basis_input2_mem1_30 mux_l2_in_0_ ( .mem ( sram[1] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_4 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_188 ( .A ( BUF_net_189 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_189 ( - .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_189 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_186 ( .A ( BUF_net_187 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_187 ( + .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_187 ) ) ; endmodule @@ -52299,9 +55971,9 @@ sb_1__0__mux_2level_tapbuf_basis_input2_mem1_28 mux_l2_in_0_ ( .mem ( sram[1] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_4 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_186 ( .A ( BUF_net_187 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_187 ( - .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_187 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_184 ( .A ( BUF_net_185 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_185 ( + .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_185 ) ) ; endmodule @@ -52347,8 +56019,6 @@ wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ; sb_1__0__const1_35 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) ) ; sb_1__0__mux_2level_tapbuf_basis_input2_mem1_25 mux_l1_in_0_ ( .in ( in ) , .mem ( sram[0] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_2 } ) , @@ -52359,6 +56029,9 @@ sb_1__0__mux_2level_tapbuf_basis_input2_mem1_26 mux_l2_in_0_ ( .mem ( sram[1] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_4 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_182 ( .A ( BUF_net_183 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_183 ( + .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_183 ) ) ; endmodule @@ -52414,9 +56087,9 @@ sb_1__0__mux_2level_tapbuf_basis_input2_mem1_24 mux_l2_in_0_ ( .mem ( sram[1] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_4 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_184 ( .A ( BUF_net_185 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_185 ( - .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_185 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_180 ( .A ( BUF_net_181 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_181 ( + .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_181 ) ) ; endmodule @@ -52485,7 +56158,7 @@ input [0:0] mem_inv ; output [0:0] out ; input p0 ; -sky130_fd_sc_hd__mux2_2 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , +sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ; endmodule @@ -52519,6 +56192,8 @@ wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ; sb_1__0__const1_32 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) ) ; sb_1__0__mux_2level_tapbuf_basis_input2_mem1_19 mux_l1_in_0_ ( .in ( in ) , .mem ( sram[0] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_2 } ) , @@ -52529,8 +56204,6 @@ sb_1__0__mux_2level_tapbuf_basis_input2_mem1_20 mux_l2_in_0_ ( .mem ( sram[1] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_4 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_183 ( - .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) ) ; endmodule @@ -52643,9 +56316,9 @@ sb_1__0__mux_2level_tapbuf_basis_input2_mem1_16 mux_l2_in_0_ ( .mem ( sram[1] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_4 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_181 ( .A ( BUF_net_182 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_182 ( - .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_182 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_178 ( .A ( BUF_net_179 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_179 ( + .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_179 ) ) ; endmodule @@ -52799,9 +56472,9 @@ sb_1__0__mux_2level_tapbuf_basis_input2_mem1_14 mux_l2_in_0_ ( .mem ( sram[1] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_5 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_2_out ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_179 ( .A ( BUF_net_180 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_180 ( - .A ( mux_2level_tapbuf_basis_input2_mem1_2_out[0] ) , .Y ( BUF_net_180 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_176 ( .A ( BUF_net_177 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_177 ( + .A ( mux_2level_tapbuf_basis_input2_mem1_2_out[0] ) , .Y ( BUF_net_177 ) ) ; endmodule @@ -52812,7 +56485,7 @@ input [0:0] mem ; input [0:0] mem_inv ; output [0:0] out ; -sky130_fd_sc_hd__mux2_2 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) , +sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ; endmodule @@ -52860,8 +56533,6 @@ wire [0:0] mux_2level_tapbuf_basis_input2_mem1_2_out ; sb_1__0__const1_28 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( mux_2level_tapbuf_basis_input2_mem1_2_out[0] ) , .X ( out[0] ) ) ; sb_1__0__mux_2level_tapbuf_basis_input2_mem1_9 mux_l1_in_0_ ( .in ( in[0:1] ) , .mem ( sram[0] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_2 } ) , @@ -52877,6 +56548,9 @@ sb_1__0__mux_2level_tapbuf_basis_input2_mem1_11 mux_l2_in_0_ ( .mem ( sram[1] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_5 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_2_out ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_174 ( .A ( BUF_net_175 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_175 ( + .A ( mux_2level_tapbuf_basis_input2_mem1_2_out[0] ) , .Y ( BUF_net_175 ) ) ; endmodule @@ -52950,9 +56624,9 @@ sb_1__0__mux_2level_tapbuf_basis_input2_mem1_8 mux_l2_in_0_ ( .mem ( sram[1] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_5 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_2_out ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_177 ( .A ( BUF_net_178 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_178 ( - .A ( mux_2level_tapbuf_basis_input2_mem1_2_out[0] ) , .Y ( BUF_net_178 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_172 ( .A ( BUF_net_173 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_173 ( + .A ( mux_2level_tapbuf_basis_input2_mem1_2_out[0] ) , .Y ( BUF_net_173 ) ) ; endmodule @@ -53026,9 +56700,9 @@ sb_1__0__mux_2level_tapbuf_basis_input2_mem1_5 mux_l2_in_0_ ( .mem ( sram[1] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_5 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_2_out ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_175 ( .A ( BUF_net_176 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_176 ( - .A ( mux_2level_tapbuf_basis_input2_mem1_2_out[0] ) , .Y ( BUF_net_176 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_170 ( .A ( BUF_net_171 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_171 ( + .A ( mux_2level_tapbuf_basis_input2_mem1_2_out[0] ) , .Y ( BUF_net_171 ) ) ; endmodule @@ -53087,6 +56761,8 @@ wire [0:0] mux_2level_tapbuf_basis_input2_mem1_2_out ; sb_1__0__const1_25 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( mux_2level_tapbuf_basis_input2_mem1_2_out[0] ) , .X ( out[0] ) ) ; sb_1__0__mux_2level_tapbuf_basis_input2_mem1_0 mux_l1_in_0_ ( .in ( in[0:1] ) , .mem ( sram[0] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_2 } ) , @@ -53102,9 +56778,6 @@ sb_1__0__mux_2level_tapbuf_basis_input2_mem1_2 mux_l2_in_0_ ( .mem ( sram[1] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_5 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_2_out ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_173 ( .A ( BUF_net_174 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_174 ( - .A ( mux_2level_tapbuf_basis_input2_mem1_2_out[0] ) , .Y ( BUF_net_174 ) ) ; endmodule @@ -53236,10 +56909,14 @@ input [0:2] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -53250,10 +56927,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -53326,8 +57007,9 @@ sb_1__0__mux_2level_tapbuf_basis_input3_mem3_62 mux_l2_in_0_ ( .mem ( local_encoder2to3_1_data ) , .mem_inv ( local_encoder2to3_1_data_inv ) , .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_172 ( - .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_209 ( .A ( BUF_net_210 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_210 ( + .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_210 ) ) ; endmodule @@ -53339,10 +57021,14 @@ input [0:2] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -53353,10 +57039,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -53429,8 +57119,9 @@ sb_1__0__mux_2level_tapbuf_basis_input3_mem3_60 mux_l2_in_0_ ( .mem ( local_encoder2to3_1_data ) , .mem_inv ( local_encoder2to3_1_data_inv ) , .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_171 ( - .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_168 ( .A ( BUF_net_169 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_169 ( + .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_169 ) ) ; endmodule @@ -53442,10 +57133,14 @@ input [0:2] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -53456,10 +57151,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -53532,9 +57231,8 @@ sb_1__0__mux_2level_tapbuf_basis_input3_mem3_58 mux_l2_in_0_ ( .mem ( local_encoder2to3_1_data ) , .mem_inv ( local_encoder2to3_1_data_inv ) , .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_169 ( .A ( BUF_net_170 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_170 ( - .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_170 ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_167 ( + .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .X ( out[0] ) ) ; endmodule @@ -53546,10 +57244,14 @@ input [0:2] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -53560,10 +57262,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -53636,9 +57342,9 @@ sb_1__0__mux_2level_tapbuf_basis_input3_mem3_56 mux_l2_in_0_ ( .mem ( local_encoder2to3_1_data ) , .mem_inv ( local_encoder2to3_1_data_inv ) , .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_167 ( .A ( BUF_net_168 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_168 ( - .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_168 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_165 ( .A ( BUF_net_166 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_166 ( + .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_166 ) ) ; endmodule @@ -53650,10 +57356,14 @@ input [0:2] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -53664,10 +57374,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -53740,9 +57454,8 @@ sb_1__0__mux_2level_tapbuf_basis_input3_mem3_54 mux_l2_in_0_ ( .mem ( local_encoder2to3_1_data ) , .mem_inv ( local_encoder2to3_1_data_inv ) , .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_165 ( .A ( BUF_net_166 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_166 ( - .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_166 ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_164 ( + .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .X ( out[0] ) ) ; endmodule @@ -53754,10 +57467,14 @@ input [0:2] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -53768,10 +57485,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -53828,6 +57549,8 @@ wire [0:0] mux_2level_tapbuf_basis_input3_mem3_1_out ; sb_1__0__const1_19 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .X ( out[0] ) ) ; sb_1__0__local_encoder2to3_38 local_encoder2to3_0_ ( .addr ( sram[0:1] ) , .data ( local_encoder2to3_0_data ) , .data_inv ( local_encoder2to3_0_data_inv ) ) ; @@ -53844,9 +57567,6 @@ sb_1__0__mux_2level_tapbuf_basis_input3_mem3_52 mux_l2_in_0_ ( .mem ( local_encoder2to3_1_data ) , .mem_inv ( local_encoder2to3_1_data_inv ) , .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_163 ( .A ( BUF_net_164 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_164 ( - .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_164 ) ) ; endmodule @@ -53977,9 +57697,13 @@ input [0:1] mem ; input [0:1] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -53991,10 +57715,14 @@ input [0:2] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -54005,10 +57733,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -54087,9 +57819,9 @@ sb_1__0__mux_2level_tapbuf_basis_input2_mem2_15 mux_l1_in_1_ ( .in ( in[3:4] ) , .mem ( local_encoder2to3_0_data[0:1] ) , .mem_inv ( local_encoder2to3_0_data_inv[0:1] ) , .out ( mux_2level_tapbuf_basis_input2_mem2_0_out ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_161 ( .A ( BUF_net_162 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_162 ( - .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_162 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_162 ( .A ( BUF_net_163 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_163 ( + .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_163 ) ) ; endmodule @@ -54100,9 +57832,13 @@ input [0:1] mem ; input [0:1] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -54114,10 +57850,14 @@ input [0:2] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -54128,10 +57868,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -54210,9 +57954,9 @@ sb_1__0__mux_2level_tapbuf_basis_input2_mem2_14 mux_l1_in_1_ ( .in ( in[3:4] ) , .mem ( local_encoder2to3_0_data[0:1] ) , .mem_inv ( local_encoder2to3_0_data_inv[0:1] ) , .out ( mux_2level_tapbuf_basis_input2_mem2_0_out ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_159 ( .A ( BUF_net_160 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_160 ( - .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_160 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_160 ( .A ( BUF_net_161 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_161 ( + .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_161 ) ) ; endmodule @@ -54223,9 +57967,13 @@ input [0:1] mem ; input [0:1] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -54237,10 +57985,14 @@ input [0:2] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -54251,10 +58003,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -54333,9 +58089,9 @@ sb_1__0__mux_2level_tapbuf_basis_input2_mem2_13 mux_l1_in_1_ ( .in ( in[3:4] ) , .mem ( local_encoder2to3_0_data[0:1] ) , .mem_inv ( local_encoder2to3_0_data_inv[0:1] ) , .out ( mux_2level_tapbuf_basis_input2_mem2_0_out ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_157 ( .A ( BUF_net_158 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_158 ( - .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_158 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_158 ( .A ( BUF_net_159 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_159 ( + .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_159 ) ) ; endmodule @@ -54346,9 +58102,13 @@ input [0:1] mem ; input [0:1] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -54360,10 +58120,14 @@ input [0:2] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -54374,10 +58138,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -54456,9 +58224,9 @@ sb_1__0__mux_2level_tapbuf_basis_input2_mem2_12 mux_l1_in_1_ ( .in ( in[3:4] ) , .mem ( local_encoder2to3_0_data[0:1] ) , .mem_inv ( local_encoder2to3_0_data_inv[0:1] ) , .out ( mux_2level_tapbuf_basis_input2_mem2_0_out ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_205 ( .A ( BUF_net_206 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_206 ( - .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_206 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_156 ( .A ( BUF_net_157 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_157 ( + .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_157 ) ) ; endmodule @@ -54469,9 +58237,13 @@ input [0:1] mem ; input [0:1] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -54483,10 +58255,14 @@ input [0:2] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -54497,10 +58273,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -54558,6 +58338,8 @@ wire [0:0] mux_2level_tapbuf_basis_input3_mem3_1_out ; sb_1__0__const1_14 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .X ( out[0] ) ) ; sb_1__0__local_encoder2to3_28 local_encoder2to3_0_ ( .addr ( sram[0:1] ) , .data ( local_encoder2to3_0_data ) , .data_inv ( local_encoder2to3_0_data_inv ) ) ; @@ -54579,9 +58361,6 @@ sb_1__0__mux_2level_tapbuf_basis_input2_mem2_11 mux_l1_in_1_ ( .in ( in[3:4] ) , .mem ( local_encoder2to3_0_data[0:1] ) , .mem_inv ( local_encoder2to3_0_data_inv[0:1] ) , .out ( mux_2level_tapbuf_basis_input2_mem2_0_out ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_155 ( .A ( BUF_net_156 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_156 ( - .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_156 ) ) ; endmodule @@ -54592,9 +58371,13 @@ input [0:1] mem ; input [0:1] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -54606,10 +58389,14 @@ input [0:2] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -54620,10 +58407,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -54702,9 +58493,8 @@ sb_1__0__mux_2level_tapbuf_basis_input2_mem2_10 mux_l1_in_1_ ( .in ( in[3:4] ) , .mem ( local_encoder2to3_0_data[0:1] ) , .mem_inv ( local_encoder2to3_0_data_inv[0:1] ) , .out ( mux_2level_tapbuf_basis_input2_mem2_0_out ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_153 ( .A ( BUF_net_154 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_154 ( - .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_154 ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_155 ( + .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .X ( out[0] ) ) ; endmodule @@ -54776,10 +58566,14 @@ input [0:2] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -54790,10 +58584,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -54804,10 +58602,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -54899,10 +58701,14 @@ input [0:2] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -54913,10 +58719,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -54927,10 +58737,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -54988,6 +58802,8 @@ wire [0:0] mux_2level_tapbuf_basis_input3_mem3_2_out ; sb_1__0__const1_11 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( mux_2level_tapbuf_basis_input3_mem3_2_out[0] ) , .X ( out[0] ) ) ; sb_1__0__local_encoder2to3_22 local_encoder2to3_0_ ( .addr ( sram[0:1] ) , .data ( local_encoder2to3_0_data ) , .data_inv ( local_encoder2to3_0_data_inv ) ) ; @@ -55009,9 +58825,6 @@ sb_1__0__mux_2level_tapbuf_basis_input3_mem3_35 mux_l2_in_0_ ( .mem ( local_encoder2to3_1_data ) , .mem_inv ( local_encoder2to3_1_data_inv ) , .out ( mux_2level_tapbuf_basis_input3_mem3_2_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_151 ( .A ( BUF_net_152 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_152 ( - .A ( mux_2level_tapbuf_basis_input3_mem3_2_out[0] ) , .Y ( BUF_net_152 ) ) ; endmodule @@ -55023,10 +58836,14 @@ input [0:2] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -55037,10 +58854,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -55051,10 +58872,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -55133,9 +58958,9 @@ sb_1__0__mux_2level_tapbuf_basis_input3_mem3_32 mux_l2_in_0_ ( .mem ( local_encoder2to3_1_data ) , .mem_inv ( local_encoder2to3_1_data_inv ) , .out ( mux_2level_tapbuf_basis_input3_mem3_2_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_149 ( .A ( BUF_net_150 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_150 ( - .A ( mux_2level_tapbuf_basis_input3_mem3_2_out[0] ) , .Y ( BUF_net_150 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_153 ( .A ( BUF_net_154 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_154 ( + .A ( mux_2level_tapbuf_basis_input3_mem3_2_out[0] ) , .Y ( BUF_net_154 ) ) ; endmodule @@ -55327,7 +59152,7 @@ input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ropt_net_249 ) , +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ropt_net_255 ) , .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; @@ -55336,34 +59161,32 @@ sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__buf_1 FTB_21__20 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1414 ( .A ( ropt_net_250 ) , - .X ( copt_net_213 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1415 ( .A ( copt_net_213 ) , - .X ( copt_net_214 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1416 ( .A ( copt_net_214 ) , - .X ( copt_net_215 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1417 ( .A ( copt_net_218 ) , - .X ( copt_net_216 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1418 ( .A ( ccff_head[0] ) , - .X ( copt_net_217 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1419 ( .A ( copt_net_215 ) , - .X ( copt_net_218 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1444 ( .A ( copt_net_216 ) , - .X ( ropt_net_243 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1445 ( .A ( ropt_net_243 ) , - .X ( ropt_net_244 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1446 ( .A ( ropt_net_244 ) , - .X ( ropt_net_245 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1447 ( .A ( ropt_net_245 ) , - .X ( ropt_net_246 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1448 ( .A ( ropt_net_246 ) , - .X ( ropt_net_247 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1449 ( .A ( ropt_net_247 ) , - .X ( ropt_net_248 ) ) ; -sky130_fd_sc_hd__buf_4 ropt_h_inst_1450 ( .A ( ropt_net_248 ) , - .X ( ropt_net_249 ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 ropt_h_inst_1451 ( .A ( copt_net_217 ) , - .X ( ropt_net_250 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1435 ( .A ( ropt_net_258 ) , + .X ( copt_net_226 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1436 ( .A ( ccff_head[0] ) , + .X ( copt_net_227 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1437 ( .A ( copt_net_226 ) , + .X ( copt_net_228 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1438 ( .A ( copt_net_227 ) , + .X ( copt_net_229 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1439 ( .A ( copt_net_228 ) , + .X ( copt_net_230 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1440 ( .A ( copt_net_229 ) , + .X ( copt_net_231 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1461 ( .A ( ropt_net_254 ) , + .X ( ropt_net_252 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1462 ( .A ( ropt_net_252 ) , + .X ( ropt_net_253 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1463 ( .A ( copt_net_230 ) , + .X ( ropt_net_254 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1464 ( .A ( ropt_net_257 ) , + .X ( ropt_net_255 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1465 ( .A ( ropt_net_253 ) , + .X ( ropt_net_256 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1466 ( .A ( ropt_net_256 ) , + .X ( ropt_net_257 ) ) ; +sky130_fd_sc_hd__buf_1 ropt_h_inst_1467 ( .A ( copt_net_231 ) , + .X ( ropt_net_258 ) ) ; endmodule @@ -55375,9 +59198,13 @@ input [0:1] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( p0 ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -55388,10 +59215,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -55402,10 +59233,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -55416,10 +59251,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -55478,8 +59317,6 @@ wire [0:0] mux_2level_tapbuf_basis_input3_mem3_2_out ; sb_1__0__const1_9 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( mux_2level_tapbuf_basis_input3_mem3_2_out[0] ) , .X ( out[0] ) ) ; sb_1__0__local_encoder2to3_18 local_encoder2to3_0_ ( .addr ( sram[0:1] ) , .data ( local_encoder2to3_0_data ) , .data_inv ( local_encoder2to3_0_data_inv ) ) ; @@ -55506,6 +59343,9 @@ sb_1__0__mux_2level_tapbuf_basis_input2_mem2_9 mux_l1_in_2_ ( .mem ( local_encoder2to3_0_data[0:1] ) , .mem_inv ( local_encoder2to3_0_data_inv[0:1] ) , .out ( mux_2level_tapbuf_basis_input2_mem2_0_out ) , .p0 ( p0 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_151 ( .A ( BUF_net_152 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_152 ( + .A ( mux_2level_tapbuf_basis_input3_mem3_2_out[0] ) , .Y ( BUF_net_152 ) ) ; endmodule @@ -55517,9 +59357,13 @@ input [0:1] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( p0 ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -55530,10 +59374,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -55544,10 +59392,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -55558,10 +59410,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -55659,9 +59515,13 @@ input [0:1] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( p0 ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -55672,10 +59532,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -55686,10 +59550,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -55700,10 +59568,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -55762,8 +59634,6 @@ wire [0:0] mux_2level_tapbuf_basis_input3_mem3_2_out ; sb_1__0__const1_7 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( mux_2level_tapbuf_basis_input3_mem3_2_out[0] ) , .X ( out[0] ) ) ; sb_1__0__local_encoder2to3_14 local_encoder2to3_0_ ( .addr ( sram[0:1] ) , .data ( local_encoder2to3_0_data ) , .data_inv ( local_encoder2to3_0_data_inv ) ) ; @@ -55790,6 +59660,9 @@ sb_1__0__mux_2level_tapbuf_basis_input2_mem2_7 mux_l1_in_2_ ( .mem ( local_encoder2to3_0_data[0:1] ) , .mem_inv ( local_encoder2to3_0_data_inv[0:1] ) , .out ( mux_2level_tapbuf_basis_input2_mem2_0_out ) , .p0 ( p0 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_149 ( .A ( BUF_net_150 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_150 ( + .A ( mux_2level_tapbuf_basis_input3_mem3_2_out[0] ) , .Y ( BUF_net_150 ) ) ; endmodule @@ -55801,9 +59674,13 @@ input [0:1] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( p0 ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -55814,10 +59691,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -55828,10 +59709,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -55842,10 +59727,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -55904,8 +59793,6 @@ wire [0:0] mux_2level_tapbuf_basis_input3_mem3_2_out ; sb_1__0__const1_6 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( mux_2level_tapbuf_basis_input3_mem3_2_out[0] ) , .X ( out[0] ) ) ; sb_1__0__local_encoder2to3_12 local_encoder2to3_0_ ( .addr ( sram[0:1] ) , .data ( local_encoder2to3_0_data ) , .data_inv ( local_encoder2to3_0_data_inv ) ) ; @@ -55932,6 +59819,9 @@ sb_1__0__mux_2level_tapbuf_basis_input2_mem2_6 mux_l1_in_2_ ( .mem ( local_encoder2to3_0_data[0:1] ) , .mem_inv ( local_encoder2to3_0_data_inv[0:1] ) , .out ( mux_2level_tapbuf_basis_input2_mem2_0_out ) , .p0 ( p0 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_147 ( .A ( BUF_net_148 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_148 ( + .A ( mux_2level_tapbuf_basis_input3_mem3_2_out[0] ) , .Y ( BUF_net_148 ) ) ; endmodule @@ -55943,9 +59833,13 @@ input [0:1] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( p0 ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -55956,10 +59850,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -55970,10 +59868,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -55984,10 +59886,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -56046,8 +59952,6 @@ wire [0:0] mux_2level_tapbuf_basis_input3_mem3_2_out ; sb_1__0__const1_5 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( mux_2level_tapbuf_basis_input3_mem3_2_out[0] ) , .X ( out[0] ) ) ; sb_1__0__local_encoder2to3_10 local_encoder2to3_0_ ( .addr ( sram[0:1] ) , .data ( local_encoder2to3_0_data ) , .data_inv ( local_encoder2to3_0_data_inv ) ) ; @@ -56074,6 +59978,9 @@ sb_1__0__mux_2level_tapbuf_basis_input2_mem2_5 mux_l1_in_2_ ( .mem ( local_encoder2to3_0_data[0:1] ) , .mem_inv ( local_encoder2to3_0_data_inv[0:1] ) , .out ( mux_2level_tapbuf_basis_input2_mem2_0_out ) , .p0 ( p0 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_207 ( .A ( BUF_net_208 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_208 ( + .A ( mux_2level_tapbuf_basis_input3_mem3_2_out[0] ) , .Y ( BUF_net_208 ) ) ; endmodule @@ -56085,9 +59992,13 @@ input [0:1] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( p0 ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -56098,10 +60009,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -56112,10 +60027,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -56126,10 +60045,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -56188,6 +60111,8 @@ wire [0:0] mux_2level_tapbuf_basis_input3_mem3_2_out ; sb_1__0__const1_4 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( mux_2level_tapbuf_basis_input3_mem3_2_out[0] ) , .X ( out[0] ) ) ; sb_1__0__local_encoder2to3_8 local_encoder2to3_0_ ( .addr ( sram[0:1] ) , .data ( local_encoder2to3_0_data ) , .data_inv ( local_encoder2to3_0_data_inv ) ) ; @@ -56214,9 +60139,6 @@ sb_1__0__mux_2level_tapbuf_basis_input2_mem2_4 mux_l1_in_2_ ( .mem ( local_encoder2to3_0_data[0:1] ) , .mem_inv ( local_encoder2to3_0_data_inv[0:1] ) , .out ( mux_2level_tapbuf_basis_input2_mem2_0_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_147 ( .A ( BUF_net_148 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_148 ( - .A ( mux_2level_tapbuf_basis_input3_mem3_2_out[0] ) , .Y ( BUF_net_148 ) ) ; endmodule @@ -56228,9 +60150,13 @@ input [0:1] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( p0 ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -56241,10 +60167,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -56255,10 +60185,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -56269,10 +60203,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -56331,8 +60269,6 @@ wire [0:0] mux_2level_tapbuf_basis_input3_mem3_2_out ; sb_1__0__const1_3 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( mux_2level_tapbuf_basis_input3_mem3_2_out[0] ) , .X ( out[0] ) ) ; sb_1__0__local_encoder2to3_6 local_encoder2to3_0_ ( .addr ( sram[0:1] ) , .data ( local_encoder2to3_0_data ) , .data_inv ( local_encoder2to3_0_data_inv ) ) ; @@ -56359,6 +60295,9 @@ sb_1__0__mux_2level_tapbuf_basis_input2_mem2_3 mux_l1_in_2_ ( .mem ( local_encoder2to3_0_data[0:1] ) , .mem_inv ( local_encoder2to3_0_data_inv[0:1] ) , .out ( mux_2level_tapbuf_basis_input2_mem2_0_out ) , .p0 ( p0 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_215 ( .A ( BUF_net_216 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_216 ( + .A ( mux_2level_tapbuf_basis_input3_mem3_2_out[0] ) , .Y ( BUF_net_216 ) ) ; endmodule @@ -56370,9 +60309,13 @@ input [0:1] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( p0 ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -56383,10 +60326,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -56397,10 +60344,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -56411,10 +60362,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -56512,9 +60467,13 @@ input [0:1] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( p0 ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -56525,10 +60484,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -56539,10 +60502,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -56553,10 +60520,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -56615,8 +60586,6 @@ wire [0:0] mux_2level_tapbuf_basis_input3_mem3_2_out ; sb_1__0__const1_1 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( mux_2level_tapbuf_basis_input3_mem3_2_out[0] ) , .X ( out[0] ) ) ; sb_1__0__local_encoder2to3_2 local_encoder2to3_0_ ( .addr ( sram[0:1] ) , .data ( local_encoder2to3_0_data ) , .data_inv ( local_encoder2to3_0_data_inv ) ) ; @@ -56643,6 +60612,9 @@ sb_1__0__mux_2level_tapbuf_basis_input2_mem2_1 mux_l1_in_2_ ( .mem ( local_encoder2to3_0_data[0:1] ) , .mem_inv ( local_encoder2to3_0_data_inv[0:1] ) , .out ( mux_2level_tapbuf_basis_input2_mem2_0_out ) , .p0 ( p0 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_205 ( .A ( BUF_net_206 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_206 ( + .A ( mux_2level_tapbuf_basis_input3_mem3_2_out[0] ) , .Y ( BUF_net_206 ) ) ; endmodule @@ -56654,9 +60626,13 @@ input [0:1] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( p0 ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -56667,10 +60643,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -56681,10 +60661,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -56695,10 +60679,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -56858,7 +60846,7 @@ output prog_clk_3_N_out ; input clk_3_S_in ; output clk_3_N_out ; -wire ropt_net_229 ; +wire ropt_net_242 ; wire [0:0] prog_clk ; wire prog_clk_0 ; wire [0:3] mux_2level_tapbuf_size10_0_sram ; @@ -56968,7 +60956,7 @@ sb_1__0__mux_2level_tapbuf_size7_0 mux_top_track_0 ( .sram ( mux_2level_tapbuf_size7_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 , SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) , - .out ( chany_top_out[0] ) , .p0 ( optlc_net_212 ) ) ; + .out ( chany_top_out[0] ) , .p0 ( optlc_net_220 ) ) ; sb_1__0__mux_2level_tapbuf_size7_1 mux_right_track_0 ( .in ( { chany_top_in[10] , chany_top_in[21] , right_bottom_grid_pin_1_[0] , right_bottom_grid_pin_7_[0] , @@ -56977,7 +60965,7 @@ sb_1__0__mux_2level_tapbuf_size7_1 mux_right_track_0 ( .sram ( mux_2level_tapbuf_size7_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 , SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 } ) , - .out ( chanx_right_out[0] ) , .p0 ( optlc_net_212 ) ) ; + .out ( chanx_right_out[0] ) , .p0 ( optlc_net_220 ) ) ; sb_1__0__mux_2level_tapbuf_size7_2 mux_right_track_12 ( .in ( { chany_top_in[4] , chany_top_in[15] , chany_top_in[26] , right_bottom_grid_pin_1_[0] , right_bottom_grid_pin_13_[0] , @@ -56985,7 +60973,7 @@ sb_1__0__mux_2level_tapbuf_size7_2 mux_right_track_12 ( .sram ( mux_2level_tapbuf_size7_2_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_9 , SYNOPSYS_UNCONNECTED_10 , SYNOPSYS_UNCONNECTED_11 , SYNOPSYS_UNCONNECTED_12 } ) , - .out ( chanx_right_out[6] ) , .p0 ( optlc_net_212 ) ) ; + .out ( chanx_right_out[6] ) , .p0 ( optlc_net_224 ) ) ; sb_1__0__mux_2level_tapbuf_size7_3 mux_right_track_20 ( .in ( { chany_top_in[5] , chany_top_in[16] , chany_top_in[27] , right_bottom_grid_pin_3_[0] , right_bottom_grid_pin_15_[0] , @@ -56993,7 +60981,7 @@ sb_1__0__mux_2level_tapbuf_size7_3 mux_right_track_20 ( .sram ( mux_2level_tapbuf_size7_3_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 , SYNOPSYS_UNCONNECTED_15 , SYNOPSYS_UNCONNECTED_16 } ) , - .out ( chanx_right_out[10] ) , .p0 ( optlc_net_209 ) ) ; + .out ( chanx_right_out[10] ) , .p0 ( optlc_net_224 ) ) ; sb_1__0__mux_2level_tapbuf_size7_4 mux_right_track_28 ( .in ( { chany_top_in[6] , chany_top_in[17] , chany_top_in[28] , right_bottom_grid_pin_5_[0] , right_bottom_grid_pin_17_[0] , @@ -57001,7 +60989,7 @@ sb_1__0__mux_2level_tapbuf_size7_4 mux_right_track_28 ( .sram ( mux_2level_tapbuf_size7_4_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_17 , SYNOPSYS_UNCONNECTED_18 , SYNOPSYS_UNCONNECTED_19 , SYNOPSYS_UNCONNECTED_20 } ) , - .out ( chanx_right_out[14] ) , .p0 ( optlc_net_209 ) ) ; + .out ( chanx_right_out[14] ) , .p0 ( optlc_net_224 ) ) ; sb_1__0__mux_2level_tapbuf_size7_5 mux_left_track_3 ( .in ( { chany_top_in[10] , chany_top_in[21] , chanx_left_out[7] , chanx_left_out[21] , left_bottom_grid_pin_3_[0] , @@ -57009,7 +60997,7 @@ sb_1__0__mux_2level_tapbuf_size7_5 mux_left_track_3 ( .sram ( mux_2level_tapbuf_size7_5_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_21 , SYNOPSYS_UNCONNECTED_22 , SYNOPSYS_UNCONNECTED_23 , SYNOPSYS_UNCONNECTED_24 } ) , - .out ( chanx_left_out[1] ) , .p0 ( optlc_net_207 ) ) ; + .out ( chanx_left_out[1] ) , .p0 ( optlc_net_223 ) ) ; sb_1__0__mux_2level_tapbuf_size7_6 mux_left_track_5 ( .in ( { chany_top_in[9] , chany_top_in[20] , chanx_left_out[8] , chanx_left_out[23] , left_bottom_grid_pin_5_[0] , @@ -57017,7 +61005,7 @@ sb_1__0__mux_2level_tapbuf_size7_6 mux_left_track_5 ( .sram ( mux_2level_tapbuf_size7_6_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_25 , SYNOPSYS_UNCONNECTED_26 , SYNOPSYS_UNCONNECTED_27 , SYNOPSYS_UNCONNECTED_28 } ) , - .out ( chanx_left_out[2] ) , .p0 ( optlc_net_210 ) ) ; + .out ( chanx_left_out[2] ) , .p0 ( optlc_net_221 ) ) ; sb_1__0__mux_2level_tapbuf_size7_7 mux_left_track_13 ( .in ( { chany_top_in[6] , chany_top_in[17] , chany_top_in[28] , chanx_left_out[12] , chanx_left_out[27] , left_bottom_grid_pin_1_[0] , @@ -57025,7 +61013,7 @@ sb_1__0__mux_2level_tapbuf_size7_7 mux_left_track_13 ( .sram ( mux_2level_tapbuf_size7_7_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_29 , SYNOPSYS_UNCONNECTED_30 , SYNOPSYS_UNCONNECTED_31 , SYNOPSYS_UNCONNECTED_32 } ) , - .out ( chanx_left_out[6] ) , .p0 ( optlc_net_211 ) ) ; + .out ( chanx_left_out[6] ) , .p0 ( optlc_net_223 ) ) ; sb_1__0__mux_2level_tapbuf_size7_8 mux_left_track_21 ( .in ( { chany_top_in[5] , chany_top_in[16] , chany_top_in[27] , chanx_left_out[13] , chanx_left_out[28] , left_bottom_grid_pin_3_[0] , @@ -57033,7 +61021,7 @@ sb_1__0__mux_2level_tapbuf_size7_8 mux_left_track_21 ( .sram ( mux_2level_tapbuf_size7_8_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_33 , SYNOPSYS_UNCONNECTED_34 , SYNOPSYS_UNCONNECTED_35 , SYNOPSYS_UNCONNECTED_36 } ) , - .out ( chanx_left_out[10] ) , .p0 ( optlc_net_207 ) ) ; + .out ( chanx_left_out[10] ) , .p0 ( optlc_net_223 ) ) ; sb_1__0__mux_2level_tapbuf_size7 mux_left_track_29 ( .in ( { chany_top_in[4] , chany_top_in[15] , chany_top_in[26] , chanx_left_out[15] , chanx_left_out[29] , left_bottom_grid_pin_5_[0] , @@ -57041,7 +61029,7 @@ sb_1__0__mux_2level_tapbuf_size7 mux_left_track_29 ( .sram ( mux_2level_tapbuf_size7_9_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_37 , SYNOPSYS_UNCONNECTED_38 , SYNOPSYS_UNCONNECTED_39 , SYNOPSYS_UNCONNECTED_40 } ) , - .out ( chanx_left_out[14] ) , .p0 ( optlc_net_210 ) ) ; + .out ( chanx_left_out[14] ) , .p0 ( optlc_net_223 ) ) ; sb_1__0__mux_2level_tapbuf_size7_mem_0 mem_top_track_0 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( mux_2level_tapbuf_size7_mem_0_ccff_tail ) , @@ -57098,7 +61086,7 @@ sb_1__0__mux_2level_tapbuf_size6_0 mux_top_track_2 ( .sram ( mux_2level_tapbuf_size6_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_41 , SYNOPSYS_UNCONNECTED_42 , SYNOPSYS_UNCONNECTED_43 , SYNOPSYS_UNCONNECTED_44 } ) , - .out ( chany_top_out[1] ) , .p0 ( optlc_net_210 ) ) ; + .out ( chany_top_out[1] ) , .p0 ( optlc_net_218 ) ) ; sb_1__0__mux_2level_tapbuf_size6_1 mux_top_track_6 ( .in ( { top_left_grid_pin_44_[0] , top_left_grid_pin_47_[0] , top_left_grid_pin_50_[0] , chanx_right_in[5] , chanx_left_out[9] , @@ -57106,7 +61094,7 @@ sb_1__0__mux_2level_tapbuf_size6_1 mux_top_track_6 ( .sram ( mux_2level_tapbuf_size6_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_45 , SYNOPSYS_UNCONNECTED_46 , SYNOPSYS_UNCONNECTED_47 , SYNOPSYS_UNCONNECTED_48 } ) , - .out ( chany_top_out[3] ) , .p0 ( optlc_net_212 ) ) ; + .out ( chany_top_out[3] ) , .p0 ( optlc_net_218 ) ) ; sb_1__0__mux_2level_tapbuf_size6 mux_top_track_8 ( .in ( { chany_top_out[19] , top_left_grid_pin_48_[0] , top_left_grid_pin_51_[0] , chanx_right_in[9] , chanx_left_out[11] , @@ -57114,7 +61102,7 @@ sb_1__0__mux_2level_tapbuf_size6 mux_top_track_8 ( .sram ( mux_2level_tapbuf_size6_2_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_49 , SYNOPSYS_UNCONNECTED_50 , SYNOPSYS_UNCONNECTED_51 , SYNOPSYS_UNCONNECTED_52 } ) , - .out ( chany_top_out[4] ) , .p0 ( optlc_net_208 ) ) ; + .out ( chany_top_out[4] ) , .p0 ( optlc_net_225 ) ) ; sb_1__0__mux_2level_tapbuf_size6_mem_0 mem_top_track_2 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( mux_2level_tapbuf_size7_mem_0_ccff_tail ) , @@ -57136,42 +61124,42 @@ sb_1__0__mux_2level_tapbuf_size5_0 mux_top_track_4 ( .sram ( mux_2level_tapbuf_size5_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_53 , SYNOPSYS_UNCONNECTED_54 , SYNOPSYS_UNCONNECTED_55 , SYNOPSYS_UNCONNECTED_56 } ) , - .out ( chany_top_out[2] ) , .p0 ( optlc_net_210 ) ) ; + .out ( chany_top_out[2] ) , .p0 ( optlc_net_223 ) ) ; sb_1__0__mux_2level_tapbuf_size5_1 mux_top_track_10 ( .in ( { top_left_grid_pin_46_[0] , top_left_grid_pin_49_[0] , chanx_left_out[12] , chanx_right_in[13] , chanx_right_out[12] } ) , .sram ( mux_2level_tapbuf_size5_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_57 , SYNOPSYS_UNCONNECTED_58 , SYNOPSYS_UNCONNECTED_59 , SYNOPSYS_UNCONNECTED_60 } ) , - .out ( chany_top_out[5] ) , .p0 ( optlc_net_210 ) ) ; + .out ( chany_top_out[5] ) , .p0 ( optlc_net_222 ) ) ; sb_1__0__mux_2level_tapbuf_size5_2 mux_right_track_36 ( .in ( { chany_top_in[7] , chany_top_in[18] , chany_top_in[29] , right_bottom_grid_pin_7_[0] , chanx_right_out[16] } ) , .sram ( mux_2level_tapbuf_size5_2_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_61 , SYNOPSYS_UNCONNECTED_62 , SYNOPSYS_UNCONNECTED_63 , SYNOPSYS_UNCONNECTED_64 } ) , - .out ( chanx_right_out[18] ) , .p0 ( optlc_net_209 ) ) ; + .out ( chanx_right_out[18] ) , .p0 ( optlc_net_220 ) ) ; sb_1__0__mux_2level_tapbuf_size5_3 mux_left_track_37 ( .in ( { chany_top_in[3] , chany_top_in[14] , chany_top_in[25] , chanx_left_out[16] , left_bottom_grid_pin_7_[0] } ) , .sram ( mux_2level_tapbuf_size5_3_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_65 , SYNOPSYS_UNCONNECTED_66 , SYNOPSYS_UNCONNECTED_67 , SYNOPSYS_UNCONNECTED_68 } ) , - .out ( chanx_left_out[18] ) , .p0 ( optlc_net_210 ) ) ; + .out ( chanx_left_out[18] ) , .p0 ( optlc_net_223 ) ) ; sb_1__0__mux_2level_tapbuf_size5_4 mux_left_track_45 ( .in ( { chany_top_in[2] , chany_top_in[13] , chany_top_in[24] , chanx_left_out[17] , left_bottom_grid_pin_9_[0] } ) , .sram ( mux_2level_tapbuf_size5_4_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_69 , SYNOPSYS_UNCONNECTED_70 , SYNOPSYS_UNCONNECTED_71 , SYNOPSYS_UNCONNECTED_72 } ) , - .out ( chanx_left_out[22] ) , .p0 ( optlc_net_210 ) ) ; + .out ( chanx_left_out[22] ) , .p0 ( optlc_net_221 ) ) ; sb_1__0__mux_2level_tapbuf_size5 mux_left_track_53 ( .in ( { chany_top_in[1] , chany_top_in[12] , chany_top_in[23] , chanx_left_out[19] , left_bottom_grid_pin_11_[0] } ) , .sram ( mux_2level_tapbuf_size5_5_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_73 , SYNOPSYS_UNCONNECTED_74 , SYNOPSYS_UNCONNECTED_75 , SYNOPSYS_UNCONNECTED_76 } ) , - .out ( chanx_left_out[26] ) , .p0 ( optlc_net_210 ) ) ; + .out ( chanx_left_out[26] ) , .p0 ( optlc_net_221 ) ) ; sb_1__0__mux_2level_tapbuf_size5_mem_0 mem_top_track_4 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( mux_2level_tapbuf_size6_mem_0_ccff_tail ) , @@ -57207,42 +61195,42 @@ sb_1__0__mux_2level_tapbuf_size4_0 mux_top_track_12 ( .sram ( mux_2level_tapbuf_size4_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_77 , SYNOPSYS_UNCONNECTED_78 , SYNOPSYS_UNCONNECTED_79 , SYNOPSYS_UNCONNECTED_80 } ) , - .out ( chany_top_out[6] ) , .p0 ( optlc_net_208 ) ) ; + .out ( chany_top_out[6] ) , .p0 ( optlc_net_224 ) ) ; sb_1__0__mux_2level_tapbuf_size4_1 mux_top_track_14 ( .in ( { chany_top_out[19] , chanx_left_out[15] , chanx_right_in[21] , chanx_right_out[15] } ) , .sram ( mux_2level_tapbuf_size4_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_81 , SYNOPSYS_UNCONNECTED_82 , SYNOPSYS_UNCONNECTED_83 , SYNOPSYS_UNCONNECTED_84 } ) , - .out ( chany_top_out[7] ) , .p0 ( optlc_net_208 ) ) ; + .out ( chany_top_out[7] ) , .p0 ( optlc_net_222 ) ) ; sb_1__0__mux_2level_tapbuf_size4_2 mux_top_track_16 ( .in ( { top_left_grid_pin_46_[0] , chanx_left_out[16] , chanx_right_in[25] , chanx_right_out[16] } ) , .sram ( mux_2level_tapbuf_size4_2_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_85 , SYNOPSYS_UNCONNECTED_86 , SYNOPSYS_UNCONNECTED_87 , SYNOPSYS_UNCONNECTED_88 } ) , - .out ( chany_top_out[8] ) , .p0 ( optlc_net_208 ) ) ; + .out ( chany_top_out[8] ) , .p0 ( optlc_net_220 ) ) ; sb_1__0__mux_2level_tapbuf_size4_3 mux_top_track_18 ( .in ( { top_left_grid_pin_47_[0] , chanx_left_out[17] , chanx_right_in[29] , chanx_right_out[17] } ) , .sram ( mux_2level_tapbuf_size4_3_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_89 , SYNOPSYS_UNCONNECTED_90 , SYNOPSYS_UNCONNECTED_91 , SYNOPSYS_UNCONNECTED_92 } ) , - .out ( chany_top_out[9] ) , .p0 ( optlc_net_208 ) ) ; + .out ( chany_top_out[9] ) , .p0 ( optlc_net_220 ) ) ; sb_1__0__mux_2level_tapbuf_size4_4 mux_right_track_44 ( .in ( { chany_top_in[8] , chany_top_in[19] , right_bottom_grid_pin_9_[0] , chanx_right_out[17] } ) , .sram ( mux_2level_tapbuf_size4_4_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_93 , SYNOPSYS_UNCONNECTED_94 , SYNOPSYS_UNCONNECTED_95 , SYNOPSYS_UNCONNECTED_96 } ) , - .out ( chanx_right_out[22] ) , .p0 ( optlc_net_209 ) ) ; + .out ( chanx_right_out[22] ) , .p0 ( optlc_net_218 ) ) ; sb_1__0__mux_2level_tapbuf_size4 mux_right_track_52 ( .in ( { chany_top_in[9] , chany_top_in[20] , right_bottom_grid_pin_11_[0] , chanx_right_out[19] } ) , .sram ( mux_2level_tapbuf_size4_5_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_97 , SYNOPSYS_UNCONNECTED_98 , SYNOPSYS_UNCONNECTED_99 , SYNOPSYS_UNCONNECTED_100 } ) , - .out ( chanx_right_out[26] ) , .p0 ( optlc_net_208 ) ) ; + .out ( chanx_right_out[26] ) , .p0 ( optlc_net_218 ) ) ; sb_1__0__mux_2level_tapbuf_size4_mem_0 mem_top_track_12 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( mux_2level_tapbuf_size5_mem_1_ccff_tail ) , @@ -57278,31 +61266,31 @@ sb_1__0__mux_2level_tapbuf_size3_0 mux_top_track_20 ( chanx_right_out[19] } ) , .sram ( mux_2level_tapbuf_size3_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_101 , SYNOPSYS_UNCONNECTED_102 } ) , - .out ( chany_top_out[10] ) , .p0 ( optlc_net_212 ) ) ; + .out ( chany_top_out[10] ) , .p0 ( optlc_net_225 ) ) ; sb_1__0__mux_2level_tapbuf_size3_1 mux_top_track_22 ( .in ( { top_left_grid_pin_49_[0] , chanx_left_out[20] , chanx_right_out[20] } ) , .sram ( mux_2level_tapbuf_size3_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_103 , SYNOPSYS_UNCONNECTED_104 } ) , - .out ( chany_top_out[11] ) , .p0 ( optlc_net_212 ) ) ; + .out ( chany_top_out[11] ) , .p0 ( optlc_net_217 ) ) ; sb_1__0__mux_2level_tapbuf_size3_2 mux_top_track_24 ( .in ( { top_left_grid_pin_50_[0] , chanx_left_out[21] , chanx_right_out[21] } ) , .sram ( mux_2level_tapbuf_size3_2_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_105 , SYNOPSYS_UNCONNECTED_106 } ) , - .out ( chany_top_out[12] ) , .p0 ( optlc_net_212 ) ) ; + .out ( chany_top_out[12] ) , .p0 ( optlc_net_217 ) ) ; sb_1__0__mux_2level_tapbuf_size3_3 mux_top_track_26 ( .in ( { top_left_grid_pin_51_[0] , chanx_left_out[23] , chanx_right_out[23] } ) , .sram ( mux_2level_tapbuf_size3_3_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_107 , SYNOPSYS_UNCONNECTED_108 } ) , - .out ( chany_top_out[13] ) , .p0 ( optlc_net_212 ) ) ; + .out ( chany_top_out[13] ) , .p0 ( optlc_net_222 ) ) ; sb_1__0__mux_2level_tapbuf_size3 mux_top_track_36 ( .in ( { top_left_grid_pin_44_[0] , chanx_left_out[29] , chanx_right_out[29] } ) , .sram ( mux_2level_tapbuf_size3_4_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_109 , SYNOPSYS_UNCONNECTED_110 } ) , - .out ( chany_top_out[18] ) , .p0 ( optlc_net_211 ) ) ; + .out ( chany_top_out[18] ) , .p0 ( optlc_net_217 ) ) ; sb_1__0__mux_2level_tapbuf_size3_mem_0 mem_top_track_20 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( mux_2level_tapbuf_size4_mem_3_ccff_tail ) , @@ -57332,57 +61320,57 @@ sb_1__0__mux_2level_tapbuf_size2_0 mux_top_track_28 ( .in ( { chanx_left_out[24] , chanx_right_out[24] } ) , .sram ( mux_2level_tapbuf_size2_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_111 , SYNOPSYS_UNCONNECTED_112 } ) , - .out ( chany_top_out[14] ) , .p0 ( optlc_net_211 ) ) ; + .out ( chany_top_out[14] ) , .p0 ( optlc_net_222 ) ) ; sb_1__0__mux_2level_tapbuf_size2_1 mux_top_track_30 ( .in ( { chanx_left_out[25] , chanx_right_out[25] } ) , .sram ( mux_2level_tapbuf_size2_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_113 , SYNOPSYS_UNCONNECTED_114 } ) , - .out ( chany_top_out[15] ) , .p0 ( optlc_net_209 ) ) ; + .out ( chany_top_out[15] ) , .p0 ( optlc_net_222 ) ) ; sb_1__0__mux_2level_tapbuf_size2_2 mux_top_track_32 ( .in ( { chanx_left_out[27] , chanx_right_out[27] } ) , .sram ( mux_2level_tapbuf_size2_2_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_115 , SYNOPSYS_UNCONNECTED_116 } ) , - .out ( chany_top_out[16] ) , .p0 ( optlc_net_211 ) ) ; + .out ( chany_top_out[16] ) , .p0 ( optlc_net_222 ) ) ; sb_1__0__mux_2level_tapbuf_size2_3 mux_top_track_34 ( .in ( { chanx_left_out[28] , chanx_right_out[28] } ) , .sram ( mux_2level_tapbuf_size2_3_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_117 , SYNOPSYS_UNCONNECTED_118 } ) , - .out ( chany_top_out[17] ) , .p0 ( optlc_net_211 ) ) ; + .out ( chany_top_out[17] ) , .p0 ( optlc_net_222 ) ) ; sb_1__0__mux_2level_tapbuf_size2_4 mux_top_track_40 ( .in ( { top_left_grid_pin_46_[0] , chanx_left_in[29] } ) , .sram ( mux_2level_tapbuf_size2_4_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_119 , SYNOPSYS_UNCONNECTED_120 } ) , - .out ( chany_top_out[20] ) , .p0 ( optlc_net_207 ) ) ; + .out ( chany_top_out[20] ) , .p0 ( optlc_net_217 ) ) ; sb_1__0__mux_2level_tapbuf_size2_5 mux_top_track_42 ( .in ( { top_left_grid_pin_47_[0] , chanx_left_in[25] } ) , .sram ( mux_2level_tapbuf_size2_5_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_121 , SYNOPSYS_UNCONNECTED_122 } ) , - .out ( chany_top_out[21] ) , .p0 ( optlc_net_207 ) ) ; + .out ( chany_top_out[21] ) , .p0 ( optlc_net_217 ) ) ; sb_1__0__mux_2level_tapbuf_size2_6 mux_top_track_44 ( .in ( { top_left_grid_pin_48_[0] , chanx_left_in[21] } ) , .sram ( mux_2level_tapbuf_size2_6_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_123 , SYNOPSYS_UNCONNECTED_124 } ) , - .out ( chany_top_out[22] ) , .p0 ( optlc_net_207 ) ) ; + .out ( chany_top_out[22] ) , .p0 ( optlc_net_217 ) ) ; sb_1__0__mux_2level_tapbuf_size2_7 mux_top_track_46 ( .in ( { top_left_grid_pin_49_[0] , chanx_left_in[17] } ) , .sram ( mux_2level_tapbuf_size2_7_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_125 , SYNOPSYS_UNCONNECTED_126 } ) , - .out ( chany_top_out[23] ) , .p0 ( optlc_net_207 ) ) ; + .out ( chany_top_out[23] ) , .p0 ( optlc_net_217 ) ) ; sb_1__0__mux_2level_tapbuf_size2_8 mux_top_track_48 ( .in ( { top_left_grid_pin_50_[0] , chanx_left_in[13] } ) , .sram ( mux_2level_tapbuf_size2_8_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_127 , SYNOPSYS_UNCONNECTED_128 } ) , - .out ( chany_top_out[24] ) , .p0 ( optlc_net_211 ) ) ; + .out ( chany_top_out[24] ) , .p0 ( optlc_net_217 ) ) ; sb_1__0__mux_2level_tapbuf_size2_9 mux_top_track_50 ( .in ( { top_left_grid_pin_51_[0] , chanx_left_in[9] } ) , .sram ( mux_2level_tapbuf_size2_9_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_129 , SYNOPSYS_UNCONNECTED_130 } ) , - .out ( chany_top_out[25] ) , .p0 ( optlc_net_211 ) ) ; + .out ( chany_top_out[25] ) , .p0 ( optlc_net_217 ) ) ; sb_1__0__mux_2level_tapbuf_size2 mux_top_track_58 ( .in ( { chanx_right_in[0] , chanx_left_in[1] } ) , .sram ( mux_2level_tapbuf_size2_10_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_131 , SYNOPSYS_UNCONNECTED_132 } ) , - .out ( chany_top_out[29] ) , .p0 ( optlc_net_211 ) ) ; + .out ( chany_top_out[29] ) , .p0 ( optlc_net_224 ) ) ; sb_1__0__mux_2level_tapbuf_size2_mem_0 mem_top_track_28 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( mux_2level_tapbuf_size3_mem_3_ccff_tail ) , @@ -57446,7 +61434,7 @@ sb_1__0__mux_2level_tapbuf_size8_0 mux_right_track_2 ( .sram ( mux_2level_tapbuf_size8_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_133 , SYNOPSYS_UNCONNECTED_134 , SYNOPSYS_UNCONNECTED_135 , SYNOPSYS_UNCONNECTED_136 } ) , - .out ( chanx_right_out[1] ) , .p0 ( optlc_net_209 ) ) ; + .out ( chanx_right_out[1] ) , .p0 ( optlc_net_220 ) ) ; sb_1__0__mux_2level_tapbuf_size8_1 mux_right_track_4 ( .in ( { chany_top_in[1] , chany_top_in[12] , chany_top_in[23] , right_bottom_grid_pin_5_[0] , right_bottom_grid_pin_11_[0] , @@ -57455,7 +61443,7 @@ sb_1__0__mux_2level_tapbuf_size8_1 mux_right_track_4 ( .sram ( mux_2level_tapbuf_size8_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_137 , SYNOPSYS_UNCONNECTED_138 , SYNOPSYS_UNCONNECTED_139 , SYNOPSYS_UNCONNECTED_140 } ) , - .out ( chanx_right_out[2] ) , .p0 ( optlc_net_208 ) ) ; + .out ( chanx_right_out[2] ) , .p0 ( optlc_net_219 ) ) ; sb_1__0__mux_2level_tapbuf_size8 mux_left_track_1 ( .in ( { chany_top_in[0] , chany_top_in[11] , chany_top_in[22] , chanx_left_out[4] , chanx_left_out[20] , left_bottom_grid_pin_1_[0] , @@ -57463,7 +61451,7 @@ sb_1__0__mux_2level_tapbuf_size8 mux_left_track_1 ( .sram ( mux_2level_tapbuf_size8_2_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_141 , SYNOPSYS_UNCONNECTED_142 , SYNOPSYS_UNCONNECTED_143 , SYNOPSYS_UNCONNECTED_144 } ) , - .out ( chanx_left_out[0] ) , .p0 ( optlc_net_212 ) ) ; + .out ( chanx_left_out[0] ) , .p0 ( optlc_net_221 ) ) ; sb_1__0__mux_2level_tapbuf_size8_mem_0 mem_right_track_2 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( mux_2level_tapbuf_size7_mem_1_ccff_tail ) , @@ -57488,8 +61476,8 @@ sb_1__0__mux_2level_tapbuf_size10 mux_right_track_6 ( .sram ( mux_2level_tapbuf_size10_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_145 , SYNOPSYS_UNCONNECTED_146 , SYNOPSYS_UNCONNECTED_147 , SYNOPSYS_UNCONNECTED_148 } ) , - .out ( { aps_rename_505_ } ) , - .p0 ( optlc_net_208 ) ) ; + .out ( { aps_rename_506_ } ) , + .p0 ( optlc_net_219 ) ) ; sb_1__0__mux_2level_tapbuf_size10_mem mem_right_track_6 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( mux_2level_tapbuf_size8_mem_1_ccff_tail ) , @@ -57503,7 +61491,8 @@ sb_1__0__mux_2level_tapbuf_size9_0 mux_right_track_10 ( .sram ( mux_2level_tapbuf_size9_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_149 , SYNOPSYS_UNCONNECTED_150 , SYNOPSYS_UNCONNECTED_151 , SYNOPSYS_UNCONNECTED_152 } ) , - .out ( chanx_right_out[5] ) , .p0 ( optlc_net_208 ) ) ; + .out ( { aps_rename_507_ } ) , + .p0 ( optlc_net_220 ) ) ; sb_1__0__mux_2level_tapbuf_size9_1 mux_left_track_7 ( .in ( { chany_top_in[8] , chany_top_in[19] , chanx_left_out[9] , chanx_left_out[24] , left_bottom_grid_pin_1_[0] , @@ -57512,8 +61501,7 @@ sb_1__0__mux_2level_tapbuf_size9_1 mux_left_track_7 ( .sram ( mux_2level_tapbuf_size9_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_153 , SYNOPSYS_UNCONNECTED_154 , SYNOPSYS_UNCONNECTED_155 , SYNOPSYS_UNCONNECTED_156 } ) , - .out ( { aps_rename_506_ } ) , - .p0 ( optlc_net_210 ) ) ; + .out ( chanx_left_out[3] ) , .p0 ( optlc_net_221 ) ) ; sb_1__0__mux_2level_tapbuf_size9 mux_left_track_11 ( .in ( { chany_top_in[7] , chany_top_in[18] , chany_top_in[29] , chanx_left_out[11] , chanx_left_out[25] , left_bottom_grid_pin_3_[0] , @@ -57522,7 +61510,8 @@ sb_1__0__mux_2level_tapbuf_size9 mux_left_track_11 ( .sram ( mux_2level_tapbuf_size9_2_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_157 , SYNOPSYS_UNCONNECTED_158 , SYNOPSYS_UNCONNECTED_159 , SYNOPSYS_UNCONNECTED_160 } ) , - .out ( chanx_left_out[5] ) , .p0 ( optlc_net_207 ) ) ; + .out ( { aps_rename_508_ } ) , + .p0 ( optlc_net_223 ) ) ; sb_1__0__mux_2level_tapbuf_size9_mem_0 mem_right_track_10 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( mux_2level_tapbuf_size10_mem_0_ccff_tail ) , @@ -57538,23 +61527,23 @@ sb_1__0__mux_2level_tapbuf_size9_mem mem_left_track_11 ( .pReset ( pReset ) , .ccff_head ( mux_2level_tapbuf_size9_mem_1_ccff_tail ) , .ccff_tail ( mux_2level_tapbuf_size9_mem_2_ccff_tail ) , .mem_out ( mux_2level_tapbuf_size9_2_sram ) ) ; -sky130_fd_sc_hd__conb_1 optlc_209 ( .LO ( SYNOPSYS_UNCONNECTED_161 ) , - .HI ( optlc_net_207 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_219 ( .LO ( SYNOPSYS_UNCONNECTED_161 ) , + .HI ( optlc_net_217 ) ) ; sky130_fd_sc_hd__buf_8 pReset_FTB00 ( .A ( pReset_E_in ) , .X ( pReset[0] ) ) ; sky130_fd_sc_hd__buf_1 pReset_N_FTB01 ( .A ( pReset_E_in ) , - .X ( aps_rename_507_ ) ) ; + .X ( aps_rename_509_ ) ) ; sky130_fd_sc_hd__bufbuf_16 pReset_W_FTB01 ( .A ( pReset_E_in ) , .X ( pReset_W_out ) ) ; sky130_fd_sc_hd__buf_1 pReset_E_FTB01 ( .A ( pReset_E_in ) , - .X ( aps_rename_508_ ) ) ; -sky130_fd_sc_hd__conb_1 optlc_211 ( .LO ( SYNOPSYS_UNCONNECTED_162 ) , - .HI ( optlc_net_208 ) ) ; + .X ( aps_rename_510_ ) ) ; +sky130_fd_sc_hd__conb_1 optlc_223 ( .LO ( SYNOPSYS_UNCONNECTED_162 ) , + .HI ( optlc_net_218 ) ) ; sky130_fd_sc_hd__buf_1 prog_clk_0_FTB00 ( .A ( prog_clk_0_N_in ) , .X ( prog_clk[0] ) ) ; sky130_fd_sc_hd__buf_1 prog_clk_3_N_FTB01 ( .A ( prog_clk_3_S_in ) , - .X ( aps_rename_509_ ) ) ; + .X ( aps_rename_511_ ) ) ; sky130_fd_sc_hd__buf_1 clk_3_N_FTB01 ( .A ( clk_3_S_in ) , - .X ( aps_rename_510_ ) ) ; + .X ( aps_rename_512_ ) ) ; sky130_fd_sc_hd__buf_8 FTB_105__104 ( .A ( top_left_grid_pin_45_[0] ) , .X ( chany_top_out[19] ) ) ; sky130_fd_sc_hd__buf_8 FTB_106__105 ( .A ( chanx_right_in[3] ) , @@ -57600,7 +61589,7 @@ sky130_fd_sc_hd__buf_8 FTB_125__124 ( .A ( chanx_left_in[2] ) , sky130_fd_sc_hd__buf_8 FTB_126__125 ( .A ( chanx_left_in[3] ) , .X ( chanx_right_out[4] ) ) ; sky130_fd_sc_hd__buf_6 FTB_127__126 ( .A ( chanx_left_in[4] ) , - .X ( ropt_net_229 ) ) ; + .X ( ropt_net_242 ) ) ; sky130_fd_sc_hd__buf_8 FTB_128__127 ( .A ( chanx_left_in[5] ) , .X ( chany_top_out[26] ) ) ; sky130_fd_sc_hd__buf_8 FTB_129__128 ( .A ( chanx_left_in[6] ) , @@ -57644,32 +61633,40 @@ sky130_fd_sc_hd__inv_8 BINV_R_195 ( .A ( BUF_net_196 ) , .Y ( Test_en_N_out ) ) ; sky130_fd_sc_hd__inv_1 BINV_R_196 ( .A ( Test_en_S_in ) , .Y ( BUF_net_196 ) ) ; sky130_fd_sc_hd__inv_8 BINV_R_197 ( .A ( BUF_net_198 ) , .Y ( pReset_N_out ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_198 ( .A ( aps_rename_507_ ) , +sky130_fd_sc_hd__inv_1 BINV_R_198 ( .A ( aps_rename_509_ ) , .Y ( BUF_net_198 ) ) ; sky130_fd_sc_hd__inv_8 BINV_R_199 ( .A ( BUF_net_200 ) , .Y ( Reset_N_out ) ) ; sky130_fd_sc_hd__inv_1 BINV_R_200 ( .A ( Reset_S_in ) , .Y ( BUF_net_200 ) ) ; sky130_fd_sc_hd__inv_8 BINV_R_201 ( .A ( BUF_net_202 ) , .Y ( prog_clk_3_N_out ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_202 ( .A ( aps_rename_509_ ) , +sky130_fd_sc_hd__inv_1 BINV_R_202 ( .A ( aps_rename_511_ ) , .Y ( BUF_net_202 ) ) ; sky130_fd_sc_hd__inv_8 BINV_R_203 ( .A ( BUF_net_204 ) , .Y ( clk_3_N_out ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_204 ( .A ( aps_rename_510_ ) , +sky130_fd_sc_hd__inv_1 BINV_R_204 ( .A ( aps_rename_512_ ) , .Y ( BUF_net_204 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_213 ( .LO ( SYNOPSYS_UNCONNECTED_163 ) , - .HI ( optlc_net_209 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_215 ( .LO ( SYNOPSYS_UNCONNECTED_164 ) , - .HI ( optlc_net_210 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_217 ( .LO ( SYNOPSYS_UNCONNECTED_165 ) , - .HI ( optlc_net_211 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_219 ( .LO ( SYNOPSYS_UNCONNECTED_166 ) , - .HI ( optlc_net_212 ) ) ; -sky130_fd_sc_hd__buf_6 ZBUF_6_f_inst_220 ( .A ( aps_rename_505_ ) , +sky130_fd_sc_hd__conb_1 optlc_225 ( .LO ( SYNOPSYS_UNCONNECTED_163 ) , + .HI ( optlc_net_219 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_227 ( .LO ( SYNOPSYS_UNCONNECTED_164 ) , + .HI ( optlc_net_220 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_230 ( .LO ( SYNOPSYS_UNCONNECTED_165 ) , + .HI ( optlc_net_221 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_232 ( .LO ( SYNOPSYS_UNCONNECTED_166 ) , + .HI ( optlc_net_222 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_235 ( .LO ( SYNOPSYS_UNCONNECTED_167 ) , + .HI ( optlc_net_223 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_237 ( .LO ( SYNOPSYS_UNCONNECTED_168 ) , + .HI ( optlc_net_224 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_239 ( .LO ( SYNOPSYS_UNCONNECTED_169 ) , + .HI ( optlc_net_225 ) ) ; +sky130_fd_sc_hd__buf_6 ZBUF_6_f_inst_240 ( .A ( aps_rename_506_ ) , .X ( chanx_right_out[3] ) ) ; -sky130_fd_sc_hd__buf_6 ZBUF_6_f_inst_221 ( .A ( aps_rename_508_ ) , +sky130_fd_sc_hd__buf_6 ZBUF_6_f_inst_241 ( .A ( aps_rename_508_ ) , + .X ( chanx_left_out[5] ) ) ; +sky130_fd_sc_hd__buf_6 ZBUF_6_f_inst_242 ( .A ( aps_rename_507_ ) , + .X ( chanx_right_out[5] ) ) ; +sky130_fd_sc_hd__buf_6 ZBUF_6_f_inst_243 ( .A ( aps_rename_510_ ) , .X ( pReset_E_out ) ) ; -sky130_fd_sc_hd__buf_6 ZBUF_6_f_inst_222 ( .A ( aps_rename_506_ ) , - .X ( chanx_left_out[3] ) ) ; -sky130_fd_sc_hd__buf_8 ropt_mt_inst_1431 ( .A ( ropt_net_229 ) , +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1451 ( .A ( ropt_net_242 ) , .X ( chany_top_out[27] ) ) ; endmodule @@ -57713,7 +61710,7 @@ input [0:0] mem ; input [0:0] mem_inv ; output [0:0] out ; -sky130_fd_sc_hd__mux2_2 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) , +sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ; endmodule @@ -57761,8 +61758,6 @@ wire [0:0] mux_2level_tapbuf_basis_input2_mem1_2_out ; sb_0__2__const1 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( mux_2level_tapbuf_basis_input2_mem1_2_out[0] ) , .X ( out[0] ) ) ; sb_0__2__mux_2level_tapbuf_basis_input2_mem1_57 mux_l1_in_0_ ( .in ( in[0:1] ) , .mem ( sram[0] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_2 } ) , @@ -57778,6 +61773,9 @@ sb_0__2__mux_2level_tapbuf_basis_input2_mem1 mux_l2_in_0_ ( .mem ( sram[1] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_5 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_2_out ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_100 ( .A ( BUF_net_101 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_101 ( + .A ( mux_2level_tapbuf_basis_input2_mem1_2_out[0] ) , .Y ( BUF_net_101 ) ) ; endmodule @@ -57851,9 +61849,9 @@ sb_0__2__mux_2level_tapbuf_basis_input2_mem1_56 mux_l2_in_0_ ( .mem ( sram[1] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_5 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_2_out ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_92 ( .A ( BUF_net_93 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_93 ( - .A ( mux_2level_tapbuf_basis_input2_mem1_2_out[0] ) , .Y ( BUF_net_93 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_98 ( .A ( BUF_net_99 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_99 ( + .A ( mux_2level_tapbuf_basis_input2_mem1_2_out[0] ) , .Y ( BUF_net_99 ) ) ; endmodule @@ -57865,18 +61863,18 @@ input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -wire copt_net_111 ; +wire copt_net_129 ; sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( copt_net_111 ) ) ; + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( copt_net_129 ) ) ; sky130_fd_sc_hd__buf_6 FTB_45__44 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1289 ( .A ( copt_net_111 ) , - .X ( copt_net_109 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1290 ( .A ( copt_net_109 ) , - .X ( copt_net_110 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1291 ( .A ( copt_net_110 ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1311 ( .A ( copt_net_129 ) , + .X ( copt_net_127 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1312 ( .A ( copt_net_127 ) , + .X ( copt_net_128 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1313 ( .A ( copt_net_128 ) , .X ( mem_out[1] ) ) ; endmodule @@ -58339,8 +62337,6 @@ wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ; sb_0__2__const1_32 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) ) ; sb_0__2__mux_2level_tapbuf_basis_input2_mem1_52 mux_l1_in_0_ ( .in ( in ) , .mem ( sram[0] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_2 } ) , @@ -58351,6 +62347,8 @@ sb_0__2__mux_2level_tapbuf_basis_input2_mem1_53 mux_l2_in_0_ ( .mem ( sram[1] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_4 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_97 ( + .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) ) ; endmodule @@ -58419,7 +62417,7 @@ input [0:0] mem_inv ; output [0:0] out ; input p0 ; -sky130_fd_sc_hd__mux2_2 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , +sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ; endmodule @@ -58453,8 +62451,6 @@ wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ; sb_0__2__const1_30 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) ) ; sb_0__2__mux_2level_tapbuf_basis_input2_mem1_48 mux_l1_in_0_ ( .in ( in ) , .mem ( sram[0] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_2 } ) , @@ -58465,6 +62461,9 @@ sb_0__2__mux_2level_tapbuf_basis_input2_mem1_49 mux_l2_in_0_ ( .mem ( sram[1] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_4 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_95 ( .A ( BUF_net_96 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_96 ( + .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_96 ) ) ; endmodule @@ -58567,8 +62566,6 @@ wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ; sb_0__2__const1_28 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) ) ; sb_0__2__mux_2level_tapbuf_basis_input2_mem1_44 mux_l1_in_0_ ( .in ( in ) , .mem ( sram[0] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_2 } ) , @@ -58579,6 +62576,8 @@ sb_0__2__mux_2level_tapbuf_basis_input2_mem1_45 mux_l2_in_0_ ( .mem ( sram[1] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_4 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_94 ( + .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) ) ; endmodule @@ -58590,7 +62589,7 @@ input [0:0] mem_inv ; output [0:0] out ; input p0 ; -sky130_fd_sc_hd__mux2_2 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , +sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ; endmodule @@ -58681,6 +62680,8 @@ wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ; sb_0__2__const1_26 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) ) ; sb_0__2__mux_2level_tapbuf_basis_input2_mem1_40 mux_l1_in_0_ ( .in ( in ) , .mem ( sram[0] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_2 } ) , @@ -58691,9 +62692,6 @@ sb_0__2__mux_2level_tapbuf_basis_input2_mem1_41 mux_l2_in_0_ ( .mem ( sram[1] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_4 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_6 BINV_R_94 ( .A ( BUF_net_95 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_2 BINV_R_95 ( - .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_95 ) ) ; endmodule @@ -58749,9 +62747,9 @@ sb_0__2__mux_2level_tapbuf_basis_input2_mem1_39 mux_l2_in_0_ ( .mem ( sram[1] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_4 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_90 ( .A ( BUF_net_91 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_91 ( - .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_91 ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_92 ( .A ( BUF_net_93 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_93 ( + .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_93 ) ) ; endmodule @@ -58820,7 +62818,7 @@ input [0:0] mem_inv ; output [0:0] out ; input p0 ; -sky130_fd_sc_hd__mux2_2 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , +sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ; endmodule @@ -58854,8 +62852,6 @@ wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ; sb_0__2__const1_23 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) ) ; sb_0__2__mux_2level_tapbuf_basis_input2_mem1_34 mux_l1_in_0_ ( .in ( in ) , .mem ( sram[0] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_2 } ) , @@ -58866,6 +62862,9 @@ sb_0__2__mux_2level_tapbuf_basis_input2_mem1_35 mux_l2_in_0_ ( .mem ( sram[1] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_4 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_90 ( .A ( BUF_net_91 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_91 ( + .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_91 ) ) ; endmodule @@ -58934,7 +62933,7 @@ input [0:0] mem_inv ; output [0:0] out ; input p0 ; -sky130_fd_sc_hd__mux2_2 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , +sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ; endmodule @@ -58968,8 +62967,6 @@ wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ; sb_0__2__const1_21 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) ) ; sb_0__2__mux_2level_tapbuf_basis_input2_mem1_30 mux_l1_in_0_ ( .in ( in ) , .mem ( sram[0] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_2 } ) , @@ -58980,6 +62977,9 @@ sb_0__2__mux_2level_tapbuf_basis_input2_mem1_31 mux_l2_in_0_ ( .mem ( sram[1] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_4 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_88 ( .A ( BUF_net_89 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_89 ( + .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_89 ) ) ; endmodule @@ -58991,7 +62991,7 @@ input [0:0] mem_inv ; output [0:0] out ; input p0 ; -sky130_fd_sc_hd__mux2_2 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , +sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ; endmodule @@ -59025,8 +63025,6 @@ wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ; sb_0__2__const1_20 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) ) ; sb_0__2__mux_2level_tapbuf_basis_input2_mem1_28 mux_l1_in_0_ ( .in ( in ) , .mem ( sram[0] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_2 } ) , @@ -59037,6 +63035,9 @@ sb_0__2__mux_2level_tapbuf_basis_input2_mem1_29 mux_l2_in_0_ ( .mem ( sram[1] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_4 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_87 ( + .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_87 ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_110 ( .A ( BUF_net_87 ) , .Y ( out[0] ) ) ; endmodule @@ -59048,7 +63049,7 @@ input [0:0] mem_inv ; output [0:0] out ; input p0 ; -sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , +sky130_fd_sc_hd__mux2_2 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ; endmodule @@ -59082,6 +63083,8 @@ wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ; sb_0__2__const1_19 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) ) ; sb_0__2__mux_2level_tapbuf_basis_input2_mem1_26 mux_l1_in_0_ ( .in ( in ) , .mem ( sram[0] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_2 } ) , @@ -59092,9 +63095,6 @@ sb_0__2__mux_2level_tapbuf_basis_input2_mem1_27 mux_l2_in_0_ ( .mem ( sram[1] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_4 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_88 ( .A ( BUF_net_89 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_89 ( - .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_89 ) ) ; endmodule @@ -59207,9 +63207,9 @@ sb_0__2__mux_2level_tapbuf_basis_input2_mem1_23 mux_l2_in_0_ ( .mem ( sram[1] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_4 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_86 ( .A ( BUF_net_87 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_87 ( - .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_87 ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_85 ( + .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_85 ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_108 ( .A ( BUF_net_85 ) , .Y ( out[0] ) ) ; endmodule @@ -59265,9 +63265,9 @@ sb_0__2__mux_2level_tapbuf_basis_input2_mem1_21 mux_l2_in_0_ ( .mem ( sram[1] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_4 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_6 BINV_R_84 ( .A ( BUF_net_85 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_2 BINV_R_85 ( - .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_85 ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_104 ( .A ( BUF_net_105 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_105 ( + .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_105 ) ) ; endmodule @@ -59313,8 +63313,6 @@ wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ; sb_0__2__const1_15 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) ) ; sb_0__2__mux_2level_tapbuf_basis_input2_mem1_18 mux_l1_in_0_ ( .in ( in ) , .mem ( sram[0] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_2 } ) , @@ -59325,6 +63323,9 @@ sb_0__2__mux_2level_tapbuf_basis_input2_mem1_19 mux_l2_in_0_ ( .mem ( sram[1] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_4 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_83 ( + .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_83 ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_106 ( .A ( BUF_net_83 ) , .Y ( out[0] ) ) ; endmodule @@ -59380,9 +63381,9 @@ sb_0__2__mux_2level_tapbuf_basis_input2_mem1_17 mux_l2_in_0_ ( .mem ( sram[1] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_4 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_82 ( .A ( BUF_net_83 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_83 ( - .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_83 ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_80 ( .A ( BUF_net_81 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_81 ( + .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_81 ) ) ; endmodule @@ -59542,6 +63543,8 @@ wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ; sb_0__2__const1_11 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) ) ; sb_0__2__mux_2level_tapbuf_basis_input2_mem1_10 mux_l1_in_0_ ( .in ( in ) , .mem ( sram[0] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_2 } ) , @@ -59552,9 +63555,6 @@ sb_0__2__mux_2level_tapbuf_basis_input2_mem1_11 mux_l2_in_0_ ( .mem ( sram[1] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_4 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_80 ( .A ( BUF_net_81 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_81 ( - .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_81 ) ) ; endmodule @@ -59600,8 +63600,6 @@ wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ; sb_0__2__const1_10 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) ) ; sb_0__2__mux_2level_tapbuf_basis_input2_mem1_8 mux_l1_in_0_ ( .in ( in ) , .mem ( sram[0] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_2 } ) , @@ -59612,6 +63610,8 @@ sb_0__2__mux_2level_tapbuf_basis_input2_mem1_9 mux_l2_in_0_ ( .mem ( sram[1] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_4 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_79 ( + .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) ) ; endmodule @@ -59657,6 +63657,8 @@ wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ; sb_0__2__const1_9 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) ) ; sb_0__2__mux_2level_tapbuf_basis_input2_mem1_6 mux_l1_in_0_ ( .in ( in ) , .mem ( sram[0] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_2 } ) , @@ -59667,9 +63669,6 @@ sb_0__2__mux_2level_tapbuf_basis_input2_mem1_7 mux_l2_in_0_ ( .mem ( sram[1] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_4 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_6 BINV_R_78 ( .A ( BUF_net_79 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_2 BINV_R_79 ( - .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_79 ) ) ; endmodule @@ -59725,9 +63724,9 @@ sb_0__2__mux_2level_tapbuf_basis_input2_mem1_5 mux_l2_in_0_ ( .mem ( sram[1] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_4 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_6 BINV_R_76 ( .A ( BUF_net_77 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_2 BINV_R_77 ( - .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_77 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_77 ( .A ( BUF_net_78 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_78 ( + .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_78 ) ) ; endmodule @@ -59953,7 +63952,7 @@ input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ropt_net_180 ) , +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ropt_net_158 ) , .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; @@ -59962,24 +63961,24 @@ sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__buf_1 FTB_13__12 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1280 ( .A ( ccff_head[0] ) , - .X ( copt_net_100 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1281 ( .A ( copt_net_100 ) , - .X ( copt_net_101 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1282 ( .A ( copt_net_101 ) , - .X ( copt_net_102 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1283 ( .A ( copt_net_102 ) , - .X ( copt_net_103 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1284 ( .A ( copt_net_103 ) , - .X ( copt_net_104 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1285 ( .A ( copt_net_104 ) , - .X ( copt_net_105 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1357 ( .A ( ropt_net_179 ) , - .X ( ropt_net_178 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1358 ( .A ( copt_net_105 ) , - .X ( ropt_net_179 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1359 ( .A ( ropt_net_178 ) , - .X ( ropt_net_180 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1302 ( .A ( ccff_head[0] ) , + .X ( copt_net_118 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1303 ( .A ( copt_net_118 ) , + .X ( copt_net_119 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1304 ( .A ( copt_net_119 ) , + .X ( copt_net_120 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1305 ( .A ( copt_net_120 ) , + .X ( copt_net_121 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1306 ( .A ( copt_net_121 ) , + .X ( copt_net_122 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1307 ( .A ( copt_net_122 ) , + .X ( copt_net_123 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1341 ( .A ( ropt_net_160 ) , + .X ( ropt_net_158 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1342 ( .A ( copt_net_123 ) , + .X ( ropt_net_159 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1343 ( .A ( ropt_net_159 ) , + .X ( ropt_net_160 ) ) ; endmodule @@ -59991,10 +63990,14 @@ input [0:2] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -60005,10 +64008,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -60094,10 +64101,14 @@ input [0:2] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -60108,10 +64119,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -60197,10 +64212,14 @@ input [0:2] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -60211,10 +64230,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -60271,8 +64294,6 @@ wire [0:0] mux_2level_tapbuf_basis_input3_mem3_1_out ; sb_0__2__const1_3 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .X ( out[0] ) ) ; sb_0__2__local_encoder2to3_6 local_encoder2to3_0_ ( .addr ( sram[0:1] ) , .data ( local_encoder2to3_0_data ) , .data_inv ( local_encoder2to3_0_data_inv ) ) ; @@ -60289,6 +64310,9 @@ sb_0__2__mux_2level_tapbuf_basis_input3_mem3_7 mux_l2_in_0_ ( .mem ( local_encoder2to3_1_data ) , .mem_inv ( local_encoder2to3_1_data_inv ) , .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .p0 ( p0 ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_75 ( .A ( BUF_net_76 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_76 ( + .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_76 ) ) ; endmodule @@ -60300,10 +64324,14 @@ input [0:2] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -60314,10 +64342,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -60374,6 +64406,8 @@ wire [0:0] mux_2level_tapbuf_basis_input3_mem3_1_out ; sb_0__2__const1_2 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .X ( out[0] ) ) ; sb_0__2__local_encoder2to3_4 local_encoder2to3_0_ ( .addr ( sram[0:1] ) , .data ( local_encoder2to3_0_data ) , .data_inv ( local_encoder2to3_0_data_inv ) ) ; @@ -60390,9 +64424,6 @@ sb_0__2__mux_2level_tapbuf_basis_input3_mem3_5 mux_l2_in_0_ ( .mem ( local_encoder2to3_1_data ) , .mem_inv ( local_encoder2to3_1_data_inv ) , .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_6 BINV_R_74 ( .A ( BUF_net_75 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_75 ( - .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_75 ) ) ; endmodule @@ -60404,10 +64435,14 @@ input [0:2] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -60418,10 +64453,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -60507,10 +64546,14 @@ input [0:2] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -60521,10 +64564,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -60597,8 +64644,9 @@ sb_0__2__mux_2level_tapbuf_basis_input3_mem3_1 mux_l2_in_0_ ( .mem ( local_encoder2to3_1_data ) , .mem_inv ( local_encoder2to3_1_data_inv ) , .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_73 ( - .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_73 ( .A ( BUF_net_74 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_74 ( + .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_74 ) ) ; endmodule @@ -60633,8 +64681,6 @@ input pReset_E_in ; output pReset_S_out ; input prog_clk_0_E_in ; -wire ropt_net_134 ; -wire ropt_net_132 ; wire [0:0] prog_clk ; wire prog_clk_0 ; wire [0:1] mux_2level_tapbuf_size2_0_sram ; @@ -60715,42 +64761,42 @@ sb_0__2__mux_2level_tapbuf_size4_0 mux_right_track_0 ( .sram ( mux_2level_tapbuf_size4_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 , SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) , - .out ( chanx_right_out[0] ) , .p0 ( optlc_net_98 ) ) ; + .out ( chanx_right_out[0] ) , .p0 ( optlc_net_114 ) ) ; sb_0__2__mux_2level_tapbuf_size4_1 mux_right_track_2 ( .in ( { right_bottom_grid_pin_36_[0] , right_bottom_grid_pin_39_[0] , right_bottom_grid_pin_42_[0] , chany_bottom_in[27] } ) , .sram ( mux_2level_tapbuf_size4_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 , SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 } ) , - .out ( chanx_right_out[1] ) , .p0 ( optlc_net_96 ) ) ; + .out ( chanx_right_out[1] ) , .p0 ( optlc_net_113 ) ) ; sb_0__2__mux_2level_tapbuf_size4_2 mux_right_track_4 ( .in ( { right_bottom_grid_pin_37_[0] , right_bottom_grid_pin_40_[0] , right_bottom_grid_pin_43_[0] , chany_bottom_in[26] } ) , .sram ( mux_2level_tapbuf_size4_2_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_9 , SYNOPSYS_UNCONNECTED_10 , SYNOPSYS_UNCONNECTED_11 , SYNOPSYS_UNCONNECTED_12 } ) , - .out ( chanx_right_out[2] ) , .p0 ( optlc_net_96 ) ) ; + .out ( chanx_right_out[2] ) , .p0 ( optlc_net_113 ) ) ; sb_0__2__mux_2level_tapbuf_size4_3 mux_right_track_6 ( .in ( { right_top_grid_pin_1_[0] , right_bottom_grid_pin_38_[0] , right_bottom_grid_pin_41_[0] , chany_bottom_in[25] } ) , .sram ( mux_2level_tapbuf_size4_3_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 , SYNOPSYS_UNCONNECTED_15 , SYNOPSYS_UNCONNECTED_16 } ) , - .out ( chanx_right_out[3] ) , .p0 ( optlc_net_98 ) ) ; + .out ( chanx_right_out[3] ) , .p0 ( optlc_net_114 ) ) ; sb_0__2__mux_2level_tapbuf_size4_4 mux_right_track_8 ( .in ( { right_bottom_grid_pin_36_[0] , right_bottom_grid_pin_39_[0] , right_bottom_grid_pin_42_[0] , chany_bottom_in[24] } ) , .sram ( mux_2level_tapbuf_size4_4_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_17 , SYNOPSYS_UNCONNECTED_18 , SYNOPSYS_UNCONNECTED_19 , SYNOPSYS_UNCONNECTED_20 } ) , - .out ( chanx_right_out[4] ) , .p0 ( optlc_net_96 ) ) ; + .out ( chanx_right_out[4] ) , .p0 ( optlc_net_114 ) ) ; sb_0__2__mux_2level_tapbuf_size4 mux_right_track_10 ( .in ( { right_bottom_grid_pin_37_[0] , right_bottom_grid_pin_40_[0] , right_bottom_grid_pin_43_[0] , chany_bottom_in[23] } ) , .sram ( mux_2level_tapbuf_size4_5_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_21 , SYNOPSYS_UNCONNECTED_22 , SYNOPSYS_UNCONNECTED_23 , SYNOPSYS_UNCONNECTED_24 } ) , - .out ( chanx_right_out[5] ) , .p0 ( optlc_net_96 ) ) ; + .out ( chanx_right_out[5] ) , .p0 ( optlc_net_113 ) ) ; sb_0__2__mux_2level_tapbuf_size4_mem_0 mem_right_track_0 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( mux_2level_tapbuf_size4_mem_0_ccff_tail ) , @@ -60784,137 +64830,137 @@ sb_0__2__mux_2level_tapbuf_size2_0 mux_right_track_12 ( .in ( { right_top_grid_pin_1_[0] , chany_bottom_in[22] } ) , .sram ( mux_2level_tapbuf_size2_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_25 , SYNOPSYS_UNCONNECTED_26 } ) , - .out ( chanx_right_out[6] ) , .p0 ( optlc_net_96 ) ) ; + .out ( chanx_right_out[6] ) , .p0 ( optlc_net_116 ) ) ; sb_0__2__mux_2level_tapbuf_size2_1 mux_right_track_14 ( .in ( { right_bottom_grid_pin_36_[0] , chany_bottom_in[21] } ) , .sram ( mux_2level_tapbuf_size2_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_27 , SYNOPSYS_UNCONNECTED_28 } ) , - .out ( chanx_right_out[7] ) , .p0 ( optlc_net_96 ) ) ; + .out ( chanx_right_out[7] ) , .p0 ( optlc_net_113 ) ) ; sb_0__2__mux_2level_tapbuf_size2_2 mux_right_track_16 ( .in ( { right_bottom_grid_pin_37_[0] , chany_bottom_in[20] } ) , .sram ( mux_2level_tapbuf_size2_2_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_29 , SYNOPSYS_UNCONNECTED_30 } ) , - .out ( chanx_right_out[8] ) , .p0 ( optlc_net_96 ) ) ; + .out ( chanx_right_out[8] ) , .p0 ( optlc_net_115 ) ) ; sb_0__2__mux_2level_tapbuf_size2_3 mux_right_track_18 ( .in ( { right_bottom_grid_pin_38_[0] , chany_bottom_in[19] } ) , .sram ( mux_2level_tapbuf_size2_3_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_31 , SYNOPSYS_UNCONNECTED_32 } ) , - .out ( chanx_right_out[9] ) , .p0 ( optlc_net_96 ) ) ; + .out ( chanx_right_out[9] ) , .p0 ( optlc_net_116 ) ) ; sb_0__2__mux_2level_tapbuf_size2_4 mux_right_track_20 ( .in ( { right_bottom_grid_pin_39_[0] , chany_bottom_in[18] } ) , .sram ( mux_2level_tapbuf_size2_4_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_33 , SYNOPSYS_UNCONNECTED_34 } ) , - .out ( chanx_right_out[10] ) , .p0 ( optlc_net_99 ) ) ; + .out ( chanx_right_out[10] ) , .p0 ( optlc_net_115 ) ) ; sb_0__2__mux_2level_tapbuf_size2_5 mux_right_track_22 ( .in ( { right_bottom_grid_pin_40_[0] , chany_bottom_in[17] } ) , .sram ( mux_2level_tapbuf_size2_5_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_35 , SYNOPSYS_UNCONNECTED_36 } ) , - .out ( chanx_right_out[11] ) , .p0 ( optlc_net_97 ) ) ; + .out ( chanx_right_out[11] ) , .p0 ( optlc_net_114 ) ) ; sb_0__2__mux_2level_tapbuf_size2_6 mux_right_track_24 ( .in ( { right_bottom_grid_pin_41_[0] , chany_bottom_in[16] } ) , .sram ( mux_2level_tapbuf_size2_6_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_37 , SYNOPSYS_UNCONNECTED_38 } ) , - .out ( chanx_right_out[12] ) , .p0 ( optlc_net_99 ) ) ; + .out ( chanx_right_out[12] ) , .p0 ( optlc_net_114 ) ) ; sb_0__2__mux_2level_tapbuf_size2_7 mux_right_track_26 ( .in ( { right_bottom_grid_pin_42_[0] , chany_bottom_in[15] } ) , .sram ( mux_2level_tapbuf_size2_7_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_39 , SYNOPSYS_UNCONNECTED_40 } ) , - .out ( chanx_right_out[13] ) , .p0 ( optlc_net_99 ) ) ; + .out ( chanx_right_out[13] ) , .p0 ( optlc_net_114 ) ) ; sb_0__2__mux_2level_tapbuf_size2_8 mux_right_track_30 ( .in ( { right_bottom_grid_pin_36_[0] , chany_bottom_in[13] } ) , .sram ( mux_2level_tapbuf_size2_8_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_41 , SYNOPSYS_UNCONNECTED_42 } ) , - .out ( chanx_right_out[15] ) , .p0 ( optlc_net_96 ) ) ; + .out ( chanx_right_out[15] ) , .p0 ( optlc_net_117 ) ) ; sb_0__2__mux_2level_tapbuf_size2_9 mux_right_track_32 ( .in ( { right_bottom_grid_pin_37_[0] , chany_bottom_in[12] } ) , .sram ( mux_2level_tapbuf_size2_9_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_43 , SYNOPSYS_UNCONNECTED_44 } ) , - .out ( chanx_right_out[16] ) , .p0 ( optlc_net_97 ) ) ; + .out ( chanx_right_out[16] ) , .p0 ( optlc_net_116 ) ) ; sb_0__2__mux_2level_tapbuf_size2_10 mux_right_track_34 ( .in ( { right_bottom_grid_pin_38_[0] , chany_bottom_in[11] } ) , .sram ( mux_2level_tapbuf_size2_10_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_45 , SYNOPSYS_UNCONNECTED_46 } ) , - .out ( chanx_right_out[17] ) , .p0 ( optlc_net_97 ) ) ; + .out ( chanx_right_out[17] ) , .p0 ( optlc_net_116 ) ) ; sb_0__2__mux_2level_tapbuf_size2_11 mux_right_track_36 ( .in ( { right_bottom_grid_pin_39_[0] , chany_bottom_in[10] } ) , .sram ( mux_2level_tapbuf_size2_11_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_47 , SYNOPSYS_UNCONNECTED_48 } ) , - .out ( chanx_right_out[18] ) , .p0 ( optlc_net_99 ) ) ; + .out ( chanx_right_out[18] ) , .p0 ( optlc_net_117 ) ) ; sb_0__2__mux_2level_tapbuf_size2_12 mux_right_track_38 ( .in ( { right_bottom_grid_pin_40_[0] , chany_bottom_in[9] } ) , .sram ( mux_2level_tapbuf_size2_12_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_49 , SYNOPSYS_UNCONNECTED_50 } ) , - .out ( chanx_right_out[19] ) , .p0 ( optlc_net_99 ) ) ; + .out ( chanx_right_out[19] ) , .p0 ( optlc_net_117 ) ) ; sb_0__2__mux_2level_tapbuf_size2_13 mux_right_track_40 ( .in ( { right_bottom_grid_pin_41_[0] , chany_bottom_in[8] } ) , .sram ( mux_2level_tapbuf_size2_13_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_51 , SYNOPSYS_UNCONNECTED_52 } ) , - .out ( chanx_right_out[20] ) , .p0 ( optlc_net_99 ) ) ; + .out ( chanx_right_out[20] ) , .p0 ( optlc_net_117 ) ) ; sb_0__2__mux_2level_tapbuf_size2_14 mux_right_track_42 ( .in ( { right_bottom_grid_pin_42_[0] , chany_bottom_in[7] } ) , .sram ( mux_2level_tapbuf_size2_14_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_53 , SYNOPSYS_UNCONNECTED_54 } ) , - .out ( chanx_right_out[21] ) , .p0 ( optlc_net_99 ) ) ; + .out ( chanx_right_out[21] ) , .p0 ( optlc_net_116 ) ) ; sb_0__2__mux_2level_tapbuf_size2_15 mux_right_track_44 ( .in ( { right_top_grid_pin_1_[0] , chany_bottom_in[6] } ) , .sram ( mux_2level_tapbuf_size2_15_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_55 , SYNOPSYS_UNCONNECTED_56 } ) , - .out ( chanx_right_out[22] ) , .p0 ( optlc_net_99 ) ) ; + .out ( chanx_right_out[22] ) , .p0 ( optlc_net_116 ) ) ; sb_0__2__mux_2level_tapbuf_size2_16 mux_right_track_46 ( .in ( { right_bottom_grid_pin_36_[0] , chany_bottom_in[5] } ) , .sram ( mux_2level_tapbuf_size2_16_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_57 , SYNOPSYS_UNCONNECTED_58 } ) , - .out ( chanx_right_out[23] ) , .p0 ( optlc_net_99 ) ) ; + .out ( chanx_right_out[23] ) , .p0 ( optlc_net_117 ) ) ; sb_0__2__mux_2level_tapbuf_size2_17 mux_right_track_48 ( .in ( { right_bottom_grid_pin_37_[0] , chany_bottom_in[4] } ) , .sram ( mux_2level_tapbuf_size2_17_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_59 , SYNOPSYS_UNCONNECTED_60 } ) , - .out ( chanx_right_out[24] ) , .p0 ( optlc_net_99 ) ) ; + .out ( chanx_right_out[24] ) , .p0 ( optlc_net_116 ) ) ; sb_0__2__mux_2level_tapbuf_size2_18 mux_right_track_50 ( .in ( { right_bottom_grid_pin_38_[0] , chany_bottom_in[3] } ) , .sram ( mux_2level_tapbuf_size2_18_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_61 , SYNOPSYS_UNCONNECTED_62 } ) , - .out ( chanx_right_out[25] ) , .p0 ( optlc_net_99 ) ) ; + .out ( chanx_right_out[25] ) , .p0 ( optlc_net_115 ) ) ; sb_0__2__mux_2level_tapbuf_size2_19 mux_right_track_54 ( .in ( { right_bottom_grid_pin_40_[0] , chany_bottom_in[1] } ) , .sram ( mux_2level_tapbuf_size2_19_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_63 , SYNOPSYS_UNCONNECTED_64 } ) , - .out ( chanx_right_out[27] ) , .p0 ( optlc_net_98 ) ) ; + .out ( chanx_right_out[27] ) , .p0 ( optlc_net_114 ) ) ; sb_0__2__mux_2level_tapbuf_size2_20 mux_right_track_56 ( .in ( { right_bottom_grid_pin_41_[0] , chany_bottom_in[0] } ) , .sram ( mux_2level_tapbuf_size2_20_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_65 , SYNOPSYS_UNCONNECTED_66 } ) , - .out ( chanx_right_out[28] ) , .p0 ( optlc_net_96 ) ) ; + .out ( chanx_right_out[28] ) , .p0 ( optlc_net_114 ) ) ; sb_0__2__mux_2level_tapbuf_size2_21 mux_right_track_58 ( .in ( { right_bottom_grid_pin_42_[0] , chany_bottom_in[29] } ) , .sram ( mux_2level_tapbuf_size2_21_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_67 , SYNOPSYS_UNCONNECTED_68 } ) , - .out ( chanx_right_out[29] ) , .p0 ( optlc_net_99 ) ) ; + .out ( chanx_right_out[29] ) , .p0 ( optlc_net_113 ) ) ; sb_0__2__mux_2level_tapbuf_size2_22 mux_bottom_track_1 ( .in ( { chanx_right_in[28] , bottom_left_grid_pin_1_[0] } ) , .sram ( mux_2level_tapbuf_size2_22_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_69 , SYNOPSYS_UNCONNECTED_70 } ) , - .out ( chany_bottom_out[0] ) , .p0 ( optlc_net_97 ) ) ; + .out ( chany_bottom_out[0] ) , .p0 ( optlc_net_112 ) ) ; sb_0__2__mux_2level_tapbuf_size2_23 mux_bottom_track_7 ( .in ( { chanx_right_in[25] , bottom_left_grid_pin_1_[0] } ) , .sram ( mux_2level_tapbuf_size2_23_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_71 , SYNOPSYS_UNCONNECTED_72 } ) , - .out ( chany_bottom_out[3] ) , .p0 ( optlc_net_97 ) ) ; + .out ( chany_bottom_out[3] ) , .p0 ( optlc_net_112 ) ) ; sb_0__2__mux_2level_tapbuf_size2_24 mux_bottom_track_13 ( .in ( { chanx_right_in[22] , bottom_left_grid_pin_1_[0] } ) , .sram ( mux_2level_tapbuf_size2_24_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_73 , SYNOPSYS_UNCONNECTED_74 } ) , - .out ( chany_bottom_out[6] ) , .p0 ( optlc_net_97 ) ) ; + .out ( chany_bottom_out[6] ) , .p0 ( optlc_net_112 ) ) ; sb_0__2__mux_2level_tapbuf_size2_25 mux_bottom_track_29 ( .in ( { chanx_right_in[14] , bottom_left_grid_pin_1_[0] } ) , .sram ( mux_2level_tapbuf_size2_25_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_75 , SYNOPSYS_UNCONNECTED_76 } ) , - .out ( chany_bottom_out[14] ) , .p0 ( optlc_net_97 ) ) ; + .out ( chany_bottom_out[14] ) , .p0 ( optlc_net_112 ) ) ; sb_0__2__mux_2level_tapbuf_size2 mux_bottom_track_45 ( .in ( { chanx_right_in[6] , bottom_left_grid_pin_1_[0] } ) , .sram ( mux_2level_tapbuf_size2_26_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_77 , SYNOPSYS_UNCONNECTED_78 } ) , - .out ( chany_bottom_out[22] ) , .p0 ( optlc_net_97 ) ) ; + .out ( chany_bottom_out[22] ) , .p0 ( optlc_net_112 ) ) ; sb_0__2__mux_2level_tapbuf_size2_mem_0 mem_right_track_12 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( mux_2level_tapbuf_size4_mem_5_ccff_tail ) , @@ -61054,13 +65100,13 @@ sb_0__2__mux_2level_tapbuf_size3_0 mux_right_track_28 ( chany_bottom_in[14] } ) , .sram ( mux_2level_tapbuf_size3_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_79 , SYNOPSYS_UNCONNECTED_80 } ) , - .out ( chanx_right_out[14] ) , .p0 ( optlc_net_99 ) ) ; + .out ( chanx_right_out[14] ) , .p0 ( optlc_net_115 ) ) ; sb_0__2__mux_2level_tapbuf_size3 mux_right_track_52 ( .in ( { right_bottom_grid_pin_39_[0] , right_bottom_grid_pin_43_[0] , chany_bottom_in[2] } ) , .sram ( mux_2level_tapbuf_size3_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_81 , SYNOPSYS_UNCONNECTED_82 } ) , - .out ( chanx_right_out[26] ) , .p0 ( optlc_net_96 ) ) ; + .out ( chanx_right_out[26] ) , .p0 ( optlc_net_114 ) ) ; sb_0__2__mux_2level_tapbuf_size3_mem_0 mem_right_track_28 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( mux_2level_tapbuf_size2_mem_7_ccff_tail ) , @@ -61072,8 +65118,8 @@ sb_0__2__mux_2level_tapbuf_size3_mem mem_right_track_52 ( .pReset ( pReset ) , .ccff_tail ( mux_2level_tapbuf_size3_mem_1_ccff_tail ) , .mem_out ( mux_2level_tapbuf_size3_1_sram ) ) ; sky130_fd_sc_hd__buf_8 pReset_FTB00 ( .A ( pReset_E_in ) , .X ( pReset[0] ) ) ; -sky130_fd_sc_hd__buf_6 pReset_S_FTB01 ( .A ( pReset_E_in ) , - .X ( pReset_S_out ) ) ; +sky130_fd_sc_hd__conb_1 optlc_115 ( .LO ( SYNOPSYS_UNCONNECTED_83 ) , + .HI ( optlc_net_112 ) ) ; sky130_fd_sc_hd__buf_1 prog_clk_0_FTB00 ( .A ( prog_clk_0_E_in ) , .X ( prog_clk[0] ) ) ; sky130_fd_sc_hd__buf_8 FTB_48__47 ( .A ( chanx_right_in[0] ) , @@ -61096,16 +65142,16 @@ sky130_fd_sc_hd__buf_8 FTB_56__55 ( .A ( chanx_right_in[9] ) , .X ( chany_bottom_out[19] ) ) ; sky130_fd_sc_hd__buf_8 FTB_57__56 ( .A ( chanx_right_in[10] ) , .X ( chany_bottom_out[18] ) ) ; -sky130_fd_sc_hd__buf_6 FTB_58__57 ( .A ( chanx_right_in[11] ) , - .X ( ropt_net_134 ) ) ; +sky130_fd_sc_hd__buf_8 FTB_58__57 ( .A ( chanx_right_in[11] ) , + .X ( chany_bottom_out[17] ) ) ; sky130_fd_sc_hd__buf_8 FTB_59__58 ( .A ( chanx_right_in[12] ) , .X ( chany_bottom_out[16] ) ) ; sky130_fd_sc_hd__buf_8 FTB_60__59 ( .A ( chanx_right_in[13] ) , .X ( chany_bottom_out[15] ) ) ; sky130_fd_sc_hd__buf_8 FTB_61__60 ( .A ( chanx_right_in[15] ) , .X ( chany_bottom_out[13] ) ) ; -sky130_fd_sc_hd__buf_6 FTB_62__61 ( .A ( chanx_right_in[16] ) , - .X ( ropt_net_132 ) ) ; +sky130_fd_sc_hd__buf_8 FTB_62__61 ( .A ( chanx_right_in[16] ) , + .X ( chany_bottom_out[12] ) ) ; sky130_fd_sc_hd__buf_8 FTB_63__62 ( .A ( chanx_right_in[17] ) , .X ( chany_bottom_out[11] ) ) ; sky130_fd_sc_hd__buf_8 FTB_64__63 ( .A ( chanx_right_in[18] ) , @@ -61120,25 +65166,25 @@ sky130_fd_sc_hd__buf_8 FTB_68__67 ( .A ( chanx_right_in[23] ) , .X ( chany_bottom_out[5] ) ) ; sky130_fd_sc_hd__buf_8 FTB_69__68 ( .A ( chanx_right_in[24] ) , .X ( chany_bottom_out[4] ) ) ; -sky130_fd_sc_hd__buf_8 FTB_70__69 ( .A ( chanx_right_in[26] ) , +sky130_fd_sc_hd__buf_6 FTB_70__69 ( .A ( chanx_right_in[26] ) , .X ( chany_bottom_out[2] ) ) ; sky130_fd_sc_hd__buf_8 FTB_71__70 ( .A ( chanx_right_in[27] ) , .X ( chany_bottom_out[1] ) ) ; sky130_fd_sc_hd__buf_8 FTB_72__71 ( .A ( chanx_right_in[29] ) , .X ( chany_bottom_out[29] ) ) ; sky130_fd_sc_hd__buf_6 FTB_73__72 ( .A ( SC_IN_TOP ) , .X ( SC_OUT_BOT ) ) ; -sky130_fd_sc_hd__conb_1 optlc_98 ( .LO ( SYNOPSYS_UNCONNECTED_83 ) , - .HI ( optlc_net_96 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_100 ( .LO ( SYNOPSYS_UNCONNECTED_84 ) , - .HI ( optlc_net_97 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_102 ( .LO ( SYNOPSYS_UNCONNECTED_85 ) , - .HI ( optlc_net_98 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_104 ( .LO ( SYNOPSYS_UNCONNECTED_86 ) , - .HI ( optlc_net_99 ) ) ; -sky130_fd_sc_hd__buf_8 ropt_mt_inst_1311 ( .A ( ropt_net_132 ) , - .X ( chany_bottom_out[12] ) ) ; -sky130_fd_sc_hd__buf_8 ropt_mt_inst_1313 ( .A ( ropt_net_134 ) , - .X ( chany_bottom_out[17] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_102 ( .A ( BUF_net_103 ) , .Y ( pReset_S_out ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_103 ( .A ( pReset_E_in ) , .Y ( BUF_net_103 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_117 ( .LO ( SYNOPSYS_UNCONNECTED_84 ) , + .HI ( optlc_net_113 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_119 ( .LO ( SYNOPSYS_UNCONNECTED_85 ) , + .HI ( optlc_net_114 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_122 ( .LO ( SYNOPSYS_UNCONNECTED_86 ) , + .HI ( optlc_net_115 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_124 ( .LO ( SYNOPSYS_UNCONNECTED_87 ) , + .HI ( optlc_net_116 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_126 ( .LO ( SYNOPSYS_UNCONNECTED_88 ) , + .HI ( optlc_net_117 ) ) ; endmodule @@ -61330,9 +65376,9 @@ sb_0__1__mux_2level_tapbuf_basis_input2_mem1 mux_l2_in_0_ ( .mem ( sram[1] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_4 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_216 ( .A ( BUF_net_217 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_217 ( - .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_217 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_209 ( .A ( BUF_net_210 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_210 ( + .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_210 ) ) ; endmodule @@ -61445,9 +65491,9 @@ sb_0__1__mux_2level_tapbuf_basis_input2_mem1_41 mux_l2_in_0_ ( .mem ( sram[1] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_4 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_214 ( .A ( BUF_net_215 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_215 ( - .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_215 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_201 ( .A ( BUF_net_202 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_202 ( + .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_202 ) ) ; endmodule @@ -61617,9 +65663,9 @@ sb_0__1__mux_2level_tapbuf_basis_input2_mem1_35 mux_l2_in_0_ ( .mem ( sram[1] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_4 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_212 ( .A ( BUF_net_213 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_213 ( - .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_213 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_199 ( .A ( BUF_net_200 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_200 ( + .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_200 ) ) ; endmodule @@ -61675,9 +65721,9 @@ sb_0__1__mux_2level_tapbuf_basis_input2_mem1_33 mux_l2_in_0_ ( .mem ( sram[1] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_4 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_210 ( .A ( BUF_net_211 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_211 ( - .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_211 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_197 ( .A ( BUF_net_198 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_198 ( + .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_198 ) ) ; endmodule @@ -61723,8 +65769,6 @@ wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ; sb_0__1__const1_42 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) ) ; sb_0__1__mux_2level_tapbuf_basis_input2_mem1_30 mux_l1_in_0_ ( .in ( in ) , .mem ( sram[0] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_2 } ) , @@ -61735,6 +65779,9 @@ sb_0__1__mux_2level_tapbuf_basis_input2_mem1_31 mux_l2_in_0_ ( .mem ( sram[1] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_4 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_195 ( .A ( BUF_net_196 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_196 ( + .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_196 ) ) ; endmodule @@ -62061,7 +66108,7 @@ input [0:0] mem ; input [0:0] mem_inv ; output [0:0] out ; -sky130_fd_sc_hd__mux2_2 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) , +sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ; endmodule @@ -62124,8 +66171,9 @@ sb_0__1__mux_2level_tapbuf_basis_input2_mem1_23 mux_l2_in_0_ ( .mem ( sram[1] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_5 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_2_out ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_209 ( - .A ( mux_2level_tapbuf_basis_input2_mem1_2_out[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_193 ( .A ( BUF_net_194 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_194 ( + .A ( mux_2level_tapbuf_basis_input2_mem1_2_out[0] ) , .Y ( BUF_net_194 ) ) ; endmodule @@ -62184,6 +66232,8 @@ wire [0:0] mux_2level_tapbuf_basis_input2_mem1_2_out ; sb_0__1__const1_38 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( mux_2level_tapbuf_basis_input2_mem1_2_out[0] ) , .X ( out[0] ) ) ; sb_0__1__mux_2level_tapbuf_basis_input2_mem1_18 mux_l1_in_0_ ( .in ( in[0:1] ) , .mem ( sram[0] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_2 } ) , @@ -62199,8 +66249,6 @@ sb_0__1__mux_2level_tapbuf_basis_input2_mem1_20 mux_l2_in_0_ ( .mem ( sram[1] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_5 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_2_out ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_208 ( - .A ( mux_2level_tapbuf_basis_input2_mem1_2_out[0] ) , .X ( out[0] ) ) ; endmodule @@ -62211,7 +66259,7 @@ input [0:0] mem ; input [0:0] mem_inv ; output [0:0] out ; -sky130_fd_sc_hd__mux2_2 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) , +sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ; endmodule @@ -62259,8 +66307,6 @@ wire [0:0] mux_2level_tapbuf_basis_input2_mem1_2_out ; sb_0__1__const1_37 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( mux_2level_tapbuf_basis_input2_mem1_2_out[0] ) , .X ( out[0] ) ) ; sb_0__1__mux_2level_tapbuf_basis_input2_mem1_15 mux_l1_in_0_ ( .in ( in[0:1] ) , .mem ( sram[0] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_2 } ) , @@ -62276,6 +66322,9 @@ sb_0__1__mux_2level_tapbuf_basis_input2_mem1_17 mux_l2_in_0_ ( .mem ( sram[1] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_5 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_2_out ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_213 ( .A ( BUF_net_214 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_214 ( + .A ( mux_2level_tapbuf_basis_input2_mem1_2_out[0] ) , .Y ( BUF_net_214 ) ) ; endmodule @@ -62286,7 +66335,7 @@ input [0:0] mem ; input [0:0] mem_inv ; output [0:0] out ; -sky130_fd_sc_hd__mux2_2 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) , +sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ; endmodule @@ -62334,8 +66383,6 @@ wire [0:0] mux_2level_tapbuf_basis_input2_mem1_2_out ; sb_0__1__const1_36 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( mux_2level_tapbuf_basis_input2_mem1_2_out[0] ) , .X ( out[0] ) ) ; sb_0__1__mux_2level_tapbuf_basis_input2_mem1_12 mux_l1_in_0_ ( .in ( in[0:1] ) , .mem ( sram[0] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_2 } ) , @@ -62351,6 +66398,9 @@ sb_0__1__mux_2level_tapbuf_basis_input2_mem1_14 mux_l2_in_0_ ( .mem ( sram[1] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_5 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_2_out ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_191 ( .A ( BUF_net_192 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_192 ( + .A ( mux_2level_tapbuf_basis_input2_mem1_2_out[0] ) , .Y ( BUF_net_192 ) ) ; endmodule @@ -62361,7 +66411,7 @@ input [0:0] mem ; input [0:0] mem_inv ; output [0:0] out ; -sky130_fd_sc_hd__mux2_2 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) , +sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ; endmodule @@ -62424,8 +66474,9 @@ sb_0__1__mux_2level_tapbuf_basis_input2_mem1_11 mux_l2_in_0_ ( .mem ( sram[1] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_5 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_2_out ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_207 ( - .A ( mux_2level_tapbuf_basis_input2_mem1_2_out[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_207 ( .A ( BUF_net_208 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_208 ( + .A ( mux_2level_tapbuf_basis_input2_mem1_2_out[0] ) , .Y ( BUF_net_208 ) ) ; endmodule @@ -62436,7 +66487,7 @@ input [0:0] mem ; input [0:0] mem_inv ; output [0:0] out ; -sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) , +sky130_fd_sc_hd__mux2_2 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ; endmodule @@ -62484,6 +66535,8 @@ wire [0:0] mux_2level_tapbuf_basis_input2_mem1_2_out ; sb_0__1__const1_34 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( mux_2level_tapbuf_basis_input2_mem1_2_out[0] ) , .X ( out[0] ) ) ; sb_0__1__mux_2level_tapbuf_basis_input2_mem1_6 mux_l1_in_0_ ( .in ( in[0:1] ) , .mem ( sram[0] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_2 } ) , @@ -62499,9 +66552,6 @@ sb_0__1__mux_2level_tapbuf_basis_input2_mem1_8 mux_l2_in_0_ ( .mem ( sram[1] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_5 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_2_out ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_205 ( .A ( BUF_net_206 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_206 ( - .A ( mux_2level_tapbuf_basis_input2_mem1_2_out[0] ) , .Y ( BUF_net_206 ) ) ; endmodule @@ -62560,6 +66610,8 @@ wire [0:0] mux_2level_tapbuf_basis_input2_mem1_2_out ; sb_0__1__const1_33 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( mux_2level_tapbuf_basis_input2_mem1_2_out[0] ) , .X ( out[0] ) ) ; sb_0__1__mux_2level_tapbuf_basis_input2_mem1_3 mux_l1_in_0_ ( .in ( in[0:1] ) , .mem ( sram[0] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_2 } ) , @@ -62575,9 +66627,6 @@ sb_0__1__mux_2level_tapbuf_basis_input2_mem1_5 mux_l2_in_0_ ( .mem ( sram[1] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_5 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_2_out ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_203 ( .A ( BUF_net_204 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_204 ( - .A ( mux_2level_tapbuf_basis_input2_mem1_2_out[0] ) , .Y ( BUF_net_204 ) ) ; endmodule @@ -62636,6 +66685,8 @@ wire [0:0] mux_2level_tapbuf_basis_input2_mem1_2_out ; sb_0__1__const1_32 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( mux_2level_tapbuf_basis_input2_mem1_2_out[0] ) , .X ( out[0] ) ) ; sb_0__1__mux_2level_tapbuf_basis_input2_mem1_0 mux_l1_in_0_ ( .in ( in[0:1] ) , .mem ( sram[0] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_2 } ) , @@ -62651,9 +66702,6 @@ sb_0__1__mux_2level_tapbuf_basis_input2_mem1_2 mux_l2_in_0_ ( .mem ( sram[1] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_5 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_2_out ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_201 ( .A ( BUF_net_202 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_202 ( - .A ( mux_2level_tapbuf_basis_input2_mem1_2_out[0] ) , .Y ( BUF_net_202 ) ) ; endmodule @@ -62905,10 +66953,14 @@ input [0:2] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -62919,10 +66971,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -62979,6 +67035,8 @@ wire [0:0] mux_2level_tapbuf_basis_input3_mem3_1_out ; sb_0__1__const1_31 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .X ( out[0] ) ) ; sb_0__1__local_encoder2to3_62 local_encoder2to3_0_ ( .addr ( sram[0:1] ) , .data ( local_encoder2to3_0_data ) , .data_inv ( local_encoder2to3_0_data_inv ) ) ; @@ -62995,9 +67053,6 @@ sb_0__1__mux_2level_tapbuf_basis_input3_mem3 mux_l2_in_0_ ( .mem ( local_encoder2to3_1_data ) , .mem_inv ( local_encoder2to3_1_data_inv ) , .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_199 ( .A ( BUF_net_200 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_200 ( - .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_200 ) ) ; endmodule @@ -63009,10 +67064,14 @@ input [0:2] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -63023,10 +67082,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -63112,10 +67175,14 @@ input [0:2] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -63126,10 +67193,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -63186,8 +67257,6 @@ wire [0:0] mux_2level_tapbuf_basis_input3_mem3_1_out ; sb_0__1__const1_29 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .X ( out[0] ) ) ; sb_0__1__local_encoder2to3_58 local_encoder2to3_0_ ( .addr ( sram[0:1] ) , .data ( local_encoder2to3_0_data ) , .data_inv ( local_encoder2to3_0_data_inv ) ) ; @@ -63204,6 +67273,9 @@ sb_0__1__mux_2level_tapbuf_basis_input3_mem3_67 mux_l2_in_0_ ( .mem ( local_encoder2to3_1_data ) , .mem_inv ( local_encoder2to3_1_data_inv ) , .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .p0 ( p0 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_189 ( .A ( BUF_net_190 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_190 ( + .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_190 ) ) ; endmodule @@ -63215,10 +67287,14 @@ input [0:2] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -63229,10 +67305,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -63289,6 +67369,8 @@ wire [0:0] mux_2level_tapbuf_basis_input3_mem3_1_out ; sb_0__1__const1_28 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .X ( out[0] ) ) ; sb_0__1__local_encoder2to3_56 local_encoder2to3_0_ ( .addr ( sram[0:1] ) , .data ( local_encoder2to3_0_data ) , .data_inv ( local_encoder2to3_0_data_inv ) ) ; @@ -63305,9 +67387,6 @@ sb_0__1__mux_2level_tapbuf_basis_input3_mem3_65 mux_l2_in_0_ ( .mem ( local_encoder2to3_1_data ) , .mem_inv ( local_encoder2to3_1_data_inv ) , .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_197 ( .A ( BUF_net_198 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_198 ( - .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_198 ) ) ; endmodule @@ -63319,10 +67398,14 @@ input [0:2] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -63333,10 +67416,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -63409,9 +67496,8 @@ sb_0__1__mux_2level_tapbuf_basis_input3_mem3_63 mux_l2_in_0_ ( .mem ( local_encoder2to3_1_data ) , .mem_inv ( local_encoder2to3_1_data_inv ) , .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_195 ( .A ( BUF_net_196 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_196 ( - .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_196 ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_188 ( + .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .X ( out[0] ) ) ; endmodule @@ -63423,10 +67509,14 @@ input [0:2] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -63437,10 +67527,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -63513,9 +67607,9 @@ sb_0__1__mux_2level_tapbuf_basis_input3_mem3_61 mux_l2_in_0_ ( .mem ( local_encoder2to3_1_data ) , .mem_inv ( local_encoder2to3_1_data_inv ) , .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_193 ( .A ( BUF_net_194 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_194 ( - .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_194 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_186 ( .A ( BUF_net_187 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_187 ( + .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_187 ) ) ; endmodule @@ -63527,10 +67621,14 @@ input [0:2] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -63541,10 +67639,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -63617,9 +67719,9 @@ sb_0__1__mux_2level_tapbuf_basis_input3_mem3_59 mux_l2_in_0_ ( .mem ( local_encoder2to3_1_data ) , .mem_inv ( local_encoder2to3_1_data_inv ) , .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_191 ( .A ( BUF_net_192 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_192 ( - .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_192 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_184 ( .A ( BUF_net_185 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_185 ( + .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_185 ) ) ; endmodule @@ -63631,10 +67733,14 @@ input [0:2] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -63645,10 +67751,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -63721,9 +67831,9 @@ sb_0__1__mux_2level_tapbuf_basis_input3_mem3_57 mux_l2_in_0_ ( .mem ( local_encoder2to3_1_data ) , .mem_inv ( local_encoder2to3_1_data_inv ) , .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_189 ( .A ( BUF_net_190 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_190 ( - .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_190 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_182 ( .A ( BUF_net_183 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_183 ( + .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_183 ) ) ; endmodule @@ -63735,10 +67845,14 @@ input [0:2] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -63749,10 +67863,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -63825,9 +67943,9 @@ sb_0__1__mux_2level_tapbuf_basis_input3_mem3_55 mux_l2_in_0_ ( .mem ( local_encoder2to3_1_data ) , .mem_inv ( local_encoder2to3_1_data_inv ) , .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_187 ( .A ( BUF_net_188 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_188 ( - .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_188 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_180 ( .A ( BUF_net_181 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_181 ( + .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_181 ) ) ; endmodule @@ -63839,10 +67957,14 @@ input [0:2] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -63853,10 +67975,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -63929,9 +68055,9 @@ sb_0__1__mux_2level_tapbuf_basis_input3_mem3_53 mux_l2_in_0_ ( .mem ( local_encoder2to3_1_data ) , .mem_inv ( local_encoder2to3_1_data_inv ) , .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_185 ( .A ( BUF_net_186 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_186 ( - .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_186 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_178 ( .A ( BUF_net_179 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_179 ( + .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_179 ) ) ; endmodule @@ -63943,10 +68069,14 @@ input [0:2] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -63957,10 +68087,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -64017,6 +68151,8 @@ wire [0:0] mux_2level_tapbuf_basis_input3_mem3_1_out ; sb_0__1__const1_21 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .X ( out[0] ) ) ; sb_0__1__local_encoder2to3_42 local_encoder2to3_0_ ( .addr ( sram[0:1] ) , .data ( local_encoder2to3_0_data ) , .data_inv ( local_encoder2to3_0_data_inv ) ) ; @@ -64033,8 +68169,6 @@ sb_0__1__mux_2level_tapbuf_basis_input3_mem3_51 mux_l2_in_0_ ( .mem ( local_encoder2to3_1_data ) , .mem_inv ( local_encoder2to3_1_data_inv ) , .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_184 ( - .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .X ( out[0] ) ) ; endmodule @@ -64046,10 +68180,14 @@ input [0:2] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -64060,10 +68198,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -64136,9 +68278,8 @@ sb_0__1__mux_2level_tapbuf_basis_input3_mem3_49 mux_l2_in_0_ ( .mem ( local_encoder2to3_1_data ) , .mem_inv ( local_encoder2to3_1_data_inv ) , .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_182 ( .A ( BUF_net_183 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_183 ( - .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_183 ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_177 ( + .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .X ( out[0] ) ) ; endmodule @@ -64389,9 +68530,13 @@ input [0:1] mem ; input [0:1] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -64403,10 +68548,14 @@ input [0:2] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -64417,10 +68566,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -64478,8 +68631,6 @@ wire [0:0] mux_2level_tapbuf_basis_input3_mem3_1_out ; sb_0__1__const1_19 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .X ( out[0] ) ) ; sb_0__1__local_encoder2to3_38 local_encoder2to3_0_ ( .addr ( sram[0:1] ) , .data ( local_encoder2to3_0_data ) , .data_inv ( local_encoder2to3_0_data_inv ) ) ; @@ -64501,6 +68652,9 @@ sb_0__1__mux_2level_tapbuf_basis_input2_mem2 mux_l1_in_1_ ( .in ( in[3:4] ) , .mem ( local_encoder2to3_0_data[0:1] ) , .mem_inv ( local_encoder2to3_0_data_inv[0:1] ) , .out ( mux_2level_tapbuf_basis_input2_mem2_0_out ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_205 ( .A ( BUF_net_206 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_206 ( + .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_206 ) ) ; endmodule @@ -64511,9 +68665,13 @@ input [0:1] mem ; input [0:1] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -64525,10 +68683,14 @@ input [0:2] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -64539,10 +68701,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -64633,9 +68799,13 @@ input [0:1] mem ; input [0:1] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -64647,10 +68817,14 @@ input [0:2] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -64661,10 +68835,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -64743,9 +68921,9 @@ sb_0__1__mux_2level_tapbuf_basis_input2_mem2_9 mux_l1_in_1_ ( .in ( in[3:4] ) , .mem ( local_encoder2to3_0_data[0:1] ) , .mem_inv ( local_encoder2to3_0_data_inv[0:1] ) , .out ( mux_2level_tapbuf_basis_input2_mem2_0_out ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_180 ( .A ( BUF_net_181 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_181 ( - .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_181 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_175 ( .A ( BUF_net_176 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_176 ( + .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_176 ) ) ; endmodule @@ -64756,9 +68934,13 @@ input [0:1] mem ; input [0:1] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -64770,10 +68952,14 @@ input [0:2] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -64784,10 +68970,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -64866,9 +69056,9 @@ sb_0__1__mux_2level_tapbuf_basis_input2_mem2_8 mux_l1_in_1_ ( .in ( in[3:4] ) , .mem ( local_encoder2to3_0_data[0:1] ) , .mem_inv ( local_encoder2to3_0_data_inv[0:1] ) , .out ( mux_2level_tapbuf_basis_input2_mem2_0_out ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_178 ( .A ( BUF_net_179 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_179 ( - .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_179 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_173 ( .A ( BUF_net_174 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_174 ( + .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_174 ) ) ; endmodule @@ -64879,9 +69069,13 @@ input [0:1] mem ; input [0:1] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -64893,10 +69087,14 @@ input [0:2] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -64907,10 +69105,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -65001,9 +69203,13 @@ input [0:1] mem ; input [0:1] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -65015,10 +69221,14 @@ input [0:2] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -65029,10 +69239,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -65111,9 +69325,9 @@ sb_0__1__mux_2level_tapbuf_basis_input2_mem2_6 mux_l1_in_1_ ( .in ( in[3:4] ) , .mem ( local_encoder2to3_0_data[0:1] ) , .mem_inv ( local_encoder2to3_0_data_inv[0:1] ) , .out ( mux_2level_tapbuf_basis_input2_mem2_0_out ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_176 ( .A ( BUF_net_177 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_177 ( - .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_177 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_171 ( .A ( BUF_net_172 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_172 ( + .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_172 ) ) ; endmodule @@ -65124,9 +69338,13 @@ input [0:1] mem ; input [0:1] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -65138,10 +69356,14 @@ input [0:2] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -65152,10 +69374,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -65234,9 +69460,9 @@ sb_0__1__mux_2level_tapbuf_basis_input2_mem2_5 mux_l1_in_1_ ( .in ( in[3:4] ) , .mem ( local_encoder2to3_0_data[0:1] ) , .mem_inv ( local_encoder2to3_0_data_inv[0:1] ) , .out ( mux_2level_tapbuf_basis_input2_mem2_0_out ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_174 ( .A ( BUF_net_175 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_175 ( - .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_175 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_169 ( .A ( BUF_net_170 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_170 ( + .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_170 ) ) ; endmodule @@ -65247,9 +69473,13 @@ input [0:1] mem ; input [0:1] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -65261,10 +69491,14 @@ input [0:2] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -65275,10 +69509,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -65357,9 +69595,8 @@ sb_0__1__mux_2level_tapbuf_basis_input2_mem2_4 mux_l1_in_1_ ( .in ( in[3:4] ) , .mem ( local_encoder2to3_0_data[0:1] ) , .mem_inv ( local_encoder2to3_0_data_inv[0:1] ) , .out ( mux_2level_tapbuf_basis_input2_mem2_0_out ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_172 ( .A ( BUF_net_173 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_173 ( - .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_173 ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_168 ( + .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .X ( out[0] ) ) ; endmodule @@ -65370,9 +69607,13 @@ input [0:1] mem ; input [0:1] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -65384,10 +69625,14 @@ input [0:2] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -65398,10 +69643,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -65459,8 +69708,6 @@ wire [0:0] mux_2level_tapbuf_basis_input3_mem3_1_out ; sb_0__1__const1_11 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .X ( out[0] ) ) ; sb_0__1__local_encoder2to3_22 local_encoder2to3_0_ ( .addr ( sram[0:1] ) , .data ( local_encoder2to3_0_data ) , .data_inv ( local_encoder2to3_0_data_inv ) ) ; @@ -65482,6 +69729,9 @@ sb_0__1__mux_2level_tapbuf_basis_input2_mem2_3 mux_l1_in_1_ ( .in ( in[3:4] ) , .mem ( local_encoder2to3_0_data[0:1] ) , .mem_inv ( local_encoder2to3_0_data_inv[0:1] ) , .out ( mux_2level_tapbuf_basis_input2_mem2_0_out ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_166 ( .A ( BUF_net_167 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_167 ( + .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_167 ) ) ; endmodule @@ -65492,9 +69742,13 @@ input [0:1] mem ; input [0:1] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -65506,10 +69760,14 @@ input [0:2] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -65520,10 +69778,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -65602,9 +69864,9 @@ sb_0__1__mux_2level_tapbuf_basis_input2_mem2_2 mux_l1_in_1_ ( .in ( in[3:4] ) , .mem ( local_encoder2to3_0_data[0:1] ) , .mem_inv ( local_encoder2to3_0_data_inv[0:1] ) , .out ( mux_2level_tapbuf_basis_input2_mem2_0_out ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_170 ( .A ( BUF_net_171 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_171 ( - .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_171 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_164 ( .A ( BUF_net_165 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_165 ( + .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_165 ) ) ; endmodule @@ -65615,9 +69877,13 @@ input [0:1] mem ; input [0:1] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -65629,10 +69895,14 @@ input [0:2] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -65643,10 +69913,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -65725,9 +69999,8 @@ sb_0__1__mux_2level_tapbuf_basis_input2_mem2_1 mux_l1_in_1_ ( .in ( in[3:4] ) , .mem ( local_encoder2to3_0_data[0:1] ) , .mem_inv ( local_encoder2to3_0_data_inv[0:1] ) , .out ( mux_2level_tapbuf_basis_input2_mem2_0_out ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_168 ( .A ( BUF_net_169 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_169 ( - .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_169 ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_163 ( + .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .X ( out[0] ) ) ; endmodule @@ -65738,9 +70011,13 @@ input [0:1] mem ; input [0:1] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -65752,10 +70029,14 @@ input [0:2] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -65766,10 +70047,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -65848,9 +70133,9 @@ sb_0__1__mux_2level_tapbuf_basis_input2_mem2_0 mux_l1_in_1_ ( .in ( in[3:4] ) , .mem ( local_encoder2to3_0_data[0:1] ) , .mem_inv ( local_encoder2to3_0_data_inv[0:1] ) , .out ( mux_2level_tapbuf_basis_input2_mem2_0_out ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_218 ( .A ( BUF_net_219 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_219 ( - .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_219 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_203 ( .A ( BUF_net_204 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_204 ( + .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_204 ) ) ; endmodule @@ -66002,7 +70287,7 @@ input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ropt_net_245 ) , +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ropt_net_236 ) , .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; @@ -66011,34 +70296,26 @@ sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__buf_1 FTB_17__16 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1417 ( .A ( ccff_head[0] ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1412 ( .A ( ccff_head[0] ) , + .X ( copt_net_222 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1413 ( .A ( copt_net_224 ) , + .X ( copt_net_223 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1414 ( .A ( copt_net_222 ) , + .X ( copt_net_224 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1415 ( .A ( copt_net_226 ) , + .X ( copt_net_225 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1416 ( .A ( ropt_net_238 ) , + .X ( copt_net_226 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1417 ( .A ( copt_net_223 ) , .X ( copt_net_227 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1418 ( .A ( ropt_net_249 ) , - .X ( copt_net_228 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1419 ( .A ( copt_net_228 ) , - .X ( copt_net_229 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1420 ( .A ( copt_net_229 ) , - .X ( copt_net_230 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1421 ( .A ( ropt_net_248 ) , - .X ( copt_net_231 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1422 ( .A ( copt_net_230 ) , - .X ( copt_net_232 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1432 ( .A ( copt_net_231 ) , - .X ( ropt_net_243 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1433 ( .A ( ropt_net_243 ) , - .X ( ropt_net_244 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1434 ( .A ( ropt_net_246 ) , - .X ( ropt_net_245 ) ) ; -sky130_fd_sc_hd__buf_2 ropt_h_inst_1435 ( .A ( ropt_net_244 ) , - .X ( ropt_net_246 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1436 ( .A ( copt_net_232 ) , - .X ( ropt_net_247 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1437 ( .A ( ropt_net_247 ) , - .X ( ropt_net_248 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1438 ( .A ( ropt_net_250 ) , - .X ( ropt_net_249 ) ) ; -sky130_fd_sc_hd__buf_2 ropt_h_inst_1439 ( .A ( copt_net_227 ) , - .X ( ropt_net_250 ) ) ; +sky130_fd_sc_hd__buf_1 ropt_h_inst_1426 ( .A ( ropt_net_239 ) , + .X ( ropt_net_236 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1427 ( .A ( copt_net_227 ) , + .X ( ropt_net_237 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1428 ( .A ( ropt_net_237 ) , + .X ( ropt_net_238 ) ) ; +sky130_fd_sc_hd__buf_1 ropt_h_inst_1429 ( .A ( copt_net_225 ) , + .X ( ropt_net_239 ) ) ; endmodule @@ -66050,10 +70327,14 @@ input [0:2] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -66064,10 +70345,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -66078,10 +70363,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -66139,6 +70428,8 @@ wire [0:0] mux_2level_tapbuf_basis_input3_mem3_2_out ; sb_0__1__const1_7 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( mux_2level_tapbuf_basis_input3_mem3_2_out[0] ) , .X ( out[0] ) ) ; sb_0__1__local_encoder2to3_14 local_encoder2to3_0_ ( .addr ( sram[0:1] ) , .data ( local_encoder2to3_0_data ) , .data_inv ( local_encoder2to3_0_data_inv ) ) ; @@ -66160,9 +70451,6 @@ sb_0__1__mux_2level_tapbuf_basis_input3_mem3_23 mux_l2_in_0_ ( .mem ( local_encoder2to3_1_data ) , .mem_inv ( local_encoder2to3_1_data_inv ) , .out ( mux_2level_tapbuf_basis_input3_mem3_2_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_166 ( .A ( BUF_net_167 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_167 ( - .A ( mux_2level_tapbuf_basis_input3_mem3_2_out[0] ) , .Y ( BUF_net_167 ) ) ; endmodule @@ -66174,10 +70462,14 @@ input [0:2] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -66188,10 +70480,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -66202,10 +70498,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -66284,9 +70584,9 @@ sb_0__1__mux_2level_tapbuf_basis_input3_mem3_20 mux_l2_in_0_ ( .mem ( local_encoder2to3_1_data ) , .mem_inv ( local_encoder2to3_1_data_inv ) , .out ( mux_2level_tapbuf_basis_input3_mem3_2_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_164 ( .A ( BUF_net_165 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_165 ( - .A ( mux_2level_tapbuf_basis_input3_mem3_2_out[0] ) , .Y ( BUF_net_165 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_161 ( .A ( BUF_net_162 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_162 ( + .A ( mux_2level_tapbuf_basis_input3_mem3_2_out[0] ) , .Y ( BUF_net_162 ) ) ; endmodule @@ -66298,10 +70598,14 @@ input [0:2] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -66312,10 +70616,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -66326,10 +70634,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -66408,9 +70720,9 @@ sb_0__1__mux_2level_tapbuf_basis_input3_mem3_17 mux_l2_in_0_ ( .mem ( local_encoder2to3_1_data ) , .mem_inv ( local_encoder2to3_1_data_inv ) , .out ( mux_2level_tapbuf_basis_input3_mem3_2_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_162 ( .A ( BUF_net_163 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_163 ( - .A ( mux_2level_tapbuf_basis_input3_mem3_2_out[0] ) , .Y ( BUF_net_163 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_159 ( .A ( BUF_net_160 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_160 ( + .A ( mux_2level_tapbuf_basis_input3_mem3_2_out[0] ) , .Y ( BUF_net_160 ) ) ; endmodule @@ -66422,10 +70734,14 @@ input [0:2] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -66436,10 +70752,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -66450,10 +70770,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -66532,9 +70856,9 @@ sb_0__1__mux_2level_tapbuf_basis_input3_mem3_14 mux_l2_in_0_ ( .mem ( local_encoder2to3_1_data ) , .mem_inv ( local_encoder2to3_1_data_inv ) , .out ( mux_2level_tapbuf_basis_input3_mem3_2_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_160 ( .A ( BUF_net_161 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_161 ( - .A ( mux_2level_tapbuf_basis_input3_mem3_2_out[0] ) , .Y ( BUF_net_161 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_157 ( .A ( BUF_net_158 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_158 ( + .A ( mux_2level_tapbuf_basis_input3_mem3_2_out[0] ) , .Y ( BUF_net_158 ) ) ; endmodule @@ -66546,10 +70870,14 @@ input [0:2] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -66560,10 +70888,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -66574,10 +70906,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -66656,9 +70992,9 @@ sb_0__1__mux_2level_tapbuf_basis_input3_mem3_11 mux_l2_in_0_ ( .mem ( local_encoder2to3_1_data ) , .mem_inv ( local_encoder2to3_1_data_inv ) , .out ( mux_2level_tapbuf_basis_input3_mem3_2_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_158 ( .A ( BUF_net_159 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_159 ( - .A ( mux_2level_tapbuf_basis_input3_mem3_2_out[0] ) , .Y ( BUF_net_159 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_155 ( .A ( BUF_net_156 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_156 ( + .A ( mux_2level_tapbuf_basis_input3_mem3_2_out[0] ) , .Y ( BUF_net_156 ) ) ; endmodule @@ -66670,10 +71006,14 @@ input [0:2] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -66684,10 +71024,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -66698,10 +71042,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -66759,6 +71107,8 @@ wire [0:0] mux_2level_tapbuf_basis_input3_mem3_2_out ; sb_0__1__const1_2 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( mux_2level_tapbuf_basis_input3_mem3_2_out[0] ) , .X ( out[0] ) ) ; sb_0__1__local_encoder2to3_4 local_encoder2to3_0_ ( .addr ( sram[0:1] ) , .data ( local_encoder2to3_0_data ) , .data_inv ( local_encoder2to3_0_data_inv ) ) ; @@ -66780,9 +71130,6 @@ sb_0__1__mux_2level_tapbuf_basis_input3_mem3_8 mux_l2_in_0_ ( .mem ( local_encoder2to3_1_data ) , .mem_inv ( local_encoder2to3_1_data_inv ) , .out ( mux_2level_tapbuf_basis_input3_mem3_2_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_156 ( .A ( BUF_net_157 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_157 ( - .A ( mux_2level_tapbuf_basis_input3_mem3_2_out[0] ) , .Y ( BUF_net_157 ) ) ; endmodule @@ -66794,10 +71141,14 @@ input [0:2] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -66808,10 +71159,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -66822,10 +71177,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -66904,8 +71263,9 @@ sb_0__1__mux_2level_tapbuf_basis_input3_mem3_5 mux_l2_in_0_ ( .mem ( local_encoder2to3_1_data ) , .mem_inv ( local_encoder2to3_1_data_inv ) , .out ( mux_2level_tapbuf_basis_input3_mem3_2_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_155 ( - .A ( mux_2level_tapbuf_basis_input3_mem3_2_out[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_153 ( .A ( BUF_net_154 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_154 ( + .A ( mux_2level_tapbuf_basis_input3_mem3_2_out[0] ) , .Y ( BUF_net_154 ) ) ; endmodule @@ -66917,10 +71277,14 @@ input [0:2] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -66931,10 +71295,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -66945,10 +71313,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -67006,6 +71378,8 @@ wire [0:0] mux_2level_tapbuf_basis_input3_mem3_2_out ; sb_0__1__const1_0 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( mux_2level_tapbuf_basis_input3_mem3_2_out[0] ) , .X ( out[0] ) ) ; sb_0__1__local_encoder2to3_0 local_encoder2to3_0_ ( .addr ( sram[0:1] ) , .data ( local_encoder2to3_0_data ) , .data_inv ( local_encoder2to3_0_data_inv ) ) ; @@ -67027,9 +71401,6 @@ sb_0__1__mux_2level_tapbuf_basis_input3_mem3_2 mux_l2_in_0_ ( .mem ( local_encoder2to3_1_data ) , .mem_inv ( local_encoder2to3_1_data_inv ) , .out ( mux_2level_tapbuf_basis_input3_mem3_2_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_153 ( .A ( BUF_net_154 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_154 ( - .A ( mux_2level_tapbuf_basis_input3_mem3_2_out[0] ) , .Y ( BUF_net_154 ) ) ; endmodule @@ -67174,21 +71545,21 @@ sb_0__1__mux_2level_tapbuf_size6_0 mux_top_track_0 ( .sram ( mux_2level_tapbuf_size6_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 , SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) , - .out ( chany_top_out[0] ) , .p0 ( optlc_net_220 ) ) ; + .out ( chany_top_out[0] ) , .p0 ( optlc_net_219 ) ) ; sb_0__1__mux_2level_tapbuf_size6_1 mux_top_track_6 ( .in ( { top_left_grid_pin_1_[0] , chanx_right_in[4] , chanx_right_in[15] , chanx_right_in[26] , chany_top_out[9] , chany_top_out[24] } ) , .sram ( mux_2level_tapbuf_size6_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 , SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 } ) , - .out ( chany_top_out[3] ) , .p0 ( optlc_net_220 ) ) ; + .out ( chany_top_out[3] ) , .p0 ( optlc_net_215 ) ) ; sb_0__1__mux_2level_tapbuf_size6_2 mux_top_track_12 ( .in ( { top_left_grid_pin_1_[0] , chanx_right_in[6] , chanx_right_in[17] , chanx_right_in[28] , chany_top_out[12] , chany_top_out[27] } ) , .sram ( mux_2level_tapbuf_size6_2_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_9 , SYNOPSYS_UNCONNECTED_10 , SYNOPSYS_UNCONNECTED_11 , SYNOPSYS_UNCONNECTED_12 } ) , - .out ( chany_top_out[6] ) , .p0 ( optlc_net_225 ) ) ; + .out ( chany_top_out[6] ) , .p0 ( optlc_net_219 ) ) ; sb_0__1__mux_2level_tapbuf_size6_3 mux_right_track_2 ( .in ( { chany_top_in[0] , chany_bottom_out[7] , right_bottom_grid_pin_37_[0] , right_bottom_grid_pin_40_[0] , @@ -67196,7 +71567,7 @@ sb_0__1__mux_2level_tapbuf_size6_3 mux_right_track_2 ( .sram ( mux_2level_tapbuf_size6_3_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 , SYNOPSYS_UNCONNECTED_15 , SYNOPSYS_UNCONNECTED_16 } ) , - .out ( chanx_right_out[1] ) , .p0 ( optlc_net_223 ) ) ; + .out ( chanx_right_out[1] ) , .p0 ( optlc_net_215 ) ) ; sb_0__1__mux_2level_tapbuf_size6_4 mux_right_track_6 ( .in ( { chany_top_in[2] , chany_bottom_out[9] , right_bottom_grid_pin_36_[0] , right_bottom_grid_pin_39_[0] , @@ -67204,7 +71575,7 @@ sb_0__1__mux_2level_tapbuf_size6_4 mux_right_track_6 ( .sram ( mux_2level_tapbuf_size6_4_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_17 , SYNOPSYS_UNCONNECTED_18 , SYNOPSYS_UNCONNECTED_19 , SYNOPSYS_UNCONNECTED_20 } ) , - .out ( chanx_right_out[3] ) , .p0 ( optlc_net_222 ) ) ; + .out ( chanx_right_out[3] ) , .p0 ( optlc_net_217 ) ) ; sb_0__1__mux_2level_tapbuf_size6_5 mux_right_track_8 ( .in ( { chany_top_in[4] , chany_bottom_out[11] , right_bottom_grid_pin_37_[0] , right_bottom_grid_pin_40_[0] , @@ -67212,21 +71583,21 @@ sb_0__1__mux_2level_tapbuf_size6_5 mux_right_track_8 ( .sram ( mux_2level_tapbuf_size6_5_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_21 , SYNOPSYS_UNCONNECTED_22 , SYNOPSYS_UNCONNECTED_23 , SYNOPSYS_UNCONNECTED_24 } ) , - .out ( chanx_right_out[4] ) , .p0 ( optlc_net_222 ) ) ; + .out ( chanx_right_out[4] ) , .p0 ( optlc_net_217 ) ) ; sb_0__1__mux_2level_tapbuf_size6_6 mux_bottom_track_7 ( .in ( { chany_bottom_out[9] , chany_bottom_out[24] , chanx_right_in[6] , chanx_right_in[17] , chanx_right_in[28] , bottom_left_grid_pin_1_[0] } ) , .sram ( mux_2level_tapbuf_size6_6_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_25 , SYNOPSYS_UNCONNECTED_26 , SYNOPSYS_UNCONNECTED_27 , SYNOPSYS_UNCONNECTED_28 } ) , - .out ( chany_bottom_out[3] ) , .p0 ( optlc_net_221 ) ) ; + .out ( chany_bottom_out[3] ) , .p0 ( optlc_net_220 ) ) ; sb_0__1__mux_2level_tapbuf_size6 mux_bottom_track_13 ( .in ( { chany_bottom_out[12] , chany_bottom_out[27] , chanx_right_in[4] , chanx_right_in[15] , chanx_right_in[26] , bottom_left_grid_pin_1_[0] } ) , .sram ( mux_2level_tapbuf_size6_7_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_29 , SYNOPSYS_UNCONNECTED_30 , SYNOPSYS_UNCONNECTED_31 , SYNOPSYS_UNCONNECTED_32 } ) , - .out ( chany_bottom_out[6] ) , .p0 ( optlc_net_221 ) ) ; + .out ( chany_bottom_out[6] ) , .p0 ( optlc_net_216 ) ) ; sb_0__1__mux_2level_tapbuf_size6_mem_0 mem_top_track_0 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( mux_2level_tapbuf_size6_mem_0_ccff_tail ) , @@ -67272,28 +71643,28 @@ sb_0__1__mux_2level_tapbuf_size5_0 mux_top_track_2 ( .sram ( mux_2level_tapbuf_size5_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_33 , SYNOPSYS_UNCONNECTED_34 , SYNOPSYS_UNCONNECTED_35 , SYNOPSYS_UNCONNECTED_36 } ) , - .out ( chany_top_out[1] ) , .p0 ( optlc_net_220 ) ) ; + .out ( chany_top_out[1] ) , .p0 ( optlc_net_215 ) ) ; sb_0__1__mux_2level_tapbuf_size5_1 mux_top_track_4 ( .in ( { chanx_right_in[3] , chanx_right_in[14] , chanx_right_in[25] , chany_top_out[8] , chany_top_out[23] } ) , .sram ( mux_2level_tapbuf_size5_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_37 , SYNOPSYS_UNCONNECTED_38 , SYNOPSYS_UNCONNECTED_39 , SYNOPSYS_UNCONNECTED_40 } ) , - .out ( chany_top_out[2] ) , .p0 ( optlc_net_220 ) ) ; + .out ( chany_top_out[2] ) , .p0 ( optlc_net_215 ) ) ; sb_0__1__mux_2level_tapbuf_size5_2 mux_top_track_10 ( .in ( { chanx_right_in[5] , chanx_right_in[16] , chanx_right_in[27] , chany_top_out[11] , chany_top_out[25] } ) , .sram ( mux_2level_tapbuf_size5_2_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_41 , SYNOPSYS_UNCONNECTED_42 , SYNOPSYS_UNCONNECTED_43 , SYNOPSYS_UNCONNECTED_44 } ) , - .out ( chany_top_out[5] ) , .p0 ( optlc_net_222 ) ) ; + .out ( chany_top_out[5] ) , .p0 ( optlc_net_217 ) ) ; sb_0__1__mux_2level_tapbuf_size5_3 mux_top_track_20 ( .in ( { chanx_right_in[7] , chanx_right_in[18] , chanx_right_in[29] , chany_top_out[13] , chany_top_out[28] } ) , .sram ( mux_2level_tapbuf_size5_3_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_45 , SYNOPSYS_UNCONNECTED_46 , SYNOPSYS_UNCONNECTED_47 , SYNOPSYS_UNCONNECTED_48 } ) , - .out ( chany_top_out[10] ) , .p0 ( optlc_net_225 ) ) ; + .out ( chany_top_out[10] ) , .p0 ( optlc_net_219 ) ) ; sb_0__1__mux_2level_tapbuf_size5_4 mux_right_track_0 ( .in ( { chany_bottom_out[4] , right_bottom_grid_pin_36_[0] , right_bottom_grid_pin_39_[0] , right_bottom_grid_pin_42_[0] , @@ -67301,7 +71672,7 @@ sb_0__1__mux_2level_tapbuf_size5_4 mux_right_track_0 ( .sram ( mux_2level_tapbuf_size5_4_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_49 , SYNOPSYS_UNCONNECTED_50 , SYNOPSYS_UNCONNECTED_51 , SYNOPSYS_UNCONNECTED_52 } ) , - .out ( chanx_right_out[0] ) , .p0 ( optlc_net_223 ) ) ; + .out ( chanx_right_out[0] ) , .p0 ( optlc_net_215 ) ) ; sb_0__1__mux_2level_tapbuf_size5_5 mux_right_track_4 ( .in ( { chany_top_in[1] , chany_bottom_out[8] , right_bottom_grid_pin_38_[0] , right_bottom_grid_pin_41_[0] , @@ -67309,7 +71680,7 @@ sb_0__1__mux_2level_tapbuf_size5_5 mux_right_track_4 ( .sram ( mux_2level_tapbuf_size5_5_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_53 , SYNOPSYS_UNCONNECTED_54 , SYNOPSYS_UNCONNECTED_55 , SYNOPSYS_UNCONNECTED_56 } ) , - .out ( chanx_right_out[2] ) , .p0 ( optlc_net_222 ) ) ; + .out ( chanx_right_out[2] ) , .p0 ( optlc_net_217 ) ) ; sb_0__1__mux_2level_tapbuf_size5_6 mux_right_track_10 ( .in ( { chany_top_in[5] , chany_bottom_out[12] , right_bottom_grid_pin_38_[0] , right_bottom_grid_pin_41_[0] , @@ -67317,7 +71688,7 @@ sb_0__1__mux_2level_tapbuf_size5_6 mux_right_track_10 ( .sram ( mux_2level_tapbuf_size5_6_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_57 , SYNOPSYS_UNCONNECTED_58 , SYNOPSYS_UNCONNECTED_59 , SYNOPSYS_UNCONNECTED_60 } ) , - .out ( chanx_right_out[5] ) , .p0 ( optlc_net_222 ) ) ; + .out ( chanx_right_out[5] ) , .p0 ( optlc_net_217 ) ) ; sb_0__1__mux_2level_tapbuf_size5_7 mux_bottom_track_1 ( .in ( { chany_bottom_out[4] , chany_bottom_out[20] , chanx_right_in[9] , chanx_right_in[20] , bottom_left_grid_pin_1_[0] } ) , @@ -67331,28 +71702,28 @@ sb_0__1__mux_2level_tapbuf_size5_8 mux_bottom_track_5 ( .sram ( mux_2level_tapbuf_size5_8_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_65 , SYNOPSYS_UNCONNECTED_66 , SYNOPSYS_UNCONNECTED_67 , SYNOPSYS_UNCONNECTED_68 } ) , - .out ( chany_bottom_out[2] ) , .p0 ( optlc_net_225 ) ) ; + .out ( chany_bottom_out[2] ) , .p0 ( optlc_net_221 ) ) ; sb_0__1__mux_2level_tapbuf_size5_9 mux_bottom_track_11 ( .in ( { chany_bottom_out[11] , chany_bottom_out[25] , chanx_right_in[5] , chanx_right_in[16] , chanx_right_in[27] } ) , .sram ( mux_2level_tapbuf_size5_9_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_69 , SYNOPSYS_UNCONNECTED_70 , SYNOPSYS_UNCONNECTED_71 , SYNOPSYS_UNCONNECTED_72 } ) , - .out ( chany_bottom_out[5] ) , .p0 ( optlc_net_221 ) ) ; + .out ( chany_bottom_out[5] ) , .p0 ( optlc_net_216 ) ) ; sb_0__1__mux_2level_tapbuf_size5_10 mux_bottom_track_21 ( .in ( { chany_bottom_out[13] , chany_bottom_out[28] , chanx_right_in[3] , chanx_right_in[14] , chanx_right_in[25] } ) , .sram ( mux_2level_tapbuf_size5_10_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_73 , SYNOPSYS_UNCONNECTED_74 , SYNOPSYS_UNCONNECTED_75 , SYNOPSYS_UNCONNECTED_76 } ) , - .out ( chany_bottom_out[10] ) , .p0 ( optlc_net_224 ) ) ; + .out ( chany_bottom_out[10] ) , .p0 ( optlc_net_218 ) ) ; sb_0__1__mux_2level_tapbuf_size5 mux_bottom_track_29 ( .in ( { chany_bottom_out[15] , chany_bottom_out[29] , chanx_right_in[2] , chanx_right_in[13] , chanx_right_in[24] } ) , .sram ( mux_2level_tapbuf_size5_11_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_77 , SYNOPSYS_UNCONNECTED_78 , SYNOPSYS_UNCONNECTED_79 , SYNOPSYS_UNCONNECTED_80 } ) , - .out ( chany_bottom_out[14] ) , .p0 ( optlc_net_224 ) ) ; + .out ( chany_bottom_out[14] ) , .p0 ( optlc_net_221 ) ) ; sb_0__1__mux_2level_tapbuf_size5_mem_0 mem_top_track_2 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( mux_2level_tapbuf_size6_mem_0_ccff_tail ) , @@ -67419,84 +71790,84 @@ sb_0__1__mux_2level_tapbuf_size4_0 mux_top_track_28 ( .sram ( mux_2level_tapbuf_size4_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_81 , SYNOPSYS_UNCONNECTED_82 , SYNOPSYS_UNCONNECTED_83 , SYNOPSYS_UNCONNECTED_84 } ) , - .out ( chany_top_out[14] ) , .p0 ( optlc_net_223 ) ) ; + .out ( chany_top_out[14] ) , .p0 ( optlc_net_221 ) ) ; sb_0__1__mux_2level_tapbuf_size4_1 mux_top_track_52 ( .in ( { chanx_right_in[0] , chanx_right_in[11] , chanx_right_in[22] , chany_top_out[19] } ) , .sram ( mux_2level_tapbuf_size4_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_85 , SYNOPSYS_UNCONNECTED_86 , SYNOPSYS_UNCONNECTED_87 , SYNOPSYS_UNCONNECTED_88 } ) , - .out ( chany_top_out[26] ) , .p0 ( optlc_net_226 ) ) ; + .out ( chany_top_out[26] ) , .p0 ( optlc_net_217 ) ) ; sb_0__1__mux_2level_tapbuf_size4_2 mux_right_track_12 ( .in ( { chany_top_in[9] , chany_bottom_out[13] , right_bottom_grid_pin_36_[0] , chany_top_out[13] } ) , .sram ( mux_2level_tapbuf_size4_2_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_89 , SYNOPSYS_UNCONNECTED_90 , SYNOPSYS_UNCONNECTED_91 , SYNOPSYS_UNCONNECTED_92 } ) , - .out ( chanx_right_out[6] ) , .p0 ( optlc_net_226 ) ) ; + .out ( chanx_right_out[6] ) , .p0 ( optlc_net_219 ) ) ; sb_0__1__mux_2level_tapbuf_size4_3 mux_right_track_14 ( .in ( { chany_top_in[13] , chany_bottom_out[15] , right_bottom_grid_pin_37_[0] , chany_top_out[15] } ) , .sram ( mux_2level_tapbuf_size4_3_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_93 , SYNOPSYS_UNCONNECTED_94 , SYNOPSYS_UNCONNECTED_95 , SYNOPSYS_UNCONNECTED_96 } ) , - .out ( chanx_right_out[7] ) , .p0 ( optlc_net_223 ) ) ; + .out ( chanx_right_out[7] ) , .p0 ( optlc_net_219 ) ) ; sb_0__1__mux_2level_tapbuf_size4_4 mux_right_track_16 ( .in ( { chany_bottom_out[16] , chany_top_in[17] , right_bottom_grid_pin_38_[0] , chany_top_out[16] } ) , .sram ( mux_2level_tapbuf_size4_4_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_97 , SYNOPSYS_UNCONNECTED_98 , SYNOPSYS_UNCONNECTED_99 , SYNOPSYS_UNCONNECTED_100 } ) , - .out ( chanx_right_out[8] ) , .p0 ( optlc_net_223 ) ) ; + .out ( chanx_right_out[8] ) , .p0 ( optlc_net_219 ) ) ; sb_0__1__mux_2level_tapbuf_size4_5 mux_right_track_18 ( .in ( { chany_bottom_out[17] , chany_top_in[21] , right_bottom_grid_pin_39_[0] , chany_top_out[17] } ) , .sram ( mux_2level_tapbuf_size4_5_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_101 , SYNOPSYS_UNCONNECTED_102 , SYNOPSYS_UNCONNECTED_103 , SYNOPSYS_UNCONNECTED_104 } ) , - .out ( chanx_right_out[9] ) , .p0 ( optlc_net_223 ) ) ; + .out ( chanx_right_out[9] ) , .p0 ( optlc_net_219 ) ) ; sb_0__1__mux_2level_tapbuf_size4_6 mux_right_track_20 ( .in ( { chany_bottom_out[19] , chany_top_in[25] , right_bottom_grid_pin_40_[0] , chany_top_out[19] } ) , .sram ( mux_2level_tapbuf_size4_6_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_105 , SYNOPSYS_UNCONNECTED_106 , SYNOPSYS_UNCONNECTED_107 , SYNOPSYS_UNCONNECTED_108 } ) , - .out ( chanx_right_out[10] ) , .p0 ( optlc_net_223 ) ) ; + .out ( chanx_right_out[10] ) , .p0 ( optlc_net_215 ) ) ; sb_0__1__mux_2level_tapbuf_size4_7 mux_right_track_22 ( .in ( { chany_bottom_out[20] , chany_top_in[29] , right_bottom_grid_pin_41_[0] , chany_top_out[20] } ) , .sram ( mux_2level_tapbuf_size4_7_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_109 , SYNOPSYS_UNCONNECTED_110 , SYNOPSYS_UNCONNECTED_111 , SYNOPSYS_UNCONNECTED_112 } ) , - .out ( chanx_right_out[11] ) , .p0 ( optlc_net_223 ) ) ; + .out ( chanx_right_out[11] ) , .p0 ( optlc_net_215 ) ) ; sb_0__1__mux_2level_tapbuf_size4_8 mux_right_track_36 ( .in ( { chany_bottom_out[29] , right_bottom_grid_pin_40_[0] , chany_top_out[29] , chany_bottom_in[29] } ) , .sram ( mux_2level_tapbuf_size4_8_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_113 , SYNOPSYS_UNCONNECTED_114 , SYNOPSYS_UNCONNECTED_115 , SYNOPSYS_UNCONNECTED_116 } ) , - .out ( chanx_right_out[18] ) , .p0 ( optlc_net_221 ) ) ; + .out ( chanx_right_out[18] ) , .p0 ( optlc_net_218 ) ) ; sb_0__1__mux_2level_tapbuf_size4_9 mux_bottom_track_3 ( .in ( { chany_bottom_out[7] , chany_bottom_out[21] , chanx_right_in[8] , chanx_right_in[19] } ) , .sram ( mux_2level_tapbuf_size4_9_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_117 , SYNOPSYS_UNCONNECTED_118 , SYNOPSYS_UNCONNECTED_119 , SYNOPSYS_UNCONNECTED_120 } ) , - .out ( chany_bottom_out[1] ) , .p0 ( optlc_net_225 ) ) ; + .out ( chany_bottom_out[1] ) , .p0 ( optlc_net_220 ) ) ; sb_0__1__mux_2level_tapbuf_size4_10 mux_bottom_track_37 ( .in ( { chany_bottom_out[16] , chanx_right_in[1] , chanx_right_in[12] , chanx_right_in[23] } ) , .sram ( mux_2level_tapbuf_size4_10_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_121 , SYNOPSYS_UNCONNECTED_122 , SYNOPSYS_UNCONNECTED_123 , SYNOPSYS_UNCONNECTED_124 } ) , - .out ( chany_bottom_out[18] ) , .p0 ( optlc_net_224 ) ) ; + .out ( chany_bottom_out[18] ) , .p0 ( optlc_net_221 ) ) ; sb_0__1__mux_2level_tapbuf_size4 mux_bottom_track_45 ( .in ( { chany_bottom_out[17] , chanx_right_in[0] , chanx_right_in[11] , chanx_right_in[22] } ) , .sram ( mux_2level_tapbuf_size4_11_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_125 , SYNOPSYS_UNCONNECTED_126 , SYNOPSYS_UNCONNECTED_127 , SYNOPSYS_UNCONNECTED_128 } ) , - .out ( chany_bottom_out[22] ) , .p0 ( optlc_net_224 ) ) ; + .out ( chany_bottom_out[22] ) , .p0 ( optlc_net_216 ) ) ; sb_0__1__mux_2level_tapbuf_size4_mem_0 mem_top_track_28 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( mux_2level_tapbuf_size5_mem_3_ccff_tail ) , @@ -67561,59 +71932,59 @@ sb_0__1__mux_2level_tapbuf_size3_0 mux_top_track_36 ( .in ( { chanx_right_in[9] , chanx_right_in[20] , chany_top_out[16] } ) , .sram ( mux_2level_tapbuf_size3_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_129 , SYNOPSYS_UNCONNECTED_130 } ) , - .out ( chany_top_out[18] ) , .p0 ( optlc_net_226 ) ) ; + .out ( chany_top_out[18] ) , .p0 ( optlc_net_221 ) ) ; sb_0__1__mux_2level_tapbuf_size3_1 mux_top_track_44 ( .in ( { chanx_right_in[10] , chanx_right_in[21] , chany_top_out[17] } ) , .sram ( mux_2level_tapbuf_size3_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_131 , SYNOPSYS_UNCONNECTED_132 } ) , - .out ( chany_top_out[22] ) , .p0 ( optlc_net_226 ) ) ; + .out ( chany_top_out[22] ) , .p0 ( optlc_net_221 ) ) ; sb_0__1__mux_2level_tapbuf_size3_2 mux_right_track_24 ( .in ( { chany_bottom_out[21] , right_bottom_grid_pin_42_[0] , chany_top_out[21] } ) , .sram ( mux_2level_tapbuf_size3_2_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_133 , SYNOPSYS_UNCONNECTED_134 } ) , - .out ( chanx_right_out[12] ) , .p0 ( optlc_net_225 ) ) ; + .out ( chanx_right_out[12] ) , .p0 ( optlc_net_218 ) ) ; sb_0__1__mux_2level_tapbuf_size3_3 mux_right_track_26 ( .in ( { chany_bottom_out[23] , right_bottom_grid_pin_43_[0] , chany_top_out[23] } ) , .sram ( mux_2level_tapbuf_size3_3_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_135 , SYNOPSYS_UNCONNECTED_136 } ) , - .out ( chanx_right_out[13] ) , .p0 ( optlc_net_221 ) ) ; + .out ( chanx_right_out[13] ) , .p0 ( optlc_net_218 ) ) ; sb_0__1__mux_2level_tapbuf_size3_4 mux_right_track_28 ( .in ( { chany_bottom_out[24] , right_bottom_grid_pin_36_[0] , chany_top_out[24] } ) , .sram ( mux_2level_tapbuf_size3_4_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_137 , SYNOPSYS_UNCONNECTED_138 } ) , - .out ( chanx_right_out[14] ) , .p0 ( optlc_net_221 ) ) ; + .out ( chanx_right_out[14] ) , .p0 ( optlc_net_216 ) ) ; sb_0__1__mux_2level_tapbuf_size3_5 mux_right_track_30 ( .in ( { chany_bottom_out[25] , right_bottom_grid_pin_37_[0] , chany_top_out[25] } ) , .sram ( mux_2level_tapbuf_size3_5_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_139 , SYNOPSYS_UNCONNECTED_140 } ) , - .out ( chanx_right_out[15] ) , .p0 ( optlc_net_221 ) ) ; + .out ( chanx_right_out[15] ) , .p0 ( optlc_net_216 ) ) ; sb_0__1__mux_2level_tapbuf_size3_6 mux_right_track_32 ( .in ( { chany_bottom_out[27] , right_bottom_grid_pin_38_[0] , chany_top_out[27] } ) , .sram ( mux_2level_tapbuf_size3_6_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_141 , SYNOPSYS_UNCONNECTED_142 } ) , - .out ( chanx_right_out[16] ) , .p0 ( optlc_net_221 ) ) ; + .out ( chanx_right_out[16] ) , .p0 ( optlc_net_218 ) ) ; sb_0__1__mux_2level_tapbuf_size3_7 mux_right_track_34 ( .in ( { chany_bottom_out[28] , right_bottom_grid_pin_39_[0] , chany_top_out[28] } ) , .sram ( mux_2level_tapbuf_size3_7_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_143 , SYNOPSYS_UNCONNECTED_144 } ) , - .out ( chanx_right_out[17] ) , .p0 ( optlc_net_221 ) ) ; + .out ( chanx_right_out[17] ) , .p0 ( optlc_net_218 ) ) ; sb_0__1__mux_2level_tapbuf_size3_8 mux_right_track_50 ( .in ( { right_bottom_grid_pin_39_[0] , right_bottom_grid_pin_43_[0] , chany_bottom_in[4] } ) , .sram ( mux_2level_tapbuf_size3_8_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_145 , SYNOPSYS_UNCONNECTED_146 } ) , - .out ( chanx_right_out[25] ) , .p0 ( optlc_net_221 ) ) ; + .out ( chanx_right_out[25] ) , .p0 ( optlc_net_218 ) ) ; sb_0__1__mux_2level_tapbuf_size3 mux_bottom_track_53 ( .in ( { chany_bottom_out[19] , chanx_right_in[10] , chanx_right_in[21] } ) , .sram ( mux_2level_tapbuf_size3_9_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_147 , SYNOPSYS_UNCONNECTED_148 } ) , - .out ( chany_bottom_out[26] ) , .p0 ( optlc_net_224 ) ) ; + .out ( chany_bottom_out[26] ) , .p0 ( optlc_net_218 ) ) ; sb_0__1__mux_2level_tapbuf_size3_mem_0 mem_top_track_36 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( mux_2level_tapbuf_size4_mem_0_ccff_tail ) , @@ -67667,42 +72038,42 @@ sb_0__1__mux_2level_tapbuf_size2_0 mux_right_track_38 ( .in ( { right_bottom_grid_pin_41_[0] , chany_bottom_in[25] } ) , .sram ( mux_2level_tapbuf_size2_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_149 , SYNOPSYS_UNCONNECTED_150 } ) , - .out ( chanx_right_out[19] ) , .p0 ( optlc_net_221 ) ) ; + .out ( chanx_right_out[19] ) , .p0 ( optlc_net_218 ) ) ; sb_0__1__mux_2level_tapbuf_size2_1 mux_right_track_40 ( .in ( { right_bottom_grid_pin_42_[0] , chany_bottom_in[21] } ) , .sram ( mux_2level_tapbuf_size2_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_151 , SYNOPSYS_UNCONNECTED_152 } ) , - .out ( chanx_right_out[20] ) , .p0 ( optlc_net_221 ) ) ; + .out ( chanx_right_out[20] ) , .p0 ( optlc_net_218 ) ) ; sb_0__1__mux_2level_tapbuf_size2_2 mux_right_track_44 ( .in ( { right_bottom_grid_pin_36_[0] , chany_bottom_in[13] } ) , .sram ( mux_2level_tapbuf_size2_2_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_153 , SYNOPSYS_UNCONNECTED_154 } ) , - .out ( chanx_right_out[22] ) , .p0 ( optlc_net_221 ) ) ; + .out ( chanx_right_out[22] ) , .p0 ( optlc_net_216 ) ) ; sb_0__1__mux_2level_tapbuf_size2_3 mux_right_track_46 ( .in ( { right_bottom_grid_pin_37_[0] , chany_bottom_in[9] } ) , .sram ( mux_2level_tapbuf_size2_3_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_155 , SYNOPSYS_UNCONNECTED_156 } ) , - .out ( chanx_right_out[23] ) , .p0 ( optlc_net_221 ) ) ; + .out ( chanx_right_out[23] ) , .p0 ( optlc_net_216 ) ) ; sb_0__1__mux_2level_tapbuf_size2_4 mux_right_track_48 ( .in ( { right_bottom_grid_pin_38_[0] , chany_bottom_in[5] } ) , .sram ( mux_2level_tapbuf_size2_4_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_157 , SYNOPSYS_UNCONNECTED_158 } ) , - .out ( chanx_right_out[24] ) , .p0 ( optlc_net_221 ) ) ; + .out ( chanx_right_out[24] ) , .p0 ( optlc_net_216 ) ) ; sb_0__1__mux_2level_tapbuf_size2_5 mux_right_track_52 ( .in ( { right_bottom_grid_pin_40_[0] , chany_bottom_in[2] } ) , .sram ( mux_2level_tapbuf_size2_5_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_159 , SYNOPSYS_UNCONNECTED_160 } ) , - .out ( chanx_right_out[26] ) , .p0 ( optlc_net_221 ) ) ; + .out ( chanx_right_out[26] ) , .p0 ( optlc_net_218 ) ) ; sb_0__1__mux_2level_tapbuf_size2_6 mux_right_track_54 ( .in ( { right_bottom_grid_pin_41_[0] , chany_bottom_in[1] } ) , .sram ( mux_2level_tapbuf_size2_6_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_161 , SYNOPSYS_UNCONNECTED_162 } ) , - .out ( chanx_right_out[27] ) , .p0 ( optlc_net_221 ) ) ; + .out ( chanx_right_out[27] ) , .p0 ( optlc_net_218 ) ) ; sb_0__1__mux_2level_tapbuf_size2 mux_right_track_56 ( .in ( { right_bottom_grid_pin_42_[0] , chany_bottom_in[0] } ) , .sram ( mux_2level_tapbuf_size2_7_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_163 , SYNOPSYS_UNCONNECTED_164 } ) , - .out ( chanx_right_out[28] ) , .p0 ( optlc_net_221 ) ) ; + .out ( chanx_right_out[28] ) , .p0 ( optlc_net_218 ) ) ; sb_0__1__mux_2level_tapbuf_size2_mem_0 mem_right_track_38 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( mux_2level_tapbuf_size4_mem_8_ccff_tail ) , @@ -67744,8 +72115,8 @@ sb_0__1__mux_2level_tapbuf_size2_mem mem_right_track_56 ( .pReset ( pReset ) , .ccff_tail ( mux_2level_tapbuf_size2_mem_7_ccff_tail ) , .mem_out ( mux_2level_tapbuf_size2_7_sram ) ) ; sky130_fd_sc_hd__buf_8 pReset_FTB00 ( .A ( pReset_E_in ) , .X ( pReset[0] ) ) ; -sky130_fd_sc_hd__buf_6 pReset_S_FTB01 ( .A ( pReset_E_in ) , - .X ( pReset_S_out ) ) ; +sky130_fd_sc_hd__conb_1 optlc_217 ( .LO ( SYNOPSYS_UNCONNECTED_165 ) , + .HI ( optlc_net_215 ) ) ; sky130_fd_sc_hd__buf_1 prog_clk_0_FTB00 ( .A ( prog_clk_0_E_in ) , .X ( prog_clk[0] ) ) ; sky130_fd_sc_hd__buf_8 FTB_115__114 ( .A ( chany_top_in[3] ) , @@ -67826,20 +72197,20 @@ sky130_fd_sc_hd__buf_8 FTB_152__151 ( .A ( chany_bottom_in[27] ) , .X ( chany_top_out[28] ) ) ; sky130_fd_sc_hd__buf_8 FTB_153__152 ( .A ( chany_bottom_in[28] ) , .X ( chany_top_out[29] ) ) ; -sky130_fd_sc_hd__conb_1 optlc_222 ( .LO ( SYNOPSYS_UNCONNECTED_165 ) , +sky130_fd_sc_hd__inv_8 BINV_R_211 ( .A ( BUF_net_212 ) , .Y ( pReset_S_out ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_212 ( .A ( pReset_E_in ) , .Y ( BUF_net_212 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_219 ( .LO ( SYNOPSYS_UNCONNECTED_166 ) , + .HI ( optlc_net_216 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_221 ( .LO ( SYNOPSYS_UNCONNECTED_167 ) , + .HI ( optlc_net_217 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_224 ( .LO ( SYNOPSYS_UNCONNECTED_168 ) , + .HI ( optlc_net_218 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_226 ( .LO ( SYNOPSYS_UNCONNECTED_169 ) , + .HI ( optlc_net_219 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_228 ( .LO ( SYNOPSYS_UNCONNECTED_170 ) , .HI ( optlc_net_220 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_224 ( .LO ( SYNOPSYS_UNCONNECTED_166 ) , +sky130_fd_sc_hd__conb_1 optlc_230 ( .LO ( SYNOPSYS_UNCONNECTED_171 ) , .HI ( optlc_net_221 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_226 ( .LO ( SYNOPSYS_UNCONNECTED_167 ) , - .HI ( optlc_net_222 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_228 ( .LO ( SYNOPSYS_UNCONNECTED_168 ) , - .HI ( optlc_net_223 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_230 ( .LO ( SYNOPSYS_UNCONNECTED_169 ) , - .HI ( optlc_net_224 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_233 ( .LO ( SYNOPSYS_UNCONNECTED_170 ) , - .HI ( optlc_net_225 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_235 ( .LO ( SYNOPSYS_UNCONNECTED_171 ) , - .HI ( optlc_net_226 ) ) ; endmodule @@ -67946,6 +72317,8 @@ wire [0:0] mux_2level_tapbuf_basis_input2_mem1_2_out ; sb_0__0__const1 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( mux_2level_tapbuf_basis_input2_mem1_2_out[0] ) , .X ( out[0] ) ) ; sb_0__0__mux_2level_tapbuf_basis_input2_mem1_58 mux_l1_in_0_ ( .in ( in[0:1] ) , .mem ( sram[0] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_2 } ) , @@ -67961,8 +72334,6 @@ sb_0__0__mux_2level_tapbuf_basis_input2_mem1 mux_l2_in_0_ ( .mem ( sram[1] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_5 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_2_out ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_99 ( - .A ( mux_2level_tapbuf_basis_input2_mem1_2_out[0] ) , .X ( out[0] ) ) ; endmodule @@ -68021,8 +72392,6 @@ wire [0:0] mux_2level_tapbuf_basis_input2_mem1_2_out ; sb_0__0__const1_33 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( mux_2level_tapbuf_basis_input2_mem1_2_out[0] ) , .X ( out[0] ) ) ; sb_0__0__mux_2level_tapbuf_basis_input2_mem1_55 mux_l1_in_0_ ( .in ( in[0:1] ) , .mem ( sram[0] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_2 } ) , @@ -68038,6 +72407,8 @@ sb_0__0__mux_2level_tapbuf_basis_input2_mem1_57 mux_l2_in_0_ ( .mem ( sram[1] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_5 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_2_out ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_100 ( + .A ( mux_2level_tapbuf_basis_input2_mem1_2_out[0] ) , .X ( out[0] ) ) ; endmodule @@ -68096,8 +72467,6 @@ wire [0:0] mux_2level_tapbuf_basis_input2_mem1_2_out ; sb_0__0__const1_32 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( mux_2level_tapbuf_basis_input2_mem1_2_out[0] ) , .X ( out[0] ) ) ; sb_0__0__mux_2level_tapbuf_basis_input2_mem1_52 mux_l1_in_0_ ( .in ( in[0:1] ) , .mem ( sram[0] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_2 } ) , @@ -68113,6 +72482,8 @@ sb_0__0__mux_2level_tapbuf_basis_input2_mem1_54 mux_l2_in_0_ ( .mem ( sram[1] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_5 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_2_out ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_99 ( + .A ( mux_2level_tapbuf_basis_input2_mem1_2_out[0] ) , .X ( out[0] ) ) ; endmodule @@ -68244,10 +72615,14 @@ input [0:2] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -68258,10 +72633,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -68347,10 +72726,14 @@ input [0:2] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -68361,10 +72744,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -68437,8 +72824,9 @@ sb_0__0__mux_2level_tapbuf_basis_input3_mem3_9 mux_l2_in_0_ ( .mem ( local_encoder2to3_1_data ) , .mem_inv ( local_encoder2to3_1_data_inv ) , .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_98 ( - .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_97 ( .A ( BUF_net_98 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_98 ( + .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_98 ) ) ; endmodule @@ -68450,10 +72838,14 @@ input [0:2] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -68464,10 +72856,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -68540,9 +72936,8 @@ sb_0__0__mux_2level_tapbuf_basis_input3_mem3_7 mux_l2_in_0_ ( .mem ( local_encoder2to3_1_data ) , .mem_inv ( local_encoder2to3_1_data_inv ) , .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_96 ( .A ( BUF_net_97 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_97 ( - .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_97 ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_96 ( + .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .X ( out[0] ) ) ; endmodule @@ -68554,10 +72949,14 @@ input [0:2] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -68568,10 +72967,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -68628,8 +73031,6 @@ wire [0:0] mux_2level_tapbuf_basis_input3_mem3_1_out ; sb_0__0__const1_28 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .X ( out[0] ) ) ; sb_0__0__local_encoder2to3_4 local_encoder2to3_0_ ( .addr ( sram[0:1] ) , .data ( local_encoder2to3_0_data ) , .data_inv ( local_encoder2to3_0_data_inv ) ) ; @@ -68646,6 +73047,9 @@ sb_0__0__mux_2level_tapbuf_basis_input3_mem3_5 mux_l2_in_0_ ( .mem ( local_encoder2to3_1_data ) , .mem_inv ( local_encoder2to3_1_data_inv ) , .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .p0 ( p0 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_94 ( .A ( BUF_net_95 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_95 ( + .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_95 ) ) ; endmodule @@ -68657,10 +73061,14 @@ input [0:2] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -68671,10 +73079,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -68731,6 +73143,8 @@ wire [0:0] mux_2level_tapbuf_basis_input3_mem3_1_out ; sb_0__0__const1_27 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .X ( out[0] ) ) ; sb_0__0__local_encoder2to3_2 local_encoder2to3_0_ ( .addr ( sram[0:1] ) , .data ( local_encoder2to3_0_data ) , .data_inv ( local_encoder2to3_0_data_inv ) ) ; @@ -68747,9 +73161,6 @@ sb_0__0__mux_2level_tapbuf_basis_input3_mem3_3 mux_l2_in_0_ ( .mem ( local_encoder2to3_1_data ) , .mem_inv ( local_encoder2to3_1_data_inv ) , .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_100 ( .A ( BUF_net_101 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_101 ( - .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_101 ) ) ; endmodule @@ -68761,10 +73172,14 @@ input [0:2] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -68775,10 +73190,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -68851,9 +73270,8 @@ sb_0__0__mux_2level_tapbuf_basis_input3_mem3_1 mux_l2_in_0_ ( .mem ( local_encoder2to3_1_data ) , .mem_inv ( local_encoder2to3_1_data_inv ) , .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_94 ( .A ( BUF_net_95 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_95 ( - .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_95 ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_93 ( + .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .X ( out[0] ) ) ; endmodule @@ -68865,19 +73283,18 @@ input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -wire copt_net_120 ; - sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( copt_net_120 ) ) ; -sky130_fd_sc_hd__buf_6 FTB_26__25 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1300 ( .A ( copt_net_120 ) , - .X ( copt_net_118 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1301 ( .A ( copt_net_118 ) , - .X ( copt_net_119 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1302 ( .A ( copt_net_119 ) , - .X ( mem_out[1] ) ) ; + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_6 FTB_26__25 ( .A ( ropt_net_183 ) , + .X ( ccff_tail[0] ) ) ; +sky130_fd_sc_hd__buf_1 ropt_h_inst_1364 ( .A ( copt_net_117 ) , + .X ( ropt_net_183 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1297 ( .A ( mem_out[1] ) , + .X ( copt_net_116 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1298 ( .A ( copt_net_116 ) , + .X ( copt_net_117 ) ) ; endmodule @@ -69273,29 +73690,31 @@ input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ropt_net_157 ) , +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ropt_net_182 ) , .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__buf_1 FTB_1__0 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1291 ( .A ( copt_net_112 ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1289 ( .A ( ccff_head[0] ) , + .X ( copt_net_108 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1290 ( .A ( copt_net_108 ) , .X ( copt_net_109 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1292 ( .A ( copt_net_109 ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1291 ( .A ( copt_net_109 ) , .X ( copt_net_110 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1293 ( .A ( ccff_head[0] ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1292 ( .A ( copt_net_112 ) , .X ( copt_net_111 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1294 ( .A ( copt_net_111 ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1293 ( .A ( copt_net_110 ) , .X ( copt_net_112 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1295 ( .A ( copt_net_110 ) , +sky130_fd_sc_hd__buf_1 copt_h_inst_1294 ( .A ( copt_net_111 ) , .X ( copt_net_113 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1296 ( .A ( copt_net_113 ) , - .X ( copt_net_114 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1336 ( .A ( copt_net_114 ) , - .X ( ropt_net_155 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1337 ( .A ( ropt_net_155 ) , - .X ( ropt_net_156 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1338 ( .A ( ropt_net_156 ) , - .X ( ropt_net_157 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1360 ( .A ( ropt_net_180 ) , + .X ( ropt_net_179 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1361 ( .A ( copt_net_113 ) , + .X ( ropt_net_180 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1362 ( .A ( ropt_net_179 ) , + .X ( ropt_net_181 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1363 ( .A ( ropt_net_181 ) , + .X ( ropt_net_182 ) ) ; endmodule @@ -69307,7 +73726,7 @@ input [0:0] mem_inv ; output [0:0] out ; input p0 ; -sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , +sky130_fd_sc_hd__mux2_2 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ; endmodule @@ -69364,7 +73783,7 @@ input [0:0] mem_inv ; output [0:0] out ; input p0 ; -sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , +sky130_fd_sc_hd__mux2_2 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ; endmodule @@ -69465,9 +73884,9 @@ sb_0__0__mux_2level_tapbuf_basis_input2_mem1_47 mux_l2_in_0_ ( .mem ( sram[1] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_4 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_102 ( .A ( BUF_net_103 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_103 ( - .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_103 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_91 ( .A ( BUF_net_92 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_92 ( + .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_92 ) ) ; endmodule @@ -69513,8 +73932,6 @@ wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ; sb_0__0__const1_22 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) ) ; sb_0__0__mux_2level_tapbuf_basis_input2_mem1_44 mux_l1_in_0_ ( .in ( in ) , .mem ( sram[0] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_2 } ) , @@ -69525,6 +73942,9 @@ sb_0__0__mux_2level_tapbuf_basis_input2_mem1_45 mux_l2_in_0_ ( .mem ( sram[1] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_4 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_89 ( .A ( BUF_net_90 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_90 ( + .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_90 ) ) ; endmodule @@ -69570,6 +73990,8 @@ wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ; sb_0__0__const1_21 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) ) ; sb_0__0__mux_2level_tapbuf_basis_input2_mem1_42 mux_l1_in_0_ ( .in ( in ) , .mem ( sram[0] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_2 } ) , @@ -69580,9 +74002,6 @@ sb_0__0__mux_2level_tapbuf_basis_input2_mem1_43 mux_l2_in_0_ ( .mem ( sram[1] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_4 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_92 ( .A ( BUF_net_93 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_93 ( - .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_93 ) ) ; endmodule @@ -69651,7 +74070,7 @@ input [0:0] mem_inv ; output [0:0] out ; input p0 ; -sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , +sky130_fd_sc_hd__mux2_2 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ; endmodule @@ -69708,7 +74127,7 @@ input [0:0] mem_inv ; output [0:0] out ; input p0 ; -sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , +sky130_fd_sc_hd__mux2_2 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ; endmodule @@ -69809,9 +74228,9 @@ sb_0__0__mux_2level_tapbuf_basis_input2_mem1_35 mux_l2_in_0_ ( .mem ( sram[1] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_4 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_90 ( .A ( BUF_net_91 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_91 ( - .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_91 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_87 ( .A ( BUF_net_88 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_88 ( + .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_88 ) ) ; endmodule @@ -69823,7 +74242,7 @@ input [0:0] mem_inv ; output [0:0] out ; input p0 ; -sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , +sky130_fd_sc_hd__mux2_2 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ; endmodule @@ -69924,9 +74343,9 @@ sb_0__0__mux_2level_tapbuf_basis_input2_mem1_31 mux_l2_in_0_ ( .mem ( sram[1] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_4 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_88 ( .A ( BUF_net_89 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_89 ( - .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_89 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_101 ( .A ( BUF_net_102 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_102 ( + .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_102 ) ) ; endmodule @@ -69938,7 +74357,7 @@ input [0:0] mem_inv ; output [0:0] out ; input p0 ; -sky130_fd_sc_hd__mux2_2 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , +sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ; endmodule @@ -69972,8 +74391,6 @@ wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ; sb_0__0__const1_14 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) ) ; sb_0__0__mux_2level_tapbuf_basis_input2_mem1_28 mux_l1_in_0_ ( .in ( in ) , .mem ( sram[0] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_2 } ) , @@ -69984,6 +74401,9 @@ sb_0__0__mux_2level_tapbuf_basis_input2_mem1_29 mux_l2_in_0_ ( .mem ( sram[1] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_4 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_85 ( .A ( BUF_net_86 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_86 ( + .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_86 ) ) ; endmodule @@ -70039,9 +74459,9 @@ sb_0__0__mux_2level_tapbuf_basis_input2_mem1_27 mux_l2_in_0_ ( .mem ( sram[1] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_4 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_86 ( .A ( BUF_net_87 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_87 ( - .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_87 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_83 ( .A ( BUF_net_84 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_84 ( + .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_84 ) ) ; endmodule @@ -70097,9 +74517,9 @@ sb_0__0__mux_2level_tapbuf_basis_input2_mem1_25 mux_l2_in_0_ ( .mem ( sram[1] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_4 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_84 ( .A ( BUF_net_85 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_85 ( - .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_85 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_81 ( .A ( BUF_net_82 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_82 ( + .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_82 ) ) ; endmodule @@ -70225,7 +74645,7 @@ input [0:0] mem_inv ; output [0:0] out ; input p0 ; -sky130_fd_sc_hd__mux2_2 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , +sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ; endmodule @@ -70269,8 +74689,9 @@ sb_0__0__mux_2level_tapbuf_basis_input2_mem1_19 mux_l2_in_0_ ( .mem ( sram[1] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_4 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_83 ( - .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_79 ( .A ( BUF_net_80 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_80 ( + .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_80 ) ) ; endmodule @@ -70282,7 +74703,7 @@ input [0:0] mem_inv ; output [0:0] out ; input p0 ; -sky130_fd_sc_hd__mux2_2 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , +sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ; endmodule @@ -70316,6 +74737,8 @@ wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ; sb_0__0__const1_8 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) ) ; sb_0__0__mux_2level_tapbuf_basis_input2_mem1_16 mux_l1_in_0_ ( .in ( in ) , .mem ( sram[0] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_2 } ) , @@ -70326,8 +74749,6 @@ sb_0__0__mux_2level_tapbuf_basis_input2_mem1_17 mux_l2_in_0_ ( .mem ( sram[1] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_4 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_82 ( - .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) ) ; endmodule @@ -70373,6 +74794,8 @@ wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ; sb_0__0__const1_7 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) ) ; sb_0__0__mux_2level_tapbuf_basis_input2_mem1_14 mux_l1_in_0_ ( .in ( in ) , .mem ( sram[0] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_2 } ) , @@ -70383,9 +74806,6 @@ sb_0__0__mux_2level_tapbuf_basis_input2_mem1_15 mux_l2_in_0_ ( .mem ( sram[1] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_4 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_80 ( .A ( BUF_net_81 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_81 ( - .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_81 ) ) ; endmodule @@ -70431,8 +74851,6 @@ wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ; sb_0__0__const1_6 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) ) ; sb_0__0__mux_2level_tapbuf_basis_input2_mem1_12 mux_l1_in_0_ ( .in ( in ) , .mem ( sram[0] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_2 } ) , @@ -70443,6 +74861,9 @@ sb_0__0__mux_2level_tapbuf_basis_input2_mem1_13 mux_l2_in_0_ ( .mem ( sram[1] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_4 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_77 ( .A ( BUF_net_78 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_78 ( + .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_78 ) ) ; endmodule @@ -70454,7 +74875,7 @@ input [0:0] mem_inv ; output [0:0] out ; input p0 ; -sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , +sky130_fd_sc_hd__mux2_2 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ; endmodule @@ -70488,8 +74909,6 @@ wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ; sb_0__0__const1_5 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) ) ; sb_0__0__mux_2level_tapbuf_basis_input2_mem1_10 mux_l1_in_0_ ( .in ( in ) , .mem ( sram[0] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_2 } ) , @@ -70500,6 +74919,8 @@ sb_0__0__mux_2level_tapbuf_basis_input2_mem1_11 mux_l2_in_0_ ( .mem ( sram[1] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_4 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_76 ( + .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) ) ; endmodule @@ -70545,6 +74966,8 @@ wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ; sb_0__0__const1_4 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) ) ; sb_0__0__mux_2level_tapbuf_basis_input2_mem1_8 mux_l1_in_0_ ( .in ( in ) , .mem ( sram[0] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_2 } ) , @@ -70555,9 +74978,6 @@ sb_0__0__mux_2level_tapbuf_basis_input2_mem1_9 mux_l2_in_0_ ( .mem ( sram[1] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_4 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_78 ( .A ( BUF_net_79 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_79 ( - .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_79 ) ) ; endmodule @@ -70670,9 +75090,8 @@ sb_0__0__mux_2level_tapbuf_basis_input2_mem1_5 mux_l2_in_0_ ( .mem ( sram[1] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_4 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_76 ( .A ( BUF_net_77 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_77 ( - .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_77 ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_75 ( + .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) ) ; endmodule @@ -70728,9 +75147,8 @@ sb_0__0__mux_2level_tapbuf_basis_input2_mem1_3 mux_l2_in_0_ ( .mem ( sram[1] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_4 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_74 ( .A ( BUF_net_75 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_75 ( - .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_75 ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_74 ( + .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) ) ; endmodule @@ -70819,6 +75237,7 @@ output [0:0] ccff_tail ; input pReset_E_in ; input prog_clk_0_E_in ; +wire ropt_net_136 ; wire [0:0] prog_clk ; wire prog_clk_0 ; wire [0:1] mux_2level_tapbuf_size2_0_sram ; @@ -70897,22 +75316,22 @@ sb_0__0__mux_2level_tapbuf_size2_0 mux_top_track_0 ( .in ( { top_left_grid_pin_1_[0] , chanx_right_in[1] } ) , .sram ( mux_2level_tapbuf_size2_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 } ) , - .out ( chany_top_out[0] ) , .p0 ( optlc_net_106 ) ) ; + .out ( chany_top_out[0] ) , .p0 ( optlc_net_103 ) ) ; sb_0__0__mux_2level_tapbuf_size2_1 mux_top_track_6 ( .in ( { top_left_grid_pin_1_[0] , chanx_right_in[4] } ) , .sram ( mux_2level_tapbuf_size2_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) , - .out ( chany_top_out[3] ) , .p0 ( optlc_net_106 ) ) ; + .out ( chany_top_out[3] ) , .p0 ( optlc_net_103 ) ) ; sb_0__0__mux_2level_tapbuf_size2_2 mux_top_track_12 ( .in ( { top_left_grid_pin_1_[0] , chanx_right_in[7] } ) , .sram ( mux_2level_tapbuf_size2_2_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 } ) , - .out ( chany_top_out[6] ) , .p0 ( optlc_net_106 ) ) ; + .out ( chany_top_out[6] ) , .p0 ( optlc_net_103 ) ) ; sb_0__0__mux_2level_tapbuf_size2_3 mux_top_track_28 ( .in ( { top_left_grid_pin_1_[0] , chanx_right_in[15] } ) , .sram ( mux_2level_tapbuf_size2_3_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 } ) , - .out ( chany_top_out[14] ) , .p0 ( optlc_net_105 ) ) ; + .out ( chany_top_out[14] ) , .p0 ( optlc_net_103 ) ) ; sb_0__0__mux_2level_tapbuf_size2_4 mux_top_track_44 ( .in ( { top_left_grid_pin_1_[0] , chanx_right_in[23] } ) , .sram ( mux_2level_tapbuf_size2_4_sram ) , @@ -70922,17 +75341,17 @@ sb_0__0__mux_2level_tapbuf_size2_5 mux_right_track_14 ( .in ( { chany_top_in[6] , right_bottom_grid_pin_3_[0] } ) , .sram ( mux_2level_tapbuf_size2_5_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_11 , SYNOPSYS_UNCONNECTED_12 } ) , - .out ( chanx_right_out[7] ) , .p0 ( optlc_net_108 ) ) ; + .out ( chanx_right_out[7] ) , .p0 ( optlc_net_103 ) ) ; sb_0__0__mux_2level_tapbuf_size2_6 mux_right_track_16 ( .in ( { chany_top_in[7] , right_bottom_grid_pin_5_[0] } ) , .sram ( mux_2level_tapbuf_size2_6_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 } ) , - .out ( chanx_right_out[8] ) , .p0 ( optlc_net_104 ) ) ; + .out ( chanx_right_out[8] ) , .p0 ( optlc_net_103 ) ) ; sb_0__0__mux_2level_tapbuf_size2_7 mux_right_track_18 ( .in ( { chany_top_in[8] , right_bottom_grid_pin_7_[0] } ) , .sram ( mux_2level_tapbuf_size2_7_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_15 , SYNOPSYS_UNCONNECTED_16 } ) , - .out ( chanx_right_out[9] ) , .p0 ( optlc_net_104 ) ) ; + .out ( chanx_right_out[9] ) , .p0 ( optlc_net_103 ) ) ; sb_0__0__mux_2level_tapbuf_size2_8 mux_right_track_20 ( .in ( { chany_top_in[9] , right_bottom_grid_pin_9_[0] } ) , .sram ( mux_2level_tapbuf_size2_8_sram ) , @@ -70957,22 +75376,22 @@ sb_0__0__mux_2level_tapbuf_size2_12 mux_right_track_30 ( .in ( { chany_top_in[14] , right_bottom_grid_pin_3_[0] } ) , .sram ( mux_2level_tapbuf_size2_12_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_25 , SYNOPSYS_UNCONNECTED_26 } ) , - .out ( chanx_right_out[15] ) , .p0 ( optlc_net_104 ) ) ; + .out ( chanx_right_out[15] ) , .p0 ( optlc_net_103 ) ) ; sb_0__0__mux_2level_tapbuf_size2_13 mux_right_track_32 ( .in ( { chany_top_in[15] , right_bottom_grid_pin_5_[0] } ) , .sram ( mux_2level_tapbuf_size2_13_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_27 , SYNOPSYS_UNCONNECTED_28 } ) , - .out ( chanx_right_out[16] ) , .p0 ( optlc_net_104 ) ) ; + .out ( chanx_right_out[16] ) , .p0 ( optlc_net_103 ) ) ; sb_0__0__mux_2level_tapbuf_size2_14 mux_right_track_34 ( .in ( { chany_top_in[16] , right_bottom_grid_pin_7_[0] } ) , .sram ( mux_2level_tapbuf_size2_14_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_29 , SYNOPSYS_UNCONNECTED_30 } ) , - .out ( chanx_right_out[17] ) , .p0 ( optlc_net_104 ) ) ; + .out ( chanx_right_out[17] ) , .p0 ( optlc_net_103 ) ) ; sb_0__0__mux_2level_tapbuf_size2_15 mux_right_track_36 ( .in ( { chany_top_in[17] , right_bottom_grid_pin_9_[0] } ) , .sram ( mux_2level_tapbuf_size2_15_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_31 , SYNOPSYS_UNCONNECTED_32 } ) , - .out ( chanx_right_out[18] ) , .p0 ( optlc_net_106 ) ) ; + .out ( chanx_right_out[18] ) , .p0 ( optlc_net_103 ) ) ; sb_0__0__mux_2level_tapbuf_size2_16 mux_right_track_38 ( .in ( { chany_top_in[18] , right_bottom_grid_pin_11_[0] } ) , .sram ( mux_2level_tapbuf_size2_16_sram ) , @@ -70982,7 +75401,7 @@ sb_0__0__mux_2level_tapbuf_size2_17 mux_right_track_40 ( .in ( { chany_top_in[19] , right_bottom_grid_pin_13_[0] } ) , .sram ( mux_2level_tapbuf_size2_17_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_35 , SYNOPSYS_UNCONNECTED_36 } ) , - .out ( chanx_right_out[20] ) , .p0 ( optlc_net_105 ) ) ; + .out ( chanx_right_out[20] ) , .p0 ( optlc_net_106 ) ) ; sb_0__0__mux_2level_tapbuf_size2_18 mux_right_track_42 ( .in ( { chany_top_in[20] , right_bottom_grid_pin_15_[0] } ) , .sram ( mux_2level_tapbuf_size2_18_sram ) , @@ -70997,12 +75416,12 @@ sb_0__0__mux_2level_tapbuf_size2_20 mux_right_track_48 ( .in ( { chany_top_in[23] , right_bottom_grid_pin_5_[0] } ) , .sram ( mux_2level_tapbuf_size2_20_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_41 , SYNOPSYS_UNCONNECTED_42 } ) , - .out ( chanx_right_out[24] ) , .p0 ( optlc_net_104 ) ) ; + .out ( chanx_right_out[24] ) , .p0 ( optlc_net_105 ) ) ; sb_0__0__mux_2level_tapbuf_size2_21 mux_right_track_50 ( .in ( { chany_top_in[24] , right_bottom_grid_pin_7_[0] } ) , .sram ( mux_2level_tapbuf_size2_21_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_43 , SYNOPSYS_UNCONNECTED_44 } ) , - .out ( chanx_right_out[25] ) , .p0 ( optlc_net_104 ) ) ; + .out ( chanx_right_out[25] ) , .p0 ( optlc_net_103 ) ) ; sb_0__0__mux_2level_tapbuf_size2_22 mux_right_track_52 ( .in ( { chany_top_in[25] , right_bottom_grid_pin_9_[0] } ) , .sram ( mux_2level_tapbuf_size2_22_sram ) , @@ -71012,7 +75431,7 @@ sb_0__0__mux_2level_tapbuf_size2_23 mux_right_track_54 ( .in ( { chany_top_in[26] , right_bottom_grid_pin_11_[0] } ) , .sram ( mux_2level_tapbuf_size2_23_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_47 , SYNOPSYS_UNCONNECTED_48 } ) , - .out ( chanx_right_out[27] ) , .p0 ( optlc_net_105 ) ) ; + .out ( chanx_right_out[27] ) , .p0 ( optlc_net_106 ) ) ; sb_0__0__mux_2level_tapbuf_size2_24 mux_right_track_56 ( .in ( { chany_top_in[27] , right_bottom_grid_pin_13_[0] } ) , .sram ( mux_2level_tapbuf_size2_24_sram ) , @@ -71164,7 +75583,7 @@ sb_0__0__mux_2level_tapbuf_size4_1 mux_right_track_2 ( .sram ( mux_2level_tapbuf_size4_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_57 , SYNOPSYS_UNCONNECTED_58 , SYNOPSYS_UNCONNECTED_59 , SYNOPSYS_UNCONNECTED_60 } ) , - .out ( chanx_right_out[1] ) , .p0 ( optlc_net_108 ) ) ; + .out ( chanx_right_out[1] ) , .p0 ( optlc_net_104 ) ) ; sb_0__0__mux_2level_tapbuf_size4_2 mux_right_track_4 ( .in ( { chany_top_in[1] , right_bottom_grid_pin_5_[0] , right_bottom_grid_pin_11_[0] , right_bottom_grid_pin_17_[0] } ) , @@ -71185,14 +75604,14 @@ sb_0__0__mux_2level_tapbuf_size4_4 mux_right_track_8 ( .sram ( mux_2level_tapbuf_size4_4_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_69 , SYNOPSYS_UNCONNECTED_70 , SYNOPSYS_UNCONNECTED_71 , SYNOPSYS_UNCONNECTED_72 } ) , - .out ( chanx_right_out[4] ) , .p0 ( optlc_net_108 ) ) ; + .out ( chanx_right_out[4] ) , .p0 ( optlc_net_104 ) ) ; sb_0__0__mux_2level_tapbuf_size4 mux_right_track_10 ( .in ( { chany_top_in[4] , right_bottom_grid_pin_5_[0] , right_bottom_grid_pin_11_[0] , right_bottom_grid_pin_17_[0] } ) , .sram ( mux_2level_tapbuf_size4_5_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_73 , SYNOPSYS_UNCONNECTED_74 , SYNOPSYS_UNCONNECTED_75 , SYNOPSYS_UNCONNECTED_76 } ) , - .out ( chanx_right_out[5] ) , .p0 ( optlc_net_108 ) ) ; + .out ( chanx_right_out[5] ) , .p0 ( optlc_net_104 ) ) ; sb_0__0__mux_2level_tapbuf_size4_mem_0 mem_right_track_0 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( mux_2level_tapbuf_size2_mem_4_ccff_tail ) , @@ -71228,7 +75647,7 @@ sb_0__0__mux_2level_tapbuf_size3_0 mux_right_track_12 ( right_bottom_grid_pin_17_[0] } ) , .sram ( mux_2level_tapbuf_size3_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_77 , SYNOPSYS_UNCONNECTED_78 } ) , - .out ( chanx_right_out[6] ) , .p0 ( optlc_net_108 ) ) ; + .out ( chanx_right_out[6] ) , .p0 ( optlc_net_105 ) ) ; sb_0__0__mux_2level_tapbuf_size3_1 mux_right_track_28 ( .in ( { chany_top_in[13] , right_bottom_grid_pin_1_[0] , right_bottom_grid_pin_17_[0] } ) , @@ -71279,7 +75698,7 @@ sky130_fd_sc_hd__buf_8 FTB_56__55 ( .A ( chanx_right_in[11] ) , .X ( chany_top_out[10] ) ) ; sky130_fd_sc_hd__buf_8 FTB_57__56 ( .A ( chanx_right_in[12] ) , .X ( chany_top_out[11] ) ) ; -sky130_fd_sc_hd__buf_8 FTB_58__57 ( .A ( chanx_right_in[13] ) , +sky130_fd_sc_hd__buf_6 FTB_58__57 ( .A ( chanx_right_in[13] ) , .X ( chany_top_out[12] ) ) ; sky130_fd_sc_hd__buf_8 FTB_59__58 ( .A ( chanx_right_in[14] ) , .X ( chany_top_out[13] ) ) ; @@ -71303,22 +75722,24 @@ sky130_fd_sc_hd__buf_8 FTB_68__67 ( .A ( chanx_right_in[25] ) , .X ( chany_top_out[24] ) ) ; sky130_fd_sc_hd__buf_6 FTB_69__68 ( .A ( chanx_right_in[26] ) , .X ( chany_top_out[25] ) ) ; -sky130_fd_sc_hd__buf_8 FTB_70__69 ( .A ( chanx_right_in[27] ) , - .X ( chany_top_out[26] ) ) ; +sky130_fd_sc_hd__buf_6 FTB_70__69 ( .A ( chanx_right_in[27] ) , + .X ( ropt_net_136 ) ) ; sky130_fd_sc_hd__buf_8 FTB_71__70 ( .A ( chanx_right_in[28] ) , .X ( chany_top_out[27] ) ) ; sky130_fd_sc_hd__buf_8 FTB_72__71 ( .A ( chanx_right_in[29] ) , .X ( chany_top_out[28] ) ) ; -sky130_fd_sc_hd__conb_1 optlc_106 ( .LO ( SYNOPSYS_UNCONNECTED_83 ) , +sky130_fd_sc_hd__conb_1 optlc_105 ( .LO ( SYNOPSYS_UNCONNECTED_83 ) , + .HI ( optlc_net_103 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_107 ( .LO ( SYNOPSYS_UNCONNECTED_84 ) , .HI ( optlc_net_104 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_109 ( .LO ( SYNOPSYS_UNCONNECTED_84 ) , +sky130_fd_sc_hd__conb_1 optlc_109 ( .LO ( SYNOPSYS_UNCONNECTED_85 ) , .HI ( optlc_net_105 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_111 ( .LO ( SYNOPSYS_UNCONNECTED_85 ) , +sky130_fd_sc_hd__conb_1 optlc_111 ( .LO ( SYNOPSYS_UNCONNECTED_86 ) , .HI ( optlc_net_106 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_113 ( .LO ( SYNOPSYS_UNCONNECTED_86 ) , +sky130_fd_sc_hd__conb_1 optlc_113 ( .LO ( SYNOPSYS_UNCONNECTED_87 ) , .HI ( optlc_net_107 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_115 ( .LO ( SYNOPSYS_UNCONNECTED_87 ) , - .HI ( optlc_net_108 ) ) ; +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1317 ( .A ( ropt_net_136 ) , + .X ( chany_top_out[26] ) ) ; endmodule @@ -71334,18 +75755,18 @@ sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__buf_6 FTB_111__110 ( .A ( copt_net_248 ) , +sky130_fd_sc_hd__buf_6 FTB_111__110 ( .A ( copt_net_243 ) , .X ( ccff_tail[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1706 ( .A ( copt_net_250 ) , - .X ( copt_net_246 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1707 ( .A ( copt_net_246 ) , - .X ( copt_net_247 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1708 ( .A ( copt_net_247 ) , - .X ( copt_net_248 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1709 ( .A ( mem_out[1] ) , - .X ( copt_net_249 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1710 ( .A ( copt_net_249 ) , - .X ( copt_net_250 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1596 ( .A ( mem_out[1] ) , + .X ( copt_net_239 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1597 ( .A ( copt_net_242 ) , + .X ( copt_net_240 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1598 ( .A ( copt_net_240 ) , + .X ( copt_net_241 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1599 ( .A ( copt_net_239 ) , + .X ( copt_net_242 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1600 ( .A ( copt_net_241 ) , + .X ( copt_net_243 ) ) ; endmodule @@ -71366,14 +75787,14 @@ sky130_fd_sc_hd__buf_1 FTB_110__109 ( .A ( mem_out[1] ) , endmodule -module grid_clb_mux_1level_basis_input3_mem3 ( in , mem , mem_inv , out , p0 ) ; +module grid_clb_mux_1level_basis_input3_mem3 ( in , mem , mem_inv , out , p3 ) ; input [0:2] in ; input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; -input p0 ; +input p3 ; -scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , +scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p3 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out[0] ) ) ; @@ -71401,12 +75822,12 @@ output [0:0] const1 ; endmodule -module grid_clb_mux_1level_size2 ( in , sram , sram_inv , out , p0 ) ; +module grid_clb_mux_1level_size2 ( in , sram , sram_inv , out , p3 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; output [0:0] out ; -input p0 ; +input p3 ; wire [0:2] local_encoder2to3_0_data ; wire [0:2] local_encoder2to3_0_data_inv ; @@ -71423,7 +75844,7 @@ grid_clb_mux_1level_basis_input3_mem3 mux_l1_in_0_ ( .in ( { in[0] , in[1] , SYNOPSYS_UNCONNECTED_2 } ) , .mem ( local_encoder2to3_0_data ) , .mem_inv ( local_encoder2to3_0_data_inv ) , - .out ( mux_1level_basis_input3_mem3_0_out ) , .p0 ( p0 ) ) ; + .out ( mux_1level_basis_input3_mem3_0_out ) , .p3 ( p3 ) ) ; endmodule @@ -71582,9 +76003,9 @@ grid_clb_mux_1level_tapbuf_basis_input3_mem3 mux_l1_in_0_ ( .mem ( local_encoder2to3_0_data ) , .mem_inv ( local_encoder2to3_0_data_inv ) , .out ( mux_1level_tapbuf_basis_input3_mem3_0_out ) , .p3 ( p3 ) ) ; -sky130_fd_sc_hd__inv_2 BINV_R_178 ( +sky130_fd_sc_hd__inv_8 BINV_R_177 ( .A ( mux_1level_tapbuf_basis_input3_mem3_0_out[0] ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_179 ( +sky130_fd_sc_hd__inv_2 BINV_R_178 ( .A ( mux_1level_tapbuf_basis_input3_mem3_0_out[0] ) , .Y ( p_abuf0 ) ) ; endmodule @@ -71648,16 +76069,15 @@ grid_clb_mux_1level_tapbuf_basis_input3_mem3_14 mux_l1_in_0_ ( .mem ( local_encoder2to3_0_data ) , .mem_inv ( local_encoder2to3_0_data_inv ) , .out ( mux_1level_tapbuf_basis_input3_mem3_0_out ) , .p3 ( p3 ) ) ; -sky130_fd_sc_hd__inv_2 BINV_R_175 ( +sky130_fd_sc_hd__inv_2 BINV_R_174 ( .A ( mux_1level_tapbuf_basis_input3_mem3_0_out[0] ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_176 ( +sky130_fd_sc_hd__inv_8 BINV_R_175 ( .A ( mux_1level_tapbuf_basis_input3_mem3_0_out[0] ) , .Y ( p_abuf0 ) ) ; endmodule module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff ( - Test_en , ff_D , ff_DI , ff_reset , ff_Q , ff_clk , p_abuf0 , p_abuf1 , - p_abuf2 ) ; + Test_en , ff_D , ff_DI , ff_reset , ff_Q , ff_clk , p_abuf0 , p_abuf1 ) ; input [0:0] Test_en ; input [0:0] ff_D ; input [0:0] ff_DI ; @@ -71666,15 +76086,13 @@ output [0:0] ff_Q ; input [0:0] ff_clk ; output p_abuf0 ; output p_abuf1 ; -output p_abuf2 ; sky130_fd_sc_hd__sdfrtp_1 sky130_fd_sc_hd__sdfrtp_1_0_ ( .D ( ff_D[0] ) , .SCD ( ff_DI[0] ) , .SCE ( Test_en[0] ) , .CLK ( ff_clk[0] ) , - .RESET_B ( ff_reset[0] ) , .Q ( p_abuf2 ) ) ; -sky130_fd_sc_hd__inv_2 BINV_R_129 ( .A ( BUF_net_132 ) , .Y ( ff_Q[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_130 ( .A ( BUF_net_132 ) , .Y ( p_abuf0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_131 ( .A ( BUF_net_132 ) , .Y ( p_abuf1 ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_132 ( .A ( p_abuf2 ) , .Y ( BUF_net_132 ) ) ; + .RESET_B ( ff_reset[0] ) , .Q ( p_abuf1 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_129 ( .A ( BUF_net_131 ) , .Y ( ff_Q[0] ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_130 ( .A ( BUF_net_131 ) , .Y ( p_abuf0 ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_131 ( .A ( p_abuf1 ) , .Y ( BUF_net_131 ) ) ; endmodule @@ -72130,7 +76548,7 @@ module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric ( pReset , prog_clk , Test_en , fabric_in , fabric_reg_in , fabric_sc_in , fabric_cin , fabric_reset , fabric_clk , ccff_head , fabric_out , fabric_reg_out , fabric_sc_out , fabric_cout , ccff_tail , p_abuf0 , - p_abuf3 , p_abuf4 , p0 , p3 ) ; + p_abuf2 , p_abuf3 , p0 , p3 ) ; input [0:0] pReset ; input [0:0] prog_clk ; input [0:0] Test_en ; @@ -72147,8 +76565,8 @@ output [0:0] fabric_sc_out ; output [0:0] fabric_cout ; output [0:0] ccff_tail ; output p_abuf0 ; +output p_abuf2 ; output p_abuf3 ; -output p_abuf4 ; input p0 ; input p3 ; @@ -72185,8 +76603,7 @@ grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ .Test_en ( Test_en ) , .ff_D ( mux_1level_size2_1_out ) , .ff_DI ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ) , .ff_reset ( fabric_reset ) , .ff_Q ( fabric_sc_out ) , - .ff_clk ( fabric_clk ) , .p_abuf0 ( aps_rename_506_ ) , - .p_abuf1 ( p_abuf0 ) , .p_abuf2 ( p_abuf2 ) ) ; + .ff_clk ( fabric_clk ) , .p_abuf0 ( p_abuf0 ) , .p_abuf1 ( p_abuf1 ) ) ; grid_clb_mux_1level_tapbuf_size2_14 mux_fabric_out_0 ( .in ( { logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q[0] , @@ -72194,14 +76611,14 @@ grid_clb_mux_1level_tapbuf_size2_14 mux_fabric_out_0 ( } ) , .sram ( mux_1level_tapbuf_size2_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_2 , SYNOPSYS_UNCONNECTED_3 } ) , - .out ( fabric_out[0] ) , .p_abuf0 ( p_abuf3 ) , .p3 ( p3 ) ) ; + .out ( fabric_out[0] ) , .p_abuf0 ( p_abuf2 ) , .p3 ( p3 ) ) ; grid_clb_mux_1level_tapbuf_size2 mux_fabric_out_1 ( - .in ( { aps_rename_506_ , + .in ( { p_abuf0 , logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] } ) , .sram ( mux_1level_tapbuf_size2_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_4 , SYNOPSYS_UNCONNECTED_5 } ) , - .out ( fabric_out[1] ) , .p_abuf0 ( p_abuf4 ) , .p3 ( p3 ) ) ; + .out ( fabric_out[1] ) , .p_abuf0 ( p_abuf3 ) , .p3 ( p3 ) ) ; grid_clb_mux_1level_tapbuf_size2_mem_14 mem_fabric_out_0 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) , @@ -72212,7 +76629,7 @@ grid_clb_mux_1level_tapbuf_size2_mem mem_fabric_out_1 ( .pReset ( pReset ) , .ccff_head ( mux_1level_tapbuf_size2_mem_0_ccff_tail ) , .ccff_tail ( mux_1level_tapbuf_size2_mem_1_ccff_tail ) , .mem_out ( mux_1level_tapbuf_size2_1_sram ) ) ; -sky130_fd_sc_hd__buf_6 FTB_112__111 ( .A ( p_abuf2 ) , +sky130_fd_sc_hd__buf_6 FTB_112__111 ( .A ( p_abuf1 ) , .X ( fabric_reg_out[0] ) ) ; grid_clb_mux_1level_size2_30 mux_ff_0_D_0 ( .in ( { @@ -72228,7 +76645,7 @@ grid_clb_mux_1level_size2 mux_ff_1_D_0 ( } ) , .sram ( mux_1level_size2_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_8 , SYNOPSYS_UNCONNECTED_9 } ) , - .out ( mux_1level_size2_1_out ) , .p0 ( p0 ) ) ; + .out ( mux_1level_size2_1_out ) , .p3 ( p3 ) ) ; grid_clb_mux_1level_size2_mem_30 mem_ff_0_D_0 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( mux_1level_tapbuf_size2_mem_1_ccff_tail ) , @@ -72274,7 +76691,7 @@ grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric logical_tile_c .ccff_head ( ccff_head ) , .fabric_out ( fle_out ) , .fabric_reg_out ( fle_reg_out ) , .fabric_sc_out ( fle_sc_out ) , .fabric_cout ( fle_cout ) , .ccff_tail ( ccff_tail ) , - .p_abuf0 ( p_abuf0 ) , .p_abuf3 ( p_abuf1 ) , .p_abuf4 ( p_abuf2 ) , + .p_abuf0 ( p_abuf0 ) , .p_abuf2 ( p_abuf1 ) , .p_abuf3 ( p_abuf2 ) , .p0 ( p0 ) , .p3 ( p3 ) ) ; endmodule @@ -72312,14 +76729,14 @@ endmodule module grid_clb_mux_1level_basis_input3_mem3_27 ( in , mem , mem_inv , out , - p6 ) ; + p3 ) ; input [0:2] in ; input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; -input p6 ; +input p3 ; -scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p6 ) , +scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p3 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out[0] ) ) ; @@ -72347,12 +76764,12 @@ output [0:0] const1 ; endmodule -module grid_clb_mux_1level_size2_27 ( in , sram , sram_inv , out , p6 ) ; +module grid_clb_mux_1level_size2_27 ( in , sram , sram_inv , out , p3 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; output [0:0] out ; -input p6 ; +input p3 ; wire [0:2] local_encoder2to3_0_data ; wire [0:2] local_encoder2to3_0_data_inv ; @@ -72369,19 +76786,19 @@ grid_clb_mux_1level_basis_input3_mem3_27 mux_l1_in_0_ ( .in ( { in[0] , in[1] , SYNOPSYS_UNCONNECTED_2 } ) , .mem ( local_encoder2to3_0_data ) , .mem_inv ( local_encoder2to3_0_data_inv ) , - .out ( mux_1level_basis_input3_mem3_0_out ) , .p6 ( p6 ) ) ; + .out ( mux_1level_basis_input3_mem3_0_out ) , .p3 ( p3 ) ) ; endmodule module grid_clb_mux_1level_basis_input3_mem3_26 ( in , mem , mem_inv , out , - p6 ) ; + p0 ) ; input [0:2] in ; input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; -input p6 ; +input p0 ; -scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p6 ) , +scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out[0] ) ) ; @@ -72409,12 +76826,12 @@ output [0:0] const1 ; endmodule -module grid_clb_mux_1level_size2_26 ( in , sram , sram_inv , out , p6 ) ; +module grid_clb_mux_1level_size2_26 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; output [0:0] out ; -input p6 ; +input p0 ; wire [0:2] local_encoder2to3_0_data ; wire [0:2] local_encoder2to3_0_data_inv ; @@ -72431,7 +76848,7 @@ grid_clb_mux_1level_basis_input3_mem3_26 mux_l1_in_0_ ( .in ( { in[0] , in[1] , SYNOPSYS_UNCONNECTED_2 } ) , .mem ( local_encoder2to3_0_data ) , .mem_inv ( local_encoder2to3_0_data_inv ) , - .out ( mux_1level_basis_input3_mem3_0_out ) , .p6 ( p6 ) ) ; + .out ( mux_1level_basis_input3_mem3_0_out ) , .p0 ( p0 ) ) ; endmodule @@ -72526,9 +76943,9 @@ grid_clb_mux_1level_tapbuf_basis_input3_mem3_13 mux_l1_in_0_ ( .mem ( local_encoder2to3_0_data ) , .mem_inv ( local_encoder2to3_0_data_inv ) , .out ( mux_1level_tapbuf_basis_input3_mem3_0_out ) , .p3 ( p3 ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_172 ( +sky130_fd_sc_hd__inv_8 BINV_R_171 ( .A ( mux_1level_tapbuf_basis_input3_mem3_0_out[0] ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_173 ( +sky130_fd_sc_hd__inv_1 BINV_R_172 ( .A ( mux_1level_tapbuf_basis_input3_mem3_0_out[0] ) , .Y ( p_abuf0 ) ) ; endmodule @@ -72592,9 +77009,9 @@ grid_clb_mux_1level_tapbuf_basis_input3_mem3_12 mux_l1_in_0_ ( .mem ( local_encoder2to3_0_data ) , .mem_inv ( local_encoder2to3_0_data_inv ) , .out ( mux_1level_tapbuf_basis_input3_mem3_0_out ) , .p3 ( p3 ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_169 ( +sky130_fd_sc_hd__inv_1 BINV_R_168 ( .A ( mux_1level_tapbuf_basis_input3_mem3_0_out[0] ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_170 ( +sky130_fd_sc_hd__inv_8 BINV_R_169 ( .A ( mux_1level_tapbuf_basis_input3_mem3_0_out[0] ) , .Y ( p_abuf0 ) ) ; endmodule @@ -72724,14 +77141,14 @@ endmodule module grid_clb_mux_1level_basis_input3_mem3_24 ( in , mem , mem_inv , out , - p6 ) ; + p3 ) ; input [0:2] in ; input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; -input p6 ; +input p3 ; -scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p6 ) , +scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p3 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out[0] ) ) ; @@ -72759,12 +77176,12 @@ output [0:0] const1 ; endmodule -module grid_clb_mux_1level_size2_24 ( in , sram , sram_inv , out , p6 ) ; +module grid_clb_mux_1level_size2_24 ( in , sram , sram_inv , out , p3 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; output [0:0] out ; -input p6 ; +input p3 ; wire [0:2] local_encoder2to3_0_data ; wire [0:2] local_encoder2to3_0_data_inv ; @@ -72781,7 +77198,7 @@ grid_clb_mux_1level_basis_input3_mem3_24 mux_l1_in_0_ ( .in ( { in[0] , in[1] , SYNOPSYS_UNCONNECTED_2 } ) , .mem ( local_encoder2to3_0_data ) , .mem_inv ( local_encoder2to3_0_data_inv ) , - .out ( mux_1level_basis_input3_mem3_0_out ) , .p6 ( p6 ) ) ; + .out ( mux_1level_basis_input3_mem3_0_out ) , .p3 ( p3 ) ) ; endmodule @@ -72998,7 +77415,7 @@ endmodule module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_6 ( pReset , prog_clk , frac_logic_in , frac_logic_cin , ccff_head , - frac_logic_out , frac_logic_cout , ccff_tail , p3 , p6 ) ; + frac_logic_out , frac_logic_cout , ccff_tail , p3 ) ; input [0:0] pReset ; input [0:0] prog_clk ; input [0:3] frac_logic_in ; @@ -73008,7 +77425,6 @@ output [0:1] frac_logic_out ; output [0:0] frac_logic_cout ; output [0:0] ccff_tail ; input p3 ; -input p6 ; wire [0:0] direct_interc_5_out ; wire [0:0] direct_interc_7_out ; @@ -73044,7 +77460,7 @@ grid_clb_mux_1level_size2_24 mux_frac_logic_out_0 ( } ) , .sram ( mux_1level_size2_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_2 , SYNOPSYS_UNCONNECTED_3 } ) , - .out ( frac_logic_out[0] ) , .p6 ( p6 ) ) ; + .out ( frac_logic_out[0] ) , .p3 ( p3 ) ) ; grid_clb_mux_1level_size2_25 mux_frac_lut4_0_in_2 ( .in ( { frac_logic_cin[0] , frac_logic_in[2] } ) , .sram ( mux_1level_size2_1_sram ) , @@ -73065,7 +77481,7 @@ module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_6 ( pReset , prog_clk , Test_en , fabric_in , fabric_reg_in , fabric_sc_in , fabric_cin , fabric_reset , fabric_clk , ccff_head , fabric_out , fabric_reg_out , fabric_sc_out , fabric_cout , ccff_tail , p_abuf0 , - p_abuf1 , p3 , p6 ) ; + p_abuf1 , p0 , p3 ) ; input [0:0] pReset ; input [0:0] prog_clk ; input [0:0] Test_en ; @@ -73083,8 +77499,8 @@ output [0:0] fabric_cout ; output [0:0] ccff_tail ; output p_abuf0 ; output p_abuf1 ; +input p0 ; input p3 ; -input p6 ; wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ; wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ; @@ -73109,7 +77525,7 @@ grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ .frac_logic_cout ( { SYNOPSYS_UNCONNECTED_1 } ) , .ccff_tail ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) , - .p3 ( p3 ) , .p6 ( p6 ) ) ; + .p3 ( p3 ) ) ; grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_12 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0 ( .Test_en ( Test_en ) , .ff_D ( mux_1level_size2_0_out ) , .ff_DI ( fabric_sc_in ) , .ff_reset ( fabric_reset ) , @@ -73153,7 +77569,7 @@ grid_clb_mux_1level_size2_26 mux_ff_0_D_0 ( fabric_reg_in[0] } ) , .sram ( mux_1level_size2_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_6 , SYNOPSYS_UNCONNECTED_7 } ) , - .out ( mux_1level_size2_0_out ) , .p6 ( p6 ) ) ; + .out ( mux_1level_size2_0_out ) , .p0 ( p0 ) ) ; grid_clb_mux_1level_size2_27 mux_ff_1_D_0 ( .in ( { logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] , @@ -73161,7 +77577,7 @@ grid_clb_mux_1level_size2_27 mux_ff_1_D_0 ( } ) , .sram ( mux_1level_size2_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_8 , SYNOPSYS_UNCONNECTED_9 } ) , - .out ( mux_1level_size2_1_out ) , .p6 ( p6 ) ) ; + .out ( mux_1level_size2_1_out ) , .p3 ( p3 ) ) ; grid_clb_mux_1level_size2_mem_26 mem_ff_0_D_0 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( mux_1level_tapbuf_size2_mem_1_ccff_tail ) , @@ -73176,7 +77592,7 @@ endmodule module grid_clb_logical_tile_clb_mode_default__fle_6 ( pReset , prog_clk , Test_en , fle_in , fle_reg_in , fle_sc_in , fle_cin , fle_reset , fle_clk , ccff_head , fle_out , fle_reg_out , fle_sc_out , fle_cout , - ccff_tail , p_abuf0 , p_abuf1 , p3 , p6 ) ; + ccff_tail , p_abuf0 , p_abuf1 , p0 , p3 ) ; input [0:0] pReset ; input [0:0] prog_clk ; input [0:0] Test_en ; @@ -73194,8 +77610,8 @@ output [0:0] fle_cout ; output [0:0] ccff_tail ; output p_abuf0 ; output p_abuf1 ; +input p0 ; input p3 ; -input p6 ; grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_6 logical_tile_clb_mode_default__fle_mode_physical__fabric_0 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , @@ -73207,7 +77623,7 @@ grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_6 logical_tile .fabric_reg_out ( fle_reg_out ) , .fabric_sc_out ( fle_sc_out ) , .fabric_cout ( { SYNOPSYS_UNCONNECTED_2 } ) , .ccff_tail ( ccff_tail ) , .p_abuf0 ( p_abuf0 ) , .p_abuf1 ( p_abuf1 ) , - .p3 ( p3 ) , .p6 ( p6 ) ) ; + .p0 ( p0 ) , .p3 ( p3 ) ) ; endmodule @@ -73306,14 +77722,14 @@ endmodule module grid_clb_mux_1level_basis_input3_mem3_22 ( in , mem , mem_inv , out , - p6 ) ; + p0 ) ; input [0:2] in ; input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; -input p6 ; +input p0 ; -scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p6 ) , +scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out[0] ) ) ; @@ -73341,12 +77757,12 @@ output [0:0] const1 ; endmodule -module grid_clb_mux_1level_size2_22 ( in , sram , sram_inv , out , p6 ) ; +module grid_clb_mux_1level_size2_22 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; output [0:0] out ; -input p6 ; +input p0 ; wire [0:2] local_encoder2to3_0_data ; wire [0:2] local_encoder2to3_0_data_inv ; @@ -73363,7 +77779,7 @@ grid_clb_mux_1level_basis_input3_mem3_22 mux_l1_in_0_ ( .in ( { in[0] , in[1] , SYNOPSYS_UNCONNECTED_2 } ) , .mem ( local_encoder2to3_0_data ) , .mem_inv ( local_encoder2to3_0_data_inv ) , - .out ( mux_1level_basis_input3_mem3_0_out ) , .p6 ( p6 ) ) ; + .out ( mux_1level_basis_input3_mem3_0_out ) , .p0 ( p0 ) ) ; endmodule @@ -73400,14 +77816,14 @@ endmodule module grid_clb_mux_1level_tapbuf_basis_input3_mem3_11 ( in , mem , mem_inv , - out , p6 ) ; + out , p3 ) ; input [0:2] in ; input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; -input p6 ; +input p3 ; -scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p6 ) , +scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p3 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out[0] ) ) ; @@ -73436,13 +77852,13 @@ endmodule module grid_clb_mux_1level_tapbuf_size2_11 ( in , sram , sram_inv , out , - p_abuf0 , p6 ) ; + p_abuf0 , p3 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; output [0:0] out ; output p_abuf0 ; -input p6 ; +input p3 ; wire [0:2] local_encoder2to3_0_data ; wire [0:2] local_encoder2to3_0_data_inv ; @@ -73457,23 +77873,23 @@ grid_clb_mux_1level_tapbuf_basis_input3_mem3_11 mux_l1_in_0_ ( .in ( { in[0] , in[1] , SYNOPSYS_UNCONNECTED_2 } ) , .mem ( local_encoder2to3_0_data ) , .mem_inv ( local_encoder2to3_0_data_inv ) , - .out ( mux_1level_tapbuf_basis_input3_mem3_0_out ) , .p6 ( p6 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_166 ( + .out ( mux_1level_tapbuf_basis_input3_mem3_0_out ) , .p3 ( p3 ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_165 ( .A ( mux_1level_tapbuf_basis_input3_mem3_0_out[0] ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_167 ( +sky130_fd_sc_hd__inv_8 BINV_R_166 ( .A ( mux_1level_tapbuf_basis_input3_mem3_0_out[0] ) , .Y ( p_abuf0 ) ) ; endmodule module grid_clb_mux_1level_tapbuf_basis_input3_mem3_10 ( in , mem , mem_inv , - out , p6 ) ; + out , p3 ) ; input [0:2] in ; input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; -input p6 ; +input p3 ; -scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p6 ) , +scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p3 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out[0] ) ) ; @@ -73502,13 +77918,13 @@ endmodule module grid_clb_mux_1level_tapbuf_size2_10 ( in , sram , sram_inv , out , - p_abuf0 , p6 ) ; + p_abuf0 , p3 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; output [0:0] out ; output p_abuf0 ; -input p6 ; +input p3 ; wire [0:2] local_encoder2to3_0_data ; wire [0:2] local_encoder2to3_0_data_inv ; @@ -73523,10 +77939,10 @@ grid_clb_mux_1level_tapbuf_basis_input3_mem3_10 mux_l1_in_0_ ( .in ( { in[0] , in[1] , SYNOPSYS_UNCONNECTED_2 } ) , .mem ( local_encoder2to3_0_data ) , .mem_inv ( local_encoder2to3_0_data_inv ) , - .out ( mux_1level_tapbuf_basis_input3_mem3_0_out ) , .p6 ( p6 ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_163 ( + .out ( mux_1level_tapbuf_basis_input3_mem3_0_out ) , .p3 ( p3 ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_162 ( .A ( mux_1level_tapbuf_basis_input3_mem3_0_out[0] ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_164 ( +sky130_fd_sc_hd__inv_8 BINV_R_163 ( .A ( mux_1level_tapbuf_basis_input3_mem3_0_out[0] ) , .Y ( p_abuf0 ) ) ; endmodule @@ -73996,7 +78412,7 @@ module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_5 ( pReset , prog_clk , Test_en , fabric_in , fabric_reg_in , fabric_sc_in , fabric_cin , fabric_reset , fabric_clk , ccff_head , fabric_out , fabric_reg_out , fabric_sc_out , fabric_cout , ccff_tail , p_abuf0 , - p_abuf1 , p6 ) ; + p_abuf1 , p0 , p3 , p6 ) ; input [0:0] pReset ; input [0:0] prog_clk ; input [0:0] Test_en ; @@ -74014,6 +78430,8 @@ output [0:0] fabric_cout ; output [0:0] ccff_tail ; output p_abuf0 ; output p_abuf1 ; +input p0 ; +input p3 ; input p6 ; wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ; @@ -74057,14 +78475,14 @@ grid_clb_mux_1level_tapbuf_size2_10 mux_fabric_out_0 ( } ) , .sram ( mux_1level_tapbuf_size2_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_2 , SYNOPSYS_UNCONNECTED_3 } ) , - .out ( fabric_out[0] ) , .p_abuf0 ( p_abuf0 ) , .p6 ( p6 ) ) ; + .out ( fabric_out[0] ) , .p_abuf0 ( p_abuf0 ) , .p3 ( p3 ) ) ; grid_clb_mux_1level_tapbuf_size2_11 mux_fabric_out_1 ( .in ( { fabric_sc_out[0] , logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] } ) , .sram ( mux_1level_tapbuf_size2_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_4 , SYNOPSYS_UNCONNECTED_5 } ) , - .out ( fabric_out[1] ) , .p_abuf0 ( p_abuf1 ) , .p6 ( p6 ) ) ; + .out ( fabric_out[1] ) , .p_abuf0 ( p_abuf1 ) , .p3 ( p3 ) ) ; grid_clb_mux_1level_tapbuf_size2_mem_10 mem_fabric_out_0 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) , @@ -74083,7 +78501,7 @@ grid_clb_mux_1level_size2_22 mux_ff_0_D_0 ( fabric_reg_in[0] } ) , .sram ( mux_1level_size2_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_6 , SYNOPSYS_UNCONNECTED_7 } ) , - .out ( mux_1level_size2_0_out ) , .p6 ( p6 ) ) ; + .out ( mux_1level_size2_0_out ) , .p0 ( p0 ) ) ; grid_clb_mux_1level_size2_23 mux_ff_1_D_0 ( .in ( { logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] , @@ -74106,7 +78524,7 @@ endmodule module grid_clb_logical_tile_clb_mode_default__fle_5 ( pReset , prog_clk , Test_en , fle_in , fle_reg_in , fle_sc_in , fle_cin , fle_reset , fle_clk , ccff_head , fle_out , fle_reg_out , fle_sc_out , fle_cout , - ccff_tail , p_abuf0 , p_abuf1 , p6 ) ; + ccff_tail , p_abuf0 , p_abuf1 , p0 , p3 , p6 ) ; input [0:0] pReset ; input [0:0] prog_clk ; input [0:0] Test_en ; @@ -74124,6 +78542,8 @@ output [0:0] fle_cout ; output [0:0] ccff_tail ; output p_abuf0 ; output p_abuf1 ; +input p0 ; +input p3 ; input p6 ; grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_5 logical_tile_clb_mode_default__fle_mode_physical__fabric_0 ( @@ -74136,7 +78556,7 @@ grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_5 logical_tile .fabric_reg_out ( fle_reg_out ) , .fabric_sc_out ( fle_sc_out ) , .fabric_cout ( { SYNOPSYS_UNCONNECTED_2 } ) , .ccff_tail ( ccff_tail ) , .p_abuf0 ( p_abuf0 ) , .p_abuf1 ( p_abuf1 ) , - .p6 ( p6 ) ) ; + .p0 ( p0 ) , .p3 ( p3 ) , .p6 ( p6 ) ) ; endmodule @@ -74173,14 +78593,14 @@ endmodule module grid_clb_mux_1level_basis_input3_mem3_19 ( in , mem , mem_inv , out , - p0 ) ; + p6 ) ; input [0:2] in ; input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; -input p0 ; +input p6 ; -scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , +scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p6 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out[0] ) ) ; @@ -74208,12 +78628,12 @@ output [0:0] const1 ; endmodule -module grid_clb_mux_1level_size2_19 ( in , sram , sram_inv , out , p0 ) ; +module grid_clb_mux_1level_size2_19 ( in , sram , sram_inv , out , p6 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; output [0:0] out ; -input p0 ; +input p6 ; wire [0:2] local_encoder2to3_0_data ; wire [0:2] local_encoder2to3_0_data_inv ; @@ -74230,19 +78650,19 @@ grid_clb_mux_1level_basis_input3_mem3_19 mux_l1_in_0_ ( .in ( { in[0] , in[1] , SYNOPSYS_UNCONNECTED_2 } ) , .mem ( local_encoder2to3_0_data ) , .mem_inv ( local_encoder2to3_0_data_inv ) , - .out ( mux_1level_basis_input3_mem3_0_out ) , .p0 ( p0 ) ) ; + .out ( mux_1level_basis_input3_mem3_0_out ) , .p6 ( p6 ) ) ; endmodule module grid_clb_mux_1level_basis_input3_mem3_18 ( in , mem , mem_inv , out , - p0 ) ; + p6 ) ; input [0:2] in ; input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; -input p0 ; +input p6 ; -scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , +scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p6 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out[0] ) ) ; @@ -74270,12 +78690,12 @@ output [0:0] const1 ; endmodule -module grid_clb_mux_1level_size2_18 ( in , sram , sram_inv , out , p0 ) ; +module grid_clb_mux_1level_size2_18 ( in , sram , sram_inv , out , p6 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; output [0:0] out ; -input p0 ; +input p6 ; wire [0:2] local_encoder2to3_0_data ; wire [0:2] local_encoder2to3_0_data_inv ; @@ -74292,7 +78712,7 @@ grid_clb_mux_1level_basis_input3_mem3_18 mux_l1_in_0_ ( .in ( { in[0] , in[1] , SYNOPSYS_UNCONNECTED_2 } ) , .mem ( local_encoder2to3_0_data ) , .mem_inv ( local_encoder2to3_0_data_inv ) , - .out ( mux_1level_basis_input3_mem3_0_out ) , .p0 ( p0 ) ) ; + .out ( mux_1level_basis_input3_mem3_0_out ) , .p6 ( p6 ) ) ; endmodule @@ -74329,14 +78749,14 @@ endmodule module grid_clb_mux_1level_tapbuf_basis_input3_mem3_9 ( in , mem , mem_inv , - out , p0 ) ; + out , p6 ) ; input [0:2] in ; input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; -input p0 ; +input p6 ; -scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , +scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p6 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out[0] ) ) ; @@ -74365,13 +78785,13 @@ endmodule module grid_clb_mux_1level_tapbuf_size2_9 ( in , sram , sram_inv , out , - p_abuf0 , p0 ) ; + p_abuf0 , p6 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; output [0:0] out ; output p_abuf0 ; -input p0 ; +input p6 ; wire [0:2] local_encoder2to3_0_data ; wire [0:2] local_encoder2to3_0_data_inv ; @@ -74386,23 +78806,23 @@ grid_clb_mux_1level_tapbuf_basis_input3_mem3_9 mux_l1_in_0_ ( .in ( { in[0] , in[1] , SYNOPSYS_UNCONNECTED_2 } ) , .mem ( local_encoder2to3_0_data ) , .mem_inv ( local_encoder2to3_0_data_inv ) , - .out ( mux_1level_tapbuf_basis_input3_mem3_0_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_160 ( + .out ( mux_1level_tapbuf_basis_input3_mem3_0_out ) , .p6 ( p6 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_159 ( .A ( mux_1level_tapbuf_basis_input3_mem3_0_out[0] ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_161 ( +sky130_fd_sc_hd__inv_1 BINV_R_160 ( .A ( mux_1level_tapbuf_basis_input3_mem3_0_out[0] ) , .Y ( p_abuf0 ) ) ; endmodule module grid_clb_mux_1level_tapbuf_basis_input3_mem3_8 ( in , mem , mem_inv , - out , p0 ) ; + out , p6 ) ; input [0:2] in ; input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; -input p0 ; +input p6 ; -scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , +scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p6 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out[0] ) ) ; @@ -74431,13 +78851,13 @@ endmodule module grid_clb_mux_1level_tapbuf_size2_8 ( in , sram , sram_inv , out , - p_abuf0 , p0 ) ; + p_abuf0 , p6 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; output [0:0] out ; output p_abuf0 ; -input p0 ; +input p6 ; wire [0:2] local_encoder2to3_0_data ; wire [0:2] local_encoder2to3_0_data_inv ; @@ -74452,10 +78872,10 @@ grid_clb_mux_1level_tapbuf_basis_input3_mem3_8 mux_l1_in_0_ ( .in ( { in[0] , in[1] , SYNOPSYS_UNCONNECTED_2 } ) , .mem ( local_encoder2to3_0_data ) , .mem_inv ( local_encoder2to3_0_data_inv ) , - .out ( mux_1level_tapbuf_basis_input3_mem3_0_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_157 ( + .out ( mux_1level_tapbuf_basis_input3_mem3_0_out ) , .p6 ( p6 ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_156 ( .A ( mux_1level_tapbuf_basis_input3_mem3_0_out[0] ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_158 ( +sky130_fd_sc_hd__inv_8 BINV_R_157 ( .A ( mux_1level_tapbuf_basis_input3_mem3_0_out[0] ) , .Y ( p_abuf0 ) ) ; endmodule @@ -74523,14 +78943,14 @@ endmodule module grid_clb_mux_1level_basis_input3_mem3_17 ( in , mem , mem_inv , out , - p0 ) ; + p6 ) ; input [0:2] in ; input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; -input p0 ; +input p6 ; -scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , +scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p6 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out[0] ) ) ; @@ -74558,12 +78978,12 @@ output [0:0] const1 ; endmodule -module grid_clb_mux_1level_size2_17 ( in , sram , sram_inv , out , p0 ) ; +module grid_clb_mux_1level_size2_17 ( in , sram , sram_inv , out , p6 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; output [0:0] out ; -input p0 ; +input p6 ; wire [0:2] local_encoder2to3_0_data ; wire [0:2] local_encoder2to3_0_data_inv ; @@ -74580,19 +79000,19 @@ grid_clb_mux_1level_basis_input3_mem3_17 mux_l1_in_0_ ( .in ( { in[0] , in[1] , SYNOPSYS_UNCONNECTED_2 } ) , .mem ( local_encoder2to3_0_data ) , .mem_inv ( local_encoder2to3_0_data_inv ) , - .out ( mux_1level_basis_input3_mem3_0_out ) , .p0 ( p0 ) ) ; + .out ( mux_1level_basis_input3_mem3_0_out ) , .p6 ( p6 ) ) ; endmodule module grid_clb_mux_1level_basis_input3_mem3_16 ( in , mem , mem_inv , out , - p0 ) ; + p6 ) ; input [0:2] in ; input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; -input p0 ; +input p6 ; -scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , +scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p6 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out[0] ) ) ; @@ -74620,12 +79040,12 @@ output [0:0] const1 ; endmodule -module grid_clb_mux_1level_size2_16 ( in , sram , sram_inv , out , p0 ) ; +module grid_clb_mux_1level_size2_16 ( in , sram , sram_inv , out , p6 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; output [0:0] out ; -input p0 ; +input p6 ; wire [0:2] local_encoder2to3_0_data ; wire [0:2] local_encoder2to3_0_data_inv ; @@ -74642,7 +79062,7 @@ grid_clb_mux_1level_basis_input3_mem3_16 mux_l1_in_0_ ( .in ( { in[0] , in[1] , SYNOPSYS_UNCONNECTED_2 } ) , .mem ( local_encoder2to3_0_data ) , .mem_inv ( local_encoder2to3_0_data_inv ) , - .out ( mux_1level_basis_input3_mem3_0_out ) , .p0 ( p0 ) ) ; + .out ( mux_1level_basis_input3_mem3_0_out ) , .p6 ( p6 ) ) ; endmodule @@ -74859,7 +79279,7 @@ endmodule module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_4 ( pReset , prog_clk , frac_logic_in , frac_logic_cin , ccff_head , - frac_logic_out , frac_logic_cout , ccff_tail , p0 ) ; + frac_logic_out , frac_logic_cout , ccff_tail , p6 ) ; input [0:0] pReset ; input [0:0] prog_clk ; input [0:3] frac_logic_in ; @@ -74868,7 +79288,7 @@ input [0:0] ccff_head ; output [0:1] frac_logic_out ; output [0:0] frac_logic_cout ; output [0:0] ccff_tail ; -input p0 ; +input p6 ; wire [0:0] direct_interc_5_out ; wire [0:0] direct_interc_7_out ; @@ -74904,12 +79324,12 @@ grid_clb_mux_1level_size2_16 mux_frac_logic_out_0 ( } ) , .sram ( mux_1level_size2_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_2 , SYNOPSYS_UNCONNECTED_3 } ) , - .out ( frac_logic_out[0] ) , .p0 ( p0 ) ) ; + .out ( frac_logic_out[0] ) , .p6 ( p6 ) ) ; grid_clb_mux_1level_size2_17 mux_frac_lut4_0_in_2 ( .in ( { frac_logic_cin[0] , frac_logic_in[2] } ) , .sram ( mux_1level_size2_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_4 , SYNOPSYS_UNCONNECTED_5 } ) , - .out ( mux_1level_size2_1_out ) , .p0 ( p0 ) ) ; + .out ( mux_1level_size2_1_out ) , .p6 ( p6 ) ) ; grid_clb_mux_1level_size2_mem_16 mem_frac_logic_out_0 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ) , @@ -74925,7 +79345,7 @@ module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_4 ( pReset , prog_clk , Test_en , fabric_in , fabric_reg_in , fabric_sc_in , fabric_cin , fabric_reset , fabric_clk , ccff_head , fabric_out , fabric_reg_out , fabric_sc_out , fabric_cout , ccff_tail , p_abuf0 , - p_abuf1 , p0 ) ; + p_abuf1 , p6 ) ; input [0:0] pReset ; input [0:0] prog_clk ; input [0:0] Test_en ; @@ -74943,7 +79363,7 @@ output [0:0] fabric_cout ; output [0:0] ccff_tail ; output p_abuf0 ; output p_abuf1 ; -input p0 ; +input p6 ; wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ; wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ; @@ -74968,7 +79388,7 @@ grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ .frac_logic_cout ( { SYNOPSYS_UNCONNECTED_1 } ) , .ccff_tail ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) , - .p0 ( p0 ) ) ; + .p6 ( p6 ) ) ; grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_8 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0 ( .Test_en ( Test_en ) , .ff_D ( mux_1level_size2_0_out ) , .ff_DI ( fabric_sc_in ) , .ff_reset ( fabric_reset ) , @@ -74986,14 +79406,14 @@ grid_clb_mux_1level_tapbuf_size2_8 mux_fabric_out_0 ( } ) , .sram ( mux_1level_tapbuf_size2_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_2 , SYNOPSYS_UNCONNECTED_3 } ) , - .out ( fabric_out[0] ) , .p_abuf0 ( p_abuf0 ) , .p0 ( p0 ) ) ; + .out ( fabric_out[0] ) , .p_abuf0 ( p_abuf0 ) , .p6 ( p6 ) ) ; grid_clb_mux_1level_tapbuf_size2_9 mux_fabric_out_1 ( .in ( { fabric_sc_out[0] , logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] } ) , .sram ( mux_1level_tapbuf_size2_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_4 , SYNOPSYS_UNCONNECTED_5 } ) , - .out ( fabric_out[1] ) , .p_abuf0 ( p_abuf1 ) , .p0 ( p0 ) ) ; + .out ( fabric_out[1] ) , .p_abuf0 ( p_abuf1 ) , .p6 ( p6 ) ) ; grid_clb_mux_1level_tapbuf_size2_mem_8 mem_fabric_out_0 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) , @@ -75012,7 +79432,7 @@ grid_clb_mux_1level_size2_18 mux_ff_0_D_0 ( fabric_reg_in[0] } ) , .sram ( mux_1level_size2_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_6 , SYNOPSYS_UNCONNECTED_7 } ) , - .out ( mux_1level_size2_0_out ) , .p0 ( p0 ) ) ; + .out ( mux_1level_size2_0_out ) , .p6 ( p6 ) ) ; grid_clb_mux_1level_size2_19 mux_ff_1_D_0 ( .in ( { logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] , @@ -75020,7 +79440,7 @@ grid_clb_mux_1level_size2_19 mux_ff_1_D_0 ( } ) , .sram ( mux_1level_size2_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_8 , SYNOPSYS_UNCONNECTED_9 } ) , - .out ( mux_1level_size2_1_out ) , .p0 ( p0 ) ) ; + .out ( mux_1level_size2_1_out ) , .p6 ( p6 ) ) ; grid_clb_mux_1level_size2_mem_18 mem_ff_0_D_0 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( mux_1level_tapbuf_size2_mem_1_ccff_tail ) , @@ -75035,7 +79455,7 @@ endmodule module grid_clb_logical_tile_clb_mode_default__fle_4 ( pReset , prog_clk , Test_en , fle_in , fle_reg_in , fle_sc_in , fle_cin , fle_reset , fle_clk , ccff_head , fle_out , fle_reg_out , fle_sc_out , fle_cout , - ccff_tail , p_abuf0 , p_abuf1 , p0 ) ; + ccff_tail , p_abuf0 , p_abuf1 , p6 ) ; input [0:0] pReset ; input [0:0] prog_clk ; input [0:0] Test_en ; @@ -75053,7 +79473,7 @@ output [0:0] fle_cout ; output [0:0] ccff_tail ; output p_abuf0 ; output p_abuf1 ; -input p0 ; +input p6 ; grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_4 logical_tile_clb_mode_default__fle_mode_physical__fabric_0 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , @@ -75065,7 +79485,7 @@ grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_4 logical_tile .fabric_reg_out ( fle_reg_out ) , .fabric_sc_out ( fle_sc_out ) , .fabric_cout ( { SYNOPSYS_UNCONNECTED_2 } ) , .ccff_tail ( ccff_tail ) , .p_abuf0 ( p_abuf0 ) , .p_abuf1 ( p_abuf1 ) , - .p0 ( p0 ) ) ; + .p6 ( p6 ) ) ; endmodule @@ -75102,14 +79522,14 @@ endmodule module grid_clb_mux_1level_basis_input3_mem3_15 ( in , mem , mem_inv , out , - p0 ) ; + p6 ) ; input [0:2] in ; input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; -input p0 ; +input p6 ; -scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , +scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p6 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out[0] ) ) ; @@ -75137,12 +79557,12 @@ output [0:0] const1 ; endmodule -module grid_clb_mux_1level_size2_15 ( in , sram , sram_inv , out , p0 ) ; +module grid_clb_mux_1level_size2_15 ( in , sram , sram_inv , out , p6 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; output [0:0] out ; -input p0 ; +input p6 ; wire [0:2] local_encoder2to3_0_data ; wire [0:2] local_encoder2to3_0_data_inv ; @@ -75159,19 +79579,19 @@ grid_clb_mux_1level_basis_input3_mem3_15 mux_l1_in_0_ ( .in ( { in[0] , in[1] , SYNOPSYS_UNCONNECTED_2 } ) , .mem ( local_encoder2to3_0_data ) , .mem_inv ( local_encoder2to3_0_data_inv ) , - .out ( mux_1level_basis_input3_mem3_0_out ) , .p0 ( p0 ) ) ; + .out ( mux_1level_basis_input3_mem3_0_out ) , .p6 ( p6 ) ) ; endmodule module grid_clb_mux_1level_basis_input3_mem3_14 ( in , mem , mem_inv , out , - p2 ) ; + p0 ) ; input [0:2] in ; input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; -input p2 ; +input p0 ; -scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p2 ) , +scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out[0] ) ) ; @@ -75199,12 +79619,12 @@ output [0:0] const1 ; endmodule -module grid_clb_mux_1level_size2_14 ( in , sram , sram_inv , out , p2 ) ; +module grid_clb_mux_1level_size2_14 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; output [0:0] out ; -input p2 ; +input p0 ; wire [0:2] local_encoder2to3_0_data ; wire [0:2] local_encoder2to3_0_data_inv ; @@ -75221,7 +79641,7 @@ grid_clb_mux_1level_basis_input3_mem3_14 mux_l1_in_0_ ( .in ( { in[0] , in[1] , SYNOPSYS_UNCONNECTED_2 } ) , .mem ( local_encoder2to3_0_data ) , .mem_inv ( local_encoder2to3_0_data_inv ) , - .out ( mux_1level_basis_input3_mem3_0_out ) , .p2 ( p2 ) ) ; + .out ( mux_1level_basis_input3_mem3_0_out ) , .p0 ( p0 ) ) ; endmodule @@ -75258,14 +79678,14 @@ endmodule module grid_clb_mux_1level_tapbuf_basis_input3_mem3_7 ( in , mem , mem_inv , - out , p0 ) ; + out , p6 ) ; input [0:2] in ; input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; -input p0 ; +input p6 ; -scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , +scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p6 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out[0] ) ) ; @@ -75294,13 +79714,13 @@ endmodule module grid_clb_mux_1level_tapbuf_size2_7 ( in , sram , sram_inv , out , - p_abuf0 , p0 ) ; + p_abuf0 , p6 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; output [0:0] out ; output p_abuf0 ; -input p0 ; +input p6 ; wire [0:2] local_encoder2to3_0_data ; wire [0:2] local_encoder2to3_0_data_inv ; @@ -75315,23 +79735,23 @@ grid_clb_mux_1level_tapbuf_basis_input3_mem3_7 mux_l1_in_0_ ( .in ( { in[0] , in[1] , SYNOPSYS_UNCONNECTED_2 } ) , .mem ( local_encoder2to3_0_data ) , .mem_inv ( local_encoder2to3_0_data_inv ) , - .out ( mux_1level_tapbuf_basis_input3_mem3_0_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_154 ( + .out ( mux_1level_tapbuf_basis_input3_mem3_0_out ) , .p6 ( p6 ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_153 ( .A ( mux_1level_tapbuf_basis_input3_mem3_0_out[0] ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_155 ( +sky130_fd_sc_hd__inv_8 BINV_R_154 ( .A ( mux_1level_tapbuf_basis_input3_mem3_0_out[0] ) , .Y ( p_abuf0 ) ) ; endmodule module grid_clb_mux_1level_tapbuf_basis_input3_mem3_6 ( in , mem , mem_inv , - out , p2 ) ; + out , p0 ) ; input [0:2] in ; input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; -input p2 ; +input p0 ; -scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p2 ) , +scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out[0] ) ) ; @@ -75360,13 +79780,13 @@ endmodule module grid_clb_mux_1level_tapbuf_size2_6 ( in , sram , sram_inv , out , - p_abuf0 , p2 ) ; + p_abuf0 , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; output [0:0] out ; output p_abuf0 ; -input p2 ; +input p0 ; wire [0:2] local_encoder2to3_0_data ; wire [0:2] local_encoder2to3_0_data_inv ; @@ -75381,10 +79801,10 @@ grid_clb_mux_1level_tapbuf_basis_input3_mem3_6 mux_l1_in_0_ ( .in ( { in[0] , in[1] , SYNOPSYS_UNCONNECTED_2 } ) , .mem ( local_encoder2to3_0_data ) , .mem_inv ( local_encoder2to3_0_data_inv ) , - .out ( mux_1level_tapbuf_basis_input3_mem3_0_out ) , .p2 ( p2 ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_151 ( + .out ( mux_1level_tapbuf_basis_input3_mem3_0_out ) , .p0 ( p0 ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_150 ( .A ( mux_1level_tapbuf_basis_input3_mem3_0_out[0] ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_152 ( +sky130_fd_sc_hd__inv_8 BINV_R_151 ( .A ( mux_1level_tapbuf_basis_input3_mem3_0_out[0] ) , .Y ( p_abuf0 ) ) ; endmodule @@ -75452,14 +79872,14 @@ endmodule module grid_clb_mux_1level_basis_input3_mem3_13 ( in , mem , mem_inv , out , - p2 ) ; + p0 ) ; input [0:2] in ; input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; -input p2 ; +input p0 ; -scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p2 ) , +scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out[0] ) ) ; @@ -75487,12 +79907,12 @@ output [0:0] const1 ; endmodule -module grid_clb_mux_1level_size2_13 ( in , sram , sram_inv , out , p2 ) ; +module grid_clb_mux_1level_size2_13 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; output [0:0] out ; -input p2 ; +input p0 ; wire [0:2] local_encoder2to3_0_data ; wire [0:2] local_encoder2to3_0_data_inv ; @@ -75509,19 +79929,19 @@ grid_clb_mux_1level_basis_input3_mem3_13 mux_l1_in_0_ ( .in ( { in[0] , in[1] , SYNOPSYS_UNCONNECTED_2 } ) , .mem ( local_encoder2to3_0_data ) , .mem_inv ( local_encoder2to3_0_data_inv ) , - .out ( mux_1level_basis_input3_mem3_0_out ) , .p2 ( p2 ) ) ; + .out ( mux_1level_basis_input3_mem3_0_out ) , .p0 ( p0 ) ) ; endmodule module grid_clb_mux_1level_basis_input3_mem3_12 ( in , mem , mem_inv , out , - p2 ) ; + p0 ) ; input [0:2] in ; input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; -input p2 ; +input p0 ; -scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p2 ) , +scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out[0] ) ) ; @@ -75549,12 +79969,12 @@ output [0:0] const1 ; endmodule -module grid_clb_mux_1level_size2_12 ( in , sram , sram_inv , out , p2 ) ; +module grid_clb_mux_1level_size2_12 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; output [0:0] out ; -input p2 ; +input p0 ; wire [0:2] local_encoder2to3_0_data ; wire [0:2] local_encoder2to3_0_data_inv ; @@ -75571,7 +79991,7 @@ grid_clb_mux_1level_basis_input3_mem3_12 mux_l1_in_0_ ( .in ( { in[0] , in[1] , SYNOPSYS_UNCONNECTED_2 } ) , .mem ( local_encoder2to3_0_data ) , .mem_inv ( local_encoder2to3_0_data_inv ) , - .out ( mux_1level_basis_input3_mem3_0_out ) , .p2 ( p2 ) ) ; + .out ( mux_1level_basis_input3_mem3_0_out ) , .p0 ( p0 ) ) ; endmodule @@ -75788,7 +80208,7 @@ endmodule module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_3 ( pReset , prog_clk , frac_logic_in , frac_logic_cin , ccff_head , - frac_logic_out , frac_logic_cout , ccff_tail , p2 ) ; + frac_logic_out , frac_logic_cout , ccff_tail , p0 ) ; input [0:0] pReset ; input [0:0] prog_clk ; input [0:3] frac_logic_in ; @@ -75797,7 +80217,7 @@ input [0:0] ccff_head ; output [0:1] frac_logic_out ; output [0:0] frac_logic_cout ; output [0:0] ccff_tail ; -input p2 ; +input p0 ; wire [0:0] direct_interc_5_out ; wire [0:0] direct_interc_7_out ; @@ -75833,12 +80253,12 @@ grid_clb_mux_1level_size2_12 mux_frac_logic_out_0 ( } ) , .sram ( mux_1level_size2_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_2 , SYNOPSYS_UNCONNECTED_3 } ) , - .out ( frac_logic_out[0] ) , .p2 ( p2 ) ) ; + .out ( frac_logic_out[0] ) , .p0 ( p0 ) ) ; grid_clb_mux_1level_size2_13 mux_frac_lut4_0_in_2 ( .in ( { frac_logic_cin[0] , frac_logic_in[2] } ) , .sram ( mux_1level_size2_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_4 , SYNOPSYS_UNCONNECTED_5 } ) , - .out ( mux_1level_size2_1_out ) , .p2 ( p2 ) ) ; + .out ( mux_1level_size2_1_out ) , .p0 ( p0 ) ) ; grid_clb_mux_1level_size2_mem_12 mem_frac_logic_out_0 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ) , @@ -75854,7 +80274,7 @@ module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_3 ( pReset , prog_clk , Test_en , fabric_in , fabric_reg_in , fabric_sc_in , fabric_cin , fabric_reset , fabric_clk , ccff_head , fabric_out , fabric_reg_out , fabric_sc_out , fabric_cout , ccff_tail , p_abuf0 , - p_abuf1 , p0 , p2 ) ; + p_abuf1 , p0 , p6 ) ; input [0:0] pReset ; input [0:0] prog_clk ; input [0:0] Test_en ; @@ -75873,7 +80293,7 @@ output [0:0] ccff_tail ; output p_abuf0 ; output p_abuf1 ; input p0 ; -input p2 ; +input p6 ; wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ; wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ; @@ -75898,7 +80318,7 @@ grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ .frac_logic_cout ( { SYNOPSYS_UNCONNECTED_1 } ) , .ccff_tail ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) , - .p2 ( p2 ) ) ; + .p0 ( p0 ) ) ; grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_6 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0 ( .Test_en ( Test_en ) , .ff_D ( mux_1level_size2_0_out ) , .ff_DI ( fabric_sc_in ) , .ff_reset ( fabric_reset ) , @@ -75916,14 +80336,14 @@ grid_clb_mux_1level_tapbuf_size2_6 mux_fabric_out_0 ( } ) , .sram ( mux_1level_tapbuf_size2_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_2 , SYNOPSYS_UNCONNECTED_3 } ) , - .out ( fabric_out[0] ) , .p_abuf0 ( p_abuf0 ) , .p2 ( p2 ) ) ; + .out ( fabric_out[0] ) , .p_abuf0 ( p_abuf0 ) , .p0 ( p0 ) ) ; grid_clb_mux_1level_tapbuf_size2_7 mux_fabric_out_1 ( .in ( { fabric_sc_out[0] , logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] } ) , .sram ( mux_1level_tapbuf_size2_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_4 , SYNOPSYS_UNCONNECTED_5 } ) , - .out ( fabric_out[1] ) , .p_abuf0 ( p_abuf1 ) , .p0 ( p0 ) ) ; + .out ( fabric_out[1] ) , .p_abuf0 ( p_abuf1 ) , .p6 ( p6 ) ) ; grid_clb_mux_1level_tapbuf_size2_mem_6 mem_fabric_out_0 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) , @@ -75942,7 +80362,7 @@ grid_clb_mux_1level_size2_14 mux_ff_0_D_0 ( fabric_reg_in[0] } ) , .sram ( mux_1level_size2_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_6 , SYNOPSYS_UNCONNECTED_7 } ) , - .out ( mux_1level_size2_0_out ) , .p2 ( p2 ) ) ; + .out ( mux_1level_size2_0_out ) , .p0 ( p0 ) ) ; grid_clb_mux_1level_size2_15 mux_ff_1_D_0 ( .in ( { logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] , @@ -75950,7 +80370,7 @@ grid_clb_mux_1level_size2_15 mux_ff_1_D_0 ( } ) , .sram ( mux_1level_size2_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_8 , SYNOPSYS_UNCONNECTED_9 } ) , - .out ( mux_1level_size2_1_out ) , .p0 ( p0 ) ) ; + .out ( mux_1level_size2_1_out ) , .p6 ( p6 ) ) ; grid_clb_mux_1level_size2_mem_14 mem_ff_0_D_0 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( mux_1level_tapbuf_size2_mem_1_ccff_tail ) , @@ -75965,7 +80385,7 @@ endmodule module grid_clb_logical_tile_clb_mode_default__fle_3 ( pReset , prog_clk , Test_en , fle_in , fle_reg_in , fle_sc_in , fle_cin , fle_reset , fle_clk , ccff_head , fle_out , fle_reg_out , fle_sc_out , fle_cout , - ccff_tail , p_abuf0 , p_abuf1 , p0 , p2 ) ; + ccff_tail , p_abuf0 , p_abuf1 , p0 , p6 ) ; input [0:0] pReset ; input [0:0] prog_clk ; input [0:0] Test_en ; @@ -75984,7 +80404,7 @@ output [0:0] ccff_tail ; output p_abuf0 ; output p_abuf1 ; input p0 ; -input p2 ; +input p6 ; grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_3 logical_tile_clb_mode_default__fle_mode_physical__fabric_0 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , @@ -75996,7 +80416,7 @@ grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_3 logical_tile .fabric_reg_out ( fle_reg_out ) , .fabric_sc_out ( fle_sc_out ) , .fabric_cout ( { SYNOPSYS_UNCONNECTED_2 } ) , .ccff_tail ( ccff_tail ) , .p_abuf0 ( p_abuf0 ) , .p_abuf1 ( p_abuf1 ) , - .p0 ( p0 ) , .p2 ( p2 ) ) ; + .p0 ( p0 ) , .p6 ( p6 ) ) ; endmodule @@ -76033,14 +80453,14 @@ endmodule module grid_clb_mux_1level_basis_input3_mem3_11 ( in , mem , mem_inv , out , - p2 ) ; + p4 ) ; input [0:2] in ; input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; -input p2 ; +input p4 ; -scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p2 ) , +scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p4 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out[0] ) ) ; @@ -76068,12 +80488,12 @@ output [0:0] const1 ; endmodule -module grid_clb_mux_1level_size2_11 ( in , sram , sram_inv , out , p2 ) ; +module grid_clb_mux_1level_size2_11 ( in , sram , sram_inv , out , p4 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; output [0:0] out ; -input p2 ; +input p4 ; wire [0:2] local_encoder2to3_0_data ; wire [0:2] local_encoder2to3_0_data_inv ; @@ -76090,19 +80510,19 @@ grid_clb_mux_1level_basis_input3_mem3_11 mux_l1_in_0_ ( .in ( { in[0] , in[1] , SYNOPSYS_UNCONNECTED_2 } ) , .mem ( local_encoder2to3_0_data ) , .mem_inv ( local_encoder2to3_0_data_inv ) , - .out ( mux_1level_basis_input3_mem3_0_out ) , .p2 ( p2 ) ) ; + .out ( mux_1level_basis_input3_mem3_0_out ) , .p4 ( p4 ) ) ; endmodule module grid_clb_mux_1level_basis_input3_mem3_10 ( in , mem , mem_inv , out , - p1 ) ; + p4 ) ; input [0:2] in ; input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; -input p1 ; +input p4 ; -scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p1 ) , +scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p4 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out[0] ) ) ; @@ -76130,12 +80550,12 @@ output [0:0] const1 ; endmodule -module grid_clb_mux_1level_size2_10 ( in , sram , sram_inv , out , p1 ) ; +module grid_clb_mux_1level_size2_10 ( in , sram , sram_inv , out , p4 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; output [0:0] out ; -input p1 ; +input p4 ; wire [0:2] local_encoder2to3_0_data ; wire [0:2] local_encoder2to3_0_data_inv ; @@ -76152,7 +80572,7 @@ grid_clb_mux_1level_basis_input3_mem3_10 mux_l1_in_0_ ( .in ( { in[0] , in[1] , SYNOPSYS_UNCONNECTED_2 } ) , .mem ( local_encoder2to3_0_data ) , .mem_inv ( local_encoder2to3_0_data_inv ) , - .out ( mux_1level_basis_input3_mem3_0_out ) , .p1 ( p1 ) ) ; + .out ( mux_1level_basis_input3_mem3_0_out ) , .p4 ( p4 ) ) ; endmodule @@ -76189,14 +80609,14 @@ endmodule module grid_clb_mux_1level_tapbuf_basis_input3_mem3_5 ( in , mem , mem_inv , - out , p2 ) ; + out , p4 ) ; input [0:2] in ; input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; -input p2 ; +input p4 ; -scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p2 ) , +scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p4 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out[0] ) ) ; @@ -76225,13 +80645,13 @@ endmodule module grid_clb_mux_1level_tapbuf_size2_5 ( in , sram , sram_inv , out , - p_abuf0 , p2 ) ; + p_abuf0 , p4 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; output [0:0] out ; output p_abuf0 ; -input p2 ; +input p4 ; wire [0:2] local_encoder2to3_0_data ; wire [0:2] local_encoder2to3_0_data_inv ; @@ -76246,23 +80666,23 @@ grid_clb_mux_1level_tapbuf_basis_input3_mem3_5 mux_l1_in_0_ ( .in ( { in[0] , in[1] , SYNOPSYS_UNCONNECTED_2 } ) , .mem ( local_encoder2to3_0_data ) , .mem_inv ( local_encoder2to3_0_data_inv ) , - .out ( mux_1level_tapbuf_basis_input3_mem3_0_out ) , .p2 ( p2 ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_148 ( + .out ( mux_1level_tapbuf_basis_input3_mem3_0_out ) , .p4 ( p4 ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_147 ( .A ( mux_1level_tapbuf_basis_input3_mem3_0_out[0] ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_149 ( +sky130_fd_sc_hd__inv_8 BINV_R_148 ( .A ( mux_1level_tapbuf_basis_input3_mem3_0_out[0] ) , .Y ( p_abuf0 ) ) ; endmodule module grid_clb_mux_1level_tapbuf_basis_input3_mem3_4 ( in , mem , mem_inv , - out , p1 ) ; + out , p4 ) ; input [0:2] in ; input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; -input p1 ; +input p4 ; -scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p1 ) , +scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p4 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out[0] ) ) ; @@ -76291,13 +80711,13 @@ endmodule module grid_clb_mux_1level_tapbuf_size2_4 ( in , sram , sram_inv , out , - p_abuf0 , p1 ) ; + p_abuf0 , p4 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; output [0:0] out ; output p_abuf0 ; -input p1 ; +input p4 ; wire [0:2] local_encoder2to3_0_data ; wire [0:2] local_encoder2to3_0_data_inv ; @@ -76312,10 +80732,10 @@ grid_clb_mux_1level_tapbuf_basis_input3_mem3_4 mux_l1_in_0_ ( .in ( { in[0] , in[1] , SYNOPSYS_UNCONNECTED_2 } ) , .mem ( local_encoder2to3_0_data ) , .mem_inv ( local_encoder2to3_0_data_inv ) , - .out ( mux_1level_tapbuf_basis_input3_mem3_0_out ) , .p1 ( p1 ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_145 ( + .out ( mux_1level_tapbuf_basis_input3_mem3_0_out ) , .p4 ( p4 ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_144 ( .A ( mux_1level_tapbuf_basis_input3_mem3_0_out[0] ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_146 ( +sky130_fd_sc_hd__inv_8 BINV_R_145 ( .A ( mux_1level_tapbuf_basis_input3_mem3_0_out[0] ) , .Y ( p_abuf0 ) ) ; endmodule @@ -76383,14 +80803,14 @@ endmodule module grid_clb_mux_1level_basis_input3_mem3_9 ( in , mem , mem_inv , out , - p1 ) ; + p2 ) ; input [0:2] in ; input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; -input p1 ; +input p2 ; -scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p1 ) , +scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p2 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out[0] ) ) ; @@ -76418,12 +80838,12 @@ output [0:0] const1 ; endmodule -module grid_clb_mux_1level_size2_9 ( in , sram , sram_inv , out , p1 ) ; +module grid_clb_mux_1level_size2_9 ( in , sram , sram_inv , out , p2 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; output [0:0] out ; -input p1 ; +input p2 ; wire [0:2] local_encoder2to3_0_data ; wire [0:2] local_encoder2to3_0_data_inv ; @@ -76440,7 +80860,7 @@ grid_clb_mux_1level_basis_input3_mem3_9 mux_l1_in_0_ ( .in ( { in[0] , in[1] , SYNOPSYS_UNCONNECTED_2 } ) , .mem ( local_encoder2to3_0_data ) , .mem_inv ( local_encoder2to3_0_data_inv ) , - .out ( mux_1level_basis_input3_mem3_0_out ) , .p1 ( p1 ) ) ; + .out ( mux_1level_basis_input3_mem3_0_out ) , .p2 ( p2 ) ) ; endmodule @@ -76719,7 +81139,7 @@ endmodule module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_2 ( pReset , prog_clk , frac_logic_in , frac_logic_cin , ccff_head , - frac_logic_out , frac_logic_cout , ccff_tail , p1 , p2 ) ; + frac_logic_out , frac_logic_cout , ccff_tail , p2 ) ; input [0:0] pReset ; input [0:0] prog_clk ; input [0:3] frac_logic_in ; @@ -76728,7 +81148,6 @@ input [0:0] ccff_head ; output [0:1] frac_logic_out ; output [0:0] frac_logic_cout ; output [0:0] ccff_tail ; -input p1 ; input p2 ; wire [0:0] direct_interc_5_out ; @@ -76770,7 +81189,7 @@ grid_clb_mux_1level_size2_9 mux_frac_lut4_0_in_2 ( .in ( { frac_logic_cin[0] , frac_logic_in[2] } ) , .sram ( mux_1level_size2_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_4 , SYNOPSYS_UNCONNECTED_5 } ) , - .out ( mux_1level_size2_1_out ) , .p1 ( p1 ) ) ; + .out ( mux_1level_size2_1_out ) , .p2 ( p2 ) ) ; grid_clb_mux_1level_size2_mem_8 mem_frac_logic_out_0 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ) , @@ -76786,7 +81205,7 @@ module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_2 ( pReset , prog_clk , Test_en , fabric_in , fabric_reg_in , fabric_sc_in , fabric_cin , fabric_reset , fabric_clk , ccff_head , fabric_out , fabric_reg_out , fabric_sc_out , fabric_cout , ccff_tail , p_abuf0 , - p_abuf1 , p1 , p2 ) ; + p_abuf1 , p2 , p4 ) ; input [0:0] pReset ; input [0:0] prog_clk ; input [0:0] Test_en ; @@ -76804,8 +81223,8 @@ output [0:0] fabric_cout ; output [0:0] ccff_tail ; output p_abuf0 ; output p_abuf1 ; -input p1 ; input p2 ; +input p4 ; wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ; wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ; @@ -76830,7 +81249,7 @@ grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ .frac_logic_cout ( { SYNOPSYS_UNCONNECTED_1 } ) , .ccff_tail ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) , - .p1 ( p1 ) , .p2 ( p2 ) ) ; + .p2 ( p2 ) ) ; grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_4 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0 ( .Test_en ( Test_en ) , .ff_D ( mux_1level_size2_0_out ) , .ff_DI ( fabric_sc_in ) , .ff_reset ( fabric_reset ) , @@ -76848,14 +81267,14 @@ grid_clb_mux_1level_tapbuf_size2_4 mux_fabric_out_0 ( } ) , .sram ( mux_1level_tapbuf_size2_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_2 , SYNOPSYS_UNCONNECTED_3 } ) , - .out ( fabric_out[0] ) , .p_abuf0 ( p_abuf0 ) , .p1 ( p1 ) ) ; + .out ( fabric_out[0] ) , .p_abuf0 ( p_abuf0 ) , .p4 ( p4 ) ) ; grid_clb_mux_1level_tapbuf_size2_5 mux_fabric_out_1 ( .in ( { fabric_sc_out[0] , logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] } ) , .sram ( mux_1level_tapbuf_size2_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_4 , SYNOPSYS_UNCONNECTED_5 } ) , - .out ( fabric_out[1] ) , .p_abuf0 ( p_abuf1 ) , .p2 ( p2 ) ) ; + .out ( fabric_out[1] ) , .p_abuf0 ( p_abuf1 ) , .p4 ( p4 ) ) ; grid_clb_mux_1level_tapbuf_size2_mem_4 mem_fabric_out_0 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) , @@ -76874,7 +81293,7 @@ grid_clb_mux_1level_size2_10 mux_ff_0_D_0 ( fabric_reg_in[0] } ) , .sram ( mux_1level_size2_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_6 , SYNOPSYS_UNCONNECTED_7 } ) , - .out ( mux_1level_size2_0_out ) , .p1 ( p1 ) ) ; + .out ( mux_1level_size2_0_out ) , .p4 ( p4 ) ) ; grid_clb_mux_1level_size2_11 mux_ff_1_D_0 ( .in ( { logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] , @@ -76882,7 +81301,7 @@ grid_clb_mux_1level_size2_11 mux_ff_1_D_0 ( } ) , .sram ( mux_1level_size2_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_8 , SYNOPSYS_UNCONNECTED_9 } ) , - .out ( mux_1level_size2_1_out ) , .p2 ( p2 ) ) ; + .out ( mux_1level_size2_1_out ) , .p4 ( p4 ) ) ; grid_clb_mux_1level_size2_mem_10 mem_ff_0_D_0 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( mux_1level_tapbuf_size2_mem_1_ccff_tail ) , @@ -76897,7 +81316,7 @@ endmodule module grid_clb_logical_tile_clb_mode_default__fle_2 ( pReset , prog_clk , Test_en , fle_in , fle_reg_in , fle_sc_in , fle_cin , fle_reset , fle_clk , ccff_head , fle_out , fle_reg_out , fle_sc_out , fle_cout , - ccff_tail , p_abuf0 , p_abuf1 , p1 , p2 ) ; + ccff_tail , p_abuf0 , p_abuf1 , p2 , p4 ) ; input [0:0] pReset ; input [0:0] prog_clk ; input [0:0] Test_en ; @@ -76915,8 +81334,8 @@ output [0:0] fle_cout ; output [0:0] ccff_tail ; output p_abuf0 ; output p_abuf1 ; -input p1 ; input p2 ; +input p4 ; grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_2 logical_tile_clb_mode_default__fle_mode_physical__fabric_0 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , @@ -76928,7 +81347,7 @@ grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_2 logical_tile .fabric_reg_out ( fle_reg_out ) , .fabric_sc_out ( fle_sc_out ) , .fabric_cout ( { SYNOPSYS_UNCONNECTED_2 } ) , .ccff_tail ( ccff_tail ) , .p_abuf0 ( p_abuf0 ) , .p_abuf1 ( p_abuf1 ) , - .p1 ( p1 ) , .p2 ( p2 ) ) ; + .p2 ( p2 ) , .p4 ( p4 ) ) ; endmodule @@ -76965,14 +81384,14 @@ endmodule module grid_clb_mux_1level_basis_input3_mem3_7 ( in , mem , mem_inv , out , - p0 ) ; + p5 ) ; input [0:2] in ; input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; -input p0 ; +input p5 ; -scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , +scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p5 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out[0] ) ) ; @@ -77000,12 +81419,12 @@ output [0:0] const1 ; endmodule -module grid_clb_mux_1level_size2_7 ( in , sram , sram_inv , out , p0 ) ; +module grid_clb_mux_1level_size2_7 ( in , sram , sram_inv , out , p5 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; output [0:0] out ; -input p0 ; +input p5 ; wire [0:2] local_encoder2to3_0_data ; wire [0:2] local_encoder2to3_0_data_inv ; @@ -77022,19 +81441,19 @@ grid_clb_mux_1level_basis_input3_mem3_7 mux_l1_in_0_ ( .in ( { in[0] , in[1] , SYNOPSYS_UNCONNECTED_2 } ) , .mem ( local_encoder2to3_0_data ) , .mem_inv ( local_encoder2to3_0_data_inv ) , - .out ( mux_1level_basis_input3_mem3_0_out ) , .p0 ( p0 ) ) ; + .out ( mux_1level_basis_input3_mem3_0_out ) , .p5 ( p5 ) ) ; endmodule module grid_clb_mux_1level_basis_input3_mem3_6 ( in , mem , mem_inv , out , - p0 ) ; + p5 ) ; input [0:2] in ; input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; -input p0 ; +input p5 ; -scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , +scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p5 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out[0] ) ) ; @@ -77062,12 +81481,12 @@ output [0:0] const1 ; endmodule -module grid_clb_mux_1level_size2_6 ( in , sram , sram_inv , out , p0 ) ; +module grid_clb_mux_1level_size2_6 ( in , sram , sram_inv , out , p5 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; output [0:0] out ; -input p0 ; +input p5 ; wire [0:2] local_encoder2to3_0_data ; wire [0:2] local_encoder2to3_0_data_inv ; @@ -77084,7 +81503,7 @@ grid_clb_mux_1level_basis_input3_mem3_6 mux_l1_in_0_ ( .in ( { in[0] , in[1] , SYNOPSYS_UNCONNECTED_2 } ) , .mem ( local_encoder2to3_0_data ) , .mem_inv ( local_encoder2to3_0_data_inv ) , - .out ( mux_1level_basis_input3_mem3_0_out ) , .p0 ( p0 ) ) ; + .out ( mux_1level_basis_input3_mem3_0_out ) , .p5 ( p5 ) ) ; endmodule @@ -77121,14 +81540,14 @@ endmodule module grid_clb_mux_1level_tapbuf_basis_input3_mem3_3 ( in , mem , mem_inv , - out , p0 ) ; + out , p5 ) ; input [0:2] in ; input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; -input p0 ; +input p5 ; -scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , +scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p5 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out[0] ) ) ; @@ -77157,13 +81576,13 @@ endmodule module grid_clb_mux_1level_tapbuf_size2_3 ( in , sram , sram_inv , out , - p_abuf0 , p0 ) ; + p_abuf0 , p5 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; output [0:0] out ; output p_abuf0 ; -input p0 ; +input p5 ; wire [0:2] local_encoder2to3_0_data ; wire [0:2] local_encoder2to3_0_data_inv ; @@ -77178,10 +81597,10 @@ grid_clb_mux_1level_tapbuf_basis_input3_mem3_3 mux_l1_in_0_ ( .in ( { in[0] , in[1] , SYNOPSYS_UNCONNECTED_2 } ) , .mem ( local_encoder2to3_0_data ) , .mem_inv ( local_encoder2to3_0_data_inv ) , - .out ( mux_1level_tapbuf_basis_input3_mem3_0_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_142 ( + .out ( mux_1level_tapbuf_basis_input3_mem3_0_out ) , .p5 ( p5 ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_141 ( .A ( mux_1level_tapbuf_basis_input3_mem3_0_out[0] ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_143 ( +sky130_fd_sc_hd__inv_8 BINV_R_142 ( .A ( mux_1level_tapbuf_basis_input3_mem3_0_out[0] ) , .Y ( p_abuf0 ) ) ; endmodule @@ -77245,9 +81664,9 @@ grid_clb_mux_1level_tapbuf_basis_input3_mem3_2 mux_l1_in_0_ ( .mem ( local_encoder2to3_0_data ) , .mem_inv ( local_encoder2to3_0_data_inv ) , .out ( mux_1level_tapbuf_basis_input3_mem3_0_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_139 ( +sky130_fd_sc_hd__inv_1 BINV_R_138 ( .A ( mux_1level_tapbuf_basis_input3_mem3_0_out[0] ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_140 ( +sky130_fd_sc_hd__inv_8 BINV_R_139 ( .A ( mux_1level_tapbuf_basis_input3_mem3_0_out[0] ) , .Y ( p_abuf0 ) ) ; endmodule @@ -77315,14 +81734,14 @@ endmodule module grid_clb_mux_1level_basis_input3_mem3_5 ( in , mem , mem_inv , out , - p5 ) ; + p1 ) ; input [0:2] in ; input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; -input p5 ; +input p1 ; -scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p5 ) , +scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p1 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out[0] ) ) ; @@ -77350,12 +81769,12 @@ output [0:0] const1 ; endmodule -module grid_clb_mux_1level_size2_5 ( in , sram , sram_inv , out , p5 ) ; +module grid_clb_mux_1level_size2_5 ( in , sram , sram_inv , out , p1 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; output [0:0] out ; -input p5 ; +input p1 ; wire [0:2] local_encoder2to3_0_data ; wire [0:2] local_encoder2to3_0_data_inv ; @@ -77372,19 +81791,19 @@ grid_clb_mux_1level_basis_input3_mem3_5 mux_l1_in_0_ ( .in ( { in[0] , in[1] , SYNOPSYS_UNCONNECTED_2 } ) , .mem ( local_encoder2to3_0_data ) , .mem_inv ( local_encoder2to3_0_data_inv ) , - .out ( mux_1level_basis_input3_mem3_0_out ) , .p5 ( p5 ) ) ; + .out ( mux_1level_basis_input3_mem3_0_out ) , .p1 ( p1 ) ) ; endmodule module grid_clb_mux_1level_basis_input3_mem3_4 ( in , mem , mem_inv , out , - p5 ) ; + p0 ) ; input [0:2] in ; input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; -input p5 ; +input p0 ; -scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p5 ) , +scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out[0] ) ) ; @@ -77412,12 +81831,12 @@ output [0:0] const1 ; endmodule -module grid_clb_mux_1level_size2_4 ( in , sram , sram_inv , out , p5 ) ; +module grid_clb_mux_1level_size2_4 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; output [0:0] out ; -input p5 ; +input p0 ; wire [0:2] local_encoder2to3_0_data ; wire [0:2] local_encoder2to3_0_data_inv ; @@ -77434,7 +81853,7 @@ grid_clb_mux_1level_basis_input3_mem3_4 mux_l1_in_0_ ( .in ( { in[0] , in[1] , SYNOPSYS_UNCONNECTED_2 } ) , .mem ( local_encoder2to3_0_data ) , .mem_inv ( local_encoder2to3_0_data_inv ) , - .out ( mux_1level_basis_input3_mem3_0_out ) , .p5 ( p5 ) ) ; + .out ( mux_1level_basis_input3_mem3_0_out ) , .p0 ( p0 ) ) ; endmodule @@ -77651,7 +82070,7 @@ endmodule module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_1 ( pReset , prog_clk , frac_logic_in , frac_logic_cin , ccff_head , - frac_logic_out , frac_logic_cout , ccff_tail , p5 ) ; + frac_logic_out , frac_logic_cout , ccff_tail , p0 , p1 ) ; input [0:0] pReset ; input [0:0] prog_clk ; input [0:3] frac_logic_in ; @@ -77660,7 +82079,8 @@ input [0:0] ccff_head ; output [0:1] frac_logic_out ; output [0:0] frac_logic_cout ; output [0:0] ccff_tail ; -input p5 ; +input p0 ; +input p1 ; wire [0:0] direct_interc_5_out ; wire [0:0] direct_interc_7_out ; @@ -77696,12 +82116,12 @@ grid_clb_mux_1level_size2_4 mux_frac_logic_out_0 ( } ) , .sram ( mux_1level_size2_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_2 , SYNOPSYS_UNCONNECTED_3 } ) , - .out ( frac_logic_out[0] ) , .p5 ( p5 ) ) ; + .out ( frac_logic_out[0] ) , .p0 ( p0 ) ) ; grid_clb_mux_1level_size2_5 mux_frac_lut4_0_in_2 ( .in ( { frac_logic_cin[0] , frac_logic_in[2] } ) , .sram ( mux_1level_size2_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_4 , SYNOPSYS_UNCONNECTED_5 } ) , - .out ( mux_1level_size2_1_out ) , .p5 ( p5 ) ) ; + .out ( mux_1level_size2_1_out ) , .p1 ( p1 ) ) ; grid_clb_mux_1level_size2_mem_4 mem_frac_logic_out_0 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ) , @@ -77717,7 +82137,7 @@ module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_1 ( pReset , prog_clk , Test_en , fabric_in , fabric_reg_in , fabric_sc_in , fabric_cin , fabric_reset , fabric_clk , ccff_head , fabric_out , fabric_reg_out , fabric_sc_out , fabric_cout , ccff_tail , p_abuf0 , - p_abuf1 , p0 , p5 ) ; + p_abuf1 , p0 , p1 , p5 ) ; input [0:0] pReset ; input [0:0] prog_clk ; input [0:0] Test_en ; @@ -77736,6 +82156,7 @@ output [0:0] ccff_tail ; output p_abuf0 ; output p_abuf1 ; input p0 ; +input p1 ; input p5 ; wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ; @@ -77761,7 +82182,7 @@ grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ .frac_logic_cout ( { SYNOPSYS_UNCONNECTED_1 } ) , .ccff_tail ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) , - .p5 ( p5 ) ) ; + .p0 ( p0 ) , .p1 ( p1 ) ) ; grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_2 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0 ( .Test_en ( Test_en ) , .ff_D ( mux_1level_size2_0_out ) , .ff_DI ( fabric_sc_in ) , .ff_reset ( fabric_reset ) , @@ -77786,7 +82207,7 @@ grid_clb_mux_1level_tapbuf_size2_3 mux_fabric_out_1 ( } ) , .sram ( mux_1level_tapbuf_size2_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_4 , SYNOPSYS_UNCONNECTED_5 } ) , - .out ( fabric_out[1] ) , .p_abuf0 ( p_abuf1 ) , .p0 ( p0 ) ) ; + .out ( fabric_out[1] ) , .p_abuf0 ( p_abuf1 ) , .p5 ( p5 ) ) ; grid_clb_mux_1level_tapbuf_size2_mem_2 mem_fabric_out_0 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) , @@ -77805,7 +82226,7 @@ grid_clb_mux_1level_size2_6 mux_ff_0_D_0 ( fabric_reg_in[0] } ) , .sram ( mux_1level_size2_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_6 , SYNOPSYS_UNCONNECTED_7 } ) , - .out ( mux_1level_size2_0_out ) , .p0 ( p0 ) ) ; + .out ( mux_1level_size2_0_out ) , .p5 ( p5 ) ) ; grid_clb_mux_1level_size2_7 mux_ff_1_D_0 ( .in ( { logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] , @@ -77813,7 +82234,7 @@ grid_clb_mux_1level_size2_7 mux_ff_1_D_0 ( } ) , .sram ( mux_1level_size2_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_8 , SYNOPSYS_UNCONNECTED_9 } ) , - .out ( mux_1level_size2_1_out ) , .p0 ( p0 ) ) ; + .out ( mux_1level_size2_1_out ) , .p5 ( p5 ) ) ; grid_clb_mux_1level_size2_mem_6 mem_ff_0_D_0 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( mux_1level_tapbuf_size2_mem_1_ccff_tail ) , @@ -77828,7 +82249,7 @@ endmodule module grid_clb_logical_tile_clb_mode_default__fle_1 ( pReset , prog_clk , Test_en , fle_in , fle_reg_in , fle_sc_in , fle_cin , fle_reset , fle_clk , ccff_head , fle_out , fle_reg_out , fle_sc_out , fle_cout , - ccff_tail , p_abuf0 , p_abuf1 , p0 , p5 ) ; + ccff_tail , p_abuf0 , p_abuf1 , p0 , p1 , p5 ) ; input [0:0] pReset ; input [0:0] prog_clk ; input [0:0] Test_en ; @@ -77847,6 +82268,7 @@ output [0:0] ccff_tail ; output p_abuf0 ; output p_abuf1 ; input p0 ; +input p1 ; input p5 ; grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_1 logical_tile_clb_mode_default__fle_mode_physical__fabric_0 ( @@ -77859,7 +82281,7 @@ grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_1 logical_tile .fabric_reg_out ( fle_reg_out ) , .fabric_sc_out ( fle_sc_out ) , .fabric_cout ( { SYNOPSYS_UNCONNECTED_2 } ) , .ccff_tail ( ccff_tail ) , .p_abuf0 ( p_abuf0 ) , .p_abuf1 ( p_abuf1 ) , - .p0 ( p0 ) , .p5 ( p5 ) ) ; + .p0 ( p0 ) , .p1 ( p1 ) , .p5 ( p5 ) ) ; endmodule @@ -77896,14 +82318,14 @@ endmodule module grid_clb_mux_1level_basis_input3_mem3_3 ( in , mem , mem_inv , out , - p1 ) ; + p5 ) ; input [0:2] in ; input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; -input p1 ; +input p5 ; -scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p1 ) , +scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p5 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out[0] ) ) ; @@ -77931,12 +82353,12 @@ output [0:0] const1 ; endmodule -module grid_clb_mux_1level_size2_3 ( in , sram , sram_inv , out , p1 ) ; +module grid_clb_mux_1level_size2_3 ( in , sram , sram_inv , out , p5 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; output [0:0] out ; -input p1 ; +input p5 ; wire [0:2] local_encoder2to3_0_data ; wire [0:2] local_encoder2to3_0_data_inv ; @@ -77953,19 +82375,19 @@ grid_clb_mux_1level_basis_input3_mem3_3 mux_l1_in_0_ ( .in ( { in[0] , in[1] , SYNOPSYS_UNCONNECTED_2 } ) , .mem ( local_encoder2to3_0_data ) , .mem_inv ( local_encoder2to3_0_data_inv ) , - .out ( mux_1level_basis_input3_mem3_0_out ) , .p1 ( p1 ) ) ; + .out ( mux_1level_basis_input3_mem3_0_out ) , .p5 ( p5 ) ) ; endmodule module grid_clb_mux_1level_basis_input3_mem3_2 ( in , mem , mem_inv , out , - p5 ) ; + p1 ) ; input [0:2] in ; input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; -input p5 ; +input p1 ; -scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p5 ) , +scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p1 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out[0] ) ) ; @@ -77993,12 +82415,12 @@ output [0:0] const1 ; endmodule -module grid_clb_mux_1level_size2_2 ( in , sram , sram_inv , out , p5 ) ; +module grid_clb_mux_1level_size2_2 ( in , sram , sram_inv , out , p1 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; output [0:0] out ; -input p5 ; +input p1 ; wire [0:2] local_encoder2to3_0_data ; wire [0:2] local_encoder2to3_0_data_inv ; @@ -78015,7 +82437,7 @@ grid_clb_mux_1level_basis_input3_mem3_2 mux_l1_in_0_ ( .in ( { in[0] , in[1] , SYNOPSYS_UNCONNECTED_2 } ) , .mem ( local_encoder2to3_0_data ) , .mem_inv ( local_encoder2to3_0_data_inv ) , - .out ( mux_1level_basis_input3_mem3_0_out ) , .p5 ( p5 ) ) ; + .out ( mux_1level_basis_input3_mem3_0_out ) , .p1 ( p1 ) ) ; endmodule @@ -78110,22 +82532,22 @@ grid_clb_mux_1level_tapbuf_basis_input3_mem3_1 mux_l1_in_0_ ( .mem ( local_encoder2to3_0_data ) , .mem_inv ( local_encoder2to3_0_data_inv ) , .out ( mux_1level_tapbuf_basis_input3_mem3_0_out ) , .p1 ( p1 ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_136 ( +sky130_fd_sc_hd__inv_1 BINV_R_135 ( .A ( mux_1level_tapbuf_basis_input3_mem3_0_out[0] ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_137 ( +sky130_fd_sc_hd__inv_8 BINV_R_136 ( .A ( mux_1level_tapbuf_basis_input3_mem3_0_out[0] ) , .Y ( p_abuf0 ) ) ; endmodule module grid_clb_mux_1level_tapbuf_basis_input3_mem3_0 ( in , mem , mem_inv , - out , p4 ) ; + out , p1 ) ; input [0:2] in ; input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; -input p4 ; +input p1 ; -scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p4 ) , +scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p1 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out[0] ) ) ; @@ -78154,13 +82576,13 @@ endmodule module grid_clb_mux_1level_tapbuf_size2_0 ( in , sram , sram_inv , out , - p_abuf0 , p4 ) ; + p_abuf0 , p1 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; output [0:0] out ; output p_abuf0 ; -input p4 ; +input p1 ; wire [0:2] local_encoder2to3_0_data ; wire [0:2] local_encoder2to3_0_data_inv ; @@ -78175,10 +82597,10 @@ grid_clb_mux_1level_tapbuf_basis_input3_mem3_0 mux_l1_in_0_ ( .in ( { in[0] , in[1] , SYNOPSYS_UNCONNECTED_2 } ) , .mem ( local_encoder2to3_0_data ) , .mem_inv ( local_encoder2to3_0_data_inv ) , - .out ( mux_1level_tapbuf_basis_input3_mem3_0_out ) , .p4 ( p4 ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_133 ( + .out ( mux_1level_tapbuf_basis_input3_mem3_0_out ) , .p1 ( p1 ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_132 ( .A ( mux_1level_tapbuf_basis_input3_mem3_0_out[0] ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_134 ( +sky130_fd_sc_hd__inv_8 BINV_R_133 ( .A ( mux_1level_tapbuf_basis_input3_mem3_0_out[0] ) , .Y ( p_abuf0 ) ) ; endmodule @@ -78246,14 +82668,14 @@ endmodule module grid_clb_mux_1level_basis_input3_mem3_1 ( in , mem , mem_inv , out , - p4 ) ; + p2 ) ; input [0:2] in ; input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; -input p4 ; +input p2 ; -scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p4 ) , +scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p2 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out[0] ) ) ; @@ -78281,12 +82703,12 @@ output [0:0] const1 ; endmodule -module grid_clb_mux_1level_size2_1 ( in , sram , sram_inv , out , p4 ) ; +module grid_clb_mux_1level_size2_1 ( in , sram , sram_inv , out , p2 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; output [0:0] out ; -input p4 ; +input p2 ; wire [0:2] local_encoder2to3_0_data ; wire [0:2] local_encoder2to3_0_data_inv ; @@ -78303,19 +82725,19 @@ grid_clb_mux_1level_basis_input3_mem3_1 mux_l1_in_0_ ( .in ( { in[0] , in[1] , SYNOPSYS_UNCONNECTED_2 } ) , .mem ( local_encoder2to3_0_data ) , .mem_inv ( local_encoder2to3_0_data_inv ) , - .out ( mux_1level_basis_input3_mem3_0_out ) , .p4 ( p4 ) ) ; + .out ( mux_1level_basis_input3_mem3_0_out ) , .p2 ( p2 ) ) ; endmodule module grid_clb_mux_1level_basis_input3_mem3_0 ( in , mem , mem_inv , out , - p4 ) ; + p2 ) ; input [0:2] in ; input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; -input p4 ; +input p2 ; -scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p4 ) , +scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p2 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out[0] ) ) ; @@ -78343,12 +82765,12 @@ output [0:0] const1 ; endmodule -module grid_clb_mux_1level_size2_0 ( in , sram , sram_inv , out , p4 ) ; +module grid_clb_mux_1level_size2_0 ( in , sram , sram_inv , out , p2 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; output [0:0] out ; -input p4 ; +input p2 ; wire [0:2] local_encoder2to3_0_data ; wire [0:2] local_encoder2to3_0_data_inv ; @@ -78365,7 +82787,7 @@ grid_clb_mux_1level_basis_input3_mem3_0 mux_l1_in_0_ ( .in ( { in[0] , in[1] , SYNOPSYS_UNCONNECTED_2 } ) , .mem ( local_encoder2to3_0_data ) , .mem_inv ( local_encoder2to3_0_data_inv ) , - .out ( mux_1level_basis_input3_mem3_0_out ) , .p4 ( p4 ) ) ; + .out ( mux_1level_basis_input3_mem3_0_out ) , .p2 ( p2 ) ) ; endmodule @@ -78402,7 +82824,7 @@ input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:16] mem_out ; -sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ropt_net_252 ) , +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ropt_net_244 ) , .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; @@ -78437,20 +82859,20 @@ sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_15_ ( .D ( mem_out[14] ) , sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_16_ ( .D ( mem_out[15] ) , .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[16] ) ) ; sky130_fd_sc_hd__buf_1 FTB_1__0 ( .A ( mem_out[16] ) , .X ( ccff_tail[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1699 ( .A ( copt_net_242 ) , - .X ( copt_net_239 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1700 ( .A ( copt_net_239 ) , - .X ( copt_net_240 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1701 ( .A ( copt_net_244 ) , - .X ( copt_net_241 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1702 ( .A ( copt_net_243 ) , - .X ( copt_net_242 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1703 ( .A ( copt_net_241 ) , - .X ( copt_net_243 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1704 ( .A ( ccff_head[0] ) , - .X ( copt_net_244 ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 ropt_h_inst_1712 ( .A ( copt_net_240 ) , - .X ( ropt_net_252 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1589 ( .A ( ccff_head[0] ) , + .X ( copt_net_232 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1590 ( .A ( copt_net_232 ) , + .X ( copt_net_233 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1591 ( .A ( copt_net_233 ) , + .X ( copt_net_234 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1592 ( .A ( copt_net_234 ) , + .X ( copt_net_235 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1593 ( .A ( copt_net_237 ) , + .X ( copt_net_236 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1594 ( .A ( copt_net_235 ) , + .X ( copt_net_237 ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 ropt_h_inst_1601 ( .A ( copt_net_236 ) , + .X ( ropt_net_244 ) ) ; endmodule @@ -78596,7 +83018,7 @@ endmodule module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0 ( pReset , prog_clk , frac_logic_in , frac_logic_cin , ccff_head , - frac_logic_out , frac_logic_cout , ccff_tail , p4 ) ; + frac_logic_out , frac_logic_cout , ccff_tail , p2 ) ; input [0:0] pReset ; input [0:0] prog_clk ; input [0:3] frac_logic_in ; @@ -78605,7 +83027,7 @@ input [0:0] ccff_head ; output [0:1] frac_logic_out ; output [0:0] frac_logic_cout ; output [0:0] ccff_tail ; -input p4 ; +input p2 ; wire [0:0] direct_interc_5_out ; wire [0:0] direct_interc_7_out ; @@ -78641,12 +83063,12 @@ grid_clb_mux_1level_size2_0 mux_frac_logic_out_0 ( } ) , .sram ( mux_1level_size2_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_2 , SYNOPSYS_UNCONNECTED_3 } ) , - .out ( frac_logic_out[0] ) , .p4 ( p4 ) ) ; + .out ( frac_logic_out[0] ) , .p2 ( p2 ) ) ; grid_clb_mux_1level_size2_1 mux_frac_lut4_0_in_2 ( .in ( { frac_logic_cin[0] , frac_logic_in[2] } ) , .sram ( mux_1level_size2_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_4 , SYNOPSYS_UNCONNECTED_5 } ) , - .out ( mux_1level_size2_1_out ) , .p4 ( p4 ) ) ; + .out ( mux_1level_size2_1_out ) , .p2 ( p2 ) ) ; grid_clb_mux_1level_size2_mem_0 mem_frac_logic_out_0 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ) , @@ -78662,7 +83084,7 @@ module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_0 ( pReset , prog_clk , Test_en , fabric_in , fabric_reg_in , fabric_sc_in , fabric_cin , fabric_reset , fabric_clk , ccff_head , fabric_out , fabric_reg_out , fabric_sc_out , fabric_cout , ccff_tail , p_abuf0 , - p_abuf1 , p1 , p4 , p5 ) ; + p_abuf1 , p1 , p2 , p5 ) ; input [0:0] pReset ; input [0:0] prog_clk ; input [0:0] Test_en ; @@ -78681,7 +83103,7 @@ output [0:0] ccff_tail ; output p_abuf0 ; output p_abuf1 ; input p1 ; -input p4 ; +input p2 ; input p5 ; wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ; @@ -78707,7 +83129,7 @@ grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ .frac_logic_cout ( { SYNOPSYS_UNCONNECTED_1 } ) , .ccff_tail ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) , - .p4 ( p4 ) ) ; + .p2 ( p2 ) ) ; grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0 ( .Test_en ( Test_en ) , .ff_D ( mux_1level_size2_0_out ) , .ff_DI ( fabric_sc_in ) , .ff_reset ( fabric_reset ) , @@ -78725,7 +83147,7 @@ grid_clb_mux_1level_tapbuf_size2_0 mux_fabric_out_0 ( } ) , .sram ( mux_1level_tapbuf_size2_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_2 , SYNOPSYS_UNCONNECTED_3 } ) , - .out ( fabric_out[0] ) , .p_abuf0 ( p_abuf0 ) , .p4 ( p4 ) ) ; + .out ( fabric_out[0] ) , .p_abuf0 ( p_abuf0 ) , .p1 ( p1 ) ) ; grid_clb_mux_1level_tapbuf_size2_1 mux_fabric_out_1 ( .in ( { fabric_sc_out[0] , logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] @@ -78751,7 +83173,7 @@ grid_clb_mux_1level_size2_2 mux_ff_0_D_0 ( fabric_reg_in[0] } ) , .sram ( mux_1level_size2_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_6 , SYNOPSYS_UNCONNECTED_7 } ) , - .out ( mux_1level_size2_0_out ) , .p5 ( p5 ) ) ; + .out ( mux_1level_size2_0_out ) , .p1 ( p1 ) ) ; grid_clb_mux_1level_size2_3 mux_ff_1_D_0 ( .in ( { logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] , @@ -78759,7 +83181,7 @@ grid_clb_mux_1level_size2_3 mux_ff_1_D_0 ( } ) , .sram ( mux_1level_size2_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_8 , SYNOPSYS_UNCONNECTED_9 } ) , - .out ( mux_1level_size2_1_out ) , .p1 ( p1 ) ) ; + .out ( mux_1level_size2_1_out ) , .p5 ( p5 ) ) ; grid_clb_mux_1level_size2_mem_2 mem_ff_0_D_0 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( mux_1level_tapbuf_size2_mem_1_ccff_tail ) , @@ -78774,7 +83196,7 @@ endmodule module grid_clb_logical_tile_clb_mode_default__fle_0 ( pReset , prog_clk , Test_en , fle_in , fle_reg_in , fle_sc_in , fle_cin , fle_reset , fle_clk , ccff_head , fle_out , fle_reg_out , fle_sc_out , fle_cout , - ccff_tail , p_abuf0 , p_abuf1 , p1 , p4 , p5 ) ; + ccff_tail , p_abuf0 , p_abuf1 , p1 , p2 , p5 ) ; input [0:0] pReset ; input [0:0] prog_clk ; input [0:0] Test_en ; @@ -78793,7 +83215,7 @@ output [0:0] ccff_tail ; output p_abuf0 ; output p_abuf1 ; input p1 ; -input p4 ; +input p2 ; input p5 ; grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_0 logical_tile_clb_mode_default__fle_mode_physical__fabric_0 ( @@ -78806,7 +83228,7 @@ grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_0 logical_tile .fabric_reg_out ( fle_reg_out ) , .fabric_sc_out ( fle_sc_out ) , .fabric_cout ( { SYNOPSYS_UNCONNECTED_2 } ) , .ccff_tail ( ccff_tail ) , .p_abuf0 ( p_abuf0 ) , .p_abuf1 ( p_abuf1 ) , - .p1 ( p1 ) , .p4 ( p4 ) , .p5 ( p5 ) ) ; + .p1 ( p1 ) , .p2 ( p2 ) , .p5 ( p5 ) ) ; endmodule @@ -78909,7 +83331,7 @@ grid_clb_logical_tile_clb_mode_default__fle_0 logical_tile_clb_mode_default__fle .fle_sc_out ( logical_tile_clb_mode_default__fle_0_fle_sc_out ) , .fle_cout ( { SYNOPSYS_UNCONNECTED_2 } ) , .ccff_tail ( logical_tile_clb_mode_default__fle_0_ccff_tail ) , - .p_abuf0 ( p_abuf1 ) , .p_abuf1 ( p_abuf2 ) , .p1 ( p2 ) , .p4 ( p5 ) , + .p_abuf0 ( p_abuf1 ) , .p_abuf1 ( p_abuf2 ) , .p1 ( p2 ) , .p2 ( p3 ) , .p5 ( p6 ) ) ; grid_clb_logical_tile_clb_mode_default__fle_1 logical_tile_clb_mode_default__fle_1 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , @@ -78924,7 +83346,8 @@ grid_clb_logical_tile_clb_mode_default__fle_1 logical_tile_clb_mode_default__fle .fle_sc_out ( logical_tile_clb_mode_default__fle_1_fle_sc_out ) , .fle_cout ( { SYNOPSYS_UNCONNECTED_4 } ) , .ccff_tail ( logical_tile_clb_mode_default__fle_1_ccff_tail ) , - .p_abuf0 ( p_abuf3 ) , .p_abuf1 ( p_abuf4 ) , .p0 ( p0 ) , .p5 ( p6 ) ) ; + .p_abuf0 ( p_abuf3 ) , .p_abuf1 ( p_abuf4 ) , .p0 ( p0 ) , .p1 ( p2 ) , + .p5 ( p6 ) ) ; grid_clb_logical_tile_clb_mode_default__fle_2 logical_tile_clb_mode_default__fle_2 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , .fle_in ( { clb_I2[0] , clb_I2[1] , clb_I2i[0] , clb_I2i[1] } ) , @@ -78938,7 +83361,7 @@ grid_clb_logical_tile_clb_mode_default__fle_2 logical_tile_clb_mode_default__fle .fle_sc_out ( logical_tile_clb_mode_default__fle_2_fle_sc_out ) , .fle_cout ( { SYNOPSYS_UNCONNECTED_6 } ) , .ccff_tail ( logical_tile_clb_mode_default__fle_2_ccff_tail ) , - .p_abuf0 ( p_abuf5 ) , .p_abuf1 ( p_abuf6 ) , .p1 ( p2 ) , .p2 ( p3 ) ) ; + .p_abuf0 ( p_abuf5 ) , .p_abuf1 ( p_abuf6 ) , .p2 ( p3 ) , .p4 ( p5 ) ) ; grid_clb_logical_tile_clb_mode_default__fle_3 logical_tile_clb_mode_default__fle_3 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , .fle_in ( { clb_I3[0] , clb_I3[1] , clb_I3i[0] , clb_I3i[1] } ) , @@ -78952,7 +83375,7 @@ grid_clb_logical_tile_clb_mode_default__fle_3 logical_tile_clb_mode_default__fle .fle_sc_out ( logical_tile_clb_mode_default__fle_3_fle_sc_out ) , .fle_cout ( { SYNOPSYS_UNCONNECTED_8 } ) , .ccff_tail ( logical_tile_clb_mode_default__fle_3_ccff_tail ) , - .p_abuf0 ( p_abuf7 ) , .p_abuf1 ( p_abuf8 ) , .p0 ( p1 ) , .p2 ( p3 ) ) ; + .p_abuf0 ( p_abuf7 ) , .p_abuf1 ( p_abuf8 ) , .p0 ( p1 ) , .p6 ( p7 ) ) ; grid_clb_logical_tile_clb_mode_default__fle_4 logical_tile_clb_mode_default__fle_4 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , .fle_in ( { clb_I4[0] , clb_I4[1] , clb_I4i[0] , clb_I4i[1] } ) , @@ -78966,7 +83389,7 @@ grid_clb_logical_tile_clb_mode_default__fle_4 logical_tile_clb_mode_default__fle .fle_sc_out ( logical_tile_clb_mode_default__fle_4_fle_sc_out ) , .fle_cout ( { SYNOPSYS_UNCONNECTED_10 } ) , .ccff_tail ( logical_tile_clb_mode_default__fle_4_ccff_tail ) , - .p_abuf0 ( p_abuf9 ) , .p_abuf1 ( p_abuf10 ) , .p0 ( p1 ) ) ; + .p_abuf0 ( p_abuf9 ) , .p_abuf1 ( p_abuf10 ) , .p6 ( p7 ) ) ; grid_clb_logical_tile_clb_mode_default__fle_5 logical_tile_clb_mode_default__fle_5 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , .fle_in ( { clb_I5[0] , clb_I5[1] , clb_I5i[0] , clb_I5i[1] } ) , @@ -78980,7 +83403,8 @@ grid_clb_logical_tile_clb_mode_default__fle_5 logical_tile_clb_mode_default__fle .fle_sc_out ( logical_tile_clb_mode_default__fle_5_fle_sc_out ) , .fle_cout ( { SYNOPSYS_UNCONNECTED_12 } ) , .ccff_tail ( logical_tile_clb_mode_default__fle_5_ccff_tail ) , - .p_abuf0 ( p_abuf11 ) , .p_abuf1 ( p_abuf12 ) , .p6 ( p7 ) ) ; + .p_abuf0 ( p_abuf11 ) , .p_abuf1 ( p_abuf12 ) , .p0 ( p1 ) , .p3 ( p4 ) , + .p6 ( p7 ) ) ; grid_clb_logical_tile_clb_mode_default__fle_6 logical_tile_clb_mode_default__fle_6 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , .fle_in ( { clb_I6[0] , clb_I6[1] , clb_I6i[0] , clb_I6i[1] } ) , @@ -78994,7 +83418,7 @@ grid_clb_logical_tile_clb_mode_default__fle_6 logical_tile_clb_mode_default__fle .fle_sc_out ( logical_tile_clb_mode_default__fle_6_fle_sc_out ) , .fle_cout ( { SYNOPSYS_UNCONNECTED_14 } ) , .ccff_tail ( logical_tile_clb_mode_default__fle_6_ccff_tail ) , - .p_abuf0 ( p_abuf13 ) , .p_abuf1 ( p_abuf14 ) , .p3 ( p4 ) , .p6 ( p7 ) ) ; + .p_abuf0 ( p_abuf13 ) , .p_abuf1 ( p_abuf14 ) , .p0 ( p1 ) , .p3 ( p4 ) ) ; grid_clb_logical_tile_clb_mode_default__fle logical_tile_clb_mode_default__fle_7 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , .fle_in ( { clb_I7[0] , clb_I7[1] , clb_I7i[0] , clb_I7i[1] } ) , @@ -79006,7 +83430,7 @@ grid_clb_logical_tile_clb_mode_default__fle logical_tile_clb_mode_default__fle_7 .fle_out ( { clb_O[15] , clb_O[14] } ) , .fle_reg_out ( clb_reg_out ) , .fle_sc_out ( clb_sc_out ) , .fle_cout ( clb_cout ) , .ccff_tail ( ccff_tail ) , .p_abuf0 ( p_abuf0 ) , - .p_abuf1 ( p_abuf15 ) , .p_abuf2 ( p_abuf16 ) , .p0 ( p0 ) , .p3 ( p4 ) ) ; + .p_abuf1 ( p_abuf15 ) , .p_abuf2 ( p_abuf16 ) , .p0 ( p1 ) , .p3 ( p4 ) ) ; endmodule @@ -79155,7 +83579,10 @@ output prog_clk_0_N_out ; input clk_0_N_in ; input clk_0_S_in ; -wire p_abuf12 ; +wire p_abuf10 ; +wire p_abuf14 ; +wire p_abuf16 ; +wire p_abuf0 ; wire prog_clk_0 ; wire [0:0] prog_clk ; wire [0:0] clk ; @@ -79210,16 +83637,17 @@ grid_clb_logical_tile_clb_mode_clb_ logical_tile_clb_mode_clb__0 ( .clb_sc_in ( { SC_IN_BOT } ) , .clb_cin ( { SYNOPSYS_UNCONNECTED_1 } ) , .clb_reset ( Reset ) , .clb_clk ( clk ) , .ccff_head ( ccff_head ) , - .clb_O ( { aps_rename_507_ , aps_rename_508_ , aps_rename_509_ , - aps_rename_510_ , aps_rename_511_ , aps_rename_512_ , - aps_rename_513_ , aps_rename_514_ , aps_rename_515_ , - aps_rename_516_ , right_width_0_height_0__pin_46_lower[0] , - aps_rename_518_ , aps_rename_519_ , aps_rename_520_ , - aps_rename_521_ , aps_rename_522_ } ) , + .clb_O ( { aps_rename_506_ , aps_rename_507_ , aps_rename_508_ , + aps_rename_509_ , aps_rename_510_ , aps_rename_511_ , + aps_rename_512_ , aps_rename_513_ , + right_width_0_height_0__pin_44_lower[0] , aps_rename_515_ , + aps_rename_516_ , aps_rename_517_ , + right_width_0_height_0__pin_48_lower[0] , aps_rename_519_ , + right_width_0_height_0__pin_50_lower[0] , aps_rename_521_ } ) , .clb_reg_out ( bottom_width_0_height_0__pin_52_ ) , - .clb_sc_out ( { aps_rename_523_ } ) , + .clb_sc_out ( { SC_OUT_BOT } ) , .clb_cout ( bottom_width_0_height_0__pin_54_ ) , - .ccff_tail ( ccff_tail ) , .p_abuf0 ( SC_OUT_BOT ) , + .ccff_tail ( ccff_tail ) , .p_abuf0 ( p_abuf0 ) , .p_abuf1 ( top_width_0_height_0__pin_37_lower[0] ) , .p_abuf2 ( top_width_0_height_0__pin_36_lower[0] ) , .p_abuf3 ( top_width_0_height_0__pin_39_lower[0] ) , @@ -79229,106 +83657,94 @@ grid_clb_logical_tile_clb_mode_clb_ logical_tile_clb_mode_clb__0 ( .p_abuf7 ( top_width_0_height_0__pin_43_lower[0] ) , .p_abuf8 ( top_width_0_height_0__pin_42_lower[0] ) , .p_abuf9 ( right_width_0_height_0__pin_45_lower[0] ) , - .p_abuf10 ( right_width_0_height_0__pin_44_lower[0] ) , + .p_abuf10 ( p_abuf10 ) , .p_abuf11 ( right_width_0_height_0__pin_47_lower[0] ) , - .p_abuf12 ( p_abuf12 ) , + .p_abuf12 ( right_width_0_height_0__pin_46_lower[0] ) , .p_abuf13 ( right_width_0_height_0__pin_49_lower[0] ) , - .p_abuf14 ( right_width_0_height_0__pin_48_lower[0] ) , + .p_abuf14 ( p_abuf14 ) , .p_abuf15 ( right_width_0_height_0__pin_51_lower[0] ) , - .p_abuf16 ( right_width_0_height_0__pin_50_lower[0] ) , - .p0 ( optlc_net_227 ) , .p1 ( optlc_net_228 ) , .p2 ( optlc_net_229 ) , - .p3 ( optlc_net_230 ) , .p4 ( optlc_net_231 ) , .p5 ( optlc_net_232 ) , - .p6 ( optlc_net_233 ) , .p7 ( optlc_net_234 ) ) ; + .p_abuf16 ( p_abuf16 ) , .p0 ( optlc_net_220 ) , .p1 ( optlc_net_221 ) , + .p2 ( optlc_net_222 ) , .p3 ( optlc_net_223 ) , .p4 ( optlc_net_224 ) , + .p5 ( optlc_net_225 ) , .p6 ( optlc_net_226 ) , .p7 ( optlc_net_227 ) ) ; sky130_fd_sc_hd__buf_2 Test_en_FTB00 ( .A ( Test_en_W_in ) , .X ( Test_en[0] ) ) ; -sky130_fd_sc_hd__buf_1 Test_en_W_FTB01 ( .A ( Test_en_W_in ) , - .X ( net_net_181 ) ) ; -sky130_fd_sc_hd__buf_1 Test_en_E_FTB01 ( .A ( Test_en_W_in ) , - .X ( net_net_182 ) ) ; +sky130_fd_sc_hd__bufbuf_16 Test_en_W_FTB01 ( .A ( Test_en_W_in ) , + .X ( Test_en_W_out ) ) ; +sky130_fd_sc_hd__bufbuf_16 Test_en_E_FTB01 ( .A ( Test_en_W_in ) , + .X ( Test_en_E_out ) ) ; sky130_fd_sc_hd__buf_8 pReset_FTB00 ( .A ( pReset_N_in ) , .X ( pReset[0] ) ) ; sky130_fd_sc_hd__buf_4 Reset_FTB00 ( .A ( Reset_W_in ) , .X ( Reset[0] ) ) ; -sky130_fd_sc_hd__buf_1 Reset_W_FTB01 ( .A ( Reset_W_in ) , - .X ( aps_rename_524_ ) ) ; -sky130_fd_sc_hd__buf_1 Reset_E_FTB01 ( .A ( Reset_W_in ) , - .X ( aps_rename_525_ ) ) ; +sky130_fd_sc_hd__bufbuf_16 Reset_W_FTB01 ( .A ( Reset_W_in ) , + .X ( Reset_W_out ) ) ; +sky130_fd_sc_hd__bufbuf_16 Reset_E_FTB01 ( .A ( Reset_W_in ) , + .X ( Reset_E_out ) ) ; sky130_fd_sc_hd__buf_6 prog_clk_0_FTB00 ( .A ( prog_clk_0_S_in ) , .X ( prog_clk_0 ) ) ; -sky130_fd_sc_hd__clkbuf_1 prog_clk_0_S_FTB01 ( .A ( prog_clk_0_S_in ) , - .X ( ctsbuf_net_1235 ) ) ; +sky130_fd_sc_hd__buf_4 prog_clk_0_S_FTB01 ( .A ( prog_clk_0_S_in ) , + .X ( ctsbuf_net_1228 ) ) ; sky130_fd_sc_hd__clkbuf_1 prog_clk_0_E_FTB01 ( .A ( prog_clk_0_S_in ) , - .X ( ctsbuf_net_2236 ) ) ; + .X ( ctsbuf_net_2229 ) ) ; sky130_fd_sc_hd__clkbuf_1 prog_clk_0_W_FTB01 ( .A ( prog_clk_0_S_in ) , - .X ( ctsbuf_net_3237 ) ) ; -sky130_fd_sc_hd__buf_4 prog_clk_0_N_FTB01 ( .A ( prog_clk_0_S_in ) , - .X ( ctsbuf_net_4238 ) ) ; + .X ( ctsbuf_net_3230 ) ) ; +sky130_fd_sc_hd__clkbuf_1 prog_clk_0_N_FTB01 ( .A ( prog_clk_0_S_in ) , + .X ( ctsbuf_net_4231 ) ) ; sky130_fd_sc_hd__buf_1 clk_0_FTB00 ( .A ( clk_0_S_in ) , .X ( clk[0] ) ) ; -sky130_fd_sc_hd__buf_6 FTB_113__112 ( .A ( aps_rename_507_ ) , +sky130_fd_sc_hd__buf_6 FTB_113__112 ( .A ( aps_rename_506_ ) , .X ( top_width_0_height_0__pin_36_upper[0] ) ) ; -sky130_fd_sc_hd__buf_6 FTB_114__113 ( .A ( aps_rename_508_ ) , +sky130_fd_sc_hd__buf_6 FTB_114__113 ( .A ( aps_rename_507_ ) , .X ( top_width_0_height_0__pin_37_upper[0] ) ) ; -sky130_fd_sc_hd__buf_6 FTB_115__114 ( .A ( aps_rename_509_ ) , +sky130_fd_sc_hd__buf_6 FTB_115__114 ( .A ( aps_rename_508_ ) , .X ( top_width_0_height_0__pin_38_upper[0] ) ) ; -sky130_fd_sc_hd__buf_6 FTB_116__115 ( .A ( aps_rename_510_ ) , +sky130_fd_sc_hd__buf_6 FTB_116__115 ( .A ( aps_rename_509_ ) , .X ( top_width_0_height_0__pin_39_upper[0] ) ) ; -sky130_fd_sc_hd__buf_6 FTB_117__116 ( .A ( aps_rename_511_ ) , +sky130_fd_sc_hd__buf_6 FTB_117__116 ( .A ( aps_rename_510_ ) , .X ( top_width_0_height_0__pin_40_upper[0] ) ) ; -sky130_fd_sc_hd__buf_6 FTB_118__117 ( .A ( aps_rename_512_ ) , +sky130_fd_sc_hd__buf_6 FTB_118__117 ( .A ( aps_rename_511_ ) , .X ( top_width_0_height_0__pin_41_upper[0] ) ) ; -sky130_fd_sc_hd__buf_6 FTB_119__118 ( .A ( aps_rename_513_ ) , +sky130_fd_sc_hd__buf_6 FTB_119__118 ( .A ( aps_rename_512_ ) , .X ( top_width_0_height_0__pin_42_upper[0] ) ) ; -sky130_fd_sc_hd__buf_6 FTB_120__119 ( .A ( aps_rename_514_ ) , +sky130_fd_sc_hd__buf_6 FTB_120__119 ( .A ( aps_rename_513_ ) , .X ( top_width_0_height_0__pin_43_upper[0] ) ) ; -sky130_fd_sc_hd__buf_6 FTB_121__120 ( .A ( aps_rename_515_ ) , +sky130_fd_sc_hd__buf_6 FTB_121__120 ( .A ( p_abuf10 ) , .X ( right_width_0_height_0__pin_44_upper[0] ) ) ; -sky130_fd_sc_hd__buf_6 FTB_122__121 ( .A ( aps_rename_516_ ) , +sky130_fd_sc_hd__buf_6 FTB_122__121 ( .A ( aps_rename_515_ ) , .X ( right_width_0_height_0__pin_45_upper[0] ) ) ; -sky130_fd_sc_hd__buf_6 FTB_123__122 ( .A ( p_abuf12 ) , +sky130_fd_sc_hd__buf_6 FTB_123__122 ( .A ( aps_rename_516_ ) , .X ( right_width_0_height_0__pin_46_upper[0] ) ) ; -sky130_fd_sc_hd__buf_6 FTB_124__123 ( .A ( aps_rename_518_ ) , +sky130_fd_sc_hd__buf_6 FTB_124__123 ( .A ( aps_rename_517_ ) , .X ( right_width_0_height_0__pin_47_upper[0] ) ) ; -sky130_fd_sc_hd__buf_6 FTB_125__124 ( .A ( aps_rename_519_ ) , +sky130_fd_sc_hd__buf_6 FTB_125__124 ( .A ( p_abuf14 ) , .X ( right_width_0_height_0__pin_48_upper[0] ) ) ; -sky130_fd_sc_hd__buf_6 FTB_126__125 ( .A ( aps_rename_520_ ) , +sky130_fd_sc_hd__buf_6 FTB_126__125 ( .A ( aps_rename_519_ ) , .X ( right_width_0_height_0__pin_49_upper[0] ) ) ; -sky130_fd_sc_hd__buf_6 FTB_127__126 ( .A ( aps_rename_521_ ) , +sky130_fd_sc_hd__buf_6 FTB_127__126 ( .A ( p_abuf16 ) , .X ( right_width_0_height_0__pin_50_upper[0] ) ) ; -sky130_fd_sc_hd__buf_6 FTB_128__127 ( .A ( aps_rename_522_ ) , +sky130_fd_sc_hd__buf_6 FTB_128__127 ( .A ( aps_rename_521_ ) , .X ( right_width_0_height_0__pin_51_upper[0] ) ) ; -sky130_fd_sc_hd__buf_6 FTB_129__128 ( .A ( aps_rename_523_ ) , - .X ( SC_OUT_TOP ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_181 ( .A ( net_net_181 ) , - .X ( Test_en_W_out ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_182 ( .A ( net_net_182 ) , - .X ( Test_en_E_out ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_183 ( .A ( BUF_net_184 ) , .Y ( Reset_W_out ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_184 ( .A ( aps_rename_524_ ) , - .Y ( BUF_net_184 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_185 ( .A ( BUF_net_186 ) , .Y ( Reset_E_out ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_186 ( .A ( aps_rename_525_ ) , - .Y ( BUF_net_186 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_189 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , +sky130_fd_sc_hd__buf_6 FTB_129__128 ( .A ( p_abuf0 ) , .X ( SC_OUT_TOP ) ) ; +sky130_fd_sc_hd__conb_1 optlc_182 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , + .HI ( optlc_net_220 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_184 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , + .HI ( optlc_net_221 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_186 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , + .HI ( optlc_net_222 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_188 ( .LO ( SYNOPSYS_UNCONNECTED_5 ) , + .HI ( optlc_net_223 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_190 ( .LO ( SYNOPSYS_UNCONNECTED_6 ) , + .HI ( optlc_net_224 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_192 ( .LO ( SYNOPSYS_UNCONNECTED_7 ) , + .HI ( optlc_net_225 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_194 ( .LO ( SYNOPSYS_UNCONNECTED_8 ) , + .HI ( optlc_net_226 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_196 ( .LO ( SYNOPSYS_UNCONNECTED_9 ) , .HI ( optlc_net_227 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_191 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , - .HI ( optlc_net_228 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_193 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , - .HI ( optlc_net_229 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_195 ( .LO ( SYNOPSYS_UNCONNECTED_5 ) , - .HI ( optlc_net_230 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_197 ( .LO ( SYNOPSYS_UNCONNECTED_6 ) , - .HI ( optlc_net_231 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_199 ( .LO ( SYNOPSYS_UNCONNECTED_7 ) , - .HI ( optlc_net_232 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_201 ( .LO ( SYNOPSYS_UNCONNECTED_8 ) , - .HI ( optlc_net_233 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_203 ( .LO ( SYNOPSYS_UNCONNECTED_9 ) , - .HI ( optlc_net_234 ) ) ; -sky130_fd_sc_hd__buf_6 cts_buf_4181396 ( .A ( ctsbuf_net_1235 ) , +sky130_fd_sc_hd__buf_6 cts_buf_4181389 ( .A ( ctsbuf_net_1228 ) , .X ( prog_clk_0_S_out ) ) ; -sky130_fd_sc_hd__buf_6 cts_buf_4231401 ( .A ( ctsbuf_net_2236 ) , +sky130_fd_sc_hd__clkbuf_8 cts_buf_4231394 ( .A ( ctsbuf_net_2229 ) , .X ( prog_clk_0_E_out ) ) ; -sky130_fd_sc_hd__buf_6 cts_buf_4281406 ( .A ( ctsbuf_net_3237 ) , +sky130_fd_sc_hd__buf_6 cts_buf_4281399 ( .A ( ctsbuf_net_3230 ) , .X ( prog_clk_0_W_out ) ) ; -sky130_fd_sc_hd__buf_6 cts_buf_4331411 ( .A ( ctsbuf_net_4238 ) , +sky130_fd_sc_hd__buf_6 cts_buf_4331404 ( .A ( ctsbuf_net_4231 ) , .X ( prog_clk_0_N_out ) ) ; endmodule @@ -79713,7 +84129,19 @@ module fpga_core ( pReset , prog_clk , Test_en , IO_ISOL_N , clk , Reset , p3480 , p3481 , p3482 , p3483 , p3484 , p3485 , p3486 , p3487 , p3488 , p3489 , p3490 , p3491 , p3492 , p3493 , p3494 , p3495 , p3496 , p3497 , p3498 , p3499 , p3500 , p3501 , p3502 , p3503 , p3504 , p3505 , p3506 , - p3507 , p3508 , p3509 ) ; + p3507 , p3508 , p3509 , p3510 , p3511 , p3512 , p3513 , p3514 , p3515 , + p3516 , p3517 , p3518 , p3519 , p3520 , p3521 , p3522 , p3523 , p3524 , + p3525 , p3526 , p3527 , p3528 , p3529 , p3530 , p3531 , p3532 , p3533 , + p3534 , p3535 , p3536 , p3537 , p3538 , p3539 , p3540 , p3541 , p3542 , + p3543 , p3544 , p3545 , p3546 , p3547 , p3548 , p3549 , p3550 , p3551 , + p3552 , p3553 , p3554 , p3555 , p3556 , p3557 , p3558 , p3559 , p3560 , + p3561 , p3562 , p3563 , p3564 , p3565 , p3566 , p3567 , p3568 , p3569 , + p3570 , p3571 , p3572 , p3573 , p3574 , p3575 , p3576 , p3577 , p3578 , + p3579 , p3580 , p3581 , p3582 , p3583 , p3584 , p3585 , p3586 , p3587 , + p3588 , p3589 , p3590 , p3591 , p3592 , p3593 , p3594 , p3595 , p3596 , + p3597 , p3598 , p3599 , p3600 , p3601 , p3602 , p3603 , p3604 , p3605 , + p3606 , p3607 , p3608 , p3609 , p3610 , p3611 , p3612 , p3613 , p3614 , + p3615 , p3616 , p3617 , p3618 , p3619 , p3620 ) ; input [0:0] pReset ; input [0:0] prog_clk ; input [0:0] Test_en ; @@ -83238,6 +87666,117 @@ input p3506 ; input p3507 ; input p3508 ; input p3509 ; +input p3510 ; +input p3511 ; +input p3512 ; +input p3513 ; +input p3514 ; +input p3515 ; +input p3516 ; +input p3517 ; +input p3518 ; +input p3519 ; +input p3520 ; +input p3521 ; +input p3522 ; +input p3523 ; +input p3524 ; +input p3525 ; +input p3526 ; +input p3527 ; +input p3528 ; +input p3529 ; +input p3530 ; +input p3531 ; +input p3532 ; +input p3533 ; +input p3534 ; +input p3535 ; +input p3536 ; +input p3537 ; +input p3538 ; +input p3539 ; +input p3540 ; +input p3541 ; +input p3542 ; +input p3543 ; +input p3544 ; +input p3545 ; +input p3546 ; +input p3547 ; +input p3548 ; +input p3549 ; +input p3550 ; +input p3551 ; +input p3552 ; +input p3553 ; +input p3554 ; +input p3555 ; +input p3556 ; +input p3557 ; +input p3558 ; +input p3559 ; +input p3560 ; +input p3561 ; +input p3562 ; +input p3563 ; +input p3564 ; +input p3565 ; +input p3566 ; +input p3567 ; +input p3568 ; +input p3569 ; +input p3570 ; +input p3571 ; +input p3572 ; +input p3573 ; +input p3574 ; +input p3575 ; +input p3576 ; +input p3577 ; +input p3578 ; +input p3579 ; +input p3580 ; +input p3581 ; +input p3582 ; +input p3583 ; +input p3584 ; +input p3585 ; +input p3586 ; +input p3587 ; +input p3588 ; +input p3589 ; +input p3590 ; +input p3591 ; +input p3592 ; +input p3593 ; +input p3594 ; +input p3595 ; +input p3596 ; +input p3597 ; +input p3598 ; +input p3599 ; +input p3600 ; +input p3601 ; +input p3602 ; +input p3603 ; +input p3604 ; +input p3605 ; +input p3606 ; +input p3607 ; +input p3608 ; +input p3609 ; +input p3610 ; +input p3611 ; +input p3612 ; +input p3613 ; +input p3614 ; +input p3615 ; +input p3616 ; +input p3617 ; +input p3618 ; +input p3619 ; +input p3620 ; wire [0:0] cbx_1__0__0_bottom_grid_pin_0_ ; wire [0:0] cbx_1__0__0_bottom_grid_pin_10_ ; @@ -109133,16 +113672,16 @@ sb_1__0_ sb_1__0_ ( .chanx_right_out ( sb_1__0__0_chanx_right_out ) , .chanx_left_out ( sb_1__0__0_chanx_left_out ) , .ccff_tail ( sb_1__0__0_ccff_tail ) , .SC_IN_TOP ( scff_Wires[26] ) , - .SC_OUT_TOP ( scff_Wires[27] ) , .Test_en_S_in ( p829 ) , + .SC_OUT_TOP ( scff_Wires[27] ) , .Test_en_S_in ( p1352 ) , .Test_en_N_out ( SYNOPSYS_UNCONNECTED_2055 ) , .pReset_S_in ( SYNOPSYS_UNCONNECTED_2056 ) , .pReset_E_in ( pResetWires[28] ) , .pReset_W_in ( SYNOPSYS_UNCONNECTED_2057 ) , .pReset_N_out ( pResetWires[27] ) , .pReset_W_out ( pResetWires[26] ) , - .pReset_E_out ( SYNOPSYS_UNCONNECTED_2058 ) , .Reset_S_in ( p829 ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_2058 ) , .Reset_S_in ( p1352 ) , .Reset_N_out ( SYNOPSYS_UNCONNECTED_2059 ) , - .prog_clk_0_N_in ( prog_clk_0_wires[2] ) , .prog_clk_3_S_in ( p829 ) , - .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_2060 ) , .clk_3_S_in ( p829 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[2] ) , .prog_clk_3_S_in ( p1352 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_2060 ) , .clk_3_S_in ( p1352 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_2061 ) ) ; sb_1__0_ sb_2__0_ ( .pReset ( { SYNOPSYS_UNCONNECTED_2062 } ) , @@ -109179,17 +113718,17 @@ sb_1__0_ sb_2__0_ ( .chany_top_out ( sb_1__0__1_chany_top_out ) , .chanx_right_out ( sb_1__0__1_chanx_right_out ) , .chanx_left_out ( sb_1__0__1_chanx_left_out ) , - .ccff_tail ( sb_1__0__1_ccff_tail ) , .SC_IN_TOP ( p1229 ) , - .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_2063 ) , .Test_en_S_in ( p753 ) , + .ccff_tail ( sb_1__0__1_ccff_tail ) , .SC_IN_TOP ( p1155 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_2063 ) , .Test_en_S_in ( p1142 ) , .Test_en_N_out ( SYNOPSYS_UNCONNECTED_2064 ) , .pReset_S_in ( SYNOPSYS_UNCONNECTED_2065 ) , .pReset_E_in ( pResetWires[31] ) , .pReset_W_in ( SYNOPSYS_UNCONNECTED_2066 ) , .pReset_N_out ( pResetWires[30] ) , .pReset_W_out ( pResetWires[29] ) , - .pReset_E_out ( SYNOPSYS_UNCONNECTED_2067 ) , .Reset_S_in ( p753 ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_2067 ) , .Reset_S_in ( p1142 ) , .Reset_N_out ( SYNOPSYS_UNCONNECTED_2068 ) , - .prog_clk_0_N_in ( prog_clk_0_wires[65] ) , .prog_clk_3_S_in ( p753 ) , - .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_2069 ) , .clk_3_S_in ( p753 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[65] ) , .prog_clk_3_S_in ( p1142 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_2069 ) , .clk_3_S_in ( p1142 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_2070 ) ) ; sb_1__0_ sb_3__0_ ( .pReset ( { SYNOPSYS_UNCONNECTED_2071 } ) , @@ -109227,16 +113766,16 @@ sb_1__0_ sb_3__0_ ( .chanx_right_out ( sb_1__0__2_chanx_right_out ) , .chanx_left_out ( sb_1__0__2_chanx_left_out ) , .ccff_tail ( sb_1__0__2_ccff_tail ) , .SC_IN_TOP ( scff_Wires[79] ) , - .SC_OUT_TOP ( scff_Wires[80] ) , .Test_en_S_in ( p1276 ) , + .SC_OUT_TOP ( scff_Wires[80] ) , .Test_en_S_in ( p1149 ) , .Test_en_N_out ( SYNOPSYS_UNCONNECTED_2072 ) , .pReset_S_in ( SYNOPSYS_UNCONNECTED_2073 ) , .pReset_E_in ( pResetWires[34] ) , .pReset_W_in ( SYNOPSYS_UNCONNECTED_2074 ) , .pReset_N_out ( pResetWires[33] ) , .pReset_W_out ( pResetWires[32] ) , - .pReset_E_out ( SYNOPSYS_UNCONNECTED_2075 ) , .Reset_S_in ( p1276 ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_2075 ) , .Reset_S_in ( p1149 ) , .Reset_N_out ( SYNOPSYS_UNCONNECTED_2076 ) , - .prog_clk_0_N_in ( prog_clk_0_wires[103] ) , .prog_clk_3_S_in ( p1276 ) , - .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_2077 ) , .clk_3_S_in ( p1276 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[103] ) , .prog_clk_3_S_in ( p1149 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_2077 ) , .clk_3_S_in ( p1149 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_2078 ) ) ; sb_1__0_ sb_4__0_ ( .pReset ( { SYNOPSYS_UNCONNECTED_2079 } ) , @@ -109273,17 +113812,17 @@ sb_1__0_ sb_4__0_ ( .chany_top_out ( sb_1__0__3_chany_top_out ) , .chanx_right_out ( sb_1__0__3_chanx_right_out ) , .chanx_left_out ( sb_1__0__3_chanx_left_out ) , - .ccff_tail ( sb_1__0__3_ccff_tail ) , .SC_IN_TOP ( p1395 ) , - .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_2080 ) , .Test_en_S_in ( p1329 ) , + .ccff_tail ( sb_1__0__3_ccff_tail ) , .SC_IN_TOP ( p1309 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_2080 ) , .Test_en_S_in ( p1251 ) , .Test_en_N_out ( SYNOPSYS_UNCONNECTED_2081 ) , .pReset_S_in ( SYNOPSYS_UNCONNECTED_2082 ) , .pReset_E_in ( pResetWires[37] ) , .pReset_W_in ( SYNOPSYS_UNCONNECTED_2083 ) , .pReset_N_out ( pResetWires[36] ) , .pReset_W_out ( pResetWires[35] ) , - .pReset_E_out ( SYNOPSYS_UNCONNECTED_2084 ) , .Reset_S_in ( p1329 ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_2084 ) , .Reset_S_in ( p1251 ) , .Reset_N_out ( SYNOPSYS_UNCONNECTED_2085 ) , - .prog_clk_0_N_in ( prog_clk_0_wires[141] ) , .prog_clk_3_S_in ( p1329 ) , - .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_2086 ) , .clk_3_S_in ( p1329 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[141] ) , .prog_clk_3_S_in ( p1251 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_2086 ) , .clk_3_S_in ( p1251 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_2087 ) ) ; sb_1__0_ sb_5__0_ ( .pReset ( { SYNOPSYS_UNCONNECTED_2088 } ) , @@ -109321,16 +113860,16 @@ sb_1__0_ sb_5__0_ ( .chanx_right_out ( sb_1__0__4_chanx_right_out ) , .chanx_left_out ( sb_1__0__4_chanx_left_out ) , .ccff_tail ( sb_1__0__4_ccff_tail ) , .SC_IN_TOP ( scff_Wires[132] ) , - .SC_OUT_TOP ( scff_Wires[133] ) , .Test_en_S_in ( p1210 ) , + .SC_OUT_TOP ( scff_Wires[133] ) , .Test_en_S_in ( p1141 ) , .Test_en_N_out ( SYNOPSYS_UNCONNECTED_2089 ) , .pReset_S_in ( SYNOPSYS_UNCONNECTED_2090 ) , .pReset_E_in ( pResetWires[40] ) , .pReset_W_in ( SYNOPSYS_UNCONNECTED_2091 ) , .pReset_N_out ( pResetWires[39] ) , .pReset_W_out ( pResetWires[38] ) , - .pReset_E_out ( SYNOPSYS_UNCONNECTED_2092 ) , .Reset_S_in ( p1210 ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_2092 ) , .Reset_S_in ( p1141 ) , .Reset_N_out ( SYNOPSYS_UNCONNECTED_2093 ) , - .prog_clk_0_N_in ( prog_clk_0_wires[179] ) , .prog_clk_3_S_in ( p1210 ) , - .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_2094 ) , .clk_3_S_in ( p1210 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[179] ) , .prog_clk_3_S_in ( p1481 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_2094 ) , .clk_3_S_in ( p1141 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_2095 ) ) ; sb_1__0_ sb_6__0_ ( .pReset ( { SYNOPSYS_UNCONNECTED_2096 } ) , @@ -109367,7 +113906,7 @@ sb_1__0_ sb_6__0_ ( .chany_top_out ( sb_1__0__5_chany_top_out ) , .chanx_right_out ( sb_1__0__5_chanx_right_out ) , .chanx_left_out ( sb_1__0__5_chanx_left_out ) , - .ccff_tail ( sb_1__0__5_ccff_tail ) , .SC_IN_TOP ( p1330 ) , + .ccff_tail ( sb_1__0__5_ccff_tail ) , .SC_IN_TOP ( p1313 ) , .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_2097 ) , .Test_en_S_in ( Test_en[0] ) , .Test_en_N_out ( Test_enWires[1] ) , .pReset_S_in ( pReset[0] ) , .pReset_E_in ( SYNOPSYS_UNCONNECTED_2098 ) , @@ -109415,16 +113954,16 @@ sb_1__0_ sb_7__0_ ( .chanx_right_out ( sb_1__0__6_chanx_right_out ) , .chanx_left_out ( sb_1__0__6_chanx_left_out ) , .ccff_tail ( sb_1__0__6_ccff_tail ) , .SC_IN_TOP ( scff_Wires[185] ) , - .SC_OUT_TOP ( scff_Wires[186] ) , .Test_en_S_in ( p1165 ) , + .SC_OUT_TOP ( scff_Wires[186] ) , .Test_en_S_in ( p893 ) , .Test_en_N_out ( SYNOPSYS_UNCONNECTED_2101 ) , .pReset_S_in ( SYNOPSYS_UNCONNECTED_2102 ) , .pReset_E_in ( SYNOPSYS_UNCONNECTED_2103 ) , .pReset_W_in ( pResetWires[44] ) , .pReset_N_out ( pResetWires[45] ) , .pReset_W_out ( SYNOPSYS_UNCONNECTED_2104 ) , - .pReset_E_out ( pResetWires[46] ) , .Reset_S_in ( p1523 ) , + .pReset_E_out ( pResetWires[46] ) , .Reset_S_in ( p893 ) , .Reset_N_out ( SYNOPSYS_UNCONNECTED_2105 ) , - .prog_clk_0_N_in ( prog_clk_0_wires[255] ) , .prog_clk_3_S_in ( p1523 ) , - .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_2106 ) , .clk_3_S_in ( p1523 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[255] ) , .prog_clk_3_S_in ( p893 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_2106 ) , .clk_3_S_in ( p893 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_2107 ) ) ; sb_1__0_ sb_8__0_ ( .pReset ( { SYNOPSYS_UNCONNECTED_2108 } ) , @@ -109461,17 +114000,17 @@ sb_1__0_ sb_8__0_ ( .chany_top_out ( sb_1__0__7_chany_top_out ) , .chanx_right_out ( sb_1__0__7_chanx_right_out ) , .chanx_left_out ( sb_1__0__7_chanx_left_out ) , - .ccff_tail ( sb_1__0__7_ccff_tail ) , .SC_IN_TOP ( p1461 ) , - .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_2109 ) , .Test_en_S_in ( p981 ) , + .ccff_tail ( sb_1__0__7_ccff_tail ) , .SC_IN_TOP ( p1448 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_2109 ) , .Test_en_S_in ( p1046 ) , .Test_en_N_out ( SYNOPSYS_UNCONNECTED_2110 ) , .pReset_S_in ( SYNOPSYS_UNCONNECTED_2111 ) , .pReset_E_in ( SYNOPSYS_UNCONNECTED_2112 ) , .pReset_W_in ( pResetWires[47] ) , .pReset_N_out ( pResetWires[48] ) , .pReset_W_out ( SYNOPSYS_UNCONNECTED_2113 ) , - .pReset_E_out ( pResetWires[49] ) , .Reset_S_in ( p981 ) , + .pReset_E_out ( pResetWires[49] ) , .Reset_S_in ( p1046 ) , .Reset_N_out ( SYNOPSYS_UNCONNECTED_2114 ) , - .prog_clk_0_N_in ( prog_clk_0_wires[293] ) , .prog_clk_3_S_in ( p981 ) , - .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_2115 ) , .clk_3_S_in ( p981 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[293] ) , .prog_clk_3_S_in ( p1046 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_2115 ) , .clk_3_S_in ( p1046 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_2116 ) ) ; sb_1__0_ sb_9__0_ ( .pReset ( { SYNOPSYS_UNCONNECTED_2117 } ) , @@ -109509,16 +114048,16 @@ sb_1__0_ sb_9__0_ ( .chanx_right_out ( sb_1__0__8_chanx_right_out ) , .chanx_left_out ( sb_1__0__8_chanx_left_out ) , .ccff_tail ( sb_1__0__8_ccff_tail ) , .SC_IN_TOP ( scff_Wires[238] ) , - .SC_OUT_TOP ( scff_Wires[239] ) , .Test_en_S_in ( p1066 ) , + .SC_OUT_TOP ( scff_Wires[239] ) , .Test_en_S_in ( p813 ) , .Test_en_N_out ( SYNOPSYS_UNCONNECTED_2118 ) , .pReset_S_in ( SYNOPSYS_UNCONNECTED_2119 ) , .pReset_E_in ( SYNOPSYS_UNCONNECTED_2120 ) , .pReset_W_in ( pResetWires[50] ) , .pReset_N_out ( pResetWires[51] ) , .pReset_W_out ( SYNOPSYS_UNCONNECTED_2121 ) , - .pReset_E_out ( pResetWires[52] ) , .Reset_S_in ( p1066 ) , + .pReset_E_out ( pResetWires[52] ) , .Reset_S_in ( p813 ) , .Reset_N_out ( SYNOPSYS_UNCONNECTED_2122 ) , - .prog_clk_0_N_in ( prog_clk_0_wires[331] ) , .prog_clk_3_S_in ( p1066 ) , - .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_2123 ) , .clk_3_S_in ( p1066 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[331] ) , .prog_clk_3_S_in ( p1447 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_2123 ) , .clk_3_S_in ( p813 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_2124 ) ) ; sb_1__0_ sb_10__0_ ( .pReset ( { SYNOPSYS_UNCONNECTED_2125 } ) , @@ -109555,17 +114094,17 @@ sb_1__0_ sb_10__0_ ( .chany_top_out ( sb_1__0__9_chany_top_out ) , .chanx_right_out ( sb_1__0__9_chanx_right_out ) , .chanx_left_out ( sb_1__0__9_chanx_left_out ) , - .ccff_tail ( sb_1__0__9_ccff_tail ) , .SC_IN_TOP ( p1181 ) , - .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_2126 ) , .Test_en_S_in ( p1086 ) , + .ccff_tail ( sb_1__0__9_ccff_tail ) , .SC_IN_TOP ( p1221 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_2126 ) , .Test_en_S_in ( p1477 ) , .Test_en_N_out ( SYNOPSYS_UNCONNECTED_2127 ) , .pReset_S_in ( SYNOPSYS_UNCONNECTED_2128 ) , .pReset_E_in ( SYNOPSYS_UNCONNECTED_2129 ) , .pReset_W_in ( pResetWires[53] ) , .pReset_N_out ( pResetWires[54] ) , .pReset_W_out ( SYNOPSYS_UNCONNECTED_2130 ) , - .pReset_E_out ( pResetWires[55] ) , .Reset_S_in ( p1086 ) , + .pReset_E_out ( pResetWires[55] ) , .Reset_S_in ( p1477 ) , .Reset_N_out ( SYNOPSYS_UNCONNECTED_2131 ) , - .prog_clk_0_N_in ( prog_clk_0_wires[369] ) , .prog_clk_3_S_in ( p1086 ) , - .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_2132 ) , .clk_3_S_in ( p1086 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[369] ) , .prog_clk_3_S_in ( p1084 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_2132 ) , .clk_3_S_in ( p1477 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_2133 ) ) ; sb_1__0_ sb_11__0_ ( .pReset ( { SYNOPSYS_UNCONNECTED_2134 } ) , @@ -109603,16 +114142,16 @@ sb_1__0_ sb_11__0_ ( .chanx_right_out ( sb_1__0__10_chanx_right_out ) , .chanx_left_out ( sb_1__0__10_chanx_left_out ) , .ccff_tail ( sb_1__0__10_ccff_tail ) , .SC_IN_TOP ( scff_Wires[291] ) , - .SC_OUT_TOP ( scff_Wires[292] ) , .Test_en_S_in ( p1368 ) , + .SC_OUT_TOP ( scff_Wires[292] ) , .Test_en_S_in ( p1374 ) , .Test_en_N_out ( SYNOPSYS_UNCONNECTED_2135 ) , .pReset_S_in ( SYNOPSYS_UNCONNECTED_2136 ) , .pReset_E_in ( SYNOPSYS_UNCONNECTED_2137 ) , .pReset_W_in ( pResetWires[56] ) , .pReset_N_out ( pResetWires[57] ) , .pReset_W_out ( SYNOPSYS_UNCONNECTED_2138 ) , - .pReset_E_out ( pResetWires[58] ) , .Reset_S_in ( p1368 ) , + .pReset_E_out ( pResetWires[58] ) , .Reset_S_in ( p1374 ) , .Reset_N_out ( SYNOPSYS_UNCONNECTED_2139 ) , - .prog_clk_0_N_in ( prog_clk_0_wires[407] ) , .prog_clk_3_S_in ( p1368 ) , - .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_2140 ) , .clk_3_S_in ( p1368 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[407] ) , .prog_clk_3_S_in ( p1374 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_2140 ) , .clk_3_S_in ( p1374 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_2141 ) ) ; sb_1__1_ sb_1__1_ ( .pReset ( { SYNOPSYS_UNCONNECTED_2142 } ) , @@ -109657,27 +114196,27 @@ sb_1__1_ sb_1__1_ ( .chanx_right_out ( sb_1__1__0_chanx_right_out ) , .chany_bottom_out ( sb_1__1__0_chany_bottom_out ) , .chanx_left_out ( sb_1__1__0_chanx_left_out ) , - .ccff_tail ( sb_1__1__0_ccff_tail ) , .Test_en_S_in ( p2487 ) , + .ccff_tail ( sb_1__1__0_ccff_tail ) , .Test_en_S_in ( p2787 ) , .Test_en_N_out ( SYNOPSYS_UNCONNECTED_2143 ) , .pReset_S_in ( SYNOPSYS_UNCONNECTED_2144 ) , .pReset_E_in ( pResetWires[66] ) , .pReset_W_in ( SYNOPSYS_UNCONNECTED_2145 ) , .pReset_N_out ( pResetWires[65] ) , .pReset_W_out ( pResetWires[62] ) , - .pReset_E_out ( SYNOPSYS_UNCONNECTED_2146 ) , .Reset_S_in ( p3360 ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_2146 ) , .Reset_S_in ( p2787 ) , .Reset_N_out ( SYNOPSYS_UNCONNECTED_2147 ) , .prog_clk_0_N_in ( prog_clk_0_wires[8] ) , .prog_clk_1_N_in ( prog_clk_2_wires[4] ) , .prog_clk_1_S_in ( SYNOPSYS_UNCONNECTED_2148 ) , .prog_clk_1_E_out ( prog_clk_1_wires[1] ) , - .prog_clk_1_W_out ( prog_clk_1_wires[2] ) , .prog_clk_2_N_in ( p3487 ) , - .prog_clk_2_E_in ( p1183 ) , .prog_clk_2_S_in ( p378 ) , - .prog_clk_2_W_in ( p1176 ) , + .prog_clk_1_W_out ( prog_clk_1_wires[2] ) , .prog_clk_2_N_in ( p3228 ) , + .prog_clk_2_E_in ( p437 ) , .prog_clk_2_S_in ( p76 ) , + .prog_clk_2_W_in ( p439 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_2149 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_2150 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_2151 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_2152 ) , - .prog_clk_3_W_in ( p2693 ) , .prog_clk_3_E_in ( p168 ) , - .prog_clk_3_S_in ( p1116 ) , .prog_clk_3_N_in ( p3483 ) , + .prog_clk_3_W_in ( p2990 ) , .prog_clk_3_E_in ( p674 ) , + .prog_clk_3_S_in ( p887 ) , .prog_clk_3_N_in ( p3191 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_2153 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_2154 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_2155 ) , @@ -109685,12 +114224,12 @@ sb_1__1_ sb_1__1_ ( .clk_1_N_in ( clk_2_wires[4] ) , .clk_1_S_in ( SYNOPSYS_UNCONNECTED_2157 ) , .clk_1_E_out ( clk_1_wires[1] ) , .clk_1_W_out ( clk_1_wires[2] ) , - .clk_2_N_in ( p3177 ) , .clk_2_E_in ( p986 ) , .clk_2_S_in ( p3340 ) , - .clk_2_W_in ( p2571 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_2158 ) , + .clk_2_N_in ( p3000 ) , .clk_2_E_in ( p117 ) , .clk_2_S_in ( p541 ) , + .clk_2_W_in ( p2868 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_2158 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_2159 ) , .clk_2_N_out ( SYNOPSYS_UNCONNECTED_2160 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_2161 ) , .clk_3_W_in ( p2693 ) , - .clk_3_E_in ( p858 ) , .clk_3_S_in ( p83 ) , .clk_3_N_in ( p3130 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_2161 ) , .clk_3_W_in ( p2975 ) , + .clk_3_E_in ( p962 ) , .clk_3_S_in ( p2672 ) , .clk_3_N_in ( p2922 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_2162 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_2163 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_2164 ) , @@ -109738,16 +114277,16 @@ sb_1__1_ sb_1__2_ ( .chanx_right_out ( sb_1__1__1_chanx_right_out ) , .chany_bottom_out ( sb_1__1__1_chany_bottom_out ) , .chanx_left_out ( sb_1__1__1_chanx_left_out ) , - .ccff_tail ( sb_1__1__1_ccff_tail ) , .Test_en_S_in ( p2944 ) , + .ccff_tail ( sb_1__1__1_ccff_tail ) , .Test_en_S_in ( p2997 ) , .Test_en_N_out ( SYNOPSYS_UNCONNECTED_2167 ) , .pReset_S_in ( SYNOPSYS_UNCONNECTED_2168 ) , .pReset_E_in ( pResetWires[115] ) , .pReset_W_in ( SYNOPSYS_UNCONNECTED_2169 ) , .pReset_N_out ( pResetWires[114] ) , .pReset_W_out ( pResetWires[111] ) , - .pReset_E_out ( SYNOPSYS_UNCONNECTED_2170 ) , .Reset_S_in ( p2944 ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_2170 ) , .Reset_S_in ( p2997 ) , .Reset_N_out ( SYNOPSYS_UNCONNECTED_2171 ) , - .prog_clk_0_N_in ( prog_clk_0_wires[13] ) , .prog_clk_1_N_in ( p1220 ) , - .prog_clk_1_S_in ( p383 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[13] ) , .prog_clk_1_N_in ( p1504 ) , + .prog_clk_1_S_in ( p519 ) , .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_2172 ) , .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_2173 ) , .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_2174 ) , @@ -109758,13 +114297,13 @@ sb_1__1_ sb_1__2_ ( .prog_clk_2_S_out ( prog_clk_2_wires[3] ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_2178 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_2179 ) , - .prog_clk_3_W_in ( p2150 ) , .prog_clk_3_E_in ( p238 ) , - .prog_clk_3_S_in ( p6 ) , .prog_clk_3_N_in ( p236 ) , + .prog_clk_3_W_in ( p1393 ) , .prog_clk_3_E_in ( p348 ) , + .prog_clk_3_S_in ( p545 ) , .prog_clk_3_N_in ( p114 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_2180 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_2181 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_2182 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_2183 ) , .clk_1_N_in ( p1220 ) , - .clk_1_S_in ( p106 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_2184 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_2183 ) , .clk_1_N_in ( p1504 ) , + .clk_1_S_in ( p1097 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_2184 ) , .clk_1_W_out ( SYNOPSYS_UNCONNECTED_2185 ) , .clk_2_N_in ( SYNOPSYS_UNCONNECTED_2186 ) , .clk_2_E_in ( clk_2_wires[1] ) , @@ -109773,8 +114312,8 @@ sb_1__1_ sb_1__2_ ( .clk_2_W_out ( SYNOPSYS_UNCONNECTED_2189 ) , .clk_2_S_out ( clk_2_wires[3] ) , .clk_2_N_out ( SYNOPSYS_UNCONNECTED_2190 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_2191 ) , .clk_3_W_in ( p2150 ) , - .clk_3_E_in ( p810 ) , .clk_3_S_in ( p2867 ) , .clk_3_N_in ( p625 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_2191 ) , .clk_3_W_in ( p1393 ) , + .clk_3_E_in ( p1748 ) , .clk_3_S_in ( p2876 ) , .clk_3_N_in ( p507 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_2192 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_2193 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_2194 ) , @@ -109822,27 +114361,27 @@ sb_1__1_ sb_1__3_ ( .chanx_right_out ( sb_1__1__2_chanx_right_out ) , .chany_bottom_out ( sb_1__1__2_chany_bottom_out ) , .chanx_left_out ( sb_1__1__2_chanx_left_out ) , - .ccff_tail ( sb_1__1__2_ccff_tail ) , .Test_en_S_in ( p3357 ) , + .ccff_tail ( sb_1__1__2_ccff_tail ) , .Test_en_S_in ( p1444 ) , .Test_en_N_out ( SYNOPSYS_UNCONNECTED_2197 ) , .pReset_S_in ( SYNOPSYS_UNCONNECTED_2198 ) , .pReset_E_in ( pResetWires[164] ) , .pReset_W_in ( SYNOPSYS_UNCONNECTED_2199 ) , .pReset_N_out ( pResetWires[163] ) , .pReset_W_out ( pResetWires[160] ) , - .pReset_E_out ( SYNOPSYS_UNCONNECTED_2200 ) , .Reset_S_in ( p3408 ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_2200 ) , .Reset_S_in ( p1444 ) , .Reset_N_out ( SYNOPSYS_UNCONNECTED_2201 ) , .prog_clk_0_N_in ( prog_clk_0_wires[18] ) , .prog_clk_1_N_in ( prog_clk_2_wires[11] ) , .prog_clk_1_S_in ( SYNOPSYS_UNCONNECTED_2202 ) , .prog_clk_1_E_out ( prog_clk_1_wires[8] ) , - .prog_clk_1_W_out ( prog_clk_1_wires[9] ) , .prog_clk_2_N_in ( p3466 ) , - .prog_clk_2_E_in ( p720 ) , .prog_clk_2_S_in ( p140 ) , - .prog_clk_2_W_in ( p264 ) , + .prog_clk_1_W_out ( prog_clk_1_wires[9] ) , .prog_clk_2_N_in ( p3553 ) , + .prog_clk_2_E_in ( p665 ) , .prog_clk_2_S_in ( p657 ) , + .prog_clk_2_W_in ( p884 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_2203 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_2204 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_2205 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_2206 ) , - .prog_clk_3_W_in ( p2239 ) , .prog_clk_3_E_in ( p279 ) , - .prog_clk_3_S_in ( p808 ) , .prog_clk_3_N_in ( p3461 ) , + .prog_clk_3_W_in ( p3016 ) , .prog_clk_3_E_in ( p627 ) , + .prog_clk_3_S_in ( p1233 ) , .prog_clk_3_N_in ( p3547 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_2207 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_2208 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_2209 ) , @@ -109850,12 +114389,12 @@ sb_1__1_ sb_1__3_ ( .clk_1_N_in ( clk_2_wires[11] ) , .clk_1_S_in ( SYNOPSYS_UNCONNECTED_2211 ) , .clk_1_E_out ( clk_1_wires[8] ) , .clk_1_W_out ( clk_1_wires[9] ) , - .clk_2_N_in ( p3358 ) , .clk_2_E_in ( p984 ) , .clk_2_S_in ( p3391 ) , - .clk_2_W_in ( p2043 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_2212 ) , + .clk_2_N_in ( p3270 ) , .clk_2_E_in ( p86 ) , .clk_2_S_in ( p1148 ) , + .clk_2_W_in ( p2902 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_2212 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_2213 ) , .clk_2_N_out ( SYNOPSYS_UNCONNECTED_2214 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_2215 ) , .clk_3_W_in ( p2239 ) , - .clk_3_E_in ( p796 ) , .clk_3_S_in ( p384 ) , .clk_3_N_in ( p3354 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_2215 ) , .clk_3_W_in ( p2543 ) , + .clk_3_E_in ( p1069 ) , .clk_3_S_in ( p286 ) , .clk_3_N_in ( p3176 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_2216 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_2217 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_2218 ) , @@ -109903,16 +114442,16 @@ sb_1__1_ sb_1__4_ ( .chanx_right_out ( sb_1__1__3_chanx_right_out ) , .chany_bottom_out ( sb_1__1__3_chany_bottom_out ) , .chanx_left_out ( sb_1__1__3_chanx_left_out ) , - .ccff_tail ( sb_1__1__3_ccff_tail ) , .Test_en_S_in ( p2972 ) , + .ccff_tail ( sb_1__1__3_ccff_tail ) , .Test_en_S_in ( p1966 ) , .Test_en_N_out ( SYNOPSYS_UNCONNECTED_2221 ) , .pReset_S_in ( SYNOPSYS_UNCONNECTED_2222 ) , .pReset_E_in ( pResetWires[213] ) , .pReset_W_in ( SYNOPSYS_UNCONNECTED_2223 ) , .pReset_N_out ( pResetWires[212] ) , .pReset_W_out ( pResetWires[209] ) , - .pReset_E_out ( SYNOPSYS_UNCONNECTED_2224 ) , .Reset_S_in ( p2972 ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_2224 ) , .Reset_S_in ( p1966 ) , .Reset_N_out ( SYNOPSYS_UNCONNECTED_2225 ) , - .prog_clk_0_N_in ( prog_clk_0_wires[23] ) , .prog_clk_1_N_in ( p1431 ) , - .prog_clk_1_S_in ( p222 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[23] ) , .prog_clk_1_N_in ( p1908 ) , + .prog_clk_1_S_in ( p177 ) , .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_2226 ) , .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_2227 ) , .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_2228 ) , @@ -109923,13 +114462,13 @@ sb_1__1_ sb_1__4_ ( .prog_clk_2_S_out ( prog_clk_2_wires[10] ) , .prog_clk_2_N_out ( prog_clk_2_wires[8] ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_2232 ) , - .prog_clk_3_W_in ( p2227 ) , .prog_clk_3_E_in ( p1192 ) , - .prog_clk_3_S_in ( p590 ) , .prog_clk_3_N_in ( p1671 ) , + .prog_clk_3_W_in ( p1971 ) , .prog_clk_3_E_in ( p855 ) , + .prog_clk_3_S_in ( p868 ) , .prog_clk_3_N_in ( p2089 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_2233 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_2234 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_2235 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_2236 ) , .clk_1_N_in ( p1431 ) , - .clk_1_S_in ( p498 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_2237 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_2236 ) , .clk_1_N_in ( p1908 ) , + .clk_1_S_in ( p1063 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_2237 ) , .clk_1_W_out ( SYNOPSYS_UNCONNECTED_2238 ) , .clk_2_N_in ( SYNOPSYS_UNCONNECTED_2239 ) , .clk_2_E_in ( clk_2_wires[6] ) , @@ -109937,8 +114476,8 @@ sb_1__1_ sb_1__4_ ( .clk_2_W_in ( SYNOPSYS_UNCONNECTED_2241 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_2242 ) , .clk_2_S_out ( clk_2_wires[10] ) , .clk_2_N_out ( clk_2_wires[8] ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_2243 ) , .clk_3_W_in ( p2227 ) , - .clk_3_E_in ( p1676 ) , .clk_3_S_in ( p2883 ) , .clk_3_N_in ( p353 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_2243 ) , .clk_3_W_in ( p1971 ) , + .clk_3_E_in ( p136 ) , .clk_3_S_in ( p1738 ) , .clk_3_N_in ( p1783 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_2244 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_2245 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_2246 ) , @@ -109986,40 +114525,40 @@ sb_1__1_ sb_1__5_ ( .chanx_right_out ( sb_1__1__4_chanx_right_out ) , .chany_bottom_out ( sb_1__1__4_chany_bottom_out ) , .chanx_left_out ( sb_1__1__4_chanx_left_out ) , - .ccff_tail ( sb_1__1__4_ccff_tail ) , .Test_en_S_in ( p2645 ) , + .ccff_tail ( sb_1__1__4_ccff_tail ) , .Test_en_S_in ( p1909 ) , .Test_en_N_out ( SYNOPSYS_UNCONNECTED_2249 ) , .pReset_S_in ( SYNOPSYS_UNCONNECTED_2250 ) , .pReset_E_in ( pResetWires[262] ) , .pReset_W_in ( SYNOPSYS_UNCONNECTED_2251 ) , .pReset_N_out ( pResetWires[261] ) , .pReset_W_out ( pResetWires[258] ) , - .pReset_E_out ( SYNOPSYS_UNCONNECTED_2252 ) , .Reset_S_in ( p3168 ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_2252 ) , .Reset_S_in ( p1909 ) , .Reset_N_out ( SYNOPSYS_UNCONNECTED_2253 ) , .prog_clk_0_N_in ( prog_clk_0_wires[28] ) , .prog_clk_1_N_in ( SYNOPSYS_UNCONNECTED_2254 ) , .prog_clk_1_S_in ( prog_clk_2_wires[9] ) , .prog_clk_1_E_out ( prog_clk_1_wires[15] ) , - .prog_clk_1_W_out ( prog_clk_1_wires[16] ) , .prog_clk_2_N_in ( p3432 ) , - .prog_clk_2_E_in ( p131 ) , .prog_clk_2_S_in ( p619 ) , - .prog_clk_2_W_in ( p990 ) , + .prog_clk_1_W_out ( prog_clk_1_wires[16] ) , .prog_clk_2_N_in ( p3577 ) , + .prog_clk_2_E_in ( p534 ) , .prog_clk_2_S_in ( p748 ) , + .prog_clk_2_W_in ( p516 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_2255 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_2256 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_2257 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_2258 ) , - .prog_clk_3_W_in ( p2226 ) , .prog_clk_3_E_in ( p1251 ) , - .prog_clk_3_S_in ( p1138 ) , .prog_clk_3_N_in ( p3418 ) , + .prog_clk_3_W_in ( p2793 ) , .prog_clk_3_E_in ( p210 ) , + .prog_clk_3_S_in ( p1120 ) , .prog_clk_3_N_in ( p3564 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_2259 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_2260 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_2261 ) , .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_2262 ) , .clk_1_N_in ( SYNOPSYS_UNCONNECTED_2263 ) , .clk_1_S_in ( clk_2_wires[9] ) , .clk_1_E_out ( clk_1_wires[15] ) , - .clk_1_W_out ( clk_1_wires[16] ) , .clk_2_N_in ( p3359 ) , - .clk_2_E_in ( p786 ) , .clk_2_S_in ( p3131 ) , .clk_2_W_in ( p1971 ) , + .clk_1_W_out ( clk_1_wires[16] ) , .clk_2_N_in ( p3134 ) , + .clk_2_E_in ( p585 ) , .clk_2_S_in ( p669 ) , .clk_2_W_in ( p3174 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_2264 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_2265 ) , .clk_2_N_out ( SYNOPSYS_UNCONNECTED_2266 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_2267 ) , .clk_3_W_in ( p2226 ) , - .clk_3_E_in ( p819 ) , .clk_3_S_in ( p552 ) , .clk_3_N_in ( p3351 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_2267 ) , .clk_3_W_in ( p3260 ) , + .clk_3_E_in ( p1062 ) , .clk_3_S_in ( p1697 ) , .clk_3_N_in ( p3091 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_2268 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_2269 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_2270 ) , @@ -110067,38 +114606,38 @@ sb_1__1_ sb_1__6_ ( .chanx_right_out ( sb_1__1__5_chanx_right_out ) , .chany_bottom_out ( sb_1__1__5_chany_bottom_out ) , .chanx_left_out ( sb_1__1__5_chanx_left_out ) , - .ccff_tail ( sb_1__1__5_ccff_tail ) , .Test_en_S_in ( p2476 ) , + .ccff_tail ( sb_1__1__5_ccff_tail ) , .Test_en_S_in ( p1849 ) , .Test_en_N_out ( SYNOPSYS_UNCONNECTED_2273 ) , .pReset_S_in ( SYNOPSYS_UNCONNECTED_2274 ) , .pReset_E_in ( pResetWires[311] ) , .pReset_W_in ( SYNOPSYS_UNCONNECTED_2275 ) , .pReset_N_out ( pResetWires[310] ) , .pReset_W_out ( pResetWires[307] ) , - .pReset_E_out ( SYNOPSYS_UNCONNECTED_2276 ) , .Reset_S_in ( p3453 ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_2276 ) , .Reset_S_in ( p1849 ) , .Reset_N_out ( SYNOPSYS_UNCONNECTED_2277 ) , - .prog_clk_0_N_in ( prog_clk_0_wires[33] ) , .prog_clk_1_N_in ( p1382 ) , - .prog_clk_1_S_in ( p924 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[33] ) , .prog_clk_1_N_in ( p2245 ) , + .prog_clk_1_S_in ( p300 ) , .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_2278 ) , .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_2279 ) , - .prog_clk_2_N_in ( p3467 ) , .prog_clk_2_E_in ( p1064 ) , - .prog_clk_2_S_in ( p1163 ) , .prog_clk_2_W_in ( p78 ) , + .prog_clk_2_N_in ( p1629 ) , .prog_clk_2_E_in ( p787 ) , + .prog_clk_2_S_in ( p23 ) , .prog_clk_2_W_in ( p142 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_2280 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_2281 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_2282 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_2283 ) , - .prog_clk_3_W_in ( p1836 ) , .prog_clk_3_E_in ( p181 ) , - .prog_clk_3_S_in ( p486 ) , .prog_clk_3_N_in ( p3458 ) , + .prog_clk_3_W_in ( p3355 ) , .prog_clk_3_E_in ( p968 ) , + .prog_clk_3_S_in ( p857 ) , .prog_clk_3_N_in ( p781 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_2284 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_2285 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_2286 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_2287 ) , .clk_1_N_in ( p1382 ) , - .clk_1_S_in ( p656 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_2288 ) , - .clk_1_W_out ( SYNOPSYS_UNCONNECTED_2289 ) , .clk_2_N_in ( p3110 ) , - .clk_2_E_in ( p840 ) , .clk_2_S_in ( p3445 ) , .clk_2_W_in ( p1703 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_2287 ) , .clk_1_N_in ( p2245 ) , + .clk_1_S_in ( p998 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_2288 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_2289 ) , .clk_2_N_in ( p3514 ) , + .clk_2_E_in ( p1152 ) , .clk_2_S_in ( p242 ) , .clk_2_W_in ( p3488 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_2290 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_2291 ) , .clk_2_N_out ( SYNOPSYS_UNCONNECTED_2292 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_2293 ) , .clk_3_W_in ( p1836 ) , - .clk_3_E_in ( p861 ) , .clk_3_S_in ( p1465 ) , .clk_3_N_in ( p3017 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_2293 ) , .clk_3_W_in ( p3501 ) , + .clk_3_E_in ( p81 ) , .clk_3_S_in ( p1765 ) , .clk_3_N_in ( p3492 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_2294 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_2295 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_2296 ) , @@ -110146,27 +114685,27 @@ sb_1__1_ sb_1__7_ ( .chanx_right_out ( sb_1__1__6_chanx_right_out ) , .chany_bottom_out ( sb_1__1__6_chany_bottom_out ) , .chanx_left_out ( sb_1__1__6_chanx_left_out ) , - .ccff_tail ( sb_1__1__6_ccff_tail ) , .Test_en_S_in ( p2928 ) , + .ccff_tail ( sb_1__1__6_ccff_tail ) , .Test_en_S_in ( p2195 ) , .Test_en_N_out ( SYNOPSYS_UNCONNECTED_2299 ) , .pReset_S_in ( SYNOPSYS_UNCONNECTED_2300 ) , .pReset_E_in ( pResetWires[360] ) , .pReset_W_in ( SYNOPSYS_UNCONNECTED_2301 ) , .pReset_N_out ( pResetWires[359] ) , .pReset_W_out ( pResetWires[356] ) , - .pReset_E_out ( SYNOPSYS_UNCONNECTED_2302 ) , .Reset_S_in ( p3318 ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_2302 ) , .Reset_S_in ( p2195 ) , .Reset_N_out ( SYNOPSYS_UNCONNECTED_2303 ) , .prog_clk_0_N_in ( prog_clk_0_wires[38] ) , .prog_clk_1_N_in ( prog_clk_2_wires[18] ) , .prog_clk_1_S_in ( SYNOPSYS_UNCONNECTED_2304 ) , .prog_clk_1_E_out ( prog_clk_1_wires[22] ) , - .prog_clk_1_W_out ( prog_clk_1_wires[23] ) , .prog_clk_2_N_in ( p3272 ) , - .prog_clk_2_E_in ( p944 ) , .prog_clk_2_S_in ( p23 ) , - .prog_clk_2_W_in ( p1226 ) , + .prog_clk_1_W_out ( prog_clk_1_wires[23] ) , .prog_clk_2_N_in ( p3408 ) , + .prog_clk_2_E_in ( p694 ) , .prog_clk_2_S_in ( p281 ) , + .prog_clk_2_W_in ( p850 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_2305 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_2306 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_2307 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_2308 ) , - .prog_clk_3_W_in ( p2515 ) , .prog_clk_3_E_in ( p313 ) , - .prog_clk_3_S_in ( p1221 ) , .prog_clk_3_N_in ( p3214 ) , + .prog_clk_3_W_in ( p2587 ) , .prog_clk_3_E_in ( p59 ) , + .prog_clk_3_S_in ( p902 ) , .prog_clk_3_N_in ( p3372 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_2309 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_2310 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_2311 ) , @@ -110174,12 +114713,12 @@ sb_1__1_ sb_1__7_ ( .clk_1_N_in ( clk_2_wires[18] ) , .clk_1_S_in ( SYNOPSYS_UNCONNECTED_2313 ) , .clk_1_E_out ( clk_1_wires[22] ) , .clk_1_W_out ( clk_1_wires[23] ) , - .clk_2_N_in ( p3264 ) , .clk_2_E_in ( p291 ) , .clk_2_S_in ( p3285 ) , - .clk_2_W_in ( p2330 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_2314 ) , + .clk_2_N_in ( p2812 ) , .clk_2_E_in ( p992 ) , .clk_2_S_in ( p479 ) , + .clk_2_W_in ( p3520 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_2314 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_2315 ) , .clk_2_N_out ( SYNOPSYS_UNCONNECTED_2316 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_2317 ) , .clk_3_W_in ( p2515 ) , - .clk_3_E_in ( p925 ) , .clk_3_S_in ( p454 ) , .clk_3_N_in ( p3235 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_2317 ) , .clk_3_W_in ( p3529 ) , + .clk_3_E_in ( p786 ) , .clk_3_S_in ( p2106 ) , .clk_3_N_in ( p2702 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_2318 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_2319 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_2320 ) , @@ -110227,16 +114766,16 @@ sb_1__1_ sb_1__8_ ( .chanx_right_out ( sb_1__1__7_chanx_right_out ) , .chany_bottom_out ( sb_1__1__7_chany_bottom_out ) , .chanx_left_out ( sb_1__1__7_chanx_left_out ) , - .ccff_tail ( sb_1__1__7_ccff_tail ) , .Test_en_S_in ( p3241 ) , + .ccff_tail ( sb_1__1__7_ccff_tail ) , .Test_en_S_in ( p2285 ) , .Test_en_N_out ( SYNOPSYS_UNCONNECTED_2323 ) , .pReset_S_in ( SYNOPSYS_UNCONNECTED_2324 ) , .pReset_E_in ( pResetWires[409] ) , .pReset_W_in ( SYNOPSYS_UNCONNECTED_2325 ) , .pReset_N_out ( pResetWires[408] ) , .pReset_W_out ( pResetWires[405] ) , - .pReset_E_out ( SYNOPSYS_UNCONNECTED_2326 ) , .Reset_S_in ( p3241 ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_2326 ) , .Reset_S_in ( p2285 ) , .Reset_N_out ( SYNOPSYS_UNCONNECTED_2327 ) , - .prog_clk_0_N_in ( prog_clk_0_wires[43] ) , .prog_clk_1_N_in ( p2138 ) , - .prog_clk_1_S_in ( p61 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[43] ) , .prog_clk_1_N_in ( p1503 ) , + .prog_clk_1_S_in ( p62 ) , .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_2328 ) , .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_2329 ) , .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_2330 ) , @@ -110247,13 +114786,13 @@ sb_1__1_ sb_1__8_ ( .prog_clk_2_S_out ( prog_clk_2_wires[17] ) , .prog_clk_2_N_out ( prog_clk_2_wires[15] ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_2334 ) , - .prog_clk_3_W_in ( p1190 ) , .prog_clk_3_E_in ( p234 ) , - .prog_clk_3_S_in ( p290 ) , .prog_clk_3_N_in ( p1647 ) , + .prog_clk_3_W_in ( p1628 ) , .prog_clk_3_E_in ( p187 ) , + .prog_clk_3_S_in ( p49 ) , .prog_clk_3_N_in ( p403 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_2335 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_2336 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_2337 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_2338 ) , .clk_1_N_in ( p2138 ) , - .clk_1_S_in ( p794 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_2339 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_2338 ) , .clk_1_N_in ( p1503 ) , + .clk_1_S_in ( p976 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_2339 ) , .clk_1_W_out ( SYNOPSYS_UNCONNECTED_2340 ) , .clk_2_N_in ( SYNOPSYS_UNCONNECTED_2341 ) , .clk_2_E_in ( clk_2_wires[13] ) , @@ -110261,8 +114800,8 @@ sb_1__1_ sb_1__8_ ( .clk_2_W_in ( SYNOPSYS_UNCONNECTED_2343 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_2344 ) , .clk_2_S_out ( clk_2_wires[17] ) , .clk_2_N_out ( clk_2_wires[15] ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_2345 ) , .clk_3_W_in ( p1190 ) , - .clk_3_E_in ( p1629 ) , .clk_3_S_in ( p3229 ) , .clk_3_N_in ( p1977 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_2345 ) , .clk_3_W_in ( p1628 ) , + .clk_3_E_in ( p825 ) , .clk_3_S_in ( p2093 ) , .clk_3_N_in ( p118 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_2346 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_2347 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_2348 ) , @@ -110310,40 +114849,40 @@ sb_1__1_ sb_1__9_ ( .chanx_right_out ( sb_1__1__8_chanx_right_out ) , .chany_bottom_out ( sb_1__1__8_chany_bottom_out ) , .chanx_left_out ( sb_1__1__8_chanx_left_out ) , - .ccff_tail ( sb_1__1__8_ccff_tail ) , .Test_en_S_in ( p3251 ) , + .ccff_tail ( sb_1__1__8_ccff_tail ) , .Test_en_S_in ( p2297 ) , .Test_en_N_out ( SYNOPSYS_UNCONNECTED_2351 ) , .pReset_S_in ( SYNOPSYS_UNCONNECTED_2352 ) , .pReset_E_in ( pResetWires[458] ) , .pReset_W_in ( SYNOPSYS_UNCONNECTED_2353 ) , .pReset_N_out ( pResetWires[457] ) , .pReset_W_out ( pResetWires[454] ) , - .pReset_E_out ( SYNOPSYS_UNCONNECTED_2354 ) , .Reset_S_in ( p3316 ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_2354 ) , .Reset_S_in ( p2297 ) , .Reset_N_out ( SYNOPSYS_UNCONNECTED_2355 ) , .prog_clk_0_N_in ( prog_clk_0_wires[48] ) , .prog_clk_1_N_in ( SYNOPSYS_UNCONNECTED_2356 ) , .prog_clk_1_S_in ( prog_clk_2_wires[16] ) , .prog_clk_1_E_out ( prog_clk_1_wires[29] ) , - .prog_clk_1_W_out ( prog_clk_1_wires[30] ) , .prog_clk_2_N_in ( p3074 ) , - .prog_clk_2_E_in ( p866 ) , .prog_clk_2_S_in ( p412 ) , - .prog_clk_2_W_in ( p1073 ) , + .prog_clk_1_W_out ( prog_clk_1_wires[30] ) , .prog_clk_2_N_in ( p3425 ) , + .prog_clk_2_E_in ( p422 ) , .prog_clk_2_S_in ( p594 ) , + .prog_clk_2_W_in ( p795 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_2357 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_2358 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_2359 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_2360 ) , - .prog_clk_3_W_in ( p2242 ) , .prog_clk_3_E_in ( p1030 ) , - .prog_clk_3_S_in ( p803 ) , .prog_clk_3_N_in ( p3023 ) , + .prog_clk_3_W_in ( p3004 ) , .prog_clk_3_E_in ( p1022 ) , + .prog_clk_3_S_in ( p573 ) , .prog_clk_3_N_in ( p3370 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_2361 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_2362 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_2363 ) , .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_2364 ) , .clk_1_N_in ( SYNOPSYS_UNCONNECTED_2365 ) , .clk_1_S_in ( clk_2_wires[16] ) , .clk_1_E_out ( clk_1_wires[29] ) , - .clk_1_W_out ( clk_1_wires[30] ) , .clk_2_N_in ( p2652 ) , - .clk_2_E_in ( p51 ) , .clk_2_S_in ( p3277 ) , .clk_2_W_in ( p1984 ) , + .clk_1_W_out ( clk_1_wires[30] ) , .clk_2_N_in ( p3598 ) , + .clk_2_E_in ( p1053 ) , .clk_2_S_in ( p279 ) , .clk_2_W_in ( p3611 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_2366 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_2367 ) , .clk_2_N_out ( SYNOPSYS_UNCONNECTED_2368 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_2369 ) , .clk_3_W_in ( p2242 ) , - .clk_3_E_in ( p671 ) , .clk_3_S_in ( p189 ) , .clk_3_N_in ( p2587 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_2369 ) , .clk_3_W_in ( p3613 ) , + .clk_3_E_in ( p273 ) , .clk_3_S_in ( p2091 ) , .clk_3_N_in ( p3593 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_2370 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_2371 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_2372 ) , @@ -110391,16 +114930,16 @@ sb_1__1_ sb_1__10_ ( .chanx_right_out ( sb_1__1__9_chanx_right_out ) , .chany_bottom_out ( sb_1__1__9_chany_bottom_out ) , .chanx_left_out ( sb_1__1__9_chanx_left_out ) , - .ccff_tail ( sb_1__1__9_ccff_tail ) , .Test_en_S_in ( p2650 ) , + .ccff_tail ( sb_1__1__9_ccff_tail ) , .Test_en_S_in ( p2504 ) , .Test_en_N_out ( SYNOPSYS_UNCONNECTED_2375 ) , .pReset_S_in ( SYNOPSYS_UNCONNECTED_2376 ) , .pReset_E_in ( pResetWires[507] ) , .pReset_W_in ( SYNOPSYS_UNCONNECTED_2377 ) , .pReset_N_out ( pResetWires[506] ) , .pReset_W_out ( pResetWires[503] ) , - .pReset_E_out ( SYNOPSYS_UNCONNECTED_2378 ) , .Reset_S_in ( p2650 ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_2378 ) , .Reset_S_in ( p2504 ) , .Reset_N_out ( SYNOPSYS_UNCONNECTED_2379 ) , - .prog_clk_0_N_in ( prog_clk_0_wires[53] ) , .prog_clk_1_N_in ( p1361 ) , - .prog_clk_1_S_in ( p869 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[53] ) , .prog_clk_1_N_in ( p1542 ) , + .prog_clk_1_S_in ( p880 ) , .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_2380 ) , .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_2381 ) , .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_2382 ) , @@ -110411,13 +114950,13 @@ sb_1__1_ sb_1__10_ ( .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_2386 ) , .prog_clk_2_N_out ( prog_clk_2_wires[22] ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_2387 ) , - .prog_clk_3_W_in ( p1476 ) , .prog_clk_3_E_in ( p348 ) , - .prog_clk_3_S_in ( p136 ) , .prog_clk_3_N_in ( p1637 ) , + .prog_clk_3_W_in ( p2351 ) , .prog_clk_3_E_in ( p799 ) , + .prog_clk_3_S_in ( p78 ) , .prog_clk_3_N_in ( p85 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_2388 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_2389 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_2390 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_2391 ) , .clk_1_N_in ( p1361 ) , - .clk_1_S_in ( p485 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_2392 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_2391 ) , .clk_1_N_in ( p1542 ) , + .clk_1_S_in ( p243 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_2392 ) , .clk_1_W_out ( SYNOPSYS_UNCONNECTED_2393 ) , .clk_2_N_in ( SYNOPSYS_UNCONNECTED_2394 ) , .clk_2_E_in ( clk_2_wires[20] ) , @@ -110426,8 +114965,8 @@ sb_1__1_ sb_1__10_ ( .clk_2_W_out ( SYNOPSYS_UNCONNECTED_2397 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_2398 ) , .clk_2_N_out ( clk_2_wires[22] ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_2399 ) , .clk_3_W_in ( p1476 ) , - .clk_3_E_in ( p795 ) , .clk_3_S_in ( p2577 ) , .clk_3_N_in ( p114 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_2399 ) , .clk_3_W_in ( p2351 ) , + .clk_3_E_in ( p127 ) , .clk_3_S_in ( p2443 ) , .clk_3_N_in ( p483 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_2400 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_2401 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_2402 ) , @@ -110475,40 +115014,40 @@ sb_1__1_ sb_1__11_ ( .chanx_right_out ( sb_1__1__10_chanx_right_out ) , .chany_bottom_out ( sb_1__1__10_chany_bottom_out ) , .chanx_left_out ( sb_1__1__10_chanx_left_out ) , - .ccff_tail ( sb_1__1__10_ccff_tail ) , .Test_en_S_in ( p3162 ) , + .ccff_tail ( sb_1__1__10_ccff_tail ) , .Test_en_S_in ( p2043 ) , .Test_en_N_out ( SYNOPSYS_UNCONNECTED_2405 ) , .pReset_S_in ( SYNOPSYS_UNCONNECTED_2406 ) , .pReset_E_in ( pResetWires[556] ) , .pReset_W_in ( SYNOPSYS_UNCONNECTED_2407 ) , .pReset_N_out ( pResetWires[555] ) , .pReset_W_out ( pResetWires[552] ) , - .pReset_E_out ( SYNOPSYS_UNCONNECTED_2408 ) , .Reset_S_in ( p3162 ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_2408 ) , .Reset_S_in ( p2043 ) , .Reset_N_out ( SYNOPSYS_UNCONNECTED_2409 ) , .prog_clk_0_N_in ( prog_clk_0_wires[58] ) , .prog_clk_1_N_in ( SYNOPSYS_UNCONNECTED_2410 ) , .prog_clk_1_S_in ( prog_clk_2_wires[23] ) , .prog_clk_1_E_out ( prog_clk_1_wires[36] ) , - .prog_clk_1_W_out ( prog_clk_1_wires[37] ) , .prog_clk_2_N_in ( p3456 ) , - .prog_clk_2_E_in ( p774 ) , .prog_clk_2_S_in ( p479 ) , - .prog_clk_2_W_in ( p8 ) , + .prog_clk_1_W_out ( prog_clk_1_wires[37] ) , .prog_clk_2_N_in ( p3585 ) , + .prog_clk_2_E_in ( p800 ) , .prog_clk_2_S_in ( p765 ) , + .prog_clk_2_W_in ( p150 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_2411 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_2412 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_2413 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_2414 ) , - .prog_clk_3_W_in ( p2494 ) , .prog_clk_3_E_in ( p1101 ) , - .prog_clk_3_S_in ( p1308 ) , .prog_clk_3_N_in ( p3444 ) , + .prog_clk_3_W_in ( p2638 ) , .prog_clk_3_E_in ( p8 ) , + .prog_clk_3_S_in ( p1200 ) , .prog_clk_3_N_in ( p3580 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_2415 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_2416 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_2417 ) , .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_2418 ) , .clk_1_N_in ( SYNOPSYS_UNCONNECTED_2419 ) , .clk_1_S_in ( clk_2_wires[23] ) , .clk_1_E_out ( clk_1_wires[36] ) , - .clk_1_W_out ( clk_1_wires[37] ) , .clk_2_N_in ( p2982 ) , - .clk_2_E_in ( p1194 ) , .clk_2_S_in ( p3132 ) , .clk_2_W_in ( p2288 ) , + .clk_1_W_out ( clk_1_wires[37] ) , .clk_2_N_in ( p3415 ) , + .clk_2_E_in ( p542 ) , .clk_2_S_in ( p1176 ) , .clk_2_W_in ( p2707 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_2420 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_2421 ) , .clk_2_N_out ( SYNOPSYS_UNCONNECTED_2422 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_2423 ) , .clk_3_W_in ( p2494 ) , - .clk_3_E_in ( p112 ) , .clk_3_S_in ( p1312 ) , .clk_3_N_in ( p2919 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_2423 ) , .clk_3_W_in ( p2856 ) , + .clk_3_E_in ( p828 ) , .clk_3_S_in ( p1699 ) , .clk_3_N_in ( p3374 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_2424 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_2425 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_2426 ) , @@ -110556,38 +115095,38 @@ sb_1__1_ sb_2__1_ ( .chanx_right_out ( sb_1__1__11_chanx_right_out ) , .chany_bottom_out ( sb_1__1__11_chany_bottom_out ) , .chanx_left_out ( sb_1__1__11_chanx_left_out ) , - .ccff_tail ( sb_1__1__11_ccff_tail ) , .Test_en_S_in ( p2659 ) , + .ccff_tail ( sb_1__1__11_ccff_tail ) , .Test_en_S_in ( p1654 ) , .Test_en_N_out ( SYNOPSYS_UNCONNECTED_2429 ) , .pReset_S_in ( SYNOPSYS_UNCONNECTED_2430 ) , .pReset_E_in ( pResetWires[70] ) , .pReset_W_in ( SYNOPSYS_UNCONNECTED_2431 ) , .pReset_N_out ( pResetWires[69] ) , .pReset_W_out ( pResetWires[67] ) , - .pReset_E_out ( SYNOPSYS_UNCONNECTED_2432 ) , .Reset_S_in ( p3267 ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_2432 ) , .Reset_S_in ( p1654 ) , .Reset_N_out ( SYNOPSYS_UNCONNECTED_2433 ) , - .prog_clk_0_N_in ( prog_clk_0_wires[68] ) , .prog_clk_1_N_in ( p1791 ) , - .prog_clk_1_S_in ( p836 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[68] ) , .prog_clk_1_N_in ( p1582 ) , + .prog_clk_1_S_in ( p60 ) , .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_2434 ) , .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_2435 ) , - .prog_clk_2_N_in ( p2258 ) , .prog_clk_2_E_in ( p877 ) , - .prog_clk_2_S_in ( p442 ) , .prog_clk_2_W_in ( p1214 ) , + .prog_clk_2_N_in ( p3410 ) , .prog_clk_2_E_in ( p290 ) , + .prog_clk_2_S_in ( p227 ) , .prog_clk_2_W_in ( p626 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_2436 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_2437 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_2438 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_2439 ) , - .prog_clk_3_W_in ( p2093 ) , .prog_clk_3_E_in ( p1218 ) , - .prog_clk_3_S_in ( p1124 ) , .prog_clk_3_N_in ( p1998 ) , + .prog_clk_3_W_in ( p2209 ) , .prog_clk_3_E_in ( p1123 ) , + .prog_clk_3_S_in ( p1146 ) , .prog_clk_3_N_in ( p3375 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_2440 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_2441 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_2442 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_2443 ) , .clk_1_N_in ( p1791 ) , - .clk_1_S_in ( p223 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_2444 ) , - .clk_1_W_out ( SYNOPSYS_UNCONNECTED_2445 ) , .clk_2_N_in ( p2702 ) , - .clk_2_E_in ( p129 ) , .clk_2_S_in ( p3209 ) , .clk_2_W_in ( p2036 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_2443 ) , .clk_1_N_in ( p1582 ) , + .clk_1_S_in ( p1101 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_2444 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_2445 ) , .clk_2_N_in ( p3513 ) , + .clk_2_E_in ( p33 ) , .clk_2_S_in ( p1095 ) , .clk_2_W_in ( p3612 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_2446 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_2447 ) , .clk_2_N_out ( SYNOPSYS_UNCONNECTED_2448 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_2449 ) , .clk_3_W_in ( p2093 ) , - .clk_3_E_in ( p634 ) , .clk_3_S_in ( p1082 ) , .clk_3_N_in ( p2555 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_2449 ) , .clk_3_W_in ( p3614 ) , + .clk_3_E_in ( p1079 ) , .clk_3_S_in ( p319 ) , .clk_3_N_in ( p3487 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_2450 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_2451 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_2452 ) , @@ -110635,16 +115174,16 @@ sb_1__1_ sb_2__2_ ( .chanx_right_out ( sb_1__1__12_chanx_right_out ) , .chany_bottom_out ( sb_1__1__12_chany_bottom_out ) , .chanx_left_out ( sb_1__1__12_chanx_left_out ) , - .ccff_tail ( sb_1__1__12_ccff_tail ) , .Test_en_S_in ( p2619 ) , + .ccff_tail ( sb_1__1__12_ccff_tail ) , .Test_en_S_in ( p1316 ) , .Test_en_N_out ( SYNOPSYS_UNCONNECTED_2455 ) , .pReset_S_in ( SYNOPSYS_UNCONNECTED_2456 ) , .pReset_E_in ( pResetWires[119] ) , .pReset_W_in ( SYNOPSYS_UNCONNECTED_2457 ) , .pReset_N_out ( pResetWires[118] ) , .pReset_W_out ( pResetWires[116] ) , - .pReset_E_out ( SYNOPSYS_UNCONNECTED_2458 ) , .Reset_S_in ( p2619 ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_2458 ) , .Reset_S_in ( p1316 ) , .Reset_N_out ( SYNOPSYS_UNCONNECTED_2459 ) , - .prog_clk_0_N_in ( prog_clk_0_wires[71] ) , .prog_clk_1_N_in ( p1941 ) , - .prog_clk_1_S_in ( p314 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[71] ) , .prog_clk_1_N_in ( p2284 ) , + .prog_clk_1_S_in ( p498 ) , .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_2460 ) , .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_2461 ) , .prog_clk_2_N_in ( prog_clk_3_wires[69] ) , @@ -110655,13 +115194,13 @@ sb_1__1_ sb_2__2_ ( .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_2465 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_2466 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_2467 ) , - .prog_clk_3_W_in ( p1796 ) , .prog_clk_3_E_in ( p62 ) , - .prog_clk_3_S_in ( p844 ) , .prog_clk_3_N_in ( p394 ) , + .prog_clk_3_W_in ( p1920 ) , .prog_clk_3_E_in ( p1119 ) , + .prog_clk_3_S_in ( p776 ) , .prog_clk_3_N_in ( p397 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_2468 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_2469 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_2470 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_2471 ) , .clk_1_N_in ( p1941 ) , - .clk_1_S_in ( p870 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_2472 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_2471 ) , .clk_1_N_in ( p2284 ) , + .clk_1_S_in ( p1156 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_2472 ) , .clk_1_W_out ( SYNOPSYS_UNCONNECTED_2473 ) , .clk_2_N_in ( clk_3_wires[69] ) , .clk_2_E_in ( SYNOPSYS_UNCONNECTED_2474 ) , @@ -110670,8 +115209,8 @@ sb_1__1_ sb_2__2_ ( .clk_2_W_out ( clk_2_wires[2] ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_2477 ) , .clk_2_N_out ( SYNOPSYS_UNCONNECTED_2478 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_2479 ) , .clk_3_W_in ( p1796 ) , - .clk_3_E_in ( p838 ) , .clk_3_S_in ( p2581 ) , .clk_3_N_in ( p1630 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_2479 ) , .clk_3_W_in ( p1920 ) , + .clk_3_E_in ( p379 ) , .clk_3_S_in ( p323 ) , .clk_3_N_in ( p2128 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_2480 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_2481 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_2482 ) , @@ -110719,20 +115258,20 @@ sb_1__1_ sb_2__3_ ( .chanx_right_out ( sb_1__1__13_chanx_right_out ) , .chany_bottom_out ( sb_1__1__13_chany_bottom_out ) , .chanx_left_out ( sb_1__1__13_chanx_left_out ) , - .ccff_tail ( sb_1__1__13_ccff_tail ) , .Test_en_S_in ( p2824 ) , + .ccff_tail ( sb_1__1__13_ccff_tail ) , .Test_en_S_in ( p2338 ) , .Test_en_N_out ( SYNOPSYS_UNCONNECTED_2485 ) , .pReset_S_in ( SYNOPSYS_UNCONNECTED_2486 ) , .pReset_E_in ( pResetWires[168] ) , .pReset_W_in ( SYNOPSYS_UNCONNECTED_2487 ) , .pReset_N_out ( pResetWires[167] ) , .pReset_W_out ( pResetWires[165] ) , - .pReset_E_out ( SYNOPSYS_UNCONNECTED_2488 ) , .Reset_S_in ( p3479 ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_2488 ) , .Reset_S_in ( p2338 ) , .Reset_N_out ( SYNOPSYS_UNCONNECTED_2489 ) , - .prog_clk_0_N_in ( prog_clk_0_wires[74] ) , .prog_clk_1_N_in ( p1616 ) , - .prog_clk_1_S_in ( p268 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[74] ) , .prog_clk_1_N_in ( p1227 ) , + .prog_clk_1_S_in ( p1281 ) , .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_2490 ) , .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_2491 ) , - .prog_clk_2_N_in ( p2669 ) , .prog_clk_2_E_in ( p1080 ) , - .prog_clk_2_S_in ( p653 ) , .prog_clk_2_W_in ( p792 ) , + .prog_clk_2_N_in ( p2584 ) , .prog_clk_2_E_in ( p593 ) , + .prog_clk_2_S_in ( p1762 ) , .prog_clk_2_W_in ( p342 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_2492 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_2493 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_2494 ) , @@ -110744,10 +115283,10 @@ sb_1__1_ sb_2__3_ ( .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_2499 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_2500 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_2501 ) , - .prog_clk_3_S_out ( prog_clk_3_wires[68] ) , .clk_1_N_in ( p1616 ) , - .clk_1_S_in ( p871 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_2502 ) , - .clk_1_W_out ( SYNOPSYS_UNCONNECTED_2503 ) , .clk_2_N_in ( p2669 ) , - .clk_2_E_in ( p211 ) , .clk_2_S_in ( p3473 ) , .clk_2_W_in ( p123 ) , + .prog_clk_3_S_out ( prog_clk_3_wires[68] ) , .clk_1_N_in ( p1227 ) , + .clk_1_S_in ( p139 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_2502 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_2503 ) , .clk_2_N_in ( p1392 ) , + .clk_2_E_in ( p818 ) , .clk_2_S_in ( p2064 ) , .clk_2_W_in ( p756 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_2504 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_2505 ) , .clk_2_N_out ( SYNOPSYS_UNCONNECTED_2506 ) , @@ -110803,16 +115342,16 @@ sb_1__1_ sb_2__4_ ( .chanx_right_out ( sb_1__1__14_chanx_right_out ) , .chany_bottom_out ( sb_1__1__14_chany_bottom_out ) , .chanx_left_out ( sb_1__1__14_chanx_left_out ) , - .ccff_tail ( sb_1__1__14_ccff_tail ) , .Test_en_S_in ( p1958 ) , + .ccff_tail ( sb_1__1__14_ccff_tail ) , .Test_en_S_in ( p1850 ) , .Test_en_N_out ( SYNOPSYS_UNCONNECTED_2515 ) , .pReset_S_in ( SYNOPSYS_UNCONNECTED_2516 ) , .pReset_E_in ( pResetWires[217] ) , .pReset_W_in ( SYNOPSYS_UNCONNECTED_2517 ) , .pReset_N_out ( pResetWires[216] ) , .pReset_W_out ( pResetWires[214] ) , - .pReset_E_out ( SYNOPSYS_UNCONNECTED_2518 ) , .Reset_S_in ( p1958 ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_2518 ) , .Reset_S_in ( p1850 ) , .Reset_N_out ( SYNOPSYS_UNCONNECTED_2519 ) , - .prog_clk_0_N_in ( prog_clk_0_wires[77] ) , .prog_clk_1_N_in ( p1358 ) , - .prog_clk_1_S_in ( p629 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[77] ) , .prog_clk_1_N_in ( p1886 ) , + .prog_clk_1_S_in ( p1704 ) , .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_2520 ) , .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_2521 ) , .prog_clk_2_N_in ( prog_clk_3_wires[59] ) , @@ -110830,8 +115369,8 @@ sb_1__1_ sb_2__4_ ( .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_2531 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_2532 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_2533 ) , - .prog_clk_3_S_out ( prog_clk_3_wires[64] ) , .clk_1_N_in ( p1358 ) , - .clk_1_S_in ( p1650 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_2534 ) , + .prog_clk_3_S_out ( prog_clk_3_wires[64] ) , .clk_1_N_in ( p1886 ) , + .clk_1_S_in ( p1171 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_2534 ) , .clk_1_W_out ( SYNOPSYS_UNCONNECTED_2535 ) , .clk_2_N_in ( clk_3_wires[59] ) , .clk_2_E_in ( SYNOPSYS_UNCONNECTED_2536 ) , @@ -110892,20 +115431,20 @@ sb_1__1_ sb_2__5_ ( .chanx_right_out ( sb_1__1__15_chanx_right_out ) , .chany_bottom_out ( sb_1__1__15_chany_bottom_out ) , .chanx_left_out ( sb_1__1__15_chanx_left_out ) , - .ccff_tail ( sb_1__1__15_ccff_tail ) , .Test_en_S_in ( p2666 ) , + .ccff_tail ( sb_1__1__15_ccff_tail ) , .Test_en_S_in ( p2583 ) , .Test_en_N_out ( SYNOPSYS_UNCONNECTED_2549 ) , .pReset_S_in ( SYNOPSYS_UNCONNECTED_2550 ) , .pReset_E_in ( pResetWires[266] ) , .pReset_W_in ( SYNOPSYS_UNCONNECTED_2551 ) , .pReset_N_out ( pResetWires[265] ) , .pReset_W_out ( pResetWires[263] ) , - .pReset_E_out ( SYNOPSYS_UNCONNECTED_2552 ) , .Reset_S_in ( p3176 ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_2552 ) , .Reset_S_in ( p2583 ) , .Reset_N_out ( SYNOPSYS_UNCONNECTED_2553 ) , - .prog_clk_0_N_in ( prog_clk_0_wires[80] ) , .prog_clk_1_N_in ( p1267 ) , - .prog_clk_1_S_in ( p676 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[80] ) , .prog_clk_1_N_in ( p1863 ) , + .prog_clk_1_S_in ( p75 ) , .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_2554 ) , .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_2555 ) , - .prog_clk_2_N_in ( p2849 ) , .prog_clk_2_E_in ( p342 ) , - .prog_clk_2_S_in ( p63 ) , .prog_clk_2_W_in ( p904 ) , + .prog_clk_2_N_in ( p1980 ) , .prog_clk_2_E_in ( p641 ) , + .prog_clk_2_S_in ( p1682 ) , .prog_clk_2_W_in ( p61 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_2556 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_2557 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_2558 ) , @@ -110917,10 +115456,10 @@ sb_1__1_ sb_2__5_ ( .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_2563 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_2564 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_2565 ) , - .prog_clk_3_S_out ( prog_clk_3_wires[58] ) , .clk_1_N_in ( p1267 ) , - .clk_1_S_in ( p315 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_2566 ) , - .clk_1_W_out ( SYNOPSYS_UNCONNECTED_2567 ) , .clk_2_N_in ( p2631 ) , - .clk_2_E_in ( p597 ) , .clk_2_S_in ( p3136 ) , .clk_2_W_in ( p609 ) , + .prog_clk_3_S_out ( prog_clk_3_wires[58] ) , .clk_1_N_in ( p1863 ) , + .clk_1_S_in ( p917 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_2566 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_2567 ) , .clk_2_N_in ( p1980 ) , + .clk_2_E_in ( p480 ) , .clk_2_S_in ( p2400 ) , .clk_2_W_in ( p863 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_2568 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_2569 ) , .clk_2_N_out ( SYNOPSYS_UNCONNECTED_2570 ) , @@ -110976,20 +115515,20 @@ sb_1__1_ sb_2__6_ ( .chanx_right_out ( sb_1__1__16_chanx_right_out ) , .chany_bottom_out ( sb_1__1__16_chany_bottom_out ) , .chanx_left_out ( sb_1__1__16_chanx_left_out ) , - .ccff_tail ( sb_1__1__16_ccff_tail ) , .Test_en_S_in ( p2123 ) , + .ccff_tail ( sb_1__1__16_ccff_tail ) , .Test_en_S_in ( p1969 ) , .Test_en_N_out ( SYNOPSYS_UNCONNECTED_2579 ) , .pReset_S_in ( SYNOPSYS_UNCONNECTED_2580 ) , .pReset_E_in ( pResetWires[315] ) , .pReset_W_in ( SYNOPSYS_UNCONNECTED_2581 ) , .pReset_N_out ( pResetWires[314] ) , .pReset_W_out ( pResetWires[312] ) , - .pReset_E_out ( SYNOPSYS_UNCONNECTED_2582 ) , .Reset_S_in ( p3274 ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_2582 ) , .Reset_S_in ( p1969 ) , .Reset_N_out ( SYNOPSYS_UNCONNECTED_2583 ) , - .prog_clk_0_N_in ( prog_clk_0_wires[83] ) , .prog_clk_1_N_in ( p1725 ) , - .prog_clk_1_S_in ( p139 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[83] ) , .prog_clk_1_N_in ( p1510 ) , + .prog_clk_1_S_in ( p680 ) , .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_2584 ) , .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_2585 ) , - .prog_clk_2_N_in ( p2225 ) , .prog_clk_2_E_in ( p1092 ) , - .prog_clk_2_S_in ( p782 ) , .prog_clk_2_W_in ( p1169 ) , + .prog_clk_2_N_in ( p2240 ) , .prog_clk_2_E_in ( p129 ) , + .prog_clk_2_S_in ( p1778 ) , .prog_clk_2_W_in ( p1037 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_2586 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_2587 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_2588 ) , @@ -111001,10 +115540,10 @@ sb_1__1_ sb_2__6_ ( .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_2593 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_2594 ) , .prog_clk_3_N_out ( prog_clk_3_wires[52] ) , - .prog_clk_3_S_out ( prog_clk_3_wires[54] ) , .clk_1_N_in ( p1725 ) , - .clk_1_S_in ( p594 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_2595 ) , - .clk_1_W_out ( SYNOPSYS_UNCONNECTED_2596 ) , .clk_2_N_in ( p1921 ) , - .clk_2_E_in ( p343 ) , .clk_2_S_in ( p3228 ) , .clk_2_W_in ( p133 ) , + .prog_clk_3_S_out ( prog_clk_3_wires[54] ) , .clk_1_N_in ( p1510 ) , + .clk_1_S_in ( p969 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_2595 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_2596 ) , .clk_2_N_in ( p2283 ) , + .clk_2_E_in ( p981 ) , .clk_2_S_in ( p1672 ) , .clk_2_W_in ( p343 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_2597 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_2598 ) , .clk_2_N_out ( SYNOPSYS_UNCONNECTED_2599 ) , @@ -111059,20 +115598,20 @@ sb_1__1_ sb_2__7_ ( .chanx_right_out ( sb_1__1__17_chanx_right_out ) , .chany_bottom_out ( sb_1__1__17_chany_bottom_out ) , .chanx_left_out ( sb_1__1__17_chanx_left_out ) , - .ccff_tail ( sb_1__1__17_ccff_tail ) , .Test_en_S_in ( p3100 ) , + .ccff_tail ( sb_1__1__17_ccff_tail ) , .Test_en_S_in ( p2001 ) , .Test_en_N_out ( SYNOPSYS_UNCONNECTED_2607 ) , .pReset_S_in ( SYNOPSYS_UNCONNECTED_2608 ) , .pReset_E_in ( pResetWires[364] ) , .pReset_W_in ( SYNOPSYS_UNCONNECTED_2609 ) , .pReset_N_out ( pResetWires[363] ) , .pReset_W_out ( pResetWires[361] ) , - .pReset_E_out ( SYNOPSYS_UNCONNECTED_2610 ) , .Reset_S_in ( p3377 ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_2610 ) , .Reset_S_in ( p2001 ) , .Reset_N_out ( SYNOPSYS_UNCONNECTED_2611 ) , - .prog_clk_0_N_in ( prog_clk_0_wires[86] ) , .prog_clk_1_N_in ( p1932 ) , - .prog_clk_1_S_in ( p241 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[86] ) , .prog_clk_1_N_in ( p1295 ) , + .prog_clk_1_S_in ( p1044 ) , .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_2612 ) , .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_2613 ) , - .prog_clk_2_N_in ( p2145 ) , .prog_clk_2_E_in ( p587 ) , - .prog_clk_2_S_in ( p618 ) , .prog_clk_2_W_in ( p1054 ) , + .prog_clk_2_N_in ( p2230 ) , .prog_clk_2_E_in ( p395 ) , + .prog_clk_2_S_in ( p52 ) , .prog_clk_2_W_in ( p774 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_2614 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_2615 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_2616 ) , @@ -111084,10 +115623,10 @@ sb_1__1_ sb_2__7_ ( .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_2621 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_2622 ) , .prog_clk_3_N_out ( prog_clk_3_wires[56] ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_2623 ) , .clk_1_N_in ( p1932 ) , - .clk_1_S_in ( p403 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_2624 ) , - .clk_1_W_out ( SYNOPSYS_UNCONNECTED_2625 ) , .clk_2_N_in ( p2191 ) , - .clk_2_E_in ( p911 ) , .clk_2_S_in ( p3348 ) , .clk_2_W_in ( p303 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_2623 ) , .clk_1_N_in ( p1295 ) , + .clk_1_S_in ( p260 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_2624 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_2625 ) , .clk_2_N_in ( p1478 ) , + .clk_2_E_in ( p819 ) , .clk_2_S_in ( p1659 ) , .clk_2_W_in ( p332 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_2626 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_2627 ) , .clk_2_N_out ( SYNOPSYS_UNCONNECTED_2628 ) , @@ -111143,16 +115682,16 @@ sb_1__1_ sb_2__8_ ( .chanx_right_out ( sb_1__1__18_chanx_right_out ) , .chany_bottom_out ( sb_1__1__18_chany_bottom_out ) , .chanx_left_out ( sb_1__1__18_chanx_left_out ) , - .ccff_tail ( sb_1__1__18_ccff_tail ) , .Test_en_S_in ( p1571 ) , + .ccff_tail ( sb_1__1__18_ccff_tail ) , .Test_en_S_in ( p1467 ) , .Test_en_N_out ( SYNOPSYS_UNCONNECTED_2637 ) , .pReset_S_in ( SYNOPSYS_UNCONNECTED_2638 ) , .pReset_E_in ( pResetWires[413] ) , .pReset_W_in ( SYNOPSYS_UNCONNECTED_2639 ) , .pReset_N_out ( pResetWires[412] ) , .pReset_W_out ( pResetWires[410] ) , - .pReset_E_out ( SYNOPSYS_UNCONNECTED_2640 ) , .Reset_S_in ( p1571 ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_2640 ) , .Reset_S_in ( p1467 ) , .Reset_N_out ( SYNOPSYS_UNCONNECTED_2641 ) , - .prog_clk_0_N_in ( prog_clk_0_wires[89] ) , .prog_clk_1_N_in ( p1394 ) , - .prog_clk_1_S_in ( p880 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[89] ) , .prog_clk_1_N_in ( p1919 ) , + .prog_clk_1_S_in ( p145 ) , .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_2642 ) , .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_2643 ) , .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_2644 ) , @@ -111170,8 +115709,8 @@ sb_1__1_ sb_2__8_ ( .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_2653 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_2654 ) , .prog_clk_3_N_out ( prog_clk_3_wires[62] ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_2655 ) , .clk_1_N_in ( p1394 ) , - .clk_1_S_in ( p252 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_2656 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_2655 ) , .clk_1_N_in ( p1919 ) , + .clk_1_S_in ( p1039 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_2656 ) , .clk_1_W_out ( SYNOPSYS_UNCONNECTED_2657 ) , .clk_2_N_in ( SYNOPSYS_UNCONNECTED_2658 ) , .clk_2_E_in ( SYNOPSYS_UNCONNECTED_2659 ) , @@ -111232,20 +115771,20 @@ sb_1__1_ sb_2__9_ ( .chanx_right_out ( sb_1__1__19_chanx_right_out ) , .chany_bottom_out ( sb_1__1__19_chany_bottom_out ) , .chanx_left_out ( sb_1__1__19_chanx_left_out ) , - .ccff_tail ( sb_1__1__19_ccff_tail ) , .Test_en_S_in ( p1864 ) , + .ccff_tail ( sb_1__1__19_ccff_tail ) , .Test_en_S_in ( p2525 ) , .Test_en_N_out ( SYNOPSYS_UNCONNECTED_2671 ) , .pReset_S_in ( SYNOPSYS_UNCONNECTED_2672 ) , .pReset_E_in ( pResetWires[462] ) , .pReset_W_in ( SYNOPSYS_UNCONNECTED_2673 ) , .pReset_N_out ( pResetWires[461] ) , .pReset_W_out ( pResetWires[459] ) , - .pReset_E_out ( SYNOPSYS_UNCONNECTED_2674 ) , .Reset_S_in ( p3452 ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_2674 ) , .Reset_S_in ( p2525 ) , .Reset_N_out ( SYNOPSYS_UNCONNECTED_2675 ) , - .prog_clk_0_N_in ( prog_clk_0_wires[92] ) , .prog_clk_1_N_in ( p1873 ) , - .prog_clk_1_S_in ( p912 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[92] ) , .prog_clk_1_N_in ( p1299 ) , + .prog_clk_1_S_in ( p1211 ) , .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_2676 ) , .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_2677 ) , - .prog_clk_2_N_in ( p2193 ) , .prog_clk_2_E_in ( p54 ) , - .prog_clk_2_S_in ( p533 ) , .prog_clk_2_W_in ( p204 ) , + .prog_clk_2_N_in ( p2809 ) , .prog_clk_2_E_in ( p538 ) , + .prog_clk_2_S_in ( p390 ) , .prog_clk_2_W_in ( p453 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_2678 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_2679 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_2680 ) , @@ -111257,10 +115796,10 @@ sb_1__1_ sb_2__9_ ( .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_2685 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_2686 ) , .prog_clk_3_N_out ( prog_clk_3_wires[66] ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_2687 ) , .clk_1_N_in ( p1873 ) , - .clk_1_S_in ( p173 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_2688 ) , - .clk_1_W_out ( SYNOPSYS_UNCONNECTED_2689 ) , .clk_2_N_in ( p2193 ) , - .clk_2_E_in ( p326 ) , .clk_2_S_in ( p3447 ) , .clk_2_W_in ( p1137 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_2687 ) , .clk_1_N_in ( p1299 ) , + .clk_1_S_in ( p214 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_2688 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_2689 ) , .clk_2_N_in ( p1650 ) , + .clk_2_E_in ( p659 ) , .clk_2_S_in ( p2395 ) , .clk_2_W_in ( p134 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_2690 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_2691 ) , .clk_2_N_out ( SYNOPSYS_UNCONNECTED_2692 ) , @@ -111316,16 +115855,16 @@ sb_1__1_ sb_2__10_ ( .chanx_right_out ( sb_1__1__20_chanx_right_out ) , .chany_bottom_out ( sb_1__1__20_chany_bottom_out ) , .chanx_left_out ( sb_1__1__20_chanx_left_out ) , - .ccff_tail ( sb_1__1__20_ccff_tail ) , .Test_en_S_in ( p2943 ) , + .ccff_tail ( sb_1__1__20_ccff_tail ) , .Test_en_S_in ( p2300 ) , .Test_en_N_out ( SYNOPSYS_UNCONNECTED_2701 ) , .pReset_S_in ( SYNOPSYS_UNCONNECTED_2702 ) , .pReset_E_in ( pResetWires[511] ) , .pReset_W_in ( SYNOPSYS_UNCONNECTED_2703 ) , .pReset_N_out ( pResetWires[510] ) , .pReset_W_out ( pResetWires[508] ) , - .pReset_E_out ( SYNOPSYS_UNCONNECTED_2704 ) , .Reset_S_in ( p2959 ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_2704 ) , .Reset_S_in ( p2300 ) , .Reset_N_out ( SYNOPSYS_UNCONNECTED_2705 ) , - .prog_clk_0_N_in ( prog_clk_0_wires[95] ) , .prog_clk_1_N_in ( p1385 ) , - .prog_clk_1_S_in ( p341 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[95] ) , .prog_clk_1_N_in ( p1429 ) , + .prog_clk_1_S_in ( p181 ) , .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_2706 ) , .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_2707 ) , .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_2708 ) , @@ -111336,13 +115875,13 @@ sb_1__1_ sb_2__10_ ( .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_2711 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_2712 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_2713 ) , - .prog_clk_3_W_in ( p1565 ) , .prog_clk_3_E_in ( p190 ) , - .prog_clk_3_S_in ( p1651 ) , .prog_clk_3_N_in ( p15 ) , + .prog_clk_3_W_in ( p1613 ) , .prog_clk_3_E_in ( p543 ) , + .prog_clk_3_S_in ( p246 ) , .prog_clk_3_N_in ( p152 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_2714 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_2715 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_2716 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_2717 ) , .clk_1_N_in ( p1385 ) , - .clk_1_S_in ( p908 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_2718 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_2717 ) , .clk_1_N_in ( p1429 ) , + .clk_1_S_in ( p1080 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_2718 ) , .clk_1_W_out ( SYNOPSYS_UNCONNECTED_2719 ) , .clk_2_N_in ( SYNOPSYS_UNCONNECTED_2720 ) , .clk_2_E_in ( SYNOPSYS_UNCONNECTED_2721 ) , @@ -111351,8 +115890,8 @@ sb_1__1_ sb_2__10_ ( .clk_2_W_out ( clk_2_wires[21] ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_2723 ) , .clk_2_N_out ( SYNOPSYS_UNCONNECTED_2724 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_2725 ) , .clk_3_W_in ( p1565 ) , - .clk_3_E_in ( p273 ) , .clk_3_S_in ( p2897 ) , .clk_3_N_in ( p540 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_2725 ) , .clk_3_W_in ( p1613 ) , + .clk_3_E_in ( p320 ) , .clk_3_S_in ( p2111 ) , .clk_3_N_in ( p677 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_2726 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_2727 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_2728 ) , @@ -111400,38 +115939,38 @@ sb_1__1_ sb_2__11_ ( .chanx_right_out ( sb_1__1__21_chanx_right_out ) , .chany_bottom_out ( sb_1__1__21_chany_bottom_out ) , .chanx_left_out ( sb_1__1__21_chanx_left_out ) , - .ccff_tail ( sb_1__1__21_ccff_tail ) , .Test_en_S_in ( p2625 ) , + .ccff_tail ( sb_1__1__21_ccff_tail ) , .Test_en_S_in ( p1648 ) , .Test_en_N_out ( SYNOPSYS_UNCONNECTED_2731 ) , .pReset_S_in ( SYNOPSYS_UNCONNECTED_2732 ) , .pReset_E_in ( pResetWires[560] ) , .pReset_W_in ( SYNOPSYS_UNCONNECTED_2733 ) , .pReset_N_out ( pResetWires[559] ) , .pReset_W_out ( pResetWires[557] ) , - .pReset_E_out ( SYNOPSYS_UNCONNECTED_2734 ) , .Reset_S_in ( p2625 ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_2734 ) , .Reset_S_in ( p1648 ) , .Reset_N_out ( SYNOPSYS_UNCONNECTED_2735 ) , - .prog_clk_0_N_in ( prog_clk_0_wires[98] ) , .prog_clk_1_N_in ( p2182 ) , - .prog_clk_1_S_in ( p239 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[98] ) , .prog_clk_1_N_in ( p2031 ) , + .prog_clk_1_S_in ( p830 ) , .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_2736 ) , .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_2737 ) , - .prog_clk_2_N_in ( p3356 ) , .prog_clk_2_E_in ( p1333 ) , - .prog_clk_2_S_in ( p1231 ) , .prog_clk_2_W_in ( p1291 ) , + .prog_clk_2_N_in ( p3504 ) , .prog_clk_2_E_in ( p508 ) , + .prog_clk_2_S_in ( p1332 ) , .prog_clk_2_W_in ( p865 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_2738 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_2739 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_2740 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_2741 ) , - .prog_clk_3_W_in ( p2848 ) , .prog_clk_3_E_in ( p145 ) , - .prog_clk_3_S_in ( p102 ) , .prog_clk_3_N_in ( p3345 ) , + .prog_clk_3_W_in ( p2369 ) , .prog_clk_3_E_in ( p158 ) , + .prog_clk_3_S_in ( p196 ) , .prog_clk_3_N_in ( p3477 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_2742 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_2743 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_2744 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_2745 ) , .clk_1_N_in ( p2182 ) , - .clk_1_S_in ( p1130 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_2746 ) , - .clk_1_W_out ( SYNOPSYS_UNCONNECTED_2747 ) , .clk_2_N_in ( p3488 ) , - .clk_2_E_in ( p888 ) , .clk_2_S_in ( p2530 ) , .clk_2_W_in ( p2728 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_2745 ) , .clk_1_N_in ( p2031 ) , + .clk_1_S_in ( p106 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_2746 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_2747 ) , .clk_2_N_in ( p2744 ) , + .clk_2_E_in ( p632 ) , .clk_2_S_in ( p351 ) , .clk_2_W_in ( p3516 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_2748 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_2749 ) , .clk_2_N_out ( SYNOPSYS_UNCONNECTED_2750 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_2751 ) , .clk_3_W_in ( p2848 ) , - .clk_3_E_in ( p971 ) , .clk_3_S_in ( p1246 ) , .clk_3_N_in ( p3484 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_2751 ) , .clk_3_W_in ( p3531 ) , + .clk_3_E_in ( p912 ) , .clk_3_S_in ( p1203 ) , .clk_3_N_in ( p2714 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_2752 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_2753 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_2754 ) , @@ -111479,27 +116018,27 @@ sb_1__1_ sb_3__1_ ( .chanx_right_out ( sb_1__1__22_chanx_right_out ) , .chany_bottom_out ( sb_1__1__22_chany_bottom_out ) , .chanx_left_out ( sb_1__1__22_chanx_left_out ) , - .ccff_tail ( sb_1__1__22_ccff_tail ) , .Test_en_S_in ( p2839 ) , + .ccff_tail ( sb_1__1__22_ccff_tail ) , .Test_en_S_in ( p2249 ) , .Test_en_N_out ( SYNOPSYS_UNCONNECTED_2757 ) , .pReset_S_in ( SYNOPSYS_UNCONNECTED_2758 ) , .pReset_E_in ( pResetWires[74] ) , .pReset_W_in ( SYNOPSYS_UNCONNECTED_2759 ) , .pReset_N_out ( pResetWires[73] ) , .pReset_W_out ( pResetWires[71] ) , - .pReset_E_out ( SYNOPSYS_UNCONNECTED_2760 ) , .Reset_S_in ( p3376 ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_2760 ) , .Reset_S_in ( p2316 ) , .Reset_N_out ( SYNOPSYS_UNCONNECTED_2761 ) , .prog_clk_0_N_in ( prog_clk_0_wires[106] ) , .prog_clk_1_N_in ( prog_clk_2_wires[30] ) , .prog_clk_1_S_in ( SYNOPSYS_UNCONNECTED_2762 ) , .prog_clk_1_E_out ( prog_clk_1_wires[43] ) , - .prog_clk_1_W_out ( prog_clk_1_wires[44] ) , .prog_clk_2_N_in ( p3071 ) , - .prog_clk_2_E_in ( p824 ) , .prog_clk_2_S_in ( p19 ) , - .prog_clk_2_W_in ( p1123 ) , + .prog_clk_1_W_out ( prog_clk_1_wires[44] ) , .prog_clk_2_N_in ( p3403 ) , + .prog_clk_2_E_in ( p155 ) , .prog_clk_2_S_in ( p816 ) , + .prog_clk_2_W_in ( p942 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_2763 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_2764 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_2765 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_2766 ) , - .prog_clk_3_W_in ( p2662 ) , .prog_clk_3_E_in ( p159 ) , - .prog_clk_3_S_in ( p1459 ) , .prog_clk_3_N_in ( p3044 ) , + .prog_clk_3_W_in ( p2756 ) , .prog_clk_3_E_in ( p872 ) , + .prog_clk_3_S_in ( p84 ) , .prog_clk_3_N_in ( p3380 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_2767 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_2768 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_2769 ) , @@ -111507,12 +116046,12 @@ sb_1__1_ sb_3__1_ ( .clk_1_N_in ( clk_2_wires[30] ) , .clk_1_S_in ( SYNOPSYS_UNCONNECTED_2771 ) , .clk_1_E_out ( clk_1_wires[43] ) , .clk_1_W_out ( clk_1_wires[44] ) , - .clk_2_N_in ( p3103 ) , .clk_2_E_in ( p1002 ) , .clk_2_S_in ( p3347 ) , - .clk_2_W_in ( p2590 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_2772 ) , + .clk_2_N_in ( p2027 ) , .clk_2_E_in ( p1190 ) , .clk_2_S_in ( p1150 ) , + .clk_2_W_in ( p3566 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_2772 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_2773 ) , .clk_2_N_out ( SYNOPSYS_UNCONNECTED_2774 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_2775 ) , .clk_3_W_in ( p2662 ) , - .clk_3_E_in ( p598 ) , .clk_3_S_in ( p681 ) , .clk_3_N_in ( p3029 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_2775 ) , .clk_3_W_in ( p3574 ) , + .clk_3_E_in ( p858 ) , .clk_3_S_in ( p2114 ) , .clk_3_N_in ( p1668 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_2776 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_2777 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_2778 ) , @@ -111560,16 +116099,16 @@ sb_1__1_ sb_3__2_ ( .chanx_right_out ( sb_1__1__23_chanx_right_out ) , .chany_bottom_out ( sb_1__1__23_chany_bottom_out ) , .chanx_left_out ( sb_1__1__23_chanx_left_out ) , - .ccff_tail ( sb_1__1__23_ccff_tail ) , .Test_en_S_in ( p2845 ) , + .ccff_tail ( sb_1__1__23_ccff_tail ) , .Test_en_S_in ( p2260 ) , .Test_en_N_out ( SYNOPSYS_UNCONNECTED_2781 ) , .pReset_S_in ( SYNOPSYS_UNCONNECTED_2782 ) , .pReset_E_in ( pResetWires[123] ) , .pReset_W_in ( SYNOPSYS_UNCONNECTED_2783 ) , .pReset_N_out ( pResetWires[122] ) , .pReset_W_out ( pResetWires[120] ) , - .pReset_E_out ( SYNOPSYS_UNCONNECTED_2784 ) , .Reset_S_in ( p2845 ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_2784 ) , .Reset_S_in ( p2260 ) , .Reset_N_out ( SYNOPSYS_UNCONNECTED_2785 ) , - .prog_clk_0_N_in ( prog_clk_0_wires[109] ) , .prog_clk_1_N_in ( p1558 ) , - .prog_clk_1_S_in ( p848 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[109] ) , .prog_clk_1_N_in ( p1872 ) , + .prog_clk_1_S_in ( p919 ) , .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_2786 ) , .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_2787 ) , .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_2788 ) , @@ -111580,13 +116119,13 @@ sb_1__1_ sb_3__2_ ( .prog_clk_2_S_out ( prog_clk_2_wires[29] ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_2792 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_2793 ) , - .prog_clk_3_W_in ( p1518 ) , .prog_clk_3_E_in ( p1026 ) , - .prog_clk_3_S_in ( p855 ) , .prog_clk_3_N_in ( p579 ) , + .prog_clk_3_W_in ( p1387 ) , .prog_clk_3_E_in ( p240 ) , + .prog_clk_3_S_in ( p35 ) , .prog_clk_3_N_in ( p220 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_2794 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_2795 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_2796 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_2797 ) , .clk_1_N_in ( p1558 ) , - .clk_1_S_in ( p81 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_2798 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_2797 ) , .clk_1_N_in ( p1872 ) , + .clk_1_S_in ( p606 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_2798 ) , .clk_1_W_out ( SYNOPSYS_UNCONNECTED_2799 ) , .clk_2_N_in ( SYNOPSYS_UNCONNECTED_2800 ) , .clk_2_E_in ( clk_2_wires[28] ) , @@ -111595,8 +116134,8 @@ sb_1__1_ sb_3__2_ ( .clk_2_W_out ( SYNOPSYS_UNCONNECTED_2803 ) , .clk_2_S_out ( clk_2_wires[29] ) , .clk_2_N_out ( SYNOPSYS_UNCONNECTED_2804 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_2805 ) , .clk_3_W_in ( p1518 ) , - .clk_3_E_in ( p325 ) , .clk_3_S_in ( p2739 ) , .clk_3_N_in ( p410 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_2805 ) , .clk_3_W_in ( p1387 ) , + .clk_3_E_in ( p961 ) , .clk_3_S_in ( p2107 ) , .clk_3_N_in ( p1718 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_2806 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_2807 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_2808 ) , @@ -111644,27 +116183,27 @@ sb_1__1_ sb_3__3_ ( .chanx_right_out ( sb_1__1__24_chanx_right_out ) , .chany_bottom_out ( sb_1__1__24_chany_bottom_out ) , .chanx_left_out ( sb_1__1__24_chanx_left_out ) , - .ccff_tail ( sb_1__1__24_ccff_tail ) , .Test_en_S_in ( p2442 ) , + .ccff_tail ( sb_1__1__24_ccff_tail ) , .Test_en_S_in ( p2346 ) , .Test_en_N_out ( SYNOPSYS_UNCONNECTED_2811 ) , .pReset_S_in ( SYNOPSYS_UNCONNECTED_2812 ) , .pReset_E_in ( pResetWires[172] ) , .pReset_W_in ( SYNOPSYS_UNCONNECTED_2813 ) , .pReset_N_out ( pResetWires[171] ) , .pReset_W_out ( pResetWires[169] ) , - .pReset_E_out ( SYNOPSYS_UNCONNECTED_2814 ) , .Reset_S_in ( p2442 ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_2814 ) , .Reset_S_in ( p2346 ) , .Reset_N_out ( SYNOPSYS_UNCONNECTED_2815 ) , .prog_clk_0_N_in ( prog_clk_0_wires[112] ) , .prog_clk_1_N_in ( prog_clk_2_wires[41] ) , .prog_clk_1_S_in ( SYNOPSYS_UNCONNECTED_2816 ) , .prog_clk_1_E_out ( prog_clk_1_wires[50] ) , - .prog_clk_1_W_out ( prog_clk_1_wires[51] ) , .prog_clk_2_N_in ( p3502 ) , - .prog_clk_2_E_in ( p35 ) , .prog_clk_2_S_in ( p1122 ) , - .prog_clk_2_W_in ( p1132 ) , + .prog_clk_1_W_out ( prog_clk_1_wires[51] ) , .prog_clk_2_N_in ( p3455 ) , + .prog_clk_2_E_in ( p935 ) , .prog_clk_2_S_in ( p361 ) , + .prog_clk_2_W_in ( p179 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_2817 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_2818 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_2819 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_2820 ) , - .prog_clk_3_W_in ( p2779 ) , .prog_clk_3_E_in ( p937 ) , - .prog_clk_3_S_in ( p200 ) , .prog_clk_3_N_in ( p3500 ) , + .prog_clk_3_W_in ( p2621 ) , .prog_clk_3_E_in ( p207 ) , + .prog_clk_3_S_in ( p1278 ) , .prog_clk_3_N_in ( p3444 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_2821 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_2822 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_2823 ) , @@ -111672,12 +116211,12 @@ sb_1__1_ sb_3__3_ ( .clk_1_N_in ( clk_2_wires[41] ) , .clk_1_S_in ( SYNOPSYS_UNCONNECTED_2825 ) , .clk_1_E_out ( clk_1_wires[50] ) , .clk_1_W_out ( clk_1_wires[51] ) , - .clk_2_N_in ( p3061 ) , .clk_2_E_in ( p502 ) , .clk_2_S_in ( p2310 ) , - .clk_2_W_in ( p2745 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_2826 ) , + .clk_2_N_in ( p3407 ) , .clk_2_E_in ( p647 ) , .clk_2_S_in ( p1177 ) , + .clk_2_W_in ( p3067 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_2826 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_2827 ) , .clk_2_N_out ( SYNOPSYS_UNCONNECTED_2828 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_2829 ) , .clk_3_W_in ( p2779 ) , - .clk_3_E_in ( p680 ) , .clk_3_S_in ( p1193 ) , .clk_3_N_in ( p3011 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_2829 ) , .clk_3_W_in ( p3106 ) , + .clk_3_E_in ( p598 ) , .clk_3_S_in ( p2135 ) , .clk_3_N_in ( p3391 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_2830 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_2831 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_2832 ) , @@ -111725,16 +116264,16 @@ sb_1__1_ sb_3__4_ ( .chanx_right_out ( sb_1__1__25_chanx_right_out ) , .chany_bottom_out ( sb_1__1__25_chany_bottom_out ) , .chanx_left_out ( sb_1__1__25_chanx_left_out ) , - .ccff_tail ( sb_1__1__25_ccff_tail ) , .Test_en_S_in ( p2408 ) , + .ccff_tail ( sb_1__1__25_ccff_tail ) , .Test_en_S_in ( p2184 ) , .Test_en_N_out ( SYNOPSYS_UNCONNECTED_2835 ) , .pReset_S_in ( SYNOPSYS_UNCONNECTED_2836 ) , .pReset_E_in ( pResetWires[221] ) , .pReset_W_in ( SYNOPSYS_UNCONNECTED_2837 ) , .pReset_N_out ( pResetWires[220] ) , .pReset_W_out ( pResetWires[218] ) , - .pReset_E_out ( SYNOPSYS_UNCONNECTED_2838 ) , .Reset_S_in ( p2408 ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_2838 ) , .Reset_S_in ( p2184 ) , .Reset_N_out ( SYNOPSYS_UNCONNECTED_2839 ) , - .prog_clk_0_N_in ( prog_clk_0_wires[115] ) , .prog_clk_1_N_in ( p2254 ) , - .prog_clk_1_S_in ( p1010 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[115] ) , .prog_clk_1_N_in ( p1994 ) , + .prog_clk_1_S_in ( p82 ) , .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_2840 ) , .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_2841 ) , .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_2842 ) , @@ -111745,13 +116284,13 @@ sb_1__1_ sb_3__4_ ( .prog_clk_2_S_out ( prog_clk_2_wires[40] ) , .prog_clk_2_N_out ( prog_clk_2_wires[38] ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_2846 ) , - .prog_clk_3_W_in ( p1613 ) , .prog_clk_3_E_in ( p778 ) , - .prog_clk_3_S_in ( p475 ) , .prog_clk_3_N_in ( p2026 ) , + .prog_clk_3_W_in ( p2202 ) , .prog_clk_3_E_in ( p189 ) , + .prog_clk_3_S_in ( p625 ) , .prog_clk_3_N_in ( p1032 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_2847 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_2848 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_2849 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_2850 ) , .clk_1_N_in ( p2254 ) , - .clk_1_S_in ( p116 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_2851 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_2850 ) , .clk_1_N_in ( p1994 ) , + .clk_1_S_in ( p1259 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_2851 ) , .clk_1_W_out ( SYNOPSYS_UNCONNECTED_2852 ) , .clk_2_N_in ( SYNOPSYS_UNCONNECTED_2853 ) , .clk_2_E_in ( clk_2_wires[37] ) , @@ -111759,8 +116298,8 @@ sb_1__1_ sb_3__4_ ( .clk_2_W_in ( SYNOPSYS_UNCONNECTED_2855 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_2856 ) , .clk_2_S_out ( clk_2_wires[40] ) , .clk_2_N_out ( clk_2_wires[38] ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_2857 ) , .clk_3_W_in ( p1613 ) , - .clk_3_E_in ( p1624 ) , .clk_3_S_in ( p2337 ) , .clk_3_N_in ( p1991 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_2857 ) , .clk_3_W_in ( p2202 ) , + .clk_3_E_in ( p1753 ) , .clk_3_S_in ( p2072 ) , .clk_3_N_in ( p1689 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_2858 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_2859 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_2860 ) , @@ -111808,40 +116347,40 @@ sb_1__1_ sb_3__5_ ( .chanx_right_out ( sb_1__1__26_chanx_right_out ) , .chany_bottom_out ( sb_1__1__26_chany_bottom_out ) , .chanx_left_out ( sb_1__1__26_chanx_left_out ) , - .ccff_tail ( sb_1__1__26_ccff_tail ) , .Test_en_S_in ( p2420 ) , + .ccff_tail ( sb_1__1__26_ccff_tail ) , .Test_en_S_in ( p2234 ) , .Test_en_N_out ( SYNOPSYS_UNCONNECTED_2863 ) , .pReset_S_in ( SYNOPSYS_UNCONNECTED_2864 ) , .pReset_E_in ( pResetWires[270] ) , .pReset_W_in ( SYNOPSYS_UNCONNECTED_2865 ) , .pReset_N_out ( pResetWires[269] ) , .pReset_W_out ( pResetWires[267] ) , - .pReset_E_out ( SYNOPSYS_UNCONNECTED_2866 ) , .Reset_S_in ( p3332 ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_2866 ) , .Reset_S_in ( p2234 ) , .Reset_N_out ( SYNOPSYS_UNCONNECTED_2867 ) , .prog_clk_0_N_in ( prog_clk_0_wires[118] ) , .prog_clk_1_N_in ( SYNOPSYS_UNCONNECTED_2868 ) , .prog_clk_1_S_in ( prog_clk_2_wires[39] ) , .prog_clk_1_E_out ( prog_clk_1_wires[57] ) , - .prog_clk_1_W_out ( prog_clk_1_wires[58] ) , .prog_clk_2_N_in ( p3406 ) , - .prog_clk_2_E_in ( p651 ) , .prog_clk_2_S_in ( p711 ) , - .prog_clk_2_W_in ( p495 ) , + .prog_clk_1_W_out ( prog_clk_1_wires[58] ) , .prog_clk_2_N_in ( p3161 ) , + .prog_clk_2_E_in ( p228 ) , .prog_clk_2_S_in ( p558 ) , + .prog_clk_2_W_in ( p949 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_2869 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_2870 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_2871 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_2872 ) , - .prog_clk_3_W_in ( p2783 ) , .prog_clk_3_E_in ( p1161 ) , - .prog_clk_3_S_in ( p1336 ) , .prog_clk_3_N_in ( p3379 ) , + .prog_clk_3_W_in ( p3027 ) , .prog_clk_3_E_in ( p685 ) , + .prog_clk_3_S_in ( p1264 ) , .prog_clk_3_N_in ( p3061 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_2873 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_2874 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_2875 ) , .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_2876 ) , .clk_1_N_in ( SYNOPSYS_UNCONNECTED_2877 ) , .clk_1_S_in ( clk_2_wires[39] ) , .clk_1_E_out ( clk_1_wires[57] ) , - .clk_1_W_out ( clk_1_wires[58] ) , .clk_2_N_in ( p1574 ) , - .clk_2_E_in ( p110 ) , .clk_2_S_in ( p3296 ) , .clk_2_W_in ( p2733 ) , + .clk_1_W_out ( clk_1_wires[58] ) , .clk_2_N_in ( p3102 ) , + .clk_2_E_in ( p562 ) , .clk_2_S_in ( p955 ) , .clk_2_W_in ( p3308 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_2878 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_2879 ) , .clk_2_N_out ( SYNOPSYS_UNCONNECTED_2880 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_2881 ) , .clk_3_W_in ( p2783 ) , - .clk_3_E_in ( p503 ) , .clk_3_S_in ( p1238 ) , .clk_3_N_in ( p367 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_2881 ) , .clk_3_W_in ( p3328 ) , + .clk_3_E_in ( p1198 ) , .clk_3_S_in ( p2077 ) , .clk_3_N_in ( p3069 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_2882 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_2883 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_2884 ) , @@ -111889,20 +116428,20 @@ sb_1__1_ sb_3__6_ ( .chanx_right_out ( sb_1__1__27_chanx_right_out ) , .chany_bottom_out ( sb_1__1__27_chany_bottom_out ) , .chanx_left_out ( sb_1__1__27_chanx_left_out ) , - .ccff_tail ( sb_1__1__27_ccff_tail ) , .Test_en_S_in ( p3097 ) , + .ccff_tail ( sb_1__1__27_ccff_tail ) , .Test_en_S_in ( p2622 ) , .Test_en_N_out ( SYNOPSYS_UNCONNECTED_2887 ) , .pReset_S_in ( SYNOPSYS_UNCONNECTED_2888 ) , .pReset_E_in ( pResetWires[319] ) , .pReset_W_in ( SYNOPSYS_UNCONNECTED_2889 ) , .pReset_N_out ( pResetWires[318] ) , .pReset_W_out ( pResetWires[316] ) , - .pReset_E_out ( SYNOPSYS_UNCONNECTED_2890 ) , .Reset_S_in ( p3429 ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_2890 ) , .Reset_S_in ( p2622 ) , .Reset_N_out ( SYNOPSYS_UNCONNECTED_2891 ) , - .prog_clk_0_N_in ( prog_clk_0_wires[121] ) , .prog_clk_1_N_in ( p1498 ) , - .prog_clk_1_S_in ( p1022 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[121] ) , .prog_clk_1_N_in ( p1652 ) , + .prog_clk_1_S_in ( p958 ) , .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_2892 ) , .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_2893 ) , - .prog_clk_2_N_in ( p1942 ) , .prog_clk_2_E_in ( p30 ) , - .prog_clk_2_S_in ( p364 ) , .prog_clk_2_W_in ( p1222 ) , + .prog_clk_2_N_in ( p2628 ) , .prog_clk_2_E_in ( p297 ) , + .prog_clk_2_S_in ( p404 ) , .prog_clk_2_W_in ( p954 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_2894 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_2895 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_2896 ) , @@ -111914,10 +116453,10 @@ sb_1__1_ sb_3__6_ ( .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_2901 ) , .prog_clk_3_W_out ( prog_clk_3_wires[50] ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_2902 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_2903 ) , .clk_1_N_in ( p1498 ) , - .clk_1_S_in ( p34 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_2904 ) , - .clk_1_W_out ( SYNOPSYS_UNCONNECTED_2905 ) , .clk_2_N_in ( p1942 ) , - .clk_2_E_in ( p1144 ) , .clk_2_S_in ( p3416 ) , .clk_2_W_in ( p338 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_2903 ) , .clk_1_N_in ( p1652 ) , + .clk_1_S_in ( p119 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_2904 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_2905 ) , .clk_2_N_in ( p2317 ) , + .clk_2_E_in ( p205 ) , .clk_2_S_in ( p2449 ) , .clk_2_W_in ( p413 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_2906 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_2907 ) , .clk_2_N_out ( SYNOPSYS_UNCONNECTED_2908 ) , @@ -111973,27 +116512,27 @@ sb_1__1_ sb_3__7_ ( .chanx_right_out ( sb_1__1__28_chanx_right_out ) , .chany_bottom_out ( sb_1__1__28_chany_bottom_out ) , .chanx_left_out ( sb_1__1__28_chanx_left_out ) , - .ccff_tail ( sb_1__1__28_ccff_tail ) , .Test_en_S_in ( p2409 ) , + .ccff_tail ( sb_1__1__28_ccff_tail ) , .Test_en_S_in ( p1973 ) , .Test_en_N_out ( SYNOPSYS_UNCONNECTED_2917 ) , .pReset_S_in ( SYNOPSYS_UNCONNECTED_2918 ) , .pReset_E_in ( pResetWires[368] ) , .pReset_W_in ( SYNOPSYS_UNCONNECTED_2919 ) , .pReset_N_out ( pResetWires[367] ) , .pReset_W_out ( pResetWires[365] ) , - .pReset_E_out ( SYNOPSYS_UNCONNECTED_2920 ) , .Reset_S_in ( p2409 ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_2920 ) , .Reset_S_in ( p1973 ) , .Reset_N_out ( SYNOPSYS_UNCONNECTED_2921 ) , .prog_clk_0_N_in ( prog_clk_0_wires[124] ) , .prog_clk_1_N_in ( prog_clk_2_wires[54] ) , .prog_clk_1_S_in ( SYNOPSYS_UNCONNECTED_2922 ) , .prog_clk_1_E_out ( prog_clk_1_wires[64] ) , - .prog_clk_1_W_out ( prog_clk_1_wires[65] ) , .prog_clk_2_N_in ( p2942 ) , - .prog_clk_2_E_in ( p126 ) , .prog_clk_2_S_in ( p700 ) , - .prog_clk_2_W_in ( p1275 ) , + .prog_clk_1_W_out ( prog_clk_1_wires[65] ) , .prog_clk_2_N_in ( p2555 ) , + .prog_clk_2_E_in ( p128 ) , .prog_clk_2_S_in ( p971 ) , + .prog_clk_2_W_in ( p299 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_2923 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_2924 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_2925 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_2926 ) , - .prog_clk_3_W_in ( p3245 ) , .prog_clk_3_E_in ( p1254 ) , - .prog_clk_3_S_in ( p481 ) , .prog_clk_3_N_in ( p2895 ) , + .prog_clk_3_W_in ( p2579 ) , .prog_clk_3_E_in ( p719 ) , + .prog_clk_3_S_in ( p131 ) , .prog_clk_3_N_in ( p2437 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_2927 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_2928 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_2929 ) , @@ -112001,12 +116540,12 @@ sb_1__1_ sb_3__7_ ( .clk_1_N_in ( clk_2_wires[54] ) , .clk_1_S_in ( SYNOPSYS_UNCONNECTED_2931 ) , .clk_1_E_out ( clk_1_wires[64] ) , .clk_1_W_out ( clk_1_wires[65] ) , - .clk_2_N_in ( p2818 ) , .clk_2_E_in ( p1045 ) , .clk_2_S_in ( p2311 ) , - .clk_2_W_in ( p3224 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_2932 ) , + .clk_2_N_in ( p2973 ) , .clk_2_E_in ( p34 ) , .clk_2_S_in ( p1262 ) , + .clk_2_W_in ( p3368 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_2932 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_2933 ) , .clk_2_N_out ( SYNOPSYS_UNCONNECTED_2934 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_2935 ) , .clk_3_W_in ( p3261 ) , - .clk_3_E_in ( p1036 ) , .clk_3_S_in ( p433 ) , .clk_3_N_in ( p2764 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_2935 ) , .clk_3_W_in ( p3419 ) , + .clk_3_E_in ( p1081 ) , .clk_3_S_in ( p1784 ) , .clk_3_N_in ( p2871 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_2936 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_2937 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_2938 ) , @@ -112054,16 +116593,16 @@ sb_1__1_ sb_3__8_ ( .chanx_right_out ( sb_1__1__29_chanx_right_out ) , .chany_bottom_out ( sb_1__1__29_chany_bottom_out ) , .chanx_left_out ( sb_1__1__29_chanx_left_out ) , - .ccff_tail ( sb_1__1__29_ccff_tail ) , .Test_en_S_in ( p2833 ) , + .ccff_tail ( sb_1__1__29_ccff_tail ) , .Test_en_S_in ( p2041 ) , .Test_en_N_out ( SYNOPSYS_UNCONNECTED_2941 ) , .pReset_S_in ( SYNOPSYS_UNCONNECTED_2942 ) , .pReset_E_in ( pResetWires[417] ) , .pReset_W_in ( SYNOPSYS_UNCONNECTED_2943 ) , .pReset_N_out ( pResetWires[416] ) , .pReset_W_out ( pResetWires[414] ) , - .pReset_E_out ( SYNOPSYS_UNCONNECTED_2944 ) , .Reset_S_in ( p2833 ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_2944 ) , .Reset_S_in ( p2041 ) , .Reset_N_out ( SYNOPSYS_UNCONNECTED_2945 ) , - .prog_clk_0_N_in ( prog_clk_0_wires[127] ) , .prog_clk_1_N_in ( p1908 ) , - .prog_clk_1_S_in ( p287 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[127] ) , .prog_clk_1_N_in ( p1554 ) , + .prog_clk_1_S_in ( p442 ) , .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_2946 ) , .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_2947 ) , .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_2948 ) , @@ -112074,13 +116613,13 @@ sb_1__1_ sb_3__8_ ( .prog_clk_2_S_out ( prog_clk_2_wires[53] ) , .prog_clk_2_N_out ( prog_clk_2_wires[51] ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_2952 ) , - .prog_clk_3_W_in ( p1477 ) , .prog_clk_3_E_in ( p154 ) , - .prog_clk_3_S_in ( p56 ) , .prog_clk_3_N_in ( p1727 ) , + .prog_clk_3_W_in ( p1489 ) , .prog_clk_3_E_in ( p502 ) , + .prog_clk_3_S_in ( p112 ) , .prog_clk_3_N_in ( p1678 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_2953 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_2954 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_2955 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_2956 ) , .clk_1_N_in ( p1908 ) , - .clk_1_S_in ( p1084 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_2957 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_2956 ) , .clk_1_N_in ( p1554 ) , + .clk_1_S_in ( p581 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_2957 ) , .clk_1_W_out ( SYNOPSYS_UNCONNECTED_2958 ) , .clk_2_N_in ( SYNOPSYS_UNCONNECTED_2959 ) , .clk_2_E_in ( clk_2_wires[50] ) , @@ -112088,8 +116627,8 @@ sb_1__1_ sb_3__8_ ( .clk_2_W_in ( SYNOPSYS_UNCONNECTED_2961 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_2962 ) , .clk_2_S_out ( clk_2_wires[53] ) , .clk_2_N_out ( clk_2_wires[51] ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_2963 ) , .clk_3_W_in ( p1477 ) , - .clk_3_E_in ( p1674 ) , .clk_3_S_in ( p2730 ) , .clk_3_N_in ( p1632 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_2963 ) , .clk_3_W_in ( p1489 ) , + .clk_3_E_in ( p1758 ) , .clk_3_S_in ( p1669 ) , .clk_3_N_in ( p869 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_2964 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_2965 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_2966 ) , @@ -112137,40 +116676,40 @@ sb_1__1_ sb_3__9_ ( .chanx_right_out ( sb_1__1__30_chanx_right_out ) , .chany_bottom_out ( sb_1__1__30_chany_bottom_out ) , .chanx_left_out ( sb_1__1__30_chanx_left_out ) , - .ccff_tail ( sb_1__1__30_ccff_tail ) , .Test_en_S_in ( p3188 ) , + .ccff_tail ( sb_1__1__30_ccff_tail ) , .Test_en_S_in ( p2312 ) , .Test_en_N_out ( SYNOPSYS_UNCONNECTED_2969 ) , .pReset_S_in ( SYNOPSYS_UNCONNECTED_2970 ) , .pReset_E_in ( pResetWires[466] ) , .pReset_W_in ( SYNOPSYS_UNCONNECTED_2971 ) , .pReset_N_out ( pResetWires[465] ) , .pReset_W_out ( pResetWires[463] ) , - .pReset_E_out ( SYNOPSYS_UNCONNECTED_2972 ) , .Reset_S_in ( p3409 ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_2972 ) , .Reset_S_in ( p2312 ) , .Reset_N_out ( SYNOPSYS_UNCONNECTED_2973 ) , .prog_clk_0_N_in ( prog_clk_0_wires[130] ) , .prog_clk_1_N_in ( SYNOPSYS_UNCONNECTED_2974 ) , .prog_clk_1_S_in ( prog_clk_2_wires[52] ) , .prog_clk_1_E_out ( prog_clk_1_wires[71] ) , - .prog_clk_1_W_out ( prog_clk_1_wires[72] ) , .prog_clk_2_N_in ( p3503 ) , - .prog_clk_2_E_in ( p788 ) , .prog_clk_2_S_in ( p726 ) , - .prog_clk_2_W_in ( p289 ) , + .prog_clk_1_W_out ( prog_clk_1_wires[72] ) , .prog_clk_2_N_in ( p3498 ) , + .prog_clk_2_E_in ( p494 ) , .prog_clk_2_S_in ( p1085 ) , + .prog_clk_2_W_in ( p876 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_2975 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_2976 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_2977 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_2978 ) , - .prog_clk_3_W_in ( p2504 ) , .prog_clk_3_E_in ( p1223 ) , - .prog_clk_3_S_in ( p1191 ) , .prog_clk_3_N_in ( p3501 ) , + .prog_clk_3_W_in ( p3003 ) , .prog_clk_3_E_in ( p237 ) , + .prog_clk_3_S_in ( p852 ) , .prog_clk_3_N_in ( p3490 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_2979 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_2980 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_2981 ) , .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_2982 ) , .clk_1_N_in ( SYNOPSYS_UNCONNECTED_2983 ) , .clk_1_S_in ( clk_2_wires[52] ) , .clk_1_E_out ( clk_1_wires[71] ) , - .clk_1_W_out ( clk_1_wires[72] ) , .clk_2_N_in ( p3425 ) , - .clk_2_E_in ( p958 ) , .clk_2_S_in ( p3381 ) , .clk_2_W_in ( p2332 ) , + .clk_1_W_out ( clk_1_wires[72] ) , .clk_2_N_in ( p3402 ) , + .clk_2_E_in ( p1125 ) , .clk_2_S_in ( p26 ) , .clk_2_W_in ( p3369 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_2984 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_2985 ) , .clk_2_N_out ( SYNOPSYS_UNCONNECTED_2986 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_2987 ) , .clk_3_W_in ( p2504 ) , - .clk_3_E_in ( p24 ) , .clk_3_S_in ( p1342 ) , .clk_3_N_in ( p3422 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_2987 ) , .clk_3_W_in ( p3411 ) , + .clk_3_E_in ( p607 ) , .clk_3_S_in ( p2124 ) , .clk_3_N_in ( p3386 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_2988 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_2989 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_2990 ) , @@ -112218,16 +116757,16 @@ sb_1__1_ sb_3__10_ ( .chanx_right_out ( sb_1__1__31_chanx_right_out ) , .chany_bottom_out ( sb_1__1__31_chany_bottom_out ) , .chanx_left_out ( sb_1__1__31_chanx_left_out ) , - .ccff_tail ( sb_1__1__31_ccff_tail ) , .Test_en_S_in ( p886 ) , + .ccff_tail ( sb_1__1__31_ccff_tail ) , .Test_en_S_in ( p1398 ) , .Test_en_N_out ( SYNOPSYS_UNCONNECTED_2993 ) , .pReset_S_in ( SYNOPSYS_UNCONNECTED_2994 ) , .pReset_E_in ( pResetWires[515] ) , .pReset_W_in ( SYNOPSYS_UNCONNECTED_2995 ) , .pReset_N_out ( pResetWires[514] ) , .pReset_W_out ( pResetWires[512] ) , - .pReset_E_out ( SYNOPSYS_UNCONNECTED_2996 ) , .Reset_S_in ( p886 ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_2996 ) , .Reset_S_in ( p1398 ) , .Reset_N_out ( SYNOPSYS_UNCONNECTED_2997 ) , - .prog_clk_0_N_in ( prog_clk_0_wires[133] ) , .prog_clk_1_N_in ( p2202 ) , - .prog_clk_1_S_in ( p141 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[133] ) , .prog_clk_1_N_in ( p1491 ) , + .prog_clk_1_S_in ( p1121 ) , .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_2998 ) , .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_2999 ) , .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_3000 ) , @@ -112238,13 +116777,13 @@ sb_1__1_ sb_3__10_ ( .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_3004 ) , .prog_clk_2_N_out ( prog_clk_2_wires[64] ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_3005 ) , - .prog_clk_3_W_in ( p1499 ) , .prog_clk_3_E_in ( p217 ) , - .prog_clk_3_S_in ( p825 ) , .prog_clk_3_N_in ( p2008 ) , + .prog_clk_3_W_in ( p1611 ) , .prog_clk_3_E_in ( p833 ) , + .prog_clk_3_S_in ( p815 ) , .prog_clk_3_N_in ( p445 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_3006 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_3007 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_3008 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_3009 ) , .clk_1_N_in ( p2202 ) , - .clk_1_S_in ( p1145 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_3010 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_3009 ) , .clk_1_N_in ( p1491 ) , + .clk_1_S_in ( p310 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_3010 ) , .clk_1_W_out ( SYNOPSYS_UNCONNECTED_3011 ) , .clk_2_N_in ( SYNOPSYS_UNCONNECTED_3012 ) , .clk_2_E_in ( clk_2_wires[63] ) , @@ -112253,8 +116792,8 @@ sb_1__1_ sb_3__10_ ( .clk_2_W_out ( SYNOPSYS_UNCONNECTED_3015 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_3016 ) , .clk_2_N_out ( clk_2_wires[64] ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_3017 ) , .clk_3_W_in ( p1499 ) , - .clk_3_E_in ( p1675 ) , .clk_3_S_in ( p826 ) , .clk_3_N_in ( p2049 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_3017 ) , .clk_3_W_in ( p1611 ) , + .clk_3_E_in ( p285 ) , .clk_3_S_in ( p629 ) , .clk_3_N_in ( p153 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_3018 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_3019 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_3020 ) , @@ -112302,40 +116841,40 @@ sb_1__1_ sb_3__11_ ( .chanx_right_out ( sb_1__1__32_chanx_right_out ) , .chany_bottom_out ( sb_1__1__32_chany_bottom_out ) , .chanx_left_out ( sb_1__1__32_chanx_left_out ) , - .ccff_tail ( sb_1__1__32_ccff_tail ) , .Test_en_S_in ( p2259 ) , + .ccff_tail ( sb_1__1__32_ccff_tail ) , .Test_en_S_in ( p2331 ) , .Test_en_N_out ( SYNOPSYS_UNCONNECTED_3023 ) , .pReset_S_in ( SYNOPSYS_UNCONNECTED_3024 ) , .pReset_E_in ( pResetWires[564] ) , .pReset_W_in ( SYNOPSYS_UNCONNECTED_3025 ) , .pReset_N_out ( pResetWires[563] ) , .pReset_W_out ( pResetWires[561] ) , - .pReset_E_out ( SYNOPSYS_UNCONNECTED_3026 ) , .Reset_S_in ( p3489 ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_3026 ) , .Reset_S_in ( p2331 ) , .Reset_N_out ( SYNOPSYS_UNCONNECTED_3027 ) , .prog_clk_0_N_in ( prog_clk_0_wires[136] ) , .prog_clk_1_N_in ( SYNOPSYS_UNCONNECTED_3028 ) , .prog_clk_1_S_in ( prog_clk_2_wires[65] ) , .prog_clk_1_E_out ( prog_clk_1_wires[78] ) , - .prog_clk_1_W_out ( prog_clk_1_wires[79] ) , .prog_clk_2_N_in ( p2948 ) , - .prog_clk_2_E_in ( p1189 ) , .prog_clk_2_S_in ( p60 ) , - .prog_clk_2_W_in ( p230 ) , + .prog_clk_1_W_out ( prog_clk_1_wires[79] ) , .prog_clk_2_N_in ( p3506 ) , + .prog_clk_2_E_in ( p637 ) , .prog_clk_2_S_in ( p1255 ) , + .prog_clk_2_W_in ( p910 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_3029 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_3030 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_3031 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_3032 ) , - .prog_clk_3_W_in ( p2460 ) , .prog_clk_3_E_in ( p142 ) , - .prog_clk_3_S_in ( p1384 ) , .prog_clk_3_N_in ( p2893 ) , + .prog_clk_3_W_in ( p2251 ) , .prog_clk_3_E_in ( p837 ) , + .prog_clk_3_S_in ( p236 ) , .prog_clk_3_N_in ( p3480 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_3033 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_3034 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_3035 ) , .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_3036 ) , .clk_1_N_in ( SYNOPSYS_UNCONNECTED_3037 ) , .clk_1_S_in ( clk_2_wires[65] ) , .clk_1_E_out ( clk_1_wires[78] ) , - .clk_1_W_out ( clk_1_wires[79] ) , .clk_2_N_in ( p1826 ) , - .clk_2_E_in ( p926 ) , .clk_2_S_in ( p3482 ) , .clk_2_W_in ( p2308 ) , + .clk_1_W_out ( clk_1_wires[79] ) , .clk_2_N_in ( p3469 ) , + .clk_2_E_in ( p1199 ) , .clk_2_S_in ( p1164 ) , .clk_2_W_in ( p3523 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_3038 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_3039 ) , .clk_2_N_out ( SYNOPSYS_UNCONNECTED_3040 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_3041 ) , .clk_3_W_in ( p2460 ) , - .clk_3_E_in ( p468 ) , .clk_3_S_in ( p561 ) , .clk_3_N_in ( p1735 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_3041 ) , .clk_3_W_in ( p3530 ) , + .clk_3_E_in ( p58 ) , .clk_3_S_in ( p2126 ) , .clk_3_N_in ( p3449 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_3042 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_3043 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_3044 ) , @@ -112383,38 +116922,38 @@ sb_1__1_ sb_4__1_ ( .chanx_right_out ( sb_1__1__33_chanx_right_out ) , .chany_bottom_out ( sb_1__1__33_chany_bottom_out ) , .chanx_left_out ( sb_1__1__33_chanx_left_out ) , - .ccff_tail ( sb_1__1__33_ccff_tail ) , .Test_en_S_in ( p2501 ) , + .ccff_tail ( sb_1__1__33_ccff_tail ) , .Test_en_S_in ( p2597 ) , .Test_en_N_out ( SYNOPSYS_UNCONNECTED_3047 ) , .pReset_S_in ( SYNOPSYS_UNCONNECTED_3048 ) , .pReset_E_in ( pResetWires[78] ) , .pReset_W_in ( SYNOPSYS_UNCONNECTED_3049 ) , .pReset_N_out ( pResetWires[77] ) , .pReset_W_out ( pResetWires[75] ) , - .pReset_E_out ( SYNOPSYS_UNCONNECTED_3050 ) , .Reset_S_in ( p3431 ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_3050 ) , .Reset_S_in ( p2529 ) , .Reset_N_out ( SYNOPSYS_UNCONNECTED_3051 ) , - .prog_clk_0_N_in ( prog_clk_0_wires[144] ) , .prog_clk_1_N_in ( p1514 ) , - .prog_clk_1_S_in ( p557 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[144] ) , .prog_clk_1_N_in ( p1184 ) , + .prog_clk_1_S_in ( p1138 ) , .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_3052 ) , .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_3053 ) , - .prog_clk_2_N_in ( p3499 ) , .prog_clk_2_E_in ( p425 ) , - .prog_clk_2_S_in ( p5 ) , .prog_clk_2_W_in ( p1012 ) , + .prog_clk_2_N_in ( p3539 ) , .prog_clk_2_E_in ( p731 ) , + .prog_clk_2_S_in ( p1178 ) , .prog_clk_2_W_in ( p217 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_3054 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_3055 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_3056 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_3057 ) , - .prog_clk_3_W_in ( p2609 ) , .prog_clk_3_E_in ( p1266 ) , - .prog_clk_3_S_in ( p1535 ) , .prog_clk_3_N_in ( p3497 ) , + .prog_clk_3_W_in ( p3268 ) , .prog_clk_3_E_in ( p6 ) , + .prog_clk_3_S_in ( p99 ) , .prog_clk_3_N_in ( p3528 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_3058 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_3059 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_3060 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_3061 ) , .clk_1_N_in ( p1514 ) , - .clk_1_S_in ( p103 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_3062 ) , - .clk_1_W_out ( SYNOPSYS_UNCONNECTED_3063 ) , .clk_2_N_in ( p3327 ) , - .clk_2_E_in ( p647 ) , .clk_2_S_in ( p3421 ) , .clk_2_W_in ( p2542 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_3061 ) , .clk_1_N_in ( p1184 ) , + .clk_1_S_in ( p475 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_3062 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_3063 ) , .clk_2_N_in ( p3535 ) , + .clk_2_E_in ( p862 ) , .clk_2_S_in ( p1302 ) , .clk_2_W_in ( p3197 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_3064 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_3065 ) , .clk_2_N_out ( SYNOPSYS_UNCONNECTED_3066 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_3067 ) , .clk_3_W_in ( p2609 ) , - .clk_3_E_in ( p406 ) , .clk_3_S_in ( p511 ) , .clk_3_N_in ( p3300 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_3067 ) , .clk_3_W_in ( p1936 ) , + .clk_3_E_in ( p1189 ) , .clk_3_S_in ( p2389 ) , .clk_3_N_in ( p3522 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_3068 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_3069 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_3070 ) , @@ -112462,16 +117001,16 @@ sb_1__1_ sb_4__2_ ( .chanx_right_out ( sb_1__1__34_chanx_right_out ) , .chany_bottom_out ( sb_1__1__34_chany_bottom_out ) , .chanx_left_out ( sb_1__1__34_chanx_left_out ) , - .ccff_tail ( sb_1__1__34_ccff_tail ) , .Test_en_S_in ( p2840 ) , + .ccff_tail ( sb_1__1__34_ccff_tail ) , .Test_en_S_in ( p2348 ) , .Test_en_N_out ( SYNOPSYS_UNCONNECTED_3073 ) , .pReset_S_in ( SYNOPSYS_UNCONNECTED_3074 ) , .pReset_E_in ( pResetWires[127] ) , .pReset_W_in ( SYNOPSYS_UNCONNECTED_3075 ) , .pReset_N_out ( pResetWires[126] ) , .pReset_W_out ( pResetWires[124] ) , - .pReset_E_out ( SYNOPSYS_UNCONNECTED_3076 ) , .Reset_S_in ( p2840 ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_3076 ) , .Reset_S_in ( p2348 ) , .Reset_N_out ( SYNOPSYS_UNCONNECTED_3077 ) , - .prog_clk_0_N_in ( prog_clk_0_wires[147] ) , .prog_clk_1_N_in ( p1824 ) , - .prog_clk_1_S_in ( p374 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[147] ) , .prog_clk_1_N_in ( p1541 ) , + .prog_clk_1_S_in ( p1114 ) , .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_3078 ) , .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_3079 ) , .prog_clk_2_N_in ( prog_clk_3_wires[25] ) , @@ -112481,14 +117020,14 @@ sb_1__1_ sb_4__2_ ( .prog_clk_2_W_out ( prog_clk_2_wires[27] ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_3083 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_3084 ) , - .prog_clk_2_E_out ( prog_clk_2_wires[25] ) , .prog_clk_3_W_in ( p2500 ) , - .prog_clk_3_E_in ( p596 ) , .prog_clk_3_S_in ( p117 ) , - .prog_clk_3_N_in ( p118 ) , + .prog_clk_2_E_out ( prog_clk_2_wires[25] ) , .prog_clk_3_W_in ( p1258 ) , + .prog_clk_3_E_in ( p532 ) , .prog_clk_3_S_in ( p107 ) , + .prog_clk_3_N_in ( p340 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_3085 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_3086 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_3087 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_3088 ) , .clk_1_N_in ( p1824 ) , - .clk_1_S_in ( p662 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_3089 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_3088 ) , .clk_1_N_in ( p1541 ) , + .clk_1_S_in ( p548 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_3089 ) , .clk_1_W_out ( SYNOPSYS_UNCONNECTED_3090 ) , .clk_2_N_in ( clk_3_wires[25] ) , .clk_2_E_in ( SYNOPSYS_UNCONNECTED_3091 ) , @@ -112497,8 +117036,8 @@ sb_1__1_ sb_4__2_ ( .clk_2_W_out ( clk_2_wires[27] ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_3094 ) , .clk_2_N_out ( SYNOPSYS_UNCONNECTED_3095 ) , - .clk_2_E_out ( clk_2_wires[25] ) , .clk_3_W_in ( p2500 ) , - .clk_3_E_in ( p1631 ) , .clk_3_S_in ( p2718 ) , .clk_3_N_in ( p1665 ) , + .clk_2_E_out ( clk_2_wires[25] ) , .clk_3_W_in ( p1258 ) , + .clk_3_E_in ( p1717 ) , .clk_3_S_in ( p2139 ) , .clk_3_N_in ( p845 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_3096 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_3097 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_3098 ) , @@ -112546,20 +117085,20 @@ sb_1__1_ sb_4__3_ ( .chanx_right_out ( sb_1__1__35_chanx_right_out ) , .chany_bottom_out ( sb_1__1__35_chany_bottom_out ) , .chanx_left_out ( sb_1__1__35_chanx_left_out ) , - .ccff_tail ( sb_1__1__35_ccff_tail ) , .Test_en_S_in ( p2843 ) , + .ccff_tail ( sb_1__1__35_ccff_tail ) , .Test_en_S_in ( p2024 ) , .Test_en_N_out ( SYNOPSYS_UNCONNECTED_3101 ) , .pReset_S_in ( SYNOPSYS_UNCONNECTED_3102 ) , .pReset_E_in ( pResetWires[176] ) , .pReset_W_in ( SYNOPSYS_UNCONNECTED_3103 ) , .pReset_N_out ( pResetWires[175] ) , .pReset_W_out ( pResetWires[173] ) , - .pReset_E_out ( SYNOPSYS_UNCONNECTED_3104 ) , .Reset_S_in ( p2985 ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_3104 ) , .Reset_S_in ( p2024 ) , .Reset_N_out ( SYNOPSYS_UNCONNECTED_3105 ) , - .prog_clk_0_N_in ( prog_clk_0_wires[150] ) , .prog_clk_1_N_in ( p1374 ) , - .prog_clk_1_S_in ( p543 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[150] ) , .prog_clk_1_N_in ( p1442 ) , + .prog_clk_1_S_in ( p1052 ) , .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_3106 ) , .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_3107 ) , - .prog_clk_2_N_in ( p2446 ) , .prog_clk_2_E_in ( p402 ) , - .prog_clk_2_S_in ( p1995 ) , .prog_clk_2_W_in ( p964 ) , + .prog_clk_2_N_in ( p1563 ) , .prog_clk_2_E_in ( p811 ) , + .prog_clk_2_S_in ( p201 ) , .prog_clk_2_W_in ( p1049 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_3108 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_3109 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_3110 ) , @@ -112571,10 +117110,10 @@ sb_1__1_ sb_4__3_ ( .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_3115 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_3116 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_3117 ) , - .prog_clk_3_S_out ( prog_clk_3_wires[24] ) , .clk_1_N_in ( p1374 ) , - .clk_1_S_in ( p149 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_3118 ) , - .clk_1_W_out ( SYNOPSYS_UNCONNECTED_3119 ) , .clk_2_N_in ( p1807 ) , - .clk_2_E_in ( p73 ) , .clk_2_S_in ( p2898 ) , .clk_2_W_in ( p92 ) , + .prog_clk_3_S_out ( prog_clk_3_wires[24] ) , .clk_1_N_in ( p1442 ) , + .clk_1_S_in ( p121 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_3118 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_3119 ) , .clk_2_N_in ( p1563 ) , + .clk_2_E_in ( p123 ) , .clk_2_S_in ( p1712 ) , .clk_2_W_in ( p492 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_3120 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_3121 ) , .clk_2_N_out ( SYNOPSYS_UNCONNECTED_3122 ) , @@ -112630,16 +117169,16 @@ sb_1__1_ sb_4__4_ ( .chanx_right_out ( sb_1__1__36_chanx_right_out ) , .chany_bottom_out ( sb_1__1__36_chany_bottom_out ) , .chanx_left_out ( sb_1__1__36_chanx_left_out ) , - .ccff_tail ( sb_1__1__36_ccff_tail ) , .Test_en_S_in ( p2102 ) , + .ccff_tail ( sb_1__1__36_ccff_tail ) , .Test_en_S_in ( p1954 ) , .Test_en_N_out ( SYNOPSYS_UNCONNECTED_3131 ) , .pReset_S_in ( SYNOPSYS_UNCONNECTED_3132 ) , .pReset_E_in ( pResetWires[225] ) , .pReset_W_in ( SYNOPSYS_UNCONNECTED_3133 ) , .pReset_N_out ( pResetWires[224] ) , .pReset_W_out ( pResetWires[222] ) , - .pReset_E_out ( SYNOPSYS_UNCONNECTED_3134 ) , .Reset_S_in ( p2102 ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_3134 ) , .Reset_S_in ( p1954 ) , .Reset_N_out ( SYNOPSYS_UNCONNECTED_3135 ) , - .prog_clk_0_N_in ( prog_clk_0_wires[153] ) , .prog_clk_1_N_in ( p1584 ) , - .prog_clk_1_S_in ( p1024 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[153] ) , .prog_clk_1_N_in ( p1029 ) , + .prog_clk_1_S_in ( p1754 ) , .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_3136 ) , .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_3137 ) , .prog_clk_2_N_in ( prog_clk_3_wires[15] ) , @@ -112657,8 +117196,8 @@ sb_1__1_ sb_4__4_ ( .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_3146 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_3147 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_3148 ) , - .prog_clk_3_S_out ( prog_clk_3_wires[20] ) , .clk_1_N_in ( p1584 ) , - .clk_1_S_in ( p1980 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_3149 ) , + .prog_clk_3_S_out ( prog_clk_3_wires[20] ) , .clk_1_N_in ( p1029 ) , + .clk_1_S_in ( p1054 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_3149 ) , .clk_1_W_out ( SYNOPSYS_UNCONNECTED_3150 ) , .clk_2_N_in ( clk_3_wires[15] ) , .clk_2_E_in ( SYNOPSYS_UNCONNECTED_3151 ) , @@ -112719,20 +117258,20 @@ sb_1__1_ sb_4__5_ ( .chanx_right_out ( sb_1__1__37_chanx_right_out ) , .chany_bottom_out ( sb_1__1__37_chany_bottom_out ) , .chanx_left_out ( sb_1__1__37_chanx_left_out ) , - .ccff_tail ( sb_1__1__37_ccff_tail ) , .Test_en_S_in ( p2859 ) , + .ccff_tail ( sb_1__1__37_ccff_tail ) , .Test_en_S_in ( p1968 ) , .Test_en_N_out ( SYNOPSYS_UNCONNECTED_3163 ) , .pReset_S_in ( SYNOPSYS_UNCONNECTED_3164 ) , .pReset_E_in ( pResetWires[274] ) , .pReset_W_in ( SYNOPSYS_UNCONNECTED_3165 ) , .pReset_N_out ( pResetWires[273] ) , .pReset_W_out ( pResetWires[271] ) , - .pReset_E_out ( SYNOPSYS_UNCONNECTED_3166 ) , .Reset_S_in ( p3101 ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_3166 ) , .Reset_S_in ( p1968 ) , .Reset_N_out ( SYNOPSYS_UNCONNECTED_3167 ) , - .prog_clk_0_N_in ( prog_clk_0_wires[156] ) , .prog_clk_1_N_in ( p1448 ) , - .prog_clk_1_S_in ( p192 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[156] ) , .prog_clk_1_N_in ( p1854 ) , + .prog_clk_1_S_in ( p163 ) , .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_3168 ) , .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_3169 ) , - .prog_clk_2_N_in ( p1600 ) , .prog_clk_2_E_in ( p900 ) , - .prog_clk_2_S_in ( p563 ) , .prog_clk_2_W_in ( p520 ) , + .prog_clk_2_N_in ( p2355 ) , .prog_clk_2_E_in ( p458 ) , + .prog_clk_2_S_in ( p768 ) , .prog_clk_2_W_in ( p311 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_3170 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_3171 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_3172 ) , @@ -112744,10 +117283,10 @@ sb_1__1_ sb_4__5_ ( .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_3177 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_3178 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_3179 ) , - .prog_clk_3_S_out ( prog_clk_3_wires[14] ) , .clk_1_N_in ( p1448 ) , - .clk_1_S_in ( p130 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_3180 ) , - .clk_1_W_out ( SYNOPSYS_UNCONNECTED_3181 ) , .clk_2_N_in ( p1501 ) , - .clk_2_E_in ( p508 ) , .clk_2_S_in ( p3021 ) , .clk_2_W_in ( p593 ) , + .prog_clk_3_S_out ( prog_clk_3_wires[14] ) , .clk_1_N_in ( p1854 ) , + .clk_1_S_in ( p959 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_3180 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_3181 ) , .clk_2_N_in ( p1915 ) , + .clk_2_E_in ( p820 ) , .clk_2_S_in ( p1725 ) , .clk_2_W_in ( p736 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_3182 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_3183 ) , .clk_2_N_out ( SYNOPSYS_UNCONNECTED_3184 ) , @@ -112803,20 +117342,20 @@ sb_1__1_ sb_4__6_ ( .chanx_right_out ( sb_1__1__38_chanx_right_out ) , .chany_bottom_out ( sb_1__1__38_chany_bottom_out ) , .chanx_left_out ( sb_1__1__38_chanx_left_out ) , - .ccff_tail ( sb_1__1__38_ccff_tail ) , .Test_en_S_in ( p2969 ) , + .ccff_tail ( sb_1__1__38_ccff_tail ) , .Test_en_S_in ( p1926 ) , .Test_en_N_out ( SYNOPSYS_UNCONNECTED_3193 ) , .pReset_S_in ( SYNOPSYS_UNCONNECTED_3194 ) , .pReset_E_in ( pResetWires[323] ) , .pReset_W_in ( SYNOPSYS_UNCONNECTED_3195 ) , .pReset_N_out ( pResetWires[322] ) , .pReset_W_out ( pResetWires[320] ) , - .pReset_E_out ( SYNOPSYS_UNCONNECTED_3196 ) , .Reset_S_in ( p3311 ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_3196 ) , .Reset_S_in ( p1926 ) , .Reset_N_out ( SYNOPSYS_UNCONNECTED_3197 ) , - .prog_clk_0_N_in ( prog_clk_0_wires[159] ) , .prog_clk_1_N_in ( p1553 ) , - .prog_clk_1_S_in ( p461 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[159] ) , .prog_clk_1_N_in ( p1831 ) , + .prog_clk_1_S_in ( p1136 ) , .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_3198 ) , .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_3199 ) , - .prog_clk_2_N_in ( p2646 ) , .prog_clk_2_E_in ( p1001 ) , - .prog_clk_2_S_in ( p125 ) , .prog_clk_2_W_in ( p304 ) , + .prog_clk_2_N_in ( p2567 ) , .prog_clk_2_E_in ( p247 ) , + .prog_clk_2_S_in ( p1807 ) , .prog_clk_2_W_in ( p1690 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_3200 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_3201 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_3202 ) , @@ -112828,10 +117367,10 @@ sb_1__1_ sb_4__6_ ( .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_3207 ) , .prog_clk_3_W_out ( prog_clk_3_wires[46] ) , .prog_clk_3_N_out ( prog_clk_3_wires[8] ) , - .prog_clk_3_S_out ( prog_clk_3_wires[10] ) , .clk_1_N_in ( p1553 ) , - .clk_1_S_in ( p355 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_3208 ) , - .clk_1_W_out ( SYNOPSYS_UNCONNECTED_3209 ) , .clk_2_N_in ( p2472 ) , - .clk_2_E_in ( p215 ) , .clk_2_S_in ( p3286 ) , .clk_2_W_in ( p1198 ) , + .prog_clk_3_S_out ( prog_clk_3_wires[10] ) , .clk_1_N_in ( p1831 ) , + .clk_1_S_in ( p93 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_3208 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_3209 ) , .clk_2_N_in ( p2578 ) , + .clk_2_E_in ( p140 ) , .clk_2_S_in ( p1687 ) , .clk_2_W_in ( p231 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_3210 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_3211 ) , .clk_2_N_out ( SYNOPSYS_UNCONNECTED_3212 ) , @@ -112886,20 +117425,20 @@ sb_1__1_ sb_4__7_ ( .chanx_right_out ( sb_1__1__39_chanx_right_out ) , .chany_bottom_out ( sb_1__1__39_chany_bottom_out ) , .chanx_left_out ( sb_1__1__39_chanx_left_out ) , - .ccff_tail ( sb_1__1__39_ccff_tail ) , .Test_en_S_in ( p2237 ) , + .ccff_tail ( sb_1__1__39_ccff_tail ) , .Test_en_S_in ( p2210 ) , .Test_en_N_out ( SYNOPSYS_UNCONNECTED_3219 ) , .pReset_S_in ( SYNOPSYS_UNCONNECTED_3220 ) , .pReset_E_in ( pResetWires[372] ) , .pReset_W_in ( SYNOPSYS_UNCONNECTED_3221 ) , .pReset_N_out ( pResetWires[371] ) , .pReset_W_out ( pResetWires[369] ) , - .pReset_E_out ( SYNOPSYS_UNCONNECTED_3222 ) , .Reset_S_in ( p3243 ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_3222 ) , .Reset_S_in ( p2210 ) , .Reset_N_out ( SYNOPSYS_UNCONNECTED_3223 ) , - .prog_clk_0_N_in ( prog_clk_0_wires[162] ) , .prog_clk_1_N_in ( p1487 ) , - .prog_clk_1_S_in ( p512 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[162] ) , .prog_clk_1_N_in ( p1301 ) , + .prog_clk_1_S_in ( p1168 ) , .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_3224 ) , .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_3225 ) , - .prog_clk_2_N_in ( p2847 ) , .prog_clk_2_E_in ( p1195 ) , - .prog_clk_2_S_in ( p2010 ) , .prog_clk_2_W_in ( p1083 ) , + .prog_clk_2_N_in ( p1866 ) , .prog_clk_2_E_in ( p670 ) , + .prog_clk_2_S_in ( p2059 ) , .prog_clk_2_W_in ( p180 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_3226 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_3227 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_3228 ) , @@ -112911,10 +117450,10 @@ sb_1__1_ sb_4__7_ ( .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_3233 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_3234 ) , .prog_clk_3_N_out ( prog_clk_3_wires[12] ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_3235 ) , .clk_1_N_in ( p1487 ) , - .clk_1_S_in ( p973 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_3236 ) , - .clk_1_W_out ( SYNOPSYS_UNCONNECTED_3237 ) , .clk_2_N_in ( p2174 ) , - .clk_2_E_in ( p235 ) , .clk_2_S_in ( p3221 ) , .clk_2_W_in ( p153 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_3235 ) , .clk_1_N_in ( p1301 ) , + .clk_1_S_in ( p375 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_3236 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_3237 ) , .clk_2_N_in ( p1866 ) , + .clk_2_E_in ( p307 ) , .clk_2_S_in ( p2169 ) , .clk_2_W_in ( p829 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_3238 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_3239 ) , .clk_2_N_out ( SYNOPSYS_UNCONNECTED_3240 ) , @@ -112970,16 +117509,16 @@ sb_1__1_ sb_4__8_ ( .chanx_right_out ( sb_1__1__40_chanx_right_out ) , .chany_bottom_out ( sb_1__1__40_chany_bottom_out ) , .chanx_left_out ( sb_1__1__40_chanx_left_out ) , - .ccff_tail ( sb_1__1__40_ccff_tail ) , .Test_en_S_in ( p1882 ) , + .ccff_tail ( sb_1__1__40_ccff_tail ) , .Test_en_S_in ( p1420 ) , .Test_en_N_out ( SYNOPSYS_UNCONNECTED_3249 ) , .pReset_S_in ( SYNOPSYS_UNCONNECTED_3250 ) , .pReset_E_in ( pResetWires[421] ) , .pReset_W_in ( SYNOPSYS_UNCONNECTED_3251 ) , .pReset_N_out ( pResetWires[420] ) , .pReset_W_out ( pResetWires[418] ) , - .pReset_E_out ( SYNOPSYS_UNCONNECTED_3252 ) , .Reset_S_in ( p1882 ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_3252 ) , .Reset_S_in ( p1420 ) , .Reset_N_out ( SYNOPSYS_UNCONNECTED_3253 ) , - .prog_clk_0_N_in ( prog_clk_0_wires[165] ) , .prog_clk_1_N_in ( p1849 ) , - .prog_clk_1_S_in ( p892 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[165] ) , .prog_clk_1_N_in ( p1495 ) , + .prog_clk_1_S_in ( p1197 ) , .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_3254 ) , .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_3255 ) , .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_3256 ) , @@ -112997,8 +117536,8 @@ sb_1__1_ sb_4__8_ ( .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_3264 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_3265 ) , .prog_clk_3_N_out ( prog_clk_3_wires[18] ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_3266 ) , .clk_1_N_in ( p1764 ) , - .clk_1_S_in ( p1654 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_3267 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_3266 ) , .clk_1_N_in ( p1495 ) , + .clk_1_S_in ( p166 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_3267 ) , .clk_1_W_out ( SYNOPSYS_UNCONNECTED_3268 ) , .clk_2_N_in ( SYNOPSYS_UNCONNECTED_3269 ) , .clk_2_E_in ( SYNOPSYS_UNCONNECTED_3270 ) , @@ -113059,20 +117598,20 @@ sb_1__1_ sb_4__9_ ( .chanx_right_out ( sb_1__1__41_chanx_right_out ) , .chany_bottom_out ( sb_1__1__41_chany_bottom_out ) , .chanx_left_out ( sb_1__1__41_chanx_left_out ) , - .ccff_tail ( sb_1__1__41_ccff_tail ) , .Test_en_S_in ( p2989 ) , + .ccff_tail ( sb_1__1__41_ccff_tail ) , .Test_en_S_in ( p2295 ) , .Test_en_N_out ( SYNOPSYS_UNCONNECTED_3281 ) , .pReset_S_in ( SYNOPSYS_UNCONNECTED_3282 ) , .pReset_E_in ( pResetWires[470] ) , .pReset_W_in ( SYNOPSYS_UNCONNECTED_3283 ) , .pReset_N_out ( pResetWires[469] ) , .pReset_W_out ( pResetWires[467] ) , - .pReset_E_out ( SYNOPSYS_UNCONNECTED_3284 ) , .Reset_S_in ( p2989 ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_3284 ) , .Reset_S_in ( p2295 ) , .Reset_N_out ( SYNOPSYS_UNCONNECTED_3285 ) , - .prog_clk_0_N_in ( prog_clk_0_wires[168] ) , .prog_clk_1_N_in ( p1335 ) , - .prog_clk_1_S_in ( p714 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[168] ) , .prog_clk_1_N_in ( p1631 ) , + .prog_clk_1_S_in ( p198 ) , .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_3286 ) , .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_3287 ) , - .prog_clk_2_N_in ( p2674 ) , .prog_clk_2_E_in ( p766 ) , - .prog_clk_2_S_in ( p1740 ) , .prog_clk_2_W_in ( p1089 ) , + .prog_clk_2_N_in ( p2550 ) , .prog_clk_2_E_in ( p706 ) , + .prog_clk_2_S_in ( p515 ) , .prog_clk_2_W_in ( p218 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_3288 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_3289 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_3290 ) , @@ -113084,10 +117623,10 @@ sb_1__1_ sb_4__9_ ( .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_3295 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_3296 ) , .prog_clk_3_N_out ( prog_clk_3_wires[22] ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_3297 ) , .clk_1_N_in ( p1335 ) , - .clk_1_S_in ( p298 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_3298 ) , - .clk_1_W_out ( SYNOPSYS_UNCONNECTED_3299 ) , .clk_2_N_in ( p2484 ) , - .clk_2_E_in ( p224 ) , .clk_2_S_in ( p2891 ) , .clk_2_W_in ( p295 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_3297 ) , .clk_1_N_in ( p1631 ) , + .clk_1_S_in ( p1096 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_3298 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_3299 ) , .clk_2_N_in ( p2550 ) , + .clk_2_E_in ( p48 ) , .clk_2_S_in ( p2082 ) , .clk_2_W_in ( p566 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_3300 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_3301 ) , .clk_2_N_out ( SYNOPSYS_UNCONNECTED_3302 ) , @@ -113143,16 +117682,16 @@ sb_1__1_ sb_4__10_ ( .chanx_right_out ( sb_1__1__42_chanx_right_out ) , .chany_bottom_out ( sb_1__1__42_chany_bottom_out ) , .chanx_left_out ( sb_1__1__42_chanx_left_out ) , - .ccff_tail ( sb_1__1__42_ccff_tail ) , .Test_en_S_in ( p2170 ) , + .ccff_tail ( sb_1__1__42_ccff_tail ) , .Test_en_S_in ( p2361 ) , .Test_en_N_out ( SYNOPSYS_UNCONNECTED_3311 ) , .pReset_S_in ( SYNOPSYS_UNCONNECTED_3312 ) , .pReset_E_in ( pResetWires[519] ) , .pReset_W_in ( SYNOPSYS_UNCONNECTED_3313 ) , .pReset_N_out ( pResetWires[518] ) , .pReset_W_out ( pResetWires[516] ) , - .pReset_E_out ( SYNOPSYS_UNCONNECTED_3314 ) , .Reset_S_in ( p2170 ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_3314 ) , .Reset_S_in ( p2361 ) , .Reset_N_out ( SYNOPSYS_UNCONNECTED_3315 ) , - .prog_clk_0_N_in ( prog_clk_0_wires[171] ) , .prog_clk_1_N_in ( p1403 ) , - .prog_clk_1_S_in ( p176 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[171] ) , .prog_clk_1_N_in ( p1984 ) , + .prog_clk_1_S_in ( p256 ) , .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_3316 ) , .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_3317 ) , .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_3318 ) , @@ -113162,14 +117701,14 @@ sb_1__1_ sb_4__10_ ( .prog_clk_2_W_out ( prog_clk_2_wires[62] ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_3321 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_3322 ) , - .prog_clk_2_E_out ( prog_clk_2_wires[60] ) , .prog_clk_3_W_in ( p1934 ) , - .prog_clk_3_E_in ( p249 ) , .prog_clk_3_S_in ( p328 ) , - .prog_clk_3_N_in ( p945 ) , + .prog_clk_2_E_out ( prog_clk_2_wires[60] ) , .prog_clk_3_W_in ( p1602 ) , + .prog_clk_3_E_in ( p726 ) , .prog_clk_3_S_in ( p363 ) , + .prog_clk_3_N_in ( p493 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_3323 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_3324 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_3325 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_3326 ) , .clk_1_N_in ( p1403 ) , - .clk_1_S_in ( p1099 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_3327 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_3326 ) , .clk_1_N_in ( p1984 ) , + .clk_1_S_in ( p990 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_3327 ) , .clk_1_W_out ( SYNOPSYS_UNCONNECTED_3328 ) , .clk_2_N_in ( SYNOPSYS_UNCONNECTED_3329 ) , .clk_2_E_in ( SYNOPSYS_UNCONNECTED_3330 ) , @@ -113178,8 +117717,8 @@ sb_1__1_ sb_4__10_ ( .clk_2_W_out ( clk_2_wires[62] ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_3332 ) , .clk_2_N_out ( SYNOPSYS_UNCONNECTED_3333 ) , - .clk_2_E_out ( clk_2_wires[60] ) , .clk_3_W_in ( p1934 ) , - .clk_3_E_in ( p1992 ) , .clk_3_S_in ( p1973 ) , .clk_3_N_in ( p97 ) , + .clk_2_E_out ( clk_2_wires[60] ) , .clk_3_W_in ( p1602 ) , + .clk_3_E_in ( p202 ) , .clk_3_S_in ( p2081 ) , .clk_3_N_in ( p1658 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_3334 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_3335 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_3336 ) , @@ -113227,38 +117766,38 @@ sb_1__1_ sb_4__11_ ( .chanx_right_out ( sb_1__1__43_chanx_right_out ) , .chany_bottom_out ( sb_1__1__43_chany_bottom_out ) , .chanx_left_out ( sb_1__1__43_chanx_left_out ) , - .ccff_tail ( sb_1__1__43_ccff_tail ) , .Test_en_S_in ( p3240 ) , + .ccff_tail ( sb_1__1__43_ccff_tail ) , .Test_en_S_in ( p2009 ) , .Test_en_N_out ( SYNOPSYS_UNCONNECTED_3339 ) , .pReset_S_in ( SYNOPSYS_UNCONNECTED_3340 ) , .pReset_E_in ( pResetWires[568] ) , .pReset_W_in ( SYNOPSYS_UNCONNECTED_3341 ) , .pReset_N_out ( pResetWires[567] ) , .pReset_W_out ( pResetWires[565] ) , - .pReset_E_out ( SYNOPSYS_UNCONNECTED_3342 ) , .Reset_S_in ( p3240 ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_3342 ) , .Reset_S_in ( p2009 ) , .Reset_N_out ( SYNOPSYS_UNCONNECTED_3343 ) , - .prog_clk_0_N_in ( prog_clk_0_wires[174] ) , .prog_clk_1_N_in ( p1848 ) , - .prog_clk_1_S_in ( p746 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[174] ) , .prog_clk_1_N_in ( p2228 ) , + .prog_clk_1_S_in ( p470 ) , .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_3344 ) , .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_3345 ) , - .prog_clk_2_N_in ( p3090 ) , .prog_clk_2_E_in ( p889 ) , - .prog_clk_2_S_in ( p494 ) , .prog_clk_2_W_in ( p1271 ) , + .prog_clk_2_N_in ( p3608 ) , .prog_clk_2_E_in ( p298 ) , + .prog_clk_2_S_in ( p600 ) , .prog_clk_2_W_in ( p115 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_3346 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_3347 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_3348 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_3349 ) , - .prog_clk_3_W_in ( p2668 ) , .prog_clk_3_E_in ( p426 ) , - .prog_clk_3_S_in ( p1340 ) , .prog_clk_3_N_in ( p3009 ) , + .prog_clk_3_W_in ( p2334 ) , .prog_clk_3_E_in ( p782 ) , + .prog_clk_3_S_in ( p1043 ) , .prog_clk_3_N_in ( p3606 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_3350 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_3351 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_3352 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_3353 ) , .clk_1_N_in ( p1848 ) , - .clk_1_S_in ( p459 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_3354 ) , - .clk_1_W_out ( SYNOPSYS_UNCONNECTED_3355 ) , .clk_2_N_in ( p3411 ) , - .clk_2_E_in ( p777 ) , .clk_2_S_in ( p3217 ) , .clk_2_W_in ( p2573 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_3353 ) , .clk_1_N_in ( p2228 ) , + .clk_1_S_in ( p1127 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_3354 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_3355 ) , .clk_2_N_in ( p3130 ) , + .clk_2_E_in ( p505 ) , .clk_2_S_in ( p182 ) , .clk_2_W_in ( p3549 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_3356 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_3357 ) , .clk_2_N_out ( SYNOPSYS_UNCONNECTED_3358 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_3359 ) , .clk_3_W_in ( p2668 ) , - .clk_3_E_in ( p523 ) , .clk_3_S_in ( p1262 ) , .clk_3_N_in ( p3390 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_3359 ) , .clk_3_W_in ( p3557 ) , + .clk_3_E_in ( p1195 ) , .clk_3_S_in ( p1688 ) , .clk_3_N_in ( p3093 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_3360 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_3361 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_3362 ) , @@ -113306,27 +117845,27 @@ sb_1__1_ sb_5__1_ ( .chanx_right_out ( sb_1__1__44_chanx_right_out ) , .chany_bottom_out ( sb_1__1__44_chany_bottom_out ) , .chanx_left_out ( sb_1__1__44_chanx_left_out ) , - .ccff_tail ( sb_1__1__44_ccff_tail ) , .Test_en_S_in ( p2496 ) , + .ccff_tail ( sb_1__1__44_ccff_tail ) , .Test_en_S_in ( p2633 ) , .Test_en_N_out ( SYNOPSYS_UNCONNECTED_3365 ) , .pReset_S_in ( SYNOPSYS_UNCONNECTED_3366 ) , .pReset_E_in ( pResetWires[82] ) , .pReset_W_in ( SYNOPSYS_UNCONNECTED_3367 ) , .pReset_N_out ( pResetWires[81] ) , .pReset_W_out ( pResetWires[79] ) , - .pReset_E_out ( SYNOPSYS_UNCONNECTED_3368 ) , .Reset_S_in ( p2496 ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_3368 ) , .Reset_S_in ( p2633 ) , .Reset_N_out ( SYNOPSYS_UNCONNECTED_3369 ) , .prog_clk_0_N_in ( prog_clk_0_wires[182] ) , .prog_clk_1_N_in ( prog_clk_2_wires[32] ) , .prog_clk_1_S_in ( SYNOPSYS_UNCONNECTED_3370 ) , .prog_clk_1_E_out ( prog_clk_1_wires[85] ) , - .prog_clk_1_W_out ( prog_clk_1_wires[86] ) , .prog_clk_2_N_in ( p3331 ) , - .prog_clk_2_E_in ( p1207 ) , .prog_clk_2_S_in ( p1242 ) , - .prog_clk_2_W_in ( p529 ) , + .prog_clk_1_W_out ( prog_clk_1_wires[86] ) , .prog_clk_2_N_in ( p2804 ) , + .prog_clk_2_E_in ( p135 ) , .prog_clk_2_S_in ( p715 ) , + .prog_clk_2_W_in ( p417 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_3371 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_3372 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_3373 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_3374 ) , - .prog_clk_3_W_in ( p3164 ) , .prog_clk_3_E_in ( p186 ) , - .prog_clk_3_S_in ( p654 ) , .prog_clk_3_N_in ( p3288 ) , + .prog_clk_3_W_in ( p2757 ) , .prog_clk_3_E_in ( p963 ) , + .prog_clk_3_S_in ( p1023 ) , .prog_clk_3_N_in ( p2656 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_3375 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_3376 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_3377 ) , @@ -113334,12 +117873,12 @@ sb_1__1_ sb_5__1_ ( .clk_1_N_in ( clk_2_wires[32] ) , .clk_1_S_in ( SYNOPSYS_UNCONNECTED_3379 ) , .clk_1_E_out ( clk_1_wires[85] ) , .clk_1_W_out ( clk_1_wires[86] ) , - .clk_2_N_in ( p3403 ) , .clk_2_E_in ( p865 ) , .clk_2_S_in ( p2346 ) , - .clk_2_W_in ( p3129 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_3380 ) , + .clk_2_N_in ( p3540 ) , .clk_2_E_in ( p308 ) , .clk_2_S_in ( p1381 ) , + .clk_2_W_in ( p3615 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_3380 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_3381 ) , .clk_2_N_out ( SYNOPSYS_UNCONNECTED_3382 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_3383 ) , .clk_3_W_in ( p3164 ) , - .clk_3_E_in ( p818 ) , .clk_3_S_in ( p276 ) , .clk_3_N_in ( p3393 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_3383 ) , .clk_3_W_in ( p3616 ) , + .clk_3_E_in ( p1202 ) , .clk_3_S_in ( p2397 ) , .clk_3_N_in ( p3525 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_3384 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_3385 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_3386 ) , @@ -113387,16 +117926,16 @@ sb_1__1_ sb_5__2_ ( .chanx_right_out ( sb_1__1__45_chanx_right_out ) , .chany_bottom_out ( sb_1__1__45_chany_bottom_out ) , .chanx_left_out ( sb_1__1__45_chanx_left_out ) , - .ccff_tail ( sb_1__1__45_ccff_tail ) , .Test_en_S_in ( p2938 ) , + .ccff_tail ( sb_1__1__45_ccff_tail ) , .Test_en_S_in ( p2222 ) , .Test_en_N_out ( SYNOPSYS_UNCONNECTED_3389 ) , .pReset_S_in ( SYNOPSYS_UNCONNECTED_3390 ) , .pReset_E_in ( pResetWires[131] ) , .pReset_W_in ( SYNOPSYS_UNCONNECTED_3391 ) , .pReset_N_out ( pResetWires[130] ) , .pReset_W_out ( pResetWires[128] ) , - .pReset_E_out ( SYNOPSYS_UNCONNECTED_3392 ) , .Reset_S_in ( p2938 ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_3392 ) , .Reset_S_in ( p2222 ) , .Reset_N_out ( SYNOPSYS_UNCONNECTED_3393 ) , - .prog_clk_0_N_in ( prog_clk_0_wires[185] ) , .prog_clk_1_N_in ( p1525 ) , - .prog_clk_1_S_in ( p501 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[185] ) , .prog_clk_1_N_in ( p1370 ) , + .prog_clk_1_S_in ( p605 ) , .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_3394 ) , .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_3395 ) , .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_3396 ) , @@ -113407,13 +117946,13 @@ sb_1__1_ sb_5__2_ ( .prog_clk_2_S_out ( prog_clk_2_wires[31] ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_3400 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_3401 ) , - .prog_clk_3_W_in ( p1867 ) , .prog_clk_3_E_in ( p841 ) , - .prog_clk_3_S_in ( p429 ) , .prog_clk_3_N_in ( p551 ) , + .prog_clk_3_W_in ( p1538 ) , .prog_clk_3_E_in ( p94 ) , + .prog_clk_3_S_in ( p808 ) , .prog_clk_3_N_in ( p456 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_3402 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_3403 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_3404 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_3405 ) , .clk_1_N_in ( p1525 ) , - .clk_1_S_in ( p39 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_3406 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_3405 ) , .clk_1_N_in ( p1370 ) , + .clk_1_S_in ( p9 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_3406 ) , .clk_1_W_out ( SYNOPSYS_UNCONNECTED_3407 ) , .clk_2_N_in ( SYNOPSYS_UNCONNECTED_3408 ) , .clk_2_E_in ( SYNOPSYS_UNCONNECTED_3409 ) , @@ -113422,8 +117961,8 @@ sb_1__1_ sb_5__2_ ( .clk_2_W_out ( SYNOPSYS_UNCONNECTED_3411 ) , .clk_2_S_out ( clk_2_wires[31] ) , .clk_2_N_out ( SYNOPSYS_UNCONNECTED_3412 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_3413 ) , .clk_3_W_in ( p1867 ) , - .clk_3_E_in ( p108 ) , .clk_3_S_in ( p2896 ) , .clk_3_N_in ( p300 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_3413 ) , .clk_3_W_in ( p1538 ) , + .clk_3_E_in ( p564 ) , .clk_3_S_in ( p2068 ) , .clk_3_N_in ( p728 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_3414 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_3415 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_3416 ) , @@ -113471,27 +118010,27 @@ sb_1__1_ sb_5__3_ ( .chanx_right_out ( sb_1__1__46_chanx_right_out ) , .chany_bottom_out ( sb_1__1__46_chany_bottom_out ) , .chanx_left_out ( sb_1__1__46_chanx_left_out ) , - .ccff_tail ( sb_1__1__46_ccff_tail ) , .Test_en_S_in ( p2495 ) , + .ccff_tail ( sb_1__1__46_ccff_tail ) , .Test_en_S_in ( p2252 ) , .Test_en_N_out ( SYNOPSYS_UNCONNECTED_3419 ) , .pReset_S_in ( SYNOPSYS_UNCONNECTED_3420 ) , .pReset_E_in ( pResetWires[180] ) , .pReset_W_in ( SYNOPSYS_UNCONNECTED_3421 ) , .pReset_N_out ( pResetWires[179] ) , .pReset_W_out ( pResetWires[177] ) , - .pReset_E_out ( SYNOPSYS_UNCONNECTED_3422 ) , .Reset_S_in ( p2495 ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_3422 ) , .Reset_S_in ( p2252 ) , .Reset_N_out ( SYNOPSYS_UNCONNECTED_3423 ) , .prog_clk_0_N_in ( prog_clk_0_wires[188] ) , .prog_clk_1_N_in ( prog_clk_2_wires[45] ) , .prog_clk_1_S_in ( SYNOPSYS_UNCONNECTED_3424 ) , .prog_clk_1_E_out ( prog_clk_1_wires[92] ) , - .prog_clk_1_W_out ( prog_clk_1_wires[93] ) , .prog_clk_2_N_in ( p3326 ) , - .prog_clk_2_E_in ( p203 ) , .prog_clk_2_S_in ( p843 ) , - .prog_clk_2_W_in ( p331 ) , + .prog_clk_1_W_out ( prog_clk_1_wires[93] ) , .prog_clk_2_N_in ( p3602 ) , + .prog_clk_2_E_in ( p443 ) , .prog_clk_2_S_in ( p193 ) , + .prog_clk_2_W_in ( p784 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_3425 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_3426 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_3427 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_3428 ) , - .prog_clk_3_W_in ( p3069 ) , .prog_clk_3_E_in ( p987 ) , - .prog_clk_3_S_in ( p452 ) , .prog_clk_3_N_in ( p3287 ) , + .prog_clk_3_W_in ( p2624 ) , .prog_clk_3_E_in ( p763 ) , + .prog_clk_3_S_in ( p1181 ) , .prog_clk_3_N_in ( p3600 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_3429 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_3430 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_3431 ) , @@ -113499,12 +118038,12 @@ sb_1__1_ sb_5__3_ ( .clk_1_N_in ( clk_2_wires[45] ) , .clk_1_S_in ( SYNOPSYS_UNCONNECTED_3433 ) , .clk_1_E_out ( clk_1_wires[92] ) , .clk_1_W_out ( clk_1_wires[93] ) , - .clk_2_N_in ( p3430 ) , .clk_2_E_in ( p522 ) , .clk_2_S_in ( p2342 ) , - .clk_2_W_in ( p3028 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_3434 ) , + .clk_2_N_in ( p3141 ) , .clk_2_E_in ( p1059 ) , .clk_2_S_in ( p934 ) , + .clk_2_W_in ( p2906 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_3434 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_3435 ) , .clk_2_N_out ( SYNOPSYS_UNCONNECTED_3436 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_3437 ) , .clk_3_W_in ( p3069 ) , - .clk_3_E_in ( p769 ) , .clk_3_S_in ( p221 ) , .clk_3_N_in ( p3420 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_3437 ) , .clk_3_W_in ( p3029 ) , + .clk_3_E_in ( p225 ) , .clk_3_S_in ( p2109 ) , .clk_3_N_in ( p3038 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_3438 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_3439 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_3440 ) , @@ -113552,16 +118091,16 @@ sb_1__1_ sb_5__4_ ( .chanx_right_out ( sb_1__1__47_chanx_right_out ) , .chany_bottom_out ( sb_1__1__47_chany_bottom_out ) , .chanx_left_out ( sb_1__1__47_chanx_left_out ) , - .ccff_tail ( sb_1__1__47_ccff_tail ) , .Test_en_S_in ( p2407 ) , + .ccff_tail ( sb_1__1__47_ccff_tail ) , .Test_en_S_in ( p2605 ) , .Test_en_N_out ( SYNOPSYS_UNCONNECTED_3443 ) , .pReset_S_in ( SYNOPSYS_UNCONNECTED_3444 ) , .pReset_E_in ( pResetWires[229] ) , .pReset_W_in ( SYNOPSYS_UNCONNECTED_3445 ) , .pReset_N_out ( pResetWires[228] ) , .pReset_W_out ( pResetWires[226] ) , - .pReset_E_out ( SYNOPSYS_UNCONNECTED_3446 ) , .Reset_S_in ( p2407 ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_3446 ) , .Reset_S_in ( p2605 ) , .Reset_N_out ( SYNOPSYS_UNCONNECTED_3447 ) , - .prog_clk_0_N_in ( prog_clk_0_wires[191] ) , .prog_clk_1_N_in ( p684 ) , - .prog_clk_1_S_in ( p872 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[191] ) , .prog_clk_1_N_in ( p1937 ) , + .prog_clk_1_S_in ( p318 ) , .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_3448 ) , .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_3449 ) , .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_3450 ) , @@ -113572,13 +118111,13 @@ sb_1__1_ sb_5__4_ ( .prog_clk_2_S_out ( prog_clk_2_wires[44] ) , .prog_clk_2_N_out ( prog_clk_2_wires[42] ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_3454 ) , - .prog_clk_3_W_in ( p1590 ) , .prog_clk_3_E_in ( p560 ) , - .prog_clk_3_S_in ( p733 ) , .prog_clk_3_N_in ( p2534 ) , + .prog_clk_3_W_in ( p1498 ) , .prog_clk_3_E_in ( p336 ) , + .prog_clk_3_S_in ( p37 ) , .prog_clk_3_N_in ( p1675 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_3455 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_3456 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_3457 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_3458 ) , .clk_1_N_in ( p684 ) , - .clk_1_S_in ( p262 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_3459 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_3458 ) , .clk_1_N_in ( p1937 ) , + .clk_1_S_in ( p750 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_3459 ) , .clk_1_W_out ( SYNOPSYS_UNCONNECTED_3460 ) , .clk_2_N_in ( SYNOPSYS_UNCONNECTED_3461 ) , .clk_2_E_in ( SYNOPSYS_UNCONNECTED_3462 ) , @@ -113586,8 +118125,8 @@ sb_1__1_ sb_5__4_ ( .clk_2_W_in ( clk_2_wires[35] ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_3464 ) , .clk_2_S_out ( clk_2_wires[44] ) , .clk_2_N_out ( clk_2_wires[42] ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_3465 ) , .clk_3_W_in ( p1590 ) , - .clk_3_E_in ( p996 ) , .clk_3_S_in ( p2286 ) , .clk_3_N_in ( p802 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_3465 ) , .clk_3_W_in ( p1498 ) , + .clk_3_E_in ( p294 ) , .clk_3_S_in ( p2405 ) , .clk_3_N_in ( p1757 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_3466 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_3467 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_3468 ) , @@ -113635,40 +118174,40 @@ sb_1__1_ sb_5__5_ ( .chanx_right_out ( sb_1__1__48_chanx_right_out ) , .chany_bottom_out ( sb_1__1__48_chany_bottom_out ) , .chanx_left_out ( sb_1__1__48_chanx_left_out ) , - .ccff_tail ( sb_1__1__48_ccff_tail ) , .Test_en_S_in ( p2816 ) , + .ccff_tail ( sb_1__1__48_ccff_tail ) , .Test_en_S_in ( p2528 ) , .Test_en_N_out ( SYNOPSYS_UNCONNECTED_3471 ) , .pReset_S_in ( SYNOPSYS_UNCONNECTED_3472 ) , .pReset_E_in ( pResetWires[278] ) , .pReset_W_in ( SYNOPSYS_UNCONNECTED_3473 ) , .pReset_N_out ( pResetWires[277] ) , .pReset_W_out ( pResetWires[275] ) , - .pReset_E_out ( SYNOPSYS_UNCONNECTED_3474 ) , .Reset_S_in ( p3307 ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_3474 ) , .Reset_S_in ( p2528 ) , .Reset_N_out ( SYNOPSYS_UNCONNECTED_3475 ) , .prog_clk_0_N_in ( prog_clk_0_wires[194] ) , .prog_clk_1_N_in ( SYNOPSYS_UNCONNECTED_3476 ) , .prog_clk_1_S_in ( prog_clk_2_wires[43] ) , .prog_clk_1_E_out ( prog_clk_1_wires[99] ) , - .prog_clk_1_W_out ( prog_clk_1_wires[100] ) , .prog_clk_2_N_in ( p3486 ) , - .prog_clk_2_E_in ( p613 ) , .prog_clk_2_S_in ( p1150 ) , - .prog_clk_2_W_in ( p3 ) , + .prog_clk_1_W_out ( prog_clk_1_wires[100] ) , .prog_clk_2_N_in ( p3417 ) , + .prog_clk_2_E_in ( p529 ) , .prog_clk_2_S_in ( p1261 ) , + .prog_clk_2_W_in ( p172 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_3477 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_3478 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_3479 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_3480 ) , - .prog_clk_3_W_in ( p2168 ) , .prog_clk_3_E_in ( p1378 ) , - .prog_clk_3_S_in ( p284 ) , .prog_clk_3_N_in ( p3485 ) , + .prog_clk_3_W_in ( p3342 ) , .prog_clk_3_E_in ( p996 ) , + .prog_clk_3_S_in ( p656 ) , .prog_clk_3_N_in ( p3363 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_3481 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_3482 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_3483 ) , .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_3484 ) , .clk_1_N_in ( SYNOPSYS_UNCONNECTED_3485 ) , .clk_1_S_in ( clk_2_wires[43] ) , .clk_1_E_out ( clk_1_wires[99] ) , - .clk_1_W_out ( clk_1_wires[100] ) , .clk_2_N_in ( p2037 ) , - .clk_2_E_in ( p992 ) , .clk_2_S_in ( p3290 ) , .clk_2_W_in ( p2018 ) , + .clk_1_W_out ( clk_1_wires[100] ) , .clk_2_N_in ( p3571 ) , + .clk_2_E_in ( p1007 ) , .clk_2_S_in ( p18 ) , .clk_2_W_in ( p3310 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_3486 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_3487 ) , .clk_2_N_out ( SYNOPSYS_UNCONNECTED_3488 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_3489 ) , .clk_3_W_in ( p2168 ) , - .clk_3_E_in ( p263 ) , .clk_3_S_in ( p66 ) , .clk_3_N_in ( p2073 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_3489 ) , .clk_3_W_in ( p2961 ) , + .clk_3_E_in ( p277 ) , .clk_3_S_in ( p2417 ) , .clk_3_N_in ( p3570 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_3490 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_3491 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_3492 ) , @@ -113716,20 +118255,20 @@ sb_1__1_ sb_5__6_ ( .chanx_right_out ( sb_1__1__49_chanx_right_out ) , .chany_bottom_out ( sb_1__1__49_chany_bottom_out ) , .chanx_left_out ( sb_1__1__49_chanx_left_out ) , - .ccff_tail ( sb_1__1__49_ccff_tail ) , .Test_en_S_in ( p2514 ) , + .ccff_tail ( sb_1__1__49_ccff_tail ) , .Test_en_S_in ( p1928 ) , .Test_en_N_out ( SYNOPSYS_UNCONNECTED_3495 ) , .pReset_S_in ( SYNOPSYS_UNCONNECTED_3496 ) , .pReset_E_in ( pResetWires[327] ) , .pReset_W_in ( SYNOPSYS_UNCONNECTED_3497 ) , .pReset_N_out ( pResetWires[326] ) , .pReset_W_out ( pResetWires[324] ) , - .pReset_E_out ( SYNOPSYS_UNCONNECTED_3498 ) , .Reset_S_in ( p2514 ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_3498 ) , .Reset_S_in ( p1928 ) , .Reset_N_out ( SYNOPSYS_UNCONNECTED_3499 ) , - .prog_clk_0_N_in ( prog_clk_0_wires[197] ) , .prog_clk_1_N_in ( p1346 ) , - .prog_clk_1_S_in ( p1078 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[197] ) , .prog_clk_1_N_in ( p2045 ) , + .prog_clk_1_S_in ( p4 ) , .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_3500 ) , .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_3501 ) , - .prog_clk_2_N_in ( p2846 ) , .prog_clk_2_E_in ( p537 ) , - .prog_clk_2_S_in ( p311 ) , .prog_clk_2_W_in ( p1357 ) , + .prog_clk_2_N_in ( p2535 ) , .prog_clk_2_E_in ( p501 ) , + .prog_clk_2_S_in ( p360 ) , .prog_clk_2_W_in ( p1714 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_3502 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_3503 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_3504 ) , @@ -113741,10 +118280,10 @@ sb_1__1_ sb_5__6_ ( .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_3509 ) , .prog_clk_3_W_out ( prog_clk_3_wires[6] ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_3510 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_3511 ) , .clk_1_N_in ( p1346 ) , - .clk_1_S_in ( p17 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_3512 ) , - .clk_1_W_out ( SYNOPSYS_UNCONNECTED_3513 ) , .clk_2_N_in ( p1510 ) , - .clk_2_E_in ( p202 ) , .clk_2_S_in ( p2273 ) , .clk_2_W_in ( p251 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_3511 ) , .clk_1_N_in ( p2045 ) , + .clk_1_S_in ( p1126 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_3512 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_3513 ) , .clk_2_N_in ( p2613 ) , + .clk_2_E_in ( p761 ) , .clk_2_S_in ( p1768 ) , .clk_2_W_in ( p660 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_3514 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_3515 ) , .clk_2_N_out ( SYNOPSYS_UNCONNECTED_3516 ) , @@ -113800,27 +118339,27 @@ sb_1__1_ sb_5__7_ ( .chanx_right_out ( sb_1__1__50_chanx_right_out ) , .chany_bottom_out ( sb_1__1__50_chany_bottom_out ) , .chanx_left_out ( sb_1__1__50_chanx_left_out ) , - .ccff_tail ( sb_1__1__50_ccff_tail ) , .Test_en_S_in ( p2699 ) , + .ccff_tail ( sb_1__1__50_ccff_tail ) , .Test_en_S_in ( p2207 ) , .Test_en_N_out ( SYNOPSYS_UNCONNECTED_3525 ) , .pReset_S_in ( SYNOPSYS_UNCONNECTED_3526 ) , .pReset_E_in ( pResetWires[376] ) , .pReset_W_in ( SYNOPSYS_UNCONNECTED_3527 ) , .pReset_N_out ( pResetWires[375] ) , .pReset_W_out ( pResetWires[373] ) , - .pReset_E_out ( SYNOPSYS_UNCONNECTED_3528 ) , .Reset_S_in ( p2620 ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_3528 ) , .Reset_S_in ( p2207 ) , .Reset_N_out ( SYNOPSYS_UNCONNECTED_3529 ) , .prog_clk_0_N_in ( prog_clk_0_wires[200] ) , .prog_clk_1_N_in ( prog_clk_2_wires[58] ) , .prog_clk_1_S_in ( SYNOPSYS_UNCONNECTED_3530 ) , .prog_clk_1_E_out ( prog_clk_1_wires[106] ) , - .prog_clk_1_W_out ( prog_clk_1_wires[107] ) , .prog_clk_2_N_in ( p3367 ) , - .prog_clk_2_E_in ( p1213 ) , .prog_clk_2_S_in ( p1279 ) , - .prog_clk_2_W_in ( p1011 ) , + .prog_clk_1_W_out ( prog_clk_1_wires[107] ) , .prog_clk_2_N_in ( p2825 ) , + .prog_clk_2_E_in ( p684 ) , .prog_clk_2_S_in ( p1185 ) , + .prog_clk_2_W_in ( p313 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_3531 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_3532 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_3533 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_3534 ) , - .prog_clk_3_W_in ( p2680 ) , .prog_clk_3_E_in ( p804 ) , - .prog_clk_3_S_in ( p578 ) , .prog_clk_3_N_in ( p3352 ) , + .prog_clk_3_W_in ( p3166 ) , .prog_clk_3_E_in ( p444 ) , + .prog_clk_3_S_in ( p278 ) , .prog_clk_3_N_in ( p2705 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_3535 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_3536 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_3537 ) , @@ -113828,12 +118367,12 @@ sb_1__1_ sb_5__7_ ( .clk_1_N_in ( clk_2_wires[58] ) , .clk_1_S_in ( SYNOPSYS_UNCONNECTED_3539 ) , .clk_1_E_out ( clk_1_wires[106] ) , .clk_1_W_out ( clk_1_wires[107] ) , - .clk_2_N_in ( p3465 ) , .clk_2_E_in ( p801 ) , .clk_2_S_in ( p2549 ) , - .clk_2_W_in ( p2570 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_3540 ) , + .clk_2_N_in ( p3272 ) , .clk_2_E_in ( p66 ) , .clk_2_S_in ( p1028 ) , + .clk_2_W_in ( p3054 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_3540 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_3541 ) , .clk_2_N_out ( SYNOPSYS_UNCONNECTED_3542 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_3543 ) , .clk_3_W_in ( p2680 ) , - .clk_3_E_in ( p530 ) , .clk_3_S_in ( p179 ) , .clk_3_N_in ( p3464 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_3543 ) , .clk_3_W_in ( p2949 ) , + .clk_3_E_in ( p1167 ) , .clk_3_S_in ( p2061 ) , .clk_3_N_in ( p3175 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_3544 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_3545 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_3546 ) , @@ -113881,16 +118420,16 @@ sb_1__1_ sb_5__8_ ( .chanx_right_out ( sb_1__1__51_chanx_right_out ) , .chany_bottom_out ( sb_1__1__51_chany_bottom_out ) , .chanx_left_out ( sb_1__1__51_chanx_left_out ) , - .ccff_tail ( sb_1__1__51_ccff_tail ) , .Test_en_S_in ( p2117 ) , + .ccff_tail ( sb_1__1__51_ccff_tail ) , .Test_en_S_in ( p2548 ) , .Test_en_N_out ( SYNOPSYS_UNCONNECTED_3549 ) , .pReset_S_in ( SYNOPSYS_UNCONNECTED_3550 ) , .pReset_E_in ( pResetWires[425] ) , .pReset_W_in ( SYNOPSYS_UNCONNECTED_3551 ) , .pReset_N_out ( pResetWires[424] ) , .pReset_W_out ( pResetWires[422] ) , - .pReset_E_out ( SYNOPSYS_UNCONNECTED_3552 ) , .Reset_S_in ( p2117 ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_3552 ) , .Reset_S_in ( p2548 ) , .Reset_N_out ( SYNOPSYS_UNCONNECTED_3553 ) , - .prog_clk_0_N_in ( prog_clk_0_wires[203] ) , .prog_clk_1_N_in ( p1338 ) , - .prog_clk_1_S_in ( p308 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[203] ) , .prog_clk_1_N_in ( p1852 ) , + .prog_clk_1_S_in ( p451 ) , .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_3554 ) , .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_3555 ) , .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_3556 ) , @@ -113901,13 +118440,13 @@ sb_1__1_ sb_5__8_ ( .prog_clk_2_S_out ( prog_clk_2_wires[57] ) , .prog_clk_2_N_out ( prog_clk_2_wires[55] ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_3560 ) , - .prog_clk_3_W_in ( p2417 ) , .prog_clk_3_E_in ( p87 ) , - .prog_clk_3_S_in ( p100 ) , .prog_clk_3_N_in ( p1677 ) , + .prog_clk_3_W_in ( p1526 ) , .prog_clk_3_E_in ( p365 ) , + .prog_clk_3_S_in ( p274 ) , .prog_clk_3_N_in ( p1791 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_3561 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_3562 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_3563 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_3564 ) , .clk_1_N_in ( p1338 ) , - .clk_1_S_in ( p789 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_3565 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_3564 ) , .clk_1_N_in ( p1852 ) , + .clk_1_S_in ( p1089 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_3565 ) , .clk_1_W_out ( SYNOPSYS_UNCONNECTED_3566 ) , .clk_2_N_in ( SYNOPSYS_UNCONNECTED_3567 ) , .clk_2_E_in ( SYNOPSYS_UNCONNECTED_3568 ) , @@ -113915,8 +118454,8 @@ sb_1__1_ sb_5__8_ ( .clk_2_W_in ( clk_2_wires[48] ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_3570 ) , .clk_2_S_out ( clk_2_wires[57] ) , .clk_2_N_out ( clk_2_wires[55] ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_3571 ) , .clk_3_W_in ( p2417 ) , - .clk_3_E_in ( p1015 ) , .clk_3_S_in ( p1978 ) , .clk_3_N_in ( p534 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_3571 ) , .clk_3_W_in ( p1526 ) , + .clk_3_E_in ( p103 ) , .clk_3_S_in ( p2385 ) , .clk_3_N_in ( p1710 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_3572 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_3573 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_3574 ) , @@ -113964,40 +118503,40 @@ sb_1__1_ sb_5__9_ ( .chanx_right_out ( sb_1__1__52_chanx_right_out ) , .chany_bottom_out ( sb_1__1__52_chany_bottom_out ) , .chanx_left_out ( sb_1__1__52_chanx_left_out ) , - .ccff_tail ( sb_1__1__52_ccff_tail ) , .Test_en_S_in ( p3083 ) , + .ccff_tail ( sb_1__1__52_ccff_tail ) , .Test_en_S_in ( p1829 ) , .Test_en_N_out ( SYNOPSYS_UNCONNECTED_3577 ) , .pReset_S_in ( SYNOPSYS_UNCONNECTED_3578 ) , .pReset_E_in ( pResetWires[474] ) , .pReset_W_in ( SYNOPSYS_UNCONNECTED_3579 ) , .pReset_N_out ( pResetWires[473] ) , .pReset_W_out ( pResetWires[471] ) , - .pReset_E_out ( SYNOPSYS_UNCONNECTED_3580 ) , .Reset_S_in ( p3192 ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_3580 ) , .Reset_S_in ( p1829 ) , .Reset_N_out ( SYNOPSYS_UNCONNECTED_3581 ) , .prog_clk_0_N_in ( prog_clk_0_wires[206] ) , .prog_clk_1_N_in ( SYNOPSYS_UNCONNECTED_3582 ) , .prog_clk_1_S_in ( prog_clk_2_wires[56] ) , .prog_clk_1_E_out ( prog_clk_1_wires[113] ) , - .prog_clk_1_W_out ( prog_clk_1_wires[114] ) , .prog_clk_2_N_in ( p3471 ) , - .prog_clk_2_E_in ( p1263 ) , .prog_clk_2_S_in ( p602 ) , - .prog_clk_2_W_in ( p1088 ) , + .prog_clk_1_W_out ( prog_clk_1_wires[114] ) , .prog_clk_2_N_in ( p3618 ) , + .prog_clk_2_E_in ( p269 ) , .prog_clk_2_S_in ( p987 ) , + .prog_clk_2_W_in ( p733 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_3583 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_3584 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_3585 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_3586 ) , - .prog_clk_3_W_in ( p2445 ) , .prog_clk_3_E_in ( p91 ) , - .prog_clk_3_S_in ( p1034 ) , .prog_clk_3_N_in ( p3463 ) , + .prog_clk_3_W_in ( p3274 ) , .prog_clk_3_E_in ( p686 ) , + .prog_clk_3_S_in ( p794 ) , .prog_clk_3_N_in ( p3617 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_3587 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_3588 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_3589 ) , .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_3590 ) , .clk_1_N_in ( SYNOPSYS_UNCONNECTED_3591 ) , .clk_1_S_in ( clk_2_wires[56] ) , .clk_1_E_out ( clk_1_wires[113] ) , - .clk_1_W_out ( clk_1_wires[114] ) , .clk_2_N_in ( p2584 ) , - .clk_2_E_in ( p742 ) , .clk_2_S_in ( p3138 ) , .clk_2_W_in ( p2331 ) , + .clk_1_W_out ( clk_1_wires[114] ) , .clk_2_N_in ( p3267 ) , + .clk_2_E_in ( p345 ) , .clk_2_S_in ( p923 ) , .clk_2_W_in ( p3190 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_3592 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_3593 ) , .clk_2_N_out ( SYNOPSYS_UNCONNECTED_3594 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_3595 ) , .clk_3_W_in ( p2445 ) , - .clk_3_E_in ( p1162 ) , .clk_3_S_in ( p1298 ) , .clk_3_N_in ( p2556 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_3595 ) , .clk_3_W_in ( p3024 ) , + .clk_3_E_in ( p938 ) , .clk_3_S_in ( p1667 ) , .clk_3_N_in ( p3217 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_3596 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_3597 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_3598 ) , @@ -114045,16 +118584,16 @@ sb_1__1_ sb_5__10_ ( .chanx_right_out ( sb_1__1__53_chanx_right_out ) , .chany_bottom_out ( sb_1__1__53_chany_bottom_out ) , .chanx_left_out ( sb_1__1__53_chanx_left_out ) , - .ccff_tail ( sb_1__1__53_ccff_tail ) , .Test_en_S_in ( p2467 ) , + .ccff_tail ( sb_1__1__53_ccff_tail ) , .Test_en_S_in ( p2221 ) , .Test_en_N_out ( SYNOPSYS_UNCONNECTED_3601 ) , .pReset_S_in ( SYNOPSYS_UNCONNECTED_3602 ) , .pReset_E_in ( pResetWires[523] ) , .pReset_W_in ( SYNOPSYS_UNCONNECTED_3603 ) , .pReset_N_out ( pResetWires[522] ) , .pReset_W_out ( pResetWires[520] ) , - .pReset_E_out ( SYNOPSYS_UNCONNECTED_3604 ) , .Reset_S_in ( p2467 ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_3604 ) , .Reset_S_in ( p2221 ) , .Reset_N_out ( SYNOPSYS_UNCONNECTED_3605 ) , - .prog_clk_0_N_in ( prog_clk_0_wires[209] ) , .prog_clk_1_N_in ( p1813 ) , - .prog_clk_1_S_in ( p457 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[209] ) , .prog_clk_1_N_in ( p1399 ) , + .prog_clk_1_S_in ( p1269 ) , .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_3606 ) , .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_3607 ) , .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_3608 ) , @@ -114065,13 +118604,13 @@ sb_1__1_ sb_5__10_ ( .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_3612 ) , .prog_clk_2_N_out ( prog_clk_2_wires[66] ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_3613 ) , - .prog_clk_3_W_in ( p1493 ) , .prog_clk_3_E_in ( p93 ) , - .prog_clk_3_S_in ( p7 ) , .prog_clk_3_N_in ( p728 ) , + .prog_clk_3_W_in ( p1903 ) , .prog_clk_3_E_in ( p305 ) , + .prog_clk_3_S_in ( p559 ) , .prog_clk_3_N_in ( p1683 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_3614 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_3615 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_3616 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_3617 ) , .clk_1_N_in ( p1813 ) , - .clk_1_S_in ( p417 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_3618 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_3617 ) , .clk_1_N_in ( p1399 ) , + .clk_1_S_in ( p654 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_3618 ) , .clk_1_W_out ( SYNOPSYS_UNCONNECTED_3619 ) , .clk_2_N_in ( SYNOPSYS_UNCONNECTED_3620 ) , .clk_2_E_in ( SYNOPSYS_UNCONNECTED_3621 ) , @@ -114080,8 +118619,8 @@ sb_1__1_ sb_5__10_ ( .clk_2_W_out ( SYNOPSYS_UNCONNECTED_3623 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_3624 ) , .clk_2_N_out ( clk_2_wires[66] ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_3625 ) , .clk_3_W_in ( p1493 ) , - .clk_3_E_in ( p790 ) , .clk_3_S_in ( p2278 ) , .clk_3_N_in ( p1642 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_3625 ) , .clk_3_W_in ( p1903 ) , + .clk_3_E_in ( p1025 ) , .clk_3_S_in ( p2117 ) , .clk_3_N_in ( p266 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_3626 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_3627 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_3628 ) , @@ -114129,40 +118668,40 @@ sb_1__1_ sb_5__11_ ( .chanx_right_out ( sb_1__1__54_chanx_right_out ) , .chany_bottom_out ( sb_1__1__54_chany_bottom_out ) , .chanx_left_out ( sb_1__1__54_chanx_left_out ) , - .ccff_tail ( sb_1__1__54_ccff_tail ) , .Test_en_S_in ( p2194 ) , + .ccff_tail ( sb_1__1__54_ccff_tail ) , .Test_en_S_in ( p2767 ) , .Test_en_N_out ( SYNOPSYS_UNCONNECTED_3631 ) , .pReset_S_in ( SYNOPSYS_UNCONNECTED_3632 ) , .pReset_E_in ( pResetWires[572] ) , .pReset_W_in ( SYNOPSYS_UNCONNECTED_3633 ) , .pReset_N_out ( pResetWires[571] ) , .pReset_W_out ( pResetWires[569] ) , - .pReset_E_out ( SYNOPSYS_UNCONNECTED_3634 ) , .Reset_S_in ( p2194 ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_3634 ) , .Reset_S_in ( p2767 ) , .Reset_N_out ( SYNOPSYS_UNCONNECTED_3635 ) , .prog_clk_0_N_in ( prog_clk_0_wires[212] ) , .prog_clk_1_N_in ( SYNOPSYS_UNCONNECTED_3636 ) , .prog_clk_1_S_in ( prog_clk_2_wires[67] ) , .prog_clk_1_E_out ( prog_clk_1_wires[120] ) , - .prog_clk_1_W_out ( prog_clk_1_wires[121] ) , .prog_clk_2_N_in ( p3451 ) , - .prog_clk_2_E_in ( p772 ) , .prog_clk_2_S_in ( p280 ) , - .prog_clk_2_W_in ( p351 ) , + .prog_clk_1_W_out ( prog_clk_1_wires[121] ) , .prog_clk_2_N_in ( p3414 ) , + .prog_clk_2_E_in ( p331 ) , .prog_clk_2_S_in ( p1312 ) , + .prog_clk_2_W_in ( p461 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_3637 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_3638 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_3639 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_3640 ) , - .prog_clk_3_W_in ( p2630 ) , .prog_clk_3_E_in ( p1273 ) , - .prog_clk_3_S_in ( p1349 ) , .prog_clk_3_N_in ( p3446 ) , + .prog_clk_3_W_in ( p2816 ) , .prog_clk_3_E_in ( p540 ) , + .prog_clk_3_S_in ( p653 ) , .prog_clk_3_N_in ( p3373 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_3641 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_3642 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_3643 ) , .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_3644 ) , .clk_1_N_in ( SYNOPSYS_UNCONNECTED_3645 ) , .clk_1_S_in ( clk_2_wires[67] ) , .clk_1_E_out ( clk_1_wires[120] ) , - .clk_1_W_out ( clk_1_wires[121] ) , .clk_2_N_in ( p3172 ) , - .clk_2_E_in ( p43 ) , .clk_2_S_in ( p1990 ) , .clk_2_W_in ( p2540 ) , + .clk_1_W_out ( clk_1_wires[121] ) , .clk_2_N_in ( p3232 ) , + .clk_2_E_in ( p394 ) , .clk_2_S_in ( p288 ) , .clk_2_W_in ( p3582 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_3646 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_3647 ) , .clk_2_N_out ( SYNOPSYS_UNCONNECTED_3648 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_3649 ) , .clk_3_W_in ( p2630 ) , - .clk_3_E_in ( p875 ) , .clk_3_S_in ( p225 ) , .clk_3_N_in ( p3144 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_3649 ) , .clk_3_W_in ( p3590 ) , + .clk_3_E_in ( p758 ) , .clk_3_S_in ( p2685 ) , .clk_3_N_in ( p3203 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_3650 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_3651 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_3652 ) , @@ -114217,12 +118756,12 @@ sb_1__1_ sb_6__1_ ( .pReset_N_out ( pResetWires[85] ) , .pReset_W_out ( pResetWires[83] ) , .pReset_E_out ( pResetWires[86] ) , .Reset_S_in ( ResetWires[2] ) , .Reset_N_out ( ResetWires[3] ) , - .prog_clk_0_N_in ( prog_clk_0_wires[220] ) , .prog_clk_1_N_in ( p1347 ) , - .prog_clk_1_S_in ( p178 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[220] ) , .prog_clk_1_N_in ( p1553 ) , + .prog_clk_1_S_in ( p1102 ) , .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_3657 ) , .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_3658 ) , - .prog_clk_2_N_in ( p1503 ) , .prog_clk_2_E_in ( p1100 ) , - .prog_clk_2_S_in ( p1999 ) , .prog_clk_2_W_in ( p205 ) , + .prog_clk_2_N_in ( p1270 ) , .prog_clk_2_E_in ( p306 ) , + .prog_clk_2_S_in ( p620 ) , .prog_clk_2_W_in ( p859 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_3659 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_3660 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_3661 ) , @@ -114234,10 +118773,10 @@ sb_1__1_ sb_6__1_ ( .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_3666 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_3667 ) , .prog_clk_3_N_out ( prog_clk_3_wires[92] ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_3668 ) , .clk_1_N_in ( p1347 ) , - .clk_1_S_in ( p630 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_3669 ) , - .clk_1_W_out ( SYNOPSYS_UNCONNECTED_3670 ) , .clk_2_N_in ( p1503 ) , - .clk_2_E_in ( p558 ) , .clk_2_S_in ( p695 ) , .clk_2_W_in ( p1153 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_3668 ) , .clk_1_N_in ( p1553 ) , + .clk_1_S_in ( p672 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_3669 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_3670 ) , .clk_2_N_in ( p1270 ) , + .clk_2_E_in ( p184 ) , .clk_2_S_in ( p95 ) , .clk_2_W_in ( p410 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_3671 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_3672 ) , .clk_2_N_out ( SYNOPSYS_UNCONNECTED_3673 ) , @@ -114300,12 +118839,12 @@ sb_1__1_ sb_6__2_ ( .pReset_N_out ( pResetWires[134] ) , .pReset_W_out ( pResetWires[132] ) , .pReset_E_out ( pResetWires[135] ) , .Reset_S_in ( ResetWires[4] ) , .Reset_N_out ( ResetWires[5] ) , - .prog_clk_0_N_in ( prog_clk_0_wires[223] ) , .prog_clk_1_N_in ( p1615 ) , - .prog_clk_1_S_in ( p86 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[223] ) , .prog_clk_1_N_in ( p1508 ) , + .prog_clk_1_S_in ( p317 ) , .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_3684 ) , .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_3685 ) , - .prog_clk_2_N_in ( p2696 ) , .prog_clk_2_E_in ( p377 ) , - .prog_clk_2_S_in ( p1668 ) , .prog_clk_2_W_in ( p1114 ) , + .prog_clk_2_N_in ( p2580 ) , .prog_clk_2_E_in ( p549 ) , + .prog_clk_2_S_in ( p89 ) , .prog_clk_2_W_in ( p409 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_3686 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_3687 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_3688 ) , @@ -114317,10 +118856,10 @@ sb_1__1_ sb_6__2_ ( .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_3693 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_3694 ) , .prog_clk_3_N_out ( prog_clk_3_wires[94] ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_3695 ) , .clk_1_N_in ( p1615 ) , - .clk_1_S_in ( p862 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_3696 ) , - .clk_1_W_out ( SYNOPSYS_UNCONNECTED_3697 ) , .clk_2_N_in ( p1940 ) , - .clk_2_E_in ( p704 ) , .clk_2_S_in ( p446 ) , .clk_2_W_in ( p296 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_3695 ) , .clk_1_N_in ( p1508 ) , + .clk_1_S_in ( p1188 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_3696 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_3697 ) , .clk_2_N_in ( p2580 ) , + .clk_2_E_in ( p556 ) , .clk_2_S_in ( p466 ) , .clk_2_W_in ( p209 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_3698 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_3699 ) , .clk_2_N_out ( SYNOPSYS_UNCONNECTED_3700 ) , @@ -114383,12 +118922,12 @@ sb_1__1_ sb_6__3_ ( .pReset_N_out ( pResetWires[183] ) , .pReset_W_out ( pResetWires[181] ) , .pReset_E_out ( pResetWires[184] ) , .Reset_S_in ( ResetWires[6] ) , .Reset_N_out ( ResetWires[7] ) , - .prog_clk_0_N_in ( prog_clk_0_wires[226] ) , .prog_clk_1_N_in ( p1550 ) , - .prog_clk_1_S_in ( p710 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[226] ) , .prog_clk_1_N_in ( p1567 ) , + .prog_clk_1_S_in ( p897 ) , .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_3711 ) , .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_3712 ) , - .prog_clk_2_N_in ( p1931 ) , .prog_clk_2_E_in ( p729 ) , - .prog_clk_2_S_in ( p1680 ) , .prog_clk_2_W_in ( p916 ) , + .prog_clk_2_N_in ( p3139 ) , .prog_clk_2_E_in ( p610 ) , + .prog_clk_2_S_in ( p783 ) , .prog_clk_2_W_in ( p264 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_3713 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_3714 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_3715 ) , @@ -114400,10 +118939,10 @@ sb_1__1_ sb_6__3_ ( .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_3720 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_3721 ) , .prog_clk_3_N_out ( prog_clk_3_wires[96] ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_3722 ) , .clk_1_N_in ( p1550 ) , - .clk_1_S_in ( p135 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_3723 ) , - .clk_1_W_out ( SYNOPSYS_UNCONNECTED_3724 ) , .clk_2_N_in ( p1931 ) , - .clk_2_E_in ( p74 ) , .clk_2_S_in ( p565 ) , .clk_2_W_in ( p247 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_3722 ) , .clk_1_N_in ( p1567 ) , + .clk_1_S_in ( p253 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_3723 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_3724 ) , .clk_2_N_in ( p1874 ) , + .clk_2_E_in ( p149 ) , .clk_2_S_in ( p283 ) , .clk_2_W_in ( p693 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_3725 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_3726 ) , .clk_2_N_out ( SYNOPSYS_UNCONNECTED_3727 ) , @@ -114466,12 +119005,12 @@ sb_1__1_ sb_6__4_ ( .pReset_N_out ( pResetWires[232] ) , .pReset_W_out ( pResetWires[230] ) , .pReset_E_out ( pResetWires[233] ) , .Reset_S_in ( ResetWires[8] ) , .Reset_N_out ( ResetWires[9] ) , - .prog_clk_0_N_in ( prog_clk_0_wires[229] ) , .prog_clk_1_N_in ( p1317 ) , - .prog_clk_1_S_in ( p96 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[229] ) , .prog_clk_1_N_in ( p1438 ) , + .prog_clk_1_S_in ( p206 ) , .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_3738 ) , .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_3739 ) , - .prog_clk_2_N_in ( p2949 ) , .prog_clk_2_E_in ( p706 ) , - .prog_clk_2_S_in ( p1670 ) , .prog_clk_2_W_in ( p201 ) , + .prog_clk_2_N_in ( p2213 ) , .prog_clk_2_E_in ( p377 ) , + .prog_clk_2_S_in ( p1772 ) , .prog_clk_2_W_in ( p235 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_3740 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_3741 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_3742 ) , @@ -114483,10 +119022,10 @@ sb_1__1_ sb_6__4_ ( .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_3747 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_3748 ) , .prog_clk_3_N_out ( prog_clk_3_wires[98] ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_3749 ) , .clk_1_N_in ( p1317 ) , - .clk_1_S_in ( p1075 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_3750 ) , - .clk_1_W_out ( SYNOPSYS_UNCONNECTED_3751 ) , .clk_2_N_in ( p2452 ) , - .clk_2_E_in ( p254 ) , .clk_2_S_in ( p431 ) , .clk_2_W_in ( p393 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_3749 ) , .clk_1_N_in ( p1438 ) , + .clk_1_S_in ( p578 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_3750 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_3751 ) , .clk_2_N_in ( p1277 ) , + .clk_2_E_in ( p233 ) , .clk_2_S_in ( p1686 ) , .clk_2_W_in ( p937 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_3752 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_3753 ) , .clk_2_N_out ( SYNOPSYS_UNCONNECTED_3754 ) , @@ -114550,12 +119089,12 @@ sb_1__1_ sb_6__5_ ( .pReset_N_out ( pResetWires[281] ) , .pReset_W_out ( pResetWires[279] ) , .pReset_E_out ( pResetWires[282] ) , .Reset_S_in ( ResetWires[10] ) , .Reset_N_out ( ResetWires[11] ) , - .prog_clk_0_N_in ( prog_clk_0_wires[232] ) , .prog_clk_1_N_in ( p1821 ) , - .prog_clk_1_S_in ( p1006 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[232] ) , .prog_clk_1_N_in ( p1458 ) , + .prog_clk_1_S_in ( p1159 ) , .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_3765 ) , .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_3766 ) , - .prog_clk_2_N_in ( p2804 ) , .prog_clk_2_E_in ( p399 ) , - .prog_clk_2_S_in ( p1673 ) , .prog_clk_2_W_in ( p310 ) , + .prog_clk_2_N_in ( p1878 ) , .prog_clk_2_E_in ( p592 ) , + .prog_clk_2_S_in ( p446 ) , .prog_clk_2_W_in ( p710 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_3767 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_3768 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_3769 ) , @@ -114567,10 +119106,10 @@ sb_1__1_ sb_6__5_ ( .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_3774 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_3775 ) , .prog_clk_3_N_out ( prog_clk_3_wires[100] ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_3776 ) , .clk_1_N_in ( p1821 ) , - .clk_1_S_in ( p432 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_3777 ) , - .clk_1_W_out ( SYNOPSYS_UNCONNECTED_3778 ) , .clk_2_N_in ( p2712 ) , - .clk_2_E_in ( p799 ) , .clk_2_S_in ( p483 ) , .clk_2_W_in ( p1168 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_3776 ) , .clk_1_N_in ( p1458 ) , + .clk_1_S_in ( p28 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_3777 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_3778 ) , .clk_2_N_in ( p1878 ) , + .clk_2_E_in ( p729 ) , .clk_2_S_in ( p704 ) , .clk_2_W_in ( p53 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_3779 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_3780 ) , .clk_2_N_out ( SYNOPSYS_UNCONNECTED_3781 ) , @@ -114634,12 +119173,12 @@ sb_1__1_ sb_6__6_ ( .pReset_N_out ( pResetWires[330] ) , .pReset_W_out ( pResetWires[328] ) , .pReset_E_out ( pResetWires[331] ) , .Reset_S_in ( ResetWires[12] ) , .Reset_N_out ( ResetWires[13] ) , - .prog_clk_0_N_in ( prog_clk_0_wires[235] ) , .prog_clk_1_N_in ( p1521 ) , - .prog_clk_1_S_in ( p773 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[235] ) , .prog_clk_1_N_in ( p1476 ) , + .prog_clk_1_S_in ( p1035 ) , .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_3792 ) , .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_3793 ) , - .prog_clk_2_N_in ( p1435 ) , .prog_clk_2_E_in ( p963 ) , - .prog_clk_2_S_in ( p2001 ) , .prog_clk_2_W_in ( p1666 ) , + .prog_clk_2_N_in ( p3011 ) , .prog_clk_2_E_in ( p709 ) , + .prog_clk_2_S_in ( p359 ) , .prog_clk_2_W_in ( p2053 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_3794 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_3795 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_3796 ) , @@ -114651,10 +119190,10 @@ sb_1__1_ sb_6__6_ ( .prog_clk_3_E_out ( prog_clk_3_wires[0] ) , .prog_clk_3_W_out ( prog_clk_3_wires[2] ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_3801 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_3802 ) , .clk_1_N_in ( p1521 ) , - .clk_1_S_in ( p365 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_3803 ) , - .clk_1_W_out ( SYNOPSYS_UNCONNECTED_3804 ) , .clk_2_N_in ( p1840 ) , - .clk_2_E_in ( p26 ) , .clk_2_S_in ( p390 ) , .clk_2_W_in ( p174 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_3802 ) , .clk_1_N_in ( p1476 ) , + .clk_1_S_in ( p98 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_3803 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_3804 ) , .clk_2_N_in ( p2015 ) , + .clk_2_E_in ( p272 ) , .clk_2_S_in ( p671 ) , .clk_2_W_in ( p617 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_3805 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_3806 ) , .clk_2_N_out ( SYNOPSYS_UNCONNECTED_3807 ) , @@ -114717,30 +119256,30 @@ sb_1__1_ sb_6__7_ ( .pReset_N_out ( pResetWires[379] ) , .pReset_W_out ( pResetWires[377] ) , .pReset_E_out ( pResetWires[380] ) , .Reset_S_in ( ResetWires[14] ) , .Reset_N_out ( ResetWires[15] ) , - .prog_clk_0_N_in ( prog_clk_0_wires[238] ) , .prog_clk_1_N_in ( p2161 ) , - .prog_clk_1_S_in ( p1170 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[238] ) , .prog_clk_1_N_in ( p1206 ) , + .prog_clk_1_S_in ( p560 ) , .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_3817 ) , .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_3818 ) , - .prog_clk_2_N_in ( p3435 ) , .prog_clk_2_E_in ( p887 ) , - .prog_clk_2_S_in ( p663 ) , .prog_clk_2_W_in ( p57 ) , + .prog_clk_2_N_in ( p3609 ) , .prog_clk_2_E_in ( p10 ) , + .prog_clk_2_S_in ( p293 ) , .prog_clk_2_W_in ( p270 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_3819 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_3820 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_3821 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_3822 ) , - .prog_clk_3_W_in ( p2465 ) , .prog_clk_3_E_in ( p1234 ) , - .prog_clk_3_S_in ( p1175 ) , .prog_clk_3_N_in ( p3423 ) , + .prog_clk_3_W_in ( p3341 ) , .prog_clk_3_E_in ( p635 ) , + .prog_clk_3_S_in ( p1107 ) , .prog_clk_3_N_in ( p3607 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_3823 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_3824 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_3825 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_3826 ) , .clk_1_N_in ( p2161 ) , - .clk_1_S_in ( p99 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_3827 ) , - .clk_1_W_out ( SYNOPSYS_UNCONNECTED_3828 ) , .clk_2_N_in ( p3494 ) , - .clk_2_E_in ( p113 ) , .clk_2_S_in ( p1072 ) , .clk_2_W_in ( p2282 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_3826 ) , .clk_1_N_in ( p1206 ) , + .clk_1_S_in ( p1027 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_3827 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_3828 ) , .clk_2_N_in ( p2833 ) , + .clk_2_E_in ( p1220 ) , .clk_2_S_in ( p922 ) , .clk_2_W_in ( p3379 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_3829 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_3830 ) , .clk_2_N_out ( SYNOPSYS_UNCONNECTED_3831 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_3832 ) , .clk_3_W_in ( p2465 ) , - .clk_3_E_in ( p883 ) , .clk_3_S_in ( p260 ) , .clk_3_N_in ( p3491 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_3832 ) , .clk_3_W_in ( p3398 ) , + .clk_3_E_in ( p392 ) , .clk_3_S_in ( p223 ) , .clk_3_N_in ( p2712 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_3833 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_3834 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_3835 ) , @@ -114796,30 +119335,30 @@ sb_1__1_ sb_6__8_ ( .pReset_N_out ( pResetWires[428] ) , .pReset_W_out ( pResetWires[426] ) , .pReset_E_out ( pResetWires[429] ) , .Reset_S_in ( ResetWires[16] ) , .Reset_N_out ( ResetWires[17] ) , - .prog_clk_0_N_in ( prog_clk_0_wires[241] ) , .prog_clk_1_N_in ( p1203 ) , - .prog_clk_1_S_in ( p228 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[241] ) , .prog_clk_1_N_in ( p2028 ) , + .prog_clk_1_S_in ( p1296 ) , .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_3840 ) , .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_3841 ) , - .prog_clk_2_N_in ( p3355 ) , .prog_clk_2_E_in ( p949 ) , - .prog_clk_2_S_in ( p283 ) , .prog_clk_2_W_in ( p1390 ) , + .prog_clk_2_N_in ( p3401 ) , .prog_clk_2_E_in ( p426 ) , + .prog_clk_2_S_in ( p1131 ) , .prog_clk_2_W_in ( p57 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_3842 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_3843 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_3844 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_3845 ) , - .prog_clk_3_W_in ( p2622 ) , .prog_clk_3_E_in ( p435 ) , - .prog_clk_3_S_in ( p956 ) , .prog_clk_3_N_in ( p3349 ) , + .prog_clk_3_W_in ( p2635 ) , .prog_clk_3_E_in ( p478 ) , + .prog_clk_3_S_in ( p408 ) , .prog_clk_3_N_in ( p3389 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_3846 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_3847 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_3848 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_3849 ) , .clk_1_N_in ( p1203 ) , - .clk_1_S_in ( p709 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_3850 ) , - .clk_1_W_out ( SYNOPSYS_UNCONNECTED_3851 ) , .clk_2_N_in ( p3075 ) , - .clk_2_E_in ( p712 ) , .clk_2_S_in ( p1282 ) , .clk_2_W_in ( p2531 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_3849 ) , .clk_1_N_in ( p2028 ) , + .clk_1_S_in ( p400 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_3850 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_3851 ) , .clk_2_N_in ( p3512 ) , + .clk_2_E_in ( p186 ) , .clk_2_S_in ( p1212 ) , .clk_2_W_in ( p3188 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_3852 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_3853 ) , .clk_2_N_out ( SYNOPSYS_UNCONNECTED_3854 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_3855 ) , .clk_3_W_in ( p2622 ) , - .clk_3_E_in ( p180 ) , .clk_3_S_in ( p717 ) , .clk_3_N_in ( p3026 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_3855 ) , .clk_3_W_in ( p3271 ) , + .clk_3_E_in ( p1099 ) , .clk_3_S_in ( p101 ) , .clk_3_N_in ( p3478 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_3856 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_3857 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_3858 ) , @@ -114875,30 +119414,30 @@ sb_1__1_ sb_6__9_ ( .pReset_N_out ( pResetWires[477] ) , .pReset_W_out ( pResetWires[475] ) , .pReset_E_out ( pResetWires[478] ) , .Reset_S_in ( ResetWires[18] ) , .Reset_N_out ( ResetWires[19] ) , - .prog_clk_0_N_in ( prog_clk_0_wires[244] ) , .prog_clk_1_N_in ( p1573 ) , - .prog_clk_1_S_in ( p258 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[244] ) , .prog_clk_1_N_in ( p1556 ) , + .prog_clk_1_S_in ( p947 ) , .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_3863 ) , .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_3864 ) , - .prog_clk_2_N_in ( p3455 ) , .prog_clk_2_E_in ( p968 ) , - .prog_clk_2_S_in ( p1303 ) , .prog_clk_2_W_in ( p269 ) , + .prog_clk_2_N_in ( p3559 ) , .prog_clk_2_E_in ( p321 ) , + .prog_clk_2_S_in ( p966 ) , .prog_clk_2_W_in ( p116 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_3865 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_3866 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_3867 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_3868 ) , - .prog_clk_3_W_in ( p2149 ) , .prog_clk_3_E_in ( p219 ) , - .prog_clk_3_S_in ( p686 ) , .prog_clk_3_N_in ( p3439 ) , + .prog_clk_3_W_in ( p3226 ) , .prog_clk_3_E_in ( p832 ) , + .prog_clk_3_S_in ( p553 ) , .prog_clk_3_N_in ( p3550 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_3869 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_3870 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_3871 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_3872 ) , .clk_1_N_in ( p1573 ) , - .clk_1_S_in ( p660 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_3873 ) , - .clk_1_W_out ( SYNOPSYS_UNCONNECTED_3874 ) , .clk_2_N_in ( p2703 ) , - .clk_2_E_in ( p416 ) , .clk_2_S_in ( p1444 ) , .clk_2_W_in ( p1972 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_3872 ) , .clk_1_N_in ( p1556 ) , + .clk_1_S_in ( p407 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_3873 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_3874 ) , .clk_2_N_in ( p3399 ) , + .clk_2_E_in ( p364 ) , .clk_2_S_in ( p289 ) , .clk_2_W_in ( p3186 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_3875 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_3876 ) , .clk_2_N_out ( SYNOPSYS_UNCONNECTED_3877 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_3878 ) , .clk_3_W_in ( p2149 ) , - .clk_3_E_in ( p162 ) , .clk_3_S_in ( p482 ) , .clk_3_N_in ( p2583 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_3878 ) , .clk_3_W_in ( p3256 ) , + .clk_3_E_in ( p1076 ) , .clk_3_S_in ( p1117 ) , .clk_3_N_in ( p3392 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_3879 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_3880 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_3881 ) , @@ -114954,30 +119493,30 @@ sb_1__1_ sb_6__10_ ( .pReset_N_out ( pResetWires[526] ) , .pReset_W_out ( pResetWires[524] ) , .pReset_E_out ( pResetWires[527] ) , .Reset_S_in ( ResetWires[20] ) , .Reset_N_out ( ResetWires[21] ) , - .prog_clk_0_N_in ( prog_clk_0_wires[247] ) , .prog_clk_1_N_in ( p1876 ) , - .prog_clk_1_S_in ( p554 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[247] ) , .prog_clk_1_N_in ( p1294 ) , + .prog_clk_1_S_in ( p1219 ) , .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_3886 ) , .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_3887 ) , - .prog_clk_2_N_in ( p2974 ) , .prog_clk_2_E_in ( p1352 ) , - .prog_clk_2_S_in ( p1241 ) , .prog_clk_2_W_in ( p212 ) , + .prog_clk_2_N_in ( p3351 ) , .prog_clk_2_E_in ( p40 ) , + .prog_clk_2_S_in ( p1019 ) , .prog_clk_2_W_in ( p932 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_3888 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_3889 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_3890 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_3891 ) , - .prog_clk_3_W_in ( p3073 ) , .prog_clk_3_E_in ( p1076 ) , - .prog_clk_3_S_in ( p77 ) , .prog_clk_3_N_in ( p2918 ) , + .prog_clk_3_W_in ( p2199 ) , .prog_clk_3_E_in ( p682 ) , + .prog_clk_3_S_in ( p197 ) , .prog_clk_3_N_in ( p3295 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_3892 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_3893 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_3894 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_3895 ) , .clk_1_N_in ( p1876 ) , - .clk_1_S_in ( p306 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_3896 ) , - .clk_1_W_out ( SYNOPSYS_UNCONNECTED_3897 ) , .clk_2_N_in ( p3268 ) , - .clk_2_E_in ( p589 ) , .clk_2_S_in ( p440 ) , .clk_2_W_in ( p3012 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_3895 ) , .clk_1_N_in ( p1294 ) , + .clk_1_S_in ( p90 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_3896 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_3897 ) , .clk_2_N_in ( p2018 ) , + .clk_2_E_in ( p580 ) , .clk_2_S_in ( p537 ) , .clk_2_W_in ( p3431 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_3898 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_3899 ) , .clk_2_N_out ( SYNOPSYS_UNCONNECTED_3900 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_3901 ) , .clk_3_W_in ( p3073 ) , - .clk_3_E_in ( p156 ) , .clk_3_S_in ( p1196 ) , .clk_3_N_in ( p3218 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_3901 ) , .clk_3_W_in ( p3473 ) , + .clk_3_E_in ( p1100 ) , .clk_3_S_in ( p1274 ) , .clk_3_N_in ( p1701 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_3902 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_3903 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_3904 ) , @@ -115033,30 +119572,30 @@ sb_1__1_ sb_6__11_ ( .pReset_N_out ( pResetWires[575] ) , .pReset_W_out ( pResetWires[573] ) , .pReset_E_out ( pResetWires[576] ) , .Reset_S_in ( ResetWires[22] ) , .Reset_N_out ( ResetWires[23] ) , - .prog_clk_0_N_in ( prog_clk_0_wires[250] ) , .prog_clk_1_N_in ( p1937 ) , - .prog_clk_1_S_in ( p998 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[250] ) , .prog_clk_1_N_in ( p1802 ) , + .prog_clk_1_S_in ( p974 ) , .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_3909 ) , .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_3910 ) , - .prog_clk_2_N_in ( p3505 ) , .prog_clk_2_E_in ( p1265 ) , - .prog_clk_2_S_in ( p1098 ) , .prog_clk_2_W_in ( p94 ) , + .prog_clk_2_N_in ( p3507 ) , .prog_clk_2_E_in ( p215 ) , + .prog_clk_2_S_in ( p1238 ) , .prog_clk_2_W_in ( p796 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_3911 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_3912 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_3913 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_3914 ) , - .prog_clk_3_W_in ( p2147 ) , .prog_clk_3_E_in ( p257 ) , - .prog_clk_3_S_in ( p182 ) , .prog_clk_3_N_in ( p3504 ) , + .prog_clk_3_W_in ( p3359 ) , .prog_clk_3_E_in ( p793 ) , + .prog_clk_3_S_in ( p531 ) , .prog_clk_3_N_in ( p3491 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_3915 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_3916 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_3917 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_3918 ) , .clk_1_N_in ( p1937 ) , - .clk_1_S_in ( p469 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_3919 ) , - .clk_1_W_out ( SYNOPSYS_UNCONNECTED_3920 ) , .clk_2_N_in ( p3092 ) , - .clk_2_E_in ( p807 ) , .clk_2_S_in ( p611 ) , .clk_2_W_in ( p2028 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_3918 ) , .clk_1_N_in ( p1802 ) , + .clk_1_S_in ( p92 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_3919 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_3920 ) , .clk_2_N_in ( p3129 ) , + .clk_2_E_in ( p738 ) , .clk_2_S_in ( p1133 ) , .clk_2_W_in ( p3305 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_3921 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_3922 ) , .clk_2_N_out ( SYNOPSYS_UNCONNECTED_3923 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_3924 ) , .clk_3_W_in ( p2147 ) , - .clk_3_E_in ( p577 ) , .clk_3_S_in ( p1118 ) , .clk_3_N_in ( p3038 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_3924 ) , .clk_3_W_in ( p3244 ) , + .clk_3_E_in ( p867 ) , .clk_3_S_in ( p412 ) , .clk_3_N_in ( p3059 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_3925 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_3926 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_3927 ) , @@ -115104,27 +119643,27 @@ sb_1__1_ sb_7__1_ ( .chanx_right_out ( sb_1__1__66_chanx_right_out ) , .chany_bottom_out ( sb_1__1__66_chany_bottom_out ) , .chanx_left_out ( sb_1__1__66_chanx_left_out ) , - .ccff_tail ( sb_1__1__66_ccff_tail ) , .Test_en_S_in ( p1292 ) , + .ccff_tail ( sb_1__1__66_ccff_tail ) , .Test_en_S_in ( p1625 ) , .Test_en_N_out ( SYNOPSYS_UNCONNECTED_3930 ) , .pReset_S_in ( SYNOPSYS_UNCONNECTED_3931 ) , .pReset_E_in ( SYNOPSYS_UNCONNECTED_3932 ) , .pReset_W_in ( pResetWires[87] ) , .pReset_N_out ( pResetWires[89] ) , .pReset_W_out ( SYNOPSYS_UNCONNECTED_3933 ) , - .pReset_E_out ( pResetWires[90] ) , .Reset_S_in ( p1292 ) , + .pReset_E_out ( pResetWires[90] ) , .Reset_S_in ( p1625 ) , .Reset_N_out ( SYNOPSYS_UNCONNECTED_3934 ) , .prog_clk_0_N_in ( prog_clk_0_wires[258] ) , .prog_clk_1_N_in ( prog_clk_2_wires[74] ) , .prog_clk_1_S_in ( SYNOPSYS_UNCONNECTED_3935 ) , .prog_clk_1_E_out ( prog_clk_1_wires[127] ) , - .prog_clk_1_W_out ( prog_clk_1_wires[128] ) , .prog_clk_2_N_in ( p3498 ) , - .prog_clk_2_E_in ( p70 ) , .prog_clk_2_S_in ( p1058 ) , - .prog_clk_2_W_in ( p1344 ) , + .prog_clk_1_W_out ( prog_clk_1_wires[128] ) , .prog_clk_2_N_in ( p3533 ) , + .prog_clk_2_E_in ( p36 ) , .prog_clk_2_S_in ( p972 ) , + .prog_clk_2_W_in ( p668 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_3936 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_3937 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_3938 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_3939 ) , - .prog_clk_3_W_in ( p2691 ) , .prog_clk_3_E_in ( p1033 ) , - .prog_clk_3_S_in ( p376 ) , .prog_clk_3_N_in ( p3496 ) , + .prog_clk_3_W_in ( p3149 ) , .prog_clk_3_E_in ( p324 ) , + .prog_clk_3_S_in ( p513 ) , .prog_clk_3_N_in ( p3517 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_3940 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_3941 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_3942 ) , @@ -115132,12 +119671,12 @@ sb_1__1_ sb_7__1_ ( .clk_1_N_in ( clk_2_wires[74] ) , .clk_1_S_in ( SYNOPSYS_UNCONNECTED_3944 ) , .clk_1_E_out ( clk_1_wires[127] ) , .clk_1_W_out ( clk_1_wires[128] ) , - .clk_2_N_in ( p2256 ) , .clk_2_E_in ( p1020 ) , .clk_2_S_in ( p1201 ) , - .clk_2_W_in ( p2533 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_3945 ) , + .clk_2_N_in ( p3620 ) , .clk_2_E_in ( p843 ) , .clk_2_S_in ( p649 ) , + .clk_2_W_in ( p3208 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_3945 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_3946 ) , .clk_2_N_out ( SYNOPSYS_UNCONNECTED_3947 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_3948 ) , .clk_3_W_in ( p2691 ) , - .clk_3_E_in ( p758 ) , .clk_3_S_in ( p261 ) , .clk_3_N_in ( p1989 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_3948 ) , .clk_3_W_in ( p3277 ) , + .clk_3_E_in ( p1118 ) , .clk_3_S_in ( p1016 ) , .clk_3_N_in ( p3619 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_3949 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_3950 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_3951 ) , @@ -115185,16 +119724,16 @@ sb_1__1_ sb_7__2_ ( .chanx_right_out ( sb_1__1__67_chanx_right_out ) , .chany_bottom_out ( sb_1__1__67_chany_bottom_out ) , .chanx_left_out ( sb_1__1__67_chanx_left_out ) , - .ccff_tail ( sb_1__1__67_ccff_tail ) , .Test_en_S_in ( p3099 ) , + .ccff_tail ( sb_1__1__67_ccff_tail ) , .Test_en_S_in ( p2520 ) , .Test_en_N_out ( SYNOPSYS_UNCONNECTED_3954 ) , .pReset_S_in ( SYNOPSYS_UNCONNECTED_3955 ) , .pReset_E_in ( SYNOPSYS_UNCONNECTED_3956 ) , .pReset_W_in ( pResetWires[136] ) , .pReset_N_out ( pResetWires[138] ) , .pReset_W_out ( SYNOPSYS_UNCONNECTED_3957 ) , - .pReset_E_out ( pResetWires[139] ) , .Reset_S_in ( p3099 ) , + .pReset_E_out ( pResetWires[139] ) , .Reset_S_in ( p2520 ) , .Reset_N_out ( SYNOPSYS_UNCONNECTED_3958 ) , - .prog_clk_0_N_in ( prog_clk_0_wires[261] ) , .prog_clk_1_N_in ( p1502 ) , - .prog_clk_1_S_in ( p381 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[261] ) , .prog_clk_1_N_in ( p1871 ) , + .prog_clk_1_S_in ( p334 ) , .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_3959 ) , .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_3960 ) , .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_3961 ) , @@ -115205,13 +119744,13 @@ sb_1__1_ sb_7__2_ ( .prog_clk_2_S_out ( prog_clk_2_wires[73] ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_3965 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_3966 ) , - .prog_clk_3_W_in ( p1872 ) , .prog_clk_3_E_in ( p806 ) , - .prog_clk_3_S_in ( p705 ) , .prog_clk_3_N_in ( p600 ) , + .prog_clk_3_W_in ( p1599 ) , .prog_clk_3_E_in ( p72 ) , + .prog_clk_3_S_in ( p878 ) , .prog_clk_3_N_in ( p716 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_3967 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_3968 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_3969 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_3970 ) , .clk_1_N_in ( p1502 ) , - .clk_1_S_in ( p434 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_3971 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_3970 ) , .clk_1_N_in ( p1871 ) , + .clk_1_S_in ( p1116 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_3971 ) , .clk_1_W_out ( SYNOPSYS_UNCONNECTED_3972 ) , .clk_2_N_in ( SYNOPSYS_UNCONNECTED_3973 ) , .clk_2_E_in ( clk_2_wires[72] ) , @@ -115220,8 +119759,8 @@ sb_1__1_ sb_7__2_ ( .clk_2_W_out ( SYNOPSYS_UNCONNECTED_3976 ) , .clk_2_S_out ( clk_2_wires[73] ) , .clk_2_N_out ( SYNOPSYS_UNCONNECTED_3977 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_3978 ) , .clk_3_W_in ( p1872 ) , - .clk_3_E_in ( p1987 ) , .clk_3_S_in ( p3025 ) , .clk_3_N_in ( p127 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_3978 ) , .clk_3_W_in ( p1599 ) , + .clk_3_E_in ( p691 ) , .clk_3_S_in ( p2429 ) , .clk_3_N_in ( p1663 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_3979 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_3980 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_3981 ) , @@ -115269,27 +119808,27 @@ sb_1__1_ sb_7__3_ ( .chanx_right_out ( sb_1__1__68_chanx_right_out ) , .chany_bottom_out ( sb_1__1__68_chany_bottom_out ) , .chanx_left_out ( sb_1__1__68_chanx_left_out ) , - .ccff_tail ( sb_1__1__68_ccff_tail ) , .Test_en_S_in ( p2642 ) , + .ccff_tail ( sb_1__1__68_ccff_tail ) , .Test_en_S_in ( p2021 ) , .Test_en_N_out ( SYNOPSYS_UNCONNECTED_3984 ) , .pReset_S_in ( SYNOPSYS_UNCONNECTED_3985 ) , .pReset_E_in ( SYNOPSYS_UNCONNECTED_3986 ) , .pReset_W_in ( pResetWires[185] ) , .pReset_N_out ( pResetWires[187] ) , .pReset_W_out ( SYNOPSYS_UNCONNECTED_3987 ) , - .pReset_E_out ( pResetWires[188] ) , .Reset_S_in ( p3173 ) , + .pReset_E_out ( pResetWires[188] ) , .Reset_S_in ( p2021 ) , .Reset_N_out ( SYNOPSYS_UNCONNECTED_3988 ) , .prog_clk_0_N_in ( prog_clk_0_wires[264] ) , .prog_clk_1_N_in ( prog_clk_2_wires[85] ) , .prog_clk_1_S_in ( SYNOPSYS_UNCONNECTED_3989 ) , .prog_clk_1_E_out ( prog_clk_1_wires[134] ) , - .prog_clk_1_W_out ( prog_clk_1_wires[135] ) , .prog_clk_2_N_in ( p3468 ) , - .prog_clk_2_E_in ( p948 ) , .prog_clk_2_S_in ( p1142 ) , - .prog_clk_2_W_in ( p170 ) , + .prog_clk_1_W_out ( prog_clk_1_wires[135] ) , .prog_clk_2_N_in ( p3603 ) , + .prog_clk_2_E_in ( p382 ) , .prog_clk_2_S_in ( p1038 ) , + .prog_clk_2_W_in ( p762 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_3990 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_3991 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_3992 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_3993 ) , - .prog_clk_3_W_in ( p2654 ) , .prog_clk_3_E_in ( p84 ) , - .prog_clk_3_S_in ( p621 ) , .prog_clk_3_N_in ( p3460 ) , + .prog_clk_3_W_in ( p3105 ) , .prog_clk_3_E_in ( p705 ) , + .prog_clk_3_S_in ( p226 ) , .prog_clk_3_N_in ( p3601 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_3994 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_3995 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_3996 ) , @@ -115297,12 +119836,12 @@ sb_1__1_ sb_7__3_ ( .clk_1_N_in ( clk_2_wires[85] ) , .clk_1_S_in ( SYNOPSYS_UNCONNECTED_3998 ) , .clk_1_E_out ( clk_1_wires[134] ) , .clk_1_W_out ( clk_1_wires[135] ) , - .clk_2_N_in ( p3495 ) , .clk_2_E_in ( p906 ) , .clk_2_S_in ( p3126 ) , - .clk_2_W_in ( p2546 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_3999 ) , + .clk_2_N_in ( p3154 ) , .clk_2_E_in ( p87 ) , .clk_2_S_in ( p275 ) , + .clk_2_W_in ( p3073 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_3999 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_4000 ) , .clk_2_N_out ( SYNOPSYS_UNCONNECTED_4001 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_4002 ) , .clk_3_W_in ( p2654 ) , - .clk_3_E_in ( p863 ) , .clk_3_S_in ( p388 ) , .clk_3_N_in ( p3492 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_4002 ) , .clk_3_W_in ( p3113 ) , + .clk_3_E_in ( p894 ) , .clk_3_S_in ( p1770 ) , .clk_3_N_in ( p3048 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_4003 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4004 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_4005 ) , @@ -115350,16 +119889,16 @@ sb_1__1_ sb_7__4_ ( .chanx_right_out ( sb_1__1__69_chanx_right_out ) , .chany_bottom_out ( sb_1__1__69_chany_bottom_out ) , .chanx_left_out ( sb_1__1__69_chanx_left_out ) , - .ccff_tail ( sb_1__1__69_ccff_tail ) , .Test_en_S_in ( p3322 ) , + .ccff_tail ( sb_1__1__69_ccff_tail ) , .Test_en_S_in ( p1651 ) , .Test_en_N_out ( SYNOPSYS_UNCONNECTED_4008 ) , .pReset_S_in ( SYNOPSYS_UNCONNECTED_4009 ) , .pReset_E_in ( SYNOPSYS_UNCONNECTED_4010 ) , .pReset_W_in ( pResetWires[234] ) , .pReset_N_out ( pResetWires[236] ) , .pReset_W_out ( SYNOPSYS_UNCONNECTED_4011 ) , - .pReset_E_out ( pResetWires[237] ) , .Reset_S_in ( p3325 ) , + .pReset_E_out ( pResetWires[237] ) , .Reset_S_in ( p1651 ) , .Reset_N_out ( SYNOPSYS_UNCONNECTED_4012 ) , - .prog_clk_0_N_in ( prog_clk_0_wires[267] ) , .prog_clk_1_N_in ( p2162 ) , - .prog_clk_1_S_in ( p650 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[267] ) , .prog_clk_1_N_in ( p1932 ) , + .prog_clk_1_S_in ( p956 ) , .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_4013 ) , .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_4014 ) , .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_4015 ) , @@ -115370,13 +119909,13 @@ sb_1__1_ sb_7__4_ ( .prog_clk_2_S_out ( prog_clk_2_wires[84] ) , .prog_clk_2_N_out ( prog_clk_2_wires[82] ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_4019 ) , - .prog_clk_3_W_in ( p1809 ) , .prog_clk_3_E_in ( p881 ) , - .prog_clk_3_S_in ( p46 ) , .prog_clk_3_N_in ( p1976 ) , + .prog_clk_3_W_in ( p2314 ) , .prog_clk_3_E_in ( p132 ) , + .prog_clk_3_S_in ( p3 ) , .prog_clk_3_N_in ( p2102 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_4020 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4021 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_4022 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_4023 ) , .clk_1_N_in ( p2162 ) , - .clk_1_S_in ( p163 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_4024 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_4023 ) , .clk_1_N_in ( p1932 ) , + .clk_1_S_in ( p252 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_4024 ) , .clk_1_W_out ( SYNOPSYS_UNCONNECTED_4025 ) , .clk_2_N_in ( SYNOPSYS_UNCONNECTED_4026 ) , .clk_2_E_in ( clk_2_wires[81] ) , @@ -115384,8 +119923,8 @@ sb_1__1_ sb_7__4_ ( .clk_2_W_in ( SYNOPSYS_UNCONNECTED_4028 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_4029 ) , .clk_2_S_out ( clk_2_wires[84] ) , .clk_2_N_out ( clk_2_wires[82] ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_4030 ) , .clk_3_W_in ( p1809 ) , - .clk_3_E_in ( p1702 ) , .clk_3_S_in ( p3292 ) , .clk_3_N_in ( p2021 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_4030 ) , .clk_3_W_in ( p2314 ) , + .clk_3_E_in ( p778 ) , .clk_3_S_in ( p797 ) , .clk_3_N_in ( p1773 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_4031 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4032 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_4033 ) , @@ -115433,40 +119972,40 @@ sb_1__1_ sb_7__5_ ( .chanx_right_out ( sb_1__1__70_chanx_right_out ) , .chany_bottom_out ( sb_1__1__70_chany_bottom_out ) , .chanx_left_out ( sb_1__1__70_chanx_left_out ) , - .ccff_tail ( sb_1__1__70_ccff_tail ) , .Test_en_S_in ( p2791 ) , + .ccff_tail ( sb_1__1__70_ccff_tail ) , .Test_en_S_in ( p2836 ) , .Test_en_N_out ( SYNOPSYS_UNCONNECTED_4036 ) , .pReset_S_in ( SYNOPSYS_UNCONNECTED_4037 ) , .pReset_E_in ( SYNOPSYS_UNCONNECTED_4038 ) , .pReset_W_in ( pResetWires[283] ) , .pReset_N_out ( pResetWires[285] ) , .pReset_W_out ( SYNOPSYS_UNCONNECTED_4039 ) , - .pReset_E_out ( pResetWires[286] ) , .Reset_S_in ( p2791 ) , + .pReset_E_out ( pResetWires[286] ) , .Reset_S_in ( p2836 ) , .Reset_N_out ( SYNOPSYS_UNCONNECTED_4040 ) , .prog_clk_0_N_in ( prog_clk_0_wires[270] ) , .prog_clk_1_N_in ( SYNOPSYS_UNCONNECTED_4041 ) , .prog_clk_1_S_in ( prog_clk_2_wires[83] ) , .prog_clk_1_E_out ( prog_clk_1_wires[141] ) , - .prog_clk_1_W_out ( prog_clk_1_wires[142] ) , .prog_clk_2_N_in ( p3434 ) , - .prog_clk_2_E_in ( p1260 ) , .prog_clk_2_S_in ( p583 ) , - .prog_clk_2_W_in ( p1070 ) , + .prog_clk_1_W_out ( prog_clk_1_wires[142] ) , .prog_clk_2_N_in ( p3604 ) , + .prog_clk_2_E_in ( p333 ) , .prog_clk_2_S_in ( p88 ) , + .prog_clk_2_W_in ( p19 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_4042 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_4043 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_4044 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_4045 ) , - .prog_clk_3_W_in ( p2617 ) , .prog_clk_3_E_in ( p797 ) , - .prog_clk_3_S_in ( p1186 ) , .prog_clk_3_N_in ( p3424 ) , + .prog_clk_3_W_in ( p2796 ) , .prog_clk_3_E_in ( p518 ) , + .prog_clk_3_S_in ( p944 ) , .prog_clk_3_N_in ( p3599 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_4046 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4047 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_4048 ) , .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_4049 ) , .clk_1_N_in ( SYNOPSYS_UNCONNECTED_4050 ) , .clk_1_S_in ( clk_2_wires[83] ) , .clk_1_E_out ( clk_1_wires[141] ) , - .clk_1_W_out ( clk_1_wires[142] ) , .clk_2_N_in ( p3204 ) , - .clk_2_E_in ( p18 ) , .clk_2_S_in ( p2736 ) , .clk_2_W_in ( p2544 ) , + .clk_1_W_out ( clk_1_wires[142] ) , .clk_2_N_in ( p3497 ) , + .clk_2_E_in ( p957 ) , .clk_2_S_in ( p1224 ) , .clk_2_W_in ( p3039 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_4051 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_4052 ) , .clk_2_N_out ( SYNOPSYS_UNCONNECTED_4053 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_4054 ) , .clk_3_W_in ( p2617 ) , - .clk_3_E_in ( p812 ) , .clk_3_S_in ( p11 ) , .clk_3_N_in ( p3153 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_4054 ) , .clk_3_W_in ( p3118 ) , + .clk_3_E_in ( p421 ) , .clk_3_S_in ( p2647 ) , .clk_3_N_in ( p3495 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_4055 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4056 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_4057 ) , @@ -115514,20 +120053,20 @@ sb_1__1_ sb_7__6_ ( .chanx_right_out ( sb_1__1__71_chanx_right_out ) , .chany_bottom_out ( sb_1__1__71_chany_bottom_out ) , .chanx_left_out ( sb_1__1__71_chanx_left_out ) , - .ccff_tail ( sb_1__1__71_ccff_tail ) , .Test_en_S_in ( p2947 ) , + .ccff_tail ( sb_1__1__71_ccff_tail ) , .Test_en_S_in ( p2212 ) , .Test_en_N_out ( SYNOPSYS_UNCONNECTED_4060 ) , .pReset_S_in ( SYNOPSYS_UNCONNECTED_4061 ) , .pReset_E_in ( SYNOPSYS_UNCONNECTED_4062 ) , .pReset_W_in ( pResetWires[332] ) , .pReset_N_out ( pResetWires[334] ) , .pReset_W_out ( SYNOPSYS_UNCONNECTED_4063 ) , - .pReset_E_out ( pResetWires[335] ) , .Reset_S_in ( p3323 ) , + .pReset_E_out ( pResetWires[335] ) , .Reset_S_in ( p2212 ) , .Reset_N_out ( SYNOPSYS_UNCONNECTED_4064 ) , - .prog_clk_0_N_in ( prog_clk_0_wires[273] ) , .prog_clk_1_N_in ( p1420 ) , - .prog_clk_1_S_in ( p516 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[273] ) , .prog_clk_1_N_in ( p1408 ) , + .prog_clk_1_S_in ( p42 ) , .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_4065 ) , .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_4066 ) , - .prog_clk_2_N_in ( p2497 ) , .prog_clk_2_E_in ( p845 ) , - .prog_clk_2_S_in ( p902 ) , .prog_clk_2_W_in ( p450 ) , + .prog_clk_2_N_in ( p1935 ) , .prog_clk_2_E_in ( p13 ) , + .prog_clk_2_S_in ( p744 ) , .prog_clk_2_W_in ( p860 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_4067 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_4068 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_4069 ) , @@ -115539,10 +120078,10 @@ sb_1__1_ sb_7__6_ ( .prog_clk_3_E_out ( prog_clk_3_wires[4] ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4074 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_4075 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_4076 ) , .clk_1_N_in ( p1420 ) , - .clk_1_S_in ( p915 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_4077 ) , - .clk_1_W_out ( SYNOPSYS_UNCONNECTED_4078 ) , .clk_2_N_in ( p2497 ) , - .clk_2_E_in ( p175 ) , .clk_2_S_in ( p3283 ) , .clk_2_W_in ( p137 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_4076 ) , .clk_1_N_in ( p1408 ) , + .clk_1_S_in ( p1266 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_4077 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_4078 ) , .clk_2_N_in ( p1449 ) , + .clk_2_E_in ( p630 ) , .clk_2_S_in ( p2097 ) , .clk_2_W_in ( p521 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_4079 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_4080 ) , .clk_2_N_out ( SYNOPSYS_UNCONNECTED_4081 ) , @@ -115598,27 +120137,27 @@ sb_1__1_ sb_7__7_ ( .chanx_right_out ( sb_1__1__72_chanx_right_out ) , .chany_bottom_out ( sb_1__1__72_chany_bottom_out ) , .chanx_left_out ( sb_1__1__72_chanx_left_out ) , - .ccff_tail ( sb_1__1__72_ccff_tail ) , .Test_en_S_in ( p3072 ) , + .ccff_tail ( sb_1__1__72_ccff_tail ) , .Test_en_S_in ( p1560 ) , .Test_en_N_out ( SYNOPSYS_UNCONNECTED_4090 ) , .pReset_S_in ( SYNOPSYS_UNCONNECTED_4091 ) , .pReset_E_in ( SYNOPSYS_UNCONNECTED_4092 ) , .pReset_W_in ( pResetWires[381] ) , .pReset_N_out ( pResetWires[383] ) , .pReset_W_out ( SYNOPSYS_UNCONNECTED_4093 ) , - .pReset_E_out ( pResetWires[384] ) , .Reset_S_in ( p3072 ) , + .pReset_E_out ( pResetWires[384] ) , .Reset_S_in ( p1560 ) , .Reset_N_out ( SYNOPSYS_UNCONNECTED_4094 ) , .prog_clk_0_N_in ( prog_clk_0_wires[276] ) , .prog_clk_1_N_in ( prog_clk_2_wires[98] ) , .prog_clk_1_S_in ( SYNOPSYS_UNCONNECTED_4095 ) , .prog_clk_1_E_out ( prog_clk_1_wires[148] ) , - .prog_clk_1_W_out ( prog_clk_1_wires[149] ) , .prog_clk_2_N_in ( p3433 ) , - .prog_clk_2_E_in ( p616 ) , .prog_clk_2_S_in ( p206 ) , - .prog_clk_2_W_in ( p1081 ) , + .prog_clk_1_W_out ( prog_clk_1_wires[149] ) , .prog_clk_2_N_in ( p3505 ) , + .prog_clk_2_E_in ( p584 ) , .prog_clk_2_S_in ( p1182 ) , + .prog_clk_2_W_in ( p804 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_4096 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_4097 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_4098 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_4099 ) , - .prog_clk_3_W_in ( p2387 ) , .prog_clk_3_E_in ( p1018 ) , - .prog_clk_3_S_in ( p985 ) , .prog_clk_3_N_in ( p3413 ) , + .prog_clk_3_W_in ( p2546 ) , .prog_clk_3_E_in ( p933 ) , + .prog_clk_3_S_in ( p386 ) , .prog_clk_3_N_in ( p3486 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_4100 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4101 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_4102 ) , @@ -115626,12 +120165,12 @@ sb_1__1_ sb_7__7_ ( .clk_1_N_in ( clk_2_wires[98] ) , .clk_1_S_in ( SYNOPSYS_UNCONNECTED_4104 ) , .clk_1_E_out ( clk_1_wires[148] ) , .clk_1_W_out ( clk_1_wires[149] ) , - .clk_2_N_in ( p3396 ) , .clk_2_E_in ( p580 ) , .clk_2_S_in ( p2999 ) , - .clk_2_W_in ( p2284 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_4105 ) , + .clk_2_N_in ( p3331 ) , .clk_2_E_in ( p126 ) , .clk_2_S_in ( p1248 ) , + .clk_2_W_in ( p3427 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_4105 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_4106 ) , .clk_2_N_out ( SYNOPSYS_UNCONNECTED_4107 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_4108 ) , .clk_3_W_in ( p2387 ) , - .clk_3_E_in ( p884 ) , .clk_3_S_in ( p1359 ) , .clk_3_N_in ( p3389 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_4108 ) , .clk_3_W_in ( p3463 ) , + .clk_3_E_in ( p1010 ) , .clk_3_S_in ( p790 ) , .clk_3_N_in ( p3294 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_4109 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4110 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_4111 ) , @@ -115679,16 +120218,16 @@ sb_1__1_ sb_7__8_ ( .chanx_right_out ( sb_1__1__73_chanx_right_out ) , .chany_bottom_out ( sb_1__1__73_chany_bottom_out ) , .chanx_left_out ( sb_1__1__73_chanx_left_out ) , - .ccff_tail ( sb_1__1__73_ccff_tail ) , .Test_en_S_in ( p2437 ) , + .ccff_tail ( sb_1__1__73_ccff_tail ) , .Test_en_S_in ( p1415 ) , .Test_en_N_out ( SYNOPSYS_UNCONNECTED_4114 ) , .pReset_S_in ( SYNOPSYS_UNCONNECTED_4115 ) , .pReset_E_in ( SYNOPSYS_UNCONNECTED_4116 ) , .pReset_W_in ( pResetWires[430] ) , .pReset_N_out ( pResetWires[432] ) , .pReset_W_out ( SYNOPSYS_UNCONNECTED_4117 ) , - .pReset_E_out ( pResetWires[433] ) , .Reset_S_in ( p2437 ) , + .pReset_E_out ( pResetWires[433] ) , .Reset_S_in ( p1415 ) , .Reset_N_out ( SYNOPSYS_UNCONNECTED_4118 ) , - .prog_clk_0_N_in ( prog_clk_0_wires[279] ) , .prog_clk_1_N_in ( p1853 ) , - .prog_clk_1_S_in ( p703 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[279] ) , .prog_clk_1_N_in ( p1307 ) , + .prog_clk_1_S_in ( p427 ) , .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_4119 ) , .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_4120 ) , .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_4121 ) , @@ -115699,13 +120238,13 @@ sb_1__1_ sb_7__8_ ( .prog_clk_2_S_out ( prog_clk_2_wires[97] ) , .prog_clk_2_N_out ( prog_clk_2_wires[95] ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_4125 ) , - .prog_clk_3_W_in ( p2263 ) , .prog_clk_3_E_in ( p959 ) , - .prog_clk_3_S_in ( p581 ) , .prog_clk_3_N_in ( p85 ) , + .prog_clk_3_W_in ( p1272 ) , .prog_clk_3_E_in ( p296 ) , + .prog_clk_3_S_in ( p151 ) , .prog_clk_3_N_in ( p449 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_4126 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4127 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_4128 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_4129 ) , .clk_1_N_in ( p1853 ) , - .clk_1_S_in ( p286 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_4130 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_4129 ) , .clk_1_N_in ( p1307 ) , + .clk_1_S_in ( p1093 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_4130 ) , .clk_1_W_out ( SYNOPSYS_UNCONNECTED_4131 ) , .clk_2_N_in ( SYNOPSYS_UNCONNECTED_4132 ) , .clk_2_E_in ( clk_2_wires[94] ) , @@ -115713,8 +120252,8 @@ sb_1__1_ sb_7__8_ ( .clk_2_W_in ( SYNOPSYS_UNCONNECTED_4134 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_4135 ) , .clk_2_S_out ( clk_2_wires[97] ) , .clk_2_N_out ( clk_2_wires[95] ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_4136 ) , .clk_3_W_in ( p2263 ) , - .clk_3_E_in ( p161 ) , .clk_3_S_in ( p2269 ) , .clk_3_N_in ( p1640 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_4136 ) , .clk_3_W_in ( p1272 ) , + .clk_3_E_in ( p703 ) , .clk_3_S_in ( p582 ) , .clk_3_N_in ( p47 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_4137 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4138 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_4139 ) , @@ -115762,40 +120301,40 @@ sb_1__1_ sb_7__9_ ( .chanx_right_out ( sb_1__1__74_chanx_right_out ) , .chany_bottom_out ( sb_1__1__74_chany_bottom_out ) , .chanx_left_out ( sb_1__1__74_chanx_left_out ) , - .ccff_tail ( sb_1__1__74_ccff_tail ) , .Test_en_S_in ( p3186 ) , + .ccff_tail ( sb_1__1__74_ccff_tail ) , .Test_en_S_in ( p1925 ) , .Test_en_N_out ( SYNOPSYS_UNCONNECTED_4142 ) , .pReset_S_in ( SYNOPSYS_UNCONNECTED_4143 ) , .pReset_E_in ( SYNOPSYS_UNCONNECTED_4144 ) , .pReset_W_in ( pResetWires[479] ) , .pReset_N_out ( pResetWires[481] ) , .pReset_W_out ( SYNOPSYS_UNCONNECTED_4145 ) , - .pReset_E_out ( pResetWires[482] ) , .Reset_S_in ( p3186 ) , + .pReset_E_out ( pResetWires[482] ) , .Reset_S_in ( p1925 ) , .Reset_N_out ( SYNOPSYS_UNCONNECTED_4146 ) , .prog_clk_0_N_in ( prog_clk_0_wires[282] ) , .prog_clk_1_N_in ( SYNOPSYS_UNCONNECTED_4147 ) , .prog_clk_1_S_in ( prog_clk_2_wires[96] ) , .prog_clk_1_E_out ( prog_clk_1_wires[155] ) , - .prog_clk_1_W_out ( prog_clk_1_wires[156] ) , .prog_clk_2_N_in ( p3095 ) , - .prog_clk_2_E_in ( p1188 ) , .prog_clk_2_S_in ( p1008 ) , - .prog_clk_2_W_in ( p1119 ) , + .prog_clk_1_W_out ( prog_clk_1_wires[156] ) , .prog_clk_2_N_in ( p1540 ) , + .prog_clk_2_E_in ( p609 ) , .prog_clk_2_S_in ( p826 ) , + .prog_clk_2_W_in ( p952 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_4148 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_4149 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_4150 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_4151 ) , - .prog_clk_3_W_in ( p2854 ) , .prog_clk_3_E_in ( p407 ) , - .prog_clk_3_S_in ( p471 ) , .prog_clk_3_N_in ( p3041 ) , + .prog_clk_3_W_in ( p2631 ) , .prog_clk_3_E_in ( p683 ) , + .prog_clk_3_S_in ( p983 ) , .prog_clk_3_N_in ( p583 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_4152 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4153 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_4154 ) , .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_4155 ) , .clk_1_N_in ( SYNOPSYS_UNCONNECTED_4156 ) , .clk_1_S_in ( clk_2_wires[96] ) , .clk_1_E_out ( clk_1_wires[155] ) , - .clk_1_W_out ( clk_1_wires[156] ) , .clk_2_N_in ( p3057 ) , - .clk_2_E_in ( p917 ) , .clk_2_S_in ( p3114 ) , .clk_2_W_in ( p2723 ) , + .clk_1_W_out ( clk_1_wires[156] ) , .clk_2_N_in ( p3572 ) , + .clk_2_E_in ( p1366 ) , .clk_2_S_in ( p1172 ) , .clk_2_W_in ( p3086 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_4157 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_4158 ) , .clk_2_N_out ( SYNOPSYS_UNCONNECTED_4159 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_4160 ) , .clk_3_W_in ( p2854 ) , - .clk_3_E_in ( p48 ) , .clk_3_S_in ( p240 ) , .clk_3_N_in ( p3015 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_4160 ) , .clk_3_W_in ( p3159 ) , + .clk_3_E_in ( p303 ) , .clk_3_S_in ( p1670 ) , .clk_3_N_in ( p3563 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_4161 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4162 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_4163 ) , @@ -115843,16 +120382,16 @@ sb_1__1_ sb_7__10_ ( .chanx_right_out ( sb_1__1__75_chanx_right_out ) , .chany_bottom_out ( sb_1__1__75_chany_bottom_out ) , .chanx_left_out ( sb_1__1__75_chanx_left_out ) , - .ccff_tail ( sb_1__1__75_ccff_tail ) , .Test_en_S_in ( p3050 ) , + .ccff_tail ( sb_1__1__75_ccff_tail ) , .Test_en_S_in ( p1552 ) , .Test_en_N_out ( SYNOPSYS_UNCONNECTED_4166 ) , .pReset_S_in ( SYNOPSYS_UNCONNECTED_4167 ) , .pReset_E_in ( SYNOPSYS_UNCONNECTED_4168 ) , .pReset_W_in ( pResetWires[528] ) , .pReset_N_out ( pResetWires[530] ) , .pReset_W_out ( SYNOPSYS_UNCONNECTED_4169 ) , - .pReset_E_out ( pResetWires[531] ) , .Reset_S_in ( p3068 ) , + .pReset_E_out ( pResetWires[531] ) , .Reset_S_in ( p1552 ) , .Reset_N_out ( SYNOPSYS_UNCONNECTED_4170 ) , - .prog_clk_0_N_in ( prog_clk_0_wires[285] ) , .prog_clk_1_N_in ( p1350 ) , - .prog_clk_1_S_in ( p923 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[285] ) , .prog_clk_1_N_in ( p1515 ) , + .prog_clk_1_S_in ( p388 ) , .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_4171 ) , .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_4172 ) , .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_4173 ) , @@ -115863,13 +120402,13 @@ sb_1__1_ sb_7__10_ ( .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_4177 ) , .prog_clk_2_N_out ( prog_clk_2_wires[108] ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_4178 ) , - .prog_clk_3_W_in ( p1253 ) , .prog_clk_3_E_in ( p784 ) , - .prog_clk_3_S_in ( p510 ) , .prog_clk_3_N_in ( p1622 ) , + .prog_clk_3_W_in ( p1645 ) , .prog_clk_3_E_in ( p170 ) , + .prog_clk_3_S_in ( p881 ) , .prog_clk_3_N_in ( p764 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_4179 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4180 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_4181 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_4182 ) , .clk_1_N_in ( p1350 ) , - .clk_1_S_in ( p37 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_4183 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_4182 ) , .clk_1_N_in ( p1515 ) , + .clk_1_S_in ( p1078 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_4183 ) , .clk_1_W_out ( SYNOPSYS_UNCONNECTED_4184 ) , .clk_2_N_in ( SYNOPSYS_UNCONNECTED_4185 ) , .clk_2_E_in ( clk_2_wires[107] ) , @@ -115878,8 +120417,8 @@ sb_1__1_ sb_7__10_ ( .clk_2_W_out ( SYNOPSYS_UNCONNECTED_4188 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_4189 ) , .clk_2_N_out ( clk_2_wires[108] ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_4190 ) , .clk_3_W_in ( p1253 ) , - .clk_3_E_in ( p1698 ) , .clk_3_S_in ( p3024 ) , .clk_3_N_in ( p197 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_4190 ) , .clk_3_W_in ( p1423 ) , + .clk_3_E_in ( p792 ) , .clk_3_S_in ( p717 ) , .clk_3_N_in ( p203 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_4191 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4192 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_4193 ) , @@ -115927,40 +120466,40 @@ sb_1__1_ sb_7__11_ ( .chanx_right_out ( sb_1__1__76_chanx_right_out ) , .chany_bottom_out ( sb_1__1__76_chany_bottom_out ) , .chanx_left_out ( sb_1__1__76_chanx_left_out ) , - .ccff_tail ( sb_1__1__76_ccff_tail ) , .Test_en_S_in ( p2633 ) , + .ccff_tail ( sb_1__1__76_ccff_tail ) , .Test_en_S_in ( p1549 ) , .Test_en_N_out ( SYNOPSYS_UNCONNECTED_4196 ) , .pReset_S_in ( SYNOPSYS_UNCONNECTED_4197 ) , .pReset_E_in ( SYNOPSYS_UNCONNECTED_4198 ) , .pReset_W_in ( pResetWires[577] ) , .pReset_N_out ( pResetWires[579] ) , .pReset_W_out ( SYNOPSYS_UNCONNECTED_4199 ) , - .pReset_E_out ( pResetWires[580] ) , .Reset_S_in ( p2633 ) , + .pReset_E_out ( pResetWires[580] ) , .Reset_S_in ( p1549 ) , .Reset_N_out ( SYNOPSYS_UNCONNECTED_4200 ) , .prog_clk_0_N_in ( prog_clk_0_wires[288] ) , .prog_clk_1_N_in ( SYNOPSYS_UNCONNECTED_4201 ) , .prog_clk_1_S_in ( prog_clk_2_wires[109] ) , .prog_clk_1_E_out ( prog_clk_1_wires[162] ) , - .prog_clk_1_W_out ( prog_clk_1_wires[163] ) , .prog_clk_2_N_in ( p3507 ) , - .prog_clk_2_E_in ( p38 ) , .prog_clk_2_S_in ( p1060 ) , - .prog_clk_2_W_in ( p555 ) , + .prog_clk_1_W_out ( prog_clk_1_wires[163] ) , .prog_clk_2_N_in ( p3534 ) , + .prog_clk_2_E_in ( p276 ) , .prog_clk_2_S_in ( p430 ) , + .prog_clk_2_W_in ( p687 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_4202 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_4203 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_4204 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_4205 ) , - .prog_clk_3_W_in ( p2522 ) , .prog_clk_3_E_in ( p715 ) , - .prog_clk_3_S_in ( p631 ) , .prog_clk_3_N_in ( p3506 ) , + .prog_clk_3_W_in ( p3240 ) , .prog_clk_3_E_in ( p810 ) , + .prog_clk_3_S_in ( p1009 ) , .prog_clk_3_N_in ( p3524 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_4206 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4207 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_4208 ) , .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_4209 ) , .clk_1_N_in ( SYNOPSYS_UNCONNECTED_4210 ) , .clk_1_S_in ( clk_2_wires[109] ) , .clk_1_E_out ( clk_1_wires[162] ) , - .clk_1_W_out ( clk_1_wires[163] ) , .clk_2_N_in ( p2937 ) , - .clk_2_E_in ( p1042 ) , .clk_2_S_in ( p2561 ) , .clk_2_W_in ( p2309 ) , + .clk_1_W_out ( clk_1_wires[163] ) , .clk_2_N_in ( p3461 ) , + .clk_2_E_in ( p1175 ) , .clk_2_S_in ( p441 ) , .clk_2_W_in ( p3282 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_4211 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_4212 ) , .clk_2_N_out ( SYNOPSYS_UNCONNECTED_4213 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_4214 ) , .clk_3_W_in ( p2522 ) , - .clk_3_E_in ( p966 ) , .clk_3_S_in ( p277 ) , .clk_3_N_in ( p2916 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_4214 ) , .clk_3_W_in ( p3360 ) , + .clk_3_E_in ( p476 ) , .clk_3_S_in ( p1194 ) , .clk_3_N_in ( p3440 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_4215 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4216 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_4217 ) , @@ -116008,38 +120547,38 @@ sb_1__1_ sb_8__1_ ( .chanx_right_out ( sb_1__1__77_chanx_right_out ) , .chany_bottom_out ( sb_1__1__77_chany_bottom_out ) , .chanx_left_out ( sb_1__1__77_chanx_left_out ) , - .ccff_tail ( sb_1__1__77_ccff_tail ) , .Test_en_S_in ( p3200 ) , + .ccff_tail ( sb_1__1__77_ccff_tail ) , .Test_en_S_in ( p1426 ) , .Test_en_N_out ( SYNOPSYS_UNCONNECTED_4220 ) , .pReset_S_in ( SYNOPSYS_UNCONNECTED_4221 ) , .pReset_E_in ( SYNOPSYS_UNCONNECTED_4222 ) , .pReset_W_in ( pResetWires[91] ) , .pReset_N_out ( pResetWires[93] ) , .pReset_W_out ( SYNOPSYS_UNCONNECTED_4223 ) , - .pReset_E_out ( pResetWires[94] ) , .Reset_S_in ( p3457 ) , + .pReset_E_out ( pResetWires[94] ) , .Reset_S_in ( p1426 ) , .Reset_N_out ( SYNOPSYS_UNCONNECTED_4224 ) , - .prog_clk_0_N_in ( prog_clk_0_wires[296] ) , .prog_clk_1_N_in ( p1389 ) , - .prog_clk_1_S_in ( p856 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[296] ) , .prog_clk_1_N_in ( p1581 ) , + .prog_clk_1_S_in ( p973 ) , .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_4225 ) , .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_4226 ) , - .prog_clk_2_N_in ( p3375 ) , .prog_clk_2_E_in ( p957 ) , - .prog_clk_2_S_in ( p121 ) , .prog_clk_2_W_in ( p373 ) , + .prog_clk_2_N_in ( p3542 ) , .prog_clk_2_E_in ( p374 ) , + .prog_clk_2_S_in ( p510 ) , .prog_clk_2_W_in ( p838 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_4227 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_4228 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_4229 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_4230 ) , - .prog_clk_3_W_in ( p1760 ) , .prog_clk_3_E_in ( p1016 ) , - .prog_clk_3_S_in ( p989 ) , .prog_clk_3_N_in ( p3336 ) , + .prog_clk_3_W_in ( p3128 ) , .prog_clk_3_E_in ( p823 ) , + .prog_clk_3_S_in ( p1098 ) , .prog_clk_3_N_in ( p3515 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_4231 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4232 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_4233 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_4234 ) , .clk_1_N_in ( p1389 ) , - .clk_1_S_in ( p332 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_4235 ) , - .clk_1_W_out ( SYNOPSYS_UNCONNECTED_4236 ) , .clk_2_N_in ( p3397 ) , - .clk_2_E_in ( p0 ) , .clk_2_S_in ( p3441 ) , .clk_2_W_in ( p1731 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_4234 ) , .clk_1_N_in ( p1581 ) , + .clk_1_S_in ( p330 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_4235 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_4236 ) , .clk_2_N_in ( p3261 ) , + .clk_2_E_in ( p0 ) , .clk_2_S_in ( p74 ) , .clk_2_W_in ( p3299 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_4237 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_4238 ) , .clk_2_N_out ( SYNOPSYS_UNCONNECTED_4239 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_4240 ) , .clk_3_W_in ( p1760 ) , - .clk_3_E_in ( p566 ) , .clk_3_S_in ( p847 ) , .clk_3_N_in ( p3388 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_4240 ) , .clk_3_W_in ( p3333 ) , + .clk_3_E_in ( p1057 ) , .clk_3_S_in ( p1341 ) , .clk_3_N_in ( p3181 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_4241 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4242 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_4243 ) , @@ -116087,16 +120626,16 @@ sb_1__1_ sb_8__2_ ( .chanx_right_out ( sb_1__1__78_chanx_right_out ) , .chany_bottom_out ( sb_1__1__78_chany_bottom_out ) , .chanx_left_out ( sb_1__1__78_chanx_left_out ) , - .ccff_tail ( sb_1__1__78_ccff_tail ) , .Test_en_S_in ( p1947 ) , + .ccff_tail ( sb_1__1__78_ccff_tail ) , .Test_en_S_in ( p2549 ) , .Test_en_N_out ( SYNOPSYS_UNCONNECTED_4246 ) , .pReset_S_in ( SYNOPSYS_UNCONNECTED_4247 ) , .pReset_E_in ( SYNOPSYS_UNCONNECTED_4248 ) , .pReset_W_in ( pResetWires[140] ) , .pReset_N_out ( pResetWires[142] ) , .pReset_W_out ( SYNOPSYS_UNCONNECTED_4249 ) , - .pReset_E_out ( pResetWires[143] ) , .Reset_S_in ( p1947 ) , + .pReset_E_out ( pResetWires[143] ) , .Reset_S_in ( p2549 ) , .Reset_N_out ( SYNOPSYS_UNCONNECTED_4250 ) , - .prog_clk_0_N_in ( prog_clk_0_wires[299] ) , .prog_clk_1_N_in ( p1620 ) , - .prog_clk_1_S_in ( p891 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[299] ) , .prog_clk_1_N_in ( p2321 ) , + .prog_clk_1_S_in ( p436 ) , .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_4251 ) , .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_4252 ) , .prog_clk_2_N_in ( prog_clk_3_wires[43] ) , @@ -116106,14 +120645,14 @@ sb_1__1_ sb_8__2_ ( .prog_clk_2_W_out ( prog_clk_2_wires[71] ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_4256 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_4257 ) , - .prog_clk_2_E_out ( prog_clk_2_wires[69] ) , .prog_clk_3_W_in ( p2152 ) , - .prog_clk_3_E_in ( p798 ) , .prog_clk_3_S_in ( p740 ) , - .prog_clk_3_N_in ( p699 ) , + .prog_clk_2_E_out ( prog_clk_2_wires[69] ) , .prog_clk_3_W_in ( p2047 ) , + .prog_clk_3_E_in ( p871 ) , .prog_clk_3_S_in ( p125 ) , + .prog_clk_3_N_in ( p788 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_4258 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4259 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_4260 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_4261 ) , .clk_1_N_in ( p1620 ) , - .clk_1_S_in ( p301 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_4262 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_4261 ) , .clk_1_N_in ( p2321 ) , + .clk_1_S_in ( p1106 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_4262 ) , .clk_1_W_out ( SYNOPSYS_UNCONNECTED_4263 ) , .clk_2_N_in ( clk_3_wires[43] ) , .clk_2_E_in ( SYNOPSYS_UNCONNECTED_4264 ) , @@ -116122,8 +120661,8 @@ sb_1__1_ sb_8__2_ ( .clk_2_W_out ( clk_2_wires[71] ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_4267 ) , .clk_2_N_out ( SYNOPSYS_UNCONNECTED_4268 ) , - .clk_2_E_out ( clk_2_wires[69] ) , .clk_3_W_in ( p2152 ) , - .clk_3_E_in ( p1634 ) , .clk_3_S_in ( p1720 ) , .clk_3_N_in ( p460 ) , + .clk_2_E_out ( clk_2_wires[69] ) , .clk_3_W_in ( p2047 ) , + .clk_3_E_in ( p341 ) , .clk_3_S_in ( p2377 ) , .clk_3_N_in ( p2122 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_4269 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4270 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_4271 ) , @@ -116171,20 +120710,20 @@ sb_1__1_ sb_8__3_ ( .chanx_right_out ( sb_1__1__79_chanx_right_out ) , .chany_bottom_out ( sb_1__1__79_chany_bottom_out ) , .chanx_left_out ( sb_1__1__79_chanx_left_out ) , - .ccff_tail ( sb_1__1__79_ccff_tail ) , .Test_en_S_in ( p2643 ) , + .ccff_tail ( sb_1__1__79_ccff_tail ) , .Test_en_S_in ( p2262 ) , .Test_en_N_out ( SYNOPSYS_UNCONNECTED_4274 ) , .pReset_S_in ( SYNOPSYS_UNCONNECTED_4275 ) , .pReset_E_in ( SYNOPSYS_UNCONNECTED_4276 ) , .pReset_W_in ( pResetWires[189] ) , .pReset_N_out ( pResetWires[191] ) , .pReset_W_out ( SYNOPSYS_UNCONNECTED_4277 ) , - .pReset_E_out ( pResetWires[192] ) , .Reset_S_in ( p2643 ) , + .pReset_E_out ( pResetWires[192] ) , .Reset_S_in ( p2262 ) , .Reset_N_out ( SYNOPSYS_UNCONNECTED_4278 ) , - .prog_clk_0_N_in ( prog_clk_0_wires[302] ) , .prog_clk_1_N_in ( p1509 ) , - .prog_clk_1_S_in ( p664 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[302] ) , .prog_clk_1_N_in ( p1601 ) , + .prog_clk_1_S_in ( p568 ) , .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_4279 ) , .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_4280 ) , - .prog_clk_2_N_in ( p2267 ) , .prog_clk_2_E_in ( p639 ) , - .prog_clk_2_S_in ( p1967 ) , .prog_clk_2_W_in ( p323 ) , + .prog_clk_2_N_in ( p2325 ) , .prog_clk_2_E_in ( p459 ) , + .prog_clk_2_S_in ( p1782 ) , .prog_clk_2_W_in ( p506 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_4281 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_4282 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_4283 ) , @@ -116196,10 +120735,10 @@ sb_1__1_ sb_8__3_ ( .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_4288 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4289 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_4290 ) , - .prog_clk_3_S_out ( prog_clk_3_wires[42] ) , .clk_1_N_in ( p1509 ) , - .clk_1_S_in ( p128 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_4291 ) , - .clk_1_W_out ( SYNOPSYS_UNCONNECTED_4292 ) , .clk_2_N_in ( p2267 ) , - .clk_2_E_in ( p265 ) , .clk_2_S_in ( p2564 ) , .clk_2_W_in ( p1185 ) , + .prog_clk_3_S_out ( prog_clk_3_wires[42] ) , .clk_1_N_in ( p1601 ) , + .clk_1_S_in ( p831 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_4291 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_4292 ) , .clk_2_N_in ( p1497 ) , + .clk_2_E_in ( p699 ) , .clk_2_S_in ( p2067 ) , .clk_2_W_in ( p885 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_4293 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_4294 ) , .clk_2_N_out ( SYNOPSYS_UNCONNECTED_4295 ) , @@ -116255,16 +120794,16 @@ sb_1__1_ sb_8__4_ ( .chanx_right_out ( sb_1__1__80_chanx_right_out ) , .chany_bottom_out ( sb_1__1__80_chany_bottom_out ) , .chanx_left_out ( sb_1__1__80_chanx_left_out ) , - .ccff_tail ( sb_1__1__80_ccff_tail ) , .Test_en_S_in ( p1822 ) , + .ccff_tail ( sb_1__1__80_ccff_tail ) , .Test_en_S_in ( p1902 ) , .Test_en_N_out ( SYNOPSYS_UNCONNECTED_4304 ) , .pReset_S_in ( SYNOPSYS_UNCONNECTED_4305 ) , .pReset_E_in ( SYNOPSYS_UNCONNECTED_4306 ) , .pReset_W_in ( pResetWires[238] ) , .pReset_N_out ( pResetWires[240] ) , .pReset_W_out ( SYNOPSYS_UNCONNECTED_4307 ) , - .pReset_E_out ( pResetWires[241] ) , .Reset_S_in ( p1822 ) , + .pReset_E_out ( pResetWires[241] ) , .Reset_S_in ( p1902 ) , .Reset_N_out ( SYNOPSYS_UNCONNECTED_4308 ) , - .prog_clk_0_N_in ( prog_clk_0_wires[305] ) , .prog_clk_1_N_in ( p1174 ) , - .prog_clk_1_S_in ( p509 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[305] ) , .prog_clk_1_N_in ( p1856 ) , + .prog_clk_1_S_in ( p1715 ) , .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_4309 ) , .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_4310 ) , .prog_clk_2_N_in ( prog_clk_3_wires[33] ) , @@ -116282,8 +120821,8 @@ sb_1__1_ sb_8__4_ ( .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_4319 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4320 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_4321 ) , - .prog_clk_3_S_out ( prog_clk_3_wires[38] ) , .clk_1_N_in ( p1174 ) , - .clk_1_S_in ( p1649 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_4322 ) , + .prog_clk_3_S_out ( prog_clk_3_wires[38] ) , .clk_1_N_in ( p1856 ) , + .clk_1_S_in ( p208 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_4322 ) , .clk_1_W_out ( SYNOPSYS_UNCONNECTED_4323 ) , .clk_2_N_in ( clk_3_wires[33] ) , .clk_2_E_in ( SYNOPSYS_UNCONNECTED_4324 ) , @@ -116344,20 +120883,20 @@ sb_1__1_ sb_8__5_ ( .chanx_right_out ( sb_1__1__81_chanx_right_out ) , .chany_bottom_out ( sb_1__1__81_chany_bottom_out ) , .chanx_left_out ( sb_1__1__81_chanx_left_out ) , - .ccff_tail ( sb_1__1__81_ccff_tail ) , .Test_en_S_in ( p2962 ) , + .ccff_tail ( sb_1__1__81_ccff_tail ) , .Test_en_S_in ( p2512 ) , .Test_en_N_out ( SYNOPSYS_UNCONNECTED_4336 ) , .pReset_S_in ( SYNOPSYS_UNCONNECTED_4337 ) , .pReset_E_in ( SYNOPSYS_UNCONNECTED_4338 ) , .pReset_W_in ( pResetWires[287] ) , .pReset_N_out ( pResetWires[289] ) , .pReset_W_out ( SYNOPSYS_UNCONNECTED_4339 ) , - .pReset_E_out ( pResetWires[290] ) , .Reset_S_in ( p3252 ) , + .pReset_E_out ( pResetWires[290] ) , .Reset_S_in ( p2512 ) , .Reset_N_out ( SYNOPSYS_UNCONNECTED_4340 ) , - .prog_clk_0_N_in ( prog_clk_0_wires[308] ) , .prog_clk_1_N_in ( p1748 ) , - .prog_clk_1_S_in ( p233 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[308] ) , .prog_clk_1_N_in ( p1617 ) , + .prog_clk_1_S_in ( p137 ) , .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_4341 ) , .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_4342 ) , - .prog_clk_2_N_in ( p1833 ) , .prog_clk_2_E_in ( p811 ) , - .prog_clk_2_S_in ( p1625 ) , .prog_clk_2_W_in ( p1164 ) , + .prog_clk_2_N_in ( p2484 ) , .prog_clk_2_E_in ( p486 ) , + .prog_clk_2_S_in ( p2055 ) , .prog_clk_2_W_in ( p827 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_4343 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_4344 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_4345 ) , @@ -116369,10 +120908,10 @@ sb_1__1_ sb_8__5_ ( .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_4350 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4351 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_4352 ) , - .prog_clk_3_S_out ( prog_clk_3_wires[32] ) , .clk_1_N_in ( p1748 ) , - .clk_1_S_in ( p910 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_4353 ) , - .clk_1_W_out ( SYNOPSYS_UNCONNECTED_4354 ) , .clk_2_N_in ( p1924 ) , - .clk_2_E_in ( p47 ) , .clk_2_S_in ( p3211 ) , .clk_2_W_in ( p389 ) , + .prog_clk_3_S_out ( prog_clk_3_wires[32] ) , .clk_1_N_in ( p1617 ) , + .clk_1_S_in ( p905 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_4353 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_4354 ) , .clk_2_N_in ( p1976 ) , + .clk_2_E_in ( p491 ) , .clk_2_S_in ( p2384 ) , .clk_2_W_in ( p304 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_4355 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_4356 ) , .clk_2_N_out ( SYNOPSYS_UNCONNECTED_4357 ) , @@ -116428,20 +120967,20 @@ sb_1__1_ sb_8__6_ ( .chanx_right_out ( sb_1__1__82_chanx_right_out ) , .chany_bottom_out ( sb_1__1__82_chany_bottom_out ) , .chanx_left_out ( sb_1__1__82_chanx_left_out ) , - .ccff_tail ( sb_1__1__82_ccff_tail ) , .Test_en_S_in ( p2206 ) , + .ccff_tail ( sb_1__1__82_ccff_tail ) , .Test_en_S_in ( p2516 ) , .Test_en_N_out ( SYNOPSYS_UNCONNECTED_4366 ) , .pReset_S_in ( SYNOPSYS_UNCONNECTED_4367 ) , .pReset_E_in ( SYNOPSYS_UNCONNECTED_4368 ) , .pReset_W_in ( pResetWires[336] ) , .pReset_N_out ( pResetWires[338] ) , .pReset_W_out ( SYNOPSYS_UNCONNECTED_4369 ) , - .pReset_E_out ( pResetWires[339] ) , .Reset_S_in ( p3107 ) , + .pReset_E_out ( pResetWires[339] ) , .Reset_S_in ( p2516 ) , .Reset_N_out ( SYNOPSYS_UNCONNECTED_4370 ) , - .prog_clk_0_N_in ( prog_clk_0_wires[311] ) , .prog_clk_1_N_in ( p1861 ) , - .prog_clk_1_S_in ( p144 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[311] ) , .prog_clk_1_N_in ( p1328 ) , + .prog_clk_1_S_in ( p43 ) , .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_4371 ) , .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_4372 ) , - .prog_clk_2_N_in ( p2957 ) , .prog_clk_2_E_in ( p294 ) , - .prog_clk_2_S_in ( p1661 ) , .prog_clk_2_W_in ( p386 ) , + .prog_clk_2_N_in ( p2046 ) , .prog_clk_2_E_in ( p512 ) , + .prog_clk_2_S_in ( p385 ) , .prog_clk_2_W_in ( p511 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_4373 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_4374 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_4375 ) , @@ -116453,10 +120992,10 @@ sb_1__1_ sb_8__6_ ( .prog_clk_3_E_out ( prog_clk_3_wires[44] ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4380 ) , .prog_clk_3_N_out ( prog_clk_3_wires[26] ) , - .prog_clk_3_S_out ( prog_clk_3_wires[28] ) , .clk_1_N_in ( p1861 ) , - .clk_1_S_in ( p839 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_4381 ) , - .clk_1_W_out ( SYNOPSYS_UNCONNECTED_4382 ) , .clk_2_N_in ( p2926 ) , - .clk_2_E_in ( p822 ) , .clk_2_S_in ( p3001 ) , .clk_2_W_in ( p1247 ) , + .prog_clk_3_S_out ( prog_clk_3_wires[28] ) , .clk_1_N_in ( p1328 ) , + .clk_1_S_in ( p1002 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_4381 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_4382 ) , .clk_2_N_in ( p2046 ) , + .clk_2_E_in ( p801 ) , .clk_2_S_in ( p2390 ) , .clk_2_W_in ( p370 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_4383 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_4384 ) , .clk_2_N_out ( SYNOPSYS_UNCONNECTED_4385 ) , @@ -116511,20 +121050,20 @@ sb_1__1_ sb_8__7_ ( .chanx_right_out ( sb_1__1__83_chanx_right_out ) , .chany_bottom_out ( sb_1__1__83_chany_bottom_out ) , .chanx_left_out ( sb_1__1__83_chanx_left_out ) , - .ccff_tail ( sb_1__1__83_ccff_tail ) , .Test_en_S_in ( p2136 ) , + .ccff_tail ( sb_1__1__83_ccff_tail ) , .Test_en_S_in ( p2523 ) , .Test_en_N_out ( SYNOPSYS_UNCONNECTED_4392 ) , .pReset_S_in ( SYNOPSYS_UNCONNECTED_4393 ) , .pReset_E_in ( SYNOPSYS_UNCONNECTED_4394 ) , .pReset_W_in ( pResetWires[385] ) , .pReset_N_out ( pResetWires[387] ) , .pReset_W_out ( SYNOPSYS_UNCONNECTED_4395 ) , - .pReset_E_out ( pResetWires[388] ) , .Reset_S_in ( p3271 ) , + .pReset_E_out ( pResetWires[388] ) , .Reset_S_in ( p2523 ) , .Reset_N_out ( SYNOPSYS_UNCONNECTED_4396 ) , - .prog_clk_0_N_in ( prog_clk_0_wires[314] ) , .prog_clk_1_N_in ( p1827 ) , - .prog_clk_1_S_in ( p868 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[314] ) , .prog_clk_1_N_in ( p1445 ) , + .prog_clk_1_S_in ( p1225 ) , .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_4397 ) , .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_4398 ) , - .prog_clk_2_N_in ( p2463 ) , .prog_clk_2_E_in ( p152 ) , - .prog_clk_2_S_in ( p1645 ) , .prog_clk_2_W_in ( p177 ) , + .prog_clk_2_N_in ( p2501 ) , .prog_clk_2_E_in ( p433 ) , + .prog_clk_2_S_in ( p387 ) , .prog_clk_2_W_in ( p171 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_4399 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_4400 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_4401 ) , @@ -116536,10 +121075,10 @@ sb_1__1_ sb_8__7_ ( .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_4406 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4407 ) , .prog_clk_3_N_out ( prog_clk_3_wires[30] ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_4408 ) , .clk_1_N_in ( p1827 ) , - .clk_1_S_in ( p507 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_4409 ) , - .clk_1_W_out ( SYNOPSYS_UNCONNECTED_4410 ) , .clk_2_N_in ( p2463 ) , - .clk_2_E_in ( p942 ) , .clk_2_S_in ( p3226 ) , .clk_2_W_in ( p528 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_4408 ) , .clk_1_N_in ( p1445 ) , + .clk_1_S_in ( p157 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_4409 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_4410 ) , .clk_2_N_in ( p2594 ) , + .clk_2_E_in ( p597 ) , .clk_2_S_in ( p2386 ) , .clk_2_W_in ( p590 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_4411 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_4412 ) , .clk_2_N_out ( SYNOPSYS_UNCONNECTED_4413 ) , @@ -116595,16 +121134,16 @@ sb_1__1_ sb_8__8_ ( .chanx_right_out ( sb_1__1__84_chanx_right_out ) , .chany_bottom_out ( sb_1__1__84_chany_bottom_out ) , .chanx_left_out ( sb_1__1__84_chanx_left_out ) , - .ccff_tail ( sb_1__1__84_ccff_tail ) , .Test_en_S_in ( p1491 ) , + .ccff_tail ( sb_1__1__84_ccff_tail ) , .Test_en_S_in ( p2323 ) , .Test_en_N_out ( SYNOPSYS_UNCONNECTED_4422 ) , .pReset_S_in ( SYNOPSYS_UNCONNECTED_4423 ) , .pReset_E_in ( SYNOPSYS_UNCONNECTED_4424 ) , .pReset_W_in ( pResetWires[434] ) , .pReset_N_out ( pResetWires[436] ) , .pReset_W_out ( SYNOPSYS_UNCONNECTED_4425 ) , - .pReset_E_out ( pResetWires[437] ) , .Reset_S_in ( p1491 ) , + .pReset_E_out ( pResetWires[437] ) , .Reset_S_in ( p2323 ) , .Reset_N_out ( SYNOPSYS_UNCONNECTED_4426 ) , - .prog_clk_0_N_in ( prog_clk_0_wires[317] ) , .prog_clk_1_N_in ( p1793 ) , - .prog_clk_1_S_in ( p165 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[317] ) , .prog_clk_1_N_in ( p1425 ) , + .prog_clk_1_S_in ( p2105 ) , .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_4427 ) , .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_4428 ) , .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_4429 ) , @@ -116622,8 +121161,8 @@ sb_1__1_ sb_8__8_ ( .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_4437 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4438 ) , .prog_clk_3_N_out ( prog_clk_3_wires[36] ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_4439 ) , .clk_1_N_in ( p1793 ) , - .clk_1_S_in ( p805 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_4440 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_4439 ) , .clk_1_N_in ( p1425 ) , + .clk_1_S_in ( p1187 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_4440 ) , .clk_1_W_out ( SYNOPSYS_UNCONNECTED_4441 ) , .clk_2_N_in ( SYNOPSYS_UNCONNECTED_4442 ) , .clk_2_E_in ( SYNOPSYS_UNCONNECTED_4443 ) , @@ -116684,20 +121223,20 @@ sb_1__1_ sb_8__9_ ( .chanx_right_out ( sb_1__1__85_chanx_right_out ) , .chany_bottom_out ( sb_1__1__85_chany_bottom_out ) , .chanx_left_out ( sb_1__1__85_chanx_left_out ) , - .ccff_tail ( sb_1__1__85_ccff_tail ) , .Test_en_S_in ( p2466 ) , + .ccff_tail ( sb_1__1__85_ccff_tail ) , .Test_en_S_in ( p2302 ) , .Test_en_N_out ( SYNOPSYS_UNCONNECTED_4454 ) , .pReset_S_in ( SYNOPSYS_UNCONNECTED_4455 ) , .pReset_E_in ( SYNOPSYS_UNCONNECTED_4456 ) , .pReset_W_in ( pResetWires[483] ) , .pReset_N_out ( pResetWires[485] ) , .pReset_W_out ( SYNOPSYS_UNCONNECTED_4457 ) , - .pReset_E_out ( pResetWires[486] ) , .Reset_S_in ( p2466 ) , + .pReset_E_out ( pResetWires[486] ) , .Reset_S_in ( p2302 ) , .Reset_N_out ( SYNOPSYS_UNCONNECTED_4458 ) , - .prog_clk_0_N_in ( prog_clk_0_wires[320] ) , .prog_clk_1_N_in ( p1563 ) , - .prog_clk_1_S_in ( p588 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[320] ) , .prog_clk_1_N_in ( p1486 ) , + .prog_clk_1_S_in ( p376 ) , .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_4459 ) , .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_4460 ) , - .prog_clk_2_N_in ( p2433 ) , .prog_clk_2_E_in ( p909 ) , - .prog_clk_2_S_in ( p2011 ) , .prog_clk_2_W_in ( p345 ) , + .prog_clk_2_N_in ( p1867 ) , .prog_clk_2_E_in ( p757 ) , + .prog_clk_2_S_in ( p791 ) , .prog_clk_2_W_in ( p165 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_4461 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_4462 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_4463 ) , @@ -116709,10 +121248,10 @@ sb_1__1_ sb_8__9_ ( .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_4468 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4469 ) , .prog_clk_3_N_out ( prog_clk_3_wires[40] ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_4470 ) , .clk_1_N_in ( p1563 ) , - .clk_1_S_in ( p1028 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_4471 ) , - .clk_1_W_out ( SYNOPSYS_UNCONNECTED_4472 ) , .clk_2_N_in ( p2121 ) , - .clk_2_E_in ( p115 ) , .clk_2_S_in ( p2307 ) , .clk_2_W_in ( p894 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_4470 ) , .clk_1_N_in ( p1486 ) , + .clk_1_S_in ( p848 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_4471 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_4472 ) , .clk_2_N_in ( p1867 ) , + .clk_2_E_in ( p814 ) , .clk_2_S_in ( p2116 ) , .clk_2_W_in ( p873 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_4473 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_4474 ) , .clk_2_N_out ( SYNOPSYS_UNCONNECTED_4475 ) , @@ -116768,16 +121307,16 @@ sb_1__1_ sb_8__10_ ( .chanx_right_out ( sb_1__1__86_chanx_right_out ) , .chany_bottom_out ( sb_1__1__86_chany_bottom_out ) , .chanx_left_out ( sb_1__1__86_chanx_left_out ) , - .ccff_tail ( sb_1__1__86_ccff_tail ) , .Test_en_S_in ( p1907 ) , + .ccff_tail ( sb_1__1__86_ccff_tail ) , .Test_en_S_in ( p2241 ) , .Test_en_N_out ( SYNOPSYS_UNCONNECTED_4484 ) , .pReset_S_in ( SYNOPSYS_UNCONNECTED_4485 ) , .pReset_E_in ( SYNOPSYS_UNCONNECTED_4486 ) , .pReset_W_in ( pResetWires[532] ) , .pReset_N_out ( pResetWires[534] ) , .pReset_W_out ( SYNOPSYS_UNCONNECTED_4487 ) , - .pReset_E_out ( pResetWires[535] ) , .Reset_S_in ( p1907 ) , + .pReset_E_out ( pResetWires[535] ) , .Reset_S_in ( p2241 ) , .Reset_N_out ( SYNOPSYS_UNCONNECTED_4488 ) , - .prog_clk_0_N_in ( prog_clk_0_wires[323] ) , .prog_clk_1_N_in ( p1562 ) , - .prog_clk_1_S_in ( p55 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[323] ) , .prog_clk_1_N_in ( p2264 ) , + .prog_clk_1_S_in ( p623 ) , .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_4489 ) , .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_4490 ) , .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_4491 ) , @@ -116787,14 +121326,14 @@ sb_1__1_ sb_8__10_ ( .prog_clk_2_W_out ( prog_clk_2_wires[106] ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_4494 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_4495 ) , - .prog_clk_2_E_out ( prog_clk_2_wires[104] ) , .prog_clk_3_W_in ( p2183 ) , - .prog_clk_3_E_in ( p1074 ) , .prog_clk_3_S_in ( p1969 ) , - .prog_clk_3_N_in ( p750 ) , + .prog_clk_2_E_out ( prog_clk_2_wires[104] ) , .prog_clk_3_W_in ( p1434 ) , + .prog_clk_3_E_in ( p20 ) , .prog_clk_3_S_in ( p2087 ) , + .prog_clk_3_N_in ( p468 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_4496 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4497 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_4498 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_4499 ) , .clk_1_N_in ( p1562 ) , - .clk_1_S_in ( p515 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_4500 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_4499 ) , .clk_1_N_in ( p2264 ) , + .clk_1_S_in ( p886 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_4500 ) , .clk_1_W_out ( SYNOPSYS_UNCONNECTED_4501 ) , .clk_2_N_in ( SYNOPSYS_UNCONNECTED_4502 ) , .clk_2_E_in ( SYNOPSYS_UNCONNECTED_4503 ) , @@ -116803,8 +121342,8 @@ sb_1__1_ sb_8__10_ ( .clk_2_W_out ( clk_2_wires[106] ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_4505 ) , .clk_2_N_out ( SYNOPSYS_UNCONNECTED_4506 ) , - .clk_2_E_out ( clk_2_wires[104] ) , .clk_3_W_in ( p2183 ) , - .clk_3_E_in ( p2009 ) , .clk_3_S_in ( p1730 ) , .clk_3_N_in ( p293 ) , + .clk_2_E_out ( clk_2_wires[104] ) , .clk_3_W_in ( p1434 ) , + .clk_3_E_in ( p916 ) , .clk_3_S_in ( p2150 ) , .clk_3_N_in ( p2118 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_4507 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4508 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_4509 ) , @@ -116852,38 +121391,38 @@ sb_1__1_ sb_8__11_ ( .chanx_right_out ( sb_1__1__87_chanx_right_out ) , .chany_bottom_out ( sb_1__1__87_chany_bottom_out ) , .chanx_left_out ( sb_1__1__87_chanx_left_out ) , - .ccff_tail ( sb_1__1__87_ccff_tail ) , .Test_en_S_in ( p2997 ) , + .ccff_tail ( sb_1__1__87_ccff_tail ) , .Test_en_S_in ( p1860 ) , .Test_en_N_out ( SYNOPSYS_UNCONNECTED_4512 ) , .pReset_S_in ( SYNOPSYS_UNCONNECTED_4513 ) , .pReset_E_in ( SYNOPSYS_UNCONNECTED_4514 ) , .pReset_W_in ( pResetWires[581] ) , .pReset_N_out ( pResetWires[583] ) , .pReset_W_out ( SYNOPSYS_UNCONNECTED_4515 ) , - .pReset_E_out ( pResetWires[584] ) , .Reset_S_in ( p3373 ) , + .pReset_E_out ( pResetWires[584] ) , .Reset_S_in ( p1860 ) , .Reset_N_out ( SYNOPSYS_UNCONNECTED_4516 ) , - .prog_clk_0_N_in ( prog_clk_0_wires[326] ) , .prog_clk_1_N_in ( p1539 ) , - .prog_clk_1_S_in ( p438 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[326] ) , .prog_clk_1_N_in ( p1473 ) , + .prog_clk_1_S_in ( p621 ) , .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_4517 ) , .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_4518 ) , - .prog_clk_2_N_in ( p3410 ) , .prog_clk_2_E_in ( p731 ) , - .prog_clk_2_S_in ( p1627 ) , .prog_clk_2_W_in ( p196 ) , + .prog_clk_2_N_in ( p3575 ) , .prog_clk_2_E_in ( p520 ) , + .prog_clk_2_S_in ( p1250 ) , .prog_clk_2_W_in ( p185 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_4519 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_4520 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_4521 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_4522 ) , - .prog_clk_3_W_in ( p3078 ) , .prog_clk_3_E_in ( p982 ) , - .prog_clk_3_S_in ( p339 ) , .prog_clk_3_N_in ( p3382 ) , + .prog_clk_3_W_in ( p2762 ) , .prog_clk_3_E_in ( p16 ) , + .prog_clk_3_S_in ( p7 ) , .prog_clk_3_N_in ( p3565 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_4523 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4524 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_4525 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_4526 ) , .clk_1_N_in ( p1539 ) , - .clk_1_S_in ( p993 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_4527 ) , - .clk_1_W_out ( SYNOPSYS_UNCONNECTED_4528 ) , .clk_2_N_in ( p3402 ) , - .clk_2_E_in ( p833 ) , .clk_2_S_in ( p3334 ) , .clk_2_W_in ( p3006 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_4526 ) , .clk_1_N_in ( p1473 ) , + .clk_1_S_in ( p730 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_4527 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_4528 ) , .clk_2_N_in ( p3589 ) , + .clk_2_E_in ( p1279 ) , .clk_2_S_in ( p1105 ) , .clk_2_W_in ( p3605 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_4529 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_4530 ) , .clk_2_N_out ( SYNOPSYS_UNCONNECTED_4531 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_4532 ) , .clk_3_W_in ( p3078 ) , - .clk_3_E_in ( p274 ) , .clk_3_S_in ( p14 ) , .clk_3_N_in ( p3394 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_4532 ) , .clk_3_W_in ( p3610 ) , + .clk_3_E_in ( p337 ) , .clk_3_S_in ( p1781 ) , .clk_3_N_in ( p3584 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_4533 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4534 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_4535 ) , @@ -116931,27 +121470,27 @@ sb_1__1_ sb_9__1_ ( .chanx_right_out ( sb_1__1__88_chanx_right_out ) , .chany_bottom_out ( sb_1__1__88_chany_bottom_out ) , .chanx_left_out ( sb_1__1__88_chanx_left_out ) , - .ccff_tail ( sb_1__1__88_ccff_tail ) , .Test_en_S_in ( p2936 ) , + .ccff_tail ( sb_1__1__88_ccff_tail ) , .Test_en_S_in ( p1545 ) , .Test_en_N_out ( SYNOPSYS_UNCONNECTED_4538 ) , .pReset_S_in ( SYNOPSYS_UNCONNECTED_4539 ) , .pReset_E_in ( SYNOPSYS_UNCONNECTED_4540 ) , .pReset_W_in ( pResetWires[95] ) , .pReset_N_out ( pResetWires[97] ) , .pReset_W_out ( SYNOPSYS_UNCONNECTED_4541 ) , - .pReset_E_out ( pResetWires[98] ) , .Reset_S_in ( p2936 ) , + .pReset_E_out ( pResetWires[98] ) , .Reset_S_in ( p1545 ) , .Reset_N_out ( SYNOPSYS_UNCONNECTED_4542 ) , .prog_clk_0_N_in ( prog_clk_0_wires[334] ) , .prog_clk_1_N_in ( prog_clk_2_wires[76] ) , .prog_clk_1_S_in ( SYNOPSYS_UNCONNECTED_4543 ) , .prog_clk_1_E_out ( prog_clk_1_wires[169] ) , - .prog_clk_1_W_out ( prog_clk_1_wires[170] ) , .prog_clk_2_N_in ( p3282 ) , - .prog_clk_2_E_in ( p370 ) , .prog_clk_2_S_in ( p1409 ) , - .prog_clk_2_W_in ( p58 ) , + .prog_clk_1_W_out ( prog_clk_1_wires[170] ) , .prog_clk_2_N_in ( p3509 ) , + .prog_clk_2_E_in ( p213 ) , .prog_clk_2_S_in ( p711 ) , + .prog_clk_2_W_in ( p292 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_4544 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_4545 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_4546 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_4547 ) , - .prog_clk_3_W_in ( p3062 ) , .prog_clk_3_E_in ( p1061 ) , - .prog_clk_3_S_in ( p188 ) , .prog_clk_3_N_in ( p3304 ) , + .prog_clk_3_W_in ( p2983 ) , .prog_clk_3_E_in ( p1066 ) , + .prog_clk_3_S_in ( p1306 ) , .prog_clk_3_N_in ( p3493 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_4548 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4549 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_4550 ) , @@ -116959,12 +121498,12 @@ sb_1__1_ sb_9__1_ ( .clk_1_N_in ( clk_2_wires[76] ) , .clk_1_S_in ( SYNOPSYS_UNCONNECTED_4552 ) , .clk_1_E_out ( clk_1_wires[169] ) , .clk_1_W_out ( clk_1_wires[170] ) , - .clk_2_N_in ( p3493 ) , .clk_2_E_in ( p157 ) , .clk_2_S_in ( p2878 ) , - .clk_2_W_in ( p3014 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_4553 ) , + .clk_2_N_in ( p2821 ) , .clk_2_E_in ( p1192 ) , .clk_2_S_in ( p55 ) , + .clk_2_W_in ( p3189 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_4553 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_4554 ) , .clk_2_N_out ( SYNOPSYS_UNCONNECTED_4555 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_4556 ) , .clk_3_W_in ( p3062 ) , - .clk_3_E_in ( p955 ) , .clk_3_S_in ( p1304 ) , .clk_3_N_in ( p3490 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_4556 ) , .clk_3_W_in ( p3249 ) , + .clk_3_E_in ( p326 ) , .clk_3_S_in ( p1143 ) , .clk_3_N_in ( p2655 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_4557 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4558 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_4559 ) , @@ -117012,16 +121551,16 @@ sb_1__1_ sb_9__2_ ( .chanx_right_out ( sb_1__1__89_chanx_right_out ) , .chany_bottom_out ( sb_1__1__89_chany_bottom_out ) , .chanx_left_out ( sb_1__1__89_chanx_left_out ) , - .ccff_tail ( sb_1__1__89_ccff_tail ) , .Test_en_S_in ( p2440 ) , + .ccff_tail ( sb_1__1__89_ccff_tail ) , .Test_en_S_in ( p1918 ) , .Test_en_N_out ( SYNOPSYS_UNCONNECTED_4562 ) , .pReset_S_in ( SYNOPSYS_UNCONNECTED_4563 ) , .pReset_E_in ( SYNOPSYS_UNCONNECTED_4564 ) , .pReset_W_in ( pResetWires[144] ) , .pReset_N_out ( pResetWires[146] ) , .pReset_W_out ( SYNOPSYS_UNCONNECTED_4565 ) , - .pReset_E_out ( pResetWires[147] ) , .Reset_S_in ( p2440 ) , + .pReset_E_out ( pResetWires[147] ) , .Reset_S_in ( p1918 ) , .Reset_N_out ( SYNOPSYS_UNCONNECTED_4566 ) , - .prog_clk_0_N_in ( prog_clk_0_wires[337] ) , .prog_clk_1_N_in ( p1903 ) , - .prog_clk_1_S_in ( p413 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[337] ) , .prog_clk_1_N_in ( p1462 ) , + .prog_clk_1_S_in ( p745 ) , .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_4567 ) , .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_4568 ) , .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_4569 ) , @@ -117032,13 +121571,13 @@ sb_1__1_ sb_9__2_ ( .prog_clk_2_S_out ( prog_clk_2_wires[75] ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_4573 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_4574 ) , - .prog_clk_3_W_in ( p1400 ) , .prog_clk_3_E_in ( p45 ) , - .prog_clk_3_S_in ( p646 ) , .prog_clk_3_N_in ( p763 ) , + .prog_clk_3_W_in ( p1636 ) , .prog_clk_3_E_in ( p851 ) , + .prog_clk_3_S_in ( p639 ) , .prog_clk_3_N_in ( p191 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_4575 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4576 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_4577 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_4578 ) , .clk_1_N_in ( p1903 ) , - .clk_1_S_in ( p1103 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_4579 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_4578 ) , .clk_1_N_in ( p1462 ) , + .clk_1_S_in ( p41 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_4579 ) , .clk_1_W_out ( SYNOPSYS_UNCONNECTED_4580 ) , .clk_2_N_in ( SYNOPSYS_UNCONNECTED_4581 ) , .clk_2_E_in ( SYNOPSYS_UNCONNECTED_4582 ) , @@ -117047,8 +121586,8 @@ sb_1__1_ sb_9__2_ ( .clk_2_W_out ( SYNOPSYS_UNCONNECTED_4584 ) , .clk_2_S_out ( clk_2_wires[75] ) , .clk_2_N_out ( SYNOPSYS_UNCONNECTED_4585 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_4586 ) , .clk_3_W_in ( p1400 ) , - .clk_3_E_in ( p821 ) , .clk_3_S_in ( p2336 ) , .clk_3_N_in ( p1633 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_4586 ) , .clk_3_W_in ( p1636 ) , + .clk_3_E_in ( p120 ) , .clk_3_S_in ( p1674 ) , .clk_3_N_in ( p753 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_4587 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4588 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_4589 ) , @@ -117096,27 +121635,27 @@ sb_1__1_ sb_9__3_ ( .chanx_right_out ( sb_1__1__90_chanx_right_out ) , .chany_bottom_out ( sb_1__1__90_chany_bottom_out ) , .chanx_left_out ( sb_1__1__90_chanx_left_out ) , - .ccff_tail ( sb_1__1__90_ccff_tail ) , .Test_en_S_in ( p3273 ) , + .ccff_tail ( sb_1__1__90_ccff_tail ) , .Test_en_S_in ( p1985 ) , .Test_en_N_out ( SYNOPSYS_UNCONNECTED_4592 ) , .pReset_S_in ( SYNOPSYS_UNCONNECTED_4593 ) , .pReset_E_in ( SYNOPSYS_UNCONNECTED_4594 ) , .pReset_W_in ( pResetWires[193] ) , .pReset_N_out ( pResetWires[195] ) , .pReset_W_out ( SYNOPSYS_UNCONNECTED_4595 ) , - .pReset_E_out ( pResetWires[196] ) , .Reset_S_in ( p3395 ) , + .pReset_E_out ( pResetWires[196] ) , .Reset_S_in ( p1985 ) , .Reset_N_out ( SYNOPSYS_UNCONNECTED_4596 ) , .prog_clk_0_N_in ( prog_clk_0_wires[340] ) , .prog_clk_1_N_in ( prog_clk_2_wires[89] ) , .prog_clk_1_S_in ( SYNOPSYS_UNCONNECTED_4597 ) , .prog_clk_1_E_out ( prog_clk_1_wires[176] ) , - .prog_clk_1_W_out ( prog_clk_1_wires[177] ) , .prog_clk_2_N_in ( p2379 ) , - .prog_clk_2_E_in ( p492 ) , .prog_clk_2_S_in ( p1270 ) , - .prog_clk_2_W_in ( p437 ) , + .prog_clk_1_W_out ( prog_clk_1_wires[177] ) , .prog_clk_2_N_in ( p3511 ) , + .prog_clk_2_E_in ( p347 ) , .prog_clk_2_S_in ( p195 ) , + .prog_clk_2_W_in ( p1012 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_4598 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_4599 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_4600 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_4601 ) , - .prog_clk_3_W_in ( p2204 ) , .prog_clk_3_E_in ( p1371 ) , - .prog_clk_3_S_in ( p640 ) , .prog_clk_3_N_in ( p2319 ) , + .prog_clk_3_W_in ( p3426 ) , .prog_clk_3_E_in ( p999 ) , + .prog_clk_3_S_in ( p1214 ) , .prog_clk_3_N_in ( p3479 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_4602 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4603 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_4604 ) , @@ -117124,12 +121663,12 @@ sb_1__1_ sb_9__3_ ( .clk_1_N_in ( clk_2_wires[89] ) , .clk_1_S_in ( SYNOPSYS_UNCONNECTED_4606 ) , .clk_1_E_out ( clk_1_wires[176] ) , .clk_1_W_out ( clk_1_wires[177] ) , - .clk_2_N_in ( p2265 ) , .clk_2_E_in ( p1053 ) , .clk_2_S_in ( p3380 ) , - .clk_2_W_in ( p2035 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_4607 ) , + .clk_2_N_in ( p3502 ) , .clk_2_E_in ( p551 ) , .clk_2_S_in ( p489 ) , + .clk_2_W_in ( p3521 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_4607 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_4608 ) , .clk_2_N_out ( SYNOPSYS_UNCONNECTED_4609 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_4610 ) , .clk_3_W_in ( p2204 ) , - .clk_3_E_in ( p147 ) , .clk_3_S_in ( p1326 ) , .clk_3_N_in ( p2048 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_4610 ) , .clk_3_W_in ( p3538 ) , + .clk_3_E_in ( p167 ) , .clk_3_S_in ( p1716 ) , .clk_3_N_in ( p3494 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_4611 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4612 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_4613 ) , @@ -117177,16 +121716,16 @@ sb_1__1_ sb_9__4_ ( .chanx_right_out ( sb_1__1__91_chanx_right_out ) , .chany_bottom_out ( sb_1__1__91_chany_bottom_out ) , .chanx_left_out ( sb_1__1__91_chanx_left_out ) , - .ccff_tail ( sb_1__1__91_ccff_tail ) , .Test_en_S_in ( p2836 ) , + .ccff_tail ( sb_1__1__91_ccff_tail ) , .Test_en_S_in ( p2801 ) , .Test_en_N_out ( SYNOPSYS_UNCONNECTED_4616 ) , .pReset_S_in ( SYNOPSYS_UNCONNECTED_4617 ) , .pReset_E_in ( SYNOPSYS_UNCONNECTED_4618 ) , .pReset_W_in ( pResetWires[242] ) , .pReset_N_out ( pResetWires[244] ) , .pReset_W_out ( SYNOPSYS_UNCONNECTED_4619 ) , - .pReset_E_out ( pResetWires[245] ) , .Reset_S_in ( p2836 ) , + .pReset_E_out ( pResetWires[245] ) , .Reset_S_in ( p2801 ) , .Reset_N_out ( SYNOPSYS_UNCONNECTED_4620 ) , - .prog_clk_0_N_in ( prog_clk_0_wires[343] ) , .prog_clk_1_N_in ( p1557 ) , - .prog_clk_1_S_in ( p832 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[343] ) , .prog_clk_1_N_in ( p2310 ) , + .prog_clk_1_S_in ( p1086 ) , .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_4621 ) , .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_4622 ) , .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_4623 ) , @@ -117197,13 +121736,13 @@ sb_1__1_ sb_9__4_ ( .prog_clk_2_S_out ( prog_clk_2_wires[88] ) , .prog_clk_2_N_out ( prog_clk_2_wires[86] ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_4627 ) , - .prog_clk_3_W_in ( p1614 ) , .prog_clk_3_E_in ( p744 ) , - .prog_clk_3_S_in ( p347 ) , .prog_clk_3_N_in ( p2017 ) , + .prog_clk_3_W_in ( p2218 ) , .prog_clk_3_E_in ( p812 ) , + .prog_clk_3_S_in ( p698 ) , .prog_clk_3_N_in ( p1803 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_4628 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4629 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_4630 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_4631 ) , .clk_1_N_in ( p1557 ) , - .clk_1_S_in ( p52 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_4632 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_4631 ) , .clk_1_N_in ( p2310 ) , + .clk_1_S_in ( p644 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_4632 ) , .clk_1_W_out ( SYNOPSYS_UNCONNECTED_4633 ) , .clk_2_N_in ( SYNOPSYS_UNCONNECTED_4634 ) , .clk_2_E_in ( SYNOPSYS_UNCONNECTED_4635 ) , @@ -117211,8 +121750,8 @@ sb_1__1_ sb_9__4_ ( .clk_2_W_in ( clk_2_wires[79] ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_4637 ) , .clk_2_S_out ( clk_2_wires[88] ) , .clk_2_N_out ( clk_2_wires[86] ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_4638 ) , .clk_3_W_in ( p1614 ) , - .clk_3_E_in ( p42 ) , .clk_3_S_in ( p2740 ) , .clk_3_N_in ( p361 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_4638 ) , .clk_3_W_in ( p2305 ) , + .clk_3_E_in ( p56 ) , .clk_3_S_in ( p2665 ) , .clk_3_N_in ( p2063 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_4639 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4640 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_4641 ) , @@ -117260,40 +121799,40 @@ sb_1__1_ sb_9__5_ ( .chanx_right_out ( sb_1__1__92_chanx_right_out ) , .chany_bottom_out ( sb_1__1__92_chany_bottom_out ) , .chanx_left_out ( sb_1__1__92_chanx_left_out ) , - .ccff_tail ( sb_1__1__92_ccff_tail ) , .Test_en_S_in ( p2826 ) , + .ccff_tail ( sb_1__1__92_ccff_tail ) , .Test_en_S_in ( p1956 ) , .Test_en_N_out ( SYNOPSYS_UNCONNECTED_4644 ) , .pReset_S_in ( SYNOPSYS_UNCONNECTED_4645 ) , .pReset_E_in ( SYNOPSYS_UNCONNECTED_4646 ) , .pReset_W_in ( pResetWires[291] ) , .pReset_N_out ( pResetWires[293] ) , .pReset_W_out ( SYNOPSYS_UNCONNECTED_4647 ) , - .pReset_E_out ( pResetWires[294] ) , .Reset_S_in ( p3407 ) , + .pReset_E_out ( pResetWires[294] ) , .Reset_S_in ( p1956 ) , .Reset_N_out ( SYNOPSYS_UNCONNECTED_4648 ) , .prog_clk_0_N_in ( prog_clk_0_wires[346] ) , .prog_clk_1_N_in ( SYNOPSYS_UNCONNECTED_4649 ) , .prog_clk_1_S_in ( prog_clk_2_wires[87] ) , .prog_clk_1_E_out ( prog_clk_1_wires[183] ) , - .prog_clk_1_W_out ( prog_clk_1_wires[184] ) , .prog_clk_2_N_in ( p3509 ) , - .prog_clk_2_E_in ( p830 ) , .prog_clk_2_S_in ( p713 ) , - .prog_clk_2_W_in ( p195 ) , + .prog_clk_1_W_out ( prog_clk_1_wires[184] ) , .prog_clk_2_N_in ( p3157 ) , + .prog_clk_2_E_in ( p577 ) , .prog_clk_2_S_in ( p432 ) , + .prog_clk_2_W_in ( p50 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_4650 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_4651 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_4652 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_4653 ) , - .prog_clk_3_W_in ( p2708 ) , .prog_clk_3_E_in ( p281 ) , - .prog_clk_3_S_in ( p1331 ) , .prog_clk_3_N_in ( p3508 ) , + .prog_clk_3_W_in ( p3474 ) , .prog_clk_3_E_in ( p821 ) , + .prog_clk_3_S_in ( p1253 ) , .prog_clk_3_N_in ( p3047 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_4654 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4655 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_4656 ) , .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_4657 ) , .clk_1_N_in ( SYNOPSYS_UNCONNECTED_4658 ) , .clk_1_S_in ( clk_2_wires[87] ) , .clk_1_E_out ( clk_1_wires[183] ) , - .clk_1_W_out ( clk_1_wires[184] ) , .clk_2_N_in ( p1960 ) , - .clk_2_E_in ( p1031 ) , .clk_2_S_in ( p3387 ) , .clk_2_W_in ( p2566 ) , + .clk_1_W_out ( clk_1_wires[184] ) , .clk_2_N_in ( p3412 ) , + .clk_2_E_in ( p712 ) , .clk_2_S_in ( p473 ) , .clk_2_W_in ( p3442 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_4659 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_4660 ) , .clk_2_N_out ( SYNOPSYS_UNCONNECTED_4661 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_4662 ) , .clk_3_W_in ( p2708 ) , - .clk_3_E_in ( p1129 ) , .clk_3_S_in ( p318 ) , .clk_3_N_in ( p1713 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_4662 ) , .clk_3_W_in ( p3347 ) , + .clk_3_E_in ( p160 ) , .clk_3_S_in ( p1691 ) , .clk_3_N_in ( p3371 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_4663 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4664 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_4665 ) , @@ -117341,20 +121880,20 @@ sb_1__1_ sb_9__6_ ( .chanx_right_out ( sb_1__1__93_chanx_right_out ) , .chany_bottom_out ( sb_1__1__93_chany_bottom_out ) , .chanx_left_out ( sb_1__1__93_chanx_left_out ) , - .ccff_tail ( sb_1__1__93_ccff_tail ) , .Test_en_S_in ( p2965 ) , + .ccff_tail ( sb_1__1__93_ccff_tail ) , .Test_en_S_in ( p1547 ) , .Test_en_N_out ( SYNOPSYS_UNCONNECTED_4668 ) , .pReset_S_in ( SYNOPSYS_UNCONNECTED_4669 ) , .pReset_E_in ( SYNOPSYS_UNCONNECTED_4670 ) , .pReset_W_in ( pResetWires[340] ) , .pReset_N_out ( pResetWires[342] ) , .pReset_W_out ( SYNOPSYS_UNCONNECTED_4671 ) , - .pReset_E_out ( pResetWires[343] ) , .Reset_S_in ( p2965 ) , + .pReset_E_out ( pResetWires[343] ) , .Reset_S_in ( p1547 ) , .Reset_N_out ( SYNOPSYS_UNCONNECTED_4672 ) , - .prog_clk_0_N_in ( prog_clk_0_wires[349] ) , .prog_clk_1_N_in ( p1956 ) , - .prog_clk_1_S_in ( p297 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[349] ) , .prog_clk_1_N_in ( p1877 ) , + .prog_clk_1_S_in ( p1160 ) , .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_4673 ) , .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_4674 ) , - .prog_clk_2_N_in ( p2122 ) , .prog_clk_2_E_in ( p1151 ) , - .prog_clk_2_S_in ( p455 ) , .prog_clk_2_W_in ( p907 ) , + .prog_clk_2_N_in ( p1952 ) , .prog_clk_2_E_in ( p667 ) , + .prog_clk_2_S_in ( p39 ) , .prog_clk_2_W_in ( p743 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_4675 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_4676 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_4677 ) , @@ -117366,10 +121905,10 @@ sb_1__1_ sb_9__6_ ( .prog_clk_3_E_out ( prog_clk_3_wires[48] ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4682 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_4683 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_4684 ) , .clk_1_N_in ( p1956 ) , - .clk_1_S_in ( p75 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_4685 ) , - .clk_1_W_out ( SYNOPSYS_UNCONNECTED_4686 ) , .clk_2_N_in ( p1766 ) , - .clk_2_E_in ( p337 ) , .clk_2_S_in ( p2871 ) , .clk_2_W_in ( p216 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_4684 ) , .clk_1_N_in ( p1877 ) , + .clk_1_S_in ( p454 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_4685 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_4686 ) , .clk_2_N_in ( p1952 ) , + .clk_2_E_in ( p267 ) , .clk_2_S_in ( p724 ) , .clk_2_W_in ( p258 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_4687 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_4688 ) , .clk_2_N_out ( SYNOPSYS_UNCONNECTED_4689 ) , @@ -117425,27 +121964,27 @@ sb_1__1_ sb_9__7_ ( .chanx_right_out ( sb_1__1__94_chanx_right_out ) , .chany_bottom_out ( sb_1__1__94_chany_bottom_out ) , .chanx_left_out ( sb_1__1__94_chanx_left_out ) , - .ccff_tail ( sb_1__1__94_ccff_tail ) , .Test_en_S_in ( p3160 ) , + .ccff_tail ( sb_1__1__94_ccff_tail ) , .Test_en_S_in ( p2344 ) , .Test_en_N_out ( SYNOPSYS_UNCONNECTED_4698 ) , .pReset_S_in ( SYNOPSYS_UNCONNECTED_4699 ) , .pReset_E_in ( SYNOPSYS_UNCONNECTED_4700 ) , .pReset_W_in ( pResetWires[389] ) , .pReset_N_out ( pResetWires[391] ) , .pReset_W_out ( SYNOPSYS_UNCONNECTED_4701 ) , - .pReset_E_out ( pResetWires[392] ) , .Reset_S_in ( p3160 ) , + .pReset_E_out ( pResetWires[392] ) , .Reset_S_in ( p2344 ) , .Reset_N_out ( SYNOPSYS_UNCONNECTED_4702 ) , .prog_clk_0_N_in ( prog_clk_0_wires[352] ) , .prog_clk_1_N_in ( prog_clk_2_wires[102] ) , .prog_clk_1_S_in ( SYNOPSYS_UNCONNECTED_4703 ) , .prog_clk_1_E_out ( prog_clk_1_wires[190] ) , - .prog_clk_1_W_out ( prog_clk_1_wires[191] ) , .prog_clk_2_N_in ( p3454 ) , - .prog_clk_2_E_in ( p724 ) , .prog_clk_2_S_in ( p752 ) , - .prog_clk_2_W_in ( p256 ) , + .prog_clk_1_W_out ( prog_clk_1_wires[191] ) , .prog_clk_2_N_in ( p3573 ) , + .prog_clk_2_E_in ( p565 ) , .prog_clk_2_S_in ( p1336 ) , + .prog_clk_2_W_in ( p339 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_4704 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_4705 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_4706 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_4707 ) , - .prog_clk_3_W_in ( p2475 ) , .prog_clk_3_E_in ( p95 ) , - .prog_clk_3_S_in ( p1046 ) , .prog_clk_3_N_in ( p3440 ) , + .prog_clk_3_W_in ( p2630 ) , .prog_clk_3_E_in ( p1113 ) , + .prog_clk_3_S_in ( p595 ) , .prog_clk_3_N_in ( p3569 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_4708 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4709 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_4710 ) , @@ -117453,12 +121992,12 @@ sb_1__1_ sb_9__7_ ( .clk_1_N_in ( clk_2_wires[102] ) , .clk_1_S_in ( SYNOPSYS_UNCONNECTED_4712 ) , .clk_1_E_out ( clk_1_wires[190] ) , .clk_1_W_out ( clk_1_wires[191] ) , - .clk_2_N_in ( p3308 ) , .clk_2_E_in ( p1063 ) , .clk_2_S_in ( p3125 ) , - .clk_2_W_in ( p2297 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_4713 ) , + .clk_2_N_in ( p2819 ) , .clk_2_E_in ( p219 ) , .clk_2_S_in ( p1031 ) , + .clk_2_W_in ( p2431 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_4713 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_4714 ) , .clk_2_N_out ( SYNOPSYS_UNCONNECTED_4715 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_4716 ) , .clk_3_W_in ( p2475 ) , - .clk_3_E_in ( p1087 ) , .clk_3_S_in ( p1269 ) , .clk_3_N_in ( p3301 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_4716 ) , .clk_3_W_in ( p1326 ) , + .clk_3_E_in ( p1056 ) , .clk_3_S_in ( p2136 ) , .clk_3_N_in ( p2660 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_4717 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4718 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_4719 ) , @@ -117506,16 +122045,16 @@ sb_1__1_ sb_9__8_ ( .chanx_right_out ( sb_1__1__95_chanx_right_out ) , .chany_bottom_out ( sb_1__1__95_chany_bottom_out ) , .chanx_left_out ( sb_1__1__95_chanx_left_out ) , - .ccff_tail ( sb_1__1__95_ccff_tail ) , .Test_en_S_in ( p3082 ) , + .ccff_tail ( sb_1__1__95_ccff_tail ) , .Test_en_S_in ( p2313 ) , .Test_en_N_out ( SYNOPSYS_UNCONNECTED_4722 ) , .pReset_S_in ( SYNOPSYS_UNCONNECTED_4723 ) , .pReset_E_in ( SYNOPSYS_UNCONNECTED_4724 ) , .pReset_W_in ( pResetWires[438] ) , .pReset_N_out ( pResetWires[440] ) , .pReset_W_out ( SYNOPSYS_UNCONNECTED_4725 ) , - .pReset_E_out ( pResetWires[441] ) , .Reset_S_in ( p3082 ) , + .pReset_E_out ( pResetWires[441] ) , .Reset_S_in ( p2313 ) , .Reset_N_out ( SYNOPSYS_UNCONNECTED_4726 ) , - .prog_clk_0_N_in ( prog_clk_0_wires[355] ) , .prog_clk_1_N_in ( p1416 ) , - .prog_clk_1_S_in ( p591 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[355] ) , .prog_clk_1_N_in ( p2011 ) , + .prog_clk_1_S_in ( p96 ) , .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_4727 ) , .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_4728 ) , .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_4729 ) , @@ -117526,13 +122065,13 @@ sb_1__1_ sb_9__8_ ( .prog_clk_2_S_out ( prog_clk_2_wires[101] ) , .prog_clk_2_N_out ( prog_clk_2_wires[99] ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_4733 ) , - .prog_clk_3_W_in ( p1868 ) , .prog_clk_3_E_in ( p897 ) , - .prog_clk_3_S_in ( p575 ) , .prog_clk_3_N_in ( p169 ) , + .prog_clk_3_W_in ( p1433 ) , .prog_clk_3_E_in ( p130 ) , + .prog_clk_3_S_in ( p576 ) , .prog_clk_3_N_in ( p405 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_4734 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4735 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_4736 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_4737 ) , .clk_1_N_in ( p1416 ) , - .clk_1_S_in ( p893 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_4738 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_4737 ) , .clk_1_N_in ( p2011 ) , + .clk_1_S_in ( p875 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_4738 ) , .clk_1_W_out ( SYNOPSYS_UNCONNECTED_4739 ) , .clk_2_N_in ( SYNOPSYS_UNCONNECTED_4740 ) , .clk_2_E_in ( SYNOPSYS_UNCONNECTED_4741 ) , @@ -117540,8 +122079,8 @@ sb_1__1_ sb_9__8_ ( .clk_2_W_in ( clk_2_wires[92] ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_4743 ) , .clk_2_S_out ( clk_2_wires[101] ) , .clk_2_N_out ( clk_2_wires[99] ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_4744 ) , .clk_3_W_in ( p1868 ) , - .clk_3_E_in ( p321 ) , .clk_3_S_in ( p3018 ) , .clk_3_N_in ( p674 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_4744 ) , .clk_3_W_in ( p1433 ) , + .clk_3_E_in ( p967 ) , .clk_3_S_in ( p2104 ) , .clk_3_N_in ( p1680 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_4745 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4746 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_4747 ) , @@ -117589,40 +122128,40 @@ sb_1__1_ sb_9__9_ ( .chanx_right_out ( sb_1__1__96_chanx_right_out ) , .chany_bottom_out ( sb_1__1__96_chany_bottom_out ) , .chanx_left_out ( sb_1__1__96_chanx_left_out ) , - .ccff_tail ( sb_1__1__96_ccff_tail ) , .Test_en_S_in ( p2511 ) , + .ccff_tail ( sb_1__1__96_ccff_tail ) , .Test_en_S_in ( p1318 ) , .Test_en_N_out ( SYNOPSYS_UNCONNECTED_4750 ) , .pReset_S_in ( SYNOPSYS_UNCONNECTED_4751 ) , .pReset_E_in ( SYNOPSYS_UNCONNECTED_4752 ) , .pReset_W_in ( pResetWires[487] ) , .pReset_N_out ( pResetWires[489] ) , .pReset_W_out ( SYNOPSYS_UNCONNECTED_4753 ) , - .pReset_E_out ( pResetWires[490] ) , .Reset_S_in ( p2511 ) , + .pReset_E_out ( pResetWires[490] ) , .Reset_S_in ( p1318 ) , .Reset_N_out ( SYNOPSYS_UNCONNECTED_4754 ) , .prog_clk_0_N_in ( prog_clk_0_wires[358] ) , .prog_clk_1_N_in ( SYNOPSYS_UNCONNECTED_4755 ) , .prog_clk_1_S_in ( prog_clk_2_wires[100] ) , .prog_clk_1_E_out ( prog_clk_1_wires[197] ) , - .prog_clk_1_W_out ( prog_clk_1_wires[198] ) , .prog_clk_2_N_in ( p3470 ) , - .prog_clk_2_E_in ( p545 ) , .prog_clk_2_S_in ( p439 ) , - .prog_clk_2_W_in ( p536 ) , + .prog_clk_1_W_out ( prog_clk_1_wires[198] ) , .prog_clk_2_N_in ( p3248 ) , + .prog_clk_2_E_in ( p536 ) , .prog_clk_2_S_in ( p678 ) , + .prog_clk_2_W_in ( p903 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_4756 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_4757 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_4758 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_4759 ) , - .prog_clk_3_W_in ( p2683 ) , .prog_clk_3_E_in ( p1215 ) , - .prog_clk_3_S_in ( p1450 ) , .prog_clk_3_N_in ( p3462 ) , + .prog_clk_3_W_in ( p2311 ) , .prog_clk_3_E_in ( p544 ) , + .prog_clk_3_S_in ( p1077 ) , .prog_clk_3_N_in ( p3195 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_4760 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4761 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_4762 ) , .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_4763 ) , .clk_1_N_in ( SYNOPSYS_UNCONNECTED_4764 ) , .clk_1_S_in ( clk_2_wires[100] ) , .clk_1_E_out ( clk_1_wires[197] ) , - .clk_1_W_out ( clk_1_wires[198] ) , .clk_2_N_in ( p3370 ) , - .clk_2_E_in ( p927 ) , .clk_2_S_in ( p2318 ) , .clk_2_W_in ( p2537 ) , + .clk_1_W_out ( clk_1_wires[198] ) , .clk_2_N_in ( p2074 ) , + .clk_2_E_in ( p69 ) , .clk_2_S_in ( p159 ) , .clk_2_W_in ( p3438 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_4765 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_4766 ) , .clk_2_N_out ( SYNOPSYS_UNCONNECTED_4767 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_4768 ) , .clk_3_W_in ( p2683 ) , - .clk_3_E_in ( p335 ) , .clk_3_S_in ( p1332 ) , .clk_3_N_in ( p3343 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_4768 ) , .clk_3_W_in ( p3458 ) , + .clk_3_E_in ( p1231 ) , .clk_3_S_in ( p1144 ) , .clk_3_N_in ( p2198 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_4769 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4770 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_4771 ) , @@ -117670,16 +122209,16 @@ sb_1__1_ sb_9__10_ ( .chanx_right_out ( sb_1__1__97_chanx_right_out ) , .chany_bottom_out ( sb_1__1__97_chany_bottom_out ) , .chanx_left_out ( sb_1__1__97_chanx_left_out ) , - .ccff_tail ( sb_1__1__97_ccff_tail ) , .Test_en_S_in ( p2967 ) , + .ccff_tail ( sb_1__1__97_ccff_tail ) , .Test_en_S_in ( p1942 ) , .Test_en_N_out ( SYNOPSYS_UNCONNECTED_4774 ) , .pReset_S_in ( SYNOPSYS_UNCONNECTED_4775 ) , .pReset_E_in ( SYNOPSYS_UNCONNECTED_4776 ) , .pReset_W_in ( pResetWires[536] ) , .pReset_N_out ( pResetWires[538] ) , .pReset_W_out ( SYNOPSYS_UNCONNECTED_4777 ) , - .pReset_E_out ( pResetWires[539] ) , .Reset_S_in ( p2967 ) , + .pReset_E_out ( pResetWires[539] ) , .Reset_S_in ( p1942 ) , .Reset_N_out ( SYNOPSYS_UNCONNECTED_4778 ) , - .prog_clk_0_N_in ( prog_clk_0_wires[361] ) , .prog_clk_1_N_in ( p1328 ) , - .prog_clk_1_S_in ( p1019 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[361] ) , .prog_clk_1_N_in ( p1961 ) , + .prog_clk_1_S_in ( p751 ) , .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_4779 ) , .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_4780 ) , .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_4781 ) , @@ -117690,13 +122229,13 @@ sb_1__1_ sb_9__10_ ( .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_4785 ) , .prog_clk_2_N_out ( prog_clk_2_wires[110] ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_4786 ) , - .prog_clk_3_W_in ( p1556 ) , .prog_clk_3_E_in ( p760 ) , - .prog_clk_3_S_in ( p368 ) , .prog_clk_3_N_in ( p765 ) , + .prog_clk_3_W_in ( p1898 ) , .prog_clk_3_E_in ( p624 ) , + .prog_clk_3_S_in ( p147 ) , .prog_clk_3_N_in ( p367 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_4787 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4788 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_4789 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_4790 ) , .clk_1_N_in ( p1328 ) , - .clk_1_S_in ( p104 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_4791 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_4790 ) , .clk_1_N_in ( p1961 ) , + .clk_1_S_in ( p415 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_4791 ) , .clk_1_W_out ( SYNOPSYS_UNCONNECTED_4792 ) , .clk_2_N_in ( SYNOPSYS_UNCONNECTED_4793 ) , .clk_2_E_in ( SYNOPSYS_UNCONNECTED_4794 ) , @@ -117705,8 +122244,8 @@ sb_1__1_ sb_9__10_ ( .clk_2_W_out ( SYNOPSYS_UNCONNECTED_4796 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_4797 ) , .clk_2_N_out ( clk_2_wires[110] ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_4798 ) , .clk_3_W_in ( p1556 ) , - .clk_3_E_in ( p210 ) , .clk_3_S_in ( p2869 ) , .clk_3_N_in ( p395 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_4798 ) , .clk_3_W_in ( p1898 ) , + .clk_3_E_in ( p393 ) , .clk_3_S_in ( p1709 ) , .clk_3_N_in ( p1721 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_4799 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4800 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_4801 ) , @@ -117754,40 +122293,40 @@ sb_1__1_ sb_9__11_ ( .chanx_right_out ( sb_1__1__98_chanx_right_out ) , .chany_bottom_out ( sb_1__1__98_chany_bottom_out ) , .chanx_left_out ( sb_1__1__98_chanx_left_out ) , - .ccff_tail ( sb_1__1__98_ccff_tail ) , .Test_en_S_in ( p2151 ) , + .ccff_tail ( sb_1__1__98_ccff_tail ) , .Test_en_S_in ( p2558 ) , .Test_en_N_out ( SYNOPSYS_UNCONNECTED_4804 ) , .pReset_S_in ( SYNOPSYS_UNCONNECTED_4805 ) , .pReset_E_in ( SYNOPSYS_UNCONNECTED_4806 ) , .pReset_W_in ( pResetWires[585] ) , .pReset_N_out ( pResetWires[587] ) , .pReset_W_out ( SYNOPSYS_UNCONNECTED_4807 ) , - .pReset_E_out ( pResetWires[588] ) , .Reset_S_in ( p3478 ) , + .pReset_E_out ( pResetWires[588] ) , .Reset_S_in ( p2558 ) , .Reset_N_out ( SYNOPSYS_UNCONNECTED_4808 ) , .prog_clk_0_N_in ( prog_clk_0_wires[364] ) , .prog_clk_1_N_in ( SYNOPSYS_UNCONNECTED_4809 ) , .prog_clk_1_S_in ( prog_clk_2_wires[111] ) , .prog_clk_1_E_out ( prog_clk_1_wires[204] ) , - .prog_clk_1_W_out ( prog_clk_1_wires[205] ) , .prog_clk_2_N_in ( p3469 ) , - .prog_clk_2_E_in ( p929 ) , .prog_clk_2_S_in ( p478 ) , - .prog_clk_2_W_in ( p524 ) , + .prog_clk_1_W_out ( prog_clk_1_wires[205] ) , .prog_clk_2_N_in ( p2515 ) , + .prog_clk_2_E_in ( p474 ) , .prog_clk_2_S_in ( p174 ) , + .prog_clk_2_W_in ( p221 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_4810 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_4811 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_4812 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_4813 ) , - .prog_clk_3_W_in ( p1851 ) , .prog_clk_3_E_in ( p214 ) , - .prog_clk_3_S_in ( p754 ) , .prog_clk_3_N_in ( p3459 ) , + .prog_clk_3_W_in ( p2040 ) , .prog_clk_3_E_in ( p888 ) , + .prog_clk_3_S_in ( p1128 ) , .prog_clk_3_N_in ( p2467 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_4814 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4815 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_4816 ) , .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_4817 ) , .clk_1_N_in ( SYNOPSYS_UNCONNECTED_4818 ) , .clk_1_S_in ( clk_2_wires[111] ) , .clk_1_E_out ( clk_1_wires[204] ) , - .clk_1_W_out ( clk_1_wires[205] ) , .clk_2_N_in ( p3098 ) , - .clk_2_E_in ( p913 ) , .clk_2_S_in ( p3474 ) , .clk_2_W_in ( p1704 ) , + .clk_1_W_out ( clk_1_wires[205] ) , .clk_2_N_in ( p3556 ) , + .clk_2_E_in ( p108 ) , .clk_2_S_in ( p931 ) , .clk_2_W_in ( p2913 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_4819 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_4820 ) , .clk_2_N_out ( SYNOPSYS_UNCONNECTED_4821 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_4822 ) , .clk_3_W_in ( p1851 ) , - .clk_3_E_in ( p873 ) , .clk_3_S_in ( p1386 ) , .clk_3_N_in ( p3004 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_4822 ) , .clk_3_W_in ( p2993 ) , + .clk_3_E_in ( p1247 ) , .clk_3_S_in ( p2383 ) , .clk_3_N_in ( p3551 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_4823 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4824 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_4825 ) , @@ -117835,38 +122374,38 @@ sb_1__1_ sb_10__1_ ( .chanx_right_out ( sb_1__1__99_chanx_right_out ) , .chany_bottom_out ( sb_1__1__99_chany_bottom_out ) , .chanx_left_out ( sb_1__1__99_chanx_left_out ) , - .ccff_tail ( sb_1__1__99_ccff_tail ) , .Test_en_S_in ( p2490 ) , + .ccff_tail ( sb_1__1__99_ccff_tail ) , .Test_en_S_in ( p1357 ) , .Test_en_N_out ( SYNOPSYS_UNCONNECTED_4828 ) , .pReset_S_in ( SYNOPSYS_UNCONNECTED_4829 ) , .pReset_E_in ( SYNOPSYS_UNCONNECTED_4830 ) , .pReset_W_in ( pResetWires[99] ) , .pReset_N_out ( pResetWires[101] ) , .pReset_W_out ( SYNOPSYS_UNCONNECTED_4831 ) , - .pReset_E_out ( pResetWires[102] ) , .Reset_S_in ( p2388 ) , + .pReset_E_out ( pResetWires[102] ) , .Reset_S_in ( p1357 ) , .Reset_N_out ( SYNOPSYS_UNCONNECTED_4832 ) , - .prog_clk_0_N_in ( prog_clk_0_wires[372] ) , .prog_clk_1_N_in ( p1841 ) , - .prog_clk_1_S_in ( p1079 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[372] ) , .prog_clk_1_N_in ( p1838 ) , + .prog_clk_1_S_in ( p1072 ) , .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_4833 ) , .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_4834 ) , - .prog_clk_2_N_in ( p3371 ) , .prog_clk_2_E_in ( p827 ) , - .prog_clk_2_S_in ( p658 ) , .prog_clk_2_W_in ( p1268 ) , + .prog_clk_2_N_in ( p3503 ) , .prog_clk_2_E_in ( p953 ) , + .prog_clk_2_S_in ( p844 ) , .prog_clk_2_W_in ( p232 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_4835 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_4836 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_4837 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_4838 ) , - .prog_clk_3_W_in ( p2934 ) , .prog_clk_3_E_in ( p1152 ) , - .prog_clk_3_S_in ( p1187 ) , .prog_clk_3_N_in ( p3342 ) , + .prog_clk_3_W_in ( p1993 ) , .prog_clk_3_E_in ( p561 ) , + .prog_clk_3_S_in ( p46 ) , .prog_clk_3_N_in ( p3483 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_4839 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4840 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_4841 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_4842 ) , .clk_1_N_in ( p1841 ) , - .clk_1_S_in ( p208 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_4843 ) , - .clk_1_W_out ( SYNOPSYS_UNCONNECTED_4844 ) , .clk_2_N_in ( p2695 ) , - .clk_2_E_in ( p708 ) , .clk_2_S_in ( p2334 ) , .clk_2_W_in ( p2875 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_4842 ) , .clk_1_N_in ( p1838 ) , + .clk_1_S_in ( p419 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_4843 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_4844 ) , .clk_2_N_in ( p3532 ) , + .clk_2_E_in ( p807 ) , .clk_2_S_in ( p773 ) , .clk_2_W_in ( p3293 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_4845 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_4846 ) , .clk_2_N_out ( SYNOPSYS_UNCONNECTED_4847 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_4848 ) , .clk_3_W_in ( p2934 ) , - .clk_3_E_in ( p28 ) , .clk_3_S_in ( p1408 ) , .clk_3_N_in ( p2557 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_4848 ) , .clk_3_W_in ( p3338 ) , + .clk_3_E_in ( p29 ) , .clk_3_S_in ( p1124 ) , .clk_3_N_in ( p3519 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_4849 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4850 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_4851 ) , @@ -117914,16 +122453,16 @@ sb_1__1_ sb_10__2_ ( .chanx_right_out ( sb_1__1__100_chanx_right_out ) , .chany_bottom_out ( sb_1__1__100_chany_bottom_out ) , .chanx_left_out ( sb_1__1__100_chanx_left_out ) , - .ccff_tail ( sb_1__1__100_ccff_tail ) , .Test_en_S_in ( p2505 ) , + .ccff_tail ( sb_1__1__100_ccff_tail ) , .Test_en_S_in ( p2007 ) , .Test_en_N_out ( SYNOPSYS_UNCONNECTED_4854 ) , .pReset_S_in ( SYNOPSYS_UNCONNECTED_4855 ) , .pReset_E_in ( SYNOPSYS_UNCONNECTED_4856 ) , .pReset_W_in ( pResetWires[148] ) , .pReset_N_out ( pResetWires[150] ) , .pReset_W_out ( SYNOPSYS_UNCONNECTED_4857 ) , - .pReset_E_out ( pResetWires[151] ) , .Reset_S_in ( p2505 ) , + .pReset_E_out ( pResetWires[151] ) , .Reset_S_in ( p2007 ) , .Reset_N_out ( SYNOPSYS_UNCONNECTED_4858 ) , - .prog_clk_0_N_in ( prog_clk_0_wires[375] ) , .prog_clk_1_N_in ( p1913 ) , - .prog_clk_1_S_in ( p231 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[375] ) , .prog_clk_1_N_in ( p2290 ) , + .prog_clk_1_S_in ( p557 ) , .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_4859 ) , .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_4860 ) , .prog_clk_2_N_in ( prog_clk_3_wires[87] ) , @@ -117933,14 +122472,14 @@ sb_1__1_ sb_10__2_ ( .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_4864 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_4865 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_4866 ) , - .prog_clk_2_E_out ( prog_clk_2_wires[114] ) , .prog_clk_3_W_in ( p1451 ) , - .prog_clk_3_E_in ( p397 ) , .prog_clk_3_S_in ( p666 ) , - .prog_clk_3_N_in ( p109 ) , + .prog_clk_2_E_out ( prog_clk_2_wires[114] ) , .prog_clk_3_W_in ( p1432 ) , + .prog_clk_3_E_in ( p110 ) , .prog_clk_3_S_in ( p572 ) , + .prog_clk_3_N_in ( p780 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_4867 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4868 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_4869 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_4870 ) , .clk_1_N_in ( p1829 ) , - .clk_1_S_in ( p967 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_4871 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_4870 ) , .clk_1_N_in ( p2290 ) , + .clk_1_S_in ( p946 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_4871 ) , .clk_1_W_out ( SYNOPSYS_UNCONNECTED_4872 ) , .clk_2_N_in ( clk_3_wires[87] ) , .clk_2_E_in ( SYNOPSYS_UNCONNECTED_4873 ) , @@ -117949,8 +122488,8 @@ sb_1__1_ sb_10__2_ ( .clk_2_W_out ( SYNOPSYS_UNCONNECTED_4876 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_4877 ) , .clk_2_N_out ( SYNOPSYS_UNCONNECTED_4878 ) , - .clk_2_E_out ( clk_2_wires[114] ) , .clk_3_W_in ( p1451 ) , - .clk_3_E_in ( p1069 ) , .clk_3_S_in ( p2317 ) , .clk_3_N_in ( p1681 ) , + .clk_2_E_out ( clk_2_wires[114] ) , .clk_3_W_in ( p1432 ) , + .clk_3_E_in ( p1673 ) , .clk_3_S_in ( p1760 ) , .clk_3_N_in ( p2100 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_4879 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4880 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_4881 ) , @@ -117998,20 +122537,20 @@ sb_1__1_ sb_10__3_ ( .chanx_right_out ( sb_1__1__101_chanx_right_out ) , .chany_bottom_out ( sb_1__1__101_chany_bottom_out ) , .chanx_left_out ( sb_1__1__101_chanx_left_out ) , - .ccff_tail ( sb_1__1__101_ccff_tail ) , .Test_en_S_in ( p2931 ) , + .ccff_tail ( sb_1__1__101_ccff_tail ) , .Test_en_S_in ( p1137 ) , .Test_en_N_out ( SYNOPSYS_UNCONNECTED_4884 ) , .pReset_S_in ( SYNOPSYS_UNCONNECTED_4885 ) , .pReset_E_in ( SYNOPSYS_UNCONNECTED_4886 ) , .pReset_W_in ( pResetWires[197] ) , .pReset_N_out ( pResetWires[199] ) , .pReset_W_out ( SYNOPSYS_UNCONNECTED_4887 ) , - .pReset_E_out ( pResetWires[200] ) , .Reset_S_in ( p3249 ) , + .pReset_E_out ( pResetWires[200] ) , .Reset_S_in ( p1137 ) , .Reset_N_out ( SYNOPSYS_UNCONNECTED_4888 ) , - .prog_clk_0_N_in ( prog_clk_0_wires[378] ) , .prog_clk_1_N_in ( p1846 ) , - .prog_clk_1_S_in ( p527 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[378] ) , .prog_clk_1_N_in ( p1580 ) , + .prog_clk_1_S_in ( p1217 ) , .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_4889 ) , .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_4890 ) , - .prog_clk_2_N_in ( p2991 ) , .prog_clk_2_E_in ( p928 ) , - .prog_clk_2_S_in ( p1653 ) , .prog_clk_2_W_in ( p1180 ) , + .prog_clk_2_N_in ( p1949 ) , .prog_clk_2_E_in ( p1034 ) , + .prog_clk_2_S_in ( p1792 ) , .prog_clk_2_W_in ( p368 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_4891 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_4892 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_4893 ) , @@ -118023,10 +122562,10 @@ sb_1__1_ sb_10__3_ ( .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_4898 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4899 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_4900 ) , - .prog_clk_3_S_out ( prog_clk_3_wires[86] ) , .clk_1_N_in ( p1846 ) , - .clk_1_S_in ( p401 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_4901 ) , - .clk_1_W_out ( SYNOPSYS_UNCONNECTED_4902 ) , .clk_2_N_in ( p2694 ) , - .clk_2_E_in ( p513 ) , .clk_2_S_in ( p3215 ) , .clk_2_W_in ( p29 ) , + .prog_clk_3_S_out ( prog_clk_3_wires[86] ) , .clk_1_N_in ( p1580 ) , + .clk_1_S_in ( p463 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_4901 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_4902 ) , .clk_2_N_in ( p1949 ) , + .clk_2_E_in ( p424 ) , .clk_2_S_in ( p1702 ) , .clk_2_W_in ( p839 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_4903 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_4904 ) , .clk_2_N_out ( SYNOPSYS_UNCONNECTED_4905 ) , @@ -118082,16 +122621,16 @@ sb_1__1_ sb_10__4_ ( .chanx_right_out ( sb_1__1__102_chanx_right_out ) , .chany_bottom_out ( sb_1__1__102_chany_bottom_out ) , .chanx_left_out ( sb_1__1__102_chanx_left_out ) , - .ccff_tail ( sb_1__1__102_ccff_tail ) , .Test_en_S_in ( p1810 ) , + .ccff_tail ( sb_1__1__102_ccff_tail ) , .Test_en_S_in ( p1931 ) , .Test_en_N_out ( SYNOPSYS_UNCONNECTED_4914 ) , .pReset_S_in ( SYNOPSYS_UNCONNECTED_4915 ) , .pReset_E_in ( SYNOPSYS_UNCONNECTED_4916 ) , .pReset_W_in ( pResetWires[246] ) , .pReset_N_out ( pResetWires[248] ) , .pReset_W_out ( SYNOPSYS_UNCONNECTED_4917 ) , - .pReset_E_out ( pResetWires[249] ) , .Reset_S_in ( p1810 ) , + .pReset_E_out ( pResetWires[249] ) , .Reset_S_in ( p1931 ) , .Reset_N_out ( SYNOPSYS_UNCONNECTED_4918 ) , - .prog_clk_0_N_in ( prog_clk_0_wires[381] ) , .prog_clk_1_N_in ( p1520 ) , - .prog_clk_1_S_in ( p158 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[381] ) , .prog_clk_1_N_in ( p1362 ) , + .prog_clk_1_S_in ( p1677 ) , .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_4919 ) , .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_4920 ) , .prog_clk_2_N_in ( prog_clk_3_wires[77] ) , @@ -118109,8 +122648,8 @@ sb_1__1_ sb_10__4_ ( .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_4930 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4931 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_4932 ) , - .prog_clk_3_S_out ( prog_clk_3_wires[82] ) , .clk_1_N_in ( p1520 ) , - .clk_1_S_in ( p1655 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_4933 ) , + .prog_clk_3_S_out ( prog_clk_3_wires[82] ) , .clk_1_N_in ( p1362 ) , + .clk_1_S_in ( p759 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_4933 ) , .clk_1_W_out ( SYNOPSYS_UNCONNECTED_4934 ) , .clk_2_N_in ( clk_3_wires[77] ) , .clk_2_E_in ( SYNOPSYS_UNCONNECTED_4935 ) , @@ -118171,20 +122710,20 @@ sb_1__1_ sb_10__5_ ( .chanx_right_out ( sb_1__1__103_chanx_right_out ) , .chany_bottom_out ( sb_1__1__103_chany_bottom_out ) , .chanx_left_out ( sb_1__1__103_chanx_left_out ) , - .ccff_tail ( sb_1__1__103_ccff_tail ) , .Test_en_S_in ( p2634 ) , + .ccff_tail ( sb_1__1__103_ccff_tail ) , .Test_en_S_in ( p1953 ) , .Test_en_N_out ( SYNOPSYS_UNCONNECTED_4948 ) , .pReset_S_in ( SYNOPSYS_UNCONNECTED_4949 ) , .pReset_E_in ( SYNOPSYS_UNCONNECTED_4950 ) , .pReset_W_in ( pResetWires[295] ) , .pReset_N_out ( pResetWires[297] ) , .pReset_W_out ( SYNOPSYS_UNCONNECTED_4951 ) , - .pReset_E_out ( pResetWires[298] ) , .Reset_S_in ( p2634 ) , + .pReset_E_out ( pResetWires[298] ) , .Reset_S_in ( p1953 ) , .Reset_N_out ( SYNOPSYS_UNCONNECTED_4952 ) , - .prog_clk_0_N_in ( prog_clk_0_wires[384] ) , .prog_clk_1_N_in ( p2154 ) , - .prog_clk_1_S_in ( p725 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[384] ) , .prog_clk_1_N_in ( p1590 ) , + .prog_clk_1_S_in ( p1061 ) , .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_4953 ) , .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_4954 ) , - .prog_clk_2_N_in ( p2607 ) , .prog_clk_2_E_in ( p379 ) , - .prog_clk_2_S_in ( p1965 ) , .prog_clk_2_W_in ( p227 ) , + .prog_clk_2_N_in ( p3006 ) , .prog_clk_2_E_in ( p263 ) , + .prog_clk_2_S_in ( p396 ) , .prog_clk_2_W_in ( p615 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_4955 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_4956 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_4957 ) , @@ -118196,10 +122735,10 @@ sb_1__1_ sb_10__5_ ( .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_4962 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4963 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_4964 ) , - .prog_clk_3_S_out ( prog_clk_3_wires[76] ) , .clk_1_N_in ( p2154 ) , - .clk_1_S_in ( p359 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_4965 ) , - .clk_1_W_out ( SYNOPSYS_UNCONNECTED_4966 ) , .clk_2_N_in ( p2607 ) , - .clk_2_E_in ( p635 ) , .clk_2_S_in ( p2554 ) , .clk_2_W_in ( p816 ) , + .prog_clk_3_S_out ( prog_clk_3_wires[76] ) , .clk_1_N_in ( p1590 ) , + .clk_1_S_in ( p111 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_4965 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_4966 ) , .clk_2_N_in ( p2775 ) , + .clk_2_E_in ( p602 ) , .clk_2_S_in ( p1692 ) , .clk_2_W_in ( p315 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_4967 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_4968 ) , .clk_2_N_out ( SYNOPSYS_UNCONNECTED_4969 ) , @@ -118255,20 +122794,20 @@ sb_1__1_ sb_10__6_ ( .chanx_right_out ( sb_1__1__104_chanx_right_out ) , .chany_bottom_out ( sb_1__1__104_chany_bottom_out ) , .chanx_left_out ( sb_1__1__104_chanx_left_out ) , - .ccff_tail ( sb_1__1__104_ccff_tail ) , .Test_en_S_in ( p2775 ) , + .ccff_tail ( sb_1__1__104_ccff_tail ) , .Test_en_S_in ( p2265 ) , .Test_en_N_out ( SYNOPSYS_UNCONNECTED_4978 ) , .pReset_S_in ( SYNOPSYS_UNCONNECTED_4979 ) , .pReset_E_in ( SYNOPSYS_UNCONNECTED_4980 ) , .pReset_W_in ( pResetWires[344] ) , .pReset_N_out ( pResetWires[346] ) , .pReset_W_out ( SYNOPSYS_UNCONNECTED_4981 ) , - .pReset_E_out ( pResetWires[347] ) , .Reset_S_in ( p2775 ) , + .pReset_E_out ( pResetWires[347] ) , .Reset_S_in ( p2265 ) , .Reset_N_out ( SYNOPSYS_UNCONNECTED_4982 ) , - .prog_clk_0_N_in ( prog_clk_0_wires[387] ) , .prog_clk_1_N_in ( p1337 ) , - .prog_clk_1_S_in ( p307 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[387] ) , .prog_clk_1_N_in ( p1400 ) , + .prog_clk_1_S_in ( p870 ) , .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_4983 ) , .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_4984 ) , - .prog_clk_2_N_in ( p2209 ) , .prog_clk_2_E_in ( p1052 ) , - .prog_clk_2_S_in ( p1694 ) , .prog_clk_2_W_in ( p346 ) , + .prog_clk_2_N_in ( p2577 ) , .prog_clk_2_E_in ( p24 ) , + .prog_clk_2_S_in ( p358 ) , .prog_clk_2_W_in ( p495 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_4985 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_4986 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_4987 ) , @@ -118280,10 +122819,10 @@ sb_1__1_ sb_10__6_ ( .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_4992 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4993 ) , .prog_clk_3_N_out ( prog_clk_3_wires[70] ) , - .prog_clk_3_S_out ( prog_clk_3_wires[72] ) , .clk_1_N_in ( p1337 ) , - .clk_1_S_in ( p1025 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_4994 ) , - .clk_1_W_out ( SYNOPSYS_UNCONNECTED_4995 ) , .clk_2_N_in ( p2209 ) , - .clk_2_E_in ( p448 ) , .clk_2_S_in ( p2743 ) , .clk_2_W_in ( p1228 ) , + .prog_clk_3_S_out ( prog_clk_3_wires[72] ) , .clk_1_N_in ( p1400 ) , + .clk_1_S_in ( p141 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_4994 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_4995 ) , .clk_2_N_in ( p1191 ) , + .clk_2_E_in ( p898 ) , .clk_2_S_in ( p2101 ) , .clk_2_W_in ( p68 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_4996 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_4997 ) , .clk_2_N_out ( SYNOPSYS_UNCONNECTED_4998 ) , @@ -118338,20 +122877,20 @@ sb_1__1_ sb_10__7_ ( .chanx_right_out ( sb_1__1__105_chanx_right_out ) , .chany_bottom_out ( sb_1__1__105_chany_bottom_out ) , .chanx_left_out ( sb_1__1__105_chanx_left_out ) , - .ccff_tail ( sb_1__1__105_ccff_tail ) , .Test_en_S_in ( p2637 ) , + .ccff_tail ( sb_1__1__105_ccff_tail ) , .Test_en_S_in ( p1603 ) , .Test_en_N_out ( SYNOPSYS_UNCONNECTED_5006 ) , .pReset_S_in ( SYNOPSYS_UNCONNECTED_5007 ) , .pReset_E_in ( SYNOPSYS_UNCONNECTED_5008 ) , .pReset_W_in ( pResetWires[393] ) , .pReset_N_out ( pResetWires[395] ) , .pReset_W_out ( SYNOPSYS_UNCONNECTED_5009 ) , - .pReset_E_out ( pResetWires[396] ) , .Reset_S_in ( p3275 ) , + .pReset_E_out ( pResetWires[396] ) , .Reset_S_in ( p1603 ) , .Reset_N_out ( SYNOPSYS_UNCONNECTED_5010 ) , - .prog_clk_0_N_in ( prog_clk_0_wires[390] ) , .prog_clk_1_N_in ( p1926 ) , - .prog_clk_1_S_in ( p253 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[390] ) , .prog_clk_1_N_in ( p1566 ) , + .prog_clk_1_S_in ( p372 ) , .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_5011 ) , .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_5012 ) , - .prog_clk_2_N_in ( p2796 ) , .prog_clk_2_E_in ( p837 ) , - .prog_clk_2_S_in ( p360 ) , .prog_clk_2_W_in ( p409 ) , + .prog_clk_2_N_in ( p1573 ) , .prog_clk_2_E_in ( p503 ) , + .prog_clk_2_S_in ( p440 ) , .prog_clk_2_W_in ( p985 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5013 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_5014 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_5015 ) , @@ -118363,10 +122902,10 @@ sb_1__1_ sb_10__7_ ( .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5020 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5021 ) , .prog_clk_3_N_out ( prog_clk_3_wires[74] ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_5022 ) , .clk_1_N_in ( p1926 ) , - .clk_1_S_in ( p1280 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_5023 ) , - .clk_1_W_out ( SYNOPSYS_UNCONNECTED_5024 ) , .clk_2_N_in ( p2776 ) , - .clk_2_E_in ( p350 ) , .clk_2_S_in ( p3212 ) , .clk_2_W_in ( p53 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_5022 ) , .clk_1_N_in ( p1566 ) , + .clk_1_S_in ( p900 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_5023 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_5024 ) , .clk_2_N_in ( p1573 ) , + .clk_2_E_in ( p316 ) , .clk_2_S_in ( p346 ) , .clk_2_W_in ( p362 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5025 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_5026 ) , .clk_2_N_out ( SYNOPSYS_UNCONNECTED_5027 ) , @@ -118422,16 +122961,16 @@ sb_1__1_ sb_10__8_ ( .chanx_right_out ( sb_1__1__106_chanx_right_out ) , .chany_bottom_out ( sb_1__1__106_chany_bottom_out ) , .chanx_left_out ( sb_1__1__106_chanx_left_out ) , - .ccff_tail ( sb_1__1__106_ccff_tail ) , .Test_en_S_in ( p1891 ) , + .ccff_tail ( sb_1__1__106_ccff_tail ) , .Test_en_S_in ( p1910 ) , .Test_en_N_out ( SYNOPSYS_UNCONNECTED_5036 ) , .pReset_S_in ( SYNOPSYS_UNCONNECTED_5037 ) , .pReset_E_in ( SYNOPSYS_UNCONNECTED_5038 ) , .pReset_W_in ( pResetWires[442] ) , .pReset_N_out ( pResetWires[444] ) , .pReset_W_out ( SYNOPSYS_UNCONNECTED_5039 ) , - .pReset_E_out ( pResetWires[445] ) , .Reset_S_in ( p1891 ) , + .pReset_E_out ( pResetWires[445] ) , .Reset_S_in ( p1910 ) , .Reset_N_out ( SYNOPSYS_UNCONNECTED_5040 ) , - .prog_clk_0_N_in ( prog_clk_0_wires[393] ) , .prog_clk_1_N_in ( p2113 ) , - .prog_clk_1_S_in ( p309 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[393] ) , .prog_clk_1_N_in ( p1638 ) , + .prog_clk_1_S_in ( p1661 ) , .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_5041 ) , .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_5042 ) , .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_5043 ) , @@ -118449,8 +122988,8 @@ sb_1__1_ sb_10__8_ ( .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5052 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5053 ) , .prog_clk_3_N_out ( prog_clk_3_wires[80] ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_5054 ) , .clk_1_N_in ( p2113 ) , - .clk_1_S_in ( p1687 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_5055 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_5054 ) , .clk_1_N_in ( p1638 ) , + .clk_1_S_in ( p755 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_5055 ) , .clk_1_W_out ( SYNOPSYS_UNCONNECTED_5056 ) , .clk_2_N_in ( SYNOPSYS_UNCONNECTED_5057 ) , .clk_2_E_in ( SYNOPSYS_UNCONNECTED_5058 ) , @@ -118511,20 +123050,20 @@ sb_1__1_ sb_10__9_ ( .chanx_right_out ( sb_1__1__107_chanx_right_out ) , .chany_bottom_out ( sb_1__1__107_chany_bottom_out ) , .chanx_left_out ( sb_1__1__107_chanx_left_out ) , - .ccff_tail ( sb_1__1__107_ccff_tail ) , .Test_en_S_in ( p2710 ) , + .ccff_tail ( sb_1__1__107_ccff_tail ) , .Test_en_S_in ( p1842 ) , .Test_en_N_out ( SYNOPSYS_UNCONNECTED_5070 ) , .pReset_S_in ( SYNOPSYS_UNCONNECTED_5071 ) , .pReset_E_in ( SYNOPSYS_UNCONNECTED_5072 ) , .pReset_W_in ( pResetWires[491] ) , .pReset_N_out ( pResetWires[493] ) , .pReset_W_out ( SYNOPSYS_UNCONNECTED_5073 ) , - .pReset_E_out ( pResetWires[494] ) , .Reset_S_in ( p2676 ) , + .pReset_E_out ( pResetWires[494] ) , .Reset_S_in ( p1842 ) , .Reset_N_out ( SYNOPSYS_UNCONNECTED_5074 ) , - .prog_clk_0_N_in ( prog_clk_0_wires[396] ) , .prog_clk_1_N_in ( p1470 ) , - .prog_clk_1_S_in ( p167 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[396] ) , .prog_clk_1_N_in ( p1471 ) , + .prog_clk_1_S_in ( p725 ) , .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_5075 ) , .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_5076 ) , - .prog_clk_2_N_in ( p1843 ) , .prog_clk_2_E_in ( p553 ) , - .prog_clk_2_S_in ( p1657 ) , .prog_clk_2_W_in ( p36 ) , + .prog_clk_2_N_in ( p2941 ) , .prog_clk_2_E_in ( p490 ) , + .prog_clk_2_S_in ( p1774 ) , .prog_clk_2_W_in ( p638 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5077 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_5078 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_5079 ) , @@ -118536,10 +123075,10 @@ sb_1__1_ sb_10__9_ ( .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5084 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5085 ) , .prog_clk_3_N_out ( prog_clk_3_wires[84] ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_5086 ) , .clk_1_N_in ( p1470 ) , - .clk_1_S_in ( p756 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_5087 ) , - .clk_1_W_out ( SYNOPSYS_UNCONNECTED_5088 ) , .clk_2_N_in ( p1925 ) , - .clk_2_E_in ( p333 ) , .clk_2_S_in ( p2543 ) , .clk_2_W_in ( p1134 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_5086 ) , .clk_1_N_in ( p1471 ) , + .clk_1_S_in ( p259 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_5087 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_5088 ) , .clk_2_N_in ( p2211 ) , + .clk_2_E_in ( p380 ) , .clk_2_S_in ( p1681 ) , .clk_2_W_in ( p176 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5089 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_5090 ) , .clk_2_N_out ( SYNOPSYS_UNCONNECTED_5091 ) , @@ -118595,16 +123134,16 @@ sb_1__1_ sb_10__10_ ( .chanx_right_out ( sb_1__1__108_chanx_right_out ) , .chany_bottom_out ( sb_1__1__108_chany_bottom_out ) , .chanx_left_out ( sb_1__1__108_chanx_left_out ) , - .ccff_tail ( sb_1__1__108_ccff_tail ) , .Test_en_S_in ( p2821 ) , + .ccff_tail ( sb_1__1__108_ccff_tail ) , .Test_en_S_in ( p1428 ) , .Test_en_N_out ( SYNOPSYS_UNCONNECTED_5100 ) , .pReset_S_in ( SYNOPSYS_UNCONNECTED_5101 ) , .pReset_E_in ( SYNOPSYS_UNCONNECTED_5102 ) , .pReset_W_in ( pResetWires[540] ) , .pReset_N_out ( pResetWires[542] ) , .pReset_W_out ( SYNOPSYS_UNCONNECTED_5103 ) , - .pReset_E_out ( pResetWires[543] ) , .Reset_S_in ( p2821 ) , + .pReset_E_out ( pResetWires[543] ) , .Reset_S_in ( p1428 ) , .Reset_N_out ( SYNOPSYS_UNCONNECTED_5104 ) , - .prog_clk_0_N_in ( prog_clk_0_wires[399] ) , .prog_clk_1_N_in ( p1471 ) , - .prog_clk_1_S_in ( p67 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[399] ) , .prog_clk_1_N_in ( p1885 ) , + .prog_clk_1_S_in ( p71 ) , .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_5105 ) , .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_5106 ) , .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_5107 ) , @@ -118614,14 +123153,14 @@ sb_1__1_ sb_10__10_ ( .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5110 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_5111 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_5112 ) , - .prog_clk_2_E_out ( prog_clk_2_wires[133] ) , .prog_clk_3_W_in ( p1579 ) , - .prog_clk_3_E_in ( p1155 ) , .prog_clk_3_S_in ( p1994 ) , - .prog_clk_3_N_in ( p40 ) , + .prog_clk_2_E_out ( prog_clk_2_wires[133] ) , .prog_clk_3_W_in ( p1287 ) , + .prog_clk_3_E_in ( p1026 ) , .prog_clk_3_S_in ( p418 ) , + .prog_clk_3_N_in ( p38 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5113 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5114 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_5115 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_5116 ) , .clk_1_N_in ( p1471 ) , - .clk_1_S_in ( p1004 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_5117 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_5116 ) , .clk_1_N_in ( p1885 ) , + .clk_1_S_in ( p1216 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_5117 ) , .clk_1_W_out ( SYNOPSYS_UNCONNECTED_5118 ) , .clk_2_N_in ( SYNOPSYS_UNCONNECTED_5119 ) , .clk_2_E_in ( SYNOPSYS_UNCONNECTED_5120 ) , @@ -118630,8 +123169,8 @@ sb_1__1_ sb_10__10_ ( .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5122 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_5123 ) , .clk_2_N_out ( SYNOPSYS_UNCONNECTED_5124 ) , - .clk_2_E_out ( clk_2_wires[133] ) , .clk_3_W_in ( p1579 ) , - .clk_3_E_in ( p1659 ) , .clk_3_S_in ( p2748 ) , .clk_3_N_in ( p730 ) , + .clk_2_E_out ( clk_2_wires[133] ) , .clk_3_W_in ( p1287 ) , + .clk_3_E_in ( p329 ) , .clk_3_S_in ( p701 ) , .clk_3_N_in ( p1749 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5125 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5126 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_5127 ) , @@ -118679,38 +123218,38 @@ sb_1__1_ sb_10__11_ ( .chanx_right_out ( sb_1__1__109_chanx_right_out ) , .chany_bottom_out ( sb_1__1__109_chany_bottom_out ) , .chanx_left_out ( sb_1__1__109_chanx_left_out ) , - .ccff_tail ( sb_1__1__109_ccff_tail ) , .Test_en_S_in ( p1845 ) , + .ccff_tail ( sb_1__1__109_ccff_tail ) , .Test_en_S_in ( p1995 ) , .Test_en_N_out ( SYNOPSYS_UNCONNECTED_5130 ) , .pReset_S_in ( SYNOPSYS_UNCONNECTED_5131 ) , .pReset_E_in ( SYNOPSYS_UNCONNECTED_5132 ) , .pReset_W_in ( pResetWires[589] ) , .pReset_N_out ( pResetWires[591] ) , .pReset_W_out ( SYNOPSYS_UNCONNECTED_5133 ) , - .pReset_E_out ( pResetWires[592] ) , .Reset_S_in ( p3093 ) , + .pReset_E_out ( pResetWires[592] ) , .Reset_S_in ( p1995 ) , .Reset_N_out ( SYNOPSYS_UNCONNECTED_5134 ) , - .prog_clk_0_N_in ( prog_clk_0_wires[402] ) , .prog_clk_1_N_in ( p1915 ) , - .prog_clk_1_S_in ( p641 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[402] ) , .prog_clk_1_N_in ( p2036 ) , + .prog_clk_1_S_in ( p64 ) , .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_5135 ) , .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_5136 ) , - .prog_clk_2_N_in ( p3320 ) , .prog_clk_2_E_in ( p80 ) , - .prog_clk_2_S_in ( p1356 ) , .prog_clk_2_W_in ( p151 ) , + .prog_clk_2_N_in ( p3471 ) , .prog_clk_2_E_in ( p434 ) , + .prog_clk_2_S_in ( p989 ) , .prog_clk_2_W_in ( p928 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5137 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_5138 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_5139 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5140 ) , - .prog_clk_3_W_in ( p2614 ) , .prog_clk_3_E_in ( p1345 ) , - .prog_clk_3_S_in ( p691 ) , .prog_clk_3_N_in ( p3284 ) , + .prog_clk_3_W_in ( p1615 ) , .prog_clk_3_E_in ( p700 ) , + .prog_clk_3_S_in ( p628 ) , .prog_clk_3_N_in ( p3441 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5141 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5142 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_5143 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_5144 ) , .clk_1_N_in ( p1915 ) , - .clk_1_S_in ( p1057 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_5145 ) , - .clk_1_W_out ( SYNOPSYS_UNCONNECTED_5146 ) , .clk_2_N_in ( p3159 ) , - .clk_2_E_in ( p767 ) , .clk_2_S_in ( p3035 ) , .clk_2_W_in ( p2551 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_5144 ) , .clk_1_N_in ( p2036 ) , + .clk_1_S_in ( p1112 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_5145 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_5146 ) , .clk_2_N_in ( p3334 ) , + .clk_2_E_in ( p67 ) , .clk_2_S_in ( p1218 ) , .clk_2_W_in ( p2682 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5147 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_5148 ) , .clk_2_N_out ( SYNOPSYS_UNCONNECTED_5149 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5150 ) , .clk_3_W_in ( p2614 ) , - .clk_3_E_in ( p623 ) , .clk_3_S_in ( p1321 ) , .clk_3_N_in ( p3123 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5150 ) , .clk_3_W_in ( p2779 ) , + .clk_3_E_in ( p1139 ) , .clk_3_S_in ( p1726 ) , .clk_3_N_in ( p3315 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5151 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5152 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_5153 ) , @@ -118758,27 +123297,27 @@ sb_1__1_ sb_11__1_ ( .chanx_right_out ( sb_1__1__110_chanx_right_out ) , .chany_bottom_out ( sb_1__1__110_chany_bottom_out ) , .chanx_left_out ( sb_1__1__110_chanx_left_out ) , - .ccff_tail ( sb_1__1__110_ccff_tail ) , .Test_en_S_in ( p2635 ) , + .ccff_tail ( sb_1__1__110_ccff_tail ) , .Test_en_S_in ( p2570 ) , .Test_en_N_out ( SYNOPSYS_UNCONNECTED_5156 ) , .pReset_S_in ( SYNOPSYS_UNCONNECTED_5157 ) , .pReset_E_in ( SYNOPSYS_UNCONNECTED_5158 ) , .pReset_W_in ( pResetWires[103] ) , .pReset_N_out ( pResetWires[105] ) , .pReset_W_out ( SYNOPSYS_UNCONNECTED_5159 ) , - .pReset_E_out ( pResetWires[106] ) , .Reset_S_in ( p3427 ) , + .pReset_E_out ( pResetWires[106] ) , .Reset_S_in ( p2570 ) , .Reset_N_out ( SYNOPSYS_UNCONNECTED_5160 ) , .prog_clk_0_N_in ( prog_clk_0_wires[410] ) , .prog_clk_1_N_in ( prog_clk_2_wires[116] ) , .prog_clk_1_S_in ( SYNOPSYS_UNCONNECTED_5161 ) , .prog_clk_1_E_out ( prog_clk_1_wires[211] ) , - .prog_clk_1_W_out ( prog_clk_1_wires[212] ) , .prog_clk_2_N_in ( p3401 ) , - .prog_clk_2_E_in ( p64 ) , .prog_clk_2_S_in ( p292 ) , - .prog_clk_2_W_in ( p1149 ) , + .prog_clk_1_W_out ( prog_clk_1_wires[212] ) , .prog_clk_2_N_in ( p3586 ) , + .prog_clk_2_E_in ( p401 ) , .prog_clk_2_S_in ( p1173 ) , + .prog_clk_2_W_in ( p836 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5162 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_5163 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_5164 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5165 ) , - .prog_clk_3_W_in ( p2992 ) , .prog_clk_3_E_in ( p1248 ) , - .prog_clk_3_S_in ( p544 ) , .prog_clk_3_N_in ( p3378 ) , + .prog_clk_3_W_in ( p2598 ) , .prog_clk_3_E_in ( p747 ) , + .prog_clk_3_S_in ( p63 ) , .prog_clk_3_N_in ( p3581 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5166 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5167 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_5168 ) , @@ -118786,12 +123325,12 @@ sb_1__1_ sb_11__1_ ( .clk_1_N_in ( clk_2_wires[116] ) , .clk_1_S_in ( SYNOPSYS_UNCONNECTED_5170 ) , .clk_1_E_out ( clk_1_wires[211] ) , .clk_1_W_out ( clk_1_wires[212] ) , - .clk_2_N_in ( p1544 ) , .clk_2_E_in ( p978 ) , .clk_2_S_in ( p3412 ) , - .clk_2_W_in ( p2889 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5171 ) , + .clk_2_N_in ( p3465 ) , .clk_2_E_in ( p5 ) , .clk_2_S_in ( p1067 ) , + .clk_2_W_in ( p3583 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5171 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_5172 ) , .clk_2_N_out ( SYNOPSYS_UNCONNECTED_5173 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5174 ) , .clk_3_W_in ( p2992 ) , - .clk_3_E_in ( p1071 ) , .clk_3_S_in ( p209 ) , .clk_3_N_in ( p312 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5174 ) , .clk_3_W_in ( p3587 ) , + .clk_3_E_in ( p849 ) , .clk_3_S_in ( p2388 ) , .clk_3_N_in ( p3437 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5175 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5176 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_5177 ) , @@ -118839,16 +123378,16 @@ sb_1__1_ sb_11__2_ ( .chanx_right_out ( sb_1__1__111_chanx_right_out ) , .chany_bottom_out ( sb_1__1__111_chany_bottom_out ) , .chanx_left_out ( sb_1__1__111_chanx_left_out ) , - .ccff_tail ( sb_1__1__111_ccff_tail ) , .Test_en_S_in ( p2112 ) , + .ccff_tail ( sb_1__1__111_ccff_tail ) , .Test_en_S_in ( p2354 ) , .Test_en_N_out ( SYNOPSYS_UNCONNECTED_5180 ) , .pReset_S_in ( SYNOPSYS_UNCONNECTED_5181 ) , .pReset_E_in ( SYNOPSYS_UNCONNECTED_5182 ) , .pReset_W_in ( pResetWires[152] ) , .pReset_N_out ( pResetWires[154] ) , .pReset_W_out ( SYNOPSYS_UNCONNECTED_5183 ) , - .pReset_E_out ( pResetWires[155] ) , .Reset_S_in ( p2112 ) , + .pReset_E_out ( pResetWires[155] ) , .Reset_S_in ( p2354 ) , .Reset_N_out ( SYNOPSYS_UNCONNECTED_5184 ) , - .prog_clk_0_N_in ( prog_clk_0_wires[413] ) , .prog_clk_1_N_in ( p1506 ) , - .prog_clk_1_S_in ( p352 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[413] ) , .prog_clk_1_N_in ( p1978 ) , + .prog_clk_1_S_in ( p940 ) , .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_5185 ) , .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_5186 ) , .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_5187 ) , @@ -118859,13 +123398,13 @@ sb_1__1_ sb_11__2_ ( .prog_clk_2_S_out ( prog_clk_2_wires[115] ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_5191 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5192 ) , - .prog_clk_3_W_in ( p1859 ) , .prog_clk_3_E_in ( p857 ) , - .prog_clk_3_S_in ( p302 ) , .prog_clk_3_N_in ( p408 ) , + .prog_clk_3_W_in ( p1999 ) , .prog_clk_3_E_in ( p70 ) , + .prog_clk_3_S_in ( p673 ) , .prog_clk_3_N_in ( p156 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5193 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5194 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_5195 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_5196 ) , .clk_1_N_in ( p1506 ) , - .clk_1_S_in ( p1017 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_5197 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_5196 ) , .clk_1_N_in ( p1978 ) , + .clk_1_S_in ( p229 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_5197 ) , .clk_1_W_out ( SYNOPSYS_UNCONNECTED_5198 ) , .clk_2_N_in ( SYNOPSYS_UNCONNECTED_5199 ) , .clk_2_E_in ( SYNOPSYS_UNCONNECTED_5200 ) , @@ -118874,8 +123413,8 @@ sb_1__1_ sb_11__2_ ( .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5202 ) , .clk_2_S_out ( clk_2_wires[115] ) , .clk_2_N_out ( SYNOPSYS_UNCONNECTED_5203 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5204 ) , .clk_3_W_in ( p1859 ) , - .clk_3_E_in ( p356 ) , .clk_3_S_in ( p1983 ) , .clk_3_N_in ( p143 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5204 ) , .clk_3_W_in ( p1999 ) , + .clk_3_E_in ( p882 ) , .clk_3_S_in ( p2088 ) , .clk_3_N_in ( p1763 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5205 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5206 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_5207 ) , @@ -118923,27 +123462,27 @@ sb_1__1_ sb_11__3_ ( .chanx_right_out ( sb_1__1__112_chanx_right_out ) , .chany_bottom_out ( sb_1__1__112_chany_bottom_out ) , .chanx_left_out ( sb_1__1__112_chanx_left_out ) , - .ccff_tail ( sb_1__1__112_ccff_tail ) , .Test_en_S_in ( p2410 ) , + .ccff_tail ( sb_1__1__112_ccff_tail ) , .Test_en_S_in ( p1858 ) , .Test_en_N_out ( SYNOPSYS_UNCONNECTED_5210 ) , .pReset_S_in ( SYNOPSYS_UNCONNECTED_5211 ) , .pReset_E_in ( SYNOPSYS_UNCONNECTED_5212 ) , .pReset_W_in ( pResetWires[201] ) , .pReset_N_out ( pResetWires[203] ) , .pReset_W_out ( SYNOPSYS_UNCONNECTED_5213 ) , - .pReset_E_out ( pResetWires[204] ) , .Reset_S_in ( p3199 ) , + .pReset_E_out ( pResetWires[204] ) , .Reset_S_in ( p1858 ) , .Reset_N_out ( SYNOPSYS_UNCONNECTED_5214 ) , .prog_clk_0_N_in ( prog_clk_0_wires[416] ) , .prog_clk_1_N_in ( prog_clk_2_wires[123] ) , .prog_clk_1_S_in ( SYNOPSYS_UNCONNECTED_5215 ) , .prog_clk_1_E_out ( prog_clk_1_wires[218] ) , - .prog_clk_1_W_out ( prog_clk_1_wires[219] ) , .prog_clk_2_N_in ( p3270 ) , - .prog_clk_2_E_in ( p895 ) , .prog_clk_2_S_in ( p1211 ) , - .prog_clk_2_W_in ( p4 ) , + .prog_clk_1_W_out ( prog_clk_1_wires[219] ) , .prog_clk_2_N_in ( p3588 ) , + .prog_clk_2_E_in ( p907 ) , .prog_clk_2_S_in ( p866 ) , + .prog_clk_2_W_in ( p254 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5216 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_5217 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_5218 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5219 ) , - .prog_clk_3_W_in ( p2853 ) , .prog_clk_3_E_in ( p71 ) , - .prog_clk_3_S_in ( p246 ) , .prog_clk_3_N_in ( p3219 ) , + .prog_clk_3_W_in ( p3151 ) , .prog_clk_3_E_in ( p664 ) , + .prog_clk_3_S_in ( p1385 ) , .prog_clk_3_N_in ( p3579 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5220 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5221 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_5222 ) , @@ -118951,12 +123490,12 @@ sb_1__1_ sb_11__3_ ( .clk_1_N_in ( clk_2_wires[123] ) , .clk_1_S_in ( SYNOPSYS_UNCONNECTED_5224 ) , .clk_1_E_out ( clk_1_wires[218] ) , .clk_1_W_out ( clk_1_wires[219] ) , - .clk_2_N_in ( p3202 ) , .clk_2_E_in ( p947 ) , .clk_2_S_in ( p3121 ) , - .clk_2_W_in ( p2719 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5225 ) , + .clk_2_N_in ( p3595 ) , .clk_2_E_in ( p1241 ) , .clk_2_S_in ( p535 ) , + .clk_2_W_in ( p3064 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5225 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_5226 ) , .clk_2_N_out ( SYNOPSYS_UNCONNECTED_5227 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5228 ) , .clk_3_W_in ( p2853 ) , - .clk_3_E_in ( p723 ) , .clk_3_S_in ( p943 ) , .clk_3_N_in ( p3128 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5228 ) , .clk_3_W_in ( p3135 ) , + .clk_3_E_in ( p138 ) , .clk_3_S_in ( p1706 ) , .clk_3_N_in ( p3592 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5229 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5230 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_5231 ) , @@ -119004,16 +123543,16 @@ sb_1__1_ sb_11__4_ ( .chanx_right_out ( sb_1__1__113_chanx_right_out ) , .chany_bottom_out ( sb_1__1__113_chany_bottom_out ) , .chanx_left_out ( sb_1__1__113_chanx_left_out ) , - .ccff_tail ( sb_1__1__113_ccff_tail ) , .Test_en_S_in ( p2424 ) , + .ccff_tail ( sb_1__1__113_ccff_tail ) , .Test_en_S_in ( p2834 ) , .Test_en_N_out ( SYNOPSYS_UNCONNECTED_5234 ) , .pReset_S_in ( SYNOPSYS_UNCONNECTED_5235 ) , .pReset_E_in ( SYNOPSYS_UNCONNECTED_5236 ) , .pReset_W_in ( pResetWires[250] ) , .pReset_N_out ( pResetWires[252] ) , .pReset_W_out ( SYNOPSYS_UNCONNECTED_5237 ) , - .pReset_E_out ( pResetWires[253] ) , .Reset_S_in ( p2424 ) , + .pReset_E_out ( pResetWires[253] ) , .Reset_S_in ( p2834 ) , .Reset_N_out ( SYNOPSYS_UNCONNECTED_5238 ) , - .prog_clk_0_N_in ( prog_clk_0_wires[419] ) , .prog_clk_1_N_in ( p1567 ) , - .prog_clk_1_S_in ( p441 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[419] ) , .prog_clk_1_N_in ( p1459 ) , + .prog_clk_1_S_in ( p1122 ) , .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_5239 ) , .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_5240 ) , .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_5241 ) , @@ -119024,13 +123563,13 @@ sb_1__1_ sb_11__4_ ( .prog_clk_2_S_out ( prog_clk_2_wires[122] ) , .prog_clk_2_N_out ( prog_clk_2_wires[120] ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5245 ) , - .prog_clk_3_W_in ( p2426 ) , .prog_clk_3_E_in ( p764 ) , - .prog_clk_3_S_in ( p514 ) , .prog_clk_3_N_in ( p546 ) , + .prog_clk_3_W_in ( p2559 ) , .prog_clk_3_E_in ( p216 ) , + .prog_clk_3_S_in ( p918 ) , .prog_clk_3_N_in ( p777 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5246 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5247 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_5248 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_5249 ) , .clk_1_N_in ( p1567 ) , - .clk_1_S_in ( p617 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_5250 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_5249 ) , .clk_1_N_in ( p1459 ) , + .clk_1_S_in ( p73 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_5250 ) , .clk_1_W_out ( SYNOPSYS_UNCONNECTED_5251 ) , .clk_2_N_in ( SYNOPSYS_UNCONNECTED_5252 ) , .clk_2_E_in ( SYNOPSYS_UNCONNECTED_5253 ) , @@ -119038,8 +123577,8 @@ sb_1__1_ sb_11__4_ ( .clk_2_W_in ( clk_2_wires[118] ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5255 ) , .clk_2_S_out ( clk_2_wires[122] ) , .clk_2_N_out ( clk_2_wires[120] ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5256 ) , .clk_3_W_in ( p2426 ) , - .clk_3_E_in ( p248 ) , .clk_3_S_in ( p2289 ) , .clk_3_N_in ( p255 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5256 ) , .clk_3_W_in ( p2559 ) , + .clk_3_E_in ( p1048 ) , .clk_3_S_in ( p2669 ) , .clk_3_N_in ( p350 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5257 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5258 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_5259 ) , @@ -119087,40 +123626,40 @@ sb_1__1_ sb_11__5_ ( .chanx_right_out ( sb_1__1__114_chanx_right_out ) , .chany_bottom_out ( sb_1__1__114_chany_bottom_out ) , .chanx_left_out ( sb_1__1__114_chanx_left_out ) , - .ccff_tail ( sb_1__1__114_ccff_tail ) , .Test_en_S_in ( p3321 ) , + .ccff_tail ( sb_1__1__114_ccff_tail ) , .Test_en_S_in ( p2267 ) , .Test_en_N_out ( SYNOPSYS_UNCONNECTED_5262 ) , .pReset_S_in ( SYNOPSYS_UNCONNECTED_5263 ) , .pReset_E_in ( SYNOPSYS_UNCONNECTED_5264 ) , .pReset_W_in ( pResetWires[299] ) , .pReset_N_out ( pResetWires[301] ) , .pReset_W_out ( SYNOPSYS_UNCONNECTED_5265 ) , - .pReset_E_out ( pResetWires[302] ) , .Reset_S_in ( p3428 ) , + .pReset_E_out ( pResetWires[302] ) , .Reset_S_in ( p2267 ) , .Reset_N_out ( SYNOPSYS_UNCONNECTED_5266 ) , .prog_clk_0_N_in ( prog_clk_0_wires[422] ) , .prog_clk_1_N_in ( SYNOPSYS_UNCONNECTED_5267 ) , .prog_clk_1_S_in ( prog_clk_2_wires[121] ) , .prog_clk_1_E_out ( prog_clk_1_wires[225] ) , - .prog_clk_1_W_out ( prog_clk_1_wires[226] ) , .prog_clk_2_N_in ( p2658 ) , - .prog_clk_2_E_in ( p1160 ) , .prog_clk_2_S_in ( p101 ) , - .prog_clk_2_W_in ( p1208 ) , + .prog_clk_1_W_out ( prog_clk_1_wires[226] ) , .prog_clk_2_N_in ( p2781 ) , + .prog_clk_2_E_in ( p690 ) , .prog_clk_2_S_in ( p1276 ) , + .prog_clk_2_W_in ( p754 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5268 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_5269 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_5270 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5271 ) , - .prog_clk_3_W_in ( p2922 ) , .prog_clk_3_E_in ( p780 ) , - .prog_clk_3_S_in ( p1412 ) , .prog_clk_3_N_in ( p2575 ) , + .prog_clk_3_W_in ( p2996 ) , .prog_clk_3_E_in ( p1003 ) , + .prog_clk_3_S_in ( p175 ) , .prog_clk_3_N_in ( p2718 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5272 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5273 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_5274 ) , .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_5275 ) , .clk_1_N_in ( SYNOPSYS_UNCONNECTED_5276 ) , .clk_1_S_in ( clk_2_wires[121] ) , .clk_1_E_out ( clk_1_wires[225] ) , - .clk_1_W_out ( clk_1_wires[226] ) , .clk_2_N_in ( p3313 ) , - .clk_2_E_in ( p166 ) , .clk_2_S_in ( p3417 ) , .clk_2_W_in ( p2866 ) , + .clk_1_W_out ( clk_1_wires[226] ) , .clk_2_N_in ( p3554 ) , + .clk_2_E_in ( p840 ) , .clk_2_S_in ( p1260 ) , .clk_2_W_in ( p3568 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5277 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_5278 ) , .clk_2_N_out ( SYNOPSYS_UNCONNECTED_5279 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5280 ) , .clk_3_W_in ( p2922 ) , - .clk_3_E_in ( p584 ) , .clk_3_S_in ( p941 ) , .clk_3_N_in ( p3294 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5280 ) , .clk_3_W_in ( p3578 ) , + .clk_3_E_in ( p105 ) , .clk_3_S_in ( p2069 ) , .clk_3_N_in ( p3543 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5281 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5282 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_5283 ) , @@ -119168,38 +123707,38 @@ sb_1__1_ sb_11__6_ ( .chanx_right_out ( sb_1__1__115_chanx_right_out ) , .chany_bottom_out ( sb_1__1__115_chany_bottom_out ) , .chanx_left_out ( sb_1__1__115_chanx_left_out ) , - .ccff_tail ( sb_1__1__115_ccff_tail ) , .Test_en_S_in ( p2924 ) , + .ccff_tail ( sb_1__1__115_ccff_tail ) , .Test_en_S_in ( p2051 ) , .Test_en_N_out ( SYNOPSYS_UNCONNECTED_5286 ) , .pReset_S_in ( SYNOPSYS_UNCONNECTED_5287 ) , .pReset_E_in ( SYNOPSYS_UNCONNECTED_5288 ) , .pReset_W_in ( pResetWires[348] ) , .pReset_N_out ( pResetWires[350] ) , .pReset_W_out ( SYNOPSYS_UNCONNECTED_5289 ) , - .pReset_E_out ( pResetWires[351] ) , .Reset_S_in ( p2924 ) , + .pReset_E_out ( pResetWires[351] ) , .Reset_S_in ( p2051 ) , .Reset_N_out ( SYNOPSYS_UNCONNECTED_5290 ) , - .prog_clk_0_N_in ( prog_clk_0_wires[425] ) , .prog_clk_1_N_in ( p1136 ) , - .prog_clk_1_S_in ( p1043 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[425] ) , .prog_clk_1_N_in ( p1621 ) , + .prog_clk_1_S_in ( p411 ) , .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_5291 ) , .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_5292 ) , - .prog_clk_2_N_in ( p3374 ) , .prog_clk_2_E_in ( p1013 ) , - .prog_clk_2_S_in ( p213 ) , .prog_clk_2_W_in ( p938 ) , + .prog_clk_2_N_in ( p3464 ) , .prog_clk_2_E_in ( p249 ) , + .prog_clk_2_S_in ( p1158 ) , .prog_clk_2_W_in ( p1064 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5293 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_5294 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_5295 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5296 ) , - .prog_clk_3_W_in ( p2416 ) , .prog_clk_3_E_in ( p305 ) , - .prog_clk_3_S_in ( p1398 ) , .prog_clk_3_N_in ( p3333 ) , + .prog_clk_3_W_in ( p2521 ) , .prog_clk_3_E_in ( p554 ) , + .prog_clk_3_S_in ( p527 ) , .prog_clk_3_N_in ( p3429 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5297 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5298 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_5299 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_5300 ) , .clk_1_N_in ( p1136 ) , - .clk_1_S_in ( p505 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_5301 ) , - .clk_1_W_out ( SYNOPSYS_UNCONNECTED_5302 ) , .clk_2_N_in ( p3058 ) , - .clk_2_E_in ( p991 ) , .clk_2_S_in ( p2902 ) , .clk_2_W_in ( p2281 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_5300 ) , .clk_1_N_in ( p1621 ) , + .clk_1_S_in ( p1147 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_5301 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_5302 ) , .clk_2_N_in ( p3596 ) , + .clk_2_E_in ( p122 ) , .clk_2_S_in ( p1288 ) , .clk_2_W_in ( p3032 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5303 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_5304 ) , .clk_2_N_out ( SYNOPSYS_UNCONNECTED_5305 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5306 ) , .clk_3_W_in ( p2416 ) , - .clk_3_E_in ( p854 ) , .clk_3_S_in ( p1290 ) , .clk_3_N_in ( p3036 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5306 ) , .clk_3_W_in ( p3140 ) , + .clk_3_E_in ( p1108 ) , .clk_3_S_in ( p1771 ) , .clk_3_N_in ( p3594 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5307 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5308 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_5309 ) , @@ -119247,27 +123786,27 @@ sb_1__1_ sb_11__7_ ( .chanx_right_out ( sb_1__1__116_chanx_right_out ) , .chany_bottom_out ( sb_1__1__116_chany_bottom_out ) , .chanx_left_out ( sb_1__1__116_chanx_left_out ) , - .ccff_tail ( sb_1__1__116_ccff_tail ) , .Test_en_S_in ( p2988 ) , + .ccff_tail ( sb_1__1__116_ccff_tail ) , .Test_en_S_in ( p2617 ) , .Test_en_N_out ( SYNOPSYS_UNCONNECTED_5312 ) , .pReset_S_in ( SYNOPSYS_UNCONNECTED_5313 ) , .pReset_E_in ( SYNOPSYS_UNCONNECTED_5314 ) , .pReset_W_in ( pResetWires[397] ) , .pReset_N_out ( pResetWires[399] ) , .pReset_W_out ( SYNOPSYS_UNCONNECTED_5315 ) , - .pReset_E_out ( pResetWires[400] ) , .Reset_S_in ( p2988 ) , + .pReset_E_out ( pResetWires[400] ) , .Reset_S_in ( p2617 ) , .Reset_N_out ( SYNOPSYS_UNCONNECTED_5316 ) , .prog_clk_0_N_in ( prog_clk_0_wires[428] ) , .prog_clk_1_N_in ( prog_clk_2_wires[130] ) , .prog_clk_1_S_in ( SYNOPSYS_UNCONNECTED_5317 ) , .prog_clk_1_E_out ( prog_clk_1_wires[232] ) , - .prog_clk_1_W_out ( prog_clk_1_wires[233] ) , .prog_clk_2_N_in ( p3436 ) , - .prog_clk_2_E_in ( p1141 ) , .prog_clk_2_S_in ( p535 ) , - .prog_clk_2_W_in ( p1140 ) , + .prog_clk_1_W_out ( prog_clk_1_wires[233] ) , .prog_clk_2_N_in ( p3597 ) , + .prog_clk_2_E_in ( p248 ) , .prog_clk_2_S_in ( p708 ) , + .prog_clk_2_W_in ( p640 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5318 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_5319 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_5320 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5321 ) , - .prog_clk_3_W_in ( p2187 ) , .prog_clk_3_E_in ( p105 ) , - .prog_clk_3_S_in ( p1107 ) , .prog_clk_3_N_in ( p3415 ) , + .prog_clk_3_W_in ( p3321 ) , .prog_clk_3_E_in ( p477 ) , + .prog_clk_3_S_in ( p1071 ) , .prog_clk_3_N_in ( p3591 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5322 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5323 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_5324 ) , @@ -119275,12 +123814,12 @@ sb_1__1_ sb_11__7_ ( .clk_1_N_in ( clk_2_wires[130] ) , .clk_1_S_in ( SYNOPSYS_UNCONNECTED_5326 ) , .clk_1_E_out ( clk_1_wires[232] ) , .clk_1_W_out ( clk_1_wires[233] ) , - .clk_2_N_in ( p2164 ) , .clk_2_E_in ( p683 ) , .clk_2_S_in ( p2888 ) , - .clk_2_W_in ( p2016 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5327 ) , + .clk_2_N_in ( p1502 ) , .clk_2_E_in ( p312 ) , .clk_2_S_in ( p977 ) , + .clk_2_W_in ( p3304 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5327 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_5328 ) , .clk_2_N_out ( SYNOPSYS_UNCONNECTED_5329 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5330 ) , .clk_3_W_in ( p2187 ) , - .clk_3_E_in ( p659 ) , .clk_3_S_in ( p1377 ) , .clk_3_N_in ( p1970 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5330 ) , .clk_3_W_in ( p2759 ) , + .clk_3_E_in ( p975 ) , .clk_3_S_in ( p2411 ) , .clk_3_N_in ( p517 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5331 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5332 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_5333 ) , @@ -119328,16 +123867,16 @@ sb_1__1_ sb_11__8_ ( .chanx_right_out ( sb_1__1__117_chanx_right_out ) , .chany_bottom_out ( sb_1__1__117_chany_bottom_out ) , .chanx_left_out ( sb_1__1__117_chanx_left_out ) , - .ccff_tail ( sb_1__1__117_ccff_tail ) , .Test_en_S_in ( p2394 ) , + .ccff_tail ( sb_1__1__117_ccff_tail ) , .Test_en_S_in ( p1304 ) , .Test_en_N_out ( SYNOPSYS_UNCONNECTED_5336 ) , .pReset_S_in ( SYNOPSYS_UNCONNECTED_5337 ) , .pReset_E_in ( SYNOPSYS_UNCONNECTED_5338 ) , .pReset_W_in ( pResetWires[446] ) , .pReset_N_out ( pResetWires[448] ) , .pReset_W_out ( SYNOPSYS_UNCONNECTED_5339 ) , - .pReset_E_out ( pResetWires[449] ) , .Reset_S_in ( p2394 ) , + .pReset_E_out ( pResetWires[449] ) , .Reset_S_in ( p1304 ) , .Reset_N_out ( SYNOPSYS_UNCONNECTED_5340 ) , - .prog_clk_0_N_in ( prog_clk_0_wires[431] ) , .prog_clk_1_N_in ( p1795 ) , - .prog_clk_1_S_in ( p547 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[431] ) , .prog_clk_1_N_in ( p1945 ) , + .prog_clk_1_S_in ( p982 ) , .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_5341 ) , .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_5342 ) , .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_5343 ) , @@ -119348,13 +123887,13 @@ sb_1__1_ sb_11__8_ ( .prog_clk_2_S_out ( prog_clk_2_wires[129] ) , .prog_clk_2_N_out ( prog_clk_2_wires[127] ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5347 ) , - .prog_clk_3_W_in ( p2438 ) , .prog_clk_3_E_in ( p191 ) , - .prog_clk_3_S_in ( p823 ) , .prog_clk_3_N_in ( p1658 ) , + .prog_clk_3_W_in ( p2023 ) , .prog_clk_3_E_in ( p846 ) , + .prog_clk_3_S_in ( p723 ) , .prog_clk_3_N_in ( p1724 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5348 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5349 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_5350 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_5351 ) , .clk_1_N_in ( p1795 ) , - .clk_1_S_in ( p447 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_5352 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_5351 ) , .clk_1_N_in ( p1945 ) , + .clk_1_S_in ( p448 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_5352 ) , .clk_1_W_out ( SYNOPSYS_UNCONNECTED_5353 ) , .clk_2_N_in ( SYNOPSYS_UNCONNECTED_5354 ) , .clk_2_E_in ( SYNOPSYS_UNCONNECTED_5355 ) , @@ -119362,8 +123901,8 @@ sb_1__1_ sb_11__8_ ( .clk_2_W_in ( clk_2_wires[125] ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5357 ) , .clk_2_S_out ( clk_2_wires[129] ) , .clk_2_N_out ( clk_2_wires[127] ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5358 ) , .clk_3_W_in ( p2438 ) , - .clk_3_E_in ( p953 ) , .clk_3_S_in ( p2287 ) , .clk_3_N_in ( p1718 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5358 ) , .clk_3_W_in ( p2023 ) , + .clk_3_E_in ( p280 ) , .clk_3_S_in ( p555 ) , .clk_3_N_in ( p1665 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5359 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5360 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_5361 ) , @@ -119411,40 +123950,40 @@ sb_1__1_ sb_11__9_ ( .chanx_right_out ( sb_1__1__118_chanx_right_out ) , .chany_bottom_out ( sb_1__1__118_chany_bottom_out ) , .chanx_left_out ( sb_1__1__118_chanx_left_out ) , - .ccff_tail ( sb_1__1__118_ccff_tail ) , .Test_en_S_in ( p2397 ) , + .ccff_tail ( sb_1__1__118_ccff_tail ) , .Test_en_S_in ( p2037 ) , .Test_en_N_out ( SYNOPSYS_UNCONNECTED_5364 ) , .pReset_S_in ( SYNOPSYS_UNCONNECTED_5365 ) , .pReset_E_in ( SYNOPSYS_UNCONNECTED_5366 ) , .pReset_W_in ( pResetWires[495] ) , .pReset_N_out ( pResetWires[497] ) , .pReset_W_out ( SYNOPSYS_UNCONNECTED_5367 ) , - .pReset_E_out ( pResetWires[498] ) , .Reset_S_in ( p3089 ) , + .pReset_E_out ( pResetWires[498] ) , .Reset_S_in ( p2037 ) , .Reset_N_out ( SYNOPSYS_UNCONNECTED_5368 ) , .prog_clk_0_N_in ( prog_clk_0_wires[434] ) , .prog_clk_1_N_in ( SYNOPSYS_UNCONNECTED_5369 ) , .prog_clk_1_S_in ( prog_clk_2_wires[128] ) , .prog_clk_1_E_out ( prog_clk_1_wires[239] ) , - .prog_clk_1_W_out ( prog_clk_1_wires[240] ) , .prog_clk_2_N_in ( p3481 ) , - .prog_clk_2_E_in ( p1277 ) , .prog_clk_2_S_in ( p667 ) , - .prog_clk_2_W_in ( p82 ) , + .prog_clk_1_W_out ( prog_clk_1_wires[240] ) , .prog_clk_2_N_in ( p3273 ) , + .prog_clk_2_E_in ( p11 ) , .prog_clk_2_S_in ( p1210 ) , + .prog_clk_2_W_in ( p612 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5370 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_5371 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_5372 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5373 ) , - .prog_clk_3_W_in ( p2981 ) , .prog_clk_3_E_in ( p997 ) , - .prog_clk_3_S_in ( p1110 ) , .prog_clk_3_N_in ( p3475 ) , + .prog_clk_3_W_in ( p3349 ) , .prog_clk_3_E_in ( p550 ) , + .prog_clk_3_S_in ( p452 ) , .prog_clk_3_N_in ( p3173 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5374 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5375 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_5376 ) , .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_5377 ) , .clk_1_N_in ( SYNOPSYS_UNCONNECTED_5378 ) , .clk_1_S_in ( clk_2_wires[128] ) , .clk_1_E_out ( clk_1_wires[239] ) , - .clk_1_W_out ( clk_1_wires[240] ) , .clk_2_N_in ( p2835 ) , - .clk_2_E_in ( p484 ) , .clk_2_S_in ( p3020 ) , .clk_2_W_in ( p2899 ) , + .clk_1_W_out ( clk_1_wires[240] ) , .clk_2_N_in ( p3561 ) , + .clk_2_E_in ( p245 ) , .clk_2_S_in ( p1325 ) , .clk_2_W_in ( p3548 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5379 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_5380 ) , .clk_2_N_out ( SYNOPSYS_UNCONNECTED_5381 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5382 ) , .clk_3_W_in ( p2981 ) , - .clk_3_E_in ( p122 ) , .clk_3_S_in ( p419 ) , .clk_3_N_in ( p2735 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5382 ) , .clk_3_W_in ( p3562 ) , + .clk_3_E_in ( p1222 ) , .clk_3_S_in ( p1743 ) , .clk_3_N_in ( p3552 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5383 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5384 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_5385 ) , @@ -119492,16 +124031,16 @@ sb_1__1_ sb_11__10_ ( .chanx_right_out ( sb_1__1__119_chanx_right_out ) , .chany_bottom_out ( sb_1__1__119_chany_bottom_out ) , .chanx_left_out ( sb_1__1__119_chanx_left_out ) , - .ccff_tail ( sb_1__1__119_ccff_tail ) , .Test_en_S_in ( p3094 ) , + .ccff_tail ( sb_1__1__119_ccff_tail ) , .Test_en_S_in ( p2266 ) , .Test_en_N_out ( SYNOPSYS_UNCONNECTED_5388 ) , .pReset_S_in ( SYNOPSYS_UNCONNECTED_5389 ) , .pReset_E_in ( SYNOPSYS_UNCONNECTED_5390 ) , .pReset_W_in ( pResetWires[544] ) , .pReset_N_out ( pResetWires[546] ) , .pReset_W_out ( SYNOPSYS_UNCONNECTED_5391 ) , - .pReset_E_out ( pResetWires[547] ) , .Reset_S_in ( p3094 ) , + .pReset_E_out ( pResetWires[547] ) , .Reset_S_in ( p2266 ) , .Reset_N_out ( SYNOPSYS_UNCONNECTED_5392 ) , - .prog_clk_0_N_in ( prog_clk_0_wires[437] ) , .prog_clk_1_N_in ( p1586 ) , - .prog_clk_1_S_in ( p453 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[437] ) , .prog_clk_1_N_in ( p2258 ) , + .prog_clk_1_S_in ( p1204 ) , .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_5393 ) , .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_5394 ) , .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_5395 ) , @@ -119512,13 +124051,13 @@ sb_1__1_ sb_11__10_ ( .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_5399 ) , .prog_clk_2_N_out ( prog_clk_2_wires[134] ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5400 ) , - .prog_clk_3_W_in ( p1555 ) , .prog_clk_3_E_in ( p385 ) , - .prog_clk_3_S_in ( p172 ) , .prog_clk_3_N_in ( p878 ) , + .prog_clk_3_W_in ( p1957 ) , .prog_clk_3_E_in ( p51 ) , + .prog_clk_3_S_in ( p338 ) , .prog_clk_3_N_in ( p587 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5401 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5402 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_5403 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_5404 ) , .clk_1_N_in ( p1586 ) , - .clk_1_S_in ( p20 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_5405 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_5404 ) , .clk_1_N_in ( p2258 ) , + .clk_1_S_in ( p178 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_5405 ) , .clk_1_W_out ( SYNOPSYS_UNCONNECTED_5406 ) , .clk_2_N_in ( SYNOPSYS_UNCONNECTED_5407 ) , .clk_2_E_in ( SYNOPSYS_UNCONNECTED_5408 ) , @@ -119527,8 +124066,8 @@ sb_1__1_ sb_11__10_ ( .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5410 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_5411 ) , .clk_2_N_out ( clk_2_wires[134] ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5412 ) , .clk_3_W_in ( p1555 ) , - .clk_3_E_in ( p550 ) , .clk_3_S_in ( p3030 ) , .clk_3_N_in ( p336 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5412 ) , .clk_3_W_in ( p1957 ) , + .clk_3_E_in ( p514 ) , .clk_3_S_in ( p2120 ) , .clk_3_N_in ( p2070 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5413 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5414 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_5415 ) , @@ -119576,40 +124115,40 @@ sb_1__1_ sb_11__11_ ( .chanx_right_out ( sb_1__1__120_chanx_right_out ) , .chany_bottom_out ( sb_1__1__120_chany_bottom_out ) , .chanx_left_out ( sb_1__1__120_chanx_left_out ) , - .ccff_tail ( sb_1__1__120_ccff_tail ) , .Test_en_S_in ( p2803 ) , + .ccff_tail ( sb_1__1__120_ccff_tail ) , .Test_en_S_in ( p2224 ) , .Test_en_N_out ( SYNOPSYS_UNCONNECTED_5418 ) , .pReset_S_in ( SYNOPSYS_UNCONNECTED_5419 ) , .pReset_E_in ( SYNOPSYS_UNCONNECTED_5420 ) , .pReset_W_in ( pResetWires[593] ) , .pReset_N_out ( pResetWires[595] ) , .pReset_W_out ( SYNOPSYS_UNCONNECTED_5421 ) , - .pReset_E_out ( pResetWires[596] ) , .Reset_S_in ( p3054 ) , + .pReset_E_out ( pResetWires[596] ) , .Reset_S_in ( p2224 ) , .Reset_N_out ( SYNOPSYS_UNCONNECTED_5422 ) , .prog_clk_0_N_in ( prog_clk_0_wires[440] ) , .prog_clk_1_N_in ( SYNOPSYS_UNCONNECTED_5423 ) , .prog_clk_1_S_in ( prog_clk_2_wires[135] ) , .prog_clk_1_E_out ( prog_clk_1_wires[246] ) , - .prog_clk_1_W_out ( prog_clk_1_wires[247] ) , .prog_clk_2_N_in ( p3480 ) , - .prog_clk_2_E_in ( p68 ) , .prog_clk_2_S_in ( p363 ) , - .prog_clk_2_W_in ( p1050 ) , + .prog_clk_1_W_out ( prog_clk_1_wires[247] ) , .prog_clk_2_N_in ( p3164 ) , + .prog_clk_2_E_in ( p357 ) , .prog_clk_2_S_in ( p1036 ) , + .prog_clk_2_W_in ( p302 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5424 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_5425 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_5426 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5427 ) , - .prog_clk_3_W_in ( p2698 ) , .prog_clk_3_E_in ( p783 ) , - .prog_clk_3_S_in ( p1301 ) , .prog_clk_3_N_in ( p3472 ) , + .prog_clk_3_W_in ( p2981 ) , .prog_clk_3_E_in ( p265 ) , + .prog_clk_3_S_in ( p645 ) , .prog_clk_3_N_in ( p3062 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5428 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5429 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_5430 ) , .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_5431 ) , .clk_1_N_in ( SYNOPSYS_UNCONNECTED_5432 ) , .clk_1_S_in ( clk_2_wires[135] ) , .clk_1_E_out ( clk_1_wires[246] ) , - .clk_1_W_out ( clk_1_wires[247] ) , .clk_2_N_in ( p2964 ) , - .clk_2_E_in ( p1159 ) , .clk_2_S_in ( p3019 ) , .clk_2_W_in ( p2558 ) , + .clk_1_W_out ( clk_1_wires[247] ) , .clk_2_N_in ( p3002 ) , + .clk_2_E_in ( p1268 ) , .clk_2_S_in ( p1284 ) , .clk_2_W_in ( p3031 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5433 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_5434 ) , .clk_2_N_out ( SYNOPSYS_UNCONNECTED_5435 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5436 ) , .clk_3_W_in ( p2698 ) , - .clk_3_E_in ( p864 ) , .clk_3_S_in ( p690 ) , .clk_3_N_in ( p2911 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5436 ) , .clk_3_W_in ( p3120 ) , + .clk_3_E_in ( p522 ) , .clk_3_S_in ( p2058 ) , .clk_3_N_in ( p2865 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5437 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5438 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_5439 ) , @@ -119649,7 +124188,7 @@ sb_1__2_ sb_1__12_ ( .chanx_right_out ( sb_1__12__0_chanx_right_out ) , .chany_bottom_out ( sb_1__12__0_chany_bottom_out ) , .chanx_left_out ( sb_1__12__0_chanx_left_out ) , - .ccff_tail ( sb_1__12__0_ccff_tail ) , .SC_IN_BOT ( p1216 ) , + .ccff_tail ( sb_1__12__0_ccff_tail ) , .SC_IN_BOT ( p1338 ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_5442 ) , .pReset_S_in ( SYNOPSYS_UNCONNECTED_5443 ) , .pReset_E_in ( pResetWires[604] ) , @@ -119735,7 +124274,7 @@ sb_1__2_ sb_3__12_ ( .chanx_right_out ( sb_1__12__2_chanx_right_out ) , .chany_bottom_out ( sb_1__12__2_chany_bottom_out ) , .chanx_left_out ( sb_1__12__2_chanx_left_out ) , - .ccff_tail ( sb_1__12__2_ccff_tail ) , .SC_IN_BOT ( p1272 ) , + .ccff_tail ( sb_1__12__2_ccff_tail ) , .SC_IN_BOT ( p1257 ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_5451 ) , .pReset_S_in ( SYNOPSYS_UNCONNECTED_5452 ) , .pReset_E_in ( pResetWires[610] ) , @@ -119821,7 +124360,7 @@ sb_1__2_ sb_5__12_ ( .chanx_right_out ( sb_1__12__4_chanx_right_out ) , .chany_bottom_out ( sb_1__12__4_chany_bottom_out ) , .chanx_left_out ( sb_1__12__4_chanx_left_out ) , - .ccff_tail ( sb_1__12__4_ccff_tail ) , .SC_IN_BOT ( p1462 ) , + .ccff_tail ( sb_1__12__4_ccff_tail ) , .SC_IN_BOT ( p1412 ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_5460 ) , .pReset_S_in ( SYNOPSYS_UNCONNECTED_5461 ) , .pReset_E_in ( pResetWires[616] ) , @@ -119905,7 +124444,7 @@ sb_1__2_ sb_7__12_ ( .chanx_right_out ( sb_1__12__6_chanx_right_out ) , .chany_bottom_out ( sb_1__12__6_chany_bottom_out ) , .chanx_left_out ( sb_1__12__6_chanx_left_out ) , - .ccff_tail ( sb_1__12__6_ccff_tail ) , .SC_IN_BOT ( p1524 ) , + .ccff_tail ( sb_1__12__6_ccff_tail ) , .SC_IN_BOT ( p1384 ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_5468 ) , .pReset_S_in ( SYNOPSYS_UNCONNECTED_5469 ) , .pReset_E_in ( SYNOPSYS_UNCONNECTED_5470 ) , @@ -119991,7 +124530,7 @@ sb_1__2_ sb_9__12_ ( .chanx_right_out ( sb_1__12__8_chanx_right_out ) , .chany_bottom_out ( sb_1__12__8_chany_bottom_out ) , .chanx_left_out ( sb_1__12__8_chanx_left_out ) , - .ccff_tail ( sb_1__12__8_ccff_tail ) , .SC_IN_BOT ( p1396 ) , + .ccff_tail ( sb_1__12__8_ccff_tail ) , .SC_IN_BOT ( p1360 ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_5477 ) , .pReset_S_in ( SYNOPSYS_UNCONNECTED_5478 ) , .pReset_E_in ( SYNOPSYS_UNCONNECTED_5479 ) , @@ -120077,7 +124616,7 @@ sb_1__2_ sb_11__12_ ( .chanx_right_out ( sb_1__12__10_chanx_right_out ) , .chany_bottom_out ( sb_1__12__10_chany_bottom_out ) , .chanx_left_out ( sb_1__12__10_chanx_left_out ) , - .ccff_tail ( sb_1__12__10_ccff_tail ) , .SC_IN_BOT ( p1310 ) , + .ccff_tail ( sb_1__12__10_ccff_tail ) , .SC_IN_BOT ( p1480 ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_5486 ) , .pReset_S_in ( SYNOPSYS_UNCONNECTED_5487 ) , .pReset_E_in ( SYNOPSYS_UNCONNECTED_5488 ) , @@ -120607,7 +125146,7 @@ cbx_1__0_ cbx_1__0_ ( .top_width_0_height_0__pin_17_upper ( grid_io_bottom_11_top_width_0_height_0__pin_17_upper ) , .top_width_0_height_0__pin_17_lower ( grid_io_bottom_11_top_width_0_height_0__pin_17_lower ) , .SC_IN_TOP ( scff_Wires[25] ) , .SC_OUT_BOT ( scff_Wires[26] ) , - .SC_IN_BOT ( p1495 ) , .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_5504 ) , + .SC_IN_BOT ( p1011 ) , .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_5504 ) , .pReset_E_in ( pResetWires[26] ) , .pReset_W_in ( SYNOPSYS_UNCONNECTED_5505 ) , .pReset_W_out ( pResetWires[25] ) , @@ -120661,7 +125200,7 @@ cbx_1__0_ cbx_2__0_ ( .top_width_0_height_0__pin_15_lower ( grid_io_bottom_10_top_width_0_height_0__pin_15_lower ) , .top_width_0_height_0__pin_17_upper ( grid_io_bottom_10_top_width_0_height_0__pin_17_upper ) , .top_width_0_height_0__pin_17_lower ( grid_io_bottom_10_top_width_0_height_0__pin_17_lower ) , - .SC_IN_TOP ( p1229 ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_5508 ) , + .SC_IN_TOP ( p1608 ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_5508 ) , .SC_IN_BOT ( scff_Wires[27] ) , .SC_OUT_TOP ( scff_Wires[28] ) , .pReset_E_in ( pResetWires[29] ) , .pReset_W_in ( SYNOPSYS_UNCONNECTED_5509 ) , @@ -120717,7 +125256,7 @@ cbx_1__0_ cbx_3__0_ ( .top_width_0_height_0__pin_17_upper ( grid_io_bottom_9_top_width_0_height_0__pin_17_upper ) , .top_width_0_height_0__pin_17_lower ( grid_io_bottom_9_top_width_0_height_0__pin_17_lower ) , .SC_IN_TOP ( scff_Wires[78] ) , .SC_OUT_BOT ( scff_Wires[79] ) , - .SC_IN_BOT ( p1391 ) , .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_5513 ) , + .SC_IN_BOT ( p1622 ) , .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_5513 ) , .pReset_E_in ( pResetWires[32] ) , .pReset_W_in ( SYNOPSYS_UNCONNECTED_5514 ) , .pReset_W_out ( pResetWires[31] ) , @@ -120771,7 +125310,7 @@ cbx_1__0_ cbx_4__0_ ( .top_width_0_height_0__pin_15_lower ( grid_io_bottom_8_top_width_0_height_0__pin_15_lower ) , .top_width_0_height_0__pin_17_upper ( grid_io_bottom_8_top_width_0_height_0__pin_17_upper ) , .top_width_0_height_0__pin_17_lower ( grid_io_bottom_8_top_width_0_height_0__pin_17_lower ) , - .SC_IN_TOP ( p1395 ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_5518 ) , + .SC_IN_TOP ( p1309 ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_5518 ) , .SC_IN_BOT ( scff_Wires[80] ) , .SC_OUT_TOP ( scff_Wires[81] ) , .pReset_E_in ( pResetWires[35] ) , .pReset_W_in ( SYNOPSYS_UNCONNECTED_5519 ) , @@ -120827,7 +125366,7 @@ cbx_1__0_ cbx_5__0_ ( .top_width_0_height_0__pin_17_upper ( grid_io_bottom_7_top_width_0_height_0__pin_17_upper ) , .top_width_0_height_0__pin_17_lower ( grid_io_bottom_7_top_width_0_height_0__pin_17_lower ) , .SC_IN_TOP ( scff_Wires[131] ) , .SC_OUT_BOT ( scff_Wires[132] ) , - .SC_IN_BOT ( p1429 ) , .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_5523 ) , + .SC_IN_BOT ( p1555 ) , .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_5523 ) , .pReset_E_in ( pResetWires[38] ) , .pReset_W_in ( SYNOPSYS_UNCONNECTED_5524 ) , .pReset_W_out ( pResetWires[37] ) , @@ -120881,7 +125420,7 @@ cbx_1__0_ cbx_6__0_ ( .top_width_0_height_0__pin_15_lower ( grid_io_bottom_6_top_width_0_height_0__pin_15_lower ) , .top_width_0_height_0__pin_17_upper ( grid_io_bottom_6_top_width_0_height_0__pin_17_upper ) , .top_width_0_height_0__pin_17_lower ( grid_io_bottom_6_top_width_0_height_0__pin_17_lower ) , - .SC_IN_TOP ( p1330 ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_5528 ) , + .SC_IN_TOP ( p1246 ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_5528 ) , .SC_IN_BOT ( scff_Wires[133] ) , .SC_OUT_TOP ( scff_Wires[134] ) , .pReset_E_in ( pResetWires[41] ) , .pReset_W_in ( SYNOPSYS_UNCONNECTED_5529 ) , @@ -120937,7 +125476,7 @@ cbx_1__0_ cbx_7__0_ ( .top_width_0_height_0__pin_17_upper ( grid_io_bottom_5_top_width_0_height_0__pin_17_upper ) , .top_width_0_height_0__pin_17_lower ( grid_io_bottom_5_top_width_0_height_0__pin_17_lower ) , .SC_IN_TOP ( scff_Wires[184] ) , .SC_OUT_BOT ( scff_Wires[185] ) , - .SC_IN_BOT ( p1819 ) , .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_5533 ) , + .SC_IN_BOT ( p1228 ) , .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_5533 ) , .pReset_E_in ( SYNOPSYS_UNCONNECTED_5534 ) , .pReset_W_in ( pResetWires[43] ) , .pReset_W_out ( SYNOPSYS_UNCONNECTED_5535 ) , @@ -120991,7 +125530,7 @@ cbx_1__0_ cbx_8__0_ ( .top_width_0_height_0__pin_15_lower ( grid_io_bottom_4_top_width_0_height_0__pin_15_lower ) , .top_width_0_height_0__pin_17_upper ( grid_io_bottom_4_top_width_0_height_0__pin_17_upper ) , .top_width_0_height_0__pin_17_lower ( grid_io_bottom_4_top_width_0_height_0__pin_17_lower ) , - .SC_IN_TOP ( p1461 ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_5538 ) , + .SC_IN_TOP ( p1448 ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_5538 ) , .SC_IN_BOT ( scff_Wires[186] ) , .SC_OUT_TOP ( scff_Wires[187] ) , .pReset_E_in ( SYNOPSYS_UNCONNECTED_5539 ) , .pReset_W_in ( pResetWires[46] ) , @@ -121047,7 +125586,7 @@ cbx_1__0_ cbx_9__0_ ( .top_width_0_height_0__pin_17_upper ( grid_io_bottom_3_top_width_0_height_0__pin_17_upper ) , .top_width_0_height_0__pin_17_lower ( grid_io_bottom_3_top_width_0_height_0__pin_17_lower ) , .SC_IN_TOP ( scff_Wires[237] ) , .SC_OUT_BOT ( scff_Wires[238] ) , - .SC_IN_BOT ( p1316 ) , .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_5543 ) , + .SC_IN_BOT ( p1837 ) , .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_5543 ) , .pReset_E_in ( SYNOPSYS_UNCONNECTED_5544 ) , .pReset_W_in ( pResetWires[49] ) , .pReset_W_out ( SYNOPSYS_UNCONNECTED_5545 ) , @@ -121101,7 +125640,7 @@ cbx_1__0_ cbx_10__0_ ( .top_width_0_height_0__pin_15_lower ( grid_io_bottom_2_top_width_0_height_0__pin_15_lower ) , .top_width_0_height_0__pin_17_upper ( grid_io_bottom_2_top_width_0_height_0__pin_17_upper ) , .top_width_0_height_0__pin_17_lower ( grid_io_bottom_2_top_width_0_height_0__pin_17_lower ) , - .SC_IN_TOP ( p1181 ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_5548 ) , + .SC_IN_TOP ( p1221 ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_5548 ) , .SC_IN_BOT ( scff_Wires[239] ) , .SC_OUT_TOP ( scff_Wires[240] ) , .pReset_E_in ( SYNOPSYS_UNCONNECTED_5549 ) , .pReset_W_in ( pResetWires[52] ) , @@ -121157,7 +125696,7 @@ cbx_1__0_ cbx_11__0_ ( .top_width_0_height_0__pin_17_upper ( grid_io_bottom_1_top_width_0_height_0__pin_17_upper ) , .top_width_0_height_0__pin_17_lower ( grid_io_bottom_1_top_width_0_height_0__pin_17_lower ) , .SC_IN_TOP ( scff_Wires[290] ) , .SC_OUT_BOT ( scff_Wires[291] ) , - .SC_IN_BOT ( p1800 ) , .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_5553 ) , + .SC_IN_BOT ( p1290 ) , .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_5553 ) , .pReset_E_in ( SYNOPSYS_UNCONNECTED_5554 ) , .pReset_W_in ( pResetWires[55] ) , .pReset_W_out ( SYNOPSYS_UNCONNECTED_5555 ) , @@ -121211,7 +125750,7 @@ cbx_1__0_ cbx_12__0_ ( .top_width_0_height_0__pin_15_lower ( grid_io_bottom_0_top_width_0_height_0__pin_15_lower ) , .top_width_0_height_0__pin_17_upper ( grid_io_bottom_0_top_width_0_height_0__pin_17_upper ) , .top_width_0_height_0__pin_17_lower ( grid_io_bottom_0_top_width_0_height_0__pin_17_lower ) , - .SC_IN_TOP ( p1418 ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_5558 ) , + .SC_IN_TOP ( p1529 ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_5558 ) , .SC_IN_BOT ( scff_Wires[292] ) , .SC_OUT_TOP ( scff_Wires[293] ) , .pReset_E_in ( SYNOPSYS_UNCONNECTED_5559 ) , .pReset_W_in ( pResetWires[58] ) , @@ -121243,7 +125782,7 @@ cbx_1__1_ cbx_1__1_ ( .bottom_grid_pin_14_ ( cbx_1__1__0_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__0_bottom_grid_pin_15_ ) , .ccff_tail ( cbx_1__1__0_ccff_tail ) , .SC_IN_TOP ( scff_Wires[22] ) , - .SC_OUT_BOT ( scff_Wires[23] ) , .SC_IN_BOT ( p1388 ) , + .SC_OUT_BOT ( scff_Wires[23] ) , .SC_IN_BOT ( p1963 ) , .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_5563 ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[0] ) , .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[0] ) , @@ -121258,19 +125797,19 @@ cbx_1__1_ cbx_1__1_ ( .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_5566 ) , .prog_clk_1_E_in ( prog_clk_1_wires[2] ) , .prog_clk_1_N_out ( prog_clk_1_wires[3] ) , - .prog_clk_1_S_out ( prog_clk_1_wires[4] ) , .prog_clk_2_E_in ( p1411 ) , - .prog_clk_2_W_in ( p366 ) , + .prog_clk_1_S_out ( prog_clk_1_wires[4] ) , .prog_clk_2_E_in ( p3241 ) , + .prog_clk_2_W_in ( p1657 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5567 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5568 ) , - .prog_clk_3_W_in ( p2715 ) , .prog_clk_3_E_in ( p1415 ) , + .prog_clk_3_W_in ( p1870 ) , .prog_clk_3_E_in ( p3179 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5569 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5570 ) , .clk_1_W_in ( SYNOPSYS_UNCONNECTED_5571 ) , .clk_1_E_in ( clk_1_wires[2] ) , .clk_1_N_out ( clk_1_wires[3] ) , - .clk_1_S_out ( clk_1_wires[4] ) , .clk_2_E_in ( p1411 ) , - .clk_2_W_in ( p2580 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5572 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5573 ) , .clk_3_W_in ( p2094 ) , - .clk_3_E_in ( p90 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5574 ) , + .clk_1_S_out ( clk_1_wires[4] ) , .clk_2_E_in ( p2243 ) , + .clk_2_W_in ( p2119 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5572 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5573 ) , .clk_3_W_in ( p2246 ) , + .clk_3_E_in ( p2171 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5574 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5575 ) ) ; cbx_1__1_ cbx_1__2_ ( .pReset ( { SYNOPSYS_UNCONNECTED_5576 } ) , @@ -121296,7 +125835,7 @@ cbx_1__1_ cbx_1__2_ ( .bottom_grid_pin_14_ ( cbx_1__1__1_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__1_bottom_grid_pin_15_ ) , .ccff_tail ( cbx_1__1__1_ccff_tail ) , .SC_IN_TOP ( scff_Wires[20] ) , - .SC_OUT_BOT ( scff_Wires[21] ) , .SC_IN_BOT ( p2247 ) , + .SC_OUT_BOT ( scff_Wires[21] ) , .SC_IN_BOT ( p2637 ) , .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_5577 ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[1] ) , .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[1] ) , @@ -121307,21 +125846,21 @@ cbx_1__1_ cbx_1__2_ ( .pReset_W_out ( pResetWires[110] ) , .pReset_S_out ( pResetWires[112] ) , .pReset_E_out ( SYNOPSYS_UNCONNECTED_5579 ) , .prog_clk_0_N_in ( prog_clk_0_wires[11] ) , - .prog_clk_0_W_out ( prog_clk_0_wires[10] ) , .prog_clk_1_W_in ( p2842 ) , - .prog_clk_1_E_in ( p2005 ) , + .prog_clk_0_W_out ( prog_clk_0_wires[10] ) , .prog_clk_1_W_in ( p1561 ) , + .prog_clk_1_E_in ( p2379 ) , .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_5580 ) , .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_5581 ) , - .prog_clk_2_E_in ( p2684 ) , .prog_clk_2_W_in ( p2760 ) , + .prog_clk_2_E_in ( p2625 ) , .prog_clk_2_W_in ( p3382 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5582 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5583 ) , - .prog_clk_3_W_in ( p2685 ) , .prog_clk_3_E_in ( p518 ) , + .prog_clk_3_W_in ( p3405 ) , .prog_clk_3_E_in ( p2471 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5584 ) , - .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5585 ) , .clk_1_W_in ( p1466 ) , - .clk_1_E_in ( p2076 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_5586 ) , - .clk_1_S_out ( SYNOPSYS_UNCONNECTED_5587 ) , .clk_2_E_in ( p2684 ) , - .clk_2_W_in ( p2560 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5588 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5589 ) , .clk_3_W_in ( p1783 ) , - .clk_3_E_in ( p2579 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5590 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5585 ) , .clk_1_W_in ( p2591 ) , + .clk_1_E_in ( p574 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_5586 ) , + .clk_1_S_out ( SYNOPSYS_UNCONNECTED_5587 ) , .clk_2_E_in ( p2965 ) , + .clk_2_W_in ( p3198 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5588 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5589 ) , .clk_3_W_in ( p3259 ) , + .clk_3_E_in ( p2859 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5590 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5591 ) ) ; cbx_1__1_ cbx_1__3_ ( .pReset ( { SYNOPSYS_UNCONNECTED_5592 } ) , @@ -121347,7 +125886,7 @@ cbx_1__1_ cbx_1__3_ ( .bottom_grid_pin_14_ ( cbx_1__1__2_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__2_bottom_grid_pin_15_ ) , .ccff_tail ( cbx_1__1__2_ccff_tail ) , .SC_IN_TOP ( scff_Wires[18] ) , - .SC_OUT_BOT ( scff_Wires[19] ) , .SC_IN_BOT ( p1530 ) , + .SC_OUT_BOT ( scff_Wires[19] ) , .SC_IN_BOT ( p1368 ) , .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_5593 ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[2] ) , .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[2] ) , @@ -121362,19 +125901,19 @@ cbx_1__1_ cbx_1__3_ ( .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_5596 ) , .prog_clk_1_E_in ( prog_clk_1_wires[9] ) , .prog_clk_1_N_out ( prog_clk_1_wires[10] ) , - .prog_clk_1_S_out ( prog_clk_1_wires[11] ) , .prog_clk_2_E_in ( p2808 ) , - .prog_clk_2_W_in ( p1236 ) , + .prog_clk_1_S_out ( prog_clk_1_wires[11] ) , .prog_clk_2_E_in ( p3541 ) , + .prog_clk_2_W_in ( p2141 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5597 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5598 ) , - .prog_clk_3_W_in ( p3165 ) , .prog_clk_3_E_in ( p1369 ) , + .prog_clk_3_W_in ( p2324 ) , .prog_clk_3_E_in ( p3518 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5599 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5600 ) , .clk_1_W_in ( SYNOPSYS_UNCONNECTED_5601 ) , .clk_1_E_in ( clk_1_wires[9] ) , .clk_1_N_out ( clk_1_wires[10] ) , - .clk_1_S_out ( clk_1_wires[11] ) , .clk_2_E_in ( p2808 ) , - .clk_2_W_in ( p3145 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5602 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5603 ) , .clk_3_W_in ( p1785 ) , - .clk_3_E_in ( p2753 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5604 ) , + .clk_1_S_out ( clk_1_wires[11] ) , .clk_2_E_in ( p2216 ) , + .clk_2_W_in ( p2921 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5602 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5603 ) , .clk_3_W_in ( p2982 ) , + .clk_3_E_in ( p2057 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5604 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5605 ) ) ; cbx_1__1_ cbx_1__4_ ( .pReset ( { SYNOPSYS_UNCONNECTED_5606 } ) , @@ -121400,7 +125939,7 @@ cbx_1__1_ cbx_1__4_ ( .bottom_grid_pin_14_ ( cbx_1__1__3_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__3_bottom_grid_pin_15_ ) , .ccff_tail ( cbx_1__1__3_ccff_tail ) , .SC_IN_TOP ( scff_Wires[16] ) , - .SC_OUT_BOT ( scff_Wires[17] ) , .SC_IN_BOT ( p1944 ) , + .SC_OUT_BOT ( scff_Wires[17] ) , .SC_IN_BOT ( p1439 ) , .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_5607 ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[3] ) , .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[3] ) , @@ -121411,21 +125950,21 @@ cbx_1__1_ cbx_1__4_ ( .pReset_W_out ( pResetWires[208] ) , .pReset_S_out ( pResetWires[210] ) , .pReset_E_out ( SYNOPSYS_UNCONNECTED_5609 ) , .prog_clk_0_N_in ( prog_clk_0_wires[21] ) , - .prog_clk_0_W_out ( prog_clk_0_wires[20] ) , .prog_clk_1_W_in ( p2825 ) , - .prog_clk_1_E_in ( p1997 ) , + .prog_clk_0_W_out ( prog_clk_0_wires[20] ) , .prog_clk_1_W_in ( p1597 ) , + .prog_clk_1_E_in ( p190 ) , .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_5610 ) , .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_5611 ) , - .prog_clk_2_E_in ( p2115 ) , .prog_clk_2_W_in ( p2773 ) , + .prog_clk_2_E_in ( p2585 ) , .prog_clk_2_W_in ( p3101 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5612 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5613 ) , - .prog_clk_3_W_in ( p3190 ) , .prog_clk_3_E_in ( p1040 ) , + .prog_clk_3_W_in ( p3051 ) , .prog_clk_3_E_in ( p2416 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5614 ) , - .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5615 ) , .clk_1_W_in ( p1322 ) , - .clk_1_E_in ( p1732 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_5616 ) , - .clk_1_S_out ( SYNOPSYS_UNCONNECTED_5617 ) , .clk_2_E_in ( p2115 ) , - .clk_2_W_in ( p3137 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5618 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5619 ) , .clk_3_W_in ( p2471 ) , - .clk_3_E_in ( p2077 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5620 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5615 ) , .clk_1_W_in ( p1941 ) , + .clk_1_E_in ( p1818 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_5616 ) , + .clk_1_S_out ( SYNOPSYS_UNCONNECTED_5617 ) , .clk_2_E_in ( p3234 ) , + .clk_2_W_in ( p3367 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5618 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5619 ) , .clk_3_W_in ( p3404 ) , + .clk_3_E_in ( p3219 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5620 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5621 ) ) ; cbx_1__1_ cbx_1__5_ ( .pReset ( { SYNOPSYS_UNCONNECTED_5622 } ) , @@ -121451,7 +125990,7 @@ cbx_1__1_ cbx_1__5_ ( .bottom_grid_pin_14_ ( cbx_1__1__4_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__4_bottom_grid_pin_15_ ) , .ccff_tail ( cbx_1__1__4_ccff_tail ) , .SC_IN_TOP ( scff_Wires[14] ) , - .SC_OUT_BOT ( scff_Wires[15] ) , .SC_IN_BOT ( p1912 ) , + .SC_OUT_BOT ( scff_Wires[15] ) , .SC_IN_BOT ( p1234 ) , .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_5623 ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[4] ) , .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[4] ) , @@ -121466,19 +126005,19 @@ cbx_1__1_ cbx_1__5_ ( .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_5626 ) , .prog_clk_1_E_in ( prog_clk_1_wires[16] ) , .prog_clk_1_N_out ( prog_clk_1_wires[17] ) , - .prog_clk_1_S_out ( prog_clk_1_wires[18] ) , .prog_clk_2_E_in ( p2488 ) , - .prog_clk_2_W_in ( p184 ) , + .prog_clk_1_S_out ( prog_clk_1_wires[18] ) , .prog_clk_2_E_in ( p2850 ) , + .prog_clk_2_W_in ( p1799 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5627 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5628 ) , - .prog_clk_3_W_in ( p1938 ) , .prog_clk_3_E_in ( p1311 ) , + .prog_clk_3_W_in ( p1981 ) , .prog_clk_3_E_in ( p2645 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5629 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5630 ) , .clk_1_W_in ( SYNOPSYS_UNCONNECTED_5631 ) , .clk_1_E_in ( clk_1_wires[16] ) , .clk_1_N_out ( clk_1_wires[17] ) , - .clk_1_S_out ( clk_1_wires[18] ) , .clk_2_E_in ( p2488 ) , - .clk_2_W_in ( p2356 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5632 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5633 ) , .clk_3_W_in ( p2461 ) , - .clk_3_E_in ( p2335 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5634 ) , + .clk_1_S_out ( clk_1_wires[18] ) , .clk_2_E_in ( p1815 ) , + .clk_2_W_in ( p3077 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5632 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5633 ) , .clk_3_W_in ( p3155 ) , + .clk_3_E_in ( p1825 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5634 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5635 ) ) ; cbx_1__1_ cbx_1__6_ ( .pReset ( { SYNOPSYS_UNCONNECTED_5636 } ) , @@ -121504,7 +126043,7 @@ cbx_1__1_ cbx_1__6_ ( .bottom_grid_pin_14_ ( cbx_1__1__5_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__5_bottom_grid_pin_15_ ) , .ccff_tail ( cbx_1__1__5_ccff_tail ) , .SC_IN_TOP ( scff_Wires[12] ) , - .SC_OUT_BOT ( scff_Wires[13] ) , .SC_IN_BOT ( p1802 ) , + .SC_OUT_BOT ( scff_Wires[13] ) , .SC_IN_BOT ( p1196 ) , .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_5637 ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[5] ) , .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[5] ) , @@ -121515,21 +126054,21 @@ cbx_1__1_ cbx_1__6_ ( .pReset_W_out ( pResetWires[306] ) , .pReset_S_out ( pResetWires[308] ) , .pReset_E_out ( SYNOPSYS_UNCONNECTED_5639 ) , .prog_clk_0_N_in ( prog_clk_0_wires[31] ) , - .prog_clk_0_W_out ( prog_clk_0_wires[30] ) , .prog_clk_1_W_in ( p2189 ) , - .prog_clk_1_E_in ( p879 ) , + .prog_clk_0_W_out ( prog_clk_0_wires[30] ) , .prog_clk_1_W_in ( p1864 ) , + .prog_clk_1_E_in ( p727 ) , .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_5640 ) , .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_5641 ) , - .prog_clk_2_E_in ( p1568 ) , .prog_clk_2_W_in ( p2090 ) , + .prog_clk_2_E_in ( p3114 ) , .prog_clk_2_W_in ( p2861 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5642 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5643 ) , - .prog_clk_3_W_in ( p2146 ) , .prog_clk_3_E_in ( p414 ) , + .prog_clk_3_W_in ( p2998 ) , .prog_clk_3_E_in ( p3097 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5644 ) , - .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5645 ) , .clk_1_W_in ( p1353 ) , - .clk_1_E_in ( p1690 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_5646 ) , - .clk_1_S_out ( SYNOPSYS_UNCONNECTED_5647 ) , .clk_2_E_in ( p1568 ) , - .clk_2_W_in ( p2277 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5648 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5649 ) , .clk_3_W_in ( p2386 ) , - .clk_3_E_in ( p1255 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5650 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5645 ) , .clk_1_W_in ( p2561 ) , + .clk_1_E_in ( p662 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_5646 ) , + .clk_1_S_out ( SYNOPSYS_UNCONNECTED_5647 ) , .clk_2_E_in ( p3162 ) , + .clk_2_W_in ( p3385 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5648 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5649 ) , .clk_3_W_in ( p3418 ) , + .clk_3_E_in ( p3081 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5650 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5651 ) ) ; cbx_1__1_ cbx_1__7_ ( .pReset ( { SYNOPSYS_UNCONNECTED_5652 } ) , @@ -121555,7 +126094,7 @@ cbx_1__1_ cbx_1__7_ ( .bottom_grid_pin_14_ ( cbx_1__1__6_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__6_bottom_grid_pin_15_ ) , .ccff_tail ( cbx_1__1__6_ccff_tail ) , .SC_IN_TOP ( scff_Wires[10] ) , - .SC_OUT_BOT ( scff_Wires[11] ) , .SC_IN_BOT ( p1313 ) , + .SC_OUT_BOT ( scff_Wires[11] ) , .SC_IN_BOT ( p1475 ) , .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_5653 ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[6] ) , .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[6] ) , @@ -121570,19 +126109,19 @@ cbx_1__1_ cbx_1__7_ ( .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_5656 ) , .prog_clk_1_E_in ( prog_clk_1_wires[23] ) , .prog_clk_1_N_out ( prog_clk_1_wires[24] ) , - .prog_clk_1_S_out ( prog_clk_1_wires[25] ) , .prog_clk_2_E_in ( p2932 ) , - .prog_clk_2_W_in ( p320 ) , + .prog_clk_1_S_out ( prog_clk_1_wires[25] ) , .prog_clk_2_E_in ( p2813 ) , + .prog_clk_2_W_in ( p3383 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5657 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5658 ) , - .prog_clk_3_W_in ( p2392 ) , .prog_clk_3_E_in ( p573 ) , + .prog_clk_3_W_in ( p3409 ) , .prog_clk_3_E_in ( p2724 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5659 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5660 ) , .clk_1_W_in ( SYNOPSYS_UNCONNECTED_5661 ) , .clk_1_E_in ( clk_1_wires[23] ) , .clk_1_N_out ( clk_1_wires[24] ) , - .clk_1_S_out ( clk_1_wires[25] ) , .clk_2_E_in ( p2932 ) , - .clk_2_W_in ( p2357 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5662 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5663 ) , .clk_3_W_in ( p2492 ) , - .clk_3_E_in ( p2915 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5664 ) , + .clk_1_S_out ( clk_1_wires[25] ) , .clk_2_E_in ( p2939 ) , + .clk_2_W_in ( p3316 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5662 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5663 ) , .clk_3_W_in ( p3353 ) , + .clk_3_E_in ( p2928 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5664 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5665 ) ) ; cbx_1__1_ cbx_1__8_ ( .pReset ( { SYNOPSYS_UNCONNECTED_5666 } ) , @@ -121608,7 +126147,7 @@ cbx_1__1_ cbx_1__8_ ( .bottom_grid_pin_14_ ( cbx_1__1__7_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__7_bottom_grid_pin_15_ ) , .ccff_tail ( cbx_1__1__7_ccff_tail ) , .SC_IN_TOP ( scff_Wires[8] ) , - .SC_OUT_BOT ( scff_Wires[9] ) , .SC_IN_BOT ( p1909 ) , + .SC_OUT_BOT ( scff_Wires[9] ) , .SC_IN_BOT ( p1627 ) , .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_5667 ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[7] ) , .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[7] ) , @@ -121619,21 +126158,21 @@ cbx_1__1_ cbx_1__8_ ( .pReset_W_out ( pResetWires[404] ) , .pReset_S_out ( pResetWires[406] ) , .pReset_E_out ( SYNOPSYS_UNCONNECTED_5669 ) , .prog_clk_0_N_in ( prog_clk_0_wires[41] ) , - .prog_clk_0_W_out ( prog_clk_0_wires[40] ) , .prog_clk_1_W_in ( p1419 ) , - .prog_clk_1_E_in ( p421 ) , + .prog_clk_0_W_out ( prog_clk_0_wires[40] ) , .prog_clk_1_W_in ( p1596 ) , + .prog_clk_1_E_in ( p575 ) , .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_5670 ) , .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_5671 ) , - .prog_clk_2_E_in ( p2439 ) , .prog_clk_2_W_in ( p920 ) , + .prog_clk_2_E_in ( p3252 ) , .prog_clk_2_W_in ( p3193 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5672 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5673 ) , - .prog_clk_3_W_in ( p3109 ) , .prog_clk_3_E_in ( p626 ) , + .prog_clk_3_W_in ( p3222 ) , .prog_clk_3_E_in ( p3178 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5674 ) , - .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5675 ) , .clk_1_W_in ( p1289 ) , - .clk_1_E_in ( p1685 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_5676 ) , - .clk_1_S_out ( SYNOPSYS_UNCONNECTED_5677 ) , .clk_2_E_in ( p2439 ) , - .clk_2_W_in ( p3033 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5678 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5679 ) , .clk_3_W_in ( p1469 ) , - .clk_3_E_in ( p2343 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5680 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5675 ) , .clk_1_W_in ( p2020 ) , + .clk_1_E_in ( p1058 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_5676 ) , + .clk_1_S_out ( SYNOPSYS_UNCONNECTED_5677 ) , .clk_2_E_in ( p1132 ) , + .clk_2_W_in ( p3450 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5678 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5679 ) , .clk_3_W_in ( p3470 ) , + .clk_3_E_in ( p1267 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5680 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5681 ) ) ; cbx_1__1_ cbx_1__9_ ( .pReset ( { SYNOPSYS_UNCONNECTED_5682 } ) , @@ -121659,7 +126198,7 @@ cbx_1__1_ cbx_1__9_ ( .bottom_grid_pin_14_ ( cbx_1__1__8_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__8_bottom_grid_pin_15_ ) , .ccff_tail ( cbx_1__1__8_ccff_tail ) , .SC_IN_TOP ( scff_Wires[6] ) , - .SC_OUT_BOT ( scff_Wires[7] ) , .SC_IN_BOT ( p1511 ) , + .SC_OUT_BOT ( scff_Wires[7] ) , .SC_IN_BOT ( p1417 ) , .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_5683 ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[8] ) , .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[8] ) , @@ -121674,19 +126213,19 @@ cbx_1__1_ cbx_1__9_ ( .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_5686 ) , .prog_clk_1_E_in ( prog_clk_1_wires[30] ) , .prog_clk_1_N_out ( prog_clk_1_wires[31] ) , - .prog_clk_1_S_out ( prog_clk_1_wires[32] ) , .prog_clk_2_E_in ( p2118 ) , - .prog_clk_2_W_in ( p567 ) , + .prog_clk_1_S_out ( prog_clk_1_wires[32] ) , .prog_clk_2_E_in ( p2966 ) , + .prog_clk_2_W_in ( p3284 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5687 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5688 ) , - .prog_clk_3_W_in ( p2441 ) , .prog_clk_3_E_in ( p1392 ) , + .prog_clk_3_W_in ( p3337 ) , .prog_clk_3_E_in ( p2930 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5689 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5690 ) , .clk_1_W_in ( SYNOPSYS_UNCONNECTED_5691 ) , .clk_1_E_in ( clk_1_wires[30] ) , .clk_1_N_out ( clk_1_wires[31] ) , - .clk_1_S_out ( clk_1_wires[32] ) , .clk_2_E_in ( p2118 ) , - .clk_2_W_in ( p3140 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5692 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5693 ) , .clk_3_W_in ( p3187 ) , - .clk_3_E_in ( p2069 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5694 ) , + .clk_1_S_out ( clk_1_wires[32] ) , .clk_2_E_in ( p1469 ) , + .clk_2_W_in ( p2914 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5692 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5693 ) , .clk_3_W_in ( p2948 ) , + .clk_3_E_in ( p161 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5694 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5695 ) ) ; cbx_1__1_ cbx_1__10_ ( .pReset ( { SYNOPSYS_UNCONNECTED_5696 } ) , @@ -121712,7 +126251,7 @@ cbx_1__1_ cbx_1__10_ ( .bottom_grid_pin_14_ ( cbx_1__1__9_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__9_bottom_grid_pin_15_ ) , .ccff_tail ( cbx_1__1__9_ccff_tail ) , .SC_IN_TOP ( scff_Wires[4] ) , - .SC_OUT_BOT ( scff_Wires[5] ) , .SC_IN_BOT ( p1803 ) , + .SC_OUT_BOT ( scff_Wires[5] ) , .SC_IN_BOT ( p1518 ) , .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_5697 ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[9] ) , .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[9] ) , @@ -121723,21 +126262,21 @@ cbx_1__1_ cbx_1__10_ ( .pReset_W_out ( pResetWires[502] ) , .pReset_S_out ( pResetWires[504] ) , .pReset_E_out ( SYNOPSYS_UNCONNECTED_5699 ) , .prog_clk_0_N_in ( prog_clk_0_wires[51] ) , - .prog_clk_0_W_out ( prog_clk_0_wires[50] ) , .prog_clk_1_W_in ( p2157 ) , - .prog_clk_1_E_in ( p1085 ) , + .prog_clk_0_W_out ( prog_clk_0_wires[50] ) , .prog_clk_1_W_in ( p1315 ) , + .prog_clk_1_E_in ( p789 ) , .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_5700 ) , .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_5701 ) , - .prog_clk_2_E_in ( p1575 ) , .prog_clk_2_W_in ( p2106 ) , + .prog_clk_2_E_in ( p2798 ) , .prog_clk_2_W_in ( p2729 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5702 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5703 ) , - .prog_clk_3_W_in ( p2933 ) , .prog_clk_3_E_in ( p612 ) , + .prog_clk_3_W_in ( p2797 ) , .prog_clk_3_E_in ( p2739 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5704 ) , - .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5705 ) , .clk_1_W_in ( p1496 ) , - .clk_1_E_in ( p1719 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_5706 ) , - .clk_1_S_out ( SYNOPSYS_UNCONNECTED_5707 ) , .clk_2_E_in ( p1575 ) , - .clk_2_W_in ( p2905 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5708 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5709 ) , .clk_3_W_in ( p2502 ) , - .clk_3_E_in ( p1397 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5710 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5705 ) , .clk_1_W_in ( p1821 ) , + .clk_1_E_in ( p2178 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_5706 ) , + .clk_1_S_out ( SYNOPSYS_UNCONNECTED_5707 ) , .clk_2_E_in ( p2742 ) , + .clk_2_W_in ( p3209 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5708 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5709 ) , .clk_3_W_in ( p3254 ) , + .clk_3_E_in ( p2663 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5710 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5711 ) ) ; cbx_1__1_ cbx_1__11_ ( .pReset ( { SYNOPSYS_UNCONNECTED_5712 } ) , @@ -121763,7 +126302,7 @@ cbx_1__1_ cbx_1__11_ ( .bottom_grid_pin_14_ ( cbx_1__1__10_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__10_bottom_grid_pin_15_ ) , .ccff_tail ( cbx_1__1__10_ccff_tail ) , .SC_IN_TOP ( scff_Wires[2] ) , - .SC_OUT_BOT ( scff_Wires[3] ) , .SC_IN_BOT ( p1552 ) , + .SC_OUT_BOT ( scff_Wires[3] ) , .SC_IN_BOT ( p1646 ) , .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_5713 ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[10] ) , .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[10] ) , @@ -121778,19 +126317,19 @@ cbx_1__1_ cbx_1__11_ ( .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_5716 ) , .prog_clk_1_E_in ( prog_clk_1_wires[37] ) , .prog_clk_1_N_out ( prog_clk_1_wires[38] ) , - .prog_clk_1_S_out ( prog_clk_1_wires[39] ) , .prog_clk_2_E_in ( p2266 ) , - .prog_clk_2_W_in ( p132 ) , + .prog_clk_1_S_out ( prog_clk_1_wires[39] ) , .prog_clk_2_E_in ( p2999 ) , + .prog_clk_2_W_in ( p2683 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5717 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5718 ) , - .prog_clk_3_W_in ( p2478 ) , .prog_clk_3_E_in ( p1209 ) , + .prog_clk_3_W_in ( p2828 ) , .prog_clk_3_E_in ( p2910 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5719 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5720 ) , .clk_1_W_in ( SYNOPSYS_UNCONNECTED_5721 ) , .clk_1_E_in ( clk_1_wires[37] ) , .clk_1_N_out ( clk_1_wires[38] ) , - .clk_1_S_out ( clk_1_wires[39] ) , .clk_2_E_in ( p2266 ) , - .clk_2_W_in ( p2749 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5722 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5723 ) , .clk_3_W_in ( p2838 ) , - .clk_3_E_in ( p2082 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5724 ) , + .clk_1_S_out ( clk_1_wires[39] ) , .clk_2_E_in ( p2200 ) , + .clk_2_W_in ( p2398 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5722 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5723 ) , .clk_3_W_in ( p2634 ) , + .clk_3_E_in ( p2164 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5724 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5725 ) ) ; cbx_1__1_ cbx_2__1_ ( .pReset ( { SYNOPSYS_UNCONNECTED_5726 } ) , @@ -121815,7 +126354,7 @@ cbx_1__1_ cbx_2__1_ ( .bottom_grid_pin_13_ ( cbx_1__1__11_bottom_grid_pin_13_ ) , .bottom_grid_pin_14_ ( cbx_1__1__11_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__11_bottom_grid_pin_15_ ) , - .ccff_tail ( cbx_1__1__11_ccff_tail ) , .SC_IN_TOP ( p1910 ) , + .ccff_tail ( cbx_1__1__11_ccff_tail ) , .SC_IN_TOP ( p2048 ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_5727 ) , .SC_IN_BOT ( scff_Wires[29] ) , .SC_OUT_TOP ( scff_Wires[30] ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[11] ) , @@ -121831,20 +126370,20 @@ cbx_1__1_ cbx_2__1_ ( .prog_clk_1_W_in ( prog_clk_1_wires[1] ) , .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_5731 ) , .prog_clk_1_N_out ( prog_clk_1_wires[5] ) , - .prog_clk_1_S_out ( prog_clk_1_wires[6] ) , .prog_clk_2_E_in ( p2473 ) , - .prog_clk_2_W_in ( p874 ) , + .prog_clk_1_S_out ( prog_clk_1_wires[6] ) , .prog_clk_2_E_in ( p2852 ) , + .prog_clk_2_W_in ( p3210 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5732 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5733 ) , - .prog_clk_3_W_in ( p3242 ) , .prog_clk_3_E_in ( p1767 ) , + .prog_clk_3_W_in ( p3275 ) , .prog_clk_3_E_in ( p2727 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5734 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5735 ) , .clk_1_W_in ( clk_1_wires[1] ) , .clk_1_E_in ( SYNOPSYS_UNCONNECTED_5736 ) , .clk_1_N_out ( clk_1_wires[5] ) , .clk_1_S_out ( clk_1_wires[6] ) , - .clk_2_E_in ( p2473 ) , .clk_2_W_in ( p3232 ) , + .clk_2_E_in ( p1577 ) , .clk_2_W_in ( p2932 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5737 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5738 ) , .clk_3_W_in ( p2403 ) , - .clk_3_E_in ( p2324 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5739 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5738 ) , .clk_3_W_in ( p3007 ) , + .clk_3_E_in ( p874 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5739 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5740 ) ) ; cbx_1__1_ cbx_2__2_ ( .pReset ( { SYNOPSYS_UNCONNECTED_5741 } ) , @@ -121869,7 +126408,7 @@ cbx_1__1_ cbx_2__2_ ( .bottom_grid_pin_13_ ( cbx_1__1__12_bottom_grid_pin_13_ ) , .bottom_grid_pin_14_ ( cbx_1__1__12_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__12_bottom_grid_pin_15_ ) , - .ccff_tail ( cbx_1__1__12_ccff_tail ) , .SC_IN_TOP ( p2224 ) , + .ccff_tail ( cbx_1__1__12_ccff_tail ) , .SC_IN_TOP ( p2339 ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_5742 ) , .SC_IN_BOT ( scff_Wires[31] ) , .SC_OUT_TOP ( scff_Wires[32] ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[12] ) , @@ -121882,23 +126421,23 @@ cbx_1__1_ cbx_2__2_ ( .pReset_E_out ( SYNOPSYS_UNCONNECTED_5744 ) , .prog_clk_0_N_in ( prog_clk_0_wires[69] ) , .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_5745 ) , - .prog_clk_1_W_in ( p1288 ) , .prog_clk_1_E_in ( p1623 ) , + .prog_clk_1_W_in ( p1331 ) , .prog_clk_1_E_in ( p633 ) , .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_5746 ) , .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_5747 ) , .prog_clk_2_E_in ( prog_clk_2_wires[2] ) , .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_5748 ) , .prog_clk_2_W_out ( prog_clk_2_wires[1] ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5749 ) , - .prog_clk_3_W_in ( p1288 ) , .prog_clk_3_E_in ( p2045 ) , + .prog_clk_3_W_in ( p1887 ) , .prog_clk_3_E_in ( p2142 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5750 ) , - .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5751 ) , .clk_1_W_in ( p1605 ) , - .clk_1_E_in ( p148 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_5752 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5751 ) , .clk_1_W_in ( p1887 ) , + .clk_1_E_in ( p1736 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_5752 ) , .clk_1_S_out ( SYNOPSYS_UNCONNECTED_5753 ) , .clk_2_E_in ( clk_2_wires[2] ) , .clk_2_W_in ( SYNOPSYS_UNCONNECTED_5754 ) , .clk_2_W_out ( clk_2_wires[1] ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5755 ) , .clk_3_W_in ( p1288 ) , - .clk_3_E_in ( p1751 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5756 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5755 ) , .clk_3_W_in ( p1887 ) , + .clk_3_E_in ( p1817 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5756 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5757 ) ) ; cbx_1__1_ cbx_2__3_ ( .pReset ( { SYNOPSYS_UNCONNECTED_5758 } ) , @@ -121923,7 +126462,7 @@ cbx_1__1_ cbx_2__3_ ( .bottom_grid_pin_13_ ( cbx_1__1__13_bottom_grid_pin_13_ ) , .bottom_grid_pin_14_ ( cbx_1__1__13_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__13_bottom_grid_pin_15_ ) , - .ccff_tail ( cbx_1__1__13_ccff_tail ) , .SC_IN_TOP ( p1475 ) , + .ccff_tail ( cbx_1__1__13_ccff_tail ) , .SC_IN_TOP ( p1881 ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_5759 ) , .SC_IN_BOT ( scff_Wires[33] ) , .SC_OUT_TOP ( scff_Wires[34] ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[13] ) , @@ -121939,20 +126478,20 @@ cbx_1__1_ cbx_2__3_ ( .prog_clk_1_W_in ( prog_clk_1_wires[8] ) , .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_5763 ) , .prog_clk_1_N_out ( prog_clk_1_wires[12] ) , - .prog_clk_1_S_out ( prog_clk_1_wires[13] ) , .prog_clk_2_E_in ( p2455 ) , - .prog_clk_2_W_in ( p814 ) , + .prog_clk_1_S_out ( prog_clk_1_wires[13] ) , .prog_clk_2_E_in ( p3250 ) , + .prog_clk_2_W_in ( p3365 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5764 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5765 ) , - .prog_clk_3_W_in ( p2841 ) , .prog_clk_3_E_in ( p542 ) , + .prog_clk_3_W_in ( p3400 ) , .prog_clk_3_E_in ( p3201 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5766 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5767 ) , .clk_1_W_in ( clk_1_wires[8] ) , .clk_1_E_in ( SYNOPSYS_UNCONNECTED_5768 ) , .clk_1_N_out ( clk_1_wires[12] ) , .clk_1_S_out ( clk_1_wires[13] ) , - .clk_2_E_in ( p2455 ) , .clk_2_W_in ( p2762 ) , + .clk_2_E_in ( p2352 ) , .clk_2_W_in ( p2936 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5769 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5770 ) , .clk_3_W_in ( p2176 ) , - .clk_3_E_in ( p2344 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5771 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5770 ) , .clk_3_W_in ( p2968 ) , + .clk_3_E_in ( p2185 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5771 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5772 ) ) ; cbx_1__1_ cbx_2__4_ ( .pReset ( { SYNOPSYS_UNCONNECTED_5773 } ) , @@ -121977,7 +126516,7 @@ cbx_1__1_ cbx_2__4_ ( .bottom_grid_pin_13_ ( cbx_1__1__14_bottom_grid_pin_13_ ) , .bottom_grid_pin_14_ ( cbx_1__1__14_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__14_bottom_grid_pin_15_ ) , - .ccff_tail ( cbx_1__1__14_ccff_tail ) , .SC_IN_TOP ( p1452 ) , + .ccff_tail ( cbx_1__1__14_ccff_tail ) , .SC_IN_TOP ( p1551 ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_5774 ) , .SC_IN_BOT ( scff_Wires[35] ) , .SC_OUT_TOP ( scff_Wires[36] ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[14] ) , @@ -121990,23 +126529,23 @@ cbx_1__1_ cbx_2__4_ ( .pReset_E_out ( SYNOPSYS_UNCONNECTED_5776 ) , .prog_clk_0_N_in ( prog_clk_0_wires[75] ) , .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_5777 ) , - .prog_clk_1_W_in ( p1927 ) , .prog_clk_1_E_in ( p649 ) , + .prog_clk_1_W_in ( p1557 ) , .prog_clk_1_E_in ( p854 ) , .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_5778 ) , .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_5779 ) , .prog_clk_2_E_in ( prog_clk_2_wires[7] ) , .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_5780 ) , .prog_clk_2_W_out ( prog_clk_2_wires[6] ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5781 ) , - .prog_clk_3_W_in ( p1927 ) , .prog_clk_3_E_in ( p1104 ) , + .prog_clk_3_W_in ( p1340 ) , .prog_clk_3_E_in ( p741 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5782 ) , - .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5783 ) , .clk_1_W_in ( p1776 ) , - .clk_1_E_in ( p569 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_5784 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5783 ) , .clk_1_W_in ( p1340 ) , + .clk_1_E_in ( p354 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_5784 ) , .clk_1_S_out ( SYNOPSYS_UNCONNECTED_5785 ) , .clk_2_E_in ( clk_2_wires[7] ) , .clk_2_W_in ( SYNOPSYS_UNCONNECTED_5786 ) , .clk_2_W_out ( clk_2_wires[6] ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5787 ) , .clk_3_W_in ( p1927 ) , - .clk_3_E_in ( p13 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5788 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5787 ) , .clk_3_W_in ( p1465 ) , + .clk_3_E_in ( p1047 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5788 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5789 ) ) ; cbx_1__1_ cbx_2__5_ ( .pReset ( { SYNOPSYS_UNCONNECTED_5790 } ) , @@ -122031,7 +126570,7 @@ cbx_1__1_ cbx_2__5_ ( .bottom_grid_pin_13_ ( cbx_1__1__15_bottom_grid_pin_13_ ) , .bottom_grid_pin_14_ ( cbx_1__1__15_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__15_bottom_grid_pin_15_ ) , - .ccff_tail ( cbx_1__1__15_ccff_tail ) , .SC_IN_TOP ( p2210 ) , + .ccff_tail ( cbx_1__1__15_ccff_tail ) , .SC_IN_TOP ( p1323 ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_5791 ) , .SC_IN_BOT ( scff_Wires[37] ) , .SC_OUT_TOP ( scff_Wires[38] ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[15] ) , @@ -122047,20 +126586,20 @@ cbx_1__1_ cbx_2__5_ ( .prog_clk_1_W_in ( prog_clk_1_wires[15] ) , .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_5795 ) , .prog_clk_1_N_out ( prog_clk_1_wires[19] ) , - .prog_clk_1_S_out ( prog_clk_1_wires[20] ) , .prog_clk_2_E_in ( p1443 ) , - .prog_clk_2_W_in ( p470 ) , + .prog_clk_1_S_out ( prog_clk_1_wires[20] ) , .prog_clk_2_E_in ( p3148 ) , + .prog_clk_2_W_in ( p2490 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5796 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5797 ) , - .prog_clk_3_W_in ( p1945 ) , .prog_clk_3_E_in ( p1985 ) , + .prog_clk_3_W_in ( p2554 ) , .prog_clk_3_E_in ( p3085 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5798 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5799 ) , .clk_1_W_in ( clk_1_wires[15] ) , .clk_1_E_in ( SYNOPSYS_UNCONNECTED_5800 ) , .clk_1_N_out ( clk_1_wires[19] ) , .clk_1_S_out ( clk_1_wires[20] ) , - .clk_2_E_in ( p1443 ) , .clk_2_W_in ( p1717 ) , + .clk_2_E_in ( p2227 ) , .clk_2_W_in ( p3527 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5801 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5802 ) , .clk_3_W_in ( p1576 ) , - .clk_3_E_in ( p975 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5803 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5802 ) , .clk_3_W_in ( p3537 ) , + .clk_3_E_in ( p2167 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5803 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5804 ) ) ; cbx_1__1_ cbx_2__6_ ( .pReset ( { SYNOPSYS_UNCONNECTED_5805 } ) , @@ -122085,7 +126624,7 @@ cbx_1__1_ cbx_2__6_ ( .bottom_grid_pin_13_ ( cbx_1__1__16_bottom_grid_pin_13_ ) , .bottom_grid_pin_14_ ( cbx_1__1__16_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__16_bottom_grid_pin_15_ ) , - .ccff_tail ( cbx_1__1__16_ccff_tail ) , .SC_IN_TOP ( p2186 ) , + .ccff_tail ( cbx_1__1__16_ccff_tail ) , .SC_IN_TOP ( p1208 ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_5806 ) , .SC_IN_BOT ( scff_Wires[39] ) , .SC_OUT_TOP ( scff_Wires[40] ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[16] ) , @@ -122098,20 +126637,20 @@ cbx_1__1_ cbx_2__6_ ( .pReset_E_out ( SYNOPSYS_UNCONNECTED_5808 ) , .prog_clk_0_N_in ( prog_clk_0_wires[81] ) , .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_5809 ) , - .prog_clk_1_W_in ( p2788 ) , .prog_clk_1_E_in ( p472 ) , + .prog_clk_1_W_in ( p1343 ) , .prog_clk_1_E_in ( p571 ) , .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_5810 ) , .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_5811 ) , - .prog_clk_2_E_in ( p1875 ) , .prog_clk_2_W_in ( p2755 ) , + .prog_clk_2_E_in ( p3476 ) , .prog_clk_2_W_in ( p2462 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5812 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5813 ) , - .prog_clk_3_W_in ( p3364 ) , .prog_clk_3_E_in ( p2015 ) , + .prog_clk_3_W_in ( p2619 ) , .prog_clk_3_E_in ( p3451 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5814 ) , - .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5815 ) , .clk_1_W_in ( p1768 ) , - .clk_1_E_in ( p846 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_5816 ) , - .clk_1_S_out ( SYNOPSYS_UNCONNECTED_5817 ) , .clk_2_E_in ( p1875 ) , - .clk_2_W_in ( p3353 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5818 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5819 ) , .clk_3_W_in ( p2632 ) , - .clk_3_E_in ( p1741 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5820 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5815 ) , .clk_1_W_in ( p2544 ) , + .clk_1_E_in ( p805 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_5816 ) , + .clk_1_S_out ( SYNOPSYS_UNCONNECTED_5817 ) , .clk_2_E_in ( p2498 ) , + .clk_2_W_in ( p3430 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5818 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5819 ) , .clk_3_W_in ( p3454 ) , + .clk_3_E_in ( p2447 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5820 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5821 ) ) ; cbx_1__1_ cbx_2__7_ ( .pReset ( { SYNOPSYS_UNCONNECTED_5822 } ) , @@ -122136,7 +126675,7 @@ cbx_1__1_ cbx_2__7_ ( .bottom_grid_pin_13_ ( cbx_1__1__17_bottom_grid_pin_13_ ) , .bottom_grid_pin_14_ ( cbx_1__1__17_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__17_bottom_grid_pin_15_ ) , - .ccff_tail ( cbx_1__1__17_ccff_tail ) , .SC_IN_TOP ( p2100 ) , + .ccff_tail ( cbx_1__1__17_ccff_tail ) , .SC_IN_TOP ( p2004 ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_5823 ) , .SC_IN_BOT ( scff_Wires[41] ) , .SC_OUT_TOP ( scff_Wires[42] ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[17] ) , @@ -122152,20 +126691,20 @@ cbx_1__1_ cbx_2__7_ ( .prog_clk_1_W_in ( prog_clk_1_wires[22] ) , .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_5827 ) , .prog_clk_1_N_out ( prog_clk_1_wires[26] ) , - .prog_clk_1_S_out ( prog_clk_1_wires[27] ) , .prog_clk_2_E_in ( p1855 ) , - .prog_clk_2_W_in ( p1090 ) , + .prog_clk_1_S_out ( prog_clk_1_wires[27] ) , .prog_clk_2_E_in ( p3325 ) , + .prog_clk_2_W_in ( p3204 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5828 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5829 ) , - .prog_clk_3_W_in ( p2780 ) , .prog_clk_3_E_in ( p1981 ) , + .prog_clk_3_W_in ( p3225 ) , .prog_clk_3_E_in ( p3306 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5830 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5831 ) , .clk_1_W_in ( clk_1_wires[22] ) , .clk_1_E_in ( SYNOPSYS_UNCONNECTED_5832 ) , .clk_1_N_out ( clk_1_wires[26] ) , .clk_1_S_out ( clk_1_wires[27] ) , - .clk_2_E_in ( p1855 ) , .clk_2_W_in ( p3043 ) , + .clk_2_E_in ( p2571 ) , .clk_2_W_in ( p2934 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5833 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5834 ) , .clk_3_W_in ( p3055 ) , - .clk_3_E_in ( p1773 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5835 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5834 ) , .clk_3_W_in ( p2952 ) , + .clk_3_E_in ( p2464 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5835 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5836 ) ) ; cbx_1__1_ cbx_2__8_ ( .pReset ( { SYNOPSYS_UNCONNECTED_5837 } ) , @@ -122190,7 +126729,7 @@ cbx_1__1_ cbx_2__8_ ( .bottom_grid_pin_13_ ( cbx_1__1__18_bottom_grid_pin_13_ ) , .bottom_grid_pin_14_ ( cbx_1__1__18_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__18_bottom_grid_pin_15_ ) , - .ccff_tail ( cbx_1__1__18_ccff_tail ) , .SC_IN_TOP ( p1759 ) , + .ccff_tail ( cbx_1__1__18_ccff_tail ) , .SC_IN_TOP ( p1612 ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_5838 ) , .SC_IN_BOT ( scff_Wires[43] ) , .SC_OUT_TOP ( scff_Wires[44] ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[18] ) , @@ -122203,23 +126742,23 @@ cbx_1__1_ cbx_2__8_ ( .pReset_E_out ( SYNOPSYS_UNCONNECTED_5840 ) , .prog_clk_0_N_in ( prog_clk_0_wires[87] ) , .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_5841 ) , - .prog_clk_1_W_in ( p1825 ) , .prog_clk_1_E_in ( p411 ) , + .prog_clk_1_W_in ( p1484 ) , .prog_clk_1_E_in ( p655 ) , .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_5842 ) , .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_5843 ) , .prog_clk_2_E_in ( prog_clk_2_wires[14] ) , .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_5844 ) , .prog_clk_2_W_out ( prog_clk_2_wires[13] ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5845 ) , - .prog_clk_3_W_in ( p1825 ) , .prog_clk_3_E_in ( p1712 ) , + .prog_clk_3_W_in ( p1655 ) , .prog_clk_3_E_in ( p1070 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5846 ) , - .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5847 ) , .clk_1_W_in ( p1534 ) , - .clk_1_E_in ( p465 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_5848 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5847 ) , .clk_1_W_in ( p1335 ) , + .clk_1_E_in ( p255 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_5848 ) , .clk_1_S_out ( SYNOPSYS_UNCONNECTED_5849 ) , .clk_2_E_in ( clk_2_wires[14] ) , .clk_2_W_in ( SYNOPSYS_UNCONNECTED_5850 ) , .clk_2_W_out ( clk_2_wires[13] ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5851 ) , .clk_3_W_in ( p1825 ) , - .clk_3_E_in ( p1287 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5852 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5851 ) , .clk_3_W_in ( p371 ) , + .clk_3_E_in ( p528 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5852 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5853 ) ) ; cbx_1__1_ cbx_2__9_ ( .pReset ( { SYNOPSYS_UNCONNECTED_5854 } ) , @@ -122244,7 +126783,7 @@ cbx_1__1_ cbx_2__9_ ( .bottom_grid_pin_13_ ( cbx_1__1__19_bottom_grid_pin_13_ ) , .bottom_grid_pin_14_ ( cbx_1__1__19_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__19_bottom_grid_pin_15_ ) , - .ccff_tail ( cbx_1__1__19_ccff_tail ) , .SC_IN_TOP ( p1526 ) , + .ccff_tail ( cbx_1__1__19_ccff_tail ) , .SC_IN_TOP ( p1305 ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_5855 ) , .SC_IN_BOT ( scff_Wires[45] ) , .SC_OUT_TOP ( scff_Wires[46] ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[19] ) , @@ -122260,20 +126799,20 @@ cbx_1__1_ cbx_2__9_ ( .prog_clk_1_W_in ( prog_clk_1_wires[29] ) , .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_5859 ) , .prog_clk_1_N_out ( prog_clk_1_wires[33] ) , - .prog_clk_1_S_out ( prog_clk_1_wires[34] ) , .prog_clk_2_E_in ( p2809 ) , - .prog_clk_2_W_in ( p1225 ) , + .prog_clk_1_S_out ( prog_clk_1_wires[34] ) , .prog_clk_2_E_in ( p3165 ) , + .prog_clk_2_W_in ( p2673 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5860 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5861 ) , - .prog_clk_3_W_in ( p3449 ) , .prog_clk_3_E_in ( p672 ) , + .prog_clk_3_W_in ( p2760 ) , .prog_clk_3_E_in ( p3083 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5862 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5863 ) , .clk_1_W_in ( clk_1_wires[29] ) , .clk_1_E_in ( SYNOPSYS_UNCONNECTED_5864 ) , .clk_1_N_out ( clk_1_wires[33] ) , .clk_1_S_out ( clk_1_wires[34] ) , - .clk_2_E_in ( p2809 ) , .clk_2_W_in ( p3443 ) , + .clk_2_E_in ( p1591 ) , .clk_2_W_in ( p2428 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5865 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5866 ) , .clk_3_W_in ( p1929 ) , - .clk_3_E_in ( p2758 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5867 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5866 ) , .clk_3_W_in ( p2524 ) , + .clk_3_E_in ( p1087 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5867 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5868 ) ) ; cbx_1__1_ cbx_2__10_ ( .pReset ( { SYNOPSYS_UNCONNECTED_5869 } ) , @@ -122298,7 +126837,7 @@ cbx_1__1_ cbx_2__10_ ( .bottom_grid_pin_13_ ( cbx_1__1__20_bottom_grid_pin_13_ ) , .bottom_grid_pin_14_ ( cbx_1__1__20_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__20_bottom_grid_pin_15_ ) , - .ccff_tail ( cbx_1__1__20_ccff_tail ) , .SC_IN_TOP ( p2158 ) , + .ccff_tail ( cbx_1__1__20_ccff_tail ) , .SC_IN_TOP ( p1991 ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_5870 ) , .SC_IN_BOT ( scff_Wires[47] ) , .SC_OUT_TOP ( scff_Wires[48] ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[20] ) , @@ -122311,23 +126850,23 @@ cbx_1__1_ cbx_2__10_ ( .pReset_E_out ( SYNOPSYS_UNCONNECTED_5872 ) , .prog_clk_0_N_in ( prog_clk_0_wires[93] ) , .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_5873 ) , - .prog_clk_1_W_in ( p1607 ) , .prog_clk_1_E_in ( p921 ) , + .prog_clk_1_W_in ( p1506 ) , .prog_clk_1_E_in ( p803 ) , .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_5874 ) , .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_5875 ) , .prog_clk_2_E_in ( prog_clk_2_wires[21] ) , .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_5876 ) , .prog_clk_2_W_out ( prog_clk_2_wires[20] ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5877 ) , - .prog_clk_3_W_in ( p1527 ) , .prog_clk_3_E_in ( p2047 ) , + .prog_clk_3_W_in ( p1604 ) , .prog_clk_3_E_in ( p1769 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5878 ) , - .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5879 ) , .clk_1_W_in ( p1422 ) , - .clk_1_E_in ( p380 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_5880 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5879 ) , .clk_1_W_in ( p1604 ) , + .clk_1_E_in ( p530 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_5880 ) , .clk_1_S_out ( SYNOPSYS_UNCONNECTED_5881 ) , .clk_2_E_in ( clk_2_wires[21] ) , .clk_2_W_in ( SYNOPSYS_UNCONNECTED_5882 ) , .clk_2_W_out ( clk_2_wires[20] ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5883 ) , .clk_3_W_in ( p1527 ) , - .clk_3_E_in ( p1320 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5884 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5883 ) , .clk_3_W_in ( p1604 ) , + .clk_3_E_in ( p15 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5884 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5885 ) ) ; cbx_1__1_ cbx_2__11_ ( .pReset ( { SYNOPSYS_UNCONNECTED_5886 } ) , @@ -122352,7 +126891,7 @@ cbx_1__1_ cbx_2__11_ ( .bottom_grid_pin_13_ ( cbx_1__1__21_bottom_grid_pin_13_ ) , .bottom_grid_pin_14_ ( cbx_1__1__21_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__21_bottom_grid_pin_15_ ) , - .ccff_tail ( cbx_1__1__21_ccff_tail ) , .SC_IN_TOP ( p1787 ) , + .ccff_tail ( cbx_1__1__21_ccff_tail ) , .SC_IN_TOP ( p1454 ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_5887 ) , .SC_IN_BOT ( scff_Wires[49] ) , .SC_OUT_TOP ( scff_Wires[50] ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[21] ) , @@ -122368,20 +126907,20 @@ cbx_1__1_ cbx_2__11_ ( .prog_clk_1_W_in ( prog_clk_1_wires[36] ) , .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_5891 ) , .prog_clk_1_N_out ( prog_clk_1_wires[40] ) , - .prog_clk_1_S_out ( prog_clk_1_wires[41] ) , .prog_clk_2_E_in ( p1939 ) , - .prog_clk_2_W_in ( p751 ) , + .prog_clk_1_S_out ( prog_clk_1_wires[41] ) , .prog_clk_2_E_in ( p3131 ) , + .prog_clk_2_W_in ( p2917 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5892 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5893 ) , - .prog_clk_3_W_in ( p2700 ) , .prog_clk_3_E_in ( p1765 ) , + .prog_clk_3_W_in ( p2974 ) , .prog_clk_3_E_in ( p3035 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5894 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5895 ) , .clk_1_W_in ( clk_1_wires[36] ) , .clk_1_E_in ( SYNOPSYS_UNCONNECTED_5896 ) , .clk_1_N_out ( clk_1_wires[40] ) , .clk_1_S_out ( clk_1_wires[41] ) , - .clk_2_E_in ( p1939 ) , .clk_2_W_in ( p2894 ) , + .clk_2_E_in ( p2248 ) , .clk_2_W_in ( p3177 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5897 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5898 ) , .clk_3_W_in ( p2940 ) , - .clk_3_E_in ( p1697 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5899 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5898 ) , .clk_3_W_in ( p3262 ) , + .clk_3_E_in ( p2205 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5899 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5900 ) ) ; cbx_1__1_ cbx_3__1_ ( .pReset ( { SYNOPSYS_UNCONNECTED_5901 } ) , @@ -122407,7 +126946,7 @@ cbx_1__1_ cbx_3__1_ ( .bottom_grid_pin_14_ ( cbx_1__1__22_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__22_bottom_grid_pin_15_ ) , .ccff_tail ( cbx_1__1__22_ccff_tail ) , .SC_IN_TOP ( scff_Wires[75] ) , - .SC_OUT_BOT ( scff_Wires[76] ) , .SC_IN_BOT ( p1327 ) , + .SC_OUT_BOT ( scff_Wires[76] ) , .SC_IN_BOT ( p1435 ) , .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_5902 ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[22] ) , .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[22] ) , @@ -122422,19 +126961,19 @@ cbx_1__1_ cbx_3__1_ ( .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_5906 ) , .prog_clk_1_E_in ( prog_clk_1_wires[44] ) , .prog_clk_1_N_out ( prog_clk_1_wires[45] ) , - .prog_clk_1_S_out ( prog_clk_1_wires[46] ) , .prog_clk_2_E_in ( p2647 ) , - .prog_clk_2_W_in ( p1182 ) , + .prog_clk_1_S_out ( prog_clk_1_wires[46] ) , .prog_clk_2_E_in ( p2795 ) , + .prog_clk_2_W_in ( p2496 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5907 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5908 ) , - .prog_clk_3_W_in ( p3317 ) , .prog_clk_3_E_in ( p972 ) , + .prog_clk_3_W_in ( p2538 ) , .prog_clk_3_E_in ( p2731 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5909 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5910 ) , .clk_1_W_in ( SYNOPSYS_UNCONNECTED_5911 ) , .clk_1_E_in ( clk_1_wires[44] ) , .clk_1_N_out ( clk_1_wires[45] ) , - .clk_1_S_out ( clk_1_wires[46] ) , .clk_2_E_in ( p2647 ) , - .clk_2_W_in ( p3295 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5912 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5913 ) , .clk_3_W_in ( p2628 ) , - .clk_3_E_in ( p2525 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5914 ) , + .clk_1_S_out ( clk_1_wires[46] ) , .clk_2_E_in ( p2247 ) , + .clk_2_W_in ( p3289 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5912 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5913 ) , .clk_3_W_in ( p3348 ) , + .clk_3_E_in ( p2170 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5914 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5915 ) ) ; cbx_1__1_ cbx_3__2_ ( .pReset ( { SYNOPSYS_UNCONNECTED_5916 } ) , @@ -122460,7 +126999,7 @@ cbx_1__1_ cbx_3__2_ ( .bottom_grid_pin_14_ ( cbx_1__1__23_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__23_bottom_grid_pin_15_ ) , .ccff_tail ( cbx_1__1__23_ccff_tail ) , .SC_IN_TOP ( scff_Wires[73] ) , - .SC_OUT_BOT ( scff_Wires[74] ) , .SC_IN_BOT ( p1570 ) , + .SC_OUT_BOT ( scff_Wires[74] ) , .SC_IN_BOT ( p1924 ) , .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_5917 ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[23] ) , .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[23] ) , @@ -122472,20 +127011,20 @@ cbx_1__1_ cbx_3__2_ ( .pReset_E_out ( SYNOPSYS_UNCONNECTED_5919 ) , .prog_clk_0_N_in ( prog_clk_0_wires[107] ) , .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_5920 ) , - .prog_clk_1_W_in ( p2689 ) , .prog_clk_1_E_in ( p716 ) , + .prog_clk_1_W_in ( p1310 ) , .prog_clk_1_E_in ( p1779 ) , .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_5921 ) , .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_5922 ) , - .prog_clk_2_E_in ( p1786 ) , .prog_clk_2_W_in ( p2593 ) , + .prog_clk_2_E_in ( p2945 ) , .prog_clk_2_W_in ( p2112 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5923 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5924 ) , - .prog_clk_3_W_in ( p3477 ) , .prog_clk_3_E_in ( p1126 ) , + .prog_clk_3_W_in ( p1533 ) , .prog_clk_3_E_in ( p2908 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5925 ) , - .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5926 ) , .clk_1_W_in ( p1486 ) , - .clk_1_E_in ( p2 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_5927 ) , - .clk_1_S_out ( SYNOPSYS_UNCONNECTED_5928 ) , .clk_2_E_in ( p1786 ) , - .clk_2_W_in ( p3476 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5929 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5930 ) , .clk_3_W_in ( p2811 ) , - .clk_3_E_in ( p1738 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5931 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5926 ) , .clk_1_W_in ( p2193 ) , + .clk_1_E_in ( p211 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_5927 ) , + .clk_1_S_out ( SYNOPSYS_UNCONNECTED_5928 ) , .clk_2_E_in ( p1828 ) , + .clk_2_W_in ( p3436 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5929 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5930 ) , .clk_3_W_in ( p3466 ) , + .clk_3_E_in ( p1705 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5931 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5932 ) ) ; cbx_1__1_ cbx_3__3_ ( .pReset ( { SYNOPSYS_UNCONNECTED_5933 } ) , @@ -122511,7 +127050,7 @@ cbx_1__1_ cbx_3__3_ ( .bottom_grid_pin_14_ ( cbx_1__1__24_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__24_bottom_grid_pin_15_ ) , .ccff_tail ( cbx_1__1__24_ccff_tail ) , .SC_IN_TOP ( scff_Wires[71] ) , - .SC_OUT_BOT ( scff_Wires[72] ) , .SC_IN_BOT ( p1370 ) , + .SC_OUT_BOT ( scff_Wires[72] ) , .SC_IN_BOT ( p1494 ) , .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_5934 ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[24] ) , .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[24] ) , @@ -122526,19 +127065,19 @@ cbx_1__1_ cbx_3__3_ ( .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_5938 ) , .prog_clk_1_E_in ( prog_clk_1_wires[51] ) , .prog_clk_1_N_out ( prog_clk_1_wires[52] ) , - .prog_clk_1_S_out ( prog_clk_1_wires[53] ) , .prog_clk_2_E_in ( p2110 ) , - .prog_clk_2_W_in ( p668 ) , + .prog_clk_1_S_out ( prog_clk_1_wires[53] ) , .prog_clk_2_E_in ( p2959 ) , + .prog_clk_2_W_in ( p3366 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5939 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5940 ) , - .prog_clk_3_W_in ( p2640 ) , .prog_clk_3_E_in ( p299 ) , + .prog_clk_3_W_in ( p3422 ) , .prog_clk_3_E_in ( p2929 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5941 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5942 ) , .clk_1_W_in ( SYNOPSYS_UNCONNECTED_5943 ) , .clk_1_E_in ( clk_1_wires[51] ) , .clk_1_N_out ( clk_1_wires[52] ) , - .clk_1_S_out ( clk_1_wires[53] ) , .clk_2_E_in ( p2110 ) , - .clk_2_W_in ( p2586 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5944 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5945 ) , .clk_3_W_in ( p2709 ) , - .clk_3_E_in ( p1966 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5946 ) , + .clk_1_S_out ( clk_1_wires[53] ) , .clk_2_E_in ( p1499 ) , + .clk_2_W_in ( p2488 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5944 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5945 ) , .clk_3_W_in ( p2493 ) , + .clk_3_E_in ( p1090 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5946 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5947 ) ) ; cbx_1__1_ cbx_3__4_ ( .pReset ( { SYNOPSYS_UNCONNECTED_5948 } ) , @@ -122564,7 +127103,7 @@ cbx_1__1_ cbx_3__4_ ( .bottom_grid_pin_14_ ( cbx_1__1__25_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__25_bottom_grid_pin_15_ ) , .ccff_tail ( cbx_1__1__25_ccff_tail ) , .SC_IN_TOP ( scff_Wires[69] ) , - .SC_OUT_BOT ( scff_Wires[70] ) , .SC_IN_BOT ( p1517 ) , + .SC_OUT_BOT ( scff_Wires[70] ) , .SC_IN_BOT ( p1249 ) , .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_5949 ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[25] ) , .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[25] ) , @@ -122576,20 +127115,20 @@ cbx_1__1_ cbx_3__4_ ( .pReset_E_out ( SYNOPSYS_UNCONNECTED_5951 ) , .prog_clk_0_N_in ( prog_clk_0_wires[113] ) , .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_5952 ) , - .prog_clk_1_W_in ( p1604 ) , .prog_clk_1_E_in ( p692 ) , + .prog_clk_1_W_in ( p1531 ) , .prog_clk_1_E_in ( p464 ) , .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_5953 ) , .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_5954 ) , - .prog_clk_2_E_in ( p1828 ) , .prog_clk_2_W_in ( p387 ) , + .prog_clk_2_E_in ( p2698 ) , .prog_clk_2_W_in ( p3448 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5955 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5956 ) , - .prog_clk_3_W_in ( p1962 ) , .prog_clk_3_E_in ( p120 ) , + .prog_clk_3_W_in ( p3472 ) , .prog_clk_3_E_in ( p2737 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5957 ) , - .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5958 ) , .clk_1_W_in ( p1372 ) , - .clk_1_E_in ( p669 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_5959 ) , - .clk_1_S_out ( SYNOPSYS_UNCONNECTED_5960 ) , .clk_2_E_in ( p1828 ) , - .clk_2_W_in ( p2721 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5961 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5962 ) , .clk_3_W_in ( p2795 ) , - .clk_3_E_in ( p1688 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5963 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5958 ) , .clk_1_W_in ( p2805 ) , + .clk_1_E_in ( p2174 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_5959 ) , + .clk_1_S_out ( SYNOPSYS_UNCONNECTED_5960 ) , .clk_2_E_in ( p2292 ) , + .clk_2_W_in ( p3489 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5961 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5962 ) , .clk_3_W_in ( p3510 ) , + .clk_3_E_in ( p2151 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5963 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5964 ) ) ; cbx_1__1_ cbx_3__5_ ( .pReset ( { SYNOPSYS_UNCONNECTED_5965 } ) , @@ -122615,7 +127154,7 @@ cbx_1__1_ cbx_3__5_ ( .bottom_grid_pin_14_ ( cbx_1__1__26_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__26_bottom_grid_pin_15_ ) , .ccff_tail ( cbx_1__1__26_ccff_tail ) , .SC_IN_TOP ( scff_Wires[67] ) , - .SC_OUT_BOT ( scff_Wires[68] ) , .SC_IN_BOT ( p1319 ) , + .SC_OUT_BOT ( scff_Wires[68] ) , .SC_IN_BOT ( p1490 ) , .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_5966 ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[26] ) , .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[26] ) , @@ -122630,19 +127169,19 @@ cbx_1__1_ cbx_3__5_ ( .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_5970 ) , .prog_clk_1_E_in ( prog_clk_1_wires[58] ) , .prog_clk_1_N_out ( prog_clk_1_wires[59] ) , - .prog_clk_1_S_out ( prog_clk_1_wires[60] ) , .prog_clk_2_E_in ( p2682 ) , - .prog_clk_2_W_in ( p1005 ) , + .prog_clk_1_S_out ( prog_clk_1_wires[60] ) , .prog_clk_2_E_in ( p3453 ) , + .prog_clk_2_W_in ( p2715 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5971 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5972 ) , - .prog_clk_3_W_in ( p3077 ) , .prog_clk_3_E_in ( p979 ) , + .prog_clk_3_W_in ( p2761 ) , .prog_clk_3_E_in ( p3433 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5973 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5974 ) , .clk_1_W_in ( SYNOPSYS_UNCONNECTED_5975 ) , .clk_1_E_in ( clk_1_wires[58] ) , .clk_1_N_out ( clk_1_wires[59] ) , - .clk_1_S_out ( clk_1_wires[60] ) , .clk_2_E_in ( p2682 ) , - .clk_2_W_in ( p3000 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5976 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5977 ) , .clk_3_W_in ( p3060 ) , - .clk_3_E_in ( p2595 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5978 ) , + .clk_1_S_out ( clk_1_wires[60] ) , .clk_2_E_in ( p1424 ) , + .clk_2_W_in ( p3435 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5976 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5977 ) , .clk_3_W_in ( p3475 ) , + .clk_3_E_in ( p1017 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5978 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5979 ) ) ; cbx_1__1_ cbx_3__6_ ( .pReset ( { SYNOPSYS_UNCONNECTED_5980 } ) , @@ -122668,7 +127207,7 @@ cbx_1__1_ cbx_3__6_ ( .bottom_grid_pin_14_ ( cbx_1__1__27_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__27_bottom_grid_pin_15_ ) , .ccff_tail ( cbx_1__1__27_ccff_tail ) , .SC_IN_TOP ( scff_Wires[65] ) , - .SC_OUT_BOT ( scff_Wires[66] ) , .SC_IN_BOT ( p2253 ) , + .SC_OUT_BOT ( scff_Wires[66] ) , .SC_IN_BOT ( p1240 ) , .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_5981 ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[27] ) , .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[27] ) , @@ -122680,19 +127219,19 @@ cbx_1__1_ cbx_3__6_ ( .pReset_E_out ( SYNOPSYS_UNCONNECTED_5983 ) , .prog_clk_0_N_in ( prog_clk_0_wires[119] ) , .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_5984 ) , - .prog_clk_1_W_in ( p1585 ) , .prog_clk_1_E_in ( p474 ) , + .prog_clk_1_W_in ( p1367 ) , .prog_clk_1_E_in ( p257 ) , .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_5985 ) , .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_5986 ) , - .prog_clk_2_E_in ( p1091 ) , .prog_clk_2_W_in ( p1314 ) , + .prog_clk_2_E_in ( p1388 ) , .prog_clk_2_W_in ( p2670 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5987 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5988 ) , .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_5989 ) , .prog_clk_3_E_in ( prog_clk_3_wires[50] ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5990 ) , - .prog_clk_3_W_out ( prog_clk_3_wires[51] ) , .clk_1_W_in ( p1428 ) , - .clk_1_E_in ( p1996 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_5991 ) , - .clk_1_S_out ( SYNOPSYS_UNCONNECTED_5992 ) , .clk_2_E_in ( p1091 ) , - .clk_2_W_in ( p652 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5993 ) , + .prog_clk_3_W_out ( prog_clk_3_wires[51] ) , .clk_1_W_in ( p2838 ) , + .clk_1_E_in ( p853 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_5991 ) , + .clk_1_S_out ( SYNOPSYS_UNCONNECTED_5992 ) , .clk_2_E_in ( p1451 ) , + .clk_2_W_in ( p930 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5993 ) , .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5994 ) , .clk_3_W_in ( SYNOPSYS_UNCONNECTED_5995 ) , .clk_3_E_in ( clk_3_wires[50] ) , @@ -122722,7 +127261,7 @@ cbx_1__1_ cbx_3__7_ ( .bottom_grid_pin_14_ ( cbx_1__1__28_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__28_bottom_grid_pin_15_ ) , .ccff_tail ( cbx_1__1__28_ccff_tail ) , .SC_IN_TOP ( scff_Wires[63] ) , - .SC_OUT_BOT ( scff_Wires[64] ) , .SC_IN_BOT ( p1285 ) , + .SC_OUT_BOT ( scff_Wires[64] ) , .SC_IN_BOT ( p1450 ) , .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_5998 ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[28] ) , .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[28] ) , @@ -122737,19 +127276,19 @@ cbx_1__1_ cbx_3__7_ ( .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_6002 ) , .prog_clk_1_E_in ( prog_clk_1_wires[65] ) , .prog_clk_1_N_out ( prog_clk_1_wires[66] ) , - .prog_clk_1_S_out ( prog_clk_1_wires[67] ) , .prog_clk_2_E_in ( p2422 ) , - .prog_clk_2_W_in ( p834 ) , + .prog_clk_1_S_out ( prog_clk_1_wires[67] ) , .prog_clk_2_E_in ( p2353 ) , + .prog_clk_2_W_in ( p3300 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6003 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6004 ) , - .prog_clk_3_W_in ( p2771 ) , .prog_clk_3_E_in ( p1274 ) , + .prog_clk_3_W_in ( p3320 ) , .prog_clk_3_E_in ( p2182 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6005 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6006 ) , .clk_1_W_in ( SYNOPSYS_UNCONNECTED_6007 ) , .clk_1_E_in ( clk_1_wires[65] ) , .clk_1_N_out ( clk_1_wires[66] ) , - .clk_1_S_out ( clk_1_wires[67] ) , .clk_2_E_in ( p2422 ) , - .clk_2_W_in ( p2892 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6008 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6009 ) , .clk_3_W_in ( p2994 ) , - .clk_3_E_in ( p2333 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6010 ) , + .clk_1_S_out ( clk_1_wires[67] ) , .clk_2_E_in ( p3019 ) , + .clk_2_W_in ( p3434 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6008 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6009 ) , .clk_3_W_in ( p3460 ) , + .clk_3_E_in ( p2920 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6010 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6011 ) ) ; cbx_1__1_ cbx_3__8_ ( .pReset ( { SYNOPSYS_UNCONNECTED_6012 } ) , @@ -122775,7 +127314,7 @@ cbx_1__1_ cbx_3__8_ ( .bottom_grid_pin_14_ ( cbx_1__1__29_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__29_bottom_grid_pin_15_ ) , .ccff_tail ( cbx_1__1__29_ccff_tail ) , .SC_IN_TOP ( scff_Wires[61] ) , - .SC_OUT_BOT ( scff_Wires[62] ) , .SC_IN_BOT ( p1490 ) , + .SC_OUT_BOT ( scff_Wires[62] ) , .SC_IN_BOT ( p2257 ) , .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_6013 ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[29] ) , .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[29] ) , @@ -122787,20 +127326,20 @@ cbx_1__1_ cbx_3__8_ ( .pReset_E_out ( SYNOPSYS_UNCONNECTED_6015 ) , .prog_clk_0_N_in ( prog_clk_0_wires[125] ) , .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6016 ) , - .prog_clk_1_W_in ( p2648 ) , .prog_clk_1_E_in ( p146 ) , + .prog_clk_1_W_in ( p1201 ) , .prog_clk_1_E_in ( p2147 ) , .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_6017 ) , .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_6018 ) , - .prog_clk_2_E_in ( p2248 ) , .prog_clk_2_W_in ( p2606 ) , + .prog_clk_2_E_in ( p3255 ) , .prog_clk_2_W_in ( p2186 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6019 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6020 ) , - .prog_clk_3_W_in ( p2211 ) , .prog_clk_3_E_in ( p687 ) , + .prog_clk_3_W_in ( p2026 ) , .prog_clk_3_E_in ( p3196 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6021 ) , - .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6022 ) , .clk_1_W_in ( p1770 ) , - .clk_1_E_in ( p637 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_6023 ) , - .clk_1_S_out ( SYNOPSYS_UNCONNECTED_6024 ) , .clk_2_E_in ( p2248 ) , - .clk_2_W_in ( p2909 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6025 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6026 ) , .clk_3_W_in ( p2986 ) , - .clk_3_E_in ( p2068 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6027 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6022 ) , .clk_1_W_in ( p2356 ) , + .clk_1_E_in ( p994 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_6023 ) , + .clk_1_S_out ( SYNOPSYS_UNCONNECTED_6024 ) , .clk_2_E_in ( p3025 ) , + .clk_2_W_in ( p3076 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6025 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6026 ) , .clk_3_W_in ( p3109 ) , + .clk_3_E_in ( p2935 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6027 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6028 ) ) ; cbx_1__1_ cbx_3__9_ ( .pReset ( { SYNOPSYS_UNCONNECTED_6029 } ) , @@ -122826,7 +127365,7 @@ cbx_1__1_ cbx_3__9_ ( .bottom_grid_pin_14_ ( cbx_1__1__30_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__30_bottom_grid_pin_15_ ) , .ccff_tail ( cbx_1__1__30_ccff_tail ) , .SC_IN_TOP ( scff_Wires[59] ) , - .SC_OUT_BOT ( scff_Wires[60] ) , .SC_IN_BOT ( p1566 ) , + .SC_OUT_BOT ( scff_Wires[60] ) , .SC_IN_BOT ( p1375 ) , .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_6030 ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[30] ) , .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[30] ) , @@ -122841,19 +127380,19 @@ cbx_1__1_ cbx_3__9_ ( .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_6034 ) , .prog_clk_1_E_in ( prog_clk_1_wires[72] ) , .prog_clk_1_N_out ( prog_clk_1_wires[73] ) , - .prog_clk_1_S_out ( prog_clk_1_wires[74] ) , .prog_clk_2_E_in ( p1850 ) , - .prog_clk_2_W_in ( p449 ) , + .prog_clk_1_S_out ( prog_clk_1_wires[74] ) , .prog_clk_2_E_in ( p2766 ) , + .prog_clk_2_W_in ( p2690 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6035 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6036 ) , - .prog_clk_3_W_in ( p3437 ) , .prog_clk_3_E_in ( p954 ) , + .prog_clk_3_W_in ( p2831 ) , .prog_clk_3_E_in ( p2649 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6037 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6038 ) , .clk_1_W_in ( SYNOPSYS_UNCONNECTED_6039 ) , .clk_1_E_in ( clk_1_wires[72] ) , .clk_1_N_out ( clk_1_wires[73] ) , - .clk_1_S_out ( clk_1_wires[74] ) , .clk_2_E_in ( p1850 ) , - .clk_2_W_in ( p3419 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6040 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6041 ) , .clk_3_W_in ( p2692 ) , - .clk_3_E_in ( p1742 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6042 ) , + .clk_1_S_out ( clk_1_wires[74] ) , .clk_2_E_in ( p1418 ) , + .clk_2_W_in ( p3312 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6040 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6041 ) , .clk_3_W_in ( p3322 ) , + .clk_3_E_in ( p1151 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6042 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6043 ) ) ; cbx_1__1_ cbx_3__10_ ( .pReset ( { SYNOPSYS_UNCONNECTED_6044 } ) , @@ -122879,7 +127418,7 @@ cbx_1__1_ cbx_3__10_ ( .bottom_grid_pin_14_ ( cbx_1__1__31_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__31_bottom_grid_pin_15_ ) , .ccff_tail ( cbx_1__1__31_ccff_tail ) , .SC_IN_TOP ( scff_Wires[57] ) , - .SC_OUT_BOT ( scff_Wires[58] ) , .SC_IN_BOT ( p1456 ) , + .SC_OUT_BOT ( scff_Wires[58] ) , .SC_IN_BOT ( p1129 ) , .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_6045 ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[31] ) , .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[31] ) , @@ -122891,20 +127430,20 @@ cbx_1__1_ cbx_3__10_ ( .pReset_E_out ( SYNOPSYS_UNCONNECTED_6047 ) , .prog_clk_0_N_in ( prog_clk_0_wires[131] ) , .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6048 ) , - .prog_clk_1_W_in ( p2817 ) , .prog_clk_1_E_in ( p980 ) , + .prog_clk_1_W_in ( p1365 ) , .prog_clk_1_E_in ( p469 ) , .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_6049 ) , .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_6050 ) , - .prog_clk_2_E_in ( p1499 ) , .prog_clk_2_W_in ( p2759 ) , + .prog_clk_2_E_in ( p2522 ) , .prog_clk_2_W_in ( p2881 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6051 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6052 ) , - .prog_clk_3_W_in ( p2234 ) , .prog_clk_3_E_in ( p571 ) , + .prog_clk_3_W_in ( p2987 ) , .prog_clk_3_E_in ( p2492 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6053 ) , - .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6054 ) , .clk_1_W_in ( p1445 ) , - .clk_1_E_in ( p398 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_6055 ) , - .clk_1_S_out ( SYNOPSYS_UNCONNECTED_6056 ) , .clk_2_E_in ( p1499 ) , - .clk_2_W_in ( p2095 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6057 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6058 ) , .clk_3_W_in ( p2192 ) , - .clk_3_E_in ( p1106 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6059 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6054 ) , .clk_1_W_in ( p2575 ) , + .clk_1_E_in ( p1088 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_6055 ) , + .clk_1_S_out ( SYNOPSYS_UNCONNECTED_6056 ) , .clk_2_E_in ( p2513 ) , + .clk_2_W_in ( p3212 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6057 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6058 ) , .clk_3_W_in ( p3265 ) , + .clk_3_E_in ( p2392 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6059 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6060 ) ) ; cbx_1__1_ cbx_3__11_ ( .pReset ( { SYNOPSYS_UNCONNECTED_6061 } ) , @@ -122930,7 +127469,7 @@ cbx_1__1_ cbx_3__11_ ( .bottom_grid_pin_14_ ( cbx_1__1__32_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__32_bottom_grid_pin_15_ ) , .ccff_tail ( cbx_1__1__32_ccff_tail ) , .SC_IN_TOP ( scff_Wires[55] ) , - .SC_OUT_BOT ( scff_Wires[56] ) , .SC_IN_BOT ( p1489 ) , + .SC_OUT_BOT ( scff_Wires[56] ) , .SC_IN_BOT ( p1880 ) , .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_6062 ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[32] ) , .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[32] ) , @@ -122945,19 +127484,19 @@ cbx_1__1_ cbx_3__11_ ( .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_6066 ) , .prog_clk_1_E_in ( prog_clk_1_wires[79] ) , .prog_clk_1_N_out ( prog_clk_1_wires[80] ) , - .prog_clk_1_S_out ( prog_clk_1_wires[81] ) , .prog_clk_2_E_in ( p1581 ) , - .prog_clk_2_W_in ( p1166 ) , + .prog_clk_1_S_out ( prog_clk_1_wires[81] ) , .prog_clk_2_E_in ( p2802 ) , + .prog_clk_2_W_in ( p3283 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6067 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6068 ) , - .prog_clk_3_W_in ( p3259 ) , .prog_clk_3_E_in ( p745 ) , + .prog_clk_3_W_in ( p3323 ) , .prog_clk_3_E_in ( p2704 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6069 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6070 ) , .clk_1_W_in ( SYNOPSYS_UNCONNECTED_6071 ) , .clk_1_E_in ( clk_1_wires[79] ) , .clk_1_N_out ( clk_1_wires[80] ) , - .clk_1_S_out ( clk_1_wires[81] ) , .clk_2_E_in ( p1581 ) , - .clk_2_W_in ( p3234 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6072 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6073 ) , .clk_3_W_in ( p2789 ) , - .clk_3_E_in ( p1205 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6074 ) , + .clk_1_S_out ( clk_1_wires[81] ) , .clk_2_E_in ( p2822 ) , + .clk_2_W_in ( p2483 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6072 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6073 ) , .clk_3_W_in ( p2556 ) , + .clk_3_E_in ( p2735 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6074 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6075 ) ) ; cbx_1__1_ cbx_4__1_ ( .pReset ( { SYNOPSYS_UNCONNECTED_6076 } ) , @@ -122982,7 +127521,7 @@ cbx_1__1_ cbx_4__1_ ( .bottom_grid_pin_13_ ( cbx_1__1__33_bottom_grid_pin_13_ ) , .bottom_grid_pin_14_ ( cbx_1__1__33_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__33_bottom_grid_pin_15_ ) , - .ccff_tail ( cbx_1__1__33_ccff_tail ) , .SC_IN_TOP ( p1007 ) , + .ccff_tail ( cbx_1__1__33_ccff_tail ) , .SC_IN_TOP ( p1379 ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_6077 ) , .SC_IN_BOT ( scff_Wires[82] ) , .SC_OUT_TOP ( scff_Wires[83] ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[33] ) , @@ -122998,20 +127537,20 @@ cbx_1__1_ cbx_4__1_ ( .prog_clk_1_W_in ( prog_clk_1_wires[43] ) , .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_6081 ) , .prog_clk_1_N_out ( prog_clk_1_wires[47] ) , - .prog_clk_1_S_out ( prog_clk_1_wires[48] ) , .prog_clk_2_E_in ( p2513 ) , - .prog_clk_2_W_in ( p815 ) , + .prog_clk_1_S_out ( prog_clk_1_wires[48] ) , .prog_clk_2_E_in ( p3263 ) , + .prog_clk_2_W_in ( p842 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6082 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6083 ) , - .prog_clk_3_W_in ( p3085 ) , .prog_clk_3_E_in ( p787 ) , + .prog_clk_3_W_in ( p1329 ) , .prog_clk_3_E_in ( p3215 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6084 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6085 ) , .clk_1_W_in ( clk_1_wires[43] ) , .clk_1_E_in ( SYNOPSYS_UNCONNECTED_6086 ) , .clk_1_N_out ( clk_1_wires[47] ) , .clk_1_S_out ( clk_1_wires[48] ) , - .clk_2_E_in ( p2513 ) , .clk_2_W_in ( p3003 ) , + .clk_2_E_in ( p2629 ) , .clk_2_W_in ( p3040 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6087 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6088 ) , .clk_3_W_in ( p2777 ) , - .clk_3_E_in ( p2275 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6089 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6088 ) , .clk_3_W_in ( p3163 ) , + .clk_3_E_in ( p2480 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6089 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6090 ) ) ; cbx_1__1_ cbx_4__2_ ( .pReset ( { SYNOPSYS_UNCONNECTED_6091 } ) , @@ -123036,7 +127575,7 @@ cbx_1__1_ cbx_4__2_ ( .bottom_grid_pin_13_ ( cbx_1__1__34_bottom_grid_pin_13_ ) , .bottom_grid_pin_14_ ( cbx_1__1__34_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__34_bottom_grid_pin_15_ ) , - .ccff_tail ( cbx_1__1__34_ccff_tail ) , .SC_IN_TOP ( p2133 ) , + .ccff_tail ( cbx_1__1__34_ccff_tail ) , .SC_IN_TOP ( p1441 ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_6092 ) , .SC_IN_BOT ( scff_Wires[84] ) , .SC_OUT_TOP ( scff_Wires[85] ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[34] ) , @@ -123049,23 +127588,23 @@ cbx_1__1_ cbx_4__2_ ( .pReset_E_out ( SYNOPSYS_UNCONNECTED_6094 ) , .prog_clk_0_N_in ( prog_clk_0_wires[145] ) , .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6095 ) , - .prog_clk_1_W_in ( p1421 ) , .prog_clk_1_E_in ( p2359 ) , + .prog_clk_1_W_in ( p1492 ) , .prog_clk_1_E_in ( p104 ) , .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_6096 ) , .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_6097 ) , .prog_clk_2_E_in ( prog_clk_2_wires[27] ) , .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_6098 ) , .prog_clk_2_W_out ( prog_clk_2_wires[28] ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6099 ) , - .prog_clk_3_W_in ( p1421 ) , .prog_clk_3_E_in ( p2088 ) , + .prog_clk_3_W_in ( p1391 ) , .prog_clk_3_E_in ( p352 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6100 ) , - .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6101 ) , .clk_1_W_in ( p1500 ) , - .clk_1_E_in ( p615 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_6102 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6101 ) , .clk_1_W_in ( p1391 ) , + .clk_1_E_in ( p806 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_6102 ) , .clk_1_S_out ( SYNOPSYS_UNCONNECTED_6103 ) , .clk_2_E_in ( clk_2_wires[27] ) , .clk_2_W_in ( SYNOPSYS_UNCONNECTED_6104 ) , .clk_2_W_out ( clk_2_wires[28] ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6105 ) , .clk_3_W_in ( p1421 ) , - .clk_3_E_in ( p2285 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6106 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6105 ) , .clk_3_W_in ( p1391 ) , + .clk_3_E_in ( p1230 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6106 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6107 ) ) ; cbx_1__1_ cbx_4__3_ ( .pReset ( { SYNOPSYS_UNCONNECTED_6108 } ) , @@ -123090,7 +127629,7 @@ cbx_1__1_ cbx_4__3_ ( .bottom_grid_pin_13_ ( cbx_1__1__35_bottom_grid_pin_13_ ) , .bottom_grid_pin_14_ ( cbx_1__1__35_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__35_bottom_grid_pin_15_ ) , - .ccff_tail ( cbx_1__1__35_ccff_tail ) , .SC_IN_TOP ( p1577 ) , + .ccff_tail ( cbx_1__1__35_ccff_tail ) , .SC_IN_TOP ( p1548 ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_6109 ) , .SC_IN_BOT ( scff_Wires[86] ) , .SC_OUT_TOP ( scff_Wires[87] ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[35] ) , @@ -123106,20 +127645,20 @@ cbx_1__1_ cbx_4__3_ ( .prog_clk_1_W_in ( prog_clk_1_wires[50] ) , .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_6113 ) , .prog_clk_1_N_out ( prog_clk_1_wires[54] ) , - .prog_clk_1_S_out ( prog_clk_1_wires[55] ) , .prog_clk_2_E_in ( p2443 ) , - .prog_clk_2_W_in ( p1318 ) , + .prog_clk_1_S_out ( prog_clk_1_wires[55] ) , .prog_clk_2_E_in ( p2219 ) , + .prog_clk_2_W_in ( p3066 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6114 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6115 ) , - .prog_clk_3_W_in ( p2802 ) , .prog_clk_3_E_in ( p72 ) , + .prog_clk_3_W_in ( p3146 ) , .prog_clk_3_E_in ( p2153 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6116 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6117 ) , .clk_1_W_in ( clk_1_wires[50] ) , .clk_1_E_in ( SYNOPSYS_UNCONNECTED_6118 ) , .clk_1_N_out ( clk_1_wires[54] ) , .clk_1_S_out ( clk_1_wires[55] ) , - .clk_2_E_in ( p2443 ) , .clk_2_W_in ( p2750 ) , + .clk_2_E_in ( p2250 ) , .clk_2_W_in ( p1806 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6119 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6120 ) , .clk_3_W_in ( p1847 ) , - .clk_3_E_in ( p2279 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6121 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6120 ) , .clk_3_W_in ( p2002 ) , + .clk_3_E_in ( p2083 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6121 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6122 ) ) ; cbx_1__1_ cbx_4__4_ ( .pReset ( { SYNOPSYS_UNCONNECTED_6123 } ) , @@ -123144,7 +127683,7 @@ cbx_1__1_ cbx_4__4_ ( .bottom_grid_pin_13_ ( cbx_1__1__36_bottom_grid_pin_13_ ) , .bottom_grid_pin_14_ ( cbx_1__1__36_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__36_bottom_grid_pin_15_ ) , - .ccff_tail ( cbx_1__1__36_ccff_tail ) , .SC_IN_TOP ( p1885 ) , + .ccff_tail ( cbx_1__1__36_ccff_tail ) , .SC_IN_TOP ( p2574 ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_6124 ) , .SC_IN_BOT ( scff_Wires[88] ) , .SC_OUT_TOP ( scff_Wires[89] ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[36] ) , @@ -123157,23 +127696,23 @@ cbx_1__1_ cbx_4__4_ ( .pReset_E_out ( SYNOPSYS_UNCONNECTED_6126 ) , .prog_clk_0_N_in ( prog_clk_0_wires[151] ) , .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6127 ) , - .prog_clk_1_W_in ( p1794 ) , .prog_clk_1_E_in ( p340 ) , + .prog_clk_1_W_in ( p1205 ) , .prog_clk_1_E_in ( p241 ) , .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_6128 ) , .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_6129 ) , .prog_clk_2_E_in ( prog_clk_2_wires[36] ) , .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_6130 ) , .prog_clk_2_W_out ( prog_clk_2_wires[37] ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6131 ) , - .prog_clk_3_W_in ( p1878 ) , .prog_clk_3_E_in ( p1715 ) , + .prog_clk_3_W_in ( p1840 ) , .prog_clk_3_E_in ( p2432 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6132 ) , - .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6133 ) , .clk_1_W_in ( p1133 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6133 ) , .clk_1_W_in ( p1840 ) , .clk_1_E_in ( p688 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_6134 ) , .clk_1_S_out ( SYNOPSYS_UNCONNECTED_6135 ) , .clk_2_E_in ( clk_2_wires[36] ) , .clk_2_W_in ( SYNOPSYS_UNCONNECTED_6136 ) , .clk_2_W_out ( clk_2_wires[37] ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6137 ) , .clk_3_W_in ( p1878 ) , - .clk_3_E_in ( p1184 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6138 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6137 ) , .clk_3_W_in ( p1840 ) , + .clk_3_E_in ( p194 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6138 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6139 ) ) ; cbx_1__1_ cbx_4__5_ ( .pReset ( { SYNOPSYS_UNCONNECTED_6140 } ) , @@ -123198,7 +127737,7 @@ cbx_1__1_ cbx_4__5_ ( .bottom_grid_pin_13_ ( cbx_1__1__37_bottom_grid_pin_13_ ) , .bottom_grid_pin_14_ ( cbx_1__1__37_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__37_bottom_grid_pin_15_ ) , - .ccff_tail ( cbx_1__1__37_ccff_tail ) , .SC_IN_TOP ( p2431 ) , + .ccff_tail ( cbx_1__1__37_ccff_tail ) , .SC_IN_TOP ( p1578 ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_6141 ) , .SC_IN_BOT ( scff_Wires[90] ) , .SC_OUT_TOP ( scff_Wires[91] ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[37] ) , @@ -123214,20 +127753,20 @@ cbx_1__1_ cbx_4__5_ ( .prog_clk_1_W_in ( prog_clk_1_wires[57] ) , .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_6145 ) , .prog_clk_1_N_out ( prog_clk_1_wires[61] ) , - .prog_clk_1_S_out ( prog_clk_1_wires[62] ) , .prog_clk_2_E_in ( p2181 ) , - .prog_clk_2_W_in ( p1219 ) , + .prog_clk_1_S_out ( prog_clk_1_wires[62] ) , .prog_clk_2_E_in ( p3023 ) , + .prog_clk_2_W_in ( p2451 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6146 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6147 ) , - .prog_clk_3_W_in ( p3400 ) , .prog_clk_3_E_in ( p2301 ) , + .prog_clk_3_W_in ( p2615 ) , .prog_clk_3_E_in ( p2863 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6148 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6149 ) , .clk_1_W_in ( clk_1_wires[57] ) , .clk_1_E_in ( SYNOPSYS_UNCONNECTED_6150 ) , .clk_1_N_out ( clk_1_wires[61] ) , .clk_1_S_out ( clk_1_wires[62] ) , - .clk_2_E_in ( p2201 ) , .clk_2_W_in ( p3392 ) , + .clk_2_E_in ( p3167 ) , .clk_2_W_in ( p2709 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6151 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6152 ) , .clk_3_W_in ( p2850 ) , - .clk_3_E_in ( p2060 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6153 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6152 ) , .clk_3_W_in ( p2788 ) , + .clk_3_E_in ( p3063 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6153 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6154 ) ) ; cbx_1__1_ cbx_4__6_ ( .pReset ( { SYNOPSYS_UNCONNECTED_6155 } ) , @@ -123252,7 +127791,7 @@ cbx_1__1_ cbx_4__6_ ( .bottom_grid_pin_13_ ( cbx_1__1__38_bottom_grid_pin_13_ ) , .bottom_grid_pin_14_ ( cbx_1__1__38_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__38_bottom_grid_pin_15_ ) , - .ccff_tail ( cbx_1__1__38_ccff_tail ) , .SC_IN_TOP ( p1299 ) , + .ccff_tail ( cbx_1__1__38_ccff_tail ) , .SC_IN_TOP ( p1543 ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_6156 ) , .SC_IN_BOT ( scff_Wires[92] ) , .SC_OUT_TOP ( scff_Wires[93] ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[38] ) , @@ -123265,19 +127804,19 @@ cbx_1__1_ cbx_4__6_ ( .pReset_E_out ( SYNOPSYS_UNCONNECTED_6158 ) , .prog_clk_0_N_in ( prog_clk_0_wires[157] ) , .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6159 ) , - .prog_clk_1_W_in ( p2468 ) , .prog_clk_1_E_in ( p831 ) , + .prog_clk_1_W_in ( p1193 ) , .prog_clk_1_E_in ( p435 ) , .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_6160 ) , .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_6161 ) , - .prog_clk_2_E_in ( p1299 ) , .prog_clk_2_W_in ( p2338 ) , + .prog_clk_2_E_in ( p1997 ) , .prog_clk_2_W_in ( p2406 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6162 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6163 ) , .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_6164 ) , .prog_clk_3_E_in ( prog_clk_3_wires[46] ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6165 ) , - .prog_clk_3_W_out ( prog_clk_3_wires[47] ) , .clk_1_W_in ( p1472 ) , - .clk_1_E_in ( p601 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_6166 ) , - .clk_1_S_out ( SYNOPSYS_UNCONNECTED_6167 ) , .clk_2_E_in ( p1299 ) , - .clk_2_W_in ( p1302 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6168 ) , + .prog_clk_3_W_out ( prog_clk_3_wires[47] ) , .clk_1_W_in ( p2596 ) , + .clk_1_E_in ( p658 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_6166 ) , + .clk_1_S_out ( SYNOPSYS_UNCONNECTED_6167 ) , .clk_2_E_in ( p1997 ) , + .clk_2_W_in ( p899 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6168 ) , .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6169 ) , .clk_3_W_in ( SYNOPSYS_UNCONNECTED_6170 ) , .clk_3_E_in ( clk_3_wires[46] ) , @@ -123306,7 +127845,7 @@ cbx_1__1_ cbx_4__7_ ( .bottom_grid_pin_13_ ( cbx_1__1__39_bottom_grid_pin_13_ ) , .bottom_grid_pin_14_ ( cbx_1__1__39_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__39_bottom_grid_pin_15_ ) , - .ccff_tail ( cbx_1__1__39_ccff_tail ) , .SC_IN_TOP ( p2389 ) , + .ccff_tail ( cbx_1__1__39_ccff_tail ) , .SC_IN_TOP ( p1501 ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_6173 ) , .SC_IN_BOT ( scff_Wires[94] ) , .SC_OUT_TOP ( scff_Wires[95] ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[39] ) , @@ -123322,20 +127861,20 @@ cbx_1__1_ cbx_4__7_ ( .prog_clk_1_W_in ( prog_clk_1_wires[64] ) , .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_6177 ) , .prog_clk_1_N_out ( prog_clk_1_wires[68] ) , - .prog_clk_1_S_out ( prog_clk_1_wires[69] ) , .prog_clk_2_E_in ( p2421 ) , - .prog_clk_2_W_in ( p266 ) , + .prog_clk_1_S_out ( prog_clk_1_wires[69] ) , .prog_clk_2_E_in ( p2306 ) , + .prog_clk_2_W_in ( p2722 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6178 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6179 ) , - .prog_clk_3_W_in ( p2963 ) , .prog_clk_3_E_in ( p2304 ) , + .prog_clk_3_W_in ( p2832 ) , .prog_clk_3_E_in ( p2145 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6180 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6181 ) , .clk_1_W_in ( clk_1_wires[64] ) , .clk_1_E_in ( SYNOPSYS_UNCONNECTED_6182 ) , .clk_1_N_out ( clk_1_wires[68] ) , .clk_1_S_out ( clk_1_wires[69] ) , - .clk_2_E_in ( p2421 ) , .clk_2_W_in ( p3002 ) , + .clk_2_E_in ( p1933 ) , .clk_2_W_in ( p3296 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6183 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6184 ) , .clk_3_W_in ( p3053 ) , - .clk_3_E_in ( p2385 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6185 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6184 ) , .clk_3_W_in ( p3358 ) , + .clk_3_E_in ( p1813 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6185 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6186 ) ) ; cbx_1__1_ cbx_4__8_ ( .pReset ( { SYNOPSYS_UNCONNECTED_6187 } ) , @@ -123360,7 +127899,7 @@ cbx_1__1_ cbx_4__8_ ( .bottom_grid_pin_13_ ( cbx_1__1__40_bottom_grid_pin_13_ ) , .bottom_grid_pin_14_ ( cbx_1__1__40_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__40_bottom_grid_pin_15_ ) , - .ccff_tail ( cbx_1__1__40_ccff_tail ) , .SC_IN_TOP ( p1792 ) , + .ccff_tail ( cbx_1__1__40_ccff_tail ) , .SC_IN_TOP ( p1174 ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_6188 ) , .SC_IN_BOT ( scff_Wires[96] ) , .SC_OUT_TOP ( scff_Wires[97] ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[40] ) , @@ -123373,23 +127912,23 @@ cbx_1__1_ cbx_4__8_ ( .pReset_E_out ( SYNOPSYS_UNCONNECTED_6190 ) , .prog_clk_0_N_in ( prog_clk_0_wires[163] ) , .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6191 ) , - .prog_clk_1_W_in ( p1871 ) , .prog_clk_1_E_in ( p10 ) , + .prog_clk_1_W_in ( p721 ) , .prog_clk_1_E_in ( p746 ) , .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_6192 ) , .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_6193 ) , .prog_clk_2_E_in ( prog_clk_2_wires[49] ) , .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_6194 ) , .prog_clk_2_W_out ( prog_clk_2_wires[50] ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6195 ) , - .prog_clk_3_W_in ( p1817 ) , .prog_clk_3_E_in ( p1708 ) , + .prog_clk_3_W_in ( p1964 ) , .prog_clk_3_E_in ( p964 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6196 ) , - .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6197 ) , .clk_1_W_in ( p1407 ) , - .clk_1_E_in ( p531 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_6198 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6197 ) , .clk_1_W_in ( p1875 ) , + .clk_1_E_in ( p414 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_6198 ) , .clk_1_S_out ( SYNOPSYS_UNCONNECTED_6199 ) , .clk_2_E_in ( clk_2_wires[49] ) , .clk_2_W_in ( SYNOPSYS_UNCONNECTED_6200 ) , .clk_2_W_out ( clk_2_wires[50] ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6201 ) , .clk_3_W_in ( p1817 ) , - .clk_3_E_in ( p762 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6202 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6201 ) , .clk_3_W_in ( p1964 ) , + .clk_3_E_in ( p603 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6202 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6203 ) ) ; cbx_1__1_ cbx_4__9_ ( .pReset ( { SYNOPSYS_UNCONNECTED_6204 } ) , @@ -123414,7 +127953,7 @@ cbx_1__1_ cbx_4__9_ ( .bottom_grid_pin_13_ ( cbx_1__1__41_bottom_grid_pin_13_ ) , .bottom_grid_pin_14_ ( cbx_1__1__41_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__41_bottom_grid_pin_15_ ) , - .ccff_tail ( cbx_1__1__41_ccff_tail ) , .SC_IN_TOP ( p2091 ) , + .ccff_tail ( cbx_1__1__41_ccff_tail ) , .SC_IN_TOP ( p1411 ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_6205 ) , .SC_IN_BOT ( scff_Wires[98] ) , .SC_OUT_TOP ( scff_Wires[99] ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[41] ) , @@ -123430,20 +127969,20 @@ cbx_1__1_ cbx_4__9_ ( .prog_clk_1_W_in ( prog_clk_1_wires[71] ) , .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_6209 ) , .prog_clk_1_N_out ( prog_clk_1_wires[75] ) , - .prog_clk_1_S_out ( prog_clk_1_wires[76] ) , .prog_clk_2_E_in ( p2444 ) , - .prog_clk_2_W_in ( p1148 ) , + .prog_clk_1_S_out ( prog_clk_1_wires[76] ) , .prog_clk_2_E_in ( p3361 ) , + .prog_clk_2_W_in ( p3485 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6210 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6211 ) , - .prog_clk_3_W_in ( p1516 ) , .prog_clk_3_E_in ( p1993 ) , + .prog_clk_3_W_in ( p3499 ) , .prog_clk_3_E_in ( p3286 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6212 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6213 ) , .clk_1_W_in ( clk_1_wires[71] ) , .clk_1_E_in ( SYNOPSYS_UNCONNECTED_6214 ) , .clk_1_N_out ( clk_1_wires[75] ) , .clk_1_S_out ( clk_1_wires[76] ) , - .clk_2_E_in ( p2444 ) , .clk_2_W_in ( p2906 ) , + .clk_2_E_in ( p2839 ) , .clk_2_W_in ( p2076 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6215 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6216 ) , .clk_3_W_in ( p2970 ) , - .clk_3_E_in ( p2321 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6217 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6216 ) , .clk_3_W_in ( p2329 ) , + .clk_3_E_in ( p2740 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6217 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6218 ) ) ; cbx_1__1_ cbx_4__10_ ( .pReset ( { SYNOPSYS_UNCONNECTED_6219 } ) , @@ -123468,7 +128007,7 @@ cbx_1__1_ cbx_4__10_ ( .bottom_grid_pin_13_ ( cbx_1__1__42_bottom_grid_pin_13_ ) , .bottom_grid_pin_14_ ( cbx_1__1__42_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__42_bottom_grid_pin_15_ ) , - .ccff_tail ( cbx_1__1__42_ccff_tail ) , .SC_IN_TOP ( p1425 ) , + .ccff_tail ( cbx_1__1__42_ccff_tail ) , .SC_IN_TOP ( p1130 ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_6220 ) , .SC_IN_BOT ( scff_Wires[100] ) , .SC_OUT_TOP ( scff_Wires[101] ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[42] ) , @@ -123481,23 +128020,23 @@ cbx_1__1_ cbx_4__10_ ( .pReset_E_out ( SYNOPSYS_UNCONNECTED_6222 ) , .prog_clk_0_N_in ( prog_clk_0_wires[169] ) , .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6223 ) , - .prog_clk_1_W_in ( p1799 ) , .prog_clk_1_E_in ( p1643 ) , + .prog_clk_1_W_in ( p1282 ) , .prog_clk_1_E_in ( p676 ) , .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_6224 ) , .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_6225 ) , .prog_clk_2_E_in ( prog_clk_2_wires[62] ) , .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_6226 ) , .prog_clk_2_W_out ( prog_clk_2_wires[63] ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6227 ) , - .prog_clk_3_W_in ( p1799 ) , .prog_clk_3_E_in ( p860 ) , + .prog_clk_3_W_in ( p1223 ) , .prog_clk_3_E_in ( p1005 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6228 ) , - .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6229 ) , .clk_1_W_in ( p1383 ) , - .clk_1_E_in ( p354 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_6230 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6229 ) , .clk_1_W_in ( p1223 ) , + .clk_1_E_in ( p1004 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_6230 ) , .clk_1_S_out ( SYNOPSYS_UNCONNECTED_6231 ) , .clk_2_E_in ( clk_2_wires[62] ) , .clk_2_W_in ( SYNOPSYS_UNCONNECTED_6232 ) , .clk_2_W_out ( clk_2_wires[63] ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6233 ) , .clk_3_W_in ( p1799 ) , - .clk_3_E_in ( p1747 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6234 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6233 ) , .clk_3_W_in ( p1223 ) , + .clk_3_E_in ( p12 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6234 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6235 ) ) ; cbx_1__1_ cbx_4__11_ ( .pReset ( { SYNOPSYS_UNCONNECTED_6236 } ) , @@ -123522,7 +128061,7 @@ cbx_1__1_ cbx_4__11_ ( .bottom_grid_pin_13_ ( cbx_1__1__43_bottom_grid_pin_13_ ) , .bottom_grid_pin_14_ ( cbx_1__1__43_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__43_bottom_grid_pin_15_ ) , - .ccff_tail ( cbx_1__1__43_ccff_tail ) , .SC_IN_TOP ( p1884 ) , + .ccff_tail ( cbx_1__1__43_ccff_tail ) , .SC_IN_TOP ( p1916 ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_6237 ) , .SC_IN_BOT ( scff_Wires[102] ) , .SC_OUT_TOP ( scff_Wires[103] ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[43] ) , @@ -123538,20 +128077,20 @@ cbx_1__1_ cbx_4__11_ ( .prog_clk_1_W_in ( prog_clk_1_wires[78] ) , .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_6241 ) , .prog_clk_1_N_out ( prog_clk_1_wires[82] ) , - .prog_clk_1_S_out ( prog_clk_1_wires[83] ) , .prog_clk_2_E_in ( p1442 ) , - .prog_clk_2_W_in ( p1257 ) , + .prog_clk_1_S_out ( prog_clk_1_wires[83] ) , .prog_clk_2_E_in ( p2814 ) , + .prog_clk_2_W_in ( p802 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6242 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6243 ) , - .prog_clk_3_W_in ( p3169 ) , .prog_clk_3_E_in ( p1636 ) , + .prog_clk_3_W_in ( p1239 ) , .prog_clk_3_E_in ( p2716 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6244 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6245 ) , .clk_1_W_in ( clk_1_wires[78] ) , .clk_1_E_in ( SYNOPSYS_UNCONNECTED_6246 ) , .clk_1_N_out ( clk_1_wires[82] ) , .clk_1_S_out ( clk_1_wires[83] ) , - .clk_2_E_in ( p1442 ) , .clk_2_W_in ( p3143 ) , + .clk_2_E_in ( p2824 ) , .clk_2_W_in ( p3447 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6247 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6248 ) , .clk_3_W_in ( p1806 ) , - .clk_3_E_in ( p250 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6249 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6248 ) , .clk_3_W_in ( p3456 ) , + .clk_3_E_in ( p2738 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6249 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6250 ) ) ; cbx_1__1_ cbx_5__1_ ( .pReset ( { SYNOPSYS_UNCONNECTED_6251 } ) , @@ -123577,7 +128116,7 @@ cbx_1__1_ cbx_5__1_ ( .bottom_grid_pin_14_ ( cbx_1__1__44_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__44_bottom_grid_pin_15_ ) , .ccff_tail ( cbx_1__1__44_ccff_tail ) , .SC_IN_TOP ( scff_Wires[128] ) , - .SC_OUT_BOT ( scff_Wires[129] ) , .SC_IN_BOT ( p1404 ) , + .SC_OUT_BOT ( scff_Wires[129] ) , .SC_IN_BOT ( p1346 ) , .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_6252 ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[44] ) , .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[44] ) , @@ -123592,19 +128131,19 @@ cbx_1__1_ cbx_5__1_ ( .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_6256 ) , .prog_clk_1_E_in ( prog_clk_1_wires[86] ) , .prog_clk_1_N_out ( prog_clk_1_wires[87] ) , - .prog_clk_1_S_out ( prog_clk_1_wires[88] ) , .prog_clk_2_E_in ( p2612 ) , - .prog_clk_2_W_in ( p1250 ) , + .prog_clk_1_S_out ( prog_clk_1_wires[88] ) , .prog_clk_2_E_in ( p3243 ) , + .prog_clk_2_W_in ( p3192 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6257 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6258 ) , - .prog_clk_3_W_in ( p3244 ) , .prog_clk_3_E_in ( p1038 ) , + .prog_clk_3_W_in ( p3279 ) , .prog_clk_3_E_in ( p3184 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6259 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6260 ) , .clk_1_W_in ( SYNOPSYS_UNCONNECTED_6261 ) , .clk_1_E_in ( clk_1_wires[86] ) , .clk_1_N_out ( clk_1_wires[87] ) , - .clk_1_S_out ( clk_1_wires[88] ) , .clk_2_E_in ( p2612 ) , - .clk_2_W_in ( p3231 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6262 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6263 ) , .clk_3_W_in ( p2653 ) , - .clk_3_E_in ( p2598 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6264 ) , + .clk_1_S_out ( clk_1_wires[88] ) , .clk_2_E_in ( p1624 ) , + .clk_2_W_in ( p3362 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6262 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6263 ) , .clk_3_W_in ( p3396 ) , + .clk_3_E_in ( p284 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6264 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6265 ) ) ; cbx_1__1_ cbx_5__2_ ( .pReset ( { SYNOPSYS_UNCONNECTED_6266 } ) , @@ -123630,7 +128169,7 @@ cbx_1__1_ cbx_5__2_ ( .bottom_grid_pin_14_ ( cbx_1__1__45_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__45_bottom_grid_pin_15_ ) , .ccff_tail ( cbx_1__1__45_ccff_tail ) , .SC_IN_TOP ( scff_Wires[126] ) , - .SC_OUT_BOT ( scff_Wires[127] ) , .SC_IN_BOT ( p1457 ) , + .SC_OUT_BOT ( scff_Wires[127] ) , .SC_IN_BOT ( p2280 ) , .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_6267 ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[45] ) , .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[45] ) , @@ -123642,23 +128181,23 @@ cbx_1__1_ cbx_5__2_ ( .pReset_E_out ( SYNOPSYS_UNCONNECTED_6269 ) , .prog_clk_0_N_in ( prog_clk_0_wires[183] ) , .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6270 ) , - .prog_clk_1_W_in ( p1870 ) , .prog_clk_1_E_in ( p1711 ) , + .prog_clk_1_W_in ( p1500 ) , .prog_clk_1_E_in ( p2092 ) , .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_6271 ) , .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_6272 ) , .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_6273 ) , .prog_clk_2_W_in ( prog_clk_2_wires[25] ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6274 ) , - .prog_clk_2_E_out ( prog_clk_2_wires[26] ) , .prog_clk_3_W_in ( p1919 ) , - .prog_clk_3_E_in ( p952 ) , + .prog_clk_2_E_out ( prog_clk_2_wires[26] ) , .prog_clk_3_W_in ( p1990 ) , + .prog_clk_3_E_in ( p906 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6275 ) , - .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6276 ) , .clk_1_W_in ( p1167 ) , - .clk_1_E_in ( p636 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_6277 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6276 ) , .clk_1_W_in ( p1934 ) , + .clk_1_E_in ( p927 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_6277 ) , .clk_1_S_out ( SYNOPSYS_UNCONNECTED_6278 ) , .clk_2_E_in ( SYNOPSYS_UNCONNECTED_6279 ) , .clk_2_W_in ( clk_2_wires[25] ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6280 ) , - .clk_2_E_out ( clk_2_wires[26] ) , .clk_3_W_in ( p1919 ) , - .clk_3_E_in ( p1749 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6281 ) , + .clk_2_E_out ( clk_2_wires[26] ) , .clk_3_W_in ( p1990 ) , + .clk_3_E_in ( p244 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6281 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6282 ) ) ; cbx_1__1_ cbx_5__3_ ( .pReset ( { SYNOPSYS_UNCONNECTED_6283 } ) , @@ -123684,7 +128223,7 @@ cbx_1__1_ cbx_5__3_ ( .bottom_grid_pin_14_ ( cbx_1__1__46_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__46_bottom_grid_pin_15_ ) , .ccff_tail ( cbx_1__1__46_ccff_tail ) , .SC_IN_TOP ( scff_Wires[124] ) , - .SC_OUT_BOT ( scff_Wires[125] ) , .SC_IN_BOT ( p1769 ) , + .SC_OUT_BOT ( scff_Wires[125] ) , .SC_IN_BOT ( p1616 ) , .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_6284 ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[46] ) , .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[46] ) , @@ -123699,19 +128238,19 @@ cbx_1__1_ cbx_5__3_ ( .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_6288 ) , .prog_clk_1_E_in ( prog_clk_1_wires[93] ) , .prog_clk_1_N_out ( prog_clk_1_wires[94] ) , - .prog_clk_1_S_out ( prog_clk_1_wires[95] ) , .prog_clk_2_E_in ( p1492 ) , - .prog_clk_2_W_in ( p734 ) , + .prog_clk_1_S_out ( prog_clk_1_wires[95] ) , .prog_clk_2_E_in ( p3015 ) , + .prog_clk_2_W_in ( p3378 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6289 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6290 ) , - .prog_clk_3_W_in ( p2774 ) , .prog_clk_3_E_in ( p592 ) , + .prog_clk_3_W_in ( p3421 ) , .prog_clk_3_E_in ( p2891 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6291 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6292 ) , .clk_1_W_in ( SYNOPSYS_UNCONNECTED_6293 ) , .clk_1_E_in ( clk_1_wires[93] ) , .clk_1_N_out ( clk_1_wires[94] ) , - .clk_1_S_out ( clk_1_wires[95] ) , .clk_2_E_in ( p1492 ) , - .clk_2_W_in ( p2870 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6294 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6295 ) , .clk_3_W_in ( p2995 ) , - .clk_3_E_in ( p1067 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6296 ) , + .clk_1_S_out ( clk_1_wires[95] ) , .clk_2_E_in ( p2526 ) , + .clk_2_W_in ( p3317 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6294 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6295 ) , .clk_3_W_in ( p3336 ) , + .clk_3_E_in ( p2476 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6296 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6297 ) ) ; cbx_1__1_ cbx_5__4_ ( .pReset ( { SYNOPSYS_UNCONNECTED_6298 } ) , @@ -123737,7 +128276,7 @@ cbx_1__1_ cbx_5__4_ ( .bottom_grid_pin_14_ ( cbx_1__1__47_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__47_bottom_grid_pin_15_ ) , .ccff_tail ( cbx_1__1__47_ccff_tail ) , .SC_IN_TOP ( scff_Wires[122] ) , - .SC_OUT_BOT ( scff_Wires[123] ) , .SC_IN_BOT ( p1790 ) , + .SC_OUT_BOT ( scff_Wires[123] ) , .SC_IN_BOT ( p1576 ) , .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_6299 ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[47] ) , .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[47] ) , @@ -123749,23 +128288,23 @@ cbx_1__1_ cbx_5__4_ ( .pReset_E_out ( SYNOPSYS_UNCONNECTED_6301 ) , .prog_clk_0_N_in ( prog_clk_0_wires[189] ) , .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6302 ) , - .prog_clk_1_W_in ( p1224 ) , .prog_clk_1_E_in ( p319 ) , + .prog_clk_1_W_in ( p1457 ) , .prog_clk_1_E_in ( p622 ) , .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_6303 ) , .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_6304 ) , .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_6305 ) , .prog_clk_2_W_in ( prog_clk_2_wires[34] ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6306 ) , - .prog_clk_2_E_out ( prog_clk_2_wires[35] ) , .prog_clk_3_W_in ( p1224 ) , - .prog_clk_3_E_in ( p244 ) , + .prog_clk_2_E_out ( prog_clk_2_wires[35] ) , .prog_clk_3_W_in ( p1041 ) , + .prog_clk_3_E_in ( p984 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6307 ) , - .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6308 ) , .clk_1_W_in ( p1528 ) , - .clk_1_E_in ( p1714 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_6309 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6308 ) , .clk_1_W_in ( p1041 ) , + .clk_1_E_in ( p604 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_6309 ) , .clk_1_S_out ( SYNOPSYS_UNCONNECTED_6310 ) , .clk_2_E_in ( SYNOPSYS_UNCONNECTED_6311 ) , .clk_2_W_in ( clk_2_wires[34] ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6312 ) , - .clk_2_E_out ( clk_2_wires[35] ) , .clk_3_W_in ( p1224 ) , - .clk_3_E_in ( p1156 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6313 ) , + .clk_2_E_out ( clk_2_wires[35] ) , .clk_3_W_in ( p1041 ) , + .clk_3_E_in ( p328 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6313 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6314 ) ) ; cbx_1__1_ cbx_5__5_ ( .pReset ( { SYNOPSYS_UNCONNECTED_6315 } ) , @@ -123791,7 +128330,7 @@ cbx_1__1_ cbx_5__5_ ( .bottom_grid_pin_14_ ( cbx_1__1__48_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__48_bottom_grid_pin_15_ ) , .ccff_tail ( cbx_1__1__48_ccff_tail ) , .SC_IN_TOP ( scff_Wires[120] ) , - .SC_OUT_BOT ( scff_Wires[121] ) , .SC_IN_BOT ( p1351 ) , + .SC_OUT_BOT ( scff_Wires[121] ) , .SC_IN_BOT ( p1350 ) , .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_6316 ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[48] ) , .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[48] ) , @@ -123806,19 +128345,19 @@ cbx_1__1_ cbx_5__5_ ( .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_6320 ) , .prog_clk_1_E_in ( prog_clk_1_wires[100] ) , .prog_clk_1_N_out ( prog_clk_1_wires[101] ) , - .prog_clk_1_S_out ( prog_clk_1_wires[102] ) , .prog_clk_2_E_in ( p1900 ) , - .prog_clk_2_W_in ( p270 ) , + .prog_clk_1_S_out ( prog_clk_1_wires[102] ) , .prog_clk_2_E_in ( p3397 ) , + .prog_clk_2_W_in ( p1800 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6321 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6322 ) , - .prog_clk_3_W_in ( p2167 ) , .prog_clk_3_E_in ( p1217 ) , + .prog_clk_3_W_in ( p2049 ) , .prog_clk_3_E_in ( p3377 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6323 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6324 ) , .clk_1_W_in ( SYNOPSYS_UNCONNECTED_6325 ) , .clk_1_E_in ( clk_1_wires[100] ) , .clk_1_N_out ( clk_1_wires[101] ) , - .clk_1_S_out ( clk_1_wires[102] ) , .clk_2_E_in ( p1900 ) , - .clk_2_W_in ( p2056 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6326 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6327 ) , .clk_3_W_in ( p1569 ) , - .clk_3_E_in ( p1695 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6328 ) , + .clk_1_S_out ( clk_1_wires[102] ) , .clk_2_E_in ( p2551 ) , + .clk_2_W_in ( p3482 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6326 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6327 ) , .clk_3_W_in ( p3508 ) , + .clk_3_E_in ( p2455 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6328 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6329 ) ) ; cbx_1__1_ cbx_5__6_ ( .pReset ( { SYNOPSYS_UNCONNECTED_6330 } ) , @@ -123844,7 +128383,7 @@ cbx_1__1_ cbx_5__6_ ( .bottom_grid_pin_14_ ( cbx_1__1__49_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__49_bottom_grid_pin_15_ ) , .ccff_tail ( cbx_1__1__49_ccff_tail ) , .SC_IN_TOP ( scff_Wires[118] ) , - .SC_OUT_BOT ( scff_Wires[119] ) , .SC_IN_BOT ( p1249 ) , + .SC_OUT_BOT ( scff_Wires[119] ) , .SC_IN_BOT ( p1483 ) , .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_6331 ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[49] ) , .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[49] ) , @@ -123856,19 +128395,19 @@ cbx_1__1_ cbx_5__6_ ( .pReset_E_out ( SYNOPSYS_UNCONNECTED_6333 ) , .prog_clk_0_N_in ( prog_clk_0_wires[195] ) , .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6334 ) , - .prog_clk_1_W_in ( p1354 ) , .prog_clk_1_E_in ( p620 ) , + .prog_clk_1_W_in ( p1342 ) , .prog_clk_1_E_in ( p327 ) , .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_6335 ) , .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_6336 ) , - .prog_clk_2_E_in ( p1393 ) , .prog_clk_2_W_in ( p50 ) , + .prog_clk_2_E_in ( p1843 ) , .prog_clk_2_W_in ( p1766 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6337 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6338 ) , .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_6339 ) , .prog_clk_3_E_in ( prog_clk_3_wires[6] ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6340 ) , - .prog_clk_3_W_out ( prog_clk_3_wires[7] ) , .clk_1_W_in ( p1154 ) , - .clk_1_E_in ( p633 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_6341 ) , - .clk_1_S_out ( SYNOPSYS_UNCONNECTED_6342 ) , .clk_2_E_in ( p1393 ) , - .clk_2_W_in ( p960 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6343 ) , + .prog_clk_3_W_out ( prog_clk_3_wires[7] ) , .clk_1_W_in ( p2000 ) , + .clk_1_E_in ( p734 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_6341 ) , + .clk_1_S_out ( SYNOPSYS_UNCONNECTED_6342 ) , .clk_2_E_in ( p1921 ) , + .clk_2_W_in ( p749 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6343 ) , .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6344 ) , .clk_3_W_in ( SYNOPSYS_UNCONNECTED_6345 ) , .clk_3_E_in ( clk_3_wires[6] ) , @@ -123898,7 +128437,7 @@ cbx_1__1_ cbx_5__7_ ( .bottom_grid_pin_14_ ( cbx_1__1__50_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__50_bottom_grid_pin_15_ ) , .ccff_tail ( cbx_1__1__50_ccff_tail ) , .SC_IN_TOP ( scff_Wires[116] ) , - .SC_OUT_BOT ( scff_Wires[117] ) , .SC_IN_BOT ( p1325 ) , + .SC_OUT_BOT ( scff_Wires[117] ) , .SC_IN_BOT ( p1153 ) , .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_6348 ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[50] ) , .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[50] ) , @@ -123913,19 +128452,19 @@ cbx_1__1_ cbx_5__7_ ( .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_6352 ) , .prog_clk_1_E_in ( prog_clk_1_wires[107] ) , .prog_clk_1_N_out ( prog_clk_1_wires[108] ) , - .prog_clk_1_S_out ( prog_clk_1_wires[109] ) , .prog_clk_2_E_in ( p1811 ) , - .prog_clk_2_W_in ( p1139 ) , + .prog_clk_1_S_out ( prog_clk_1_wires[109] ) , .prog_clk_2_E_in ( p2818 ) , + .prog_clk_2_W_in ( p2666 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6353 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6354 ) , - .prog_clk_3_W_in ( p3329 ) , .prog_clk_3_E_in ( p1055 ) , + .prog_clk_3_W_in ( p2791 ) , .prog_clk_3_E_in ( p2667 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6355 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6356 ) , .clk_1_W_in ( SYNOPSYS_UNCONNECTED_6357 ) , .clk_1_E_in ( clk_1_wires[107] ) , .clk_1_N_out ( clk_1_wires[108] ) , - .clk_1_S_out ( clk_1_wires[109] ) , .clk_2_E_in ( p1811 ) , - .clk_2_W_in ( p3297 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6358 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6359 ) , .clk_3_W_in ( p2120 ) , - .clk_3_E_in ( p1689 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6360 ) , + .clk_1_S_out ( clk_1_wires[109] ) , .clk_2_E_in ( p1609 ) , + .clk_2_W_in ( p2407 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6358 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6359 ) , .clk_3_W_in ( p2618 ) , + .clk_3_E_in ( p268 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6360 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6361 ) ) ; cbx_1__1_ cbx_5__8_ ( .pReset ( { SYNOPSYS_UNCONNECTED_6362 } ) , @@ -123951,7 +128490,7 @@ cbx_1__1_ cbx_5__8_ ( .bottom_grid_pin_14_ ( cbx_1__1__51_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__51_bottom_grid_pin_15_ ) , .ccff_tail ( cbx_1__1__51_ccff_tail ) , .SC_IN_TOP ( scff_Wires[114] ) , - .SC_OUT_BOT ( scff_Wires[115] ) , .SC_IN_BOT ( p1200 ) , + .SC_OUT_BOT ( scff_Wires[115] ) , .SC_IN_BOT ( p1586 ) , .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_6363 ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[51] ) , .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[51] ) , @@ -123963,23 +128502,23 @@ cbx_1__1_ cbx_5__8_ ( .pReset_E_out ( SYNOPSYS_UNCONNECTED_6365 ) , .prog_clk_0_N_in ( prog_clk_0_wires[201] ) , .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6366 ) , - .prog_clk_1_W_in ( p1447 ) , .prog_clk_1_E_in ( p2354 ) , + .prog_clk_1_W_in ( p924 ) , .prog_clk_1_E_in ( p533 ) , .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_6367 ) , .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_6368 ) , .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_6369 ) , .prog_clk_2_W_in ( prog_clk_2_wires[47] ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6370 ) , - .prog_clk_2_E_out ( prog_clk_2_wires[48] ) , .prog_clk_3_W_in ( p1447 ) , - .prog_clk_3_E_in ( p1281 ) , + .prog_clk_2_E_out ( prog_clk_2_wires[48] ) , .prog_clk_3_W_in ( p1353 ) , + .prog_clk_3_E_in ( p914 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6371 ) , - .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6372 ) , .clk_1_W_in ( p1365 ) , - .clk_1_E_in ( p237 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_6373 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6372 ) , .clk_1_W_in ( p1353 ) , + .clk_1_E_in ( p911 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_6373 ) , .clk_1_S_out ( SYNOPSYS_UNCONNECTED_6374 ) , .clk_2_E_in ( SYNOPSYS_UNCONNECTED_6375 ) , .clk_2_W_in ( clk_2_wires[47] ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6376 ) , - .clk_2_E_out ( clk_2_wires[48] ) , .clk_3_W_in ( p1447 ) , - .clk_3_E_in ( p2302 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6377 ) , + .clk_2_E_out ( clk_2_wires[48] ) , .clk_3_W_in ( p1353 ) , + .clk_3_E_in ( p369 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6377 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6378 ) ) ; cbx_1__1_ cbx_5__9_ ( .pReset ( { SYNOPSYS_UNCONNECTED_6379 } ) , @@ -124005,7 +128544,7 @@ cbx_1__1_ cbx_5__9_ ( .bottom_grid_pin_14_ ( cbx_1__1__52_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__52_bottom_grid_pin_15_ ) , .ccff_tail ( cbx_1__1__52_ccff_tail ) , .SC_IN_TOP ( scff_Wires[112] ) , - .SC_OUT_BOT ( scff_Wires[113] ) , .SC_IN_BOT ( p1519 ) , + .SC_OUT_BOT ( scff_Wires[113] ) , .SC_IN_BOT ( p1358 ) , .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_6380 ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[52] ) , .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[52] ) , @@ -124020,19 +128559,19 @@ cbx_1__1_ cbx_5__9_ ( .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_6384 ) , .prog_clk_1_E_in ( prog_clk_1_wires[114] ) , .prog_clk_1_N_out ( prog_clk_1_wires[115] ) , - .prog_clk_1_S_out ( prog_clk_1_wires[116] ) , .prog_clk_2_E_in ( p1564 ) , - .prog_clk_2_W_in ( p371 ) , + .prog_clk_1_S_out ( prog_clk_1_wires[116] ) , .prog_clk_2_E_in ( p3098 ) , + .prog_clk_2_W_in ( p1103 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6385 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6386 ) , - .prog_clk_3_W_in ( p2105 ) , .prog_clk_3_E_in ( p1202 ) , + .prog_clk_3_W_in ( p1291 ) , .prog_clk_3_E_in ( p3065 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6387 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6388 ) , .clk_1_W_in ( SYNOPSYS_UNCONNECTED_6389 ) , .clk_1_E_in ( clk_1_wires[114] ) , .clk_1_N_out ( clk_1_wires[115] ) , - .clk_1_S_out ( clk_1_wires[116] ) , .clk_2_E_in ( p1564 ) , - .clk_2_W_in ( p2526 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6390 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6391 ) , .clk_3_W_in ( p2711 ) , - .clk_3_E_in ( p396 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6392 ) , + .clk_1_S_out ( clk_1_wires[116] ) , .clk_2_E_in ( p2269 ) , + .clk_2_W_in ( p2401 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6390 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6391 ) , .clk_3_W_in ( p2612 ) , + .clk_3_E_in ( p2166 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6392 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6393 ) ) ; cbx_1__1_ cbx_5__10_ ( .pReset ( { SYNOPSYS_UNCONNECTED_6394 } ) , @@ -124058,7 +128597,7 @@ cbx_1__1_ cbx_5__10_ ( .bottom_grid_pin_14_ ( cbx_1__1__53_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__53_bottom_grid_pin_15_ ) , .ccff_tail ( cbx_1__1__53_ccff_tail ) , .SC_IN_TOP ( scff_Wires[110] ) , - .SC_OUT_BOT ( scff_Wires[111] ) , .SC_IN_BOT ( p1062 ) , + .SC_OUT_BOT ( scff_Wires[111] ) , .SC_IN_BOT ( p1967 ) , .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_6395 ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[53] ) , .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[53] ) , @@ -124070,23 +128609,23 @@ cbx_1__1_ cbx_5__10_ ( .pReset_E_out ( SYNOPSYS_UNCONNECTED_6397 ) , .prog_clk_0_N_in ( prog_clk_0_wires[207] ) , .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6398 ) , - .prog_clk_1_W_in ( p2111 ) , .prog_clk_1_E_in ( p632 ) , + .prog_clk_1_W_in ( p1364 ) , .prog_clk_1_E_in ( p1734 ) , .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_6399 ) , .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_6400 ) , .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_6401 ) , .prog_clk_2_W_in ( prog_clk_2_wires[60] ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6402 ) , - .prog_clk_2_E_out ( prog_clk_2_wires[61] ) , .prog_clk_3_W_in ( p2128 ) , - .prog_clk_3_E_in ( p187 ) , + .prog_clk_2_E_out ( prog_clk_2_wires[61] ) , .prog_clk_3_W_in ( p1319 ) , + .prog_clk_3_E_in ( p1094 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6403 ) , - .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6404 ) , .clk_1_W_in ( p1432 ) , - .clk_1_E_in ( p473 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_6405 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6404 ) , .clk_1_W_in ( p1319 ) , + .clk_1_E_in ( p1744 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_6405 ) , .clk_1_S_out ( SYNOPSYS_UNCONNECTED_6406 ) , .clk_2_E_in ( SYNOPSYS_UNCONNECTED_6407 ) , .clk_2_W_in ( clk_2_wires[60] ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6408 ) , - .clk_2_E_out ( clk_2_wires[61] ) , .clk_3_W_in ( p2128 ) , - .clk_3_E_in ( p1278 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6409 ) , + .clk_2_E_out ( clk_2_wires[61] ) , .clk_3_W_in ( p1319 ) , + .clk_3_E_in ( p1767 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6409 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6410 ) ) ; cbx_1__1_ cbx_5__11_ ( .pReset ( { SYNOPSYS_UNCONNECTED_6411 } ) , @@ -124112,7 +128651,7 @@ cbx_1__1_ cbx_5__11_ ( .bottom_grid_pin_14_ ( cbx_1__1__54_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__54_bottom_grid_pin_15_ ) , .ccff_tail ( cbx_1__1__54_ccff_tail ) , .SC_IN_TOP ( scff_Wires[108] ) , - .SC_OUT_BOT ( scff_Wires[109] ) , .SC_IN_BOT ( p1436 ) , + .SC_OUT_BOT ( scff_Wires[109] ) , .SC_IN_BOT ( p1289 ) , .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_6412 ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[54] ) , .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[54] ) , @@ -124127,19 +128666,19 @@ cbx_1__1_ cbx_5__11_ ( .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_6416 ) , .prog_clk_1_E_in ( prog_clk_1_wires[121] ) , .prog_clk_1_N_out ( prog_clk_1_wires[122] ) , - .prog_clk_1_S_out ( prog_clk_1_wires[123] ) , .prog_clk_2_E_in ( p2241 ) , - .prog_clk_2_W_in ( p757 ) , + .prog_clk_1_S_out ( prog_clk_1_wires[123] ) , .prog_clk_2_E_in ( p2810 ) , + .prog_clk_2_W_in ( p3446 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6417 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6418 ) , - .prog_clk_3_W_in ( p3201 ) , .prog_clk_3_E_in ( p207 ) , + .prog_clk_3_W_in ( p3457 ) , .prog_clk_3_E_in ( p2736 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6419 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6420 ) , .clk_1_W_in ( SYNOPSYS_UNCONNECTED_6421 ) , .clk_1_E_in ( clk_1_wires[121] ) , .clk_1_N_out ( clk_1_wires[122] ) , - .clk_1_S_out ( clk_1_wires[123] ) , .clk_2_E_in ( p2241 ) , - .clk_2_W_in ( p3116 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6422 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6423 ) , .clk_3_W_in ( p2830 ) , - .clk_3_E_in ( p2020 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6424 ) , + .clk_1_S_out ( clk_1_wires[123] ) , .clk_2_E_in ( p3013 ) , + .clk_2_W_in ( p951 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6422 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6423 ) , .clk_3_W_in ( p1349 ) , + .clk_3_E_in ( p2911 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6424 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6425 ) ) ; cbx_1__1_ cbx_6__1_ ( .pReset ( { SYNOPSYS_UNCONNECTED_6426 } ) , @@ -124164,7 +128703,7 @@ cbx_1__1_ cbx_6__1_ ( .bottom_grid_pin_13_ ( cbx_1__1__55_bottom_grid_pin_13_ ) , .bottom_grid_pin_14_ ( cbx_1__1__55_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__55_bottom_grid_pin_15_ ) , - .ccff_tail ( cbx_1__1__55_ccff_tail ) , .SC_IN_TOP ( p1930 ) , + .ccff_tail ( cbx_1__1__55_ccff_tail ) , .SC_IN_TOP ( p1996 ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_6427 ) , .SC_IN_BOT ( scff_Wires[135] ) , .SC_OUT_TOP ( scff_Wires[136] ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[55] ) , @@ -124180,20 +128719,20 @@ cbx_1__1_ cbx_6__1_ ( .prog_clk_1_W_in ( prog_clk_1_wires[85] ) , .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_6431 ) , .prog_clk_1_N_out ( prog_clk_1_wires[89] ) , - .prog_clk_1_S_out ( prog_clk_1_wires[90] ) , .prog_clk_2_E_in ( p1529 ) , - .prog_clk_2_W_in ( p562 ) , + .prog_clk_1_S_out ( prog_clk_1_wires[90] ) , .prog_clk_2_E_in ( p1846 ) , + .prog_clk_2_W_in ( p3211 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6432 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6433 ) , - .prog_clk_3_W_in ( p2215 ) , .prog_clk_3_E_in ( p1644 ) , + .prog_clk_3_W_in ( p3278 ) , .prog_clk_3_E_in ( p1785 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6434 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6435 ) , .clk_1_W_in ( clk_1_wires[85] ) , .clk_1_E_in ( SYNOPSYS_UNCONNECTED_6436 ) , .clk_1_N_out ( clk_1_wires[89] ) , .clk_1_S_out ( clk_1_wires[90] ) , - .clk_2_E_in ( p1529 ) , .clk_2_W_in ( p2910 ) , + .clk_2_E_in ( p2786 ) , .clk_2_W_in ( p2933 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6437 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6438 ) , .clk_3_W_in ( p2939 ) , - .clk_3_E_in ( p79 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6439 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6438 ) , .clk_3_W_in ( p2986 ) , + .clk_3_E_in ( p2664 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6439 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6440 ) ) ; cbx_1__1_ cbx_6__2_ ( .pReset ( { SYNOPSYS_UNCONNECTED_6441 } ) , @@ -124218,7 +128757,7 @@ cbx_1__1_ cbx_6__2_ ( .bottom_grid_pin_13_ ( cbx_1__1__56_bottom_grid_pin_13_ ) , .bottom_grid_pin_14_ ( cbx_1__1__56_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__56_bottom_grid_pin_15_ ) , - .ccff_tail ( cbx_1__1__56_ccff_tail ) , .SC_IN_TOP ( p1922 ) , + .ccff_tail ( cbx_1__1__56_ccff_tail ) , .SC_IN_TOP ( p1855 ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_6442 ) , .SC_IN_BOT ( scff_Wires[137] ) , .SC_OUT_TOP ( scff_Wires[138] ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[56] ) , @@ -124231,20 +128770,20 @@ cbx_1__1_ cbx_6__2_ ( .pReset_E_out ( SYNOPSYS_UNCONNECTED_6444 ) , .prog_clk_0_N_in ( prog_clk_0_wires[221] ) , .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6445 ) , - .prog_clk_1_W_in ( p2398 ) , .prog_clk_1_E_in ( p930 ) , + .prog_clk_1_W_in ( p1421 ) , .prog_clk_1_E_in ( p271 ) , .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_6446 ) , .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_6447 ) , - .prog_clk_2_E_in ( p2235 ) , .prog_clk_2_W_in ( p2292 ) , + .prog_clk_2_E_in ( p3030 ) , .prog_clk_2_W_in ( p2895 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6448 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6449 ) , - .prog_clk_3_W_in ( p3108 ) , .prog_clk_3_E_in ( p1726 ) , + .prog_clk_3_W_in ( p3017 ) , .prog_clk_3_E_in ( p2893 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6450 ) , - .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6451 ) , .clk_1_W_in ( p1111 ) , - .clk_1_E_in ( p476 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_6452 ) , - .clk_1_S_out ( SYNOPSYS_UNCONNECTED_6453 ) , .clk_2_E_in ( p2235 ) , - .clk_2_W_in ( p3016 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6454 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6455 ) , .clk_3_W_in ( p2180 ) , - .clk_3_E_in ( p2042 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6456 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6451 ) , .clk_1_W_in ( p1509 ) , + .clk_1_E_in ( p817 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_6452 ) , + .clk_1_S_out ( SYNOPSYS_UNCONNECTED_6453 ) , .clk_2_E_in ( p2333 ) , + .clk_2_W_in ( p2475 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6454 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6455 ) , .clk_3_W_in ( p2636 ) , + .clk_3_E_in ( p2079 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6456 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6457 ) ) ; cbx_1__1_ cbx_6__3_ ( .pReset ( { SYNOPSYS_UNCONNECTED_6458 } ) , @@ -124269,7 +128808,7 @@ cbx_1__1_ cbx_6__3_ ( .bottom_grid_pin_13_ ( cbx_1__1__57_bottom_grid_pin_13_ ) , .bottom_grid_pin_14_ ( cbx_1__1__57_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__57_bottom_grid_pin_15_ ) , - .ccff_tail ( cbx_1__1__57_ccff_tail ) , .SC_IN_TOP ( p2626 ) , + .ccff_tail ( cbx_1__1__57_ccff_tail ) , .SC_IN_TOP ( p1443 ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_6459 ) , .SC_IN_BOT ( scff_Wires[139] ) , .SC_OUT_TOP ( scff_Wires[140] ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[57] ) , @@ -124285,20 +128824,20 @@ cbx_1__1_ cbx_6__3_ ( .prog_clk_1_W_in ( prog_clk_1_wires[92] ) , .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_6463 ) , .prog_clk_1_N_out ( prog_clk_1_wires[96] ) , - .prog_clk_1_S_out ( prog_clk_1_wires[97] ) , .prog_clk_2_E_in ( p1865 ) , - .prog_clk_2_W_in ( p698 ) , + .prog_clk_1_S_out ( prog_clk_1_wires[97] ) , .prog_clk_2_E_in ( p2363 ) , + .prog_clk_2_W_in ( p1797 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6464 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6465 ) , - .prog_clk_3_W_in ( p3310 ) , .prog_clk_3_E_in ( p2550 ) , + .prog_clk_3_W_in ( p1923 ) , .prog_clk_3_E_in ( p2134 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6466 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6467 ) , .clk_1_W_in ( clk_1_wires[92] ) , .clk_1_E_in ( SYNOPSYS_UNCONNECTED_6468 ) , .clk_1_N_out ( clk_1_wires[96] ) , .clk_1_S_out ( clk_1_wires[97] ) , - .clk_2_E_in ( p1865 ) , .clk_2_W_in ( p3281 ) , + .clk_2_E_in ( p2299 ) , .clk_2_W_in ( p2394 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6469 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6470 ) , .clk_3_W_in ( p3194 ) , - .clk_3_E_in ( p1736 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6471 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6470 ) , .clk_3_W_in ( p2627 ) , + .clk_3_E_in ( p2175 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6471 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6472 ) ) ; cbx_1__1_ cbx_6__4_ ( .pReset ( { SYNOPSYS_UNCONNECTED_6473 } ) , @@ -124323,7 +128862,7 @@ cbx_1__1_ cbx_6__4_ ( .bottom_grid_pin_13_ ( cbx_1__1__58_bottom_grid_pin_13_ ) , .bottom_grid_pin_14_ ( cbx_1__1__58_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__58_bottom_grid_pin_15_ ) , - .ccff_tail ( cbx_1__1__58_ccff_tail ) , .SC_IN_TOP ( p2130 ) , + .ccff_tail ( cbx_1__1__58_ccff_tail ) , .SC_IN_TOP ( p1273 ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_6474 ) , .SC_IN_BOT ( scff_Wires[141] ) , .SC_OUT_TOP ( scff_Wires[142] ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[58] ) , @@ -124336,20 +128875,20 @@ cbx_1__1_ cbx_6__4_ ( .pReset_E_out ( SYNOPSYS_UNCONNECTED_6476 ) , .prog_clk_0_N_in ( prog_clk_0_wires[227] ) , .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6477 ) , - .prog_clk_1_W_in ( p2436 ) , .prog_clk_1_E_in ( p673 ) , + .prog_clk_1_W_in ( p1232 ) , .prog_clk_1_E_in ( p596 ) , .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_6478 ) , .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_6479 ) , - .prog_clk_2_E_in ( p842 ) , .prog_clk_2_W_in ( p2381 ) , + .prog_clk_2_E_in ( p2259 ) , .prog_clk_2_W_in ( p3183 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6480 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6481 ) , - .prog_clk_3_W_in ( p3051 ) , .prog_clk_3_E_in ( p2044 ) , + .prog_clk_3_W_in ( p3231 ) , .prog_clk_3_E_in ( p2084 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6482 ) , - .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6483 ) , .clk_1_W_in ( p1293 ) , - .clk_1_E_in ( p890 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_6484 ) , - .clk_1_S_out ( SYNOPSYS_UNCONNECTED_6485 ) , .clk_2_E_in ( p842 ) , - .clk_2_W_in ( p3008 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6486 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6487 ) , .clk_3_W_in ( p2236 ) , - .clk_3_E_in ( p727 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6488 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6483 ) , .clk_1_W_in ( p1308 ) , + .clk_1_E_in ( p97 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_6484 ) , + .clk_1_S_out ( SYNOPSYS_UNCONNECTED_6485 ) , .clk_2_E_in ( p3171 ) , + .clk_2_W_in ( p3301 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6486 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6487 ) , .clk_3_W_in ( p3343 ) , + .clk_3_E_in ( p3041 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6488 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6489 ) ) ; cbx_1__1_ cbx_6__5_ ( .pReset ( { SYNOPSYS_UNCONNECTED_6490 } ) , @@ -124374,7 +128913,7 @@ cbx_1__1_ cbx_6__5_ ( .bottom_grid_pin_13_ ( cbx_1__1__59_bottom_grid_pin_13_ ) , .bottom_grid_pin_14_ ( cbx_1__1__59_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__59_bottom_grid_pin_15_ ) , - .ccff_tail ( cbx_1__1__59_ccff_tail ) , .SC_IN_TOP ( p2413 ) , + .ccff_tail ( cbx_1__1__59_ccff_tail ) , .SC_IN_TOP ( p1559 ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_6491 ) , .SC_IN_BOT ( scff_Wires[143] ) , .SC_OUT_TOP ( scff_Wires[144] ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[59] ) , @@ -124390,20 +128929,20 @@ cbx_1__1_ cbx_6__5_ ( .prog_clk_1_W_in ( prog_clk_1_wires[99] ) , .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_6495 ) , .prog_clk_1_N_out ( prog_clk_1_wires[103] ) , - .prog_clk_1_S_out ( prog_clk_1_wires[104] ) , .prog_clk_2_E_in ( p2675 ) , - .prog_clk_2_W_in ( p939 ) , + .prog_clk_1_S_out ( prog_clk_1_wires[104] ) , .prog_clk_2_E_in ( p1505 ) , + .prog_clk_2_W_in ( p2658 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6496 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6497 ) , - .prog_clk_3_W_in ( p3063 ) , .prog_clk_3_E_in ( p2384 ) , + .prog_clk_3_W_in ( p2750 ) , .prog_clk_3_E_in ( p618 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6498 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6499 ) , .clk_1_W_in ( clk_1_wires[99] ) , .clk_1_E_in ( SYNOPSYS_UNCONNECTED_6500 ) , .clk_1_N_out ( clk_1_wires[103] ) , .clk_1_S_out ( clk_1_wires[104] ) , - .clk_2_E_in ( p2675 ) , .clk_2_W_in ( p3022 ) , + .clk_2_E_in ( p1958 ) , .clk_2_W_in ( p3087 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6501 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6502 ) , .clk_3_W_in ( p2983 ) , - .clk_3_E_in ( p2569 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6503 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6502 ) , .clk_3_W_in ( p3122 ) , + .clk_3_E_in ( p1742 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6503 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6504 ) ) ; cbx_1__1_ cbx_6__6_ ( .pReset ( { SYNOPSYS_UNCONNECTED_6505 } ) , @@ -124428,7 +128967,7 @@ cbx_1__1_ cbx_6__6_ ( .bottom_grid_pin_13_ ( cbx_1__1__60_bottom_grid_pin_13_ ) , .bottom_grid_pin_14_ ( cbx_1__1__60_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__60_bottom_grid_pin_15_ ) , - .ccff_tail ( cbx_1__1__60_ccff_tail ) , .SC_IN_TOP ( p1835 ) , + .ccff_tail ( cbx_1__1__60_ccff_tail ) , .SC_IN_TOP ( p2017 ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_6506 ) , .SC_IN_BOT ( scff_Wires[145] ) , .SC_OUT_TOP ( scff_Wires[146] ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[60] ) , @@ -124441,19 +128980,19 @@ cbx_1__1_ cbx_6__6_ ( .pReset_E_out ( SYNOPSYS_UNCONNECTED_6508 ) , .prog_clk_0_N_in ( prog_clk_0_wires[233] ) , .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6509 ) , - .prog_clk_1_W_in ( p1858 ) , .prog_clk_1_E_in ( p677 ) , + .prog_clk_1_W_in ( p1626 ) , .prog_clk_1_E_in ( p499 ) , .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_6510 ) , .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_6511 ) , - .prog_clk_2_E_in ( p1835 ) , .prog_clk_2_W_in ( p1683 ) , + .prog_clk_2_E_in ( p2206 ) , .prog_clk_2_W_in ( p1731 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6512 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6513 ) , .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_6514 ) , .prog_clk_3_E_in ( prog_clk_3_wires[2] ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6515 ) , - .prog_clk_3_W_out ( prog_clk_3_wires[3] ) , .clk_1_W_in ( p1426 ) , - .clk_1_E_in ( p532 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_6516 ) , - .clk_1_S_out ( SYNOPSYS_UNCONNECTED_6517 ) , .clk_2_E_in ( p1835 ) , - .clk_2_W_in ( p1109 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6518 ) , + .prog_clk_3_W_out ( prog_clk_3_wires[3] ) , .clk_1_W_in ( p2030 ) , + .clk_1_E_in ( p200 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_6516 ) , + .clk_1_S_out ( SYNOPSYS_UNCONNECTED_6517 ) , .clk_2_E_in ( p2239 ) , + .clk_2_W_in ( p943 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6518 ) , .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6519 ) , .clk_3_W_in ( SYNOPSYS_UNCONNECTED_6520 ) , .clk_3_E_in ( clk_3_wires[2] ) , @@ -124482,7 +129021,7 @@ cbx_1__1_ cbx_6__7_ ( .bottom_grid_pin_13_ ( cbx_1__1__61_bottom_grid_pin_13_ ) , .bottom_grid_pin_14_ ( cbx_1__1__61_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__61_bottom_grid_pin_15_ ) , - .ccff_tail ( cbx_1__1__61_ccff_tail ) , .SC_IN_TOP ( p2649 ) , + .ccff_tail ( cbx_1__1__61_ccff_tail ) , .SC_IN_TOP ( p2256 ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_6523 ) , .SC_IN_BOT ( scff_Wires[147] ) , .SC_OUT_TOP ( scff_Wires[148] ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[61] ) , @@ -124498,20 +129037,20 @@ cbx_1__1_ cbx_6__7_ ( .prog_clk_1_W_in ( prog_clk_1_wires[106] ) , .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_6527 ) , .prog_clk_1_N_out ( prog_clk_1_wires[110] ) , - .prog_clk_1_S_out ( prog_clk_1_wires[111] ) , .prog_clk_2_E_in ( p1559 ) , - .prog_clk_2_W_in ( p988 ) , + .prog_clk_1_S_out ( prog_clk_1_wires[111] ) , .prog_clk_2_E_in ( p2620 ) , + .prog_clk_2_W_in ( p2444 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6528 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6529 ) , - .prog_clk_3_W_in ( p1954 ) , .prog_clk_3_E_in ( p2535 ) , + .prog_clk_3_W_in ( p2614 ) , .prog_clk_3_E_in ( p2489 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6530 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6531 ) , .clk_1_W_in ( clk_1_wires[106] ) , .clk_1_E_in ( SYNOPSYS_UNCONNECTED_6532 ) , .clk_1_N_out ( clk_1_wires[110] ) , .clk_1_S_out ( clk_1_wires[111] ) , - .clk_2_E_in ( p1559 ) , .clk_2_W_in ( p1628 ) , + .clk_2_E_in ( p2846 ) , .clk_2_W_in ( p2677 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6533 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6534 ) , .clk_3_W_in ( p1341 ) , - .clk_3_E_in ( p549 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6535 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6534 ) , .clk_3_W_in ( p2848 ) , + .clk_3_E_in ( p2726 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6535 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6536 ) ) ; cbx_1__1_ cbx_6__8_ ( .pReset ( { SYNOPSYS_UNCONNECTED_6537 } ) , @@ -124536,7 +129075,7 @@ cbx_1__1_ cbx_6__8_ ( .bottom_grid_pin_13_ ( cbx_1__1__62_bottom_grid_pin_13_ ) , .bottom_grid_pin_14_ ( cbx_1__1__62_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__62_bottom_grid_pin_15_ ) , - .ccff_tail ( cbx_1__1__62_ccff_tail ) , .SC_IN_TOP ( p1538 ) , + .ccff_tail ( cbx_1__1__62_ccff_tail ) , .SC_IN_TOP ( p2006 ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_6538 ) , .SC_IN_BOT ( scff_Wires[149] ) , .SC_OUT_TOP ( scff_Wires[150] ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[62] ) , @@ -124549,20 +129088,20 @@ cbx_1__1_ cbx_6__8_ ( .pReset_E_out ( SYNOPSYS_UNCONNECTED_6540 ) , .prog_clk_0_N_in ( prog_clk_0_wires[239] ) , .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6541 ) , - .prog_clk_1_W_in ( p2447 ) , .prog_clk_1_E_in ( p218 ) , + .prog_clk_1_W_in ( p1407 ) , .prog_clk_1_E_in ( p552 ) , .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_6542 ) , .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_6543 ) , - .prog_clk_2_E_in ( p1943 ) , .prog_clk_2_W_in ( p2371 ) , + .prog_clk_2_E_in ( p3329 ) , .prog_clk_2_W_in ( p2700 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6544 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6545 ) , - .prog_clk_3_W_in ( p1619 ) , .prog_clk_3_E_in ( p1041 ) , + .prog_clk_3_W_in ( p2777 ) , .prog_clk_3_E_in ( p3288 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6546 ) , - .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6547 ) , .clk_1_W_in ( p994 ) , - .clk_1_E_in ( p624 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_6548 ) , - .clk_1_S_out ( SYNOPSYS_UNCONNECTED_6549 ) , .clk_2_E_in ( p1943 ) , - .clk_2_W_in ( p2738 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6550 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6551 ) , .clk_3_W_in ( p2781 ) , - .clk_3_E_in ( p1722 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6552 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6547 ) , .clk_1_W_in ( p1550 ) , + .clk_1_E_in ( p697 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_6548 ) , + .clk_1_S_out ( SYNOPSYS_UNCONNECTED_6549 ) , .clk_2_E_in ( p1588 ) , + .clk_2_W_in ( p3185 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6550 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6551 ) , .clk_3_W_in ( p3237 ) , + .clk_3_E_in ( p929 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6552 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6553 ) ) ; cbx_1__1_ cbx_6__9_ ( .pReset ( { SYNOPSYS_UNCONNECTED_6554 } ) , @@ -124587,7 +129126,7 @@ cbx_1__1_ cbx_6__9_ ( .bottom_grid_pin_13_ ( cbx_1__1__63_bottom_grid_pin_13_ ) , .bottom_grid_pin_14_ ( cbx_1__1__63_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__63_bottom_grid_pin_15_ ) , - .ccff_tail ( cbx_1__1__63_ccff_tail ) , .SC_IN_TOP ( p2199 ) , + .ccff_tail ( cbx_1__1__63_ccff_tail ) , .SC_IN_TOP ( p1321 ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_6555 ) , .SC_IN_BOT ( scff_Wires[151] ) , .SC_OUT_TOP ( scff_Wires[152] ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[63] ) , @@ -124603,20 +129142,20 @@ cbx_1__1_ cbx_6__9_ ( .prog_clk_1_W_in ( prog_clk_1_wires[113] ) , .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_6559 ) , .prog_clk_1_N_out ( prog_clk_1_wires[117] ) , - .prog_clk_1_S_out ( prog_clk_1_wires[118] ) , .prog_clk_2_E_in ( p2155 ) , - .prog_clk_2_W_in ( p430 ) , + .prog_clk_1_S_out ( prog_clk_1_wires[118] ) , .prog_clk_2_E_in ( p2641 ) , + .prog_clk_2_W_in ( p2717 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6560 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6561 ) , - .prog_clk_3_W_in ( p3312 ) , .prog_clk_3_E_in ( p2078 ) , + .prog_clk_3_W_in ( p2851 ) , .prog_clk_3_E_in ( p2423 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6562 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6563 ) , .clk_1_W_in ( clk_1_wires[113] ) , .clk_1_E_in ( SYNOPSYS_UNCONNECTED_6564 ) , .clk_1_N_out ( clk_1_wires[117] ) , .clk_1_S_out ( clk_1_wires[118] ) , - .clk_2_E_in ( p2155 ) , .clk_2_W_in ( p3280 ) , + .clk_2_E_in ( p2229 ) , .clk_2_W_in ( p3443 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6565 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6566 ) , .clk_3_W_in ( p2251 ) , - .clk_3_E_in ( p2059 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6567 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6566 ) , .clk_3_W_in ( p3459 ) , + .clk_3_E_in ( p2176 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6567 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6568 ) ) ; cbx_1__1_ cbx_6__10_ ( .pReset ( { SYNOPSYS_UNCONNECTED_6569 } ) , @@ -124641,7 +129180,7 @@ cbx_1__1_ cbx_6__10_ ( .bottom_grid_pin_13_ ( cbx_1__1__64_bottom_grid_pin_13_ ) , .bottom_grid_pin_14_ ( cbx_1__1__64_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__64_bottom_grid_pin_15_ ) , - .ccff_tail ( cbx_1__1__64_ccff_tail ) , .SC_IN_TOP ( p2219 ) , + .ccff_tail ( cbx_1__1__64_ccff_tail ) , .SC_IN_TOP ( p1380 ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_6570 ) , .SC_IN_BOT ( scff_Wires[153] ) , .SC_OUT_TOP ( scff_Wires[154] ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[64] ) , @@ -124654,20 +129193,20 @@ cbx_1__1_ cbx_6__10_ ( .pReset_E_out ( SYNOPSYS_UNCONNECTED_6572 ) , .prog_clk_0_N_in ( prog_clk_0_wires[245] ) , .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6573 ) , - .prog_clk_1_W_in ( p1815 ) , .prog_clk_1_E_in ( p119 ) , + .prog_clk_1_W_in ( p1530 ) , .prog_clk_1_E_in ( p124 ) , .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_6574 ) , .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_6575 ) , - .prog_clk_2_E_in ( p1405 ) , .prog_clk_2_W_in ( p1743 ) , + .prog_clk_2_E_in ( p2970 ) , .prog_clk_2_W_in ( p1790 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6576 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6577 ) , - .prog_clk_3_W_in ( p2629 ) , .prog_clk_3_E_in ( p2053 ) , + .prog_clk_3_W_in ( p1992 ) , .prog_clk_3_E_in ( p2924 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6578 ) , - .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6579 ) , .clk_1_W_in ( p1483 ) , - .clk_1_E_in ( p665 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_6580 ) , - .clk_1_S_out ( SYNOPSYS_UNCONNECTED_6581 ) , .clk_2_E_in ( p1405 ) , - .clk_2_W_in ( p2572 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6582 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6583 ) , .clk_3_W_in ( p2429 ) , - .clk_3_E_in ( p1021 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6584 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6579 ) , .clk_1_W_in ( p1940 ) , + .clk_1_E_in ( p222 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_6580 ) , + .clk_1_S_out ( SYNOPSYS_UNCONNECTED_6581 ) , .clk_2_E_in ( p1814 ) , + .clk_2_W_in ( p1719 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6582 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6583 ) , .clk_3_W_in ( p1970 ) , + .clk_3_E_in ( p1824 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6584 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6585 ) ) ; cbx_1__1_ cbx_6__11_ ( .pReset ( { SYNOPSYS_UNCONNECTED_6586 } ) , @@ -124692,7 +129231,7 @@ cbx_1__1_ cbx_6__11_ ( .bottom_grid_pin_13_ ( cbx_1__1__65_bottom_grid_pin_13_ ) , .bottom_grid_pin_14_ ( cbx_1__1__65_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__65_bottom_grid_pin_15_ ) , - .ccff_tail ( cbx_1__1__65_ccff_tail ) , .SC_IN_TOP ( p2171 ) , + .ccff_tail ( cbx_1__1__65_ccff_tail ) , .SC_IN_TOP ( p2373 ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_6587 ) , .SC_IN_BOT ( scff_Wires[155] ) , .SC_OUT_TOP ( scff_Wires[156] ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[65] ) , @@ -124708,20 +129247,20 @@ cbx_1__1_ cbx_6__11_ ( .prog_clk_1_W_in ( prog_clk_1_wires[120] ) , .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_6591 ) , .prog_clk_1_N_out ( prog_clk_1_wires[124] ) , - .prog_clk_1_S_out ( prog_clk_1_wires[125] ) , .prog_clk_2_E_in ( p2701 ) , - .prog_clk_2_W_in ( p693 ) , + .prog_clk_1_S_out ( prog_clk_1_wires[125] ) , .prog_clk_2_E_in ( p3147 ) , + .prog_clk_2_W_in ( p3297 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6592 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6593 ) , - .prog_clk_3_W_in ( p3104 ) , .prog_clk_3_E_in ( p2014 ) , + .prog_clk_3_W_in ( p3357 ) , .prog_clk_3_E_in ( p3060 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6594 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6595 ) , .clk_1_W_in ( clk_1_wires[120] ) , .clk_1_E_in ( SYNOPSYS_UNCONNECTED_6596 ) , .clk_1_N_out ( clk_1_wires[124] ) , .clk_1_S_out ( clk_1_wires[125] ) , - .clk_2_E_in ( p2701 ) , .clk_2_W_in ( p3042 ) , + .clk_2_E_in ( p3152 ) , .clk_2_W_in ( p2479 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6597 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6598 ) , .clk_3_W_in ( p2618 ) , - .clk_3_E_in ( p2567 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6599 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6598 ) , .clk_3_W_in ( p2527 ) , + .clk_3_E_in ( p3099 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6599 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6600 ) ) ; cbx_1__1_ cbx_7__1_ ( .pReset ( { SYNOPSYS_UNCONNECTED_6601 } ) , @@ -124747,7 +129286,7 @@ cbx_1__1_ cbx_7__1_ ( .bottom_grid_pin_14_ ( cbx_1__1__66_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__66_bottom_grid_pin_15_ ) , .ccff_tail ( cbx_1__1__66_ccff_tail ) , .SC_IN_TOP ( scff_Wires[181] ) , - .SC_OUT_BOT ( scff_Wires[182] ) , .SC_IN_BOT ( p2222 ) , + .SC_OUT_BOT ( scff_Wires[182] ) , .SC_IN_BOT ( p1595 ) , .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_6602 ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[66] ) , .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[66] ) , @@ -124762,19 +129301,19 @@ cbx_1__1_ cbx_7__1_ ( .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_6606 ) , .prog_clk_1_E_in ( prog_clk_1_wires[128] ) , .prog_clk_1_N_out ( prog_clk_1_wires[129] ) , - .prog_clk_1_S_out ( prog_clk_1_wires[130] ) , .prog_clk_2_E_in ( p1543 ) , - .prog_clk_2_W_in ( p1051 ) , + .prog_clk_1_S_out ( prog_clk_1_wires[130] ) , .prog_clk_2_E_in ( p3142 ) , + .prog_clk_2_W_in ( p3545 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6607 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6608 ) , - .prog_clk_3_W_in ( p3399 ) , .prog_clk_3_E_in ( p585 ) , + .prog_clk_3_W_in ( p3558 ) , .prog_clk_3_E_in ( p3092 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6609 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6610 ) , .clk_1_W_in ( SYNOPSYS_UNCONNECTED_6611 ) , .clk_1_E_in ( clk_1_wires[128] ) , .clk_1_N_out ( clk_1_wires[129] ) , - .clk_1_S_out ( clk_1_wires[130] ) , .clk_2_E_in ( p1543 ) , - .clk_2_W_in ( p3386 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6612 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6613 ) , .clk_3_W_in ( p3076 ) , - .clk_3_E_in ( p27 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6614 ) , + .clk_1_S_out ( clk_1_wires[130] ) , .clk_2_E_in ( p2293 ) , + .clk_2_W_in ( p2470 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6612 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6613 ) , .clk_3_W_in ( p2519 ) , + .clk_3_E_in ( p2078 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6614 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6615 ) ) ; cbx_1__1_ cbx_7__2_ ( .pReset ( { SYNOPSYS_UNCONNECTED_6616 } ) , @@ -124800,7 +129339,7 @@ cbx_1__1_ cbx_7__2_ ( .bottom_grid_pin_14_ ( cbx_1__1__67_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__67_bottom_grid_pin_15_ ) , .ccff_tail ( cbx_1__1__67_ccff_tail ) , .SC_IN_TOP ( scff_Wires[179] ) , - .SC_OUT_BOT ( scff_Wires[180] ) , .SC_IN_BOT ( p2129 ) , + .SC_OUT_BOT ( scff_Wires[180] ) , .SC_IN_BOT ( p2203 ) , .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_6617 ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[67] ) , .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[67] ) , @@ -124812,20 +129351,20 @@ cbx_1__1_ cbx_7__2_ ( .pReset_S_out ( pResetWires[137] ) , .pReset_E_out ( pResetWires[136] ) , .prog_clk_0_N_in ( prog_clk_0_wires[259] ) , .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6620 ) , - .prog_clk_1_W_in ( p1243 ) , .prog_clk_1_E_in ( p1621 ) , + .prog_clk_1_W_in ( p1440 ) , .prog_clk_1_E_in ( p2080 ) , .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_6621 ) , .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_6622 ) , - .prog_clk_2_E_in ( p2454 ) , .prog_clk_2_W_in ( p1157 ) , + .prog_clk_2_E_in ( p2530 ) , .prog_clk_2_W_in ( p3071 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6623 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6624 ) , - .prog_clk_3_W_in ( p2697 ) , .prog_clk_3_E_in ( p134 ) , + .prog_clk_3_W_in ( p3138 ) , .prog_clk_3_E_in ( p2481 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6625 ) , - .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6626 ) , .clk_1_W_in ( p1609 ) , - .clk_1_E_in ( p2000 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_6627 ) , - .clk_1_S_out ( SYNOPSYS_UNCONNECTED_6628 ) , .clk_2_E_in ( p2454 ) , - .clk_2_W_in ( p2742 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6629 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6630 ) , .clk_3_W_in ( p2862 ) , - .clk_3_E_in ( p2271 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6631 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6626 ) , .clk_1_W_in ( p1653 ) , + .clk_1_E_in ( p148 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_6627 ) , + .clk_1_S_out ( SYNOPSYS_UNCONNECTED_6628 ) , .clk_2_E_in ( p2854 ) , + .clk_2_W_in ( p2873 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6629 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6630 ) , .clk_3_W_in ( p2984 ) , + .clk_3_E_in ( p2681 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6631 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6632 ) ) ; cbx_1__1_ cbx_7__3_ ( .pReset ( { SYNOPSYS_UNCONNECTED_6633 } ) , @@ -124851,7 +129390,7 @@ cbx_1__1_ cbx_7__3_ ( .bottom_grid_pin_14_ ( cbx_1__1__68_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__68_bottom_grid_pin_15_ ) , .ccff_tail ( cbx_1__1__68_ccff_tail ) , .SC_IN_TOP ( scff_Wires[177] ) , - .SC_OUT_BOT ( scff_Wires[178] ) , .SC_IN_BOT ( p1261 ) , + .SC_OUT_BOT ( scff_Wires[178] ) , .SC_IN_BOT ( p1207 ) , .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_6634 ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[68] ) , .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[68] ) , @@ -124866,19 +129405,19 @@ cbx_1__1_ cbx_7__3_ ( .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_6638 ) , .prog_clk_1_E_in ( prog_clk_1_wires[135] ) , .prog_clk_1_N_out ( prog_clk_1_wires[136] ) , - .prog_clk_1_S_out ( prog_clk_1_wires[137] ) , .prog_clk_2_E_in ( p2218 ) , - .prog_clk_2_W_in ( p564 ) , + .prog_clk_1_S_out ( prog_clk_1_wires[137] ) , .prog_clk_2_E_in ( p2770 ) , + .prog_clk_2_W_in ( p3291 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6639 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6640 ) , - .prog_clk_3_W_in ( p3166 ) , .prog_clk_3_E_in ( p1171 ) , + .prog_clk_3_W_in ( p3335 ) , .prog_clk_3_E_in ( p2706 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6641 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6642 ) , .clk_1_W_in ( SYNOPSYS_UNCONNECTED_6643 ) , .clk_1_E_in ( clk_1_wires[135] ) , .clk_1_N_out ( clk_1_wires[136] ) , - .clk_1_S_out ( clk_1_wires[137] ) , .clk_2_E_in ( p2218 ) , - .clk_2_W_in ( p3142 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6644 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6645 ) , .clk_3_W_in ( p2973 ) , - .clk_3_E_in ( p2079 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6646 ) , + .clk_1_S_out ( clk_1_wires[137] ) , .clk_2_E_in ( p2294 ) , + .clk_2_W_in ( p2456 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6644 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6645 ) , .clk_3_W_in ( p2491 ) , + .clk_3_E_in ( p2096 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6646 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6647 ) ) ; cbx_1__1_ cbx_7__4_ ( .pReset ( { SYNOPSYS_UNCONNECTED_6648 } ) , @@ -124904,7 +129443,7 @@ cbx_1__1_ cbx_7__4_ ( .bottom_grid_pin_14_ ( cbx_1__1__69_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__69_bottom_grid_pin_15_ ) , .ccff_tail ( cbx_1__1__69_ccff_tail ) , .SC_IN_TOP ( scff_Wires[175] ) , - .SC_OUT_BOT ( scff_Wires[176] ) , .SC_IN_BOT ( p1814 ) , + .SC_OUT_BOT ( scff_Wires[176] ) , .SC_IN_BOT ( p1614 ) , .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_6649 ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[69] ) , .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[69] ) , @@ -124916,20 +129455,20 @@ cbx_1__1_ cbx_7__4_ ( .pReset_S_out ( pResetWires[235] ) , .pReset_E_out ( pResetWires[234] ) , .prog_clk_0_N_in ( prog_clk_0_wires[265] ) , .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6652 ) , - .prog_clk_1_W_in ( p2159 ) , .prog_clk_1_E_in ( p1709 ) , + .prog_clk_1_W_in ( p1571 ) , .prog_clk_1_E_in ( p425 ) , .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_6653 ) , .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_6654 ) , - .prog_clk_2_E_in ( p2245 ) , .prog_clk_2_W_in ( p2075 ) , + .prog_clk_2_E_in ( p3229 ) , .prog_clk_2_W_in ( p3439 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6655 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6656 ) , - .prog_clk_3_W_in ( p3253 ) , .prog_clk_3_E_in ( p1178 ) , + .prog_clk_3_W_in ( p3462 ) , .prog_clk_3_E_in ( p3205 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6657 ) , - .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6658 ) , .clk_1_W_in ( p1540 ) , - .clk_1_E_in ( p1700 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_6659 ) , - .clk_1_S_out ( SYNOPSYS_UNCONNECTED_6660 ) , .clk_2_E_in ( p2216 ) , - .clk_2_W_in ( p3233 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6661 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6662 ) , .clk_3_W_in ( p2243 ) , - .clk_3_E_in ( p2027 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6663 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6658 ) , .clk_1_W_in ( p1285 ) , + .clk_1_E_in ( p2066 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_6659 ) , + .clk_1_S_out ( SYNOPSYS_UNCONNECTED_6660 ) , .clk_2_E_in ( p2508 ) , + .clk_2_W_in ( p2874 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6661 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6662 ) , .clk_3_W_in ( p2971 ) , + .clk_3_E_in ( p2375 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6663 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6664 ) ) ; cbx_1__1_ cbx_7__5_ ( .pReset ( { SYNOPSYS_UNCONNECTED_6665 } ) , @@ -124955,7 +129494,7 @@ cbx_1__1_ cbx_7__5_ ( .bottom_grid_pin_14_ ( cbx_1__1__70_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__70_bottom_grid_pin_15_ ) , .ccff_tail ( cbx_1__1__70_ccff_tail ) , .SC_IN_TOP ( scff_Wires[173] ) , - .SC_OUT_BOT ( scff_Wires[174] ) , .SC_IN_BOT ( p1854 ) , + .SC_OUT_BOT ( scff_Wires[174] ) , .SC_IN_BOT ( p1897 ) , .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_6666 ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[70] ) , .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[70] ) , @@ -124970,19 +129509,19 @@ cbx_1__1_ cbx_7__5_ ( .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_6670 ) , .prog_clk_1_E_in ( prog_clk_1_wires[142] ) , .prog_clk_1_N_out ( prog_clk_1_wires[143] ) , - .prog_clk_1_S_out ( prog_clk_1_wires[144] ) , .prog_clk_2_E_in ( p1823 ) , - .prog_clk_2_W_in ( p194 ) , + .prog_clk_1_S_out ( prog_clk_1_wires[144] ) , .prog_clk_2_E_in ( p2991 ) , + .prog_clk_2_W_in ( p1745 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6671 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6672 ) , - .prog_clk_3_W_in ( p3328 ) , .prog_clk_3_E_in ( p467 ) , + .prog_clk_3_W_in ( p1847 ) , .prog_clk_3_E_in ( p2858 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6673 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6674 ) , .clk_1_W_in ( SYNOPSYS_UNCONNECTED_6675 ) , .clk_1_E_in ( clk_1_wires[142] ) , .clk_1_N_out ( clk_1_wires[143] ) , - .clk_1_S_out ( clk_1_wires[144] ) , .clk_2_E_in ( p1823 ) , - .clk_2_W_in ( p3298 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6676 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6677 ) , .clk_3_W_in ( p2790 ) , - .clk_3_E_in ( p1701 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6678 ) , + .clk_1_S_out ( clk_1_wires[144] ) , .clk_2_E_in ( p2536 ) , + .clk_2_W_in ( p3053 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6676 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6677 ) , .clk_3_W_in ( p3168 ) , + .clk_3_E_in ( p2453 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6678 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6679 ) ) ; cbx_1__1_ cbx_7__6_ ( .pReset ( { SYNOPSYS_UNCONNECTED_6680 } ) , @@ -125008,7 +129547,7 @@ cbx_1__1_ cbx_7__6_ ( .bottom_grid_pin_14_ ( cbx_1__1__71_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__71_bottom_grid_pin_15_ ) , .ccff_tail ( cbx_1__1__71_ccff_tail ) , .SC_IN_TOP ( scff_Wires[171] ) , - .SC_OUT_BOT ( scff_Wires[172] ) , .SC_IN_BOT ( p1902 ) , + .SC_OUT_BOT ( scff_Wires[172] ) , .SC_IN_BOT ( p720 ) , .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_6681 ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[71] ) , .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[71] ) , @@ -125020,19 +129559,19 @@ cbx_1__1_ cbx_7__6_ ( .pReset_S_out ( pResetWires[333] ) , .pReset_E_out ( pResetWires[332] ) , .prog_clk_0_N_in ( prog_clk_0_wires[271] ) , .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6684 ) , - .prog_clk_1_W_in ( p2636 ) , .prog_clk_1_E_in ( p404 ) , + .prog_clk_1_W_in ( p1300 ) , .prog_clk_1_E_in ( p402 ) , .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_6685 ) , .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_6686 ) , - .prog_clk_2_E_in ( p1348 ) , .prog_clk_2_W_in ( p2585 ) , + .prog_clk_2_E_in ( p1422 ) , .prog_clk_2_W_in ( p2127 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6687 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6688 ) , .prog_clk_3_W_in ( prog_clk_3_wires[0] ) , .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_6689 ) , .prog_clk_3_E_out ( prog_clk_3_wires[1] ) , - .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6690 ) , .clk_1_W_in ( p1439 ) , - .clk_1_E_in ( p1678 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_6691 ) , - .clk_1_S_out ( SYNOPSYS_UNCONNECTED_6692 ) , .clk_2_E_in ( p1348 ) , - .clk_2_W_in ( p329 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6693 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6690 ) , .clk_1_W_in ( p2358 ) , + .clk_1_E_in ( p199 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_6691 ) , + .clk_1_S_out ( SYNOPSYS_UNCONNECTED_6692 ) , .clk_2_E_in ( p1422 ) , + .clk_2_W_in ( p675 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6693 ) , .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6694 ) , .clk_3_W_in ( clk_3_wires[0] ) , .clk_3_E_in ( SYNOPSYS_UNCONNECTED_6695 ) , @@ -125062,7 +129601,7 @@ cbx_1__1_ cbx_7__7_ ( .bottom_grid_pin_14_ ( cbx_1__1__72_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__72_bottom_grid_pin_15_ ) , .ccff_tail ( cbx_1__1__72_ccff_tail ) , .SC_IN_TOP ( scff_Wires[169] ) , - .SC_OUT_BOT ( scff_Wires[170] ) , .SC_IN_BOT ( p1283 ) , + .SC_OUT_BOT ( scff_Wires[170] ) , .SC_IN_BOT ( p920 ) , .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_6698 ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[72] ) , .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[72] ) , @@ -125077,19 +129616,19 @@ cbx_1__1_ cbx_7__7_ ( .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_6702 ) , .prog_clk_1_E_in ( prog_clk_1_wires[149] ) , .prog_clk_1_N_out ( prog_clk_1_wires[150] ) , - .prog_clk_1_S_out ( prog_clk_1_wires[151] ) , .prog_clk_2_E_in ( p1522 ) , - .prog_clk_2_W_in ( p480 ) , + .prog_clk_1_S_out ( prog_clk_1_wires[151] ) , .prog_clk_2_E_in ( p2340 ) , + .prog_clk_2_W_in ( p2701 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6703 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6704 ) , - .prog_clk_3_W_in ( p3448 ) , .prog_clk_3_E_in ( p914 ) , + .prog_clk_3_W_in ( p2751 ) , .prog_clk_3_E_in ( p2125 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6705 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6706 ) , .clk_1_W_in ( SYNOPSYS_UNCONNECTED_6707 ) , .clk_1_E_in ( clk_1_wires[149] ) , .clk_1_N_out ( clk_1_wires[150] ) , - .clk_1_S_out ( clk_1_wires[151] ) , .clk_2_E_in ( p1522 ) , - .clk_2_W_in ( p3438 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6708 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6709 ) , .clk_3_W_in ( p2980 ) , - .clk_3_E_in ( p608 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6710 ) , + .clk_1_S_out ( clk_1_wires[151] ) , .clk_2_E_in ( p2309 ) , + .clk_2_W_in ( p2163 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6708 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6709 ) , .clk_3_W_in ( p2336 ) , + .clk_3_E_in ( p2140 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6710 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6711 ) ) ; cbx_1__1_ cbx_7__8_ ( .pReset ( { SYNOPSYS_UNCONNECTED_6712 } ) , @@ -125115,7 +129654,7 @@ cbx_1__1_ cbx_7__8_ ( .bottom_grid_pin_14_ ( cbx_1__1__73_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__73_bottom_grid_pin_15_ ) , .ccff_tail ( cbx_1__1__73_ccff_tail ) , .SC_IN_TOP ( scff_Wires[167] ) , - .SC_OUT_BOT ( scff_Wires[168] ) , .SC_IN_BOT ( p2198 ) , + .SC_OUT_BOT ( scff_Wires[168] ) , .SC_IN_BOT ( p2039 ) , .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_6713 ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[73] ) , .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[73] ) , @@ -125127,20 +129666,20 @@ cbx_1__1_ cbx_7__8_ ( .pReset_S_out ( pResetWires[431] ) , .pReset_E_out ( pResetWires[430] ) , .prog_clk_0_N_in ( prog_clk_0_wires[277] ) , .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6716 ) , - .prog_clk_1_W_in ( p2485 ) , .prog_clk_1_E_in ( p2051 ) , + .prog_clk_1_W_in ( p1394 ) , .prog_clk_1_E_in ( p1684 ) , .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_6717 ) , .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_6718 ) , - .prog_clk_2_E_in ( p2126 ) , .prog_clk_2_W_in ( p2361 ) , + .prog_clk_2_E_in ( p2976 ) , .prog_clk_2_W_in ( p2090 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6719 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6720 ) , - .prog_clk_3_W_in ( p3362 ) , .prog_clk_3_E_in ( p1244 ) , + .prog_clk_3_W_in ( p2194 ) , .prog_clk_3_E_in ( p2907 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6721 ) , - .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6722 ) , .clk_1_W_in ( p1513 ) , - .clk_1_E_in ( p1982 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_6723 ) , - .clk_1_S_out ( SYNOPSYS_UNCONNECTED_6724 ) , .clk_2_E_in ( p2126 ) , - .clk_2_W_in ( p3341 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6725 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6726 ) , .clk_3_W_in ( p2470 ) , - .clk_3_E_in ( p2007 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6727 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6722 ) , .clk_1_W_in ( p2350 ) , + .clk_1_E_in ( p406 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_6723 ) , + .clk_1_S_out ( SYNOPSYS_UNCONNECTED_6724 ) , .clk_2_E_in ( p2238 ) , + .clk_2_W_in ( p2438 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6725 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6726 ) , .clk_3_W_in ( p2589 ) , + .clk_3_E_in ( p2132 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6727 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6728 ) ) ; cbx_1__1_ cbx_7__9_ ( .pReset ( { SYNOPSYS_UNCONNECTED_6729 } ) , @@ -125166,7 +129705,7 @@ cbx_1__1_ cbx_7__9_ ( .bottom_grid_pin_14_ ( cbx_1__1__74_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__74_bottom_grid_pin_15_ ) , .ccff_tail ( cbx_1__1__74_ccff_tail ) , .SC_IN_TOP ( scff_Wires[165] ) , - .SC_OUT_BOT ( scff_Wires[166] ) , .SC_IN_BOT ( p1402 ) , + .SC_OUT_BOT ( scff_Wires[166] ) , .SC_IN_BOT ( p1579 ) , .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_6730 ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[74] ) , .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[74] ) , @@ -125181,19 +129720,19 @@ cbx_1__1_ cbx_7__9_ ( .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_6734 ) , .prog_clk_1_E_in ( prog_clk_1_wires[156] ) , .prog_clk_1_N_out ( prog_clk_1_wires[157] ) , - .prog_clk_1_S_out ( prog_clk_1_wires[158] ) , .prog_clk_2_E_in ( p1488 ) , - .prog_clk_2_W_in ( p1105 ) , + .prog_clk_1_S_out ( prog_clk_1_wires[158] ) , .prog_clk_2_E_in ( p3233 ) , + .prog_clk_2_W_in ( p3057 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6735 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6736 ) , - .prog_clk_3_W_in ( p3096 ) , .prog_clk_3_E_in ( p976 ) , + .prog_clk_3_W_in ( p3119 ) , .prog_clk_3_E_in ( p3213 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6737 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6738 ) , .clk_1_W_in ( SYNOPSYS_UNCONNECTED_6739 ) , .clk_1_E_in ( clk_1_wires[156] ) , .clk_1_N_out ( clk_1_wires[157] ) , - .clk_1_S_out ( clk_1_wires[158] ) , .clk_2_E_in ( p1488 ) , - .clk_2_W_in ( p3027 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6740 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6741 ) , .clk_3_W_in ( p3066 ) , - .clk_3_E_in ( p627 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6742 ) , + .clk_1_S_out ( clk_1_wires[158] ) , .clk_2_E_in ( p2214 ) , + .clk_2_W_in ( p2473 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6740 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6741 ) , .clk_3_W_in ( p2537 ) , + .clk_3_E_in ( p2158 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6742 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6743 ) ) ; cbx_1__1_ cbx_7__10_ ( .pReset ( { SYNOPSYS_UNCONNECTED_6744 } ) , @@ -125219,7 +129758,7 @@ cbx_1__1_ cbx_7__10_ ( .bottom_grid_pin_14_ ( cbx_1__1__75_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__75_bottom_grid_pin_15_ ) , .ccff_tail ( cbx_1__1__75_ccff_tail ) , .SC_IN_TOP ( scff_Wires[163] ) , - .SC_OUT_BOT ( scff_Wires[164] ) , .SC_IN_BOT ( p1227 ) , + .SC_OUT_BOT ( scff_Wires[164] ) , .SC_IN_BOT ( p1534 ) , .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_6745 ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[75] ) , .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[75] ) , @@ -125231,20 +129770,20 @@ cbx_1__1_ cbx_7__10_ ( .pReset_S_out ( pResetWires[529] ) , .pReset_E_out ( pResetWires[528] ) , .prog_clk_0_N_in ( prog_clk_0_wires[283] ) , .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6748 ) , - .prog_clk_1_W_in ( p2483 ) , .prog_clk_1_E_in ( p614 ) , + .prog_clk_1_W_in ( p1369 ) , .prog_clk_1_E_in ( p471 ) , .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_6749 ) , .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_6750 ) , - .prog_clk_2_E_in ( p1464 ) , .prog_clk_2_W_in ( p2315 ) , + .prog_clk_2_E_in ( p2988 ) , .prog_clk_2_W_in ( p3050 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6751 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6752 ) , - .prog_clk_3_W_in ( p2956 ) , .prog_clk_3_E_in ( p1172 ) , + .prog_clk_3_W_in ( p2052 ) , .prog_clk_3_E_in ( p2909 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6753 ) , - .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6754 ) , .clk_1_W_in ( p1798 ) , - .clk_1_E_in ( p160 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_6755 ) , - .clk_1_S_out ( SYNOPSYS_UNCONNECTED_6756 ) , .clk_2_E_in ( p1464 ) , - .clk_2_W_in ( p2885 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6757 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6758 ) , .clk_3_W_in ( p2399 ) , - .clk_3_E_in ( p185 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6759 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6754 ) , .clk_1_W_in ( p3100 ) , + .clk_1_E_in ( p563 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_6755 ) , + .clk_1_S_out ( SYNOPSYS_UNCONNECTED_6756 ) , .clk_2_E_in ( p2273 ) , + .clk_2_W_in ( p3214 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6757 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6758 ) , .clk_3_W_in ( p3236 ) , + .clk_3_E_in ( p2137 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6759 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6760 ) ) ; cbx_1__1_ cbx_7__11_ ( .pReset ( { SYNOPSYS_UNCONNECTED_6761 } ) , @@ -125270,7 +129809,7 @@ cbx_1__1_ cbx_7__11_ ( .bottom_grid_pin_14_ ( cbx_1__1__76_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__76_bottom_grid_pin_15_ ) , .ccff_tail ( cbx_1__1__76_ccff_tail ) , .SC_IN_TOP ( scff_Wires[161] ) , - .SC_OUT_BOT ( scff_Wires[162] ) , .SC_IN_BOT ( p1608 ) , + .SC_OUT_BOT ( scff_Wires[162] ) , .SC_IN_BOT ( p1183 ) , .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_6762 ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[76] ) , .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[76] ) , @@ -125285,19 +129824,19 @@ cbx_1__1_ cbx_7__11_ ( .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_6766 ) , .prog_clk_1_E_in ( prog_clk_1_wires[163] ) , .prog_clk_1_N_out ( prog_clk_1_wires[164] ) , - .prog_clk_1_S_out ( prog_clk_1_wires[165] ) , .prog_clk_2_E_in ( p2453 ) , - .prog_clk_2_W_in ( p1029 ) , + .prog_clk_1_S_out ( prog_clk_1_wires[165] ) , .prog_clk_2_E_in ( p2803 ) , + .prog_clk_2_W_in ( p3309 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6767 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6768 ) , - .prog_clk_3_W_in ( p3306 ) , .prog_clk_3_E_in ( p1158 ) , + .prog_clk_3_W_in ( p3326 ) , .prog_clk_3_E_in ( p2688 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6769 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6770 ) , .clk_1_W_in ( SYNOPSYS_UNCONNECTED_6771 ) , .clk_1_E_in ( clk_1_wires[163] ) , .clk_1_N_out ( clk_1_wires[164] ) , - .clk_1_S_out ( clk_1_wires[165] ) , .clk_2_E_in ( p2453 ) , - .clk_2_W_in ( p3278 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6772 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6773 ) , .clk_3_W_in ( p2616 ) , - .clk_3_E_in ( p2373 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6774 ) , + .clk_1_S_out ( clk_1_wires[165] ) , .clk_2_E_in ( p2342 ) , + .clk_2_W_in ( p2454 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6772 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6773 ) , .clk_3_W_in ( p2566 ) , + .clk_3_E_in ( p2187 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6774 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6775 ) ) ; cbx_1__1_ cbx_8__1_ ( .pReset ( { SYNOPSYS_UNCONNECTED_6776 } ) , @@ -125322,7 +129861,7 @@ cbx_1__1_ cbx_8__1_ ( .bottom_grid_pin_13_ ( cbx_1__1__77_bottom_grid_pin_13_ ) , .bottom_grid_pin_14_ ( cbx_1__1__77_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__77_bottom_grid_pin_15_ ) , - .ccff_tail ( cbx_1__1__77_ccff_tail ) , .SC_IN_TOP ( p1879 ) , + .ccff_tail ( cbx_1__1__77_ccff_tail ) , .SC_IN_TOP ( p1583 ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_6777 ) , .SC_IN_BOT ( scff_Wires[188] ) , .SC_OUT_TOP ( scff_Wires[189] ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[77] ) , @@ -125338,20 +129877,20 @@ cbx_1__1_ cbx_8__1_ ( .prog_clk_1_W_in ( prog_clk_1_wires[127] ) , .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_6781 ) , .prog_clk_1_N_out ( prog_clk_1_wires[131] ) , - .prog_clk_1_S_out ( prog_clk_1_wires[132] ) , .prog_clk_2_E_in ( p1424 ) , - .prog_clk_2_W_in ( p1230 ) , + .prog_clk_1_S_out ( prog_clk_1_wires[132] ) , .prog_clk_2_E_in ( p2964 ) , + .prog_clk_2_W_in ( p2183 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6782 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6783 ) , - .prog_clk_3_W_in ( p670 ) , .prog_clk_3_E_in ( p1667 ) , + .prog_clk_3_W_in ( p2232 ) , .prog_clk_3_E_in ( p2878 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6784 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6785 ) , .clk_1_W_in ( clk_1_wires[127] ) , .clk_1_E_in ( SYNOPSYS_UNCONNECTED_6786 ) , .clk_1_N_out ( clk_1_wires[131] ) , .clk_1_S_out ( clk_1_wires[132] ) , - .clk_2_E_in ( p1424 ) , .clk_2_W_in ( p2582 ) , + .clk_2_E_in ( p2778 ) , .clk_2_W_in ( p3303 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6787 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6788 ) , .clk_3_W_in ( p2678 ) , - .clk_3_E_in ( p193 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6789 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6788 ) , .clk_3_W_in ( p3330 ) , + .clk_3_E_in ( p2680 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6789 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6790 ) ) ; cbx_1__1_ cbx_8__2_ ( .pReset ( { SYNOPSYS_UNCONNECTED_6791 } ) , @@ -125376,7 +129915,7 @@ cbx_1__1_ cbx_8__2_ ( .bottom_grid_pin_13_ ( cbx_1__1__78_bottom_grid_pin_13_ ) , .bottom_grid_pin_14_ ( cbx_1__1__78_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__78_bottom_grid_pin_15_ ) , - .ccff_tail ( cbx_1__1__78_ccff_tail ) , .SC_IN_TOP ( p1928 ) , + .ccff_tail ( cbx_1__1__78_ccff_tail ) , .SC_IN_TOP ( p1517 ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_6792 ) , .SC_IN_BOT ( scff_Wires[190] ) , .SC_OUT_TOP ( scff_Wires[191] ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[78] ) , @@ -125389,23 +129928,23 @@ cbx_1__1_ cbx_8__2_ ( .pReset_S_out ( pResetWires[141] ) , .pReset_E_out ( pResetWires[140] ) , .prog_clk_0_N_in ( prog_clk_0_wires[297] ) , .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6795 ) , - .prog_clk_1_W_in ( p1121 ) , .prog_clk_1_E_in ( p2025 ) , + .prog_clk_1_W_in ( p1060 ) , .prog_clk_1_E_in ( p204 ) , .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_6796 ) , .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_6797 ) , .prog_clk_2_E_in ( prog_clk_2_wires[71] ) , .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_6798 ) , .prog_clk_2_W_out ( prog_clk_2_wires[72] ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6799 ) , - .prog_clk_3_W_in ( p1121 ) , .prog_clk_3_E_in ( p1679 ) , + .prog_clk_3_W_in ( p1562 ) , .prog_clk_3_E_in ( p936 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6800 ) , - .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6801 ) , .clk_1_W_in ( p1121 ) , - .clk_1_E_in ( p98 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_6802 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6801 ) , .clk_1_W_in ( p1452 ) , + .clk_1_E_in ( p1671 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_6802 ) , .clk_1_S_out ( SYNOPSYS_UNCONNECTED_6803 ) , .clk_2_E_in ( clk_2_wires[71] ) , .clk_2_W_in ( SYNOPSYS_UNCONNECTED_6804 ) , .clk_2_W_out ( clk_2_wires[72] ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6805 ) , .clk_3_W_in ( p2230 ) , - .clk_3_E_in ( p2022 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6806 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6805 ) , .clk_3_W_in ( p1562 ) , + .clk_3_E_in ( p1793 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6806 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6807 ) ) ; cbx_1__1_ cbx_8__3_ ( .pReset ( { SYNOPSYS_UNCONNECTED_6808 } ) , @@ -125430,7 +129969,7 @@ cbx_1__1_ cbx_8__3_ ( .bottom_grid_pin_13_ ( cbx_1__1__79_bottom_grid_pin_13_ ) , .bottom_grid_pin_14_ ( cbx_1__1__79_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__79_bottom_grid_pin_15_ ) , - .ccff_tail ( cbx_1__1__79_ccff_tail ) , .SC_IN_TOP ( p2378 ) , + .ccff_tail ( cbx_1__1__79_ccff_tail ) , .SC_IN_TOP ( p1922 ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_6809 ) , .SC_IN_BOT ( scff_Wires[192] ) , .SC_OUT_TOP ( scff_Wires[193] ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[79] ) , @@ -125446,20 +129985,20 @@ cbx_1__1_ cbx_8__3_ ( .prog_clk_1_W_in ( prog_clk_1_wires[134] ) , .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_6813 ) , .prog_clk_1_N_out ( prog_clk_1_wires[138] ) , - .prog_clk_1_S_out ( prog_clk_1_wires[139] ) , .prog_clk_2_E_in ( p1235 ) , - .prog_clk_2_W_in ( p648 ) , + .prog_clk_1_S_out ( prog_clk_1_wires[139] ) , .prog_clk_2_E_in ( p2514 ) , + .prog_clk_2_W_in ( p3207 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6814 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6815 ) , - .prog_clk_3_W_in ( p2705 ) , .prog_clk_3_E_in ( p2349 ) , + .prog_clk_3_W_in ( p3245 ) , .prog_clk_3_E_in ( p2486 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6816 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6817 ) , .clk_1_W_in ( clk_1_wires[134] ) , .clk_1_E_in ( SYNOPSYS_UNCONNECTED_6818 ) , .clk_1_N_out ( clk_1_wires[138] ) , .clk_1_S_out ( clk_1_wires[139] ) , - .clk_2_E_in ( p1235 ) , .clk_2_W_in ( p2578 ) , + .clk_2_E_in ( p2754 ) , .clk_2_W_in ( p2393 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6819 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6820 ) , .clk_3_W_in ( p2393 ) , - .clk_3_E_in ( p1237 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6821 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6820 ) , .clk_3_W_in ( p2565 ) , + .clk_3_E_in ( p2691 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6821 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6822 ) ) ; cbx_1__1_ cbx_8__4_ ( .pReset ( { SYNOPSYS_UNCONNECTED_6823 } ) , @@ -125484,7 +130023,7 @@ cbx_1__1_ cbx_8__4_ ( .bottom_grid_pin_13_ ( cbx_1__1__80_bottom_grid_pin_13_ ) , .bottom_grid_pin_14_ ( cbx_1__1__80_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__80_bottom_grid_pin_15_ ) , - .ccff_tail ( cbx_1__1__80_ccff_tail ) , .SC_IN_TOP ( p1551 ) , + .ccff_tail ( cbx_1__1__80_ccff_tail ) , .SC_IN_TOP ( p1893 ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_6824 ) , .SC_IN_BOT ( scff_Wires[194] ) , .SC_OUT_TOP ( scff_Wires[195] ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[80] ) , @@ -125497,23 +130036,23 @@ cbx_1__1_ cbx_8__4_ ( .pReset_S_out ( pResetWires[239] ) , .pReset_E_out ( pResetWires[238] ) , .prog_clk_0_N_in ( prog_clk_0_wires[303] ) , .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6827 ) , - .prog_clk_1_W_in ( p1920 ) , .prog_clk_1_E_in ( p685 ) , + .prog_clk_1_W_in ( p1453 ) , .prog_clk_1_E_in ( p295 ) , .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_6828 ) , .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_6829 ) , .prog_clk_2_E_in ( prog_clk_2_wires[80] ) , .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_6830 ) , .prog_clk_2_W_out ( prog_clk_2_wires[81] ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6831 ) , - .prog_clk_3_W_in ( p1801 ) , .prog_clk_3_E_in ( p1294 ) , + .prog_clk_3_W_in ( p1275 ) , .prog_clk_3_E_in ( p1739 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6832 ) , - .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6833 ) , .clk_1_W_in ( p1468 ) , - .clk_1_E_in ( p556 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_6834 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6833 ) , .clk_1_W_in ( p1169 ) , + .clk_1_E_in ( p631 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_6834 ) , .clk_1_S_out ( SYNOPSYS_UNCONNECTED_6835 ) , .clk_2_E_in ( clk_2_wires[80] ) , .clk_2_W_in ( SYNOPSYS_UNCONNECTED_6836 ) , .clk_2_W_out ( clk_2_wires[81] ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6837 ) , .clk_3_W_in ( p1801 ) , - .clk_3_E_in ( p358 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6838 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6837 ) , .clk_3_W_in ( p1275 ) , + .clk_3_E_in ( p1015 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6838 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6839 ) ) ; cbx_1__1_ cbx_8__5_ ( .pReset ( { SYNOPSYS_UNCONNECTED_6840 } ) , @@ -125538,7 +130077,7 @@ cbx_1__1_ cbx_8__5_ ( .bottom_grid_pin_13_ ( cbx_1__1__81_bottom_grid_pin_13_ ) , .bottom_grid_pin_14_ ( cbx_1__1__81_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__81_bottom_grid_pin_15_ ) , - .ccff_tail ( cbx_1__1__81_ccff_tail ) , .SC_IN_TOP ( p1898 ) , + .ccff_tail ( cbx_1__1__81_ccff_tail ) , .SC_IN_TOP ( p2368 ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_6841 ) , .SC_IN_BOT ( scff_Wires[196] ) , .SC_OUT_TOP ( scff_Wires[197] ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[81] ) , @@ -125554,20 +130093,20 @@ cbx_1__1_ cbx_8__5_ ( .prog_clk_1_W_in ( prog_clk_1_wires[141] ) , .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_6845 ) , .prog_clk_1_N_out ( prog_clk_1_wires[145] ) , - .prog_clk_1_S_out ( prog_clk_1_wires[146] ) , .prog_clk_2_E_in ( p1950 ) , - .prog_clk_2_W_in ( p521 ) , + .prog_clk_1_S_out ( prog_clk_1_wires[146] ) , .prog_clk_2_E_in ( p2962 ) , + .prog_clk_2_W_in ( p2191 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6846 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6847 ) , - .prog_clk_3_W_in ( p2610 ) , .prog_clk_3_E_in ( p1763 ) , + .prog_clk_3_W_in ( p2303 ) , .prog_clk_3_E_in ( p2897 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6848 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6849 ) , .clk_1_W_in ( clk_1_wires[141] ) , .clk_1_E_in ( SYNOPSYS_UNCONNECTED_6850 ) , .clk_1_N_out ( clk_1_wires[145] ) , .clk_1_S_out ( clk_1_wires[146] ) , - .clk_2_E_in ( p1950 ) , .clk_2_W_in ( p3149 ) , + .clk_2_E_in ( p1895 ) , .clk_2_W_in ( p2095 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6851 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6852 ) , .clk_3_W_in ( p3182 ) , - .clk_3_E_in ( p1662 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6853 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6852 ) , .clk_3_W_in ( p2276 ) , + .clk_3_E_in ( p1693 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6853 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6854 ) ) ; cbx_1__1_ cbx_8__6_ ( .pReset ( { SYNOPSYS_UNCONNECTED_6855 } ) , @@ -125592,7 +130131,7 @@ cbx_1__1_ cbx_8__6_ ( .bottom_grid_pin_13_ ( cbx_1__1__82_bottom_grid_pin_13_ ) , .bottom_grid_pin_14_ ( cbx_1__1__82_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__82_bottom_grid_pin_15_ ) , - .ccff_tail ( cbx_1__1__82_ccff_tail ) , .SC_IN_TOP ( p1592 ) , + .ccff_tail ( cbx_1__1__82_ccff_tail ) , .SC_IN_TOP ( p1514 ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_6856 ) , .SC_IN_BOT ( scff_Wires[198] ) , .SC_OUT_TOP ( scff_Wires[199] ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[82] ) , @@ -125605,19 +130144,19 @@ cbx_1__1_ cbx_8__6_ ( .pReset_S_out ( pResetWires[337] ) , .pReset_E_out ( pResetWires[336] ) , .prog_clk_0_N_in ( prog_clk_0_wires[309] ) , .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6859 ) , - .prog_clk_1_W_in ( p2414 ) , .prog_clk_1_E_in ( p466 ) , + .prog_clk_1_W_in ( p809 ) , .prog_clk_1_E_in ( p589 ) , .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_6860 ) , .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_6861 ) , - .prog_clk_2_E_in ( p1597 ) , .prog_clk_2_W_in ( p2323 ) , + .prog_clk_2_E_in ( p1414 ) , .prog_clk_2_W_in ( p2113 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6862 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6863 ) , .prog_clk_3_W_in ( prog_clk_3_wires[4] ) , .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_6864 ) , .prog_clk_3_E_out ( prog_clk_3_wires[5] ) , - .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6865 ) , .clk_1_W_in ( p1360 ) , - .clk_1_E_in ( p285 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_6866 ) , - .clk_1_S_out ( SYNOPSYS_UNCONNECTED_6867 ) , .clk_2_E_in ( p1597 ) , - .clk_2_W_in ( p1135 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6868 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6865 ) , .clk_1_W_in ( p2301 ) , + .clk_1_E_in ( p356 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_6866 ) , + .clk_1_S_out ( SYNOPSYS_UNCONNECTED_6867 ) , .clk_2_E_in ( p1414 ) , + .clk_2_W_in ( p798 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6868 ) , .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6869 ) , .clk_3_W_in ( clk_3_wires[4] ) , .clk_3_E_in ( SYNOPSYS_UNCONNECTED_6870 ) , @@ -125646,7 +130185,7 @@ cbx_1__1_ cbx_8__7_ ( .bottom_grid_pin_13_ ( cbx_1__1__83_bottom_grid_pin_13_ ) , .bottom_grid_pin_14_ ( cbx_1__1__83_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__83_bottom_grid_pin_15_ ) , - .ccff_tail ( cbx_1__1__83_ccff_tail ) , .SC_IN_TOP ( p2135 ) , + .ccff_tail ( cbx_1__1__83_ccff_tail ) , .SC_IN_TOP ( p1474 ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_6873 ) , .SC_IN_BOT ( scff_Wires[200] ) , .SC_OUT_TOP ( scff_Wires[201] ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[83] ) , @@ -125662,20 +130201,20 @@ cbx_1__1_ cbx_8__7_ ( .prog_clk_1_W_in ( prog_clk_1_wires[148] ) , .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_6877 ) , .prog_clk_1_N_out ( prog_clk_1_wires[152] ) , - .prog_clk_1_S_out ( prog_clk_1_wires[153] ) , .prog_clk_2_E_in ( p1830 ) , - .prog_clk_2_W_in ( p882 ) , + .prog_clk_1_S_out ( prog_clk_1_wires[153] ) , .prog_clk_2_E_in ( p1986 ) , + .prog_clk_2_W_in ( p3526 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6878 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6879 ) , - .prog_clk_3_W_in ( p3309 ) , .prog_clk_3_E_in ( p2033 ) , + .prog_clk_3_W_in ( p3536 ) , .prog_clk_3_E_in ( p1737 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6880 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6881 ) , .clk_1_W_in ( clk_1_wires[148] ) , .clk_1_E_in ( SYNOPSYS_UNCONNECTED_6882 ) , .clk_1_N_out ( clk_1_wires[152] ) , .clk_1_S_out ( clk_1_wires[153] ) , - .clk_2_E_in ( p1830 ) , .clk_2_W_in ( p3291 ) , + .clk_2_E_in ( p1979 ) , .clk_2_W_in ( p3544 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6883 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6884 ) , .clk_3_W_in ( p2987 ) , - .clk_3_E_in ( p1672 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6885 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6884 ) , .clk_3_W_in ( p3555 ) , + .clk_3_E_in ( p1752 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6885 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6886 ) ) ; cbx_1__1_ cbx_8__8_ ( .pReset ( { SYNOPSYS_UNCONNECTED_6887 } ) , @@ -125700,7 +130239,7 @@ cbx_1__1_ cbx_8__8_ ( .bottom_grid_pin_13_ ( cbx_1__1__84_bottom_grid_pin_13_ ) , .bottom_grid_pin_14_ ( cbx_1__1__84_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__84_bottom_grid_pin_15_ ) , - .ccff_tail ( cbx_1__1__84_ccff_tail ) , .SC_IN_TOP ( p2706 ) , + .ccff_tail ( cbx_1__1__84_ccff_tail ) , .SC_IN_TOP ( p1383 ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_6888 ) , .SC_IN_BOT ( scff_Wires[202] ) , .SC_OUT_TOP ( scff_Wires[203] ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[84] ) , @@ -125713,23 +130252,23 @@ cbx_1__1_ cbx_8__8_ ( .pReset_S_out ( pResetWires[435] ) , .pReset_E_out ( pResetWires[434] ) , .prog_clk_0_N_in ( prog_clk_0_wires[315] ) , .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6891 ) , - .prog_clk_1_W_in ( p962 ) , .prog_clk_1_E_in ( p675 ) , + .prog_clk_1_W_in ( p1633 ) , .prog_clk_1_E_in ( p384 ) , .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_6892 ) , .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_6893 ) , .prog_clk_2_E_in ( prog_clk_2_wires[93] ) , .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_6894 ) , .prog_clk_2_W_out ( prog_clk_2_wires[94] ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6895 ) , - .prog_clk_3_W_in ( p962 ) , .prog_clk_3_E_in ( p2539 ) , + .prog_clk_3_W_in ( p1361 ) , .prog_clk_3_E_in ( p948 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6896 ) , - .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6897 ) , .clk_1_W_in ( p1355 ) , - .clk_1_E_in ( p199 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_6898 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6897 ) , .clk_1_W_in ( p1361 ) , + .clk_1_E_in ( p772 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_6898 ) , .clk_1_S_out ( SYNOPSYS_UNCONNECTED_6899 ) , .clk_2_E_in ( clk_2_wires[93] ) , .clk_2_W_in ( SYNOPSYS_UNCONNECTED_6900 ) , .clk_2_W_out ( clk_2_wires[94] ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6901 ) , .clk_3_W_in ( p962 ) , - .clk_3_E_in ( p539 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6902 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6901 ) , .clk_3_W_in ( p1361 ) , + .clk_3_E_in ( p504 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6902 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6903 ) ) ; cbx_1__1_ cbx_8__9_ ( .pReset ( { SYNOPSYS_UNCONNECTED_6904 } ) , @@ -125754,7 +130293,7 @@ cbx_1__1_ cbx_8__9_ ( .bottom_grid_pin_13_ ( cbx_1__1__85_bottom_grid_pin_13_ ) , .bottom_grid_pin_14_ ( cbx_1__1__85_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__85_bottom_grid_pin_15_ ) , - .ccff_tail ( cbx_1__1__85_ccff_tail ) , .SC_IN_TOP ( p1589 ) , + .ccff_tail ( cbx_1__1__85_ccff_tail ) , .SC_IN_TOP ( p2360 ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_6905 ) , .SC_IN_BOT ( scff_Wires[204] ) , .SC_OUT_TOP ( scff_Wires[205] ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[85] ) , @@ -125770,20 +130309,20 @@ cbx_1__1_ cbx_8__9_ ( .prog_clk_1_W_in ( prog_clk_1_wires[155] ) , .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_6909 ) , .prog_clk_1_N_out ( prog_clk_1_wires[159] ) , - .prog_clk_1_S_out ( prog_clk_1_wires[160] ) , .prog_clk_2_E_in ( p1780 ) , - .prog_clk_2_W_in ( p1056 ) , + .prog_clk_1_S_out ( prog_clk_1_wires[160] ) , .prog_clk_2_E_in ( p2274 ) , + .prog_clk_2_W_in ( p2648 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6910 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6911 ) , - .prog_clk_3_W_in ( p3254 ) , .prog_clk_3_E_in ( p655 ) , + .prog_clk_3_W_in ( p2753 ) , .prog_clk_3_E_in ( p2161 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6912 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6913 ) , .clk_1_W_in ( clk_1_wires[155] ) , .clk_1_E_in ( SYNOPSYS_UNCONNECTED_6914 ) , .clk_1_N_out ( clk_1_wires[159] ) , .clk_1_S_out ( clk_1_wires[160] ) , - .clk_2_E_in ( p1780 ) , .clk_2_W_in ( p3216 ) , + .clk_2_E_in ( p2553 ) , .clk_2_W_in ( p2149 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6915 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6916 ) , .clk_3_W_in ( p1905 ) , - .clk_3_E_in ( p1710 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6917 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6916 ) , .clk_3_W_in ( p2367 ) , + .clk_3_E_in ( p2380 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6917 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6918 ) ) ; cbx_1__1_ cbx_8__10_ ( .pReset ( { SYNOPSYS_UNCONNECTED_6919 } ) , @@ -125808,7 +130347,7 @@ cbx_1__1_ cbx_8__10_ ( .bottom_grid_pin_13_ ( cbx_1__1__86_bottom_grid_pin_13_ ) , .bottom_grid_pin_14_ ( cbx_1__1__86_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__86_bottom_grid_pin_15_ ) , - .ccff_tail ( cbx_1__1__86_ccff_tail ) , .SC_IN_TOP ( p2165 ) , + .ccff_tail ( cbx_1__1__86_ccff_tail ) , .SC_IN_TOP ( p2225 ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_6920 ) , .SC_IN_BOT ( scff_Wires[206] ) , .SC_OUT_TOP ( scff_Wires[207] ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[86] ) , @@ -125821,23 +130360,23 @@ cbx_1__1_ cbx_8__10_ ( .pReset_S_out ( pResetWires[533] ) , .pReset_E_out ( pResetWires[532] ) , .prog_clk_0_N_in ( prog_clk_0_wires[321] ) , .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6923 ) , - .prog_clk_1_W_in ( p1804 ) , .prog_clk_1_E_in ( p2058 ) , + .prog_clk_1_W_in ( p1347 ) , .prog_clk_1_E_in ( p702 ) , .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_6924 ) , .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_6925 ) , .prog_clk_2_E_in ( prog_clk_2_wires[106] ) , .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_6926 ) , .prog_clk_2_W_out ( prog_clk_2_wires[107] ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6927 ) , - .prog_clk_3_W_in ( p1959 ) , .prog_clk_3_E_in ( p2081 ) , + .prog_clk_3_W_in ( p1600 ) , .prog_clk_3_E_in ( p2131 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6928 ) , - .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6929 ) , .clk_1_W_in ( p1410 ) , - .clk_1_E_in ( p599 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_6930 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6929 ) , .clk_1_W_in ( p1324 ) , + .clk_1_E_in ( p100 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_6930 ) , .clk_1_S_out ( SYNOPSYS_UNCONNECTED_6931 ) , .clk_2_E_in ( clk_2_wires[106] ) , .clk_2_W_in ( SYNOPSYS_UNCONNECTED_6932 ) , .clk_2_W_out ( clk_2_wires[107] ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6933 ) , .clk_3_W_in ( p1959 ) , - .clk_3_E_in ( p1964 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6934 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6933 ) , .clk_3_W_in ( p1600 ) , + .clk_3_E_in ( p546 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6934 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6935 ) ) ; cbx_1__1_ cbx_8__11_ ( .pReset ( { SYNOPSYS_UNCONNECTED_6936 } ) , @@ -125862,7 +130401,7 @@ cbx_1__1_ cbx_8__11_ ( .bottom_grid_pin_13_ ( cbx_1__1__87_bottom_grid_pin_13_ ) , .bottom_grid_pin_14_ ( cbx_1__1__87_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__87_bottom_grid_pin_15_ ) , - .ccff_tail ( cbx_1__1__87_ccff_tail ) , .SC_IN_TOP ( p2491 ) , + .ccff_tail ( cbx_1__1__87_ccff_tail ) , .SC_IN_TOP ( p1876 ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_6937 ) , .SC_IN_BOT ( scff_Wires[208] ) , .SC_OUT_TOP ( scff_Wires[209] ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[87] ) , @@ -125878,20 +130417,20 @@ cbx_1__1_ cbx_8__11_ ( .prog_clk_1_W_in ( prog_clk_1_wires[162] ) , .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_6941 ) , .prog_clk_1_N_out ( prog_clk_1_wires[166] ) , - .prog_clk_1_S_out ( prog_clk_1_wires[167] ) , .prog_clk_2_E_in ( p2402 ) , - .prog_clk_2_W_in ( p242 ) , + .prog_clk_1_S_out ( prog_clk_1_wires[167] ) , .prog_clk_2_E_in ( p3121 ) , + .prog_clk_2_W_in ( p3484 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6942 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6943 ) , - .prog_clk_3_W_in ( p2482 ) , .prog_clk_3_E_in ( p2364 ) , + .prog_clk_3_W_in ( p3496 ) , .prog_clk_3_E_in ( p3079 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6944 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6945 ) , .clk_1_W_in ( clk_1_wires[162] ) , .clk_1_E_in ( SYNOPSYS_UNCONNECTED_6946 ) , .clk_1_N_out ( clk_1_wires[166] ) , .clk_1_S_out ( clk_1_wires[167] ) , - .clk_2_E_in ( p2402 ) , .clk_2_W_in ( p2339 ) , + .clk_2_E_in ( p2755 ) , .clk_2_W_in ( p2433 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6947 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6948 ) , .clk_3_W_in ( p2506 ) , - .clk_3_E_in ( p2270 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6949 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6948 ) , .clk_3_W_in ( p2568 ) , + .clk_3_E_in ( p2692 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6949 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6950 ) ) ; cbx_1__1_ cbx_9__1_ ( .pReset ( { SYNOPSYS_UNCONNECTED_6951 } ) , @@ -125917,7 +130456,7 @@ cbx_1__1_ cbx_9__1_ ( .bottom_grid_pin_14_ ( cbx_1__1__88_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__88_bottom_grid_pin_15_ ) , .ccff_tail ( cbx_1__1__88_ccff_tail ) , .SC_IN_TOP ( scff_Wires[234] ) , - .SC_OUT_BOT ( scff_Wires[235] ) , .SC_IN_BOT ( p946 ) , + .SC_OUT_BOT ( scff_Wires[235] ) , .SC_IN_BOT ( p1237 ) , .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_6952 ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[88] ) , .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[88] ) , @@ -125932,19 +130471,19 @@ cbx_1__1_ cbx_9__1_ ( .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_6956 ) , .prog_clk_1_E_in ( prog_clk_1_wires[170] ) , .prog_clk_1_N_out ( prog_clk_1_wires[171] ) , - .prog_clk_1_S_out ( prog_clk_1_wires[172] ) , .prog_clk_2_E_in ( p1816 ) , - .prog_clk_2_W_in ( p643 ) , + .prog_clk_1_S_out ( prog_clk_1_wires[172] ) , .prog_clk_2_E_in ( p3009 ) , + .prog_clk_2_W_in ( p3037 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6957 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6958 ) , - .prog_clk_3_W_in ( p2673 ) , .prog_clk_3_E_in ( p427 ) , + .prog_clk_3_W_in ( p3150 ) , .prog_clk_3_E_in ( p2862 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6959 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6960 ) , .clk_1_W_in ( SYNOPSYS_UNCONNECTED_6961 ) , .clk_1_E_in ( clk_1_wires[170] ) , .clk_1_N_out ( clk_1_wires[171] ) , - .clk_1_S_out ( clk_1_wires[172] ) , .clk_2_E_in ( p1816 ) , - .clk_2_W_in ( p2761 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6962 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6963 ) , .clk_3_W_in ( p2787 ) , - .clk_3_E_in ( p1706 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6964 ) , + .clk_1_S_out ( clk_1_wires[172] ) , .clk_2_E_in ( p2835 ) , + .clk_2_W_in ( p3381 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6962 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6963 ) , .clk_3_W_in ( p3423 ) , + .clk_3_E_in ( p2713 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6964 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6965 ) ) ; cbx_1__1_ cbx_9__2_ ( .pReset ( { SYNOPSYS_UNCONNECTED_6966 } ) , @@ -125970,7 +130509,7 @@ cbx_1__1_ cbx_9__2_ ( .bottom_grid_pin_14_ ( cbx_1__1__89_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__89_bottom_grid_pin_15_ ) , .ccff_tail ( cbx_1__1__89_ccff_tail ) , .SC_IN_TOP ( scff_Wires[232] ) , - .SC_OUT_BOT ( scff_Wires[233] ) , .SC_IN_BOT ( p1832 ) , + .SC_OUT_BOT ( scff_Wires[233] ) , .SC_IN_BOT ( p1536 ) , .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_6967 ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[89] ) , .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[89] ) , @@ -125982,23 +130521,23 @@ cbx_1__1_ cbx_9__2_ ( .pReset_S_out ( pResetWires[145] ) , .pReset_E_out ( pResetWires[144] ) , .prog_clk_0_N_in ( prog_clk_0_wires[335] ) , .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6970 ) , - .prog_clk_1_W_in ( p1887 ) , .prog_clk_1_E_in ( p451 ) , + .prog_clk_1_W_in ( p1271 ) , .prog_clk_1_E_in ( p634 ) , .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_6971 ) , .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_6972 ) , .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_6973 ) , .prog_clk_2_W_in ( prog_clk_2_wires[69] ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6974 ) , - .prog_clk_2_E_out ( prog_clk_2_wires[70] ) , .prog_clk_3_W_in ( p1887 ) , - .prog_clk_3_E_in ( p1027 ) , + .prog_clk_2_E_out ( prog_clk_2_wires[70] ) , .prog_clk_3_W_in ( p1635 ) , + .prog_clk_3_E_in ( p173 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6975 ) , - .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6976 ) , .clk_1_W_in ( p1430 ) , - .clk_1_E_in ( p1682 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_6977 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6976 ) , .clk_1_W_in ( p1493 ) , + .clk_1_E_in ( p608 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_6977 ) , .clk_1_S_out ( SYNOPSYS_UNCONNECTED_6978 ) , .clk_2_E_in ( SYNOPSYS_UNCONNECTED_6979 ) , .clk_2_W_in ( clk_2_wires[69] ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6980 ) , - .clk_2_E_out ( clk_2_wires[70] ) , .clk_3_W_in ( p1887 ) , - .clk_3_E_in ( p164 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6981 ) , + .clk_2_E_out ( clk_2_wires[70] ) , .clk_3_W_in ( p1635 ) , + .clk_3_E_in ( p945 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6981 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6982 ) ) ; cbx_1__1_ cbx_9__3_ ( .pReset ( { SYNOPSYS_UNCONNECTED_6983 } ) , @@ -126024,7 +130563,7 @@ cbx_1__1_ cbx_9__3_ ( .bottom_grid_pin_14_ ( cbx_1__1__90_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__90_bottom_grid_pin_15_ ) , .ccff_tail ( cbx_1__1__90_ccff_tail ) , .SC_IN_TOP ( scff_Wires[230] ) , - .SC_OUT_BOT ( scff_Wires[231] ) , .SC_IN_BOT ( p1533 ) , + .SC_OUT_BOT ( scff_Wires[231] ) , .SC_IN_BOT ( p1456 ) , .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_6984 ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[90] ) , .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[90] ) , @@ -126039,19 +130578,19 @@ cbx_1__1_ cbx_9__3_ ( .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_6988 ) , .prog_clk_1_E_in ( prog_clk_1_wires[177] ) , .prog_clk_1_N_out ( prog_clk_1_wires[178] ) , - .prog_clk_1_S_out ( prog_clk_1_wires[179] ) , .prog_clk_2_E_in ( p2605 ) , - .prog_clk_2_W_in ( p977 ) , + .prog_clk_1_S_out ( prog_clk_1_wires[179] ) , .prog_clk_2_E_in ( p3345 ) , + .prog_clk_2_W_in ( p2686 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6989 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6990 ) , - .prog_clk_3_W_in ( p3248 ) , .prog_clk_3_E_in ( p817 ) , + .prog_clk_3_W_in ( p2780 ) , .prog_clk_3_E_in ( p3281 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6991 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6992 ) , .clk_1_W_in ( SYNOPSYS_UNCONNECTED_6993 ) , .clk_1_E_in ( clk_1_wires[177] ) , .clk_1_N_out ( clk_1_wires[178] ) , - .clk_1_S_out ( clk_1_wires[179] ) , .clk_2_E_in ( p2605 ) , - .clk_2_W_in ( p3230 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6994 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6995 ) , .clk_3_W_in ( p2229 ) , - .clk_3_E_in ( p2568 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6996 ) , + .clk_1_S_out ( clk_1_wires[179] ) , .clk_2_E_in ( p1404 ) , + .clk_2_W_in ( p83 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6994 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6995 ) , .clk_3_W_in ( p1311 ) , + .clk_3_E_in ( p779 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6996 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6997 ) ) ; cbx_1__1_ cbx_9__4_ ( .pReset ( { SYNOPSYS_UNCONNECTED_6998 } ) , @@ -126077,7 +130616,7 @@ cbx_1__1_ cbx_9__4_ ( .bottom_grid_pin_14_ ( cbx_1__1__91_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__91_bottom_grid_pin_15_ ) , .ccff_tail ( cbx_1__1__91_ccff_tail ) , .SC_IN_TOP ( scff_Wires[228] ) , - .SC_OUT_BOT ( scff_Wires[229] ) , .SC_IN_BOT ( p1449 ) , + .SC_OUT_BOT ( scff_Wires[229] ) , .SC_IN_BOT ( p1841 ) , .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_6999 ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[91] ) , .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[91] ) , @@ -126089,23 +130628,23 @@ cbx_1__1_ cbx_9__4_ ( .pReset_S_out ( pResetWires[243] ) , .pReset_E_out ( pResetWires[242] ) , .prog_clk_0_N_in ( prog_clk_0_wires[341] ) , .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_7002 ) , - .prog_clk_1_W_in ( p1549 ) , .prog_clk_1_E_in ( p150 ) , + .prog_clk_1_W_in ( p1145 ) , .prog_clk_1_E_in ( p1676 ) , .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_7003 ) , .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_7004 ) , .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_7005 ) , .prog_clk_2_W_in ( prog_clk_2_wires[78] ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_7006 ) , - .prog_clk_2_E_out ( prog_clk_2_wires[79] ) , .prog_clk_3_W_in ( p809 ) , - .prog_clk_3_E_in ( p1212 ) , + .prog_clk_2_E_out ( prog_clk_2_wires[79] ) , .prog_clk_3_W_in ( p1263 ) , + .prog_clk_3_E_in ( p465 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_7007 ) , - .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_7008 ) , .clk_1_W_in ( p1482 ) , - .clk_1_E_in ( p489 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_7009 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_7008 ) , .clk_1_W_in ( p1263 ) , + .clk_1_E_in ( p2162 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_7009 ) , .clk_1_S_out ( SYNOPSYS_UNCONNECTED_7010 ) , .clk_2_E_in ( SYNOPSYS_UNCONNECTED_7011 ) , .clk_2_W_in ( clk_2_wires[78] ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7012 ) , - .clk_2_E_out ( clk_2_wires[79] ) , .clk_3_W_in ( p809 ) , - .clk_3_E_in ( p526 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7013 ) , + .clk_2_E_out ( clk_2_wires[79] ) , .clk_3_W_in ( p1263 ) , + .clk_3_E_in ( p2086 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7013 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7014 ) ) ; cbx_1__1_ cbx_9__5_ ( .pReset ( { SYNOPSYS_UNCONNECTED_7015 } ) , @@ -126131,7 +130670,7 @@ cbx_1__1_ cbx_9__5_ ( .bottom_grid_pin_14_ ( cbx_1__1__92_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__92_bottom_grid_pin_15_ ) , .ccff_tail ( cbx_1__1__92_ccff_tail ) , .SC_IN_TOP ( scff_Wires[226] ) , - .SC_OUT_BOT ( scff_Wires[227] ) , .SC_IN_BOT ( p1611 ) , + .SC_OUT_BOT ( scff_Wires[227] ) , .SC_IN_BOT ( p1511 ) , .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_7016 ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[92] ) , .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[92] ) , @@ -126146,19 +130685,19 @@ cbx_1__1_ cbx_9__5_ ( .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_7020 ) , .prog_clk_1_E_in ( prog_clk_1_wires[184] ) , .prog_clk_1_N_out ( prog_clk_1_wires[185] ) , - .prog_clk_1_S_out ( prog_clk_1_wires[186] ) , .prog_clk_2_E_in ( p1598 ) , - .prog_clk_2_W_in ( p415 ) , + .prog_clk_1_S_out ( prog_clk_1_wires[186] ) , .prog_clk_2_E_in ( p2855 ) , + .prog_clk_2_W_in ( p696 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_7021 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_7022 ) , - .prog_clk_3_W_in ( p3366 ) , .prog_clk_3_E_in ( p1245 ) , + .prog_clk_3_W_in ( p1213 ) , .prog_clk_3_E_in ( p2657 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_7023 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_7024 ) , .clk_1_W_in ( SYNOPSYS_UNCONNECTED_7025 ) , .clk_1_E_in ( clk_1_wires[184] ) , .clk_1_N_out ( clk_1_wires[185] ) , - .clk_1_S_out ( clk_1_wires[186] ) , .clk_2_E_in ( p1598 ) , - .clk_2_W_in ( p3338 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7026 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7027 ) , .clk_3_W_in ( p2778 ) , - .clk_3_E_in ( p487 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7028 ) , + .clk_1_S_out ( clk_1_wires[186] ) , .clk_2_E_in ( p2330 ) , + .clk_2_W_in ( p1777 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7026 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7027 ) , .clk_3_W_in ( p2019 ) , + .clk_3_E_in ( p2177 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7028 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7029 ) ) ; cbx_1__1_ cbx_9__6_ ( .pReset ( { SYNOPSYS_UNCONNECTED_7030 } ) , @@ -126184,7 +130723,7 @@ cbx_1__1_ cbx_9__6_ ( .bottom_grid_pin_14_ ( cbx_1__1__93_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__93_bottom_grid_pin_15_ ) , .ccff_tail ( cbx_1__1__93_ccff_tail ) , .SC_IN_TOP ( scff_Wires[224] ) , - .SC_OUT_BOT ( scff_Wires[225] ) , .SC_IN_BOT ( p1587 ) , + .SC_OUT_BOT ( scff_Wires[225] ) , .SC_IN_BOT ( p1314 ) , .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_7031 ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[93] ) , .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[93] ) , @@ -126196,19 +130735,19 @@ cbx_1__1_ cbx_9__6_ ( .pReset_S_out ( pResetWires[341] ) , .pReset_E_out ( pResetWires[340] ) , .prog_clk_0_N_in ( prog_clk_0_wires[347] ) , .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_7034 ) , - .prog_clk_1_W_in ( p1599 ) , .prog_clk_1_E_in ( p747 ) , + .prog_clk_1_W_in ( p1322 ) , .prog_clk_1_E_in ( p431 ) , .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_7035 ) , .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_7036 ) , - .prog_clk_2_E_in ( p1379 ) , .prog_clk_2_W_in ( p1048 ) , + .prog_clk_2_E_in ( p1482 ) , .prog_clk_2_W_in ( p2434 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_7037 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_7038 ) , .prog_clk_3_W_in ( prog_clk_3_wires[44] ) , .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_7039 ) , .prog_clk_3_E_out ( prog_clk_3_wires[45] ) , - .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_7040 ) , .clk_1_W_in ( p1494 ) , - .clk_1_E_in ( p586 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_7041 ) , - .clk_1_S_out ( SYNOPSYS_UNCONNECTED_7042 ) , .clk_2_E_in ( p1379 ) , - .clk_2_W_in ( p506 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7043 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_7040 ) , .clk_1_W_in ( p2632 ) , + .clk_1_E_in ( p901 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_7041 ) , + .clk_1_S_out ( SYNOPSYS_UNCONNECTED_7042 ) , .clk_2_E_in ( p1482 ) , + .clk_2_W_in ( p238 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7043 ) , .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7044 ) , .clk_3_W_in ( clk_3_wires[44] ) , .clk_3_E_in ( SYNOPSYS_UNCONNECTED_7045 ) , @@ -126238,7 +130777,7 @@ cbx_1__1_ cbx_9__7_ ( .bottom_grid_pin_14_ ( cbx_1__1__94_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__94_bottom_grid_pin_15_ ) , .ccff_tail ( cbx_1__1__94_ccff_tail ) , .SC_IN_TOP ( scff_Wires[222] ) , - .SC_OUT_BOT ( scff_Wires[223] ) , .SC_IN_BOT ( p1606 ) , + .SC_OUT_BOT ( scff_Wires[223] ) , .SC_IN_BOT ( p1532 ) , .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_7048 ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[94] ) , .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[94] ) , @@ -126253,19 +130792,19 @@ cbx_1__1_ cbx_9__7_ ( .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_7052 ) , .prog_clk_1_E_in ( prog_clk_1_wires[191] ) , .prog_clk_1_N_out ( prog_clk_1_wires[192] ) , - .prog_clk_1_S_out ( prog_clk_1_wires[193] ) , .prog_clk_2_E_in ( p1797 ) , - .prog_clk_2_W_in ( p605 ) , + .prog_clk_1_S_out ( prog_clk_1_wires[193] ) , .prog_clk_2_E_in ( p2957 ) , + .prog_clk_2_W_in ( p1662 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_7053 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_7054 ) , - .prog_clk_3_W_in ( p3161 ) , .prog_clk_3_E_in ( p1095 ) , + .prog_clk_3_W_in ( p1975 ) , .prog_clk_3_E_in ( p2882 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_7055 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_7056 ) , .clk_1_W_in ( SYNOPSYS_UNCONNECTED_7057 ) , .clk_1_E_in ( clk_1_wires[191] ) , .clk_1_N_out ( clk_1_wires[192] ) , - .clk_1_S_out ( clk_1_wires[193] ) , .clk_2_E_in ( p1797 ) , - .clk_2_W_in ( p3118 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7058 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7059 ) , .clk_3_W_in ( p2996 ) , - .clk_3_E_in ( p1684 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7060 ) , + .clk_1_S_out ( clk_1_wires[193] ) , .clk_2_E_in ( p2288 ) , + .clk_2_W_in ( p3200 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7058 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7059 ) , .clk_3_W_in ( p3235 ) , + .clk_3_E_in ( p2172 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7060 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7061 ) ) ; cbx_1__1_ cbx_9__8_ ( .pReset ( { SYNOPSYS_UNCONNECTED_7062 } ) , @@ -126291,7 +130830,7 @@ cbx_1__1_ cbx_9__8_ ( .bottom_grid_pin_14_ ( cbx_1__1__95_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__95_bottom_grid_pin_15_ ) , .ccff_tail ( cbx_1__1__95_ccff_tail ) , .SC_IN_TOP ( scff_Wires[220] ) , - .SC_OUT_BOT ( scff_Wires[221] ) , .SC_IN_BOT ( p1839 ) , + .SC_OUT_BOT ( scff_Wires[221] ) , .SC_IN_BOT ( p1371 ) , .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_7063 ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[95] ) , .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[95] ) , @@ -126303,23 +130842,23 @@ cbx_1__1_ cbx_9__8_ ( .pReset_S_out ( pResetWires[439] ) , .pReset_E_out ( pResetWires[438] ) , .prog_clk_0_N_in ( prog_clk_0_wires[353] ) , .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_7066 ) , - .prog_clk_1_W_in ( p1324 ) , .prog_clk_1_E_in ( p1652 ) , + .prog_clk_1_W_in ( p1140 ) , .prog_clk_1_E_in ( p500 ) , .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_7067 ) , .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_7068 ) , .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_7069 ) , .prog_clk_2_W_in ( prog_clk_2_wires[91] ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_7070 ) , - .prog_clk_2_E_out ( prog_clk_2_wires[92] ) , .prog_clk_3_W_in ( p1595 ) , - .prog_clk_3_E_in ( p1112 ) , + .prog_clk_2_E_out ( prog_clk_2_wires[92] ) , .prog_clk_3_W_in ( p1021 ) , + .prog_clk_3_E_in ( p909 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_7071 ) , - .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_7072 ) , .clk_1_W_in ( p1414 ) , - .clk_1_E_in ( p1723 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_7073 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_7072 ) , .clk_1_W_in ( p1021 ) , + .clk_1_E_in ( p739 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_7073 ) , .clk_1_S_out ( SYNOPSYS_UNCONNECTED_7074 ) , .clk_2_E_in ( SYNOPSYS_UNCONNECTED_7075 ) , .clk_2_W_in ( clk_2_wires[91] ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7076 ) , - .clk_2_E_out ( clk_2_wires[92] ) , .clk_3_W_in ( p1595 ) , - .clk_3_E_in ( p1734 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7077 ) , + .clk_2_E_out ( clk_2_wires[92] ) , .clk_3_W_in ( p1021 ) , + .clk_3_E_in ( p1 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7077 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7078 ) ) ; cbx_1__1_ cbx_9__9_ ( .pReset ( { SYNOPSYS_UNCONNECTED_7079 } ) , @@ -126345,7 +130884,7 @@ cbx_1__1_ cbx_9__9_ ( .bottom_grid_pin_14_ ( cbx_1__1__96_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__96_bottom_grid_pin_15_ ) , .ccff_tail ( cbx_1__1__96_ccff_tail ) , .SC_IN_TOP ( scff_Wires[218] ) , - .SC_OUT_BOT ( scff_Wires[219] ) , .SC_IN_BOT ( p1334 ) , + .SC_OUT_BOT ( scff_Wires[219] ) , .SC_IN_BOT ( p1641 ) , .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_7080 ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[96] ) , .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[96] ) , @@ -126360,19 +130899,19 @@ cbx_1__1_ cbx_9__9_ ( .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_7084 ) , .prog_clk_1_E_in ( prog_clk_1_wires[198] ) , .prog_clk_1_N_out ( prog_clk_1_wires[199] ) , - .prog_clk_1_S_out ( prog_clk_1_wires[200] ) , .prog_clk_2_E_in ( p1 ) , - .prog_clk_2_W_in ( p155 ) , + .prog_clk_1_S_out ( prog_clk_1_wires[200] ) , .prog_clk_2_E_in ( p2817 ) , + .prog_clk_2_W_in ( p1811 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_7085 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_7086 ) , - .prog_clk_3_W_in ( p3324 ) , .prog_clk_3_E_in ( p918 ) , + .prog_clk_3_W_in ( p1982 ) , .prog_clk_3_E_in ( p2652 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_7087 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_7088 ) , .clk_1_W_in ( SYNOPSYS_UNCONNECTED_7089 ) , .clk_1_E_in ( clk_1_wires[198] ) , .clk_1_N_out ( clk_1_wires[199] ) , - .clk_1_S_out ( clk_1_wires[200] ) , .clk_2_E_in ( p1 ) , - .clk_2_W_in ( p3293 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7090 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7091 ) , .clk_3_W_in ( p2395 ) , - .clk_3_E_in ( p697 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7092 ) , + .clk_1_S_out ( clk_1_wires[200] ) , .clk_2_E_in ( p2607 ) , + .clk_2_W_in ( p2708 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7090 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7091 ) , .clk_3_W_in ( p2840 ) , + .clk_3_E_in ( p2478 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7092 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7093 ) ) ; cbx_1__1_ cbx_9__10_ ( .pReset ( { SYNOPSYS_UNCONNECTED_7094 } ) , @@ -126398,7 +130937,7 @@ cbx_1__1_ cbx_9__10_ ( .bottom_grid_pin_14_ ( cbx_1__1__97_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__97_bottom_grid_pin_15_ ) , .ccff_tail ( cbx_1__1__97_ccff_tail ) , .SC_IN_TOP ( scff_Wires[216] ) , - .SC_OUT_BOT ( scff_Wires[217] ) , .SC_IN_BOT ( p719 ) , + .SC_OUT_BOT ( scff_Wires[217] ) , .SC_IN_BOT ( p1320 ) , .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_7095 ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[97] ) , .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[97] ) , @@ -126410,23 +130949,23 @@ cbx_1__1_ cbx_9__10_ ( .pReset_S_out ( pResetWires[537] ) , .pReset_E_out ( pResetWires[536] ) , .prog_clk_0_N_in ( prog_clk_0_wires[359] ) , .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_7098 ) , - .prog_clk_1_W_in ( p2195 ) , .prog_clk_1_E_in ( p610 ) , + .prog_clk_1_W_in ( p1488 ) , .prog_clk_1_E_in ( p455 ) , .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_7099 ) , .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_7100 ) , .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_7101 ) , .prog_clk_2_W_in ( prog_clk_2_wires[104] ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_7102 ) , - .prog_clk_2_E_out ( prog_clk_2_wires[105] ) , .prog_clk_3_W_in ( p2169 ) , - .prog_clk_3_E_in ( p500 ) , + .prog_clk_2_E_out ( prog_clk_2_wires[105] ) , .prog_clk_3_W_in ( p1386 ) , + .prog_clk_3_E_in ( p1065 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_7103 ) , - .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_7104 ) , .clk_1_W_in ( p1417 ) , - .clk_1_E_in ( p436 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_7105 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_7104 ) , .clk_1_W_in ( p1386 ) , + .clk_1_E_in ( p1810 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_7105 ) , .clk_1_S_out ( SYNOPSYS_UNCONNECTED_7106 ) , .clk_2_E_in ( SYNOPSYS_UNCONNECTED_7107 ) , .clk_2_W_in ( clk_2_wires[104] ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7108 ) , - .clk_2_E_out ( clk_2_wires[105] ) , .clk_3_W_in ( p2169 ) , - .clk_3_E_in ( p1127 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7109 ) , + .clk_2_E_out ( clk_2_wires[105] ) , .clk_3_W_in ( p1386 ) , + .clk_3_E_in ( p1656 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7109 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7110 ) ) ; cbx_1__1_ cbx_9__11_ ( .pReset ( { SYNOPSYS_UNCONNECTED_7111 } ) , @@ -126452,7 +130991,7 @@ cbx_1__1_ cbx_9__11_ ( .bottom_grid_pin_14_ ( cbx_1__1__98_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__98_bottom_grid_pin_15_ ) , .ccff_tail ( cbx_1__1__98_ccff_tail ) , .SC_IN_TOP ( scff_Wires[214] ) , - .SC_OUT_BOT ( scff_Wires[215] ) , .SC_IN_BOT ( p1844 ) , + .SC_OUT_BOT ( scff_Wires[215] ) , .SC_IN_BOT ( p1845 ) , .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_7112 ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[98] ) , .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[98] ) , @@ -126467,19 +131006,19 @@ cbx_1__1_ cbx_9__11_ ( .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_7116 ) , .prog_clk_1_E_in ( prog_clk_1_wires[205] ) , .prog_clk_1_N_out ( prog_clk_1_wires[206] ) , - .prog_clk_1_S_out ( prog_clk_1_wires[207] ) , .prog_clk_2_E_in ( p1537 ) , - .prog_clk_2_W_in ( p1206 ) , + .prog_clk_1_S_out ( prog_clk_1_wires[207] ) , .prog_clk_2_E_in ( p3468 ) , + .prog_clk_2_W_in ( p2459 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_7117 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_7118 ) , - .prog_clk_3_W_in ( p3181 ) , .prog_clk_3_E_in ( p1197 ) , + .prog_clk_3_W_in ( p2603 ) , .prog_clk_3_E_in ( p3428 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_7119 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_7120 ) , .clk_1_W_in ( SYNOPSYS_UNCONNECTED_7121 ) , .clk_1_E_in ( clk_1_wires[205] ) , .clk_1_N_out ( clk_1_wires[206] ) , - .clk_1_S_out ( clk_1_wires[207] ) , .clk_2_E_in ( p1537 ) , - .clk_2_W_in ( p3146 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7122 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7123 ) , .clk_3_W_in ( p2390 ) , - .clk_3_E_in ( p259 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7124 ) , + .clk_1_S_out ( clk_1_wires[207] ) , .clk_2_E_in ( p2510 ) , + .clk_2_W_in ( p3072 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7122 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7123 ) , .clk_3_W_in ( p3169 ) , + .clk_3_E_in ( p2474 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7124 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7125 ) ) ; cbx_1__1_ cbx_10__1_ ( .pReset ( { SYNOPSYS_UNCONNECTED_7126 } ) , @@ -126504,7 +131043,7 @@ cbx_1__1_ cbx_10__1_ ( .bottom_grid_pin_13_ ( cbx_1__1__99_bottom_grid_pin_13_ ) , .bottom_grid_pin_14_ ( cbx_1__1__99_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__99_bottom_grid_pin_15_ ) , - .ccff_tail ( cbx_1__1__99_ccff_tail ) , .SC_IN_TOP ( p1541 ) , + .ccff_tail ( cbx_1__1__99_ccff_tail ) , .SC_IN_TOP ( p1254 ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_7127 ) , .SC_IN_BOT ( scff_Wires[241] ) , .SC_OUT_TOP ( scff_Wires[242] ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[99] ) , @@ -126520,20 +131059,20 @@ cbx_1__1_ cbx_10__1_ ( .prog_clk_1_W_in ( prog_clk_1_wires[169] ) , .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_7131 ) , .prog_clk_1_N_out ( prog_clk_1_wires[173] ) , - .prog_clk_1_S_out ( prog_clk_1_wires[174] ) , .prog_clk_2_E_in ( p2175 ) , - .prog_clk_2_W_in ( p1775 ) , + .prog_clk_1_S_out ( prog_clk_1_wires[174] ) , .prog_clk_2_E_in ( p2626 ) , + .prog_clk_2_W_in ( p3224 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_7132 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_7133 ) , - .prog_clk_3_W_in ( p3198 ) , .prog_clk_3_E_in ( p1305 ) , + .prog_clk_3_W_in ( p3238 ) , .prog_clk_3_E_in ( p2499 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_7134 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_7135 ) , .clk_1_W_in ( clk_1_wires[169] ) , .clk_1_E_in ( SYNOPSYS_UNCONNECTED_7136 ) , .clk_1_N_out ( clk_1_wires[173] ) , .clk_1_S_out ( clk_1_wires[174] ) , - .clk_2_E_in ( p2175 ) , .clk_2_W_in ( p3156 ) , + .clk_2_E_in ( p1265 ) , .clk_2_W_in ( p3393 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7137 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7138 ) , .clk_3_W_in ( p2644 ) , - .clk_3_E_in ( p2099 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7139 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7138 ) , .clk_3_W_in ( p3406 ) , + .clk_3_E_in ( p1605 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7139 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7140 ) ) ; cbx_1__1_ cbx_10__2_ ( .pReset ( { SYNOPSYS_UNCONNECTED_7141 } ) , @@ -126558,7 +131097,7 @@ cbx_1__1_ cbx_10__2_ ( .bottom_grid_pin_13_ ( cbx_1__1__100_bottom_grid_pin_13_ ) , .bottom_grid_pin_14_ ( cbx_1__1__100_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__100_bottom_grid_pin_15_ ) , - .ccff_tail ( cbx_1__1__100_ccff_tail ) , .SC_IN_TOP ( p1771 ) , + .ccff_tail ( cbx_1__1__100_ccff_tail ) , .SC_IN_TOP ( p1819 ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_7142 ) , .SC_IN_BOT ( scff_Wires[243] ) , .SC_OUT_TOP ( scff_Wires[244] ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[100] ) , @@ -126571,20 +131110,20 @@ cbx_1__1_ cbx_10__2_ ( .pReset_S_out ( pResetWires[149] ) , .pReset_E_out ( pResetWires[148] ) , .prog_clk_0_N_in ( prog_clk_0_wires[373] ) , .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_7145 ) , - .prog_clk_1_W_in ( p2231 ) , .prog_clk_1_E_in ( p1258 ) , + .prog_clk_1_W_in ( p1430 ) , .prog_clk_1_E_in ( p1179 ) , .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_7146 ) , .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_7147 ) , - .prog_clk_2_E_in ( p2681 ) , .prog_clk_2_W_in ( p2080 ) , + .prog_clk_2_E_in ( p1819 ) , .prog_clk_2_W_in ( p3390 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_7148 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_7149 ) , - .prog_clk_3_W_in ( p2367 ) , .prog_clk_3_E_in ( p1890 ) , + .prog_clk_3_W_in ( p3424 ) , .prog_clk_3_E_in ( p1930 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_7150 ) , - .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_7151 ) , .clk_1_W_in ( p1286 ) , - .clk_1_E_in ( p867 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_7152 ) , - .clk_1_S_out ( SYNOPSYS_UNCONNECTED_7153 ) , .clk_2_E_in ( p2681 ) , - .clk_2_W_in ( p2493 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7154 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7155 ) , .clk_3_W_in ( p2419 ) , - .clk_3_E_in ( p2604 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7156 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_7151 ) , .clk_1_W_in ( p2289 ) , + .clk_1_E_in ( p1373 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_7152 ) , + .clk_1_S_out ( SYNOPSYS_UNCONNECTED_7153 ) , .clk_2_E_in ( p1521 ) , + .clk_2_W_in ( p2938 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7154 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7155 ) , .clk_3_W_in ( p2946 ) , + .clk_3_E_in ( p428 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7156 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7157 ) ) ; cbx_1__1_ cbx_10__3_ ( .pReset ( { SYNOPSYS_UNCONNECTED_7158 } ) , @@ -126609,7 +131148,7 @@ cbx_1__1_ cbx_10__3_ ( .bottom_grid_pin_13_ ( cbx_1__1__101_bottom_grid_pin_13_ ) , .bottom_grid_pin_14_ ( cbx_1__1__101_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__101_bottom_grid_pin_15_ ) , - .ccff_tail ( cbx_1__1__101_ccff_tail ) , .SC_IN_TOP ( p1880 ) , + .ccff_tail ( cbx_1__1__101_ccff_tail ) , .SC_IN_TOP ( p1861 ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_7159 ) , .SC_IN_BOT ( scff_Wires[245] ) , .SC_OUT_TOP ( scff_Wires[246] ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[101] ) , @@ -126625,20 +131164,20 @@ cbx_1__1_ cbx_10__3_ ( .prog_clk_1_W_in ( prog_clk_1_wires[176] ) , .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_7163 ) , .prog_clk_1_N_out ( prog_clk_1_wires[180] ) , - .prog_clk_1_S_out ( prog_clk_1_wires[181] ) , .prog_clk_2_E_in ( p2451 ) , - .prog_clk_2_W_in ( p1343 ) , + .prog_clk_1_S_out ( prog_clk_1_wires[181] ) , .prog_clk_2_E_in ( p2190 ) , + .prog_clk_2_W_in ( p3220 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_7164 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_7165 ) , - .prog_clk_3_W_in ( p2822 ) , .prog_clk_3_E_in ( p1779 ) , + .prog_clk_3_W_in ( p3269 ) , .prog_clk_3_E_in ( p2365 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_7166 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_7167 ) , .clk_1_W_in ( clk_1_wires[176] ) , .clk_1_E_in ( SYNOPSYS_UNCONNECTED_7168 ) , .clk_1_N_out ( clk_1_wires[180] ) , .clk_1_S_out ( clk_1_wires[181] ) , - .clk_2_E_in ( p2451 ) , .clk_2_W_in ( p2769 ) , + .clk_2_E_in ( p2189 ) , .clk_2_W_in ( p2925 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7169 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7170 ) , .clk_3_W_in ( p1952 ) , - .clk_3_E_in ( p2347 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7171 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7170 ) , .clk_3_W_in ( p2979 ) , + .clk_3_E_in ( p2156 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7171 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7172 ) ) ; cbx_1__1_ cbx_10__4_ ( .pReset ( { SYNOPSYS_UNCONNECTED_7173 } ) , @@ -126663,7 +131202,7 @@ cbx_1__1_ cbx_10__4_ ( .bottom_grid_pin_13_ ( cbx_1__1__102_bottom_grid_pin_13_ ) , .bottom_grid_pin_14_ ( cbx_1__1__102_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__102_bottom_grid_pin_15_ ) , - .ccff_tail ( cbx_1__1__102_ccff_tail ) , .SC_IN_TOP ( p2427 ) , + .ccff_tail ( cbx_1__1__102_ccff_tail ) , .SC_IN_TOP ( p1610 ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_7174 ) , .SC_IN_BOT ( scff_Wires[247] ) , .SC_OUT_TOP ( scff_Wires[248] ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[102] ) , @@ -126676,20 +131215,20 @@ cbx_1__1_ cbx_10__4_ ( .pReset_S_out ( pResetWires[247] ) , .pReset_E_out ( pResetWires[246] ) , .prog_clk_0_N_in ( prog_clk_0_wires[379] ) , .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_7177 ) , - .prog_clk_1_W_in ( p2613 ) , .prog_clk_1_E_in ( p1096 ) , + .prog_clk_1_W_in ( p1516 ) , .prog_clk_1_E_in ( p847 ) , .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_7178 ) , .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_7179 ) , - .prog_clk_2_E_in ( p1914 ) , .prog_clk_2_W_in ( p2611 ) , + .prog_clk_2_E_in ( p1959 ) , .prog_clk_2_W_in ( p3206 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_7180 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_7181 ) , - .prog_clk_3_W_in ( p3183 ) , .prog_clk_3_E_in ( p2360 ) , + .prog_clk_3_W_in ( p3247 ) , .prog_clk_3_E_in ( p1761 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_7182 ) , - .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_7183 ) , .clk_1_W_in ( p1591 ) , - .clk_1_E_in ( p779 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_7184 ) , - .clk_1_S_out ( SYNOPSYS_UNCONNECTED_7185 ) , .clk_2_E_in ( p1914 ) , - .clk_2_W_in ( p3148 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7186 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7187 ) , .clk_3_W_in ( p2178 ) , - .clk_3_E_in ( p1756 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7188 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_7183 ) , .clk_1_W_in ( p2271 ) , + .clk_1_E_in ( p1050 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_7184 ) , + .clk_1_S_out ( SYNOPSYS_UNCONNECTED_7185 ) , .clk_2_E_in ( p2794 ) , + .clk_2_W_in ( p3103 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7186 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7187 ) , .clk_3_W_in ( p3112 ) , + .clk_3_E_in ( p2733 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7188 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7189 ) ) ; cbx_1__1_ cbx_10__5_ ( .pReset ( { SYNOPSYS_UNCONNECTED_7190 } ) , @@ -126714,7 +131253,7 @@ cbx_1__1_ cbx_10__5_ ( .bottom_grid_pin_13_ ( cbx_1__1__103_bottom_grid_pin_13_ ) , .bottom_grid_pin_14_ ( cbx_1__1__103_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__103_bottom_grid_pin_15_ ) , - .ccff_tail ( cbx_1__1__103_ccff_tail ) , .SC_IN_TOP ( p2108 ) , + .ccff_tail ( cbx_1__1__103_ccff_tail ) , .SC_IN_TOP ( p2244 ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_7191 ) , .SC_IN_BOT ( scff_Wires[249] ) , .SC_OUT_TOP ( scff_Wires[250] ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[103] ) , @@ -126730,20 +131269,20 @@ cbx_1__1_ cbx_10__5_ ( .prog_clk_1_W_in ( prog_clk_1_wires[183] ) , .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_7195 ) , .prog_clk_1_N_out ( prog_clk_1_wires[187] ) , - .prog_clk_1_S_out ( prog_clk_1_wires[188] ) , .prog_clk_2_E_in ( p2142 ) , - .prog_clk_2_W_in ( p1047 ) , + .prog_clk_1_S_out ( prog_clk_1_wires[188] ) , .prog_clk_2_E_in ( p3020 ) , + .prog_clk_2_W_in ( p2495 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_7196 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_7197 ) , - .prog_clk_3_W_in ( p3052 ) , .prog_clk_3_E_in ( p2072 ) , + .prog_clk_3_W_in ( p2608 ) , .prog_clk_3_E_in ( p2931 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_7198 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_7199 ) , .clk_1_W_in ( clk_1_wires[183] ) , .clk_1_E_in ( SYNOPSYS_UNCONNECTED_7200 ) , .clk_1_N_out ( clk_1_wires[187] ) , .clk_1_S_out ( clk_1_wires[188] ) , - .clk_2_E_in ( p2142 ) , .clk_2_W_in ( p3049 ) , + .clk_2_E_in ( p2327 ) , .clk_2_W_in ( p2426 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7201 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7202 ) , .clk_3_W_in ( p1808 ) , - .clk_3_E_in ( p2213 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7203 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7202 ) , .clk_3_W_in ( p2576 ) , + .clk_3_E_in ( p2144 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7203 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7204 ) ) ; cbx_1__1_ cbx_10__6_ ( .pReset ( { SYNOPSYS_UNCONNECTED_7205 } ) , @@ -126768,7 +131307,7 @@ cbx_1__1_ cbx_10__6_ ( .bottom_grid_pin_13_ ( cbx_1__1__104_bottom_grid_pin_13_ ) , .bottom_grid_pin_14_ ( cbx_1__1__104_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__104_bottom_grid_pin_15_ ) , - .ccff_tail ( cbx_1__1__104_ccff_tail ) , .SC_IN_TOP ( p1531 ) , + .ccff_tail ( cbx_1__1__104_ccff_tail ) , .SC_IN_TOP ( p1479 ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_7206 ) , .SC_IN_BOT ( scff_Wires[251] ) , .SC_OUT_TOP ( scff_Wires[252] ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[104] ) , @@ -126781,19 +131320,19 @@ cbx_1__1_ cbx_10__6_ ( .pReset_S_out ( pResetWires[345] ) , .pReset_E_out ( pResetWires[344] ) , .prog_clk_0_N_in ( prog_clk_0_wires[385] ) , .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_7209 ) , - .prog_clk_1_W_in ( p1610 ) , .prog_clk_1_E_in ( p1108 ) , + .prog_clk_1_W_in ( p1512 ) , .prog_clk_1_E_in ( p1000 ) , .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_7210 ) , .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_7211 ) , - .prog_clk_2_E_in ( p1531 ) , .prog_clk_2_W_in ( p1376 ) , + .prog_clk_2_E_in ( p1649 ) , .prog_clk_2_W_in ( p2168 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_7212 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_7213 ) , .prog_clk_3_W_in ( prog_clk_3_wires[48] ) , .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_7214 ) , .prog_clk_3_E_out ( prog_clk_3_wires[49] ) , - .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_7215 ) , .clk_1_W_in ( p1588 ) , - .clk_1_E_in ( p1131 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_7216 ) , - .clk_1_S_out ( SYNOPSYS_UNCONNECTED_7217 ) , .clk_2_E_in ( p1531 ) , - .clk_2_W_in ( p898 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7218 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_7215 ) , .clk_1_W_in ( p2296 ) , + .clk_1_E_in ( p769 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_7216 ) , + .clk_1_S_out ( SYNOPSYS_UNCONNECTED_7217 ) , .clk_2_E_in ( p1344 ) , + .clk_2_W_in ( p1235 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7218 ) , .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7219 ) , .clk_3_W_in ( clk_3_wires[48] ) , .clk_3_E_in ( SYNOPSYS_UNCONNECTED_7220 ) , @@ -126822,7 +131361,7 @@ cbx_1__1_ cbx_10__7_ ( .bottom_grid_pin_13_ ( cbx_1__1__105_bottom_grid_pin_13_ ) , .bottom_grid_pin_14_ ( cbx_1__1__105_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__105_bottom_grid_pin_15_ ) , - .ccff_tail ( cbx_1__1__105_ccff_tail ) , .SC_IN_TOP ( p1454 ) , + .ccff_tail ( cbx_1__1__105_ccff_tail ) , .SC_IN_TOP ( p1539 ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_7223 ) , .SC_IN_BOT ( scff_Wires[253] ) , .SC_OUT_TOP ( scff_Wires[254] ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[105] ) , @@ -126838,20 +131377,20 @@ cbx_1__1_ cbx_10__7_ ( .prog_clk_1_W_in ( prog_clk_1_wires[190] ) , .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_7227 ) , .prog_clk_1_N_out ( prog_clk_1_wires[194] ) , - .prog_clk_1_S_out ( prog_clk_1_wires[195] ) , .prog_clk_2_E_in ( p2418 ) , - .prog_clk_2_W_in ( p1729 ) , + .prog_clk_1_S_out ( prog_clk_1_wires[195] ) , .prog_clk_2_E_in ( p3251 ) , + .prog_clk_2_W_in ( p1068 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_7228 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_7229 ) , - .prog_clk_3_W_in ( p3106 ) , .prog_clk_3_E_in ( p849 ) , + .prog_clk_3_W_in ( p1410 ) , .prog_clk_3_E_in ( p3202 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_7230 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_7231 ) , .clk_1_W_in ( clk_1_wires[190] ) , .clk_1_E_in ( SYNOPSYS_UNCONNECTED_7232 ) , .clk_1_N_out ( clk_1_wires[194] ) , .clk_1_S_out ( clk_1_wires[195] ) , - .clk_2_E_in ( p2418 ) , .clk_2_W_in ( p3046 ) , + .clk_2_E_in ( p2507 ) , .clk_2_W_in ( p3218 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7233 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7234 ) , .clk_3_W_in ( p1805 ) , - .clk_3_E_in ( p2368 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7235 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7234 ) , .clk_3_W_in ( p3246 ) , + .clk_3_E_in ( p2506 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7235 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7236 ) ) ; cbx_1__1_ cbx_10__8_ ( .pReset ( { SYNOPSYS_UNCONNECTED_7237 } ) , @@ -126876,7 +131415,7 @@ cbx_1__1_ cbx_10__8_ ( .bottom_grid_pin_13_ ( cbx_1__1__106_bottom_grid_pin_13_ ) , .bottom_grid_pin_14_ ( cbx_1__1__106_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__106_bottom_grid_pin_15_ ) , - .ccff_tail ( cbx_1__1__106_ccff_tail ) , .SC_IN_TOP ( p1856 ) , + .ccff_tail ( cbx_1__1__106_ccff_tail ) , .SC_IN_TOP ( p2268 ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_7238 ) , .SC_IN_BOT ( scff_Wires[255] ) , .SC_OUT_TOP ( scff_Wires[256] ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[106] ) , @@ -126889,20 +131428,20 @@ cbx_1__1_ cbx_10__8_ ( .pReset_S_out ( pResetWires[443] ) , .pReset_E_out ( pResetWires[442] ) , .prog_clk_0_N_in ( prog_clk_0_wires[391] ) , .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_7241 ) , - .prog_clk_1_W_in ( p2516 ) , .prog_clk_1_E_in ( p462 ) , + .prog_clk_1_W_in ( p1513 ) , .prog_clk_1_E_in ( p462 ) , .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_7242 ) , .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_7243 ) , - .prog_clk_2_E_in ( p2863 ) , .prog_clk_2_W_in ( p2316 ) , + .prog_clk_2_E_in ( p3395 ) , .prog_clk_2_W_in ( p3314 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_7244 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_7245 ) , - .prog_clk_3_W_in ( p3330 ) , .prog_clk_3_E_in ( p1693 ) , + .prog_clk_3_W_in ( p3340 ) , .prog_clk_3_E_in ( p3376 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_7246 ) , - .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_7247 ) , .clk_1_W_in ( p1820 ) , - .clk_1_E_in ( p678 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_7248 ) , - .clk_1_S_out ( SYNOPSYS_UNCONNECTED_7249 ) , .clk_2_E_in ( p2863 ) , - .clk_2_W_in ( p3302 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7250 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7251 ) , .clk_3_W_in ( p2238 ) , - .clk_3_E_in ( p2751 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7252 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_7247 ) , .clk_1_W_in ( p1134 ) , + .clk_1_E_in ( p619 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_7248 ) , + .clk_1_S_out ( SYNOPSYS_UNCONNECTED_7249 ) , .clk_2_E_in ( p2748 ) , + .clk_2_W_in ( p3049 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7250 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7251 ) , .clk_3_W_in ( p3144 ) , + .clk_3_E_in ( p2745 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7252 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7253 ) ) ; cbx_1__1_ cbx_10__9_ ( .pReset ( { SYNOPSYS_UNCONNECTED_7254 } ) , @@ -126927,7 +131466,7 @@ cbx_1__1_ cbx_10__9_ ( .bottom_grid_pin_13_ ( cbx_1__1__107_bottom_grid_pin_13_ ) , .bottom_grid_pin_14_ ( cbx_1__1__107_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__107_bottom_grid_pin_15_ ) , - .ccff_tail ( cbx_1__1__107_ccff_tail ) , .SC_IN_TOP ( p2244 ) , + .ccff_tail ( cbx_1__1__107_ccff_tail ) , .SC_IN_TOP ( p1988 ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_7255 ) , .SC_IN_BOT ( scff_Wires[257] ) , .SC_OUT_TOP ( scff_Wires[258] ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[107] ) , @@ -126943,20 +131482,20 @@ cbx_1__1_ cbx_10__9_ ( .prog_clk_1_W_in ( prog_clk_1_wires[197] ) , .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_7259 ) , .prog_clk_1_N_out ( prog_clk_1_wires[201] ) , - .prog_clk_1_S_out ( prog_clk_1_wires[202] ) , .prog_clk_2_E_in ( p1479 ) , - .prog_clk_2_W_in ( p689 ) , + .prog_clk_1_S_out ( prog_clk_1_wires[202] ) , .prog_clk_2_E_in ( p1988 ) , + .prog_clk_2_W_in ( p2487 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_7260 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_7261 ) , - .prog_clk_3_W_in ( p1423 ) , .prog_clk_3_E_in ( p2050 ) , + .prog_clk_3_W_in ( p2599 ) , .prog_clk_3_E_in ( p1794 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_7262 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_7263 ) , .clk_1_W_in ( clk_1_wires[197] ) , .clk_1_E_in ( SYNOPSYS_UNCONNECTED_7264 ) , .clk_1_N_out ( clk_1_wires[201] ) , .clk_1_S_out ( clk_1_wires[202] ) , - .clk_2_E_in ( p1479 ) , .clk_2_W_in ( p2917 ) , + .clk_2_E_in ( p1827 ) , .clk_2_W_in ( p1833 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7265 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7266 ) , .clk_3_W_in ( p2952 ) , - .clk_3_E_in ( p1315 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7267 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7266 ) , .clk_3_W_in ( p1948 ) , + .clk_3_E_in ( p1873 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7267 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7268 ) ) ; cbx_1__1_ cbx_10__10_ ( .pReset ( { SYNOPSYS_UNCONNECTED_7269 } ) , @@ -126981,7 +131520,7 @@ cbx_1__1_ cbx_10__10_ ( .bottom_grid_pin_13_ ( cbx_1__1__108_bottom_grid_pin_13_ ) , .bottom_grid_pin_14_ ( cbx_1__1__108_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__108_bottom_grid_pin_15_ ) , - .ccff_tail ( cbx_1__1__108_ccff_tail ) , .SC_IN_TOP ( p1239 ) , + .ccff_tail ( cbx_1__1__108_ccff_tail ) , .SC_IN_TOP ( p1487 ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_7270 ) , .SC_IN_BOT ( scff_Wires[259] ) , .SC_OUT_TOP ( scff_Wires[260] ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[108] ) , @@ -126994,20 +131533,20 @@ cbx_1__1_ cbx_10__10_ ( .pReset_S_out ( pResetWires[541] ) , .pReset_E_out ( pResetWires[540] ) , .prog_clk_0_N_in ( prog_clk_0_wires[397] ) , .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_7273 ) , - .prog_clk_1_W_in ( p1233 ) , .prog_clk_1_E_in ( p1037 ) , + .prog_clk_1_W_in ( p1157 ) , .prog_clk_1_E_in ( p993 ) , .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_7274 ) , .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_7275 ) , - .prog_clk_2_E_in ( p1583 ) , .prog_clk_2_W_in ( p1373 ) , + .prog_clk_2_E_in ( p1293 ) , .prog_clk_2_W_in ( p1389 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_7276 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_7277 ) , - .prog_clk_3_W_in ( p1373 ) , .prog_clk_3_E_in ( p1239 ) , + .prog_clk_3_W_in ( p1389 ) , .prog_clk_3_E_in ( p1293 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_7278 ) , - .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_7279 ) , .clk_1_W_in ( p1467 ) , - .clk_1_E_in ( p853 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_7280 ) , - .clk_1_S_out ( SYNOPSYS_UNCONNECTED_7281 ) , .clk_2_E_in ( p1583 ) , - .clk_2_W_in ( p1373 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7282 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7283 ) , .clk_3_W_in ( p1373 ) , - .clk_3_E_in ( p1239 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7284 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_7279 ) , .clk_1_W_in ( p1389 ) , + .clk_1_E_in ( p835 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_7280 ) , + .clk_1_S_out ( SYNOPSYS_UNCONNECTED_7281 ) , .clk_2_E_in ( p1507 ) , + .clk_2_W_in ( p1389 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7282 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7283 ) , .clk_3_W_in ( p1389 ) , + .clk_3_E_in ( p1507 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7284 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7285 ) ) ; cbx_1__1_ cbx_10__11_ ( .pReset ( { SYNOPSYS_UNCONNECTED_7286 } ) , @@ -127032,7 +131571,7 @@ cbx_1__1_ cbx_10__11_ ( .bottom_grid_pin_13_ ( cbx_1__1__109_bottom_grid_pin_13_ ) , .bottom_grid_pin_14_ ( cbx_1__1__109_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__109_bottom_grid_pin_15_ ) , - .ccff_tail ( cbx_1__1__109_ccff_tail ) , .SC_IN_TOP ( p2125 ) , + .ccff_tail ( cbx_1__1__109_ccff_tail ) , .SC_IN_TOP ( p1485 ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_7287 ) , .SC_IN_BOT ( scff_Wires[261] ) , .SC_OUT_TOP ( scff_Wires[262] ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[109] ) , @@ -127048,20 +131587,20 @@ cbx_1__1_ cbx_10__11_ ( .prog_clk_1_W_in ( prog_clk_1_wires[204] ) , .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_7291 ) , .prog_clk_1_N_out ( prog_clk_1_wires[208] ) , - .prog_clk_1_S_out ( prog_clk_1_wires[209] ) , .prog_clk_2_E_in ( p1963 ) , - .prog_clk_2_W_in ( p1746 ) , + .prog_clk_1_S_out ( prog_clk_1_wires[209] ) , .prog_clk_2_E_in ( p1485 ) , + .prog_clk_2_W_in ( p1166 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_7292 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_7293 ) , - .prog_clk_3_W_in ( p3045 ) , .prog_clk_3_E_in ( p2125 ) , + .prog_clk_3_W_in ( p1166 ) , .prog_clk_3_E_in ( p1485 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_7294 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_7295 ) , .clk_1_W_in ( clk_1_wires[204] ) , .clk_1_E_in ( SYNOPSYS_UNCONNECTED_7296 ) , .clk_1_N_out ( clk_1_wires[208] ) , .clk_1_S_out ( clk_1_wires[209] ) , - .clk_2_E_in ( p1963 ) , .clk_2_W_in ( p3045 ) , + .clk_2_E_in ( p2196 ) , .clk_2_W_in ( p1244 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7297 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7298 ) , .clk_3_W_in ( p3070 ) , - .clk_3_E_in ( p2104 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7299 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7298 ) , .clk_3_W_in ( p1244 ) , + .clk_3_E_in ( p2235 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7299 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7300 ) ) ; cbx_1__1_ cbx_11__1_ ( .pReset ( { SYNOPSYS_UNCONNECTED_7301 } ) , @@ -127087,7 +131626,7 @@ cbx_1__1_ cbx_11__1_ ( .bottom_grid_pin_14_ ( cbx_1__1__110_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__110_bottom_grid_pin_15_ ) , .ccff_tail ( cbx_1__1__110_ccff_tail ) , .SC_IN_TOP ( scff_Wires[287] ) , - .SC_OUT_BOT ( scff_Wires[288] ) , .SC_IN_BOT ( p1433 ) , + .SC_OUT_BOT ( scff_Wires[288] ) , .SC_IN_BOT ( p1594 ) , .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_7302 ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[110] ) , .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[110] ) , @@ -127102,19 +131641,19 @@ cbx_1__1_ cbx_11__1_ ( .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_7306 ) , .prog_clk_1_E_in ( prog_clk_1_wires[212] ) , .prog_clk_1_N_out ( prog_clk_1_wires[213] ) , - .prog_clk_1_S_out ( prog_clk_1_wires[214] ) , .prog_clk_2_E_in ( p1901 ) , - .prog_clk_2_W_in ( p813 ) , + .prog_clk_1_S_out ( prog_clk_1_wires[214] ) , .prog_clk_2_E_in ( p2332 ) , + .prog_clk_2_W_in ( p2725 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_7307 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_7308 ) , - .prog_clk_3_W_in ( p2660 ) , .prog_clk_3_E_in ( p1896 ) , + .prog_clk_3_W_in ( p2773 ) , .prog_clk_3_E_in ( p2188 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_7309 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_7310 ) , .clk_1_W_in ( SYNOPSYS_UNCONNECTED_7311 ) , .clk_1_E_in ( clk_1_wires[212] ) , .clk_1_N_out ( clk_1_wires[213] ) , - .clk_1_S_out ( clk_1_wires[214] ) , .clk_2_E_in ( p1901 ) , - .clk_2_W_in ( p2914 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7312 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7313 ) , .clk_3_W_in ( p2951 ) , - .clk_3_E_in ( p1752 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7314 ) , + .clk_1_S_out ( clk_1_wires[214] ) , .clk_2_E_in ( p1317 ) , + .clk_2_W_in ( p1082 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7312 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7313 ) , .clk_3_W_in ( p1592 ) , + .clk_3_E_in ( p689 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7314 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7315 ) ) ; cbx_1__1_ cbx_11__2_ ( .pReset ( { SYNOPSYS_UNCONNECTED_7316 } ) , @@ -127140,7 +131679,7 @@ cbx_1__1_ cbx_11__2_ ( .bottom_grid_pin_14_ ( cbx_1__1__111_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__111_bottom_grid_pin_15_ ) , .ccff_tail ( cbx_1__1__111_ccff_tail ) , .SC_IN_TOP ( scff_Wires[285] ) , - .SC_OUT_BOT ( scff_Wires[286] ) , .SC_IN_BOT ( p2127 ) , + .SC_OUT_BOT ( scff_Wires[286] ) , .SC_IN_BOT ( p1464 ) , .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_7317 ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[111] ) , .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[111] ) , @@ -127152,23 +131691,23 @@ cbx_1__1_ cbx_11__2_ ( .pReset_S_out ( pResetWires[153] ) , .pReset_E_out ( pResetWires[152] ) , .prog_clk_0_N_in ( prog_clk_0_wires[411] ) , .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_7320 ) , - .prog_clk_1_W_in ( p1399 ) , .prog_clk_1_E_in ( p1737 ) , + .prog_clk_1_W_in ( p1162 ) , .prog_clk_1_E_in ( p718 ) , .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_7321 ) , .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_7322 ) , .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_7323 ) , .prog_clk_2_W_in ( prog_clk_2_wires[114] ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_7324 ) , - .prog_clk_2_E_out ( prog_clk_2_wires[113] ) , .prog_clk_3_W_in ( p1413 ) , - .prog_clk_3_E_in ( p1339 ) , + .prog_clk_2_E_out ( prog_clk_2_wires[113] ) , .prog_clk_3_W_in ( p1162 ) , + .prog_clk_3_E_in ( p722 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_7325 ) , - .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_7326 ) , .clk_1_W_in ( p1453 ) , - .clk_1_E_in ( p2066 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_7327 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_7326 ) , .clk_1_W_in ( p1162 ) , + .clk_1_E_in ( p1848 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_7327 ) , .clk_1_S_out ( SYNOPSYS_UNCONNECTED_7328 ) , .clk_2_E_in ( SYNOPSYS_UNCONNECTED_7329 ) , .clk_2_W_in ( clk_2_wires[114] ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7330 ) , - .clk_2_E_out ( clk_2_wires[113] ) , .clk_3_W_in ( p1413 ) , - .clk_3_E_in ( p1724 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7331 ) , + .clk_2_E_out ( clk_2_wires[113] ) , .clk_3_W_in ( p1851 ) , + .clk_3_E_in ( p1764 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7331 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7332 ) ) ; cbx_1__1_ cbx_11__3_ ( .pReset ( { SYNOPSYS_UNCONNECTED_7333 } ) , @@ -127194,7 +131733,7 @@ cbx_1__1_ cbx_11__3_ ( .bottom_grid_pin_14_ ( cbx_1__1__112_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__112_bottom_grid_pin_15_ ) , .ccff_tail ( cbx_1__1__112_ccff_tail ) , .SC_IN_TOP ( scff_Wires[283] ) , - .SC_OUT_BOT ( scff_Wires[284] ) , .SC_IN_BOT ( p1603 ) , + .SC_OUT_BOT ( scff_Wires[284] ) , .SC_IN_BOT ( p2022 ) , .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_7334 ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[112] ) , .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[112] ) , @@ -127209,19 +131748,19 @@ cbx_1__1_ cbx_11__3_ ( .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_7338 ) , .prog_clk_1_E_in ( prog_clk_1_wires[219] ) , .prog_clk_1_N_out ( prog_clk_1_wires[220] ) , - .prog_clk_1_S_out ( prog_clk_1_wires[221] ) , .prog_clk_2_E_in ( p2507 ) , - .prog_clk_2_W_in ( p1204 ) , + .prog_clk_1_S_out ( prog_clk_1_wires[221] ) , .prog_clk_2_E_in ( p2236 ) , + .prog_clk_2_W_in ( p3034 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_7339 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_7340 ) , - .prog_clk_3_W_in ( p2953 ) , .prog_clk_3_E_in ( p607 ) , + .prog_clk_3_W_in ( p3143 ) , .prog_clk_3_E_in ( p2181 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_7341 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_7342 ) , .clk_1_W_in ( SYNOPSYS_UNCONNECTED_7343 ) , .clk_1_E_in ( clk_1_wires[219] ) , .clk_1_N_out ( clk_1_wires[220] ) , - .clk_1_S_out ( clk_1_wires[221] ) , .clk_2_E_in ( p2507 ) , - .clk_2_W_in ( p2913 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7344 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7345 ) , .clk_3_W_in ( p1888 ) , - .clk_3_E_in ( p2383 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7346 ) , + .clk_1_S_out ( clk_1_wires[221] ) , .clk_2_E_in ( p2042 ) , + .clk_2_W_in ( p2734 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7344 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7345 ) , .clk_3_W_in ( p2676 ) , + .clk_3_E_in ( p1786 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7346 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7347 ) ) ; cbx_1__1_ cbx_11__4_ ( .pReset ( { SYNOPSYS_UNCONNECTED_7348 } ) , @@ -127247,7 +131786,7 @@ cbx_1__1_ cbx_11__4_ ( .bottom_grid_pin_14_ ( cbx_1__1__113_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__113_bottom_grid_pin_15_ ) , .ccff_tail ( cbx_1__1__113_ccff_tail ) , .SC_IN_TOP ( scff_Wires[281] ) , - .SC_OUT_BOT ( scff_Wires[282] ) , .SC_IN_BOT ( p1143 ) , + .SC_OUT_BOT ( scff_Wires[282] ) , .SC_IN_BOT ( p1974 ) , .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_7349 ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[113] ) , .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[113] ) , @@ -127259,23 +131798,23 @@ cbx_1__1_ cbx_11__4_ ( .pReset_S_out ( pResetWires[251] ) , .pReset_E_out ( pResetWires[250] ) , .prog_clk_0_N_in ( prog_clk_0_wires[417] ) , .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_7352 ) , - .prog_clk_1_W_in ( p1504 ) , .prog_clk_1_E_in ( p2380 ) , + .prog_clk_1_W_in ( p1333 ) , .prog_clk_1_E_in ( p1835 ) , .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_7353 ) , .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_7354 ) , .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_7355 ) , .prog_clk_2_W_in ( prog_clk_2_wires[119] ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_7356 ) , - .prog_clk_2_E_out ( prog_clk_2_wires[118] ) , .prog_clk_3_W_in ( p1306 ) , - .prog_clk_3_E_in ( p541 ) , + .prog_clk_2_E_out ( prog_clk_2_wires[118] ) , .prog_clk_3_W_in ( p1243 ) , + .prog_clk_3_E_in ( p1242 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_7357 ) , - .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_7358 ) , .clk_1_W_in ( p1473 ) , - .clk_1_E_in ( p1023 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_7359 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_7358 ) , .clk_1_W_in ( p1243 ) , + .clk_1_E_in ( p2477 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_7359 ) , .clk_1_S_out ( SYNOPSYS_UNCONNECTED_7360 ) , .clk_2_E_in ( SYNOPSYS_UNCONNECTED_7361 ) , .clk_2_W_in ( clk_2_wires[119] ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7362 ) , - .clk_2_E_out ( clk_2_wires[118] ) , .clk_3_W_in ( p1306 ) , - .clk_3_E_in ( p2276 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7363 ) , + .clk_2_E_out ( clk_2_wires[118] ) , .clk_3_W_in ( p1243 ) , + .clk_3_E_in ( p2457 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7363 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7364 ) ) ; cbx_1__1_ cbx_11__5_ ( .pReset ( { SYNOPSYS_UNCONNECTED_7365 } ) , @@ -127301,7 +131840,7 @@ cbx_1__1_ cbx_11__5_ ( .bottom_grid_pin_14_ ( cbx_1__1__114_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__114_bottom_grid_pin_15_ ) , .ccff_tail ( cbx_1__1__114_ccff_tail ) , .SC_IN_TOP ( scff_Wires[279] ) , - .SC_OUT_BOT ( scff_Wires[280] ) , .SC_IN_BOT ( p2144 ) , + .SC_OUT_BOT ( scff_Wires[280] ) , .SC_IN_BOT ( p1372 ) , .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_7366 ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[114] ) , .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[114] ) , @@ -127316,19 +131855,19 @@ cbx_1__1_ cbx_11__5_ ( .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_7370 ) , .prog_clk_1_E_in ( prog_clk_1_wires[226] ) , .prog_clk_1_N_out ( prog_clk_1_wires[227] ) , - .prog_clk_1_S_out ( prog_clk_1_wires[228] ) , .prog_clk_2_E_in ( p2450 ) , - .prog_clk_2_W_in ( p1252 ) , + .prog_clk_1_S_out ( prog_clk_1_wires[228] ) , .prog_clk_2_E_in ( p3117 ) , + .prog_clk_2_W_in ( p3364 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_7371 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_7372 ) , - .prog_clk_3_W_in ( p2925 ) , .prog_clk_3_E_in ( p974 ) , + .prog_clk_3_W_in ( p3420 ) , .prog_clk_3_E_in ( p3094 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_7373 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_7374 ) , .clk_1_W_in ( SYNOPSYS_UNCONNECTED_7375 ) , .clk_1_E_in ( clk_1_wires[226] ) , .clk_1_N_out ( clk_1_wires[227] ) , - .clk_1_S_out ( clk_1_wires[228] ) , .clk_2_E_in ( p2450 ) , - .clk_2_W_in ( p2920 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7376 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7377 ) , .clk_3_W_in ( p2663 ) , - .clk_3_E_in ( p2377 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7378 ) , + .clk_1_S_out ( clk_1_wires[228] ) , .clk_2_E_in ( p1998 ) , + .clk_2_W_in ( p1402 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7376 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7377 ) , .clk_3_W_in ( p1045 ) , + .clk_3_E_in ( p1830 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7378 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7379 ) ) ; cbx_1__1_ cbx_11__6_ ( .pReset ( { SYNOPSYS_UNCONNECTED_7380 } ) , @@ -127354,7 +131893,7 @@ cbx_1__1_ cbx_11__6_ ( .bottom_grid_pin_14_ ( cbx_1__1__115_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__115_bottom_grid_pin_15_ ) , .ccff_tail ( cbx_1__1__115_ccff_tail ) , .SC_IN_TOP ( scff_Wires[277] ) , - .SC_OUT_BOT ( scff_Wires[278] ) , .SC_IN_BOT ( p1102 ) , + .SC_OUT_BOT ( scff_Wires[278] ) , .SC_IN_BOT ( p1585 ) , .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_7381 ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[115] ) , .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[115] ) , @@ -127366,20 +131905,20 @@ cbx_1__1_ cbx_11__6_ ( .pReset_S_out ( pResetWires[349] ) , .pReset_E_out ( pResetWires[348] ) , .prog_clk_0_N_in ( prog_clk_0_wires[423] ) , .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_7384 ) , - .prog_clk_1_W_in ( p2434 ) , .prog_clk_1_E_in ( p770 ) , + .prog_clk_1_W_in ( p1376 ) , .prog_clk_1_E_in ( p614 ) , .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_7385 ) , .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_7386 ) , - .prog_clk_2_E_in ( p2512 ) , .prog_clk_2_W_in ( p2348 ) , + .prog_clk_2_E_in ( p1896 ) , .prog_clk_2_W_in ( p2743 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_7387 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_7388 ) , - .prog_clk_3_W_in ( p1881 ) , .prog_clk_3_E_in ( p1375 ) , + .prog_clk_3_W_in ( p2776 ) , .prog_clk_3_E_in ( p1834 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_7389 ) , - .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_7390 ) , .clk_1_W_in ( p1946 ) , - .clk_1_E_in ( p464 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_7391 ) , - .clk_1_S_out ( SYNOPSYS_UNCONNECTED_7392 ) , .clk_2_E_in ( p2512 ) , - .clk_2_W_in ( p2757 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7393 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7394 ) , .clk_3_W_in ( p2820 ) , - .clk_3_E_in ( p2375 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7395 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_7390 ) , .clk_1_W_in ( p2799 ) , + .clk_1_E_in ( p1135 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_7391 ) , + .clk_1_S_out ( SYNOPSYS_UNCONNECTED_7392 ) , .clk_2_E_in ( p1983 ) , + .clk_2_W_in ( p2915 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7393 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7394 ) , .clk_3_W_in ( p2977 ) , + .clk_3_E_in ( p1660 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7395 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7396 ) ) ; cbx_1__1_ cbx_11__7_ ( .pReset ( { SYNOPSYS_UNCONNECTED_7397 } ) , @@ -127405,7 +131944,7 @@ cbx_1__1_ cbx_11__7_ ( .bottom_grid_pin_14_ ( cbx_1__1__116_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__116_bottom_grid_pin_15_ ) , .ccff_tail ( cbx_1__1__116_ccff_tail ) , .SC_IN_TOP ( scff_Wires[275] ) , - .SC_OUT_BOT ( scff_Wires[276] ) , .SC_IN_BOT ( p1427 ) , + .SC_OUT_BOT ( scff_Wires[276] ) , .SC_IN_BOT ( p1355 ) , .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_7398 ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[116] ) , .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[116] ) , @@ -127420,19 +131959,19 @@ cbx_1__1_ cbx_11__7_ ( .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_7402 ) , .prog_clk_1_E_in ( prog_clk_1_wires[233] ) , .prog_clk_1_N_out ( prog_clk_1_wires[234] ) , - .prog_clk_1_S_out ( prog_clk_1_wires[235] ) , .prog_clk_2_E_in ( p1892 ) , - .prog_clk_2_W_in ( p1177 ) , + .prog_clk_1_S_out ( prog_clk_1_wires[235] ) , .prog_clk_2_E_in ( p3339 ) , + .prog_clk_2_W_in ( p2860 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_7403 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_7404 ) , - .prog_clk_3_W_in ( p3250 ) , .prog_clk_3_E_in ( p1146 ) , + .prog_clk_3_W_in ( p2947 ) , .prog_clk_3_E_in ( p3318 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_7405 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_7406 ) , .clk_1_W_in ( SYNOPSYS_UNCONNECTED_7407 ) , .clk_1_E_in ( clk_1_wires[233] ) , .clk_1_N_out ( clk_1_wires[234] ) , - .clk_1_S_out ( clk_1_wires[235] ) , .clk_2_E_in ( p1892 ) , - .clk_2_W_in ( p3236 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7408 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7409 ) , .clk_3_W_in ( p2686 ) , - .clk_3_E_in ( p1781 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7410 ) , + .clk_1_S_out ( clk_1_wires[235] ) , .clk_2_E_in ( p2590 ) , + .clk_2_W_in ( p3445 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7408 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7409 ) , .clk_3_W_in ( p3467 ) , + .clk_3_E_in ( p2500 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7410 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7411 ) ) ; cbx_1__1_ cbx_11__8_ ( .pReset ( { SYNOPSYS_UNCONNECTED_7412 } ) , @@ -127458,7 +131997,7 @@ cbx_1__1_ cbx_11__8_ ( .bottom_grid_pin_14_ ( cbx_1__1__117_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__117_bottom_grid_pin_15_ ) , .ccff_tail ( cbx_1__1__117_ccff_tail ) , .SC_IN_TOP ( scff_Wires[273] ) , - .SC_OUT_BOT ( scff_Wires[274] ) , .SC_IN_BOT ( p1601 ) , + .SC_OUT_BOT ( scff_Wires[274] ) , .SC_IN_BOT ( p2282 ) , .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_7413 ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[117] ) , .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[117] ) , @@ -127470,23 +132009,23 @@ cbx_1__1_ cbx_11__8_ ( .pReset_S_out ( pResetWires[447] ) , .pReset_E_out ( pResetWires[446] ) , .prog_clk_0_N_in ( prog_clk_0_wires[429] ) , .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_7416 ) , - .prog_clk_1_W_in ( p444 ) , .prog_clk_1_E_in ( p2358 ) , + .prog_clk_1_W_in ( p1620 ) , .prog_clk_1_E_in ( p2110 ) , .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_7417 ) , .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_7418 ) , .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_7419 ) , .prog_clk_2_W_in ( prog_clk_2_wires[126] ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_7420 ) , - .prog_clk_2_E_out ( prog_clk_2_wires[125] ) , .prog_clk_3_W_in ( p1460 ) , - .prog_clk_3_E_in ( p316 ) , + .prog_clk_2_E_out ( prog_clk_2_wires[125] ) , .prog_clk_3_W_in ( p1339 ) , + .prog_clk_3_E_in ( p1186 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_7421 ) , - .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_7422 ) , .clk_1_W_in ( p1284 ) , - .clk_1_E_in ( p423 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_7423 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_7422 ) , .clk_1_W_in ( p1104 ) , + .clk_1_E_in ( p1809 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_7423 ) , .clk_1_S_out ( SYNOPSYS_UNCONNECTED_7424 ) , .clk_2_E_in ( SYNOPSYS_UNCONNECTED_7425 ) , .clk_2_W_in ( clk_2_wires[126] ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7426 ) , - .clk_2_E_out ( clk_2_wires[125] ) , .clk_3_W_in ( p1460 ) , - .clk_3_E_in ( p2345 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7427 ) , + .clk_2_E_out ( clk_2_wires[125] ) , .clk_3_W_in ( p1339 ) , + .clk_3_E_in ( p1720 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7427 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7428 ) ) ; cbx_1__1_ cbx_11__9_ ( .pReset ( { SYNOPSYS_UNCONNECTED_7429 } ) , @@ -127512,7 +132051,7 @@ cbx_1__1_ cbx_11__9_ ( .bottom_grid_pin_14_ ( cbx_1__1__118_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__118_bottom_grid_pin_15_ ) , .ccff_tail ( cbx_1__1__118_ccff_tail ) , .SC_IN_TOP ( scff_Wires[271] ) , - .SC_OUT_BOT ( scff_Wires[272] ) , .SC_IN_BOT ( p1009 ) , + .SC_OUT_BOT ( scff_Wires[272] ) , .SC_IN_BOT ( p1377 ) , .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_7430 ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[118] ) , .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[118] ) , @@ -127527,19 +132066,19 @@ cbx_1__1_ cbx_11__9_ ( .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_7434 ) , .prog_clk_1_E_in ( prog_clk_1_wires[240] ) , .prog_clk_1_N_out ( prog_clk_1_wires[241] ) , - .prog_clk_1_S_out ( prog_clk_1_wires[242] ) , .prog_clk_2_E_in ( p1777 ) , - .prog_clk_2_W_in ( p1240 ) , + .prog_clk_1_S_out ( prog_clk_1_wires[242] ) , .prog_clk_2_E_in ( p2328 ) , + .prog_clk_2_W_in ( p3307 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_7435 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_7436 ) , - .prog_clk_3_W_in ( p3398 ) , .prog_clk_3_E_in ( p1381 ) , + .prog_clk_3_W_in ( p3352 ) , .prog_clk_3_E_in ( p2065 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_7437 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_7438 ) , .clk_1_W_in ( SYNOPSYS_UNCONNECTED_7439 ) , .clk_1_E_in ( clk_1_wires[240] ) , .clk_1_N_out ( clk_1_wires[241] ) , - .clk_1_S_out ( clk_1_wires[242] ) , .clk_2_E_in ( p1777 ) , - .clk_2_W_in ( p3385 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7440 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7441 ) , .clk_3_W_in ( p2521 ) , - .clk_3_E_in ( p1626 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7442 ) , + .clk_1_S_out ( clk_1_wires[242] ) , .clk_2_E_in ( p2595 ) , + .clk_2_W_in ( p3221 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7440 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7441 ) , .clk_3_W_in ( p3230 ) , + .clk_3_E_in ( p2482 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7442 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7443 ) ) ; cbx_1__1_ cbx_11__10_ ( .pReset ( { SYNOPSYS_UNCONNECTED_7444 } ) , @@ -127565,7 +132104,7 @@ cbx_1__1_ cbx_11__10_ ( .bottom_grid_pin_14_ ( cbx_1__1__119_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__119_bottom_grid_pin_15_ ) , .ccff_tail ( cbx_1__1__119_ccff_tail ) , .SC_IN_TOP ( scff_Wires[269] ) , - .SC_OUT_BOT ( scff_Wires[270] ) , .SC_IN_BOT ( p1077 ) , + .SC_OUT_BOT ( scff_Wires[270] ) , .SC_IN_BOT ( p1987 ) , .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_7445 ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[119] ) , .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[119] ) , @@ -127577,23 +132116,23 @@ cbx_1__1_ cbx_11__10_ ( .pReset_S_out ( pResetWires[545] ) , .pReset_E_out ( pResetWires[544] ) , .prog_clk_0_N_in ( prog_clk_0_wires[435] ) , .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_7448 ) , - .prog_clk_1_W_in ( p1874 ) , .prog_clk_1_E_in ( p497 ) , + .prog_clk_1_W_in ( p1298 ) , .prog_clk_1_E_in ( p1756 ) , .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_7449 ) , .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_7450 ) , .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_7451 ) , .prog_clk_2_W_in ( prog_clk_2_wires[133] ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_7452 ) , - .prog_clk_2_E_out ( prog_clk_2_wires[132] ) , .prog_clk_3_W_in ( p1874 ) , - .prog_clk_3_E_in ( p961 ) , + .prog_clk_2_E_out ( prog_clk_2_wires[132] ) , .prog_clk_3_W_in ( p1109 ) , + .prog_clk_3_E_in ( p601 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_7453 ) , - .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_7454 ) , .clk_1_W_in ( p1837 ) , - .clk_1_E_in ( p722 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_7455 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_7454 ) , .clk_1_W_in ( p1109 ) , + .clk_1_E_in ( p1820 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_7455 ) , .clk_1_S_out ( SYNOPSYS_UNCONNECTED_7456 ) , .clk_2_E_in ( SYNOPSYS_UNCONNECTED_7457 ) , .clk_2_W_in ( clk_2_wires[133] ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7458 ) , - .clk_2_E_out ( clk_2_wires[132] ) , .clk_3_W_in ( p1874 ) , - .clk_3_E_in ( p1481 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7459 ) , + .clk_2_E_out ( clk_2_wires[132] ) , .clk_3_W_in ( p1109 ) , + .clk_3_E_in ( p1795 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7459 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7460 ) ) ; cbx_1__1_ cbx_11__11_ ( .pReset ( { SYNOPSYS_UNCONNECTED_7461 } ) , @@ -127619,7 +132158,7 @@ cbx_1__1_ cbx_11__11_ ( .bottom_grid_pin_14_ ( cbx_1__1__120_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__120_bottom_grid_pin_15_ ) , .ccff_tail ( cbx_1__1__120_ccff_tail ) , .SC_IN_TOP ( scff_Wires[267] ) , - .SC_OUT_BOT ( scff_Wires[268] ) , .SC_IN_BOT ( p1300 ) , + .SC_OUT_BOT ( scff_Wires[268] ) , .SC_IN_BOT ( p1413 ) , .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_7462 ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[120] ) , .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[120] ) , @@ -127634,19 +132173,19 @@ cbx_1__1_ cbx_11__11_ ( .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_7466 ) , .prog_clk_1_E_in ( prog_clk_1_wires[247] ) , .prog_clk_1_N_out ( prog_clk_1_wires[248] ) , - .prog_clk_1_S_out ( prog_clk_1_wires[249] ) , .prog_clk_2_E_in ( p2107 ) , - .prog_clk_2_W_in ( p718 ) , + .prog_clk_1_S_out ( prog_clk_1_wires[249] ) , .prog_clk_2_E_in ( p3145 ) , + .prog_clk_2_W_in ( p1832 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_7467 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_7468 ) , - .prog_clk_3_W_in ( p1894 ) , .prog_clk_3_E_in ( p1232 ) , + .prog_clk_3_W_in ( p1889 ) , .prog_clk_3_E_in ( p3096 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_7469 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_7470 ) , .clk_1_W_in ( SYNOPSYS_UNCONNECTED_7471 ) , .clk_1_E_in ( clk_1_wires[247] ) , .clk_1_N_out ( clk_1_wires[248] ) , - .clk_1_S_out ( clk_1_wires[249] ) , .clk_2_E_in ( p2107 ) , - .clk_2_W_in ( p2369 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7472 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7473 ) , .clk_3_W_in ( p2428 ) , - .clk_3_E_in ( p2086 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7474 ) , + .clk_1_S_out ( clk_1_wires[249] ) , .clk_2_E_in ( p2534 ) , + .clk_2_W_in ( p3546 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7472 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7473 ) , .clk_3_W_in ( p3560 ) , + .clk_3_E_in ( p2502 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7474 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7475 ) ) ; cbx_1__1_ cbx_12__1_ ( .pReset ( { SYNOPSYS_UNCONNECTED_7476 } ) , @@ -127671,7 +132210,7 @@ cbx_1__1_ cbx_12__1_ ( .bottom_grid_pin_13_ ( cbx_1__1__121_bottom_grid_pin_13_ ) , .bottom_grid_pin_14_ ( cbx_1__1__121_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__121_bottom_grid_pin_15_ ) , - .ccff_tail ( cbx_1__1__121_ccff_tail ) , .SC_IN_TOP ( p1446 ) , + .ccff_tail ( cbx_1__1__121_ccff_tail ) , .SC_IN_TOP ( p1907 ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_7477 ) , .SC_IN_BOT ( scff_Wires[294] ) , .SC_OUT_TOP ( scff_Wires[295] ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[121] ) , @@ -127687,20 +132226,20 @@ cbx_1__1_ cbx_12__1_ ( .prog_clk_1_W_in ( prog_clk_1_wires[211] ) , .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_7481 ) , .prog_clk_1_N_out ( prog_clk_1_wires[215] ) , - .prog_clk_1_S_out ( prog_clk_1_wires[216] ) , .prog_clk_2_E_in ( p2185 ) , - .prog_clk_2_W_in ( p1323 ) , + .prog_clk_1_S_out ( prog_clk_1_wires[216] ) , .prog_clk_2_E_in ( p2764 ) , + .prog_clk_2_W_in ( p3033 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_7482 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_7483 ) , - .prog_clk_3_W_in ( p2325 ) , .prog_clk_3_E_in ( p1380 ) , + .prog_clk_3_W_in ( p3160 ) , .prog_clk_3_E_in ( p2728 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_7484 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_7485 ) , .clk_1_W_in ( clk_1_wires[211] ) , .clk_1_E_in ( SYNOPSYS_UNCONNECTED_7486 ) , .clk_1_N_out ( clk_1_wires[215] ) , .clk_1_S_out ( clk_1_wires[216] ) , - .clk_2_E_in ( p2185 ) , .clk_2_W_in ( p2401 ) , + .clk_2_E_in ( p2533 ) , .clk_2_W_in ( p3313 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7487 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7488 ) , .clk_3_W_in ( p1546 ) , - .clk_3_E_in ( p2054 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7489 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7488 ) , .clk_3_W_in ( p3319 ) , + .clk_3_E_in ( p2441 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7489 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7490 ) ) ; cbx_1__1_ cbx_12__2_ ( .pReset ( { SYNOPSYS_UNCONNECTED_7491 } ) , @@ -127725,7 +132264,7 @@ cbx_1__1_ cbx_12__2_ ( .bottom_grid_pin_13_ ( cbx_1__1__122_bottom_grid_pin_13_ ) , .bottom_grid_pin_14_ ( cbx_1__1__122_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__122_bottom_grid_pin_15_ ) , - .ccff_tail ( cbx_1__1__122_ccff_tail ) , .SC_IN_TOP ( p1593 ) , + .ccff_tail ( cbx_1__1__122_ccff_tail ) , .SC_IN_TOP ( p1965 ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_7492 ) , .SC_IN_BOT ( scff_Wires[296] ) , .SC_OUT_TOP ( scff_Wires[297] ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[122] ) , @@ -127738,20 +132277,20 @@ cbx_1__1_ cbx_12__2_ ( .pReset_S_out ( pResetWires[157] ) , .pReset_E_out ( pResetWires[156] ) , .prog_clk_0_N_in ( prog_clk_0_wires[449] ) , .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_7495 ) , - .prog_clk_1_W_in ( p2188 ) , .prog_clk_1_E_in ( p1117 ) , + .prog_clk_1_W_in ( p1226 ) , .prog_clk_1_E_in ( p325 ) , .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_7496 ) , .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_7497 ) , - .prog_clk_2_E_in ( p1774 ) , .prog_clk_2_W_in ( p2085 ) , + .prog_clk_2_E_in ( p1944 ) , .prog_clk_2_W_in ( p2430 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_7498 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_7499 ) , - .prog_clk_3_W_in ( p2464 ) , .prog_clk_3_E_in ( p1582 ) , + .prog_clk_3_W_in ( p2517 ) , .prog_clk_3_E_in ( p1708 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_7500 ) , - .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_7501 ) , .clk_1_W_in ( p1093 ) , - .clk_1_E_in ( p1000 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_7502 ) , - .clk_1_S_out ( SYNOPSYS_UNCONNECTED_7503 ) , .clk_2_E_in ( p1774 ) , - .clk_2_W_in ( p3037 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7504 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7505 ) , .clk_3_W_in ( p3111 ) , - .clk_3_E_in ( p1707 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7506 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_7501 ) , .clk_1_W_in ( p1891 ) , + .clk_1_E_in ( p586 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_7502 ) , + .clk_1_S_out ( SYNOPSYS_UNCONNECTED_7503 ) , .clk_2_E_in ( p2741 ) , + .clk_2_W_in ( p3070 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7504 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7505 ) , .clk_3_W_in ( p3115 ) , + .clk_3_E_in ( p2684 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7506 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7507 ) ) ; cbx_1__1_ cbx_12__3_ ( .pReset ( { SYNOPSYS_UNCONNECTED_7508 } ) , @@ -127776,7 +132315,7 @@ cbx_1__1_ cbx_12__3_ ( .bottom_grid_pin_13_ ( cbx_1__1__123_bottom_grid_pin_13_ ) , .bottom_grid_pin_14_ ( cbx_1__1__123_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__123_bottom_grid_pin_15_ ) , - .ccff_tail ( cbx_1__1__123_ccff_tail ) , .SC_IN_TOP ( p1515 ) , + .ccff_tail ( cbx_1__1__123_ccff_tail ) , .SC_IN_TOP ( p1527 ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_7509 ) , .SC_IN_BOT ( scff_Wires[298] ) , .SC_OUT_TOP ( scff_Wires[299] ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[123] ) , @@ -127792,20 +132331,20 @@ cbx_1__1_ cbx_12__3_ ( .prog_clk_1_W_in ( prog_clk_1_wires[218] ) , .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_7513 ) , .prog_clk_1_N_out ( prog_clk_1_wires[222] ) , - .prog_clk_1_S_out ( prog_clk_1_wires[223] ) , .prog_clk_2_E_in ( p1458 ) , - .prog_clk_2_W_in ( p970 ) , + .prog_clk_1_S_out ( prog_clk_1_wires[223] ) , .prog_clk_2_E_in ( p2969 ) , + .prog_clk_2_W_in ( p3481 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_7514 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_7515 ) , - .prog_clk_3_W_in ( p3450 ) , .prog_clk_3_E_in ( p935 ) , + .prog_clk_3_W_in ( p3500 ) , .prog_clk_3_E_in ( p2903 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_7516 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_7517 ) , .clk_1_W_in ( clk_1_wires[218] ) , .clk_1_E_in ( SYNOPSYS_UNCONNECTED_7518 ) , .clk_1_N_out ( clk_1_wires[222] ) , .clk_1_S_out ( clk_1_wires[223] ) , - .clk_2_E_in ( p1458 ) , .clk_2_W_in ( p3442 ) , + .clk_2_E_in ( p1884 ) , .clk_2_W_in ( p2494 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7519 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7520 ) , .clk_3_W_in ( p2793 ) , - .clk_3_E_in ( p604 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7521 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7520 ) , .clk_3_W_in ( p2592 ) , + .clk_3_E_in ( p1839 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7521 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7522 ) ) ; cbx_1__1_ cbx_12__4_ ( .pReset ( { SYNOPSYS_UNCONNECTED_7523 } ) , @@ -127830,7 +132369,7 @@ cbx_1__1_ cbx_12__4_ ( .bottom_grid_pin_13_ ( cbx_1__1__124_bottom_grid_pin_13_ ) , .bottom_grid_pin_14_ ( cbx_1__1__124_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__124_bottom_grid_pin_15_ ) , - .ccff_tail ( cbx_1__1__124_ccff_tail ) , .SC_IN_TOP ( p1862 ) , + .ccff_tail ( cbx_1__1__124_ccff_tail ) , .SC_IN_TOP ( p1939 ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_7524 ) , .SC_IN_BOT ( scff_Wires[300] ) , .SC_OUT_TOP ( scff_Wires[301] ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[124] ) , @@ -127843,20 +132382,20 @@ cbx_1__1_ cbx_12__4_ ( .pReset_S_out ( pResetWires[255] ) , .pReset_E_out ( pResetWires[254] ) , .prog_clk_0_N_in ( prog_clk_0_wires[455] ) , .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_7527 ) , - .prog_clk_1_W_in ( p2179 ) , .prog_clk_1_E_in ( p919 ) , + .prog_clk_1_W_in ( p1382 ) , .prog_clk_1_E_in ( p482 ) , .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_7528 ) , .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_7529 ) , - .prog_clk_2_E_in ( p1877 ) , .prog_clk_2_W_in ( p2101 ) , + .prog_clk_2_E_in ( p3018 ) , .prog_clk_2_W_in ( p3089 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_7530 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_7531 ) , - .prog_clk_3_W_in ( p3239 ) , .prog_clk_3_E_in ( p1757 ) , + .prog_clk_3_W_in ( p3125 ) , .prog_clk_3_E_in ( p2927 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_7532 ) , - .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_7533 ) , .clk_1_W_in ( p1542 ) , - .clk_1_E_in ( p517 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_7534 ) , - .clk_1_S_out ( SYNOPSYS_UNCONNECTED_7535 ) , .clk_2_E_in ( p1877 ) , - .clk_2_W_in ( p3210 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7536 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7537 ) , .clk_3_W_in ( p2855 ) , - .clk_3_E_in ( p1664 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7538 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_7533 ) , .clk_1_W_in ( p2349 ) , + .clk_1_E_in ( p547 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_7534 ) , + .clk_1_S_out ( SYNOPSYS_UNCONNECTED_7535 ) , .clk_2_E_in ( p2844 ) , + .clk_2_W_in ( p2889 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7536 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7537 ) , .clk_3_W_in ( p2955 ) , + .clk_3_E_in ( p2710 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7538 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7539 ) ) ; cbx_1__1_ cbx_12__5_ ( .pReset ( { SYNOPSYS_UNCONNECTED_7540 } ) , @@ -127881,7 +132420,7 @@ cbx_1__1_ cbx_12__5_ ( .bottom_grid_pin_13_ ( cbx_1__1__125_bottom_grid_pin_13_ ) , .bottom_grid_pin_14_ ( cbx_1__1__125_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__125_bottom_grid_pin_15_ ) , - .ccff_tail ( cbx_1__1__125_ccff_tail ) , .SC_IN_TOP ( p2132 ) , + .ccff_tail ( cbx_1__1__125_ccff_tail ) , .SC_IN_TOP ( p1904 ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_7541 ) , .SC_IN_BOT ( scff_Wires[302] ) , .SC_OUT_TOP ( scff_Wires[303] ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[125] ) , @@ -127897,20 +132436,20 @@ cbx_1__1_ cbx_12__5_ ( .prog_clk_1_W_in ( prog_clk_1_wires[225] ) , .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_7545 ) , .prog_clk_1_N_out ( prog_clk_1_wires[229] ) , - .prog_clk_1_S_out ( prog_clk_1_wires[230] ) , .prog_clk_2_E_in ( p2651 ) , - .prog_clk_2_W_in ( p548 ) , + .prog_clk_1_S_out ( prog_clk_1_wires[230] ) , .prog_clk_2_E_in ( p3416 ) , + .prog_clk_2_W_in ( p3567 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_7546 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_7547 ) , - .prog_clk_3_W_in ( p3314 ) , .prog_clk_3_E_in ( p2040 ) , + .prog_clk_3_W_in ( p3576 ) , .prog_clk_3_E_in ( p3388 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_7548 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_7549 ) , .clk_1_W_in ( clk_1_wires[225] ) , .clk_1_E_in ( SYNOPSYS_UNCONNECTED_7550 ) , .clk_1_N_out ( clk_1_wires[229] ) , .clk_1_S_out ( clk_1_wires[230] ) , - .clk_2_E_in ( p2651 ) , .clk_2_W_in ( p3303 ) , + .clk_2_E_in ( p2800 ) , .clk_2_W_in ( p1823 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7551 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7552 ) , .clk_3_W_in ( p2812 ) , - .clk_3_E_in ( p2576 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7553 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7552 ) , .clk_3_W_in ( p2016 ) , + .clk_3_E_in ( p2730 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7553 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7554 ) ) ; cbx_1__1_ cbx_12__6_ ( .pReset ( { SYNOPSYS_UNCONNECTED_7555 } ) , @@ -127935,7 +132474,7 @@ cbx_1__1_ cbx_12__6_ ( .bottom_grid_pin_13_ ( cbx_1__1__126_bottom_grid_pin_13_ ) , .bottom_grid_pin_14_ ( cbx_1__1__126_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__126_bottom_grid_pin_15_ ) , - .ccff_tail ( cbx_1__1__126_ccff_tail ) , .SC_IN_TOP ( p2124 ) , + .ccff_tail ( cbx_1__1__126_ccff_tail ) , .SC_IN_TOP ( p1632 ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_7556 ) , .SC_IN_BOT ( scff_Wires[304] ) , .SC_OUT_TOP ( scff_Wires[305] ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[126] ) , @@ -127948,20 +132487,20 @@ cbx_1__1_ cbx_12__6_ ( .pReset_S_out ( pResetWires[353] ) , .pReset_E_out ( pResetWires[352] ) , .prog_clk_0_N_in ( prog_clk_0_wires[461] ) , .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_7559 ) , - .prog_clk_1_W_in ( p2411 ) , .prog_clk_1_E_in ( p9 ) , + .prog_clk_1_W_in ( p1327 ) , .prog_clk_1_E_in ( p861 ) , .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_7560 ) , .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_7561 ) , - .prog_clk_2_E_in ( p1692 ) , .prog_clk_2_W_in ( p2370 ) , + .prog_clk_2_E_in ( p2345 ) , .prog_clk_2_W_in ( p3082 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_7562 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_7563 ) , - .prog_clk_3_W_in ( p3405 ) , .prog_clk_3_E_in ( p2064 ) , + .prog_clk_3_W_in ( p3124 ) , .prog_clk_3_E_in ( p2180 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_7564 ) , - .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_7565 ) , .clk_1_W_in ( p1561 ) , - .clk_1_E_in ( p418 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_7566 ) , - .clk_1_S_out ( SYNOPSYS_UNCONNECTED_7567 ) , .clk_2_E_in ( p1692 ) , - .clk_2_W_in ( p3383 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7568 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7569 ) , .clk_3_W_in ( p3067 ) , - .clk_3_E_in ( p1745 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7570 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_7565 ) , .clk_1_W_in ( p1209 ) , + .clk_1_E_in ( p980 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_7566 ) , + .clk_1_S_out ( SYNOPSYS_UNCONNECTED_7567 ) , .clk_2_E_in ( p2563 ) , + .clk_2_W_in ( p2918 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7568 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7569 ) , .clk_3_W_in ( p2995 ) , + .clk_3_E_in ( p2463 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7570 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7571 ) ) ; cbx_1__1_ cbx_12__7_ ( .pReset ( { SYNOPSYS_UNCONNECTED_7572 } ) , @@ -127986,7 +132525,7 @@ cbx_1__1_ cbx_12__7_ ( .bottom_grid_pin_13_ ( cbx_1__1__127_bottom_grid_pin_13_ ) , .bottom_grid_pin_14_ ( cbx_1__1__127_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__127_bottom_grid_pin_15_ ) , - .ccff_tail ( cbx_1__1__127_ccff_tail ) , .SC_IN_TOP ( p2255 ) , + .ccff_tail ( cbx_1__1__127_ccff_tail ) , .SC_IN_TOP ( p2277 ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_7573 ) , .SC_IN_BOT ( scff_Wires[306] ) , .SC_OUT_TOP ( scff_Wires[307] ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[127] ) , @@ -128002,20 +132541,20 @@ cbx_1__1_ cbx_12__7_ ( .prog_clk_1_W_in ( prog_clk_1_wires[232] ) , .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_7577 ) , .prog_clk_1_N_out ( prog_clk_1_wires[236] ) , - .prog_clk_1_S_out ( prog_clk_1_wires[237] ) , .prog_clk_2_E_in ( p2798 ) , - .prog_clk_2_W_in ( p791 ) , + .prog_clk_1_S_out ( prog_clk_1_wires[237] ) , .prog_clk_2_E_in ( p2826 ) , + .prog_clk_2_W_in ( p2440 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_7578 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_7579 ) , - .prog_clk_3_W_in ( p2968 ) , .prog_clk_3_E_in ( p2006 ) , + .prog_clk_3_W_in ( p2497 ) , .prog_clk_3_E_in ( p2674 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_7580 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_7581 ) , .clk_1_W_in ( clk_1_wires[232] ) , .clk_1_E_in ( SYNOPSYS_UNCONNECTED_7582 ) , .clk_1_N_out ( clk_1_wires[236] ) , .clk_1_S_out ( clk_1_wires[237] ) , - .clk_2_E_in ( p2798 ) , .clk_2_W_in ( p2868 ) , + .clk_2_E_in ( p2366 ) , .clk_2_W_in ( p3311 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7583 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7584 ) , .clk_3_W_in ( p2687 ) , - .clk_3_E_in ( p2766 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7585 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7584 ) , .clk_3_W_in ( p3356 ) , + .clk_3_E_in ( p2192 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7585 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7586 ) ) ; cbx_1__1_ cbx_12__8_ ( .pReset ( { SYNOPSYS_UNCONNECTED_7587 } ) , @@ -128040,7 +132579,7 @@ cbx_1__1_ cbx_12__8_ ( .bottom_grid_pin_13_ ( cbx_1__1__128_bottom_grid_pin_13_ ) , .bottom_grid_pin_14_ ( cbx_1__1__128_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__128_bottom_grid_pin_15_ ) , - .ccff_tail ( cbx_1__1__128_ccff_tail ) , .SC_IN_TOP ( p2688 ) , + .ccff_tail ( cbx_1__1__128_ccff_tail ) , .SC_IN_TOP ( p1905 ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_7588 ) , .SC_IN_BOT ( scff_Wires[308] ) , .SC_OUT_TOP ( scff_Wires[309] ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[128] ) , @@ -128053,20 +132592,20 @@ cbx_1__1_ cbx_12__8_ ( .pReset_S_out ( pResetWires[451] ) , .pReset_E_out ( pResetWires[450] ) , .prog_clk_0_N_in ( prog_clk_0_wires[467] ) , .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_7591 ) , - .prog_clk_1_W_in ( p2508 ) , .prog_clk_1_E_in ( p771 ) , + .prog_clk_1_W_in ( p1165 ) , .prog_clk_1_E_in ( p960 ) , .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_7592 ) , .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_7593 ) , - .prog_clk_2_E_in ( p2432 ) , .prog_clk_2_W_in ( p2320 ) , + .prog_clk_2_E_in ( p2034 ) , .prog_clk_2_W_in ( p1729 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_7594 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_7595 ) , - .prog_clk_3_W_in ( p2713 ) , .prog_clk_3_E_in ( p2548 ) , + .prog_clk_3_W_in ( p1960 ) , .prog_clk_3_E_in ( p1707 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_7596 ) , - .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_7597 ) , .clk_1_W_in ( p1363 ) , - .clk_1_E_in ( p272 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_7598 ) , - .clk_1_S_out ( SYNOPSYS_UNCONNECTED_7599 ) , .clk_2_E_in ( p2432 ) , - .clk_2_W_in ( p2608 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7600 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7601 ) , .clk_3_W_in ( p2591 ) , - .clk_3_E_in ( p2353 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7602 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_7597 ) , .clk_1_W_in ( p1427 ) , + .clk_1_E_in ( p381 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_7598 ) , + .clk_1_S_out ( SYNOPSYS_UNCONNECTED_7599 ) , .clk_2_E_in ( p1647 ) , + .clk_2_W_in ( p3432 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7600 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7601 ) , .clk_3_W_in ( p3452 ) , + .clk_3_E_in ( p1115 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7602 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7603 ) ) ; cbx_1__1_ cbx_12__9_ ( .pReset ( { SYNOPSYS_UNCONNECTED_7604 } ) , @@ -128091,7 +132630,7 @@ cbx_1__1_ cbx_12__9_ ( .bottom_grid_pin_13_ ( cbx_1__1__129_bottom_grid_pin_13_ ) , .bottom_grid_pin_14_ ( cbx_1__1__129_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__129_bottom_grid_pin_15_ ) , - .ccff_tail ( cbx_1__1__129_ccff_tail ) , .SC_IN_TOP ( p1406 ) , + .ccff_tail ( cbx_1__1__129_ccff_tail ) , .SC_IN_TOP ( p1348 ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_7605 ) , .SC_IN_BOT ( scff_Wires[310] ) , .SC_OUT_TOP ( scff_Wires[311] ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[129] ) , @@ -128107,20 +132646,20 @@ cbx_1__1_ cbx_12__9_ ( .prog_clk_1_W_in ( prog_clk_1_wires[239] ) , .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_7609 ) , .prog_clk_1_N_out ( prog_clk_1_wires[243] ) , - .prog_clk_1_S_out ( prog_clk_1_wires[244] ) , .prog_clk_2_E_in ( p2190 ) , - .prog_clk_2_W_in ( p679 ) , + .prog_clk_1_S_out ( prog_clk_1_wires[244] ) , .prog_clk_2_E_in ( p1728 ) , + .prog_clk_2_W_in ( p3216 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_7610 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_7611 ) , - .prog_clk_3_W_in ( p2861 ) , .prog_clk_3_E_in ( p1264 ) , + .prog_clk_3_W_in ( p3276 ) , .prog_clk_3_E_in ( p1869 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_7612 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_7613 ) , .clk_1_W_in ( clk_1_wires[239] ) , .clk_1_E_in ( SYNOPSYS_UNCONNECTED_7614 ) , .clk_1_N_out ( clk_1_wires[243] ) , .clk_1_S_out ( clk_1_wires[244] ) , - .clk_2_E_in ( p2190 ) , .clk_2_W_in ( p2904 ) , + .clk_2_E_in ( p2547 ) , .clk_2_W_in ( p3068 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7615 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7616 ) , .clk_3_W_in ( p2923 ) , - .clk_3_E_in ( p2029 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7617 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7616 ) , .clk_3_W_in ( p3132 ) , + .clk_3_E_in ( p2408 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7617 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7618 ) ) ; cbx_1__1_ cbx_12__10_ ( .pReset ( { SYNOPSYS_UNCONNECTED_7619 } ) , @@ -128145,7 +132684,7 @@ cbx_1__1_ cbx_12__10_ ( .bottom_grid_pin_13_ ( cbx_1__1__130_bottom_grid_pin_13_ ) , .bottom_grid_pin_14_ ( cbx_1__1__130_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__130_bottom_grid_pin_15_ ) , - .ccff_tail ( cbx_1__1__130_ccff_tail ) , .SC_IN_TOP ( p2252 ) , + .ccff_tail ( cbx_1__1__130_ccff_tail ) , .SC_IN_TOP ( p965 ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_7620 ) , .SC_IN_BOT ( scff_Wires[312] ) , .SC_OUT_TOP ( scff_Wires[313] ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[130] ) , @@ -128158,20 +132697,20 @@ cbx_1__1_ cbx_12__10_ ( .pReset_S_out ( pResetWires[549] ) , .pReset_E_out ( pResetWires[548] ) , .prog_clk_0_N_in ( prog_clk_0_wires[473] ) , .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_7623 ) , - .prog_clk_1_W_in ( p2366 ) , .prog_clk_1_E_in ( p405 ) , + .prog_clk_1_W_in ( p1356 ) , .prog_clk_1_E_in ( p941 ) , .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_7624 ) , .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_7625 ) , - .prog_clk_2_E_in ( p2600 ) , .prog_clk_2_W_in ( p2391 ) , + .prog_clk_2_E_in ( p2980 ) , .prog_clk_2_W_in ( p3223 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_7626 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_7627 ) , - .prog_clk_3_W_in ( p3319 ) , .prog_clk_3_E_in ( p2119 ) , + .prog_clk_3_W_in ( p3227 ) , .prog_clk_3_E_in ( p2904 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_7628 ) , - .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_7629 ) , .clk_1_W_in ( p1401 ) , - .clk_1_E_in ( p628 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_7630 ) , - .clk_1_S_out ( SYNOPSYS_UNCONNECTED_7631 ) , .clk_2_E_in ( p2600 ) , - .clk_2_W_in ( p3279 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7632 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7633 ) , .clk_3_W_in ( p3246 ) , - .clk_3_E_in ( p2562 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7634 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_7629 ) , .clk_1_W_in ( p1395 ) , + .clk_1_E_in ( p1236 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_7630 ) , + .clk_1_S_out ( SYNOPSYS_UNCONNECTED_7631 ) , .clk_2_E_in ( p2347 ) , + .clk_2_W_in ( p3387 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7632 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7633 ) , .clk_3_W_in ( p3413 ) , + .clk_3_E_in ( p2103 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7634 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7635 ) ) ; cbx_1__1_ cbx_12__11_ ( .pReset ( { SYNOPSYS_UNCONNECTED_7636 } ) , @@ -128196,7 +132735,7 @@ cbx_1__1_ cbx_12__11_ ( .bottom_grid_pin_13_ ( cbx_1__1__131_bottom_grid_pin_13_ ) , .bottom_grid_pin_14_ ( cbx_1__1__131_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__131_bottom_grid_pin_15_ ) , - .ccff_tail ( cbx_1__1__131_ccff_tail ) , .SC_IN_TOP ( p2114 ) , + .ccff_tail ( cbx_1__1__131_ccff_tail ) , .SC_IN_TOP ( p2231 ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_7637 ) , .SC_IN_BOT ( scff_Wires[314] ) , .SC_OUT_TOP ( scff_Wires[315] ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[131] ) , @@ -128212,20 +132751,20 @@ cbx_1__1_ cbx_12__11_ ( .prog_clk_1_W_in ( prog_clk_1_wires[246] ) , .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_7641 ) , .prog_clk_1_N_out ( prog_clk_1_wires[250] ) , - .prog_clk_1_S_out ( prog_clk_1_wires[251] ) , .prog_clk_2_E_in ( p2480 ) , - .prog_clk_2_W_in ( p1256 ) , + .prog_clk_1_S_out ( prog_clk_1_wires[251] ) , .prog_clk_2_E_in ( p2604 ) , + .prog_clk_2_W_in ( p2926 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_7642 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_7643 ) , - .prog_clk_3_W_in ( p2509 ) , .prog_clk_3_E_in ( p1974 ) , + .prog_clk_3_W_in ( p3012 ) , .prog_clk_3_E_in ( p2445 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_7644 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_7645 ) , .clk_1_W_in ( clk_1_wires[246] ) , .clk_1_E_in ( SYNOPSYS_UNCONNECTED_7646 ) , .clk_1_N_out ( clk_1_wires[250] ) , .clk_1_S_out ( clk_1_wires[251] ) , - .clk_2_E_in ( p2480 ) , .clk_2_W_in ( p2720 ) , + .clk_2_E_in ( p2847 ) , .clk_2_W_in ( p3199 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7647 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7648 ) , .clk_3_W_in ( p2823 ) , - .clk_3_E_in ( p2274 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7649 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7648 ) , .clk_3_W_in ( p3266 ) , + .clk_3_E_in ( p2693 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7649 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7650 ) ) ; cbx_1__2_ cbx_1__12_ ( .pReset ( { SYNOPSYS_UNCONNECTED_7651 } ) , @@ -128259,7 +132798,7 @@ cbx_1__2_ cbx_1__12_ ( .bottom_width_0_height_0__pin_1_upper ( grid_io_top_0_bottom_width_0_height_0__pin_1_upper ) , .bottom_width_0_height_0__pin_1_lower ( grid_io_top_0_bottom_width_0_height_0__pin_1_lower ) , .SC_IN_TOP ( scff_Wires[0] ) , .SC_OUT_BOT ( scff_Wires[1] ) , - .SC_IN_BOT ( p1216 ) , .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_7652 ) , + .SC_IN_BOT ( p1338 ) , .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_7652 ) , .pReset_E_in ( pResetWires[601] ) , .pReset_W_in ( SYNOPSYS_UNCONNECTED_7653 ) , .pReset_W_out ( pResetWires[600] ) , .pReset_S_out ( pResetWires[602] ) , @@ -128297,7 +132836,7 @@ cbx_1__2_ cbx_2__12_ ( .bottom_width_0_height_0__pin_0_ ( cbx_1__12__1_top_grid_pin_0_ ) , .bottom_width_0_height_0__pin_1_upper ( grid_io_top_1_bottom_width_0_height_0__pin_1_upper ) , .bottom_width_0_height_0__pin_1_lower ( grid_io_top_1_bottom_width_0_height_0__pin_1_lower ) , - .SC_IN_TOP ( p1789 ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_7656 ) , + .SC_IN_TOP ( p1639 ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_7656 ) , .SC_IN_BOT ( scff_Wires[51] ) , .SC_OUT_TOP ( scff_Wires[52] ) , .pReset_E_in ( pResetWires[605] ) , .pReset_W_in ( SYNOPSYS_UNCONNECTED_7657 ) , @@ -128337,7 +132876,7 @@ cbx_1__2_ cbx_3__12_ ( .bottom_width_0_height_0__pin_1_upper ( grid_io_top_2_bottom_width_0_height_0__pin_1_upper ) , .bottom_width_0_height_0__pin_1_lower ( grid_io_top_2_bottom_width_0_height_0__pin_1_lower ) , .SC_IN_TOP ( scff_Wires[53] ) , .SC_OUT_BOT ( scff_Wires[54] ) , - .SC_IN_BOT ( p1272 ) , .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_7661 ) , + .SC_IN_BOT ( p1606 ) , .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_7661 ) , .pReset_E_in ( pResetWires[608] ) , .pReset_W_in ( SYNOPSYS_UNCONNECTED_7662 ) , .pReset_W_out ( pResetWires[607] ) , .pReset_S_out ( pResetWires[609] ) , @@ -128375,7 +132914,7 @@ cbx_1__2_ cbx_4__12_ ( .bottom_width_0_height_0__pin_0_ ( cbx_1__12__3_top_grid_pin_0_ ) , .bottom_width_0_height_0__pin_1_upper ( grid_io_top_3_bottom_width_0_height_0__pin_1_upper ) , .bottom_width_0_height_0__pin_1_lower ( grid_io_top_3_bottom_width_0_height_0__pin_1_lower ) , - .SC_IN_TOP ( p1618 ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_7666 ) , + .SC_IN_TOP ( p1397 ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_7666 ) , .SC_IN_BOT ( scff_Wires[104] ) , .SC_OUT_TOP ( scff_Wires[105] ) , .pReset_E_in ( pResetWires[611] ) , .pReset_W_in ( SYNOPSYS_UNCONNECTED_7667 ) , @@ -128415,7 +132954,7 @@ cbx_1__2_ cbx_5__12_ ( .bottom_width_0_height_0__pin_1_upper ( grid_io_top_4_bottom_width_0_height_0__pin_1_upper ) , .bottom_width_0_height_0__pin_1_lower ( grid_io_top_4_bottom_width_0_height_0__pin_1_lower ) , .SC_IN_TOP ( scff_Wires[106] ) , .SC_OUT_BOT ( scff_Wires[107] ) , - .SC_IN_BOT ( p1199 ) , .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_7671 ) , + .SC_IN_BOT ( p1412 ) , .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_7671 ) , .pReset_E_in ( pResetWires[614] ) , .pReset_W_in ( SYNOPSYS_UNCONNECTED_7672 ) , .pReset_W_out ( pResetWires[613] ) , .pReset_S_out ( pResetWires[615] ) , @@ -128453,7 +132992,7 @@ cbx_1__2_ cbx_6__12_ ( .bottom_width_0_height_0__pin_0_ ( cbx_1__12__5_top_grid_pin_0_ ) , .bottom_width_0_height_0__pin_1_upper ( grid_io_top_5_bottom_width_0_height_0__pin_1_upper ) , .bottom_width_0_height_0__pin_1_lower ( grid_io_top_5_bottom_width_0_height_0__pin_1_lower ) , - .SC_IN_TOP ( p1560 ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_7676 ) , + .SC_IN_TOP ( p1252 ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_7676 ) , .SC_IN_BOT ( scff_Wires[157] ) , .SC_OUT_TOP ( scff_Wires[158] ) , .pReset_E_in ( pResetWires[617] ) , .pReset_W_in ( SYNOPSYS_UNCONNECTED_7677 ) , @@ -128493,7 +133032,7 @@ cbx_1__2_ cbx_7__12_ ( .bottom_width_0_height_0__pin_1_upper ( grid_io_top_6_bottom_width_0_height_0__pin_1_upper ) , .bottom_width_0_height_0__pin_1_lower ( grid_io_top_6_bottom_width_0_height_0__pin_1_lower ) , .SC_IN_TOP ( scff_Wires[159] ) , .SC_OUT_BOT ( scff_Wires[160] ) , - .SC_IN_BOT ( p1307 ) , .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_7681 ) , + .SC_IN_BOT ( p1461 ) , .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_7681 ) , .pReset_E_in ( SYNOPSYS_UNCONNECTED_7682 ) , .pReset_W_in ( pResetWires[619] ) , .pReset_W_out ( SYNOPSYS_UNCONNECTED_7683 ) , @@ -128531,7 +133070,7 @@ cbx_1__2_ cbx_8__12_ ( .bottom_width_0_height_0__pin_0_ ( cbx_1__12__7_top_grid_pin_0_ ) , .bottom_width_0_height_0__pin_1_upper ( grid_io_top_7_bottom_width_0_height_0__pin_1_upper ) , .bottom_width_0_height_0__pin_1_lower ( grid_io_top_7_bottom_width_0_height_0__pin_1_lower ) , - .SC_IN_TOP ( p1438 ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_7686 ) , + .SC_IN_TOP ( p1565 ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_7686 ) , .SC_IN_BOT ( scff_Wires[210] ) , .SC_OUT_TOP ( scff_Wires[211] ) , .pReset_E_in ( SYNOPSYS_UNCONNECTED_7687 ) , .pReset_W_in ( pResetWires[622] ) , @@ -128571,7 +133110,7 @@ cbx_1__2_ cbx_9__12_ ( .bottom_width_0_height_0__pin_1_upper ( grid_io_top_8_bottom_width_0_height_0__pin_1_upper ) , .bottom_width_0_height_0__pin_1_lower ( grid_io_top_8_bottom_width_0_height_0__pin_1_lower ) , .SC_IN_TOP ( scff_Wires[212] ) , .SC_OUT_BOT ( scff_Wires[213] ) , - .SC_IN_BOT ( p1396 ) , .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_7691 ) , + .SC_IN_BOT ( p1360 ) , .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_7691 ) , .pReset_E_in ( SYNOPSYS_UNCONNECTED_7692 ) , .pReset_W_in ( pResetWires[625] ) , .pReset_W_out ( SYNOPSYS_UNCONNECTED_7693 ) , @@ -128609,7 +133148,7 @@ cbx_1__2_ cbx_10__12_ ( .bottom_width_0_height_0__pin_0_ ( cbx_1__12__9_top_grid_pin_0_ ) , .bottom_width_0_height_0__pin_1_upper ( grid_io_top_9_bottom_width_0_height_0__pin_1_upper ) , .bottom_width_0_height_0__pin_1_lower ( grid_io_top_9_bottom_width_0_height_0__pin_1_lower ) , - .SC_IN_TOP ( p1434 ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_7696 ) , + .SC_IN_TOP ( p1642 ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_7696 ) , .SC_IN_BOT ( scff_Wires[263] ) , .SC_OUT_TOP ( scff_Wires[264] ) , .pReset_E_in ( SYNOPSYS_UNCONNECTED_7697 ) , .pReset_W_in ( pResetWires[628] ) , @@ -128649,7 +133188,7 @@ cbx_1__2_ cbx_11__12_ ( .bottom_width_0_height_0__pin_1_upper ( grid_io_top_10_bottom_width_0_height_0__pin_1_upper ) , .bottom_width_0_height_0__pin_1_lower ( grid_io_top_10_bottom_width_0_height_0__pin_1_lower ) , .SC_IN_TOP ( scff_Wires[265] ) , .SC_OUT_BOT ( scff_Wires[266] ) , - .SC_IN_BOT ( p1310 ) , .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_7701 ) , + .SC_IN_BOT ( p1480 ) , .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_7701 ) , .pReset_E_in ( SYNOPSYS_UNCONNECTED_7702 ) , .pReset_W_in ( pResetWires[631] ) , .pReset_W_out ( SYNOPSYS_UNCONNECTED_7703 ) , @@ -128687,7 +133226,7 @@ cbx_1__2_ cbx_12__12_ ( .bottom_width_0_height_0__pin_0_ ( cbx_1__12__11_top_grid_pin_0_ ) , .bottom_width_0_height_0__pin_1_upper ( grid_io_top_11_bottom_width_0_height_0__pin_1_upper ) , .bottom_width_0_height_0__pin_1_lower ( grid_io_top_11_bottom_width_0_height_0__pin_1_lower ) , - .SC_IN_TOP ( p1784 ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_7706 ) , + .SC_IN_TOP ( p1354 ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_7706 ) , .SC_IN_BOT ( scff_Wires[316] ) , .SC_OUT_TOP ( scff_Wires[317] ) , .pReset_E_in ( SYNOPSYS_UNCONNECTED_7707 ) , .pReset_W_in ( pResetWires[634] ) , @@ -128940,15 +133479,15 @@ cby_1__1_ cby_1__1_ ( .prog_clk_0_W_in ( prog_clk_0_wires[1] ) , .prog_clk_0_S_out ( prog_clk_0_wires[2] ) , .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_7732 ) , - .prog_clk_2_N_in ( p1955 ) , .prog_clk_2_S_in ( p775 ) , + .prog_clk_2_N_in ( p2253 ) , .prog_clk_2_S_in ( p663 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_7733 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_7734 ) , - .prog_clk_3_S_in ( p2955 ) , .prog_clk_3_N_in ( p1656 ) , + .prog_clk_3_S_in ( p2279 ) , .prog_clk_3_N_in ( p2062 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_7735 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_7736 ) , .clk_2_N_in ( p2139 ) , - .clk_2_S_in ( p3344 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_7737 ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_7738 ) , .clk_3_S_in ( p3363 ) , - .clk_3_N_in ( p2013 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_7739 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_7736 ) , .clk_2_N_in ( p1330 ) , + .clk_2_S_in ( p3056 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_7737 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_7738 ) , .clk_3_S_in ( p3137 ) , + .clk_3_N_in ( p1110 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_7739 ) , .clk_3_S_out ( SYNOPSYS_UNCONNECTED_7740 ) ) ; cby_1__1_ cby_1__2_ ( .pReset ( { SYNOPSYS_UNCONNECTED_7741 } ) , @@ -128995,14 +133534,14 @@ cby_1__1_ cby_1__2_ ( .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_7752 ) , .prog_clk_2_S_out ( prog_clk_2_wires[4] ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_7753 ) , - .prog_clk_3_S_in ( p1866 ) , .prog_clk_3_N_in ( p835 ) , + .prog_clk_3_S_in ( p2035 ) , .prog_clk_3_N_in ( p389 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_7754 ) , .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_7755 ) , .clk_2_N_in ( clk_2_wires[3] ) , .clk_2_S_in ( SYNOPSYS_UNCONNECTED_7756 ) , .clk_2_S_out ( clk_2_wires[4] ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_7757 ) , .clk_3_S_in ( p1866 ) , - .clk_3_N_in ( p89 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_7758 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_7757 ) , .clk_3_S_in ( p2035 ) , + .clk_3_N_in ( p883 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_7758 ) , .clk_3_S_out ( SYNOPSYS_UNCONNECTED_7759 ) ) ; cby_1__1_ cby_1__3_ ( .pReset ( { SYNOPSYS_UNCONNECTED_7760 } ) , @@ -129045,15 +133584,15 @@ cby_1__1_ cby_1__3_ ( .prog_clk_0_W_in ( prog_clk_0_wires[12] ) , .prog_clk_0_S_out ( prog_clk_0_wires[13] ) , .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_7770 ) , - .prog_clk_2_N_in ( p3171 ) , .prog_clk_2_S_in ( p934 ) , + .prog_clk_2_N_in ( p2275 ) , .prog_clk_2_S_in ( p679 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_7771 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_7772 ) , - .prog_clk_3_S_in ( p2665 ) , .prog_clk_3_N_in ( p3152 ) , + .prog_clk_3_S_in ( p2958 ) , .prog_clk_3_N_in ( p2155 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_7773 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_7774 ) , .clk_2_N_in ( p2960 ) , - .clk_2_S_in ( p2732 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_7775 ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_7776 ) , .clk_3_S_in ( p2814 ) , - .clk_3_N_in ( p2879 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_7777 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_7774 ) , .clk_2_N_in ( p3001 ) , + .clk_2_S_in ( p2892 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_7775 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_7776 ) , .clk_3_S_in ( p2956 ) , + .clk_3_N_in ( p2905 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_7777 ) , .clk_3_S_out ( SYNOPSYS_UNCONNECTED_7778 ) ) ; cby_1__1_ cby_1__4_ ( .pReset ( { SYNOPSYS_UNCONNECTED_7779 } ) , @@ -129100,14 +133639,14 @@ cby_1__1_ cby_1__4_ ( .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_7790 ) , .prog_clk_2_S_out ( prog_clk_2_wires[11] ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_7791 ) , - .prog_clk_3_S_in ( p2097 ) , .prog_clk_3_N_in ( p220 ) , + .prog_clk_3_S_in ( p1640 ) , .prog_clk_3_N_in ( p423 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_7792 ) , .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_7793 ) , .clk_2_N_in ( clk_2_wires[10] ) , .clk_2_S_in ( SYNOPSYS_UNCONNECTED_7794 ) , .clk_2_S_out ( clk_2_wires[11] ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_7795 ) , .clk_3_S_in ( p2097 ) , - .clk_3_N_in ( p490 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_7796 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_7795 ) , .clk_3_S_in ( p1640 ) , + .clk_3_N_in ( p950 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_7796 ) , .clk_3_S_out ( SYNOPSYS_UNCONNECTED_7797 ) ) ; cby_1__1_ cby_1__5_ ( .pReset ( { SYNOPSYS_UNCONNECTED_7798 } ) , @@ -129153,15 +133692,15 @@ cby_1__1_ cby_1__5_ ( .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_7809 ) , .prog_clk_2_S_in ( prog_clk_2_wires[8] ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_7810 ) , - .prog_clk_2_N_out ( prog_clk_2_wires[9] ) , .prog_clk_3_S_in ( p1951 ) , - .prog_clk_3_N_in ( p25 ) , + .prog_clk_2_N_out ( prog_clk_2_wires[9] ) , .prog_clk_3_S_in ( p2304 ) , + .prog_clk_3_N_in ( p91 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_7811 ) , .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_7812 ) , .clk_2_N_in ( SYNOPSYS_UNCONNECTED_7813 ) , .clk_2_S_in ( clk_2_wires[8] ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_7814 ) , - .clk_2_N_out ( clk_2_wires[9] ) , .clk_3_S_in ( p1834 ) , - .clk_3_N_in ( p682 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_7815 ) , + .clk_2_N_out ( clk_2_wires[9] ) , .clk_3_S_in ( p2304 ) , + .clk_3_N_in ( p1092 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_7815 ) , .clk_3_S_out ( SYNOPSYS_UNCONNECTED_7816 ) ) ; cby_1__1_ cby_1__6_ ( .pReset ( { SYNOPSYS_UNCONNECTED_7817 } ) , @@ -129204,15 +133743,15 @@ cby_1__1_ cby_1__6_ ( .prog_clk_0_W_in ( prog_clk_0_wires[27] ) , .prog_clk_0_S_out ( prog_clk_0_wires[28] ) , .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_7827 ) , - .prog_clk_2_N_in ( p2435 ) , .prog_clk_2_S_in ( p519 ) , + .prog_clk_2_N_in ( p2569 ) , .prog_clk_2_S_in ( p864 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_7828 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_7829 ) , - .prog_clk_3_S_in ( p2479 ) , .prog_clk_3_N_in ( p2365 ) , + .prog_clk_3_S_in ( p2642 ) , .prog_clk_3_N_in ( p2466 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_7830 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_7831 ) , .clk_2_N_in ( p3262 ) , - .clk_2_S_in ( p2355 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_7832 ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_7833 ) , .clk_3_S_in ( p1512 ) , - .clk_3_N_in ( p3222 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_7834 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_7831 ) , .clk_2_N_in ( p2586 ) , + .clk_2_S_in ( p3084 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_7832 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_7833 ) , .clk_3_S_in ( p3111 ) , + .clk_3_N_in ( p2415 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_7834 ) , .clk_3_S_out ( SYNOPSYS_UNCONNECTED_7835 ) ) ; cby_1__1_ cby_1__7_ ( .pReset ( { SYNOPSYS_UNCONNECTED_7836 } ) , @@ -129255,15 +133794,15 @@ cby_1__1_ cby_1__7_ ( .prog_clk_0_W_in ( prog_clk_0_wires[32] ) , .prog_clk_0_S_out ( prog_clk_0_wires[33] ) , .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_7846 ) , - .prog_clk_2_N_in ( p2449 ) , .prog_clk_2_S_in ( p488 ) , + .prog_clk_2_N_in ( p1523 ) , .prog_clk_2_S_in ( p570 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_7847 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_7848 ) , - .prog_clk_3_S_in ( p3372 ) , .prog_clk_3_N_in ( p2363 ) , + .prog_clk_3_S_in ( p1955 ) , .prog_clk_3_N_in ( p162 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_7849 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_7850 ) , .clk_2_N_in ( p2930 ) , - .clk_2_S_in ( p3337 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_7851 ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_7852 ) , .clk_3_S_in ( p2827 ) , - .clk_3_N_in ( p2908 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_7853 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_7850 ) , .clk_2_N_in ( p1900 ) , + .clk_2_S_in ( p2381 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_7851 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_7852 ) , .clk_3_S_in ( p2581 ) , + .clk_3_N_in ( p1730 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_7853 ) , .clk_3_S_out ( SYNOPSYS_UNCONNECTED_7854 ) ) ; cby_1__1_ cby_1__8_ ( .pReset ( { SYNOPSYS_UNCONNECTED_7855 } ) , @@ -129310,14 +133849,14 @@ cby_1__1_ cby_1__8_ ( .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_7866 ) , .prog_clk_2_S_out ( prog_clk_2_wires[18] ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_7867 ) , - .prog_clk_3_S_in ( p1602 ) , .prog_clk_3_N_in ( p1128 ) , + .prog_clk_3_S_in ( p1607 ) , .prog_clk_3_N_in ( p636 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_7868 ) , .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_7869 ) , .clk_2_N_in ( clk_2_wires[17] ) , .clk_2_S_in ( SYNOPSYS_UNCONNECTED_7870 ) , .clk_2_S_out ( clk_2_wires[18] ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_7871 ) , .clk_3_S_in ( p1602 ) , - .clk_3_N_in ( p491 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_7872 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_7871 ) , .clk_3_S_in ( p1607 ) , + .clk_3_N_in ( p1091 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_7872 ) , .clk_3_S_out ( SYNOPSYS_UNCONNECTED_7873 ) ) ; cby_1__1_ cby_1__9_ ( .pReset ( { SYNOPSYS_UNCONNECTED_7874 } ) , @@ -129363,15 +133902,15 @@ cby_1__1_ cby_1__9_ ( .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_7885 ) , .prog_clk_2_S_in ( prog_clk_2_wires[15] ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_7886 ) , - .prog_clk_2_N_out ( prog_clk_2_wires[16] ) , .prog_clk_3_S_in ( p1899 ) , - .prog_clk_3_N_in ( p445 ) , + .prog_clk_2_N_out ( prog_clk_2_wires[16] ) , .prog_clk_3_S_in ( p1337 ) , + .prog_clk_3_N_in ( p27 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_7887 ) , .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_7888 ) , .clk_2_N_in ( SYNOPSYS_UNCONNECTED_7889 ) , .clk_2_S_in ( clk_2_wires[15] ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_7890 ) , - .clk_2_N_out ( clk_2_wires[16] ) , .clk_3_S_in ( p1899 ) , - .clk_3_N_in ( p922 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_7891 ) , + .clk_2_N_out ( clk_2_wires[16] ) , .clk_3_S_in ( p1337 ) , + .clk_3_N_in ( p1170 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_7891 ) , .clk_3_S_out ( SYNOPSYS_UNCONNECTED_7892 ) ) ; cby_1__1_ cby_1__10_ ( .pReset ( { SYNOPSYS_UNCONNECTED_7893 } ) , @@ -129414,15 +133953,15 @@ cby_1__1_ cby_1__10_ ( .prog_clk_0_W_in ( prog_clk_0_wires[47] ) , .prog_clk_0_S_out ( prog_clk_0_wires[48] ) , .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_7903 ) , - .prog_clk_2_N_in ( p2860 ) , .prog_clk_2_S_in ( p876 ) , + .prog_clk_2_N_in ( p1390 ) , .prog_clk_2_S_in ( p908 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_7904 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_7905 ) , - .prog_clk_3_S_in ( p1545 ) , .prog_clk_3_N_in ( p2767 ) , + .prog_clk_3_S_in ( p3008 ) , .prog_clk_3_N_in ( p1008 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_7906 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_7907 ) , .clk_2_N_in ( p3064 ) , - .clk_2_S_in ( p3289 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_7908 ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_7909 ) , .clk_3_S_in ( p3315 ) , - .clk_3_N_in ( p3007 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_7910 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_7907 ) , .clk_2_N_in ( p2943 ) , + .clk_2_S_in ( p2883 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_7908 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_7909 ) , .clk_3_S_in ( p2278 ) , + .clk_3_N_in ( p2870 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_7910 ) , .clk_3_S_out ( SYNOPSYS_UNCONNECTED_7911 ) ) ; cby_1__1_ cby_1__11_ ( .pReset ( { SYNOPSYS_UNCONNECTED_7912 } ) , @@ -129468,15 +134007,15 @@ cby_1__1_ cby_1__11_ ( .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_7923 ) , .prog_clk_2_S_in ( prog_clk_2_wires[22] ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_7924 ) , - .prog_clk_2_N_out ( prog_clk_2_wires[23] ) , .prog_clk_3_S_in ( p1906 ) , - .prog_clk_3_N_in ( p138 ) , + .prog_clk_2_N_out ( prog_clk_2_wires[23] ) , .prog_clk_3_S_in ( p1546 ) , + .prog_clk_3_N_in ( p509 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_7925 ) , .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_7926 ) , .clk_2_N_in ( SYNOPSYS_UNCONNECTED_7927 ) , .clk_2_S_in ( clk_2_wires[22] ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_7928 ) , - .clk_2_N_out ( clk_2_wires[23] ) , .clk_3_S_in ( p1906 ) , - .clk_3_N_in ( p776 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_7929 ) , + .clk_2_N_out ( clk_2_wires[23] ) , .clk_3_S_in ( p1546 ) , + .clk_3_N_in ( p526 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_7929 ) , .clk_3_S_out ( SYNOPSYS_UNCONNECTED_7930 ) ) ; cby_1__1_ cby_1__12_ ( .pReset ( { SYNOPSYS_UNCONNECTED_7931 } ) , @@ -129518,16 +134057,16 @@ cby_1__1_ cby_1__12_ ( .Reset_E_out ( SYNOPSYS_UNCONNECTED_7940 ) , .prog_clk_0_W_in ( prog_clk_0_wires[57] ) , .prog_clk_0_S_out ( prog_clk_0_wires[58] ) , - .prog_clk_0_N_out ( prog_clk_0_wires[60] ) , .prog_clk_2_N_in ( p2831 ) , - .prog_clk_2_S_in ( p391 ) , + .prog_clk_0_N_out ( prog_clk_0_wires[60] ) , .prog_clk_2_N_in ( p2774 ) , + .prog_clk_2_S_in ( p1040 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_7941 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_7942 ) , - .prog_clk_3_S_in ( p2430 ) , .prog_clk_3_N_in ( p2726 ) , + .prog_clk_3_S_in ( p2837 ) , .prog_clk_3_N_in ( p2646 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_7943 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_7944 ) , .clk_2_N_in ( p3260 ) , - .clk_2_S_in ( p2283 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_7945 ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_7946 ) , .clk_3_S_in ( p2519 ) , - .clk_3_N_in ( p3223 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_7947 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_7944 ) , .clk_2_N_in ( p2562 ) , + .clk_2_S_in ( p2720 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_7945 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_7946 ) , .clk_3_S_in ( p349 ) , + .clk_3_N_in ( p2435 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_7947 ) , .clk_3_S_out ( SYNOPSYS_UNCONNECTED_7948 ) ) ; cby_1__1_ cby_2__1_ ( .pReset ( { SYNOPSYS_UNCONNECTED_7949 } ) , @@ -129570,15 +134109,15 @@ cby_1__1_ cby_2__1_ ( .prog_clk_0_W_in ( prog_clk_0_wires[64] ) , .prog_clk_0_S_out ( prog_clk_0_wires[65] ) , .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_7959 ) , - .prog_clk_2_N_in ( p2834 ) , .prog_clk_2_S_in ( p638 ) , + .prog_clk_2_N_in ( p1695 ) , .prog_clk_2_S_in ( p707 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_7960 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_7961 ) , - .prog_clk_3_S_in ( p2166 ) , .prog_clk_3_N_in ( p2765 ) , + .prog_clk_3_S_in ( p2944 ) , .prog_clk_3_N_in ( p1812 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_7962 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_7963 ) , .clk_2_N_in ( p2184 ) , - .clk_2_S_in ( p2538 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_7964 ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_7965 ) , .clk_3_S_in ( p2667 ) , - .clk_3_N_in ( p2046 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_7966 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_7963 ) , .clk_2_N_in ( p3242 ) , + .clk_2_S_in ( p2884 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_7964 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_7965 ) , .clk_3_S_in ( p2518 ) , + .clk_3_N_in ( p3172 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_7966 ) , .clk_3_S_out ( SYNOPSYS_UNCONNECTED_7967 ) ) ; cby_1__1_ cby_2__2_ ( .pReset ( { SYNOPSYS_UNCONNECTED_7968 } ) , @@ -129621,15 +134160,15 @@ cby_1__1_ cby_2__2_ ( .prog_clk_0_W_in ( prog_clk_0_wires[67] ) , .prog_clk_0_S_out ( prog_clk_0_wires[68] ) , .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_7978 ) , - .prog_clk_2_N_in ( p2406 ) , .prog_clk_2_S_in ( p1044 ) , + .prog_clk_2_N_in ( p2747 ) , .prog_clk_2_S_in ( p309 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_7979 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_7980 ) , - .prog_clk_3_S_in ( p2486 ) , .prog_clk_3_N_in ( p2376 ) , + .prog_clk_3_S_in ( p2843 ) , .prog_clk_3_N_in ( p2659 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_7981 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_7982 ) , .clk_2_N_in ( p3174 ) , - .clk_2_S_in ( p2291 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_7983 ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_7984 ) , .clk_3_S_in ( p1933 ) , - .clk_3_N_in ( p3120 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_7985 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_7982 ) , .clk_2_N_in ( p2545 ) , + .clk_2_S_in ( p3043 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_7983 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_7984 ) , .clk_3_S_in ( p3133 ) , + .clk_3_N_in ( p2418 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_7985 ) , .clk_3_S_out ( SYNOPSYS_UNCONNECTED_7986 ) ) ; cby_1__1_ cby_2__3_ ( .pReset ( { SYNOPSYS_UNCONNECTED_7987 } ) , @@ -129672,14 +134211,14 @@ cby_1__1_ cby_2__3_ ( .prog_clk_0_W_in ( prog_clk_0_wires[70] ) , .prog_clk_0_S_out ( prog_clk_0_wires[71] ) , .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_7997 ) , - .prog_clk_2_N_in ( p1484 ) , .prog_clk_2_S_in ( p820 ) , + .prog_clk_2_N_in ( p1946 ) , .prog_clk_2_S_in ( p785 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_7998 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_7999 ) , .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_8000 ) , .prog_clk_3_N_in ( prog_clk_3_wires[68] ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_8001 ) , - .prog_clk_3_S_out ( prog_clk_3_wires[69] ) , .clk_2_N_in ( p1484 ) , - .clk_2_S_in ( p375 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8002 ) , + .prog_clk_3_S_out ( prog_clk_3_wires[69] ) , .clk_2_N_in ( p1946 ) , + .clk_2_S_in ( p2 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8002 ) , .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8003 ) , .clk_3_S_in ( SYNOPSYS_UNCONNECTED_8004 ) , .clk_3_N_in ( clk_3_wires[68] ) , @@ -129726,14 +134265,14 @@ cby_1__1_ cby_2__4_ ( .prog_clk_0_W_in ( prog_clk_0_wires[73] ) , .prog_clk_0_S_out ( prog_clk_0_wires[74] ) , .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_8016 ) , - .prog_clk_2_N_in ( p1497 ) , .prog_clk_2_S_in ( p2596 ) , + .prog_clk_2_N_in ( p1292 ) , .prog_clk_2_S_in ( p335 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_8017 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_8018 ) , .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_8019 ) , .prog_clk_3_N_in ( prog_clk_3_wires[64] ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_8020 ) , - .prog_clk_3_S_out ( prog_clk_3_wires[65] ) , .clk_2_N_in ( p1497 ) , - .clk_2_S_in ( p2523 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8021 ) , + .prog_clk_3_S_out ( prog_clk_3_wires[65] ) , .clk_2_N_in ( p1292 ) , + .clk_2_S_in ( p2442 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8021 ) , .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8022 ) , .clk_3_S_in ( SYNOPSYS_UNCONNECTED_8023 ) , .clk_3_N_in ( clk_3_wires[64] ) , @@ -129780,14 +134319,14 @@ cby_1__1_ cby_2__5_ ( .prog_clk_0_W_in ( prog_clk_0_wires[76] ) , .prog_clk_0_S_out ( prog_clk_0_wires[77] ) , .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_8035 ) , - .prog_clk_2_N_in ( p1113 ) , .prog_clk_2_S_in ( p232 ) , + .prog_clk_2_N_in ( p1883 ) , .prog_clk_2_S_in ( p1747 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_8036 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_8037 ) , .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_8038 ) , .prog_clk_3_N_in ( prog_clk_3_wires[58] ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_8039 ) , - .prog_clk_3_S_out ( prog_clk_3_wires[59] ) , .clk_2_N_in ( p1113 ) , - .clk_2_S_in ( p330 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8040 ) , + .prog_clk_3_S_out ( prog_clk_3_wires[59] ) , .clk_2_N_in ( p1883 ) , + .clk_2_S_in ( p890 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8040 ) , .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8041 ) , .clk_3_S_in ( SYNOPSYS_UNCONNECTED_8042 ) , .clk_3_N_in ( clk_3_wires[58] ) , @@ -129834,14 +134373,14 @@ cby_1__1_ cby_2__6_ ( .prog_clk_0_W_in ( prog_clk_0_wires[79] ) , .prog_clk_0_S_out ( prog_clk_0_wires[80] ) , .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_8054 ) , - .prog_clk_2_N_in ( p1572 ) , .prog_clk_2_S_in ( p2599 ) , + .prog_clk_2_N_in ( p1914 ) , .prog_clk_2_S_in ( p1787 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_8055 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_8056 ) , .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_8057 ) , .prog_clk_3_N_in ( prog_clk_3_wires[54] ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_8058 ) , - .prog_clk_3_S_out ( prog_clk_3_wires[55] ) , .clk_2_N_in ( p1572 ) , - .clk_2_S_in ( p2741 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8059 ) , + .prog_clk_3_S_out ( prog_clk_3_wires[55] ) , .clk_2_N_in ( p1789 ) , + .clk_2_S_in ( p1746 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8059 ) , .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8060 ) , .clk_3_S_in ( SYNOPSYS_UNCONNECTED_8061 ) , .clk_3_N_in ( clk_3_wires[54] ) , @@ -129888,14 +134427,14 @@ cby_1__1_ cby_2__7_ ( .prog_clk_0_W_in ( prog_clk_0_wires[82] ) , .prog_clk_0_S_out ( prog_clk_0_wires[83] ) , .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_8073 ) , - .prog_clk_2_N_in ( p1594 ) , .prog_clk_2_S_in ( p1691 ) , + .prog_clk_2_N_in ( p1378 ) , .prog_clk_2_S_in ( p2143 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_8074 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_8075 ) , .prog_clk_3_S_in ( prog_clk_3_wires[52] ) , .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_8076 ) , .prog_clk_3_N_out ( prog_clk_3_wires[53] ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8077 ) , .clk_2_N_in ( p1594 ) , - .clk_2_S_in ( p2003 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8078 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8077 ) , .clk_2_N_in ( p1524 ) , + .clk_2_S_in ( p2073 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8078 ) , .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8079 ) , .clk_3_S_in ( clk_3_wires[52] ) , .clk_3_N_in ( SYNOPSYS_UNCONNECTED_8080 ) , @@ -129942,14 +134481,14 @@ cby_1__1_ cby_2__8_ ( .prog_clk_0_W_in ( prog_clk_0_wires[85] ) , .prog_clk_0_S_out ( prog_clk_0_wires[86] ) , .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_8092 ) , - .prog_clk_2_N_in ( p1297 ) , .prog_clk_2_S_in ( p2070 ) , + .prog_clk_2_N_in ( p991 ) , .prog_clk_2_S_in ( p168 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_8093 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_8094 ) , .prog_clk_3_S_in ( prog_clk_3_wires[56] ) , .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_8095 ) , .prog_clk_3_N_out ( prog_clk_3_wires[57] ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8096 ) , .clk_2_N_in ( p1297 ) , - .clk_2_S_in ( p1975 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8097 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8096 ) , .clk_2_N_in ( p1460 ) , + .clk_2_S_in ( p2129 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8097 ) , .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8098 ) , .clk_3_S_in ( clk_3_wires[56] ) , .clk_3_N_in ( SYNOPSYS_UNCONNECTED_8099 ) , @@ -129996,14 +134535,14 @@ cby_1__1_ cby_2__9_ ( .prog_clk_0_W_in ( prog_clk_0_wires[88] ) , .prog_clk_0_S_out ( prog_clk_0_wires[89] ) , .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_8111 ) , - .prog_clk_2_N_in ( p1362 ) , .prog_clk_2_S_in ( p443 ) , + .prog_clk_2_N_in ( p1416 ) , .prog_clk_2_S_in ( p1679 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_8112 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_8113 ) , .prog_clk_3_S_in ( prog_clk_3_wires[62] ) , .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_8114 ) , .prog_clk_3_N_out ( prog_clk_3_wires[63] ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8115 ) , .clk_2_N_in ( p1362 ) , - .clk_2_S_in ( p828 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8116 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8115 ) , .clk_2_N_in ( p1363 ) , + .clk_2_S_in ( p44 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8116 ) , .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8117 ) , .clk_3_S_in ( clk_3_wires[62] ) , .clk_3_N_in ( SYNOPSYS_UNCONNECTED_8118 ) , @@ -130050,14 +134589,14 @@ cby_1__1_ cby_2__10_ ( .prog_clk_0_W_in ( prog_clk_0_wires[91] ) , .prog_clk_0_S_out ( prog_clk_0_wires[92] ) , .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_8130 ) , - .prog_clk_2_N_in ( p1883 ) , .prog_clk_2_S_in ( p2074 ) , + .prog_clk_2_N_in ( p1359 ) , .prog_clk_2_S_in ( p988 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_8131 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_8132 ) , .prog_clk_3_S_in ( prog_clk_3_wires[66] ) , .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_8133 ) , .prog_clk_3_N_out ( prog_clk_3_wires[67] ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8134 ) , .clk_2_N_in ( p1883 ) , - .clk_2_S_in ( p2019 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8135 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8134 ) , .clk_2_N_in ( p1359 ) , + .clk_2_S_in ( p2697 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8135 ) , .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8136 ) , .clk_3_S_in ( clk_3_wires[66] ) , .clk_3_N_in ( SYNOPSYS_UNCONNECTED_8137 ) , @@ -130104,15 +134643,15 @@ cby_1__1_ cby_2__11_ ( .prog_clk_0_W_in ( prog_clk_0_wires[94] ) , .prog_clk_0_S_out ( prog_clk_0_wires[95] ) , .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_8149 ) , - .prog_clk_2_N_in ( p2096 ) , .prog_clk_2_S_in ( p800 ) , + .prog_clk_2_N_in ( p2025 ) , .prog_clk_2_S_in ( p1042 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_8150 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_8151 ) , - .prog_clk_3_S_in ( p2979 ) , .prog_clk_3_N_in ( p2067 ) , + .prog_clk_3_S_in ( p2532 ) , .prog_clk_3_N_in ( p1733 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_8152 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8153 ) , .clk_2_N_in ( p2807 ) , - .clk_2_S_in ( p2872 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8154 ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8155 ) , .clk_3_S_in ( p2819 ) , - .clk_3_N_in ( p2747 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8156 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8153 ) , .clk_2_N_in ( p3239 ) , + .clk_2_S_in ( p2425 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8154 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8155 ) , .clk_3_S_in ( p2033 ) , + .clk_3_N_in ( p3180 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8156 ) , .clk_3_S_out ( SYNOPSYS_UNCONNECTED_8157 ) ) ; cby_1__1_ cby_2__12_ ( .pReset ( { SYNOPSYS_UNCONNECTED_8158 } ) , @@ -130154,16 +134693,16 @@ cby_1__1_ cby_2__12_ ( .Reset_E_out ( SYNOPSYS_UNCONNECTED_8167 ) , .prog_clk_0_W_in ( prog_clk_0_wires[97] ) , .prog_clk_0_S_out ( prog_clk_0_wires[98] ) , - .prog_clk_0_N_out ( prog_clk_0_wires[100] ) , .prog_clk_2_N_in ( p2196 ) , - .prog_clk_2_S_in ( p901 ) , + .prog_clk_0_N_out ( prog_clk_0_wires[100] ) , .prog_clk_2_N_in ( p2204 ) , + .prog_clk_2_S_in ( p366 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_8168 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_8169 ) , - .prog_clk_3_S_in ( p2805 ) , .prog_clk_3_N_in ( p1968 ) , + .prog_clk_3_S_in ( p2639 ) , .prog_clk_3_N_in ( p2060 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_8170 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8171 ) , .clk_2_N_in ( p3080 ) , - .clk_2_S_in ( p3034 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8172 ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8173 ) , .clk_3_S_in ( p3087 ) , - .clk_3_N_in ( p2998 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8174 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8171 ) , .clk_2_N_in ( p2503 ) , + .clk_2_S_in ( p2472 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8172 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8173 ) , .clk_3_S_in ( p1989 ) , + .clk_3_N_in ( p2387 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8174 ) , .clk_3_S_out ( SYNOPSYS_UNCONNECTED_8175 ) ) ; cby_1__1_ cby_3__1_ ( .pReset ( { SYNOPSYS_UNCONNECTED_8176 } ) , @@ -130206,15 +134745,15 @@ cby_1__1_ cby_3__1_ ( .prog_clk_0_W_in ( prog_clk_0_wires[102] ) , .prog_clk_0_S_out ( prog_clk_0_wires[103] ) , .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_8186 ) , - .prog_clk_2_N_in ( p2262 ) , .prog_clk_2_S_in ( p793 ) , + .prog_clk_2_N_in ( p1857 ) , .prog_clk_2_S_in ( p45 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_8187 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_8188 ) , - .prog_clk_3_S_in ( p2257 ) , .prog_clk_3_N_in ( p2038 ) , + .prog_clk_3_S_in ( p2038 ) , .prog_clk_3_N_in ( p1755 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_8189 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8190 ) , .clk_2_N_in ( p2800 ) , - .clk_2_S_in ( p1988 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8191 ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8192 ) , .clk_3_S_in ( p1886 ) , - .clk_3_N_in ( p2716 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8193 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8190 ) , .clk_2_N_in ( p2752 ) , + .clk_2_S_in ( p3182 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8191 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8192 ) , .clk_3_S_in ( p3264 ) , + .clk_3_N_in ( p2654 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8193 ) , .clk_3_S_out ( SYNOPSYS_UNCONNECTED_8194 ) ) ; cby_1__1_ cby_3__2_ ( .pReset ( { SYNOPSYS_UNCONNECTED_8195 } ) , @@ -130261,14 +134800,14 @@ cby_1__1_ cby_3__2_ ( .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_8206 ) , .prog_clk_2_S_out ( prog_clk_2_wires[30] ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_8207 ) , - .prog_clk_3_S_in ( p2109 ) , .prog_clk_3_N_in ( p344 ) , + .prog_clk_3_S_in ( p2237 ) , .prog_clk_3_N_in ( p666 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_8208 ) , .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8209 ) , .clk_2_N_in ( clk_2_wires[29] ) , .clk_2_S_in ( SYNOPSYS_UNCONNECTED_8210 ) , .clk_2_S_out ( clk_2_wires[30] ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8211 ) , .clk_3_S_in ( p2109 ) , - .clk_3_N_in ( p738 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8212 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8211 ) , .clk_3_S_in ( p2237 ) , + .clk_3_N_in ( p970 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8212 ) , .clk_3_S_out ( SYNOPSYS_UNCONNECTED_8213 ) ) ; cby_1__1_ cby_3__3_ ( .pReset ( { SYNOPSYS_UNCONNECTED_8214 } ) , @@ -130311,15 +134850,15 @@ cby_1__1_ cby_3__3_ ( .prog_clk_0_W_in ( prog_clk_0_wires[108] ) , .prog_clk_0_S_out ( prog_clk_0_wires[109] ) , .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_8224 ) , - .prog_clk_2_N_in ( p1911 ) , .prog_clk_2_S_in ( p743 ) , + .prog_clk_2_N_in ( p2783 ) , .prog_clk_2_S_in ( p457 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_8225 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_8226 ) , - .prog_clk_3_S_in ( p2797 ) , .prog_clk_3_N_in ( p1638 ) , + .prog_clk_3_S_in ( p1575 ) , .prog_clk_3_N_in ( p2651 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_8227 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8228 ) , .clk_2_N_in ( p2400 ) , - .clk_2_S_in ( p2725 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8229 ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8230 ) , .clk_3_S_in ( p2268 ) , - .clk_3_N_in ( p2322 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8231 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8228 ) , .clk_2_N_in ( p2790 ) , + .clk_2_S_in ( p3044 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8229 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8230 ) , .clk_3_S_in ( p3127 ) , + .clk_3_N_in ( p2721 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8231 ) , .clk_3_S_out ( SYNOPSYS_UNCONNECTED_8232 ) ) ; cby_1__1_ cby_3__4_ ( .pReset ( { SYNOPSYS_UNCONNECTED_8233 } ) , @@ -130366,14 +134905,14 @@ cby_1__1_ cby_3__4_ ( .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_8244 ) , .prog_clk_2_S_out ( prog_clk_2_wires[41] ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_8245 ) , - .prog_clk_3_S_in ( p1547 ) , .prog_clk_3_N_in ( p369 ) , + .prog_clk_3_S_in ( p895 ) , .prog_clk_3_N_in ( p497 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_8246 ) , .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8247 ) , .clk_2_N_in ( clk_2_wires[40] ) , .clk_2_S_in ( SYNOPSYS_UNCONNECTED_8248 ) , .clk_2_S_out ( clk_2_wires[41] ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8249 ) , .clk_3_S_in ( p1547 ) , - .clk_3_N_in ( p198 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8250 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8249 ) , .clk_3_S_in ( p895 ) , + .clk_3_N_in ( p429 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8250 ) , .clk_3_S_out ( SYNOPSYS_UNCONNECTED_8251 ) ) ; cby_1__1_ cby_3__5_ ( .pReset ( { SYNOPSYS_UNCONNECTED_8252 } ) , @@ -130419,15 +134958,15 @@ cby_1__1_ cby_3__5_ ( .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_8263 ) , .prog_clk_2_S_in ( prog_clk_2_wires[38] ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_8264 ) , - .prog_clk_2_N_out ( prog_clk_2_wires[39] ) , .prog_clk_3_S_in ( p2131 ) , - .prog_clk_3_N_in ( p606 ) , + .prog_clk_2_N_out ( prog_clk_2_wires[39] ) , .prog_clk_3_S_in ( p1520 ) , + .prog_clk_3_N_in ( p642 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_8265 ) , .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8266 ) , .clk_2_N_in ( SYNOPSYS_UNCONNECTED_8267 ) , .clk_2_S_in ( clk_2_wires[38] ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8268 ) , - .clk_2_N_out ( clk_2_wires[39] ) , .clk_3_S_in ( p2131 ) , - .clk_3_N_in ( p88 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8269 ) , + .clk_2_N_out ( clk_2_wires[39] ) , .clk_3_S_in ( p1520 ) , + .clk_3_N_in ( p1215 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8269 ) , .clk_3_S_out ( SYNOPSYS_UNCONNECTED_8270 ) ) ; cby_1__1_ cby_3__6_ ( .pReset ( { SYNOPSYS_UNCONNECTED_8271 } ) , @@ -130470,15 +135009,15 @@ cby_1__1_ cby_3__6_ ( .prog_clk_0_W_in ( prog_clk_0_wires[117] ) , .prog_clk_0_S_out ( prog_clk_0_wires[118] ) , .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_8281 ) , - .prog_clk_2_N_in ( p1366 ) , .prog_clk_2_S_in ( p349 ) , + .prog_clk_2_N_in ( p2827 ) , .prog_clk_2_S_in ( p588 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_8282 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_8283 ) , - .prog_clk_3_S_in ( p2423 ) , .prog_clk_3_N_in ( p768 ) , + .prog_clk_3_S_in ( p1403 ) , .prog_clk_3_N_in ( p2703 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_8284 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8285 ) , .clk_2_N_in ( p2412 ) , - .clk_2_S_in ( p3237 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8286 ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8287 ) , .clk_3_S_in ( p3256 ) , - .clk_3_N_in ( p2351 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8288 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8285 ) , .clk_2_N_in ( p2963 ) , + .clk_2_S_in ( p2867 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8286 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8287 ) , .clk_3_S_in ( p2940 ) , + .clk_3_N_in ( p2866 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8288 ) , .clk_3_S_out ( SYNOPSYS_UNCONNECTED_8289 ) ) ; cby_1__1_ cby_3__7_ ( .pReset ( { SYNOPSYS_UNCONNECTED_8290 } ) , @@ -130521,15 +135060,15 @@ cby_1__1_ cby_3__7_ ( .prog_clk_0_W_in ( prog_clk_0_wires[120] ) , .prog_clk_0_S_out ( prog_clk_0_wires[121] ) , .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_8300 ) , - .prog_clk_2_N_in ( p2704 ) , .prog_clk_2_S_in ( p1750 ) , + .prog_clk_2_N_in ( p2003 ) , .prog_clk_2_S_in ( p2160 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_8301 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_8302 ) , - .prog_clk_3_S_in ( p1480 ) , .prog_clk_3_N_in ( p2553 ) , + .prog_clk_3_S_in ( p3170 ) , .prog_clk_3_N_in ( p1723 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_8303 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8304 ) , .clk_2_N_in ( p2707 ) , - .clk_2_S_in ( p2541 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8305 ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8306 ) , .clk_3_S_in ( p2641 ) , - .clk_3_N_in ( p2602 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8307 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8304 ) , .clk_2_N_in ( p2985 ) , + .clk_2_S_in ( p3055 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8305 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8306 ) , .clk_3_S_in ( p3153 ) , + .clk_3_N_in ( p2896 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8307 ) , .clk_3_S_out ( SYNOPSYS_UNCONNECTED_8308 ) ) ; cby_1__1_ cby_3__8_ ( .pReset ( { SYNOPSYS_UNCONNECTED_8309 } ) , @@ -130576,14 +135115,14 @@ cby_1__1_ cby_3__8_ ( .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_8320 ) , .prog_clk_2_S_out ( prog_clk_2_wires[54] ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_8321 ) , - .prog_clk_3_S_in ( p1474 ) , .prog_clk_3_N_in ( p576 ) , + .prog_clk_3_S_in ( p1455 ) , .prog_clk_3_N_in ( p1033 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_8322 ) , .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8323 ) , .clk_2_N_in ( clk_2_wires[53] ) , .clk_2_S_in ( SYNOPSYS_UNCONNECTED_8324 ) , .clk_2_S_out ( clk_2_wires[54] ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8325 ) , .clk_3_S_in ( p1474 ) , - .clk_3_N_in ( p885 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8326 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8325 ) , .clk_3_S_in ( p1455 ) , + .clk_3_N_in ( p752 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8326 ) , .clk_3_S_out ( SYNOPSYS_UNCONNECTED_8327 ) ) ; cby_1__1_ cby_3__9_ ( .pReset ( { SYNOPSYS_UNCONNECTED_8328 } ) , @@ -130629,15 +135168,15 @@ cby_1__1_ cby_3__9_ ( .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_8339 ) , .prog_clk_2_S_in ( prog_clk_2_wires[51] ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_8340 ) , - .prog_clk_2_N_out ( prog_clk_2_wires[52] ) , .prog_clk_3_S_in ( p1758 ) , - .prog_clk_3_N_in ( p525 ) , + .prog_clk_2_N_out ( prog_clk_2_wires[52] ) , .prog_clk_3_S_in ( p2014 ) , + .prog_clk_3_N_in ( p539 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_8341 ) , .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8342 ) , .clk_2_N_in ( SYNOPSYS_UNCONNECTED_8343 ) , .clk_2_S_in ( clk_2_wires[51] ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8344 ) , - .clk_2_N_out ( clk_2_wires[52] ) , .clk_3_S_in ( p1758 ) , - .clk_3_N_in ( p936 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8345 ) , + .clk_2_N_out ( clk_2_wires[52] ) , .clk_3_S_in ( p2014 ) , + .clk_3_N_in ( p652 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8345 ) , .clk_3_S_out ( SYNOPSYS_UNCONNECTED_8346 ) ) ; cby_1__1_ cby_3__10_ ( .pReset ( { SYNOPSYS_UNCONNECTED_8347 } ) , @@ -130680,15 +135219,15 @@ cby_1__1_ cby_3__10_ ( .prog_clk_0_W_in ( prog_clk_0_wires[129] ) , .prog_clk_0_S_out ( prog_clk_0_wires[130] ) , .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_8357 ) , - .prog_clk_2_N_in ( p2153 ) , .prog_clk_2_S_in ( p603 ) , + .prog_clk_2_N_in ( p2270 ) , .prog_clk_2_S_in ( p524 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_8358 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_8359 ) , - .prog_clk_3_S_in ( p2197 ) , .prog_clk_3_N_in ( p2057 ) , + .prog_clk_3_S_in ( p3028 ) , .prog_clk_3_N_in ( p2173 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_8360 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8361 ) , .clk_2_N_in ( p2382 ) , - .clk_2_S_in ( p3335 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8362 ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8363 ) , .clk_3_S_in ( p3361 ) , - .clk_3_N_in ( p2314 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8364 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8361 ) , .clk_2_N_in ( p2785 ) , + .clk_2_S_in ( p2872 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8362 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8363 ) , .clk_3_S_in ( p1525 ) , + .clk_3_N_in ( p2678 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8364 ) , .clk_3_S_out ( SYNOPSYS_UNCONNECTED_8365 ) ) ; cby_1__1_ cby_3__11_ ( .pReset ( { SYNOPSYS_UNCONNECTED_8366 } ) , @@ -130734,15 +135273,15 @@ cby_1__1_ cby_3__11_ ( .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_8377 ) , .prog_clk_2_S_in ( prog_clk_2_wires[64] ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_8378 ) , - .prog_clk_2_N_out ( prog_clk_2_wires[65] ) , .prog_clk_3_S_in ( p2160 ) , - .prog_clk_3_N_in ( p903 ) , + .prog_clk_2_N_out ( prog_clk_2_wires[65] ) , .prog_clk_3_S_in ( p1472 ) , + .prog_clk_3_N_in ( p760 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_8379 ) , .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8380 ) , .clk_2_N_in ( SYNOPSYS_UNCONNECTED_8381 ) , .clk_2_S_in ( clk_2_wires[64] ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8382 ) , - .clk_2_N_out ( clk_2_wires[65] ) , .clk_3_S_in ( p2160 ) , - .clk_3_N_in ( p572 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8383 ) , + .clk_2_N_out ( clk_2_wires[65] ) , .clk_3_S_in ( p1472 ) , + .clk_3_N_in ( p525 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8383 ) , .clk_3_S_out ( SYNOPSYS_UNCONNECTED_8384 ) ) ; cby_1__1_ cby_3__12_ ( .pReset ( { SYNOPSYS_UNCONNECTED_8385 } ) , @@ -130784,16 +135323,16 @@ cby_1__1_ cby_3__12_ ( .Reset_E_out ( SYNOPSYS_UNCONNECTED_8394 ) , .prog_clk_0_W_in ( prog_clk_0_wires[135] ) , .prog_clk_0_S_out ( prog_clk_0_wires[136] ) , - .prog_clk_0_N_out ( prog_clk_0_wires[138] ) , .prog_clk_2_N_in ( p2462 ) , - .prog_clk_2_S_in ( p707 ) , + .prog_clk_0_N_out ( prog_clk_0_wires[138] ) , .prog_clk_2_N_in ( p1836 ) , + .prog_clk_2_S_in ( p1024 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_8395 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_8396 ) , - .prog_clk_3_S_in ( p3247 ) , .prog_clk_3_N_in ( p2298 ) , + .prog_clk_3_S_in ( p3394 ) , .prog_clk_3_N_in ( p1740 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_8397 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8398 ) , .clk_2_N_in ( p3203 ) , - .clk_2_S_in ( p3299 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8399 ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8400 ) , .clk_3_S_in ( p3305 ) , - .clk_3_N_in ( p3113 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8401 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8398 ) , .clk_2_N_in ( p3095 ) , + .clk_2_S_in ( p3384 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8399 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8400 ) , .clk_3_S_in ( p1853 ) , + .clk_3_N_in ( p3074 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8401 ) , .clk_3_S_out ( SYNOPSYS_UNCONNECTED_8402 ) ) ; cby_1__1_ cby_4__1_ ( .pReset ( { SYNOPSYS_UNCONNECTED_8403 } ) , @@ -130836,15 +135375,15 @@ cby_1__1_ cby_4__1_ ( .prog_clk_0_W_in ( prog_clk_0_wires[140] ) , .prog_clk_0_S_out ( prog_clk_0_wires[141] ) , .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_8413 ) , - .prog_clk_2_N_in ( p2950 ) , .prog_clk_2_S_in ( p372 ) , + .prog_clk_2_N_in ( p2326 ) , .prog_clk_2_S_in ( p79 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_8414 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_8415 ) , - .prog_clk_3_S_in ( p2671 ) , .prog_clk_3_N_in ( p2877 ) , + .prog_clk_3_S_in ( p2829 ) , .prog_clk_3_N_in ( p2179 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_8416 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8417 ) , .clk_2_N_in ( p3255 ) , - .clk_2_S_in ( p2903 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8418 ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8419 ) , .clk_3_S_in ( p2946 ) , - .clk_3_N_in ( p3207 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8420 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8417 ) , .clk_2_N_in ( p2359 ) , + .clk_2_S_in ( p2661 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8418 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8419 ) , .clk_3_S_in ( p2606 ) , + .clk_3_N_in ( p2130 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8420 ) , .clk_3_S_out ( SYNOPSYS_UNCONNECTED_8421 ) ) ; cby_1__1_ cby_4__2_ ( .pReset ( { SYNOPSYS_UNCONNECTED_8422 } ) , @@ -130887,15 +135426,15 @@ cby_1__1_ cby_4__2_ ( .prog_clk_0_W_in ( prog_clk_0_wires[143] ) , .prog_clk_0_S_out ( prog_clk_0_wires[144] ) , .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_8432 ) , - .prog_clk_2_N_in ( p2228 ) , .prog_clk_2_S_in ( p282 ) , + .prog_clk_2_N_in ( p2254 ) , .prog_clk_2_S_in ( p995 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_8433 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_8434 ) , - .prog_clk_3_S_in ( p1935 ) , .prog_clk_3_N_in ( p2062 ) , + .prog_clk_3_S_in ( p3021 ) , .prog_clk_3_N_in ( p2075 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_8435 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8436 ) , .clk_2_N_in ( p2012 ) , - .clk_2_S_in ( p3151 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8437 ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8438 ) , .clk_3_S_in ( p3170 ) , - .clk_3_N_in ( p2083 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8439 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8436 ) , .clk_2_N_in ( p3126 ) , + .clk_2_S_in ( p2923 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8437 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8438 ) , .clk_3_S_in ( p2967 ) , + .clk_3_N_in ( p3036 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8439 ) , .clk_3_S_out ( SYNOPSYS_UNCONNECTED_8440 ) ) ; cby_1__1_ cby_4__3_ ( .pReset ( { SYNOPSYS_UNCONNECTED_8441 } ) , @@ -130938,14 +135477,14 @@ cby_1__1_ cby_4__3_ ( .prog_clk_0_W_in ( prog_clk_0_wires[146] ) , .prog_clk_0_S_out ( prog_clk_0_wires[147] ) , .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_8451 ) , - .prog_clk_2_N_in ( p2240 ) , .prog_clk_2_S_in ( p661 ) , + .prog_clk_2_N_in ( p1564 ) , .prog_clk_2_S_in ( p344 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_8452 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_8453 ) , .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_8454 ) , .prog_clk_3_N_in ( prog_clk_3_wires[24] ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_8455 ) , - .prog_clk_3_S_out ( prog_clk_3_wires[25] ) , .clk_2_N_in ( p2240 ) , - .clk_2_S_in ( p1059 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8456 ) , + .prog_clk_3_S_out ( prog_clk_3_wires[25] ) , .clk_2_N_in ( p1564 ) , + .clk_2_S_in ( p1083 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8456 ) , .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8457 ) , .clk_3_S_in ( SYNOPSYS_UNCONNECTED_8458 ) , .clk_3_N_in ( clk_3_wires[24] ) , @@ -130992,14 +135531,14 @@ cby_1__1_ cby_4__4_ ( .prog_clk_0_W_in ( prog_clk_0_wires[149] ) , .prog_clk_0_S_out ( prog_clk_0_wires[150] ) , .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_8470 ) , - .prog_clk_2_N_in ( p1596 ) , .prog_clk_2_S_in ( p1663 ) , + .prog_clk_2_N_in ( p1280 ) , .prog_clk_2_S_in ( p892 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_8471 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_8472 ) , .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_8473 ) , .prog_clk_3_N_in ( prog_clk_3_wires[20] ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_8474 ) , - .prog_clk_3_S_out ( prog_clk_3_wires[21] ) , .clk_2_N_in ( p1596 ) , - .clk_2_S_in ( p2313 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8475 ) , + .prog_clk_3_S_out ( prog_clk_3_wires[21] ) , .clk_2_N_in ( p1280 ) , + .clk_2_S_in ( p212 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8475 ) , .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8476 ) , .clk_3_S_in ( SYNOPSYS_UNCONNECTED_8477 ) , .clk_3_N_in ( clk_3_wires[20] ) , @@ -131046,14 +135585,14 @@ cby_1__1_ cby_4__5_ ( .prog_clk_0_W_in ( prog_clk_0_wires[152] ) , .prog_clk_0_S_out ( prog_clk_0_wires[153] ) , .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_8489 ) , - .prog_clk_2_N_in ( p1367 ) , .prog_clk_2_S_in ( p271 ) , + .prog_clk_2_N_in ( p1630 ) , .prog_clk_2_S_in ( p322 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_8490 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_8491 ) , .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_8492 ) , .prog_clk_3_N_in ( prog_clk_3_wires[14] ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_8493 ) , - .prog_clk_3_S_out ( prog_clk_3_wires[15] ) , .clk_2_N_in ( p1367 ) , - .clk_2_S_in ( p761 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8494 ) , + .prog_clk_3_S_out ( prog_clk_3_wires[15] ) , .clk_2_N_in ( p1630 ) , + .clk_2_S_in ( p1006 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8494 ) , .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8495 ) , .clk_3_S_in ( SYNOPSYS_UNCONNECTED_8496 ) , .clk_3_N_in ( clk_3_wires[14] ) , @@ -131100,14 +135639,14 @@ cby_1__1_ cby_4__6_ ( .prog_clk_0_W_in ( prog_clk_0_wires[155] ) , .prog_clk_0_S_out ( prog_clk_0_wires[156] ) , .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_8508 ) , - .prog_clk_2_N_in ( p1296 ) , .prog_clk_2_S_in ( p327 ) , + .prog_clk_2_N_in ( p2044 ) , .prog_clk_2_S_in ( p1775 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_8509 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_8510 ) , .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_8511 ) , .prog_clk_3_N_in ( prog_clk_3_wires[10] ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_8512 ) , - .prog_clk_3_S_out ( prog_clk_3_wires[11] ) , .clk_2_N_in ( p1296 ) , - .clk_2_S_in ( p456 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8513 ) , + .prog_clk_3_S_out ( prog_clk_3_wires[11] ) , .clk_2_N_in ( p2044 ) , + .clk_2_S_in ( p2099 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8513 ) , .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8514 ) , .clk_3_S_in ( SYNOPSYS_UNCONNECTED_8515 ) , .clk_3_N_in ( clk_3_wires[10] ) , @@ -131154,14 +135693,14 @@ cby_1__1_ cby_4__7_ ( .prog_clk_0_W_in ( prog_clk_0_wires[158] ) , .prog_clk_0_S_out ( prog_clk_0_wires[159] ) , .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_8527 ) , - .prog_clk_2_N_in ( p2223 ) , .prog_clk_2_S_in ( p2372 ) , + .prog_clk_2_N_in ( p2320 ) , .prog_clk_2_S_in ( p2409 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_8528 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_8529 ) , .prog_clk_3_S_in ( prog_clk_3_wires[8] ) , .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_8530 ) , .prog_clk_3_N_out ( prog_clk_3_wires[9] ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8531 ) , .clk_2_N_in ( p2223 ) , - .clk_2_S_in ( p2536 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8532 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8531 ) , .clk_2_N_in ( p2217 ) , + .clk_2_S_in ( p2469 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8532 ) , .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8533 ) , .clk_3_S_in ( clk_3_wires[8] ) , .clk_3_N_in ( SYNOPSYS_UNCONNECTED_8534 ) , @@ -131208,14 +135747,14 @@ cby_1__1_ cby_4__8_ ( .prog_clk_0_W_in ( prog_clk_0_wires[161] ) , .prog_clk_0_S_out ( prog_clk_0_wires[162] ) , .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_8546 ) , - .prog_clk_2_N_in ( p538 ) , .prog_clk_2_S_in ( p1979 ) , + .prog_clk_2_N_in ( p1256 ) , .prog_clk_2_S_in ( p1664 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_8547 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_8548 ) , .prog_clk_3_S_in ( prog_clk_3_wires[12] ) , .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_8549 ) , .prog_clk_3_N_out ( prog_clk_3_wires[13] ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8550 ) , .clk_2_N_in ( p538 ) , - .clk_2_S_in ( p2754 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8551 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8550 ) , .clk_2_N_in ( p1256 ) , + .clk_2_S_in ( p1727 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8551 ) , .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8552 ) , .clk_3_S_in ( clk_3_wires[12] ) , .clk_3_N_in ( SYNOPSYS_UNCONNECTED_8553 ) , @@ -131262,14 +135801,14 @@ cby_1__1_ cby_4__9_ ( .prog_clk_0_W_in ( prog_clk_0_wires[164] ) , .prog_clk_0_S_out ( prog_clk_0_wires[165] ) , .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_8565 ) , - .prog_clk_2_N_in ( p1904 ) , .prog_clk_2_S_in ( p1696 ) , + .prog_clk_2_N_in ( p1436 ) , .prog_clk_2_S_in ( p109 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_8566 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_8567 ) , .prog_clk_3_S_in ( prog_clk_3_wires[18] ) , .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_8568 ) , .prog_clk_3_N_out ( prog_clk_3_wires[19] ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8569 ) , .clk_2_N_in ( p1904 ) , - .clk_2_S_in ( p595 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8570 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8569 ) , .clk_2_N_in ( p1637 ) , + .clk_2_S_in ( p692 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8570 ) , .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8571 ) , .clk_3_S_in ( clk_3_wires[18] ) , .clk_3_N_in ( SYNOPSYS_UNCONNECTED_8572 ) , @@ -131316,14 +135855,14 @@ cby_1__1_ cby_4__10_ ( .prog_clk_0_W_in ( prog_clk_0_wires[167] ) , .prog_clk_0_S_out ( prog_clk_0_wires[168] ) , .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_8584 ) , - .prog_clk_2_N_in ( p1179 ) , .prog_clk_2_S_in ( p2306 ) , + .prog_clk_2_N_in ( p1111 ) , .prog_clk_2_S_in ( p2413 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_8585 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_8586 ) , .prog_clk_3_S_in ( prog_clk_3_wires[22] ) , .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_8587 ) , .prog_clk_3_N_out ( prog_clk_3_wires[23] ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8588 ) , .clk_2_N_in ( p1179 ) , - .clk_2_S_in ( p2545 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8589 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8588 ) , .clk_2_N_in ( p1111 ) , + .clk_2_S_in ( p2448 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8589 ) , .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8590 ) , .clk_3_S_in ( clk_3_wires[22] ) , .clk_3_N_in ( SYNOPSYS_UNCONNECTED_8591 ) , @@ -131370,15 +135909,15 @@ cby_1__1_ cby_4__11_ ( .prog_clk_0_W_in ( prog_clk_0_wires[170] ) , .prog_clk_0_S_out ( prog_clk_0_wires[171] ) , .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_8603 ) , - .prog_clk_2_N_in ( p2503 ) , .prog_clk_2_S_in ( p931 ) , + .prog_clk_2_N_in ( p2539 ) , .prog_clk_2_S_in ( p591 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_8604 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_8605 ) , - .prog_clk_3_S_in ( p1772 ) , .prog_clk_3_N_in ( p2293 ) , + .prog_clk_3_S_in ( p2792 ) , .prog_clk_3_N_in ( p2399 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_8606 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8607 ) , .clk_2_N_in ( p3079 ) , - .clk_2_S_in ( p2280 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8608 ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8609 ) , .clk_3_S_in ( p2498 ) , - .clk_3_N_in ( p3031 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8610 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8607 ) , .clk_2_N_in ( p1892 ) , + .clk_2_S_in ( p3302 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8608 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8609 ) , .clk_3_S_in ( p3350 ) , + .clk_3_N_in ( p1776 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8610 ) , .clk_3_S_out ( SYNOPSYS_UNCONNECTED_8611 ) ) ; cby_1__1_ cby_4__12_ ( .pReset ( { SYNOPSYS_UNCONNECTED_8612 } ) , @@ -131420,16 +135959,16 @@ cby_1__1_ cby_4__12_ ( .Reset_E_out ( SYNOPSYS_UNCONNECTED_8621 ) , .prog_clk_0_W_in ( prog_clk_0_wires[173] ) , .prog_clk_0_S_out ( prog_clk_0_wires[174] ) , - .prog_clk_0_N_out ( prog_clk_0_wires[176] ) , .prog_clk_2_N_in ( p1762 ) , - .prog_clk_2_S_in ( p622 ) , + .prog_clk_0_N_out ( prog_clk_0_wires[176] ) , .prog_clk_2_N_in ( p1862 ) , + .prog_clk_2_S_in ( p133 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_8622 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_8623 ) , - .prog_clk_3_S_in ( p2404 ) , .prog_clk_3_N_in ( p1754 ) , + .prog_clk_3_S_in ( p1868 ) , .prog_clk_3_N_in ( p1788 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_8624 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8625 ) , .clk_2_N_in ( p2396 ) , - .clk_2_S_in ( p2326 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8626 ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8627 ) , .clk_3_S_in ( p2415 ) , - .clk_3_N_in ( p2303 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8628 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8625 ) , .clk_2_N_in ( p2972 ) , + .clk_2_S_in ( p2468 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8626 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8627 ) , .clk_3_S_in ( p2600 ) , + .clk_3_N_in ( p2898 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8628 ) , .clk_3_S_out ( SYNOPSYS_UNCONNECTED_8629 ) ) ; cby_1__1_ cby_5__1_ ( .pReset ( { SYNOPSYS_UNCONNECTED_8630 } ) , @@ -131472,15 +136011,15 @@ cby_1__1_ cby_5__1_ ( .prog_clk_0_W_in ( prog_clk_0_wires[178] ) , .prog_clk_0_S_out ( prog_clk_0_wires[179] ) , .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_8640 ) , - .prog_clk_2_N_in ( p1869 ) , .prog_clk_2_S_in ( p41 ) , + .prog_clk_2_N_in ( p1901 ) , .prog_clk_2_S_in ( p17 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_8641 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_8642 ) , - .prog_clk_3_S_in ( p2976 ) , .prog_clk_3_N_in ( p1669 ) , + .prog_clk_3_S_in ( p2830 ) , .prog_clk_3_N_in ( p1666 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_8643 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8644 ) , .clk_2_N_in ( p2425 ) , - .clk_2_S_in ( p2881 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8645 ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8646 ) , .clk_3_S_in ( p2261 ) , - .clk_3_N_in ( p2299 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8647 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8644 ) , .clk_2_N_in ( p2242 ) , + .clk_2_S_in ( p2679 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8645 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8646 ) , .clk_3_S_in ( p2298 ) , + .clk_3_N_in ( p2146 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8647 ) , .clk_3_S_out ( SYNOPSYS_UNCONNECTED_8648 ) ) ; cby_1__1_ cby_5__2_ ( .pReset ( { SYNOPSYS_UNCONNECTED_8649 } ) , @@ -131527,14 +136066,14 @@ cby_1__1_ cby_5__2_ ( .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_8660 ) , .prog_clk_2_S_out ( prog_clk_2_wires[32] ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_8661 ) , - .prog_clk_3_S_in ( p2177 ) , .prog_clk_3_N_in ( p1115 ) , + .prog_clk_3_S_in ( p1917 ) , .prog_clk_3_N_in ( p399 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_8662 ) , .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8663 ) , .clk_2_N_in ( clk_2_wires[31] ) , .clk_2_S_in ( SYNOPSYS_UNCONNECTED_8664 ) , .clk_2_S_out ( clk_2_wires[32] ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8665 ) , .clk_3_S_in ( p2177 ) , - .clk_3_N_in ( p644 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8666 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8665 ) , .clk_3_S_in ( p1917 ) , + .clk_3_N_in ( p611 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8666 ) , .clk_3_S_out ( SYNOPSYS_UNCONNECTED_8667 ) ) ; cby_1__1_ cby_5__3_ ( .pReset ( { SYNOPSYS_UNCONNECTED_8668 } ) , @@ -131577,15 +136116,15 @@ cby_1__1_ cby_5__3_ ( .prog_clk_0_W_in ( prog_clk_0_wires[184] ) , .prog_clk_0_S_out ( prog_clk_0_wires[185] ) , .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_8678 ) , - .prog_clk_2_N_in ( p1863 ) , .prog_clk_2_S_in ( p400 ) , + .prog_clk_2_N_in ( p2286 ) , .prog_clk_2_S_in ( p496 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_8679 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_8680 ) , - .prog_clk_3_S_in ( p2852 ) , .prog_clk_3_N_in ( p1635 ) , + .prog_clk_3_S_in ( p1406 ) , .prog_clk_3_N_in ( p2159 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_8681 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8682 ) , .clk_2_N_in ( p2801 ) , - .clk_2_S_in ( p3112 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8683 ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8684 ) , .clk_3_S_in ( p3179 ) , - .clk_3_N_in ( p2722 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8685 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8682 ) , .clk_2_N_in ( p2769 ) , + .clk_2_S_in ( p1741 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8683 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8684 ) , .clk_3_S_in ( p1890 ) , + .clk_3_N_in ( p2687 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8685 ) , .clk_3_S_out ( SYNOPSYS_UNCONNECTED_8686 ) ) ; cby_1__1_ cby_5__4_ ( .pReset ( { SYNOPSYS_UNCONNECTED_8687 } ) , @@ -131632,14 +136171,14 @@ cby_1__1_ cby_5__4_ ( .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_8698 ) , .prog_clk_2_S_out ( prog_clk_2_wires[45] ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_8699 ) , - .prog_clk_3_S_in ( p1507 ) , .prog_clk_3_N_in ( p16 ) , + .prog_clk_3_S_in ( p1623 ) , .prog_clk_3_N_in ( p484 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_8700 ) , .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8701 ) , .clk_2_N_in ( clk_2_wires[44] ) , .clk_2_S_in ( SYNOPSYS_UNCONNECTED_8702 ) , .clk_2_S_out ( clk_2_wires[45] ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8703 ) , .clk_3_S_in ( p1507 ) , - .clk_3_N_in ( p642 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8704 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8703 ) , .clk_3_S_in ( p1623 ) , + .clk_3_N_in ( p822 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8704 ) , .clk_3_S_out ( SYNOPSYS_UNCONNECTED_8705 ) ) ; cby_1__1_ cby_5__5_ ( .pReset ( { SYNOPSYS_UNCONNECTED_8706 } ) , @@ -131685,15 +136224,15 @@ cby_1__1_ cby_5__5_ ( .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_8717 ) , .prog_clk_2_S_in ( prog_clk_2_wires[42] ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_8718 ) , - .prog_clk_2_N_out ( prog_clk_2_wires[43] ) , .prog_clk_3_S_in ( p2661 ) , - .prog_clk_3_N_in ( p582 ) , + .prog_clk_2_N_out ( prog_clk_2_wires[43] ) , .prog_clk_3_S_in ( p1888 ) , + .prog_clk_3_N_in ( p1180 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_8719 ) , .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8720 ) , .clk_2_N_in ( SYNOPSYS_UNCONNECTED_8721 ) , .clk_2_S_in ( clk_2_wires[42] ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8722 ) , - .clk_2_N_out ( clk_2_wires[43] ) , .clk_3_S_in ( p2661 ) , - .clk_3_N_in ( p1003 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8723 ) , + .clk_2_N_out ( clk_2_wires[43] ) , .clk_3_S_in ( p1888 ) , + .clk_3_N_in ( p488 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8723 ) , .clk_3_S_out ( SYNOPSYS_UNCONNECTED_8724 ) ) ; cby_1__1_ cby_5__6_ ( .pReset ( { SYNOPSYS_UNCONNECTED_8725 } ) , @@ -131736,15 +136275,15 @@ cby_1__1_ cby_5__6_ ( .prog_clk_0_W_in ( prog_clk_0_wires[193] ) , .prog_clk_0_S_out ( prog_clk_0_wires[194] ) , .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_8735 ) , - .prog_clk_2_N_in ( p2457 ) , .prog_clk_2_S_in ( p950 ) , + .prog_clk_2_N_in ( p2808 ) , .prog_clk_2_S_in ( p523 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_8736 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_8737 ) , - .prog_clk_3_S_in ( p2832 ) , .prog_clk_3_N_in ( p2341 ) , + .prog_clk_3_S_in ( p3107 ) , .prog_clk_3_N_in ( p2671 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_8738 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8739 ) , .clk_2_N_in ( p3191 ) , - .clk_2_S_in ( p3040 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8740 ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8741 ) , .clk_3_S_in ( p3081 ) , - .clk_3_N_in ( p3124 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8742 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8739 ) , .clk_2_N_in ( p2807 ) , + .clk_2_S_in ( p3046 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8740 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8741 ) , .clk_3_S_in ( p2541 ) , + .clk_3_N_in ( p2732 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8742 ) , .clk_3_S_out ( SYNOPSYS_UNCONNECTED_8743 ) ) ; cby_1__1_ cby_5__7_ ( .pReset ( { SYNOPSYS_UNCONNECTED_8744 } ) , @@ -131787,15 +136326,15 @@ cby_1__1_ cby_5__7_ ( .prog_clk_0_W_in ( prog_clk_0_wires[196] ) , .prog_clk_0_S_out ( prog_clk_0_wires[197] ) , .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_8754 ) , - .prog_clk_2_N_in ( p2799 ) , .prog_clk_2_S_in ( p275 ) , + .prog_clk_2_N_in ( p1468 ) , .prog_clk_2_S_in ( p2376 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_8755 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_8756 ) , - .prog_clk_3_S_in ( p2098 ) , .prog_clk_3_N_in ( p2729 ) , + .prog_clk_3_S_in ( p2593 ) , .prog_clk_3_N_in ( p373 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_8757 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8758 ) , .clk_2_N_in ( p3197 ) , - .clk_2_S_in ( p2756 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8759 ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8760 ) , .clk_3_S_in ( p2837 ) , - .clk_3_N_in ( p3141 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8761 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8758 ) , .clk_2_N_in ( p2343 ) , + .clk_2_S_in ( p2460 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8759 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8760 ) , .clk_3_S_in ( p2564 ) , + .clk_3_N_in ( p2085 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8761 ) , .clk_3_S_out ( SYNOPSYS_UNCONNECTED_8762 ) ) ; cby_1__1_ cby_5__8_ ( .pReset ( { SYNOPSYS_UNCONNECTED_8763 } ) , @@ -131842,14 +136381,14 @@ cby_1__1_ cby_5__8_ ( .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_8774 ) , .prog_clk_2_S_out ( prog_clk_2_wires[58] ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_8775 ) , - .prog_clk_3_S_in ( p1889 ) , .prog_clk_3_N_in ( p721 ) , + .prog_clk_3_S_in ( p1977 ) , .prog_clk_3_N_in ( p25 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_8776 ) , .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8777 ) , .clk_2_N_in ( clk_2_wires[57] ) , .clk_2_S_in ( SYNOPSYS_UNCONNECTED_8778 ) , .clk_2_S_out ( clk_2_wires[58] ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8779 ) , .clk_3_S_in ( p1889 ) , - .clk_3_N_in ( p759 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8780 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8779 ) , .clk_3_S_in ( p1977 ) , + .clk_3_N_in ( p613 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8780 ) , .clk_3_S_out ( SYNOPSYS_UNCONNECTED_8781 ) ) ; cby_1__1_ cby_5__9_ ( .pReset ( { SYNOPSYS_UNCONNECTED_8782 } ) , @@ -131895,15 +136434,15 @@ cby_1__1_ cby_5__9_ ( .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_8793 ) , .prog_clk_2_S_in ( prog_clk_2_wires[55] ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_8794 ) , - .prog_clk_2_N_out ( prog_clk_2_wires[56] ) , .prog_clk_3_S_in ( p1753 ) , + .prog_clk_2_N_out ( prog_clk_2_wires[56] ) , .prog_clk_3_S_in ( p1951 ) , .prog_clk_3_N_in ( p21 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_8795 ) , .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8796 ) , .clk_2_N_in ( SYNOPSYS_UNCONNECTED_8797 ) , .clk_2_S_in ( clk_2_wires[55] ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8798 ) , - .clk_2_N_out ( clk_2_wires[56] ) , .clk_3_S_in ( p1753 ) , - .clk_3_N_in ( p1147 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8799 ) , + .clk_2_N_out ( clk_2_wires[56] ) , .clk_3_S_in ( p1822 ) , + .clk_3_N_in ( p926 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8799 ) , .clk_3_S_out ( SYNOPSYS_UNCONNECTED_8800 ) ) ; cby_1__1_ cby_5__10_ ( .pReset ( { SYNOPSYS_UNCONNECTED_8801 } ) , @@ -131946,15 +136485,15 @@ cby_1__1_ cby_5__10_ ( .prog_clk_0_W_in ( prog_clk_0_wires[205] ) , .prog_clk_0_S_out ( prog_clk_0_wires[206] ) , .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_8811 ) , - .prog_clk_2_N_in ( p2927 ) , .prog_clk_2_S_in ( p65 ) , + .prog_clk_2_N_in ( p2255 ) , .prog_clk_2_S_in ( p695 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_8812 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_8813 ) , - .prog_clk_3_S_in ( p2655 ) , .prog_clk_3_N_in ( p2882 ) , + .prog_clk_3_S_in ( p2315 ) , .prog_clk_3_N_in ( p2054 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_8814 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8815 ) , .clk_2_N_in ( p3276 ) , - .clk_2_S_in ( p2588 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8816 ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8817 ) , .clk_3_S_in ( p2233 ) , - .clk_3_N_in ( p3220 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8818 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8815 ) , .clk_2_N_in ( p2540 ) , + .clk_2_S_in ( p3088 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8816 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8817 ) , .clk_3_S_in ( p3123 ) , + .clk_3_N_in ( p2446 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8818 ) , .clk_3_S_out ( SYNOPSYS_UNCONNECTED_8819 ) ) ; cby_1__1_ cby_5__11_ ( .pReset ( { SYNOPSYS_UNCONNECTED_8820 } ) , @@ -132000,15 +136539,15 @@ cby_1__1_ cby_5__11_ ( .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_8831 ) , .prog_clk_2_S_in ( prog_clk_2_wires[66] ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_8832 ) , - .prog_clk_2_N_out ( prog_clk_2_wires[67] ) , .prog_clk_3_S_in ( p1554 ) , - .prog_clk_3_N_in ( p59 ) , + .prog_clk_2_N_out ( prog_clk_2_wires[67] ) , .prog_clk_3_S_in ( p1912 ) , + .prog_clk_3_N_in ( p1018 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_8833 ) , .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8834 ) , .clk_2_N_in ( SYNOPSYS_UNCONNECTED_8835 ) , .clk_2_S_in ( clk_2_wires[66] ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8836 ) , - .clk_2_N_out ( clk_2_wires[67] ) , .clk_3_S_in ( p1554 ) , - .clk_3_N_in ( p696 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8837 ) , + .clk_2_N_out ( clk_2_wires[67] ) , .clk_3_S_in ( p1912 ) , + .clk_3_N_in ( p183 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8837 ) , .clk_3_S_out ( SYNOPSYS_UNCONNECTED_8838 ) ) ; cby_1__1_ cby_5__12_ ( .pReset ( { SYNOPSYS_UNCONNECTED_8839 } ) , @@ -132050,16 +136589,16 @@ cby_1__1_ cby_5__12_ ( .Reset_E_out ( SYNOPSYS_UNCONNECTED_8848 ) , .prog_clk_0_W_in ( prog_clk_0_wires[211] ) , .prog_clk_0_S_out ( prog_clk_0_wires[212] ) , - .prog_clk_0_N_out ( prog_clk_0_wires[214] ) , .prog_clk_2_N_in ( p2794 ) , - .prog_clk_2_S_in ( p694 ) , + .prog_clk_0_N_out ( prog_clk_0_wires[214] ) , .prog_clk_2_N_in ( p1537 ) , + .prog_clk_2_S_in ( p487 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_8849 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_8850 ) , - .prog_clk_3_S_in ( p2929 ) , .prog_clk_3_N_in ( p2734 ) , + .prog_clk_3_S_in ( p1911 ) , .prog_clk_3_N_in ( p1075 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_8851 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8852 ) , .clk_2_N_in ( p2456 ) , - .clk_2_S_in ( p3346 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8853 ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8854 ) , .clk_3_S_in ( p3368 ) , - .clk_3_N_in ( p2295 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8855 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8852 ) , .clk_2_N_in ( p2640 ) , + .clk_2_S_in ( p2450 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8853 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8854 ) , .clk_3_S_in ( p2572 ) , + .clk_3_N_in ( p2436 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8855 ) , .clk_3_S_out ( SYNOPSYS_UNCONNECTED_8856 ) ) ; cby_1__1_ cby_6__1_ ( .pReset ( { SYNOPSYS_UNCONNECTED_8857 } ) , @@ -132098,14 +136637,14 @@ cby_1__1_ cby_6__1_ ( .prog_clk_0_W_in ( prog_clk_0_wires[216] ) , .prog_clk_0_S_out ( prog_clk_0_wires[217] ) , .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_8862 ) , - .prog_clk_2_N_in ( p1755 ) , .prog_clk_2_S_in ( p334 ) , + .prog_clk_2_N_in ( p1572 ) , .prog_clk_2_S_in ( p889 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_8863 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_8864 ) , .prog_clk_3_S_in ( prog_clk_3_wires[90] ) , .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_8865 ) , .prog_clk_3_N_out ( prog_clk_3_wires[89] ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8866 ) , .clk_2_N_in ( p1755 ) , - .clk_2_S_in ( p1686 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8867 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8866 ) , .clk_2_N_in ( p1572 ) , + .clk_2_S_in ( p378 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8867 ) , .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8868 ) , .clk_3_S_in ( clk_3_wires[90] ) , .clk_3_N_in ( SYNOPSYS_UNCONNECTED_8869 ) , @@ -132148,14 +136687,14 @@ cby_1__1_ cby_6__2_ ( .prog_clk_0_W_in ( prog_clk_0_wires[219] ) , .prog_clk_0_S_out ( prog_clk_0_wires[220] ) , .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_8876 ) , - .prog_clk_2_N_in ( p1957 ) , .prog_clk_2_S_in ( p739 ) , + .prog_clk_2_N_in ( p1528 ) , .prog_clk_2_S_in ( p438 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_8877 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_8878 ) , .prog_clk_3_S_in ( prog_clk_3_wires[92] ) , .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_8879 ) , .prog_clk_3_N_out ( prog_clk_3_wires[91] ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8880 ) , .clk_2_N_in ( p1953 ) , - .clk_2_S_in ( p392 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8881 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8880 ) , .clk_2_N_in ( p1528 ) , + .clk_2_S_in ( p1020 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8881 ) , .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8882 ) , .clk_3_S_in ( clk_3_wires[92] ) , .clk_3_N_in ( SYNOPSYS_UNCONNECTED_8883 ) , @@ -132198,14 +136737,14 @@ cby_1__1_ cby_6__3_ ( .prog_clk_0_W_in ( prog_clk_0_wires[222] ) , .prog_clk_0_S_out ( prog_clk_0_wires[223] ) , .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_8890 ) , - .prog_clk_2_N_in ( p1936 ) , .prog_clk_2_S_in ( p1744 ) , + .prog_clk_2_N_in ( p1574 ) , .prog_clk_2_S_in ( p2420 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_8891 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_8892 ) , .prog_clk_3_S_in ( prog_clk_3_wires[94] ) , .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_8893 ) , .prog_clk_3_N_out ( prog_clk_3_wires[93] ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8894 ) , .clk_2_N_in ( p1936 ) , - .clk_2_S_in ( p2532 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8895 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8894 ) , .clk_2_N_in ( p1574 ) , + .clk_2_S_in ( p2402 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8895 ) , .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8896 ) , .clk_3_S_in ( clk_3_wires[94] ) , .clk_3_N_in ( SYNOPSYS_UNCONNECTED_8897 ) , @@ -132248,14 +136787,14 @@ cby_1__1_ cby_6__4_ ( .prog_clk_0_W_in ( prog_clk_0_wires[225] ) , .prog_clk_0_S_out ( prog_clk_0_wires[226] ) , .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_8904 ) , - .prog_clk_2_N_in ( p1818 ) , .prog_clk_2_S_in ( p1639 ) , + .prog_clk_2_N_in ( p1947 ) , .prog_clk_2_S_in ( p1805 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_8905 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_8906 ) , .prog_clk_3_S_in ( prog_clk_3_wires[96] ) , .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_8907 ) , .prog_clk_3_N_out ( prog_clk_3_wires[95] ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8908 ) , .clk_2_N_in ( p1818 ) , - .clk_2_S_in ( p1733 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8909 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8908 ) , .clk_2_N_in ( p2008 ) , + .clk_2_S_in ( p3052 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8909 ) , .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8910 ) , .clk_3_S_in ( clk_3_wires[96] ) , .clk_3_N_in ( SYNOPSYS_UNCONNECTED_8911 ) , @@ -132299,14 +136838,14 @@ cby_1__1_ cby_6__5_ ( .prog_clk_0_W_in ( prog_clk_0_wires[228] ) , .prog_clk_0_S_out ( prog_clk_0_wires[229] ) , .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_8918 ) , - .prog_clk_2_N_in ( p1916 ) , .prog_clk_2_S_in ( p2352 ) , + .prog_clk_2_N_in ( p1297 ) , .prog_clk_2_S_in ( p169 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_8919 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_8920 ) , .prog_clk_3_S_in ( prog_clk_3_wires[98] ) , .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_8921 ) , .prog_clk_3_N_out ( prog_clk_3_wires[97] ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8922 ) , .clk_2_N_in ( p1916 ) , - .clk_2_S_in ( p2907 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8923 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8922 ) , .clk_2_N_in ( p1297 ) , + .clk_2_S_in ( p2094 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8923 ) , .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8924 ) , .clk_3_S_in ( clk_3_wires[98] ) , .clk_3_N_in ( SYNOPSYS_UNCONNECTED_8925 ) , @@ -132350,14 +136889,14 @@ cby_1__1_ cby_6__6_ ( .prog_clk_0_W_in ( prog_clk_0_wires[231] ) , .prog_clk_0_S_out ( prog_clk_0_wires[232] ) , .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_8932 ) , - .prog_clk_2_N_in ( p2141 ) , .prog_clk_2_S_in ( p2597 ) , + .prog_clk_2_N_in ( p1419 ) , .prog_clk_2_S_in ( p1798 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_8933 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_8934 ) , .prog_clk_3_S_in ( prog_clk_3_wires[100] ) , .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_8935 ) , .prog_clk_3_N_out ( prog_clk_3_wires[99] ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8936 ) , .clk_2_N_in ( p2205 ) , - .clk_2_S_in ( p2752 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8937 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8936 ) , .clk_2_N_in ( p1419 ) , + .clk_2_S_in ( p1713 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8937 ) , .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8938 ) , .clk_3_S_in ( clk_3_wires[100] ) , .clk_3_N_in ( SYNOPSYS_UNCONNECTED_8939 ) , @@ -132401,15 +136940,15 @@ cby_1__1_ cby_6__7_ ( .prog_clk_0_W_in ( prog_clk_0_wires[234] ) , .prog_clk_0_S_out ( prog_clk_0_wires[235] ) , .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_8946 ) , - .prog_clk_2_N_in ( p2448 ) , .prog_clk_2_S_in ( p1728 ) , + .prog_clk_2_N_in ( p1334 ) , .prog_clk_2_S_in ( p1694 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_8947 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_8948 ) , - .prog_clk_3_S_in ( p1435 ) , .prog_clk_3_N_in ( p2350 ) , + .prog_clk_3_S_in ( p2746 ) , .prog_clk_3_N_in ( p737 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_8949 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8950 ) , .clk_2_N_in ( p2459 ) , - .clk_2_S_in ( p2884 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8951 ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8952 ) , .clk_3_S_in ( p2977 ) , - .clk_3_N_in ( p2327 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8953 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8950 ) , .clk_2_N_in ( p3332 ) , + .clk_2_S_in ( p2888 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8951 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8952 ) , .clk_3_S_in ( p2370 ) , + .clk_3_N_in ( p3287 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8953 ) , .clk_3_S_out ( SYNOPSYS_UNCONNECTED_8954 ) ) ; cby_1__1_ cby_6__8_ ( .pReset ( { SYNOPSYS_UNCONNECTED_8955 } ) , @@ -132449,15 +136988,15 @@ cby_1__1_ cby_6__8_ ( .prog_clk_0_W_in ( prog_clk_0_wires[237] ) , .prog_clk_0_S_out ( prog_clk_0_wires[238] ) , .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_8960 ) , - .prog_clk_2_N_in ( p1478 ) , .prog_clk_2_S_in ( p737 ) , + .prog_clk_2_N_in ( p2233 ) , .prog_clk_2_S_in ( p735 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_8961 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_8962 ) , - .prog_clk_3_S_in ( p2615 ) , .prog_clk_3_N_in ( p645 ) , + .prog_clk_3_S_in ( p3010 ) , .prog_clk_3_N_in ( p2157 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_8963 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8964 ) , .clk_2_N_in ( p3189 ) , - .clk_2_S_in ( p2768 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8965 ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8966 ) , .clk_3_S_in ( p2851 ) , - .clk_3_N_in ( p3117 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8967 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8964 ) , .clk_2_N_in ( p3104 ) , + .clk_2_S_in ( p2887 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8965 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8966 ) , .clk_3_S_in ( p1879 ) , + .clk_3_N_in ( p3042 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8967 ) , .clk_3_S_out ( SYNOPSYS_UNCONNECTED_8968 ) ) ; cby_1__1_ cby_6__9_ ( .pReset ( { SYNOPSYS_UNCONNECTED_8969 } ) , @@ -132497,15 +137036,15 @@ cby_1__1_ cby_6__9_ ( .prog_clk_0_W_in ( prog_clk_0_wires[240] ) , .prog_clk_0_S_out ( prog_clk_0_wires[241] ) , .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_8974 ) , - .prog_clk_2_N_in ( p2489 ) , .prog_clk_2_S_in ( p357 ) , + .prog_clk_2_N_in ( p2560 ) , .prog_clk_2_S_in ( p54 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_8975 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_8976 ) , - .prog_clk_3_S_in ( p2958 ) , .prog_clk_3_N_in ( p2294 ) , + .prog_clk_3_S_in ( p2509 ) , .prog_clk_3_N_in ( p2427 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_8977 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8978 ) , .clk_2_N_in ( p2639 ) , - .clk_2_S_in ( p2886 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8979 ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8980 ) , .clk_3_S_in ( p2857 ) , - .clk_3_N_in ( p2574 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8981 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8978 ) , .clk_2_N_in ( p2337 ) , + .clk_2_S_in ( p3090 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8979 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8980 ) , .clk_3_S_in ( p3156 ) , + .clk_3_N_in ( p2098 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8981 ) , .clk_3_S_out ( SYNOPSYS_UNCONNECTED_8982 ) ) ; cby_1__1_ cby_6__10_ ( .pReset ( { SYNOPSYS_UNCONNECTED_8983 } ) , @@ -132545,15 +137084,15 @@ cby_1__1_ cby_6__10_ ( .prog_clk_0_W_in ( prog_clk_0_wires[243] ) , .prog_clk_0_S_out ( prog_clk_0_wires[244] ) , .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_8988 ) , - .prog_clk_2_N_in ( p2264 ) , .prog_clk_2_S_in ( p226 ) , + .prog_clk_2_N_in ( p1943 ) , .prog_clk_2_S_in ( p230 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_8989 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_8990 ) , - .prog_clk_3_S_in ( p2624 ) , .prog_clk_3_N_in ( p2084 ) , + .prog_clk_3_S_in ( p2542 ) , .prog_clk_3_N_in ( p1796 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_8991 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8992 ) , .clk_2_N_in ( p3196 ) , - .clk_2_S_in ( p3005 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8993 ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8994 ) , .clk_3_S_in ( p3086 ) , - .clk_3_N_in ( p3127 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8995 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8992 ) , .clk_2_N_in ( p3258 ) , + .clk_2_S_in ( p2465 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8993 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8994 ) , .clk_3_S_in ( p2291 ) , + .clk_3_N_in ( p3194 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8995 ) , .clk_3_S_out ( SYNOPSYS_UNCONNECTED_8996 ) ) ; cby_1__1_ cby_6__11_ ( .pReset ( { SYNOPSYS_UNCONNECTED_8997 } ) , @@ -132593,15 +137132,15 @@ cby_1__1_ cby_6__11_ ( .prog_clk_0_W_in ( prog_clk_0_wires[246] ) , .prog_clk_0_S_out ( prog_clk_0_wires[247] ) , .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_9002 ) , - .prog_clk_2_N_in ( p2458 ) , .prog_clk_2_S_in ( p382 ) , + .prog_clk_2_N_in ( p1894 ) , .prog_clk_2_S_in ( p460 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_9003 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_9004 ) , - .prog_clk_3_S_in ( p3102 ) , .prog_clk_3_N_in ( p2305 ) , + .prog_clk_3_S_in ( p2012 ) , .prog_clk_3_N_in ( p1711 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_9005 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9006 ) , .clk_2_N_in ( p3369 ) , - .clk_2_S_in ( p3039 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9007 ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9008 ) , .clk_3_S_in ( p1782 ) , - .clk_3_N_in ( p3350 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9009 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9006 ) , .clk_2_N_in ( p2374 ) , + .clk_2_S_in ( p2424 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9007 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9008 ) , .clk_3_S_in ( p2531 ) , + .clk_3_N_in ( p2115 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9009 ) , .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9010 ) ) ; cby_1__1_ cby_6__12_ ( .pReset ( { SYNOPSYS_UNCONNECTED_9011 } ) , @@ -132640,16 +137179,16 @@ cby_1__1_ cby_6__12_ ( .Reset_W_out ( ResetWires[275] ) , .Reset_E_out ( ResetWires[277] ) , .prog_clk_0_W_in ( prog_clk_0_wires[249] ) , .prog_clk_0_S_out ( prog_clk_0_wires[250] ) , - .prog_clk_0_N_out ( prog_clk_0_wires[252] ) , .prog_clk_2_N_in ( p2203 ) , - .prog_clk_2_S_in ( p999 ) , + .prog_clk_0_N_out ( prog_clk_0_wires[252] ) , .prog_clk_2_N_in ( p2281 ) , + .prog_clk_2_S_in ( p287 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_9018 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_9019 ) , - .prog_clk_3_S_in ( p3091 ) , .prog_clk_3_N_in ( p2041 ) , + .prog_clk_3_S_in ( p2371 ) , .prog_clk_3_N_in ( p2165 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_9020 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9021 ) , .clk_2_N_in ( p3257 ) , - .clk_2_S_in ( p3225 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9022 ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9023 ) , .clk_3_S_in ( p3269 ) , - .clk_3_N_in ( p3206 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9024 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9021 ) , .clk_2_N_in ( p2978 ) , + .clk_2_S_in ( p3078 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9022 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9023 ) , .clk_3_S_in ( p3110 ) , + .clk_3_N_in ( p2886 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9024 ) , .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9025 ) ) ; cby_1__1_ cby_7__1_ ( .pReset ( { SYNOPSYS_UNCONNECTED_9026 } ) , @@ -132691,15 +137230,15 @@ cby_1__1_ cby_7__1_ ( .prog_clk_0_W_in ( prog_clk_0_wires[254] ) , .prog_clk_0_S_out ( prog_clk_0_wires[255] ) , .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_9036 ) , - .prog_clk_2_N_in ( p2249 ) , .prog_clk_2_S_in ( p49 ) , + .prog_clk_2_N_in ( p1906 ) , .prog_clk_2_S_in ( p646 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_9037 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_9038 ) , - .prog_clk_3_S_in ( p2784 ) , .prog_clk_3_N_in ( p2002 ) , + .prog_clk_3_S_in ( p2811 ) , .prog_clk_3_N_in ( p1722 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_9039 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9040 ) , .clk_2_N_in ( p3175 ) , - .clk_2_S_in ( p2727 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9041 ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9042 ) , .clk_3_S_in ( p2806 ) , - .clk_3_N_in ( p3133 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9043 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9040 ) , .clk_2_N_in ( p1558 ) , + .clk_2_S_in ( p2675 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9041 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9042 ) , .clk_3_S_in ( p2557 ) , + .clk_3_N_in ( p1013 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9043 ) , .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9044 ) ) ; cby_1__1_ cby_7__2_ ( .pReset ( { SYNOPSYS_UNCONNECTED_9045 } ) , @@ -132745,14 +137284,14 @@ cby_1__1_ cby_7__2_ ( .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_9056 ) , .prog_clk_2_S_out ( prog_clk_2_wires[74] ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_9057 ) , - .prog_clk_3_S_in ( p1548 ) , .prog_clk_3_N_in ( p1097 ) , + .prog_clk_3_S_in ( p1882 ) , .prog_clk_3_N_in ( p599 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_9058 ) , .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9059 ) , .clk_2_N_in ( clk_2_wires[73] ) , .clk_2_S_in ( SYNOPSYS_UNCONNECTED_9060 ) , .clk_2_S_out ( clk_2_wires[74] ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9061 ) , .clk_3_S_in ( p1548 ) , - .clk_3_N_in ( p111 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9062 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9061 ) , .clk_3_S_in ( p1882 ) , + .clk_3_N_in ( p113 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9062 ) , .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9063 ) ) ; cby_1__1_ cby_7__3_ ( .pReset ( { SYNOPSYS_UNCONNECTED_9064 } ) , @@ -132794,15 +137333,15 @@ cby_1__1_ cby_7__3_ ( .prog_clk_0_W_in ( prog_clk_0_wires[260] ) , .prog_clk_0_S_out ( prog_clk_0_wires[261] ) , .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_9074 ) , - .prog_clk_2_N_in ( p1508 ) , .prog_clk_2_S_in ( p741 ) , + .prog_clk_2_N_in ( p1519 ) , .prog_clk_2_S_in ( p30 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_9075 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_9076 ) , - .prog_clk_3_S_in ( p3193 ) , .prog_clk_3_N_in ( p31 ) , + .prog_clk_3_S_in ( p2357 ) , .prog_clk_3_N_in ( p732 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_9077 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9078 ) , .clk_2_N_in ( p2672 ) , - .clk_2_S_in ( p3134 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9079 ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9080 ) , .clk_3_S_in ( p2792 ) , - .clk_3_N_in ( p2594 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9081 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9078 ) , .clk_2_N_in ( p2960 ) , + .clk_2_S_in ( p2694 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9079 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9080 ) , .clk_3_S_in ( p2823 ) , + .clk_3_N_in ( p2894 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9081 ) , .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9082 ) ) ; cby_1__1_ cby_7__4_ ( .pReset ( { SYNOPSYS_UNCONNECTED_9083 } ) , @@ -132848,14 +137387,14 @@ cby_1__1_ cby_7__4_ ( .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_9094 ) , .prog_clk_2_S_out ( prog_clk_2_wires[85] ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_9095 ) , - .prog_clk_3_S_in ( p1812 ) , .prog_clk_3_N_in ( p748 ) , + .prog_clk_3_S_in ( p1927 ) , .prog_clk_3_N_in ( p742 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_9096 ) , .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9097 ) , .clk_2_N_in ( clk_2_wires[84] ) , .clk_2_S_in ( SYNOPSYS_UNCONNECTED_9098 ) , .clk_2_S_out ( clk_2_wires[85] ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9099 ) , .clk_3_S_in ( p1812 ) , - .clk_3_N_in ( p362 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9100 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9099 ) , .clk_3_S_in ( p1927 ) , + .clk_3_N_in ( p1074 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9100 ) , .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9101 ) ) ; cby_1__1_ cby_7__5_ ( .pReset ( { SYNOPSYS_UNCONNECTED_9102 } ) , @@ -132900,15 +137439,15 @@ cby_1__1_ cby_7__5_ ( .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_9113 ) , .prog_clk_2_S_in ( prog_clk_2_wires[82] ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_9114 ) , - .prog_clk_2_N_out ( prog_clk_2_wires[83] ) , .prog_clk_3_S_in ( p2163 ) , - .prog_clk_3_N_in ( p1014 ) , + .prog_clk_2_N_out ( prog_clk_2_wires[83] ) , .prog_clk_3_S_in ( p2322 ) , + .prog_clk_3_N_in ( p1073 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_9115 ) , .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9116 ) , .clk_2_N_in ( SYNOPSYS_UNCONNECTED_9117 ) , .clk_2_S_in ( clk_2_wires[82] ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9118 ) , - .clk_2_N_out ( clk_2_wires[83] ) , .clk_3_S_in ( p2163 ) , - .clk_3_N_in ( p559 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9119 ) , + .clk_2_N_out ( clk_2_wires[83] ) , .clk_3_S_in ( p2322 ) , + .clk_3_N_in ( p398 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9119 ) , .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9120 ) ) ; cby_1__1_ cby_7__6_ ( .pReset ( { SYNOPSYS_UNCONNECTED_9121 } ) , @@ -132950,15 +137489,15 @@ cby_1__1_ cby_7__6_ ( .prog_clk_0_W_in ( prog_clk_0_wires[269] ) , .prog_clk_0_S_out ( prog_clk_0_wires[270] ) , .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_9131 ) , - .prog_clk_2_N_in ( p2156 ) , .prog_clk_2_S_in ( p1035 ) , + .prog_clk_2_N_in ( p2013 ) , .prog_clk_2_S_in ( p481 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_9132 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_9133 ) , - .prog_clk_3_S_in ( p2214 ) , .prog_clk_3_N_in ( p2032 ) , + .prog_clk_3_S_in ( p2552 ) , .prog_clk_3_N_in ( p1759 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_9134 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9135 ) , .clk_2_N_in ( p3167 ) , - .clk_2_S_in ( p3414 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9136 ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9137 ) , .clk_3_S_in ( p3426 ) , - .clk_3_N_in ( p3150 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9138 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9135 ) , .clk_2_N_in ( p3324 ) , + .clk_2_S_in ( p3080 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9136 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9137 ) , .clk_3_S_in ( p3116 ) , + .clk_3_N_in ( p3292 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9138 ) , .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9139 ) ) ; cby_1__1_ cby_7__7_ ( .pReset ( { SYNOPSYS_UNCONNECTED_9140 } ) , @@ -133000,15 +137539,15 @@ cby_1__1_ cby_7__7_ ( .prog_clk_0_W_in ( prog_clk_0_wires[272] ) , .prog_clk_0_S_out ( prog_clk_0_wires[273] ) , .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_9150 ) , - .prog_clk_2_N_in ( p2714 ) , .prog_clk_2_S_in ( p2290 ) , + .prog_clk_2_N_in ( p1245 ) , .prog_clk_2_S_in ( p355 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_9151 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_9152 ) , - .prog_clk_3_S_in ( p2477 ) , .prog_clk_3_N_in ( p2592 ) , + .prog_clk_3_S_in ( p3344 ) , .prog_clk_3_N_in ( p65 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_9153 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9154 ) , .clk_2_N_in ( p2670 ) , - .clk_2_S_in ( p2362 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9155 ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9156 ) , .clk_3_S_in ( p2173 ) , - .clk_3_N_in ( p2563 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9157 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9154 ) , .clk_2_N_in ( p2771 ) , + .clk_2_S_in ( p3280 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9155 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9156 ) , .clk_3_S_in ( p3253 ) , + .clk_3_N_in ( p2695 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9157 ) , .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9158 ) ) ; cby_1__1_ cby_7__8_ ( .pReset ( { SYNOPSYS_UNCONNECTED_9159 } ) , @@ -133054,14 +137593,14 @@ cby_1__1_ cby_7__8_ ( .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_9170 ) , .prog_clk_2_S_out ( prog_clk_2_wires[98] ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_9171 ) , - .prog_clk_3_S_in ( p2143 ) , .prog_clk_3_N_in ( p76 ) , + .prog_clk_3_S_in ( p1154 ) , .prog_clk_3_N_in ( p681 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_9172 ) , .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9173 ) , .clk_2_N_in ( clk_2_wires[97] ) , .clk_2_S_in ( SYNOPSYS_UNCONNECTED_9174 ) , .clk_2_S_out ( clk_2_wires[98] ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9175 ) , .clk_3_S_in ( p2143 ) , - .clk_3_N_in ( p995 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9176 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9175 ) , .clk_3_S_in ( p1154 ) , + .clk_3_N_in ( p353 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9176 ) , .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9177 ) ) ; cby_1__1_ cby_7__9_ ( .pReset ( { SYNOPSYS_UNCONNECTED_9178 } ) , @@ -133106,15 +137645,15 @@ cby_1__1_ cby_7__9_ ( .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_9189 ) , .prog_clk_2_S_in ( prog_clk_2_wires[95] ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_9190 ) , - .prog_clk_2_N_out ( prog_clk_2_wires[96] ) , .prog_clk_3_S_in ( p1536 ) , - .prog_clk_3_N_in ( p422 ) , + .prog_clk_2_N_out ( prog_clk_2_wires[96] ) , .prog_clk_3_S_in ( p1496 ) , + .prog_clk_3_N_in ( p997 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_9191 ) , .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9192 ) , .clk_2_N_in ( SYNOPSYS_UNCONNECTED_9193 ) , .clk_2_S_in ( clk_2_wires[95] ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9194 ) , - .clk_2_N_out ( clk_2_wires[96] ) , .clk_3_S_in ( p1536 ) , - .clk_3_N_in ( p951 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9195 ) , + .clk_2_N_out ( clk_2_wires[96] ) , .clk_3_S_in ( p1496 ) , + .clk_3_N_in ( p80 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9195 ) , .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9196 ) ) ; cby_1__1_ cby_7__10_ ( .pReset ( { SYNOPSYS_UNCONNECTED_9197 } ) , @@ -133156,15 +137695,15 @@ cby_1__1_ cby_7__10_ ( .prog_clk_0_W_in ( prog_clk_0_wires[281] ) , .prog_clk_0_S_out ( prog_clk_0_wires[282] ) , .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_9207 ) , - .prog_clk_2_N_in ( p2260 ) , .prog_clk_2_S_in ( p933 ) , + .prog_clk_2_N_in ( p2223 ) , .prog_clk_2_S_in ( p1055 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_9208 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_9209 ) , - .prog_clk_3_S_in ( p2844 ) , .prog_clk_3_N_in ( p2034 ) , + .prog_clk_3_S_in ( p2789 ) , .prog_clk_3_N_in ( p2154 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_9210 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9211 ) , .clk_2_N_in ( p1505 ) , - .clk_2_S_in ( p2763 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9212 ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9213 ) , .clk_3_S_in ( p2517 ) , - .clk_3_N_in ( p288 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9214 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9211 ) , .clk_2_N_in ( p2953 ) , + .clk_2_S_in ( p2696 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9212 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9213 ) , .clk_3_S_in ( p2319 ) , + .clk_3_N_in ( p2890 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9214 ) , .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9215 ) ) ; cby_1__1_ cby_7__11_ ( .pReset ( { SYNOPSYS_UNCONNECTED_9216 } ) , @@ -133209,15 +137748,15 @@ cby_1__1_ cby_7__11_ ( .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_9227 ) , .prog_clk_2_S_in ( prog_clk_2_wires[108] ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_9228 ) , - .prog_clk_2_N_out ( prog_clk_2_wires[109] ) , .prog_clk_3_S_in ( p1961 ) , - .prog_clk_3_N_in ( p755 ) , + .prog_clk_2_N_out ( prog_clk_2_wires[109] ) , .prog_clk_3_S_in ( p1405 ) , + .prog_clk_3_N_in ( p714 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_9229 ) , .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9230 ) , .clk_2_N_in ( SYNOPSYS_UNCONNECTED_9231 ) , .clk_2_S_in ( clk_2_wires[108] ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9232 ) , - .clk_2_N_out ( clk_2_wires[109] ) , .clk_3_S_in ( p1961 ) , - .clk_3_N_in ( p732 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9233 ) , + .clk_2_N_out ( clk_2_wires[109] ) , .clk_3_S_in ( p1405 ) , + .clk_3_N_in ( p234 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9233 ) , .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9234 ) ) ; cby_1__1_ cby_7__12_ ( .pReset ( { SYNOPSYS_UNCONNECTED_9235 } ) , @@ -133258,16 +137797,16 @@ cby_1__1_ cby_7__12_ ( .Reset_E_out ( ResetWires[279] ) , .prog_clk_0_W_in ( prog_clk_0_wires[287] ) , .prog_clk_0_S_out ( prog_clk_0_wires[288] ) , - .prog_clk_0_N_out ( prog_clk_0_wires[290] ) , .prog_clk_2_N_in ( p2481 ) , - .prog_clk_2_S_in ( p850 ) , + .prog_clk_0_N_out ( prog_clk_0_wires[290] ) , .prog_clk_2_N_in ( p1229 ) , + .prog_clk_2_S_in ( p650 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_9245 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_9246 ) , - .prog_clk_3_S_in ( p1831 ) , .prog_clk_3_N_in ( p2329 ) , + .prog_clk_3_S_in ( p2511 ) , .prog_clk_3_N_in ( p383 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_9247 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9248 ) , .clk_2_N_in ( p2638 ) , - .clk_2_S_in ( p3119 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9249 ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9250 ) , .clk_3_S_in ( p3158 ) , - .clk_3_N_in ( p2552 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9251 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9248 ) , .clk_2_N_in ( p2937 ) , + .clk_2_S_in ( p2422 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9249 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9250 ) , .clk_3_S_in ( p2582 ) , + .clk_3_N_in ( p2899 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9251 ) , .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9252 ) ) ; cby_1__1_ cby_8__1_ ( .pReset ( { SYNOPSYS_UNCONNECTED_9253 } ) , @@ -133309,15 +137848,15 @@ cby_1__1_ cby_8__1_ ( .prog_clk_0_W_in ( prog_clk_0_wires[292] ) , .prog_clk_0_S_out ( prog_clk_0_wires[293] ) , .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_9263 ) , - .prog_clk_2_N_in ( p1440 ) , .prog_clk_2_S_in ( p267 ) , + .prog_clk_2_N_in ( p1470 ) , .prog_clk_2_S_in ( p391 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_9264 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_9265 ) , - .prog_clk_3_S_in ( p2945 ) , .prog_clk_3_N_in ( p1125 ) , + .prog_clk_3_S_in ( p2573 ) , .prog_clk_3_N_in ( p904 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_9266 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9267 ) , .clk_2_N_in ( p2966 ) , - .clk_2_S_in ( p3147 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9268 ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9269 ) , .clk_3_S_in ( p3184 ) , - .clk_3_N_in ( p2876 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9270 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9267 ) , .clk_2_N_in ( p1618 ) , + .clk_2_S_in ( p2414 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9268 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9269 ) , .clk_3_S_in ( p2318 ) , + .clk_3_N_in ( p314 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9270 ) , .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9271 ) ) ; cby_1__1_ cby_8__2_ ( .pReset ( { SYNOPSYS_UNCONNECTED_9272 } ) , @@ -133359,15 +137898,15 @@ cby_1__1_ cby_8__2_ ( .prog_clk_0_W_in ( prog_clk_0_wires[295] ) , .prog_clk_0_S_out ( prog_clk_0_wires[296] ) , .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_9282 ) , - .prog_clk_2_N_in ( p1578 ) , .prog_clk_2_S_in ( p107 ) , + .prog_clk_2_N_in ( p2307 ) , .prog_clk_2_S_in ( p146 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_9283 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_9284 ) , - .prog_clk_3_S_in ( p3065 ) , .prog_clk_3_N_in ( p124 ) , + .prog_clk_3_S_in ( p2841 ) , .prog_clk_3_N_in ( p2056 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_9285 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9286 ) , .clk_2_N_in ( p3088 ) , - .clk_2_S_in ( p3047 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9287 ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9288 ) , .clk_3_S_in ( p3105 ) , - .clk_3_N_in ( p3010 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9289 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9286 ) , .clk_2_N_in ( p3257 ) , + .clk_2_S_in ( p3075 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9287 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9288 ) , .clk_3_S_in ( p3136 ) , + .clk_3_N_in ( p3187 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9289 ) , .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9290 ) ) ; cby_1__1_ cby_8__3_ ( .pReset ( { SYNOPSYS_UNCONNECTED_9291 } ) , @@ -133409,14 +137948,14 @@ cby_1__1_ cby_8__3_ ( .prog_clk_0_W_in ( prog_clk_0_wires[298] ) , .prog_clk_0_S_out ( prog_clk_0_wires[299] ) , .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_9301 ) , - .prog_clk_2_N_in ( p2250 ) , .prog_clk_2_S_in ( p749 ) , + .prog_clk_2_N_in ( p1859 ) , .prog_clk_2_S_in ( p420 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_9302 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_9303 ) , .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_9304 ) , .prog_clk_3_N_in ( prog_clk_3_wires[42] ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_9305 ) , - .prog_clk_3_S_out ( prog_clk_3_wires[43] ) , .clk_2_N_in ( p2250 ) , - .clk_2_S_in ( p33 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9306 ) , + .prog_clk_3_S_out ( prog_clk_3_wires[43] ) , .clk_2_N_in ( p1859 ) , + .clk_2_S_in ( p32 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9306 ) , .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9307 ) , .clk_3_S_in ( SYNOPSYS_UNCONNECTED_9308 ) , .clk_3_N_in ( clk_3_wires[42] ) , @@ -133462,14 +138001,14 @@ cby_1__1_ cby_8__4_ ( .prog_clk_0_W_in ( prog_clk_0_wires[301] ) , .prog_clk_0_S_out ( prog_clk_0_wires[302] ) , .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_9320 ) , - .prog_clk_2_N_in ( p1364 ) , .prog_clk_2_S_in ( p2063 ) , + .prog_clk_2_N_in ( p1283 ) , .prog_clk_2_S_in ( p447 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_9321 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_9322 ) , .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_9323 ) , .prog_clk_3_N_in ( prog_clk_3_wires[38] ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_9324 ) , - .prog_clk_3_S_out ( prog_clk_3_wires[39] ) , .clk_2_N_in ( p1364 ) , - .clk_2_S_in ( p2024 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9325 ) , + .prog_clk_3_S_out ( prog_clk_3_wires[39] ) , .clk_2_N_in ( p1283 ) , + .clk_2_S_in ( p2108 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9325 ) , .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9326 ) , .clk_3_S_in ( SYNOPSYS_UNCONNECTED_9327 ) , .clk_3_N_in ( clk_3_wires[38] ) , @@ -133515,14 +138054,14 @@ cby_1__1_ cby_8__5_ ( .prog_clk_0_W_in ( prog_clk_0_wires[304] ) , .prog_clk_0_S_out ( prog_clk_0_wires[305] ) , .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_9339 ) , - .prog_clk_2_N_in ( p1860 ) , .prog_clk_2_S_in ( p32 ) , + .prog_clk_2_N_in ( p2261 ) , .prog_clk_2_S_in ( p1700 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_9340 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_9341 ) , .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_9342 ) , .prog_clk_3_N_in ( prog_clk_3_wires[32] ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_9343 ) , - .prog_clk_3_S_out ( prog_clk_3_wires[33] ) , .clk_2_N_in ( p1860 ) , - .clk_2_S_in ( p940 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9344 ) , + .prog_clk_3_S_out ( prog_clk_3_wires[33] ) , .clk_2_N_in ( p2197 ) , + .clk_2_S_in ( p31 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9344 ) , .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9345 ) , .clk_3_S_in ( SYNOPSYS_UNCONNECTED_9346 ) , .clk_3_N_in ( clk_3_wires[32] ) , @@ -133568,14 +138107,14 @@ cby_1__1_ cby_8__6_ ( .prog_clk_0_W_in ( prog_clk_0_wires[307] ) , .prog_clk_0_S_out ( prog_clk_0_wires[308] ) , .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_9358 ) , - .prog_clk_2_N_in ( p1949 ) , .prog_clk_2_S_in ( p1739 ) , + .prog_clk_2_N_in ( p1396 ) , .prog_clk_2_S_in ( p1735 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_9359 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_9360 ) , .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_9361 ) , .prog_clk_3_N_in ( prog_clk_3_wires[28] ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_9362 ) , - .prog_clk_3_S_out ( prog_clk_3_wires[29] ) , .clk_2_N_in ( p1949 ) , - .clk_2_S_in ( p1646 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9363 ) , + .prog_clk_3_S_out ( prog_clk_3_wires[29] ) , .clk_2_N_in ( p1396 ) , + .clk_2_S_in ( p2421 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9363 ) , .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9364 ) , .clk_3_S_in ( SYNOPSYS_UNCONNECTED_9365 ) , .clk_3_N_in ( clk_3_wires[28] ) , @@ -133621,14 +138160,14 @@ cby_1__1_ cby_8__7_ ( .prog_clk_0_W_in ( prog_clk_0_wires[310] ) , .prog_clk_0_S_out ( prog_clk_0_wires[311] ) , .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_9377 ) , - .prog_clk_2_N_in ( p1778 ) , .prog_clk_2_S_in ( p2887 ) , + .prog_clk_2_N_in ( p1522 ) , .prog_clk_2_S_in ( p1808 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_9378 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_9379 ) , .prog_clk_3_S_in ( prog_clk_3_wires[26] ) , .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_9380 ) , .prog_clk_3_N_out ( prog_clk_3_wires[27] ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9381 ) , .clk_2_N_in ( p1778 ) , - .clk_2_S_in ( p2912 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9382 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9381 ) , .clk_2_N_in ( p1522 ) , + .clk_2_S_in ( p1698 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9382 ) , .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9383 ) , .clk_3_S_in ( clk_3_wires[26] ) , .clk_3_N_in ( SYNOPSYS_UNCONNECTED_9384 ) , @@ -133674,14 +138213,14 @@ cby_1__1_ cby_8__8_ ( .prog_clk_0_W_in ( prog_clk_0_wires[313] ) , .prog_clk_0_S_out ( prog_clk_0_wires[314] ) , .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_9396 ) , - .prog_clk_2_N_in ( p1387 ) , .prog_clk_2_S_in ( p2272 ) , + .prog_clk_2_N_in ( p1431 ) , .prog_clk_2_S_in ( p2378 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_9397 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_9398 ) , .prog_clk_3_S_in ( prog_clk_3_wires[30] ) , .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_9399 ) , .prog_clk_3_N_out ( prog_clk_3_wires[31] ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9400 ) , .clk_2_N_in ( p1387 ) , - .clk_2_S_in ( p2340 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9401 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9400 ) , .clk_2_N_in ( p1431 ) , + .clk_2_S_in ( p2458 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9401 ) , .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9402 ) , .clk_3_S_in ( clk_3_wires[30] ) , .clk_3_N_in ( SYNOPSYS_UNCONNECTED_9403 ) , @@ -133727,14 +138266,14 @@ cby_1__1_ cby_8__9_ ( .prog_clk_0_W_in ( prog_clk_0_wires[316] ) , .prog_clk_0_S_out ( prog_clk_0_wires[317] ) , .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_9415 ) , - .prog_clk_2_N_in ( p2207 ) , .prog_clk_2_S_in ( p1648 ) , + .prog_clk_2_N_in ( p1644 ) , .prog_clk_2_S_in ( p144 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_9416 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_9417 ) , .prog_clk_3_S_in ( prog_clk_3_wires[36] ) , .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_9418 ) , .prog_clk_3_N_out ( prog_clk_3_wires[37] ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9419 ) , .clk_2_N_in ( p2207 ) , - .clk_2_S_in ( p851 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9420 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9419 ) , .clk_2_N_in ( p1644 ) , + .clk_2_S_in ( p567 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9420 ) , .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9421 ) , .clk_3_S_in ( clk_3_wires[36] ) , .clk_3_N_in ( SYNOPSYS_UNCONNECTED_9422 ) , @@ -133780,14 +138319,14 @@ cby_1__1_ cby_8__10_ ( .prog_clk_0_W_in ( prog_clk_0_wires[319] ) , .prog_clk_0_S_out ( prog_clk_0_wires[320] ) , .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_9434 ) , - .prog_clk_2_N_in ( p2103 ) , .prog_clk_2_S_in ( p2071 ) , + .prog_clk_2_N_in ( p2372 ) , .prog_clk_2_S_in ( p1732 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_9435 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_9436 ) , .prog_clk_3_S_in ( prog_clk_3_wires[40] ) , .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_9437 ) , .prog_clk_3_N_out ( prog_clk_3_wires[41] ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9438 ) , .clk_2_N_in ( p2103 ) , - .clk_2_S_in ( p2312 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9439 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9438 ) , .clk_2_N_in ( p2208 ) , + .clk_2_S_in ( p1780 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9439 ) , .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9440 ) , .clk_3_S_in ( clk_3_wires[40] ) , .clk_3_N_in ( SYNOPSYS_UNCONNECTED_9441 ) , @@ -133833,15 +138372,15 @@ cby_1__1_ cby_8__11_ ( .prog_clk_0_W_in ( prog_clk_0_wires[322] ) , .prog_clk_0_S_out ( prog_clk_0_wires[323] ) , .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_9453 ) , - .prog_clk_2_N_in ( p1857 ) , .prog_clk_2_S_in ( p570 ) , + .prog_clk_2_N_in ( p2215 ) , .prog_clk_2_S_in ( p834 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_9454 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_9455 ) , - .prog_clk_3_S_in ( p3205 ) , .prog_clk_3_N_in ( p1705 ) , + .prog_clk_3_S_in ( p2845 ) , .prog_clk_3_N_in ( p2121 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_9456 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9457 ) , .clk_2_N_in ( p2621 ) , - .clk_2_S_in ( p3135 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9458 ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9459 ) , .clk_3_S_in ( p2474 ) , - .clk_3_N_in ( p2527 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9460 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9457 ) , .clk_2_N_in ( p2032 ) , + .clk_2_S_in ( p2879 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9458 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9459 ) , .clk_3_S_in ( p2992 ) , + .clk_3_N_in ( p1703 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9460 ) , .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9461 ) ) ; cby_1__1_ cby_8__12_ ( .pReset ( { SYNOPSYS_UNCONNECTED_9462 } ) , @@ -133882,16 +138421,16 @@ cby_1__1_ cby_8__12_ ( .Reset_E_out ( ResetWires[281] ) , .prog_clk_0_W_in ( prog_clk_0_wires[325] ) , .prog_clk_0_S_out ( prog_clk_0_wires[326] ) , - .prog_clk_0_N_out ( prog_clk_0_wires[328] ) , .prog_clk_2_N_in ( p2677 ) , - .prog_clk_2_S_in ( p229 ) , + .prog_clk_0_N_out ( prog_clk_0_wires[328] ) , .prog_clk_2_N_in ( p2588 ) , + .prog_clk_2_S_in ( p282 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_9472 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_9473 ) , - .prog_clk_3_S_in ( p2469 ) , .prog_clk_3_N_in ( p2589 ) , + .prog_clk_3_S_in ( p2806 ) , .prog_clk_3_N_in ( p2419 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_9474 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9475 ) , .clk_2_N_in ( p2785 ) , - .clk_2_S_in ( p2296 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9476 ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9477 ) , .clk_3_S_in ( p2510 ) , - .clk_3_N_in ( p2737 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9478 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9475 ) , .clk_2_N_in ( p1899 ) , + .clk_2_S_in ( p3298 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9476 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9477 ) , .clk_3_S_in ( p3327 ) , + .clk_3_N_in ( p1816 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9478 ) , .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9479 ) ) ; cby_1__1_ cby_9__1_ ( .pReset ( { SYNOPSYS_UNCONNECTED_9480 } ) , @@ -133933,15 +138472,15 @@ cby_1__1_ cby_9__1_ ( .prog_clk_0_W_in ( prog_clk_0_wires[330] ) , .prog_clk_0_S_out ( prog_clk_0_wires[331] ) , .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_9490 ) , - .prog_clk_2_N_in ( p2679 ) , .prog_clk_2_S_in ( p905 ) , + .prog_clk_2_N_in ( p2272 ) , .prog_clk_2_S_in ( p467 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_9491 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_9492 ) , - .prog_clk_3_S_in ( p1852 ) , .prog_clk_3_N_in ( p2565 ) , + .prog_clk_3_S_in ( p3346 ) , .prog_clk_3_N_in ( p2148 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_9493 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9494 ) , .clk_2_N_in ( p2499 ) , - .clk_2_S_in ( p1986 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9495 ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9496 ) , .clk_3_S_in ( p2208 ) , - .clk_3_N_in ( p2300 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9497 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9494 ) , .clk_2_N_in ( p3108 ) , + .clk_2_S_in ( p3285 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9495 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9496 ) , .clk_3_S_in ( p2857 ) , + .clk_3_N_in ( p3045 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9497 ) , .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9498 ) ) ; cby_1__1_ cby_9__2_ ( .pReset ( { SYNOPSYS_UNCONNECTED_9499 } ) , @@ -133987,14 +138526,14 @@ cby_1__1_ cby_9__2_ ( .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_9510 ) , .prog_clk_2_S_out ( prog_clk_2_wires[76] ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_9511 ) , - .prog_clk_3_S_in ( p1617 ) , .prog_clk_3_N_in ( p69 ) , + .prog_clk_3_S_in ( p2201 ) , .prog_clk_3_N_in ( p841 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_9512 ) , .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9513 ) , .clk_2_N_in ( clk_2_wires[75] ) , .clk_2_S_in ( SYNOPSYS_UNCONNECTED_9514 ) , .clk_2_S_out ( clk_2_wires[76] ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9515 ) , .clk_3_S_in ( p1617 ) , - .clk_3_N_in ( p701 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9516 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9515 ) , .clk_3_S_in ( p2201 ) , + .clk_3_N_in ( p291 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9516 ) , .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9517 ) ) ; cby_1__1_ cby_9__3_ ( .pReset ( { SYNOPSYS_UNCONNECTED_9518 } ) , @@ -134036,15 +138575,15 @@ cby_1__1_ cby_9__3_ ( .prog_clk_0_W_in ( prog_clk_0_wires[336] ) , .prog_clk_0_S_out ( prog_clk_0_wires[337] ) , .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_9528 ) , - .prog_clk_2_N_in ( p2200 ) , .prog_clk_2_S_in ( p245 ) , + .prog_clk_2_N_in ( p2611 ) , .prog_clk_2_S_in ( p569 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_9529 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_9530 ) , - .prog_clk_3_S_in ( p2810 ) , .prog_clk_3_N_in ( p2004 ) , + .prog_clk_3_S_in ( p2335 ) , .prog_clk_3_N_in ( p2404 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_9531 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9532 ) , .clk_2_N_in ( p3157 ) , - .clk_2_S_in ( p3122 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9533 ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9534 ) , .clk_3_S_in ( p3163 ) , - .clk_3_N_in ( p3154 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9535 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9532 ) , .clk_2_N_in ( p2815 ) , + .clk_2_S_in ( p2699 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9533 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9534 ) , .clk_3_S_in ( p2782 ) , + .clk_3_N_in ( p2644 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9535 ) , .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9536 ) ) ; cby_1__1_ cby_9__4_ ( .pReset ( { SYNOPSYS_UNCONNECTED_9537 } ) , @@ -134090,14 +138629,14 @@ cby_1__1_ cby_9__4_ ( .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_9548 ) , .prog_clk_2_S_out ( prog_clk_2_wires[89] ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_9549 ) , - .prog_clk_3_S_in ( p1259 ) , .prog_clk_3_N_in ( p1039 ) , + .prog_clk_3_S_in ( p2364 ) , .prog_clk_3_N_in ( p915 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_9550 ) , .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9551 ) , .clk_2_N_in ( clk_2_wires[88] ) , .clk_2_S_in ( SYNOPSYS_UNCONNECTED_9552 ) , .clk_2_S_out ( clk_2_wires[89] ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9553 ) , .clk_3_S_in ( p1259 ) , - .clk_3_N_in ( p322 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9554 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9553 ) , .clk_3_S_in ( p2364 ) , + .clk_3_N_in ( p856 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9554 ) , .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9555 ) ) ; cby_1__1_ cby_9__5_ ( .pReset ( { SYNOPSYS_UNCONNECTED_9556 } ) , @@ -134142,15 +138681,15 @@ cby_1__1_ cby_9__5_ ( .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_9567 ) , .prog_clk_2_S_in ( prog_clk_2_wires[86] ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_9568 ) , - .prog_clk_2_N_out ( prog_clk_2_wires[87] ) , .prog_clk_3_S_in ( p2140 ) , - .prog_clk_3_N_in ( p12 ) , + .prog_clk_2_N_out ( prog_clk_2_wires[87] ) , .prog_clk_3_S_in ( p1972 ) , + .prog_clk_3_N_in ( p921 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_9569 ) , .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9570 ) , .clk_2_N_in ( SYNOPSYS_UNCONNECTED_9571 ) , .clk_2_S_in ( clk_2_wires[86] ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9572 ) , - .clk_2_N_out ( clk_2_wires[87] ) , .clk_3_S_in ( p2140 ) , - .clk_3_N_in ( p859 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9573 ) , + .clk_2_N_out ( clk_2_wires[87] ) , .clk_3_S_in ( p1972 ) , + .clk_3_N_in ( p14 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9573 ) , .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9574 ) ) ; cby_1__1_ cby_9__6_ ( .pReset ( { SYNOPSYS_UNCONNECTED_9575 } ) , @@ -134192,15 +138731,15 @@ cby_1__1_ cby_9__6_ ( .prog_clk_0_W_in ( prog_clk_0_wires[345] ) , .prog_clk_0_S_out ( prog_clk_0_wires[346] ) , .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_9585 ) , - .prog_clk_2_N_in ( p2232 ) , .prog_clk_2_S_in ( p428 ) , + .prog_clk_2_N_in ( p2765 ) , .prog_clk_2_S_in ( p261 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_9586 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_9587 ) , - .prog_clk_3_S_in ( p2935 ) , .prog_clk_3_N_in ( p2055 ) , + .prog_clk_3_S_in ( p2050 ) , .prog_clk_3_N_in ( p2650 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_9588 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9589 ) , .clk_2_N_in ( p2978 ) , - .clk_2_S_in ( p2874 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9590 ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9591 ) , .clk_3_S_in ( p2137 ) , - .clk_3_N_in ( p2900 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9592 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9589 ) , .clk_2_N_in ( p2308 ) , + .clk_2_S_in ( p2403 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9590 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9591 ) , .clk_3_S_in ( p2610 ) , + .clk_3_N_in ( p2152 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9592 ) , .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9593 ) ) ; cby_1__1_ cby_9__7_ ( .pReset ( { SYNOPSYS_UNCONNECTED_9594 } ) , @@ -134242,15 +138781,15 @@ cby_1__1_ cby_9__7_ ( .prog_clk_0_W_in ( prog_clk_0_wires[348] ) , .prog_clk_0_S_out ( prog_clk_0_wires[349] ) , .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_9604 ) , - .prog_clk_2_N_in ( p2990 ) , .prog_clk_2_S_in ( p1660 ) , + .prog_clk_2_N_in ( p2505 ) , .prog_clk_2_S_in ( p1801 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_9605 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_9606 ) , - .prog_clk_3_S_in ( p2656 ) , .prog_clk_3_N_in ( p2921 ) , + .prog_clk_3_S_in ( p2772 ) , .prog_clk_3_N_in ( p2391 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_9607 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9608 ) , .clk_2_N_in ( p2961 ) , - .clk_2_S_in ( p2717 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9609 ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9610 ) , .clk_3_S_in ( p2782 ) , - .clk_3_N_in ( p2873 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9611 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9608 ) , .clk_2_N_in ( p3005 ) , + .clk_2_S_in ( p2662 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9609 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9610 ) , .clk_3_S_in ( p2749 ) , + .clk_3_N_in ( p2900 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9611 ) , .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9612 ) ) ; cby_1__1_ cby_9__8_ ( .pReset ( { SYNOPSYS_UNCONNECTED_9613 } ) , @@ -134296,14 +138835,14 @@ cby_1__1_ cby_9__8_ ( .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_9624 ) , .prog_clk_2_S_out ( prog_clk_2_wires[102] ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_9625 ) , - .prog_clk_3_S_in ( p1842 ) , .prog_clk_3_N_in ( p278 ) , + .prog_clk_3_S_in ( p1303 ) , .prog_clk_3_N_in ( p1014 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_9626 ) , .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9627 ) , .clk_2_N_in ( clk_2_wires[101] ) , .clk_2_S_in ( SYNOPSYS_UNCONNECTED_9628 ) , .clk_2_S_out ( clk_2_wires[102] ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9629 ) , .clk_3_S_in ( p1842 ) , - .clk_3_N_in ( p499 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9630 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9629 ) , .clk_3_S_in ( p1303 ) , + .clk_3_N_in ( p143 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9630 ) , .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9631 ) ) ; cby_1__1_ cby_9__9_ ( .pReset ( { SYNOPSYS_UNCONNECTED_9632 } ) , @@ -134348,15 +138887,15 @@ cby_1__1_ cby_9__9_ ( .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_9643 ) , .prog_clk_2_S_in ( prog_clk_2_wires[99] ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_9644 ) , - .prog_clk_2_N_out ( prog_clk_2_wires[100] ) , .prog_clk_3_S_in ( p1463 ) , - .prog_clk_3_N_in ( p785 ) , + .prog_clk_2_N_out ( prog_clk_2_wires[100] ) , .prog_clk_3_S_in ( p1643 ) , + .prog_clk_3_N_in ( p164 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_9645 ) , .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9646 ) , .clk_2_N_in ( SYNOPSYS_UNCONNECTED_9647 ) , .clk_2_S_in ( clk_2_wires[99] ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9648 ) , - .clk_2_N_out ( clk_2_wires[100] ) , .clk_3_S_in ( p1463 ) , - .clk_3_N_in ( p896 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9649 ) , + .clk_2_N_out ( clk_2_wires[100] ) , .clk_3_S_in ( p1643 ) , + .clk_3_N_in ( p913 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9649 ) , .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9650 ) ) ; cby_1__1_ cby_9__10_ ( .pReset ( { SYNOPSYS_UNCONNECTED_9651 } ) , @@ -134398,15 +138937,15 @@ cby_1__1_ cby_9__10_ ( .prog_clk_0_W_in ( prog_clk_0_wires[357] ) , .prog_clk_0_S_out ( prog_clk_0_wires[358] ) , .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_9661 ) , - .prog_clk_2_N_in ( p1173 ) , .prog_clk_2_S_in ( p424 ) , + .prog_clk_2_N_in ( p1401 ) , .prog_clk_2_S_in ( p251 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_9662 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_9663 ) , - .prog_clk_3_S_in ( p2815 ) , .prog_clk_3_N_in ( p1068 ) , + .prog_clk_3_S_in ( p2263 ) , .prog_clk_3_N_in ( p740 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_9664 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9665 ) , .clk_2_N_in ( p2828 ) , - .clk_2_S_in ( p2880 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9666 ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9667 ) , .clk_3_S_in ( p2941 ) , - .clk_3_N_in ( p2746 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9668 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9665 ) , .clk_2_N_in ( p2623 ) , + .clk_2_S_in ( p2653 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9666 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9667 ) , .clk_3_S_in ( p2763 ) , + .clk_3_N_in ( p2412 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9668 ) , .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9669 ) ) ; cby_1__1_ cby_9__11_ ( .pReset ( { SYNOPSYS_UNCONNECTED_9670 } ) , @@ -134451,15 +138990,15 @@ cby_1__1_ cby_9__11_ ( .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_9681 ) , .prog_clk_2_S_in ( prog_clk_2_wires[110] ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_9682 ) , - .prog_clk_2_N_out ( prog_clk_2_wires[111] ) , .prog_clk_3_S_in ( p1580 ) , - .prog_clk_3_N_in ( p420 ) , + .prog_clk_2_N_out ( prog_clk_2_wires[111] ) , .prog_clk_3_S_in ( p1286 ) , + .prog_clk_3_N_in ( p651 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_9683 ) , .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9684 ) , .clk_2_N_in ( SYNOPSYS_UNCONNECTED_9685 ) , .clk_2_S_in ( clk_2_wires[110] ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9686 ) , - .clk_2_N_out ( clk_2_wires[111] ) , .clk_3_S_in ( p1580 ) , - .clk_3_N_in ( p493 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9687 ) , + .clk_2_N_out ( clk_2_wires[111] ) , .clk_3_S_in ( p1286 ) , + .clk_3_N_in ( p775 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9687 ) , .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9688 ) ) ; cby_1__1_ cby_9__12_ ( .pReset ( { SYNOPSYS_UNCONNECTED_9689 } ) , @@ -134500,16 +139039,16 @@ cby_1__1_ cby_9__12_ ( .Reset_E_out ( ResetWires[283] ) , .prog_clk_0_W_in ( prog_clk_0_wires[363] ) , .prog_clk_0_S_out ( prog_clk_0_wires[364] ) , - .prog_clk_0_N_out ( prog_clk_0_wires[366] ) , .prog_clk_2_N_in ( p2786 ) , - .prog_clk_2_S_in ( p463 ) , + .prog_clk_0_N_out ( prog_clk_0_wires[366] ) , .prog_clk_2_N_in ( p1593 ) , + .prog_clk_2_S_in ( p472 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_9699 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_9700 ) , - .prog_clk_3_S_in ( p3266 ) , .prog_clk_3_N_in ( p2772 ) , + .prog_clk_3_S_in ( p3026 ) , .prog_clk_3_N_in ( p770 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_9701 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9702 ) , .clk_2_N_in ( p3059 ) , - .clk_2_S_in ( p3238 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9703 ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9704 ) , .clk_3_S_in ( p3195 ) , - .clk_3_N_in ( p3032 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9705 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9702 ) , .clk_2_N_in ( p1929 ) , + .clk_2_S_in ( p2916 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9703 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9704 ) , .clk_3_S_in ( p2758 ) , + .clk_3_N_in ( p1685 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9705 ) , .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9706 ) ) ; cby_1__1_ cby_10__1_ ( .pReset ( { SYNOPSYS_UNCONNECTED_9707 } ) , @@ -134551,15 +139090,15 @@ cby_1__1_ cby_10__1_ ( .prog_clk_0_W_in ( prog_clk_0_wires[368] ) , .prog_clk_0_S_out ( prog_clk_0_wires[369] ) , .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_9717 ) , - .prog_clk_2_N_in ( p1788 ) , .prog_clk_2_S_in ( p171 ) , + .prog_clk_2_N_in ( p1865 ) , .prog_clk_2_S_in ( p643 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_9718 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_9719 ) , - .prog_clk_3_S_in ( p2217 ) , .prog_clk_3_N_in ( p1716 ) , + .prog_clk_3_S_in ( p2341 ) , .prog_clk_3_N_in ( p1804 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_9720 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9721 ) , .clk_2_N_in ( p2627 ) , - .clk_2_S_in ( p2031 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9722 ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9723 ) , .clk_3_S_in ( p2221 ) , - .clk_3_N_in ( p2524 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9724 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9721 ) , .clk_2_N_in ( p3354 ) , + .clk_2_S_in ( p2123 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9722 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9723 ) , .clk_3_S_in ( p2029 ) , + .clk_3_N_in ( p3290 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9724 ) , .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9725 ) ) ; cby_1__1_ cby_10__2_ ( .pReset ( { SYNOPSYS_UNCONNECTED_9726 } ) , @@ -134601,15 +139140,15 @@ cby_1__1_ cby_10__2_ ( .prog_clk_0_W_in ( prog_clk_0_wires[371] ) , .prog_clk_0_S_out ( prog_clk_0_wires[372] ) , .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_9736 ) , - .prog_clk_2_N_in ( p2148 ) , .prog_clk_2_S_in ( p932 ) , + .prog_clk_2_N_in ( p1619 ) , .prog_clk_2_S_in ( p301 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_9737 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_9738 ) , - .prog_clk_3_S_in ( p2664 ) , .prog_clk_3_N_in ( p2089 ) , + .prog_clk_3_S_in ( p2609 ) , .prog_clk_3_N_in ( p154 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_9739 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9740 ) , .clk_2_N_in ( p2856 ) , - .clk_2_S_in ( p2603 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9741 ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9742 ) , .clk_3_S_in ( p2116 ) , - .clk_3_N_in ( p2744 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9743 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9740 ) , .clk_2_N_in ( p3158 ) , + .clk_2_S_in ( p2668 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9741 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9742 ) , .clk_3_S_in ( p2853 ) , + .clk_3_N_in ( p3058 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9743 ) , .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9744 ) ) ; cby_1__1_ cby_10__3_ ( .pReset ( { SYNOPSYS_UNCONNECTED_9745 } ) , @@ -134651,14 +139190,14 @@ cby_1__1_ cby_10__3_ ( .prog_clk_0_W_in ( prog_clk_0_wires[374] ) , .prog_clk_0_S_out ( prog_clk_0_wires[375] ) , .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_9755 ) , - .prog_clk_2_N_in ( p1918 ) , .prog_clk_2_S_in ( p1065 ) , + .prog_clk_2_N_in ( p1913 ) , .prog_clk_2_S_in ( p648 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_9756 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_9757 ) , .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_9758 ) , .prog_clk_3_N_in ( prog_clk_3_wires[86] ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_9759 ) , - .prog_clk_3_S_out ( prog_clk_3_wires[87] ) , .clk_2_N_in ( p1838 ) , - .clk_2_S_in ( p736 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9760 ) , + .prog_clk_3_S_out ( prog_clk_3_wires[87] ) , .clk_2_N_in ( p1913 ) , + .clk_2_S_in ( p896 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9760 ) , .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9761 ) , .clk_3_S_in ( SYNOPSYS_UNCONNECTED_9762 ) , .clk_3_N_in ( clk_3_wires[86] ) , @@ -134704,14 +139243,14 @@ cby_1__1_ cby_10__4_ ( .prog_clk_0_W_in ( prog_clk_0_wires[377] ) , .prog_clk_0_S_out ( prog_clk_0_wires[378] ) , .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_9774 ) , - .prog_clk_2_N_in ( p1437 ) , .prog_clk_2_S_in ( p2559 ) , + .prog_clk_2_N_in ( p1437 ) , .prog_clk_2_S_in ( p1696 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_9775 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_9776 ) , .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_9777 ) , .prog_clk_3_N_in ( prog_clk_3_wires[82] ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_9778 ) , .prog_clk_3_S_out ( prog_clk_3_wires[83] ) , .clk_2_N_in ( p1437 ) , - .clk_2_S_in ( p2864 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9779 ) , + .clk_2_S_in ( p1826 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9779 ) , .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9780 ) , .clk_3_S_in ( SYNOPSYS_UNCONNECTED_9781 ) , .clk_3_N_in ( clk_3_wires[82] ) , @@ -134757,14 +139296,14 @@ cby_1__1_ cby_10__5_ ( .prog_clk_0_W_in ( prog_clk_0_wires[380] ) , .prog_clk_0_S_out ( prog_clk_0_wires[381] ) , .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_9793 ) , - .prog_clk_2_N_in ( p1120 ) , .prog_clk_2_S_in ( p317 ) , + .prog_clk_2_N_in ( p1446 ) , .prog_clk_2_S_in ( p891 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_9794 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_9795 ) , .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_9796 ) , .prog_clk_3_N_in ( prog_clk_3_wires[76] ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_9797 ) , - .prog_clk_3_S_out ( prog_clk_3_wires[77] ) , .clk_2_N_in ( p1120 ) , - .clk_2_S_in ( p899 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9798 ) , + .prog_clk_3_S_out ( prog_clk_3_wires[77] ) , .clk_2_N_in ( p1446 ) , + .clk_2_S_in ( p77 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9798 ) , .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9799 ) , .clk_3_S_in ( SYNOPSYS_UNCONNECTED_9800 ) , .clk_3_N_in ( clk_3_wires[76] ) , @@ -134810,14 +139349,14 @@ cby_1__1_ cby_10__6_ ( .prog_clk_0_W_in ( prog_clk_0_wires[383] ) , .prog_clk_0_S_out ( prog_clk_0_wires[384] ) , .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_9812 ) , - .prog_clk_2_N_in ( p1897 ) , .prog_clk_2_S_in ( p2528 ) , + .prog_clk_2_N_in ( p1466 ) , .prog_clk_2_S_in ( p2719 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_9813 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_9814 ) , .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_9815 ) , .prog_clk_3_N_in ( prog_clk_3_wires[72] ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_9816 ) , - .prog_clk_3_S_out ( prog_clk_3_wires[73] ) , .clk_2_N_in ( p1917 ) , - .clk_2_S_in ( p2601 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9817 ) , + .prog_clk_3_S_out ( prog_clk_3_wires[73] ) , .clk_2_N_in ( p1466 ) , + .clk_2_S_in ( p2875 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9817 ) , .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9818 ) , .clk_3_S_in ( SYNOPSYS_UNCONNECTED_9819 ) , .clk_3_N_in ( clk_3_wires[72] ) , @@ -134863,14 +139402,14 @@ cby_1__1_ cby_10__7_ ( .prog_clk_0_W_in ( prog_clk_0_wires[386] ) , .prog_clk_0_S_out ( prog_clk_0_wires[387] ) , .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_9831 ) , - .prog_clk_2_N_in ( p1532 ) , .prog_clk_2_S_in ( p2087 ) , + .prog_clk_2_N_in ( p1569 ) , .prog_clk_2_S_in ( p416 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_9832 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_9833 ) , .prog_clk_3_S_in ( prog_clk_3_wires[70] ) , .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_9834 ) , .prog_clk_3_N_out ( prog_clk_3_wires[71] ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9835 ) , .clk_2_N_in ( p1532 ) , - .clk_2_S_in ( p2030 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9836 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9835 ) , .clk_2_N_in ( p1569 ) , + .clk_2_S_in ( p2396 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9836 ) , .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9837 ) , .clk_3_S_in ( clk_3_wires[70] ) , .clk_3_N_in ( SYNOPSYS_UNCONNECTED_9838 ) , @@ -134916,14 +139455,14 @@ cby_1__1_ cby_10__8_ ( .prog_clk_0_W_in ( prog_clk_0_wires[389] ) , .prog_clk_0_S_out ( prog_clk_0_wires[390] ) , .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_9850 ) , - .prog_clk_2_N_in ( p1612 ) , .prog_clk_2_S_in ( p2731 ) , + .prog_clk_2_N_in ( p1544 ) , .prog_clk_2_S_in ( p250 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_9851 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_9852 ) , .prog_clk_3_S_in ( prog_clk_3_wires[74] ) , .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_9853 ) , .prog_clk_3_N_out ( prog_clk_3_wires[75] ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9854 ) , .clk_2_N_in ( p1612 ) , - .clk_2_S_in ( p2770 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9855 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9854 ) , .clk_2_N_in ( p1544 ) , + .clk_2_S_in ( p824 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9855 ) , .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9856 ) , .clk_3_S_in ( clk_3_wires[74] ) , .clk_3_N_in ( SYNOPSYS_UNCONNECTED_9857 ) , @@ -134969,14 +139508,14 @@ cby_1__1_ cby_10__9_ ( .prog_clk_0_W_in ( prog_clk_0_wires[392] ) , .prog_clk_0_S_out ( prog_clk_0_wires[393] ) , .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_9869 ) , - .prog_clk_2_N_in ( p1923 ) , .prog_clk_2_S_in ( p2039 ) , + .prog_clk_2_N_in ( p1950 ) , .prog_clk_2_S_in ( p450 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_9870 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_9871 ) , .prog_clk_3_S_in ( prog_clk_3_wires[80] ) , .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_9872 ) , .prog_clk_3_N_out ( prog_clk_3_wires[81] ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9873 ) , .clk_2_N_in ( p1923 ) , - .clk_2_S_in ( p702 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9874 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9873 ) , .clk_2_N_in ( p1950 ) , + .clk_2_S_in ( p224 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9874 ) , .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9875 ) , .clk_3_S_in ( clk_3_wires[80] ) , .clk_3_N_in ( SYNOPSYS_UNCONNECTED_9876 ) , @@ -135022,14 +139561,14 @@ cby_1__1_ cby_10__10_ ( .prog_clk_0_W_in ( prog_clk_0_wires[395] ) , .prog_clk_0_S_out ( prog_clk_0_wires[396] ) , .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_9888 ) , - .prog_clk_2_N_in ( p2134 ) , .prog_clk_2_S_in ( p1641 ) , + .prog_clk_2_N_in ( p1345 ) , .prog_clk_2_S_in ( p2071 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_9889 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_9890 ) , .prog_clk_3_S_in ( prog_clk_3_wires[84] ) , .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_9891 ) , .prog_clk_3_N_out ( prog_clk_3_wires[85] ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9892 ) , .clk_2_N_in ( p2134 ) , - .clk_2_S_in ( p1721 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9893 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9892 ) , .clk_2_N_in ( p1345 ) , + .clk_2_S_in ( p2877 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9893 ) , .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9894 ) , .clk_3_S_in ( clk_3_wires[84] ) , .clk_3_N_in ( SYNOPSYS_UNCONNECTED_9895 ) , @@ -135075,15 +139614,15 @@ cby_1__1_ cby_10__11_ ( .prog_clk_0_W_in ( prog_clk_0_wires[398] ) , .prog_clk_0_S_out ( prog_clk_0_wires[399] ) , .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_9907 ) , - .prog_clk_2_N_in ( p2520 ) , .prog_clk_2_S_in ( p735 ) , + .prog_clk_2_N_in ( p1634 ) , .prog_clk_2_S_in ( p661 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_9908 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_9909 ) , - .prog_clk_3_S_in ( p2813 ) , .prog_clk_3_N_in ( p2328 ) , + .prog_clk_3_S_in ( p2954 ) , .prog_clk_3_N_in ( p939 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_9910 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9911 ) , .clk_2_N_in ( p2220 ) , - .clk_2_S_in ( p3115 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9912 ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9913 ) , .clk_3_S_in ( p3185 ) , - .clk_3_N_in ( p2023 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9914 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9911 ) , .clk_2_N_in ( p2601 ) , + .clk_2_S_in ( p2864 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9912 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9913 ) , .clk_3_S_in ( p2820 ) , + .clk_3_N_in ( p2382 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9914 ) , .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9915 ) ) ; cby_1__1_ cby_10__12_ ( .pReset ( { SYNOPSYS_UNCONNECTED_9916 } ) , @@ -135124,16 +139663,16 @@ cby_1__1_ cby_10__12_ ( .Reset_E_out ( ResetWires[285] ) , .prog_clk_0_W_in ( prog_clk_0_wires[401] ) , .prog_clk_0_S_out ( prog_clk_0_wires[402] ) , - .prog_clk_0_N_out ( prog_clk_0_wires[404] ) , .prog_clk_2_N_in ( p2405 ) , - .prog_clk_2_S_in ( p504 ) , + .prog_clk_0_N_out ( prog_clk_0_wires[404] ) , .prog_clk_2_N_in ( p1962 ) , + .prog_clk_2_S_in ( p1030 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_9926 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_9927 ) , - .prog_clk_3_S_in ( p2971 ) , .prog_clk_3_N_in ( p2374 ) , + .prog_clk_3_S_in ( p1584 ) , .prog_clk_3_N_in ( p1751 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_9928 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9929 ) , .clk_2_N_in ( p2954 ) , - .clk_2_S_in ( p3155 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9930 ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9931 ) , .clk_3_S_in ( p3180 ) , - .clk_3_N_in ( p2865 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9932 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9929 ) , .clk_2_N_in ( p2643 ) , + .clk_2_S_in ( p2410 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9930 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9931 ) , .clk_3_S_in ( p2485 ) , + .clk_3_N_in ( p2439 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9932 ) , .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9933 ) ) ; cby_1__1_ cby_11__1_ ( .pReset ( { SYNOPSYS_UNCONNECTED_9934 } ) , @@ -135175,15 +139714,15 @@ cby_1__1_ cby_11__1_ ( .prog_clk_0_W_in ( prog_clk_0_wires[406] ) , .prog_clk_0_S_out ( prog_clk_0_wires[407] ) , .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_9944 ) , - .prog_clk_2_N_in ( p2246 ) , .prog_clk_2_S_in ( p657 ) , + .prog_clk_2_N_in ( p2220 ) , .prog_clk_2_S_in ( p1001 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_9945 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_9946 ) , - .prog_clk_3_S_in ( p2829 ) , .prog_clk_3_N_in ( p2052 ) , + .prog_clk_3_S_in ( p2226 ) , .prog_clk_3_N_in ( p2133 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_9947 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9948 ) , .clk_2_N_in ( p3258 ) , - .clk_2_S_in ( p2724 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9949 ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9950 ) , .clk_3_S_in ( p1485 ) , - .clk_3_N_in ( p3213 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9951 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9948 ) , .clk_2_N_in ( p1570 ) , + .clk_2_S_in ( p2885 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9949 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9950 ) , .clk_3_S_in ( p2989 ) , + .clk_3_N_in ( p879 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9951 ) , .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9952 ) ) ; cby_1__1_ cby_11__2_ ( .pReset ( { SYNOPSYS_UNCONNECTED_9953 } ) , @@ -135229,14 +139768,14 @@ cby_1__1_ cby_11__2_ ( .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_9964 ) , .prog_clk_2_S_out ( prog_clk_2_wires[116] ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_9965 ) , - .prog_clk_3_S_in ( p1309 ) , .prog_clk_3_N_in ( p44 ) , + .prog_clk_3_S_in ( p2005 ) , .prog_clk_3_N_in ( p192 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_9966 ) , .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9967 ) , .clk_2_N_in ( clk_2_wires[115] ) , .clk_2_S_in ( SYNOPSYS_UNCONNECTED_9968 ) , .clk_2_S_out ( clk_2_wires[116] ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9969 ) , .clk_3_S_in ( p1309 ) , - .clk_3_N_in ( p477 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9970 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9969 ) , .clk_3_S_in ( p2005 ) , + .clk_3_N_in ( p979 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9970 ) , .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9971 ) ) ; cby_1__1_ cby_11__3_ ( .pReset ( { SYNOPSYS_UNCONNECTED_9972 } ) , @@ -135278,15 +139817,15 @@ cby_1__1_ cby_11__3_ ( .prog_clk_0_W_in ( prog_clk_0_wires[412] ) , .prog_clk_0_S_out ( prog_clk_0_wires[413] ) , .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_9982 ) , - .prog_clk_2_N_in ( p2984 ) , .prog_clk_2_S_in ( p568 ) , + .prog_clk_2_N_in ( p1844 ) , .prog_clk_2_S_in ( p925 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_9983 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_9984 ) , - .prog_clk_3_S_in ( p2172 ) , .prog_clk_3_N_in ( p2901 ) , + .prog_clk_3_S_in ( p2010 ) , .prog_clk_3_N_in ( p1750 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_9985 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9986 ) , .clk_2_N_in ( p3404 ) , - .clk_2_S_in ( p3139 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9987 ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9988 ) , .clk_3_S_in ( p3178 ) , - .clk_3_N_in ( p3384 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9989 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9986 ) , .clk_2_N_in ( p2994 ) , + .clk_2_S_in ( p2138 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9987 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9988 ) , .clk_3_S_in ( p2287 ) , + .clk_3_N_in ( p2880 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9989 ) , .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9990 ) ) ; cby_1__1_ cby_11__4_ ( .pReset ( { SYNOPSYS_UNCONNECTED_9991 } ) , @@ -135332,14 +139871,14 @@ cby_1__1_ cby_11__4_ ( .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_10002 ) , .prog_clk_2_S_out ( prog_clk_2_wires[123] ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_10003 ) , - .prog_clk_3_S_in ( p1761 ) , .prog_clk_3_N_in ( p183 ) , + .prog_clk_3_S_in ( p1409 ) , .prog_clk_3_N_in ( p188 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_10004 ) , .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_10005 ) , .clk_2_N_in ( clk_2_wires[122] ) , .clk_2_S_in ( SYNOPSYS_UNCONNECTED_10006 ) , .clk_2_S_out ( clk_2_wires[123] ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_10007 ) , .clk_3_S_in ( p1761 ) , - .clk_3_N_in ( p1032 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_10008 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_10007 ) , .clk_3_S_in ( p1409 ) , + .clk_3_N_in ( p767 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_10008 ) , .clk_3_S_out ( SYNOPSYS_UNCONNECTED_10009 ) ) ; cby_1__1_ cby_11__5_ ( .pReset ( { SYNOPSYS_UNCONNECTED_10010 } ) , @@ -135384,15 +139923,15 @@ cby_1__1_ cby_11__5_ ( .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_10021 ) , .prog_clk_2_S_in ( prog_clk_2_wires[120] ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_10022 ) , - .prog_clk_2_N_out ( prog_clk_2_wires[121] ) , .prog_clk_3_S_in ( p1441 ) , - .prog_clk_3_N_in ( p969 ) , + .prog_clk_2_N_out ( prog_clk_2_wires[121] ) , .prog_clk_3_S_in ( p1161 ) , + .prog_clk_3_N_in ( p579 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_10023 ) , .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_10024 ) , .clk_2_N_in ( SYNOPSYS_UNCONNECTED_10025 ) , .clk_2_S_in ( clk_2_wires[120] ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_10026 ) , - .clk_2_N_out ( clk_2_wires[121] ) , .clk_3_S_in ( p1441 ) , - .clk_3_N_in ( p1049 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_10027 ) , + .clk_2_N_out ( clk_2_wires[121] ) , .clk_3_S_in ( p1589 ) , + .clk_3_N_in ( p485 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_10027 ) , .clk_3_S_out ( SYNOPSYS_UNCONNECTED_10028 ) ) ; cby_1__1_ cby_11__6_ ( .pReset ( { SYNOPSYS_UNCONNECTED_10029 } ) , @@ -135434,15 +139973,15 @@ cby_1__1_ cby_11__6_ ( .prog_clk_0_W_in ( prog_clk_0_wires[421] ) , .prog_clk_0_S_out ( prog_clk_0_wires[422] ) , .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_10039 ) , - .prog_clk_2_N_in ( p1895 ) , .prog_clk_2_S_in ( p781 ) , + .prog_clk_2_N_in ( p2768 ) , .prog_clk_2_S_in ( p262 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_10040 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_10041 ) , - .prog_clk_3_S_in ( p2518 ) , .prog_clk_3_N_in ( p1699 ) , + .prog_clk_3_S_in ( p2849 ) , .prog_clk_3_N_in ( p2723 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_10042 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_10043 ) , .clk_2_N_in ( p2212 ) , - .clk_2_S_in ( p3339 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_10044 ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_10045 ) , .clk_3_S_in ( p3365 ) , - .clk_3_N_in ( p2065 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_10046 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_10043 ) , .clk_2_N_in ( p2942 ) , + .clk_2_S_in ( p2711 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_10044 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_10045 ) , .clk_3_S_in ( p1587 ) , + .clk_3_N_in ( p2869 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_10046 ) , .clk_3_S_out ( SYNOPSYS_UNCONNECTED_10047 ) ) ; cby_1__1_ cby_11__7_ ( .pReset ( { SYNOPSYS_UNCONNECTED_10048 } ) , @@ -135484,15 +140023,15 @@ cby_1__1_ cby_11__7_ ( .prog_clk_0_W_in ( prog_clk_0_wires[424] ) , .prog_clk_0_S_out ( prog_clk_0_wires[425] ) , .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_10058 ) , - .prog_clk_2_N_in ( p2092 ) , .prog_clk_2_S_in ( p458 ) , + .prog_clk_2_N_in ( p1351 ) , .prog_clk_2_S_in ( p766 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_10059 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_10060 ) , - .prog_clk_3_S_in ( p2690 ) , .prog_clk_3_N_in ( p2061 ) , + .prog_clk_3_S_in ( p2950 ) , .prog_clk_3_N_in ( p1163 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_10061 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_10062 ) , .clk_2_N_in ( p2657 ) , - .clk_2_S_in ( p3048 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_10063 ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_10064 ) , .clk_3_S_in ( p3084 ) , - .clk_3_N_in ( p2547 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_10065 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_10062 ) , .clk_2_N_in ( p3014 ) , + .clk_2_S_in ( p2919 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_10063 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_10064 ) , .clk_3_S_in ( p2951 ) , + .clk_3_N_in ( p2912 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_10065 ) , .clk_3_S_out ( SYNOPSYS_UNCONNECTED_10066 ) ) ; cby_1__1_ cby_11__8_ ( .pReset ( { SYNOPSYS_UNCONNECTED_10067 } ) , @@ -135538,14 +140077,14 @@ cby_1__1_ cby_11__8_ ( .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_10078 ) , .prog_clk_2_S_out ( prog_clk_2_wires[130] ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_10079 ) , - .prog_clk_3_S_in ( p1893 ) , .prog_clk_3_N_in ( p574 ) , + .prog_clk_3_S_in ( p1568 ) , .prog_clk_3_N_in ( p1051 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_10080 ) , .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_10081 ) , .clk_2_N_in ( clk_2_wires[129] ) , .clk_2_S_in ( SYNOPSYS_UNCONNECTED_10082 ) , .clk_2_S_out ( clk_2_wires[130] ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_10083 ) , .clk_3_S_in ( p1893 ) , - .clk_3_N_in ( p983 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_10084 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_10083 ) , .clk_3_S_in ( p1568 ) , + .clk_3_N_in ( p239 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_10084 ) , .clk_3_S_out ( SYNOPSYS_UNCONNECTED_10085 ) ) ; cby_1__1_ cby_11__9_ ( .pReset ( { SYNOPSYS_UNCONNECTED_10086 } ) , @@ -135590,15 +140129,15 @@ cby_1__1_ cby_11__9_ ( .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_10097 ) , .prog_clk_2_S_in ( prog_clk_2_wires[127] ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_10098 ) , - .prog_clk_2_N_out ( prog_clk_2_wires[128] ) , .prog_clk_3_S_in ( p1948 ) , - .prog_clk_3_N_in ( p1094 ) , + .prog_clk_2_N_out ( prog_clk_2_wires[128] ) , .prog_clk_3_S_in ( p1938 ) , + .prog_clk_3_N_in ( p713 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_10099 ) , .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_10100 ) , .clk_2_N_in ( SYNOPSYS_UNCONNECTED_10101 ) , .clk_2_S_in ( clk_2_wires[127] ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_10102 ) , - .clk_2_N_out ( clk_2_wires[128] ) , .clk_3_S_in ( p1948 ) , - .clk_3_N_in ( p243 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_10103 ) , + .clk_2_N_out ( clk_2_wires[128] ) , .clk_3_S_in ( p1938 ) , + .clk_3_N_in ( p102 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_10103 ) , .clk_3_S_out ( SYNOPSYS_UNCONNECTED_10104 ) ) ; cby_1__1_ cby_11__10_ ( .pReset ( { SYNOPSYS_UNCONNECTED_10105 } ) , @@ -135640,15 +140179,15 @@ cby_1__1_ cby_11__10_ ( .prog_clk_0_W_in ( prog_clk_0_wires[433] ) , .prog_clk_0_S_out ( prog_clk_0_wires[434] ) , .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_10115 ) , - .prog_clk_2_N_in ( p2975 ) , .prog_clk_2_S_in ( p324 ) , + .prog_clk_2_N_in ( p1535 ) , .prog_clk_2_S_in ( p877 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_10116 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_10117 ) , - .prog_clk_3_S_in ( p2858 ) , .prog_clk_3_N_in ( p2890 ) , + .prog_clk_3_S_in ( p2784 ) , .prog_clk_3_N_in ( p986 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_10118 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_10119 ) , .clk_2_N_in ( p3263 ) , - .clk_2_S_in ( p3208 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_10120 ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_10121 ) , .clk_3_S_in ( p3265 ) , - .clk_3_N_in ( p3227 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_10122 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_10119 ) , .clk_2_N_in ( p2602 ) , + .clk_2_S_in ( p2689 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_10120 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_10121 ) , .clk_3_S_in ( p2842 ) , + .clk_3_N_in ( p2452 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_10122 ) , .clk_3_S_out ( SYNOPSYS_UNCONNECTED_10123 ) ) ; cby_1__1_ cby_11__11_ ( .pReset ( { SYNOPSYS_UNCONNECTED_10124 } ) , @@ -135693,15 +140232,15 @@ cby_1__1_ cby_11__11_ ( .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_10135 ) , .prog_clk_2_S_in ( prog_clk_2_wires[134] ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_10136 ) , - .prog_clk_2_N_out ( prog_clk_2_wires[135] ) , .prog_clk_3_S_in ( p1295 ) , - .prog_clk_3_N_in ( p852 ) , + .prog_clk_2_N_out ( prog_clk_2_wires[135] ) , .prog_clk_3_S_in ( p1463 ) , + .prog_clk_3_N_in ( p978 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_10137 ) , .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_10138 ) , .clk_2_N_in ( SYNOPSYS_UNCONNECTED_10139 ) , .clk_2_S_in ( clk_2_wires[134] ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_10140 ) , - .clk_2_N_out ( clk_2_wires[135] ) , .clk_3_S_in ( p1295 ) , - .clk_3_N_in ( p22 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_10141 ) , + .clk_2_N_out ( clk_2_wires[135] ) , .clk_3_S_in ( p1463 ) , + .clk_3_N_in ( p771 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_10141 ) , .clk_3_S_out ( SYNOPSYS_UNCONNECTED_10142 ) ) ; cby_1__1_ cby_11__12_ ( .pReset ( { SYNOPSYS_UNCONNECTED_10143 } ) , @@ -135742,16 +140281,16 @@ cby_1__1_ cby_11__12_ ( .Reset_E_out ( ResetWires[287] ) , .prog_clk_0_W_in ( prog_clk_0_wires[439] ) , .prog_clk_0_S_out ( prog_clk_0_wires[440] ) , - .prog_clk_0_N_out ( prog_clk_0_wires[442] ) , .prog_clk_2_N_in ( p1455 ) , - .prog_clk_2_S_in ( p496 ) , + .prog_clk_0_N_out ( prog_clk_0_wires[442] ) , .prog_clk_2_N_in ( p1598 ) , + .prog_clk_2_S_in ( p616 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_10153 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_10154 ) , - .prog_clk_3_S_in ( p2993 ) , .prog_clk_3_N_in ( p965 ) , + .prog_clk_3_S_in ( p2362 ) , .prog_clk_3_N_in ( p22 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_10155 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_10156 ) , .clk_2_N_in ( p2623 ) , - .clk_2_S_in ( p3013 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_10157 ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_10158 ) , .clk_3_S_in ( p3056 ) , - .clk_3_N_in ( p2529 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_10159 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_10156 ) , .clk_2_N_in ( p3022 ) , + .clk_2_S_in ( p2461 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_10157 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_10158 ) , .clk_3_S_in ( p2616 ) , + .clk_3_N_in ( p2901 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_10159 ) , .clk_3_S_out ( SYNOPSYS_UNCONNECTED_10160 ) ) ; cby_2__1_ cby_12__1_ ( .pReset ( { SYNOPSYS_UNCONNECTED_10161 } ) , @@ -138925,7 +143464,63 @@ fpga_core fpga_core_uut ( .pReset ( io_in[3] ) , .prog_clk ( io_in[37] ) , .p3502 ( optlc_net_3522 ) , .p3503 ( optlc_net_3523 ) , .p3504 ( optlc_net_3524 ) , .p3505 ( optlc_net_3525 ) , .p3506 ( optlc_net_3526 ) , .p3507 ( optlc_net_3527 ) , - .p3508 ( optlc_net_3528 ) , .p3509 ( optlc_net_3529 ) ) ; + .p3508 ( optlc_net_3528 ) , .p3509 ( optlc_net_3529 ) , + .p3510 ( optlc_net_3530 ) , .p3511 ( optlc_net_3531 ) , + .p3512 ( optlc_net_3532 ) , .p3513 ( optlc_net_3533 ) , + .p3514 ( optlc_net_3534 ) , .p3515 ( optlc_net_3535 ) , + .p3516 ( optlc_net_3536 ) , .p3517 ( optlc_net_3537 ) , + .p3518 ( optlc_net_3538 ) , .p3519 ( optlc_net_3539 ) , + .p3520 ( optlc_net_3540 ) , .p3521 ( optlc_net_3541 ) , + .p3522 ( optlc_net_3542 ) , .p3523 ( optlc_net_3543 ) , + .p3524 ( optlc_net_3544 ) , .p3525 ( optlc_net_3545 ) , + .p3526 ( optlc_net_3546 ) , .p3527 ( optlc_net_3547 ) , + .p3528 ( optlc_net_3548 ) , .p3529 ( optlc_net_3549 ) , + .p3530 ( optlc_net_3550 ) , .p3531 ( optlc_net_3551 ) , + .p3532 ( optlc_net_3552 ) , .p3533 ( optlc_net_3553 ) , + .p3534 ( optlc_net_3554 ) , .p3535 ( optlc_net_3555 ) , + .p3536 ( optlc_net_3556 ) , .p3537 ( optlc_net_3557 ) , + .p3538 ( optlc_net_3558 ) , .p3539 ( optlc_net_3559 ) , + .p3540 ( optlc_net_3560 ) , .p3541 ( optlc_net_3561 ) , + .p3542 ( optlc_net_3562 ) , .p3543 ( optlc_net_3563 ) , + .p3544 ( optlc_net_3564 ) , .p3545 ( optlc_net_3565 ) , + .p3546 ( optlc_net_3566 ) , .p3547 ( optlc_net_3567 ) , + .p3548 ( optlc_net_3568 ) , .p3549 ( optlc_net_3569 ) , + .p3550 ( optlc_net_3570 ) , .p3551 ( optlc_net_3571 ) , + .p3552 ( optlc_net_3572 ) , .p3553 ( optlc_net_3573 ) , + .p3554 ( optlc_net_3574 ) , .p3555 ( optlc_net_3575 ) , + .p3556 ( optlc_net_3576 ) , .p3557 ( optlc_net_3577 ) , + .p3558 ( optlc_net_3578 ) , .p3559 ( optlc_net_3579 ) , + .p3560 ( optlc_net_3580 ) , .p3561 ( optlc_net_3581 ) , + .p3562 ( optlc_net_3582 ) , .p3563 ( optlc_net_3583 ) , + .p3564 ( optlc_net_3584 ) , .p3565 ( optlc_net_3585 ) , + .p3566 ( optlc_net_3586 ) , .p3567 ( optlc_net_3587 ) , + .p3568 ( optlc_net_3588 ) , .p3569 ( optlc_net_3589 ) , + .p3570 ( optlc_net_3590 ) , .p3571 ( optlc_net_3591 ) , + .p3572 ( optlc_net_3592 ) , .p3573 ( optlc_net_3593 ) , + .p3574 ( optlc_net_3594 ) , .p3575 ( optlc_net_3595 ) , + .p3576 ( optlc_net_3596 ) , .p3577 ( optlc_net_3597 ) , + .p3578 ( optlc_net_3598 ) , .p3579 ( optlc_net_3599 ) , + .p3580 ( optlc_net_3600 ) , .p3581 ( optlc_net_3601 ) , + .p3582 ( optlc_net_3602 ) , .p3583 ( optlc_net_3603 ) , + .p3584 ( optlc_net_3604 ) , .p3585 ( optlc_net_3605 ) , + .p3586 ( optlc_net_3606 ) , .p3587 ( optlc_net_3607 ) , + .p3588 ( optlc_net_3608 ) , .p3589 ( optlc_net_3609 ) , + .p3590 ( optlc_net_3610 ) , .p3591 ( optlc_net_3611 ) , + .p3592 ( optlc_net_3612 ) , .p3593 ( optlc_net_3613 ) , + .p3594 ( optlc_net_3614 ) , .p3595 ( optlc_net_3615 ) , + .p3596 ( optlc_net_3616 ) , .p3597 ( optlc_net_3617 ) , + .p3598 ( optlc_net_3618 ) , .p3599 ( optlc_net_3619 ) , + .p3600 ( optlc_net_3620 ) , .p3601 ( optlc_net_3621 ) , + .p3602 ( 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optlc_543 ( .LO ( optlc_net_542 ) , .HI ( SYNOPSYS_UNCONNECTED_544 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_545 ( .LO ( optlc_net_543 ) , +sky130_fd_sc_hd__conb_1 optlc_544 ( .LO ( optlc_net_543 ) , .HI ( SYNOPSYS_UNCONNECTED_545 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_546 ( .LO ( optlc_net_544 ) , +sky130_fd_sc_hd__conb_1 optlc_545 ( .LO ( optlc_net_544 ) , .HI ( SYNOPSYS_UNCONNECTED_546 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_547 ( .LO ( optlc_net_545 ) , +sky130_fd_sc_hd__conb_1 optlc_546 ( .LO ( optlc_net_545 ) , .HI ( SYNOPSYS_UNCONNECTED_547 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_548 ( .LO ( optlc_net_546 ) , +sky130_fd_sc_hd__conb_1 optlc_547 ( .LO ( optlc_net_546 ) , .HI ( SYNOPSYS_UNCONNECTED_548 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_549 ( .LO ( optlc_net_547 ) , +sky130_fd_sc_hd__conb_1 optlc_548 ( .LO ( optlc_net_547 ) , .HI ( SYNOPSYS_UNCONNECTED_549 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_550 ( .LO ( optlc_net_548 ) , +sky130_fd_sc_hd__conb_1 optlc_549 ( .LO ( optlc_net_548 ) , .HI ( SYNOPSYS_UNCONNECTED_550 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_551 ( .LO ( optlc_net_549 ) , +sky130_fd_sc_hd__conb_1 optlc_550 ( .LO ( optlc_net_549 ) , .HI ( SYNOPSYS_UNCONNECTED_551 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_552 ( .LO ( optlc_net_550 ) , +sky130_fd_sc_hd__conb_1 optlc_551 ( .LO ( optlc_net_550 ) , .HI ( SYNOPSYS_UNCONNECTED_552 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_553 ( .LO ( optlc_net_551 ) , +sky130_fd_sc_hd__conb_1 optlc_552 ( .LO ( optlc_net_551 ) , .HI ( SYNOPSYS_UNCONNECTED_553 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_554 ( .LO ( optlc_net_552 ) , +sky130_fd_sc_hd__conb_1 optlc_553 ( .LO ( optlc_net_552 ) , .HI ( SYNOPSYS_UNCONNECTED_554 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_555 ( .LO ( optlc_net_553 ) , +sky130_fd_sc_hd__conb_1 optlc_554 ( .LO ( optlc_net_553 ) , .HI ( SYNOPSYS_UNCONNECTED_555 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_556 ( .LO ( optlc_net_554 ) , +sky130_fd_sc_hd__conb_1 optlc_555 ( .LO ( optlc_net_554 ) , .HI ( SYNOPSYS_UNCONNECTED_556 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_557 ( .LO ( optlc_net_555 ) , +sky130_fd_sc_hd__conb_1 optlc_556 ( .LO ( optlc_net_555 ) , .HI ( SYNOPSYS_UNCONNECTED_557 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_558 ( .LO ( optlc_net_556 ) , +sky130_fd_sc_hd__conb_1 optlc_557 ( .LO ( optlc_net_556 ) , .HI ( SYNOPSYS_UNCONNECTED_558 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_559 ( .LO ( optlc_net_557 ) , +sky130_fd_sc_hd__conb_1 optlc_558 ( .LO ( optlc_net_557 ) , .HI ( SYNOPSYS_UNCONNECTED_559 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_561 ( .LO ( optlc_net_558 ) , +sky130_fd_sc_hd__conb_1 optlc_559 ( .LO ( optlc_net_558 ) , .HI ( SYNOPSYS_UNCONNECTED_560 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_562 ( .LO ( optlc_net_559 ) , +sky130_fd_sc_hd__conb_1 optlc_560 ( .LO ( optlc_net_559 ) , .HI ( SYNOPSYS_UNCONNECTED_561 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_563 ( .LO ( optlc_net_560 ) , +sky130_fd_sc_hd__conb_1 optlc_561 ( .LO ( optlc_net_560 ) , .HI ( SYNOPSYS_UNCONNECTED_562 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_564 ( .LO ( optlc_net_561 ) , +sky130_fd_sc_hd__conb_1 optlc_562 ( .LO ( optlc_net_561 ) , .HI ( SYNOPSYS_UNCONNECTED_563 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_565 ( .LO ( optlc_net_562 ) , +sky130_fd_sc_hd__conb_1 optlc_563 ( .LO ( optlc_net_562 ) , .HI ( SYNOPSYS_UNCONNECTED_564 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_566 ( .LO ( optlc_net_563 ) , +sky130_fd_sc_hd__conb_1 optlc_564 ( .LO ( optlc_net_563 ) , .HI ( SYNOPSYS_UNCONNECTED_565 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_567 ( .LO ( optlc_net_564 ) , +sky130_fd_sc_hd__conb_1 optlc_565 ( .LO ( optlc_net_564 ) , .HI ( SYNOPSYS_UNCONNECTED_566 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_568 ( .LO ( optlc_net_565 ) , +sky130_fd_sc_hd__conb_1 optlc_566 ( .LO ( optlc_net_565 ) , .HI ( SYNOPSYS_UNCONNECTED_567 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_569 ( .LO ( optlc_net_566 ) , +sky130_fd_sc_hd__conb_1 optlc_567 ( .LO ( optlc_net_566 ) , .HI ( SYNOPSYS_UNCONNECTED_568 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_570 ( .LO ( optlc_net_567 ) , +sky130_fd_sc_hd__conb_1 optlc_568 ( .LO ( optlc_net_567 ) , .HI ( SYNOPSYS_UNCONNECTED_569 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_571 ( .LO ( optlc_net_568 ) , +sky130_fd_sc_hd__conb_1 optlc_569 ( .LO ( optlc_net_568 ) , .HI ( SYNOPSYS_UNCONNECTED_570 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_572 ( .LO ( optlc_net_569 ) , +sky130_fd_sc_hd__conb_1 optlc_570 ( .LO ( optlc_net_569 ) , .HI ( SYNOPSYS_UNCONNECTED_571 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_573 ( .LO ( optlc_net_570 ) , +sky130_fd_sc_hd__conb_1 optlc_571 ( .LO ( optlc_net_570 ) , .HI ( SYNOPSYS_UNCONNECTED_572 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_574 ( .LO ( optlc_net_571 ) , +sky130_fd_sc_hd__conb_1 optlc_572 ( .LO ( optlc_net_571 ) , .HI ( SYNOPSYS_UNCONNECTED_573 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_575 ( .LO ( optlc_net_572 ) , +sky130_fd_sc_hd__conb_1 optlc_573 ( .LO ( optlc_net_572 ) , .HI ( SYNOPSYS_UNCONNECTED_574 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_576 ( .LO ( optlc_net_573 ) , +sky130_fd_sc_hd__conb_1 optlc_574 ( .LO ( optlc_net_573 ) , .HI ( SYNOPSYS_UNCONNECTED_575 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_577 ( .LO ( optlc_net_574 ) , +sky130_fd_sc_hd__conb_1 optlc_575 ( .LO ( optlc_net_574 ) , .HI ( SYNOPSYS_UNCONNECTED_576 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_578 ( .LO ( optlc_net_575 ) , +sky130_fd_sc_hd__conb_1 optlc_576 ( .LO ( optlc_net_575 ) , .HI ( SYNOPSYS_UNCONNECTED_577 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_579 ( .LO ( optlc_net_576 ) , +sky130_fd_sc_hd__conb_1 optlc_577 ( .LO ( optlc_net_576 ) , .HI ( SYNOPSYS_UNCONNECTED_578 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_580 ( .LO ( optlc_net_577 ) , +sky130_fd_sc_hd__conb_1 optlc_578 ( .LO ( optlc_net_577 ) , .HI ( SYNOPSYS_UNCONNECTED_579 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_581 ( .LO ( optlc_net_578 ) , +sky130_fd_sc_hd__conb_1 optlc_579 ( .LO ( optlc_net_578 ) , .HI ( SYNOPSYS_UNCONNECTED_580 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_582 ( .LO ( optlc_net_579 ) , +sky130_fd_sc_hd__conb_1 optlc_580 ( .LO ( optlc_net_579 ) , .HI ( SYNOPSYS_UNCONNECTED_581 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_583 ( .LO ( optlc_net_580 ) , +sky130_fd_sc_hd__conb_1 optlc_581 ( .LO ( optlc_net_580 ) , .HI ( SYNOPSYS_UNCONNECTED_582 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_584 ( .LO ( optlc_net_581 ) , +sky130_fd_sc_hd__conb_1 optlc_582 ( .LO ( optlc_net_581 ) , .HI ( SYNOPSYS_UNCONNECTED_583 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_585 ( .LO ( optlc_net_582 ) , +sky130_fd_sc_hd__conb_1 optlc_583 ( .LO ( optlc_net_582 ) , .HI ( SYNOPSYS_UNCONNECTED_584 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_586 ( .LO ( optlc_net_583 ) , +sky130_fd_sc_hd__conb_1 optlc_584 ( .LO ( optlc_net_583 ) , .HI ( SYNOPSYS_UNCONNECTED_585 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_587 ( .LO ( optlc_net_584 ) , +sky130_fd_sc_hd__conb_1 optlc_585 ( .LO ( optlc_net_584 ) , .HI ( SYNOPSYS_UNCONNECTED_586 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_588 ( .LO ( optlc_net_585 ) , +sky130_fd_sc_hd__conb_1 optlc_586 ( .LO ( optlc_net_585 ) , .HI ( SYNOPSYS_UNCONNECTED_587 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_589 ( .LO ( optlc_net_586 ) , +sky130_fd_sc_hd__conb_1 optlc_587 ( .LO ( optlc_net_586 ) , .HI ( SYNOPSYS_UNCONNECTED_588 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_590 ( .LO ( optlc_net_587 ) , +sky130_fd_sc_hd__conb_1 optlc_588 ( .LO ( optlc_net_587 ) , .HI ( SYNOPSYS_UNCONNECTED_589 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_591 ( .LO ( optlc_net_588 ) , +sky130_fd_sc_hd__conb_1 optlc_589 ( .LO ( optlc_net_588 ) , .HI ( SYNOPSYS_UNCONNECTED_590 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_592 ( .LO ( optlc_net_589 ) , +sky130_fd_sc_hd__conb_1 optlc_590 ( .LO ( optlc_net_589 ) , .HI ( SYNOPSYS_UNCONNECTED_591 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_593 ( .LO ( optlc_net_590 ) , +sky130_fd_sc_hd__conb_1 optlc_591 ( .LO ( optlc_net_590 ) , .HI ( SYNOPSYS_UNCONNECTED_592 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_594 ( .LO ( optlc_net_591 ) , +sky130_fd_sc_hd__conb_1 optlc_592 ( .LO ( optlc_net_591 ) , .HI ( SYNOPSYS_UNCONNECTED_593 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_595 ( .LO ( optlc_net_592 ) , +sky130_fd_sc_hd__conb_1 optlc_593 ( .LO ( optlc_net_592 ) , .HI ( SYNOPSYS_UNCONNECTED_594 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_596 ( .LO ( optlc_net_593 ) , +sky130_fd_sc_hd__conb_1 optlc_594 ( .LO ( optlc_net_593 ) , .HI ( SYNOPSYS_UNCONNECTED_595 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_597 ( .LO ( optlc_net_594 ) , +sky130_fd_sc_hd__conb_1 optlc_595 ( .LO ( optlc_net_594 ) , .HI ( SYNOPSYS_UNCONNECTED_596 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_598 ( .LO ( optlc_net_595 ) , +sky130_fd_sc_hd__conb_1 optlc_596 ( .LO ( optlc_net_595 ) , .HI ( SYNOPSYS_UNCONNECTED_597 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_599 ( .LO ( optlc_net_596 ) , +sky130_fd_sc_hd__conb_1 optlc_597 ( .LO ( optlc_net_596 ) , .HI ( SYNOPSYS_UNCONNECTED_598 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_600 ( .LO ( optlc_net_597 ) , +sky130_fd_sc_hd__conb_1 optlc_598 ( .LO ( optlc_net_597 ) , .HI ( SYNOPSYS_UNCONNECTED_599 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_601 ( .LO ( optlc_net_598 ) , +sky130_fd_sc_hd__conb_1 optlc_599 ( .LO ( optlc_net_598 ) , .HI ( SYNOPSYS_UNCONNECTED_600 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_602 ( .LO ( optlc_net_599 ) , +sky130_fd_sc_hd__conb_1 optlc_600 ( .LO ( optlc_net_599 ) , .HI ( SYNOPSYS_UNCONNECTED_601 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_603 ( .LO ( optlc_net_600 ) , +sky130_fd_sc_hd__conb_1 optlc_601 ( .LO ( optlc_net_600 ) , .HI ( SYNOPSYS_UNCONNECTED_602 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_604 ( .LO ( optlc_net_601 ) , +sky130_fd_sc_hd__conb_1 optlc_602 ( .LO ( optlc_net_601 ) , .HI ( SYNOPSYS_UNCONNECTED_603 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_605 ( .LO ( optlc_net_602 ) , +sky130_fd_sc_hd__conb_1 optlc_603 ( .LO ( optlc_net_602 ) , .HI ( SYNOPSYS_UNCONNECTED_604 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_606 ( .LO ( optlc_net_603 ) , +sky130_fd_sc_hd__conb_1 optlc_604 ( .LO ( optlc_net_603 ) , .HI ( SYNOPSYS_UNCONNECTED_605 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_607 ( .LO ( optlc_net_604 ) , +sky130_fd_sc_hd__conb_1 optlc_605 ( .LO ( optlc_net_604 ) , .HI ( SYNOPSYS_UNCONNECTED_606 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_608 ( .LO ( optlc_net_605 ) , +sky130_fd_sc_hd__conb_1 optlc_606 ( .LO ( optlc_net_605 ) , .HI ( SYNOPSYS_UNCONNECTED_607 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_609 ( .LO ( optlc_net_606 ) , +sky130_fd_sc_hd__conb_1 optlc_607 ( .LO ( optlc_net_606 ) , .HI ( SYNOPSYS_UNCONNECTED_608 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_610 ( .LO ( optlc_net_607 ) , +sky130_fd_sc_hd__conb_1 optlc_608 ( .LO ( optlc_net_607 ) , .HI ( SYNOPSYS_UNCONNECTED_609 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_611 ( .LO ( optlc_net_608 ) , +sky130_fd_sc_hd__conb_1 optlc_609 ( .LO ( optlc_net_608 ) , .HI ( SYNOPSYS_UNCONNECTED_610 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_612 ( .LO ( optlc_net_609 ) , +sky130_fd_sc_hd__conb_1 optlc_610 ( .LO ( optlc_net_609 ) , .HI ( SYNOPSYS_UNCONNECTED_611 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_613 ( .LO ( optlc_net_610 ) , +sky130_fd_sc_hd__conb_1 optlc_611 ( .LO ( optlc_net_610 ) , .HI ( SYNOPSYS_UNCONNECTED_612 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_614 ( .LO ( optlc_net_611 ) , +sky130_fd_sc_hd__conb_1 optlc_612 ( .LO ( optlc_net_611 ) , .HI ( SYNOPSYS_UNCONNECTED_613 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_615 ( .LO ( optlc_net_612 ) , +sky130_fd_sc_hd__conb_1 optlc_613 ( .LO ( optlc_net_612 ) , .HI ( SYNOPSYS_UNCONNECTED_614 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_616 ( .LO ( optlc_net_613 ) , +sky130_fd_sc_hd__conb_1 optlc_614 ( .LO ( optlc_net_613 ) , .HI ( SYNOPSYS_UNCONNECTED_615 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_617 ( .LO ( optlc_net_614 ) , +sky130_fd_sc_hd__conb_1 optlc_615 ( .LO ( optlc_net_614 ) , .HI ( SYNOPSYS_UNCONNECTED_616 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_618 ( .LO ( optlc_net_615 ) , +sky130_fd_sc_hd__conb_1 optlc_616 ( .LO ( optlc_net_615 ) , .HI ( SYNOPSYS_UNCONNECTED_617 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_619 ( .LO ( optlc_net_616 ) , +sky130_fd_sc_hd__conb_1 optlc_617 ( .LO ( optlc_net_616 ) , .HI ( SYNOPSYS_UNCONNECTED_618 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_620 ( .LO ( optlc_net_617 ) , +sky130_fd_sc_hd__conb_1 optlc_618 ( .LO ( optlc_net_617 ) , .HI ( SYNOPSYS_UNCONNECTED_619 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_621 ( .LO ( optlc_net_618 ) , +sky130_fd_sc_hd__conb_1 optlc_619 ( .LO ( optlc_net_618 ) , .HI ( SYNOPSYS_UNCONNECTED_620 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_622 ( .LO ( optlc_net_619 ) , +sky130_fd_sc_hd__conb_1 optlc_620 ( .LO ( optlc_net_619 ) , .HI ( SYNOPSYS_UNCONNECTED_621 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_623 ( .LO ( optlc_net_620 ) , +sky130_fd_sc_hd__conb_1 optlc_621 ( .LO ( optlc_net_620 ) , .HI ( SYNOPSYS_UNCONNECTED_622 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_624 ( .LO ( optlc_net_621 ) , +sky130_fd_sc_hd__conb_1 optlc_622 ( .LO ( optlc_net_621 ) , .HI ( SYNOPSYS_UNCONNECTED_623 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_625 ( .LO ( optlc_net_622 ) , +sky130_fd_sc_hd__conb_1 optlc_623 ( .LO ( optlc_net_622 ) , .HI ( SYNOPSYS_UNCONNECTED_624 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_626 ( .LO ( optlc_net_623 ) , +sky130_fd_sc_hd__conb_1 optlc_624 ( .LO ( optlc_net_623 ) , .HI ( SYNOPSYS_UNCONNECTED_625 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_627 ( .LO ( optlc_net_624 ) , +sky130_fd_sc_hd__conb_1 optlc_625 ( .LO ( optlc_net_624 ) , .HI ( SYNOPSYS_UNCONNECTED_626 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_628 ( .LO ( optlc_net_625 ) , +sky130_fd_sc_hd__conb_1 optlc_626 ( .LO ( optlc_net_625 ) , .HI ( SYNOPSYS_UNCONNECTED_627 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_629 ( .LO ( optlc_net_626 ) , +sky130_fd_sc_hd__conb_1 optlc_627 ( .LO ( optlc_net_626 ) , .HI ( SYNOPSYS_UNCONNECTED_628 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_630 ( .LO ( optlc_net_627 ) , +sky130_fd_sc_hd__conb_1 optlc_628 ( .LO ( optlc_net_627 ) , .HI ( SYNOPSYS_UNCONNECTED_629 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_631 ( .LO ( optlc_net_628 ) , +sky130_fd_sc_hd__conb_1 optlc_629 ( .LO ( optlc_net_628 ) , .HI ( SYNOPSYS_UNCONNECTED_630 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_632 ( .LO ( optlc_net_629 ) , +sky130_fd_sc_hd__conb_1 optlc_630 ( .LO ( optlc_net_629 ) , .HI ( SYNOPSYS_UNCONNECTED_631 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_633 ( .LO ( optlc_net_630 ) , +sky130_fd_sc_hd__conb_1 optlc_631 ( .LO ( optlc_net_630 ) , .HI ( SYNOPSYS_UNCONNECTED_632 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_634 ( .LO ( optlc_net_631 ) , +sky130_fd_sc_hd__conb_1 optlc_632 ( .LO ( optlc_net_631 ) , .HI ( SYNOPSYS_UNCONNECTED_633 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_635 ( .LO ( optlc_net_632 ) , +sky130_fd_sc_hd__conb_1 optlc_633 ( .LO ( optlc_net_632 ) , .HI ( SYNOPSYS_UNCONNECTED_634 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_636 ( .LO ( optlc_net_633 ) , +sky130_fd_sc_hd__conb_1 optlc_634 ( .LO ( optlc_net_633 ) , .HI ( SYNOPSYS_UNCONNECTED_635 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_637 ( .LO ( optlc_net_634 ) , +sky130_fd_sc_hd__conb_1 optlc_635 ( .LO ( optlc_net_634 ) , .HI ( SYNOPSYS_UNCONNECTED_636 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_638 ( .LO ( optlc_net_635 ) , +sky130_fd_sc_hd__conb_1 optlc_636 ( .LO ( optlc_net_635 ) , .HI ( SYNOPSYS_UNCONNECTED_637 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_639 ( .LO ( optlc_net_636 ) , +sky130_fd_sc_hd__conb_1 optlc_637 ( .LO ( optlc_net_636 ) , .HI ( SYNOPSYS_UNCONNECTED_638 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_640 ( .LO ( optlc_net_637 ) , +sky130_fd_sc_hd__conb_1 optlc_638 ( .LO ( optlc_net_637 ) , .HI ( SYNOPSYS_UNCONNECTED_639 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_641 ( .LO ( optlc_net_638 ) , +sky130_fd_sc_hd__conb_1 optlc_639 ( .LO ( optlc_net_638 ) , .HI ( SYNOPSYS_UNCONNECTED_640 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_642 ( .LO ( optlc_net_639 ) , +sky130_fd_sc_hd__conb_1 optlc_640 ( .LO ( optlc_net_639 ) , .HI ( SYNOPSYS_UNCONNECTED_641 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_643 ( .LO ( optlc_net_640 ) , +sky130_fd_sc_hd__conb_1 optlc_641 ( .LO ( optlc_net_640 ) , .HI ( SYNOPSYS_UNCONNECTED_642 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_644 ( .LO ( optlc_net_641 ) , +sky130_fd_sc_hd__conb_1 optlc_642 ( .LO ( optlc_net_641 ) , .HI ( SYNOPSYS_UNCONNECTED_643 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_645 ( .LO ( optlc_net_642 ) , +sky130_fd_sc_hd__conb_1 optlc_643 ( .LO ( optlc_net_642 ) , .HI ( SYNOPSYS_UNCONNECTED_644 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_646 ( .LO ( optlc_net_643 ) , +sky130_fd_sc_hd__conb_1 optlc_644 ( .LO ( optlc_net_643 ) , .HI ( SYNOPSYS_UNCONNECTED_645 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_647 ( .LO ( optlc_net_644 ) , +sky130_fd_sc_hd__conb_1 optlc_645 ( .LO ( optlc_net_644 ) , .HI ( SYNOPSYS_UNCONNECTED_646 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_648 ( .LO ( optlc_net_645 ) , +sky130_fd_sc_hd__conb_1 optlc_646 ( .LO ( optlc_net_645 ) , .HI ( SYNOPSYS_UNCONNECTED_647 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_649 ( .LO ( optlc_net_646 ) , +sky130_fd_sc_hd__conb_1 optlc_647 ( .LO ( optlc_net_646 ) , .HI ( SYNOPSYS_UNCONNECTED_648 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_650 ( .LO ( optlc_net_647 ) , +sky130_fd_sc_hd__conb_1 optlc_648 ( .LO ( optlc_net_647 ) , .HI ( SYNOPSYS_UNCONNECTED_649 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_651 ( .LO ( optlc_net_648 ) , +sky130_fd_sc_hd__conb_1 optlc_649 ( .LO ( optlc_net_648 ) , .HI ( SYNOPSYS_UNCONNECTED_650 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_652 ( .LO ( optlc_net_649 ) , +sky130_fd_sc_hd__conb_1 optlc_650 ( .LO ( optlc_net_649 ) , .HI ( SYNOPSYS_UNCONNECTED_651 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_653 ( .LO ( optlc_net_650 ) , +sky130_fd_sc_hd__conb_1 optlc_651 ( .LO ( optlc_net_650 ) , .HI ( SYNOPSYS_UNCONNECTED_652 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_654 ( .LO ( optlc_net_651 ) , +sky130_fd_sc_hd__conb_1 optlc_652 ( .LO ( optlc_net_651 ) , .HI ( SYNOPSYS_UNCONNECTED_653 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_655 ( .LO ( optlc_net_652 ) , +sky130_fd_sc_hd__conb_1 optlc_653 ( .LO ( optlc_net_652 ) , .HI ( SYNOPSYS_UNCONNECTED_654 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_656 ( .LO ( optlc_net_653 ) , +sky130_fd_sc_hd__conb_1 optlc_654 ( .LO ( optlc_net_653 ) , .HI ( SYNOPSYS_UNCONNECTED_655 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_657 ( .LO ( optlc_net_654 ) , +sky130_fd_sc_hd__conb_1 optlc_655 ( .LO ( optlc_net_654 ) , .HI ( SYNOPSYS_UNCONNECTED_656 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_658 ( .LO ( optlc_net_655 ) , +sky130_fd_sc_hd__conb_1 optlc_656 ( .LO ( optlc_net_655 ) , .HI ( SYNOPSYS_UNCONNECTED_657 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_659 ( .LO ( optlc_net_656 ) , +sky130_fd_sc_hd__conb_1 optlc_657 ( .LO ( optlc_net_656 ) , .HI ( SYNOPSYS_UNCONNECTED_658 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_660 ( .LO ( optlc_net_657 ) , +sky130_fd_sc_hd__conb_1 optlc_658 ( .LO ( optlc_net_657 ) , .HI ( SYNOPSYS_UNCONNECTED_659 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_661 ( .LO ( optlc_net_658 ) , +sky130_fd_sc_hd__conb_1 optlc_659 ( .LO ( optlc_net_658 ) , .HI ( SYNOPSYS_UNCONNECTED_660 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_662 ( .LO ( optlc_net_659 ) , +sky130_fd_sc_hd__conb_1 optlc_660 ( .LO ( optlc_net_659 ) , .HI ( SYNOPSYS_UNCONNECTED_661 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_663 ( .LO ( optlc_net_660 ) , +sky130_fd_sc_hd__conb_1 optlc_661 ( .LO ( optlc_net_660 ) , .HI ( SYNOPSYS_UNCONNECTED_662 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_664 ( .LO ( optlc_net_661 ) , +sky130_fd_sc_hd__conb_1 optlc_662 ( .LO ( optlc_net_661 ) , .HI ( SYNOPSYS_UNCONNECTED_663 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_665 ( .LO ( optlc_net_662 ) , +sky130_fd_sc_hd__conb_1 optlc_663 ( .LO ( optlc_net_662 ) , .HI ( SYNOPSYS_UNCONNECTED_664 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_666 ( .LO ( optlc_net_663 ) , +sky130_fd_sc_hd__conb_1 optlc_664 ( .LO ( optlc_net_663 ) , .HI ( SYNOPSYS_UNCONNECTED_665 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_667 ( .LO ( optlc_net_664 ) , +sky130_fd_sc_hd__conb_1 optlc_665 ( .LO ( optlc_net_664 ) , .HI ( SYNOPSYS_UNCONNECTED_666 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_668 ( .LO ( optlc_net_665 ) , +sky130_fd_sc_hd__conb_1 optlc_666 ( .LO ( optlc_net_665 ) , .HI ( SYNOPSYS_UNCONNECTED_667 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_669 ( .LO ( optlc_net_666 ) , +sky130_fd_sc_hd__conb_1 optlc_667 ( .LO ( optlc_net_666 ) , .HI ( SYNOPSYS_UNCONNECTED_668 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_670 ( .LO ( optlc_net_667 ) , +sky130_fd_sc_hd__conb_1 optlc_668 ( .LO ( optlc_net_667 ) , .HI ( SYNOPSYS_UNCONNECTED_669 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_671 ( .LO ( optlc_net_668 ) , +sky130_fd_sc_hd__conb_1 optlc_669 ( .LO ( optlc_net_668 ) , .HI ( SYNOPSYS_UNCONNECTED_670 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_672 ( .LO ( optlc_net_669 ) , +sky130_fd_sc_hd__conb_1 optlc_670 ( .LO ( optlc_net_669 ) , .HI ( SYNOPSYS_UNCONNECTED_671 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_673 ( .LO ( optlc_net_670 ) , +sky130_fd_sc_hd__conb_1 optlc_671 ( .LO ( optlc_net_670 ) , .HI ( SYNOPSYS_UNCONNECTED_672 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_674 ( .LO ( optlc_net_671 ) , +sky130_fd_sc_hd__conb_1 optlc_672 ( .LO ( optlc_net_671 ) , .HI ( SYNOPSYS_UNCONNECTED_673 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_675 ( .LO ( optlc_net_672 ) , +sky130_fd_sc_hd__conb_1 optlc_673 ( .LO ( optlc_net_672 ) , .HI ( SYNOPSYS_UNCONNECTED_674 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_676 ( .LO ( optlc_net_673 ) , +sky130_fd_sc_hd__conb_1 optlc_674 ( .LO ( optlc_net_673 ) , .HI ( SYNOPSYS_UNCONNECTED_675 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_677 ( .LO ( optlc_net_674 ) , +sky130_fd_sc_hd__conb_1 optlc_675 ( .LO ( optlc_net_674 ) , .HI ( SYNOPSYS_UNCONNECTED_676 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_678 ( .LO ( optlc_net_675 ) , +sky130_fd_sc_hd__conb_1 optlc_676 ( .LO ( optlc_net_675 ) , .HI ( SYNOPSYS_UNCONNECTED_677 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_679 ( .LO ( optlc_net_676 ) , +sky130_fd_sc_hd__conb_1 optlc_677 ( .LO ( optlc_net_676 ) , .HI ( SYNOPSYS_UNCONNECTED_678 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_680 ( .LO ( optlc_net_677 ) , +sky130_fd_sc_hd__conb_1 optlc_678 ( .LO ( optlc_net_677 ) , .HI ( SYNOPSYS_UNCONNECTED_679 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_681 ( .LO ( optlc_net_678 ) , +sky130_fd_sc_hd__conb_1 optlc_679 ( .LO ( optlc_net_678 ) , .HI ( SYNOPSYS_UNCONNECTED_680 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_682 ( .LO ( optlc_net_679 ) , +sky130_fd_sc_hd__conb_1 optlc_680 ( .LO ( optlc_net_679 ) , .HI ( SYNOPSYS_UNCONNECTED_681 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_683 ( .LO ( optlc_net_680 ) , +sky130_fd_sc_hd__conb_1 optlc_681 ( .LO ( optlc_net_680 ) , .HI ( SYNOPSYS_UNCONNECTED_682 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_684 ( .LO ( optlc_net_681 ) , +sky130_fd_sc_hd__conb_1 optlc_682 ( .LO ( optlc_net_681 ) , .HI ( SYNOPSYS_UNCONNECTED_683 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_685 ( .LO ( optlc_net_682 ) , +sky130_fd_sc_hd__conb_1 optlc_683 ( .LO ( optlc_net_682 ) , .HI ( SYNOPSYS_UNCONNECTED_684 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_686 ( .LO ( optlc_net_683 ) , +sky130_fd_sc_hd__conb_1 optlc_684 ( .LO ( optlc_net_683 ) , .HI ( SYNOPSYS_UNCONNECTED_685 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_687 ( .LO ( optlc_net_684 ) , +sky130_fd_sc_hd__conb_1 optlc_685 ( .LO ( optlc_net_684 ) , .HI ( SYNOPSYS_UNCONNECTED_686 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_688 ( .LO ( optlc_net_685 ) , +sky130_fd_sc_hd__conb_1 optlc_686 ( .LO ( optlc_net_685 ) , .HI ( SYNOPSYS_UNCONNECTED_687 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_689 ( .LO ( optlc_net_686 ) , +sky130_fd_sc_hd__conb_1 optlc_687 ( .LO ( optlc_net_686 ) , .HI ( SYNOPSYS_UNCONNECTED_688 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_690 ( .LO ( optlc_net_687 ) , +sky130_fd_sc_hd__conb_1 optlc_688 ( .LO ( optlc_net_687 ) , .HI ( SYNOPSYS_UNCONNECTED_689 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_691 ( .LO ( optlc_net_688 ) , +sky130_fd_sc_hd__conb_1 optlc_689 ( .LO ( optlc_net_688 ) , .HI ( SYNOPSYS_UNCONNECTED_690 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_692 ( .LO ( optlc_net_689 ) , +sky130_fd_sc_hd__conb_1 optlc_690 ( .LO ( optlc_net_689 ) , .HI ( SYNOPSYS_UNCONNECTED_691 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_693 ( .LO ( optlc_net_690 ) , +sky130_fd_sc_hd__conb_1 optlc_691 ( .LO ( optlc_net_690 ) , .HI ( SYNOPSYS_UNCONNECTED_692 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_694 ( .LO ( optlc_net_691 ) , +sky130_fd_sc_hd__conb_1 optlc_692 ( .LO ( optlc_net_691 ) , .HI ( SYNOPSYS_UNCONNECTED_693 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_695 ( .LO ( optlc_net_692 ) , +sky130_fd_sc_hd__conb_1 optlc_693 ( .LO ( optlc_net_692 ) , .HI ( SYNOPSYS_UNCONNECTED_694 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_696 ( .LO ( optlc_net_693 ) , +sky130_fd_sc_hd__conb_1 optlc_694 ( .LO ( optlc_net_693 ) , .HI ( SYNOPSYS_UNCONNECTED_695 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_697 ( .LO ( optlc_net_694 ) , +sky130_fd_sc_hd__conb_1 optlc_695 ( .LO ( optlc_net_694 ) , .HI ( SYNOPSYS_UNCONNECTED_696 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_698 ( .LO ( optlc_net_695 ) , +sky130_fd_sc_hd__conb_1 optlc_696 ( .LO ( optlc_net_695 ) , .HI ( SYNOPSYS_UNCONNECTED_697 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_699 ( .LO ( optlc_net_696 ) , +sky130_fd_sc_hd__conb_1 optlc_697 ( .LO ( optlc_net_696 ) , .HI ( SYNOPSYS_UNCONNECTED_698 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_700 ( .LO ( optlc_net_697 ) , +sky130_fd_sc_hd__conb_1 optlc_698 ( .LO ( optlc_net_697 ) , .HI ( SYNOPSYS_UNCONNECTED_699 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_701 ( .LO ( optlc_net_698 ) , +sky130_fd_sc_hd__conb_1 optlc_699 ( .LO ( optlc_net_698 ) , .HI ( SYNOPSYS_UNCONNECTED_700 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_702 ( .LO ( optlc_net_699 ) , +sky130_fd_sc_hd__conb_1 optlc_700 ( .LO ( optlc_net_699 ) , .HI ( SYNOPSYS_UNCONNECTED_701 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_703 ( .LO ( optlc_net_700 ) , +sky130_fd_sc_hd__conb_1 optlc_701 ( .LO ( optlc_net_700 ) , .HI ( SYNOPSYS_UNCONNECTED_702 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_704 ( .LO ( optlc_net_701 ) , +sky130_fd_sc_hd__conb_1 optlc_702 ( .LO ( optlc_net_701 ) , .HI ( SYNOPSYS_UNCONNECTED_703 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_705 ( .LO ( optlc_net_702 ) , +sky130_fd_sc_hd__conb_1 optlc_703 ( .LO ( optlc_net_702 ) , .HI ( SYNOPSYS_UNCONNECTED_704 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_706 ( .LO ( optlc_net_703 ) , +sky130_fd_sc_hd__conb_1 optlc_704 ( .LO ( optlc_net_703 ) , .HI ( SYNOPSYS_UNCONNECTED_705 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_708 ( .LO ( optlc_net_704 ) , +sky130_fd_sc_hd__conb_1 optlc_705 ( .LO ( optlc_net_704 ) , .HI ( SYNOPSYS_UNCONNECTED_706 ) ) ; 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optlc_net_811 ) , +sky130_fd_sc_hd__conb_1 optlc_812 ( .LO ( optlc_net_811 ) , .HI ( SYNOPSYS_UNCONNECTED_813 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_817 ( .LO ( optlc_net_812 ) , +sky130_fd_sc_hd__conb_1 optlc_813 ( .LO ( optlc_net_812 ) , .HI ( SYNOPSYS_UNCONNECTED_814 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_818 ( .LO ( optlc_net_813 ) , +sky130_fd_sc_hd__conb_1 optlc_814 ( .LO ( optlc_net_813 ) , .HI ( SYNOPSYS_UNCONNECTED_815 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_819 ( .LO ( optlc_net_814 ) , +sky130_fd_sc_hd__conb_1 optlc_815 ( .LO ( optlc_net_814 ) , .HI ( SYNOPSYS_UNCONNECTED_816 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_820 ( .LO ( optlc_net_815 ) , +sky130_fd_sc_hd__conb_1 optlc_816 ( .LO ( optlc_net_815 ) , .HI ( SYNOPSYS_UNCONNECTED_817 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_821 ( .LO ( optlc_net_816 ) , +sky130_fd_sc_hd__conb_1 optlc_817 ( .LO ( optlc_net_816 ) , .HI ( SYNOPSYS_UNCONNECTED_818 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_822 ( .LO ( optlc_net_817 ) , +sky130_fd_sc_hd__conb_1 optlc_818 ( .LO ( optlc_net_817 ) , .HI ( SYNOPSYS_UNCONNECTED_819 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_823 ( .LO ( optlc_net_818 ) , +sky130_fd_sc_hd__conb_1 optlc_819 ( .LO ( optlc_net_818 ) , .HI ( SYNOPSYS_UNCONNECTED_820 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_824 ( .LO ( optlc_net_819 ) , +sky130_fd_sc_hd__conb_1 optlc_820 ( .LO ( optlc_net_819 ) , .HI ( SYNOPSYS_UNCONNECTED_821 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_825 ( .LO ( optlc_net_820 ) , +sky130_fd_sc_hd__conb_1 optlc_821 ( .LO ( optlc_net_820 ) , .HI ( SYNOPSYS_UNCONNECTED_822 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_826 ( .LO ( optlc_net_821 ) , +sky130_fd_sc_hd__conb_1 optlc_822 ( .LO ( optlc_net_821 ) , .HI ( SYNOPSYS_UNCONNECTED_823 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_827 ( .LO ( optlc_net_822 ) , +sky130_fd_sc_hd__conb_1 optlc_823 ( .LO ( optlc_net_822 ) , .HI ( SYNOPSYS_UNCONNECTED_824 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_828 ( .LO ( optlc_net_823 ) , +sky130_fd_sc_hd__conb_1 optlc_824 ( .LO ( optlc_net_823 ) , .HI ( SYNOPSYS_UNCONNECTED_825 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_829 ( .LO ( optlc_net_824 ) , +sky130_fd_sc_hd__conb_1 optlc_825 ( .LO ( optlc_net_824 ) , .HI ( SYNOPSYS_UNCONNECTED_826 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_830 ( .LO ( optlc_net_825 ) , +sky130_fd_sc_hd__conb_1 optlc_826 ( .LO ( optlc_net_825 ) , .HI ( SYNOPSYS_UNCONNECTED_827 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_831 ( .LO ( optlc_net_826 ) , +sky130_fd_sc_hd__conb_1 optlc_827 ( .LO ( optlc_net_826 ) , .HI ( SYNOPSYS_UNCONNECTED_828 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_832 ( .LO ( optlc_net_827 ) , +sky130_fd_sc_hd__conb_1 optlc_828 ( .LO ( optlc_net_827 ) , .HI ( SYNOPSYS_UNCONNECTED_829 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_833 ( .LO ( optlc_net_828 ) , +sky130_fd_sc_hd__conb_1 optlc_829 ( .LO ( optlc_net_828 ) , .HI ( SYNOPSYS_UNCONNECTED_830 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_835 ( .LO ( optlc_net_829 ) , +sky130_fd_sc_hd__conb_1 optlc_830 ( .LO ( optlc_net_829 ) , .HI ( SYNOPSYS_UNCONNECTED_831 ) ) ; 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optlc_net_836 ) , +sky130_fd_sc_hd__conb_1 optlc_838 ( .LO ( optlc_net_836 ) , .HI ( SYNOPSYS_UNCONNECTED_838 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_843 ( .LO ( optlc_net_837 ) , +sky130_fd_sc_hd__conb_1 optlc_839 ( .LO ( optlc_net_837 ) , .HI ( SYNOPSYS_UNCONNECTED_839 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_844 ( .LO ( optlc_net_838 ) , +sky130_fd_sc_hd__conb_1 optlc_840 ( .LO ( optlc_net_838 ) , .HI ( SYNOPSYS_UNCONNECTED_840 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_845 ( .LO ( optlc_net_839 ) , +sky130_fd_sc_hd__conb_1 optlc_841 ( .LO ( optlc_net_839 ) , .HI ( SYNOPSYS_UNCONNECTED_841 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_846 ( .LO ( optlc_net_840 ) , +sky130_fd_sc_hd__conb_1 optlc_842 ( .LO ( optlc_net_840 ) , .HI ( SYNOPSYS_UNCONNECTED_842 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_847 ( .LO ( optlc_net_841 ) , +sky130_fd_sc_hd__conb_1 optlc_843 ( .LO ( optlc_net_841 ) , .HI ( SYNOPSYS_UNCONNECTED_843 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_848 ( .LO ( optlc_net_842 ) , +sky130_fd_sc_hd__conb_1 optlc_844 ( .LO ( optlc_net_842 ) , .HI ( SYNOPSYS_UNCONNECTED_844 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_849 ( .LO ( optlc_net_843 ) , +sky130_fd_sc_hd__conb_1 optlc_845 ( .LO ( optlc_net_843 ) , .HI ( SYNOPSYS_UNCONNECTED_845 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_850 ( .LO ( optlc_net_844 ) , +sky130_fd_sc_hd__conb_1 optlc_846 ( .LO ( optlc_net_844 ) , .HI ( SYNOPSYS_UNCONNECTED_846 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_851 ( .LO ( optlc_net_845 ) , +sky130_fd_sc_hd__conb_1 optlc_847 ( .LO ( optlc_net_845 ) , .HI ( SYNOPSYS_UNCONNECTED_847 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_852 ( .LO ( optlc_net_846 ) , +sky130_fd_sc_hd__conb_1 optlc_848 ( .LO ( optlc_net_846 ) , .HI ( SYNOPSYS_UNCONNECTED_848 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_853 ( .LO ( optlc_net_847 ) , +sky130_fd_sc_hd__conb_1 optlc_849 ( .LO ( optlc_net_847 ) , .HI ( SYNOPSYS_UNCONNECTED_849 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_854 ( .LO ( optlc_net_848 ) , +sky130_fd_sc_hd__conb_1 optlc_850 ( .LO ( optlc_net_848 ) , .HI ( SYNOPSYS_UNCONNECTED_850 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_856 ( .LO ( optlc_net_849 ) , +sky130_fd_sc_hd__conb_1 optlc_851 ( .LO ( optlc_net_849 ) , .HI ( SYNOPSYS_UNCONNECTED_851 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_857 ( .LO ( optlc_net_850 ) , +sky130_fd_sc_hd__conb_1 optlc_852 ( .LO ( optlc_net_850 ) , .HI ( SYNOPSYS_UNCONNECTED_852 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_858 ( .LO ( optlc_net_851 ) , +sky130_fd_sc_hd__conb_1 optlc_853 ( .LO ( optlc_net_851 ) , .HI ( SYNOPSYS_UNCONNECTED_853 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_859 ( .LO ( optlc_net_852 ) , +sky130_fd_sc_hd__conb_1 optlc_854 ( .LO ( optlc_net_852 ) , .HI ( SYNOPSYS_UNCONNECTED_854 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_860 ( .LO ( optlc_net_853 ) , +sky130_fd_sc_hd__conb_1 optlc_855 ( .LO ( optlc_net_853 ) , .HI ( SYNOPSYS_UNCONNECTED_855 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_861 ( .LO ( optlc_net_854 ) , +sky130_fd_sc_hd__conb_1 optlc_856 ( .LO ( optlc_net_854 ) , .HI ( SYNOPSYS_UNCONNECTED_856 ) ) ; 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optlc_net_861 ) , +sky130_fd_sc_hd__conb_1 optlc_863 ( .LO ( optlc_net_861 ) , .HI ( SYNOPSYS_UNCONNECTED_863 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_870 ( .LO ( optlc_net_862 ) , +sky130_fd_sc_hd__conb_1 optlc_864 ( .LO ( optlc_net_862 ) , .HI ( SYNOPSYS_UNCONNECTED_864 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_871 ( .LO ( optlc_net_863 ) , +sky130_fd_sc_hd__conb_1 optlc_865 ( .LO ( optlc_net_863 ) , .HI ( SYNOPSYS_UNCONNECTED_865 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_872 ( .LO ( optlc_net_864 ) , +sky130_fd_sc_hd__conb_1 optlc_866 ( .LO ( optlc_net_864 ) , .HI ( SYNOPSYS_UNCONNECTED_866 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_873 ( .LO ( optlc_net_865 ) , +sky130_fd_sc_hd__conb_1 optlc_867 ( .LO ( optlc_net_865 ) , .HI ( SYNOPSYS_UNCONNECTED_867 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_874 ( .LO ( optlc_net_866 ) , +sky130_fd_sc_hd__conb_1 optlc_868 ( .LO ( optlc_net_866 ) , .HI ( SYNOPSYS_UNCONNECTED_868 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_875 ( .LO ( optlc_net_867 ) , +sky130_fd_sc_hd__conb_1 optlc_869 ( .LO ( optlc_net_867 ) , .HI ( SYNOPSYS_UNCONNECTED_869 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_876 ( .LO ( optlc_net_868 ) , +sky130_fd_sc_hd__conb_1 optlc_870 ( .LO ( optlc_net_868 ) , .HI ( SYNOPSYS_UNCONNECTED_870 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_877 ( .LO ( optlc_net_869 ) , +sky130_fd_sc_hd__conb_1 optlc_871 ( .LO ( optlc_net_869 ) , .HI ( SYNOPSYS_UNCONNECTED_871 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_878 ( .LO ( optlc_net_870 ) , +sky130_fd_sc_hd__conb_1 optlc_872 ( .LO ( optlc_net_870 ) , .HI ( SYNOPSYS_UNCONNECTED_872 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_879 ( .LO ( optlc_net_871 ) , +sky130_fd_sc_hd__conb_1 optlc_873 ( .LO ( optlc_net_871 ) , .HI ( SYNOPSYS_UNCONNECTED_873 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_880 ( .LO ( optlc_net_872 ) , +sky130_fd_sc_hd__conb_1 optlc_874 ( .LO ( optlc_net_872 ) , .HI ( SYNOPSYS_UNCONNECTED_874 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_881 ( .LO ( optlc_net_873 ) , +sky130_fd_sc_hd__conb_1 optlc_875 ( .LO ( optlc_net_873 ) , .HI ( SYNOPSYS_UNCONNECTED_875 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_882 ( .LO ( optlc_net_874 ) , +sky130_fd_sc_hd__conb_1 optlc_876 ( .LO ( optlc_net_874 ) , .HI ( SYNOPSYS_UNCONNECTED_876 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_883 ( .LO ( optlc_net_875 ) , +sky130_fd_sc_hd__conb_1 optlc_877 ( .LO ( optlc_net_875 ) , .HI ( SYNOPSYS_UNCONNECTED_877 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_884 ( .LO ( optlc_net_876 ) , +sky130_fd_sc_hd__conb_1 optlc_878 ( .LO ( optlc_net_876 ) , .HI ( SYNOPSYS_UNCONNECTED_878 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_885 ( .LO ( optlc_net_877 ) , +sky130_fd_sc_hd__conb_1 optlc_879 ( .LO ( optlc_net_877 ) , .HI ( SYNOPSYS_UNCONNECTED_879 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_886 ( .LO ( optlc_net_878 ) , +sky130_fd_sc_hd__conb_1 optlc_880 ( .LO ( optlc_net_878 ) , .HI ( SYNOPSYS_UNCONNECTED_880 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_887 ( .LO ( optlc_net_879 ) , +sky130_fd_sc_hd__conb_1 optlc_881 ( .LO ( optlc_net_879 ) , .HI ( SYNOPSYS_UNCONNECTED_881 ) ) ; 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+sky130_fd_sc_hd__conb_1 optlc_3875 ( .LO ( optlc_net_3524 ) , .HI ( SYNOPSYS_UNCONNECTED_3526 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_3985 ( .LO ( optlc_net_3525 ) , +sky130_fd_sc_hd__conb_1 optlc_3876 ( .LO ( optlc_net_3525 ) , .HI ( SYNOPSYS_UNCONNECTED_3527 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_3986 ( .LO ( optlc_net_3526 ) , +sky130_fd_sc_hd__conb_1 optlc_3877 ( .LO ( optlc_net_3526 ) , .HI ( SYNOPSYS_UNCONNECTED_3528 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_3987 ( .LO ( optlc_net_3527 ) , +sky130_fd_sc_hd__conb_1 optlc_3878 ( .LO ( optlc_net_3527 ) , .HI ( SYNOPSYS_UNCONNECTED_3529 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_3988 ( .LO ( optlc_net_3528 ) , +sky130_fd_sc_hd__conb_1 optlc_3879 ( .LO ( optlc_net_3528 ) , .HI ( SYNOPSYS_UNCONNECTED_3530 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_3989 ( .LO ( optlc_net_3529 ) , +sky130_fd_sc_hd__conb_1 optlc_3880 ( .LO ( optlc_net_3529 ) , .HI ( SYNOPSYS_UNCONNECTED_3531 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3881 ( .LO ( optlc_net_3530 ) , + .HI ( SYNOPSYS_UNCONNECTED_3532 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3882 ( .LO ( optlc_net_3531 ) , + .HI ( SYNOPSYS_UNCONNECTED_3533 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3883 ( .LO ( optlc_net_3532 ) , + .HI ( SYNOPSYS_UNCONNECTED_3534 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3884 ( .LO ( optlc_net_3533 ) , + .HI ( SYNOPSYS_UNCONNECTED_3535 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3885 ( .LO ( optlc_net_3534 ) , + .HI ( SYNOPSYS_UNCONNECTED_3536 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3886 ( .LO ( optlc_net_3535 ) , + .HI ( SYNOPSYS_UNCONNECTED_3537 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3887 ( .LO ( optlc_net_3536 ) , + .HI ( SYNOPSYS_UNCONNECTED_3538 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3888 ( .LO ( optlc_net_3537 ) , + .HI ( SYNOPSYS_UNCONNECTED_3539 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3889 ( .LO ( optlc_net_3538 ) , + .HI ( SYNOPSYS_UNCONNECTED_3540 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3890 ( .LO ( optlc_net_3539 ) , + .HI ( SYNOPSYS_UNCONNECTED_3541 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3891 ( .LO ( optlc_net_3540 ) , + .HI ( SYNOPSYS_UNCONNECTED_3542 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3892 ( .LO ( optlc_net_3541 ) , + .HI ( SYNOPSYS_UNCONNECTED_3543 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3893 ( .LO ( optlc_net_3542 ) , + .HI ( SYNOPSYS_UNCONNECTED_3544 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3894 ( .LO ( optlc_net_3543 ) , + .HI ( SYNOPSYS_UNCONNECTED_3545 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3895 ( .LO ( optlc_net_3544 ) , + .HI ( SYNOPSYS_UNCONNECTED_3546 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3896 ( .LO ( optlc_net_3545 ) , + .HI ( SYNOPSYS_UNCONNECTED_3547 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3897 ( .LO ( optlc_net_3546 ) , + .HI ( SYNOPSYS_UNCONNECTED_3548 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3898 ( .LO ( optlc_net_3547 ) , + .HI ( SYNOPSYS_UNCONNECTED_3549 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3899 ( .LO ( optlc_net_3548 ) , + .HI ( SYNOPSYS_UNCONNECTED_3550 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3900 ( .LO ( optlc_net_3549 ) , + .HI ( SYNOPSYS_UNCONNECTED_3551 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3901 ( .LO ( optlc_net_3550 ) , + .HI ( SYNOPSYS_UNCONNECTED_3552 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3902 ( .LO ( optlc_net_3551 ) , + .HI ( SYNOPSYS_UNCONNECTED_3553 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3903 ( .LO ( optlc_net_3552 ) , + .HI ( SYNOPSYS_UNCONNECTED_3554 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3904 ( .LO ( optlc_net_3553 ) , + .HI ( SYNOPSYS_UNCONNECTED_3555 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3905 ( .LO ( optlc_net_3554 ) , + .HI ( SYNOPSYS_UNCONNECTED_3556 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3906 ( .LO ( optlc_net_3555 ) , + .HI ( SYNOPSYS_UNCONNECTED_3557 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3907 ( .LO ( optlc_net_3556 ) , + .HI ( SYNOPSYS_UNCONNECTED_3558 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3908 ( .LO ( optlc_net_3557 ) , + .HI ( SYNOPSYS_UNCONNECTED_3559 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3909 ( .LO ( optlc_net_3558 ) , + .HI ( SYNOPSYS_UNCONNECTED_3560 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3910 ( .LO ( optlc_net_3559 ) , + .HI ( SYNOPSYS_UNCONNECTED_3561 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3911 ( .LO ( optlc_net_3560 ) , + .HI ( SYNOPSYS_UNCONNECTED_3562 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3912 ( .LO ( optlc_net_3561 ) , + .HI ( SYNOPSYS_UNCONNECTED_3563 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3913 ( .LO ( optlc_net_3562 ) , + .HI ( SYNOPSYS_UNCONNECTED_3564 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3914 ( .LO ( optlc_net_3563 ) , + .HI ( SYNOPSYS_UNCONNECTED_3565 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3915 ( .LO ( optlc_net_3564 ) , + .HI ( SYNOPSYS_UNCONNECTED_3566 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3916 ( .LO ( optlc_net_3565 ) , + .HI ( SYNOPSYS_UNCONNECTED_3567 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3917 ( .LO ( optlc_net_3566 ) , + .HI ( SYNOPSYS_UNCONNECTED_3568 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3918 ( .LO ( optlc_net_3567 ) , + .HI ( SYNOPSYS_UNCONNECTED_3569 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3919 ( .LO ( optlc_net_3568 ) , + .HI ( SYNOPSYS_UNCONNECTED_3570 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3920 ( .LO ( optlc_net_3569 ) , + .HI ( SYNOPSYS_UNCONNECTED_3571 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3921 ( .LO ( optlc_net_3570 ) , + .HI ( SYNOPSYS_UNCONNECTED_3572 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3922 ( .LO ( optlc_net_3571 ) , + .HI ( SYNOPSYS_UNCONNECTED_3573 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3923 ( .LO ( optlc_net_3572 ) , + .HI ( SYNOPSYS_UNCONNECTED_3574 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3924 ( .LO ( optlc_net_3573 ) , + .HI ( SYNOPSYS_UNCONNECTED_3575 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3925 ( .LO ( optlc_net_3574 ) , + .HI ( SYNOPSYS_UNCONNECTED_3576 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3926 ( .LO ( optlc_net_3575 ) , + .HI ( SYNOPSYS_UNCONNECTED_3577 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3927 ( .LO ( optlc_net_3576 ) , + .HI ( SYNOPSYS_UNCONNECTED_3578 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3928 ( .LO ( optlc_net_3577 ) , + .HI ( SYNOPSYS_UNCONNECTED_3579 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3929 ( .LO ( optlc_net_3578 ) , + .HI ( SYNOPSYS_UNCONNECTED_3580 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3930 ( .LO ( optlc_net_3579 ) , + .HI ( SYNOPSYS_UNCONNECTED_3581 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3931 ( .LO ( optlc_net_3580 ) , + .HI ( SYNOPSYS_UNCONNECTED_3582 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3932 ( .LO ( optlc_net_3581 ) , + .HI ( SYNOPSYS_UNCONNECTED_3583 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3933 ( .LO ( optlc_net_3582 ) , + .HI ( SYNOPSYS_UNCONNECTED_3584 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3934 ( .LO ( optlc_net_3583 ) , + .HI ( SYNOPSYS_UNCONNECTED_3585 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3935 ( .LO ( optlc_net_3584 ) , + .HI ( SYNOPSYS_UNCONNECTED_3586 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3936 ( .LO ( optlc_net_3585 ) , + .HI ( SYNOPSYS_UNCONNECTED_3587 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3937 ( .LO ( optlc_net_3586 ) , + .HI ( SYNOPSYS_UNCONNECTED_3588 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3938 ( .LO ( optlc_net_3587 ) , + .HI ( SYNOPSYS_UNCONNECTED_3589 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3939 ( .LO ( optlc_net_3588 ) , + .HI ( SYNOPSYS_UNCONNECTED_3590 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3940 ( .LO ( optlc_net_3589 ) , + .HI ( SYNOPSYS_UNCONNECTED_3591 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3941 ( .LO ( optlc_net_3590 ) , + .HI ( SYNOPSYS_UNCONNECTED_3592 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3942 ( .LO ( optlc_net_3591 ) , + .HI ( SYNOPSYS_UNCONNECTED_3593 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3943 ( .LO ( optlc_net_3592 ) , + .HI ( SYNOPSYS_UNCONNECTED_3594 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3944 ( .LO ( optlc_net_3593 ) , + .HI ( SYNOPSYS_UNCONNECTED_3595 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3945 ( .LO ( optlc_net_3594 ) , + .HI ( SYNOPSYS_UNCONNECTED_3596 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3946 ( .LO ( optlc_net_3595 ) , + .HI ( SYNOPSYS_UNCONNECTED_3597 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3947 ( .LO ( optlc_net_3596 ) , + .HI ( SYNOPSYS_UNCONNECTED_3598 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3948 ( .LO ( optlc_net_3597 ) , + .HI ( SYNOPSYS_UNCONNECTED_3599 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3949 ( .LO ( optlc_net_3598 ) , + .HI ( SYNOPSYS_UNCONNECTED_3600 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3950 ( .LO ( optlc_net_3599 ) , + .HI ( SYNOPSYS_UNCONNECTED_3601 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3951 ( .LO ( optlc_net_3600 ) , + .HI ( SYNOPSYS_UNCONNECTED_3602 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3952 ( .LO ( optlc_net_3601 ) , + .HI ( SYNOPSYS_UNCONNECTED_3603 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3953 ( .LO ( optlc_net_3602 ) , + .HI ( SYNOPSYS_UNCONNECTED_3604 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3954 ( .LO ( optlc_net_3603 ) , + .HI ( SYNOPSYS_UNCONNECTED_3605 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3955 ( .LO ( optlc_net_3604 ) , + .HI ( SYNOPSYS_UNCONNECTED_3606 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3956 ( .LO ( optlc_net_3605 ) , + .HI ( SYNOPSYS_UNCONNECTED_3607 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3957 ( .LO ( optlc_net_3606 ) , + .HI ( SYNOPSYS_UNCONNECTED_3608 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3958 ( .LO ( optlc_net_3607 ) , + .HI ( SYNOPSYS_UNCONNECTED_3609 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3959 ( .LO ( optlc_net_3608 ) , + .HI ( SYNOPSYS_UNCONNECTED_3610 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3960 ( .LO ( optlc_net_3609 ) , + .HI ( SYNOPSYS_UNCONNECTED_3611 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3961 ( .LO ( optlc_net_3610 ) , + .HI ( SYNOPSYS_UNCONNECTED_3612 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3962 ( .LO ( optlc_net_3611 ) , + .HI ( SYNOPSYS_UNCONNECTED_3613 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3963 ( .LO ( optlc_net_3612 ) , + .HI ( SYNOPSYS_UNCONNECTED_3614 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3964 ( .LO ( optlc_net_3613 ) , + .HI ( SYNOPSYS_UNCONNECTED_3615 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3965 ( .LO ( optlc_net_3614 ) , + .HI ( SYNOPSYS_UNCONNECTED_3616 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3966 ( .LO ( optlc_net_3615 ) , + .HI ( SYNOPSYS_UNCONNECTED_3617 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3967 ( .LO ( optlc_net_3616 ) , + .HI ( SYNOPSYS_UNCONNECTED_3618 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3968 ( .LO ( optlc_net_3617 ) , + .HI ( SYNOPSYS_UNCONNECTED_3619 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3969 ( .LO ( optlc_net_3618 ) , + .HI ( SYNOPSYS_UNCONNECTED_3620 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3970 ( .LO ( optlc_net_3619 ) , + .HI ( SYNOPSYS_UNCONNECTED_3621 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3971 ( .LO ( optlc_net_3620 ) , + .HI ( SYNOPSYS_UNCONNECTED_3622 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3972 ( .LO ( optlc_net_3621 ) , + .HI ( SYNOPSYS_UNCONNECTED_3623 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3973 ( .LO ( optlc_net_3622 ) , + .HI ( SYNOPSYS_UNCONNECTED_3624 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3974 ( .LO ( optlc_net_3623 ) , + .HI ( SYNOPSYS_UNCONNECTED_3625 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3975 ( .LO ( optlc_net_3624 ) , + .HI ( SYNOPSYS_UNCONNECTED_3626 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3976 ( .LO ( optlc_net_3625 ) , + .HI ( SYNOPSYS_UNCONNECTED_3627 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3977 ( .LO ( optlc_net_3626 ) , + .HI ( SYNOPSYS_UNCONNECTED_3628 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3978 ( .LO ( optlc_net_3627 ) , + .HI ( SYNOPSYS_UNCONNECTED_3629 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3979 ( .LO ( optlc_net_3628 ) , + .HI ( SYNOPSYS_UNCONNECTED_3630 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3980 ( .LO ( optlc_net_3629 ) , + .HI ( SYNOPSYS_UNCONNECTED_3631 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3981 ( .LO ( optlc_net_3630 ) , + .HI ( SYNOPSYS_UNCONNECTED_3632 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3982 ( .LO ( optlc_net_3631 ) , + .HI ( SYNOPSYS_UNCONNECTED_3633 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3983 ( .LO ( optlc_net_3632 ) , + .HI ( SYNOPSYS_UNCONNECTED_3634 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3984 ( .LO ( optlc_net_3633 ) , + .HI ( SYNOPSYS_UNCONNECTED_3635 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3985 ( .LO ( optlc_net_3634 ) , + .HI ( SYNOPSYS_UNCONNECTED_3636 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3986 ( .LO ( optlc_net_3635 ) , + .HI ( SYNOPSYS_UNCONNECTED_3637 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3987 ( .LO ( optlc_net_3636 ) , + .HI ( SYNOPSYS_UNCONNECTED_3638 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3988 ( .LO ( optlc_net_3637 ) , + .HI ( SYNOPSYS_UNCONNECTED_3639 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3989 ( .LO ( optlc_net_3638 ) , + .HI ( SYNOPSYS_UNCONNECTED_3640 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3990 ( .LO ( optlc_net_3639 ) , + .HI ( SYNOPSYS_UNCONNECTED_3641 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3991 ( .LO ( optlc_net_3640 ) , + .HI ( SYNOPSYS_UNCONNECTED_3642 ) ) ; endmodule diff --git a/FPGA1212_SOFA_CHD_PNR/fpga_top/fpga_top_icv_in_design.gds.gz b/FPGA1212_SOFA_CHD_PNR/fpga_top/fpga_top_icv_in_design.gds.gz index a9053e9..02f4600 100644 Binary files a/FPGA1212_SOFA_CHD_PNR/fpga_top/fpga_top_icv_in_design.gds.gz and b/FPGA1212_SOFA_CHD_PNR/fpga_top/fpga_top_icv_in_design.gds.gz differ diff --git a/FPGA1212_SOFA_CHD_PNR/fpga_top/fpga_top_icv_in_design.lvs.v b/FPGA1212_SOFA_CHD_PNR/fpga_top/fpga_top_icv_in_design.lvs.v index 45cfbb8..b4cf798 100644 --- a/FPGA1212_SOFA_CHD_PNR/fpga_top/fpga_top_icv_in_design.lvs.v +++ b/FPGA1212_SOFA_CHD_PNR/fpga_top/fpga_top_icv_in_design.lvs.v @@ -14,21 +14,14 @@ output [0:0] mem_out ; input VDD ; input VSS ; -wire copt_net_114 ; supply1 VDD ; supply0 VSS ; +assign ccff_tail[0] = mem_out[0] ; + sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( copt_net_114 ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_6 FTB_18__17 ( .A ( copt_net_116 ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1354 ( .A ( copt_net_114 ) , - .X ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1355 ( .A ( mem_out[0] ) , - .X ( copt_net_115 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1356 ( .A ( copt_net_115 ) , - .X ( copt_net_116 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -48,18 +41,13 @@ supply1 VDD ; supply0 VSS ; sky130_fd_sc_hd__or2b_4 ISOL_EN_GATE ( .A ( FPGA_DIR ) , .B_N ( IO_ISOL_N ) , - .X ( aps_rename_510_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 INV_SOC_DIR ( .A ( aps_rename_510_ ) , - .Y ( SOC_DIR_N ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .X ( SOC_DIR ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 INV_SOC_DIR ( .A ( SOC_DIR ) , .Y ( SOC_DIR_N ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__ebufn_4 IN_PROTECT_GATE ( .A ( SOC_IN ) , .TE_B ( SOC_DIR_N ) , .Z ( FPGA_IN ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__ebufn_4 OUT_PROTECT_GATE ( .A ( FPGA_OUT ) , - .TE_B ( aps_rename_510_ ) , .Z ( SOC_OUT ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_81 ( .A ( aps_rename_510_ ) , - .Y ( BUF_net_81 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_6 BINV_R_80 ( .A ( BUF_net_81 ) , .Y ( SOC_DIR ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .TE_B ( SOC_DIR ) , .Z ( SOC_OUT ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -142,6 +130,8 @@ input VSS ; supply1 VDD ; supply0 VSS ; +assign ccff_tail[0] = mem_out[3] ; + sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -154,8 +144,6 @@ sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_1 FTB_17__16 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -172,6 +160,8 @@ input VSS ; supply1 VDD ; supply0 VSS ; +assign ccff_tail[0] = mem_out[3] ; + sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -184,8 +174,6 @@ sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_1 FTB_16__15 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -202,6 +190,8 @@ input VSS ; supply1 VDD ; supply0 VSS ; +assign ccff_tail[0] = mem_out[3] ; + sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -214,8 +204,6 @@ sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_1 FTB_15__14 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -232,6 +220,8 @@ input VSS ; supply1 VDD ; supply0 VSS ; +assign ccff_tail[0] = mem_out[3] ; + sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -244,8 +234,6 @@ sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_1 FTB_14__13 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -262,6 +250,8 @@ input VSS ; supply1 VDD ; supply0 VSS ; +assign ccff_tail[0] = mem_out[3] ; + sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -274,8 +264,6 @@ sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_1 FTB_13__12 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -292,6 +280,8 @@ input VSS ; supply1 VDD ; supply0 VSS ; +assign ccff_tail[0] = mem_out[3] ; + sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -304,8 +294,6 @@ sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_1 FTB_12__11 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -322,6 +310,8 @@ input VSS ; supply1 VDD ; supply0 VSS ; +assign ccff_tail[0] = mem_out[3] ; + sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -334,8 +324,6 @@ sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_1 FTB_11__10 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -352,6 +340,8 @@ input VSS ; supply1 VDD ; supply0 VSS ; +assign ccff_tail[0] = mem_out[3] ; + sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -364,8 +354,6 @@ sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_1 FTB_10__9 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -378,34 +366,41 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module cby_2__1__mux_2level_basis_input4_mem4 ( in , mem , mem_inv , out , - VDD , VSS , p0 ) ; + VDD , VSS ) ; input [0:3] in ; input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; input VDD ; input VSS ; -input p0 ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( p0 ) , + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -418,15 +413,22 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( ZINV_1377_17 ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__clkinv_1 ZINV_1377_inst_1023 ( .A ( in[2] ) , + .Y ( ZINV_1377_17 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -439,15 +441,20 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -473,7 +480,7 @@ sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , .Y ( data_inv[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) , .VPWR ( VDD ) , +sky130_fd_sc_hd__clkinv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -504,7 +511,7 @@ sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , .Y ( data_inv[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) , .VPWR ( VDD ) , +sky130_fd_sc_hd__clkinv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -513,16 +520,15 @@ sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , endmodule -module cby_2__1__mux_2level_size10 ( in , sram , sram_inv , out , VDD , VSS , - p0 ) ; +module cby_2__1__mux_2level_size10 ( in , sram , sram_inv , out , VDD , VSS ) ; input [0:9] in ; input [0:3] sram ; input [0:3] sram_inv ; output [0:0] out ; input VDD ; input VSS ; -input p0 ; +wire [0:0] const1_0_const1 ; wire [0:3] local_encoder2to4_0_data ; wire [0:3] local_encoder2to4_0_data_inv ; wire [0:3] local_encoder2to4_1_data ; @@ -535,7 +541,7 @@ supply1 VDD ; supply0 VSS ; sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_1_0_ ( - .A ( mux_2level_basis_input4_mem4_2_out[0] ) , .X ( net_net_95 ) , + .A ( mux_2level_basis_input4_mem4_2_out[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; cby_2__1__local_encoder2to4_32 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , .data ( local_encoder2to4_0_data ) , @@ -556,18 +562,16 @@ cby_2__1__mux_2level_basis_input4_mem4_58 mux_l1_in_1_ ( .in ( in[4:7] ) , cby_2__1__mux_2level_basis_input4_mem4 mux_l2_in_0_ ( .in ( { mux_2level_basis_input4_mem4_0_out[0] , mux_2level_basis_input4_mem4_1_out[0] , - mux_2level_basis_input2_mem2_0_out[0] , SYNOPSYS_UNCONNECTED_1 } ) , + mux_2level_basis_input2_mem2_0_out[0] , const1_0_const1[0] } ) , .mem ( local_encoder2to4_1_data ) , .mem_inv ( local_encoder2to4_1_data_inv ) , .out ( mux_2level_basis_input4_mem4_2_out ) , .VDD ( VDD ) , - .VSS ( VSS ) , .p0 ( p0 ) ) ; + .VSS ( VSS ) ) ; cby_2__1__mux_2level_basis_input2_mem2 mux_l1_in_2_ ( .in ( in[8:9] ) , .mem ( local_encoder2to4_0_data[0:1] ) , .mem_inv ( local_encoder2to4_0_data_inv[0:1] ) , .out ( mux_2level_basis_input2_mem2_0_out ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_95 ( .A ( net_net_95 ) , .X ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -580,34 +584,41 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module cby_2__1__mux_2level_basis_input4_mem4_56 ( in , mem , mem_inv , out , - VDD , VSS , p0 ) ; + VDD , VSS ) ; input [0:3] in ; input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; input VDD ; input VSS ; -input p0 ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( p0 ) , + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -620,15 +631,22 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( ZINV_4_16 ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__clkinv_1 ZINV_4_inst_1004 ( .A ( in[3] ) , .Y ( ZINV_4_16 ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -641,15 +659,20 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -675,7 +698,7 @@ sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , .Y ( data_inv[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) , .VPWR ( VDD ) , +sky130_fd_sc_hd__clkinv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -706,7 +729,7 @@ sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , .Y ( data_inv[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) , .VPWR ( VDD ) , +sky130_fd_sc_hd__clkinv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -716,15 +739,15 @@ endmodule module cby_2__1__mux_2level_size10_6 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; + VSS ) ; input [0:9] in ; input [0:3] sram ; input [0:3] sram_inv ; output [0:0] out ; input VDD ; input VSS ; -input p0 ; +wire [0:0] const1_0_const1 ; wire [0:3] local_encoder2to4_0_data ; wire [0:3] local_encoder2to4_0_data_inv ; wire [0:3] local_encoder2to4_1_data ; @@ -737,7 +760,7 @@ supply1 VDD ; supply0 VSS ; sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_1_0_ ( - .A ( mux_2level_basis_input4_mem4_2_out[0] ) , .X ( net_net_94 ) , + .A ( mux_2level_basis_input4_mem4_2_out[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; cby_2__1__local_encoder2to4_30 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , .data ( local_encoder2to4_0_data ) , @@ -758,18 +781,16 @@ cby_2__1__mux_2level_basis_input4_mem4_55 mux_l1_in_1_ ( .in ( in[4:7] ) , cby_2__1__mux_2level_basis_input4_mem4_56 mux_l2_in_0_ ( .in ( { mux_2level_basis_input4_mem4_0_out[0] , mux_2level_basis_input4_mem4_1_out[0] , - mux_2level_basis_input2_mem2_0_out[0] , SYNOPSYS_UNCONNECTED_1 } ) , + mux_2level_basis_input2_mem2_0_out[0] , const1_0_const1[0] } ) , .mem ( local_encoder2to4_1_data ) , .mem_inv ( local_encoder2to4_1_data_inv ) , .out ( mux_2level_basis_input4_mem4_2_out ) , .VDD ( VDD ) , - .VSS ( VSS ) , .p0 ( p0 ) ) ; + .VSS ( VSS ) ) ; cby_2__1__mux_2level_basis_input2_mem2_6 mux_l1_in_2_ ( .in ( in[8:9] ) , .mem ( local_encoder2to4_0_data[0:1] ) , .mem_inv ( local_encoder2to4_0_data_inv[0:1] ) , .out ( mux_2level_basis_input2_mem2_0_out ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_94 ( .A ( net_net_94 ) , .X ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -782,34 +803,41 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module cby_2__1__mux_2level_basis_input4_mem4_53 ( in , mem , mem_inv , out , - VDD , VSS , p0 ) ; + VDD , VSS ) ; input [0:3] in ; input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; input VDD ; input VSS ; -input p0 ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( p0 ) , + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -822,15 +850,22 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( ZINV_24_11 ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__clkinv_1 ZINV_24_inst_961 ( .A ( in[2] ) , + .Y ( ZINV_24_11 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -843,15 +878,22 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; -scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , +scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( ZINV_17_3 ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__clkinv_1 ZINV_17_inst_910 ( .A ( in[0] ) , .Y ( ZINV_17_3 ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -877,7 +919,7 @@ sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , .Y ( data_inv[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) , .VPWR ( VDD ) , +sky130_fd_sc_hd__clkinv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -908,7 +950,7 @@ sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , .Y ( data_inv[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) , .VPWR ( VDD ) , +sky130_fd_sc_hd__clkinv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -918,15 +960,15 @@ endmodule module cby_2__1__mux_2level_size10_5 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; + VSS ) ; input [0:9] in ; input [0:3] sram ; input [0:3] sram_inv ; output [0:0] out ; input VDD ; input VSS ; -input p0 ; +wire [0:0] const1_0_const1 ; wire [0:3] local_encoder2to4_0_data ; wire [0:3] local_encoder2to4_0_data_inv ; wire [0:3] local_encoder2to4_1_data ; @@ -939,7 +981,7 @@ supply1 VDD ; supply0 VSS ; sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_1_0_ ( - .A ( mux_2level_basis_input4_mem4_2_out[0] ) , .X ( aps_rename_509_ ) , + .A ( mux_2level_basis_input4_mem4_2_out[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; cby_2__1__local_encoder2to4_28 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , .data ( local_encoder2to4_0_data ) , @@ -960,20 +1002,16 @@ cby_2__1__mux_2level_basis_input4_mem4_52 mux_l1_in_1_ ( .in ( in[4:7] ) , cby_2__1__mux_2level_basis_input4_mem4_53 mux_l2_in_0_ ( .in ( { mux_2level_basis_input4_mem4_0_out[0] , mux_2level_basis_input4_mem4_1_out[0] , - mux_2level_basis_input2_mem2_0_out[0] , SYNOPSYS_UNCONNECTED_1 } ) , + mux_2level_basis_input2_mem2_0_out[0] , const1_0_const1[0] } ) , .mem ( local_encoder2to4_1_data ) , .mem_inv ( local_encoder2to4_1_data_inv ) , .out ( mux_2level_basis_input4_mem4_2_out ) , .VDD ( VDD ) , - .VSS ( VSS ) , .p0 ( p0 ) ) ; + .VSS ( VSS ) ) ; cby_2__1__mux_2level_basis_input2_mem2_5 mux_l1_in_2_ ( .in ( in[8:9] ) , .mem ( local_encoder2to4_0_data[0:1] ) , .mem_inv ( local_encoder2to4_0_data_inv[0:1] ) , .out ( mux_2level_basis_input2_mem2_0_out ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_92 ( .A ( BUF_net_93 ) , .Y ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_93 ( .A ( aps_rename_509_ ) , - .Y ( BUF_net_93 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -986,34 +1024,41 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module cby_2__1__mux_2level_basis_input4_mem4_50 ( in , mem , mem_inv , out , - VDD , VSS , p0 ) ; + VDD , VSS ) ; input [0:3] in ; input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; input VDD ; input VSS ; -input p0 ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( p0 ) , + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -1026,15 +1071,20 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -1047,15 +1097,24 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; -scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , +scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( ZINV_10_0 ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( ZINV_10_1 ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__clkinv_1 ZINV_10_inst_883 ( .A ( in[1] ) , .Y ( ZINV_10_0 ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__clkinv_1 ZINV_10_inst_895 ( .A ( in[3] ) , .Y ( ZINV_10_1 ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -1081,7 +1140,7 @@ sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , .Y ( data_inv[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) , .VPWR ( VDD ) , +sky130_fd_sc_hd__clkinv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -1112,7 +1171,7 @@ sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , .Y ( data_inv[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) , .VPWR ( VDD ) , +sky130_fd_sc_hd__clkinv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -1122,15 +1181,15 @@ endmodule module cby_2__1__mux_2level_size10_4 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; + VSS ) ; input [0:9] in ; input [0:3] sram ; input [0:3] sram_inv ; output [0:0] out ; input VDD ; input VSS ; -input p0 ; +wire [0:0] const1_0_const1 ; wire [0:3] local_encoder2to4_0_data ; wire [0:3] local_encoder2to4_0_data_inv ; wire [0:3] local_encoder2to4_1_data ; @@ -1142,7 +1201,7 @@ wire [0:0] mux_2level_basis_input4_mem4_2_out ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__bufbuf_16 sky130_fd_sc_hd__buf_1_0_ ( +sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_1_0_ ( .A ( mux_2level_basis_input4_mem4_2_out[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; cby_2__1__local_encoder2to4_26 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , @@ -1164,11 +1223,11 @@ cby_2__1__mux_2level_basis_input4_mem4_49 mux_l1_in_1_ ( .in ( in[4:7] ) , cby_2__1__mux_2level_basis_input4_mem4_50 mux_l2_in_0_ ( .in ( { mux_2level_basis_input4_mem4_0_out[0] , mux_2level_basis_input4_mem4_1_out[0] , - mux_2level_basis_input2_mem2_0_out[0] , SYNOPSYS_UNCONNECTED_1 } ) , + mux_2level_basis_input2_mem2_0_out[0] , const1_0_const1[0] } ) , .mem ( local_encoder2to4_1_data ) , .mem_inv ( local_encoder2to4_1_data_inv ) , .out ( mux_2level_basis_input4_mem4_2_out ) , .VDD ( VDD ) , - .VSS ( VSS ) , .p0 ( p0 ) ) ; + .VSS ( VSS ) ) ; cby_2__1__mux_2level_basis_input2_mem2_4 mux_l1_in_2_ ( .in ( in[8:9] ) , .mem ( local_encoder2to4_0_data[0:1] ) , .mem_inv ( local_encoder2to4_0_data_inv[0:1] ) , @@ -1186,34 +1245,43 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; -scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , +scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( ZINV_7_5 ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__clkinv_1 ZINV_7_inst_932 ( .A ( in[1] ) , .Y ( ZINV_7_5 ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module cby_2__1__mux_2level_basis_input4_mem4_47 ( in , mem , mem_inv , out , - VDD , VSS , p0 ) ; + VDD , VSS ) ; input [0:3] in ; input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; input VDD ; input VSS ; -input p0 ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( p0 ) , + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -1226,15 +1294,22 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( ZINV_4_9 ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__clkinv_1 ZINV_4_inst_949 ( .A ( in[3] ) , .Y ( ZINV_4_9 ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -1247,15 +1322,22 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; -scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , +scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( ZINV_10_2 ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__clkinv_1 ZINV_10_inst_904 ( .A ( in[1] ) , .Y ( ZINV_10_2 ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -1281,7 +1363,7 @@ sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , .Y ( data_inv[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) , .VPWR ( VDD ) , +sky130_fd_sc_hd__clkinv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -1312,7 +1394,7 @@ sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , .Y ( data_inv[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) , .VPWR ( VDD ) , +sky130_fd_sc_hd__clkinv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -1322,15 +1404,15 @@ endmodule module cby_2__1__mux_2level_size10_3 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; + VSS ) ; input [0:9] in ; input [0:3] sram ; input [0:3] sram_inv ; output [0:0] out ; input VDD ; input VSS ; -input p0 ; +wire [0:0] const1_0_const1 ; wire [0:3] local_encoder2to4_0_data ; wire [0:3] local_encoder2to4_0_data_inv ; wire [0:3] local_encoder2to4_1_data ; @@ -1342,7 +1424,7 @@ wire [0:0] mux_2level_basis_input4_mem4_2_out ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__bufbuf_16 sky130_fd_sc_hd__buf_1_0_ ( +sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_1_0_ ( .A ( mux_2level_basis_input4_mem4_2_out[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; cby_2__1__local_encoder2to4_24 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , @@ -1364,11 +1446,11 @@ cby_2__1__mux_2level_basis_input4_mem4_46 mux_l1_in_1_ ( .in ( in[4:7] ) , cby_2__1__mux_2level_basis_input4_mem4_47 mux_l2_in_0_ ( .in ( { mux_2level_basis_input4_mem4_0_out[0] , mux_2level_basis_input4_mem4_1_out[0] , - mux_2level_basis_input2_mem2_0_out[0] , SYNOPSYS_UNCONNECTED_1 } ) , + mux_2level_basis_input2_mem2_0_out[0] , const1_0_const1[0] } ) , .mem ( local_encoder2to4_1_data ) , .mem_inv ( local_encoder2to4_1_data_inv ) , .out ( mux_2level_basis_input4_mem4_2_out ) , .VDD ( VDD ) , - .VSS ( VSS ) , .p0 ( p0 ) ) ; + .VSS ( VSS ) ) ; cby_2__1__mux_2level_basis_input2_mem2_3 mux_l1_in_2_ ( .in ( in[8:9] ) , .mem ( local_encoder2to4_0_data[0:1] ) , .mem_inv ( local_encoder2to4_0_data_inv[0:1] ) , @@ -1386,34 +1468,43 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; -scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , +scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( ZINV_368_3 ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__clkinv_1 ZINV_368_inst_912 ( .A ( in[1] ) , + .Y ( ZINV_368_3 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module cby_2__1__mux_2level_basis_input4_mem4_44 ( in , mem , mem_inv , out , - VDD , VSS , p0 ) ; + VDD , VSS ) ; input [0:3] in ; input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; input VDD ; input VSS ; -input p0 ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( p0 ) , + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -1426,15 +1517,25 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , - .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( ZINV_200_17 ) , + .Q2 ( ZINV_4_10 ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , + .S0 ( mem[2] ) , .S1 ( mem[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__clkinv_1 ZINV_4_inst_952 ( .A ( in[3] ) , .Y ( ZINV_4_10 ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__clkinv_1 ZINV_200_inst_1016 ( .A ( in[2] ) , + .Y ( ZINV_200_17 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -1447,15 +1548,20 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -1481,7 +1587,7 @@ sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , .Y ( data_inv[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) , .VPWR ( VDD ) , +sky130_fd_sc_hd__clkinv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -1512,7 +1618,7 @@ sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , .Y ( data_inv[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) , .VPWR ( VDD ) , +sky130_fd_sc_hd__clkinv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -1522,15 +1628,15 @@ endmodule module cby_2__1__mux_2level_size10_2 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; + VSS ) ; input [0:9] in ; input [0:3] sram ; input [0:3] sram_inv ; output [0:0] out ; input VDD ; input VSS ; -input p0 ; +wire [0:0] const1_0_const1 ; wire [0:3] local_encoder2to4_0_data ; wire [0:3] local_encoder2to4_0_data_inv ; wire [0:3] local_encoder2to4_1_data ; @@ -1542,7 +1648,7 @@ wire [0:0] mux_2level_basis_input4_mem4_2_out ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__bufbuf_16 sky130_fd_sc_hd__buf_1_0_ ( +sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_1_0_ ( .A ( mux_2level_basis_input4_mem4_2_out[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; cby_2__1__local_encoder2to4_22 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , @@ -1564,11 +1670,11 @@ cby_2__1__mux_2level_basis_input4_mem4_43 mux_l1_in_1_ ( .in ( in[4:7] ) , cby_2__1__mux_2level_basis_input4_mem4_44 mux_l2_in_0_ ( .in ( { mux_2level_basis_input4_mem4_0_out[0] , mux_2level_basis_input4_mem4_1_out[0] , - mux_2level_basis_input2_mem2_0_out[0] , SYNOPSYS_UNCONNECTED_1 } ) , + mux_2level_basis_input2_mem2_0_out[0] , const1_0_const1[0] } ) , .mem ( local_encoder2to4_1_data ) , .mem_inv ( local_encoder2to4_1_data_inv ) , .out ( mux_2level_basis_input4_mem4_2_out ) , .VDD ( VDD ) , - .VSS ( VSS ) , .p0 ( p0 ) ) ; + .VSS ( VSS ) ) ; cby_2__1__mux_2level_basis_input2_mem2_2 mux_l1_in_2_ ( .in ( in[8:9] ) , .mem ( local_encoder2to4_0_data[0:1] ) , .mem_inv ( local_encoder2to4_0_data_inv[0:1] ) , @@ -1586,34 +1692,41 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module cby_2__1__mux_2level_basis_input4_mem4_41 ( in , mem , mem_inv , out , - VDD , VSS , p0 ) ; + VDD , VSS ) ; input [0:3] in ; input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; input VDD ; input VSS ; -input p0 ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( p0 ) , + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -1626,15 +1739,20 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -1647,15 +1765,24 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; -scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , +scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( ZINV_4_0 ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( ZINV_14_0 ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__clkinv_1 ZINV_4_inst_878 ( .A ( in[0] ) , .Y ( ZINV_4_0 ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__clkinv_1 ZINV_14_inst_886 ( .A ( in[2] ) , .Y ( ZINV_14_0 ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -1681,7 +1808,7 @@ sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , .Y ( data_inv[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) , .VPWR ( VDD ) , +sky130_fd_sc_hd__clkinv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -1712,7 +1839,7 @@ sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , .Y ( data_inv[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) , .VPWR ( VDD ) , +sky130_fd_sc_hd__clkinv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -1722,15 +1849,15 @@ endmodule module cby_2__1__mux_2level_size10_1 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; + VSS ) ; input [0:9] in ; input [0:3] sram ; input [0:3] sram_inv ; output [0:0] out ; input VDD ; input VSS ; -input p0 ; +wire [0:0] const1_0_const1 ; wire [0:3] local_encoder2to4_0_data ; wire [0:3] local_encoder2to4_0_data_inv ; wire [0:3] local_encoder2to4_1_data ; @@ -1742,7 +1869,7 @@ wire [0:0] mux_2level_basis_input4_mem4_2_out ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__bufbuf_16 sky130_fd_sc_hd__buf_1_0_ ( +sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_1_0_ ( .A ( mux_2level_basis_input4_mem4_2_out[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; cby_2__1__local_encoder2to4_20 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , @@ -1764,11 +1891,11 @@ cby_2__1__mux_2level_basis_input4_mem4_40 mux_l1_in_1_ ( .in ( in[4:7] ) , cby_2__1__mux_2level_basis_input4_mem4_41 mux_l2_in_0_ ( .in ( { mux_2level_basis_input4_mem4_0_out[0] , mux_2level_basis_input4_mem4_1_out[0] , - mux_2level_basis_input2_mem2_0_out[0] , SYNOPSYS_UNCONNECTED_1 } ) , + mux_2level_basis_input2_mem2_0_out[0] , const1_0_const1[0] } ) , .mem ( local_encoder2to4_1_data ) , .mem_inv ( local_encoder2to4_1_data_inv ) , .out ( mux_2level_basis_input4_mem4_2_out ) , .VDD ( VDD ) , - .VSS ( VSS ) , .p0 ( p0 ) ) ; + .VSS ( VSS ) ) ; cby_2__1__mux_2level_basis_input2_mem2_1 mux_l1_in_2_ ( .in ( in[8:9] ) , .mem ( local_encoder2to4_0_data[0:1] ) , .mem_inv ( local_encoder2to4_0_data_inv[0:1] ) , @@ -1786,34 +1913,46 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; -scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , - .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( ZINV_4_14 ) , + .Q2 ( ZINV_810_17 ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , + .S0 ( mem[0] ) , .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__clkinv_1 ZINV_4_inst_978 ( .A ( in[0] ) , .Y ( ZINV_4_14 ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__clkinv_1 ZINV_810_inst_1034 ( .A ( in[1] ) , + .Y ( ZINV_810_17 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module cby_2__1__mux_2level_basis_input4_mem4_38 ( in , mem , mem_inv , out , - VDD , VSS , p0 ) ; + VDD , VSS ) ; input [0:3] in ; input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; input VDD ; input VSS ; -input p0 ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( p0 ) , + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -1826,15 +1965,22 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; -scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , +scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( ZINV_4_15 ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__clkinv_1 ZINV_4_inst_994 ( .A ( in[0] ) , .Y ( ZINV_4_15 ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -1847,15 +1993,20 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -1881,7 +2032,7 @@ sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , .Y ( data_inv[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) , .VPWR ( VDD ) , +sky130_fd_sc_hd__clkinv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -1912,7 +2063,7 @@ sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , .Y ( data_inv[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) , .VPWR ( VDD ) , +sky130_fd_sc_hd__clkinv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -1922,15 +2073,15 @@ endmodule module cby_2__1__mux_2level_size10_0 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; + VSS ) ; input [0:9] in ; input [0:3] sram ; input [0:3] sram_inv ; output [0:0] out ; input VDD ; input VSS ; -input p0 ; +wire [0:0] const1_0_const1 ; wire [0:3] local_encoder2to4_0_data ; wire [0:3] local_encoder2to4_0_data_inv ; wire [0:3] local_encoder2to4_1_data ; @@ -1942,7 +2093,7 @@ wire [0:0] mux_2level_basis_input4_mem4_2_out ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__bufbuf_16 sky130_fd_sc_hd__buf_1_0_ ( +sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_1_0_ ( .A ( mux_2level_basis_input4_mem4_2_out[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; cby_2__1__local_encoder2to4_18 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , @@ -1964,11 +2115,11 @@ cby_2__1__mux_2level_basis_input4_mem4_37 mux_l1_in_1_ ( .in ( in[4:7] ) , cby_2__1__mux_2level_basis_input4_mem4_38 mux_l2_in_0_ ( .in ( { mux_2level_basis_input4_mem4_0_out[0] , mux_2level_basis_input4_mem4_1_out[0] , - mux_2level_basis_input2_mem2_0_out[0] , SYNOPSYS_UNCONNECTED_1 } ) , + mux_2level_basis_input2_mem2_0_out[0] , const1_0_const1[0] } ) , .mem ( local_encoder2to4_1_data ) , .mem_inv ( local_encoder2to4_1_data_inv ) , .out ( mux_2level_basis_input4_mem4_2_out ) , .VDD ( VDD ) , - .VSS ( VSS ) , .p0 ( p0 ) ) ; + .VSS ( VSS ) ) ; cby_2__1__mux_2level_basis_input2_mem2_0 mux_l1_in_2_ ( .in ( in[8:9] ) , .mem ( local_encoder2to4_0_data[0:1] ) , .mem_inv ( local_encoder2to4_0_data_inv[0:1] ) , @@ -1990,6 +2141,8 @@ input VSS ; supply1 VDD ; supply0 VSS ; +assign ccff_tail[0] = mem_out[3] ; + sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -2002,8 +2155,6 @@ sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_1 FTB_9__8 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -2020,6 +2171,8 @@ input VSS ; supply1 VDD ; supply0 VSS ; +assign ccff_tail[0] = mem_out[3] ; + sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -2032,8 +2185,6 @@ sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_1 FTB_8__7 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -2050,6 +2201,8 @@ input VSS ; supply1 VDD ; supply0 VSS ; +assign ccff_tail[0] = mem_out[3] ; + sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -2062,8 +2215,6 @@ sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_1 FTB_7__6 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -2080,6 +2231,8 @@ input VSS ; supply1 VDD ; supply0 VSS ; +assign ccff_tail[0] = mem_out[3] ; + sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -2092,8 +2245,6 @@ sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_1 FTB_6__5 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -2110,6 +2261,8 @@ input VSS ; supply1 VDD ; supply0 VSS ; +assign ccff_tail[0] = mem_out[3] ; + sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -2122,8 +2275,6 @@ sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_1 FTB_5__4 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -2140,6 +2291,8 @@ input VSS ; supply1 VDD ; supply0 VSS ; +assign ccff_tail[0] = mem_out[3] ; + sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -2152,8 +2305,6 @@ sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_1 FTB_4__3 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -2170,6 +2321,8 @@ input VSS ; supply1 VDD ; supply0 VSS ; +assign ccff_tail[0] = mem_out[3] ; + sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -2182,8 +2335,6 @@ sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_1 FTB_3__2 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -2200,6 +2351,8 @@ input VSS ; supply1 VDD ; supply0 VSS ; +assign ccff_tail[0] = mem_out[3] ; + sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -2212,8 +2365,6 @@ sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_1 FTB_2__1 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -2230,7 +2381,9 @@ input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( copt_net_106 ) , +assign ccff_tail[0] = mem_out[3] ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ropt_net_6 ) , .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , @@ -2242,50 +2395,36 @@ sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_1 FTB_1__0 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1346 ( .A ( copt_net_117 ) , - .X ( copt_net_106 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1347 ( .A ( ccff_head[0] ) , - .X ( copt_net_107 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1348 ( .A ( copt_net_107 ) , - .X ( copt_net_108 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1349 ( .A ( ropt_net_121 ) , - .X ( copt_net_109 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1350 ( .A ( copt_net_108 ) , - .X ( copt_net_110 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 copt_h_inst_1357 ( .A ( ropt_net_119 ) , - .X ( copt_net_117 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1358 ( .A ( copt_net_109 ) , - .X ( ropt_net_118 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_2 ropt_h_inst_1359 ( .A ( ropt_net_118 ) , - .X ( ropt_net_119 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1360 ( .A ( copt_net_110 ) , - .X ( ropt_net_120 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1361 ( .A ( ropt_net_120 ) , - .X ( ropt_net_121 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1044 ( .A ( ccff_head[0] ) , + .X ( ropt_net_5 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__clkbuf_2 ropt_h_inst_1045 ( .A ( ropt_net_5 ) , + .X ( ropt_net_6 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module cby_2__1__mux_2level_basis_input4_mem4_35 ( in , mem , mem_inv , out , - VDD , VSS , p0 ) ; + VDD , VSS ) ; input [0:3] in ; input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; input VDD ; input VSS ; -input p0 ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( p0 ) , + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -2298,15 +2437,20 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -2319,15 +2463,22 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( ZINV_11_12 ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__clkinv_1 ZINV_11_inst_968 ( .A ( in[2] ) , + .Y ( ZINV_11_12 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -2340,15 +2491,20 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -2374,7 +2530,7 @@ sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , .Y ( data_inv[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) , .VPWR ( VDD ) , +sky130_fd_sc_hd__clkinv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -2405,7 +2561,7 @@ sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , .Y ( data_inv[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) , .VPWR ( VDD ) , +sky130_fd_sc_hd__clkinv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -2414,16 +2570,15 @@ sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , endmodule -module cby_2__1__mux_2level_size12 ( in , sram , sram_inv , out , VDD , VSS , - p0 ) ; +module cby_2__1__mux_2level_size12 ( in , sram , sram_inv , out , VDD , VSS ) ; input [0:11] in ; input [0:3] sram ; input [0:3] sram_inv ; output [0:0] out ; input VDD ; input VSS ; -input p0 ; +wire [0:0] const1_0_const1 ; wire [0:3] local_encoder2to4_0_data ; wire [0:3] local_encoder2to4_0_data_inv ; wire [0:3] local_encoder2to4_1_data ; @@ -2436,7 +2591,7 @@ supply1 VDD ; supply0 VSS ; sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_1_0_ ( - .A ( mux_2level_basis_input4_mem4_3_out[0] ) , .X ( aps_rename_508_ ) , + .A ( mux_2level_basis_input4_mem4_3_out[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; cby_2__1__local_encoder2to4_16 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , .data ( local_encoder2to4_0_data ) , @@ -2462,37 +2617,37 @@ cby_2__1__mux_2level_basis_input4_mem4_34 mux_l1_in_2_ ( .in ( in[8:11] ) , cby_2__1__mux_2level_basis_input4_mem4_35 mux_l2_in_0_ ( .in ( { mux_2level_basis_input4_mem4_0_out[0] , mux_2level_basis_input4_mem4_1_out[0] , - mux_2level_basis_input4_mem4_2_out[0] , SYNOPSYS_UNCONNECTED_1 } ) , + mux_2level_basis_input4_mem4_2_out[0] , const1_0_const1[0] } ) , .mem ( local_encoder2to4_1_data ) , .mem_inv ( local_encoder2to4_1_data_inv ) , .out ( mux_2level_basis_input4_mem4_3_out ) , .VDD ( VDD ) , - .VSS ( VSS ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_90 ( .A ( BUF_net_91 ) , .Y ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_91 ( .A ( aps_rename_508_ ) , - .Y ( BUF_net_91 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .VSS ( VSS ) ) ; endmodule module cby_2__1__mux_2level_basis_input4_mem4_31 ( in , mem , mem_inv , out , - VDD , VSS , p0 ) ; + VDD , VSS ) ; input [0:3] in ; input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; input VDD ; input VSS ; -input p0 ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( p0 ) , + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -2505,15 +2660,20 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -2526,15 +2686,24 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; -scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , +scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( ZINV_7_4 ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( ZINV_7_6 ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__clkinv_1 ZINV_7_inst_922 ( .A ( in[0] ) , .Y ( ZINV_7_4 ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__clkinv_1 ZINV_7_inst_935 ( .A ( in[2] ) , .Y ( ZINV_7_6 ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -2547,15 +2716,20 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -2581,7 +2755,7 @@ sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , .Y ( data_inv[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) , .VPWR ( VDD ) , +sky130_fd_sc_hd__clkinv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -2612,7 +2786,7 @@ sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , .Y ( data_inv[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) , .VPWR ( VDD ) , +sky130_fd_sc_hd__clkinv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -2622,15 +2796,15 @@ endmodule module cby_2__1__mux_2level_size12_7 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; + VSS ) ; input [0:11] in ; input [0:3] sram ; input [0:3] sram_inv ; output [0:0] out ; input VDD ; input VSS ; -input p0 ; +wire [0:0] const1_0_const1 ; wire [0:3] local_encoder2to4_0_data ; wire [0:3] local_encoder2to4_0_data_inv ; wire [0:3] local_encoder2to4_1_data ; @@ -2642,7 +2816,7 @@ wire [0:0] mux_2level_basis_input4_mem4_3_out ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__bufbuf_16 sky130_fd_sc_hd__buf_1_0_ ( +sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_1_0_ ( .A ( mux_2level_basis_input4_mem4_3_out[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; cby_2__1__local_encoder2to4_14 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , @@ -2669,33 +2843,37 @@ cby_2__1__mux_2level_basis_input4_mem4_30 mux_l1_in_2_ ( .in ( in[8:11] ) , cby_2__1__mux_2level_basis_input4_mem4_31 mux_l2_in_0_ ( .in ( { mux_2level_basis_input4_mem4_0_out[0] , mux_2level_basis_input4_mem4_1_out[0] , - mux_2level_basis_input4_mem4_2_out[0] , SYNOPSYS_UNCONNECTED_1 } ) , + mux_2level_basis_input4_mem4_2_out[0] , const1_0_const1[0] } ) , .mem ( local_encoder2to4_1_data ) , .mem_inv ( local_encoder2to4_1_data_inv ) , .out ( mux_2level_basis_input4_mem4_3_out ) , .VDD ( VDD ) , - .VSS ( VSS ) , .p0 ( p0 ) ) ; + .VSS ( VSS ) ) ; endmodule module cby_2__1__mux_2level_basis_input4_mem4_27 ( in , mem , mem_inv , out , - VDD , VSS , p0 ) ; + VDD , VSS ) ; input [0:3] in ; input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; input VDD ; input VSS ; -input p0 ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( p0 ) , + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -2708,15 +2886,22 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; -scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , +scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( ZINV_7_3 ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__clkinv_1 ZINV_7_inst_919 ( .A ( in[0] ) , .Y ( ZINV_7_3 ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -2729,15 +2914,22 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; -scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , +scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( ZINV_4_3 ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__clkinv_1 ZINV_4_inst_916 ( .A ( in[0] ) , .Y ( ZINV_4_3 ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -2750,15 +2942,22 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; -scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , +scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( ZINV_10_3 ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__clkinv_1 ZINV_10_inst_907 ( .A ( in[0] ) , .Y ( ZINV_10_3 ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -2784,7 +2983,7 @@ sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , .Y ( data_inv[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) , .VPWR ( VDD ) , +sky130_fd_sc_hd__clkinv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -2815,7 +3014,7 @@ sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , .Y ( data_inv[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) , .VPWR ( VDD ) , +sky130_fd_sc_hd__clkinv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -2825,15 +3024,15 @@ endmodule module cby_2__1__mux_2level_size12_6 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; + VSS ) ; input [0:11] in ; input [0:3] sram ; input [0:3] sram_inv ; output [0:0] out ; input VDD ; input VSS ; -input p0 ; +wire [0:0] const1_0_const1 ; wire [0:3] local_encoder2to4_0_data ; wire [0:3] local_encoder2to4_0_data_inv ; wire [0:3] local_encoder2to4_1_data ; @@ -2846,7 +3045,7 @@ supply1 VDD ; supply0 VSS ; sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_1_0_ ( - .A ( mux_2level_basis_input4_mem4_3_out[0] ) , .X ( aps_rename_507_ ) , + .A ( mux_2level_basis_input4_mem4_3_out[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; cby_2__1__local_encoder2to4_12 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , .data ( local_encoder2to4_0_data ) , @@ -2872,37 +3071,37 @@ cby_2__1__mux_2level_basis_input4_mem4_26 mux_l1_in_2_ ( .in ( in[8:11] ) , cby_2__1__mux_2level_basis_input4_mem4_27 mux_l2_in_0_ ( .in ( { mux_2level_basis_input4_mem4_0_out[0] , mux_2level_basis_input4_mem4_1_out[0] , - mux_2level_basis_input4_mem4_2_out[0] , SYNOPSYS_UNCONNECTED_1 } ) , + mux_2level_basis_input4_mem4_2_out[0] , const1_0_const1[0] } ) , .mem ( local_encoder2to4_1_data ) , .mem_inv ( local_encoder2to4_1_data_inv ) , .out ( mux_2level_basis_input4_mem4_3_out ) , .VDD ( VDD ) , - .VSS ( VSS ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_6 BINV_R_88 ( .A ( BUF_net_89 ) , .Y ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_89 ( .A ( aps_rename_507_ ) , - .Y ( BUF_net_89 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .VSS ( VSS ) ) ; endmodule module cby_2__1__mux_2level_basis_input4_mem4_23 ( in , mem , mem_inv , out , - VDD , VSS , p0 ) ; + VDD , VSS ) ; input [0:3] in ; input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; input VDD ; input VSS ; -input p0 ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( p0 ) , + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -2915,15 +3114,20 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -2936,15 +3140,20 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -2957,15 +3166,20 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -2991,7 +3205,7 @@ sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , .Y ( data_inv[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) , .VPWR ( VDD ) , +sky130_fd_sc_hd__clkinv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -3022,7 +3236,7 @@ sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , .Y ( data_inv[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) , .VPWR ( VDD ) , +sky130_fd_sc_hd__clkinv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -3032,15 +3246,15 @@ endmodule module cby_2__1__mux_2level_size12_5 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; + VSS ) ; input [0:11] in ; input [0:3] sram ; input [0:3] sram_inv ; output [0:0] out ; input VDD ; input VSS ; -input p0 ; +wire [0:0] const1_0_const1 ; wire [0:3] local_encoder2to4_0_data ; wire [0:3] local_encoder2to4_0_data_inv ; wire [0:3] local_encoder2to4_1_data ; @@ -3053,7 +3267,7 @@ supply1 VDD ; supply0 VSS ; sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_1_0_ ( - .A ( mux_2level_basis_input4_mem4_3_out[0] ) , .X ( aps_rename_506_ ) , + .A ( mux_2level_basis_input4_mem4_3_out[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; cby_2__1__local_encoder2to4_10 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , .data ( local_encoder2to4_0_data ) , @@ -3079,37 +3293,37 @@ cby_2__1__mux_2level_basis_input4_mem4_22 mux_l1_in_2_ ( .in ( in[8:11] ) , cby_2__1__mux_2level_basis_input4_mem4_23 mux_l2_in_0_ ( .in ( { mux_2level_basis_input4_mem4_0_out[0] , mux_2level_basis_input4_mem4_1_out[0] , - mux_2level_basis_input4_mem4_2_out[0] , SYNOPSYS_UNCONNECTED_1 } ) , + mux_2level_basis_input4_mem4_2_out[0] , const1_0_const1[0] } ) , .mem ( local_encoder2to4_1_data ) , .mem_inv ( local_encoder2to4_1_data_inv ) , .out ( mux_2level_basis_input4_mem4_3_out ) , .VDD ( VDD ) , - .VSS ( VSS ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_86 ( .A ( BUF_net_87 ) , .Y ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_87 ( .A ( aps_rename_506_ ) , - .Y ( BUF_net_87 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .VSS ( VSS ) ) ; endmodule module cby_2__1__mux_2level_basis_input4_mem4_19 ( in , mem , mem_inv , out , - VDD , VSS , p0 ) ; + VDD , VSS ) ; input [0:3] in ; input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; input VDD ; input VSS ; -input p0 ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( p0 ) , + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -3122,15 +3336,20 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -3143,15 +3362,20 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -3164,15 +3388,20 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -3198,7 +3427,7 @@ sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , .Y ( data_inv[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) , .VPWR ( VDD ) , +sky130_fd_sc_hd__clkinv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -3229,7 +3458,7 @@ sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , .Y ( data_inv[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) , .VPWR ( VDD ) , +sky130_fd_sc_hd__clkinv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -3239,15 +3468,15 @@ endmodule module cby_2__1__mux_2level_size12_4 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; + VSS ) ; input [0:11] in ; input [0:3] sram ; input [0:3] sram_inv ; output [0:0] out ; input VDD ; input VSS ; -input p0 ; +wire [0:0] const1_0_const1 ; wire [0:3] local_encoder2to4_0_data ; wire [0:3] local_encoder2to4_0_data_inv ; wire [0:3] local_encoder2to4_1_data ; @@ -3260,7 +3489,7 @@ supply1 VDD ; supply0 VSS ; sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_1_0_ ( - .A ( mux_2level_basis_input4_mem4_3_out[0] ) , .X ( aps_rename_505_ ) , + .A ( mux_2level_basis_input4_mem4_3_out[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; cby_2__1__local_encoder2to4_8 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , .data ( local_encoder2to4_0_data ) , @@ -3286,37 +3515,37 @@ cby_2__1__mux_2level_basis_input4_mem4_18 mux_l1_in_2_ ( .in ( in[8:11] ) , cby_2__1__mux_2level_basis_input4_mem4_19 mux_l2_in_0_ ( .in ( { mux_2level_basis_input4_mem4_0_out[0] , mux_2level_basis_input4_mem4_1_out[0] , - mux_2level_basis_input4_mem4_2_out[0] , SYNOPSYS_UNCONNECTED_1 } ) , + mux_2level_basis_input4_mem4_2_out[0] , const1_0_const1[0] } ) , .mem ( local_encoder2to4_1_data ) , .mem_inv ( local_encoder2to4_1_data_inv ) , .out ( mux_2level_basis_input4_mem4_3_out ) , .VDD ( VDD ) , - .VSS ( VSS ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_84 ( .A ( BUF_net_85 ) , .Y ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_85 ( .A ( aps_rename_505_ ) , - .Y ( BUF_net_85 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .VSS ( VSS ) ) ; endmodule module cby_2__1__mux_2level_basis_input4_mem4_15 ( in , mem , mem_inv , out , - VDD , VSS , p0 ) ; + VDD , VSS ) ; input [0:3] in ; input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; input VDD ; input VSS ; -input p0 ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( p0 ) , + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -3329,15 +3558,20 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -3350,15 +3584,20 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -3371,15 +3610,20 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -3405,7 +3649,7 @@ sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , .Y ( data_inv[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) , .VPWR ( VDD ) , +sky130_fd_sc_hd__clkinv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -3436,7 +3680,7 @@ sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , .Y ( data_inv[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) , .VPWR ( VDD ) , +sky130_fd_sc_hd__clkinv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -3446,15 +3690,15 @@ endmodule module cby_2__1__mux_2level_size12_3 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; + VSS ) ; input [0:11] in ; input [0:3] sram ; input [0:3] sram_inv ; output [0:0] out ; input VDD ; input VSS ; -input p0 ; +wire [0:0] const1_0_const1 ; wire [0:3] local_encoder2to4_0_data ; wire [0:3] local_encoder2to4_0_data_inv ; wire [0:3] local_encoder2to4_1_data ; @@ -3467,7 +3711,7 @@ supply1 VDD ; supply0 VSS ; sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_1_0_ ( - .A ( mux_2level_basis_input4_mem4_3_out[0] ) , .X ( net_net_83 ) , + .A ( mux_2level_basis_input4_mem4_3_out[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; cby_2__1__local_encoder2to4_6 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , .data ( local_encoder2to4_0_data ) , @@ -3493,35 +3737,37 @@ cby_2__1__mux_2level_basis_input4_mem4_14 mux_l1_in_2_ ( .in ( in[8:11] ) , cby_2__1__mux_2level_basis_input4_mem4_15 mux_l2_in_0_ ( .in ( { mux_2level_basis_input4_mem4_0_out[0] , mux_2level_basis_input4_mem4_1_out[0] , - mux_2level_basis_input4_mem4_2_out[0] , SYNOPSYS_UNCONNECTED_1 } ) , + mux_2level_basis_input4_mem4_2_out[0] , const1_0_const1[0] } ) , .mem ( local_encoder2to4_1_data ) , .mem_inv ( local_encoder2to4_1_data_inv ) , .out ( mux_2level_basis_input4_mem4_3_out ) , .VDD ( VDD ) , - .VSS ( VSS ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_83 ( .A ( net_net_83 ) , .X ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .VSS ( VSS ) ) ; endmodule module cby_2__1__mux_2level_basis_input4_mem4_11 ( in , mem , mem_inv , out , - VDD , VSS , p0 ) ; + VDD , VSS ) ; input [0:3] in ; input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; input VDD ; input VSS ; -input p0 ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( p0 ) , + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -3534,15 +3780,20 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -3555,15 +3806,24 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; -scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , +scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( ZINV_7_7 ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( ZINV_11_13 ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__clkinv_1 ZINV_7_inst_939 ( .A ( in[1] ) , .Y ( ZINV_7_7 ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__clkinv_1 ZINV_11_inst_971 ( .A ( in[3] ) , + .Y ( ZINV_11_13 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -3576,15 +3836,22 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; -scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , +scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( ZINV_13_0 ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__clkinv_1 ZINV_13_inst_889 ( .A ( in[1] ) , .Y ( ZINV_13_0 ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -3610,7 +3877,7 @@ sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , .Y ( data_inv[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) , .VPWR ( VDD ) , +sky130_fd_sc_hd__clkinv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -3641,7 +3908,7 @@ sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , .Y ( data_inv[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) , .VPWR ( VDD ) , +sky130_fd_sc_hd__clkinv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -3651,15 +3918,15 @@ endmodule module cby_2__1__mux_2level_size12_2 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; + VSS ) ; input [0:11] in ; input [0:3] sram ; input [0:3] sram_inv ; output [0:0] out ; input VDD ; input VSS ; -input p0 ; +wire [0:0] const1_0_const1 ; wire [0:3] local_encoder2to4_0_data ; wire [0:3] local_encoder2to4_0_data_inv ; wire [0:3] local_encoder2to4_1_data ; @@ -3671,7 +3938,7 @@ wire [0:0] mux_2level_basis_input4_mem4_3_out ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__bufbuf_16 sky130_fd_sc_hd__buf_1_0_ ( +sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_1_0_ ( .A ( mux_2level_basis_input4_mem4_3_out[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; cby_2__1__local_encoder2to4_4 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , @@ -3698,33 +3965,37 @@ cby_2__1__mux_2level_basis_input4_mem4_10 mux_l1_in_2_ ( .in ( in[8:11] ) , cby_2__1__mux_2level_basis_input4_mem4_11 mux_l2_in_0_ ( .in ( { mux_2level_basis_input4_mem4_0_out[0] , mux_2level_basis_input4_mem4_1_out[0] , - mux_2level_basis_input4_mem4_2_out[0] , SYNOPSYS_UNCONNECTED_1 } ) , + mux_2level_basis_input4_mem4_2_out[0] , const1_0_const1[0] } ) , .mem ( local_encoder2to4_1_data ) , .mem_inv ( local_encoder2to4_1_data_inv ) , .out ( mux_2level_basis_input4_mem4_3_out ) , .VDD ( VDD ) , - .VSS ( VSS ) , .p0 ( p0 ) ) ; + .VSS ( VSS ) ) ; endmodule module cby_2__1__mux_2level_basis_input4_mem4_7 ( in , mem , mem_inv , out , - VDD , VSS , p0 ) ; + VDD , VSS ) ; input [0:3] in ; input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; input VDD ; input VSS ; -input p0 ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( p0 ) , + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -3737,15 +4008,24 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; -scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , +scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( ZINV_11_14 ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( ZINV_191_1 ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__clkinv_1 ZINV_191_inst_898 ( .A ( in[3] ) , + .Y ( ZINV_191_1 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__clkinv_1 ZINV_11_inst_990 ( .A ( in[1] ) , + .Y ( ZINV_11_14 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -3758,15 +4038,22 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( ZINV_4_11 ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__clkinv_1 ZINV_4_inst_957 ( .A ( in[3] ) , .Y ( ZINV_4_11 ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -3779,15 +4066,20 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -3813,7 +4105,7 @@ sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , .Y ( data_inv[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) , .VPWR ( VDD ) , +sky130_fd_sc_hd__clkinv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -3844,7 +4136,7 @@ sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , .Y ( data_inv[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) , .VPWR ( VDD ) , +sky130_fd_sc_hd__clkinv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -3854,15 +4146,15 @@ endmodule module cby_2__1__mux_2level_size12_1 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; + VSS ) ; input [0:11] in ; input [0:3] sram ; input [0:3] sram_inv ; output [0:0] out ; input VDD ; input VSS ; -input p0 ; +wire [0:0] const1_0_const1 ; wire [0:3] local_encoder2to4_0_data ; wire [0:3] local_encoder2to4_0_data_inv ; wire [0:3] local_encoder2to4_1_data ; @@ -3874,7 +4166,7 @@ wire [0:0] mux_2level_basis_input4_mem4_3_out ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__bufbuf_16 sky130_fd_sc_hd__buf_1_0_ ( +sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_1_0_ ( .A ( mux_2level_basis_input4_mem4_3_out[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; cby_2__1__local_encoder2to4_2 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , @@ -3901,33 +4193,37 @@ cby_2__1__mux_2level_basis_input4_mem4_6 mux_l1_in_2_ ( .in ( in[8:11] ) , cby_2__1__mux_2level_basis_input4_mem4_7 mux_l2_in_0_ ( .in ( { mux_2level_basis_input4_mem4_0_out[0] , mux_2level_basis_input4_mem4_1_out[0] , - mux_2level_basis_input4_mem4_2_out[0] , SYNOPSYS_UNCONNECTED_1 } ) , + mux_2level_basis_input4_mem4_2_out[0] , const1_0_const1[0] } ) , .mem ( local_encoder2to4_1_data ) , .mem_inv ( local_encoder2to4_1_data_inv ) , .out ( mux_2level_basis_input4_mem4_3_out ) , .VDD ( VDD ) , - .VSS ( VSS ) , .p0 ( p0 ) ) ; + .VSS ( VSS ) ) ; endmodule module cby_2__1__mux_2level_basis_input4_mem4_3 ( in , mem , mem_inv , out , - VDD , VSS , p0 ) ; + VDD , VSS ) ; input [0:3] in ; input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; input VDD ; input VSS ; -input p0 ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( p0 ) , + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -3940,15 +4236,20 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -3961,15 +4262,20 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -3982,15 +4288,20 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -4016,7 +4327,7 @@ sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , .Y ( data_inv[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) , .VPWR ( VDD ) , +sky130_fd_sc_hd__clkinv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -4047,7 +4358,7 @@ sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , .Y ( data_inv[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) , .VPWR ( VDD ) , +sky130_fd_sc_hd__clkinv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -4057,15 +4368,15 @@ endmodule module cby_2__1__mux_2level_size12_0 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; + VSS ) ; input [0:11] in ; input [0:3] sram ; input [0:3] sram_inv ; output [0:0] out ; input VDD ; input VSS ; -input p0 ; +wire [0:0] const1_0_const1 ; wire [0:3] local_encoder2to4_0_data ; wire [0:3] local_encoder2to4_0_data_inv ; wire [0:3] local_encoder2to4_1_data ; @@ -4078,7 +4389,7 @@ supply1 VDD ; supply0 VSS ; sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_1_0_ ( - .A ( mux_2level_basis_input4_mem4_3_out[0] ) , .X ( net_net_82 ) , + .A ( mux_2level_basis_input4_mem4_3_out[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; cby_2__1__local_encoder2to4_0 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , .data ( local_encoder2to4_0_data ) , @@ -4104,13 +4415,11 @@ cby_2__1__mux_2level_basis_input4_mem4_2 mux_l1_in_2_ ( .in ( in[8:11] ) , cby_2__1__mux_2level_basis_input4_mem4_3 mux_l2_in_0_ ( .in ( { mux_2level_basis_input4_mem4_0_out[0] , mux_2level_basis_input4_mem4_1_out[0] , - mux_2level_basis_input4_mem4_2_out[0] , SYNOPSYS_UNCONNECTED_1 } ) , + mux_2level_basis_input4_mem4_2_out[0] , const1_0_const1[0] } ) , .mem ( local_encoder2to4_1_data ) , .mem_inv ( local_encoder2to4_1_data_inv ) , .out ( mux_2level_basis_input4_mem4_3_out ) , .VDD ( VDD ) , - .VSS ( VSS ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_82 ( .A ( net_net_82 ) , .X ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .VSS ( VSS ) ) ; endmodule @@ -4199,101 +4508,105 @@ wire [0:0] mux_2level_size12_mem_5_ccff_tail ; wire [0:0] mux_2level_size12_mem_6_ccff_tail ; wire [0:0] mux_2level_size12_mem_7_ccff_tail ; wire [0:0] mux_2level_size12_mem_8_ccff_tail ; +wire [0:3] mux_left_ipin_0_undriven_sram_inv ; +wire [0:3] mux_right_ipin_0_undriven_sram_inv ; +wire [0:3] mux_right_ipin_10_undriven_sram_inv ; +wire [0:3] mux_right_ipin_11_undriven_sram_inv ; +wire [0:3] mux_right_ipin_12_undriven_sram_inv ; +wire [0:3] mux_right_ipin_13_undriven_sram_inv ; +wire [0:3] mux_right_ipin_14_undriven_sram_inv ; +wire [0:3] mux_right_ipin_15_undriven_sram_inv ; +wire [0:3] mux_right_ipin_1_undriven_sram_inv ; +wire [0:3] mux_right_ipin_2_undriven_sram_inv ; +wire [0:3] mux_right_ipin_3_undriven_sram_inv ; +wire [0:3] mux_right_ipin_4_undriven_sram_inv ; +wire [0:3] mux_right_ipin_5_undriven_sram_inv ; +wire [0:3] mux_right_ipin_6_undriven_sram_inv ; +wire [0:3] mux_right_ipin_7_undriven_sram_inv ; +wire [0:3] mux_right_ipin_8_undriven_sram_inv ; +wire [0:3] mux_right_ipin_9_undriven_sram_inv ; supply1 VDD ; supply0 VSS ; +assign left_width_0_height_0__pin_1_lower[0] = left_width_0_height_0__pin_1_upper[0] ; assign prog_clk_0 = prog_clk[0] ; cby_2__1__mux_2level_size12_0 mux_left_ipin_0 ( - .in ( { chany_top_out[0] , chany_bottom_out[0] , chany_top_out[3] , - chany_bottom_out[3] , chany_top_out[6] , chany_bottom_out[6] , - chany_top_out[12] , chany_bottom_out[12] , chany_top_out[18] , - chany_bottom_out[18] , chany_top_out[24] , chany_bottom_out[24] } ) , - .sram ( mux_2level_size12_0_sram ) , - .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 , - SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) , - .out ( right_grid_pin_0_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_101 ) ) ; + .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[3] , + ZINV_195_0 , chany_bottom_in[6] , chany_top_in[6] , + chany_top_out[12] , chany_top_in[12] , chany_bottom_in[18] , + chany_top_in[18] , chany_bottom_in[24] , chany_top_in[24] } ) , + .sram ( mux_2level_size12_0_sram ) , + .sram_inv ( mux_left_ipin_0_undriven_sram_inv ) , + .out ( { ZBUF_660_f_17 } ) , + .VDD ( VDD ) , .VSS ( VSS ) ) ; cby_2__1__mux_2level_size12_1 mux_right_ipin_0 ( - .in ( { chany_top_out[1] , chany_bottom_out[1] , chany_top_out[4] , - chany_bottom_out[4] , chany_top_out[7] , chany_bottom_out[7] , - chany_top_out[13] , chany_bottom_out[13] , chany_top_out[19] , - chany_bottom_out[19] , chany_top_out[25] , chany_bottom_out[25] } ) , - .sram ( mux_2level_size12_1_sram ) , - .sram_inv ( { SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 , - SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 } ) , - .out ( left_grid_pin_16_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_98 ) ) ; + .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[4] , + chany_top_in[4] , chany_bottom_in[7] , chany_bottom_out[7] , + chany_bottom_in[13] , ZINV_62_11 , chany_bottom_in[19] , ZINV_69_15 , + chany_bottom_in[25] , ZINV_267_1 } ) , + .sram ( mux_2level_size12_1_sram ) , + .sram_inv ( mux_right_ipin_0_undriven_sram_inv ) , + .out ( left_grid_pin_16_ ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; cby_2__1__mux_2level_size12_2 mux_right_ipin_2 ( - .in ( { chany_top_out[0] , chany_bottom_out[0] , chany_top_out[3] , - chany_bottom_out[3] , chany_top_out[9] , chany_bottom_out[9] , - chany_top_out[15] , chany_bottom_out[15] , chany_top_out[21] , - chany_bottom_out[21] , chany_top_out[27] , chany_bottom_out[27] } ) , - .sram ( mux_2level_size12_2_sram ) , - .sram_inv ( { SYNOPSYS_UNCONNECTED_9 , SYNOPSYS_UNCONNECTED_10 , - SYNOPSYS_UNCONNECTED_11 , SYNOPSYS_UNCONNECTED_12 } ) , - .out ( left_grid_pin_18_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_99 ) ) ; + .in ( { chany_bottom_in[0] , ZINV_71_0 , chany_bottom_in[3] , ZINV_195_0 , + chany_bottom_in[9] , ZINV_65_7 , chany_bottom_in[15] , ZINV_69_14 , + chany_bottom_in[21] , chany_bottom_out[21] , chany_bottom_in[27] , + chany_top_in[27] } ) , + .sram ( mux_2level_size12_2_sram ) , + .sram_inv ( mux_right_ipin_2_undriven_sram_inv ) , + .out ( left_grid_pin_18_ ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; cby_2__1__mux_2level_size12_3 mux_right_ipin_4 ( - .in ( { chany_top_out[2] , chany_bottom_out[2] , chany_top_out[5] , - chany_bottom_out[5] , chany_top_out[11] , chany_bottom_out[11] , - chany_top_out[17] , chany_bottom_out[17] , chany_top_out[23] , - chany_bottom_out[23] , chany_top_out[29] , chany_bottom_out[29] } ) , - .sram ( mux_2level_size12_3_sram ) , - .sram_inv ( { SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 , - SYNOPSYS_UNCONNECTED_15 , SYNOPSYS_UNCONNECTED_16 } ) , - .out ( left_grid_pin_20_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_98 ) ) ; + .in ( { chany_bottom_in[2] , chany_top_in[2] , ZINV_157_1 , + chany_top_in[5] , chany_bottom_in[11] , chany_top_in[11] , + chany_bottom_in[17] , chany_top_in[17] , chany_bottom_in[23] , + chany_top_in[23] , chany_bottom_in[29] , chany_top_in[29] } ) , + .sram ( mux_2level_size12_3_sram ) , + .sram_inv ( mux_right_ipin_4_undriven_sram_inv ) , + .out ( left_grid_pin_20_ ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; cby_2__1__mux_2level_size12_4 mux_right_ipin_6 ( - .in ( { chany_top_out[1] , chany_bottom_out[1] , chany_top_out[4] , - chany_bottom_out[4] , chany_top_out[7] , chany_bottom_out[7] , - chany_top_out[13] , chany_bottom_out[13] , chany_top_out[19] , - chany_bottom_out[19] , chany_top_out[25] , chany_bottom_out[25] } ) , - .sram ( mux_2level_size12_4_sram ) , - .sram_inv ( { SYNOPSYS_UNCONNECTED_17 , SYNOPSYS_UNCONNECTED_18 , - SYNOPSYS_UNCONNECTED_19 , SYNOPSYS_UNCONNECTED_20 } ) , - .out ( left_grid_pin_22_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_100 ) ) ; + .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[4] , + chany_top_in[4] , chany_bottom_in[7] , chany_top_in[7] , + chany_bottom_in[13] , chany_top_in[13] , chany_bottom_in[19] , + chany_top_in[19] , chany_bottom_in[25] , chany_top_in[25] } ) , + .sram ( mux_2level_size12_4_sram ) , + .sram_inv ( mux_right_ipin_6_undriven_sram_inv ) , + .out ( left_grid_pin_22_ ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; cby_2__1__mux_2level_size12_5 mux_right_ipin_8 ( - .in ( { chany_top_out[0] , chany_bottom_out[0] , chany_top_out[3] , - chany_bottom_out[3] , chany_top_out[9] , chany_bottom_out[9] , - chany_top_out[15] , chany_bottom_out[15] , chany_top_out[21] , - chany_bottom_out[21] , chany_top_out[27] , chany_bottom_out[27] } ) , - .sram ( mux_2level_size12_5_sram ) , - .sram_inv ( { SYNOPSYS_UNCONNECTED_21 , SYNOPSYS_UNCONNECTED_22 , - SYNOPSYS_UNCONNECTED_23 , SYNOPSYS_UNCONNECTED_24 } ) , - .out ( left_grid_pin_24_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_99 ) ) ; + .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[3] , + ZINV_195_0 , chany_bottom_in[9] , chany_top_in[9] , + chany_bottom_in[15] , chany_top_in[15] , chany_bottom_in[21] , + chany_bottom_out[21] , chany_bottom_in[27] , chany_top_in[27] } ) , + .sram ( mux_2level_size12_5_sram ) , + .sram_inv ( mux_right_ipin_8_undriven_sram_inv ) , + .out ( { ZBUF_274_f_16 } ) , + .VDD ( VDD ) , .VSS ( VSS ) ) ; cby_2__1__mux_2level_size12_6 mux_right_ipin_10 ( - .in ( { chany_top_out[2] , chany_bottom_out[2] , chany_top_out[5] , - chany_bottom_out[5] , chany_top_out[11] , chany_bottom_out[11] , - chany_top_out[17] , chany_bottom_out[17] , chany_top_out[23] , - chany_bottom_out[23] , chany_top_out[29] , chany_bottom_out[29] } ) , - .sram ( mux_2level_size12_6_sram ) , - .sram_inv ( { SYNOPSYS_UNCONNECTED_25 , SYNOPSYS_UNCONNECTED_26 , - SYNOPSYS_UNCONNECTED_27 , SYNOPSYS_UNCONNECTED_28 } ) , - .out ( left_grid_pin_26_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_102 ) ) ; + .in ( { ZINV_68_3 , chany_top_in[2] , ZINV_157_1 , chany_top_in[5] , + ZINV_62_3 , chany_top_in[11] , ZINV_19_4 , chany_top_in[17] , + ZINV_65_3 , chany_top_in[23] , chany_bottom_in[29] , + chany_top_in[29] } ) , + .sram ( mux_2level_size12_6_sram ) , + .sram_inv ( mux_right_ipin_10_undriven_sram_inv ) , + .out ( left_grid_pin_26_ ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; cby_2__1__mux_2level_size12_7 mux_right_ipin_12 ( - .in ( { chany_top_out[1] , chany_bottom_out[1] , chany_top_out[4] , - chany_bottom_out[4] , chany_top_out[7] , chany_bottom_out[7] , - chany_top_out[13] , chany_bottom_out[13] , chany_top_out[19] , - chany_bottom_out[19] , chany_top_out[25] , chany_bottom_out[25] } ) , - .sram ( mux_2level_size12_7_sram ) , - .sram_inv ( { SYNOPSYS_UNCONNECTED_29 , SYNOPSYS_UNCONNECTED_30 , - SYNOPSYS_UNCONNECTED_31 , SYNOPSYS_UNCONNECTED_32 } ) , - .out ( left_grid_pin_28_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_100 ) ) ; + .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[4] , + chany_top_in[4] , ZINV_65_4 , chany_top_in[7] , ZINV_65_6 , + chany_top_in[13] , chany_bottom_in[19] , chany_top_in[19] , + chany_bottom_in[25] , chany_top_in[25] } ) , + .sram ( mux_2level_size12_7_sram ) , + .sram_inv ( mux_right_ipin_12_undriven_sram_inv ) , + .out ( { ropt_net_3 } ) , + .VDD ( VDD ) , .VSS ( VSS ) ) ; cby_2__1__mux_2level_size12 mux_right_ipin_14 ( - .in ( { chany_top_out[0] , chany_bottom_out[0] , chany_top_out[3] , - chany_bottom_out[3] , chany_top_out[9] , chany_bottom_out[9] , - chany_top_out[15] , chany_bottom_out[15] , chany_top_out[21] , - chany_bottom_out[21] , chany_top_out[27] , chany_bottom_out[27] } ) , - .sram ( mux_2level_size12_8_sram ) , - .sram_inv ( { SYNOPSYS_UNCONNECTED_33 , SYNOPSYS_UNCONNECTED_34 , - SYNOPSYS_UNCONNECTED_35 , SYNOPSYS_UNCONNECTED_36 } ) , - .out ( left_grid_pin_30_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_99 ) ) ; + .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[3] , + ZINV_195_0 , chany_bottom_in[9] , chany_top_in[9] , ZINV_69_13 , + chany_top_in[15] , chany_bottom_in[21] , chany_bottom_out[21] , + chany_bottom_in[27] , chany_top_in[27] } ) , + .sram ( mux_2level_size12_8_sram ) , + .sram_inv ( mux_right_ipin_14_undriven_sram_inv ) , + .out ( { ZBUF_7_f_17 } ) , + .VDD ( VDD ) , .VSS ( VSS ) ) ; cby_2__1__mux_2level_size12_mem_0 mem_left_ipin_0 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( mux_2level_size12_mem_0_ccff_tail ) , @@ -4339,85 +4652,66 @@ cby_2__1__mux_2level_size12_mem mem_right_ipin_14 ( .pReset ( pReset ) , .ccff_tail ( mux_2level_size12_mem_8_ccff_tail ) , .mem_out ( mux_2level_size12_8_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; cby_2__1__mux_2level_size10_0 mux_right_ipin_1 ( - .in ( { chany_top_out[2] , chany_bottom_out[2] , chany_top_out[5] , - chany_bottom_out[5] , chany_top_out[8] , chany_bottom_out[8] , - chany_top_out[17] , chany_bottom_out[17] , chany_top_out[26] , - chany_bottom_out[26] } ) , - .sram ( mux_2level_size10_0_sram ) , - .sram_inv ( { SYNOPSYS_UNCONNECTED_37 , SYNOPSYS_UNCONNECTED_38 , - SYNOPSYS_UNCONNECTED_39 , SYNOPSYS_UNCONNECTED_40 } ) , - .out ( left_grid_pin_17_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_100 ) ) ; + .in ( { chany_bottom_in[2] , chany_top_in[2] , ZINV_157_1 , + chany_top_in[5] , ZINV_62_15 , chany_top_in[8] , ZINV_19_4 , + chany_top_in[17] , ZINV_62_14 , ZINV_892_f_17 } ) , + .sram ( mux_2level_size10_0_sram ) , + .sram_inv ( mux_right_ipin_1_undriven_sram_inv ) , + .out ( left_grid_pin_17_ ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; cby_2__1__mux_2level_size10_1 mux_right_ipin_3 ( - .in ( { chany_top_out[1] , chany_bottom_out[1] , chany_top_out[4] , - chany_bottom_out[4] , chany_top_out[10] , chany_bottom_out[10] , - chany_top_out[19] , chany_bottom_out[19] , chany_top_out[28] , - chany_bottom_out[28] } ) , - .sram ( mux_2level_size10_1_sram ) , - .sram_inv ( { SYNOPSYS_UNCONNECTED_41 , SYNOPSYS_UNCONNECTED_42 , - SYNOPSYS_UNCONNECTED_43 , SYNOPSYS_UNCONNECTED_44 } ) , - .out ( left_grid_pin_19_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_100 ) ) ; + .in ( { ZINV_62_0 , chany_top_in[1] , ZINV_72_0 , chany_top_in[4] , + chany_bottom_in[10] , chany_top_in[10] , chany_bottom_in[19] , + chany_top_in[19] , chany_top_out[28] , chany_top_in[28] } ) , + .sram ( mux_2level_size10_1_sram ) , + .sram_inv ( mux_right_ipin_3_undriven_sram_inv ) , + .out ( { ropt_net_2 } ) , + .VDD ( VDD ) , .VSS ( VSS ) ) ; cby_2__1__mux_2level_size10_2 mux_right_ipin_5 ( - .in ( { chany_top_out[0] , chany_bottom_out[0] , chany_top_out[3] , - chany_bottom_out[3] , chany_top_out[6] , chany_bottom_out[6] , - chany_top_out[12] , chany_bottom_out[12] , chany_top_out[21] , - chany_bottom_out[21] } ) , - .sram ( mux_2level_size10_2_sram ) , - .sram_inv ( { SYNOPSYS_UNCONNECTED_45 , SYNOPSYS_UNCONNECTED_46 , - SYNOPSYS_UNCONNECTED_47 , SYNOPSYS_UNCONNECTED_48 } ) , - .out ( left_grid_pin_21_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_99 ) ) ; + .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[3] , + ZINV_195_0 , chany_bottom_in[6] , chany_top_in[6] , ZINV_241_17 , + ZINV_62_10 , chany_bottom_in[21] , ZINV_423_3 } ) , + .sram ( mux_2level_size10_2_sram ) , + .sram_inv ( mux_right_ipin_5_undriven_sram_inv ) , + .out ( left_grid_pin_21_ ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; cby_2__1__mux_2level_size10_3 mux_right_ipin_7 ( - .in ( { chany_top_out[2] , chany_bottom_out[2] , chany_top_out[5] , - chany_bottom_out[5] , chany_top_out[8] , chany_bottom_out[8] , - chany_top_out[14] , chany_bottom_out[14] , chany_top_out[23] , - chany_bottom_out[23] } ) , - .sram ( mux_2level_size10_3_sram ) , - .sram_inv ( { SYNOPSYS_UNCONNECTED_49 , SYNOPSYS_UNCONNECTED_50 , - SYNOPSYS_UNCONNECTED_51 , SYNOPSYS_UNCONNECTED_52 } ) , - .out ( left_grid_pin_23_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_98 ) ) ; + .in ( { chany_bottom_in[2] , ZINV_68_2 , ZINV_157_1 , chany_top_in[5] , + chany_bottom_in[8] , chany_top_in[8] , chany_bottom_in[14] , + ZINV_62_9 , chany_bottom_in[23] , ZINV_65_5 } ) , + .sram ( mux_2level_size10_3_sram ) , + .sram_inv ( mux_right_ipin_7_undriven_sram_inv ) , + .out ( left_grid_pin_23_ ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; cby_2__1__mux_2level_size10_4 mux_right_ipin_9 ( - .in ( { chany_top_out[1] , chany_bottom_out[1] , chany_top_out[4] , - chany_bottom_out[4] , chany_top_out[10] , chany_bottom_out[10] , - chany_top_out[16] , chany_bottom_out[16] , chany_top_out[25] , - chany_bottom_out[25] } ) , - .sram ( mux_2level_size10_4_sram ) , - .sram_inv ( { SYNOPSYS_UNCONNECTED_53 , SYNOPSYS_UNCONNECTED_54 , - SYNOPSYS_UNCONNECTED_55 , SYNOPSYS_UNCONNECTED_56 } ) , - .out ( left_grid_pin_25_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_98 ) ) ; + .in ( { chany_bottom_in[1] , ZINV_68_0 , chany_bottom_in[4] , ZINV_68_1 , + chany_bottom_in[10] , chany_bottom_out[10] , chany_bottom_in[16] , + chany_top_in[16] , chany_bottom_in[25] , chany_bottom_out[25] } ) , + .sram ( mux_2level_size10_4_sram ) , + .sram_inv ( mux_right_ipin_9_undriven_sram_inv ) , + .out ( { ZBUF_275_f_17 } ) , + .VDD ( VDD ) , .VSS ( VSS ) ) ; cby_2__1__mux_2level_size10_5 mux_right_ipin_11 ( - .in ( { chany_top_out[0] , chany_bottom_out[0] , chany_top_out[3] , - chany_bottom_out[3] , chany_top_out[12] , chany_bottom_out[12] , - chany_top_out[18] , chany_bottom_out[18] , chany_top_out[27] , - chany_bottom_out[27] } ) , - .sram ( mux_2level_size10_5_sram ) , - .sram_inv ( { SYNOPSYS_UNCONNECTED_57 , SYNOPSYS_UNCONNECTED_58 , - SYNOPSYS_UNCONNECTED_59 , SYNOPSYS_UNCONNECTED_60 } ) , - .out ( left_grid_pin_27_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_103 ) ) ; + .in ( { ZINV_75_3 , chany_top_in[0] , chany_bottom_in[3] , ZINV_195_0 , + chany_top_out[12] , chany_top_in[12] , ZINV_69_12 , chany_top_in[18] , + chany_bottom_in[27] , chany_top_in[27] } ) , + .sram ( mux_2level_size10_5_sram ) , + .sram_inv ( mux_right_ipin_11_undriven_sram_inv ) , + .out ( { ZBUF_275_f_16 } ) , + .VDD ( VDD ) , .VSS ( VSS ) ) ; cby_2__1__mux_2level_size10_6 mux_right_ipin_13 ( - .in ( { chany_top_out[2] , chany_bottom_out[2] , chany_top_out[5] , - chany_bottom_out[5] , chany_top_out[14] , chany_bottom_out[14] , - chany_top_out[20] , chany_bottom_out[20] , chany_top_out[29] , - chany_bottom_out[29] } ) , - .sram ( mux_2level_size10_6_sram ) , - .sram_inv ( { SYNOPSYS_UNCONNECTED_61 , SYNOPSYS_UNCONNECTED_62 , - SYNOPSYS_UNCONNECTED_63 , SYNOPSYS_UNCONNECTED_64 } ) , - .out ( left_grid_pin_29_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_100 ) ) ; + .in ( { chany_bottom_in[2] , chany_top_in[2] , ZINV_157_1 , + chany_top_in[5] , chany_bottom_in[14] , chany_top_in[14] , + chany_bottom_in[20] , ZINV_62_16 , chany_bottom_in[29] , + chany_top_in[29] } ) , + .sram ( mux_2level_size10_6_sram ) , + .sram_inv ( mux_right_ipin_13_undriven_sram_inv ) , + .out ( left_grid_pin_29_ ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; cby_2__1__mux_2level_size10 mux_right_ipin_15 ( - .in ( { chany_top_out[1] , chany_bottom_out[1] , chany_top_out[4] , - chany_bottom_out[4] , chany_top_out[7] , chany_bottom_out[7] , - chany_top_out[16] , chany_bottom_out[16] , chany_top_out[22] , - chany_bottom_out[22] } ) , - .sram ( mux_2level_size10_7_sram ) , - .sram_inv ( { SYNOPSYS_UNCONNECTED_65 , SYNOPSYS_UNCONNECTED_66 , - SYNOPSYS_UNCONNECTED_67 , SYNOPSYS_UNCONNECTED_68 } ) , - .out ( left_grid_pin_31_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_100 ) ) ; + .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[4] , + chany_top_in[4] , chany_bottom_in[7] , chany_top_in[7] , + ZINV_1458_f_17 , chany_top_in[16] , chany_top_out[22] , + chany_top_in[22] } ) , + .sram ( mux_2level_size10_7_sram ) , + .sram_inv ( mux_right_ipin_15_undriven_sram_inv ) , + .out ( left_grid_pin_31_ ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; cby_2__1__mux_2level_size10_mem_0 mem_right_ipin_1 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( mux_2level_size12_mem_1_ccff_tail ) , @@ -4465,156 +4759,230 @@ cby_2__1__logical_tile_io_mode_io_ logical_tile_io_mode_io__0 ( .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ) , .io_outpad ( left_width_0_height_0__pin_0_ ) , .ccff_head ( { ccff_tail_mid } ) , - .io_inpad ( left_width_0_height_0__pin_1_lower ) , + .io_inpad ( left_width_0_height_0__pin_1_upper ) , .ccff_tail ( ccff_tail ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sky130_fd_sc_hd__buf_8 pReset_FTB00 ( .A ( pReset_S_in ) , .X ( pReset[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_1 prog_clk_0_FTB00 ( .A ( prog_clk_0_W_in ) , +sky130_fd_sc_hd__buf_16 prog_clk_0_FTB00 ( .A ( prog_clk_0_W_in ) , .X ( prog_clk[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__clkbuf_1 prog_clk_0_S_FTB01 ( .A ( prog_clk_0_W_in ) , - .X ( ctsbuf_net_1104 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .X ( ctsbuf_net_10 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__clkbuf_1 prog_clk_0_N_FTB01 ( .A ( prog_clk_0_W_in ) , - .X ( ctsbuf_net_2105 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_8 FTB_19__18 ( .A ( chany_bottom_in[0] ) , - .X ( chany_top_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_8 FTB_20__19 ( .A ( chany_bottom_in[1] ) , - .X ( chany_top_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_8 FTB_21__20 ( .A ( chany_bottom_in[2] ) , - .X ( chany_top_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_8 FTB_22__21 ( .A ( chany_bottom_in[3] ) , - .X ( chany_top_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_8 FTB_23__22 ( .A ( chany_bottom_in[4] ) , - .X ( chany_top_out[4] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_8 FTB_24__23 ( .A ( chany_bottom_in[5] ) , - .X ( chany_top_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_8 FTB_25__24 ( .A ( chany_bottom_in[6] ) , - .X ( chany_top_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_8 FTB_26__25 ( .A ( chany_bottom_in[7] ) , - .X ( chany_top_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_8 FTB_27__26 ( .A ( chany_bottom_in[8] ) , - .X ( chany_top_out[8] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_8 FTB_28__27 ( .A ( chany_bottom_in[9] ) , - .X ( chany_top_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_8 FTB_29__28 ( .A ( chany_bottom_in[10] ) , - .X ( chany_top_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_8 FTB_30__29 ( .A ( chany_bottom_in[11] ) , - .X ( chany_top_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_8 FTB_31__30 ( .A ( chany_bottom_in[12] ) , - .X ( chany_top_out[12] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_8 FTB_32__31 ( .A ( chany_bottom_in[13] ) , - .X ( chany_top_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_8 FTB_33__32 ( .A ( chany_bottom_in[14] ) , - .X ( chany_top_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_8 FTB_34__33 ( .A ( chany_bottom_in[15] ) , - .X ( chany_top_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_8 FTB_35__34 ( .A ( chany_bottom_in[16] ) , - .X ( chany_top_out[16] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_8 FTB_36__35 ( .A ( chany_bottom_in[17] ) , - .X ( chany_top_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_8 FTB_37__36 ( .A ( chany_bottom_in[18] ) , - .X ( chany_top_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_8 FTB_38__37 ( .A ( chany_bottom_in[19] ) , - .X ( chany_top_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_8 FTB_39__38 ( .A ( chany_bottom_in[20] ) , - .X ( chany_top_out[20] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_8 FTB_40__39 ( .A ( chany_bottom_in[21] ) , - .X ( chany_top_out[21] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_8 FTB_41__40 ( .A ( chany_bottom_in[22] ) , - .X ( chany_top_out[22] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_8 FTB_42__41 ( .A ( chany_bottom_in[23] ) , - .X ( chany_top_out[23] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_8 FTB_43__42 ( .A ( chany_bottom_in[24] ) , - .X ( chany_top_out[24] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_8 FTB_44__43 ( .A ( chany_bottom_in[25] ) , - .X ( chany_top_out[25] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_8 FTB_45__44 ( .A ( chany_bottom_in[26] ) , - .X ( chany_top_out[26] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_8 FTB_46__45 ( .A ( chany_bottom_in[27] ) , - .X ( chany_top_out[27] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_8 FTB_47__46 ( .A ( chany_bottom_in[28] ) , - .X ( chany_top_out[28] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_8 FTB_48__47 ( .A ( chany_bottom_in[29] ) , - .X ( chany_top_out[29] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_8 FTB_49__48 ( .A ( chany_top_in[0] ) , - .X ( chany_bottom_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_8 FTB_50__49 ( .A ( chany_top_in[1] ) , - .X ( chany_bottom_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_8 FTB_51__50 ( .A ( chany_top_in[2] ) , - .X ( chany_bottom_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_8 FTB_52__51 ( .A ( chany_top_in[3] ) , - .X ( chany_bottom_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_8 FTB_53__52 ( .A ( chany_top_in[4] ) , - .X ( chany_bottom_out[4] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_8 FTB_54__53 ( .A ( chany_top_in[5] ) , - .X ( chany_bottom_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_8 FTB_55__54 ( .A ( chany_top_in[6] ) , - .X ( chany_bottom_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_8 FTB_56__55 ( .A ( chany_top_in[7] ) , - .X ( chany_bottom_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_8 FTB_57__56 ( .A ( chany_top_in[8] ) , - .X ( chany_bottom_out[8] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_8 FTB_58__57 ( .A ( chany_top_in[9] ) , - .X ( chany_bottom_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_8 FTB_59__58 ( .A ( chany_top_in[10] ) , - .X ( chany_bottom_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_8 FTB_60__59 ( .A ( chany_top_in[11] ) , - .X ( chany_bottom_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_8 FTB_61__60 ( .A ( chany_top_in[12] ) , - .X ( chany_bottom_out[12] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_8 FTB_62__61 ( .A ( chany_top_in[13] ) , - .X ( chany_bottom_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_8 FTB_63__62 ( .A ( chany_top_in[14] ) , - .X ( chany_bottom_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_8 FTB_64__63 ( .A ( chany_top_in[15] ) , - .X ( chany_bottom_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_8 FTB_65__64 ( .A ( chany_top_in[16] ) , - .X ( chany_bottom_out[16] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_8 FTB_66__65 ( .A ( chany_top_in[17] ) , - .X ( chany_bottom_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_8 FTB_67__66 ( .A ( chany_top_in[18] ) , - .X ( chany_bottom_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_8 FTB_68__67 ( .A ( chany_top_in[19] ) , - .X ( chany_bottom_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_8 FTB_69__68 ( .A ( chany_top_in[20] ) , - .X ( chany_bottom_out[20] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_8 FTB_70__69 ( .A ( chany_top_in[21] ) , - .X ( chany_bottom_out[21] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_8 FTB_71__70 ( .A ( chany_top_in[22] ) , - .X ( chany_bottom_out[22] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_8 FTB_72__71 ( .A ( chany_top_in[23] ) , - .X ( chany_bottom_out[23] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_8 FTB_73__72 ( .A ( chany_top_in[24] ) , - .X ( chany_bottom_out[24] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_8 FTB_74__73 ( .A ( chany_top_in[25] ) , - .X ( chany_bottom_out[25] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_8 FTB_75__74 ( .A ( chany_top_in[26] ) , - .X ( chany_bottom_out[26] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_8 FTB_76__75 ( .A ( chany_top_in[27] ) , - .X ( chany_bottom_out[27] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_8 FTB_77__76 ( .A ( chany_top_in[28] ) , - .X ( chany_bottom_out[28] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_8 FTB_78__77 ( .A ( chany_top_in[29] ) , - .X ( chany_bottom_out[29] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_6 FTB_79__78 ( - .A ( left_width_0_height_0__pin_1_lower[0] ) , - .X ( left_width_0_height_0__pin_1_upper[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_99 ( .LO ( SYNOPSYS_UNCONNECTED_69 ) , - .HI ( optlc_net_98 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_102 ( .LO ( SYNOPSYS_UNCONNECTED_70 ) , - .HI ( optlc_net_99 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_104 ( .LO ( SYNOPSYS_UNCONNECTED_71 ) , - .HI ( optlc_net_100 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_105 ( .LO ( SYNOPSYS_UNCONNECTED_72 ) , - .HI ( optlc_net_101 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_107 ( .LO ( SYNOPSYS_UNCONNECTED_73 ) , - .HI ( optlc_net_102 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_108 ( .LO ( SYNOPSYS_UNCONNECTED_74 ) , - .HI ( optlc_net_103 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_6 cts_buf_3651248 ( .A ( ctsbuf_net_1104 ) , + .X ( ctsbuf_net_21 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__clkinv_4 ZINV_10_inst_877 ( .A ( ZINV_62_0 ) , + .Y ( chany_top_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 cts_buf_429755 ( .A ( ctsbuf_net_10 ) , .X ( prog_clk_0_S_out ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_6 cts_buf_3701253 ( .A ( ctsbuf_net_2105 ) , +sky130_fd_sc_hd__clkbuf_8 cts_buf_434760 ( .A ( ctsbuf_net_21 ) , .X ( prog_clk_0_N_out ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__clkinv_1 ZINV_62_inst_879 ( .A ( chany_bottom_in[1] ) , + .Y ( ZINV_62_0 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 ZBUF_18_f_inst_881 ( .A ( chany_bottom_in[3] ) , + .X ( chany_top_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__clkinv_4 ZINV_16_inst_882 ( .A ( ZINV_68_0 ) , + .Y ( chany_bottom_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__clkinv_1 ZINV_68_inst_884 ( .A ( chany_top_in[1] ) , + .Y ( ZINV_68_0 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__clkinv_4 ZINV_20_inst_885 ( .A ( ZINV_72_0 ) , + .Y ( chany_top_out[4] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__clkinv_1 ZINV_72_inst_887 ( .A ( chany_bottom_in[4] ) , + .Y ( ZINV_72_0 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__clkinv_4 ZINV_19_inst_888 ( .A ( ZINV_71_0 ) , + .Y ( chany_bottom_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__clkinv_1 ZINV_71_inst_890 ( .A ( chany_top_in[0] ) , + .Y ( ZINV_71_0 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 ZINV_205_inst_891 ( .A ( ZINV_267_0 ) , + .Y ( ropt_net_4 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 ZINV_195_inst_892 ( .A ( ZINV_267_0 ) , + .Y ( ZINV_195_0 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__clkinv_1 ZINV_267_inst_893 ( .A ( chany_top_in[3] ) , + .Y ( ZINV_267_0 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__clkinv_4 ZINV_16_inst_894 ( .A ( ZINV_68_1 ) , + .Y ( chany_bottom_out[4] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__clkinv_1 ZINV_68_inst_896 ( .A ( chany_top_in[4] ) , + .Y ( ZINV_68_1 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__clkinv_4 ZINV_215_inst_897 ( .A ( ZINV_267_1 ) , + .Y ( chany_bottom_out[25] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__clkinv_1 ZINV_267_inst_899 ( .A ( chany_top_in[25] ) , + .Y ( ZINV_267_1 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__clkinv_4 ZINV_166_inst_900 ( .A ( ZINV_252_1 ) , + .Y ( chany_top_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 ZINV_157_inst_901 ( .A ( ZINV_252_1 ) , + .Y ( ZINV_157_1 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__clkinv_1 ZINV_252_inst_902 ( .A ( chany_bottom_in[5] ) , + .Y ( ZINV_252_1 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__clkinv_4 ZINV_16_inst_903 ( .A ( ZINV_68_2 ) , + .Y ( chany_bottom_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__clkinv_1 ZINV_68_inst_905 ( .A ( chany_top_in[2] ) , + .Y ( ZINV_68_2 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__clkinv_4 ZINV_16_inst_906 ( .A ( ZINV_68_3 ) , + .Y ( chany_top_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__clkinv_1 ZINV_68_inst_908 ( .A ( chany_bottom_in[2] ) , + .Y ( ZINV_68_3 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__clkinv_4 ZINV_23_inst_909 ( .A ( ZINV_75_3 ) , + .Y ( chany_top_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__clkinv_1 ZINV_75_inst_911 ( .A ( chany_bottom_in[0] ) , + .Y ( ZINV_75_3 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 ZINV_346_inst_913 ( .A ( ZINV_423_3 ) , + .Y ( chany_bottom_out[21] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__clkinv_1 ZINV_423_inst_914 ( .A ( chany_top_in[21] ) , + .Y ( ZINV_423_3 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__clkinv_4 ZINV_10_inst_915 ( .A ( ZINV_62_3 ) , + .Y ( chany_top_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__clkinv_1 ZINV_62_inst_917 ( .A ( chany_bottom_in[11] ) , + .Y ( ZINV_62_3 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__clkinv_4 ZINV_13_inst_918 ( .A ( ZINV_65_3 ) , + .Y ( chany_top_out[23] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__clkinv_1 ZINV_65_inst_920 ( .A ( chany_bottom_in[23] ) , + .Y ( ZINV_65_3 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__clkinv_4 ZINV_13_inst_921 ( .A ( ZINV_65_4 ) , + .Y ( chany_top_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__clkinv_1 ZINV_65_inst_923 ( .A ( chany_bottom_in[7] ) , + .Y ( ZINV_65_4 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 ZBUF_11_f_inst_924 ( .A ( chany_bottom_in[27] ) , + .X ( chany_top_out[27] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 ZINV_25_inst_925 ( .A ( ZINV_77_4 ) , + .Y ( chany_top_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__clkinv_1 ZINV_19_inst_926 ( .A ( ZINV_77_4 ) , + .Y ( ZINV_19_4 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__clkinv_1 ZINV_77_inst_927 ( .A ( chany_bottom_in[17] ) , + .Y ( ZINV_77_4 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 ZBUF_14_f_inst_928 ( .A ( chany_top_in[5] ) , + .X ( chany_bottom_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 ZBUF_18_f_inst_929 ( .A ( chany_top_in[27] ) , + .X ( chany_bottom_out[27] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 ZBUF_11_f_inst_930 ( .A ( chany_bottom_in[19] ) , + .X ( chany_top_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__clkinv_4 ZINV_13_inst_931 ( .A ( ZINV_65_5 ) , + .Y ( chany_bottom_out[23] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__clkinv_1 ZINV_65_inst_933 ( .A ( chany_top_in[23] ) , + .Y ( ZINV_65_5 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__clkinv_4 ZINV_13_inst_934 ( .A ( ZINV_65_6 ) , + .Y ( chany_top_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__clkinv_1 ZINV_65_inst_936 ( .A ( chany_bottom_in[13] ) , + .Y ( ZINV_65_6 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 ZBUF_15_f_inst_937 ( .A ( chany_bottom_in[25] ) , + .X ( chany_top_out[25] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__clkinv_4 ZINV_13_inst_938 ( .A ( ZINV_65_7 ) , + .Y ( chany_bottom_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__clkinv_1 ZINV_65_inst_940 ( .A ( chany_top_in[9] ) , + .Y ( ZINV_65_7 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 ZBUF_11_f_inst_941 ( .A ( chany_bottom_in[6] ) , + .X ( chany_top_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 ZBUF_15_f_inst_942 ( .A ( chany_top_in[11] ) , + .X ( chany_bottom_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__clkbuf_8 ZBUF_14_f_inst_943 ( .A ( chany_bottom_in[14] ) , + .X ( chany_top_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 ZBUF_14_f_inst_944 ( .A ( chany_bottom_in[21] ) , + .X ( chany_top_out[21] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 ZBUF_8_f_inst_945 ( .A ( chany_bottom_in[29] ) , + .X ( chany_top_out[29] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 ZBUF_11_f_inst_946 ( .A ( chany_bottom_in[10] ) , + .X ( chany_top_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 ZBUF_8_f_inst_947 ( .A ( chany_top_in[8] ) , + .X ( chany_bottom_out[8] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__clkinv_4 ZINV_10_inst_948 ( .A ( ZINV_62_9 ) , + .Y ( chany_bottom_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__clkinv_1 ZINV_62_inst_950 ( .A ( chany_top_in[14] ) , + .Y ( ZINV_62_9 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__clkinv_4 ZINV_10_inst_951 ( .A ( ZINV_62_10 ) , + .Y ( chany_bottom_out[12] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__clkinv_1 ZINV_62_inst_953 ( .A ( chany_top_in[12] ) , + .Y ( ZINV_62_10 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 ZBUF_8_f_inst_955 ( .A ( chany_top_in[29] ) , + .X ( chany_bottom_out[29] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__clkinv_4 ZINV_10_inst_956 ( .A ( ZINV_62_11 ) , + .Y ( chany_bottom_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__clkinv_1 ZINV_62_inst_958 ( .A ( chany_top_in[13] ) , + .Y ( ZINV_62_11 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 ZBUF_15_f_inst_959 ( .A ( chany_top_in[16] ) , + .X ( chany_bottom_out[16] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__clkinv_4 ZINV_10_inst_962 ( .A ( ZINV_69_12 ) , + .Y ( chany_top_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__clkinv_1 ZINV_69_inst_963 ( .A ( chany_bottom_in[18] ) , + .Y ( ZINV_69_12 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__clkinv_4 ZINV_17_inst_967 ( .A ( ZINV_69_13 ) , + .Y ( chany_top_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__clkinv_1 ZINV_69_inst_969 ( .A ( chany_bottom_in[15] ) , + .Y ( ZINV_69_13 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__clkinv_4 ZINV_17_inst_970 ( .A ( ZINV_69_14 ) , + .Y ( chany_bottom_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__clkinv_1 ZINV_69_inst_972 ( .A ( chany_top_in[15] ) , + .Y ( ZINV_69_14 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 ZBUF_9_f_inst_976 ( .A ( chany_top_in[28] ) , + .X ( chany_bottom_out[28] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 ZINV_10_inst_977 ( .A ( ZINV_62_14 ) , + .Y ( chany_top_out[26] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__clkinv_1 ZINV_62_inst_979 ( .A ( chany_bottom_in[26] ) , + .Y ( ZINV_62_14 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__clkinv_4 ZINV_824_f_inst_986 ( .A ( ZINV_833_14 ) , + .Y ( chany_bottom_out[22] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__clkinv_1 ZINV_833_inst_987 ( .A ( chany_top_in[22] ) , + .Y ( ZINV_833_14 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__clkinv_4 ZINV_17_inst_989 ( .A ( ZINV_69_15 ) , + .Y ( chany_bottom_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__clkinv_1 ZINV_69_inst_991 ( .A ( chany_top_in[19] ) , + .Y ( ZINV_69_15 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__clkinv_4 ZINV_10_inst_993 ( .A ( ZINV_62_15 ) , + .Y ( chany_top_out[8] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__clkinv_1 ZINV_62_inst_995 ( .A ( chany_bottom_in[8] ) , + .Y ( ZINV_62_15 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 ZBUF_8_f_inst_999 ( .A ( chany_top_in[18] ) , + .X ( chany_bottom_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__clkinv_4 ZINV_10_inst_1003 ( .A ( ZINV_62_16 ) , + .Y ( chany_bottom_out[20] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__clkinv_1 ZINV_62_inst_1005 ( .A ( chany_top_in[20] ) , + .Y ( ZINV_62_16 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 ZBUF_275_f_inst_1009 ( .A ( ZBUF_275_f_16 ) , + .X ( left_grid_pin_27_[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 ZBUF_274_f_inst_1010 ( .A ( ZBUF_274_f_16 ) , + .X ( left_grid_pin_24_[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 ZBUF_275_f_inst_1011 ( .A ( ZBUF_275_f_17 ) , + .X ( left_grid_pin_25_[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 ZBUF_7_f_inst_1013 ( .A ( ZBUF_7_f_17 ) , + .X ( left_grid_pin_30_[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 ZINV_182_inst_1017 ( .A ( ZINV_241_17 ) , + .Y ( chany_top_out[12] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__clkinv_1 ZINV_241_inst_1018 ( .A ( chany_bottom_in[12] ) , + .Y ( ZINV_241_17 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 ZBUF_1030_f_inst_1019 ( .A ( chany_top_in[17] ) , + .X ( chany_bottom_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 ZBUF_815_f_inst_1021 ( .A ( chany_bottom_in[20] ) , + .X ( chany_top_out[20] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__clkinv_4 ZINV_1383_inst_1022 ( .A ( ZINV_1458_f_17 ) , + .Y ( chany_top_out[16] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__clkinv_1 ZINV_1458_f_inst_1024 ( .A ( chany_bottom_in[16] ) , + .Y ( ZINV_1458_f_17 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 ZBUF_826_f_inst_1025 ( .A ( chany_top_in[24] ) , + .X ( chany_bottom_out[24] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 ZBUF_1105_f_inst_1027 ( .A ( chany_top_in[6] ) , + .X ( chany_bottom_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__clkinv_4 ZINV_1528_f_inst_1029 ( .A ( ZINV_1537_17 ) , + .Y ( chany_bottom_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__clkinv_1 ZINV_1537_inst_1030 ( .A ( chany_top_in[7] ) , + .Y ( ZINV_1537_17 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 ZBUF_1011_f_inst_1031 ( .A ( chany_bottom_in[9] ) , + .X ( chany_top_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 ZBUF_1267_f_inst_1032 ( .A ( chany_top_in[10] ) , + .X ( chany_bottom_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__clkinv_4 ZINV_816_inst_1033 ( .A ( ZINV_892_f_17 ) , + .Y ( chany_bottom_out[26] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__clkinv_1 ZINV_892_f_inst_1035 ( .A ( chany_top_in[26] ) , + .Y ( ZINV_892_f_17 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 ZBUF_338_f_inst_1036 ( .A ( chany_bottom_in[24] ) , + .X ( chany_top_out[24] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__clkbuf_8 ZBUF_301_f_inst_1037 ( .A ( chany_bottom_in[22] ) , + .X ( chany_top_out[22] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 ZBUF_529_f_inst_1038 ( .A ( chany_bottom_in[28] ) , + .X ( chany_top_out[28] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 ZBUF_660_f_inst_1039 ( .A ( ZBUF_660_f_17 ) , + .X ( right_grid_pin_0_[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_4 ropt_mt_inst_1040 ( .A ( ropt_net_2 ) , + .X ( left_grid_pin_19_[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_4 ropt_mt_inst_1041 ( .A ( ropt_net_3 ) , + .X ( left_grid_pin_28_[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 ropt_mt_inst_1043 ( .A ( ropt_net_4 ) , + .X ( chany_bottom_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -4628,7 +4996,6 @@ output [0:3] mem_out ; input VDD ; input VSS ; -wire copt_net_121 ; supply1 VDD ; supply0 VSS ; @@ -4642,16 +5009,12 @@ sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( copt_net_121 ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_6 FTB_16__15 ( .A ( copt_net_126 ) , +sky130_fd_sc_hd__buf_6 FTB_16__15 ( .A ( copt_net_105 ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1371 ( .A ( copt_net_121 ) , - .X ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1372 ( .A ( mem_out[3] ) , - .X ( copt_net_122 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1376 ( .A ( copt_net_122 ) , - .X ( copt_net_126 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1342 ( .A ( mem_out[3] ) , + .X ( copt_net_105 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -4874,12 +5237,15 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -4893,15 +5259,20 @@ input VDD ; input VSS ; input p0 ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -4914,15 +5285,20 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -4935,15 +5311,20 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -5031,7 +5412,7 @@ supply1 VDD ; supply0 VSS ; sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_1_0_ ( - .A ( mux_2level_basis_input4_mem4_2_out[0] ) , .X ( aps_rename_512_ ) , + .A ( mux_2level_basis_input4_mem4_2_out[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; cby_1__1__local_encoder2to4_30 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , .data ( local_encoder2to4_0_data ) , @@ -5062,10 +5443,6 @@ cby_1__1__mux_2level_basis_input2_mem2 mux_l1_in_2_ ( .in ( in[8:9] ) , .mem_inv ( local_encoder2to4_0_data_inv[0:1] ) , .out ( mux_2level_basis_input2_mem2_0_out ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_93 ( .A ( BUF_net_94 ) , .Y ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_94 ( .A ( aps_rename_512_ ) , - .Y ( BUF_net_94 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -5078,12 +5455,15 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -5097,15 +5477,20 @@ input VDD ; input VSS ; input p0 ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -5118,15 +5503,20 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -5139,15 +5529,20 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -5234,7 +5629,7 @@ wire [0:0] mux_2level_basis_input4_mem4_2_out ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__bufbuf_16 sky130_fd_sc_hd__buf_1_0_ ( +sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_1_0_ ( .A ( mux_2level_basis_input4_mem4_2_out[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; cby_1__1__local_encoder2to4_28 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , @@ -5278,12 +5673,15 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -5297,15 +5695,20 @@ input VDD ; input VSS ; input p0 ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -5318,15 +5721,20 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -5339,15 +5747,20 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -5435,7 +5848,7 @@ supply1 VDD ; supply0 VSS ; sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_1_0_ ( - .A ( mux_2level_basis_input4_mem4_2_out[0] ) , .X ( out[0] ) , + .A ( mux_2level_basis_input4_mem4_2_out[0] ) , .X ( net_net_88 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; cby_1__1__local_encoder2to4_26 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , .data ( local_encoder2to4_0_data ) , @@ -5466,6 +5879,8 @@ cby_1__1__mux_2level_basis_input2_mem2_5 mux_l1_in_2_ ( .in ( in[8:9] ) , .mem_inv ( local_encoder2to4_0_data_inv[0:1] ) , .out ( mux_2level_basis_input2_mem2_0_out ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_88 ( .A ( net_net_88 ) , .X ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -5478,12 +5893,15 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -5497,15 +5915,20 @@ input VDD ; input VSS ; input p0 ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -5518,15 +5941,20 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -5539,15 +5967,20 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -5635,7 +6068,7 @@ supply1 VDD ; supply0 VSS ; sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_1_0_ ( - .A ( mux_2level_basis_input4_mem4_2_out[0] ) , .X ( aps_rename_511_ ) , + .A ( mux_2level_basis_input4_mem4_2_out[0] ) , .X ( aps_rename_510_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; cby_1__1__local_encoder2to4_24 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , .data ( local_encoder2to4_0_data ) , @@ -5666,10 +6099,10 @@ cby_1__1__mux_2level_basis_input2_mem2_4 mux_l1_in_2_ ( .in ( in[8:9] ) , .mem_inv ( local_encoder2to4_0_data_inv[0:1] ) , .out ( mux_2level_basis_input2_mem2_0_out ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sky130_fd_sc_hd__inv_6 BINV_R_104 ( .A ( BUF_net_105 ) , .Y ( out[0] ) , +sky130_fd_sc_hd__inv_6 BINV_R_86 ( .A ( BUF_net_87 ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_105 ( .A ( aps_rename_511_ ) , - .Y ( BUF_net_105 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_87 ( .A ( aps_rename_510_ ) , + .Y ( BUF_net_87 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -5682,12 +6115,15 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -5701,15 +6137,20 @@ input VDD ; input VSS ; input p0 ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -5722,15 +6163,20 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -5743,15 +6189,20 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -5882,12 +6333,15 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -5901,15 +6355,20 @@ input VDD ; input VSS ; input p0 ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -5922,15 +6381,20 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -5943,15 +6407,20 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -6082,12 +6551,15 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -6101,15 +6573,20 @@ input VDD ; input VSS ; input p0 ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -6122,15 +6599,20 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -6143,15 +6625,20 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -6239,7 +6726,7 @@ supply1 VDD ; supply0 VSS ; sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_1_0_ ( - .A ( mux_2level_basis_input4_mem4_2_out[0] ) , .X ( aps_rename_510_ ) , + .A ( mux_2level_basis_input4_mem4_2_out[0] ) , .X ( aps_rename_509_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; cby_1__1__local_encoder2to4_18 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , .data ( local_encoder2to4_0_data ) , @@ -6270,10 +6757,10 @@ cby_1__1__mux_2level_basis_input2_mem2_1 mux_l1_in_2_ ( .in ( in[8:9] ) , .mem_inv ( local_encoder2to4_0_data_inv[0:1] ) , .out ( mux_2level_basis_input2_mem2_0_out ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_89 ( .A ( BUF_net_90 ) , .Y ( out[0] ) , +sky130_fd_sc_hd__inv_8 BINV_R_84 ( .A ( BUF_net_85 ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_90 ( .A ( aps_rename_510_ ) , - .Y ( BUF_net_90 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_85 ( .A ( aps_rename_509_ ) , + .Y ( BUF_net_85 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -6286,12 +6773,15 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -6305,15 +6795,20 @@ input VDD ; input VSS ; input p0 ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -6326,15 +6821,20 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -6347,15 +6847,20 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -6443,7 +6948,7 @@ supply1 VDD ; supply0 VSS ; sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_1_0_ ( - .A ( mux_2level_basis_input4_mem4_2_out[0] ) , .X ( aps_rename_509_ ) , + .A ( mux_2level_basis_input4_mem4_2_out[0] ) , .X ( aps_rename_508_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; cby_1__1__local_encoder2to4_16 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , .data ( local_encoder2to4_0_data ) , @@ -6474,10 +6979,8 @@ cby_1__1__mux_2level_basis_input2_mem2_0 mux_l1_in_2_ ( .in ( in[8:9] ) , .mem_inv ( local_encoder2to4_0_data_inv[0:1] ) , .out ( mux_2level_basis_input2_mem2_0_out ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_87 ( .A ( BUF_net_88 ) , .Y ( out[0] ) , +sky130_fd_sc_hd__buf_6 BUFT_RR_94 ( .A ( aps_rename_508_ ) , .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_88 ( .A ( aps_rename_509_ ) , - .Y ( BUF_net_88 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -6704,7 +7207,7 @@ input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ropt_net_132 ) , +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , @@ -6718,24 +7221,6 @@ sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_1 FTB_1__0 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1364 ( .A ( ropt_net_133 ) , - .X ( copt_net_114 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1365 ( .A ( copt_net_116 ) , - .X ( copt_net_115 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1366 ( .A ( copt_net_114 ) , - .X ( copt_net_116 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1367 ( .A ( ccff_head[0] ) , - .X ( copt_net_117 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1374 ( .A ( copt_net_115 ) , - .X ( copt_net_124 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 copt_h_inst_1375 ( .A ( copt_net_124 ) , - .X ( copt_net_125 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1380 ( .A ( copt_net_125 ) , - .X ( ropt_net_131 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1381 ( .A ( ropt_net_131 ) , - .X ( ropt_net_132 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 ropt_h_inst_1382 ( .A ( copt_net_117 ) , - .X ( ropt_net_133 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -6749,15 +7234,20 @@ input VDD ; input VSS ; input p0 ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -6770,15 +7260,20 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -6791,15 +7286,20 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -6812,15 +7312,20 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -6907,7 +7412,7 @@ wire [0:0] mux_2level_basis_input4_mem4_3_out ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__bufbuf_16 sky130_fd_sc_hd__buf_1_0_ ( +sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_1_0_ ( .A ( mux_2level_basis_input4_mem4_3_out[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; cby_1__1__local_encoder2to4_14 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , @@ -6952,15 +7457,20 @@ input VDD ; input VSS ; input p0 ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -6973,15 +7483,20 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -6994,15 +7509,20 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -7015,15 +7535,20 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -7111,7 +7636,7 @@ supply1 VDD ; supply0 VSS ; sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_1_0_ ( - .A ( mux_2level_basis_input4_mem4_3_out[0] ) , .X ( aps_rename_508_ ) , + .A ( mux_2level_basis_input4_mem4_3_out[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; cby_1__1__local_encoder2to4_12 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , .data ( local_encoder2to4_0_data ) , @@ -7142,10 +7667,6 @@ cby_1__1__mux_2level_basis_input4_mem4_27 mux_l2_in_0_ ( .mem_inv ( local_encoder2to4_1_data_inv ) , .out ( mux_2level_basis_input4_mem4_3_out ) , .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_85 ( .A ( BUF_net_86 ) , .Y ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_86 ( .A ( aps_rename_508_ ) , - .Y ( BUF_net_86 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -7159,15 +7680,20 @@ input VDD ; input VSS ; input p0 ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -7180,15 +7706,20 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -7201,15 +7732,20 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -7222,15 +7758,20 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -7318,7 +7859,7 @@ supply1 VDD ; supply0 VSS ; sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_1_0_ ( - .A ( mux_2level_basis_input4_mem4_3_out[0] ) , .X ( net_net_84 ) , + .A ( mux_2level_basis_input4_mem4_3_out[0] ) , .X ( aps_rename_507_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; cby_1__1__local_encoder2to4_10 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , .data ( local_encoder2to4_0_data ) , @@ -7349,8 +7890,10 @@ cby_1__1__mux_2level_basis_input4_mem4_23 mux_l2_in_0_ ( .mem_inv ( local_encoder2to4_1_data_inv ) , .out ( mux_2level_basis_input4_mem4_3_out ) , .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_84 ( .A ( net_net_84 ) , .X ( out[0] ) , +sky130_fd_sc_hd__inv_8 BINV_R_80 ( .A ( BUF_net_81 ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_81 ( .A ( aps_rename_507_ ) , + .Y ( BUF_net_81 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -7364,15 +7907,20 @@ input VDD ; input VSS ; input p0 ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -7385,15 +7933,20 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -7406,15 +7959,20 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -7427,15 +7985,20 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -7523,7 +8086,7 @@ supply1 VDD ; supply0 VSS ; sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_1_0_ ( - .A ( mux_2level_basis_input4_mem4_3_out[0] ) , .X ( aps_rename_507_ ) , + .A ( mux_2level_basis_input4_mem4_3_out[0] ) , .X ( aps_rename_506_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; cby_1__1__local_encoder2to4_8 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , .data ( local_encoder2to4_0_data ) , @@ -7554,10 +8117,10 @@ cby_1__1__mux_2level_basis_input4_mem4_19 mux_l2_in_0_ ( .mem_inv ( local_encoder2to4_1_data_inv ) , .out ( mux_2level_basis_input4_mem4_3_out ) , .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_82 ( .A ( BUF_net_83 ) , .Y ( out[0] ) , +sky130_fd_sc_hd__inv_6 BINV_R_78 ( .A ( BUF_net_79 ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_83 ( .A ( aps_rename_507_ ) , - .Y ( BUF_net_83 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_79 ( .A ( aps_rename_506_ ) , + .Y ( BUF_net_79 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -7571,15 +8134,20 @@ input VDD ; input VSS ; input p0 ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -7592,15 +8160,20 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -7613,15 +8186,20 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -7634,15 +8212,20 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -7729,8 +8312,8 @@ wire [0:0] mux_2level_basis_input4_mem4_3_out ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_1_0_ ( - .A ( mux_2level_basis_input4_mem4_3_out[0] ) , .X ( net_net_81 ) , +sky130_fd_sc_hd__bufbuf_16 sky130_fd_sc_hd__buf_1_0_ ( + .A ( mux_2level_basis_input4_mem4_3_out[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; cby_1__1__local_encoder2to4_6 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , .data ( local_encoder2to4_0_data ) , @@ -7761,8 +8344,6 @@ cby_1__1__mux_2level_basis_input4_mem4_15 mux_l2_in_0_ ( .mem_inv ( local_encoder2to4_1_data_inv ) , .out ( mux_2level_basis_input4_mem4_3_out ) , .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_81 ( .A ( net_net_81 ) , .X ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -7776,15 +8357,20 @@ input VDD ; input VSS ; input p0 ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -7797,15 +8383,20 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -7818,15 +8409,20 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -7839,15 +8435,20 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -7934,8 +8535,8 @@ wire [0:0] mux_2level_basis_input4_mem4_3_out ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_1_0_ ( - .A ( mux_2level_basis_input4_mem4_3_out[0] ) , .X ( aps_rename_506_ ) , +sky130_fd_sc_hd__bufbuf_16 sky130_fd_sc_hd__buf_1_0_ ( + .A ( mux_2level_basis_input4_mem4_3_out[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; cby_1__1__local_encoder2to4_4 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , .data ( local_encoder2to4_0_data ) , @@ -7966,10 +8567,6 @@ cby_1__1__mux_2level_basis_input4_mem4_11 mux_l2_in_0_ ( .mem_inv ( local_encoder2to4_1_data_inv ) , .out ( mux_2level_basis_input4_mem4_3_out ) , .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_79 ( .A ( BUF_net_80 ) , .Y ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_80 ( .A ( aps_rename_506_ ) , - .Y ( BUF_net_80 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -7983,15 +8580,20 @@ input VDD ; input VSS ; input p0 ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -8004,15 +8606,20 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -8025,15 +8632,20 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -8046,15 +8658,20 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -8173,8 +8790,10 @@ cby_1__1__mux_2level_basis_input4_mem4_7 mux_l2_in_0_ ( .mem_inv ( local_encoder2to4_1_data_inv ) , .out ( mux_2level_basis_input4_mem4_3_out ) , .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_101 ( .A ( aps_rename_505_ ) , .X ( out[0] ) , +sky130_fd_sc_hd__inv_6 BINV_R_76 ( .A ( BUF_net_77 ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_77 ( .A ( aps_rename_505_ ) , + .Y ( BUF_net_77 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -8188,15 +8807,20 @@ input VDD ; input VSS ; input p0 ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -8209,15 +8833,20 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -8230,15 +8859,20 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -8251,15 +8885,20 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -8347,7 +8986,7 @@ supply1 VDD ; supply0 VSS ; sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_1_0_ ( - .A ( mux_2level_basis_input4_mem4_3_out[0] ) , .X ( net_net_76 ) , + .A ( mux_2level_basis_input4_mem4_3_out[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; cby_1__1__local_encoder2to4_0 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , .data ( local_encoder2to4_0_data ) , @@ -8378,8 +9017,6 @@ cby_1__1__mux_2level_basis_input4_mem4_3 mux_l2_in_0_ ( .mem_inv ( local_encoder2to4_1_data_inv ) , .out ( mux_2level_basis_input4_mem4_3_out ) , .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_76 ( .A ( net_net_76 ) , .X ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -8457,8 +9094,6 @@ output clk_3_S_out ; input VDD ; input VSS ; -wire ropt_net_130 ; -wire ropt_net_129 ; wire [0:0] prog_clk ; wire prog_clk_0 ; wire [0:3] mux_2level_size10_0_sram ; @@ -8514,7 +9149,7 @@ cby_1__1__mux_2level_size12_0 mux_right_ipin_0 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 , SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) , .out ( left_grid_pin_16_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_110 ) ) ; + .p0 ( optlc_net_99 ) ) ; cby_1__1__mux_2level_size12_1 mux_right_ipin_2 ( .in ( { chany_top_out[2] , chany_bottom_out[2] , chany_top_out[5] , chany_bottom_out[5] , chany_top_out[8] , chany_bottom_out[8] , @@ -8524,7 +9159,7 @@ cby_1__1__mux_2level_size12_1 mux_right_ipin_2 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 , SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 } ) , .out ( left_grid_pin_18_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_107 ) ) ; + .p0 ( optlc_net_100 ) ) ; cby_1__1__mux_2level_size12_2 mux_right_ipin_4 ( .in ( { chany_top_out[1] , chany_bottom_out[1] , chany_top_out[4] , chany_bottom_out[4] , chany_top_out[10] , chany_bottom_out[10] , @@ -8534,7 +9169,7 @@ cby_1__1__mux_2level_size12_2 mux_right_ipin_4 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_9 , SYNOPSYS_UNCONNECTED_10 , SYNOPSYS_UNCONNECTED_11 , SYNOPSYS_UNCONNECTED_12 } ) , .out ( left_grid_pin_20_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_109 ) ) ; + .p0 ( optlc_net_99 ) ) ; cby_1__1__mux_2level_size12_3 mux_right_ipin_6 ( .in ( { chany_top_out[0] , chany_bottom_out[0] , chany_top_out[3] , chany_bottom_out[3] , chany_top_out[6] , chany_bottom_out[6] , @@ -8544,7 +9179,7 @@ cby_1__1__mux_2level_size12_3 mux_right_ipin_6 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 , SYNOPSYS_UNCONNECTED_15 , SYNOPSYS_UNCONNECTED_16 } ) , .out ( left_grid_pin_22_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_110 ) ) ; + .p0 ( optlc_net_101 ) ) ; cby_1__1__mux_2level_size12_4 mux_right_ipin_8 ( .in ( { chany_top_out[2] , chany_bottom_out[2] , chany_top_out[5] , chany_bottom_out[5] , chany_top_out[8] , chany_bottom_out[8] , @@ -8554,7 +9189,7 @@ cby_1__1__mux_2level_size12_4 mux_right_ipin_8 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_17 , SYNOPSYS_UNCONNECTED_18 , SYNOPSYS_UNCONNECTED_19 , SYNOPSYS_UNCONNECTED_20 } ) , .out ( left_grid_pin_24_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_108 ) ) ; + .p0 ( optlc_net_100 ) ) ; cby_1__1__mux_2level_size12_5 mux_right_ipin_10 ( .in ( { chany_top_out[1] , chany_bottom_out[1] , chany_top_out[4] , chany_bottom_out[4] , chany_top_out[10] , chany_bottom_out[10] , @@ -8564,7 +9199,7 @@ cby_1__1__mux_2level_size12_5 mux_right_ipin_10 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_21 , SYNOPSYS_UNCONNECTED_22 , SYNOPSYS_UNCONNECTED_23 , SYNOPSYS_UNCONNECTED_24 } ) , .out ( left_grid_pin_26_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_106 ) ) ; + .p0 ( optlc_net_102 ) ) ; cby_1__1__mux_2level_size12_6 mux_right_ipin_12 ( .in ( { chany_top_out[0] , chany_bottom_out[0] , chany_top_out[3] , chany_bottom_out[3] , chany_top_out[6] , chany_bottom_out[6] , @@ -8574,7 +9209,7 @@ cby_1__1__mux_2level_size12_6 mux_right_ipin_12 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_25 , SYNOPSYS_UNCONNECTED_26 , SYNOPSYS_UNCONNECTED_27 , SYNOPSYS_UNCONNECTED_28 } ) , .out ( left_grid_pin_28_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_110 ) ) ; + .p0 ( optlc_net_101 ) ) ; cby_1__1__mux_2level_size12 mux_right_ipin_14 ( .in ( { chany_top_out[2] , chany_bottom_out[2] , chany_top_out[5] , chany_bottom_out[5] , chany_top_out[8] , chany_bottom_out[8] , @@ -8584,7 +9219,7 @@ cby_1__1__mux_2level_size12 mux_right_ipin_14 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_29 , SYNOPSYS_UNCONNECTED_30 , SYNOPSYS_UNCONNECTED_31 , SYNOPSYS_UNCONNECTED_32 } ) , .out ( left_grid_pin_30_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_108 ) ) ; + .p0 ( optlc_net_101 ) ) ; cby_1__1__mux_2level_size12_mem_0 mem_right_ipin_0 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( mux_2level_size12_mem_0_ccff_tail ) , @@ -8633,7 +9268,7 @@ cby_1__1__mux_2level_size10_0 mux_right_ipin_1 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_33 , SYNOPSYS_UNCONNECTED_34 , SYNOPSYS_UNCONNECTED_35 , SYNOPSYS_UNCONNECTED_36 } ) , .out ( left_grid_pin_17_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_108 ) ) ; + .p0 ( optlc_net_101 ) ) ; cby_1__1__mux_2level_size10_1 mux_right_ipin_3 ( .in ( { chany_top_out[0] , chany_bottom_out[0] , chany_top_out[3] , chany_bottom_out[3] , chany_top_out[9] , chany_bottom_out[9] , @@ -8643,7 +9278,7 @@ cby_1__1__mux_2level_size10_1 mux_right_ipin_3 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_37 , SYNOPSYS_UNCONNECTED_38 , SYNOPSYS_UNCONNECTED_39 , SYNOPSYS_UNCONNECTED_40 } ) , .out ( left_grid_pin_19_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_108 ) ) ; + .p0 ( optlc_net_100 ) ) ; cby_1__1__mux_2level_size10_2 mux_right_ipin_5 ( .in ( { chany_top_out[2] , chany_bottom_out[2] , chany_top_out[5] , chany_bottom_out[5] , chany_top_out[11] , chany_bottom_out[11] , @@ -8653,7 +9288,7 @@ cby_1__1__mux_2level_size10_2 mux_right_ipin_5 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_41 , SYNOPSYS_UNCONNECTED_42 , SYNOPSYS_UNCONNECTED_43 , SYNOPSYS_UNCONNECTED_44 } ) , .out ( left_grid_pin_21_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_109 ) ) ; + .p0 ( optlc_net_99 ) ) ; cby_1__1__mux_2level_size10_3 mux_right_ipin_7 ( .in ( { chany_top_out[1] , chany_bottom_out[1] , chany_top_out[4] , chany_bottom_out[4] , chany_top_out[7] , chany_bottom_out[7] , @@ -8663,7 +9298,7 @@ cby_1__1__mux_2level_size10_3 mux_right_ipin_7 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_45 , SYNOPSYS_UNCONNECTED_46 , SYNOPSYS_UNCONNECTED_47 , SYNOPSYS_UNCONNECTED_48 } ) , .out ( left_grid_pin_23_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_109 ) ) ; + .p0 ( optlc_net_99 ) ) ; cby_1__1__mux_2level_size10_4 mux_right_ipin_9 ( .in ( { chany_top_out[0] , chany_bottom_out[0] , chany_top_out[3] , chany_bottom_out[3] , chany_top_out[9] , chany_bottom_out[9] , @@ -8673,7 +9308,7 @@ cby_1__1__mux_2level_size10_4 mux_right_ipin_9 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_49 , SYNOPSYS_UNCONNECTED_50 , SYNOPSYS_UNCONNECTED_51 , SYNOPSYS_UNCONNECTED_52 } ) , .out ( left_grid_pin_25_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_106 ) ) ; + .p0 ( optlc_net_100 ) ) ; cby_1__1__mux_2level_size10_5 mux_right_ipin_11 ( .in ( { chany_top_out[2] , chany_bottom_out[2] , chany_top_out[5] , chany_bottom_out[5] , chany_top_out[11] , chany_bottom_out[11] , @@ -8682,8 +9317,8 @@ cby_1__1__mux_2level_size10_5 mux_right_ipin_11 ( .sram ( mux_2level_size10_5_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_53 , SYNOPSYS_UNCONNECTED_54 , SYNOPSYS_UNCONNECTED_55 , SYNOPSYS_UNCONNECTED_56 } ) , - .out ( { ropt_net_128 } ) , - .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_109 ) ) ; + .out ( left_grid_pin_27_ ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_101 ) ) ; cby_1__1__mux_2level_size10_6 mux_right_ipin_13 ( .in ( { chany_top_out[1] , chany_bottom_out[1] , chany_top_out[4] , chany_bottom_out[4] , chany_top_out[13] , chany_bottom_out[13] , @@ -8693,7 +9328,7 @@ cby_1__1__mux_2level_size10_6 mux_right_ipin_13 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_57 , SYNOPSYS_UNCONNECTED_58 , SYNOPSYS_UNCONNECTED_59 , SYNOPSYS_UNCONNECTED_60 } ) , .out ( left_grid_pin_29_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_106 ) ) ; + .p0 ( optlc_net_99 ) ) ; cby_1__1__mux_2level_size10 mux_right_ipin_15 ( .in ( { chany_top_out[0] , chany_bottom_out[0] , chany_top_out[3] , chany_bottom_out[3] , chany_top_out[6] , chany_bottom_out[6] , @@ -8703,7 +9338,7 @@ cby_1__1__mux_2level_size10 mux_right_ipin_15 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_61 , SYNOPSYS_UNCONNECTED_62 , SYNOPSYS_UNCONNECTED_63 , SYNOPSYS_UNCONNECTED_64 } ) , .out ( left_grid_pin_31_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_111 ) ) ; + .p0 ( optlc_net_102 ) ) ; cby_1__1__mux_2level_size10_mem_0 mem_right_ipin_1 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( mux_2level_size12_mem_0_ccff_tail ) , @@ -8744,44 +9379,44 @@ cby_1__1__mux_2level_size10_mem mem_right_ipin_15 ( .pReset ( pReset ) , .ccff_head ( mux_2level_size12_mem_7_ccff_tail ) , .ccff_tail ( ccff_tail ) , .mem_out ( mux_2level_size10_7_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sky130_fd_sc_hd__bufbuf_16 Test_en_N_FTB01 ( .A ( Test_en_E_in ) , - .X ( Test_en_N_out ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__bufbuf_16 Test_en_W_FTB01 ( .A ( Test_en_E_in ) , +sky130_fd_sc_hd__buf_1 Test_en_N_FTB01 ( .A ( Test_en_E_in ) , + .X ( net_net_89 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_4 Test_en_W_FTB01 ( .A ( Test_en_E_in ) , .X ( Test_en_W_out ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__bufbuf_16 Test_en_E_FTB01 ( .A ( Test_en_E_in ) , .X ( Test_en_E_out ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_8 pReset_FTB00 ( .A ( pReset_S_in ) , .X ( pReset[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_109 ( .LO ( SYNOPSYS_UNCONNECTED_65 ) , - .HI ( optlc_net_106 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_1 Reset_N_FTB01 ( .A ( Reset_E_in ) , - .X ( aps_rename_513_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__bufbuf_16 Reset_W_FTB01 ( .A ( Reset_E_in ) , +sky130_fd_sc_hd__conb_1 optlc_98 ( .LO ( SYNOPSYS_UNCONNECTED_65 ) , + .HI ( optlc_net_99 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__bufbuf_16 Reset_N_FTB01 ( .A ( Reset_E_in ) , + .X ( Reset_N_out ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_4 Reset_W_FTB01 ( .A ( Reset_E_in ) , .X ( Reset_W_out ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__bufbuf_16 Reset_E_FTB01 ( .A ( Reset_E_in ) , .X ( Reset_E_out ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_1 prog_clk_0_FTB00 ( .A ( prog_clk_0_W_in ) , +sky130_fd_sc_hd__buf_16 prog_clk_0_FTB00 ( .A ( prog_clk_0_W_in ) , .X ( prog_clk[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__clkbuf_1 prog_clk_0_S_FTB01 ( .A ( prog_clk_0_W_in ) , - .X ( ctsbuf_net_1112 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .X ( ctsbuf_net_1103 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__clkbuf_1 prog_clk_0_N_FTB01 ( .A ( prog_clk_0_W_in ) , - .X ( ctsbuf_net_2113 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_1 prog_clk_2_S_FTB01 ( .A ( prog_clk_2_S_in ) , - .X ( aps_rename_514_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_1 prog_clk_2_N_FTB01 ( .A ( prog_clk_2_S_in ) , - .X ( aps_rename_515_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_1 prog_clk_3_N_FTB01 ( .A ( prog_clk_3_N_in ) , - .X ( aps_rename_516_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_1 prog_clk_3_S_FTB01 ( .A ( prog_clk_3_N_in ) , - .X ( aps_rename_517_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_1 clk_2_S_FTB01 ( .A ( clk_2_S_in ) , - .X ( aps_rename_518_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_1 clk_2_N_FTB01 ( .A ( clk_2_S_in ) , - .X ( aps_rename_519_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_1 clk_3_N_FTB01 ( .A ( clk_3_N_in ) , - .X ( aps_rename_520_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_1 clk_3_S_FTB01 ( .A ( clk_3_N_in ) , - .X ( aps_rename_521_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .X ( ctsbuf_net_2104 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_4 prog_clk_2_S_FTB01 ( .A ( prog_clk_2_S_in ) , + .X ( prog_clk_2_S_out ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__bufbuf_16 prog_clk_2_N_FTB01 ( .A ( prog_clk_2_S_in ) , + .X ( prog_clk_2_N_out ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__bufbuf_16 prog_clk_3_N_FTB01 ( .A ( prog_clk_3_N_in ) , + .X ( prog_clk_3_N_out ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_4 prog_clk_3_S_FTB01 ( .A ( prog_clk_3_N_in ) , + .X ( prog_clk_3_S_out ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_4 clk_2_S_FTB01 ( .A ( clk_2_S_in ) , + .X ( clk_2_S_out ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__bufbuf_16 clk_2_N_FTB01 ( .A ( clk_2_S_in ) , + .X ( clk_2_N_out ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__bufbuf_16 clk_3_N_FTB01 ( .A ( clk_3_N_in ) , + .X ( clk_3_N_out ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_4 clk_3_S_FTB01 ( .A ( clk_3_N_in ) , + .X ( clk_3_S_out ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_8 FTB_17__16 ( .A ( chany_bottom_in[0] ) , .X ( chany_top_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_8 FTB_18__17 ( .A ( chany_bottom_in[1] ) , @@ -8829,7 +9464,7 @@ sky130_fd_sc_hd__buf_8 FTB_38__37 ( .A ( chany_bottom_in[21] ) , sky130_fd_sc_hd__buf_8 FTB_39__38 ( .A ( chany_bottom_in[22] ) , .X ( chany_top_out[22] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_6 FTB_40__39 ( .A ( chany_bottom_in[23] ) , - .X ( ropt_net_130 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .X ( chany_top_out[23] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_8 FTB_41__40 ( .A ( chany_bottom_in[24] ) , .X ( chany_top_out[24] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_8 FTB_42__41 ( .A ( chany_bottom_in[25] ) , @@ -8889,7 +9524,7 @@ sky130_fd_sc_hd__buf_8 FTB_68__67 ( .A ( chany_top_in[21] ) , sky130_fd_sc_hd__buf_8 FTB_69__68 ( .A ( chany_top_in[22] ) , .X ( chany_bottom_out[22] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_6 FTB_70__69 ( .A ( chany_top_in[23] ) , - .X ( ropt_net_129 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .X ( chany_bottom_out[23] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_8 FTB_71__70 ( .A ( chany_top_in[24] ) , .X ( chany_bottom_out[24] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_8 FTB_72__71 ( .A ( chany_top_in[25] ) , @@ -8902,52 +9537,22 @@ sky130_fd_sc_hd__buf_8 FTB_75__74 ( .A ( chany_top_in[28] ) , .X ( chany_bottom_out[28] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_8 FTB_76__75 ( .A ( chany_top_in[29] ) , .X ( chany_bottom_out[29] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_95 ( .A ( BUF_net_96 ) , .Y ( pReset_N_out ) , +sky130_fd_sc_hd__buf_6 BUFT_RR_89 ( .A ( net_net_89 ) , .X ( Test_en_N_out ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_96 ( .A ( pReset_S_in ) , .Y ( BUF_net_96 ) , +sky130_fd_sc_hd__inv_8 BINV_R_90 ( .A ( BUF_net_91 ) , .Y ( pReset_N_out ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_97 ( .A ( BUF_net_98 ) , .Y ( Reset_N_out ) , +sky130_fd_sc_hd__inv_1 BINV_R_91 ( .A ( pReset_S_in ) , .Y ( BUF_net_91 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_98 ( .A ( aps_rename_513_ ) , - .Y ( BUF_net_98 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_99 ( .A ( BUF_net_100 ) , .Y ( clk_3_N_out ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_100 ( .A ( aps_rename_520_ ) , - .Y ( BUF_net_100 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_110 ( .LO ( SYNOPSYS_UNCONNECTED_66 ) , - .HI ( optlc_net_107 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_114 ( .LO ( SYNOPSYS_UNCONNECTED_67 ) , - .HI ( optlc_net_108 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_116 ( .LO ( SYNOPSYS_UNCONNECTED_68 ) , - .HI ( optlc_net_109 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_118 ( .LO ( SYNOPSYS_UNCONNECTED_69 ) , - .HI ( optlc_net_110 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_119 ( .LO ( SYNOPSYS_UNCONNECTED_70 ) , - .HI ( optlc_net_111 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_6 ZBUF_4_f_inst_120 ( .A ( aps_rename_521_ ) , - .X ( clk_3_S_out ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_6 ZBUF_4_f_inst_121 ( .A ( aps_rename_517_ ) , - .X ( prog_clk_3_S_out ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_6 ZBUF_4_f_inst_122 ( .A ( aps_rename_519_ ) , - .X ( clk_2_N_out ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_6 ZBUF_4_f_inst_123 ( .A ( aps_rename_515_ ) , - .X ( prog_clk_2_N_out ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_6 ZBUF_4_f_inst_124 ( .A ( aps_rename_516_ ) , - .X ( prog_clk_3_N_out ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_6 ZBUF_4_f_inst_125 ( .A ( aps_rename_514_ ) , - .X ( prog_clk_2_S_out ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_6 ZBUF_4_f_inst_126 ( .A ( aps_rename_518_ ) , - .X ( clk_2_S_out ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_6 ropt_mt_inst_1377 ( .A ( ropt_net_128 ) , - .X ( left_grid_pin_27_[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_6 cts_buf_3651266 ( .A ( ctsbuf_net_1112 ) , +sky130_fd_sc_hd__conb_1 optlc_100 ( .LO ( SYNOPSYS_UNCONNECTED_66 ) , + .HI ( optlc_net_100 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_102 ( .LO ( SYNOPSYS_UNCONNECTED_67 ) , + .HI ( optlc_net_101 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_104 ( .LO ( SYNOPSYS_UNCONNECTED_68 ) , + .HI ( optlc_net_102 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 cts_buf_3651244 ( .A ( ctsbuf_net_1103 ) , .X ( prog_clk_0_S_out ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__clkbuf_8 cts_buf_3701271 ( .A ( ctsbuf_net_2113 ) , +sky130_fd_sc_hd__clkbuf_8 cts_buf_3701249 ( .A ( ctsbuf_net_2104 ) , .X ( prog_clk_0_N_out ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_8 ropt_mt_inst_1378 ( .A ( ropt_net_129 ) , - .X ( chany_bottom_out[23] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_8 ropt_mt_inst_1379 ( .A ( ropt_net_130 ) , - .X ( chany_top_out[23] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -8961,26 +9566,27 @@ output [0:0] mem_out ; input VDD ; input VSS ; +wire copt_net_73 ; supply1 VDD ; supply0 VSS ; sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( copt_net_73 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_6 FTB_2__1 ( .A ( copt_net_78 ) , .X ( ccff_tail[0] ) , +sky130_fd_sc_hd__buf_6 FTB_2__1 ( .A ( mem_out[0] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1224 ( .A ( copt_net_76 ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1223 ( .A ( copt_net_74 ) , + .X ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1224 ( .A ( copt_net_75 ) , .X ( copt_net_74 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1225 ( .A ( copt_net_74 ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1225 ( .A ( copt_net_76 ) , .X ( copt_net_75 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1226 ( .A ( mem_out[0] ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1226 ( .A ( copt_net_78 ) , .X ( copt_net_76 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1227 ( .A ( copt_net_79 ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1227 ( .A ( copt_net_73 ) , .X ( copt_net_77 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1228 ( .A ( copt_net_77 ) , .X ( copt_net_78 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1229 ( .A ( copt_net_75 ) , - .X ( copt_net_79 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -9096,7 +9702,7 @@ input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( copt_net_73 ) , +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( copt_net_72 ) , .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , @@ -9110,18 +9716,18 @@ sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_1 FTB_1__0 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1218 ( .A ( ccff_head[0] ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1217 ( .A ( ccff_head[0] ) , + .X ( copt_net_67 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1218 ( .A ( copt_net_69 ) , .X ( copt_net_68 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1219 ( .A ( copt_net_68 ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1219 ( .A ( copt_net_71 ) , .X ( copt_net_69 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1220 ( .A ( copt_net_69 ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1220 ( .A ( copt_net_67 ) , .X ( copt_net_70 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1221 ( .A ( copt_net_70 ) , .X ( copt_net_71 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1222 ( .A ( copt_net_71 ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1222 ( .A ( copt_net_68 ) , .X ( copt_net_72 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1223 ( .A ( copt_net_72 ) , - .X ( copt_net_73 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -9135,15 +9741,20 @@ input VDD ; input VSS ; input p0 ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -9156,15 +9767,20 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -9177,15 +9793,20 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -9198,15 +9819,20 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -9293,8 +9919,8 @@ wire [0:0] mux_2level_basis_input4_mem4_3_out ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_1_0_ ( - .A ( mux_2level_basis_input4_mem4_3_out[0] ) , .X ( net_net_66 ) , +sky130_fd_sc_hd__bufbuf_16 sky130_fd_sc_hd__buf_1_0_ ( + .A ( mux_2level_basis_input4_mem4_3_out[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; cby_0__1__local_encoder2to4_0 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , .data ( local_encoder2to4_0_data ) , @@ -9325,8 +9951,6 @@ cby_0__1__mux_2level_basis_input4_mem4 mux_l2_in_0_ ( .mem_inv ( local_encoder2to4_1_data_inv ) , .out ( mux_2level_basis_input4_mem4_3_out ) , .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_66 ( .A ( net_net_66 ) , .X ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -9357,30 +9981,27 @@ input prog_clk_0_E_in ; input VDD ; input VSS ; -wire ropt_net_149 ; -wire ropt_net_145 ; -wire ropt_net_129 ; -wire ropt_net_147 ; -wire ropt_net_152 ; -wire ropt_net_151 ; -wire ropt_net_142 ; -wire ropt_net_138 ; -wire ropt_net_133 ; -wire ropt_net_137 ; -wire ropt_net_130 ; -wire ropt_net_134 ; -wire ropt_net_140 ; -wire ropt_net_144 ; +wire ropt_net_122 ; wire ropt_net_135 ; -wire ropt_net_136 ; -wire ropt_net_139 ; -wire ropt_net_132 ; -wire ropt_net_150 ; -wire ropt_net_143 ; -wire ropt_net_131 ; -wire ropt_net_126 ; -wire ropt_net_127 ; wire ropt_net_128 ; +wire ropt_net_121 ; +wire ropt_net_139 ; +wire ropt_net_129 ; +wire ropt_net_134 ; +wire ropt_net_133 ; +wire ropt_net_132 ; +wire ropt_net_138 ; +wire ropt_net_123 ; +wire ropt_net_141 ; +wire ropt_net_126 ; +wire ropt_net_120 ; +wire ropt_net_125 ; +wire ropt_net_130 ; +wire ropt_net_131 ; +wire ropt_net_140 ; +wire ropt_net_137 ; +wire ropt_net_124 ; +wire ropt_net_127 ; wire [0:0] prog_clk ; wire prog_clk_0 ; wire [0:3] mux_2level_size12_0_sram ; @@ -9398,7 +10019,7 @@ cby_0__1__mux_2level_size12 mux_right_ipin_0 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 , SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) , .out ( left_grid_pin_0_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_67 ) ) ; + .p0 ( optlc_net_66 ) ) ; cby_0__1__mux_2level_size12_mem mem_right_ipin_0 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( { ccff_tail_mid } ) , @@ -9418,178 +10039,172 @@ sky130_fd_sc_hd__buf_1 prog_clk_0_FTB00 ( .A ( prog_clk_0_E_in ) , .X ( prog_clk[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_8 FTB_3__2 ( .A ( chany_bottom_in[0] ) , .X ( chany_top_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_6 FTB_4__3 ( .A ( chany_bottom_in[1] ) , - .X ( ropt_net_149 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_8 FTB_5__4 ( .A ( chany_bottom_in[2] ) , - .X ( chany_top_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_4__3 ( .A ( chany_bottom_in[1] ) , + .X ( chany_top_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 FTB_5__4 ( .A ( chany_bottom_in[2] ) , + .X ( ropt_net_122 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_8 FTB_6__5 ( .A ( chany_bottom_in[3] ) , .X ( chany_top_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_8 FTB_7__6 ( .A ( chany_bottom_in[4] ) , - .X ( chany_top_out[4] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_8 FTB_8__7 ( .A ( chany_bottom_in[5] ) , - .X ( chany_top_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 FTB_7__6 ( .A ( chany_bottom_in[4] ) , + .X ( ropt_net_135 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 FTB_8__7 ( .A ( chany_bottom_in[5] ) , + .X ( ropt_net_128 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_8 FTB_9__8 ( .A ( chany_bottom_in[6] ) , .X ( chany_top_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_8 FTB_10__9 ( .A ( chany_bottom_in[7] ) , +sky130_fd_sc_hd__buf_6 FTB_10__9 ( .A ( chany_bottom_in[7] ) , .X ( chany_top_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_6 FTB_11__10 ( .A ( chany_bottom_in[8] ) , - .X ( ropt_net_145 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_6 FTB_12__11 ( .A ( chany_bottom_in[9] ) , - .X ( ropt_net_129 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_11__10 ( .A ( chany_bottom_in[8] ) , + .X ( chany_top_out[8] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_12__11 ( .A ( chany_bottom_in[9] ) , + .X ( chany_top_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_8 FTB_13__12 ( .A ( chany_bottom_in[10] ) , .X ( chany_top_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_6 FTB_14__13 ( .A ( chany_bottom_in[11] ) , .X ( chany_top_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_8 FTB_15__14 ( .A ( chany_bottom_in[12] ) , .X ( chany_top_out[12] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_8 FTB_16__15 ( .A ( chany_bottom_in[13] ) , - .X ( chany_top_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 FTB_16__15 ( .A ( chany_bottom_in[13] ) , + .X ( ropt_net_121 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_8 FTB_17__16 ( .A ( chany_bottom_in[14] ) , .X ( chany_top_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_8 FTB_18__17 ( .A ( chany_bottom_in[15] ) , .X ( chany_top_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_8 FTB_19__18 ( .A ( chany_bottom_in[16] ) , +sky130_fd_sc_hd__buf_6 FTB_19__18 ( .A ( chany_bottom_in[16] ) , .X ( chany_top_out[16] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_6 FTB_20__19 ( .A ( chany_bottom_in[17] ) , - .X ( ropt_net_147 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .X ( ropt_net_139 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_8 FTB_21__20 ( .A ( chany_bottom_in[18] ) , .X ( chany_top_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_6 FTB_22__21 ( .A ( chany_bottom_in[19] ) , - .X ( ropt_net_152 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .X ( chany_top_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_6 FTB_23__22 ( .A ( chany_bottom_in[20] ) , - .X ( ropt_net_151 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .X ( chany_top_out[20] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_8 FTB_24__23 ( .A ( chany_bottom_in[21] ) , .X ( chany_top_out[21] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_6 FTB_25__24 ( .A ( chany_bottom_in[22] ) , - .X ( ropt_net_142 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_6 FTB_26__25 ( .A ( chany_bottom_in[23] ) , - .X ( ropt_net_138 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .X ( ropt_net_129 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_26__25 ( .A ( chany_bottom_in[23] ) , + .X ( chany_top_out[23] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_8 FTB_27__26 ( .A ( chany_bottom_in[24] ) , .X ( chany_top_out[24] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_6 FTB_28__27 ( .A ( chany_bottom_in[25] ) , - .X ( ropt_net_133 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .X ( ropt_net_134 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_6 FTB_29__28 ( .A ( chany_bottom_in[26] ) , - .X ( ropt_net_137 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .X ( ropt_net_133 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_8 FTB_30__29 ( .A ( chany_bottom_in[27] ) , .X ( chany_top_out[27] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_8 FTB_31__30 ( .A ( chany_bottom_in[28] ) , +sky130_fd_sc_hd__buf_6 FTB_31__30 ( .A ( chany_bottom_in[28] ) , .X ( chany_top_out[28] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_6 FTB_32__31 ( .A ( chany_bottom_in[29] ) , - .X ( ropt_net_130 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_32__31 ( .A ( chany_bottom_in[29] ) , + .X ( chany_top_out[29] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_8 FTB_33__32 ( .A ( chany_top_in[0] ) , .X ( chany_bottom_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_6 FTB_34__33 ( .A ( chany_top_in[1] ) , - .X ( ropt_net_134 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_34__33 ( .A ( chany_top_in[1] ) , + .X ( chany_bottom_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_6 FTB_35__34 ( .A ( chany_top_in[2] ) , - .X ( ropt_net_140 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .X ( ropt_net_132 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_8 FTB_36__35 ( .A ( chany_top_in[3] ) , .X ( chany_bottom_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_8 FTB_37__36 ( .A ( chany_top_in[4] ) , .X ( chany_bottom_out[4] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_8 FTB_38__37 ( .A ( chany_top_in[5] ) , - .X ( chany_bottom_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 FTB_38__37 ( .A ( chany_top_in[5] ) , + .X ( ropt_net_138 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_8 FTB_39__38 ( .A ( chany_top_in[6] ) , .X ( chany_bottom_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_6 FTB_40__39 ( .A ( chany_top_in[7] ) , - .X ( ropt_net_144 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_8 FTB_41__40 ( .A ( chany_top_in[8] ) , + .X ( ropt_net_123 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 FTB_41__40 ( .A ( chany_top_in[8] ) , .X ( chany_bottom_out[8] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_8 FTB_42__41 ( .A ( chany_top_in[9] ) , - .X ( chany_bottom_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 FTB_42__41 ( .A ( chany_top_in[9] ) , + .X ( ropt_net_141 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_6 FTB_43__42 ( .A ( chany_top_in[10] ) , - .X ( ropt_net_135 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .X ( ropt_net_126 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_8 FTB_44__43 ( .A ( chany_top_in[11] ) , .X ( chany_bottom_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_8 FTB_45__44 ( .A ( chany_top_in[12] ) , .X ( chany_bottom_out[12] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_6 FTB_46__45 ( .A ( chany_top_in[13] ) , - .X ( ropt_net_136 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .X ( ropt_net_120 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_6 FTB_47__46 ( .A ( chany_top_in[14] ) , - .X ( ropt_net_139 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_8 FTB_48__47 ( .A ( chany_top_in[15] ) , - .X ( chany_bottom_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .X ( ropt_net_125 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 FTB_48__47 ( .A ( chany_top_in[15] ) , + .X ( ropt_net_130 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_6 FTB_49__48 ( .A ( chany_top_in[16] ) , - .X ( chany_bottom_out[16] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .X ( ropt_net_131 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_8 FTB_50__49 ( .A ( chany_top_in[17] ) , .X ( chany_bottom_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_8 FTB_51__50 ( .A ( chany_top_in[18] ) , .X ( chany_bottom_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_6 FTB_52__51 ( .A ( chany_top_in[19] ) , - .X ( ropt_net_132 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_52__51 ( .A ( chany_top_in[19] ) , + .X ( chany_bottom_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_6 FTB_53__52 ( .A ( chany_top_in[20] ) , - .X ( ropt_net_150 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .X ( ropt_net_140 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_8 FTB_54__53 ( .A ( chany_top_in[21] ) , .X ( chany_bottom_out[21] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_6 FTB_55__54 ( .A ( chany_top_in[22] ) , - .X ( ropt_net_143 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_8 FTB_56__55 ( .A ( chany_top_in[23] ) , - .X ( chany_bottom_out[23] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .X ( ropt_net_137 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 FTB_56__55 ( .A ( chany_top_in[23] ) , + .X ( ropt_net_124 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_8 FTB_57__56 ( .A ( chany_top_in[24] ) , .X ( chany_bottom_out[24] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_6 FTB_58__57 ( .A ( chany_top_in[25] ) , - .X ( ropt_net_131 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_6 FTB_59__58 ( .A ( chany_top_in[26] ) , - .X ( ropt_net_126 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_6 FTB_60__59 ( .A ( chany_top_in[27] ) , .X ( ropt_net_127 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_59__58 ( .A ( chany_top_in[26] ) , + .X ( chany_bottom_out[26] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_60__59 ( .A ( chany_top_in[27] ) , + .X ( chany_bottom_out[27] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_8 FTB_61__60 ( .A ( chany_top_in[28] ) , .X ( chany_bottom_out[28] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_6 FTB_62__61 ( .A ( chany_top_in[29] ) , - .X ( ropt_net_128 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_62__61 ( .A ( chany_top_in[29] ) , + .X ( chany_bottom_out[29] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_6 FTB_63__62 ( .A ( right_width_0_height_0__pin_1_lower[0] ) , .X ( right_width_0_height_0__pin_1_upper[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_68 ( .LO ( SYNOPSYS_UNCONNECTED_5 ) , - .HI ( optlc_net_67 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_8 ropt_mt_inst_1276 ( .A ( ropt_net_126 ) , - .X ( chany_bottom_out[26] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_8 ropt_mt_inst_1277 ( .A ( ropt_net_127 ) , - .X ( chany_bottom_out[27] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_8 ropt_mt_inst_1278 ( .A ( ropt_net_128 ) , - .X ( chany_bottom_out[29] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_8 ropt_mt_inst_1279 ( .A ( ropt_net_129 ) , - .X ( chany_top_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_8 ropt_mt_inst_1280 ( .A ( ropt_net_130 ) , - .X ( chany_top_out[29] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_8 ropt_mt_inst_1281 ( .A ( ropt_net_131 ) , - .X ( chany_bottom_out[25] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_8 ropt_mt_inst_1282 ( .A ( ropt_net_132 ) , - .X ( chany_bottom_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_8 ropt_mt_inst_1283 ( .A ( ropt_net_133 ) , - .X ( chany_top_out[25] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_8 ropt_mt_inst_1284 ( .A ( ropt_net_134 ) , - .X ( chany_bottom_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_8 ropt_mt_inst_1285 ( .A ( ropt_net_135 ) , - .X ( chany_bottom_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_8 ropt_mt_inst_1286 ( .A ( ropt_net_136 ) , +sky130_fd_sc_hd__conb_1 optlc_67 ( .LO ( SYNOPSYS_UNCONNECTED_5 ) , + .HI ( optlc_net_66 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1270 ( .A ( ropt_net_120 ) , .X ( chany_bottom_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_8 ropt_mt_inst_1287 ( .A ( ropt_net_137 ) , - .X ( chany_top_out[26] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_8 ropt_mt_inst_1288 ( .A ( ropt_net_138 ) , - .X ( chany_top_out[23] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_8 ropt_mt_inst_1289 ( .A ( ropt_net_139 ) , - .X ( chany_bottom_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_8 ropt_mt_inst_1290 ( .A ( ropt_net_140 ) , - .X ( chany_bottom_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_8 ropt_mt_inst_1292 ( .A ( ropt_net_142 ) , - .X ( chany_top_out[22] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_8 ropt_mt_inst_1293 ( .A ( ropt_net_143 ) , - .X ( chany_bottom_out[22] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_8 ropt_mt_inst_1294 ( .A ( ropt_net_144 ) , +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1271 ( .A ( ropt_net_121 ) , + .X ( chany_top_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1272 ( .A ( ropt_net_122 ) , + .X ( chany_top_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1273 ( .A ( ropt_net_123 ) , .X ( chany_bottom_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_8 ropt_mt_inst_1295 ( .A ( ropt_net_145 ) , - .X ( chany_top_out[8] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_8 ropt_mt_inst_1297 ( .A ( ropt_net_147 ) , +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1274 ( .A ( ropt_net_124 ) , + .X ( chany_bottom_out[23] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1275 ( .A ( ropt_net_125 ) , + .X ( chany_bottom_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1276 ( .A ( ropt_net_126 ) , + .X ( chany_bottom_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1277 ( .A ( ropt_net_127 ) , + .X ( chany_bottom_out[25] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1278 ( .A ( ropt_net_128 ) , + .X ( chany_top_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1279 ( .A ( ropt_net_129 ) , + .X ( chany_top_out[22] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1280 ( .A ( ropt_net_130 ) , + .X ( chany_bottom_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1281 ( .A ( ropt_net_131 ) , + .X ( chany_bottom_out[16] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1282 ( .A ( ropt_net_132 ) , + .X ( chany_bottom_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1283 ( .A ( ropt_net_133 ) , + .X ( chany_top_out[26] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1284 ( .A ( ropt_net_134 ) , + .X ( chany_top_out[25] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1285 ( .A ( ropt_net_135 ) , + .X ( chany_top_out[4] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1287 ( .A ( ropt_net_137 ) , + .X ( chany_bottom_out[22] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1288 ( .A ( ropt_net_138 ) , + .X ( chany_bottom_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1289 ( .A ( ropt_net_139 ) , .X ( chany_top_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_8 ropt_mt_inst_1299 ( .A ( ropt_net_149 ) , - .X ( chany_top_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_8 ropt_mt_inst_1300 ( .A ( ropt_net_150 ) , +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1290 ( .A ( ropt_net_140 ) , .X ( chany_bottom_out[20] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_8 ropt_mt_inst_1301 ( .A ( ropt_net_151 ) , - .X ( chany_top_out[20] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_8 ropt_mt_inst_1302 ( .A ( ropt_net_152 ) , - .X ( chany_top_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1291 ( .A ( ropt_net_141 ) , + .X ( chany_bottom_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -9603,21 +10218,14 @@ output [0:0] mem_out ; input VDD ; input VSS ; -wire copt_net_138 ; supply1 VDD ; supply0 VSS ; sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( copt_net_138 ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_6 FTB_18__17 ( .A ( mem_out[0] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1374 ( .A ( copt_net_138 ) , - .X ( copt_net_137 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1376 ( .A ( copt_net_140 ) , - .X ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1377 ( .A ( copt_net_137 ) , - .X ( copt_net_140 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -9637,19 +10245,19 @@ supply1 VDD ; supply0 VSS ; sky130_fd_sc_hd__nand2b_1 ISOL_EN_GATE ( .A_N ( FPGA_DIR ) , - .B ( IO_ISOL_N ) , .Y ( aps_rename_516_ ) , .VPWR ( VDD ) , + .B ( IO_ISOL_N ) , .Y ( aps_rename_515_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 INV_SOC_DIR ( .A ( BUF_net_81 ) , .Y ( SOC_DIR_N ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 INV_SOC_DIR ( .A ( aps_rename_515_ ) , + .Y ( SOC_DIR_N ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__ebufn_4 IN_PROTECT_GATE ( .A ( SOC_IN ) , .TE_B ( SOC_DIR_N ) , .Z ( FPGA_IN ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__ebufn_4 OUT_PROTECT_GATE ( .A ( FPGA_OUT ) , - .TE_B ( BUF_net_81 ) , .Z ( SOC_OUT ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_4 BINV_R_81 ( .A ( BUF_net_83 ) , .Y ( BUF_net_81 ) , + .TE_B ( BUF_net_82 ) , .Z ( SOC_OUT ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_81 ( .A ( BUF_net_83 ) , .Y ( SOC_DIR ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_82 ( .A ( BUF_net_83 ) , .Y ( SOC_DIR ) , +sky130_fd_sc_hd__inv_4 BINV_R_82 ( .A ( BUF_net_83 ) , .Y ( BUF_net_82 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_83 ( .A ( aps_rename_516_ ) , +sky130_fd_sc_hd__inv_1 BINV_R_83 ( .A ( aps_rename_515_ ) , .Y ( BUF_net_83 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -9969,12 +10577,15 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -9988,15 +10599,20 @@ input VDD ; input VSS ; input p0 ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -10009,15 +10625,20 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -10030,15 +10651,20 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -10126,7 +10752,7 @@ supply1 VDD ; supply0 VSS ; sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_1_0_ ( - .A ( mux_2level_basis_input4_mem4_2_out[0] ) , .X ( out[0] ) , + .A ( mux_2level_basis_input4_mem4_2_out[0] ) , .X ( aps_rename_514_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; cbx_1__2__local_encoder2to4_32 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , .data ( local_encoder2to4_0_data ) , @@ -10157,6 +10783,10 @@ cbx_1__2__mux_2level_basis_input2_mem2 mux_l1_in_2_ ( .in ( in[8:9] ) , .mem_inv ( local_encoder2to4_0_data_inv[0:1] ) , .out ( mux_2level_basis_input2_mem2_0_out ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_95 ( .A ( aps_rename_514_ ) , + .Y ( BUF_net_95 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_101 ( .A ( BUF_net_95 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -10169,12 +10799,15 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -10188,15 +10821,20 @@ input VDD ; input VSS ; input p0 ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -10209,15 +10847,20 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -10230,15 +10873,20 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -10326,7 +10974,7 @@ supply1 VDD ; supply0 VSS ; sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_1_0_ ( - .A ( mux_2level_basis_input4_mem4_2_out[0] ) , .X ( aps_rename_515_ ) , + .A ( mux_2level_basis_input4_mem4_2_out[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; cbx_1__2__local_encoder2to4_30 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , .data ( local_encoder2to4_0_data ) , @@ -10357,10 +11005,6 @@ cbx_1__2__mux_2level_basis_input2_mem2_6 mux_l1_in_2_ ( .in ( in[8:9] ) , .mem_inv ( local_encoder2to4_0_data_inv[0:1] ) , .out ( mux_2level_basis_input2_mem2_0_out ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sky130_fd_sc_hd__inv_2 BINV_R_106 ( .A ( aps_rename_515_ ) , - .Y ( BUF_net_106 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_6 BINV_R_115 ( .A ( BUF_net_106 ) , .Y ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -10373,12 +11017,15 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -10392,15 +11039,20 @@ input VDD ; input VSS ; input p0 ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -10413,15 +11065,20 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -10434,15 +11091,20 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -10530,7 +11192,7 @@ supply1 VDD ; supply0 VSS ; sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_1_0_ ( - .A ( mux_2level_basis_input4_mem4_2_out[0] ) , .X ( aps_rename_514_ ) , + .A ( mux_2level_basis_input4_mem4_2_out[0] ) , .X ( aps_rename_513_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; cbx_1__2__local_encoder2to4_28 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , .data ( local_encoder2to4_0_data ) , @@ -10561,10 +11223,10 @@ cbx_1__2__mux_2level_basis_input2_mem2_5 mux_l1_in_2_ ( .in ( in[8:9] ) , .mem_inv ( local_encoder2to4_0_data_inv[0:1] ) , .out ( mux_2level_basis_input2_mem2_0_out ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_103 ( .A ( BUF_net_104 ) , .Y ( out[0] ) , +sky130_fd_sc_hd__inv_6 BINV_R_92 ( .A ( BUF_net_93 ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_4 BINV_R_104 ( .A ( aps_rename_514_ ) , - .Y ( BUF_net_104 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_93 ( .A ( aps_rename_513_ ) , + .Y ( BUF_net_93 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -10577,12 +11239,15 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -10596,15 +11261,20 @@ input VDD ; input VSS ; input p0 ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -10617,15 +11287,20 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -10638,15 +11313,20 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -10734,7 +11414,7 @@ supply1 VDD ; supply0 VSS ; sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_1_0_ ( - .A ( mux_2level_basis_input4_mem4_2_out[0] ) , .X ( aps_rename_513_ ) , + .A ( mux_2level_basis_input4_mem4_2_out[0] ) , .X ( aps_rename_512_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; cbx_1__2__local_encoder2to4_26 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , .data ( local_encoder2to4_0_data ) , @@ -10765,10 +11445,10 @@ cbx_1__2__mux_2level_basis_input2_mem2_4 mux_l1_in_2_ ( .in ( in[8:9] ) , .mem_inv ( local_encoder2to4_0_data_inv[0:1] ) , .out ( mux_2level_basis_input2_mem2_0_out ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sky130_fd_sc_hd__inv_2 BINV_R_102 ( .A ( aps_rename_513_ ) , - .Y ( BUF_net_102 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_6 BINV_R_119 ( .A ( BUF_net_102 ) , .Y ( out[0] ) , +sky130_fd_sc_hd__inv_6 BINV_R_109 ( .A ( BUF_net_110 ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_4 BINV_R_110 ( .A ( aps_rename_512_ ) , + .Y ( BUF_net_110 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -10781,12 +11461,15 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -10800,15 +11483,20 @@ input VDD ; input VSS ; input p0 ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -10821,15 +11509,20 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -10842,15 +11535,20 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -10981,12 +11679,15 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -11000,15 +11701,20 @@ input VDD ; input VSS ; input p0 ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -11021,15 +11727,20 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -11042,15 +11753,20 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -11138,7 +11854,7 @@ supply1 VDD ; supply0 VSS ; sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_1_0_ ( - .A ( mux_2level_basis_input4_mem4_2_out[0] ) , .X ( aps_rename_512_ ) , + .A ( mux_2level_basis_input4_mem4_2_out[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; cbx_1__2__local_encoder2to4_22 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , .data ( local_encoder2to4_0_data ) , @@ -11169,10 +11885,6 @@ cbx_1__2__mux_2level_basis_input2_mem2_2 mux_l1_in_2_ ( .in ( in[8:9] ) , .mem_inv ( local_encoder2to4_0_data_inv[0:1] ) , .out ( mux_2level_basis_input2_mem2_0_out ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sky130_fd_sc_hd__inv_4 BINV_R_123 ( .A ( BUF_net_124 ) , .Y ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_4 BINV_R_124 ( .A ( aps_rename_512_ ) , - .Y ( BUF_net_124 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -11185,12 +11897,15 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -11204,15 +11919,20 @@ input VDD ; input VSS ; input p0 ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -11225,15 +11945,20 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -11246,15 +11971,20 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -11385,12 +12115,15 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -11404,15 +12137,20 @@ input VDD ; input VSS ; input p0 ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -11425,15 +12163,20 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -11446,15 +12189,20 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -11573,9 +12321,9 @@ cbx_1__2__mux_2level_basis_input2_mem2_0 mux_l1_in_2_ ( .in ( in[8:9] ) , .mem_inv ( local_encoder2to4_0_data_inv[0:1] ) , .out ( mux_2level_basis_input2_mem2_0_out ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sky130_fd_sc_hd__inv_2 BINV_R_98 ( .A ( aps_rename_511_ ) , - .Y ( BUF_net_98 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_4 BINV_R_117 ( .A ( BUF_net_98 ) , .Y ( out[0] ) , +sky130_fd_sc_hd__inv_2 BINV_R_91 ( .A ( aps_rename_511_ ) , + .Y ( BUF_net_91 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_4 BINV_R_98 ( .A ( BUF_net_91 ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -11833,7 +12581,7 @@ input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ropt_net_146 ) , +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( copt_net_122 ) , .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , @@ -11847,26 +12595,8 @@ sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_1 FTB_1__0 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1367 ( .A ( copt_net_133 ) , - .X ( copt_net_130 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1368 ( .A ( ropt_net_147 ) , - .X ( copt_net_131 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1369 ( .A ( copt_net_130 ) , - .X ( copt_net_132 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1370 ( .A ( ccff_head[0] ) , - .X ( copt_net_133 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1371 ( .A ( copt_net_131 ) , - .X ( copt_net_134 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_1 copt_h_inst_1372 ( .A ( copt_net_132 ) , - .X ( copt_net_135 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1379 ( .A ( ropt_net_145 ) , - .X ( ropt_net_144 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1380 ( .A ( copt_net_134 ) , - .X ( ropt_net_145 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_4 ropt_h_inst_1381 ( .A ( ropt_net_144 ) , - .X ( ropt_net_146 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1382 ( .A ( copt_net_135 ) , - .X ( ropt_net_147 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 copt_h_inst_1359 ( .A ( ccff_head[0] ) , + .X ( copt_net_122 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -11880,15 +12610,20 @@ input VDD ; input VSS ; input p0 ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -11901,15 +12636,20 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -11922,15 +12662,20 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -11943,15 +12688,20 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -12039,7 +12789,7 @@ supply1 VDD ; supply0 VSS ; sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_1_0_ ( - .A ( mux_2level_basis_input4_mem4_3_out[0] ) , .X ( aps_rename_510_ ) , + .A ( mux_2level_basis_input4_mem4_3_out[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; cbx_1__2__local_encoder2to4_16 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , .data ( local_encoder2to4_0_data ) , @@ -12070,10 +12820,6 @@ cbx_1__2__mux_2level_basis_input4_mem4_35 mux_l2_in_0_ ( .mem_inv ( local_encoder2to4_1_data_inv ) , .out ( mux_2level_basis_input4_mem4_3_out ) , .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_95 ( .A ( BUF_net_96 ) , .Y ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_96 ( .A ( aps_rename_510_ ) , - .Y ( BUF_net_96 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -12087,15 +12833,20 @@ input VDD ; input VSS ; input p0 ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -12108,15 +12859,20 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -12129,15 +12885,20 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -12150,15 +12911,20 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -12246,7 +13012,7 @@ supply1 VDD ; supply0 VSS ; sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_1_0_ ( - .A ( mux_2level_basis_input4_mem4_3_out[0] ) , .X ( net_net_94 ) , + .A ( mux_2level_basis_input4_mem4_3_out[0] ) , .X ( aps_rename_510_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; cbx_1__2__local_encoder2to4_14 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , .data ( local_encoder2to4_0_data ) , @@ -12277,7 +13043,9 @@ cbx_1__2__mux_2level_basis_input4_mem4_31 mux_l2_in_0_ ( .mem_inv ( local_encoder2to4_1_data_inv ) , .out ( mux_2level_basis_input4_mem4_3_out ) , .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_94 ( .A ( net_net_94 ) , .X ( out[0] ) , +sky130_fd_sc_hd__inv_1 BINV_R_89 ( .A ( aps_rename_510_ ) , + .Y ( BUF_net_89 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_4 BINV_R_113 ( .A ( BUF_net_89 ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -12292,15 +13060,20 @@ input VDD ; input VSS ; input p0 ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -12313,15 +13086,20 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -12334,15 +13112,20 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -12355,15 +13138,20 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -12482,9 +13270,9 @@ cbx_1__2__mux_2level_basis_input4_mem4_27 mux_l2_in_0_ ( .mem_inv ( local_encoder2to4_1_data_inv ) , .out ( mux_2level_basis_input4_mem4_3_out ) , .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_2 BINV_R_93 ( .A ( aps_rename_509_ ) , - .Y ( BUF_net_93 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_6 BINV_R_111 ( .A ( BUF_net_93 ) , .Y ( out[0] ) , +sky130_fd_sc_hd__inv_2 BINV_R_87 ( .A ( aps_rename_509_ ) , + .Y ( BUF_net_87 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_4 BINV_R_111 ( .A ( BUF_net_87 ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -12499,15 +13287,20 @@ input VDD ; input VSS ; input p0 ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -12520,15 +13313,20 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -12541,15 +13339,20 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -12562,15 +13365,20 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -12689,10 +13497,10 @@ cbx_1__2__mux_2level_basis_input4_mem4_23 mux_l2_in_0_ ( .mem_inv ( local_encoder2to4_1_data_inv ) , .out ( mux_2level_basis_input4_mem4_3_out ) , .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_2 BINV_R_91 ( .A ( aps_rename_508_ ) , - .Y ( BUF_net_91 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_4 BINV_R_109 ( .A ( BUF_net_91 ) , .Y ( out[0] ) , +sky130_fd_sc_hd__inv_6 BINV_R_107 ( .A ( BUF_net_108 ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_4 BINV_R_108 ( .A ( aps_rename_508_ ) , + .Y ( BUF_net_108 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -12706,15 +13514,20 @@ input VDD ; input VSS ; input p0 ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -12727,15 +13540,20 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -12748,15 +13566,20 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -12769,15 +13592,20 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -12896,10 +13724,10 @@ cbx_1__2__mux_2level_basis_input4_mem4_19 mux_l2_in_0_ ( .mem_inv ( local_encoder2to4_1_data_inv ) , .out ( mux_2level_basis_input4_mem4_3_out ) , .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_4 BINV_R_121 ( .A ( BUF_net_122 ) , .Y ( out[0] ) , +sky130_fd_sc_hd__inv_2 BINV_R_85 ( .A ( aps_rename_507_ ) , + .Y ( BUF_net_85 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_4 BINV_R_96 ( .A ( BUF_net_85 ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_4 BINV_R_122 ( .A ( aps_rename_507_ ) , - .Y ( BUF_net_122 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -12913,15 +13741,20 @@ input VDD ; input VSS ; input p0 ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -12934,15 +13767,20 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -12955,15 +13793,20 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -12976,15 +13819,20 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -13116,15 +13964,20 @@ input VDD ; input VSS ; input p0 ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -13137,15 +13990,20 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -13158,15 +14016,20 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -13179,15 +14042,20 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -13306,10 +14174,10 @@ cbx_1__2__mux_2level_basis_input4_mem4_11 mux_l2_in_0_ ( .mem_inv ( local_encoder2to4_1_data_inv ) , .out ( mux_2level_basis_input4_mem4_3_out ) , .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_86 ( .A ( BUF_net_87 ) , .Y ( out[0] ) , +sky130_fd_sc_hd__inv_6 BINV_R_105 ( .A ( BUF_net_106 ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_87 ( .A ( aps_rename_506_ ) , - .Y ( BUF_net_87 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_4 BINV_R_106 ( .A ( aps_rename_506_ ) , + .Y ( BUF_net_106 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -13323,15 +14191,20 @@ input VDD ; input VSS ; input p0 ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -13344,15 +14217,20 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -13365,15 +14243,20 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -13386,15 +14269,20 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -13482,7 +14370,7 @@ supply1 VDD ; supply0 VSS ; sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_1_0_ ( - .A ( mux_2level_basis_input4_mem4_3_out[0] ) , .X ( out[0] ) , + .A ( mux_2level_basis_input4_mem4_3_out[0] ) , .X ( aps_rename_505_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; cbx_1__2__local_encoder2to4_2 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , .data ( local_encoder2to4_0_data ) , @@ -13513,6 +14401,10 @@ cbx_1__2__mux_2level_basis_input4_mem4_7 mux_l2_in_0_ ( .mem_inv ( local_encoder2to4_1_data_inv ) , .out ( mux_2level_basis_input4_mem4_3_out ) , .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) ) ; +sky130_fd_sc_hd__inv_12 BINV_R_103 ( .A ( BUF_net_104 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_4 BINV_R_104 ( .A ( aps_rename_505_ ) , + .Y ( BUF_net_104 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -13526,15 +14418,20 @@ input VDD ; input VSS ; input p0 ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -13547,15 +14444,20 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -13568,15 +14470,20 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -13589,15 +14496,20 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -13685,7 +14597,7 @@ supply1 VDD ; supply0 VSS ; sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_1_0_ ( - .A ( mux_2level_basis_input4_mem4_3_out[0] ) , .X ( aps_rename_505_ ) , + .A ( mux_2level_basis_input4_mem4_3_out[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; cbx_1__2__local_encoder2to4_0 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , .data ( local_encoder2to4_0_data ) , @@ -13716,10 +14628,6 @@ cbx_1__2__mux_2level_basis_input4_mem4_3 mux_l2_in_0_ ( .mem_inv ( local_encoder2to4_1_data_inv ) , .out ( mux_2level_basis_input4_mem4_3_out ) , .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_84 ( .A ( BUF_net_85 ) , .Y ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_85 ( .A ( aps_rename_505_ ) , - .Y ( BUF_net_85 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -13832,7 +14740,7 @@ cbx_1__2__mux_2level_size12_0 mux_bottom_ipin_0 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 , SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) , .out ( top_grid_pin_0_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_126 ) ) ; + .p0 ( optlc_net_120 ) ) ; cbx_1__2__mux_2level_size12_1 mux_top_ipin_0 ( .in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[4] , chanx_left_out[4] , chanx_right_out[7] , chanx_left_out[7] , @@ -13842,7 +14750,7 @@ cbx_1__2__mux_2level_size12_1 mux_top_ipin_0 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 , SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 } ) , .out ( bottom_grid_pin_0_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_127 ) ) ; + .p0 ( optlc_net_119 ) ) ; cbx_1__2__mux_2level_size12_2 mux_top_ipin_2 ( .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[3] , chanx_left_out[3] , chanx_right_out[9] , chanx_left_out[9] , @@ -13852,7 +14760,7 @@ cbx_1__2__mux_2level_size12_2 mux_top_ipin_2 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_9 , SYNOPSYS_UNCONNECTED_10 , SYNOPSYS_UNCONNECTED_11 , SYNOPSYS_UNCONNECTED_12 } ) , .out ( bottom_grid_pin_2_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_126 ) ) ; + .p0 ( optlc_net_118 ) ) ; cbx_1__2__mux_2level_size12_3 mux_top_ipin_4 ( .in ( { chanx_right_out[2] , chanx_left_out[2] , chanx_right_out[5] , chanx_left_out[5] , chanx_right_out[11] , chanx_left_out[11] , @@ -13862,7 +14770,7 @@ cbx_1__2__mux_2level_size12_3 mux_top_ipin_4 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 , SYNOPSYS_UNCONNECTED_15 , SYNOPSYS_UNCONNECTED_16 } ) , .out ( bottom_grid_pin_4_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_125 ) ) ; + .p0 ( optlc_net_116 ) ) ; cbx_1__2__mux_2level_size12_4 mux_top_ipin_6 ( .in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[4] , chanx_left_out[4] , chanx_right_out[7] , chanx_left_out[7] , @@ -13872,7 +14780,7 @@ cbx_1__2__mux_2level_size12_4 mux_top_ipin_6 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_17 , SYNOPSYS_UNCONNECTED_18 , SYNOPSYS_UNCONNECTED_19 , SYNOPSYS_UNCONNECTED_20 } ) , .out ( bottom_grid_pin_6_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_128 ) ) ; + .p0 ( optlc_net_119 ) ) ; cbx_1__2__mux_2level_size12_5 mux_top_ipin_8 ( .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[3] , chanx_left_out[3] , chanx_right_out[9] , chanx_left_out[9] , @@ -13881,8 +14789,8 @@ cbx_1__2__mux_2level_size12_5 mux_top_ipin_8 ( .sram ( mux_2level_size12_5_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_21 , SYNOPSYS_UNCONNECTED_22 , SYNOPSYS_UNCONNECTED_23 , SYNOPSYS_UNCONNECTED_24 } ) , - .out ( { ropt_net_150 } ) , - .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_126 ) ) ; + .out ( bottom_grid_pin_8_ ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_117 ) ) ; cbx_1__2__mux_2level_size12_6 mux_top_ipin_10 ( .in ( { chanx_right_out[2] , chanx_left_out[2] , chanx_right_out[5] , chanx_left_out[5] , chanx_right_out[11] , chanx_left_out[11] , @@ -13892,7 +14800,7 @@ cbx_1__2__mux_2level_size12_6 mux_top_ipin_10 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_25 , SYNOPSYS_UNCONNECTED_26 , SYNOPSYS_UNCONNECTED_27 , SYNOPSYS_UNCONNECTED_28 } ) , .out ( bottom_grid_pin_10_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_125 ) ) ; + .p0 ( optlc_net_116 ) ) ; cbx_1__2__mux_2level_size12_7 mux_top_ipin_12 ( .in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[4] , chanx_left_out[4] , chanx_right_out[7] , chanx_left_out[7] , @@ -13902,7 +14810,7 @@ cbx_1__2__mux_2level_size12_7 mux_top_ipin_12 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_29 , SYNOPSYS_UNCONNECTED_30 , SYNOPSYS_UNCONNECTED_31 , SYNOPSYS_UNCONNECTED_32 } ) , .out ( bottom_grid_pin_12_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_127 ) ) ; + .p0 ( optlc_net_120 ) ) ; cbx_1__2__mux_2level_size12 mux_top_ipin_14 ( .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[3] , chanx_left_out[3] , chanx_right_out[9] , chanx_left_out[9] , @@ -13911,8 +14819,8 @@ cbx_1__2__mux_2level_size12 mux_top_ipin_14 ( .sram ( mux_2level_size12_8_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_33 , SYNOPSYS_UNCONNECTED_34 , SYNOPSYS_UNCONNECTED_35 , SYNOPSYS_UNCONNECTED_36 } ) , - .out ( bottom_grid_pin_14_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_126 ) ) ; + .out ( { ropt_net_123 } ) , + .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_118 ) ) ; cbx_1__2__mux_2level_size12_mem_0 mem_bottom_ipin_0 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( mux_2level_size12_mem_0_ccff_tail ) , @@ -13965,8 +14873,8 @@ cbx_1__2__mux_2level_size10_0 mux_top_ipin_1 ( .sram ( mux_2level_size10_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_37 , SYNOPSYS_UNCONNECTED_38 , SYNOPSYS_UNCONNECTED_39 , SYNOPSYS_UNCONNECTED_40 } ) , - .out ( { ropt_net_149 } ) , - .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_127 ) ) ; + .out ( bottom_grid_pin_1_ ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_119 ) ) ; cbx_1__2__mux_2level_size10_1 mux_top_ipin_3 ( .in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[4] , chanx_left_out[4] , chanx_right_out[10] , chanx_left_out[10] , @@ -13976,7 +14884,7 @@ cbx_1__2__mux_2level_size10_1 mux_top_ipin_3 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_41 , SYNOPSYS_UNCONNECTED_42 , SYNOPSYS_UNCONNECTED_43 , SYNOPSYS_UNCONNECTED_44 } ) , .out ( bottom_grid_pin_3_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_125 ) ) ; + .p0 ( optlc_net_120 ) ) ; cbx_1__2__mux_2level_size10_2 mux_top_ipin_5 ( .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[3] , chanx_left_out[3] , chanx_right_out[6] , chanx_left_out[6] , @@ -13986,7 +14894,7 @@ cbx_1__2__mux_2level_size10_2 mux_top_ipin_5 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_45 , SYNOPSYS_UNCONNECTED_46 , SYNOPSYS_UNCONNECTED_47 , SYNOPSYS_UNCONNECTED_48 } ) , .out ( bottom_grid_pin_5_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_128 ) ) ; + .p0 ( optlc_net_120 ) ) ; cbx_1__2__mux_2level_size10_3 mux_top_ipin_7 ( .in ( { chanx_right_out[2] , chanx_left_out[2] , chanx_right_out[5] , chanx_left_out[5] , chanx_right_out[8] , chanx_left_out[8] , @@ -13996,7 +14904,7 @@ cbx_1__2__mux_2level_size10_3 mux_top_ipin_7 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_49 , SYNOPSYS_UNCONNECTED_50 , SYNOPSYS_UNCONNECTED_51 , SYNOPSYS_UNCONNECTED_52 } ) , .out ( bottom_grid_pin_7_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_127 ) ) ; + .p0 ( optlc_net_116 ) ) ; cbx_1__2__mux_2level_size10_4 mux_top_ipin_9 ( .in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[4] , chanx_left_out[4] , chanx_right_out[10] , chanx_left_out[10] , @@ -14006,7 +14914,7 @@ cbx_1__2__mux_2level_size10_4 mux_top_ipin_9 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_53 , SYNOPSYS_UNCONNECTED_54 , SYNOPSYS_UNCONNECTED_55 , SYNOPSYS_UNCONNECTED_56 } ) , .out ( bottom_grid_pin_9_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_125 ) ) ; + .p0 ( optlc_net_120 ) ) ; cbx_1__2__mux_2level_size10_5 mux_top_ipin_11 ( .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[3] , chanx_left_out[3] , chanx_right_out[12] , chanx_left_out[12] , @@ -14015,8 +14923,8 @@ cbx_1__2__mux_2level_size10_5 mux_top_ipin_11 ( .sram ( mux_2level_size10_5_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_57 , SYNOPSYS_UNCONNECTED_58 , SYNOPSYS_UNCONNECTED_59 , SYNOPSYS_UNCONNECTED_60 } ) , - .out ( { ropt_net_148 } ) , - .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_126 ) ) ; + .out ( bottom_grid_pin_11_ ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_117 ) ) ; cbx_1__2__mux_2level_size10_6 mux_top_ipin_13 ( .in ( { chanx_right_out[2] , chanx_left_out[2] , chanx_right_out[5] , chanx_left_out[5] , chanx_right_out[14] , chanx_left_out[14] , @@ -14026,7 +14934,7 @@ cbx_1__2__mux_2level_size10_6 mux_top_ipin_13 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_61 , SYNOPSYS_UNCONNECTED_62 , SYNOPSYS_UNCONNECTED_63 , SYNOPSYS_UNCONNECTED_64 } ) , .out ( bottom_grid_pin_13_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_127 ) ) ; + .p0 ( optlc_net_119 ) ) ; cbx_1__2__mux_2level_size10 mux_top_ipin_15 ( .in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[4] , chanx_left_out[4] , chanx_right_out[7] , chanx_left_out[7] , @@ -14036,7 +14944,7 @@ cbx_1__2__mux_2level_size10 mux_top_ipin_15 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_65 , SYNOPSYS_UNCONNECTED_66 , SYNOPSYS_UNCONNECTED_67 , SYNOPSYS_UNCONNECTED_68 } ) , .out ( bottom_grid_pin_15_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_125 ) ) ; + .p0 ( optlc_net_117 ) ) ; cbx_1__2__mux_2level_size10_mem_0 mem_top_ipin_1 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( mux_2level_size12_mem_1_ccff_tail ) , @@ -14088,16 +14996,16 @@ cbx_1__2__logical_tile_io_mode_io_ logical_tile_io_mode_io__0 ( .ccff_tail ( ccff_tail ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sky130_fd_sc_hd__buf_8 pReset_FTB00 ( .A ( pReset_W_in ) , .X ( pReset[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_4 pReset_W_FTB01 ( .A ( pReset_W_in ) , +sky130_fd_sc_hd__bufbuf_16 pReset_W_FTB01 ( .A ( pReset_W_in ) , .X ( pReset_W_out ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__bufbuf_16 pReset_S_FTB01 ( .A ( pReset_W_in ) , +sky130_fd_sc_hd__buf_4 pReset_S_FTB01 ( .A ( pReset_W_in ) , .X ( pReset_S_out ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_1 pReset_E_FTB01 ( .A ( pReset_W_in ) , - .X ( aps_rename_517_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_1 prog_clk_0_FTB00 ( .A ( prog_clk_0_S_in ) , +sky130_fd_sc_hd__buf_4 pReset_E_FTB01 ( .A ( pReset_W_in ) , + .X ( pReset_E_out ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_2 prog_clk_0_FTB00 ( .A ( prog_clk_0_S_in ) , .X ( prog_clk[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__clkbuf_1 prog_clk_0_W_FTB01 ( .A ( prog_clk_0_S_in ) , - .X ( ctsbuf_net_1129 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .X ( ctsbuf_net_1121 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_8 FTB_19__18 ( .A ( chanx_left_in[0] ) , .X ( chanx_right_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_8 FTB_20__19 ( .A ( chanx_left_in[1] ) , @@ -14226,24 +15134,20 @@ sky130_fd_sc_hd__buf_6 FTB_80__79 ( .A ( SC_IN_TOP ) , .X ( SC_OUT_BOT ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_6 FTB_81__80 ( .A ( SC_IN_BOT ) , .X ( SC_OUT_TOP ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_127 ( .LO ( SYNOPSYS_UNCONNECTED_69 ) , - .HI ( optlc_net_125 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_129 ( .LO ( SYNOPSYS_UNCONNECTED_70 ) , - .HI ( optlc_net_126 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_131 ( .LO ( SYNOPSYS_UNCONNECTED_71 ) , - .HI ( optlc_net_127 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_133 ( .LO ( SYNOPSYS_UNCONNECTED_72 ) , - .HI ( optlc_net_128 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_6 ZBUF_6_f_inst_134 ( .A ( aps_rename_517_ ) , - .X ( pReset_E_out ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_6 ropt_mt_inst_1386 ( .A ( ropt_net_148 ) , - .X ( bottom_grid_pin_11_[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_6 cts_buf_3651274 ( .A ( ctsbuf_net_1129 ) , +sky130_fd_sc_hd__conb_1 optlc_117 ( .LO ( SYNOPSYS_UNCONNECTED_69 ) , + .HI ( optlc_net_116 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_119 ( .LO ( SYNOPSYS_UNCONNECTED_70 ) , + .HI ( optlc_net_117 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_122 ( .LO ( SYNOPSYS_UNCONNECTED_71 ) , + .HI ( optlc_net_118 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_124 ( .LO ( SYNOPSYS_UNCONNECTED_72 ) , + .HI ( optlc_net_119 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_126 ( .LO ( SYNOPSYS_UNCONNECTED_73 ) , + .HI ( optlc_net_120 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 ropt_mt_inst_1360 ( .A ( ropt_net_123 ) , + .X ( bottom_grid_pin_14_[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 cts_buf_3651266 ( .A ( ctsbuf_net_1121 ) , .X ( prog_clk_0_W_out ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_6 ropt_mt_inst_1387 ( .A ( ropt_net_149 ) , - .X ( bottom_grid_pin_1_[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_6 ropt_mt_inst_1388 ( .A ( ropt_net_150 ) , - .X ( bottom_grid_pin_8_[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -14257,7 +15161,7 @@ output [0:3] mem_out ; input VDD ; input VSS ; -wire copt_net_156 ; +wire copt_net_128 ; supply1 VDD ; supply0 VSS ; @@ -14271,16 +15175,18 @@ sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( copt_net_156 ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( copt_net_128 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_6 FTB_16__15 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1394 ( .A ( copt_net_154 ) , - .X ( copt_net_152 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1395 ( .A ( copt_net_152 ) , +sky130_fd_sc_hd__buf_1 copt_h_inst_1361 ( .A ( copt_net_127 ) , .X ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1396 ( .A ( copt_net_156 ) , - .X ( copt_net_154 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1362 ( .A ( copt_net_128 ) , + .X ( copt_net_126 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1363 ( .A ( copt_net_130 ) , + .X ( copt_net_127 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1366 ( .A ( copt_net_126 ) , + .X ( copt_net_130 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -14503,12 +15409,15 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -14522,15 +15431,20 @@ input VDD ; input VSS ; input p0 ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -14543,15 +15457,20 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -14564,15 +15483,20 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -14703,12 +15627,15 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -14722,15 +15649,20 @@ input VDD ; input VSS ; input p0 ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -14743,15 +15675,20 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -14764,15 +15701,20 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -14860,7 +15802,7 @@ supply1 VDD ; supply0 VSS ; sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_1_0_ ( - .A ( mux_2level_basis_input4_mem4_2_out[0] ) , .X ( aps_rename_514_ ) , + .A ( mux_2level_basis_input4_mem4_2_out[0] ) , .X ( net_net_90 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; cbx_1__1__local_encoder2to4_28 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , .data ( local_encoder2to4_0_data ) , @@ -14891,10 +15833,8 @@ cbx_1__1__mux_2level_basis_input2_mem2_6 mux_l1_in_2_ ( .in ( in[8:9] ) , .mem_inv ( local_encoder2to4_0_data_inv[0:1] ) , .out ( mux_2level_basis_input2_mem2_0_out ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sky130_fd_sc_hd__inv_6 BINV_R_139 ( .A ( BUF_net_140 ) , .Y ( out[0] ) , +sky130_fd_sc_hd__buf_6 BUFT_RR_90 ( .A ( net_net_90 ) , .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_140 ( .A ( aps_rename_514_ ) , - .Y ( BUF_net_140 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -14907,12 +15847,15 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -14926,15 +15869,20 @@ input VDD ; input VSS ; input p0 ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -14947,15 +15895,20 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -14968,15 +15921,20 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -15064,7 +16022,7 @@ supply1 VDD ; supply0 VSS ; sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_1_0_ ( - .A ( mux_2level_basis_input4_mem4_2_out[0] ) , .X ( aps_rename_513_ ) , + .A ( mux_2level_basis_input4_mem4_2_out[0] ) , .X ( aps_rename_509_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; cbx_1__1__local_encoder2to4_26 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , .data ( local_encoder2to4_0_data ) , @@ -15095,10 +16053,10 @@ cbx_1__1__mux_2level_basis_input2_mem2_5 mux_l1_in_2_ ( .in ( in[8:9] ) , .mem_inv ( local_encoder2to4_0_data_inv[0:1] ) , .out ( mux_2level_basis_input2_mem2_0_out ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sky130_fd_sc_hd__inv_6 BINV_R_137 ( .A ( BUF_net_138 ) , .Y ( out[0] ) , +sky130_fd_sc_hd__inv_4 BINV_R_111 ( .A ( BUF_net_112 ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_138 ( .A ( aps_rename_513_ ) , - .Y ( BUF_net_138 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_4 BINV_R_112 ( .A ( aps_rename_509_ ) , + .Y ( BUF_net_112 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -15111,12 +16069,15 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -15130,15 +16091,20 @@ input VDD ; input VSS ; input p0 ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -15151,15 +16117,20 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -15172,15 +16143,20 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -15311,12 +16287,15 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -15330,15 +16309,20 @@ input VDD ; input VSS ; input p0 ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -15351,15 +16335,20 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -15372,15 +16361,20 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -15467,7 +16461,7 @@ wire [0:0] mux_2level_basis_input4_mem4_2_out ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__bufbuf_16 sky130_fd_sc_hd__buf_1_0_ ( +sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_1_0_ ( .A ( mux_2level_basis_input4_mem4_2_out[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; cbx_1__1__local_encoder2to4_22 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , @@ -15511,12 +16505,15 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -15530,15 +16527,20 @@ input VDD ; input VSS ; input p0 ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -15551,15 +16553,20 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -15572,15 +16579,20 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -15667,8 +16679,8 @@ wire [0:0] mux_2level_basis_input4_mem4_2_out ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__bufbuf_16 sky130_fd_sc_hd__buf_1_0_ ( - .A ( mux_2level_basis_input4_mem4_2_out[0] ) , .X ( out[0] ) , +sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_1_0_ ( + .A ( mux_2level_basis_input4_mem4_2_out[0] ) , .X ( aps_rename_508_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; cbx_1__1__local_encoder2to4_20 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , .data ( local_encoder2to4_0_data ) , @@ -15699,6 +16711,10 @@ cbx_1__1__mux_2level_basis_input2_mem2_2 mux_l1_in_2_ ( .in ( in[8:9] ) , .mem_inv ( local_encoder2to4_0_data_inv[0:1] ) , .out ( mux_2level_basis_input2_mem2_0_out ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sky130_fd_sc_hd__inv_4 BINV_R_109 ( .A ( BUF_net_110 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_4 BINV_R_110 ( .A ( aps_rename_508_ ) , + .Y ( BUF_net_110 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -15711,12 +16727,15 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -15730,15 +16749,20 @@ input VDD ; input VSS ; input p0 ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -15751,15 +16775,20 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -15772,15 +16801,20 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -15868,7 +16902,7 @@ supply1 VDD ; supply0 VSS ; sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_1_0_ ( - .A ( mux_2level_basis_input4_mem4_2_out[0] ) , .X ( net_net_97 ) , + .A ( mux_2level_basis_input4_mem4_2_out[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; cbx_1__1__local_encoder2to4_18 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , .data ( local_encoder2to4_0_data ) , @@ -15899,8 +16933,6 @@ cbx_1__1__mux_2level_basis_input2_mem2_1 mux_l1_in_2_ ( .in ( in[8:9] ) , .mem_inv ( local_encoder2to4_0_data_inv[0:1] ) , .out ( mux_2level_basis_input2_mem2_0_out ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_97 ( .A ( net_net_97 ) , .X ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -15913,12 +16945,15 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -15932,15 +16967,20 @@ input VDD ; input VSS ; input p0 ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -15953,15 +16993,20 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -15974,15 +17019,20 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -16070,7 +17120,7 @@ supply1 VDD ; supply0 VSS ; sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_1_0_ ( - .A ( mux_2level_basis_input4_mem4_2_out[0] ) , .X ( aps_rename_512_ ) , + .A ( mux_2level_basis_input4_mem4_2_out[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; cbx_1__1__local_encoder2to4_16 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , .data ( local_encoder2to4_0_data ) , @@ -16101,10 +17151,6 @@ cbx_1__1__mux_2level_basis_input2_mem2_0 mux_l1_in_2_ ( .in ( in[8:9] ) , .mem_inv ( local_encoder2to4_0_data_inv[0:1] ) , .out ( mux_2level_basis_input2_mem2_0_out ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_95 ( .A ( BUF_net_96 ) , .Y ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_96 ( .A ( aps_rename_512_ ) , - .Y ( BUF_net_96 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -16331,7 +17377,7 @@ input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ropt_net_179 ) , +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( copt_net_121 ) , .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , @@ -16345,26 +17391,20 @@ sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_1 FTB_1__0 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1388 ( .A ( copt_net_147 ) , - .X ( copt_net_146 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1389 ( .A ( copt_net_149 ) , - .X ( copt_net_147 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1390 ( .A ( ropt_net_182 ) , - .X ( copt_net_148 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1391 ( .A ( ropt_net_181 ) , - .X ( copt_net_149 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1392 ( .A ( ccff_head[0] ) , - .X ( copt_net_150 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 copt_h_inst_1397 ( .A ( copt_net_146 ) , - .X ( copt_net_155 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_1 ropt_h_inst_1420 ( .A ( copt_net_155 ) , - .X ( ropt_net_179 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1421 ( .A ( copt_net_150 ) , - .X ( ropt_net_180 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_1 ropt_h_inst_1422 ( .A ( copt_net_148 ) , - .X ( ropt_net_181 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1423 ( .A ( ropt_net_180 ) , - .X ( ropt_net_182 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1354 ( .A ( copt_net_119 ) , + .X ( copt_net_118 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1355 ( .A ( copt_net_123 ) , + .X ( copt_net_119 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1356 ( .A ( ropt_net_139 ) , + .X ( copt_net_120 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1357 ( .A ( copt_net_122 ) , + .X ( copt_net_121 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_2 copt_h_inst_1358 ( .A ( copt_net_120 ) , + .X ( copt_net_122 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1359 ( .A ( ccff_head[0] ) , + .X ( copt_net_123 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1376 ( .A ( copt_net_118 ) , + .X ( ropt_net_139 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -16378,15 +17418,20 @@ input VDD ; input VSS ; input p0 ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -16399,15 +17444,20 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -16420,15 +17470,20 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -16441,15 +17496,20 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -16537,7 +17597,7 @@ supply1 VDD ; supply0 VSS ; sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_1_0_ ( - .A ( mux_2level_basis_input4_mem4_3_out[0] ) , .X ( aps_rename_511_ ) , + .A ( mux_2level_basis_input4_mem4_3_out[0] ) , .X ( aps_rename_507_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; cbx_1__1__local_encoder2to4_14 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , .data ( local_encoder2to4_0_data ) , @@ -16568,10 +17628,10 @@ cbx_1__1__mux_2level_basis_input4_mem4_31 mux_l2_in_0_ ( .mem_inv ( local_encoder2to4_1_data_inv ) , .out ( mux_2level_basis_input4_mem4_3_out ) , .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_6 BINV_R_135 ( .A ( BUF_net_136 ) , .Y ( out[0] ) , +sky130_fd_sc_hd__inv_4 BINV_R_84 ( .A ( BUF_net_85 ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_136 ( .A ( aps_rename_511_ ) , - .Y ( BUF_net_136 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_4 BINV_R_85 ( .A ( aps_rename_507_ ) , + .Y ( BUF_net_85 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -16585,15 +17645,20 @@ input VDD ; input VSS ; input p0 ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -16606,15 +17671,20 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -16627,15 +17697,20 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -16648,15 +17723,20 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -16744,7 +17824,7 @@ supply1 VDD ; supply0 VSS ; sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_1_0_ ( - .A ( mux_2level_basis_input4_mem4_3_out[0] ) , .X ( aps_rename_510_ ) , + .A ( mux_2level_basis_input4_mem4_3_out[0] ) , .X ( aps_rename_506_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; cbx_1__1__local_encoder2to4_12 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , .data ( local_encoder2to4_0_data ) , @@ -16775,10 +17855,10 @@ cbx_1__1__mux_2level_basis_input4_mem4_27 mux_l2_in_0_ ( .mem_inv ( local_encoder2to4_1_data_inv ) , .out ( mux_2level_basis_input4_mem4_3_out ) , .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_6 BINV_R_133 ( .A ( BUF_net_134 ) , .Y ( out[0] ) , +sky130_fd_sc_hd__inv_4 BINV_R_107 ( .A ( BUF_net_108 ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_134 ( .A ( aps_rename_510_ ) , - .Y ( BUF_net_134 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_4 BINV_R_108 ( .A ( aps_rename_506_ ) , + .Y ( BUF_net_108 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -16792,15 +17872,20 @@ input VDD ; input VSS ; input p0 ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -16813,15 +17898,20 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -16834,15 +17924,20 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -16855,15 +17950,20 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -16951,7 +18051,7 @@ supply1 VDD ; supply0 VSS ; sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_1_0_ ( - .A ( mux_2level_basis_input4_mem4_3_out[0] ) , .X ( aps_rename_509_ ) , + .A ( mux_2level_basis_input4_mem4_3_out[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; cbx_1__1__local_encoder2to4_10 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , .data ( local_encoder2to4_0_data ) , @@ -16982,10 +18082,6 @@ cbx_1__1__mux_2level_basis_input4_mem4_23 mux_l2_in_0_ ( .mem_inv ( local_encoder2to4_1_data_inv ) , .out ( mux_2level_basis_input4_mem4_3_out ) , .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_6 BINV_R_131 ( .A ( BUF_net_132 ) , .Y ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_132 ( .A ( aps_rename_509_ ) , - .Y ( BUF_net_132 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -16999,15 +18095,20 @@ input VDD ; input VSS ; input p0 ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -17020,15 +18121,20 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -17041,15 +18147,20 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -17062,15 +18173,20 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -17158,7 +18274,7 @@ supply1 VDD ; supply0 VSS ; sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_1_0_ ( - .A ( mux_2level_basis_input4_mem4_3_out[0] ) , .X ( aps_rename_508_ ) , + .A ( mux_2level_basis_input4_mem4_3_out[0] ) , .X ( aps_rename_505_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; cbx_1__1__local_encoder2to4_8 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , .data ( local_encoder2to4_0_data ) , @@ -17189,10 +18305,10 @@ cbx_1__1__mux_2level_basis_input4_mem4_19 mux_l2_in_0_ ( .mem_inv ( local_encoder2to4_1_data_inv ) , .out ( mux_2level_basis_input4_mem4_3_out ) , .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_6 BINV_R_129 ( .A ( BUF_net_130 ) , .Y ( out[0] ) , +sky130_fd_sc_hd__inv_4 BINV_R_80 ( .A ( BUF_net_81 ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_130 ( .A ( aps_rename_508_ ) , - .Y ( BUF_net_130 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_4 BINV_R_81 ( .A ( aps_rename_505_ ) , + .Y ( BUF_net_81 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -17206,15 +18322,20 @@ input VDD ; input VSS ; input p0 ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -17227,15 +18348,20 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -17248,15 +18374,20 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -17269,15 +18400,20 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -17365,7 +18501,7 @@ supply1 VDD ; supply0 VSS ; sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_1_0_ ( - .A ( mux_2level_basis_input4_mem4_3_out[0] ) , .X ( aps_rename_507_ ) , + .A ( mux_2level_basis_input4_mem4_3_out[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; cbx_1__1__local_encoder2to4_6 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , .data ( local_encoder2to4_0_data ) , @@ -17396,10 +18532,6 @@ cbx_1__1__mux_2level_basis_input4_mem4_15 mux_l2_in_0_ ( .mem_inv ( local_encoder2to4_1_data_inv ) , .out ( mux_2level_basis_input4_mem4_3_out ) , .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_85 ( .A ( BUF_net_86 ) , .Y ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_86 ( .A ( aps_rename_507_ ) , - .Y ( BUF_net_86 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -17413,15 +18545,20 @@ input VDD ; input VSS ; input p0 ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -17434,15 +18571,20 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -17455,15 +18597,20 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -17476,15 +18623,20 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -17571,8 +18723,8 @@ wire [0:0] mux_2level_basis_input4_mem4_3_out ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_1_0_ ( - .A ( mux_2level_basis_input4_mem4_3_out[0] ) , .X ( net_net_84 ) , +sky130_fd_sc_hd__bufbuf_16 sky130_fd_sc_hd__buf_1_0_ ( + .A ( mux_2level_basis_input4_mem4_3_out[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; cbx_1__1__local_encoder2to4_4 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , .data ( local_encoder2to4_0_data ) , @@ -17603,8 +18755,6 @@ cbx_1__1__mux_2level_basis_input4_mem4_11 mux_l2_in_0_ ( .mem_inv ( local_encoder2to4_1_data_inv ) , .out ( mux_2level_basis_input4_mem4_3_out ) , .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_84 ( .A ( net_net_84 ) , .X ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -17618,15 +18768,20 @@ input VDD ; input VSS ; input p0 ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -17639,15 +18794,20 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -17660,15 +18820,20 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -17681,15 +18846,20 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -17777,7 +18947,7 @@ supply1 VDD ; supply0 VSS ; sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_1_0_ ( - .A ( mux_2level_basis_input4_mem4_3_out[0] ) , .X ( aps_rename_506_ ) , + .A ( mux_2level_basis_input4_mem4_3_out[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; cbx_1__1__local_encoder2to4_2 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , .data ( local_encoder2to4_0_data ) , @@ -17808,10 +18978,6 @@ cbx_1__1__mux_2level_basis_input4_mem4_7 mux_l2_in_0_ ( .mem_inv ( local_encoder2to4_1_data_inv ) , .out ( mux_2level_basis_input4_mem4_3_out ) , .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_82 ( .A ( BUF_net_83 ) , .Y ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_83 ( .A ( aps_rename_506_ ) , - .Y ( BUF_net_83 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -17825,15 +18991,20 @@ input VDD ; input VSS ; input p0 ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -17846,15 +19017,20 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -17867,15 +19043,20 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -17888,15 +19069,20 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -17984,7 +19170,7 @@ supply1 VDD ; supply0 VSS ; sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_1_0_ ( - .A ( mux_2level_basis_input4_mem4_3_out[0] ) , .X ( aps_rename_505_ ) , + .A ( mux_2level_basis_input4_mem4_3_out[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; cbx_1__1__local_encoder2to4_0 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , .data ( local_encoder2to4_0_data ) , @@ -18015,10 +19201,6 @@ cbx_1__1__mux_2level_basis_input4_mem4_3 mux_l2_in_0_ ( .mem_inv ( local_encoder2to4_1_data_inv ) , .out ( mux_2level_basis_input4_mem4_3_out ) , .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_6 BINV_R_127 ( .A ( BUF_net_128 ) , .Y ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_128 ( .A ( aps_rename_505_ ) , - .Y ( BUF_net_128 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -18104,9 +19286,11 @@ output clk_3_W_out ; input VDD ; input VSS ; -wire ropt_net_175 ; -wire ropt_net_166 ; -wire ropt_net_168 ; +wire ropt_net_132 ; +wire ropt_net_134 ; +wire ropt_net_133 ; +wire ropt_net_135 ; +wire ropt_net_136 ; wire [0:0] prog_clk ; wire prog_clk_0 ; wire [0:3] mux_2level_size10_0_sram ; @@ -18160,8 +19344,8 @@ cbx_1__1__mux_2level_size12_0 mux_top_ipin_0 ( .sram ( mux_2level_size12_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 , SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) , - .out ( bottom_grid_pin_0_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_143 ) ) ; + .out ( { ropt_net_140 } ) , + .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_113 ) ) ; cbx_1__1__mux_2level_size12_1 mux_top_ipin_2 ( .in ( { chanx_right_out[2] , chanx_left_out[2] , chanx_right_out[5] , chanx_left_out[5] , chanx_right_out[8] , chanx_left_out[8] , @@ -18171,7 +19355,7 @@ cbx_1__1__mux_2level_size12_1 mux_top_ipin_2 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 , SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 } ) , .out ( bottom_grid_pin_2_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_144 ) ) ; + .p0 ( optlc_net_115 ) ) ; cbx_1__1__mux_2level_size12_2 mux_top_ipin_4 ( .in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[4] , chanx_left_out[4] , chanx_right_out[10] , chanx_left_out[10] , @@ -18181,7 +19365,7 @@ cbx_1__1__mux_2level_size12_2 mux_top_ipin_4 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_9 , SYNOPSYS_UNCONNECTED_10 , SYNOPSYS_UNCONNECTED_11 , SYNOPSYS_UNCONNECTED_12 } ) , .out ( bottom_grid_pin_4_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_141 ) ) ; + .p0 ( optlc_net_113 ) ) ; cbx_1__1__mux_2level_size12_3 mux_top_ipin_6 ( .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[3] , chanx_left_out[3] , chanx_right_out[6] , chanx_left_out[6] , @@ -18191,7 +19375,7 @@ cbx_1__1__mux_2level_size12_3 mux_top_ipin_6 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 , SYNOPSYS_UNCONNECTED_15 , SYNOPSYS_UNCONNECTED_16 } ) , .out ( bottom_grid_pin_6_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_143 ) ) ; + .p0 ( optlc_net_115 ) ) ; cbx_1__1__mux_2level_size12_4 mux_top_ipin_8 ( .in ( { chanx_right_out[2] , chanx_left_out[2] , chanx_right_out[5] , chanx_left_out[5] , chanx_right_out[8] , chanx_left_out[8] , @@ -18201,7 +19385,7 @@ cbx_1__1__mux_2level_size12_4 mux_top_ipin_8 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_17 , SYNOPSYS_UNCONNECTED_18 , SYNOPSYS_UNCONNECTED_19 , SYNOPSYS_UNCONNECTED_20 } ) , .out ( bottom_grid_pin_8_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_142 ) ) ; + .p0 ( optlc_net_116 ) ) ; cbx_1__1__mux_2level_size12_5 mux_top_ipin_10 ( .in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[4] , chanx_left_out[4] , chanx_right_out[10] , chanx_left_out[10] , @@ -18211,7 +19395,7 @@ cbx_1__1__mux_2level_size12_5 mux_top_ipin_10 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_21 , SYNOPSYS_UNCONNECTED_22 , SYNOPSYS_UNCONNECTED_23 , SYNOPSYS_UNCONNECTED_24 } ) , .out ( bottom_grid_pin_10_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_141 ) ) ; + .p0 ( optlc_net_116 ) ) ; cbx_1__1__mux_2level_size12_6 mux_top_ipin_12 ( .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[3] , chanx_left_out[3] , chanx_right_out[6] , chanx_left_out[6] , @@ -18221,7 +19405,7 @@ cbx_1__1__mux_2level_size12_6 mux_top_ipin_12 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_25 , SYNOPSYS_UNCONNECTED_26 , SYNOPSYS_UNCONNECTED_27 , SYNOPSYS_UNCONNECTED_28 } ) , .out ( bottom_grid_pin_12_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_141 ) ) ; + .p0 ( optlc_net_114 ) ) ; cbx_1__1__mux_2level_size12 mux_top_ipin_14 ( .in ( { chanx_right_out[2] , chanx_left_out[2] , chanx_right_out[5] , chanx_left_out[5] , chanx_right_out[8] , chanx_left_out[8] , @@ -18231,7 +19415,7 @@ cbx_1__1__mux_2level_size12 mux_top_ipin_14 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_29 , SYNOPSYS_UNCONNECTED_30 , SYNOPSYS_UNCONNECTED_31 , SYNOPSYS_UNCONNECTED_32 } ) , .out ( bottom_grid_pin_14_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_144 ) ) ; + .p0 ( optlc_net_115 ) ) ; cbx_1__1__mux_2level_size12_mem_0 mem_top_ipin_0 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( mux_2level_size12_mem_0_ccff_tail ) , @@ -18280,7 +19464,7 @@ cbx_1__1__mux_2level_size10_0 mux_top_ipin_1 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_33 , SYNOPSYS_UNCONNECTED_34 , SYNOPSYS_UNCONNECTED_35 , SYNOPSYS_UNCONNECTED_36 } ) , .out ( bottom_grid_pin_1_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_143 ) ) ; + .p0 ( optlc_net_113 ) ) ; cbx_1__1__mux_2level_size10_1 mux_top_ipin_3 ( .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[3] , chanx_left_out[3] , chanx_right_out[9] , chanx_left_out[9] , @@ -18289,8 +19473,8 @@ cbx_1__1__mux_2level_size10_1 mux_top_ipin_3 ( .sram ( mux_2level_size10_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_37 , SYNOPSYS_UNCONNECTED_38 , SYNOPSYS_UNCONNECTED_39 , SYNOPSYS_UNCONNECTED_40 } ) , - .out ( bottom_grid_pin_3_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_143 ) ) ; + .out ( { ropt_net_131 } ) , + .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_113 ) ) ; cbx_1__1__mux_2level_size10_2 mux_top_ipin_5 ( .in ( { chanx_right_out[2] , chanx_left_out[2] , chanx_right_out[5] , chanx_left_out[5] , chanx_right_out[11] , chanx_left_out[11] , @@ -18300,7 +19484,7 @@ cbx_1__1__mux_2level_size10_2 mux_top_ipin_5 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_41 , SYNOPSYS_UNCONNECTED_42 , SYNOPSYS_UNCONNECTED_43 , SYNOPSYS_UNCONNECTED_44 } ) , .out ( bottom_grid_pin_5_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_141 ) ) ; + .p0 ( optlc_net_115 ) ) ; cbx_1__1__mux_2level_size10_3 mux_top_ipin_7 ( .in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[4] , chanx_left_out[4] , chanx_right_out[7] , chanx_left_out[7] , @@ -18310,7 +19494,7 @@ cbx_1__1__mux_2level_size10_3 mux_top_ipin_7 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_45 , SYNOPSYS_UNCONNECTED_46 , SYNOPSYS_UNCONNECTED_47 , SYNOPSYS_UNCONNECTED_48 } ) , .out ( bottom_grid_pin_7_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_142 ) ) ; + .p0 ( optlc_net_116 ) ) ; cbx_1__1__mux_2level_size10_4 mux_top_ipin_9 ( .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[3] , chanx_left_out[3] , chanx_right_out[9] , chanx_left_out[9] , @@ -18319,8 +19503,8 @@ cbx_1__1__mux_2level_size10_4 mux_top_ipin_9 ( .sram ( mux_2level_size10_4_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_49 , SYNOPSYS_UNCONNECTED_50 , SYNOPSYS_UNCONNECTED_51 , SYNOPSYS_UNCONNECTED_52 } ) , - .out ( { ZBUF_4_f_0 } ) , - .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_144 ) ) ; + .out ( bottom_grid_pin_9_ ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_113 ) ) ; cbx_1__1__mux_2level_size10_5 mux_top_ipin_11 ( .in ( { chanx_right_out[2] , chanx_left_out[2] , chanx_right_out[5] , chanx_left_out[5] , chanx_right_out[11] , chanx_left_out[11] , @@ -18330,7 +19514,7 @@ cbx_1__1__mux_2level_size10_5 mux_top_ipin_11 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_53 , SYNOPSYS_UNCONNECTED_54 , SYNOPSYS_UNCONNECTED_55 , SYNOPSYS_UNCONNECTED_56 } ) , .out ( bottom_grid_pin_11_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_142 ) ) ; + .p0 ( optlc_net_114 ) ) ; cbx_1__1__mux_2level_size10_6 mux_top_ipin_13 ( .in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[4] , chanx_left_out[4] , chanx_right_out[13] , chanx_left_out[13] , @@ -18340,7 +19524,7 @@ cbx_1__1__mux_2level_size10_6 mux_top_ipin_13 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_57 , SYNOPSYS_UNCONNECTED_58 , SYNOPSYS_UNCONNECTED_59 , SYNOPSYS_UNCONNECTED_60 } ) , .out ( bottom_grid_pin_13_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_142 ) ) ; + .p0 ( optlc_net_116 ) ) ; cbx_1__1__mux_2level_size10 mux_top_ipin_15 ( .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[3] , chanx_left_out[3] , chanx_right_out[6] , chanx_left_out[6] , @@ -18349,8 +19533,8 @@ cbx_1__1__mux_2level_size10 mux_top_ipin_15 ( .sram ( mux_2level_size10_7_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_61 , SYNOPSYS_UNCONNECTED_62 , SYNOPSYS_UNCONNECTED_63 , SYNOPSYS_UNCONNECTED_64 } ) , - .out ( { ZBUF_4_f_1 } ) , - .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_143 ) ) ; + .out ( bottom_grid_pin_15_ ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_113 ) ) ; cbx_1__1__mux_2level_size10_mem_0 mem_top_ipin_1 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( mux_2level_size12_mem_0_ccff_tail ) , @@ -18394,37 +19578,37 @@ cbx_1__1__mux_2level_size10_mem mem_top_ipin_15 ( .pReset ( pReset ) , sky130_fd_sc_hd__buf_8 pReset_FTB00 ( .A ( pReset_W_in ) , .X ( pReset[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_4 pReset_W_FTB01 ( .A ( pReset_W_in ) , - .X ( ZBUF_39_1 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_4 pReset_S_FTB01 ( .A ( pReset_W_in ) , - .X ( aps_rename_515_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_1 pReset_E_FTB01 ( .A ( pReset_W_in ) , - .X ( aps_rename_516_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .X ( pReset_W_out ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 pReset_S_FTB01 ( .A ( pReset_W_in ) , + .X ( aps_rename_510_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_4 pReset_E_FTB01 ( .A ( pReset_W_in ) , + .X ( pReset_E_out ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_1 prog_clk_0_FTB00 ( .A ( prog_clk_0_N_in ) , .X ( prog_clk[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__clkbuf_1 prog_clk_0_W_FTB01 ( .A ( prog_clk_0_N_in ) , - .X ( ctsbuf_net_1145 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__bufbuf_16 prog_clk_1_N_FTB01 ( .A ( prog_clk_1_E_in ) , - .X ( prog_clk_1_N_out ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .X ( ctsbuf_net_1117 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 prog_clk_1_N_FTB01 ( .A ( prog_clk_1_E_in ) , + .X ( aps_rename_511_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_1 prog_clk_1_S_FTB01 ( .A ( prog_clk_1_E_in ) , - .X ( aps_rename_517_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .X ( net_net_95 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__bufbuf_16 prog_clk_2_W_FTB01 ( .A ( prog_clk_2_W_in ) , .X ( prog_clk_2_W_out ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_1 prog_clk_2_E_FTB01 ( .A ( prog_clk_2_W_in ) , - .X ( aps_rename_518_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_1 prog_clk_3_E_FTB01 ( .A ( prog_clk_3_E_in ) , - .X ( aps_rename_519_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_4 prog_clk_2_E_FTB01 ( .A ( prog_clk_2_W_in ) , + .X ( prog_clk_2_E_out ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_4 prog_clk_3_E_FTB01 ( .A ( prog_clk_3_E_in ) , + .X ( prog_clk_3_E_out ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__bufbuf_16 prog_clk_3_W_FTB01 ( .A ( prog_clk_3_E_in ) , .X ( prog_clk_3_W_out ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_1 clk_1_N_FTB01 ( .A ( clk_1_E_in ) , - .X ( aps_rename_520_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__bufbuf_16 clk_1_N_FTB01 ( .A ( clk_1_E_in ) , + .X ( clk_1_N_out ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_1 clk_1_S_FTB01 ( .A ( clk_1_E_in ) , - .X ( aps_rename_521_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .X ( aps_rename_512_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__bufbuf_16 clk_2_W_FTB01 ( .A ( clk_2_W_in ) , .X ( clk_2_W_out ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_1 clk_2_E_FTB01 ( .A ( clk_2_W_in ) , - .X ( net_net_112 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_1 clk_3_E_FTB01 ( .A ( clk_3_E_in ) , - .X ( aps_rename_522_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_4 clk_2_E_FTB01 ( .A ( clk_2_W_in ) , + .X ( clk_2_E_out ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 clk_3_E_FTB01 ( .A ( clk_3_E_in ) , .X ( net_net_98 ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__bufbuf_16 clk_3_W_FTB01 ( .A ( clk_3_E_in ) , .X ( clk_3_W_out ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_8 FTB_17__16 ( .A ( chanx_left_in[0] ) , @@ -18474,7 +19658,7 @@ sky130_fd_sc_hd__buf_8 FTB_38__37 ( .A ( chanx_left_in[21] ) , sky130_fd_sc_hd__buf_8 FTB_39__38 ( .A ( chanx_left_in[22] ) , .X ( chanx_right_out[22] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_1 FTB_40__39 ( .A ( chanx_left_in[23] ) , - .X ( ropt_net_175 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .X ( ropt_net_132 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_8 FTB_41__40 ( .A ( chanx_left_in[24] ) , .X ( chanx_right_out[24] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_8 FTB_42__41 ( .A ( chanx_left_in[25] ) , @@ -18533,8 +19717,8 @@ sky130_fd_sc_hd__buf_8 FTB_68__67 ( .A ( chanx_right_in[21] ) , .X ( chanx_left_out[21] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_8 FTB_69__68 ( .A ( chanx_right_in[22] ) , .X ( chanx_left_out[22] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_1 FTB_70__69 ( .A ( chanx_right_in[23] ) , - .X ( ropt_net_166 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 FTB_70__69 ( .A ( chanx_right_in[23] ) , + .X ( ropt_net_134 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_8 FTB_71__70 ( .A ( chanx_right_in[24] ) , .X ( chanx_left_out[24] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_8 FTB_72__71 ( .A ( chanx_right_in[25] ) , @@ -18547,64 +19731,54 @@ sky130_fd_sc_hd__buf_8 FTB_75__74 ( .A ( chanx_right_in[28] ) , .X ( chanx_left_out[28] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_8 FTB_76__75 ( .A ( chanx_right_in[29] ) , .X ( chanx_left_out[29] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_8 FTB_77__76 ( .A ( SC_IN_TOP ) , .X ( SC_OUT_BOT ) , +sky130_fd_sc_hd__buf_6 FTB_77__76 ( .A ( SC_IN_TOP ) , .X ( SC_OUT_BOT ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_6 FTB_78__77 ( .A ( SC_IN_BOT ) , .X ( ropt_net_168 ) , +sky130_fd_sc_hd__buf_1 FTB_78__77 ( .A ( SC_IN_BOT ) , .X ( ropt_net_133 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_8 FTB_79__78 ( .A ( REGIN_FEEDTHROUGH ) , - .X ( REGOUT_FEEDTHROUGH ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_8 FTB_80__79 ( .A ( CIN_FEEDTHROUGH ) , - .X ( COUT_FEEDTHROUGH ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_102 ( .A ( BUF_net_103 ) , .Y ( pReset_E_out ) , +sky130_fd_sc_hd__buf_6 FTB_79__78 ( .A ( REGIN_FEEDTHROUGH ) , + .X ( ropt_net_135 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 FTB_80__79 ( .A ( CIN_FEEDTHROUGH ) , + .X ( ropt_net_136 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_115 ( .LO ( SYNOPSYS_UNCONNECTED_65 ) , + .HI ( optlc_net_113 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_92 ( .A ( aps_rename_510_ ) , + .Y ( BUF_net_92 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_93 ( .A ( BUF_net_94 ) , + .Y ( prog_clk_1_N_out ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_94 ( .A ( aps_rename_511_ ) , + .Y ( BUF_net_94 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_95 ( .A ( net_net_95 ) , + .X ( prog_clk_1_S_out ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_96 ( .A ( BUF_net_97 ) , .Y ( clk_1_S_out ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_103 ( .A ( aps_rename_516_ ) , - .Y ( BUF_net_103 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_104 ( .A ( BUF_net_105 ) , - .Y ( prog_clk_1_S_out ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_105 ( .A ( aps_rename_517_ ) , - .Y ( BUF_net_105 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_6 BINV_R_106 ( .A ( BUF_net_107 ) , - .Y ( prog_clk_3_E_out ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_107 ( .A ( aps_rename_519_ ) , - .Y ( BUF_net_107 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_108 ( .A ( BUF_net_109 ) , .Y ( clk_1_N_out ) , +sky130_fd_sc_hd__inv_1 BINV_R_97 ( .A ( aps_rename_512_ ) , + .Y ( BUF_net_97 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_98 ( .A ( net_net_98 ) , .X ( clk_3_E_out ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_109 ( .A ( aps_rename_520_ ) , - .Y ( BUF_net_109 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_110 ( .A ( BUF_net_111 ) , .Y ( clk_1_S_out ) , +sky130_fd_sc_hd__inv_4 BINV_R_105 ( .A ( BUF_net_92 ) , .Y ( pReset_S_out ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_111 ( .A ( aps_rename_521_ ) , - .Y ( BUF_net_111 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_112 ( .A ( net_net_112 ) , .X ( clk_2_E_out ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_143 ( .LO ( SYNOPSYS_UNCONNECTED_65 ) , - .HI ( optlc_net_141 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_145 ( .LO ( SYNOPSYS_UNCONNECTED_66 ) , - .HI ( optlc_net_142 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_147 ( .LO ( SYNOPSYS_UNCONNECTED_67 ) , - .HI ( optlc_net_143 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_149 ( .LO ( SYNOPSYS_UNCONNECTED_68 ) , - .HI ( optlc_net_144 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_6 ZBUF_6_f_inst_150 ( .A ( aps_rename_518_ ) , - .X ( prog_clk_2_E_out ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_6 ZBUF_6_f_inst_151 ( .A ( aps_rename_522_ ) , - .X ( clk_3_E_out ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_6 ZBUF_6_f_inst_656 ( .A ( aps_rename_515_ ) , - .X ( pReset_S_out ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_6 ZBUF_4_f_inst_1385 ( .A ( ZBUF_4_f_0 ) , - .X ( bottom_grid_pin_9_[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__clkbuf_8 cts_buf_3651292 ( .A ( ctsbuf_net_1145 ) , +sky130_fd_sc_hd__conb_1 optlc_117 ( .LO ( SYNOPSYS_UNCONNECTED_66 ) , + .HI ( optlc_net_114 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_119 ( .LO ( SYNOPSYS_UNCONNECTED_67 ) , + .HI ( optlc_net_115 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_121 ( .LO ( SYNOPSYS_UNCONNECTED_68 ) , + .HI ( optlc_net_116 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 ropt_mt_inst_1367 ( .A ( ropt_net_131 ) , + .X ( bottom_grid_pin_3_[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 cts_buf_3651261 ( .A ( ctsbuf_net_1117 ) , .X ( prog_clk_0_W_out ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_6 ZBUF_4_f_inst_1386 ( .A ( ZBUF_4_f_1 ) , - .X ( bottom_grid_pin_15_[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_6 ZBUF_39_inst_1387 ( .A ( ZBUF_39_1 ) , - .X ( pReset_W_out ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_6 ropt_mt_inst_1417 ( .A ( ropt_net_175 ) , +sky130_fd_sc_hd__buf_6 ropt_mt_inst_1371 ( .A ( ropt_net_132 ) , .X ( chanx_right_out[23] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_6 ropt_mt_inst_1408 ( .A ( ropt_net_166 ) , - .X ( chanx_left_out[23] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_6 ropt_mt_inst_1410 ( .A ( ropt_net_168 ) , +sky130_fd_sc_hd__buf_6 ropt_mt_inst_1372 ( .A ( ropt_net_133 ) , .X ( SC_OUT_TOP ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1373 ( .A ( ropt_net_134 ) , + .X ( chanx_left_out[23] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 ropt_mt_inst_1374 ( .A ( ropt_net_135 ) , + .X ( REGOUT_FEEDTHROUGH ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1375 ( .A ( ropt_net_136 ) , + .X ( COUT_FEEDTHROUGH ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 ropt_mt_inst_1377 ( .A ( ropt_net_140 ) , + .X ( bottom_grid_pin_0_[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -18618,25 +19792,25 @@ output [0:0] mem_out ; input VDD ; input VSS ; -wire copt_net_156 ; +wire copt_net_148 ; supply1 VDD ; supply0 VSS ; sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( copt_net_156 ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( copt_net_148 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_6 FTB_18__17 ( .A ( mem_out[0] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1389 ( .A ( copt_net_156 ) , - .X ( copt_net_152 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1390 ( .A ( copt_net_152 ) , - .X ( copt_net_153 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1391 ( .A ( copt_net_153 ) , - .X ( copt_net_154 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1392 ( .A ( copt_net_154 ) , - .X ( copt_net_155 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1393 ( .A ( copt_net_155 ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1383 ( .A ( copt_net_149 ) , .X ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1384 ( .A ( copt_net_150 ) , + .X ( copt_net_149 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1385 ( .A ( copt_net_151 ) , + .X ( copt_net_150 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1386 ( .A ( copt_net_152 ) , + .X ( copt_net_151 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1387 ( .A ( copt_net_148 ) , + .X ( copt_net_152 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -18655,21 +19829,21 @@ input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__nand2b_1 ISOL_EN_GATE ( .A_N ( FPGA_DIR ) , - .B ( IO_ISOL_N ) , .Y ( aps_rename_518_ ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; +sky130_fd_sc_hd__or2b_4 ISOL_EN_GATE ( .A ( FPGA_DIR ) , .B_N ( IO_ISOL_N ) , + .X ( aps_rename_517_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__inv_1 INV_SOC_DIR ( .A ( BUF_net_117 ) , .Y ( SOC_DIR_N ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__ebufn_4 IN_PROTECT_GATE ( .A ( SOC_IN ) , .TE_B ( SOC_DIR_N ) , .Z ( FPGA_IN ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__ebufn_4 OUT_PROTECT_GATE ( .A ( FPGA_OUT ) , - .TE_B ( BUF_net_117 ) , .Z ( SOC_OUT ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_116 ( .A ( BUF_net_118 ) , .Y ( SOC_DIR ) , + .TE_B ( aps_rename_517_ ) , .Z ( SOC_OUT ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_115 ( .A ( BUF_net_118 ) , .Y ( SOC_DIR ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_4 BINV_R_117 ( .A ( BUF_net_118 ) , .Y ( BUF_net_117 ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_118 ( .A ( aps_rename_518_ ) , +sky130_fd_sc_hd__inv_1 BINV_R_118 ( .A ( aps_rename_517_ ) , .Y ( BUF_net_118 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_117 ( .A ( BUF_net_118 ) , .Y ( BUF_net_117 ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -18776,20 +19950,18 @@ supply1 VDD ; supply0 VSS ; sky130_fd_sc_hd__nand2b_1 ISOL_EN_GATE ( .A_N ( FPGA_DIR ) , - .B ( IO_ISOL_N ) , .Y ( aps_rename_517_ ) , .VPWR ( VDD ) , + .B ( IO_ISOL_N ) , .Y ( aps_rename_516_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 INV_SOC_DIR ( .A ( aps_rename_517_ ) , - .Y ( SOC_DIR_N ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__ebufn_4 IN_PROTECT_GATE ( .A ( SOC_IN ) , - .TE_B ( SOC_DIR_N ) , .Z ( FPGA_IN ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .TE_B ( BUF_net_114 ) , .Z ( FPGA_IN ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__ebufn_4 OUT_PROTECT_GATE ( .A ( FPGA_OUT ) , - .TE_B ( BUF_net_113 ) , .Z ( SOC_OUT ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_4 BINV_R_113 ( .A ( BUF_net_115 ) , .Y ( BUF_net_113 ) , + .TE_B ( BUF_net_111 ) , .Z ( SOC_OUT ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_4 BINV_R_111 ( .A ( BUF_net_114 ) , .Y ( BUF_net_111 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_114 ( .A ( BUF_net_115 ) , .Y ( SOC_DIR ) , +sky130_fd_sc_hd__inv_8 BINV_R_113 ( .A ( BUF_net_114 ) , .Y ( SOC_DIR ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_115 ( .A ( aps_rename_517_ ) , - .Y ( BUF_net_115 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_114 ( .A ( aps_rename_516_ ) , + .Y ( BUF_net_114 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -18896,24 +20068,20 @@ supply1 VDD ; supply0 VSS ; sky130_fd_sc_hd__nand2b_1 ISOL_EN_GATE ( .A_N ( FPGA_DIR ) , - .B ( IO_ISOL_N ) , .Y ( aps_rename_516_ ) , .VPWR ( VDD ) , + .B ( IO_ISOL_N ) , .Y ( aps_rename_515_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 INV_SOC_DIR ( .A ( aps_rename_516_ ) , - .Y ( SOC_DIR_N ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 INV_SOC_DIR ( .A ( BUF_net_108 ) , .Y ( SOC_DIR_N ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__ebufn_4 IN_PROTECT_GATE ( .A ( SOC_IN ) , .TE_B ( SOC_DIR_N ) , .Z ( FPGA_IN ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__ebufn_4 OUT_PROTECT_GATE ( .A ( FPGA_OUT ) , - .TE_B ( BUF_net_110 ) , .Z ( SOC_OUT ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_4 BINV_R_110 ( .A ( BUF_net_112 ) , .Y ( BUF_net_110 ) , + .TE_B ( BUF_net_108 ) , .Z ( SOC_OUT ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_4 BINV_R_108 ( .A ( BUF_net_110 ) , .Y ( BUF_net_108 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_112 ( .A ( aps_rename_516_ ) , - .Y ( BUF_net_112 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_131 ( .A ( BUF_net_112 ) , .Y ( BUF_net_131 ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_6 BINV_R_137 ( .A ( BUF_net_138 ) , .Y ( SOC_DIR ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_138 ( .A ( BUF_net_131 ) , .Y ( BUF_net_138 ) , +sky130_fd_sc_hd__inv_8 BINV_R_109 ( .A ( BUF_net_110 ) , .Y ( SOC_DIR ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_110 ( .A ( aps_rename_515_ ) , + .Y ( BUF_net_110 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -19020,16 +20188,18 @@ supply1 VDD ; supply0 VSS ; sky130_fd_sc_hd__or2b_4 ISOL_EN_GATE ( .A ( FPGA_DIR ) , .B_N ( IO_ISOL_N ) , - .X ( aps_rename_515_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .X ( aps_rename_514_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 INV_SOC_DIR ( .A ( aps_rename_514_ ) , + .Y ( SOC_DIR_N ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__ebufn_4 IN_PROTECT_GATE ( .A ( SOC_IN ) , - .TE_B ( BUF_net_109 ) , .Z ( FPGA_IN ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .TE_B ( SOC_DIR_N ) , .Z ( FPGA_IN ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__ebufn_4 OUT_PROTECT_GATE ( .A ( FPGA_OUT ) , - .TE_B ( aps_rename_515_ ) , .Z ( SOC_OUT ) , .VPWR ( VDD ) , + .TE_B ( aps_rename_514_ ) , .Z ( SOC_OUT ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_107 ( .A ( BUF_net_109 ) , .Y ( SOC_DIR ) , +sky130_fd_sc_hd__inv_8 BINV_R_106 ( .A ( BUF_net_107 ) , .Y ( SOC_DIR ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_109 ( .A ( aps_rename_515_ ) , - .Y ( BUF_net_109 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_107 ( .A ( aps_rename_514_ ) , + .Y ( BUF_net_107 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -19135,19 +20305,19 @@ input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__or2b_4 ISOL_EN_GATE ( .A ( FPGA_DIR ) , .B_N ( IO_ISOL_N ) , - .X ( aps_rename_514_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 INV_SOC_DIR ( .A ( aps_rename_514_ ) , - .Y ( SOC_DIR_N ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__ebufn_4 IN_PROTECT_GATE ( .A ( SOC_IN ) , - .TE_B ( SOC_DIR_N ) , .Z ( FPGA_IN ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__ebufn_4 OUT_PROTECT_GATE ( .A ( FPGA_OUT ) , - .TE_B ( aps_rename_514_ ) , .Z ( SOC_OUT ) , .VPWR ( VDD ) , +sky130_fd_sc_hd__nand2b_1 ISOL_EN_GATE ( .A_N ( FPGA_DIR ) , + .B ( IO_ISOL_N ) , .Y ( aps_rename_513_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_103 ( .A ( BUF_net_106 ) , .Y ( SOC_DIR ) , +sky130_fd_sc_hd__ebufn_4 IN_PROTECT_GATE ( .A ( SOC_IN ) , + .TE_B ( BUF_net_105 ) , .Z ( FPGA_IN ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__ebufn_4 OUT_PROTECT_GATE ( .A ( FPGA_OUT ) , + .TE_B ( BUF_net_103 ) , .Z ( SOC_OUT ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_102 ( .A ( BUF_net_105 ) , .Y ( SOC_DIR ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_106 ( .A ( aps_rename_514_ ) , - .Y ( BUF_net_106 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_4 BINV_R_103 ( .A ( BUF_net_105 ) , .Y ( BUF_net_103 ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_105 ( .A ( aps_rename_513_ ) , + .Y ( BUF_net_105 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -19254,18 +20424,20 @@ supply1 VDD ; supply0 VSS ; sky130_fd_sc_hd__nand2b_1 ISOL_EN_GATE ( .A_N ( FPGA_DIR ) , - .B ( IO_ISOL_N ) , .Y ( aps_rename_513_ ) , .VPWR ( VDD ) , + .B ( IO_ISOL_N ) , .Y ( aps_rename_512_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 INV_SOC_DIR ( .A ( aps_rename_512_ ) , + .Y ( SOC_DIR_N ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__ebufn_4 IN_PROTECT_GATE ( .A ( SOC_IN ) , - .TE_B ( BUF_net_102 ) , .Z ( FPGA_IN ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .TE_B ( SOC_DIR_N ) , .Z ( FPGA_IN ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__ebufn_4 OUT_PROTECT_GATE ( .A ( FPGA_OUT ) , - .TE_B ( BUF_net_99 ) , .Z ( SOC_OUT ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_4 BINV_R_99 ( .A ( BUF_net_102 ) , .Y ( BUF_net_99 ) , + .TE_B ( BUF_net_100 ) , .Z ( SOC_OUT ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_98 ( .A ( BUF_net_101 ) , .Y ( SOC_DIR ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_101 ( .A ( BUF_net_102 ) , .Y ( SOC_DIR ) , +sky130_fd_sc_hd__inv_1 BINV_R_101 ( .A ( aps_rename_512_ ) , + .Y ( BUF_net_101 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_4 BINV_R_100 ( .A ( BUF_net_101 ) , .Y ( BUF_net_100 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_102 ( .A ( aps_rename_513_ ) , - .Y ( BUF_net_102 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -19371,21 +20543,21 @@ input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__nand2b_1 ISOL_EN_GATE ( .A_N ( FPGA_DIR ) , - .B ( IO_ISOL_N ) , .Y ( aps_rename_512_ ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 INV_SOC_DIR ( .A ( aps_rename_512_ ) , - .Y ( SOC_DIR_N ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__or2b_4 ISOL_EN_GATE ( .A ( FPGA_DIR ) , .B_N ( IO_ISOL_N ) , + .X ( aps_rename_511_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 INV_SOC_DIR ( .A ( BUF_net_95 ) , .Y ( SOC_DIR_N ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__ebufn_4 IN_PROTECT_GATE ( .A ( SOC_IN ) , .TE_B ( SOC_DIR_N ) , .Z ( FPGA_IN ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__ebufn_4 OUT_PROTECT_GATE ( .A ( FPGA_OUT ) , - .TE_B ( BUF_net_96 ) , .Z ( SOC_OUT ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_4 BINV_R_96 ( .A ( BUF_net_98 ) , .Y ( BUF_net_96 ) , + .TE_B ( aps_rename_511_ ) , .Z ( SOC_OUT ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_95 ( .A ( BUF_net_97 ) , .Y ( BUF_net_95 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_97 ( .A ( BUF_net_98 ) , .Y ( SOC_DIR ) , +sky130_fd_sc_hd__inv_8 BINV_R_96 ( .A ( BUF_net_97 ) , .Y ( SOC_DIR ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_98 ( .A ( aps_rename_512_ ) , - .Y ( BUF_net_98 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_97 ( .A ( aps_rename_511_ ) , + .Y ( BUF_net_97 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -19492,7 +20664,7 @@ supply1 VDD ; supply0 VSS ; sky130_fd_sc_hd__nand2b_1 ISOL_EN_GATE ( .A_N ( FPGA_DIR ) , - .B ( IO_ISOL_N ) , .Y ( aps_rename_511_ ) , .VPWR ( VDD ) , + .B ( IO_ISOL_N ) , .Y ( aps_rename_510_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__inv_1 INV_SOC_DIR ( .A ( BUF_net_93 ) , .Y ( SOC_DIR_N ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -19500,12 +20672,12 @@ sky130_fd_sc_hd__ebufn_4 IN_PROTECT_GATE ( .A ( SOC_IN ) , .TE_B ( SOC_DIR_N ) , .Z ( FPGA_IN ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__ebufn_4 OUT_PROTECT_GATE ( .A ( FPGA_OUT ) , .TE_B ( BUF_net_93 ) , .Z ( SOC_OUT ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_4 BINV_R_93 ( .A ( BUF_net_95 ) , .Y ( BUF_net_93 ) , +sky130_fd_sc_hd__inv_8 BINV_R_92 ( .A ( BUF_net_94 ) , .Y ( SOC_DIR ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_94 ( .A ( BUF_net_95 ) , .Y ( SOC_DIR ) , +sky130_fd_sc_hd__inv_4 BINV_R_93 ( .A ( BUF_net_94 ) , .Y ( BUF_net_93 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_95 ( .A ( aps_rename_511_ ) , - .Y ( BUF_net_95 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_94 ( .A ( aps_rename_510_ ) , + .Y ( BUF_net_94 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -19612,16 +20784,16 @@ supply1 VDD ; supply0 VSS ; sky130_fd_sc_hd__or2b_4 ISOL_EN_GATE ( .A ( FPGA_DIR ) , .B_N ( IO_ISOL_N ) , - .X ( aps_rename_510_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .X ( aps_rename_509_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__ebufn_4 IN_PROTECT_GATE ( .A ( SOC_IN ) , - .TE_B ( BUF_net_92 ) , .Z ( FPGA_IN ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .TE_B ( BUF_net_91 ) , .Z ( FPGA_IN ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__ebufn_4 OUT_PROTECT_GATE ( .A ( FPGA_OUT ) , - .TE_B ( aps_rename_510_ ) , .Z ( SOC_OUT ) , .VPWR ( VDD ) , + .TE_B ( aps_rename_509_ ) , .Z ( SOC_OUT ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_89 ( .A ( BUF_net_92 ) , .Y ( SOC_DIR ) , +sky130_fd_sc_hd__inv_8 BINV_R_90 ( .A ( BUF_net_91 ) , .Y ( SOC_DIR ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_92 ( .A ( aps_rename_510_ ) , - .Y ( BUF_net_92 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_91 ( .A ( aps_rename_509_ ) , + .Y ( BUF_net_91 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -19944,7 +21116,7 @@ input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ropt_net_160 ) , +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ropt_net_155 ) , .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , @@ -19958,20 +21130,20 @@ sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_1 FTB_1__0 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1382 ( .A ( ccff_head[0] ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1376 ( .A ( copt_net_142 ) , + .X ( copt_net_141 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1377 ( .A ( copt_net_143 ) , + .X ( copt_net_142 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1378 ( .A ( ccff_head[0] ) , + .X ( copt_net_143 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1379 ( .A ( copt_net_141 ) , + .X ( copt_net_144 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1380 ( .A ( copt_net_146 ) , .X ( copt_net_145 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1383 ( .A ( copt_net_145 ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1381 ( .A ( copt_net_144 ) , .X ( copt_net_146 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1384 ( .A ( copt_net_146 ) , - .X ( copt_net_147 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1385 ( .A ( copt_net_147 ) , - .X ( copt_net_148 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1386 ( .A ( copt_net_148 ) , - .X ( copt_net_149 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1387 ( .A ( copt_net_149 ) , - .X ( copt_net_150 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1395 ( .A ( copt_net_150 ) , - .X ( ropt_net_160 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1389 ( .A ( copt_net_145 ) , + .X ( ropt_net_155 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -19985,15 +21157,20 @@ input VDD ; input VSS ; input p0 ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -20006,15 +21183,20 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -20027,15 +21209,20 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -20048,15 +21235,20 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -20188,15 +21380,20 @@ input VDD ; input VSS ; input p0 ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -20209,15 +21406,20 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -20230,15 +21432,20 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -20251,15 +21458,20 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -20347,7 +21559,7 @@ supply1 VDD ; supply0 VSS ; sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_1_0_ ( - .A ( mux_2level_basis_input4_mem4_3_out[0] ) , .X ( aps_rename_509_ ) , + .A ( mux_2level_basis_input4_mem4_3_out[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; cbx_1__0__local_encoder2to4_14 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , .data ( local_encoder2to4_0_data ) , @@ -20378,10 +21590,6 @@ cbx_1__0__mux_2level_basis_input4_mem4_31 mux_l2_in_0_ ( .mem_inv ( local_encoder2to4_1_data_inv ) , .out ( mux_2level_basis_input4_mem4_3_out ) , .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_127 ( .A ( BUF_net_128 ) , .Y ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_128 ( .A ( aps_rename_509_ ) , - .Y ( BUF_net_128 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -20395,15 +21603,20 @@ input VDD ; input VSS ; input p0 ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -20416,15 +21629,20 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -20437,15 +21655,20 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -20458,15 +21681,20 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -20554,7 +21782,7 @@ supply1 VDD ; supply0 VSS ; sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_1_0_ ( - .A ( mux_2level_basis_input4_mem4_3_out[0] ) , .X ( out[0] ) , + .A ( mux_2level_basis_input4_mem4_3_out[0] ) , .X ( aps_rename_508_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; cbx_1__0__local_encoder2to4_12 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , .data ( local_encoder2to4_0_data ) , @@ -20585,6 +21813,10 @@ cbx_1__0__mux_2level_basis_input4_mem4_27 mux_l2_in_0_ ( .mem_inv ( local_encoder2to4_1_data_inv ) , .out ( mux_2level_basis_input4_mem4_3_out ) , .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_125 ( .A ( BUF_net_126 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_126 ( .A ( aps_rename_508_ ) , + .Y ( BUF_net_126 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -20598,15 +21830,20 @@ input VDD ; input VSS ; input p0 ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -20619,15 +21856,20 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -20640,15 +21882,20 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -20661,15 +21908,20 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -20757,7 +22009,7 @@ supply1 VDD ; supply0 VSS ; sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_1_0_ ( - .A ( mux_2level_basis_input4_mem4_3_out[0] ) , .X ( out[0] ) , + .A ( mux_2level_basis_input4_mem4_3_out[0] ) , .X ( aps_rename_507_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; cbx_1__0__local_encoder2to4_10 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , .data ( local_encoder2to4_0_data ) , @@ -20788,6 +22040,10 @@ cbx_1__0__mux_2level_basis_input4_mem4_23 mux_l2_in_0_ ( .mem_inv ( local_encoder2to4_1_data_inv ) , .out ( mux_2level_basis_input4_mem4_3_out ) , .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_123 ( .A ( BUF_net_124 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_124 ( .A ( aps_rename_507_ ) , + .Y ( BUF_net_124 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -20801,15 +22057,20 @@ input VDD ; input VSS ; input p0 ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -20822,15 +22083,20 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -20843,15 +22109,20 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -20864,15 +22135,20 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -20959,8 +22235,8 @@ wire [0:0] mux_2level_basis_input4_mem4_3_out ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_1_0_ ( - .A ( mux_2level_basis_input4_mem4_3_out[0] ) , .X ( aps_rename_508_ ) , +sky130_fd_sc_hd__bufbuf_16 sky130_fd_sc_hd__buf_1_0_ ( + .A ( mux_2level_basis_input4_mem4_3_out[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; cbx_1__0__local_encoder2to4_8 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , .data ( local_encoder2to4_0_data ) , @@ -20991,10 +22267,6 @@ cbx_1__0__mux_2level_basis_input4_mem4_19 mux_l2_in_0_ ( .mem_inv ( local_encoder2to4_1_data_inv ) , .out ( mux_2level_basis_input4_mem4_3_out ) , .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_125 ( .A ( BUF_net_126 ) , .Y ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_126 ( .A ( aps_rename_508_ ) , - .Y ( BUF_net_126 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -21008,15 +22280,20 @@ input VDD ; input VSS ; input p0 ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -21029,15 +22306,20 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -21050,15 +22332,20 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -21071,15 +22358,20 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -21167,7 +22459,7 @@ supply1 VDD ; supply0 VSS ; sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_1_0_ ( - .A ( mux_2level_basis_input4_mem4_3_out[0] ) , .X ( out[0] ) , + .A ( mux_2level_basis_input4_mem4_3_out[0] ) , .X ( aps_rename_506_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; cbx_1__0__local_encoder2to4_6 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , .data ( local_encoder2to4_0_data ) , @@ -21198,6 +22490,10 @@ cbx_1__0__mux_2level_basis_input4_mem4_15 mux_l2_in_0_ ( .mem_inv ( local_encoder2to4_1_data_inv ) , .out ( mux_2level_basis_input4_mem4_3_out ) , .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_121 ( .A ( BUF_net_122 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_122 ( .A ( aps_rename_506_ ) , + .Y ( BUF_net_122 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -21211,15 +22507,20 @@ input VDD ; input VSS ; input p0 ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -21232,15 +22533,20 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -21253,15 +22559,20 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -21274,15 +22585,20 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -21369,8 +22685,8 @@ wire [0:0] mux_2level_basis_input4_mem4_3_out ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_1_0_ ( - .A ( mux_2level_basis_input4_mem4_3_out[0] ) , .X ( aps_rename_507_ ) , +sky130_fd_sc_hd__bufbuf_16 sky130_fd_sc_hd__buf_1_0_ ( + .A ( mux_2level_basis_input4_mem4_3_out[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; cbx_1__0__local_encoder2to4_4 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , .data ( local_encoder2to4_0_data ) , @@ -21401,10 +22717,6 @@ cbx_1__0__mux_2level_basis_input4_mem4_11 mux_l2_in_0_ ( .mem_inv ( local_encoder2to4_1_data_inv ) , .out ( mux_2level_basis_input4_mem4_3_out ) , .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_124 ( .A ( aps_rename_507_ ) , - .Y ( BUF_net_124 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_6 BINV_R_133 ( .A ( BUF_net_124 ) , .Y ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -21418,15 +22730,20 @@ input VDD ; input VSS ; input p0 ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -21439,15 +22756,20 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -21460,15 +22782,20 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -21481,15 +22808,20 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -21577,7 +22909,7 @@ supply1 VDD ; supply0 VSS ; sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_1_0_ ( - .A ( mux_2level_basis_input4_mem4_3_out[0] ) , .X ( aps_rename_506_ ) , + .A ( mux_2level_basis_input4_mem4_3_out[0] ) , .X ( aps_rename_505_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; cbx_1__0__local_encoder2to4_2 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , .data ( local_encoder2to4_0_data ) , @@ -21608,10 +22940,10 @@ cbx_1__0__mux_2level_basis_input4_mem4_7 mux_l2_in_0_ ( .mem_inv ( local_encoder2to4_1_data_inv ) , .out ( mux_2level_basis_input4_mem4_3_out ) , .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_6 BINV_R_121 ( .A ( BUF_net_122 ) , .Y ( out[0] ) , +sky130_fd_sc_hd__inv_1 BINV_R_120 ( .A ( aps_rename_505_ ) , + .Y ( BUF_net_120 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_130 ( .A ( BUF_net_120 ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_122 ( .A ( aps_rename_506_ ) , - .Y ( BUF_net_122 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -21625,15 +22957,20 @@ input VDD ; input VSS ; input p0 ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -21646,15 +22983,20 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -21667,15 +23009,20 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -21688,15 +23035,20 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -21783,8 +23135,8 @@ wire [0:0] mux_2level_basis_input4_mem4_3_out ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_1_0_ ( - .A ( mux_2level_basis_input4_mem4_3_out[0] ) , .X ( aps_rename_505_ ) , +sky130_fd_sc_hd__bufbuf_16 sky130_fd_sc_hd__buf_1_0_ ( + .A ( mux_2level_basis_input4_mem4_3_out[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; cbx_1__0__local_encoder2to4_0 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , .data ( local_encoder2to4_0_data ) , @@ -21815,10 +23167,6 @@ cbx_1__0__mux_2level_basis_input4_mem4_3 mux_l2_in_0_ ( .mem_inv ( local_encoder2to4_1_data_inv ) , .out ( mux_2level_basis_input4_mem4_3_out ) , .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_119 ( .A ( BUF_net_120 ) , .Y ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_120 ( .A ( aps_rename_505_ ) , - .Y ( BUF_net_120 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -21947,7 +23295,7 @@ cbx_1__0__mux_2level_size12_0 mux_top_ipin_0 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 , SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) , .out ( bottom_grid_pin_0_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_142 ) ) ; + .p0 ( optlc_net_136 ) ) ; cbx_1__0__mux_2level_size12_1 mux_top_ipin_1 ( .in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[4] , chanx_left_out[4] , chanx_right_out[7] , chanx_left_out[7] , @@ -21957,7 +23305,7 @@ cbx_1__0__mux_2level_size12_1 mux_top_ipin_1 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 , SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 } ) , .out ( bottom_grid_pin_2_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_143 ) ) ; + .p0 ( optlc_net_136 ) ) ; cbx_1__0__mux_2level_size12_2 mux_top_ipin_2 ( .in ( { chanx_right_out[2] , chanx_left_out[2] , chanx_right_out[5] , chanx_left_out[5] , chanx_right_out[8] , chanx_left_out[8] , @@ -21967,7 +23315,7 @@ cbx_1__0__mux_2level_size12_2 mux_top_ipin_2 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_9 , SYNOPSYS_UNCONNECTED_10 , SYNOPSYS_UNCONNECTED_11 , SYNOPSYS_UNCONNECTED_12 } ) , .out ( bottom_grid_pin_4_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_143 ) ) ; + .p0 ( optlc_net_138 ) ) ; cbx_1__0__mux_2level_size12_3 mux_top_ipin_3 ( .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[3] , chanx_left_out[3] , chanx_right_out[9] , chanx_left_out[9] , @@ -21976,8 +23324,8 @@ cbx_1__0__mux_2level_size12_3 mux_top_ipin_3 ( .sram ( mux_2level_size12_3_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 , SYNOPSYS_UNCONNECTED_15 , SYNOPSYS_UNCONNECTED_16 } ) , - .out ( { aps_rename_519_ } ) , - .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_141 ) ) ; + .out ( bottom_grid_pin_6_ ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_139 ) ) ; cbx_1__0__mux_2level_size12_4 mux_top_ipin_4 ( .in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[4] , chanx_left_out[4] , chanx_right_out[10] , chanx_left_out[10] , @@ -21987,7 +23335,7 @@ cbx_1__0__mux_2level_size12_4 mux_top_ipin_4 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_17 , SYNOPSYS_UNCONNECTED_18 , SYNOPSYS_UNCONNECTED_19 , SYNOPSYS_UNCONNECTED_20 } ) , .out ( bottom_grid_pin_8_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_141 ) ) ; + .p0 ( optlc_net_138 ) ) ; cbx_1__0__mux_2level_size12_5 mux_top_ipin_5 ( .in ( { chanx_right_out[2] , chanx_left_out[2] , chanx_right_out[5] , chanx_left_out[5] , chanx_right_out[11] , chanx_left_out[11] , @@ -21996,8 +23344,8 @@ cbx_1__0__mux_2level_size12_5 mux_top_ipin_5 ( .sram ( mux_2level_size12_5_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_21 , SYNOPSYS_UNCONNECTED_22 , SYNOPSYS_UNCONNECTED_23 , SYNOPSYS_UNCONNECTED_24 } ) , - .out ( { aps_rename_520_ } ) , - .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_142 ) ) ; + .out ( bottom_grid_pin_10_ ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_138 ) ) ; cbx_1__0__mux_2level_size12_6 mux_top_ipin_6 ( .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[3] , chanx_left_out[3] , chanx_right_out[6] , chanx_left_out[6] , @@ -22006,8 +23354,8 @@ cbx_1__0__mux_2level_size12_6 mux_top_ipin_6 ( .sram ( mux_2level_size12_6_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_25 , SYNOPSYS_UNCONNECTED_26 , SYNOPSYS_UNCONNECTED_27 , SYNOPSYS_UNCONNECTED_28 } ) , - .out ( { aps_rename_521_ } ) , - .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_143 ) ) ; + .out ( bottom_grid_pin_12_ ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_138 ) ) ; cbx_1__0__mux_2level_size12_7 mux_top_ipin_7 ( .in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[4] , chanx_left_out[4] , chanx_right_out[7] , chanx_left_out[7] , @@ -22016,8 +23364,8 @@ cbx_1__0__mux_2level_size12_7 mux_top_ipin_7 ( .sram ( mux_2level_size12_7_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_29 , SYNOPSYS_UNCONNECTED_30 , SYNOPSYS_UNCONNECTED_31 , SYNOPSYS_UNCONNECTED_32 } ) , - .out ( bottom_grid_pin_14_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_141 ) ) ; + .out ( { aps_rename_518_ } ) , + .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_136 ) ) ; cbx_1__0__mux_2level_size12 mux_top_ipin_8 ( .in ( { chanx_right_out[2] , chanx_left_out[2] , chanx_right_out[5] , chanx_left_out[5] , chanx_right_out[8] , chanx_left_out[8] , @@ -22027,7 +23375,7 @@ cbx_1__0__mux_2level_size12 mux_top_ipin_8 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_33 , SYNOPSYS_UNCONNECTED_34 , SYNOPSYS_UNCONNECTED_35 , SYNOPSYS_UNCONNECTED_36 } ) , .out ( bottom_grid_pin_16_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_142 ) ) ; + .p0 ( optlc_net_137 ) ) ; cbx_1__0__mux_2level_size12_mem_0 mem_top_ipin_0 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( mux_2level_size12_mem_0_ccff_tail ) , @@ -22164,13 +23512,13 @@ cbx_1__0__logical_tile_io_mode_io_ logical_tile_io_mode_io__8 ( sky130_fd_sc_hd__buf_8 pReset_FTB00 ( .A ( pReset_W_in ) , .X ( pReset[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_1 pReset_W_FTB01 ( .A ( pReset_W_in ) , - .X ( aps_rename_522_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__bufbuf_16 pReset_E_FTB01 ( .A ( pReset_W_in ) , - .X ( pReset_E_out ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .X ( aps_rename_519_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 pReset_E_FTB01 ( .A ( pReset_W_in ) , + .X ( net_net_129 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_1 prog_clk_0_FTB00 ( .A ( prog_clk_0_N_in ) , .X ( prog_clk[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__clkbuf_1 prog_clk_0_W_FTB01 ( .A ( prog_clk_0_N_in ) , - .X ( ctsbuf_net_1144 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .X ( ctsbuf_net_1140 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_8 FTB_19__18 ( .A ( chanx_left_in[0] ) , .X ( chanx_right_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_8 FTB_20__19 ( .A ( chanx_left_in[1] ) , @@ -22331,23 +23679,23 @@ sky130_fd_sc_hd__buf_6 FTB_88__87 ( .A ( SC_IN_TOP ) , .X ( SC_OUT_BOT ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_6 FTB_89__88 ( .A ( SC_IN_BOT ) , .X ( SC_OUT_TOP ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_142 ( .LO ( SYNOPSYS_UNCONNECTED_37 ) , - .HI ( optlc_net_141 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_130 ( .A ( aps_rename_522_ ) , - .Y ( BUF_net_130 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_6 BINV_R_135 ( .A ( BUF_net_130 ) , .Y ( pReset_W_out ) , +sky130_fd_sc_hd__conb_1 optlc_138 ( .LO ( SYNOPSYS_UNCONNECTED_37 ) , + .HI ( optlc_net_136 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_128 ( .A ( aps_rename_519_ ) , + .Y ( BUF_net_128 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_129 ( .A ( net_net_129 ) , + .X ( pReset_E_out ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_139 ( .LO ( SYNOPSYS_UNCONNECTED_38 ) , + .HI ( optlc_net_137 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_141 ( .LO ( SYNOPSYS_UNCONNECTED_39 ) , + .HI ( optlc_net_138 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_134 ( .A ( BUF_net_128 ) , .Y ( pReset_W_out ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_144 ( .LO ( SYNOPSYS_UNCONNECTED_38 ) , - .HI ( optlc_net_142 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_146 ( .LO ( SYNOPSYS_UNCONNECTED_39 ) , - .HI ( optlc_net_143 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_6 ZBUF_6_f_inst_147 ( .A ( aps_rename_521_ ) , - .X ( bottom_grid_pin_12_[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_6 ZBUF_6_f_inst_148 ( .A ( aps_rename_519_ ) , - .X ( bottom_grid_pin_6_[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_6 ZBUF_6_f_inst_149 ( .A ( aps_rename_520_ ) , - .X ( bottom_grid_pin_10_[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_6 cts_buf_3651289 ( .A ( ctsbuf_net_1144 ) , +sky130_fd_sc_hd__conb_1 optlc_142 ( .LO ( SYNOPSYS_UNCONNECTED_40 ) , + .HI ( optlc_net_139 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 ZBUF_6_f_inst_143 ( .A ( aps_rename_518_ ) , + .X ( bottom_grid_pin_14_[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__clkbuf_8 cts_buf_3651283 ( .A ( ctsbuf_net_1140 ) , .X ( prog_clk_0_W_out ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -22460,7 +23808,7 @@ input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__mux2_2 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) , +sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -22519,9 +23867,6 @@ wire [0:0] mux_2level_tapbuf_basis_input2_mem1_2_out ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( mux_2level_tapbuf_basis_input2_mem1_2_out[0] ) , .X ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; sb_2__2__mux_2level_tapbuf_basis_input2_mem1_83 mux_l1_in_0_ ( .in ( in[0:1] ) , .mem ( sram[0] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) , @@ -22540,6 +23885,11 @@ sb_2__2__mux_2level_tapbuf_basis_input2_mem1 mux_l2_in_0_ ( .mem_inv ( { SYNOPSYS_UNCONNECTED_4 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_2_out ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_158 ( .A ( BUF_net_159 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_159 ( + .A ( mux_2level_tapbuf_basis_input2_mem1_2_out[0] ) , .Y ( BUF_net_159 ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -22555,7 +23905,7 @@ input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) , +sky130_fd_sc_hd__mux2_2 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -22614,6 +23964,9 @@ wire [0:0] mux_2level_tapbuf_basis_input2_mem1_2_out ; supply1 VDD ; supply0 VSS ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( mux_2level_tapbuf_basis_input2_mem1_2_out[0] ) , .X ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; sb_2__2__mux_2level_tapbuf_basis_input2_mem1_80 mux_l1_in_0_ ( .in ( in[0:1] ) , .mem ( sram[0] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) , @@ -22632,11 +23985,6 @@ sb_2__2__mux_2level_tapbuf_basis_input2_mem1_82 mux_l2_in_0_ ( .mem_inv ( { SYNOPSYS_UNCONNECTED_4 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_2_out ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_172 ( .A ( BUF_net_173 ) , .Y ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_173 ( - .A ( mux_2level_tapbuf_basis_input2_mem1_2_out[0] ) , .Y ( BUF_net_173 ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -22824,10 +24172,10 @@ sb_2__2__mux_2level_tapbuf_basis_input2_mem1_76 mux_l2_in_0_ ( .mem_inv ( { SYNOPSYS_UNCONNECTED_4 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_2_out ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_170 ( .A ( BUF_net_171 ) , .Y ( out[0] ) , +sky130_fd_sc_hd__inv_8 BINV_R_156 ( .A ( BUF_net_157 ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_171 ( - .A ( mux_2level_tapbuf_basis_input2_mem1_2_out[0] ) , .Y ( BUF_net_171 ) , +sky130_fd_sc_hd__inv_1 BINV_R_157 ( + .A ( mux_2level_tapbuf_basis_input2_mem1_2_out[0] ) , .Y ( BUF_net_157 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -22842,7 +24190,6 @@ output [0:1] mem_out ; input VDD ; input VSS ; -wire copt_net_180 ; supply1 VDD ; supply0 VSS ; @@ -22850,22 +24197,10 @@ sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( copt_net_180 ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_6 FTB_73__72 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1376 ( .A ( copt_net_182 ) , - .X ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1377 ( .A ( copt_net_180 ) , - .X ( copt_net_181 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1378 ( .A ( copt_net_185 ) , - .X ( copt_net_182 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1379 ( .A ( copt_net_184 ) , - .X ( copt_net_183 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1380 ( .A ( copt_net_181 ) , - .X ( copt_net_184 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1381 ( .A ( copt_net_183 ) , - .X ( copt_net_185 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -23867,10 +25202,10 @@ sb_2__2__mux_2level_tapbuf_basis_input2_mem1_71 mux_l2_in_0_ ( .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_168 ( .A ( BUF_net_169 ) , .Y ( out[0] ) , +sky130_fd_sc_hd__inv_8 BINV_R_154 ( .A ( BUF_net_155 ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_169 ( - .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_169 ) , +sky130_fd_sc_hd__inv_1 BINV_R_155 ( + .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_155 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -23939,10 +25274,10 @@ sb_2__2__mux_2level_tapbuf_basis_input2_mem1_69 mux_l2_in_0_ ( .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_166 ( .A ( BUF_net_167 ) , .Y ( out[0] ) , +sky130_fd_sc_hd__inv_8 BINV_R_152 ( .A ( BUF_net_153 ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_167 ( - .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_167 ) , +sky130_fd_sc_hd__inv_1 BINV_R_153 ( + .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_153 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -24011,10 +25346,10 @@ sb_2__2__mux_2level_tapbuf_basis_input2_mem1_67 mux_l2_in_0_ ( .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_164 ( .A ( BUF_net_165 ) , .Y ( out[0] ) , +sky130_fd_sc_hd__inv_8 BINV_R_150 ( .A ( BUF_net_151 ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_165 ( - .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_165 ) , +sky130_fd_sc_hd__inv_1 BINV_R_151 ( + .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_151 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -24032,7 +25367,7 @@ input p0 ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , +sky130_fd_sc_hd__mux2_2 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -24071,6 +25406,9 @@ wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ; supply1 VDD ; supply0 VSS ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; sb_2__2__mux_2level_tapbuf_basis_input2_mem1_64 mux_l1_in_0_ ( .in ( in ) , .mem ( sram[0] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) , @@ -24083,11 +25421,6 @@ sb_2__2__mux_2level_tapbuf_basis_input2_mem1_65 mux_l2_in_0_ ( .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_162 ( .A ( BUF_net_163 ) , .Y ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_163 ( - .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_163 ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -24155,10 +25488,10 @@ sb_2__2__mux_2level_tapbuf_basis_input2_mem1_63 mux_l2_in_0_ ( .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_160 ( .A ( BUF_net_161 ) , .Y ( out[0] ) , +sky130_fd_sc_hd__inv_8 BINV_R_148 ( .A ( BUF_net_149 ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_161 ( - .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_161 ) , +sky130_fd_sc_hd__inv_1 BINV_R_149 ( + .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_149 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -24227,10 +25560,10 @@ sb_2__2__mux_2level_tapbuf_basis_input2_mem1_61 mux_l2_in_0_ ( .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_158 ( .A ( BUF_net_159 ) , .Y ( out[0] ) , +sky130_fd_sc_hd__inv_8 BINV_R_146 ( .A ( BUF_net_147 ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_159 ( - .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_159 ) , +sky130_fd_sc_hd__inv_1 BINV_R_147 ( + .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_147 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -24299,10 +25632,10 @@ sb_2__2__mux_2level_tapbuf_basis_input2_mem1_59 mux_l2_in_0_ ( .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_156 ( .A ( BUF_net_157 ) , .Y ( out[0] ) , +sky130_fd_sc_hd__inv_8 BINV_R_144 ( .A ( BUF_net_145 ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_157 ( - .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_157 ) , +sky130_fd_sc_hd__inv_1 BINV_R_145 ( + .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_145 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -24371,10 +25704,10 @@ sb_2__2__mux_2level_tapbuf_basis_input2_mem1_57 mux_l2_in_0_ ( .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_154 ( .A ( BUF_net_155 ) , .Y ( out[0] ) , +sky130_fd_sc_hd__inv_8 BINV_R_142 ( .A ( BUF_net_143 ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_155 ( - .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_155 ) , +sky130_fd_sc_hd__inv_1 BINV_R_143 ( + .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_143 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -24443,10 +25776,10 @@ sb_2__2__mux_2level_tapbuf_basis_input2_mem1_55 mux_l2_in_0_ ( .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_152 ( .A ( BUF_net_153 ) , .Y ( out[0] ) , +sky130_fd_sc_hd__inv_8 BINV_R_140 ( .A ( BUF_net_141 ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_153 ( - .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_153 ) , +sky130_fd_sc_hd__inv_1 BINV_R_141 ( + .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_141 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -24515,10 +25848,10 @@ sb_2__2__mux_2level_tapbuf_basis_input2_mem1_53 mux_l2_in_0_ ( .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_150 ( .A ( BUF_net_151 ) , .Y ( out[0] ) , +sky130_fd_sc_hd__inv_8 BINV_R_138 ( .A ( BUF_net_139 ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_151 ( - .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_151 ) , +sky130_fd_sc_hd__inv_1 BINV_R_139 ( + .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_139 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -24587,10 +25920,10 @@ sb_2__2__mux_2level_tapbuf_basis_input2_mem1_51 mux_l2_in_0_ ( .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_148 ( .A ( BUF_net_149 ) , .Y ( out[0] ) , +sky130_fd_sc_hd__inv_8 BINV_R_136 ( .A ( BUF_net_137 ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_149 ( - .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_149 ) , +sky130_fd_sc_hd__inv_1 BINV_R_137 ( + .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_137 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -24608,7 +25941,7 @@ input p0 ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , +sky130_fd_sc_hd__mux2_2 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -24659,10 +25992,8 @@ sb_2__2__mux_2level_tapbuf_basis_input2_mem1_49 mux_l2_in_0_ ( .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_146 ( .A ( BUF_net_147 ) , .Y ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_147 ( - .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_147 ) , +sky130_fd_sc_hd__buf_6 BUFT_RR_135 ( + .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -24680,7 +26011,7 @@ input p0 ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , +sky130_fd_sc_hd__mux2_2 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -24731,10 +26062,8 @@ sb_2__2__mux_2level_tapbuf_basis_input2_mem1_47 mux_l2_in_0_ ( .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_144 ( .A ( BUF_net_145 ) , .Y ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_145 ( - .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_145 ) , +sky130_fd_sc_hd__buf_6 BUFT_RR_134 ( + .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -24791,9 +26120,6 @@ wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; sb_2__2__mux_2level_tapbuf_basis_input2_mem1_44 mux_l1_in_0_ ( .in ( in ) , .mem ( sram[0] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) , @@ -24806,6 +26132,9 @@ sb_2__2__mux_2level_tapbuf_basis_input2_mem1_45 mux_l2_in_0_ ( .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_133 ( + .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -24873,10 +26202,10 @@ sb_2__2__mux_2level_tapbuf_basis_input2_mem1_43 mux_l2_in_0_ ( .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_142 ( .A ( BUF_net_143 ) , .Y ( out[0] ) , +sky130_fd_sc_hd__inv_8 BINV_R_131 ( .A ( BUF_net_132 ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_143 ( - .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_143 ) , +sky130_fd_sc_hd__inv_1 BINV_R_132 ( + .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_132 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -24933,9 +26262,6 @@ wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; sb_2__2__mux_2level_tapbuf_basis_input2_mem1_40 mux_l1_in_0_ ( .in ( in ) , .mem ( sram[0] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) , @@ -24948,6 +26274,9 @@ sb_2__2__mux_2level_tapbuf_basis_input2_mem1_41 mux_l2_in_0_ ( .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_130 ( + .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -25015,10 +26344,10 @@ sb_2__2__mux_2level_tapbuf_basis_input2_mem1_39 mux_l2_in_0_ ( .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_140 ( .A ( BUF_net_141 ) , .Y ( out[0] ) , +sky130_fd_sc_hd__inv_8 BINV_R_128 ( .A ( BUF_net_129 ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_141 ( - .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_141 ) , +sky130_fd_sc_hd__inv_1 BINV_R_129 ( + .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_129 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -25087,10 +26416,10 @@ sb_2__2__mux_2level_tapbuf_basis_input2_mem1_37 mux_l2_in_0_ ( .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_138 ( .A ( BUF_net_139 ) , .Y ( out[0] ) , +sky130_fd_sc_hd__inv_8 BINV_R_126 ( .A ( BUF_net_127 ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_139 ( - .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_139 ) , +sky130_fd_sc_hd__inv_1 BINV_R_127 ( + .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_127 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -25159,10 +26488,10 @@ sb_2__2__mux_2level_tapbuf_basis_input2_mem1_35 mux_l2_in_0_ ( .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_136 ( .A ( BUF_net_137 ) , .Y ( out[0] ) , +sky130_fd_sc_hd__inv_8 BINV_R_124 ( .A ( BUF_net_125 ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_137 ( - .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_137 ) , +sky130_fd_sc_hd__inv_1 BINV_R_125 ( + .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_125 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -25231,10 +26560,10 @@ sb_2__2__mux_2level_tapbuf_basis_input2_mem1_33 mux_l2_in_0_ ( .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_134 ( .A ( BUF_net_135 ) , .Y ( out[0] ) , +sky130_fd_sc_hd__inv_8 BINV_R_122 ( .A ( BUF_net_123 ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_135 ( - .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_135 ) , +sky130_fd_sc_hd__inv_1 BINV_R_123 ( + .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_123 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -25303,10 +26632,10 @@ sb_2__2__mux_2level_tapbuf_basis_input2_mem1_31 mux_l2_in_0_ ( .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_132 ( .A ( BUF_net_133 ) , .Y ( out[0] ) , +sky130_fd_sc_hd__inv_8 BINV_R_120 ( .A ( BUF_net_121 ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_133 ( - .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_133 ) , +sky130_fd_sc_hd__inv_1 BINV_R_121 ( + .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_121 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -25375,10 +26704,10 @@ sb_2__2__mux_2level_tapbuf_basis_input2_mem1_29 mux_l2_in_0_ ( .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_130 ( .A ( BUF_net_131 ) , .Y ( out[0] ) , +sky130_fd_sc_hd__inv_8 BINV_R_118 ( .A ( BUF_net_119 ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_131 ( - .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_131 ) , +sky130_fd_sc_hd__inv_1 BINV_R_119 ( + .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_119 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -25396,7 +26725,7 @@ input p0 ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , +sky130_fd_sc_hd__mux2_2 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -25435,6 +26764,9 @@ wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ; supply1 VDD ; supply0 VSS ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; sb_2__2__mux_2level_tapbuf_basis_input2_mem1_26 mux_l1_in_0_ ( .in ( in ) , .mem ( sram[0] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) , @@ -25447,11 +26779,6 @@ sb_2__2__mux_2level_tapbuf_basis_input2_mem1_27 mux_l2_in_0_ ( .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_128 ( .A ( BUF_net_129 ) , .Y ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_129 ( - .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_129 ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -25519,10 +26846,10 @@ sb_2__2__mux_2level_tapbuf_basis_input2_mem1_25 mux_l2_in_0_ ( .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_126 ( .A ( BUF_net_127 ) , .Y ( out[0] ) , +sky130_fd_sc_hd__inv_8 BINV_R_116 ( .A ( BUF_net_117 ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_127 ( - .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_127 ) , +sky130_fd_sc_hd__inv_1 BINV_R_117 ( + .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_117 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -25540,7 +26867,7 @@ input p0 ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , +sky130_fd_sc_hd__mux2_2 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -25591,10 +26918,8 @@ sb_2__2__mux_2level_tapbuf_basis_input2_mem1_23 mux_l2_in_0_ ( .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_124 ( .A ( BUF_net_125 ) , .Y ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_125 ( - .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_125 ) , +sky130_fd_sc_hd__buf_6 BUFT_RR_115 ( + .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -25651,6 +26976,9 @@ wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ; supply1 VDD ; supply0 VSS ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; sb_2__2__mux_2level_tapbuf_basis_input2_mem1_20 mux_l1_in_0_ ( .in ( in ) , .mem ( sram[0] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) , @@ -25663,11 +26991,6 @@ sb_2__2__mux_2level_tapbuf_basis_input2_mem1_21 mux_l2_in_0_ ( .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_122 ( .A ( BUF_net_123 ) , .Y ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_123 ( - .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_123 ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -25684,7 +27007,7 @@ input p0 ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , +sky130_fd_sc_hd__mux2_2 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -25723,9 +27046,6 @@ wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; sb_2__2__mux_2level_tapbuf_basis_input2_mem1_18 mux_l1_in_0_ ( .in ( in ) , .mem ( sram[0] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) , @@ -25738,6 +27058,9 @@ sb_2__2__mux_2level_tapbuf_basis_input2_mem1_19 mux_l2_in_0_ ( .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_114 ( + .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -25805,10 +27128,10 @@ sb_2__2__mux_2level_tapbuf_basis_input2_mem1_17 mux_l2_in_0_ ( .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_120 ( .A ( BUF_net_121 ) , .Y ( out[0] ) , +sky130_fd_sc_hd__inv_8 BINV_R_112 ( .A ( BUF_net_113 ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_121 ( - .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_121 ) , +sky130_fd_sc_hd__inv_1 BINV_R_113 ( + .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_113 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -25877,10 +27200,10 @@ sb_2__2__mux_2level_tapbuf_basis_input2_mem1_15 mux_l2_in_0_ ( .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_118 ( .A ( BUF_net_119 ) , .Y ( out[0] ) , +sky130_fd_sc_hd__inv_8 BINV_R_110 ( .A ( BUF_net_111 ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_119 ( - .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_119 ) , +sky130_fd_sc_hd__inv_1 BINV_R_111 ( + .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_111 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -25937,6 +27260,9 @@ wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ; supply1 VDD ; supply0 VSS ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; sb_2__2__mux_2level_tapbuf_basis_input2_mem1_12 mux_l1_in_0_ ( .in ( in ) , .mem ( sram[0] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) , @@ -25949,11 +27275,6 @@ sb_2__2__mux_2level_tapbuf_basis_input2_mem1_13 mux_l2_in_0_ ( .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_116 ( .A ( BUF_net_117 ) , .Y ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_117 ( - .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_117 ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -26021,10 +27342,10 @@ sb_2__2__mux_2level_tapbuf_basis_input2_mem1_11 mux_l2_in_0_ ( .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_114 ( .A ( BUF_net_115 ) , .Y ( out[0] ) , +sky130_fd_sc_hd__inv_8 BINV_R_108 ( .A ( BUF_net_109 ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_115 ( - .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_115 ) , +sky130_fd_sc_hd__inv_1 BINV_R_109 ( + .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_109 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -26081,6 +27402,9 @@ wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ; supply1 VDD ; supply0 VSS ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; sb_2__2__mux_2level_tapbuf_basis_input2_mem1_8 mux_l1_in_0_ ( .in ( in ) , .mem ( sram[0] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) , @@ -26093,11 +27417,6 @@ sb_2__2__mux_2level_tapbuf_basis_input2_mem1_9 mux_l2_in_0_ ( .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_112 ( .A ( BUF_net_113 ) , .Y ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_113 ( - .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_113 ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -26153,9 +27472,6 @@ wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; sb_2__2__mux_2level_tapbuf_basis_input2_mem1_6 mux_l1_in_0_ ( .in ( in ) , .mem ( sram[0] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) , @@ -26168,6 +27484,9 @@ sb_2__2__mux_2level_tapbuf_basis_input2_mem1_7 mux_l2_in_0_ ( .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_107 ( + .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -26235,10 +27554,10 @@ sb_2__2__mux_2level_tapbuf_basis_input2_mem1_5 mux_l2_in_0_ ( .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_110 ( .A ( BUF_net_111 ) , .Y ( out[0] ) , +sky130_fd_sc_hd__inv_8 BINV_R_105 ( .A ( BUF_net_106 ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_111 ( - .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_111 ) , +sky130_fd_sc_hd__inv_1 BINV_R_106 ( + .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_106 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -26295,6 +27614,9 @@ wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ; supply1 VDD ; supply0 VSS ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; sb_2__2__mux_2level_tapbuf_basis_input2_mem1_2 mux_l1_in_0_ ( .in ( in ) , .mem ( sram[0] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) , @@ -26307,9 +27629,6 @@ sb_2__2__mux_2level_tapbuf_basis_input2_mem1_3 mux_l2_in_0_ ( .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_109 ( - .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -26377,7 +27696,7 @@ sb_2__2__mux_2level_tapbuf_basis_input2_mem1_1 mux_l2_in_0_ ( .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_108 ( +sky130_fd_sc_hd__buf_6 BUFT_RR_104 ( .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -26726,7 +28045,7 @@ input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ropt_net_200 ) , +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ropt_net_191 ) , .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , @@ -26740,18 +28059,30 @@ sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_1 FTB_25__24 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1429 ( .A ( ccff_head[0] ) , - .X ( ropt_net_197 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1430 ( .A ( ropt_net_201 ) , - .X ( ropt_net_198 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1431 ( .A ( ropt_net_198 ) , - .X ( ropt_net_199 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1432 ( .A ( ropt_net_199 ) , - .X ( ropt_net_200 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1433 ( .A ( ropt_net_202 ) , - .X ( ropt_net_201 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1434 ( .A ( ropt_net_197 ) , - .X ( ropt_net_202 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1344 ( .A ( ccff_head[0] ) , + .X ( copt_net_164 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1345 ( .A ( copt_net_164 ) , + .X ( copt_net_165 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1346 ( .A ( copt_net_165 ) , + .X ( copt_net_166 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1347 ( .A ( copt_net_166 ) , + .X ( copt_net_167 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1348 ( .A ( copt_net_167 ) , + .X ( copt_net_168 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1349 ( .A ( ropt_net_195 ) , + .X ( copt_net_169 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1367 ( .A ( copt_net_169 ) , + .X ( ropt_net_190 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1368 ( .A ( ropt_net_192 ) , + .X ( ropt_net_191 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_2 ropt_h_inst_1369 ( .A ( ropt_net_190 ) , + .X ( ropt_net_192 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1370 ( .A ( copt_net_168 ) , + .X ( ropt_net_193 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1371 ( .A ( ropt_net_193 ) , + .X ( ropt_net_194 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1372 ( .A ( ropt_net_194 ) , + .X ( ropt_net_195 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -26765,13 +28096,16 @@ input VDD ; input VSS ; input p0 ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -26784,13 +28118,16 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -26881,10 +28218,10 @@ sb_2__2__mux_2level_tapbuf_basis_input3_mem3 mux_l2_in_0_ ( .mem_inv ( local_encoder2to3_1_data_inv ) , .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_106 ( .A ( BUF_net_107 ) , .Y ( out[0] ) , +sky130_fd_sc_hd__inv_8 BINV_R_102 ( .A ( BUF_net_103 ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_107 ( - .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_107 ) , +sky130_fd_sc_hd__inv_1 BINV_R_103 ( + .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_103 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -26899,13 +28236,16 @@ input VDD ; input VSS ; input p0 ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -26918,13 +28258,16 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -27015,10 +28358,10 @@ sb_2__2__mux_2level_tapbuf_basis_input3_mem3_21 mux_l2_in_0_ ( .mem_inv ( local_encoder2to3_1_data_inv ) , .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_104 ( .A ( BUF_net_105 ) , .Y ( out[0] ) , +sky130_fd_sc_hd__inv_8 BINV_R_100 ( .A ( BUF_net_101 ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_105 ( - .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_105 ) , +sky130_fd_sc_hd__inv_1 BINV_R_101 ( + .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_101 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -27033,13 +28376,16 @@ input VDD ; input VSS ; input p0 ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -27052,13 +28398,16 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -27149,10 +28498,10 @@ sb_2__2__mux_2level_tapbuf_basis_input3_mem3_19 mux_l2_in_0_ ( .mem_inv ( local_encoder2to3_1_data_inv ) , .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_102 ( .A ( BUF_net_103 ) , .Y ( out[0] ) , +sky130_fd_sc_hd__inv_8 BINV_R_98 ( .A ( BUF_net_99 ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_103 ( - .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_103 ) , +sky130_fd_sc_hd__inv_1 BINV_R_99 ( + .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_99 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -27167,13 +28516,16 @@ input VDD ; input VSS ; input p0 ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -27186,13 +28538,16 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -27283,10 +28638,10 @@ sb_2__2__mux_2level_tapbuf_basis_input3_mem3_17 mux_l2_in_0_ ( .mem_inv ( local_encoder2to3_1_data_inv ) , .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_100 ( .A ( BUF_net_101 ) , .Y ( out[0] ) , +sky130_fd_sc_hd__inv_8 BINV_R_96 ( .A ( BUF_net_97 ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_101 ( - .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_101 ) , +sky130_fd_sc_hd__inv_1 BINV_R_97 ( + .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_97 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -27301,13 +28656,16 @@ input VDD ; input VSS ; input p0 ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -27320,13 +28678,16 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -27417,10 +28778,10 @@ sb_2__2__mux_2level_tapbuf_basis_input3_mem3_15 mux_l2_in_0_ ( .mem_inv ( local_encoder2to3_1_data_inv ) , .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_98 ( .A ( BUF_net_99 ) , .Y ( out[0] ) , +sky130_fd_sc_hd__inv_8 BINV_R_94 ( .A ( BUF_net_95 ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_99 ( - .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_99 ) , +sky130_fd_sc_hd__inv_1 BINV_R_95 ( + .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_95 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -27435,13 +28796,16 @@ input VDD ; input VSS ; input p0 ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -27454,13 +28818,16 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -27551,10 +28918,10 @@ sb_2__2__mux_2level_tapbuf_basis_input3_mem3_13 mux_l2_in_0_ ( .mem_inv ( local_encoder2to3_1_data_inv ) , .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_96 ( .A ( BUF_net_97 ) , .Y ( out[0] ) , +sky130_fd_sc_hd__inv_8 BINV_R_92 ( .A ( BUF_net_93 ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_97 ( - .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_97 ) , +sky130_fd_sc_hd__inv_1 BINV_R_93 ( + .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_93 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -27569,13 +28936,16 @@ input VDD ; input VSS ; input p0 ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -27588,13 +28958,16 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -27685,10 +29058,10 @@ sb_2__2__mux_2level_tapbuf_basis_input3_mem3_11 mux_l2_in_0_ ( .mem_inv ( local_encoder2to3_1_data_inv ) , .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_94 ( .A ( BUF_net_95 ) , .Y ( out[0] ) , +sky130_fd_sc_hd__inv_8 BINV_R_90 ( .A ( BUF_net_91 ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_95 ( - .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_95 ) , +sky130_fd_sc_hd__inv_1 BINV_R_91 ( + .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_91 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -27703,13 +29076,16 @@ input VDD ; input VSS ; input p0 ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -27722,13 +29098,16 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -27819,10 +29198,10 @@ sb_2__2__mux_2level_tapbuf_basis_input3_mem3_9 mux_l2_in_0_ ( .mem_inv ( local_encoder2to3_1_data_inv ) , .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_92 ( .A ( BUF_net_93 ) , .Y ( out[0] ) , +sky130_fd_sc_hd__inv_8 BINV_R_88 ( .A ( BUF_net_89 ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_93 ( - .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_93 ) , +sky130_fd_sc_hd__inv_1 BINV_R_89 ( + .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_89 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -27837,13 +29216,16 @@ input VDD ; input VSS ; input p0 ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -27856,13 +29238,16 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -27953,10 +29338,10 @@ sb_2__2__mux_2level_tapbuf_basis_input3_mem3_7 mux_l2_in_0_ ( .mem_inv ( local_encoder2to3_1_data_inv ) , .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_90 ( .A ( BUF_net_91 ) , .Y ( out[0] ) , +sky130_fd_sc_hd__inv_8 BINV_R_86 ( .A ( BUF_net_87 ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_91 ( - .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_91 ) , +sky130_fd_sc_hd__inv_1 BINV_R_87 ( + .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_87 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -27971,13 +29356,16 @@ input VDD ; input VSS ; input p0 ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -27990,13 +29378,16 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -28087,7 +29478,7 @@ sb_2__2__mux_2level_tapbuf_basis_input3_mem3_5 mux_l2_in_0_ ( .mem_inv ( local_encoder2to3_1_data_inv ) , .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_89 ( +sky130_fd_sc_hd__buf_6 BUFT_RR_85 ( .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -28103,13 +29494,16 @@ input VDD ; input VSS ; input p0 ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -28122,13 +29516,16 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -28201,6 +29598,9 @@ wire [0:0] mux_2level_tapbuf_basis_input3_mem3_1_out ; supply1 VDD ; supply0 VSS ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .X ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; sb_2__2__local_encoder2to3_2 local_encoder2to3_0_ ( .addr ( sram[0:1] ) , .data ( local_encoder2to3_0_data ) , .data_inv ( local_encoder2to3_0_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; @@ -28219,11 +29619,6 @@ sb_2__2__mux_2level_tapbuf_basis_input3_mem3_3 mux_l2_in_0_ ( .mem_inv ( local_encoder2to3_1_data_inv ) , .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_87 ( .A ( BUF_net_88 ) , .Y ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_88 ( - .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_88 ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -28237,13 +29632,16 @@ input VDD ; input VSS ; input p0 ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -28256,13 +29654,16 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -28335,6 +29736,9 @@ wire [0:0] mux_2level_tapbuf_basis_input3_mem3_1_out ; supply1 VDD ; supply0 VSS ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .X ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; sb_2__2__local_encoder2to3_0 local_encoder2to3_0_ ( .addr ( sram[0:1] ) , .data ( local_encoder2to3_0_data ) , .data_inv ( local_encoder2to3_0_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; @@ -28353,11 +29757,6 @@ sb_2__2__mux_2level_tapbuf_basis_input3_mem3_1 mux_l2_in_0_ ( .mem_inv ( local_encoder2to3_1_data_inv ) , .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_85 ( .A ( BUF_net_86 ) , .Y ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_86 ( - .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_86 ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -28524,7 +29923,7 @@ sb_2__2__mux_2level_tapbuf_size4_0 mux_bottom_track_1 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 , SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) , .out ( chany_bottom_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_178 ) ) ; + .p0 ( optlc_net_162 ) ) ; sb_2__2__mux_2level_tapbuf_size4_1 mux_bottom_track_3 ( .in ( { bottom_left_grid_pin_44_[0] , bottom_left_grid_pin_47_[0] , bottom_left_grid_pin_50_[0] , chanx_left_in[2] } ) , @@ -28532,7 +29931,7 @@ sb_2__2__mux_2level_tapbuf_size4_1 mux_bottom_track_3 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 , SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 } ) , .out ( chany_bottom_out[1] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_178 ) ) ; + .p0 ( optlc_net_162 ) ) ; sb_2__2__mux_2level_tapbuf_size4_2 mux_bottom_track_5 ( .in ( { bottom_left_grid_pin_45_[0] , bottom_left_grid_pin_48_[0] , bottom_left_grid_pin_51_[0] , chanx_left_in[3] } ) , @@ -28540,7 +29939,7 @@ sb_2__2__mux_2level_tapbuf_size4_2 mux_bottom_track_5 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_9 , SYNOPSYS_UNCONNECTED_10 , SYNOPSYS_UNCONNECTED_11 , SYNOPSYS_UNCONNECTED_12 } ) , .out ( chany_bottom_out[2] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_174 ) ) ; + .p0 ( optlc_net_162 ) ) ; sb_2__2__mux_2level_tapbuf_size4_3 mux_bottom_track_7 ( .in ( { bottom_right_grid_pin_1_[0] , bottom_left_grid_pin_46_[0] , bottom_left_grid_pin_49_[0] , chanx_left_in[4] } ) , @@ -28548,7 +29947,7 @@ sb_2__2__mux_2level_tapbuf_size4_3 mux_bottom_track_7 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 , SYNOPSYS_UNCONNECTED_15 , SYNOPSYS_UNCONNECTED_16 } ) , .out ( chany_bottom_out[3] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_178 ) ) ; + .p0 ( optlc_net_162 ) ) ; sb_2__2__mux_2level_tapbuf_size4_4 mux_bottom_track_9 ( .in ( { bottom_left_grid_pin_44_[0] , bottom_left_grid_pin_47_[0] , bottom_left_grid_pin_50_[0] , chanx_left_in[5] } ) , @@ -28556,7 +29955,7 @@ sb_2__2__mux_2level_tapbuf_size4_4 mux_bottom_track_9 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_17 , SYNOPSYS_UNCONNECTED_18 , SYNOPSYS_UNCONNECTED_19 , SYNOPSYS_UNCONNECTED_20 } ) , .out ( chany_bottom_out[4] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_177 ) ) ; + .p0 ( optlc_net_160 ) ) ; sb_2__2__mux_2level_tapbuf_size4_5 mux_bottom_track_11 ( .in ( { bottom_left_grid_pin_45_[0] , bottom_left_grid_pin_48_[0] , bottom_left_grid_pin_51_[0] , chanx_left_in[6] } ) , @@ -28564,7 +29963,7 @@ sb_2__2__mux_2level_tapbuf_size4_5 mux_bottom_track_11 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_21 , SYNOPSYS_UNCONNECTED_22 , SYNOPSYS_UNCONNECTED_23 , SYNOPSYS_UNCONNECTED_24 } ) , .out ( chany_bottom_out[5] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_174 ) ) ; + .p0 ( optlc_net_162 ) ) ; sb_2__2__mux_2level_tapbuf_size4_6 mux_left_track_1 ( .in ( { chany_bottom_in[29] , left_top_grid_pin_1_[0] , left_bottom_grid_pin_38_[0] , left_bottom_grid_pin_41_[0] } ) , @@ -28572,7 +29971,7 @@ sb_2__2__mux_2level_tapbuf_size4_6 mux_left_track_1 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_25 , SYNOPSYS_UNCONNECTED_26 , SYNOPSYS_UNCONNECTED_27 , SYNOPSYS_UNCONNECTED_28 } ) , .out ( chanx_left_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_174 ) ) ; + .p0 ( optlc_net_160 ) ) ; sb_2__2__mux_2level_tapbuf_size4_7 mux_left_track_3 ( .in ( { chany_bottom_in[0] , left_bottom_grid_pin_36_[0] , left_bottom_grid_pin_39_[0] , left_bottom_grid_pin_42_[0] } ) , @@ -28580,7 +29979,7 @@ sb_2__2__mux_2level_tapbuf_size4_7 mux_left_track_3 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_29 , SYNOPSYS_UNCONNECTED_30 , SYNOPSYS_UNCONNECTED_31 , SYNOPSYS_UNCONNECTED_32 } ) , .out ( chanx_left_out[1] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_174 ) ) ; + .p0 ( optlc_net_160 ) ) ; sb_2__2__mux_2level_tapbuf_size4_8 mux_left_track_5 ( .in ( { chany_bottom_in[1] , left_bottom_grid_pin_37_[0] , left_bottom_grid_pin_40_[0] , left_bottom_grid_pin_43_[0] } ) , @@ -28588,7 +29987,7 @@ sb_2__2__mux_2level_tapbuf_size4_8 mux_left_track_5 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_33 , SYNOPSYS_UNCONNECTED_34 , SYNOPSYS_UNCONNECTED_35 , SYNOPSYS_UNCONNECTED_36 } ) , .out ( chanx_left_out[2] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_174 ) ) ; + .p0 ( optlc_net_160 ) ) ; sb_2__2__mux_2level_tapbuf_size4_9 mux_left_track_7 ( .in ( { chany_bottom_in[2] , left_top_grid_pin_1_[0] , left_bottom_grid_pin_38_[0] , left_bottom_grid_pin_41_[0] } ) , @@ -28596,7 +29995,7 @@ sb_2__2__mux_2level_tapbuf_size4_9 mux_left_track_7 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_37 , SYNOPSYS_UNCONNECTED_38 , SYNOPSYS_UNCONNECTED_39 , SYNOPSYS_UNCONNECTED_40 } ) , .out ( chanx_left_out[3] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_174 ) ) ; + .p0 ( optlc_net_160 ) ) ; sb_2__2__mux_2level_tapbuf_size4_10 mux_left_track_9 ( .in ( { chany_bottom_in[3] , left_bottom_grid_pin_36_[0] , left_bottom_grid_pin_39_[0] , left_bottom_grid_pin_42_[0] } ) , @@ -28604,7 +30003,7 @@ sb_2__2__mux_2level_tapbuf_size4_10 mux_left_track_9 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_41 , SYNOPSYS_UNCONNECTED_42 , SYNOPSYS_UNCONNECTED_43 , SYNOPSYS_UNCONNECTED_44 } ) , .out ( chanx_left_out[4] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_174 ) ) ; + .p0 ( optlc_net_160 ) ) ; sb_2__2__mux_2level_tapbuf_size4 mux_left_track_11 ( .in ( { chany_bottom_in[4] , left_bottom_grid_pin_37_[0] , left_bottom_grid_pin_40_[0] , left_bottom_grid_pin_43_[0] } ) , @@ -28612,7 +30011,7 @@ sb_2__2__mux_2level_tapbuf_size4 mux_left_track_11 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_45 , SYNOPSYS_UNCONNECTED_46 , SYNOPSYS_UNCONNECTED_47 , SYNOPSYS_UNCONNECTED_48 } ) , .out ( chanx_left_out[5] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_174 ) ) ; + .p0 ( optlc_net_160 ) ) ; sb_2__2__mux_2level_tapbuf_size4_mem_0 mem_bottom_track_1 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( mux_2level_tapbuf_size4_mem_0_ccff_tail ) , @@ -28689,223 +30088,223 @@ sb_2__2__mux_2level_tapbuf_size2_0 mux_bottom_track_13 ( .sram ( mux_2level_tapbuf_size2_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_49 , SYNOPSYS_UNCONNECTED_50 } ) , .out ( chany_bottom_out[6] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_177 ) ) ; + .p0 ( optlc_net_162 ) ) ; sb_2__2__mux_2level_tapbuf_size2_1 mux_bottom_track_15 ( .in ( { bottom_left_grid_pin_44_[0] , chanx_left_in[8] } ) , .sram ( mux_2level_tapbuf_size2_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_51 , SYNOPSYS_UNCONNECTED_52 } ) , .out ( chany_bottom_out[7] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_175 ) ) ; + .p0 ( optlc_net_163 ) ) ; sb_2__2__mux_2level_tapbuf_size2_2 mux_bottom_track_17 ( .in ( { bottom_left_grid_pin_45_[0] , chanx_left_in[9] } ) , .sram ( mux_2level_tapbuf_size2_2_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_53 , SYNOPSYS_UNCONNECTED_54 } ) , .out ( chany_bottom_out[8] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_175 ) ) ; + .p0 ( optlc_net_163 ) ) ; sb_2__2__mux_2level_tapbuf_size2_3 mux_bottom_track_19 ( .in ( { bottom_left_grid_pin_46_[0] , chanx_left_in[10] } ) , .sram ( mux_2level_tapbuf_size2_3_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_55 , SYNOPSYS_UNCONNECTED_56 } ) , .out ( chany_bottom_out[9] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_175 ) ) ; + .p0 ( optlc_net_163 ) ) ; sb_2__2__mux_2level_tapbuf_size2_4 mux_bottom_track_21 ( .in ( { bottom_left_grid_pin_47_[0] , chanx_left_in[11] } ) , .sram ( mux_2level_tapbuf_size2_4_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_57 , SYNOPSYS_UNCONNECTED_58 } ) , .out ( chany_bottom_out[10] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_179 ) ) ; + .p0 ( optlc_net_163 ) ) ; sb_2__2__mux_2level_tapbuf_size2_5 mux_bottom_track_23 ( .in ( { bottom_left_grid_pin_48_[0] , chanx_left_in[12] } ) , .sram ( mux_2level_tapbuf_size2_5_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_59 , SYNOPSYS_UNCONNECTED_60 } ) , .out ( chany_bottom_out[11] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_179 ) ) ; + .p0 ( optlc_net_162 ) ) ; sb_2__2__mux_2level_tapbuf_size2_6 mux_bottom_track_25 ( .in ( { bottom_left_grid_pin_49_[0] , chanx_left_in[13] } ) , .sram ( mux_2level_tapbuf_size2_6_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_61 , SYNOPSYS_UNCONNECTED_62 } ) , .out ( chany_bottom_out[12] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_178 ) ) ; + .p0 ( optlc_net_163 ) ) ; sb_2__2__mux_2level_tapbuf_size2_7 mux_bottom_track_27 ( .in ( { bottom_left_grid_pin_50_[0] , chanx_left_in[14] } ) , .sram ( mux_2level_tapbuf_size2_7_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_63 , SYNOPSYS_UNCONNECTED_64 } ) , .out ( chany_bottom_out[13] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_177 ) ) ; + .p0 ( optlc_net_162 ) ) ; sb_2__2__mux_2level_tapbuf_size2_8 mux_bottom_track_39 ( .in ( { bottom_left_grid_pin_44_[0] , chanx_left_in[20] } ) , .sram ( mux_2level_tapbuf_size2_8_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_65 , SYNOPSYS_UNCONNECTED_66 } ) , .out ( chany_bottom_out[19] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_179 ) ) ; + .p0 ( optlc_net_162 ) ) ; sb_2__2__mux_2level_tapbuf_size2_9 mux_bottom_track_41 ( .in ( { bottom_left_grid_pin_45_[0] , chanx_left_in[21] } ) , .sram ( mux_2level_tapbuf_size2_9_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_67 , SYNOPSYS_UNCONNECTED_68 } ) , .out ( chany_bottom_out[20] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_175 ) ) ; + .p0 ( optlc_net_162 ) ) ; sb_2__2__mux_2level_tapbuf_size2_10 mux_bottom_track_43 ( .in ( { bottom_left_grid_pin_46_[0] , chanx_left_in[22] } ) , .sram ( mux_2level_tapbuf_size2_10_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_69 , SYNOPSYS_UNCONNECTED_70 } ) , .out ( chany_bottom_out[21] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_175 ) ) ; + .p0 ( optlc_net_163 ) ) ; sb_2__2__mux_2level_tapbuf_size2_11 mux_bottom_track_47 ( .in ( { bottom_left_grid_pin_48_[0] , chanx_left_in[24] } ) , .sram ( mux_2level_tapbuf_size2_11_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_71 , SYNOPSYS_UNCONNECTED_72 } ) , .out ( chany_bottom_out[23] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_175 ) ) ; + .p0 ( optlc_net_163 ) ) ; sb_2__2__mux_2level_tapbuf_size2_12 mux_bottom_track_49 ( .in ( { bottom_left_grid_pin_49_[0] , chanx_left_in[25] } ) , .sram ( mux_2level_tapbuf_size2_12_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_73 , SYNOPSYS_UNCONNECTED_74 } ) , .out ( chany_bottom_out[24] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_177 ) ) ; + .p0 ( optlc_net_163 ) ) ; sb_2__2__mux_2level_tapbuf_size2_13 mux_bottom_track_51 ( .in ( { bottom_left_grid_pin_50_[0] , chanx_left_in[26] } ) , .sram ( mux_2level_tapbuf_size2_13_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_75 , SYNOPSYS_UNCONNECTED_76 } ) , .out ( chany_bottom_out[25] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_177 ) ) ; + .p0 ( optlc_net_163 ) ) ; sb_2__2__mux_2level_tapbuf_size2_14 mux_bottom_track_53 ( .in ( { bottom_left_grid_pin_51_[0] , chanx_left_in[27] } ) , .sram ( mux_2level_tapbuf_size2_14_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_77 , SYNOPSYS_UNCONNECTED_78 } ) , .out ( chany_bottom_out[26] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_174 ) ) ; + .p0 ( optlc_net_162 ) ) ; sb_2__2__mux_2level_tapbuf_size2_15 mux_left_track_13 ( .in ( { chany_bottom_in[5] , left_top_grid_pin_1_[0] } ) , .sram ( mux_2level_tapbuf_size2_15_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_79 , SYNOPSYS_UNCONNECTED_80 } ) , .out ( chanx_left_out[6] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_176 ) ) ; + .p0 ( optlc_net_161 ) ) ; sb_2__2__mux_2level_tapbuf_size2_16 mux_left_track_15 ( .in ( { chany_bottom_in[6] , left_bottom_grid_pin_36_[0] } ) , .sram ( mux_2level_tapbuf_size2_16_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_81 , SYNOPSYS_UNCONNECTED_82 } ) , .out ( chanx_left_out[7] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_176 ) ) ; + .p0 ( optlc_net_163 ) ) ; sb_2__2__mux_2level_tapbuf_size2_17 mux_left_track_17 ( .in ( { chany_bottom_in[7] , left_bottom_grid_pin_37_[0] } ) , .sram ( mux_2level_tapbuf_size2_17_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_83 , SYNOPSYS_UNCONNECTED_84 } ) , .out ( chanx_left_out[8] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_176 ) ) ; + .p0 ( optlc_net_161 ) ) ; sb_2__2__mux_2level_tapbuf_size2_18 mux_left_track_19 ( .in ( { chany_bottom_in[8] , left_bottom_grid_pin_38_[0] } ) , .sram ( mux_2level_tapbuf_size2_18_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_85 , SYNOPSYS_UNCONNECTED_86 } ) , .out ( chanx_left_out[9] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_176 ) ) ; + .p0 ( optlc_net_161 ) ) ; sb_2__2__mux_2level_tapbuf_size2_19 mux_left_track_21 ( .in ( { chany_bottom_in[9] , left_bottom_grid_pin_39_[0] } ) , .sram ( mux_2level_tapbuf_size2_19_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_87 , SYNOPSYS_UNCONNECTED_88 } ) , .out ( chanx_left_out[10] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_175 ) ) ; + .p0 ( optlc_net_161 ) ) ; sb_2__2__mux_2level_tapbuf_size2_20 mux_left_track_23 ( .in ( { chany_bottom_in[10] , left_bottom_grid_pin_40_[0] } ) , .sram ( mux_2level_tapbuf_size2_20_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_89 , SYNOPSYS_UNCONNECTED_90 } ) , .out ( chanx_left_out[11] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_175 ) ) ; + .p0 ( optlc_net_163 ) ) ; sb_2__2__mux_2level_tapbuf_size2_21 mux_left_track_25 ( .in ( { chany_bottom_in[11] , left_bottom_grid_pin_41_[0] } ) , .sram ( mux_2level_tapbuf_size2_21_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_91 , SYNOPSYS_UNCONNECTED_92 } ) , .out ( chanx_left_out[12] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_175 ) ) ; + .p0 ( optlc_net_163 ) ) ; sb_2__2__mux_2level_tapbuf_size2_22 mux_left_track_27 ( .in ( { chany_bottom_in[12] , left_bottom_grid_pin_42_[0] } ) , .sram ( mux_2level_tapbuf_size2_22_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_93 , SYNOPSYS_UNCONNECTED_94 } ) , .out ( chanx_left_out[13] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_175 ) ) ; + .p0 ( optlc_net_163 ) ) ; sb_2__2__mux_2level_tapbuf_size2_23 mux_left_track_31 ( .in ( { chany_bottom_in[14] , left_bottom_grid_pin_36_[0] } ) , .sram ( mux_2level_tapbuf_size2_23_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_95 , SYNOPSYS_UNCONNECTED_96 } ) , .out ( chanx_left_out[15] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_176 ) ) ; + .p0 ( optlc_net_163 ) ) ; sb_2__2__mux_2level_tapbuf_size2_24 mux_left_track_33 ( .in ( { chany_bottom_in[15] , left_bottom_grid_pin_37_[0] } ) , .sram ( mux_2level_tapbuf_size2_24_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_97 , SYNOPSYS_UNCONNECTED_98 } ) , .out ( chanx_left_out[16] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_176 ) ) ; + .p0 ( optlc_net_163 ) ) ; sb_2__2__mux_2level_tapbuf_size2_25 mux_left_track_35 ( .in ( { chany_bottom_in[16] , left_bottom_grid_pin_38_[0] } ) , .sram ( mux_2level_tapbuf_size2_25_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_99 , SYNOPSYS_UNCONNECTED_100 } ) , .out ( chanx_left_out[17] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_176 ) ) ; + .p0 ( optlc_net_161 ) ) ; sb_2__2__mux_2level_tapbuf_size2_26 mux_left_track_37 ( .in ( { chany_bottom_in[17] , left_bottom_grid_pin_39_[0] } ) , .sram ( mux_2level_tapbuf_size2_26_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_101 , SYNOPSYS_UNCONNECTED_102 } ) , .out ( chanx_left_out[18] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_176 ) ) ; + .p0 ( optlc_net_161 ) ) ; sb_2__2__mux_2level_tapbuf_size2_27 mux_left_track_39 ( .in ( { chany_bottom_in[18] , left_bottom_grid_pin_40_[0] } ) , .sram ( mux_2level_tapbuf_size2_27_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_103 , SYNOPSYS_UNCONNECTED_104 } ) , .out ( chanx_left_out[19] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_176 ) ) ; + .p0 ( optlc_net_161 ) ) ; sb_2__2__mux_2level_tapbuf_size2_28 mux_left_track_41 ( .in ( { chany_bottom_in[19] , left_bottom_grid_pin_41_[0] } ) , .sram ( mux_2level_tapbuf_size2_28_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_105 , SYNOPSYS_UNCONNECTED_106 } ) , .out ( chanx_left_out[20] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_176 ) ) ; + .p0 ( optlc_net_161 ) ) ; sb_2__2__mux_2level_tapbuf_size2_29 mux_left_track_43 ( .in ( { chany_bottom_in[20] , left_bottom_grid_pin_42_[0] } ) , .sram ( mux_2level_tapbuf_size2_29_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_107 , SYNOPSYS_UNCONNECTED_108 } ) , .out ( chanx_left_out[21] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_176 ) ) ; + .p0 ( optlc_net_161 ) ) ; sb_2__2__mux_2level_tapbuf_size2_30 mux_left_track_45 ( .in ( { chany_bottom_in[21] , left_top_grid_pin_1_[0] } ) , .sram ( mux_2level_tapbuf_size2_30_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_109 , SYNOPSYS_UNCONNECTED_110 } ) , .out ( chanx_left_out[22] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_176 ) ) ; + .p0 ( optlc_net_161 ) ) ; sb_2__2__mux_2level_tapbuf_size2_31 mux_left_track_47 ( .in ( { chany_bottom_in[22] , left_bottom_grid_pin_36_[0] } ) , .sram ( mux_2level_tapbuf_size2_31_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_111 , SYNOPSYS_UNCONNECTED_112 } ) , .out ( chanx_left_out[23] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_176 ) ) ; + .p0 ( optlc_net_161 ) ) ; sb_2__2__mux_2level_tapbuf_size2_32 mux_left_track_49 ( .in ( { chany_bottom_in[23] , left_bottom_grid_pin_37_[0] } ) , .sram ( mux_2level_tapbuf_size2_32_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_113 , SYNOPSYS_UNCONNECTED_114 } ) , .out ( chanx_left_out[24] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_176 ) ) ; + .p0 ( optlc_net_163 ) ) ; sb_2__2__mux_2level_tapbuf_size2_33 mux_left_track_51 ( .in ( { chany_bottom_in[24] , left_bottom_grid_pin_38_[0] } ) , .sram ( mux_2level_tapbuf_size2_33_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_115 , SYNOPSYS_UNCONNECTED_116 } ) , .out ( chanx_left_out[25] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_176 ) ) ; + .p0 ( optlc_net_161 ) ) ; sb_2__2__mux_2level_tapbuf_size2_34 mux_left_track_55 ( .in ( { chany_bottom_in[26] , left_bottom_grid_pin_40_[0] } ) , .sram ( mux_2level_tapbuf_size2_34_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_117 , SYNOPSYS_UNCONNECTED_118 } ) , .out ( chanx_left_out[27] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_175 ) ) ; + .p0 ( optlc_net_161 ) ) ; sb_2__2__mux_2level_tapbuf_size2_35 mux_left_track_57 ( .in ( { chany_bottom_in[27] , left_bottom_grid_pin_41_[0] } ) , .sram ( mux_2level_tapbuf_size2_35_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_119 , SYNOPSYS_UNCONNECTED_120 } ) , .out ( chanx_left_out[28] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_175 ) ) ; + .p0 ( optlc_net_161 ) ) ; sb_2__2__mux_2level_tapbuf_size2 mux_left_track_59 ( .in ( { chany_bottom_in[28] , left_bottom_grid_pin_42_[0] } ) , .sram ( mux_2level_tapbuf_size2_36_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_121 , SYNOPSYS_UNCONNECTED_122 } ) , .out ( chanx_left_out[29] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_175 ) ) ; + .p0 ( optlc_net_163 ) ) ; sb_2__2__mux_2level_tapbuf_size2_mem_0 mem_bottom_track_13 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( mux_2level_tapbuf_size4_mem_5_ccff_tail ) , @@ -29133,28 +30532,28 @@ sb_2__2__mux_2level_tapbuf_size3_0 mux_bottom_track_29 ( .sram ( mux_2level_tapbuf_size3_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_123 , SYNOPSYS_UNCONNECTED_124 } ) , .out ( chany_bottom_out[14] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_177 ) ) ; + .p0 ( optlc_net_162 ) ) ; sb_2__2__mux_2level_tapbuf_size3_1 mux_bottom_track_45 ( .in ( { bottom_right_grid_pin_1_[0] , bottom_left_grid_pin_47_[0] , chanx_left_in[23] } ) , .sram ( mux_2level_tapbuf_size3_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_125 , SYNOPSYS_UNCONNECTED_126 } ) , .out ( chany_bottom_out[22] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_175 ) ) ; + .p0 ( optlc_net_163 ) ) ; sb_2__2__mux_2level_tapbuf_size3_2 mux_left_track_29 ( .in ( { chany_bottom_in[13] , left_top_grid_pin_1_[0] , left_bottom_grid_pin_43_[0] } ) , .sram ( mux_2level_tapbuf_size3_2_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_127 , SYNOPSYS_UNCONNECTED_128 } ) , .out ( chanx_left_out[14] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_176 ) ) ; + .p0 ( optlc_net_163 ) ) ; sb_2__2__mux_2level_tapbuf_size3 mux_left_track_53 ( .in ( { chany_bottom_in[25] , left_bottom_grid_pin_39_[0] , left_bottom_grid_pin_43_[0] } ) , .sram ( mux_2level_tapbuf_size3_3_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_129 , SYNOPSYS_UNCONNECTED_130 } ) , .out ( chanx_left_out[26] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_176 ) ) ; + .p0 ( optlc_net_161 ) ) ; sb_2__2__mux_2level_tapbuf_size3_mem_0 mem_bottom_track_29 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( mux_2level_tapbuf_size2_mem_7_ccff_tail ) , @@ -29181,7 +30580,7 @@ sb_2__2__mux_2level_tapbuf_size3_mem mem_left_track_53 ( .pReset ( pReset ) , .VSS ( VSS ) ) ; sky130_fd_sc_hd__buf_8 pReset_FTB00 ( .A ( pReset_W_in ) , .X ( pReset[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_8 prog_clk_0_FTB00 ( .A ( prog_clk_0_S_in ) , +sky130_fd_sc_hd__buf_1 prog_clk_0_FTB00 ( .A ( prog_clk_0_S_in ) , .X ( prog_clk[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_8 FTB_78__77 ( .A ( chanx_left_in[0] ) , .X ( chany_bottom_out[29] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -29199,18 +30598,14 @@ sky130_fd_sc_hd__buf_8 FTB_84__83 ( .A ( chanx_left_in[29] ) , .X ( chany_bottom_out[28] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_6 FTB_85__84 ( .A ( SC_IN_BOT ) , .X ( SC_OUT_BOT ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_176 ( .LO ( SYNOPSYS_UNCONNECTED_131 ) , - .HI ( optlc_net_174 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_178 ( .LO ( SYNOPSYS_UNCONNECTED_132 ) , - .HI ( optlc_net_175 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_181 ( .LO ( SYNOPSYS_UNCONNECTED_133 ) , - .HI ( optlc_net_176 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_184 ( .LO ( SYNOPSYS_UNCONNECTED_134 ) , - .HI ( optlc_net_177 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_186 ( .LO ( SYNOPSYS_UNCONNECTED_135 ) , - .HI ( optlc_net_178 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_188 ( .LO ( SYNOPSYS_UNCONNECTED_136 ) , - .HI ( optlc_net_179 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_162 ( .LO ( SYNOPSYS_UNCONNECTED_131 ) , + .HI ( optlc_net_160 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_164 ( .LO ( SYNOPSYS_UNCONNECTED_132 ) , + .HI ( optlc_net_161 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_166 ( .LO ( SYNOPSYS_UNCONNECTED_133 ) , + .HI ( optlc_net_162 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_168 ( .LO ( SYNOPSYS_UNCONNECTED_134 ) , + .HI ( optlc_net_163 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -29535,7 +30930,7 @@ input p0 ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , +sky130_fd_sc_hd__mux2_2 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -29586,10 +30981,8 @@ sb_2__1__mux_2level_tapbuf_basis_input2_mem1_33 mux_l2_in_0_ ( .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_194 ( .A ( BUF_net_195 ) , .Y ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_195 ( - .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_195 ) , +sky130_fd_sc_hd__buf_6 BUFT_RR_182 ( + .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -29728,7 +31121,7 @@ sb_2__1__mux_2level_tapbuf_basis_input2_mem1_29 mux_l2_in_0_ ( .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_193 ( +sky130_fd_sc_hd__buf_6 BUFT_RR_181 ( .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -29747,7 +31140,7 @@ input p0 ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__mux2_2 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , +sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -29786,6 +31179,9 @@ wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ; supply1 VDD ; supply0 VSS ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; sb_2__1__mux_2level_tapbuf_basis_input2_mem1_26 mux_l1_in_0_ ( .in ( in ) , .mem ( sram[0] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) , @@ -29798,9 +31194,6 @@ sb_2__1__mux_2level_tapbuf_basis_input2_mem1_27 mux_l2_in_0_ ( .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_192 ( - .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -29817,7 +31210,7 @@ input p0 ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__mux2_2 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , +sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -29856,6 +31249,9 @@ wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ; supply1 VDD ; supply0 VSS ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; sb_2__1__mux_2level_tapbuf_basis_input2_mem1_24 mux_l1_in_0_ ( .in ( in ) , .mem ( sram[0] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) , @@ -29868,9 +31264,6 @@ sb_2__1__mux_2level_tapbuf_basis_input2_mem1_25 mux_l2_in_0_ ( .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_191 ( - .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -30078,7 +31471,7 @@ input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) , +sky130_fd_sc_hd__mux2_2 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -30137,9 +31530,6 @@ wire [0:0] mux_2level_tapbuf_basis_input2_mem1_2_out ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( mux_2level_tapbuf_basis_input2_mem1_2_out[0] ) , .X ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; sb_2__1__mux_2level_tapbuf_basis_input2_mem1_21 mux_l1_in_0_ ( .in ( in[0:1] ) , .mem ( sram[0] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) , @@ -30158,6 +31548,9 @@ sb_2__1__mux_2level_tapbuf_basis_input2_mem1_23 mux_l2_in_0_ ( .mem_inv ( { SYNOPSYS_UNCONNECTED_4 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_2_out ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_180 ( + .A ( mux_2level_tapbuf_basis_input2_mem1_2_out[0] ) , .X ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -30268,7 +31661,7 @@ input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__mux2_2 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) , +sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -30345,8 +31738,10 @@ sb_2__1__mux_2level_tapbuf_basis_input2_mem1_17 mux_l2_in_0_ ( .mem_inv ( { SYNOPSYS_UNCONNECTED_4 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_2_out ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_190 ( - .A ( mux_2level_tapbuf_basis_input2_mem1_2_out[0] ) , .X ( out[0] ) , +sky130_fd_sc_hd__inv_8 BINV_R_178 ( .A ( BUF_net_179 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_179 ( + .A ( mux_2level_tapbuf_basis_input2_mem1_2_out[0] ) , .Y ( BUF_net_179 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -30422,9 +31817,6 @@ wire [0:0] mux_2level_tapbuf_basis_input2_mem1_2_out ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( mux_2level_tapbuf_basis_input2_mem1_2_out[0] ) , .X ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; sb_2__1__mux_2level_tapbuf_basis_input2_mem1_12 mux_l1_in_0_ ( .in ( in[0:1] ) , .mem ( sram[0] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) , @@ -30443,6 +31835,9 @@ sb_2__1__mux_2level_tapbuf_basis_input2_mem1_14 mux_l2_in_0_ ( .mem_inv ( { SYNOPSYS_UNCONNECTED_4 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_2_out ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_177 ( + .A ( mux_2level_tapbuf_basis_input2_mem1_2_out[0] ) , .X ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -30458,7 +31853,7 @@ input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__mux2_2 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) , +sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -30517,7 +31912,7 @@ wire [0:0] mux_2level_tapbuf_basis_input2_mem1_2_out ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( mux_2level_tapbuf_basis_input2_mem1_2_out[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sb_2__1__mux_2level_tapbuf_basis_input2_mem1_9 mux_l1_in_0_ ( @@ -30553,7 +31948,7 @@ input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__mux2_2 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) , +sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -30612,9 +32007,6 @@ wire [0:0] mux_2level_tapbuf_basis_input2_mem1_2_out ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( mux_2level_tapbuf_basis_input2_mem1_2_out[0] ) , .X ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; sb_2__1__mux_2level_tapbuf_basis_input2_mem1_6 mux_l1_in_0_ ( .in ( in[0:1] ) , .mem ( sram[0] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) , @@ -30633,6 +32025,11 @@ sb_2__1__mux_2level_tapbuf_basis_input2_mem1_8 mux_l2_in_0_ ( .mem_inv ( { SYNOPSYS_UNCONNECTED_4 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_2_out ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_175 ( .A ( BUF_net_176 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_176 ( + .A ( mux_2level_tapbuf_basis_input2_mem1_2_out[0] ) , .Y ( BUF_net_176 ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -30648,7 +32045,7 @@ input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) , +sky130_fd_sc_hd__mux2_2 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -31076,13 +32473,16 @@ input VDD ; input VSS ; input p0 ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -31095,13 +32495,16 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -31192,10 +32595,10 @@ sb_2__1__mux_2level_tapbuf_basis_input3_mem3 mux_l2_in_0_ ( .mem_inv ( local_encoder2to3_1_data_inv ) , .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_188 ( .A ( BUF_net_189 ) , .Y ( out[0] ) , +sky130_fd_sc_hd__inv_8 BINV_R_173 ( .A ( BUF_net_174 ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_189 ( - .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_189 ) , +sky130_fd_sc_hd__inv_1 BINV_R_174 ( + .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_174 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -31210,13 +32613,16 @@ input VDD ; input VSS ; input p0 ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -31229,13 +32635,16 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -31308,6 +32717,9 @@ wire [0:0] mux_2level_tapbuf_basis_input3_mem3_1_out ; supply1 VDD ; supply0 VSS ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .X ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; sb_2__1__local_encoder2to3_56 local_encoder2to3_0_ ( .addr ( sram[0:1] ) , .data ( local_encoder2to3_0_data ) , .data_inv ( local_encoder2to3_0_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; @@ -31326,11 +32738,6 @@ sb_2__1__mux_2level_tapbuf_basis_input3_mem3_77 mux_l2_in_0_ ( .mem_inv ( local_encoder2to3_1_data_inv ) , .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_186 ( .A ( BUF_net_187 ) , .Y ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_187 ( - .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_187 ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -31344,13 +32751,16 @@ input VDD ; input VSS ; input p0 ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -31363,13 +32773,16 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -31442,9 +32855,6 @@ wire [0:0] mux_2level_tapbuf_basis_input3_mem3_1_out ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .X ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; sb_2__1__local_encoder2to3_54 local_encoder2to3_0_ ( .addr ( sram[0:1] ) , .data ( local_encoder2to3_0_data ) , .data_inv ( local_encoder2to3_0_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; @@ -31463,6 +32873,11 @@ sb_2__1__mux_2level_tapbuf_basis_input3_mem3_75 mux_l2_in_0_ ( .mem_inv ( local_encoder2to3_1_data_inv ) , .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_171 ( .A ( BUF_net_172 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_172 ( + .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_172 ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -31476,13 +32891,16 @@ input VDD ; input VSS ; input p0 ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -31495,13 +32913,16 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -31592,10 +33013,8 @@ sb_2__1__mux_2level_tapbuf_basis_input3_mem3_73 mux_l2_in_0_ ( .mem_inv ( local_encoder2to3_1_data_inv ) , .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_184 ( .A ( BUF_net_185 ) , .Y ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_185 ( - .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_185 ) , +sky130_fd_sc_hd__buf_6 BUFT_RR_170 ( + .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -31610,13 +33029,16 @@ input VDD ; input VSS ; input p0 ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -31629,13 +33051,16 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -31726,10 +33151,10 @@ sb_2__1__mux_2level_tapbuf_basis_input3_mem3_71 mux_l2_in_0_ ( .mem_inv ( local_encoder2to3_1_data_inv ) , .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_182 ( .A ( BUF_net_183 ) , .Y ( out[0] ) , +sky130_fd_sc_hd__inv_8 BINV_R_168 ( .A ( BUF_net_169 ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_183 ( - .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_183 ) , +sky130_fd_sc_hd__inv_1 BINV_R_169 ( + .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_169 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -31744,13 +33169,16 @@ input VDD ; input VSS ; input p0 ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -31763,13 +33191,16 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -31842,6 +33273,9 @@ wire [0:0] mux_2level_tapbuf_basis_input3_mem3_1_out ; supply1 VDD ; supply0 VSS ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .X ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; sb_2__1__local_encoder2to3_48 local_encoder2to3_0_ ( .addr ( sram[0:1] ) , .data ( local_encoder2to3_0_data ) , .data_inv ( local_encoder2to3_0_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; @@ -31860,11 +33294,6 @@ sb_2__1__mux_2level_tapbuf_basis_input3_mem3_69 mux_l2_in_0_ ( .mem_inv ( local_encoder2to3_1_data_inv ) , .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_180 ( .A ( BUF_net_181 ) , .Y ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_181 ( - .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_181 ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -31878,13 +33307,16 @@ input VDD ; input VSS ; input p0 ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -31897,13 +33329,16 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -31994,10 +33429,8 @@ sb_2__1__mux_2level_tapbuf_basis_input3_mem3_67 mux_l2_in_0_ ( .mem_inv ( local_encoder2to3_1_data_inv ) , .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_178 ( .A ( BUF_net_179 ) , .Y ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_179 ( - .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_179 ) , +sky130_fd_sc_hd__buf_6 BUFT_RR_167 ( + .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -32012,13 +33445,16 @@ input VDD ; input VSS ; input p0 ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -32031,13 +33467,16 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -32110,6 +33549,9 @@ wire [0:0] mux_2level_tapbuf_basis_input3_mem3_1_out ; supply1 VDD ; supply0 VSS ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .X ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; sb_2__1__local_encoder2to3_44 local_encoder2to3_0_ ( .addr ( sram[0:1] ) , .data ( local_encoder2to3_0_data ) , .data_inv ( local_encoder2to3_0_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; @@ -32128,11 +33570,6 @@ sb_2__1__mux_2level_tapbuf_basis_input3_mem3_65 mux_l2_in_0_ ( .mem_inv ( local_encoder2to3_1_data_inv ) , .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_176 ( .A ( BUF_net_177 ) , .Y ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_177 ( - .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_177 ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -32296,13 +33733,16 @@ input VDD ; input VSS ; input p0 ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -32315,13 +33755,16 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -32334,13 +33777,16 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -32414,9 +33860,6 @@ wire [0:0] mux_2level_tapbuf_basis_input3_mem3_2_out ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( mux_2level_tapbuf_basis_input3_mem3_2_out[0] ) , .X ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; sb_2__1__local_encoder2to3_42 local_encoder2to3_0_ ( .addr ( sram[0:1] ) , .data ( local_encoder2to3_0_data ) , .data_inv ( local_encoder2to3_0_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; @@ -32441,6 +33884,11 @@ sb_2__1__mux_2level_tapbuf_basis_input3_mem3_63 mux_l2_in_0_ ( .mem_inv ( local_encoder2to3_1_data_inv ) , .out ( mux_2level_tapbuf_basis_input3_mem3_2_out ) , .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_165 ( .A ( BUF_net_166 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_166 ( + .A ( mux_2level_tapbuf_basis_input3_mem3_2_out[0] ) , .Y ( BUF_net_166 ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -32454,13 +33902,16 @@ input VDD ; input VSS ; input p0 ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -32473,13 +33924,16 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -32492,13 +33946,16 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -32596,10 +34053,10 @@ sb_2__1__mux_2level_tapbuf_basis_input3_mem3_60 mux_l2_in_0_ ( .mem_inv ( local_encoder2to3_1_data_inv ) , .out ( mux_2level_tapbuf_basis_input3_mem3_2_out ) , .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_174 ( .A ( BUF_net_175 ) , .Y ( out[0] ) , +sky130_fd_sc_hd__inv_8 BINV_R_163 ( .A ( BUF_net_164 ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_175 ( - .A ( mux_2level_tapbuf_basis_input3_mem3_2_out[0] ) , .Y ( BUF_net_175 ) , +sky130_fd_sc_hd__inv_1 BINV_R_164 ( + .A ( mux_2level_tapbuf_basis_input3_mem3_2_out[0] ) , .Y ( BUF_net_164 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -32614,13 +34071,16 @@ input VDD ; input VSS ; input p0 ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -32633,13 +34093,16 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -32652,13 +34115,16 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -32772,13 +34238,16 @@ input VDD ; input VSS ; input p0 ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -32791,13 +34260,16 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -32810,13 +34282,16 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -32930,13 +34405,16 @@ input VDD ; input VSS ; input p0 ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -32949,13 +34427,16 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -32968,13 +34449,16 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -33072,10 +34556,10 @@ sb_2__1__mux_2level_tapbuf_basis_input3_mem3_51 mux_l2_in_0_ ( .mem_inv ( local_encoder2to3_1_data_inv ) , .out ( mux_2level_tapbuf_basis_input3_mem3_2_out ) , .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_172 ( .A ( BUF_net_173 ) , .Y ( out[0] ) , +sky130_fd_sc_hd__inv_8 BINV_R_185 ( .A ( BUF_net_186 ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_173 ( - .A ( mux_2level_tapbuf_basis_input3_mem3_2_out[0] ) , .Y ( BUF_net_173 ) , +sky130_fd_sc_hd__inv_1 BINV_R_186 ( + .A ( mux_2level_tapbuf_basis_input3_mem3_2_out[0] ) , .Y ( BUF_net_186 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -33119,12 +34603,15 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -33138,15 +34625,20 @@ input VDD ; input VSS ; input p0 ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -33159,15 +34651,20 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -33180,15 +34677,20 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -33276,8 +34778,8 @@ supply1 VDD ; supply0 VSS ; sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_4_0_ ( - .A ( mux_2level_tapbuf_basis_input4_mem4_2_out[0] ) , - .X ( aps_rename_507_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .A ( mux_2level_tapbuf_basis_input4_mem4_2_out[0] ) , .X ( net_net_162 ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; sb_2__1__local_encoder2to4_6 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , .data ( local_encoder2to4_0_data ) , .data_inv ( local_encoder2to4_0_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; @@ -33308,10 +34810,8 @@ sb_2__1__mux_2level_tapbuf_basis_input2_mem2 mux_l1_in_2_ ( .in ( in[8:9] ) , .mem_inv ( local_encoder2to4_0_data_inv[0:1] ) , .out ( mux_2level_tapbuf_basis_input2_mem2_0_out ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_170 ( .A ( BUF_net_171 ) , .Y ( out[0] ) , +sky130_fd_sc_hd__buf_6 BUFT_RR_162 ( .A ( net_net_162 ) , .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_171 ( .A ( aps_rename_507_ ) , - .Y ( BUF_net_171 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -33504,12 +35004,15 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -33523,13 +35026,16 @@ input VDD ; input VSS ; input p0 ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -33542,13 +35048,16 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -33622,6 +35131,9 @@ wire [0:0] mux_2level_tapbuf_basis_input3_mem3_1_out ; supply1 VDD ; supply0 VSS ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .X ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; sb_2__1__local_encoder2to3_32 local_encoder2to3_0_ ( .addr ( sram[0:1] ) , .data ( local_encoder2to3_0_data ) , .data_inv ( local_encoder2to3_0_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; @@ -33646,9 +35158,6 @@ sb_2__1__mux_2level_tapbuf_basis_input2_mem2_12 mux_l1_in_1_ ( .mem_inv ( local_encoder2to3_0_data_inv[0:1] ) , .out ( mux_2level_tapbuf_basis_input2_mem2_0_out ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_169 ( - .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .X ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -33661,12 +35170,15 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -33680,13 +35192,16 @@ input VDD ; input VSS ; input p0 ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -33699,13 +35214,16 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -33803,10 +35321,10 @@ sb_2__1__mux_2level_tapbuf_basis_input2_mem2_11 mux_l1_in_1_ ( .mem_inv ( local_encoder2to3_0_data_inv[0:1] ) , .out ( mux_2level_tapbuf_basis_input2_mem2_0_out ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_167 ( .A ( BUF_net_168 ) , .Y ( out[0] ) , +sky130_fd_sc_hd__inv_8 BINV_R_160 ( .A ( BUF_net_161 ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_168 ( - .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_168 ) , +sky130_fd_sc_hd__inv_1 BINV_R_161 ( + .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_161 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -33820,12 +35338,15 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -33839,13 +35360,16 @@ input VDD ; input VSS ; input p0 ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -33858,13 +35382,16 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -33962,10 +35489,10 @@ sb_2__1__mux_2level_tapbuf_basis_input2_mem2_10 mux_l1_in_1_ ( .mem_inv ( local_encoder2to3_0_data_inv[0:1] ) , .out ( mux_2level_tapbuf_basis_input2_mem2_0_out ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_165 ( .A ( BUF_net_166 ) , .Y ( out[0] ) , +sky130_fd_sc_hd__inv_8 BINV_R_158 ( .A ( BUF_net_159 ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_166 ( - .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_166 ) , +sky130_fd_sc_hd__inv_1 BINV_R_159 ( + .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_159 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -33979,12 +35506,15 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -33998,13 +35528,16 @@ input VDD ; input VSS ; input p0 ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -34017,13 +35550,16 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -34097,6 +35633,9 @@ wire [0:0] mux_2level_tapbuf_basis_input3_mem3_1_out ; supply1 VDD ; supply0 VSS ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .X ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; sb_2__1__local_encoder2to3_26 local_encoder2to3_0_ ( .addr ( sram[0:1] ) , .data ( local_encoder2to3_0_data ) , .data_inv ( local_encoder2to3_0_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; @@ -34121,9 +35660,6 @@ sb_2__1__mux_2level_tapbuf_basis_input2_mem2_9 mux_l1_in_1_ ( .mem_inv ( local_encoder2to3_0_data_inv[0:1] ) , .out ( mux_2level_tapbuf_basis_input2_mem2_0_out ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_164 ( - .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .X ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -34136,12 +35672,15 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -34155,13 +35694,16 @@ input VDD ; input VSS ; input p0 ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -34174,13 +35716,16 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -34278,10 +35823,10 @@ sb_2__1__mux_2level_tapbuf_basis_input2_mem2_8 mux_l1_in_1_ ( .mem_inv ( local_encoder2to3_0_data_inv[0:1] ) , .out ( mux_2level_tapbuf_basis_input2_mem2_0_out ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_162 ( .A ( BUF_net_163 ) , .Y ( out[0] ) , +sky130_fd_sc_hd__inv_8 BINV_R_156 ( .A ( BUF_net_157 ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_163 ( - .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_163 ) , +sky130_fd_sc_hd__inv_1 BINV_R_157 ( + .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_157 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -34295,12 +35840,15 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -34314,13 +35862,16 @@ input VDD ; input VSS ; input p0 ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -34333,13 +35884,16 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -34413,9 +35967,6 @@ wire [0:0] mux_2level_tapbuf_basis_input3_mem3_1_out ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .X ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; sb_2__1__local_encoder2to3_22 local_encoder2to3_0_ ( .addr ( sram[0:1] ) , .data ( local_encoder2to3_0_data ) , .data_inv ( local_encoder2to3_0_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; @@ -34440,6 +35991,11 @@ sb_2__1__mux_2level_tapbuf_basis_input2_mem2_7 mux_l1_in_1_ ( .mem_inv ( local_encoder2to3_0_data_inv[0:1] ) , .out ( mux_2level_tapbuf_basis_input2_mem2_0_out ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_154 ( .A ( BUF_net_155 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_155 ( + .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_155 ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -34543,15 +36099,20 @@ input VDD ; input VSS ; input p0 ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -34564,15 +36125,20 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -34585,15 +36151,20 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -34679,9 +36250,9 @@ wire [0:0] mux_2level_tapbuf_basis_input4_mem4_2_out ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_4_0_ ( - .A ( mux_2level_tapbuf_basis_input4_mem4_2_out[0] ) , - .X ( aps_rename_506_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( mux_2level_tapbuf_basis_input4_mem4_2_out[0] ) , .X ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; sb_2__1__local_encoder2to4_4 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , .data ( local_encoder2to4_0_data ) , .data_inv ( local_encoder2to4_0_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; @@ -34706,10 +36277,6 @@ sb_2__1__mux_2level_tapbuf_basis_input4_mem4_8 mux_l2_in_0_ ( .mem_inv ( local_encoder2to4_1_data_inv ) , .out ( mux_2level_tapbuf_basis_input4_mem4_2_out ) , .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_160 ( .A ( BUF_net_161 ) , .Y ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_161 ( .A ( aps_rename_506_ ) , - .Y ( BUF_net_161 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -34723,15 +36290,20 @@ input VDD ; input VSS ; input p0 ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -34744,15 +36316,20 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -34765,15 +36342,20 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -34859,7 +36441,7 @@ wire [0:0] mux_2level_tapbuf_basis_input4_mem4_2_out ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__bufbuf_16 sky130_fd_sc_hd__buf_4_0_ ( +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( mux_2level_tapbuf_basis_input4_mem4_2_out[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sb_2__1__local_encoder2to4_2 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , @@ -34899,15 +36481,20 @@ input VDD ; input VSS ; input p0 ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -34920,15 +36507,20 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -34941,15 +36533,20 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -35035,9 +36632,9 @@ wire [0:0] mux_2level_tapbuf_basis_input4_mem4_2_out ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_4_0_ ( - .A ( mux_2level_tapbuf_basis_input4_mem4_2_out[0] ) , - .X ( aps_rename_505_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( mux_2level_tapbuf_basis_input4_mem4_2_out[0] ) , .X ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; sb_2__1__local_encoder2to4_0 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , .data ( local_encoder2to4_0_data ) , .data_inv ( local_encoder2to4_0_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; @@ -35062,10 +36659,6 @@ sb_2__1__mux_2level_tapbuf_basis_input4_mem4_2 mux_l2_in_0_ ( .mem_inv ( local_encoder2to4_1_data_inv ) , .out ( mux_2level_tapbuf_basis_input4_mem4_2_out ) , .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_158 ( .A ( BUF_net_159 ) , .Y ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_159 ( .A ( aps_rename_505_ ) , - .Y ( BUF_net_159 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -35289,12 +36882,15 @@ input VDD ; input VSS ; input p0 ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( p0 ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -35307,13 +36903,16 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -35326,13 +36925,16 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -35345,13 +36947,16 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -35422,9 +37027,13 @@ wire [0:2] local_encoder2to3_1_data_inv ; wire [0:0] mux_2level_tapbuf_basis_input2_mem2_0_out ; wire [0:0] mux_2level_tapbuf_basis_input3_mem3_0_out ; wire [0:0] mux_2level_tapbuf_basis_input3_mem3_1_out ; +wire [0:0] mux_2level_tapbuf_basis_input3_mem3_2_out ; supply1 VDD ; supply0 VSS ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( mux_2level_tapbuf_basis_input3_mem3_2_out[0] ) , .X ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; sb_2__1__local_encoder2to3_20 local_encoder2to3_0_ ( .addr ( sram[0:1] ) , .data ( local_encoder2to3_0_data ) , .data_inv ( local_encoder2to3_0_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; @@ -35446,7 +37055,8 @@ sb_2__1__mux_2level_tapbuf_basis_input3_mem3_36 mux_l2_in_0_ ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] , mux_2level_tapbuf_basis_input2_mem2_0_out[0] } ) , .mem ( local_encoder2to3_1_data ) , - .mem_inv ( local_encoder2to3_1_data_inv ) , .out ( out ) , .VDD ( VDD ) , + .mem_inv ( local_encoder2to3_1_data_inv ) , + .out ( mux_2level_tapbuf_basis_input3_mem3_2_out ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_2__1__mux_2level_tapbuf_basis_input2_mem2_6 mux_l1_in_2_ ( .in ( { in[6] , SYNOPSYS_UNCONNECTED_1 } ) , @@ -35467,12 +37077,15 @@ input VDD ; input VSS ; input p0 ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( p0 ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -35485,13 +37098,16 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -35504,13 +37120,16 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -35523,13 +37142,16 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -35604,6 +37226,9 @@ wire [0:0] mux_2level_tapbuf_basis_input3_mem3_2_out ; supply1 VDD ; supply0 VSS ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( mux_2level_tapbuf_basis_input3_mem3_2_out[0] ) , .X ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; sb_2__1__local_encoder2to3_18 local_encoder2to3_0_ ( .addr ( sram[0:1] ) , .data ( local_encoder2to3_0_data ) , .data_inv ( local_encoder2to3_0_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; @@ -35634,11 +37259,6 @@ sb_2__1__mux_2level_tapbuf_basis_input2_mem2_5 mux_l1_in_2_ ( .mem_inv ( local_encoder2to3_0_data_inv[0:1] ) , .out ( mux_2level_tapbuf_basis_input2_mem2_0_out ) , .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_156 ( .A ( BUF_net_157 ) , .Y ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_157 ( - .A ( mux_2level_tapbuf_basis_input3_mem3_2_out[0] ) , .Y ( BUF_net_157 ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -35652,12 +37272,15 @@ input VDD ; input VSS ; input p0 ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( p0 ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -35670,13 +37293,16 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -35689,13 +37315,16 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -35708,13 +37337,16 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -35835,12 +37467,15 @@ input VDD ; input VSS ; input p0 ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( p0 ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -35853,13 +37488,16 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -35872,13 +37510,16 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -35891,13 +37532,16 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -36018,12 +37662,15 @@ input VDD ; input VSS ; input p0 ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( p0 ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -36036,13 +37683,16 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -36055,13 +37705,16 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -36074,13 +37727,16 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -36155,9 +37811,6 @@ wire [0:0] mux_2level_tapbuf_basis_input3_mem3_2_out ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( mux_2level_tapbuf_basis_input3_mem3_2_out[0] ) , .X ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; sb_2__1__local_encoder2to3_12 local_encoder2to3_0_ ( .addr ( sram[0:1] ) , .data ( local_encoder2to3_0_data ) , .data_inv ( local_encoder2to3_0_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; @@ -36188,6 +37841,11 @@ sb_2__1__mux_2level_tapbuf_basis_input2_mem2_2 mux_l1_in_2_ ( .mem_inv ( local_encoder2to3_0_data_inv[0:1] ) , .out ( mux_2level_tapbuf_basis_input2_mem2_0_out ) , .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_152 ( .A ( BUF_net_153 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_153 ( + .A ( mux_2level_tapbuf_basis_input3_mem3_2_out[0] ) , .Y ( BUF_net_153 ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -36201,12 +37859,15 @@ input VDD ; input VSS ; input p0 ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( p0 ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -36219,13 +37880,16 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -36238,13 +37902,16 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -36257,13 +37924,16 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -36384,12 +38054,15 @@ input VDD ; input VSS ; input p0 ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( p0 ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -36402,13 +38075,16 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -36421,13 +38097,16 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -36440,13 +38119,16 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -36660,7 +38342,7 @@ input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ropt_net_226 ) , +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ropt_net_208 ) , .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , @@ -36674,30 +38356,28 @@ sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_1 FTB_9__8 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1392 ( .A ( ccff_head[0] ) , - .X ( copt_net_204 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1393 ( .A ( copt_net_204 ) , - .X ( copt_net_205 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1394 ( .A ( ropt_net_227 ) , - .X ( copt_net_206 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1395 ( .A ( copt_net_205 ) , - .X ( copt_net_207 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1396 ( .A ( copt_net_207 ) , - .X ( copt_net_208 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1397 ( .A ( copt_net_208 ) , - .X ( copt_net_209 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1409 ( .A ( ropt_net_225 ) , - .X ( ropt_net_222 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1410 ( .A ( ropt_net_222 ) , - .X ( ropt_net_223 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1411 ( .A ( ropt_net_223 ) , - .X ( ropt_net_224 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 ropt_h_inst_1412 ( .A ( copt_net_206 ) , - .X ( ropt_net_225 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 ropt_h_inst_1413 ( .A ( ropt_net_224 ) , - .X ( ropt_net_226 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1414 ( .A ( copt_net_209 ) , - .X ( ropt_net_227 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1381 ( .A ( copt_net_195 ) , + .X ( copt_net_193 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1382 ( .A ( copt_net_193 ) , + .X ( copt_net_194 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1383 ( .A ( ccff_head[0] ) , + .X ( copt_net_195 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1384 ( .A ( copt_net_198 ) , + .X ( copt_net_196 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1385 ( .A ( copt_net_194 ) , + .X ( copt_net_197 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 copt_h_inst_1386 ( .A ( ropt_net_210 ) , + .X ( copt_net_198 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1397 ( .A ( copt_net_196 ) , + .X ( ropt_net_206 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1398 ( .A ( ropt_net_206 ) , + .X ( ropt_net_207 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_2 ropt_h_inst_1399 ( .A ( ropt_net_207 ) , + .X ( ropt_net_208 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1400 ( .A ( copt_net_197 ) , + .X ( ropt_net_209 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 ropt_h_inst_1401 ( .A ( ropt_net_209 ) , + .X ( ropt_net_210 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -36710,13 +38390,16 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -36730,13 +38413,16 @@ input VDD ; input VSS ; input p0 ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -36749,13 +38435,16 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -36768,13 +38457,16 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -36849,6 +38541,9 @@ wire [0:0] mux_2level_tapbuf_basis_input3_mem3_3_out ; supply1 VDD ; supply0 VSS ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( mux_2level_tapbuf_basis_input3_mem3_3_out[0] ) , .X ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; sb_2__1__local_encoder2to3_6 local_encoder2to3_0_ ( .addr ( sram[0:1] ) , .data ( local_encoder2to3_0_data ) , .data_inv ( local_encoder2to3_0_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; @@ -36879,11 +38574,6 @@ sb_2__1__mux_2level_tapbuf_basis_input3_mem3_15 mux_l2_in_0_ ( .mem_inv ( local_encoder2to3_1_data_inv ) , .out ( mux_2level_tapbuf_basis_input3_mem3_3_out ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_154 ( .A ( BUF_net_155 ) , .Y ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_155 ( - .A ( mux_2level_tapbuf_basis_input3_mem3_3_out[0] ) , .Y ( BUF_net_155 ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -36896,13 +38586,16 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -36916,13 +38609,16 @@ input VDD ; input VSS ; input p0 ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -36935,13 +38631,16 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -36954,13 +38653,16 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -37035,6 +38737,9 @@ wire [0:0] mux_2level_tapbuf_basis_input3_mem3_3_out ; supply1 VDD ; supply0 VSS ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( mux_2level_tapbuf_basis_input3_mem3_3_out[0] ) , .X ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; sb_2__1__local_encoder2to3_4 local_encoder2to3_0_ ( .addr ( sram[0:1] ) , .data ( local_encoder2to3_0_data ) , .data_inv ( local_encoder2to3_0_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; @@ -37065,11 +38770,6 @@ sb_2__1__mux_2level_tapbuf_basis_input3_mem3_11 mux_l2_in_0_ ( .mem_inv ( local_encoder2to3_1_data_inv ) , .out ( mux_2level_tapbuf_basis_input3_mem3_3_out ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_152 ( .A ( BUF_net_153 ) , .Y ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_153 ( - .A ( mux_2level_tapbuf_basis_input3_mem3_3_out[0] ) , .Y ( BUF_net_153 ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -37082,13 +38782,16 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -37102,13 +38805,16 @@ input VDD ; input VSS ; input p0 ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -37121,13 +38827,16 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -37140,13 +38849,16 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -37221,6 +38933,9 @@ wire [0:0] mux_2level_tapbuf_basis_input3_mem3_3_out ; supply1 VDD ; supply0 VSS ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( mux_2level_tapbuf_basis_input3_mem3_3_out[0] ) , .X ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; sb_2__1__local_encoder2to3_2 local_encoder2to3_0_ ( .addr ( sram[0:1] ) , .data ( local_encoder2to3_0_data ) , .data_inv ( local_encoder2to3_0_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; @@ -37251,11 +38966,6 @@ sb_2__1__mux_2level_tapbuf_basis_input3_mem3_7 mux_l2_in_0_ ( .mem_inv ( local_encoder2to3_1_data_inv ) , .out ( mux_2level_tapbuf_basis_input3_mem3_3_out ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_150 ( .A ( BUF_net_151 ) , .Y ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_151 ( - .A ( mux_2level_tapbuf_basis_input3_mem3_3_out[0] ) , .Y ( BUF_net_151 ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -37268,13 +38978,16 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -37288,13 +39001,16 @@ input VDD ; input VSS ; input p0 ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -37307,13 +39023,16 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -37326,13 +39045,16 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -37407,9 +39129,6 @@ wire [0:0] mux_2level_tapbuf_basis_input3_mem3_3_out ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( mux_2level_tapbuf_basis_input3_mem3_3_out[0] ) , .X ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; sb_2__1__local_encoder2to3_0 local_encoder2to3_0_ ( .addr ( sram[0:1] ) , .data ( local_encoder2to3_0_data ) , .data_inv ( local_encoder2to3_0_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; @@ -37440,6 +39159,11 @@ sb_2__1__mux_2level_tapbuf_basis_input3_mem3_3 mux_l2_in_0_ ( .mem_inv ( local_encoder2to3_1_data_inv ) , .out ( mux_2level_tapbuf_basis_input3_mem3_3_out ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_150 ( .A ( BUF_net_151 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_151 ( + .A ( mux_2level_tapbuf_basis_input3_mem3_3_out[0] ) , .Y ( BUF_net_151 ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -37499,8 +39223,8 @@ input prog_clk_0_N_in ; input VDD ; input VSS ; -wire ropt_net_217 ; -wire ZBUF_74_0 ; +wire ZBUF_250_f_0 ; +wire ZBUF_263_f_0 ; wire [0:0] prog_clk ; wire prog_clk_0 ; wire [0:3] mux_2level_tapbuf_size10_0_sram ; @@ -37613,7 +39337,7 @@ sb_2__1__mux_2level_tapbuf_size8_0 mux_top_track_0 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 , SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) , .out ( chany_top_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_202 ) ) ; + .p0 ( optlc_net_192 ) ) ; sb_2__1__mux_2level_tapbuf_size8_1 mux_bottom_track_1 ( .in ( { chany_bottom_out[4] , chany_bottom_out[20] , bottom_right_grid_pin_1_[0] , bottom_left_grid_pin_46_[0] , @@ -37623,7 +39347,7 @@ sb_2__1__mux_2level_tapbuf_size8_1 mux_bottom_track_1 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 , SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 } ) , .out ( chany_bottom_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_202 ) ) ; + .p0 ( optlc_net_189 ) ) ; sb_2__1__mux_2level_tapbuf_size8_2 mux_bottom_track_3 ( .in ( { chany_bottom_out[7] , chany_bottom_out[21] , bottom_left_grid_pin_44_[0] , bottom_left_grid_pin_47_[0] , @@ -37633,7 +39357,7 @@ sb_2__1__mux_2level_tapbuf_size8_2 mux_bottom_track_3 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_9 , SYNOPSYS_UNCONNECTED_10 , SYNOPSYS_UNCONNECTED_11 , SYNOPSYS_UNCONNECTED_12 } ) , .out ( chany_bottom_out[1] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_199 ) ) ; + .p0 ( optlc_net_189 ) ) ; sb_2__1__mux_2level_tapbuf_size8 mux_bottom_track_5 ( .in ( { chany_bottom_out[8] , chany_bottom_out[23] , bottom_left_grid_pin_45_[0] , bottom_left_grid_pin_48_[0] , @@ -37643,7 +39367,7 @@ sb_2__1__mux_2level_tapbuf_size8 mux_bottom_track_5 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 , SYNOPSYS_UNCONNECTED_15 , SYNOPSYS_UNCONNECTED_16 } ) , .out ( chany_bottom_out[2] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_202 ) ) ; + .p0 ( optlc_net_189 ) ) ; sb_2__1__mux_2level_tapbuf_size8_mem_0 mem_top_track_0 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( mux_2level_tapbuf_size8_mem_0_ccff_tail ) , @@ -37675,7 +39399,7 @@ sb_2__1__mux_2level_tapbuf_size7_0 mux_top_track_2 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_17 , SYNOPSYS_UNCONNECTED_18 , SYNOPSYS_UNCONNECTED_19 , SYNOPSYS_UNCONNECTED_20 } ) , .out ( chany_top_out[1] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_202 ) ) ; + .p0 ( optlc_net_192 ) ) ; sb_2__1__mux_2level_tapbuf_size7_1 mux_top_track_4 ( .in ( { top_left_grid_pin_46_[0] , top_left_grid_pin_49_[0] , top_right_grid_pin_1_[0] , chany_top_out[8] , chany_top_out[23] , @@ -37684,7 +39408,7 @@ sb_2__1__mux_2level_tapbuf_size7_1 mux_top_track_4 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_21 , SYNOPSYS_UNCONNECTED_22 , SYNOPSYS_UNCONNECTED_23 , SYNOPSYS_UNCONNECTED_24 } ) , .out ( chany_top_out[2] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_201 ) ) ; + .p0 ( optlc_net_190 ) ) ; sb_2__1__mux_2level_tapbuf_size7_2 mux_top_track_12 ( .in ( { top_left_grid_pin_44_[0] , top_left_grid_pin_50_[0] , chany_top_out[12] , chany_top_out[27] , chanx_left_in[6] , @@ -37693,7 +39417,7 @@ sb_2__1__mux_2level_tapbuf_size7_2 mux_top_track_12 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_25 , SYNOPSYS_UNCONNECTED_26 , SYNOPSYS_UNCONNECTED_27 , SYNOPSYS_UNCONNECTED_28 } ) , .out ( chany_top_out[6] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_201 ) ) ; + .p0 ( optlc_net_190 ) ) ; sb_2__1__mux_2level_tapbuf_size7_3 mux_top_track_20 ( .in ( { top_left_grid_pin_45_[0] , top_left_grid_pin_51_[0] , chany_top_out[13] , chany_top_out[28] , chanx_left_in[5] , @@ -37702,7 +39426,7 @@ sb_2__1__mux_2level_tapbuf_size7_3 mux_top_track_20 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_29 , SYNOPSYS_UNCONNECTED_30 , SYNOPSYS_UNCONNECTED_31 , SYNOPSYS_UNCONNECTED_32 } ) , .out ( chany_top_out[10] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_201 ) ) ; + .p0 ( optlc_net_190 ) ) ; sb_2__1__mux_2level_tapbuf_size7_4 mux_top_track_28 ( .in ( { top_left_grid_pin_46_[0] , top_right_grid_pin_1_[0] , chany_top_out[15] , chany_top_out[29] , chanx_left_in[4] , @@ -37711,7 +39435,7 @@ sb_2__1__mux_2level_tapbuf_size7_4 mux_top_track_28 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_33 , SYNOPSYS_UNCONNECTED_34 , SYNOPSYS_UNCONNECTED_35 , SYNOPSYS_UNCONNECTED_36 } ) , .out ( chany_top_out[14] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_202 ) ) ; + .p0 ( optlc_net_192 ) ) ; sb_2__1__mux_2level_tapbuf_size7_5 mux_bottom_track_13 ( .in ( { chany_bottom_out[12] , chany_bottom_out[27] , bottom_right_grid_pin_1_[0] , bottom_left_grid_pin_49_[0] , @@ -37720,7 +39444,7 @@ sb_2__1__mux_2level_tapbuf_size7_5 mux_bottom_track_13 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_37 , SYNOPSYS_UNCONNECTED_38 , SYNOPSYS_UNCONNECTED_39 , SYNOPSYS_UNCONNECTED_40 } ) , .out ( chany_bottom_out[6] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_198 ) ) ; + .p0 ( optlc_net_187 ) ) ; sb_2__1__mux_2level_tapbuf_size7 mux_bottom_track_21 ( .in ( { chany_bottom_out[13] , chany_bottom_out[28] , bottom_left_grid_pin_44_[0] , bottom_left_grid_pin_50_[0] , @@ -37728,8 +39452,8 @@ sb_2__1__mux_2level_tapbuf_size7 mux_bottom_track_21 ( .sram ( mux_2level_tapbuf_size7_6_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_41 , SYNOPSYS_UNCONNECTED_42 , SYNOPSYS_UNCONNECTED_43 , SYNOPSYS_UNCONNECTED_44 } ) , - .out ( { aps_rename_508_ } ) , - .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_198 ) ) ; + .out ( chany_bottom_out[10] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_187 ) ) ; sb_2__1__mux_2level_tapbuf_size7_mem_0 mem_top_track_2 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( mux_2level_tapbuf_size8_mem_0_ccff_tail ) , @@ -37781,7 +39505,7 @@ sb_2__1__mux_2level_tapbuf_size9_0 mux_top_track_6 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_45 , SYNOPSYS_UNCONNECTED_46 , SYNOPSYS_UNCONNECTED_47 , SYNOPSYS_UNCONNECTED_48 } ) , .out ( chany_top_out[3] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_201 ) ) ; + .p0 ( optlc_net_190 ) ) ; sb_2__1__mux_2level_tapbuf_size9_1 mux_top_track_10 ( .in ( { top_left_grid_pin_45_[0] , top_left_grid_pin_47_[0] , top_left_grid_pin_49_[0] , top_left_grid_pin_51_[0] , @@ -37791,7 +39515,7 @@ sb_2__1__mux_2level_tapbuf_size9_1 mux_top_track_10 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_49 , SYNOPSYS_UNCONNECTED_50 , SYNOPSYS_UNCONNECTED_51 , SYNOPSYS_UNCONNECTED_52 } ) , .out ( chany_top_out[5] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_201 ) ) ; + .p0 ( optlc_net_190 ) ) ; sb_2__1__mux_2level_tapbuf_size9 mux_bottom_track_11 ( .in ( { chany_bottom_out[11] , chany_bottom_out[25] , bottom_left_grid_pin_44_[0] , bottom_left_grid_pin_46_[0] , @@ -37801,7 +39525,7 @@ sb_2__1__mux_2level_tapbuf_size9 mux_bottom_track_11 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_53 , SYNOPSYS_UNCONNECTED_54 , SYNOPSYS_UNCONNECTED_55 , SYNOPSYS_UNCONNECTED_56 } ) , .out ( chany_bottom_out[5] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_201 ) ) ; + .p0 ( optlc_net_190 ) ) ; sb_2__1__mux_2level_tapbuf_size9_mem_0 mem_top_track_6 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( mux_2level_tapbuf_size7_mem_1_ccff_tail ) , @@ -37827,7 +39551,7 @@ sb_2__1__mux_2level_tapbuf_size5_0 mux_top_track_36 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_57 , SYNOPSYS_UNCONNECTED_58 , SYNOPSYS_UNCONNECTED_59 , SYNOPSYS_UNCONNECTED_60 } ) , .out ( chany_top_out[18] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_202 ) ) ; + .p0 ( optlc_net_192 ) ) ; sb_2__1__mux_2level_tapbuf_size5_1 mux_top_track_44 ( .in ( { top_left_grid_pin_48_[0] , chany_top_out[17] , chanx_left_in[2] , chanx_left_in[13] , chanx_left_in[24] } ) , @@ -37835,7 +39559,7 @@ sb_2__1__mux_2level_tapbuf_size5_1 mux_top_track_44 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_61 , SYNOPSYS_UNCONNECTED_62 , SYNOPSYS_UNCONNECTED_63 , SYNOPSYS_UNCONNECTED_64 } ) , .out ( chany_top_out[22] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_202 ) ) ; + .p0 ( optlc_net_192 ) ) ; sb_2__1__mux_2level_tapbuf_size5_2 mux_top_track_52 ( .in ( { top_left_grid_pin_49_[0] , chany_top_out[19] , chanx_left_in[1] , chanx_left_in[12] , chanx_left_in[23] } ) , @@ -37843,7 +39567,7 @@ sb_2__1__mux_2level_tapbuf_size5_2 mux_top_track_52 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_65 , SYNOPSYS_UNCONNECTED_66 , SYNOPSYS_UNCONNECTED_67 , SYNOPSYS_UNCONNECTED_68 } ) , .out ( chany_top_out[26] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_202 ) ) ; + .p0 ( optlc_net_192 ) ) ; sb_2__1__mux_2level_tapbuf_size5_3 mux_bottom_track_53 ( .in ( { chany_bottom_out[19] , bottom_left_grid_pin_48_[0] , chanx_left_in[0] , chanx_left_in[11] , chanx_left_in[22] } ) , @@ -37851,7 +39575,7 @@ sb_2__1__mux_2level_tapbuf_size5_3 mux_bottom_track_53 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_69 , SYNOPSYS_UNCONNECTED_70 , SYNOPSYS_UNCONNECTED_71 , SYNOPSYS_UNCONNECTED_72 } ) , .out ( chany_bottom_out[26] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_201 ) ) ; + .p0 ( optlc_net_192 ) ) ; sb_2__1__mux_2level_tapbuf_size5_4 mux_left_track_5 ( .in ( { chany_bottom_out[8] , chany_bottom_in[1] , chany_top_out[8] , left_bottom_grid_pin_38_[0] , chanx_left_out[19] } ) , @@ -37859,7 +39583,7 @@ sb_2__1__mux_2level_tapbuf_size5_4 mux_left_track_5 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_73 , SYNOPSYS_UNCONNECTED_74 , SYNOPSYS_UNCONNECTED_75 , SYNOPSYS_UNCONNECTED_76 } ) , .out ( chanx_left_out[2] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_199 ) ) ; + .p0 ( optlc_net_188 ) ) ; sb_2__1__mux_2level_tapbuf_size5 mux_left_track_11 ( .in ( { chany_bottom_out[12] , chany_bottom_in[5] , chany_top_out[12] , left_bottom_grid_pin_38_[0] , chanx_left_out[19] } ) , @@ -37867,7 +39591,7 @@ sb_2__1__mux_2level_tapbuf_size5 mux_left_track_11 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_77 , SYNOPSYS_UNCONNECTED_78 , SYNOPSYS_UNCONNECTED_79 , SYNOPSYS_UNCONNECTED_80 } ) , .out ( chanx_left_out[5] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_198 ) ) ; + .p0 ( optlc_net_191 ) ) ; sb_2__1__mux_2level_tapbuf_size5_mem_0 mem_top_track_36 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( mux_2level_tapbuf_size7_mem_4_ccff_tail ) , @@ -37914,7 +39638,7 @@ sb_2__1__mux_2level_tapbuf_size10 mux_bottom_track_7 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_81 , SYNOPSYS_UNCONNECTED_82 , SYNOPSYS_UNCONNECTED_83 , SYNOPSYS_UNCONNECTED_84 } ) , .out ( chany_bottom_out[3] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_201 ) ) ; + .p0 ( optlc_net_187 ) ) ; sb_2__1__mux_2level_tapbuf_size10_mem mem_bottom_track_7 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( mux_2level_tapbuf_size8_mem_3_ccff_tail ) , @@ -37929,7 +39653,7 @@ sb_2__1__mux_2level_tapbuf_size6_0 mux_bottom_track_29 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_85 , SYNOPSYS_UNCONNECTED_86 , SYNOPSYS_UNCONNECTED_87 , SYNOPSYS_UNCONNECTED_88 } ) , .out ( chany_bottom_out[14] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_198 ) ) ; + .p0 ( optlc_net_187 ) ) ; sb_2__1__mux_2level_tapbuf_size6_1 mux_left_track_1 ( .in ( { chany_top_in[0] , chany_bottom_out[4] , chany_top_out[4] , left_bottom_grid_pin_36_[0] , left_bottom_grid_pin_39_[0] , @@ -37938,7 +39662,7 @@ sb_2__1__mux_2level_tapbuf_size6_1 mux_left_track_1 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_89 , SYNOPSYS_UNCONNECTED_90 , SYNOPSYS_UNCONNECTED_91 , SYNOPSYS_UNCONNECTED_92 } ) , .out ( chanx_left_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_200 ) ) ; + .p0 ( optlc_net_188 ) ) ; sb_2__1__mux_2level_tapbuf_size6_2 mux_left_track_3 ( .in ( { chany_bottom_out[7] , chany_bottom_in[0] , chany_top_out[7] , left_bottom_grid_pin_37_[0] , left_bottom_grid_pin_40_[0] , @@ -37947,7 +39671,7 @@ sb_2__1__mux_2level_tapbuf_size6_2 mux_left_track_3 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_93 , SYNOPSYS_UNCONNECTED_94 , SYNOPSYS_UNCONNECTED_95 , SYNOPSYS_UNCONNECTED_96 } ) , .out ( chanx_left_out[1] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_199 ) ) ; + .p0 ( optlc_net_188 ) ) ; sb_2__1__mux_2level_tapbuf_size6_3 mux_left_track_7 ( .in ( { chany_bottom_out[9] , chany_bottom_in[2] , chany_top_out[9] , left_bottom_grid_pin_36_[0] , left_bottom_grid_pin_39_[0] , @@ -37956,7 +39680,7 @@ sb_2__1__mux_2level_tapbuf_size6_3 mux_left_track_7 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_97 , SYNOPSYS_UNCONNECTED_98 , SYNOPSYS_UNCONNECTED_99 , SYNOPSYS_UNCONNECTED_100 } ) , .out ( chanx_left_out[3] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_200 ) ) ; + .p0 ( optlc_net_191 ) ) ; sb_2__1__mux_2level_tapbuf_size6 mux_left_track_9 ( .in ( { chany_bottom_out[11] , chany_bottom_in[4] , chany_top_out[11] , left_bottom_grid_pin_37_[0] , left_bottom_grid_pin_40_[0] , @@ -37965,7 +39689,7 @@ sb_2__1__mux_2level_tapbuf_size6 mux_left_track_9 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_101 , SYNOPSYS_UNCONNECTED_102 , SYNOPSYS_UNCONNECTED_103 , SYNOPSYS_UNCONNECTED_104 } ) , .out ( chanx_left_out[4] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_200 ) ) ; + .p0 ( optlc_net_191 ) ) ; sb_2__1__mux_2level_tapbuf_size6_mem_0 mem_bottom_track_29 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( mux_2level_tapbuf_size7_mem_6_ccff_tail ) , @@ -38003,7 +39727,7 @@ sb_2__1__mux_2level_tapbuf_size4_0 mux_bottom_track_37 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_105 , SYNOPSYS_UNCONNECTED_106 , SYNOPSYS_UNCONNECTED_107 , SYNOPSYS_UNCONNECTED_108 } ) , .out ( chany_bottom_out[18] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_198 ) ) ; + .p0 ( optlc_net_187 ) ) ; sb_2__1__mux_2level_tapbuf_size4_1 mux_bottom_track_45 ( .in ( { chany_bottom_out[17] , bottom_left_grid_pin_47_[0] , chanx_left_in[10] , chanx_left_in[21] } ) , @@ -38011,7 +39735,7 @@ sb_2__1__mux_2level_tapbuf_size4_1 mux_bottom_track_45 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_109 , SYNOPSYS_UNCONNECTED_110 , SYNOPSYS_UNCONNECTED_111 , SYNOPSYS_UNCONNECTED_112 } ) , .out ( chany_bottom_out[22] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_200 ) ) ; + .p0 ( optlc_net_187 ) ) ; sb_2__1__mux_2level_tapbuf_size4_2 mux_left_track_13 ( .in ( { chany_bottom_out[13] , chany_bottom_in[9] , chany_top_out[13] , left_bottom_grid_pin_36_[0] } ) , @@ -38019,7 +39743,7 @@ sb_2__1__mux_2level_tapbuf_size4_2 mux_left_track_13 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_113 , SYNOPSYS_UNCONNECTED_114 , SYNOPSYS_UNCONNECTED_115 , SYNOPSYS_UNCONNECTED_116 } ) , .out ( chanx_left_out[6] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_198 ) ) ; + .p0 ( optlc_net_187 ) ) ; sb_2__1__mux_2level_tapbuf_size4_3 mux_left_track_15 ( .in ( { chany_bottom_out[15] , chany_bottom_in[13] , chany_top_out[15] , left_bottom_grid_pin_37_[0] } ) , @@ -38027,7 +39751,7 @@ sb_2__1__mux_2level_tapbuf_size4_3 mux_left_track_15 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_117 , SYNOPSYS_UNCONNECTED_118 , SYNOPSYS_UNCONNECTED_119 , SYNOPSYS_UNCONNECTED_120 } ) , .out ( chanx_left_out[7] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_198 ) ) ; + .p0 ( optlc_net_191 ) ) ; sb_2__1__mux_2level_tapbuf_size4_4 mux_left_track_17 ( .in ( { chany_bottom_out[16] , chany_top_out[16] , chany_bottom_in[17] , left_bottom_grid_pin_38_[0] } ) , @@ -38035,7 +39759,7 @@ sb_2__1__mux_2level_tapbuf_size4_4 mux_left_track_17 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_121 , SYNOPSYS_UNCONNECTED_122 , SYNOPSYS_UNCONNECTED_123 , SYNOPSYS_UNCONNECTED_124 } ) , .out ( chanx_left_out[8] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_198 ) ) ; + .p0 ( optlc_net_191 ) ) ; sb_2__1__mux_2level_tapbuf_size4_5 mux_left_track_19 ( .in ( { chany_bottom_out[17] , chany_top_out[17] , chany_bottom_in[21] , left_bottom_grid_pin_39_[0] } ) , @@ -38043,7 +39767,7 @@ sb_2__1__mux_2level_tapbuf_size4_5 mux_left_track_19 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_125 , SYNOPSYS_UNCONNECTED_126 , SYNOPSYS_UNCONNECTED_127 , SYNOPSYS_UNCONNECTED_128 } ) , .out ( chanx_left_out[9] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_200 ) ) ; + .p0 ( optlc_net_191 ) ) ; sb_2__1__mux_2level_tapbuf_size4_6 mux_left_track_21 ( .in ( { chany_bottom_out[19] , chany_top_out[19] , chany_bottom_in[25] , left_bottom_grid_pin_40_[0] } ) , @@ -38051,7 +39775,7 @@ sb_2__1__mux_2level_tapbuf_size4_6 mux_left_track_21 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_129 , SYNOPSYS_UNCONNECTED_130 , SYNOPSYS_UNCONNECTED_131 , SYNOPSYS_UNCONNECTED_132 } ) , .out ( chanx_left_out[10] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_200 ) ) ; + .p0 ( optlc_net_191 ) ) ; sb_2__1__mux_2level_tapbuf_size4 mux_left_track_23 ( .in ( { chany_bottom_out[20] , chany_top_out[20] , chany_bottom_in[29] , chanx_left_out[19] } ) , @@ -38059,7 +39783,7 @@ sb_2__1__mux_2level_tapbuf_size4 mux_left_track_23 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_133 , SYNOPSYS_UNCONNECTED_134 , SYNOPSYS_UNCONNECTED_135 , SYNOPSYS_UNCONNECTED_136 } ) , .out ( chanx_left_out[11] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_198 ) ) ; + .p0 ( optlc_net_188 ) ) ; sb_2__1__mux_2level_tapbuf_size4_mem_0 mem_bottom_track_37 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( mux_2level_tapbuf_size6_mem_0_ccff_tail ) , @@ -38114,56 +39838,56 @@ sb_2__1__mux_2level_tapbuf_size3_0 mux_left_track_25 ( .sram ( mux_2level_tapbuf_size3_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_137 , SYNOPSYS_UNCONNECTED_138 } ) , .out ( chanx_left_out[12] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_200 ) ) ; + .p0 ( optlc_net_188 ) ) ; sb_2__1__mux_2level_tapbuf_size3_1 mux_left_track_27 ( .in ( { chany_bottom_out[23] , chany_top_out[23] , left_bottom_grid_pin_43_[0] } ) , .sram ( mux_2level_tapbuf_size3_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_139 , SYNOPSYS_UNCONNECTED_140 } ) , .out ( chanx_left_out[13] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_200 ) ) ; + .p0 ( optlc_net_188 ) ) ; sb_2__1__mux_2level_tapbuf_size3_2 mux_left_track_29 ( .in ( { chany_bottom_out[24] , chany_top_out[24] , left_bottom_grid_pin_36_[0] } ) , .sram ( mux_2level_tapbuf_size3_2_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_141 , SYNOPSYS_UNCONNECTED_142 } ) , .out ( chanx_left_out[14] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_200 ) ) ; + .p0 ( optlc_net_188 ) ) ; sb_2__1__mux_2level_tapbuf_size3_3 mux_left_track_31 ( .in ( { chany_bottom_out[25] , chany_top_out[25] , left_bottom_grid_pin_37_[0] } ) , .sram ( mux_2level_tapbuf_size3_3_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_143 , SYNOPSYS_UNCONNECTED_144 } ) , .out ( chanx_left_out[15] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_200 ) ) ; + .p0 ( optlc_net_191 ) ) ; sb_2__1__mux_2level_tapbuf_size3_4 mux_left_track_33 ( .in ( { chany_bottom_out[27] , chany_top_out[27] , left_bottom_grid_pin_38_[0] } ) , .sram ( mux_2level_tapbuf_size3_4_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_145 , SYNOPSYS_UNCONNECTED_146 } ) , .out ( chanx_left_out[16] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_198 ) ) ; + .p0 ( optlc_net_191 ) ) ; sb_2__1__mux_2level_tapbuf_size3_5 mux_left_track_35 ( .in ( { chany_bottom_out[28] , chany_top_out[28] , left_bottom_grid_pin_39_[0] } ) , .sram ( mux_2level_tapbuf_size3_5_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_147 , SYNOPSYS_UNCONNECTED_148 } ) , .out ( chanx_left_out[17] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_200 ) ) ; + .p0 ( optlc_net_191 ) ) ; sb_2__1__mux_2level_tapbuf_size3_6 mux_left_track_37 ( .in ( { chany_bottom_out[29] , chany_top_out[29] , left_bottom_grid_pin_40_[0] } ) , .sram ( mux_2level_tapbuf_size3_6_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_149 , SYNOPSYS_UNCONNECTED_150 } ) , .out ( chanx_left_out[18] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_200 ) ) ; + .p0 ( optlc_net_188 ) ) ; sb_2__1__mux_2level_tapbuf_size3 mux_left_track_51 ( .in ( { chany_top_in[9] , left_bottom_grid_pin_39_[0] , left_bottom_grid_pin_43_[0] } ) , .sram ( mux_2level_tapbuf_size3_7_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_151 , SYNOPSYS_UNCONNECTED_152 } ) , .out ( chanx_left_out[25] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_199 ) ) ; + .p0 ( optlc_net_188 ) ) ; sb_2__1__mux_2level_tapbuf_size3_mem_0 mem_left_track_25 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( mux_2level_tapbuf_size4_mem_7_ccff_tail ) , @@ -38217,43 +39941,43 @@ sb_2__1__mux_2level_tapbuf_size2_0 mux_left_track_41 ( .sram ( mux_2level_tapbuf_size2_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_153 , SYNOPSYS_UNCONNECTED_154 } ) , .out ( chanx_left_out[20] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_199 ) ) ; + .p0 ( optlc_net_189 ) ) ; sb_2__1__mux_2level_tapbuf_size2_1 mux_left_track_45 ( .in ( { chany_top_in[21] , left_bottom_grid_pin_36_[0] } ) , .sram ( mux_2level_tapbuf_size2_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_155 , SYNOPSYS_UNCONNECTED_156 } ) , .out ( chanx_left_out[22] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_199 ) ) ; + .p0 ( optlc_net_189 ) ) ; sb_2__1__mux_2level_tapbuf_size2_2 mux_left_track_47 ( .in ( { chany_top_in[17] , left_bottom_grid_pin_37_[0] } ) , .sram ( mux_2level_tapbuf_size2_2_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_157 , SYNOPSYS_UNCONNECTED_158 } ) , .out ( chanx_left_out[23] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_199 ) ) ; + .p0 ( optlc_net_188 ) ) ; sb_2__1__mux_2level_tapbuf_size2_3 mux_left_track_49 ( .in ( { chany_top_in[13] , left_bottom_grid_pin_38_[0] } ) , .sram ( mux_2level_tapbuf_size2_3_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_159 , SYNOPSYS_UNCONNECTED_160 } ) , .out ( chanx_left_out[24] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_199 ) ) ; + .p0 ( optlc_net_189 ) ) ; sb_2__1__mux_2level_tapbuf_size2_4 mux_left_track_53 ( .in ( { chany_top_in[5] , left_bottom_grid_pin_40_[0] } ) , .sram ( mux_2level_tapbuf_size2_4_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_161 , SYNOPSYS_UNCONNECTED_162 } ) , .out ( chanx_left_out[26] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_199 ) ) ; + .p0 ( optlc_net_189 ) ) ; sb_2__1__mux_2level_tapbuf_size2_5 mux_left_track_55 ( .in ( { chany_top_in[4] , chanx_left_out[19] } ) , .sram ( mux_2level_tapbuf_size2_5_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_163 , SYNOPSYS_UNCONNECTED_164 } ) , .out ( chanx_left_out[27] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_199 ) ) ; + .p0 ( optlc_net_188 ) ) ; sb_2__1__mux_2level_tapbuf_size2 mux_left_track_57 ( .in ( { chany_top_in[2] , left_bottom_grid_pin_42_[0] } ) , .sram ( mux_2level_tapbuf_size2_6_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_165 , SYNOPSYS_UNCONNECTED_166 } ) , .out ( chanx_left_out[28] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_199 ) ) ; + .p0 ( optlc_net_188 ) ) ; sb_2__1__mux_2level_tapbuf_size2_mem_0 mem_left_track_41 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( mux_2level_tapbuf_size3_mem_6_ccff_tail ) , @@ -38297,12 +40021,12 @@ sb_2__1__mux_2level_tapbuf_size2_mem mem_left_track_57 ( .pReset ( pReset ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sky130_fd_sc_hd__buf_8 pReset_FTB00 ( .A ( pReset_W_in ) , .X ( pReset[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_200 ( .LO ( SYNOPSYS_UNCONNECTED_167 ) , - .HI ( optlc_net_198 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_189 ( .LO ( SYNOPSYS_UNCONNECTED_167 ) , + .HI ( optlc_net_187 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_1 prog_clk_0_FTB00 ( .A ( prog_clk_0_N_in ) , .X ( prog_clk[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_1 FTB_110__109 ( .A ( chany_top_in[1] ) , - .X ( ropt_net_217 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .X ( ZBUF_250_f_0 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_8 FTB_111__110 ( .A ( chany_top_in[3] ) , .X ( chany_bottom_out[4] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_8 FTB_112__111 ( .A ( chany_top_in[6] ) , @@ -38336,7 +40060,7 @@ sky130_fd_sc_hd__buf_8 FTB_125__124 ( .A ( chany_top_in[23] ) , sky130_fd_sc_hd__buf_8 FTB_126__125 ( .A ( chany_top_in[24] ) , .X ( chany_bottom_out[25] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_1 FTB_127__126 ( .A ( chany_top_in[25] ) , - .X ( ZBUF_74_0 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .X ( ZBUF_263_f_0 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_8 FTB_128__127 ( .A ( chany_top_in[26] ) , .X ( chany_bottom_out[27] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_8 FTB_129__128 ( .A ( chany_top_in[27] ) , @@ -38383,23 +40107,23 @@ sky130_fd_sc_hd__buf_8 FTB_149__148 ( .A ( chany_bottom_in[28] ) , .X ( chany_top_out[29] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_8 FTB_150__149 ( .A ( left_bottom_grid_pin_41_[0] ) , .X ( chanx_left_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_196 ( .A ( BUF_net_197 ) , .Y ( pReset_N_out ) , +sky130_fd_sc_hd__inv_8 BINV_R_183 ( .A ( BUF_net_184 ) , .Y ( pReset_N_out ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_197 ( .A ( pReset_W_in ) , .Y ( BUF_net_197 ) , +sky130_fd_sc_hd__inv_1 BINV_R_184 ( .A ( pReset_W_in ) , .Y ( BUF_net_184 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_202 ( .LO ( SYNOPSYS_UNCONNECTED_168 ) , - .HI ( optlc_net_199 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_204 ( .LO ( SYNOPSYS_UNCONNECTED_169 ) , - .HI ( optlc_net_200 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_207 ( .LO ( SYNOPSYS_UNCONNECTED_170 ) , - .HI ( optlc_net_201 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_209 ( .LO ( SYNOPSYS_UNCONNECTED_171 ) , - .HI ( optlc_net_202 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_6 ZBUF_214_f_inst_210 ( .A ( aps_rename_508_ ) , - .X ( chany_bottom_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_6 ropt_mt_inst_1406 ( .A ( ropt_net_217 ) , +sky130_fd_sc_hd__conb_1 optlc_191 ( .LO ( SYNOPSYS_UNCONNECTED_168 ) , + .HI ( optlc_net_188 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_193 ( .LO ( SYNOPSYS_UNCONNECTED_169 ) , + .HI ( optlc_net_189 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_195 ( .LO ( SYNOPSYS_UNCONNECTED_170 ) , + .HI ( optlc_net_190 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_197 ( .LO ( SYNOPSYS_UNCONNECTED_171 ) , + .HI ( optlc_net_191 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_199 ( .LO ( SYNOPSYS_UNCONNECTED_172 ) , + .HI ( optlc_net_192 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 ZBUF_250_f_inst_1393 ( .A ( ZBUF_250_f_0 ) , .X ( chanx_left_out[29] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_6 ropt_mt_inst_1408 ( .A ( ZBUF_74_0 ) , +sky130_fd_sc_hd__buf_6 ropt_mt_inst_1396 ( .A ( ZBUF_263_f_0 ) , .X ( chanx_left_out[21] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -38414,7 +40138,7 @@ output [0:1] mem_out ; input VDD ; input VSS ; -wire copt_net_169 ; +wire copt_net_159 ; supply1 VDD ; supply0 VSS ; @@ -38422,14 +40146,14 @@ sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( copt_net_169 ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( copt_net_159 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_6 FTB_77__76 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_1 ropt_h_inst_1366 ( .A ( ropt_net_188 ) , +sky130_fd_sc_hd__buf_1 copt_h_inst_1344 ( .A ( copt_net_163 ) , .X ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_1 copt_h_inst_1348 ( .A ( copt_net_169 ) , - .X ( ropt_net_188 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 copt_h_inst_1346 ( .A ( copt_net_159 ) , + .X ( copt_net_163 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -39325,9 +41049,6 @@ wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; sb_2__0__mux_2level_tapbuf_basis_input2_mem1_85 mux_l1_in_0_ ( .in ( in ) , .mem ( sram[0] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) , @@ -39340,6 +41061,9 @@ sb_2__0__mux_2level_tapbuf_basis_input2_mem1 mux_l2_in_0_ ( .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_142 ( + .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -39395,9 +41119,6 @@ wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; sb_2__0__mux_2level_tapbuf_basis_input2_mem1_83 mux_l1_in_0_ ( .in ( in ) , .mem ( sram[0] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) , @@ -39410,6 +41131,9 @@ sb_2__0__mux_2level_tapbuf_basis_input2_mem1_84 mux_l2_in_0_ ( .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_141 ( + .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -39496,7 +41220,7 @@ input p0 ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__mux2_2 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , +sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -39566,7 +41290,7 @@ input p0 ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , +sky130_fd_sc_hd__mux2_2 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -39687,10 +41411,10 @@ sb_2__0__mux_2level_tapbuf_basis_input2_mem1_76 mux_l2_in_0_ ( .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_150 ( .A ( BUF_net_151 ) , .Y ( out[0] ) , +sky130_fd_sc_hd__inv_8 BINV_R_139 ( .A ( BUF_net_140 ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_151 ( - .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_151 ) , +sky130_fd_sc_hd__inv_1 BINV_R_140 ( + .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_140 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -39759,10 +41483,10 @@ sb_2__0__mux_2level_tapbuf_basis_input2_mem1_74 mux_l2_in_0_ ( .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_148 ( .A ( BUF_net_149 ) , .Y ( out[0] ) , +sky130_fd_sc_hd__inv_8 BINV_R_137 ( .A ( BUF_net_138 ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_149 ( - .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_149 ) , +sky130_fd_sc_hd__inv_1 BINV_R_138 ( + .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_138 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -39831,10 +41555,10 @@ sb_2__0__mux_2level_tapbuf_basis_input2_mem1_72 mux_l2_in_0_ ( .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_146 ( .A ( BUF_net_147 ) , .Y ( out[0] ) , +sky130_fd_sc_hd__inv_8 BINV_R_145 ( .A ( BUF_net_146 ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_147 ( - .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_147 ) , +sky130_fd_sc_hd__inv_1 BINV_R_146 ( + .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_146 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -39852,7 +41576,7 @@ input p0 ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__mux2_2 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , +sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -39891,9 +41615,6 @@ wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; sb_2__0__mux_2level_tapbuf_basis_input2_mem1_69 mux_l1_in_0_ ( .in ( in ) , .mem ( sram[0] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) , @@ -39906,6 +41627,11 @@ sb_2__0__mux_2level_tapbuf_basis_input2_mem1_70 mux_l2_in_0_ ( .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_135 ( .A ( BUF_net_136 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_136 ( + .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_136 ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -39922,7 +41648,7 @@ input p0 ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__mux2_2 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , +sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -39961,9 +41687,6 @@ wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; sb_2__0__mux_2level_tapbuf_basis_input2_mem1_67 mux_l1_in_0_ ( .in ( in ) , .mem ( sram[0] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) , @@ -39976,6 +41699,11 @@ sb_2__0__mux_2level_tapbuf_basis_input2_mem1_68 mux_l2_in_0_ ( .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_133 ( .A ( BUF_net_134 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_134 ( + .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_134 ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -39992,7 +41720,7 @@ input p0 ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , +sky130_fd_sc_hd__mux2_2 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -40031,6 +41759,9 @@ wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ; supply1 VDD ; supply0 VSS ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; sb_2__0__mux_2level_tapbuf_basis_input2_mem1_65 mux_l1_in_0_ ( .in ( in ) , .mem ( sram[0] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) , @@ -40043,11 +41774,6 @@ sb_2__0__mux_2level_tapbuf_basis_input2_mem1_66 mux_l2_in_0_ ( .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_144 ( .A ( BUF_net_145 ) , .Y ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_145 ( - .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_145 ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -40064,7 +41790,7 @@ input p0 ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , +sky130_fd_sc_hd__mux2_2 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -40103,6 +41829,9 @@ wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ; supply1 VDD ; supply0 VSS ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; sb_2__0__mux_2level_tapbuf_basis_input2_mem1_63 mux_l1_in_0_ ( .in ( in ) , .mem ( sram[0] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) , @@ -40115,11 +41844,6 @@ sb_2__0__mux_2level_tapbuf_basis_input2_mem1_64 mux_l2_in_0_ ( .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_142 ( .A ( BUF_net_143 ) , .Y ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_143 ( - .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_143 ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -40136,7 +41860,7 @@ input p0 ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , +sky130_fd_sc_hd__mux2_2 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -40175,6 +41899,9 @@ wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ; supply1 VDD ; supply0 VSS ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; sb_2__0__mux_2level_tapbuf_basis_input2_mem1_61 mux_l1_in_0_ ( .in ( in ) , .mem ( sram[0] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) , @@ -40187,11 +41914,6 @@ sb_2__0__mux_2level_tapbuf_basis_input2_mem1_62 mux_l2_in_0_ ( .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_140 ( .A ( BUF_net_141 ) , .Y ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_141 ( - .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_141 ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -40208,7 +41930,7 @@ input p0 ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , +sky130_fd_sc_hd__mux2_2 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -40247,6 +41969,9 @@ wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ; supply1 VDD ; supply0 VSS ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; sb_2__0__mux_2level_tapbuf_basis_input2_mem1_59 mux_l1_in_0_ ( .in ( in ) , .mem ( sram[0] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) , @@ -40259,11 +41984,6 @@ sb_2__0__mux_2level_tapbuf_basis_input2_mem1_60 mux_l2_in_0_ ( .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_138 ( .A ( BUF_net_139 ) , .Y ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_139 ( - .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_139 ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -40280,7 +42000,7 @@ input p0 ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , +sky130_fd_sc_hd__mux2_2 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -40319,6 +42039,9 @@ wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ; supply1 VDD ; supply0 VSS ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; sb_2__0__mux_2level_tapbuf_basis_input2_mem1_57 mux_l1_in_0_ ( .in ( in ) , .mem ( sram[0] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) , @@ -40331,11 +42054,6 @@ sb_2__0__mux_2level_tapbuf_basis_input2_mem1_58 mux_l2_in_0_ ( .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_136 ( .A ( BUF_net_137 ) , .Y ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_137 ( - .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_137 ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -40352,7 +42070,7 @@ input p0 ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , +sky130_fd_sc_hd__mux2_2 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -40403,10 +42121,8 @@ sb_2__0__mux_2level_tapbuf_basis_input2_mem1_56 mux_l2_in_0_ ( .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_134 ( .A ( BUF_net_135 ) , .Y ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_135 ( - .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_135 ) , +sky130_fd_sc_hd__buf_6 BUFT_RR_132 ( + .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -40424,7 +42140,7 @@ input p0 ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__mux2_2 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , +sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -40475,8 +42191,10 @@ sb_2__0__mux_2level_tapbuf_basis_input2_mem1_54 mux_l2_in_0_ ( .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_133 ( - .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) , +sky130_fd_sc_hd__inv_8 BINV_R_130 ( .A ( BUF_net_131 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_131 ( + .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_131 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -40603,6 +42321,9 @@ wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ; supply1 VDD ; supply0 VSS ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; sb_2__0__mux_2level_tapbuf_basis_input2_mem1_49 mux_l1_in_0_ ( .in ( in ) , .mem ( sram[0] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) , @@ -40615,9 +42336,6 @@ sb_2__0__mux_2level_tapbuf_basis_input2_mem1_50 mux_l2_in_0_ ( .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_132 ( - .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -40634,7 +42352,7 @@ input p0 ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__mux2_2 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , +sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -40704,7 +42422,7 @@ input p0 ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__mux2_2 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , +sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -40813,9 +42531,6 @@ wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; sb_2__0__mux_2level_tapbuf_basis_input2_mem1_43 mux_l1_in_0_ ( .in ( in ) , .mem ( sram[0] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) , @@ -40828,6 +42543,11 @@ sb_2__0__mux_2level_tapbuf_basis_input2_mem1_44 mux_l2_in_0_ ( .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_128 ( .A ( BUF_net_129 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_129 ( + .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_129 ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -40844,7 +42564,7 @@ input p0 ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , +sky130_fd_sc_hd__mux2_2 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -40895,10 +42615,8 @@ sb_2__0__mux_2level_tapbuf_basis_input2_mem1_42 mux_l2_in_0_ ( .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_130 ( .A ( BUF_net_131 ) , .Y ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_131 ( - .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_131 ) , +sky130_fd_sc_hd__buf_6 BUFT_RR_127 ( + .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -40916,7 +42634,7 @@ input p0 ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , +sky130_fd_sc_hd__mux2_2 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -40967,10 +42685,8 @@ sb_2__0__mux_2level_tapbuf_basis_input2_mem1_40 mux_l2_in_0_ ( .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_128 ( .A ( BUF_net_129 ) , .Y ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_129 ( - .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_129 ) , +sky130_fd_sc_hd__buf_6 BUFT_RR_126 ( + .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -41039,10 +42755,10 @@ sb_2__0__mux_2level_tapbuf_basis_input2_mem1_38 mux_l2_in_0_ ( .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_126 ( .A ( BUF_net_127 ) , .Y ( out[0] ) , +sky130_fd_sc_hd__inv_8 BINV_R_124 ( .A ( BUF_net_125 ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_127 ( - .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_127 ) , +sky130_fd_sc_hd__inv_1 BINV_R_125 ( + .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_125 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -41060,7 +42776,7 @@ input p0 ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , +sky130_fd_sc_hd__mux2_2 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -41111,10 +42827,8 @@ sb_2__0__mux_2level_tapbuf_basis_input2_mem1_36 mux_l2_in_0_ ( .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_124 ( .A ( BUF_net_125 ) , .Y ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_125 ( - .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_125 ) , +sky130_fd_sc_hd__buf_6 BUFT_RR_123 ( + .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -41132,7 +42846,7 @@ input p0 ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , +sky130_fd_sc_hd__mux2_2 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -41183,10 +42897,8 @@ sb_2__0__mux_2level_tapbuf_basis_input2_mem1_34 mux_l2_in_0_ ( .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_122 ( .A ( BUF_net_123 ) , .Y ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_123 ( - .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_123 ) , +sky130_fd_sc_hd__buf_6 BUFT_RR_122 ( + .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -41274,7 +42986,7 @@ input p0 ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , +sky130_fd_sc_hd__mux2_2 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -41325,10 +43037,8 @@ sb_2__0__mux_2level_tapbuf_basis_input2_mem1_30 mux_l2_in_0_ ( .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_120 ( .A ( BUF_net_121 ) , .Y ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_121 ( - .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_121 ) , +sky130_fd_sc_hd__buf_6 BUFT_RR_121 ( + .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -41397,10 +43107,10 @@ sb_2__0__mux_2level_tapbuf_basis_input2_mem1_28 mux_l2_in_0_ ( .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_118 ( .A ( BUF_net_119 ) , .Y ( out[0] ) , +sky130_fd_sc_hd__inv_8 BINV_R_119 ( .A ( BUF_net_120 ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_119 ( - .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_119 ) , +sky130_fd_sc_hd__inv_1 BINV_R_120 ( + .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_120 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -41469,10 +43179,10 @@ sb_2__0__mux_2level_tapbuf_basis_input2_mem1_26 mux_l2_in_0_ ( .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_116 ( .A ( BUF_net_117 ) , .Y ( out[0] ) , +sky130_fd_sc_hd__inv_8 BINV_R_117 ( .A ( BUF_net_118 ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_117 ( - .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_117 ) , +sky130_fd_sc_hd__inv_1 BINV_R_118 ( + .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_118 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -41529,6 +43239,9 @@ wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ; supply1 VDD ; supply0 VSS ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; sb_2__0__mux_2level_tapbuf_basis_input2_mem1_23 mux_l1_in_0_ ( .in ( in ) , .mem ( sram[0] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) , @@ -41541,11 +43254,6 @@ sb_2__0__mux_2level_tapbuf_basis_input2_mem1_24 mux_l2_in_0_ ( .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_114 ( .A ( BUF_net_115 ) , .Y ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_115 ( - .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_115 ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -41613,8 +43321,10 @@ sb_2__0__mux_2level_tapbuf_basis_input2_mem1_22 mux_l2_in_0_ ( .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_113 ( - .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) , +sky130_fd_sc_hd__inv_8 BINV_R_115 ( .A ( BUF_net_116 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_116 ( + .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_116 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -41683,10 +43393,10 @@ sb_2__0__mux_2level_tapbuf_basis_input2_mem1_20 mux_l2_in_0_ ( .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_111 ( .A ( BUF_net_112 ) , .Y ( out[0] ) , +sky130_fd_sc_hd__inv_8 BINV_R_113 ( .A ( BUF_net_114 ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_112 ( - .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_112 ) , +sky130_fd_sc_hd__inv_1 BINV_R_114 ( + .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_114 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -41743,6 +43453,9 @@ wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ; supply1 VDD ; supply0 VSS ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; sb_2__0__mux_2level_tapbuf_basis_input2_mem1_17 mux_l1_in_0_ ( .in ( in ) , .mem ( sram[0] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) , @@ -41755,11 +43468,6 @@ sb_2__0__mux_2level_tapbuf_basis_input2_mem1_18 mux_l2_in_0_ ( .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_109 ( .A ( BUF_net_110 ) , .Y ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_110 ( - .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_110 ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -41965,7 +43673,7 @@ input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) , +sky130_fd_sc_hd__mux2_2 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -42042,10 +43750,8 @@ sb_2__0__mux_2level_tapbuf_basis_input2_mem1_14 mux_l2_in_0_ ( .mem_inv ( { SYNOPSYS_UNCONNECTED_4 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_2_out ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_107 ( .A ( BUF_net_108 ) , .Y ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_108 ( - .A ( mux_2level_tapbuf_basis_input2_mem1_2_out[0] ) , .Y ( BUF_net_108 ) , +sky130_fd_sc_hd__buf_6 BUFT_RR_112 ( + .A ( mux_2level_tapbuf_basis_input2_mem1_2_out[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -42062,7 +43768,7 @@ input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) , +sky130_fd_sc_hd__mux2_2 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -42139,10 +43845,8 @@ sb_2__0__mux_2level_tapbuf_basis_input2_mem1_11 mux_l2_in_0_ ( .mem_inv ( { SYNOPSYS_UNCONNECTED_4 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_2_out ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_105 ( .A ( BUF_net_106 ) , .Y ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_106 ( - .A ( mux_2level_tapbuf_basis_input2_mem1_2_out[0] ) , .Y ( BUF_net_106 ) , +sky130_fd_sc_hd__buf_6 BUFT_RR_111 ( + .A ( mux_2level_tapbuf_basis_input2_mem1_2_out[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -42159,7 +43863,7 @@ input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__mux2_2 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) , +sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -42218,9 +43922,6 @@ wire [0:0] mux_2level_tapbuf_basis_input2_mem1_2_out ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( mux_2level_tapbuf_basis_input2_mem1_2_out[0] ) , .X ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; sb_2__0__mux_2level_tapbuf_basis_input2_mem1_6 mux_l1_in_0_ ( .in ( in[0:1] ) , .mem ( sram[0] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) , @@ -42239,6 +43940,11 @@ sb_2__0__mux_2level_tapbuf_basis_input2_mem1_8 mux_l2_in_0_ ( .mem_inv ( { SYNOPSYS_UNCONNECTED_4 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_2_out ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_109 ( .A ( BUF_net_110 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_110 ( + .A ( mux_2level_tapbuf_basis_input2_mem1_2_out[0] ) , .Y ( BUF_net_110 ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -42254,7 +43960,7 @@ input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__mux2_2 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) , +sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -42313,9 +44019,6 @@ wire [0:0] mux_2level_tapbuf_basis_input2_mem1_2_out ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( mux_2level_tapbuf_basis_input2_mem1_2_out[0] ) , .X ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; sb_2__0__mux_2level_tapbuf_basis_input2_mem1_3 mux_l1_in_0_ ( .in ( in[0:1] ) , .mem ( sram[0] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) , @@ -42334,6 +44037,11 @@ sb_2__0__mux_2level_tapbuf_basis_input2_mem1_5 mux_l2_in_0_ ( .mem_inv ( { SYNOPSYS_UNCONNECTED_4 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_2_out ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_107 ( .A ( BUF_net_108 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_108 ( + .A ( mux_2level_tapbuf_basis_input2_mem1_2_out[0] ) , .Y ( BUF_net_108 ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -42408,9 +44116,6 @@ wire [0:0] mux_2level_tapbuf_basis_input2_mem1_2_out ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( mux_2level_tapbuf_basis_input2_mem1_2_out[0] ) , .X ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; sb_2__0__mux_2level_tapbuf_basis_input2_mem1_0 mux_l1_in_0_ ( .in ( in[0:1] ) , .mem ( sram[0] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) , @@ -42429,6 +44134,11 @@ sb_2__0__mux_2level_tapbuf_basis_input2_mem1_2 mux_l2_in_0_ ( .mem_inv ( { SYNOPSYS_UNCONNECTED_4 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_2_out ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_105 ( .A ( BUF_net_106 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_106 ( + .A ( mux_2level_tapbuf_basis_input2_mem1_2_out[0] ) , .Y ( BUF_net_106 ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -42775,7 +44485,7 @@ input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ropt_net_186 ) , +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ropt_net_182 ) , .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , @@ -42789,28 +44499,28 @@ sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_1 FTB_25__24 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1338 ( .A ( copt_net_161 ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1336 ( .A ( ccff_head[0] ) , + .X ( copt_net_153 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1337 ( .A ( copt_net_158 ) , + .X ( copt_net_154 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1338 ( .A ( copt_net_156 ) , + .X ( copt_net_155 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1339 ( .A ( copt_net_154 ) , + .X ( copt_net_156 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1340 ( .A ( copt_net_155 ) , + .X ( copt_net_157 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1341 ( .A ( copt_net_153 ) , .X ( copt_net_158 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1339 ( .A ( copt_net_158 ) , - .X ( copt_net_159 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1340 ( .A ( copt_net_163 ) , - .X ( copt_net_160 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1341 ( .A ( ccff_head[0] ) , - .X ( copt_net_161 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1342 ( .A ( copt_net_159 ) , - .X ( copt_net_162 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1343 ( .A ( copt_net_162 ) , - .X ( copt_net_163 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1361 ( .A ( ropt_net_184 ) , - .X ( ropt_net_183 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1362 ( .A ( copt_net_160 ) , - .X ( ropt_net_184 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1363 ( .A ( ropt_net_183 ) , - .X ( ropt_net_185 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1364 ( .A ( ropt_net_187 ) , - .X ( ropt_net_186 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1365 ( .A ( ropt_net_185 ) , - .X ( ropt_net_187 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1359 ( .A ( copt_net_157 ) , + .X ( ropt_net_178 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1360 ( .A ( ropt_net_178 ) , + .X ( ropt_net_179 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1361 ( .A ( ropt_net_179 ) , + .X ( ropt_net_180 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1362 ( .A ( ropt_net_180 ) , + .X ( ropt_net_181 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1363 ( .A ( ropt_net_181 ) , + .X ( ropt_net_182 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -42824,13 +44534,16 @@ input VDD ; input VSS ; input p0 ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -42843,13 +44556,16 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -42958,13 +44674,16 @@ input VDD ; input VSS ; input p0 ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -42977,13 +44696,16 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -43092,13 +44814,16 @@ input VDD ; input VSS ; input p0 ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -43111,13 +44836,16 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -43226,13 +44954,16 @@ input VDD ; input VSS ; input p0 ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -43245,13 +44976,16 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -43360,13 +45094,16 @@ input VDD ; input VSS ; input p0 ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -43379,13 +45116,16 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -43494,13 +45234,16 @@ input VDD ; input VSS ; input p0 ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -43513,13 +45256,16 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -43628,13 +45374,16 @@ input VDD ; input VSS ; input p0 ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -43647,13 +45396,16 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -43744,8 +45496,10 @@ sb_2__0__mux_2level_tapbuf_basis_input3_mem3_11 mux_l2_in_0_ ( .mem_inv ( local_encoder2to3_1_data_inv ) , .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_92 ( - .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .X ( out[0] ) , +sky130_fd_sc_hd__inv_8 BINV_R_91 ( .A ( BUF_net_92 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_92 ( + .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_92 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -43760,13 +45514,16 @@ input VDD ; input VSS ; input p0 ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -43779,13 +45536,16 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -43876,10 +45636,10 @@ sb_2__0__mux_2level_tapbuf_basis_input3_mem3_9 mux_l2_in_0_ ( .mem_inv ( local_encoder2to3_1_data_inv ) , .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_90 ( .A ( BUF_net_91 ) , .Y ( out[0] ) , +sky130_fd_sc_hd__inv_8 BINV_R_89 ( .A ( BUF_net_90 ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_91 ( - .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_91 ) , +sky130_fd_sc_hd__inv_1 BINV_R_90 ( + .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_90 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -43894,13 +45654,16 @@ input VDD ; input VSS ; input p0 ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -43913,13 +45676,16 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -44010,10 +45776,8 @@ sb_2__0__mux_2level_tapbuf_basis_input3_mem3_7 mux_l2_in_0_ ( .mem_inv ( local_encoder2to3_1_data_inv ) , .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_88 ( .A ( BUF_net_89 ) , .Y ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_89 ( - .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_89 ) , +sky130_fd_sc_hd__buf_6 BUFT_RR_88 ( + .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -44028,13 +45792,16 @@ input VDD ; input VSS ; input p0 ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -44047,13 +45814,16 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -44160,13 +45930,16 @@ input VDD ; input VSS ; input p0 ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -44179,13 +45952,16 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -44294,13 +46070,16 @@ input VDD ; input VSS ; input p0 ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -44313,13 +46092,16 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -44578,7 +46360,7 @@ sb_2__0__mux_2level_tapbuf_size4_0 mux_top_track_0 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 , SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) , .out ( chany_top_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_156 ) ) ; + .p0 ( optlc_net_149 ) ) ; sb_2__0__mux_2level_tapbuf_size4_1 mux_top_track_2 ( .in ( { top_left_grid_pin_45_[0] , top_left_grid_pin_48_[0] , top_left_grid_pin_51_[0] , chanx_left_in[29] } ) , @@ -44586,7 +46368,7 @@ sb_2__0__mux_2level_tapbuf_size4_1 mux_top_track_2 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 , SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 } ) , .out ( chany_top_out[1] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_156 ) ) ; + .p0 ( optlc_net_149 ) ) ; sb_2__0__mux_2level_tapbuf_size4_2 mux_top_track_4 ( .in ( { top_left_grid_pin_46_[0] , top_left_grid_pin_49_[0] , top_right_grid_pin_1_[0] , chanx_left_in[28] } ) , @@ -44594,7 +46376,7 @@ sb_2__0__mux_2level_tapbuf_size4_2 mux_top_track_4 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_9 , SYNOPSYS_UNCONNECTED_10 , SYNOPSYS_UNCONNECTED_11 , SYNOPSYS_UNCONNECTED_12 } ) , .out ( chany_top_out[2] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_156 ) ) ; + .p0 ( optlc_net_149 ) ) ; sb_2__0__mux_2level_tapbuf_size4_3 mux_top_track_6 ( .in ( { top_left_grid_pin_44_[0] , top_left_grid_pin_47_[0] , top_left_grid_pin_50_[0] , chanx_left_in[27] } ) , @@ -44602,7 +46384,7 @@ sb_2__0__mux_2level_tapbuf_size4_3 mux_top_track_6 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 , SYNOPSYS_UNCONNECTED_15 , SYNOPSYS_UNCONNECTED_16 } ) , .out ( chany_top_out[3] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_156 ) ) ; + .p0 ( optlc_net_149 ) ) ; sb_2__0__mux_2level_tapbuf_size4_4 mux_top_track_8 ( .in ( { top_left_grid_pin_45_[0] , top_left_grid_pin_48_[0] , top_left_grid_pin_51_[0] , chanx_left_in[26] } ) , @@ -44610,7 +46392,7 @@ sb_2__0__mux_2level_tapbuf_size4_4 mux_top_track_8 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_17 , SYNOPSYS_UNCONNECTED_18 , SYNOPSYS_UNCONNECTED_19 , SYNOPSYS_UNCONNECTED_20 } ) , .out ( chany_top_out[4] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_156 ) ) ; + .p0 ( optlc_net_151 ) ) ; sb_2__0__mux_2level_tapbuf_size4_5 mux_top_track_10 ( .in ( { top_left_grid_pin_46_[0] , top_left_grid_pin_49_[0] , top_right_grid_pin_1_[0] , chanx_left_in[25] } ) , @@ -44618,7 +46400,7 @@ sb_2__0__mux_2level_tapbuf_size4_5 mux_top_track_10 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_21 , SYNOPSYS_UNCONNECTED_22 , SYNOPSYS_UNCONNECTED_23 , SYNOPSYS_UNCONNECTED_24 } ) , .out ( chany_top_out[5] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_156 ) ) ; + .p0 ( optlc_net_152 ) ) ; sb_2__0__mux_2level_tapbuf_size4_6 mux_left_track_1 ( .in ( { chany_top_in[0] , left_bottom_grid_pin_1_[0] , left_bottom_grid_pin_7_[0] , left_bottom_grid_pin_13_[0] } ) , @@ -44626,7 +46408,7 @@ sb_2__0__mux_2level_tapbuf_size4_6 mux_left_track_1 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_25 , SYNOPSYS_UNCONNECTED_26 , SYNOPSYS_UNCONNECTED_27 , SYNOPSYS_UNCONNECTED_28 } ) , .out ( chanx_left_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_154 ) ) ; + .p0 ( optlc_net_147 ) ) ; sb_2__0__mux_2level_tapbuf_size4_7 mux_left_track_3 ( .in ( { chany_top_in[29] , left_bottom_grid_pin_3_[0] , left_bottom_grid_pin_9_[0] , left_bottom_grid_pin_15_[0] } ) , @@ -44634,7 +46416,7 @@ sb_2__0__mux_2level_tapbuf_size4_7 mux_left_track_3 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_29 , SYNOPSYS_UNCONNECTED_30 , SYNOPSYS_UNCONNECTED_31 , SYNOPSYS_UNCONNECTED_32 } ) , .out ( chanx_left_out[1] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_154 ) ) ; + .p0 ( optlc_net_147 ) ) ; sb_2__0__mux_2level_tapbuf_size4_8 mux_left_track_5 ( .in ( { chany_top_in[28] , left_bottom_grid_pin_5_[0] , left_bottom_grid_pin_11_[0] , left_bottom_grid_pin_17_[0] } ) , @@ -44642,7 +46424,7 @@ sb_2__0__mux_2level_tapbuf_size4_8 mux_left_track_5 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_33 , SYNOPSYS_UNCONNECTED_34 , SYNOPSYS_UNCONNECTED_35 , SYNOPSYS_UNCONNECTED_36 } ) , .out ( chanx_left_out[2] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_154 ) ) ; + .p0 ( optlc_net_147 ) ) ; sb_2__0__mux_2level_tapbuf_size4_9 mux_left_track_7 ( .in ( { chany_top_in[27] , left_bottom_grid_pin_1_[0] , left_bottom_grid_pin_7_[0] , left_bottom_grid_pin_13_[0] } ) , @@ -44650,7 +46432,7 @@ sb_2__0__mux_2level_tapbuf_size4_9 mux_left_track_7 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_37 , SYNOPSYS_UNCONNECTED_38 , SYNOPSYS_UNCONNECTED_39 , SYNOPSYS_UNCONNECTED_40 } ) , .out ( chanx_left_out[3] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_154 ) ) ; + .p0 ( optlc_net_147 ) ) ; sb_2__0__mux_2level_tapbuf_size4_10 mux_left_track_9 ( .in ( { chany_top_in[26] , left_bottom_grid_pin_3_[0] , left_bottom_grid_pin_9_[0] , left_bottom_grid_pin_15_[0] } ) , @@ -44658,7 +46440,7 @@ sb_2__0__mux_2level_tapbuf_size4_10 mux_left_track_9 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_41 , SYNOPSYS_UNCONNECTED_42 , SYNOPSYS_UNCONNECTED_43 , SYNOPSYS_UNCONNECTED_44 } ) , .out ( chanx_left_out[4] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_154 ) ) ; + .p0 ( optlc_net_149 ) ) ; sb_2__0__mux_2level_tapbuf_size4 mux_left_track_11 ( .in ( { chany_top_in[25] , left_bottom_grid_pin_5_[0] , left_bottom_grid_pin_11_[0] , left_bottom_grid_pin_17_[0] } ) , @@ -44666,7 +46448,7 @@ sb_2__0__mux_2level_tapbuf_size4 mux_left_track_11 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_45 , SYNOPSYS_UNCONNECTED_46 , SYNOPSYS_UNCONNECTED_47 , SYNOPSYS_UNCONNECTED_48 } ) , .out ( chanx_left_out[5] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_156 ) ) ; + .p0 ( optlc_net_151 ) ) ; sb_2__0__mux_2level_tapbuf_size4_mem_0 mem_top_track_0 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( mux_2level_tapbuf_size4_mem_0_ccff_tail ) , @@ -44744,35 +46526,35 @@ sb_2__0__mux_2level_tapbuf_size3_0 mux_top_track_12 ( .sram ( mux_2level_tapbuf_size3_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_49 , SYNOPSYS_UNCONNECTED_50 } ) , .out ( chany_top_out[6] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_157 ) ) ; + .p0 ( optlc_net_148 ) ) ; sb_2__0__mux_2level_tapbuf_size3_1 mux_top_track_44 ( .in ( { top_left_grid_pin_48_[0] , top_right_grid_pin_1_[0] , chanx_left_in[8] } ) , .sram ( mux_2level_tapbuf_size3_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_51 , SYNOPSYS_UNCONNECTED_52 } ) , .out ( chany_top_out[22] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_156 ) ) ; + .p0 ( optlc_net_151 ) ) ; sb_2__0__mux_2level_tapbuf_size3_2 mux_left_track_13 ( .in ( { chany_top_in[24] , left_bottom_grid_pin_1_[0] , left_bottom_grid_pin_17_[0] } ) , .sram ( mux_2level_tapbuf_size3_2_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_53 , SYNOPSYS_UNCONNECTED_54 } ) , .out ( chanx_left_out[6] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_157 ) ) ; + .p0 ( optlc_net_151 ) ) ; sb_2__0__mux_2level_tapbuf_size3_3 mux_left_track_29 ( .in ( { chany_top_in[16] , left_bottom_grid_pin_1_[0] , left_bottom_grid_pin_17_[0] } ) , .sram ( mux_2level_tapbuf_size3_3_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_55 , SYNOPSYS_UNCONNECTED_56 } ) , .out ( chanx_left_out[14] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_155 ) ) ; + .p0 ( optlc_net_147 ) ) ; sb_2__0__mux_2level_tapbuf_size3 mux_left_track_45 ( .in ( { chany_top_in[8] , left_bottom_grid_pin_1_[0] , left_bottom_grid_pin_17_[0] } ) , .sram ( mux_2level_tapbuf_size3_4_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_57 , SYNOPSYS_UNCONNECTED_58 } ) , .out ( chanx_left_out[22] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_155 ) ) ; + .p0 ( optlc_net_147 ) ) ; sb_2__0__mux_2level_tapbuf_size3_mem_0 mem_top_track_12 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( mux_2level_tapbuf_size4_mem_5_ccff_tail ) , @@ -44808,217 +46590,217 @@ sb_2__0__mux_2level_tapbuf_size2_0 mux_top_track_14 ( .sram ( mux_2level_tapbuf_size2_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_59 , SYNOPSYS_UNCONNECTED_60 } ) , .out ( chany_top_out[7] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_157 ) ) ; + .p0 ( optlc_net_148 ) ) ; sb_2__0__mux_2level_tapbuf_size2_1 mux_top_track_16 ( .in ( { top_left_grid_pin_46_[0] , chanx_left_in[22] } ) , .sram ( mux_2level_tapbuf_size2_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_61 , SYNOPSYS_UNCONNECTED_62 } ) , .out ( chany_top_out[8] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_157 ) ) ; + .p0 ( optlc_net_152 ) ) ; sb_2__0__mux_2level_tapbuf_size2_2 mux_top_track_18 ( .in ( { top_left_grid_pin_47_[0] , chanx_left_in[21] } ) , .sram ( mux_2level_tapbuf_size2_2_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_63 , SYNOPSYS_UNCONNECTED_64 } ) , .out ( chany_top_out[9] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_157 ) ) ; + .p0 ( optlc_net_148 ) ) ; sb_2__0__mux_2level_tapbuf_size2_3 mux_top_track_20 ( .in ( { top_left_grid_pin_48_[0] , chanx_left_in[20] } ) , .sram ( mux_2level_tapbuf_size2_3_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_65 , SYNOPSYS_UNCONNECTED_66 } ) , .out ( chany_top_out[10] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_157 ) ) ; + .p0 ( optlc_net_150 ) ) ; sb_2__0__mux_2level_tapbuf_size2_4 mux_top_track_22 ( .in ( { top_left_grid_pin_49_[0] , chanx_left_in[19] } ) , .sram ( mux_2level_tapbuf_size2_4_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_67 , SYNOPSYS_UNCONNECTED_68 } ) , .out ( chany_top_out[11] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_157 ) ) ; + .p0 ( optlc_net_150 ) ) ; sb_2__0__mux_2level_tapbuf_size2_5 mux_top_track_24 ( .in ( { top_left_grid_pin_50_[0] , chanx_left_in[18] } ) , .sram ( mux_2level_tapbuf_size2_5_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_69 , SYNOPSYS_UNCONNECTED_70 } ) , .out ( chany_top_out[12] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_155 ) ) ; + .p0 ( optlc_net_148 ) ) ; sb_2__0__mux_2level_tapbuf_size2_6 mux_top_track_26 ( .in ( { top_left_grid_pin_51_[0] , chanx_left_in[17] } ) , .sram ( mux_2level_tapbuf_size2_6_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_71 , SYNOPSYS_UNCONNECTED_72 } ) , .out ( chany_top_out[13] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_155 ) ) ; + .p0 ( optlc_net_150 ) ) ; sb_2__0__mux_2level_tapbuf_size2_7 mux_top_track_28 ( .in ( { top_right_grid_pin_1_[0] , chanx_left_in[16] } ) , .sram ( mux_2level_tapbuf_size2_7_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_73 , SYNOPSYS_UNCONNECTED_74 } ) , .out ( chany_top_out[14] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_157 ) ) ; + .p0 ( optlc_net_148 ) ) ; sb_2__0__mux_2level_tapbuf_size2_8 mux_top_track_36 ( .in ( { top_left_grid_pin_44_[0] , chanx_left_in[12] } ) , .sram ( mux_2level_tapbuf_size2_8_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_75 , SYNOPSYS_UNCONNECTED_76 } ) , .out ( chany_top_out[18] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_157 ) ) ; + .p0 ( optlc_net_148 ) ) ; sb_2__0__mux_2level_tapbuf_size2_9 mux_top_track_38 ( .in ( { top_left_grid_pin_45_[0] , chanx_left_in[11] } ) , .sram ( mux_2level_tapbuf_size2_9_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_77 , SYNOPSYS_UNCONNECTED_78 } ) , .out ( chany_top_out[19] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_157 ) ) ; + .p0 ( optlc_net_148 ) ) ; sb_2__0__mux_2level_tapbuf_size2_10 mux_top_track_40 ( .in ( { top_left_grid_pin_46_[0] , chanx_left_in[10] } ) , .sram ( mux_2level_tapbuf_size2_10_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_79 , SYNOPSYS_UNCONNECTED_80 } ) , .out ( chany_top_out[20] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_157 ) ) ; + .p0 ( optlc_net_148 ) ) ; sb_2__0__mux_2level_tapbuf_size2_11 mux_top_track_42 ( .in ( { top_left_grid_pin_47_[0] , chanx_left_in[9] } ) , .sram ( mux_2level_tapbuf_size2_11_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_81 , SYNOPSYS_UNCONNECTED_82 } ) , .out ( chany_top_out[21] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_157 ) ) ; + .p0 ( optlc_net_148 ) ) ; sb_2__0__mux_2level_tapbuf_size2_12 mux_top_track_46 ( .in ( { top_left_grid_pin_49_[0] , chanx_left_in[7] } ) , .sram ( mux_2level_tapbuf_size2_12_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_83 , SYNOPSYS_UNCONNECTED_84 } ) , .out ( chany_top_out[23] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_156 ) ) ; + .p0 ( optlc_net_149 ) ) ; sb_2__0__mux_2level_tapbuf_size2_13 mux_top_track_48 ( .in ( { top_left_grid_pin_50_[0] , chanx_left_in[6] } ) , .sram ( mux_2level_tapbuf_size2_13_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_85 , SYNOPSYS_UNCONNECTED_86 } ) , .out ( chany_top_out[24] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_156 ) ) ; + .p0 ( optlc_net_152 ) ) ; sb_2__0__mux_2level_tapbuf_size2_14 mux_top_track_50 ( .in ( { top_left_grid_pin_51_[0] , chanx_left_in[5] } ) , .sram ( mux_2level_tapbuf_size2_14_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_87 , SYNOPSYS_UNCONNECTED_88 } ) , .out ( chany_top_out[25] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_156 ) ) ; + .p0 ( optlc_net_149 ) ) ; sb_2__0__mux_2level_tapbuf_size2_15 mux_left_track_15 ( .in ( { chany_top_in[23] , left_bottom_grid_pin_3_[0] } ) , .sram ( mux_2level_tapbuf_size2_15_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_89 , SYNOPSYS_UNCONNECTED_90 } ) , .out ( chanx_left_out[7] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_157 ) ) ; + .p0 ( optlc_net_152 ) ) ; sb_2__0__mux_2level_tapbuf_size2_16 mux_left_track_17 ( .in ( { chany_top_in[22] , left_bottom_grid_pin_5_[0] } ) , .sram ( mux_2level_tapbuf_size2_16_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_91 , SYNOPSYS_UNCONNECTED_92 } ) , .out ( chanx_left_out[8] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_157 ) ) ; + .p0 ( optlc_net_152 ) ) ; sb_2__0__mux_2level_tapbuf_size2_17 mux_left_track_19 ( .in ( { chany_top_in[21] , left_bottom_grid_pin_7_[0] } ) , .sram ( mux_2level_tapbuf_size2_17_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_93 , SYNOPSYS_UNCONNECTED_94 } ) , .out ( chanx_left_out[9] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_157 ) ) ; + .p0 ( optlc_net_148 ) ) ; sb_2__0__mux_2level_tapbuf_size2_18 mux_left_track_21 ( .in ( { chany_top_in[20] , left_bottom_grid_pin_9_[0] } ) , .sram ( mux_2level_tapbuf_size2_18_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_95 , SYNOPSYS_UNCONNECTED_96 } ) , .out ( chanx_left_out[10] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_155 ) ) ; + .p0 ( optlc_net_148 ) ) ; sb_2__0__mux_2level_tapbuf_size2_19 mux_left_track_23 ( .in ( { chany_top_in[19] , left_bottom_grid_pin_11_[0] } ) , .sram ( mux_2level_tapbuf_size2_19_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_97 , SYNOPSYS_UNCONNECTED_98 } ) , .out ( chanx_left_out[11] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_155 ) ) ; + .p0 ( optlc_net_150 ) ) ; sb_2__0__mux_2level_tapbuf_size2_20 mux_left_track_25 ( .in ( { chany_top_in[18] , left_bottom_grid_pin_13_[0] } ) , .sram ( mux_2level_tapbuf_size2_20_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_99 , SYNOPSYS_UNCONNECTED_100 } ) , .out ( chanx_left_out[12] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_155 ) ) ; + .p0 ( optlc_net_148 ) ) ; sb_2__0__mux_2level_tapbuf_size2_21 mux_left_track_27 ( .in ( { chany_top_in[17] , left_bottom_grid_pin_15_[0] } ) , .sram ( mux_2level_tapbuf_size2_21_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_101 , SYNOPSYS_UNCONNECTED_102 } ) , .out ( chanx_left_out[13] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_155 ) ) ; + .p0 ( optlc_net_150 ) ) ; sb_2__0__mux_2level_tapbuf_size2_22 mux_left_track_31 ( .in ( { chany_top_in[15] , left_bottom_grid_pin_3_[0] } ) , .sram ( mux_2level_tapbuf_size2_22_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_103 , SYNOPSYS_UNCONNECTED_104 } ) , .out ( chanx_left_out[15] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_155 ) ) ; + .p0 ( optlc_net_150 ) ) ; sb_2__0__mux_2level_tapbuf_size2_23 mux_left_track_33 ( .in ( { chany_top_in[14] , left_bottom_grid_pin_5_[0] } ) , .sram ( mux_2level_tapbuf_size2_23_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_105 , SYNOPSYS_UNCONNECTED_106 } ) , .out ( chanx_left_out[16] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_155 ) ) ; + .p0 ( optlc_net_150 ) ) ; sb_2__0__mux_2level_tapbuf_size2_24 mux_left_track_35 ( .in ( { chany_top_in[13] , left_bottom_grid_pin_7_[0] } ) , .sram ( mux_2level_tapbuf_size2_24_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_107 , SYNOPSYS_UNCONNECTED_108 } ) , .out ( chanx_left_out[17] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_154 ) ) ; + .p0 ( optlc_net_150 ) ) ; sb_2__0__mux_2level_tapbuf_size2_25 mux_left_track_37 ( .in ( { chany_top_in[12] , left_bottom_grid_pin_9_[0] } ) , .sram ( mux_2level_tapbuf_size2_25_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_109 , SYNOPSYS_UNCONNECTED_110 } ) , .out ( chanx_left_out[18] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_154 ) ) ; + .p0 ( optlc_net_150 ) ) ; sb_2__0__mux_2level_tapbuf_size2_26 mux_left_track_39 ( .in ( { chany_top_in[11] , left_bottom_grid_pin_11_[0] } ) , .sram ( mux_2level_tapbuf_size2_26_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_111 , SYNOPSYS_UNCONNECTED_112 } ) , .out ( chanx_left_out[19] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_155 ) ) ; + .p0 ( optlc_net_150 ) ) ; sb_2__0__mux_2level_tapbuf_size2_27 mux_left_track_41 ( .in ( { chany_top_in[10] , left_bottom_grid_pin_13_[0] } ) , .sram ( mux_2level_tapbuf_size2_27_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_113 , SYNOPSYS_UNCONNECTED_114 } ) , .out ( chanx_left_out[20] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_155 ) ) ; + .p0 ( optlc_net_150 ) ) ; sb_2__0__mux_2level_tapbuf_size2_28 mux_left_track_43 ( .in ( { chany_top_in[9] , left_bottom_grid_pin_15_[0] } ) , .sram ( mux_2level_tapbuf_size2_28_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_115 , SYNOPSYS_UNCONNECTED_116 } ) , .out ( chanx_left_out[21] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_155 ) ) ; + .p0 ( optlc_net_150 ) ) ; sb_2__0__mux_2level_tapbuf_size2_29 mux_left_track_47 ( .in ( { chany_top_in[7] , left_bottom_grid_pin_3_[0] } ) , .sram ( mux_2level_tapbuf_size2_29_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_117 , SYNOPSYS_UNCONNECTED_118 } ) , .out ( chanx_left_out[23] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_154 ) ) ; + .p0 ( optlc_net_150 ) ) ; sb_2__0__mux_2level_tapbuf_size2_30 mux_left_track_49 ( .in ( { chany_top_in[6] , left_bottom_grid_pin_5_[0] } ) , .sram ( mux_2level_tapbuf_size2_30_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_119 , SYNOPSYS_UNCONNECTED_120 } ) , .out ( chanx_left_out[24] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_154 ) ) ; + .p0 ( optlc_net_147 ) ) ; sb_2__0__mux_2level_tapbuf_size2_31 mux_left_track_51 ( .in ( { chany_top_in[5] , left_bottom_grid_pin_7_[0] } ) , .sram ( mux_2level_tapbuf_size2_31_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_121 , SYNOPSYS_UNCONNECTED_122 } ) , .out ( chanx_left_out[25] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_154 ) ) ; + .p0 ( optlc_net_148 ) ) ; sb_2__0__mux_2level_tapbuf_size2_32 mux_left_track_53 ( .in ( { chany_top_in[4] , left_bottom_grid_pin_9_[0] } ) , .sram ( mux_2level_tapbuf_size2_32_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_123 , SYNOPSYS_UNCONNECTED_124 } ) , .out ( chanx_left_out[26] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_155 ) ) ; + .p0 ( optlc_net_152 ) ) ; sb_2__0__mux_2level_tapbuf_size2_33 mux_left_track_55 ( .in ( { chany_top_in[3] , left_bottom_grid_pin_11_[0] } ) , .sram ( mux_2level_tapbuf_size2_33_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_125 , SYNOPSYS_UNCONNECTED_126 } ) , .out ( chanx_left_out[27] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_155 ) ) ; + .p0 ( optlc_net_148 ) ) ; sb_2__0__mux_2level_tapbuf_size2_34 mux_left_track_57 ( .in ( { chany_top_in[2] , left_bottom_grid_pin_13_[0] } ) , .sram ( mux_2level_tapbuf_size2_34_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_127 , SYNOPSYS_UNCONNECTED_128 } ) , .out ( chanx_left_out[28] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_157 ) ) ; + .p0 ( optlc_net_148 ) ) ; sb_2__0__mux_2level_tapbuf_size2 mux_left_track_59 ( .in ( { chany_top_in[1] , left_bottom_grid_pin_15_[0] } ) , .sram ( mux_2level_tapbuf_size2_35_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_129 , SYNOPSYS_UNCONNECTED_130 } ) , .out ( chanx_left_out[29] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_157 ) ) ; + .p0 ( optlc_net_152 ) ) ; sb_2__0__mux_2level_tapbuf_size2_mem_0 mem_top_track_14 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( mux_2level_tapbuf_size3_mem_0_ccff_tail ) , @@ -45236,34 +47018,38 @@ sb_2__0__mux_2level_tapbuf_size2_mem mem_left_track_59 ( .pReset ( pReset ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sky130_fd_sc_hd__buf_8 pReset_FTB00 ( .A ( pReset_W_in ) , .X ( pReset[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_156 ( .LO ( SYNOPSYS_UNCONNECTED_131 ) , - .HI ( optlc_net_154 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_149 ( .LO ( SYNOPSYS_UNCONNECTED_131 ) , + .HI ( optlc_net_147 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_1 prog_clk_0_FTB00 ( .A ( prog_clk_0_N_in ) , .X ( prog_clk[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_8 FTB_78__77 ( .A ( chanx_left_in[1] ) , +sky130_fd_sc_hd__buf_6 FTB_78__77 ( .A ( chanx_left_in[1] ) , .X ( chany_top_out[29] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_6 FTB_79__78 ( .A ( chanx_left_in[2] ) , +sky130_fd_sc_hd__buf_8 FTB_79__78 ( .A ( chanx_left_in[2] ) , .X ( chany_top_out[28] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_8 FTB_80__79 ( .A ( chanx_left_in[3] ) , .X ( chany_top_out[27] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_8 FTB_81__80 ( .A ( chanx_left_in[4] ) , .X ( chany_top_out[26] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_8 FTB_82__81 ( .A ( chanx_left_in[13] ) , +sky130_fd_sc_hd__buf_6 FTB_82__81 ( .A ( chanx_left_in[13] ) , .X ( chany_top_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_8 FTB_83__82 ( .A ( chanx_left_in[14] ) , .X ( chany_top_out[16] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_8 FTB_84__83 ( .A ( chanx_left_in[15] ) , .X ( chany_top_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_152 ( .A ( BUF_net_153 ) , .Y ( pReset_N_out ) , +sky130_fd_sc_hd__inv_8 BINV_R_143 ( .A ( BUF_net_144 ) , .Y ( pReset_N_out ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_153 ( .A ( pReset_W_in ) , .Y ( BUF_net_153 ) , +sky130_fd_sc_hd__inv_1 BINV_R_144 ( .A ( pReset_W_in ) , .Y ( BUF_net_144 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_158 ( .LO ( SYNOPSYS_UNCONNECTED_132 ) , - .HI ( optlc_net_155 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_160 ( .LO ( SYNOPSYS_UNCONNECTED_133 ) , - .HI ( optlc_net_156 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_162 ( .LO ( SYNOPSYS_UNCONNECTED_134 ) , - .HI ( optlc_net_157 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_151 ( .LO ( SYNOPSYS_UNCONNECTED_132 ) , + .HI ( optlc_net_148 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_153 ( .LO ( SYNOPSYS_UNCONNECTED_133 ) , + .HI ( optlc_net_149 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_156 ( .LO ( SYNOPSYS_UNCONNECTED_134 ) , + .HI ( optlc_net_150 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_158 ( .LO ( SYNOPSYS_UNCONNECTED_135 ) , + .HI ( optlc_net_151 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_160 ( .LO ( SYNOPSYS_UNCONNECTED_136 ) , + .HI ( optlc_net_152 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -45544,7 +47330,7 @@ input p0 ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , +sky130_fd_sc_hd__mux2_2 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -45653,9 +47439,6 @@ wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; sb_1__2__mux_2level_tapbuf_basis_input2_mem1_30 mux_l1_in_0_ ( .in ( in ) , .mem ( sram[0] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) , @@ -45668,6 +47451,11 @@ sb_1__2__mux_2level_tapbuf_basis_input2_mem1_31 mux_l2_in_0_ ( .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_195 ( .A ( BUF_net_196 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_196 ( + .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_196 ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -45684,7 +47472,7 @@ input p0 ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , +sky130_fd_sc_hd__mux2_2 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -45754,7 +47542,7 @@ input p0 ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , +sky130_fd_sc_hd__mux2_2 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -45863,6 +47651,9 @@ wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ; supply1 VDD ; supply0 VSS ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; sb_1__2__mux_2level_tapbuf_basis_input2_mem1_24 mux_l1_in_0_ ( .in ( in ) , .mem ( sram[0] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) , @@ -45875,9 +47666,6 @@ sb_1__2__mux_2level_tapbuf_basis_input2_mem1_25 mux_l2_in_0_ ( .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_197 ( - .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -45933,6 +47721,9 @@ wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ; supply1 VDD ; supply0 VSS ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; sb_1__2__mux_2level_tapbuf_basis_input2_mem1_22 mux_l1_in_0_ ( .in ( in ) , .mem ( sram[0] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) , @@ -45945,11 +47736,6 @@ sb_1__2__mux_2level_tapbuf_basis_input2_mem1_23 mux_l2_in_0_ ( .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_195 ( .A ( BUF_net_196 ) , .Y ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_196 ( - .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_196 ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -45966,7 +47752,7 @@ input p0 ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , +sky130_fd_sc_hd__mux2_2 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -46005,9 +47791,6 @@ wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; sb_1__2__mux_2level_tapbuf_basis_input2_mem1_20 mux_l1_in_0_ ( .in ( in ) , .mem ( sram[0] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) , @@ -46020,6 +47803,9 @@ sb_1__2__mux_2level_tapbuf_basis_input2_mem1_21 mux_l2_in_0_ ( .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_194 ( + .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -46036,7 +47822,7 @@ input p0 ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , +sky130_fd_sc_hd__mux2_2 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -46075,6 +47861,9 @@ wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ; supply1 VDD ; supply0 VSS ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; sb_1__2__mux_2level_tapbuf_basis_input2_mem1_18 mux_l1_in_0_ ( .in ( in ) , .mem ( sram[0] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) , @@ -46087,11 +47876,6 @@ sb_1__2__mux_2level_tapbuf_basis_input2_mem1_19 mux_l2_in_0_ ( .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_193 ( .A ( BUF_net_194 ) , .Y ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_194 ( - .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_194 ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -46108,7 +47892,7 @@ input p0 ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , +sky130_fd_sc_hd__mux2_2 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -46287,6 +48071,9 @@ wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ; supply1 VDD ; supply0 VSS ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; sb_1__2__mux_2level_tapbuf_basis_input2_mem1_12 mux_l1_in_0_ ( .in ( in ) , .mem ( sram[0] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) , @@ -46299,9 +48086,6 @@ sb_1__2__mux_2level_tapbuf_basis_input2_mem1_13 mux_l2_in_0_ ( .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_192 ( - .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -46413,7 +48197,7 @@ input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__mux2_2 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) , +sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -46472,9 +48256,6 @@ wire [0:0] mux_2level_tapbuf_basis_input2_mem1_2_out ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( mux_2level_tapbuf_basis_input2_mem1_2_out[0] ) , .X ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; sb_1__2__mux_2level_tapbuf_basis_input2_mem1_9 mux_l1_in_0_ ( .in ( in[0:1] ) , .mem ( sram[0] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) , @@ -46493,6 +48274,11 @@ sb_1__2__mux_2level_tapbuf_basis_input2_mem1_11 mux_l2_in_0_ ( .mem_inv ( { SYNOPSYS_UNCONNECTED_4 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_2_out ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_192 ( .A ( BUF_net_193 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_193 ( + .A ( mux_2level_tapbuf_basis_input2_mem1_2_out[0] ) , .Y ( BUF_net_193 ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -46662,6 +48448,9 @@ wire [0:0] mux_2level_tapbuf_basis_input2_mem1_2_out ; supply1 VDD ; supply0 VSS ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( mux_2level_tapbuf_basis_input2_mem1_2_out[0] ) , .X ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; sb_1__2__mux_2level_tapbuf_basis_input2_mem1_3 mux_l1_in_0_ ( .in ( in[0:1] ) , .mem ( sram[0] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) , @@ -46680,9 +48469,6 @@ sb_1__2__mux_2level_tapbuf_basis_input2_mem1_5 mux_l2_in_0_ ( .mem_inv ( { SYNOPSYS_UNCONNECTED_4 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_2_out ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_191 ( - .A ( mux_2level_tapbuf_basis_input2_mem1_2_out[0] ) , .X ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -46775,10 +48561,10 @@ sb_1__2__mux_2level_tapbuf_basis_input2_mem1_2 mux_l2_in_0_ ( .mem_inv ( { SYNOPSYS_UNCONNECTED_4 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_2_out ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_189 ( .A ( BUF_net_190 ) , .Y ( out[0] ) , +sky130_fd_sc_hd__inv_8 BINV_R_190 ( .A ( BUF_net_191 ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_190 ( - .A ( mux_2level_tapbuf_basis_input2_mem1_2_out[0] ) , .Y ( BUF_net_190 ) , +sky130_fd_sc_hd__inv_1 BINV_R_191 ( + .A ( mux_2level_tapbuf_basis_input2_mem1_2_out[0] ) , .Y ( BUF_net_191 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -46913,13 +48699,16 @@ input VDD ; input VSS ; input p0 ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -46932,13 +48721,16 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -46951,13 +48743,16 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -47055,10 +48850,10 @@ sb_1__2__mux_2level_tapbuf_basis_input3_mem3 mux_l2_in_0_ ( .mem_inv ( local_encoder2to3_1_data_inv ) , .out ( mux_2level_tapbuf_basis_input3_mem3_2_out ) , .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_187 ( .A ( BUF_net_188 ) , .Y ( out[0] ) , +sky130_fd_sc_hd__inv_8 BINV_R_188 ( .A ( BUF_net_189 ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_188 ( - .A ( mux_2level_tapbuf_basis_input3_mem3_2_out[0] ) , .Y ( BUF_net_188 ) , +sky130_fd_sc_hd__inv_1 BINV_R_189 ( + .A ( mux_2level_tapbuf_basis_input3_mem3_2_out[0] ) , .Y ( BUF_net_189 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -47073,13 +48868,16 @@ input VDD ; input VSS ; input p0 ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -47092,13 +48890,16 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -47111,13 +48912,16 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -47215,10 +49019,8 @@ sb_1__2__mux_2level_tapbuf_basis_input3_mem3_73 mux_l2_in_0_ ( .mem_inv ( local_encoder2to3_1_data_inv ) , .out ( mux_2level_tapbuf_basis_input3_mem3_2_out ) , .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_185 ( .A ( BUF_net_186 ) , .Y ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_186 ( - .A ( mux_2level_tapbuf_basis_input3_mem3_2_out[0] ) , .Y ( BUF_net_186 ) , +sky130_fd_sc_hd__buf_6 BUFT_RR_187 ( + .A ( mux_2level_tapbuf_basis_input3_mem3_2_out[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -47233,13 +49035,16 @@ input VDD ; input VSS ; input p0 ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -47252,13 +49057,16 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -47271,13 +49079,16 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -47375,7 +49186,7 @@ sb_1__2__mux_2level_tapbuf_basis_input3_mem3_70 mux_l2_in_0_ ( .mem_inv ( local_encoder2to3_1_data_inv ) , .out ( mux_2level_tapbuf_basis_input3_mem3_2_out ) , .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_184 ( +sky130_fd_sc_hd__buf_6 BUFT_RR_186 ( .A ( mux_2level_tapbuf_basis_input3_mem3_2_out[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -47391,13 +49202,16 @@ input VDD ; input VSS ; input p0 ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -47410,13 +49224,16 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -47429,13 +49246,16 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -47533,10 +49353,10 @@ sb_1__2__mux_2level_tapbuf_basis_input3_mem3_67 mux_l2_in_0_ ( .mem_inv ( local_encoder2to3_1_data_inv ) , .out ( mux_2level_tapbuf_basis_input3_mem3_2_out ) , .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_182 ( .A ( BUF_net_183 ) , .Y ( out[0] ) , +sky130_fd_sc_hd__inv_8 BINV_R_184 ( .A ( BUF_net_185 ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_183 ( - .A ( mux_2level_tapbuf_basis_input3_mem3_2_out[0] ) , .Y ( BUF_net_183 ) , +sky130_fd_sc_hd__inv_1 BINV_R_185 ( + .A ( mux_2level_tapbuf_basis_input3_mem3_2_out[0] ) , .Y ( BUF_net_185 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -47791,13 +49611,16 @@ input VDD ; input VSS ; input p0 ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -47810,13 +49633,16 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -47923,13 +49749,16 @@ input VDD ; input VSS ; input p0 ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -47942,13 +49771,16 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -48021,9 +49853,6 @@ wire [0:0] mux_2level_tapbuf_basis_input3_mem3_1_out ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .X ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; sb_1__2__local_encoder2to3_46 local_encoder2to3_0_ ( .addr ( sram[0:1] ) , .data ( local_encoder2to3_0_data ) , .data_inv ( local_encoder2to3_0_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; @@ -48042,6 +49871,9 @@ sb_1__2__mux_2level_tapbuf_basis_input3_mem3_62 mux_l2_in_0_ ( .mem_inv ( local_encoder2to3_1_data_inv ) , .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_183 ( + .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .X ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -48055,13 +49887,16 @@ input VDD ; input VSS ; input p0 ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -48074,13 +49909,16 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -48153,6 +49991,9 @@ wire [0:0] mux_2level_tapbuf_basis_input3_mem3_1_out ; supply1 VDD ; supply0 VSS ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .X ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; sb_1__2__local_encoder2to3_44 local_encoder2to3_0_ ( .addr ( sram[0:1] ) , .data ( local_encoder2to3_0_data ) , .data_inv ( local_encoder2to3_0_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; @@ -48171,11 +50012,6 @@ sb_1__2__mux_2level_tapbuf_basis_input3_mem3_60 mux_l2_in_0_ ( .mem_inv ( local_encoder2to3_1_data_inv ) , .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_180 ( .A ( BUF_net_181 ) , .Y ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_181 ( - .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_181 ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -48189,13 +50025,16 @@ input VDD ; input VSS ; input p0 ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -48208,13 +50047,16 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -48305,10 +50147,10 @@ sb_1__2__mux_2level_tapbuf_basis_input3_mem3_58 mux_l2_in_0_ ( .mem_inv ( local_encoder2to3_1_data_inv ) , .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_178 ( .A ( BUF_net_179 ) , .Y ( out[0] ) , +sky130_fd_sc_hd__inv_8 BINV_R_181 ( .A ( BUF_net_182 ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_179 ( - .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_179 ) , +sky130_fd_sc_hd__inv_1 BINV_R_182 ( + .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_182 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -48323,13 +50165,16 @@ input VDD ; input VSS ; input p0 ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -48342,13 +50187,16 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -48439,10 +50287,10 @@ sb_1__2__mux_2level_tapbuf_basis_input3_mem3_56 mux_l2_in_0_ ( .mem_inv ( local_encoder2to3_1_data_inv ) , .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_176 ( .A ( BUF_net_177 ) , .Y ( out[0] ) , +sky130_fd_sc_hd__inv_8 BINV_R_179 ( .A ( BUF_net_180 ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_177 ( - .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_177 ) , +sky130_fd_sc_hd__inv_1 BINV_R_180 ( + .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_180 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -48457,13 +50305,16 @@ input VDD ; input VSS ; input p0 ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -48476,13 +50327,16 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -48573,10 +50427,10 @@ sb_1__2__mux_2level_tapbuf_basis_input3_mem3_54 mux_l2_in_0_ ( .mem_inv ( local_encoder2to3_1_data_inv ) , .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_174 ( .A ( BUF_net_175 ) , .Y ( out[0] ) , +sky130_fd_sc_hd__inv_8 BINV_R_177 ( .A ( BUF_net_178 ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_175 ( - .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_175 ) , +sky130_fd_sc_hd__inv_1 BINV_R_178 ( + .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_178 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -48591,13 +50445,16 @@ input VDD ; input VSS ; input p0 ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -48610,13 +50467,16 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -48707,10 +50567,10 @@ sb_1__2__mux_2level_tapbuf_basis_input3_mem3_52 mux_l2_in_0_ ( .mem_inv ( local_encoder2to3_1_data_inv ) , .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_172 ( .A ( BUF_net_173 ) , .Y ( out[0] ) , +sky130_fd_sc_hd__inv_8 BINV_R_175 ( .A ( BUF_net_176 ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_173 ( - .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_173 ) , +sky130_fd_sc_hd__inv_1 BINV_R_176 ( + .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_176 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -48725,13 +50585,16 @@ input VDD ; input VSS ; input p0 ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -48744,13 +50607,16 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -48841,10 +50707,8 @@ sb_1__2__mux_2level_tapbuf_basis_input3_mem3_50 mux_l2_in_0_ ( .mem_inv ( local_encoder2to3_1_data_inv ) , .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_170 ( .A ( BUF_net_171 ) , .Y ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_171 ( - .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_171 ) , +sky130_fd_sc_hd__buf_6 BUFT_RR_174 ( + .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -49008,12 +50872,15 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -49027,13 +50894,16 @@ input VDD ; input VSS ; input p0 ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -49046,13 +50916,16 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -49165,12 +51038,15 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -49184,13 +51060,16 @@ input VDD ; input VSS ; input p0 ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -49203,13 +51082,16 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -49307,8 +51189,10 @@ sb_1__2__mux_2level_tapbuf_basis_input2_mem2_14 mux_l1_in_1_ ( .mem_inv ( local_encoder2to3_0_data_inv[0:1] ) , .out ( mux_2level_tapbuf_basis_input2_mem2_0_out ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_169 ( - .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .X ( out[0] ) , +sky130_fd_sc_hd__inv_8 BINV_R_172 ( .A ( BUF_net_173 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_173 ( + .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_173 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -49322,12 +51206,15 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -49341,13 +51228,16 @@ input VDD ; input VSS ; input p0 ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -49360,13 +51250,16 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -49479,12 +51372,15 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -49498,13 +51394,16 @@ input VDD ; input VSS ; input p0 ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -49517,13 +51416,16 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -49621,10 +51523,10 @@ sb_1__2__mux_2level_tapbuf_basis_input2_mem2_12 mux_l1_in_1_ ( .mem_inv ( local_encoder2to3_0_data_inv[0:1] ) , .out ( mux_2level_tapbuf_basis_input2_mem2_0_out ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_167 ( .A ( BUF_net_168 ) , .Y ( out[0] ) , +sky130_fd_sc_hd__inv_8 BINV_R_170 ( .A ( BUF_net_171 ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_168 ( - .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_168 ) , +sky130_fd_sc_hd__inv_1 BINV_R_171 ( + .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_171 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -49638,12 +51540,15 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -49657,13 +51562,16 @@ input VDD ; input VSS ; input p0 ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -49676,13 +51584,16 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -49780,10 +51691,10 @@ sb_1__2__mux_2level_tapbuf_basis_input2_mem2_11 mux_l1_in_1_ ( .mem_inv ( local_encoder2to3_0_data_inv[0:1] ) , .out ( mux_2level_tapbuf_basis_input2_mem2_0_out ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_165 ( .A ( BUF_net_166 ) , .Y ( out[0] ) , +sky130_fd_sc_hd__inv_8 BINV_R_168 ( .A ( BUF_net_169 ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_166 ( - .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_166 ) , +sky130_fd_sc_hd__inv_1 BINV_R_169 ( + .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_169 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -49858,15 +51769,20 @@ input VDD ; input VSS ; input p0 ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -49879,15 +51795,20 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -49900,15 +51821,20 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -49996,7 +51922,7 @@ supply0 VSS ; sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_4_0_ ( .A ( mux_2level_tapbuf_basis_input4_mem4_2_out[0] ) , - .X ( aps_rename_506_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .X ( aps_rename_507_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sb_1__2__local_encoder2to4_6 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , .data ( local_encoder2to4_0_data ) , .data_inv ( local_encoder2to4_0_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; @@ -50021,10 +51947,10 @@ sb_1__2__mux_2level_tapbuf_basis_input4_mem4 mux_l2_in_0_ ( .mem_inv ( local_encoder2to4_1_data_inv ) , .out ( mux_2level_tapbuf_basis_input4_mem4_2_out ) , .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_163 ( .A ( BUF_net_164 ) , .Y ( out[0] ) , +sky130_fd_sc_hd__inv_8 BINV_R_166 ( .A ( BUF_net_167 ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_164 ( .A ( aps_rename_506_ ) , - .Y ( BUF_net_164 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_167 ( .A ( aps_rename_507_ ) , + .Y ( BUF_net_167 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -50038,15 +51964,20 @@ input VDD ; input VSS ; input p0 ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -50059,15 +51990,20 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -50080,15 +52016,20 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -50273,12 +52214,15 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -50292,15 +52236,20 @@ input VDD ; input VSS ; input p0 ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -50313,15 +52262,20 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -50334,15 +52288,20 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -50430,8 +52389,8 @@ supply1 VDD ; supply0 VSS ; sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_4_0_ ( - .A ( mux_2level_tapbuf_basis_input4_mem4_2_out[0] ) , .X ( net_net_162 ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .A ( mux_2level_tapbuf_basis_input4_mem4_2_out[0] ) , + .X ( aps_rename_506_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sb_1__2__local_encoder2to4_2 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , .data ( local_encoder2to4_0_data ) , .data_inv ( local_encoder2to4_0_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; @@ -50462,8 +52421,10 @@ sb_1__2__mux_2level_tapbuf_basis_input2_mem2_10 mux_l1_in_2_ ( .mem_inv ( local_encoder2to4_0_data_inv[0:1] ) , .out ( mux_2level_tapbuf_basis_input2_mem2_0_out ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_162 ( .A ( net_net_162 ) , .X ( out[0] ) , +sky130_fd_sc_hd__inv_8 BINV_R_164 ( .A ( BUF_net_165 ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_165 ( .A ( aps_rename_506_ ) , + .Y ( BUF_net_165 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -50476,12 +52437,15 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -50495,15 +52459,20 @@ input VDD ; input VSS ; input p0 ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -50516,15 +52485,20 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -50537,15 +52511,20 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -50665,10 +52644,10 @@ sb_1__2__mux_2level_tapbuf_basis_input2_mem2_9 mux_l1_in_2_ ( .mem_inv ( local_encoder2to4_0_data_inv[0:1] ) , .out ( mux_2level_tapbuf_basis_input2_mem2_0_out ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_199 ( .A ( BUF_net_200 ) , .Y ( out[0] ) , +sky130_fd_sc_hd__inv_8 BINV_R_162 ( .A ( BUF_net_163 ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_200 ( .A ( aps_rename_505_ ) , - .Y ( BUF_net_200 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_163 ( .A ( aps_rename_505_ ) , + .Y ( BUF_net_163 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -50771,13 +52750,16 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -50791,13 +52773,16 @@ input VDD ; input VSS ; input p0 ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -50810,13 +52795,16 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -50829,13 +52817,16 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -50957,13 +52948,16 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -50977,13 +52971,16 @@ input VDD ; input VSS ; input p0 ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -50996,13 +52993,16 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -51015,13 +53015,16 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -51126,8 +53129,10 @@ sb_1__2__mux_2level_tapbuf_basis_input3_mem3_34 mux_l2_in_0_ ( .mem_inv ( local_encoder2to3_1_data_inv ) , .out ( mux_2level_tapbuf_basis_input3_mem3_3_out ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_159 ( - .A ( mux_2level_tapbuf_basis_input3_mem3_3_out[0] ) , .X ( out[0] ) , +sky130_fd_sc_hd__inv_8 BINV_R_158 ( .A ( BUF_net_159 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_159 ( + .A ( mux_2level_tapbuf_basis_input3_mem3_3_out[0] ) , .Y ( BUF_net_159 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -51141,13 +53146,16 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -51161,13 +53169,16 @@ input VDD ; input VSS ; input p0 ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -51180,13 +53191,16 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -51199,13 +53213,16 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -51280,6 +53297,9 @@ wire [0:0] mux_2level_tapbuf_basis_input3_mem3_3_out ; supply1 VDD ; supply0 VSS ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( mux_2level_tapbuf_basis_input3_mem3_3_out[0] ) , .X ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; sb_1__2__local_encoder2to3_18 local_encoder2to3_0_ ( .addr ( sram[0:1] ) , .data ( local_encoder2to3_0_data ) , .data_inv ( local_encoder2to3_0_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; @@ -51310,9 +53330,6 @@ sb_1__2__mux_2level_tapbuf_basis_input3_mem3_30 mux_l2_in_0_ ( .mem_inv ( local_encoder2to3_1_data_inv ) , .out ( mux_2level_tapbuf_basis_input3_mem3_3_out ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_158 ( - .A ( mux_2level_tapbuf_basis_input3_mem3_3_out[0] ) , .X ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -51569,7 +53586,7 @@ input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( copt_net_216 ) , +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ropt_net_240 ) , .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , @@ -51583,34 +53600,36 @@ sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_1 FTB_19__18 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1420 ( .A ( ccff_head[0] ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1419 ( .A ( ropt_net_244 ) , .X ( copt_net_211 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1421 ( .A ( copt_net_211 ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1420 ( .A ( ropt_net_241 ) , .X ( copt_net_212 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1422 ( .A ( copt_net_212 ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1421 ( .A ( copt_net_215 ) , .X ( copt_net_213 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1423 ( .A ( ropt_net_246 ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1422 ( .A ( copt_net_213 ) , .X ( copt_net_214 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1424 ( .A ( copt_net_213 ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1423 ( .A ( copt_net_211 ) , .X ( copt_net_215 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1425 ( .A ( ropt_net_241 ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1424 ( .A ( copt_net_212 ) , .X ( copt_net_216 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1446 ( .A ( copt_net_214 ) , +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1443 ( .A ( copt_net_216 ) , + .X ( ropt_net_236 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1444 ( .A ( ropt_net_236 ) , + .X ( ropt_net_237 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1445 ( .A ( ropt_net_237 ) , + .X ( ropt_net_238 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1446 ( .A ( ropt_net_238 ) , + .X ( ropt_net_239 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_2 ropt_h_inst_1447 ( .A ( ropt_net_239 ) , .X ( ropt_net_240 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_2 ropt_h_inst_1447 ( .A ( ropt_net_240 ) , +sky130_fd_sc_hd__buf_1 ropt_h_inst_1448 ( .A ( copt_net_214 ) , .X ( ropt_net_241 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1448 ( .A ( copt_net_215 ) , +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1449 ( .A ( ropt_net_243 ) , .X ( ropt_net_242 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1449 ( .A ( ropt_net_247 ) , +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1450 ( .A ( ccff_head[0] ) , .X ( ropt_net_243 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1450 ( .A ( ropt_net_242 ) , +sky130_fd_sc_hd__buf_1 ropt_h_inst_1451 ( .A ( ropt_net_242 ) , .X ( ropt_net_244 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1451 ( .A ( ropt_net_243 ) , - .X ( ropt_net_245 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1452 ( .A ( ropt_net_245 ) , - .X ( ropt_net_246 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 ropt_h_inst_1453 ( .A ( ropt_net_244 ) , - .X ( ropt_net_247 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -51624,12 +53643,15 @@ input VDD ; input VSS ; input p0 ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( p0 ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -51642,13 +53664,16 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -51661,13 +53686,16 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -51680,13 +53708,16 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -51807,12 +53838,15 @@ input VDD ; input VSS ; input p0 ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( p0 ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -51825,13 +53859,16 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -51844,13 +53881,16 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -51863,13 +53903,16 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -51974,8 +54017,10 @@ sb_1__2__mux_2level_tapbuf_basis_input2_mem2_7 mux_l1_in_2_ ( .mem_inv ( local_encoder2to3_0_data_inv[0:1] ) , .out ( mux_2level_tapbuf_basis_input2_mem2_0_out ) , .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_157 ( - .A ( mux_2level_tapbuf_basis_input3_mem3_2_out[0] ) , .X ( out[0] ) , +sky130_fd_sc_hd__inv_8 BINV_R_156 ( .A ( BUF_net_157 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_157 ( + .A ( mux_2level_tapbuf_basis_input3_mem3_2_out[0] ) , .Y ( BUF_net_157 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -51990,12 +54035,15 @@ input VDD ; input VSS ; input p0 ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( p0 ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -52008,13 +54056,16 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -52027,13 +54078,16 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -52046,13 +54100,16 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -52157,10 +54214,10 @@ sb_1__2__mux_2level_tapbuf_basis_input2_mem2_6 mux_l1_in_2_ ( .mem_inv ( local_encoder2to3_0_data_inv[0:1] ) , .out ( mux_2level_tapbuf_basis_input2_mem2_0_out ) , .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_155 ( .A ( BUF_net_156 ) , .Y ( out[0] ) , +sky130_fd_sc_hd__inv_8 BINV_R_154 ( .A ( BUF_net_155 ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_156 ( - .A ( mux_2level_tapbuf_basis_input3_mem3_2_out[0] ) , .Y ( BUF_net_156 ) , +sky130_fd_sc_hd__inv_1 BINV_R_155 ( + .A ( mux_2level_tapbuf_basis_input3_mem3_2_out[0] ) , .Y ( BUF_net_155 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -52175,12 +54232,15 @@ input VDD ; input VSS ; input p0 ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( p0 ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -52193,13 +54253,16 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -52212,13 +54275,16 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -52231,13 +54297,16 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -52342,10 +54411,10 @@ sb_1__2__mux_2level_tapbuf_basis_input2_mem2_5 mux_l1_in_2_ ( .mem_inv ( local_encoder2to3_0_data_inv[0:1] ) , .out ( mux_2level_tapbuf_basis_input2_mem2_0_out ) , .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_153 ( .A ( BUF_net_154 ) , .Y ( out[0] ) , +sky130_fd_sc_hd__inv_8 BINV_R_152 ( .A ( BUF_net_153 ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_154 ( - .A ( mux_2level_tapbuf_basis_input3_mem3_2_out[0] ) , .Y ( BUF_net_154 ) , +sky130_fd_sc_hd__inv_1 BINV_R_153 ( + .A ( mux_2level_tapbuf_basis_input3_mem3_2_out[0] ) , .Y ( BUF_net_153 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -52360,12 +54429,15 @@ input VDD ; input VSS ; input p0 ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( p0 ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -52378,13 +54450,16 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -52397,13 +54472,16 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -52416,13 +54494,16 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -52527,10 +54608,8 @@ sb_1__2__mux_2level_tapbuf_basis_input2_mem2_4 mux_l1_in_2_ ( .mem_inv ( local_encoder2to3_0_data_inv[0:1] ) , .out ( mux_2level_tapbuf_basis_input2_mem2_0_out ) , .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_151 ( .A ( BUF_net_152 ) , .Y ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_152 ( - .A ( mux_2level_tapbuf_basis_input3_mem3_2_out[0] ) , .Y ( BUF_net_152 ) , +sky130_fd_sc_hd__buf_6 BUFT_RR_151 ( + .A ( mux_2level_tapbuf_basis_input3_mem3_2_out[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -52545,12 +54624,15 @@ input VDD ; input VSS ; input p0 ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( p0 ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -52563,13 +54645,16 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -52582,13 +54667,16 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -52601,13 +54689,16 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -52712,10 +54803,10 @@ sb_1__2__mux_2level_tapbuf_basis_input2_mem2_3 mux_l1_in_2_ ( .mem_inv ( local_encoder2to3_0_data_inv[0:1] ) , .out ( mux_2level_tapbuf_basis_input2_mem2_0_out ) , .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_149 ( .A ( BUF_net_150 ) , .Y ( out[0] ) , +sky130_fd_sc_hd__inv_8 BINV_R_199 ( .A ( BUF_net_200 ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_150 ( - .A ( mux_2level_tapbuf_basis_input3_mem3_2_out[0] ) , .Y ( BUF_net_150 ) , +sky130_fd_sc_hd__inv_1 BINV_R_200 ( + .A ( mux_2level_tapbuf_basis_input3_mem3_2_out[0] ) , .Y ( BUF_net_200 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -52730,12 +54821,15 @@ input VDD ; input VSS ; input p0 ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( p0 ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -52748,13 +54842,16 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -52767,13 +54864,16 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -52786,13 +54886,16 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -52913,12 +55016,15 @@ input VDD ; input VSS ; input p0 ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( p0 ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -52931,13 +55037,16 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -52950,13 +55059,16 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -52969,13 +55081,16 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -53096,12 +55211,15 @@ input VDD ; input VSS ; input p0 ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( p0 ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -53114,13 +55232,16 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -53133,13 +55254,16 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -53152,13 +55276,16 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -53233,9 +55360,6 @@ wire [0:0] mux_2level_tapbuf_basis_input3_mem3_2_out ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( mux_2level_tapbuf_basis_input3_mem3_2_out[0] ) , .X ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; sb_1__2__local_encoder2to3_0 local_encoder2to3_0_ ( .addr ( sram[0:1] ) , .data ( local_encoder2to3_0_data ) , .data_inv ( local_encoder2to3_0_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; @@ -53266,6 +55390,11 @@ sb_1__2__mux_2level_tapbuf_basis_input2_mem2_0 mux_l1_in_2_ ( .mem_inv ( local_encoder2to3_0_data_inv[0:1] ) , .out ( mux_2level_tapbuf_basis_input2_mem2_0_out ) , .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_149 ( .A ( BUF_net_150 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_150 ( + .A ( mux_2level_tapbuf_basis_input3_mem3_2_out[0] ) , .Y ( BUF_net_150 ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -53333,6 +55462,7 @@ input VDD ; input VSS ; wire ropt_net_228 ; +wire ropt_net_227 ; wire [0:0] prog_clk ; wire prog_clk_0 ; wire [0:3] mux_2level_tapbuf_size10_0_sram ; @@ -53445,7 +55575,7 @@ sb_1__2__mux_2level_tapbuf_size7_0 mux_right_track_0 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 , SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) , .out ( chanx_right_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_204 ) ) ; + .p0 ( optlc_net_203 ) ) ; sb_1__2__mux_2level_tapbuf_size7_1 mux_right_track_2 ( .in ( { right_bottom_grid_pin_36_[0] , right_bottom_grid_pin_39_[0] , right_bottom_grid_pin_42_[0] , chany_bottom_in[8] , @@ -53454,7 +55584,7 @@ sb_1__2__mux_2level_tapbuf_size7_1 mux_right_track_2 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 , SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 } ) , .out ( chanx_right_out[1] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_204 ) ) ; + .p0 ( optlc_net_203 ) ) ; sb_1__2__mux_2level_tapbuf_size7_2 mux_right_track_12 ( .in ( { right_top_grid_pin_1_[0] , right_bottom_grid_pin_41_[0] , chany_bottom_in[4] , chany_bottom_in[15] , chany_bottom_in[26] , @@ -53463,7 +55593,7 @@ sb_1__2__mux_2level_tapbuf_size7_2 mux_right_track_12 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_9 , SYNOPSYS_UNCONNECTED_10 , SYNOPSYS_UNCONNECTED_11 , SYNOPSYS_UNCONNECTED_12 } ) , .out ( chanx_right_out[6] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_204 ) ) ; + .p0 ( optlc_net_209 ) ) ; sb_1__2__mux_2level_tapbuf_size7_3 mux_right_track_20 ( .in ( { right_bottom_grid_pin_36_[0] , right_bottom_grid_pin_42_[0] , chany_bottom_in[3] , chany_bottom_in[14] , chany_bottom_in[25] , @@ -53490,7 +55620,7 @@ sb_1__2__mux_2level_tapbuf_size7_5 mux_left_track_1 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_21 , SYNOPSYS_UNCONNECTED_22 , SYNOPSYS_UNCONNECTED_23 , SYNOPSYS_UNCONNECTED_24 } ) , .out ( chanx_left_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_208 ) ) ; + .p0 ( optlc_net_202 ) ) ; sb_1__2__mux_2level_tapbuf_size7_6 mux_left_track_13 ( .in ( { chanx_left_out[12] , chanx_left_out[27] , chany_bottom_in[4] , chany_bottom_in[15] , chany_bottom_in[26] , left_top_grid_pin_1_[0] , @@ -53499,7 +55629,7 @@ sb_1__2__mux_2level_tapbuf_size7_6 mux_left_track_13 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_25 , SYNOPSYS_UNCONNECTED_26 , SYNOPSYS_UNCONNECTED_27 , SYNOPSYS_UNCONNECTED_28 } ) , .out ( chanx_left_out[6] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_207 ) ) ; + .p0 ( optlc_net_208 ) ) ; sb_1__2__mux_2level_tapbuf_size7_7 mux_left_track_21 ( .in ( { chanx_left_out[13] , chanx_left_out[28] , chany_bottom_in[5] , chany_bottom_in[16] , chany_bottom_in[27] , @@ -53508,7 +55638,7 @@ sb_1__2__mux_2level_tapbuf_size7_7 mux_left_track_21 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_29 , SYNOPSYS_UNCONNECTED_30 , SYNOPSYS_UNCONNECTED_31 , SYNOPSYS_UNCONNECTED_32 } ) , .out ( chanx_left_out[10] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_206 ) ) ; + .p0 ( optlc_net_205 ) ) ; sb_1__2__mux_2level_tapbuf_size7 mux_left_track_29 ( .in ( { chanx_left_out[15] , chanx_left_out[29] , chany_bottom_in[6] , chany_bottom_in[17] , chany_bottom_in[28] , @@ -53517,7 +55647,7 @@ sb_1__2__mux_2level_tapbuf_size7 mux_left_track_29 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_33 , SYNOPSYS_UNCONNECTED_34 , SYNOPSYS_UNCONNECTED_35 , SYNOPSYS_UNCONNECTED_36 } ) , .out ( chanx_left_out[14] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_206 ) ) ; + .p0 ( optlc_net_201 ) ) ; sb_1__2__mux_2level_tapbuf_size7_mem_0 mem_right_track_0 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( mux_2level_tapbuf_size7_mem_0_ccff_tail ) , @@ -53580,7 +55710,7 @@ sb_1__2__mux_2level_tapbuf_size8_0 mux_right_track_4 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_37 , SYNOPSYS_UNCONNECTED_38 , SYNOPSYS_UNCONNECTED_39 , SYNOPSYS_UNCONNECTED_40 } ) , .out ( chanx_right_out[2] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_205 ) ) ; + .p0 ( optlc_net_209 ) ) ; sb_1__2__mux_2level_tapbuf_size8_1 mux_left_track_3 ( .in ( { chanx_left_out[7] , chanx_left_out[21] , chany_bottom_in[0] , chany_bottom_in[11] , chany_bottom_in[22] , @@ -53590,7 +55720,7 @@ sb_1__2__mux_2level_tapbuf_size8_1 mux_left_track_3 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_41 , SYNOPSYS_UNCONNECTED_42 , SYNOPSYS_UNCONNECTED_43 , SYNOPSYS_UNCONNECTED_44 } ) , .out ( chanx_left_out[1] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_209 ) ) ; + .p0 ( optlc_net_206 ) ) ; sb_1__2__mux_2level_tapbuf_size8 mux_left_track_5 ( .in ( { chanx_left_out[8] , chanx_left_out[23] , chany_bottom_in[1] , chany_bottom_in[12] , chany_bottom_in[23] , @@ -53600,7 +55730,7 @@ sb_1__2__mux_2level_tapbuf_size8 mux_left_track_5 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_45 , SYNOPSYS_UNCONNECTED_46 , SYNOPSYS_UNCONNECTED_47 , SYNOPSYS_UNCONNECTED_48 } ) , .out ( chanx_left_out[2] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_209 ) ) ; + .p0 ( optlc_net_206 ) ) ; sb_1__2__mux_2level_tapbuf_size8_mem_0 mem_right_track_4 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( mux_2level_tapbuf_size7_mem_1_ccff_tail ) , @@ -53629,7 +55759,7 @@ sb_1__2__mux_2level_tapbuf_size10_0 mux_right_track_6 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_49 , SYNOPSYS_UNCONNECTED_50 , SYNOPSYS_UNCONNECTED_51 , SYNOPSYS_UNCONNECTED_52 } ) , .out ( chanx_right_out[3] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_204 ) ) ; + .p0 ( optlc_net_205 ) ) ; sb_1__2__mux_2level_tapbuf_size10 mux_left_track_7 ( .in ( { chanx_left_out[9] , chanx_left_out[24] , chany_bottom_in[2] , chany_bottom_in[13] , chany_bottom_in[24] , left_top_grid_pin_1_[0] , @@ -53639,7 +55769,7 @@ sb_1__2__mux_2level_tapbuf_size10 mux_left_track_7 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_53 , SYNOPSYS_UNCONNECTED_54 , SYNOPSYS_UNCONNECTED_55 , SYNOPSYS_UNCONNECTED_56 } ) , .out ( chanx_left_out[3] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_203 ) ) ; + .p0 ( optlc_net_207 ) ) ; sb_1__2__mux_2level_tapbuf_size10_mem_0 mem_right_track_6 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( mux_2level_tapbuf_size8_mem_0_ccff_tail ) , @@ -53660,8 +55790,8 @@ sb_1__2__mux_2level_tapbuf_size9_0 mux_right_track_10 ( .sram ( mux_2level_tapbuf_size9_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_57 , SYNOPSYS_UNCONNECTED_58 , SYNOPSYS_UNCONNECTED_59 , SYNOPSYS_UNCONNECTED_60 } ) , - .out ( { aps_rename_507_ } ) , - .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_204 ) ) ; + .out ( { aps_rename_508_ } ) , + .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_209 ) ) ; sb_1__2__mux_2level_tapbuf_size9 mux_left_track_11 ( .in ( { chanx_left_out[11] , chanx_left_out[25] , chany_bottom_in[3] , chany_bottom_in[14] , chany_bottom_in[25] , @@ -53671,7 +55801,7 @@ sb_1__2__mux_2level_tapbuf_size9 mux_left_track_11 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_61 , SYNOPSYS_UNCONNECTED_62 , SYNOPSYS_UNCONNECTED_63 , SYNOPSYS_UNCONNECTED_64 } ) , .out ( chanx_left_out[5] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_208 ) ) ; + .p0 ( optlc_net_206 ) ) ; sb_1__2__mux_2level_tapbuf_size9_mem_0 mem_right_track_10 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( mux_2level_tapbuf_size10_mem_0_ccff_tail ) , @@ -53691,7 +55821,7 @@ sb_1__2__mux_2level_tapbuf_size5_0 mux_right_track_36 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_65 , SYNOPSYS_UNCONNECTED_66 , SYNOPSYS_UNCONNECTED_67 , SYNOPSYS_UNCONNECTED_68 } ) , .out ( chanx_right_out[18] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_203 ) ) ; + .p0 ( optlc_net_204 ) ) ; sb_1__2__mux_2level_tapbuf_size5_1 mux_right_track_44 ( .in ( { right_bottom_grid_pin_39_[0] , chany_bottom_in[0] , chany_bottom_in[11] , chany_bottom_in[22] , chanx_right_out[17] } ) , @@ -53699,7 +55829,7 @@ sb_1__2__mux_2level_tapbuf_size5_1 mux_right_track_44 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_69 , SYNOPSYS_UNCONNECTED_70 , SYNOPSYS_UNCONNECTED_71 , SYNOPSYS_UNCONNECTED_72 } ) , .out ( chanx_right_out[22] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_203 ) ) ; + .p0 ( optlc_net_204 ) ) ; sb_1__2__mux_2level_tapbuf_size5_2 mux_bottom_track_5 ( .in ( { chanx_left_out[8] , bottom_left_grid_pin_46_[0] , bottom_left_grid_pin_49_[0] , chanx_left_in[4] , chanx_right_out[8] } ) , @@ -53707,7 +55837,7 @@ sb_1__2__mux_2level_tapbuf_size5_2 mux_bottom_track_5 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_73 , SYNOPSYS_UNCONNECTED_74 , SYNOPSYS_UNCONNECTED_75 , SYNOPSYS_UNCONNECTED_76 } ) , .out ( chany_bottom_out[2] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_202 ) ) ; + .p0 ( optlc_net_201 ) ) ; sb_1__2__mux_2level_tapbuf_size5_3 mux_bottom_track_11 ( .in ( { chanx_left_out[12] , bottom_left_grid_pin_46_[0] , bottom_left_grid_pin_49_[0] , chanx_right_out[12] , @@ -53716,7 +55846,7 @@ sb_1__2__mux_2level_tapbuf_size5_3 mux_bottom_track_11 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_77 , SYNOPSYS_UNCONNECTED_78 , SYNOPSYS_UNCONNECTED_79 , SYNOPSYS_UNCONNECTED_80 } ) , .out ( chany_bottom_out[5] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_202 ) ) ; + .p0 ( optlc_net_201 ) ) ; sb_1__2__mux_2level_tapbuf_size5 mux_left_track_37 ( .in ( { chanx_left_out[16] , chany_bottom_in[7] , chany_bottom_in[18] , chany_bottom_in[29] , left_bottom_grid_pin_38_[0] } ) , @@ -53762,7 +55892,7 @@ sb_1__2__mux_2level_tapbuf_size4_0 mux_right_track_52 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_85 , SYNOPSYS_UNCONNECTED_86 , SYNOPSYS_UNCONNECTED_87 , SYNOPSYS_UNCONNECTED_88 } ) , .out ( chanx_right_out[26] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_203 ) ) ; + .p0 ( optlc_net_204 ) ) ; sb_1__2__mux_2level_tapbuf_size4_1 mux_bottom_track_13 ( .in ( { chanx_left_out[13] , bottom_left_grid_pin_44_[0] , chanx_right_out[13] , chanx_left_in[17] } ) , @@ -53770,7 +55900,7 @@ sb_1__2__mux_2level_tapbuf_size4_1 mux_bottom_track_13 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_89 , SYNOPSYS_UNCONNECTED_90 , SYNOPSYS_UNCONNECTED_91 , SYNOPSYS_UNCONNECTED_92 } ) , .out ( chany_bottom_out[6] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_208 ) ) ; + .p0 ( optlc_net_207 ) ) ; sb_1__2__mux_2level_tapbuf_size4_2 mux_bottom_track_15 ( .in ( { chanx_left_out[15] , bottom_left_grid_pin_45_[0] , chanx_right_out[15] , chanx_left_in[21] } ) , @@ -53778,7 +55908,7 @@ sb_1__2__mux_2level_tapbuf_size4_2 mux_bottom_track_15 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_93 , SYNOPSYS_UNCONNECTED_94 , SYNOPSYS_UNCONNECTED_95 , SYNOPSYS_UNCONNECTED_96 } ) , .out ( chany_bottom_out[7] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_210 ) ) ; + .p0 ( optlc_net_207 ) ) ; sb_1__2__mux_2level_tapbuf_size4_3 mux_bottom_track_17 ( .in ( { chanx_left_out[16] , bottom_left_grid_pin_46_[0] , chanx_right_out[16] , chanx_left_in[25] } ) , @@ -53786,7 +55916,7 @@ sb_1__2__mux_2level_tapbuf_size4_3 mux_bottom_track_17 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_97 , SYNOPSYS_UNCONNECTED_98 , SYNOPSYS_UNCONNECTED_99 , SYNOPSYS_UNCONNECTED_100 } ) , .out ( chany_bottom_out[8] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_210 ) ) ; + .p0 ( optlc_net_207 ) ) ; sb_1__2__mux_2level_tapbuf_size4_4 mux_bottom_track_19 ( .in ( { chanx_left_out[17] , bottom_left_grid_pin_47_[0] , chanx_right_out[17] , chanx_left_in[29] } ) , @@ -53794,7 +55924,7 @@ sb_1__2__mux_2level_tapbuf_size4_4 mux_bottom_track_19 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_101 , SYNOPSYS_UNCONNECTED_102 , SYNOPSYS_UNCONNECTED_103 , SYNOPSYS_UNCONNECTED_104 } ) , .out ( chany_bottom_out[9] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_208 ) ) ; + .p0 ( optlc_net_207 ) ) ; sb_1__2__mux_2level_tapbuf_size4_5 mux_bottom_track_37 ( .in ( { chanx_left_out[29] , chanx_right_in[29] , bottom_left_grid_pin_44_[0] , chanx_right_out[29] } ) , @@ -53810,7 +55940,7 @@ sb_1__2__mux_2level_tapbuf_size4_6 mux_left_track_45 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_109 , SYNOPSYS_UNCONNECTED_110 , SYNOPSYS_UNCONNECTED_111 , SYNOPSYS_UNCONNECTED_112 } ) , .out ( chanx_left_out[22] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_208 ) ) ; + .p0 ( optlc_net_207 ) ) ; sb_1__2__mux_2level_tapbuf_size4 mux_left_track_53 ( .in ( { chanx_left_out[19] , chany_bottom_in[9] , chany_bottom_in[20] , left_bottom_grid_pin_40_[0] } ) , @@ -53818,7 +55948,7 @@ sb_1__2__mux_2level_tapbuf_size4 mux_left_track_53 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_113 , SYNOPSYS_UNCONNECTED_114 , SYNOPSYS_UNCONNECTED_115 , SYNOPSYS_UNCONNECTED_116 } ) , .out ( chanx_left_out[26] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_202 ) ) ; + .p0 ( optlc_net_201 ) ) ; sb_1__2__mux_2level_tapbuf_size4_mem_0 mem_right_track_52 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( mux_2level_tapbuf_size5_mem_1_ccff_tail ) , @@ -53874,7 +56004,7 @@ sb_1__2__mux_2level_tapbuf_size6_0 mux_bottom_track_1 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_117 , SYNOPSYS_UNCONNECTED_118 , SYNOPSYS_UNCONNECTED_119 , SYNOPSYS_UNCONNECTED_120 } ) , .out ( chany_bottom_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_202 ) ) ; + .p0 ( optlc_net_207 ) ) ; sb_1__2__mux_2level_tapbuf_size6_1 mux_bottom_track_3 ( .in ( { chanx_left_out[7] , bottom_left_grid_pin_45_[0] , bottom_left_grid_pin_48_[0] , bottom_left_grid_pin_51_[0] , @@ -53883,7 +56013,7 @@ sb_1__2__mux_2level_tapbuf_size6_1 mux_bottom_track_3 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_121 , SYNOPSYS_UNCONNECTED_122 , SYNOPSYS_UNCONNECTED_123 , SYNOPSYS_UNCONNECTED_124 } ) , .out ( chany_bottom_out[1] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_202 ) ) ; + .p0 ( optlc_net_201 ) ) ; sb_1__2__mux_2level_tapbuf_size6_2 mux_bottom_track_7 ( .in ( { chanx_left_out[9] , bottom_left_grid_pin_44_[0] , bottom_left_grid_pin_47_[0] , bottom_left_grid_pin_50_[0] , @@ -53932,7 +56062,7 @@ sb_1__2__mux_2level_tapbuf_size3_0 mux_bottom_track_21 ( .sram ( mux_2level_tapbuf_size3_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_133 , SYNOPSYS_UNCONNECTED_134 } ) , .out ( chany_bottom_out[10] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_202 ) ) ; + .p0 ( optlc_net_207 ) ) ; sb_1__2__mux_2level_tapbuf_size3_1 mux_bottom_track_23 ( .in ( { chanx_left_out[20] , bottom_left_grid_pin_49_[0] , chanx_right_out[20] } ) , @@ -53946,14 +56076,14 @@ sb_1__2__mux_2level_tapbuf_size3_2 mux_bottom_track_25 ( .sram ( mux_2level_tapbuf_size3_2_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_137 , SYNOPSYS_UNCONNECTED_138 } ) , .out ( chany_bottom_out[12] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_207 ) ) ; + .p0 ( optlc_net_210 ) ) ; sb_1__2__mux_2level_tapbuf_size3 mux_bottom_track_27 ( .in ( { chanx_left_out[23] , bottom_left_grid_pin_51_[0] , chanx_right_out[23] } ) , .sram ( mux_2level_tapbuf_size3_3_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_139 , SYNOPSYS_UNCONNECTED_140 } ) , .out ( chany_bottom_out[13] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_206 ) ) ; + .p0 ( optlc_net_201 ) ) ; sb_1__2__mux_2level_tapbuf_size3_mem_0 mem_bottom_track_21 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( mux_2level_tapbuf_size4_mem_4_ccff_tail ) , @@ -53983,67 +56113,67 @@ sb_1__2__mux_2level_tapbuf_size2_0 mux_bottom_track_29 ( .sram ( mux_2level_tapbuf_size2_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_141 , SYNOPSYS_UNCONNECTED_142 } ) , .out ( chany_bottom_out[14] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_207 ) ) ; + .p0 ( optlc_net_208 ) ) ; sb_1__2__mux_2level_tapbuf_size2_1 mux_bottom_track_31 ( .in ( { chanx_left_out[25] , chanx_right_out[25] } ) , .sram ( mux_2level_tapbuf_size2_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_143 , SYNOPSYS_UNCONNECTED_144 } ) , .out ( chany_bottom_out[15] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_207 ) ) ; + .p0 ( optlc_net_210 ) ) ; sb_1__2__mux_2level_tapbuf_size2_2 mux_bottom_track_33 ( .in ( { chanx_left_out[27] , chanx_right_out[27] } ) , .sram ( mux_2level_tapbuf_size2_2_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_145 , SYNOPSYS_UNCONNECTED_146 } ) , .out ( chany_bottom_out[16] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_204 ) ) ; + .p0 ( optlc_net_210 ) ) ; sb_1__2__mux_2level_tapbuf_size2_3 mux_bottom_track_35 ( .in ( { chanx_left_out[28] , chanx_right_out[28] } ) , .sram ( mux_2level_tapbuf_size2_3_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_147 , SYNOPSYS_UNCONNECTED_148 } ) , .out ( chany_bottom_out[17] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_207 ) ) ; + .p0 ( optlc_net_202 ) ) ; sb_1__2__mux_2level_tapbuf_size2_4 mux_bottom_track_39 ( .in ( { chanx_right_in[25] , bottom_left_grid_pin_45_[0] } ) , .sram ( mux_2level_tapbuf_size2_4_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_149 , SYNOPSYS_UNCONNECTED_150 } ) , .out ( chany_bottom_out[19] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_205 ) ) ; + .p0 ( optlc_net_203 ) ) ; sb_1__2__mux_2level_tapbuf_size2_5 mux_bottom_track_41 ( .in ( { chanx_right_in[21] , bottom_left_grid_pin_46_[0] } ) , .sram ( mux_2level_tapbuf_size2_5_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_151 , SYNOPSYS_UNCONNECTED_152 } ) , .out ( chany_bottom_out[20] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_206 ) ) ; + .p0 ( optlc_net_203 ) ) ; sb_1__2__mux_2level_tapbuf_size2_6 mux_bottom_track_43 ( .in ( { chanx_right_in[17] , bottom_left_grid_pin_47_[0] } ) , .sram ( mux_2level_tapbuf_size2_6_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_153 , SYNOPSYS_UNCONNECTED_154 } ) , .out ( chany_bottom_out[21] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_206 ) ) ; + .p0 ( optlc_net_202 ) ) ; sb_1__2__mux_2level_tapbuf_size2_7 mux_bottom_track_45 ( .in ( { chanx_right_in[13] , bottom_left_grid_pin_48_[0] } ) , .sram ( mux_2level_tapbuf_size2_7_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_155 , SYNOPSYS_UNCONNECTED_156 } ) , .out ( chany_bottom_out[22] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_201 ) ) ; + .p0 ( optlc_net_202 ) ) ; sb_1__2__mux_2level_tapbuf_size2_8 mux_bottom_track_47 ( .in ( { chanx_right_in[9] , bottom_left_grid_pin_49_[0] } ) , .sram ( mux_2level_tapbuf_size2_8_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_157 , SYNOPSYS_UNCONNECTED_158 } ) , .out ( chany_bottom_out[23] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_201 ) ) ; + .p0 ( optlc_net_202 ) ) ; sb_1__2__mux_2level_tapbuf_size2_9 mux_bottom_track_49 ( .in ( { chanx_right_in[5] , bottom_left_grid_pin_50_[0] } ) , .sram ( mux_2level_tapbuf_size2_9_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_159 , SYNOPSYS_UNCONNECTED_160 } ) , .out ( chany_bottom_out[24] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_206 ) ) ; + .p0 ( optlc_net_202 ) ) ; sb_1__2__mux_2level_tapbuf_size2 mux_bottom_track_51 ( .in ( { chanx_right_in[4] , bottom_left_grid_pin_51_[0] } ) , .sram ( mux_2level_tapbuf_size2_10_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_161 , SYNOPSYS_UNCONNECTED_162 } ) , .out ( chany_bottom_out[25] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_201 ) ) ; + .p0 ( optlc_net_210 ) ) ; sb_1__2__mux_2level_tapbuf_size2_mem_0 mem_bottom_track_29 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( mux_2level_tapbuf_size3_mem_3_ccff_tail ) , @@ -54112,18 +56242,18 @@ sb_1__2__mux_2level_tapbuf_size2_mem mem_bottom_track_51 ( .VSS ( VSS ) ) ; sky130_fd_sc_hd__buf_8 pReset_FTB00 ( .A ( pReset_E_in ) , .X ( pReset[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__bufbuf_16 pReset_W_FTB01 ( .A ( pReset_E_in ) , - .X ( pReset_W_out ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 pReset_W_FTB01 ( .A ( pReset_E_in ) , + .X ( aps_rename_509_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_1 pReset_E_FTB01 ( .A ( pReset_E_in ) , - .X ( net_net_198 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .X ( aps_rename_510_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_1 prog_clk_0_FTB00 ( .A ( prog_clk_0_S_in ) , .X ( prog_clk[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_8 FTB_107__106 ( .A ( chanx_right_in[0] ) , - .X ( chany_bottom_out[28] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 FTB_107__106 ( .A ( chanx_right_in[0] ) , + .X ( ropt_net_228 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_8 FTB_108__107 ( .A ( chanx_right_in[1] ) , .X ( chany_bottom_out[27] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_6 FTB_109__108 ( .A ( chanx_right_in[2] ) , - .X ( ropt_net_228 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .X ( ropt_net_227 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_8 FTB_110__109 ( .A ( chanx_right_in[3] ) , .X ( chanx_left_out[4] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_8 FTB_111__110 ( .A ( chanx_right_in[6] ) , @@ -54204,8 +56334,10 @@ sky130_fd_sc_hd__buf_8 FTB_148__147 ( .A ( chanx_left_in[28] ) , .X ( chanx_right_out[29] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_8 FTB_149__148 ( .A ( SC_IN_BOT ) , .X ( SC_OUT_BOT ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_198 ( .A ( net_net_198 ) , - .X ( pReset_E_out ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_197 ( .A ( BUF_net_198 ) , .Y ( pReset_W_out ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_198 ( .A ( aps_rename_509_ ) , + .Y ( BUF_net_198 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__conb_1 optlc_203 ( .LO ( SYNOPSYS_UNCONNECTED_163 ) , .HI ( optlc_net_201 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__conb_1 optlc_205 ( .LO ( SYNOPSYS_UNCONNECTED_164 ) , @@ -54216,20 +56348,24 @@ sky130_fd_sc_hd__conb_1 optlc_211 ( .LO ( SYNOPSYS_UNCONNECTED_166 ) , .HI ( optlc_net_204 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__conb_1 optlc_213 ( .LO ( SYNOPSYS_UNCONNECTED_167 ) , .HI ( optlc_net_205 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_217 ( .LO ( SYNOPSYS_UNCONNECTED_168 ) , +sky130_fd_sc_hd__conb_1 optlc_215 ( .LO ( SYNOPSYS_UNCONNECTED_168 ) , .HI ( optlc_net_206 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_219 ( .LO ( SYNOPSYS_UNCONNECTED_169 ) , +sky130_fd_sc_hd__conb_1 optlc_218 ( .LO ( SYNOPSYS_UNCONNECTED_169 ) , .HI ( optlc_net_207 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_223 ( .LO ( SYNOPSYS_UNCONNECTED_170 ) , +sky130_fd_sc_hd__conb_1 optlc_220 ( .LO ( SYNOPSYS_UNCONNECTED_170 ) , .HI ( optlc_net_208 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_225 ( .LO ( SYNOPSYS_UNCONNECTED_171 ) , +sky130_fd_sc_hd__conb_1 optlc_223 ( .LO ( SYNOPSYS_UNCONNECTED_171 ) , .HI ( optlc_net_209 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_227 ( .LO ( SYNOPSYS_UNCONNECTED_172 ) , +sky130_fd_sc_hd__conb_1 optlc_225 ( .LO ( SYNOPSYS_UNCONNECTED_172 ) , .HI ( optlc_net_210 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_6 ZBUF_6_f_inst_228 ( .A ( aps_rename_507_ ) , +sky130_fd_sc_hd__buf_6 ZBUF_6_f_inst_226 ( .A ( aps_rename_508_ ) , .X ( chanx_right_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_8 ropt_mt_inst_1437 ( .A ( ropt_net_228 ) , +sky130_fd_sc_hd__buf_6 ZBUF_6_f_inst_227 ( .A ( aps_rename_510_ ) , + .X ( pReset_E_out ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1435 ( .A ( ropt_net_227 ) , .X ( chany_bottom_out[26] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1436 ( .A ( ropt_net_228 ) , + .X ( chany_bottom_out[28] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -54243,7 +56379,6 @@ output [0:3] mem_out ; input VDD ; input VSS ; -wire copt_net_208 ; supply1 VDD ; supply0 VSS ; @@ -54257,14 +56392,10 @@ sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( copt_net_208 ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 FTB_68__67 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__bufbuf_8 FTB_68__67 ( .A ( copt_net_209 ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1418 ( .A ( copt_net_208 ) , - .X ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1419 ( .A ( mem_out[3] ) , - .X ( copt_net_209 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -54608,13 +56739,16 @@ input VDD ; input VSS ; input p0 ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -54627,13 +56761,16 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -54646,13 +56783,16 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -54726,6 +56866,9 @@ wire [0:0] mux_2level_tapbuf_basis_input3_mem3_2_out ; supply1 VDD ; supply0 VSS ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( mux_2level_tapbuf_basis_input3_mem3_2_out[0] ) , .X ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; sb_1__1__local_encoder2to3_22 local_encoder2to3_0_ ( .addr ( sram[0:1] ) , .data ( local_encoder2to3_0_data ) , .data_inv ( local_encoder2to3_0_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; @@ -54750,9 +56893,6 @@ sb_1__1__mux_2level_tapbuf_basis_input3_mem3 mux_l2_in_0_ ( .mem_inv ( local_encoder2to3_1_data_inv ) , .out ( mux_2level_tapbuf_basis_input3_mem3_2_out ) , .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_190 ( - .A ( mux_2level_tapbuf_basis_input3_mem3_2_out[0] ) , .X ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -54766,13 +56906,16 @@ input VDD ; input VSS ; input p0 ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -54785,13 +56928,16 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -54804,13 +56950,16 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -54908,10 +57057,10 @@ sb_1__1__mux_2level_tapbuf_basis_input3_mem3_40 mux_l2_in_0_ ( .mem_inv ( local_encoder2to3_1_data_inv ) , .out ( mux_2level_tapbuf_basis_input3_mem3_2_out ) , .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_188 ( .A ( BUF_net_189 ) , .Y ( out[0] ) , +sky130_fd_sc_hd__inv_8 BINV_R_170 ( .A ( BUF_net_171 ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_189 ( - .A ( mux_2level_tapbuf_basis_input3_mem3_2_out[0] ) , .Y ( BUF_net_189 ) , +sky130_fd_sc_hd__inv_1 BINV_R_171 ( + .A ( mux_2level_tapbuf_basis_input3_mem3_2_out[0] ) , .Y ( BUF_net_171 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -54926,13 +57075,16 @@ input VDD ; input VSS ; input p0 ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -54945,13 +57097,16 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -54964,13 +57119,16 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -55015,7 +57173,7 @@ sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) , .Y ( data_inv[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) , +sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) , .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -55068,10 +57226,10 @@ sb_1__1__mux_2level_tapbuf_basis_input3_mem3_37 mux_l2_in_0_ ( .mem_inv ( local_encoder2to3_1_data_inv ) , .out ( mux_2level_tapbuf_basis_input3_mem3_2_out ) , .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_186 ( .A ( BUF_net_187 ) , .Y ( out[0] ) , +sky130_fd_sc_hd__inv_8 BINV_R_164 ( .A ( BUF_net_165 ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_187 ( - .A ( mux_2level_tapbuf_basis_input3_mem3_2_out[0] ) , .Y ( BUF_net_187 ) , +sky130_fd_sc_hd__inv_1 BINV_R_165 ( + .A ( mux_2level_tapbuf_basis_input3_mem3_2_out[0] ) , .Y ( BUF_net_165 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -55086,13 +57244,16 @@ input VDD ; input VSS ; input p0 ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -55105,13 +57266,16 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -55124,13 +57288,16 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -55204,6 +57371,9 @@ wire [0:0] mux_2level_tapbuf_basis_input3_mem3_2_out ; supply1 VDD ; supply0 VSS ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( mux_2level_tapbuf_basis_input3_mem3_2_out[0] ) , .X ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; sb_1__1__local_encoder2to3_16 local_encoder2to3_0_ ( .addr ( sram[0:1] ) , .data ( local_encoder2to3_0_data ) , .data_inv ( local_encoder2to3_0_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; @@ -55228,11 +57398,6 @@ sb_1__1__mux_2level_tapbuf_basis_input3_mem3_34 mux_l2_in_0_ ( .mem_inv ( local_encoder2to3_1_data_inv ) , .out ( mux_2level_tapbuf_basis_input3_mem3_2_out ) , .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_184 ( .A ( BUF_net_185 ) , .Y ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_185 ( - .A ( mux_2level_tapbuf_basis_input3_mem3_2_out[0] ) , .Y ( BUF_net_185 ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -55246,13 +57411,16 @@ input VDD ; input VSS ; input p0 ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -55265,13 +57433,16 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -55284,13 +57455,16 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -55404,13 +57578,16 @@ input VDD ; input VSS ; input p0 ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -55423,13 +57600,16 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -55442,13 +57622,16 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -55522,6 +57705,9 @@ wire [0:0] mux_2level_tapbuf_basis_input3_mem3_2_out ; supply1 VDD ; supply0 VSS ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( mux_2level_tapbuf_basis_input3_mem3_2_out[0] ) , .X ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; sb_1__1__local_encoder2to3_12 local_encoder2to3_0_ ( .addr ( sram[0:1] ) , .data ( local_encoder2to3_0_data ) , .data_inv ( local_encoder2to3_0_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; @@ -55546,11 +57732,6 @@ sb_1__1__mux_2level_tapbuf_basis_input3_mem3_28 mux_l2_in_0_ ( .mem_inv ( local_encoder2to3_1_data_inv ) , .out ( mux_2level_tapbuf_basis_input3_mem3_2_out ) , .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_182 ( .A ( BUF_net_183 ) , .Y ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_183 ( - .A ( mux_2level_tapbuf_basis_input3_mem3_2_out[0] ) , .Y ( BUF_net_183 ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -55564,13 +57745,16 @@ input VDD ; input VSS ; input p0 ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -55583,13 +57767,16 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -55602,13 +57789,16 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -55706,10 +57896,8 @@ sb_1__1__mux_2level_tapbuf_basis_input3_mem3_25 mux_l2_in_0_ ( .mem_inv ( local_encoder2to3_1_data_inv ) , .out ( mux_2level_tapbuf_basis_input3_mem3_2_out ) , .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_180 ( .A ( BUF_net_181 ) , .Y ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_181 ( - .A ( mux_2level_tapbuf_basis_input3_mem3_2_out[0] ) , .Y ( BUF_net_181 ) , +sky130_fd_sc_hd__buf_6 BUFT_RR_163 ( + .A ( mux_2level_tapbuf_basis_input3_mem3_2_out[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -55724,13 +57912,16 @@ input VDD ; input VSS ; input p0 ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -55743,13 +57934,16 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -55762,13 +57956,16 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -55866,10 +58063,8 @@ sb_1__1__mux_2level_tapbuf_basis_input3_mem3_22 mux_l2_in_0_ ( .mem_inv ( local_encoder2to3_1_data_inv ) , .out ( mux_2level_tapbuf_basis_input3_mem3_2_out ) , .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_178 ( .A ( BUF_net_179 ) , .Y ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_179 ( - .A ( mux_2level_tapbuf_basis_input3_mem3_2_out[0] ) , .Y ( BUF_net_179 ) , +sky130_fd_sc_hd__buf_6 BUFT_RR_162 ( + .A ( mux_2level_tapbuf_basis_input3_mem3_2_out[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -55884,13 +58079,16 @@ input VDD ; input VSS ; input p0 ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -55903,13 +58101,16 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -55922,13 +58123,16 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -56002,6 +58206,9 @@ wire [0:0] mux_2level_tapbuf_basis_input3_mem3_2_out ; supply1 VDD ; supply0 VSS ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( mux_2level_tapbuf_basis_input3_mem3_2_out[0] ) , .X ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; sb_1__1__local_encoder2to3_6 local_encoder2to3_0_ ( .addr ( sram[0:1] ) , .data ( local_encoder2to3_0_data ) , .data_inv ( local_encoder2to3_0_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; @@ -56026,11 +58233,6 @@ sb_1__1__mux_2level_tapbuf_basis_input3_mem3_19 mux_l2_in_0_ ( .mem_inv ( local_encoder2to3_1_data_inv ) , .out ( mux_2level_tapbuf_basis_input3_mem3_2_out ) , .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_176 ( .A ( BUF_net_177 ) , .Y ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_177 ( - .A ( mux_2level_tapbuf_basis_input3_mem3_2_out[0] ) , .Y ( BUF_net_177 ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -56044,13 +58246,16 @@ input VDD ; input VSS ; input p0 ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -56063,13 +58268,16 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -56082,13 +58290,16 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -56162,6 +58373,9 @@ wire [0:0] mux_2level_tapbuf_basis_input3_mem3_2_out ; supply1 VDD ; supply0 VSS ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( mux_2level_tapbuf_basis_input3_mem3_2_out[0] ) , .X ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; sb_1__1__local_encoder2to3_4 local_encoder2to3_0_ ( .addr ( sram[0:1] ) , .data ( local_encoder2to3_0_data ) , .data_inv ( local_encoder2to3_0_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; @@ -56186,11 +58400,6 @@ sb_1__1__mux_2level_tapbuf_basis_input3_mem3_16 mux_l2_in_0_ ( .mem_inv ( local_encoder2to3_1_data_inv ) , .out ( mux_2level_tapbuf_basis_input3_mem3_2_out ) , .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_174 ( .A ( BUF_net_175 ) , .Y ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_175 ( - .A ( mux_2level_tapbuf_basis_input3_mem3_2_out[0] ) , .Y ( BUF_net_175 ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -56204,13 +58413,16 @@ input VDD ; input VSS ; input p0 ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -56223,13 +58435,16 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -56242,13 +58457,16 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -56322,6 +58540,9 @@ wire [0:0] mux_2level_tapbuf_basis_input3_mem3_2_out ; supply1 VDD ; supply0 VSS ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( mux_2level_tapbuf_basis_input3_mem3_2_out[0] ) , .X ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; sb_1__1__local_encoder2to3_2 local_encoder2to3_0_ ( .addr ( sram[0:1] ) , .data ( local_encoder2to3_0_data ) , .data_inv ( local_encoder2to3_0_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; @@ -56346,11 +58567,6 @@ sb_1__1__mux_2level_tapbuf_basis_input3_mem3_13 mux_l2_in_0_ ( .mem_inv ( local_encoder2to3_1_data_inv ) , .out ( mux_2level_tapbuf_basis_input3_mem3_2_out ) , .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_195 ( .A ( BUF_net_196 ) , .Y ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_196 ( - .A ( mux_2level_tapbuf_basis_input3_mem3_2_out[0] ) , .Y ( BUF_net_196 ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -56364,13 +58580,16 @@ input VDD ; input VSS ; input p0 ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -56383,13 +58602,16 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -56402,13 +58624,16 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -56642,15 +58867,20 @@ input VDD ; input VSS ; input p0 ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -56663,15 +58893,20 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -56684,15 +58919,20 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -56778,9 +59018,9 @@ wire [0:0] mux_2level_tapbuf_basis_input4_mem4_2_out ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( mux_2level_tapbuf_basis_input4_mem4_2_out[0] ) , .X ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_4_0_ ( + .A ( mux_2level_tapbuf_basis_input4_mem4_2_out[0] ) , + .X ( aps_rename_513_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sb_1__1__local_encoder2to4_62 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , .data ( local_encoder2to4_0_data ) , .data_inv ( local_encoder2to4_0_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; @@ -56805,6 +59045,10 @@ sb_1__1__mux_2level_tapbuf_basis_input4_mem4 mux_l2_in_0_ ( .mem_inv ( local_encoder2to4_1_data_inv ) , .out ( mux_2level_tapbuf_basis_input4_mem4_2_out ) , .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_160 ( .A ( BUF_net_161 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_161 ( .A ( aps_rename_513_ ) , + .Y ( BUF_net_161 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -56818,15 +59062,20 @@ input VDD ; input VSS ; input p0 ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -56839,15 +59088,20 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -56860,15 +59114,20 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -56956,7 +59215,7 @@ supply0 VSS ; sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_4_0_ ( .A ( mux_2level_tapbuf_basis_input4_mem4_2_out[0] ) , - .X ( aps_rename_520_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .X ( aps_rename_512_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sb_1__1__local_encoder2to4_60 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , .data ( local_encoder2to4_0_data ) , .data_inv ( local_encoder2to4_0_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; @@ -56981,10 +59240,10 @@ sb_1__1__mux_2level_tapbuf_basis_input4_mem4_100 mux_l2_in_0_ ( .mem_inv ( local_encoder2to4_1_data_inv ) , .out ( mux_2level_tapbuf_basis_input4_mem4_2_out ) , .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_172 ( .A ( BUF_net_173 ) , .Y ( out[0] ) , +sky130_fd_sc_hd__inv_8 BINV_R_158 ( .A ( BUF_net_159 ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_173 ( .A ( aps_rename_520_ ) , - .Y ( BUF_net_173 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_159 ( .A ( aps_rename_512_ ) , + .Y ( BUF_net_159 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -56998,15 +59257,20 @@ input VDD ; input VSS ; input p0 ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -57019,15 +59283,20 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -57040,15 +59309,20 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -57134,9 +59408,9 @@ wire [0:0] mux_2level_tapbuf_basis_input4_mem4_2_out ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_4_0_ ( - .A ( mux_2level_tapbuf_basis_input4_mem4_2_out[0] ) , - .X ( aps_rename_519_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( mux_2level_tapbuf_basis_input4_mem4_2_out[0] ) , .X ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; sb_1__1__local_encoder2to4_58 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , .data ( local_encoder2to4_0_data ) , .data_inv ( local_encoder2to4_0_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; @@ -57161,10 +59435,6 @@ sb_1__1__mux_2level_tapbuf_basis_input4_mem4_97 mux_l2_in_0_ ( .mem_inv ( local_encoder2to4_1_data_inv ) , .out ( mux_2level_tapbuf_basis_input4_mem4_2_out ) , .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_170 ( .A ( BUF_net_171 ) , .Y ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_171 ( .A ( aps_rename_519_ ) , - .Y ( BUF_net_171 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -57178,15 +59448,20 @@ input VDD ; input VSS ; input p0 ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -57199,15 +59474,20 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -57220,15 +59500,20 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -57316,7 +59601,7 @@ supply0 VSS ; sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_4_0_ ( .A ( mux_2level_tapbuf_basis_input4_mem4_2_out[0] ) , - .X ( aps_rename_518_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .X ( aps_rename_511_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sb_1__1__local_encoder2to4_56 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , .data ( local_encoder2to4_0_data ) , .data_inv ( local_encoder2to4_0_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; @@ -57341,10 +59626,10 @@ sb_1__1__mux_2level_tapbuf_basis_input4_mem4_94 mux_l2_in_0_ ( .mem_inv ( local_encoder2to4_1_data_inv ) , .out ( mux_2level_tapbuf_basis_input4_mem4_2_out ) , .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_168 ( .A ( BUF_net_169 ) , .Y ( out[0] ) , +sky130_fd_sc_hd__inv_8 BINV_R_156 ( .A ( BUF_net_157 ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_169 ( .A ( aps_rename_518_ ) , - .Y ( BUF_net_169 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_157 ( .A ( aps_rename_511_ ) , + .Y ( BUF_net_157 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -57598,15 +59883,20 @@ input VDD ; input VSS ; input p0 ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -57619,15 +59909,20 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -57640,15 +59935,20 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -57661,15 +59961,20 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -57756,9 +60061,9 @@ wire [0:0] mux_2level_tapbuf_basis_input4_mem4_3_out ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_4_0_ ( - .A ( mux_2level_tapbuf_basis_input4_mem4_3_out[0] ) , - .X ( aps_rename_517_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( mux_2level_tapbuf_basis_input4_mem4_3_out[0] ) , .X ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; sb_1__1__local_encoder2to4_54 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , .data ( local_encoder2to4_0_data ) , .data_inv ( local_encoder2to4_0_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; @@ -57789,10 +60094,6 @@ sb_1__1__mux_2level_tapbuf_basis_input4_mem4_91 mux_l2_in_0_ ( .mem_inv ( local_encoder2to4_1_data_inv ) , .out ( mux_2level_tapbuf_basis_input4_mem4_3_out ) , .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_166 ( .A ( BUF_net_167 ) , .Y ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_167 ( .A ( aps_rename_517_ ) , - .Y ( BUF_net_167 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -57806,15 +60107,20 @@ input VDD ; input VSS ; input p0 ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -57827,15 +60133,20 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -57848,15 +60159,20 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -57869,15 +60185,20 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -58010,15 +60331,20 @@ input VDD ; input VSS ; input p0 ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -58031,15 +60357,20 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -58052,15 +60383,20 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -58073,15 +60409,20 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -58168,7 +60509,7 @@ wire [0:0] mux_2level_tapbuf_basis_input4_mem4_3_out ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__bufbuf_16 sky130_fd_sc_hd__buf_4_0_ ( +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( mux_2level_tapbuf_basis_input4_mem4_3_out[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sb_1__1__local_encoder2to4_50 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , @@ -58214,15 +60555,20 @@ input VDD ; input VSS ; input p0 ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -58235,15 +60581,20 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -58256,15 +60607,20 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -58277,15 +60633,20 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -58418,15 +60779,20 @@ input VDD ; input VSS ; input p0 ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -58439,15 +60805,20 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -58460,15 +60831,20 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -58481,15 +60857,20 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -58578,7 +60959,7 @@ supply0 VSS ; sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_4_0_ ( .A ( mux_2level_tapbuf_basis_input4_mem4_3_out[0] ) , - .X ( aps_rename_516_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .X ( aps_rename_510_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sb_1__1__local_encoder2to4_46 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , .data ( local_encoder2to4_0_data ) , .data_inv ( local_encoder2to4_0_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; @@ -58609,10 +60990,10 @@ sb_1__1__mux_2level_tapbuf_basis_input4_mem4_75 mux_l2_in_0_ ( .mem_inv ( local_encoder2to4_1_data_inv ) , .out ( mux_2level_tapbuf_basis_input4_mem4_3_out ) , .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_164 ( .A ( BUF_net_165 ) , .Y ( out[0] ) , +sky130_fd_sc_hd__inv_8 BINV_R_154 ( .A ( BUF_net_155 ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_165 ( .A ( aps_rename_516_ ) , - .Y ( BUF_net_165 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_155 ( .A ( aps_rename_510_ ) , + .Y ( BUF_net_155 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -58626,15 +61007,20 @@ input VDD ; input VSS ; input p0 ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -58647,15 +61033,20 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -58668,15 +61059,20 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -58689,15 +61085,20 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -58784,7 +61185,7 @@ wire [0:0] mux_2level_tapbuf_basis_input4_mem4_3_out ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_4_0_ ( +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( mux_2level_tapbuf_basis_input4_mem4_3_out[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sb_1__1__local_encoder2to4_44 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , @@ -58830,15 +61231,20 @@ input VDD ; input VSS ; input p0 ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -58851,15 +61257,20 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -58872,15 +61283,20 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -58893,15 +61309,20 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -58988,9 +61409,9 @@ wire [0:0] mux_2level_tapbuf_basis_input4_mem4_3_out ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_4_0_ ( - .A ( mux_2level_tapbuf_basis_input4_mem4_3_out[0] ) , - .X ( aps_rename_515_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( mux_2level_tapbuf_basis_input4_mem4_3_out[0] ) , .X ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; sb_1__1__local_encoder2to4_42 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , .data ( local_encoder2to4_0_data ) , .data_inv ( local_encoder2to4_0_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; @@ -59021,10 +61442,6 @@ sb_1__1__mux_2level_tapbuf_basis_input4_mem4_67 mux_l2_in_0_ ( .mem_inv ( local_encoder2to4_1_data_inv ) , .out ( mux_2level_tapbuf_basis_input4_mem4_3_out ) , .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_162 ( .A ( BUF_net_163 ) , .Y ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_163 ( .A ( aps_rename_515_ ) , - .Y ( BUF_net_163 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -59038,15 +61455,20 @@ input VDD ; input VSS ; input p0 ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -59059,15 +61481,20 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -59080,15 +61507,20 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -59101,15 +61533,20 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -59196,9 +61633,9 @@ wire [0:0] mux_2level_tapbuf_basis_input4_mem4_3_out ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_4_0_ ( - .A ( mux_2level_tapbuf_basis_input4_mem4_3_out[0] ) , - .X ( aps_rename_514_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__bufbuf_16 sky130_fd_sc_hd__buf_4_0_ ( + .A ( mux_2level_tapbuf_basis_input4_mem4_3_out[0] ) , .X ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; sb_1__1__local_encoder2to4_40 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , .data ( local_encoder2to4_0_data ) , .data_inv ( local_encoder2to4_0_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; @@ -59229,10 +61666,6 @@ sb_1__1__mux_2level_tapbuf_basis_input4_mem4_63 mux_l2_in_0_ ( .mem_inv ( local_encoder2to4_1_data_inv ) , .out ( mux_2level_tapbuf_basis_input4_mem4_3_out ) , .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_160 ( .A ( BUF_net_161 ) , .Y ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_161 ( .A ( aps_rename_514_ ) , - .Y ( BUF_net_161 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -59605,12 +62038,15 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -59624,15 +62060,20 @@ input VDD ; input VSS ; input p0 ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -59645,15 +62086,20 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -59666,15 +62112,20 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -59806,12 +62257,15 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -59825,15 +62279,20 @@ input VDD ; input VSS ; input p0 ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -59846,15 +62305,20 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -59867,15 +62331,20 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -59963,8 +62432,8 @@ supply1 VDD ; supply0 VSS ; sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_4_0_ ( - .A ( mux_2level_tapbuf_basis_input4_mem4_2_out[0] ) , - .X ( aps_rename_513_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .A ( mux_2level_tapbuf_basis_input4_mem4_2_out[0] ) , .X ( net_net_153 ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; sb_1__1__local_encoder2to4_36 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , .data ( local_encoder2to4_0_data ) , .data_inv ( local_encoder2to4_0_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; @@ -59995,10 +62464,8 @@ sb_1__1__mux_2level_tapbuf_basis_input2_mem2_10 mux_l1_in_2_ ( .mem_inv ( local_encoder2to4_0_data_inv[0:1] ) , .out ( mux_2level_tapbuf_basis_input2_mem2_0_out ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_158 ( .A ( BUF_net_159 ) , .Y ( out[0] ) , +sky130_fd_sc_hd__buf_6 BUFT_RR_153 ( .A ( net_net_153 ) , .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_159 ( .A ( aps_rename_513_ ) , - .Y ( BUF_net_159 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -60011,12 +62478,15 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -60030,15 +62500,20 @@ input VDD ; input VSS ; input p0 ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -60051,15 +62526,20 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -60072,15 +62552,20 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -60169,7 +62654,7 @@ supply0 VSS ; sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_4_0_ ( .A ( mux_2level_tapbuf_basis_input4_mem4_2_out[0] ) , - .X ( aps_rename_512_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .X ( aps_rename_509_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sb_1__1__local_encoder2to4_34 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , .data ( local_encoder2to4_0_data ) , .data_inv ( local_encoder2to4_0_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; @@ -60200,10 +62685,10 @@ sb_1__1__mux_2level_tapbuf_basis_input2_mem2_9 mux_l1_in_2_ ( .mem_inv ( local_encoder2to4_0_data_inv[0:1] ) , .out ( mux_2level_tapbuf_basis_input2_mem2_0_out ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_156 ( .A ( BUF_net_157 ) , .Y ( out[0] ) , +sky130_fd_sc_hd__inv_8 BINV_R_151 ( .A ( BUF_net_152 ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_157 ( .A ( aps_rename_512_ ) , - .Y ( BUF_net_157 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_152 ( .A ( aps_rename_509_ ) , + .Y ( BUF_net_152 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -60216,12 +62701,15 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -60235,15 +62723,20 @@ input VDD ; input VSS ; input p0 ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -60256,15 +62749,20 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -60277,15 +62775,20 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -60417,12 +62920,15 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -60436,15 +62942,20 @@ input VDD ; input VSS ; input p0 ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -60457,15 +62968,20 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -60478,15 +62994,20 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -60618,12 +63139,15 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -60637,15 +63161,20 @@ input VDD ; input VSS ; input p0 ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -60658,15 +63187,20 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -60679,15 +63213,20 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -60819,12 +63358,15 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -60838,15 +63380,20 @@ input VDD ; input VSS ; input p0 ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -60859,15 +63406,20 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -60880,15 +63432,20 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -60975,9 +63532,9 @@ wire [0:0] mux_2level_tapbuf_basis_input4_mem4_2_out ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_4_0_ ( - .A ( mux_2level_tapbuf_basis_input4_mem4_2_out[0] ) , - .X ( aps_rename_511_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( mux_2level_tapbuf_basis_input4_mem4_2_out[0] ) , .X ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; sb_1__1__local_encoder2to4_26 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , .data ( local_encoder2to4_0_data ) , .data_inv ( local_encoder2to4_0_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; @@ -61008,10 +63565,6 @@ sb_1__1__mux_2level_tapbuf_basis_input2_mem2_5 mux_l1_in_2_ ( .mem_inv ( local_encoder2to4_0_data_inv[0:1] ) , .out ( mux_2level_tapbuf_basis_input2_mem2_0_out ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_154 ( .A ( BUF_net_155 ) , .Y ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_155 ( .A ( aps_rename_511_ ) , - .Y ( BUF_net_155 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -61024,12 +63577,15 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -61043,15 +63599,20 @@ input VDD ; input VSS ; input p0 ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -61064,15 +63625,20 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -61085,15 +63651,20 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -61182,7 +63753,7 @@ supply0 VSS ; sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_4_0_ ( .A ( mux_2level_tapbuf_basis_input4_mem4_2_out[0] ) , - .X ( aps_rename_510_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .X ( aps_rename_508_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sb_1__1__local_encoder2to4_24 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , .data ( local_encoder2to4_0_data ) , .data_inv ( local_encoder2to4_0_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; @@ -61213,10 +63784,10 @@ sb_1__1__mux_2level_tapbuf_basis_input2_mem2_4 mux_l1_in_2_ ( .mem_inv ( local_encoder2to4_0_data_inv[0:1] ) , .out ( mux_2level_tapbuf_basis_input2_mem2_0_out ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_152 ( .A ( BUF_net_153 ) , .Y ( out[0] ) , +sky130_fd_sc_hd__inv_8 BINV_R_149 ( .A ( BUF_net_150 ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_153 ( .A ( aps_rename_510_ ) , - .Y ( BUF_net_153 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_150 ( .A ( aps_rename_508_ ) , + .Y ( BUF_net_150 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -61229,12 +63800,15 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -61248,15 +63822,20 @@ input VDD ; input VSS ; input p0 ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -61269,15 +63848,20 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -61290,15 +63874,20 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -61385,9 +63974,9 @@ wire [0:0] mux_2level_tapbuf_basis_input4_mem4_2_out ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_4_0_ ( - .A ( mux_2level_tapbuf_basis_input4_mem4_2_out[0] ) , - .X ( aps_rename_509_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( mux_2level_tapbuf_basis_input4_mem4_2_out[0] ) , .X ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; sb_1__1__local_encoder2to4_22 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , .data ( local_encoder2to4_0_data ) , .data_inv ( local_encoder2to4_0_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; @@ -61418,10 +64007,6 @@ sb_1__1__mux_2level_tapbuf_basis_input2_mem2_3 mux_l1_in_2_ ( .mem_inv ( local_encoder2to4_0_data_inv[0:1] ) , .out ( mux_2level_tapbuf_basis_input2_mem2_0_out ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_150 ( .A ( BUF_net_151 ) , .Y ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_151 ( .A ( aps_rename_509_ ) , - .Y ( BUF_net_151 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -61434,12 +64019,15 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -61453,15 +64041,20 @@ input VDD ; input VSS ; input p0 ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -61474,15 +64067,20 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -61495,15 +64093,20 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -61590,7 +64193,7 @@ wire [0:0] mux_2level_tapbuf_basis_input4_mem4_2_out ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__bufbuf_16 sky130_fd_sc_hd__buf_4_0_ ( +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( mux_2level_tapbuf_basis_input4_mem4_2_out[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sb_1__1__local_encoder2to4_20 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , @@ -61635,12 +64238,15 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -61654,15 +64260,20 @@ input VDD ; input VSS ; input p0 ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -61675,15 +64286,20 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -61696,15 +64312,20 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -61791,9 +64412,9 @@ wire [0:0] mux_2level_tapbuf_basis_input4_mem4_2_out ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_4_0_ ( - .A ( mux_2level_tapbuf_basis_input4_mem4_2_out[0] ) , - .X ( aps_rename_508_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( mux_2level_tapbuf_basis_input4_mem4_2_out[0] ) , .X ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; sb_1__1__local_encoder2to4_18 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , .data ( local_encoder2to4_0_data ) , .data_inv ( local_encoder2to4_0_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; @@ -61824,10 +64445,6 @@ sb_1__1__mux_2level_tapbuf_basis_input2_mem2_1 mux_l1_in_2_ ( .mem_inv ( local_encoder2to4_0_data_inv[0:1] ) , .out ( mux_2level_tapbuf_basis_input2_mem2_0_out ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_193 ( .A ( BUF_net_194 ) , .Y ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_194 ( .A ( aps_rename_508_ ) , - .Y ( BUF_net_194 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -61840,12 +64457,15 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -61859,15 +64479,20 @@ input VDD ; input VSS ; input p0 ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -61880,15 +64505,20 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -61901,15 +64531,20 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -61996,9 +64631,9 @@ wire [0:0] mux_2level_tapbuf_basis_input4_mem4_2_out ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_4_0_ ( - .A ( mux_2level_tapbuf_basis_input4_mem4_2_out[0] ) , - .X ( aps_rename_507_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( mux_2level_tapbuf_basis_input4_mem4_2_out[0] ) , .X ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; sb_1__1__local_encoder2to4_16 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , .data ( local_encoder2to4_0_data ) , .data_inv ( local_encoder2to4_0_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; @@ -62029,10 +64664,6 @@ sb_1__1__mux_2level_tapbuf_basis_input2_mem2_0 mux_l1_in_2_ ( .mem_inv ( local_encoder2to4_0_data_inv[0:1] ) , .out ( mux_2level_tapbuf_basis_input2_mem2_0_out ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_148 ( .A ( BUF_net_149 ) , .Y ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_149 ( .A ( aps_rename_507_ ) , - .Y ( BUF_net_149 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -62259,7 +64890,7 @@ input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( copt_net_207 ) , +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , @@ -62273,10 +64904,6 @@ sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_1 FTB_1__0 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 copt_h_inst_1416 ( .A ( ccff_head[0] ) , - .X ( copt_net_206 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1417 ( .A ( copt_net_206 ) , - .X ( copt_net_207 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -62289,13 +64916,16 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -62309,15 +64939,20 @@ input VDD ; input VSS ; input p0 ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -62330,15 +64965,20 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -62351,15 +64991,20 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -62446,7 +65091,7 @@ wire [0:0] mux_2level_tapbuf_basis_input4_mem4_2_out ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__bufbuf_16 sky130_fd_sc_hd__buf_4_0_ ( +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( mux_2level_tapbuf_basis_input4_mem4_2_out[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sb_1__1__local_encoder2to4_14 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , @@ -62491,13 +65136,16 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -62511,15 +65159,20 @@ input VDD ; input VSS ; input p0 ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -62532,15 +65185,20 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -62553,15 +65211,20 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -62648,9 +65311,9 @@ wire [0:0] mux_2level_tapbuf_basis_input4_mem4_2_out ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( mux_2level_tapbuf_basis_input4_mem4_2_out[0] ) , .X ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_4_0_ ( + .A ( mux_2level_tapbuf_basis_input4_mem4_2_out[0] ) , + .X ( aps_rename_507_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sb_1__1__local_encoder2to4_12 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , .data ( local_encoder2to4_0_data ) , .data_inv ( local_encoder2to4_0_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; @@ -62681,6 +65344,10 @@ sb_1__1__mux_2level_tapbuf_basis_input3_mem3_6 mux_l1_in_2_ ( .mem_inv ( local_encoder2to4_0_data_inv[0:2] ) , .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_147 ( .A ( BUF_net_148 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_148 ( .A ( aps_rename_507_ ) , + .Y ( BUF_net_148 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -62693,13 +65360,16 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -62713,15 +65383,20 @@ input VDD ; input VSS ; input p0 ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -62734,15 +65409,20 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -62755,15 +65435,20 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -62850,8 +65535,8 @@ wire [0:0] mux_2level_tapbuf_basis_input4_mem4_2_out ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__bufbuf_16 sky130_fd_sc_hd__buf_4_0_ ( - .A ( mux_2level_tapbuf_basis_input4_mem4_2_out[0] ) , .X ( out[0] ) , +sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_4_0_ ( + .A ( mux_2level_tapbuf_basis_input4_mem4_2_out[0] ) , .X ( net_net_146 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sb_1__1__local_encoder2to4_10 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , .data ( local_encoder2to4_0_data ) , @@ -62883,6 +65568,8 @@ sb_1__1__mux_2level_tapbuf_basis_input3_mem3_5 mux_l1_in_2_ ( .mem_inv ( local_encoder2to4_0_data_inv[0:2] ) , .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_146 ( .A ( net_net_146 ) , .X ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -62895,13 +65582,16 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -62915,15 +65605,20 @@ input VDD ; input VSS ; input p0 ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -62936,15 +65631,20 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -62957,15 +65657,20 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -63085,10 +65790,10 @@ sb_1__1__mux_2level_tapbuf_basis_input3_mem3_4 mux_l1_in_2_ ( .mem_inv ( local_encoder2to4_0_data_inv[0:2] ) , .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_146 ( .A ( BUF_net_147 ) , .Y ( out[0] ) , +sky130_fd_sc_hd__inv_8 BINV_R_144 ( .A ( BUF_net_145 ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_147 ( .A ( aps_rename_506_ ) , - .Y ( BUF_net_147 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_145 ( .A ( aps_rename_506_ ) , + .Y ( BUF_net_145 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -63101,13 +65806,16 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -63121,15 +65829,20 @@ input VDD ; input VSS ; input p0 ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -63142,15 +65855,20 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -63163,15 +65881,20 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -63303,13 +66026,16 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -63323,15 +66049,20 @@ input VDD ; input VSS ; input p0 ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -63344,15 +66075,20 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -63365,15 +66101,20 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -63460,7 +66201,7 @@ wire [0:0] mux_2level_tapbuf_basis_input4_mem4_2_out ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_4_0_ ( +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( mux_2level_tapbuf_basis_input4_mem4_2_out[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sb_1__1__local_encoder2to4_4 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , @@ -63505,13 +66246,16 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -63525,15 +66269,20 @@ input VDD ; input VSS ; input p0 ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -63546,15 +66295,20 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -63567,15 +66321,20 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -63695,10 +66454,10 @@ sb_1__1__mux_2level_tapbuf_basis_input3_mem3_1 mux_l1_in_2_ ( .mem_inv ( local_encoder2to4_0_data_inv[0:2] ) , .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_144 ( .A ( BUF_net_145 ) , .Y ( out[0] ) , +sky130_fd_sc_hd__inv_8 BINV_R_172 ( .A ( BUF_net_173 ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_145 ( .A ( aps_rename_505_ ) , - .Y ( BUF_net_145 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_173 ( .A ( aps_rename_505_ ) , + .Y ( BUF_net_173 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -63711,13 +66470,16 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -63731,15 +66493,20 @@ input VDD ; input VSS ; input p0 ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -63752,15 +66519,20 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -63773,15 +66545,20 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -64169,7 +66946,7 @@ sb_1__1__mux_2level_tapbuf_size11_0 mux_top_track_0 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 , SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) , .out ( chany_top_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_200 ) ) ; + .p0 ( optlc_net_179 ) ) ; sb_1__1__mux_2level_tapbuf_size11_1 mux_top_track_2 ( .in ( { top_left_grid_pin_45_[0] , top_left_grid_pin_48_[0] , top_left_grid_pin_51_[0] , chanx_right_in[2] , chanx_left_out[7] , @@ -64179,7 +66956,7 @@ sb_1__1__mux_2level_tapbuf_size11_1 mux_top_track_2 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 , SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 } ) , .out ( chany_top_out[1] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_201 ) ) ; + .p0 ( optlc_net_179 ) ) ; sb_1__1__mux_2level_tapbuf_size11_2 mux_right_track_0 ( .in ( { chany_bottom_out[4] , chany_bottom_out[20] , chany_top_in[29] , right_bottom_grid_pin_36_[0] , right_bottom_grid_pin_39_[0] , @@ -64188,8 +66965,8 @@ sb_1__1__mux_2level_tapbuf_size11_2 mux_right_track_0 ( .sram ( mux_2level_tapbuf_size11_2_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_9 , SYNOPSYS_UNCONNECTED_10 , SYNOPSYS_UNCONNECTED_11 , SYNOPSYS_UNCONNECTED_12 } ) , - .out ( { aps_rename_521_ } ) , - .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_198 ) ) ; + .out ( chanx_right_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_180 ) ) ; sb_1__1__mux_2level_tapbuf_size11_3 mux_right_track_2 ( .in ( { chany_top_in[0] , chany_bottom_out[7] , chany_bottom_out[21] , right_bottom_grid_pin_37_[0] , right_bottom_grid_pin_40_[0] , @@ -64199,7 +66976,7 @@ sb_1__1__mux_2level_tapbuf_size11_3 mux_right_track_2 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 , SYNOPSYS_UNCONNECTED_15 , SYNOPSYS_UNCONNECTED_16 } ) , .out ( chanx_right_out[1] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_202 ) ) ; + .p0 ( optlc_net_180 ) ) ; sb_1__1__mux_2level_tapbuf_size11_4 mux_bottom_track_1 ( .in ( { chany_bottom_out[4] , chany_bottom_out[20] , chanx_left_out[4] , chanx_left_out[20] , chanx_right_in[25] , @@ -64210,7 +66987,7 @@ sb_1__1__mux_2level_tapbuf_size11_4 mux_bottom_track_1 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_17 , SYNOPSYS_UNCONNECTED_18 , SYNOPSYS_UNCONNECTED_19 , SYNOPSYS_UNCONNECTED_20 } ) , .out ( chany_bottom_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_204 ) ) ; + .p0 ( optlc_net_176 ) ) ; sb_1__1__mux_2level_tapbuf_size11_5 mux_bottom_track_3 ( .in ( { chany_bottom_out[7] , chany_bottom_out[21] , chanx_left_out[7] , chanx_left_out[21] , chanx_right_in[21] , @@ -64221,7 +66998,7 @@ sb_1__1__mux_2level_tapbuf_size11_5 mux_bottom_track_3 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_21 , SYNOPSYS_UNCONNECTED_22 , SYNOPSYS_UNCONNECTED_23 , SYNOPSYS_UNCONNECTED_24 } ) , .out ( chany_bottom_out[1] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_199 ) ) ; + .p0 ( optlc_net_177 ) ) ; sb_1__1__mux_2level_tapbuf_size11_6 mux_left_track_1 ( .in ( { chany_top_in[0] , chany_bottom_out[4] , chany_bottom_out[20] , chanx_left_out[4] , chanx_left_out[20] , chany_top_out[4] , @@ -64232,7 +67009,7 @@ sb_1__1__mux_2level_tapbuf_size11_6 mux_left_track_1 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_25 , SYNOPSYS_UNCONNECTED_26 , SYNOPSYS_UNCONNECTED_27 , SYNOPSYS_UNCONNECTED_28 } ) , .out ( chanx_left_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_204 ) ) ; + .p0 ( optlc_net_179 ) ) ; sb_1__1__mux_2level_tapbuf_size11 mux_left_track_3 ( .in ( { chany_bottom_out[7] , chany_bottom_out[21] , chany_top_in[29] , chanx_left_out[7] , chanx_left_out[21] , chany_bottom_in[0] , @@ -64242,7 +67019,7 @@ sb_1__1__mux_2level_tapbuf_size11 mux_left_track_3 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_29 , SYNOPSYS_UNCONNECTED_30 , SYNOPSYS_UNCONNECTED_31 , SYNOPSYS_UNCONNECTED_32 } ) , .out ( chanx_left_out[1] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_199 ) ) ; + .p0 ( optlc_net_177 ) ) ; sb_1__1__mux_2level_tapbuf_size11_mem_0 mem_top_track_0 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( mux_2level_tapbuf_size11_mem_0_ccff_tail ) , @@ -64299,7 +67076,7 @@ sb_1__1__mux_2level_tapbuf_size10_0 mux_top_track_4 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_33 , SYNOPSYS_UNCONNECTED_34 , SYNOPSYS_UNCONNECTED_35 , SYNOPSYS_UNCONNECTED_36 } ) , .out ( chany_top_out[2] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_197 ) ) ; + .p0 ( optlc_net_174 ) ) ; sb_1__1__mux_2level_tapbuf_size10_1 mux_top_track_12 ( .in ( { top_left_grid_pin_44_[0] , top_left_grid_pin_50_[0] , chanx_left_out[12] , chanx_right_in[13] , chanx_left_out[27] , @@ -64309,7 +67086,7 @@ sb_1__1__mux_2level_tapbuf_size10_1 mux_top_track_12 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_37 , SYNOPSYS_UNCONNECTED_38 , SYNOPSYS_UNCONNECTED_39 , SYNOPSYS_UNCONNECTED_40 } ) , .out ( chany_top_out[6] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_200 ) ) ; + .p0 ( optlc_net_175 ) ) ; sb_1__1__mux_2level_tapbuf_size10_2 mux_top_track_20 ( .in ( { top_left_grid_pin_45_[0] , top_left_grid_pin_51_[0] , chanx_left_out[13] , chanx_right_in[17] , chanx_left_out[28] , @@ -64319,7 +67096,7 @@ sb_1__1__mux_2level_tapbuf_size10_2 mux_top_track_20 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_41 , SYNOPSYS_UNCONNECTED_42 , SYNOPSYS_UNCONNECTED_43 , SYNOPSYS_UNCONNECTED_44 } ) , .out ( chany_top_out[10] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_203 ) ) ; + .p0 ( optlc_net_179 ) ) ; sb_1__1__mux_2level_tapbuf_size10_3 mux_right_track_4 ( .in ( { chany_top_in[1] , chany_bottom_out[8] , chany_bottom_out[23] , right_bottom_grid_pin_38_[0] , right_bottom_grid_pin_41_[0] , @@ -64329,7 +67106,7 @@ sb_1__1__mux_2level_tapbuf_size10_3 mux_right_track_4 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_45 , SYNOPSYS_UNCONNECTED_46 , SYNOPSYS_UNCONNECTED_47 , SYNOPSYS_UNCONNECTED_48 } ) , .out ( chanx_right_out[2] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_198 ) ) ; + .p0 ( optlc_net_175 ) ) ; sb_1__1__mux_2level_tapbuf_size10_4 mux_right_track_12 ( .in ( { chany_top_in[5] , chany_bottom_out[12] , chany_bottom_out[27] , right_bottom_grid_pin_36_[0] , right_bottom_grid_pin_42_[0] , @@ -64339,7 +67116,7 @@ sb_1__1__mux_2level_tapbuf_size10_4 mux_right_track_12 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_49 , SYNOPSYS_UNCONNECTED_50 , SYNOPSYS_UNCONNECTED_51 , SYNOPSYS_UNCONNECTED_52 } ) , .out ( chanx_right_out[6] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_202 ) ) ; + .p0 ( optlc_net_180 ) ) ; sb_1__1__mux_2level_tapbuf_size10_5 mux_right_track_20 ( .in ( { chany_top_in[9] , chany_bottom_out[13] , chany_bottom_out[28] , right_bottom_grid_pin_37_[0] , right_bottom_grid_pin_43_[0] , @@ -64349,7 +67126,7 @@ sb_1__1__mux_2level_tapbuf_size10_5 mux_right_track_20 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_53 , SYNOPSYS_UNCONNECTED_54 , SYNOPSYS_UNCONNECTED_55 , SYNOPSYS_UNCONNECTED_56 } ) , .out ( chanx_right_out[10] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_202 ) ) ; + .p0 ( optlc_net_180 ) ) ; sb_1__1__mux_2level_tapbuf_size10_6 mux_bottom_track_5 ( .in ( { chany_bottom_out[8] , chany_bottom_out[23] , chanx_left_out[8] , chanx_right_in[17] , chanx_left_out[23] , @@ -64359,7 +67136,7 @@ sb_1__1__mux_2level_tapbuf_size10_6 mux_bottom_track_5 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_57 , SYNOPSYS_UNCONNECTED_58 , SYNOPSYS_UNCONNECTED_59 , SYNOPSYS_UNCONNECTED_60 } ) , .out ( chany_bottom_out[2] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_201 ) ) ; + .p0 ( optlc_net_177 ) ) ; sb_1__1__mux_2level_tapbuf_size10_7 mux_bottom_track_13 ( .in ( { chany_bottom_out[12] , chany_bottom_out[27] , chanx_right_in[5] , chanx_left_out[12] , chanx_left_out[27] , @@ -64369,7 +67146,7 @@ sb_1__1__mux_2level_tapbuf_size10_7 mux_bottom_track_13 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_61 , SYNOPSYS_UNCONNECTED_62 , SYNOPSYS_UNCONNECTED_63 , SYNOPSYS_UNCONNECTED_64 } ) , .out ( chany_bottom_out[6] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_204 ) ) ; + .p0 ( optlc_net_176 ) ) ; sb_1__1__mux_2level_tapbuf_size10_8 mux_bottom_track_21 ( .in ( { chany_bottom_out[13] , chany_bottom_out[28] , chanx_right_in[4] , chanx_left_out[13] , chanx_left_out[28] , @@ -64379,7 +67156,7 @@ sb_1__1__mux_2level_tapbuf_size10_8 mux_bottom_track_21 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_65 , SYNOPSYS_UNCONNECTED_66 , SYNOPSYS_UNCONNECTED_67 , SYNOPSYS_UNCONNECTED_68 } ) , .out ( chany_bottom_out[10] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_204 ) ) ; + .p0 ( optlc_net_176 ) ) ; sb_1__1__mux_2level_tapbuf_size10_9 mux_left_track_5 ( .in ( { chany_bottom_out[8] , chany_bottom_out[23] , chany_top_in[25] , chanx_left_out[8] , chanx_left_out[23] , chany_bottom_in[1] , @@ -64389,7 +67166,7 @@ sb_1__1__mux_2level_tapbuf_size10_9 mux_left_track_5 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_69 , SYNOPSYS_UNCONNECTED_70 , SYNOPSYS_UNCONNECTED_71 , SYNOPSYS_UNCONNECTED_72 } ) , .out ( chanx_left_out[2] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_201 ) ) ; + .p0 ( optlc_net_182 ) ) ; sb_1__1__mux_2level_tapbuf_size10_10 mux_left_track_13 ( .in ( { chany_bottom_out[12] , chany_top_in[13] , chany_bottom_out[27] , chanx_left_out[12] , chanx_left_out[27] , chany_bottom_in[5] , @@ -64399,7 +67176,7 @@ sb_1__1__mux_2level_tapbuf_size10_10 mux_left_track_13 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_73 , SYNOPSYS_UNCONNECTED_74 , SYNOPSYS_UNCONNECTED_75 , SYNOPSYS_UNCONNECTED_76 } ) , .out ( chanx_left_out[6] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_204 ) ) ; + .p0 ( optlc_net_176 ) ) ; sb_1__1__mux_2level_tapbuf_size10 mux_left_track_21 ( .in ( { chany_top_in[9] , chany_bottom_out[13] , chany_bottom_out[28] , chanx_left_out[13] , chanx_left_out[28] , chany_bottom_in[9] , @@ -64409,7 +67186,7 @@ sb_1__1__mux_2level_tapbuf_size10 mux_left_track_21 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_77 , SYNOPSYS_UNCONNECTED_78 , SYNOPSYS_UNCONNECTED_79 , SYNOPSYS_UNCONNECTED_80 } ) , .out ( chanx_left_out[10] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_204 ) ) ; + .p0 ( optlc_net_176 ) ) ; sb_1__1__mux_2level_tapbuf_size10_mem_0 mem_top_track_4 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( mux_2level_tapbuf_size11_mem_1_ccff_tail ) , @@ -64492,7 +67269,7 @@ sb_1__1__mux_2level_tapbuf_size12_0 mux_top_track_6 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_81 , SYNOPSYS_UNCONNECTED_82 , SYNOPSYS_UNCONNECTED_83 , SYNOPSYS_UNCONNECTED_84 } ) , .out ( chany_top_out[3] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_203 ) ) ; + .p0 ( optlc_net_182 ) ) ; sb_1__1__mux_2level_tapbuf_size12_1 mux_top_track_10 ( .in ( { top_left_grid_pin_45_[0] , top_left_grid_pin_47_[0] , top_left_grid_pin_49_[0] , top_left_grid_pin_51_[0] , @@ -64503,7 +67280,7 @@ sb_1__1__mux_2level_tapbuf_size12_1 mux_top_track_10 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_85 , SYNOPSYS_UNCONNECTED_86 , SYNOPSYS_UNCONNECTED_87 , SYNOPSYS_UNCONNECTED_88 } ) , .out ( chany_top_out[5] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_201 ) ) ; + .p0 ( optlc_net_179 ) ) ; sb_1__1__mux_2level_tapbuf_size12_2 mux_right_track_6 ( .in ( { chany_top_in[2] , chany_bottom_out[9] , chany_bottom_out[24] , right_bottom_grid_pin_36_[0] , right_bottom_grid_pin_38_[0] , @@ -64513,8 +67290,8 @@ sb_1__1__mux_2level_tapbuf_size12_2 mux_right_track_6 ( .sram ( mux_2level_tapbuf_size12_2_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_89 , SYNOPSYS_UNCONNECTED_90 , SYNOPSYS_UNCONNECTED_91 , SYNOPSYS_UNCONNECTED_92 } ) , - .out ( { aps_rename_522_ } ) , - .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_202 ) ) ; + .out ( chanx_right_out[3] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_180 ) ) ; sb_1__1__mux_2level_tapbuf_size12_3 mux_right_track_10 ( .in ( { chany_top_in[4] , chany_bottom_out[11] , chany_bottom_out[25] , right_bottom_grid_pin_37_[0] , right_bottom_grid_pin_39_[0] , @@ -64525,7 +67302,7 @@ sb_1__1__mux_2level_tapbuf_size12_3 mux_right_track_10 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_93 , SYNOPSYS_UNCONNECTED_94 , SYNOPSYS_UNCONNECTED_95 , SYNOPSYS_UNCONNECTED_96 } ) , .out ( chanx_right_out[5] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_202 ) ) ; + .p0 ( optlc_net_180 ) ) ; sb_1__1__mux_2level_tapbuf_size12_4 mux_bottom_track_7 ( .in ( { chany_bottom_out[9] , chany_bottom_out[24] , chanx_left_out[9] , chanx_right_in[13] , chanx_left_out[24] , @@ -64536,7 +67313,7 @@ sb_1__1__mux_2level_tapbuf_size12_4 mux_bottom_track_7 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_97 , SYNOPSYS_UNCONNECTED_98 , SYNOPSYS_UNCONNECTED_99 , SYNOPSYS_UNCONNECTED_100 } ) , .out ( chany_bottom_out[3] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_199 ) ) ; + .p0 ( optlc_net_177 ) ) ; sb_1__1__mux_2level_tapbuf_size12_5 mux_bottom_track_11 ( .in ( { chany_bottom_out[11] , chany_bottom_out[25] , chanx_right_in[9] , chanx_left_out[11] , chanx_left_out[25] , @@ -64547,7 +67324,7 @@ sb_1__1__mux_2level_tapbuf_size12_5 mux_bottom_track_11 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_101 , SYNOPSYS_UNCONNECTED_102 , SYNOPSYS_UNCONNECTED_103 , SYNOPSYS_UNCONNECTED_104 } ) , .out ( chany_bottom_out[5] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_199 ) ) ; + .p0 ( optlc_net_176 ) ) ; sb_1__1__mux_2level_tapbuf_size12_6 mux_left_track_7 ( .in ( { chany_bottom_out[9] , chany_top_in[21] , chany_bottom_out[24] , chanx_left_out[9] , chanx_left_out[24] , chany_bottom_in[2] , @@ -64558,7 +67335,7 @@ sb_1__1__mux_2level_tapbuf_size12_6 mux_left_track_7 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_105 , SYNOPSYS_UNCONNECTED_106 , SYNOPSYS_UNCONNECTED_107 , SYNOPSYS_UNCONNECTED_108 } ) , .out ( chanx_left_out[3] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_199 ) ) ; + .p0 ( optlc_net_182 ) ) ; sb_1__1__mux_2level_tapbuf_size12 mux_left_track_11 ( .in ( { chany_bottom_out[11] , chany_top_in[17] , chany_bottom_out[25] , chanx_left_out[11] , chanx_left_out[25] , chany_bottom_in[4] , @@ -64569,7 +67346,7 @@ sb_1__1__mux_2level_tapbuf_size12 mux_left_track_11 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_109 , SYNOPSYS_UNCONNECTED_110 , SYNOPSYS_UNCONNECTED_111 , SYNOPSYS_UNCONNECTED_112 } ) , .out ( chanx_left_out[5] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_204 ) ) ; + .p0 ( optlc_net_177 ) ) ; sb_1__1__mux_2level_tapbuf_size12_mem_0 mem_top_track_6 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( mux_2level_tapbuf_size10_mem_0_ccff_tail ) , @@ -64627,7 +67404,7 @@ sb_1__1__mux_2level_tapbuf_size9_0 mux_top_track_28 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_113 , SYNOPSYS_UNCONNECTED_114 , SYNOPSYS_UNCONNECTED_115 , SYNOPSYS_UNCONNECTED_116 } ) , .out ( chany_top_out[14] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_198 ) ) ; + .p0 ( optlc_net_178 ) ) ; sb_1__1__mux_2level_tapbuf_size9_1 mux_right_track_28 ( .in ( { chany_top_in[13] , chany_bottom_out[15] , chany_bottom_out[29] , right_bottom_grid_pin_38_[0] , chany_bottom_in[2] , @@ -64637,7 +67414,7 @@ sb_1__1__mux_2level_tapbuf_size9_1 mux_right_track_28 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_117 , SYNOPSYS_UNCONNECTED_118 , SYNOPSYS_UNCONNECTED_119 , SYNOPSYS_UNCONNECTED_120 } ) , .out ( chanx_right_out[14] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_202 ) ) ; + .p0 ( optlc_net_178 ) ) ; sb_1__1__mux_2level_tapbuf_size9_2 mux_bottom_track_29 ( .in ( { chany_bottom_out[15] , chany_bottom_out[29] , chanx_right_in[2] , chanx_left_out[15] , chanx_left_out[29] , @@ -64647,7 +67424,7 @@ sb_1__1__mux_2level_tapbuf_size9_2 mux_bottom_track_29 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_121 , SYNOPSYS_UNCONNECTED_122 , SYNOPSYS_UNCONNECTED_123 , SYNOPSYS_UNCONNECTED_124 } ) , .out ( chany_bottom_out[14] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_202 ) ) ; + .p0 ( optlc_net_180 ) ) ; sb_1__1__mux_2level_tapbuf_size9 mux_left_track_29 ( .in ( { chany_top_in[5] , chany_bottom_out[15] , chany_bottom_out[29] , chanx_left_out[15] , chanx_left_out[29] , chany_bottom_in[13] , @@ -64656,7 +67433,7 @@ sb_1__1__mux_2level_tapbuf_size9 mux_left_track_29 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_125 , SYNOPSYS_UNCONNECTED_126 , SYNOPSYS_UNCONNECTED_127 , SYNOPSYS_UNCONNECTED_128 } ) , .out ( chanx_left_out[14] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_204 ) ) ; + .p0 ( optlc_net_179 ) ) ; sb_1__1__mux_2level_tapbuf_size9_mem_0 mem_top_track_28 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( mux_2level_tapbuf_size10_mem_2_ccff_tail ) , @@ -64689,7 +67466,7 @@ sb_1__1__mux_2level_tapbuf_size6_0 mux_top_track_36 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_129 , SYNOPSYS_UNCONNECTED_130 , SYNOPSYS_UNCONNECTED_131 , SYNOPSYS_UNCONNECTED_132 } ) , .out ( chany_top_out[18] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_200 ) ) ; + .p0 ( optlc_net_175 ) ) ; sb_1__1__mux_2level_tapbuf_size6_1 mux_top_track_44 ( .in ( { top_left_grid_pin_48_[0] , chanx_left_out[17] , chanx_right_in[29] , chany_top_out[17] , chanx_left_in[2] , @@ -64698,7 +67475,7 @@ sb_1__1__mux_2level_tapbuf_size6_1 mux_top_track_44 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_133 , SYNOPSYS_UNCONNECTED_134 , SYNOPSYS_UNCONNECTED_135 , SYNOPSYS_UNCONNECTED_136 } ) , .out ( chany_top_out[22] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_203 ) ) ; + .p0 ( optlc_net_181 ) ) ; sb_1__1__mux_2level_tapbuf_size6_2 mux_top_track_52 ( .in ( { top_left_grid_pin_49_[0] , chanx_right_in[0] , chanx_left_out[19] , chany_top_out[19] , chanx_left_in[1] , @@ -64707,7 +67484,7 @@ sb_1__1__mux_2level_tapbuf_size6_2 mux_top_track_52 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_137 , SYNOPSYS_UNCONNECTED_138 , SYNOPSYS_UNCONNECTED_139 , SYNOPSYS_UNCONNECTED_140 } ) , .out ( chany_top_out[26] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_203 ) ) ; + .p0 ( optlc_net_181 ) ) ; sb_1__1__mux_2level_tapbuf_size6_3 mux_right_track_36 ( .in ( { chany_bottom_out[16] , chany_top_in[17] , right_bottom_grid_pin_39_[0] , chany_bottom_in[1] , @@ -64716,7 +67493,7 @@ sb_1__1__mux_2level_tapbuf_size6_3 mux_right_track_36 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_141 , SYNOPSYS_UNCONNECTED_142 , SYNOPSYS_UNCONNECTED_143 , SYNOPSYS_UNCONNECTED_144 } ) , .out ( chanx_right_out[18] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_198 ) ) ; + .p0 ( optlc_net_178 ) ) ; sb_1__1__mux_2level_tapbuf_size6_4 mux_right_track_44 ( .in ( { chany_bottom_out[17] , chany_top_in[21] , right_bottom_grid_pin_40_[0] , chany_bottom_in[0] , @@ -64725,7 +67502,7 @@ sb_1__1__mux_2level_tapbuf_size6_4 mux_right_track_44 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_145 , SYNOPSYS_UNCONNECTED_146 , SYNOPSYS_UNCONNECTED_147 , SYNOPSYS_UNCONNECTED_148 } ) , .out ( chanx_right_out[22] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_203 ) ) ; + .p0 ( optlc_net_175 ) ) ; sb_1__1__mux_2level_tapbuf_size6_5 mux_right_track_52 ( .in ( { chany_bottom_out[19] , chany_top_in[25] , right_bottom_grid_pin_41_[0] , chany_top_out[19] , @@ -64734,7 +67511,7 @@ sb_1__1__mux_2level_tapbuf_size6_5 mux_right_track_52 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_149 , SYNOPSYS_UNCONNECTED_150 , SYNOPSYS_UNCONNECTED_151 , SYNOPSYS_UNCONNECTED_152 } ) , .out ( chanx_right_out[26] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_200 ) ) ; + .p0 ( optlc_net_178 ) ) ; sb_1__1__mux_2level_tapbuf_size6_6 mux_bottom_track_37 ( .in ( { chany_bottom_out[16] , chanx_right_in[1] , chanx_left_out[16] , bottom_left_grid_pin_47_[0] , chanx_right_out[16] , @@ -64743,7 +67520,7 @@ sb_1__1__mux_2level_tapbuf_size6_6 mux_bottom_track_37 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_153 , SYNOPSYS_UNCONNECTED_154 , SYNOPSYS_UNCONNECTED_155 , SYNOPSYS_UNCONNECTED_156 } ) , .out ( chany_bottom_out[18] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_198 ) ) ; + .p0 ( optlc_net_180 ) ) ; sb_1__1__mux_2level_tapbuf_size6_7 mux_bottom_track_45 ( .in ( { chany_bottom_out[17] , chanx_right_in[0] , chanx_left_out[17] , bottom_left_grid_pin_48_[0] , chanx_right_out[17] , @@ -64752,7 +67529,7 @@ sb_1__1__mux_2level_tapbuf_size6_7 mux_bottom_track_45 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_157 , SYNOPSYS_UNCONNECTED_158 , SYNOPSYS_UNCONNECTED_159 , SYNOPSYS_UNCONNECTED_160 } ) , .out ( chany_bottom_out[22] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_205 ) ) ; + .p0 ( optlc_net_176 ) ) ; sb_1__1__mux_2level_tapbuf_size6_8 mux_bottom_track_53 ( .in ( { chany_bottom_out[19] , chanx_left_out[19] , chanx_right_in[29] , bottom_left_grid_pin_49_[0] , chanx_left_in[0] , chanx_right_out[19] } ) , @@ -64760,7 +67537,7 @@ sb_1__1__mux_2level_tapbuf_size6_8 mux_bottom_track_53 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_161 , SYNOPSYS_UNCONNECTED_162 , SYNOPSYS_UNCONNECTED_163 , SYNOPSYS_UNCONNECTED_164 } ) , .out ( chany_bottom_out[26] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_205 ) ) ; + .p0 ( optlc_net_176 ) ) ; sb_1__1__mux_2level_tapbuf_size6_9 mux_left_track_37 ( .in ( { chany_top_in[4] , chany_bottom_out[16] , chanx_left_out[16] , chany_top_out[16] , chany_bottom_in[17] , @@ -64769,7 +67546,7 @@ sb_1__1__mux_2level_tapbuf_size6_9 mux_left_track_37 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_165 , SYNOPSYS_UNCONNECTED_166 , SYNOPSYS_UNCONNECTED_167 , SYNOPSYS_UNCONNECTED_168 } ) , .out ( chanx_left_out[18] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_200 ) ) ; + .p0 ( optlc_net_181 ) ) ; sb_1__1__mux_2level_tapbuf_size6_10 mux_left_track_45 ( .in ( { chany_top_in[2] , chany_bottom_out[17] , chanx_left_out[17] , chany_top_out[17] , chany_bottom_in[21] , @@ -64778,7 +67555,7 @@ sb_1__1__mux_2level_tapbuf_size6_10 mux_left_track_45 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_169 , SYNOPSYS_UNCONNECTED_170 , SYNOPSYS_UNCONNECTED_171 , SYNOPSYS_UNCONNECTED_172 } ) , .out ( chanx_left_out[22] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_197 ) ) ; + .p0 ( optlc_net_174 ) ) ; sb_1__1__mux_2level_tapbuf_size6 mux_left_track_53 ( .in ( { chany_top_in[1] , chany_bottom_out[19] , chanx_left_out[19] , chany_top_out[19] , chany_bottom_in[25] , @@ -64787,7 +67564,7 @@ sb_1__1__mux_2level_tapbuf_size6 mux_left_track_53 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_173 , SYNOPSYS_UNCONNECTED_174 , SYNOPSYS_UNCONNECTED_175 , SYNOPSYS_UNCONNECTED_176 } ) , .out ( chanx_left_out[26] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_197 ) ) ; + .p0 ( optlc_net_174 ) ) ; sb_1__1__mux_2level_tapbuf_size6_mem_0 mem_top_track_36 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( mux_2level_tapbuf_size9_mem_0_ccff_tail ) , @@ -64864,14 +67641,14 @@ sky130_fd_sc_hd__buf_4 Test_en_N_FTB01 ( .A ( Test_en_S_in ) , sky130_fd_sc_hd__buf_8 pReset_FTB00 ( .A ( pReset_E_in ) , .X ( pReset[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_1 pReset_N_FTB01 ( .A ( pReset_E_in ) , - .X ( aps_rename_523_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__bufbuf_16 pReset_W_FTB01 ( .A ( pReset_E_in ) , - .X ( pReset_W_out ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .X ( aps_rename_514_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 pReset_W_FTB01 ( .A ( pReset_E_in ) , + .X ( aps_rename_515_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_4 pReset_E_FTB01 ( .A ( pReset_E_in ) , .X ( pReset_E_out ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_4 Reset_N_FTB01 ( .A ( Reset_S_in ) , .X ( Reset_N_out ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_16 prog_clk_0_FTB00 ( .A ( prog_clk_0_N_in ) , +sky130_fd_sc_hd__buf_6 prog_clk_0_FTB00 ( .A ( prog_clk_0_N_in ) , .X ( prog_clk[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_8 FTB_69__68 ( .A ( chany_top_in[3] ) , .X ( chany_bottom_out[4] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -65025,32 +67802,32 @@ sky130_fd_sc_hd__buf_8 FTB_143__142 ( .A ( chanx_left_in[27] ) , .X ( chanx_right_out[28] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_8 FTB_144__143 ( .A ( chanx_left_in[28] ) , .X ( chanx_right_out[29] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_191 ( .A ( BUF_net_192 ) , .Y ( pReset_N_out ) , +sky130_fd_sc_hd__inv_8 BINV_R_166 ( .A ( BUF_net_167 ) , .Y ( pReset_N_out ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_192 ( .A ( aps_rename_523_ ) , - .Y ( BUF_net_192 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_199 ( .LO ( SYNOPSYS_UNCONNECTED_177 ) , - .HI ( optlc_net_197 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_201 ( .LO ( SYNOPSYS_UNCONNECTED_178 ) , - .HI ( optlc_net_198 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_204 ( .LO ( SYNOPSYS_UNCONNECTED_179 ) , - .HI ( optlc_net_199 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_206 ( .LO ( SYNOPSYS_UNCONNECTED_180 ) , - .HI ( optlc_net_200 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_208 ( .LO ( SYNOPSYS_UNCONNECTED_181 ) , - .HI ( optlc_net_201 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_210 ( .LO ( SYNOPSYS_UNCONNECTED_182 ) , - .HI ( optlc_net_202 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_212 ( .LO ( SYNOPSYS_UNCONNECTED_183 ) , - .HI ( optlc_net_203 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_214 ( .LO ( SYNOPSYS_UNCONNECTED_184 ) , - .HI ( optlc_net_204 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_216 ( .LO ( SYNOPSYS_UNCONNECTED_185 ) , - .HI ( optlc_net_205 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_6 ZBUF_6_f_inst_217 ( .A ( aps_rename_522_ ) , - .X ( chanx_right_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_6 ZBUF_6_f_inst_218 ( .A ( aps_rename_521_ ) , - .X ( chanx_right_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_167 ( .A ( aps_rename_514_ ) , + .Y ( BUF_net_167 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_168 ( .A ( BUF_net_169 ) , .Y ( pReset_W_out ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_169 ( .A ( aps_rename_515_ ) , + .Y ( BUF_net_169 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_176 ( .LO ( SYNOPSYS_UNCONNECTED_177 ) , + .HI ( optlc_net_174 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_178 ( .LO ( SYNOPSYS_UNCONNECTED_178 ) , + .HI ( optlc_net_175 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_180 ( .LO ( SYNOPSYS_UNCONNECTED_179 ) , + .HI ( optlc_net_176 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_182 ( .LO ( SYNOPSYS_UNCONNECTED_180 ) , + .HI ( optlc_net_177 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_184 ( .LO ( SYNOPSYS_UNCONNECTED_181 ) , + .HI ( optlc_net_178 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_186 ( .LO ( SYNOPSYS_UNCONNECTED_182 ) , + .HI ( optlc_net_179 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_188 ( .LO ( SYNOPSYS_UNCONNECTED_183 ) , + .HI ( optlc_net_180 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_190 ( .LO ( SYNOPSYS_UNCONNECTED_184 ) , + .HI ( optlc_net_181 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_192 ( .LO ( SYNOPSYS_UNCONNECTED_185 ) , + .HI ( optlc_net_182 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -65154,15 +67931,20 @@ input VDD ; input VSS ; input p0 ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -65175,15 +67957,20 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -65196,15 +67983,20 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -65290,7 +68082,7 @@ wire [0:0] mux_2level_tapbuf_basis_input4_mem4_2_out ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__bufbuf_16 sky130_fd_sc_hd__buf_4_0_ ( +sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_4_0_ ( .A ( mux_2level_tapbuf_basis_input4_mem4_2_out[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sb_1__0__local_encoder2to4_6 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , @@ -65330,15 +68122,20 @@ input VDD ; input VSS ; input p0 ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -65351,15 +68148,20 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -65372,15 +68174,20 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -65467,8 +68274,8 @@ supply1 VDD ; supply0 VSS ; sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_4_0_ ( - .A ( mux_2level_tapbuf_basis_input4_mem4_2_out[0] ) , .X ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .A ( mux_2level_tapbuf_basis_input4_mem4_2_out[0] ) , + .X ( aps_rename_505_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sb_1__0__local_encoder2to4_4 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , .data ( local_encoder2to4_0_data ) , .data_inv ( local_encoder2to4_0_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; @@ -65493,6 +68300,10 @@ sb_1__0__mux_2level_tapbuf_basis_input4_mem4_8 mux_l2_in_0_ ( .mem_inv ( local_encoder2to4_1_data_inv ) , .out ( mux_2level_tapbuf_basis_input4_mem4_2_out ) , .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_213 ( .A ( BUF_net_214 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_214 ( .A ( aps_rename_505_ ) , + .Y ( BUF_net_214 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -65506,15 +68317,20 @@ input VDD ; input VSS ; input p0 ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -65527,15 +68343,20 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -65548,15 +68369,20 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -65642,7 +68468,7 @@ wire [0:0] mux_2level_tapbuf_basis_input4_mem4_2_out ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__bufbuf_16 sky130_fd_sc_hd__buf_4_0_ ( +sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_4_0_ ( .A ( mux_2level_tapbuf_basis_input4_mem4_2_out[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sb_1__0__local_encoder2to4_2 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , @@ -65711,12 +68537,15 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -65730,15 +68559,20 @@ input VDD ; input VSS ; input p0 ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -65751,15 +68585,20 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -65772,15 +68611,20 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -66002,13 +68846,16 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -66022,13 +68869,16 @@ input VDD ; input VSS ; input p0 ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -66041,13 +68891,16 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -66060,13 +68913,16 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -66186,13 +69042,16 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -66206,13 +69065,16 @@ input VDD ; input VSS ; input p0 ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -66225,13 +69087,16 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -66244,13 +69109,16 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -66372,13 +69240,16 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -66392,13 +69263,16 @@ input VDD ; input VSS ; input p0 ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -66411,13 +69285,16 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -66430,13 +69307,16 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -66511,9 +69391,6 @@ wire [0:0] mux_2level_tapbuf_basis_input3_mem3_3_out ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( mux_2level_tapbuf_basis_input3_mem3_3_out[0] ) , .X ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; sb_1__0__local_encoder2to3_50 local_encoder2to3_0_ ( .addr ( sram[0:1] ) , .data ( local_encoder2to3_0_data ) , .data_inv ( local_encoder2to3_0_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; @@ -66544,6 +69421,11 @@ sb_1__0__mux_2level_tapbuf_basis_input3_mem3_66 mux_l2_in_0_ ( .mem_inv ( local_encoder2to3_1_data_inv ) , .out ( mux_2level_tapbuf_basis_input3_mem3_3_out ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_211 ( .A ( BUF_net_212 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_212 ( + .A ( mux_2level_tapbuf_basis_input3_mem3_3_out[0] ) , .Y ( BUF_net_212 ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -66863,9 +69745,6 @@ wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; sb_1__0__mux_2level_tapbuf_basis_input2_mem1_35 mux_l1_in_0_ ( .in ( in ) , .mem ( sram[0] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) , @@ -66878,6 +69757,9 @@ sb_1__0__mux_2level_tapbuf_basis_input2_mem1 mux_l2_in_0_ ( .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_192 ( + .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -66894,7 +69776,7 @@ input p0 ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__mux2_2 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , +sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -66945,8 +69827,10 @@ sb_1__0__mux_2level_tapbuf_basis_input2_mem1_34 mux_l2_in_0_ ( .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_192 ( - .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) , +sky130_fd_sc_hd__inv_8 BINV_R_190 ( .A ( BUF_net_191 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_191 ( + .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_191 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -67015,10 +69899,10 @@ sb_1__0__mux_2level_tapbuf_basis_input2_mem1_32 mux_l2_in_0_ ( .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_190 ( .A ( BUF_net_191 ) , .Y ( out[0] ) , +sky130_fd_sc_hd__inv_8 BINV_R_188 ( .A ( BUF_net_189 ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_191 ( - .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_191 ) , +sky130_fd_sc_hd__inv_1 BINV_R_189 ( + .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_189 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -67087,10 +69971,10 @@ sb_1__0__mux_2level_tapbuf_basis_input2_mem1_30 mux_l2_in_0_ ( .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_188 ( .A ( BUF_net_189 ) , .Y ( out[0] ) , +sky130_fd_sc_hd__inv_8 BINV_R_186 ( .A ( BUF_net_187 ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_189 ( - .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_189 ) , +sky130_fd_sc_hd__inv_1 BINV_R_187 ( + .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_187 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -67159,10 +70043,10 @@ sb_1__0__mux_2level_tapbuf_basis_input2_mem1_28 mux_l2_in_0_ ( .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_186 ( .A ( BUF_net_187 ) , .Y ( out[0] ) , +sky130_fd_sc_hd__inv_8 BINV_R_184 ( .A ( BUF_net_185 ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_187 ( - .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_187 ) , +sky130_fd_sc_hd__inv_1 BINV_R_185 ( + .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_185 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -67219,9 +70103,6 @@ wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; sb_1__0__mux_2level_tapbuf_basis_input2_mem1_25 mux_l1_in_0_ ( .in ( in ) , .mem ( sram[0] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) , @@ -67234,6 +70115,11 @@ sb_1__0__mux_2level_tapbuf_basis_input2_mem1_26 mux_l2_in_0_ ( .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_182 ( .A ( BUF_net_183 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_183 ( + .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_183 ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -67301,10 +70187,10 @@ sb_1__0__mux_2level_tapbuf_basis_input2_mem1_24 mux_l2_in_0_ ( .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_184 ( .A ( BUF_net_185 ) , .Y ( out[0] ) , +sky130_fd_sc_hd__inv_8 BINV_R_180 ( .A ( BUF_net_181 ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_185 ( - .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_185 ) , +sky130_fd_sc_hd__inv_1 BINV_R_181 ( + .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_181 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -67392,7 +70278,7 @@ input p0 ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__mux2_2 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , +sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -67431,6 +70317,9 @@ wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ; supply1 VDD ; supply0 VSS ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; sb_1__0__mux_2level_tapbuf_basis_input2_mem1_19 mux_l1_in_0_ ( .in ( in ) , .mem ( sram[0] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) , @@ -67443,9 +70332,6 @@ sb_1__0__mux_2level_tapbuf_basis_input2_mem1_20 mux_l2_in_0_ ( .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_183 ( - .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -67583,10 +70469,10 @@ sb_1__0__mux_2level_tapbuf_basis_input2_mem1_16 mux_l2_in_0_ ( .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_181 ( .A ( BUF_net_182 ) , .Y ( out[0] ) , +sky130_fd_sc_hd__inv_8 BINV_R_178 ( .A ( BUF_net_179 ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_182 ( - .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_182 ) , +sky130_fd_sc_hd__inv_1 BINV_R_179 ( + .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_179 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -67800,10 +70686,10 @@ sb_1__0__mux_2level_tapbuf_basis_input2_mem1_14 mux_l2_in_0_ ( .mem_inv ( { SYNOPSYS_UNCONNECTED_4 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_2_out ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_179 ( .A ( BUF_net_180 ) , .Y ( out[0] ) , +sky130_fd_sc_hd__inv_8 BINV_R_176 ( .A ( BUF_net_177 ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_180 ( - .A ( mux_2level_tapbuf_basis_input2_mem1_2_out[0] ) , .Y ( BUF_net_180 ) , +sky130_fd_sc_hd__inv_1 BINV_R_177 ( + .A ( mux_2level_tapbuf_basis_input2_mem1_2_out[0] ) , .Y ( BUF_net_177 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -67820,7 +70706,7 @@ input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__mux2_2 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) , +sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -67879,9 +70765,6 @@ wire [0:0] mux_2level_tapbuf_basis_input2_mem1_2_out ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( mux_2level_tapbuf_basis_input2_mem1_2_out[0] ) , .X ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; sb_1__0__mux_2level_tapbuf_basis_input2_mem1_9 mux_l1_in_0_ ( .in ( in[0:1] ) , .mem ( sram[0] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) , @@ -67900,6 +70783,11 @@ sb_1__0__mux_2level_tapbuf_basis_input2_mem1_11 mux_l2_in_0_ ( .mem_inv ( { SYNOPSYS_UNCONNECTED_4 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_2_out ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_174 ( .A ( BUF_net_175 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_175 ( + .A ( mux_2level_tapbuf_basis_input2_mem1_2_out[0] ) , .Y ( BUF_net_175 ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -67992,10 +70880,10 @@ sb_1__0__mux_2level_tapbuf_basis_input2_mem1_8 mux_l2_in_0_ ( .mem_inv ( { SYNOPSYS_UNCONNECTED_4 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_2_out ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_177 ( .A ( BUF_net_178 ) , .Y ( out[0] ) , +sky130_fd_sc_hd__inv_8 BINV_R_172 ( .A ( BUF_net_173 ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_178 ( - .A ( mux_2level_tapbuf_basis_input2_mem1_2_out[0] ) , .Y ( BUF_net_178 ) , +sky130_fd_sc_hd__inv_1 BINV_R_173 ( + .A ( mux_2level_tapbuf_basis_input2_mem1_2_out[0] ) , .Y ( BUF_net_173 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -68089,10 +70977,10 @@ sb_1__0__mux_2level_tapbuf_basis_input2_mem1_5 mux_l2_in_0_ ( .mem_inv ( { SYNOPSYS_UNCONNECTED_4 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_2_out ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_175 ( .A ( BUF_net_176 ) , .Y ( out[0] ) , +sky130_fd_sc_hd__inv_8 BINV_R_170 ( .A ( BUF_net_171 ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_176 ( - .A ( mux_2level_tapbuf_basis_input2_mem1_2_out[0] ) , .Y ( BUF_net_176 ) , +sky130_fd_sc_hd__inv_1 BINV_R_171 ( + .A ( mux_2level_tapbuf_basis_input2_mem1_2_out[0] ) , .Y ( BUF_net_171 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -68168,6 +71056,9 @@ wire [0:0] mux_2level_tapbuf_basis_input2_mem1_2_out ; supply1 VDD ; supply0 VSS ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( mux_2level_tapbuf_basis_input2_mem1_2_out[0] ) , .X ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; sb_1__0__mux_2level_tapbuf_basis_input2_mem1_0 mux_l1_in_0_ ( .in ( in[0:1] ) , .mem ( sram[0] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) , @@ -68186,11 +71077,6 @@ sb_1__0__mux_2level_tapbuf_basis_input2_mem1_2 mux_l2_in_0_ ( .mem_inv ( { SYNOPSYS_UNCONNECTED_4 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_2_out ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_173 ( .A ( BUF_net_174 ) , .Y ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_174 ( - .A ( mux_2level_tapbuf_basis_input2_mem1_2_out[0] ) , .Y ( BUF_net_174 ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -68384,13 +71270,16 @@ input VDD ; input VSS ; input p0 ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -68403,13 +71292,16 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -68500,8 +71392,10 @@ sb_1__0__mux_2level_tapbuf_basis_input3_mem3_62 mux_l2_in_0_ ( .mem_inv ( local_encoder2to3_1_data_inv ) , .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_172 ( - .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .X ( out[0] ) , +sky130_fd_sc_hd__inv_8 BINV_R_209 ( .A ( BUF_net_210 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_210 ( + .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_210 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -68516,13 +71410,16 @@ input VDD ; input VSS ; input p0 ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -68535,13 +71432,16 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -68632,8 +71532,10 @@ sb_1__0__mux_2level_tapbuf_basis_input3_mem3_60 mux_l2_in_0_ ( .mem_inv ( local_encoder2to3_1_data_inv ) , .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_171 ( - .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .X ( out[0] ) , +sky130_fd_sc_hd__inv_8 BINV_R_168 ( .A ( BUF_net_169 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_169 ( + .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_169 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -68648,13 +71550,16 @@ input VDD ; input VSS ; input p0 ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -68667,13 +71572,16 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -68764,10 +71672,8 @@ sb_1__0__mux_2level_tapbuf_basis_input3_mem3_58 mux_l2_in_0_ ( .mem_inv ( local_encoder2to3_1_data_inv ) , .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_169 ( .A ( BUF_net_170 ) , .Y ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_170 ( - .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_170 ) , +sky130_fd_sc_hd__buf_6 BUFT_RR_167 ( + .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -68782,13 +71688,16 @@ input VDD ; input VSS ; input p0 ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -68801,13 +71710,16 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -68898,10 +71810,10 @@ sb_1__0__mux_2level_tapbuf_basis_input3_mem3_56 mux_l2_in_0_ ( .mem_inv ( local_encoder2to3_1_data_inv ) , .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_167 ( .A ( BUF_net_168 ) , .Y ( out[0] ) , +sky130_fd_sc_hd__inv_8 BINV_R_165 ( .A ( BUF_net_166 ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_168 ( - .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_168 ) , +sky130_fd_sc_hd__inv_1 BINV_R_166 ( + .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_166 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -68916,13 +71828,16 @@ input VDD ; input VSS ; input p0 ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -68935,13 +71850,16 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -69032,10 +71950,8 @@ sb_1__0__mux_2level_tapbuf_basis_input3_mem3_54 mux_l2_in_0_ ( .mem_inv ( local_encoder2to3_1_data_inv ) , .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_165 ( .A ( BUF_net_166 ) , .Y ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_166 ( - .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_166 ) , +sky130_fd_sc_hd__buf_6 BUFT_RR_164 ( + .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -69050,13 +71966,16 @@ input VDD ; input VSS ; input p0 ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -69069,13 +71988,16 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -69148,6 +72070,9 @@ wire [0:0] mux_2level_tapbuf_basis_input3_mem3_1_out ; supply1 VDD ; supply0 VSS ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .X ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; sb_1__0__local_encoder2to3_38 local_encoder2to3_0_ ( .addr ( sram[0:1] ) , .data ( local_encoder2to3_0_data ) , .data_inv ( local_encoder2to3_0_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; @@ -69166,11 +72091,6 @@ sb_1__0__mux_2level_tapbuf_basis_input3_mem3_52 mux_l2_in_0_ ( .mem_inv ( local_encoder2to3_1_data_inv ) , .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_163 ( .A ( BUF_net_164 ) , .Y ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_164 ( - .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_164 ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -69363,12 +72283,15 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -69382,13 +72305,16 @@ input VDD ; input VSS ; input p0 ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -69401,13 +72327,16 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -69505,10 +72434,10 @@ sb_1__0__mux_2level_tapbuf_basis_input2_mem2_15 mux_l1_in_1_ ( .mem_inv ( local_encoder2to3_0_data_inv[0:1] ) , .out ( mux_2level_tapbuf_basis_input2_mem2_0_out ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_161 ( .A ( BUF_net_162 ) , .Y ( out[0] ) , +sky130_fd_sc_hd__inv_8 BINV_R_162 ( .A ( BUF_net_163 ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_162 ( - .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_162 ) , +sky130_fd_sc_hd__inv_1 BINV_R_163 ( + .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_163 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -69522,12 +72451,15 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -69541,13 +72473,16 @@ input VDD ; input VSS ; input p0 ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -69560,13 +72495,16 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -69664,10 +72602,10 @@ sb_1__0__mux_2level_tapbuf_basis_input2_mem2_14 mux_l1_in_1_ ( .mem_inv ( local_encoder2to3_0_data_inv[0:1] ) , .out ( mux_2level_tapbuf_basis_input2_mem2_0_out ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_159 ( .A ( BUF_net_160 ) , .Y ( out[0] ) , +sky130_fd_sc_hd__inv_8 BINV_R_160 ( .A ( BUF_net_161 ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_160 ( - .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_160 ) , +sky130_fd_sc_hd__inv_1 BINV_R_161 ( + .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_161 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -69681,12 +72619,15 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -69700,13 +72641,16 @@ input VDD ; input VSS ; input p0 ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -69719,13 +72663,16 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -69823,10 +72770,10 @@ sb_1__0__mux_2level_tapbuf_basis_input2_mem2_13 mux_l1_in_1_ ( .mem_inv ( local_encoder2to3_0_data_inv[0:1] ) , .out ( mux_2level_tapbuf_basis_input2_mem2_0_out ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_157 ( .A ( BUF_net_158 ) , .Y ( out[0] ) , +sky130_fd_sc_hd__inv_8 BINV_R_158 ( .A ( BUF_net_159 ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_158 ( - .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_158 ) , +sky130_fd_sc_hd__inv_1 BINV_R_159 ( + .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_159 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -69840,12 +72787,15 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -69859,13 +72809,16 @@ input VDD ; input VSS ; input p0 ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -69878,13 +72831,16 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -69982,10 +72938,10 @@ sb_1__0__mux_2level_tapbuf_basis_input2_mem2_12 mux_l1_in_1_ ( .mem_inv ( local_encoder2to3_0_data_inv[0:1] ) , .out ( mux_2level_tapbuf_basis_input2_mem2_0_out ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_205 ( .A ( BUF_net_206 ) , .Y ( out[0] ) , +sky130_fd_sc_hd__inv_8 BINV_R_156 ( .A ( BUF_net_157 ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_206 ( - .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_206 ) , +sky130_fd_sc_hd__inv_1 BINV_R_157 ( + .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_157 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -69999,12 +72955,15 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -70018,13 +72977,16 @@ input VDD ; input VSS ; input p0 ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -70037,13 +72999,16 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -70117,6 +73082,9 @@ wire [0:0] mux_2level_tapbuf_basis_input3_mem3_1_out ; supply1 VDD ; supply0 VSS ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .X ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; sb_1__0__local_encoder2to3_28 local_encoder2to3_0_ ( .addr ( sram[0:1] ) , .data ( local_encoder2to3_0_data ) , .data_inv ( local_encoder2to3_0_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; @@ -70141,11 +73109,6 @@ sb_1__0__mux_2level_tapbuf_basis_input2_mem2_11 mux_l1_in_1_ ( .mem_inv ( local_encoder2to3_0_data_inv[0:1] ) , .out ( mux_2level_tapbuf_basis_input2_mem2_0_out ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_155 ( .A ( BUF_net_156 ) , .Y ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_156 ( - .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_156 ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -70158,12 +73121,15 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -70177,13 +73143,16 @@ input VDD ; input VSS ; input p0 ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -70196,13 +73165,16 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -70300,10 +73272,8 @@ sb_1__0__mux_2level_tapbuf_basis_input2_mem2_10 mux_l1_in_1_ ( .mem_inv ( local_encoder2to3_0_data_inv[0:1] ) , .out ( mux_2level_tapbuf_basis_input2_mem2_0_out ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_153 ( .A ( BUF_net_154 ) , .Y ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_154 ( - .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_154 ) , +sky130_fd_sc_hd__buf_6 BUFT_RR_155 ( + .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -70408,13 +73378,16 @@ input VDD ; input VSS ; input p0 ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -70427,13 +73400,16 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -70446,13 +73422,16 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -70566,13 +73545,16 @@ input VDD ; input VSS ; input p0 ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -70585,13 +73567,16 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -70604,13 +73589,16 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -70684,6 +73672,9 @@ wire [0:0] mux_2level_tapbuf_basis_input3_mem3_2_out ; supply1 VDD ; supply0 VSS ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( mux_2level_tapbuf_basis_input3_mem3_2_out[0] ) , .X ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; sb_1__0__local_encoder2to3_22 local_encoder2to3_0_ ( .addr ( sram[0:1] ) , .data ( local_encoder2to3_0_data ) , .data_inv ( local_encoder2to3_0_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; @@ -70708,11 +73699,6 @@ sb_1__0__mux_2level_tapbuf_basis_input3_mem3_35 mux_l2_in_0_ ( .mem_inv ( local_encoder2to3_1_data_inv ) , .out ( mux_2level_tapbuf_basis_input3_mem3_2_out ) , .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_151 ( .A ( BUF_net_152 ) , .Y ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_152 ( - .A ( mux_2level_tapbuf_basis_input3_mem3_2_out[0] ) , .Y ( BUF_net_152 ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -70726,13 +73712,16 @@ input VDD ; input VSS ; input p0 ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -70745,13 +73734,16 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -70764,13 +73756,16 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -70868,10 +73863,10 @@ sb_1__0__mux_2level_tapbuf_basis_input3_mem3_32 mux_l2_in_0_ ( .mem_inv ( local_encoder2to3_1_data_inv ) , .out ( mux_2level_tapbuf_basis_input3_mem3_2_out ) , .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_149 ( .A ( BUF_net_150 ) , .Y ( out[0] ) , +sky130_fd_sc_hd__inv_8 BINV_R_153 ( .A ( BUF_net_154 ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_150 ( - .A ( mux_2level_tapbuf_basis_input3_mem3_2_out[0] ) , .Y ( BUF_net_150 ) , +sky130_fd_sc_hd__inv_1 BINV_R_154 ( + .A ( mux_2level_tapbuf_basis_input3_mem3_2_out[0] ) , .Y ( BUF_net_154 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -71159,7 +74154,7 @@ input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ropt_net_249 ) , +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ropt_net_255 ) , .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , @@ -71173,34 +74168,32 @@ sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_1 FTB_21__20 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1414 ( .A ( ropt_net_250 ) , - .X ( copt_net_213 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1415 ( .A ( copt_net_213 ) , - .X ( copt_net_214 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1416 ( .A ( copt_net_214 ) , - .X ( copt_net_215 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1417 ( .A ( copt_net_218 ) , - .X ( copt_net_216 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1418 ( .A ( ccff_head[0] ) , - .X ( copt_net_217 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1419 ( .A ( copt_net_215 ) , - .X ( copt_net_218 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1444 ( .A ( copt_net_216 ) , - .X ( ropt_net_243 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1445 ( .A ( ropt_net_243 ) , - .X ( ropt_net_244 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1446 ( .A ( ropt_net_244 ) , - .X ( ropt_net_245 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1447 ( .A ( ropt_net_245 ) , - .X ( ropt_net_246 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1448 ( .A ( ropt_net_246 ) , - .X ( ropt_net_247 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1449 ( .A ( ropt_net_247 ) , - .X ( ropt_net_248 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_4 ropt_h_inst_1450 ( .A ( ropt_net_248 ) , - .X ( ropt_net_249 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 ropt_h_inst_1451 ( .A ( copt_net_217 ) , - .X ( ropt_net_250 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1435 ( .A ( ropt_net_258 ) , + .X ( copt_net_226 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1436 ( .A ( ccff_head[0] ) , + .X ( copt_net_227 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1437 ( .A ( copt_net_226 ) , + .X ( copt_net_228 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1438 ( .A ( copt_net_227 ) , + .X ( copt_net_229 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1439 ( .A ( copt_net_228 ) , + .X ( copt_net_230 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1440 ( .A ( copt_net_229 ) , + .X ( copt_net_231 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1461 ( .A ( ropt_net_254 ) , + .X ( ropt_net_252 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1462 ( .A ( ropt_net_252 ) , + .X ( ropt_net_253 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1463 ( .A ( copt_net_230 ) , + .X ( ropt_net_254 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1464 ( .A ( ropt_net_257 ) , + .X ( ropt_net_255 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1465 ( .A ( ropt_net_253 ) , + .X ( ropt_net_256 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1466 ( .A ( ropt_net_256 ) , + .X ( ropt_net_257 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 ropt_h_inst_1467 ( .A ( copt_net_231 ) , + .X ( ropt_net_258 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -71214,12 +74207,15 @@ input VDD ; input VSS ; input p0 ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( p0 ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -71232,13 +74228,16 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -71251,13 +74250,16 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -71270,13 +74272,16 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -71351,9 +74356,6 @@ wire [0:0] mux_2level_tapbuf_basis_input3_mem3_2_out ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( mux_2level_tapbuf_basis_input3_mem3_2_out[0] ) , .X ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; sb_1__0__local_encoder2to3_18 local_encoder2to3_0_ ( .addr ( sram[0:1] ) , .data ( local_encoder2to3_0_data ) , .data_inv ( local_encoder2to3_0_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; @@ -71384,6 +74386,11 @@ sb_1__0__mux_2level_tapbuf_basis_input2_mem2_9 mux_l1_in_2_ ( .mem_inv ( local_encoder2to3_0_data_inv[0:1] ) , .out ( mux_2level_tapbuf_basis_input2_mem2_0_out ) , .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_151 ( .A ( BUF_net_152 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_152 ( + .A ( mux_2level_tapbuf_basis_input3_mem3_2_out[0] ) , .Y ( BUF_net_152 ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -71397,12 +74404,15 @@ input VDD ; input VSS ; input p0 ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( p0 ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -71415,13 +74425,16 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -71434,13 +74447,16 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -71453,13 +74469,16 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -71580,12 +74599,15 @@ input VDD ; input VSS ; input p0 ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( p0 ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -71598,13 +74620,16 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -71617,13 +74642,16 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -71636,13 +74664,16 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -71717,9 +74748,6 @@ wire [0:0] mux_2level_tapbuf_basis_input3_mem3_2_out ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( mux_2level_tapbuf_basis_input3_mem3_2_out[0] ) , .X ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; sb_1__0__local_encoder2to3_14 local_encoder2to3_0_ ( .addr ( sram[0:1] ) , .data ( local_encoder2to3_0_data ) , .data_inv ( local_encoder2to3_0_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; @@ -71750,6 +74778,11 @@ sb_1__0__mux_2level_tapbuf_basis_input2_mem2_7 mux_l1_in_2_ ( .mem_inv ( local_encoder2to3_0_data_inv[0:1] ) , .out ( mux_2level_tapbuf_basis_input2_mem2_0_out ) , .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_149 ( .A ( BUF_net_150 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_150 ( + .A ( mux_2level_tapbuf_basis_input3_mem3_2_out[0] ) , .Y ( BUF_net_150 ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -71763,12 +74796,15 @@ input VDD ; input VSS ; input p0 ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( p0 ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -71781,13 +74817,16 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -71800,13 +74839,16 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -71819,13 +74861,16 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -71900,9 +74945,6 @@ wire [0:0] mux_2level_tapbuf_basis_input3_mem3_2_out ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( mux_2level_tapbuf_basis_input3_mem3_2_out[0] ) , .X ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; sb_1__0__local_encoder2to3_12 local_encoder2to3_0_ ( .addr ( sram[0:1] ) , .data ( local_encoder2to3_0_data ) , .data_inv ( local_encoder2to3_0_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; @@ -71933,6 +74975,11 @@ sb_1__0__mux_2level_tapbuf_basis_input2_mem2_6 mux_l1_in_2_ ( .mem_inv ( local_encoder2to3_0_data_inv[0:1] ) , .out ( mux_2level_tapbuf_basis_input2_mem2_0_out ) , .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_147 ( .A ( BUF_net_148 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_148 ( + .A ( mux_2level_tapbuf_basis_input3_mem3_2_out[0] ) , .Y ( BUF_net_148 ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -71946,12 +74993,15 @@ input VDD ; input VSS ; input p0 ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( p0 ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -71964,13 +75014,16 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -71983,13 +75036,16 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -72002,13 +75058,16 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -72083,9 +75142,6 @@ wire [0:0] mux_2level_tapbuf_basis_input3_mem3_2_out ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( mux_2level_tapbuf_basis_input3_mem3_2_out[0] ) , .X ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; sb_1__0__local_encoder2to3_10 local_encoder2to3_0_ ( .addr ( sram[0:1] ) , .data ( local_encoder2to3_0_data ) , .data_inv ( local_encoder2to3_0_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; @@ -72116,6 +75172,11 @@ sb_1__0__mux_2level_tapbuf_basis_input2_mem2_5 mux_l1_in_2_ ( .mem_inv ( local_encoder2to3_0_data_inv[0:1] ) , .out ( mux_2level_tapbuf_basis_input2_mem2_0_out ) , .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_207 ( .A ( BUF_net_208 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_208 ( + .A ( mux_2level_tapbuf_basis_input3_mem3_2_out[0] ) , .Y ( BUF_net_208 ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -72129,12 +75190,15 @@ input VDD ; input VSS ; input p0 ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( p0 ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -72147,13 +75211,16 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -72166,13 +75233,16 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -72185,13 +75255,16 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -72266,6 +75339,9 @@ wire [0:0] mux_2level_tapbuf_basis_input3_mem3_2_out ; supply1 VDD ; supply0 VSS ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( mux_2level_tapbuf_basis_input3_mem3_2_out[0] ) , .X ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; sb_1__0__local_encoder2to3_8 local_encoder2to3_0_ ( .addr ( sram[0:1] ) , .data ( local_encoder2to3_0_data ) , .data_inv ( local_encoder2to3_0_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; @@ -72296,11 +75372,6 @@ sb_1__0__mux_2level_tapbuf_basis_input2_mem2_4 mux_l1_in_2_ ( .mem_inv ( local_encoder2to3_0_data_inv[0:1] ) , .out ( mux_2level_tapbuf_basis_input2_mem2_0_out ) , .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_147 ( .A ( BUF_net_148 ) , .Y ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_148 ( - .A ( mux_2level_tapbuf_basis_input3_mem3_2_out[0] ) , .Y ( BUF_net_148 ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -72314,12 +75385,15 @@ input VDD ; input VSS ; input p0 ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( p0 ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -72332,13 +75406,16 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -72351,13 +75428,16 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -72370,13 +75450,16 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -72451,9 +75534,6 @@ wire [0:0] mux_2level_tapbuf_basis_input3_mem3_2_out ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( mux_2level_tapbuf_basis_input3_mem3_2_out[0] ) , .X ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; sb_1__0__local_encoder2to3_6 local_encoder2to3_0_ ( .addr ( sram[0:1] ) , .data ( local_encoder2to3_0_data ) , .data_inv ( local_encoder2to3_0_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; @@ -72484,6 +75564,11 @@ sb_1__0__mux_2level_tapbuf_basis_input2_mem2_3 mux_l1_in_2_ ( .mem_inv ( local_encoder2to3_0_data_inv[0:1] ) , .out ( mux_2level_tapbuf_basis_input2_mem2_0_out ) , .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_215 ( .A ( BUF_net_216 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_216 ( + .A ( mux_2level_tapbuf_basis_input3_mem3_2_out[0] ) , .Y ( BUF_net_216 ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -72497,12 +75582,15 @@ input VDD ; input VSS ; input p0 ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( p0 ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -72515,13 +75603,16 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -72534,13 +75625,16 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -72553,13 +75647,16 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -72680,12 +75777,15 @@ input VDD ; input VSS ; input p0 ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( p0 ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -72698,13 +75798,16 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -72717,13 +75820,16 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -72736,13 +75842,16 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -72817,9 +75926,6 @@ wire [0:0] mux_2level_tapbuf_basis_input3_mem3_2_out ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( mux_2level_tapbuf_basis_input3_mem3_2_out[0] ) , .X ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; sb_1__0__local_encoder2to3_2 local_encoder2to3_0_ ( .addr ( sram[0:1] ) , .data ( local_encoder2to3_0_data ) , .data_inv ( local_encoder2to3_0_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; @@ -72850,6 +75956,11 @@ sb_1__0__mux_2level_tapbuf_basis_input2_mem2_1 mux_l1_in_2_ ( .mem_inv ( local_encoder2to3_0_data_inv[0:1] ) , .out ( mux_2level_tapbuf_basis_input2_mem2_0_out ) , .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_205 ( .A ( BUF_net_206 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_206 ( + .A ( mux_2level_tapbuf_basis_input3_mem3_2_out[0] ) , .Y ( BUF_net_206 ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -72863,12 +75974,15 @@ input VDD ; input VSS ; input p0 ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( p0 ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -72881,13 +75995,16 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -72900,13 +76017,16 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -72919,13 +76039,16 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -73109,7 +76232,7 @@ output clk_3_N_out ; input VDD ; input VSS ; -wire ropt_net_229 ; +wire ropt_net_242 ; wire [0:0] prog_clk ; wire prog_clk_0 ; wire [0:3] mux_2level_tapbuf_size10_0_sram ; @@ -73222,7 +76345,7 @@ sb_1__0__mux_2level_tapbuf_size7_0 mux_top_track_0 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 , SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) , .out ( chany_top_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_212 ) ) ; + .p0 ( optlc_net_220 ) ) ; sb_1__0__mux_2level_tapbuf_size7_1 mux_right_track_0 ( .in ( { chany_top_in[10] , chany_top_in[21] , right_bottom_grid_pin_1_[0] , right_bottom_grid_pin_7_[0] , @@ -73232,7 +76355,7 @@ sb_1__0__mux_2level_tapbuf_size7_1 mux_right_track_0 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 , SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 } ) , .out ( chanx_right_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_212 ) ) ; + .p0 ( optlc_net_220 ) ) ; sb_1__0__mux_2level_tapbuf_size7_2 mux_right_track_12 ( .in ( { chany_top_in[4] , chany_top_in[15] , chany_top_in[26] , right_bottom_grid_pin_1_[0] , right_bottom_grid_pin_13_[0] , @@ -73241,7 +76364,7 @@ sb_1__0__mux_2level_tapbuf_size7_2 mux_right_track_12 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_9 , SYNOPSYS_UNCONNECTED_10 , SYNOPSYS_UNCONNECTED_11 , SYNOPSYS_UNCONNECTED_12 } ) , .out ( chanx_right_out[6] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_212 ) ) ; + .p0 ( optlc_net_224 ) ) ; sb_1__0__mux_2level_tapbuf_size7_3 mux_right_track_20 ( .in ( { chany_top_in[5] , chany_top_in[16] , chany_top_in[27] , right_bottom_grid_pin_3_[0] , right_bottom_grid_pin_15_[0] , @@ -73250,7 +76373,7 @@ sb_1__0__mux_2level_tapbuf_size7_3 mux_right_track_20 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 , SYNOPSYS_UNCONNECTED_15 , SYNOPSYS_UNCONNECTED_16 } ) , .out ( chanx_right_out[10] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_209 ) ) ; + .p0 ( optlc_net_224 ) ) ; sb_1__0__mux_2level_tapbuf_size7_4 mux_right_track_28 ( .in ( { chany_top_in[6] , chany_top_in[17] , chany_top_in[28] , right_bottom_grid_pin_5_[0] , right_bottom_grid_pin_17_[0] , @@ -73259,7 +76382,7 @@ sb_1__0__mux_2level_tapbuf_size7_4 mux_right_track_28 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_17 , SYNOPSYS_UNCONNECTED_18 , SYNOPSYS_UNCONNECTED_19 , SYNOPSYS_UNCONNECTED_20 } ) , .out ( chanx_right_out[14] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_209 ) ) ; + .p0 ( optlc_net_224 ) ) ; sb_1__0__mux_2level_tapbuf_size7_5 mux_left_track_3 ( .in ( { chany_top_in[10] , chany_top_in[21] , chanx_left_out[7] , chanx_left_out[21] , left_bottom_grid_pin_3_[0] , @@ -73268,7 +76391,7 @@ sb_1__0__mux_2level_tapbuf_size7_5 mux_left_track_3 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_21 , SYNOPSYS_UNCONNECTED_22 , SYNOPSYS_UNCONNECTED_23 , SYNOPSYS_UNCONNECTED_24 } ) , .out ( chanx_left_out[1] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_207 ) ) ; + .p0 ( optlc_net_223 ) ) ; sb_1__0__mux_2level_tapbuf_size7_6 mux_left_track_5 ( .in ( { chany_top_in[9] , chany_top_in[20] , chanx_left_out[8] , chanx_left_out[23] , left_bottom_grid_pin_5_[0] , @@ -73277,7 +76400,7 @@ sb_1__0__mux_2level_tapbuf_size7_6 mux_left_track_5 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_25 , SYNOPSYS_UNCONNECTED_26 , SYNOPSYS_UNCONNECTED_27 , SYNOPSYS_UNCONNECTED_28 } ) , .out ( chanx_left_out[2] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_210 ) ) ; + .p0 ( optlc_net_221 ) ) ; sb_1__0__mux_2level_tapbuf_size7_7 mux_left_track_13 ( .in ( { chany_top_in[6] , chany_top_in[17] , chany_top_in[28] , chanx_left_out[12] , chanx_left_out[27] , left_bottom_grid_pin_1_[0] , @@ -73286,7 +76409,7 @@ sb_1__0__mux_2level_tapbuf_size7_7 mux_left_track_13 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_29 , SYNOPSYS_UNCONNECTED_30 , SYNOPSYS_UNCONNECTED_31 , SYNOPSYS_UNCONNECTED_32 } ) , .out ( chanx_left_out[6] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_211 ) ) ; + .p0 ( optlc_net_223 ) ) ; sb_1__0__mux_2level_tapbuf_size7_8 mux_left_track_21 ( .in ( { chany_top_in[5] , chany_top_in[16] , chany_top_in[27] , chanx_left_out[13] , chanx_left_out[28] , left_bottom_grid_pin_3_[0] , @@ -73295,7 +76418,7 @@ sb_1__0__mux_2level_tapbuf_size7_8 mux_left_track_21 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_33 , SYNOPSYS_UNCONNECTED_34 , SYNOPSYS_UNCONNECTED_35 , SYNOPSYS_UNCONNECTED_36 } ) , .out ( chanx_left_out[10] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_207 ) ) ; + .p0 ( optlc_net_223 ) ) ; sb_1__0__mux_2level_tapbuf_size7 mux_left_track_29 ( .in ( { chany_top_in[4] , chany_top_in[15] , chany_top_in[26] , chanx_left_out[15] , chanx_left_out[29] , left_bottom_grid_pin_5_[0] , @@ -73304,7 +76427,7 @@ sb_1__0__mux_2level_tapbuf_size7 mux_left_track_29 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_37 , SYNOPSYS_UNCONNECTED_38 , SYNOPSYS_UNCONNECTED_39 , SYNOPSYS_UNCONNECTED_40 } ) , .out ( chanx_left_out[14] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_210 ) ) ; + .p0 ( optlc_net_223 ) ) ; sb_1__0__mux_2level_tapbuf_size7_mem_0 mem_top_track_0 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( mux_2level_tapbuf_size7_mem_0_ccff_tail ) , @@ -73372,7 +76495,7 @@ sb_1__0__mux_2level_tapbuf_size6_0 mux_top_track_2 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_41 , SYNOPSYS_UNCONNECTED_42 , SYNOPSYS_UNCONNECTED_43 , SYNOPSYS_UNCONNECTED_44 } ) , .out ( chany_top_out[1] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_210 ) ) ; + .p0 ( optlc_net_218 ) ) ; sb_1__0__mux_2level_tapbuf_size6_1 mux_top_track_6 ( .in ( { top_left_grid_pin_44_[0] , top_left_grid_pin_47_[0] , top_left_grid_pin_50_[0] , chanx_right_in[5] , chanx_left_out[9] , @@ -73381,7 +76504,7 @@ sb_1__0__mux_2level_tapbuf_size6_1 mux_top_track_6 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_45 , SYNOPSYS_UNCONNECTED_46 , SYNOPSYS_UNCONNECTED_47 , SYNOPSYS_UNCONNECTED_48 } ) , .out ( chany_top_out[3] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_212 ) ) ; + .p0 ( optlc_net_218 ) ) ; sb_1__0__mux_2level_tapbuf_size6 mux_top_track_8 ( .in ( { chany_top_out[19] , top_left_grid_pin_48_[0] , top_left_grid_pin_51_[0] , chanx_right_in[9] , chanx_left_out[11] , @@ -73390,7 +76513,7 @@ sb_1__0__mux_2level_tapbuf_size6 mux_top_track_8 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_49 , SYNOPSYS_UNCONNECTED_50 , SYNOPSYS_UNCONNECTED_51 , SYNOPSYS_UNCONNECTED_52 } ) , .out ( chany_top_out[4] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_208 ) ) ; + .p0 ( optlc_net_225 ) ) ; sb_1__0__mux_2level_tapbuf_size6_mem_0 mem_top_track_2 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( mux_2level_tapbuf_size7_mem_0_ccff_tail ) , @@ -73416,7 +76539,7 @@ sb_1__0__mux_2level_tapbuf_size5_0 mux_top_track_4 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_53 , SYNOPSYS_UNCONNECTED_54 , SYNOPSYS_UNCONNECTED_55 , SYNOPSYS_UNCONNECTED_56 } ) , .out ( chany_top_out[2] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_210 ) ) ; + .p0 ( optlc_net_223 ) ) ; sb_1__0__mux_2level_tapbuf_size5_1 mux_top_track_10 ( .in ( { top_left_grid_pin_46_[0] , top_left_grid_pin_49_[0] , chanx_left_out[12] , chanx_right_in[13] , chanx_right_out[12] } ) , @@ -73424,7 +76547,7 @@ sb_1__0__mux_2level_tapbuf_size5_1 mux_top_track_10 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_57 , SYNOPSYS_UNCONNECTED_58 , SYNOPSYS_UNCONNECTED_59 , SYNOPSYS_UNCONNECTED_60 } ) , .out ( chany_top_out[5] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_210 ) ) ; + .p0 ( optlc_net_222 ) ) ; sb_1__0__mux_2level_tapbuf_size5_2 mux_right_track_36 ( .in ( { chany_top_in[7] , chany_top_in[18] , chany_top_in[29] , right_bottom_grid_pin_7_[0] , chanx_right_out[16] } ) , @@ -73432,7 +76555,7 @@ sb_1__0__mux_2level_tapbuf_size5_2 mux_right_track_36 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_61 , SYNOPSYS_UNCONNECTED_62 , SYNOPSYS_UNCONNECTED_63 , SYNOPSYS_UNCONNECTED_64 } ) , .out ( chanx_right_out[18] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_209 ) ) ; + .p0 ( optlc_net_220 ) ) ; sb_1__0__mux_2level_tapbuf_size5_3 mux_left_track_37 ( .in ( { chany_top_in[3] , chany_top_in[14] , chany_top_in[25] , chanx_left_out[16] , left_bottom_grid_pin_7_[0] } ) , @@ -73440,7 +76563,7 @@ sb_1__0__mux_2level_tapbuf_size5_3 mux_left_track_37 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_65 , SYNOPSYS_UNCONNECTED_66 , SYNOPSYS_UNCONNECTED_67 , SYNOPSYS_UNCONNECTED_68 } ) , .out ( chanx_left_out[18] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_210 ) ) ; + .p0 ( optlc_net_223 ) ) ; sb_1__0__mux_2level_tapbuf_size5_4 mux_left_track_45 ( .in ( { chany_top_in[2] , chany_top_in[13] , chany_top_in[24] , chanx_left_out[17] , left_bottom_grid_pin_9_[0] } ) , @@ -73448,7 +76571,7 @@ sb_1__0__mux_2level_tapbuf_size5_4 mux_left_track_45 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_69 , SYNOPSYS_UNCONNECTED_70 , SYNOPSYS_UNCONNECTED_71 , SYNOPSYS_UNCONNECTED_72 } ) , .out ( chanx_left_out[22] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_210 ) ) ; + .p0 ( optlc_net_221 ) ) ; sb_1__0__mux_2level_tapbuf_size5 mux_left_track_53 ( .in ( { chany_top_in[1] , chany_top_in[12] , chany_top_in[23] , chanx_left_out[19] , left_bottom_grid_pin_11_[0] } ) , @@ -73456,7 +76579,7 @@ sb_1__0__mux_2level_tapbuf_size5 mux_left_track_53 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_73 , SYNOPSYS_UNCONNECTED_74 , SYNOPSYS_UNCONNECTED_75 , SYNOPSYS_UNCONNECTED_76 } ) , .out ( chanx_left_out[26] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_210 ) ) ; + .p0 ( optlc_net_221 ) ) ; sb_1__0__mux_2level_tapbuf_size5_mem_0 mem_top_track_4 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( mux_2level_tapbuf_size6_mem_0_ccff_tail ) , @@ -73499,7 +76622,7 @@ sb_1__0__mux_2level_tapbuf_size4_0 mux_top_track_12 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_77 , SYNOPSYS_UNCONNECTED_78 , SYNOPSYS_UNCONNECTED_79 , SYNOPSYS_UNCONNECTED_80 } ) , .out ( chany_top_out[6] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_208 ) ) ; + .p0 ( optlc_net_224 ) ) ; sb_1__0__mux_2level_tapbuf_size4_1 mux_top_track_14 ( .in ( { chany_top_out[19] , chanx_left_out[15] , chanx_right_in[21] , chanx_right_out[15] } ) , @@ -73507,7 +76630,7 @@ sb_1__0__mux_2level_tapbuf_size4_1 mux_top_track_14 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_81 , SYNOPSYS_UNCONNECTED_82 , SYNOPSYS_UNCONNECTED_83 , SYNOPSYS_UNCONNECTED_84 } ) , .out ( chany_top_out[7] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_208 ) ) ; + .p0 ( optlc_net_222 ) ) ; sb_1__0__mux_2level_tapbuf_size4_2 mux_top_track_16 ( .in ( { top_left_grid_pin_46_[0] , chanx_left_out[16] , chanx_right_in[25] , chanx_right_out[16] } ) , @@ -73515,7 +76638,7 @@ sb_1__0__mux_2level_tapbuf_size4_2 mux_top_track_16 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_85 , SYNOPSYS_UNCONNECTED_86 , SYNOPSYS_UNCONNECTED_87 , SYNOPSYS_UNCONNECTED_88 } ) , .out ( chany_top_out[8] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_208 ) ) ; + .p0 ( optlc_net_220 ) ) ; sb_1__0__mux_2level_tapbuf_size4_3 mux_top_track_18 ( .in ( { top_left_grid_pin_47_[0] , chanx_left_out[17] , chanx_right_in[29] , chanx_right_out[17] } ) , @@ -73523,7 +76646,7 @@ sb_1__0__mux_2level_tapbuf_size4_3 mux_top_track_18 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_89 , SYNOPSYS_UNCONNECTED_90 , SYNOPSYS_UNCONNECTED_91 , SYNOPSYS_UNCONNECTED_92 } ) , .out ( chany_top_out[9] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_208 ) ) ; + .p0 ( optlc_net_220 ) ) ; sb_1__0__mux_2level_tapbuf_size4_4 mux_right_track_44 ( .in ( { chany_top_in[8] , chany_top_in[19] , right_bottom_grid_pin_9_[0] , chanx_right_out[17] } ) , @@ -73531,7 +76654,7 @@ sb_1__0__mux_2level_tapbuf_size4_4 mux_right_track_44 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_93 , SYNOPSYS_UNCONNECTED_94 , SYNOPSYS_UNCONNECTED_95 , SYNOPSYS_UNCONNECTED_96 } ) , .out ( chanx_right_out[22] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_209 ) ) ; + .p0 ( optlc_net_218 ) ) ; sb_1__0__mux_2level_tapbuf_size4 mux_right_track_52 ( .in ( { chany_top_in[9] , chany_top_in[20] , right_bottom_grid_pin_11_[0] , chanx_right_out[19] } ) , @@ -73539,7 +76662,7 @@ sb_1__0__mux_2level_tapbuf_size4 mux_right_track_52 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_97 , SYNOPSYS_UNCONNECTED_98 , SYNOPSYS_UNCONNECTED_99 , SYNOPSYS_UNCONNECTED_100 } ) , .out ( chanx_right_out[26] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_208 ) ) ; + .p0 ( optlc_net_218 ) ) ; sb_1__0__mux_2level_tapbuf_size4_mem_0 mem_top_track_12 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( mux_2level_tapbuf_size5_mem_1_ccff_tail ) , @@ -73582,35 +76705,35 @@ sb_1__0__mux_2level_tapbuf_size3_0 mux_top_track_20 ( .sram ( mux_2level_tapbuf_size3_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_101 , SYNOPSYS_UNCONNECTED_102 } ) , .out ( chany_top_out[10] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_212 ) ) ; + .p0 ( optlc_net_225 ) ) ; sb_1__0__mux_2level_tapbuf_size3_1 mux_top_track_22 ( .in ( { top_left_grid_pin_49_[0] , chanx_left_out[20] , chanx_right_out[20] } ) , .sram ( mux_2level_tapbuf_size3_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_103 , SYNOPSYS_UNCONNECTED_104 } ) , .out ( chany_top_out[11] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_212 ) ) ; + .p0 ( optlc_net_217 ) ) ; sb_1__0__mux_2level_tapbuf_size3_2 mux_top_track_24 ( .in ( { top_left_grid_pin_50_[0] , chanx_left_out[21] , chanx_right_out[21] } ) , .sram ( mux_2level_tapbuf_size3_2_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_105 , SYNOPSYS_UNCONNECTED_106 } ) , .out ( chany_top_out[12] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_212 ) ) ; + .p0 ( optlc_net_217 ) ) ; sb_1__0__mux_2level_tapbuf_size3_3 mux_top_track_26 ( .in ( { top_left_grid_pin_51_[0] , chanx_left_out[23] , chanx_right_out[23] } ) , .sram ( mux_2level_tapbuf_size3_3_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_107 , SYNOPSYS_UNCONNECTED_108 } ) , .out ( chany_top_out[13] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_212 ) ) ; + .p0 ( optlc_net_222 ) ) ; sb_1__0__mux_2level_tapbuf_size3 mux_top_track_36 ( .in ( { top_left_grid_pin_44_[0] , chanx_left_out[29] , chanx_right_out[29] } ) , .sram ( mux_2level_tapbuf_size3_4_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_109 , SYNOPSYS_UNCONNECTED_110 } ) , .out ( chany_top_out[18] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_211 ) ) ; + .p0 ( optlc_net_217 ) ) ; sb_1__0__mux_2level_tapbuf_size3_mem_0 mem_top_track_20 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( mux_2level_tapbuf_size4_mem_3_ccff_tail ) , @@ -73646,67 +76769,67 @@ sb_1__0__mux_2level_tapbuf_size2_0 mux_top_track_28 ( .sram ( mux_2level_tapbuf_size2_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_111 , SYNOPSYS_UNCONNECTED_112 } ) , .out ( chany_top_out[14] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_211 ) ) ; + .p0 ( optlc_net_222 ) ) ; sb_1__0__mux_2level_tapbuf_size2_1 mux_top_track_30 ( .in ( { chanx_left_out[25] , chanx_right_out[25] } ) , .sram ( mux_2level_tapbuf_size2_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_113 , SYNOPSYS_UNCONNECTED_114 } ) , .out ( chany_top_out[15] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_209 ) ) ; + .p0 ( optlc_net_222 ) ) ; sb_1__0__mux_2level_tapbuf_size2_2 mux_top_track_32 ( .in ( { chanx_left_out[27] , chanx_right_out[27] } ) , .sram ( mux_2level_tapbuf_size2_2_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_115 , SYNOPSYS_UNCONNECTED_116 } ) , .out ( chany_top_out[16] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_211 ) ) ; + .p0 ( optlc_net_222 ) ) ; sb_1__0__mux_2level_tapbuf_size2_3 mux_top_track_34 ( .in ( { chanx_left_out[28] , chanx_right_out[28] } ) , .sram ( mux_2level_tapbuf_size2_3_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_117 , SYNOPSYS_UNCONNECTED_118 } ) , .out ( chany_top_out[17] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_211 ) ) ; + .p0 ( optlc_net_222 ) ) ; sb_1__0__mux_2level_tapbuf_size2_4 mux_top_track_40 ( .in ( { top_left_grid_pin_46_[0] , chanx_left_in[29] } ) , .sram ( mux_2level_tapbuf_size2_4_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_119 , SYNOPSYS_UNCONNECTED_120 } ) , .out ( chany_top_out[20] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_207 ) ) ; + .p0 ( optlc_net_217 ) ) ; sb_1__0__mux_2level_tapbuf_size2_5 mux_top_track_42 ( .in ( { top_left_grid_pin_47_[0] , chanx_left_in[25] } ) , .sram ( mux_2level_tapbuf_size2_5_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_121 , SYNOPSYS_UNCONNECTED_122 } ) , .out ( chany_top_out[21] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_207 ) ) ; + .p0 ( optlc_net_217 ) ) ; sb_1__0__mux_2level_tapbuf_size2_6 mux_top_track_44 ( .in ( { top_left_grid_pin_48_[0] , chanx_left_in[21] } ) , .sram ( mux_2level_tapbuf_size2_6_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_123 , SYNOPSYS_UNCONNECTED_124 } ) , .out ( chany_top_out[22] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_207 ) ) ; + .p0 ( optlc_net_217 ) ) ; sb_1__0__mux_2level_tapbuf_size2_7 mux_top_track_46 ( .in ( { top_left_grid_pin_49_[0] , chanx_left_in[17] } ) , .sram ( mux_2level_tapbuf_size2_7_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_125 , SYNOPSYS_UNCONNECTED_126 } ) , .out ( chany_top_out[23] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_207 ) ) ; + .p0 ( optlc_net_217 ) ) ; sb_1__0__mux_2level_tapbuf_size2_8 mux_top_track_48 ( .in ( { top_left_grid_pin_50_[0] , chanx_left_in[13] } ) , .sram ( mux_2level_tapbuf_size2_8_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_127 , SYNOPSYS_UNCONNECTED_128 } ) , .out ( chany_top_out[24] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_211 ) ) ; + .p0 ( optlc_net_217 ) ) ; sb_1__0__mux_2level_tapbuf_size2_9 mux_top_track_50 ( .in ( { top_left_grid_pin_51_[0] , chanx_left_in[9] } ) , .sram ( mux_2level_tapbuf_size2_9_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_129 , SYNOPSYS_UNCONNECTED_130 } ) , .out ( chany_top_out[25] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_211 ) ) ; + .p0 ( optlc_net_217 ) ) ; sb_1__0__mux_2level_tapbuf_size2 mux_top_track_58 ( .in ( { chanx_right_in[0] , chanx_left_in[1] } ) , .sram ( mux_2level_tapbuf_size2_10_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_131 , SYNOPSYS_UNCONNECTED_132 } ) , .out ( chany_top_out[29] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_211 ) ) ; + .p0 ( optlc_net_224 ) ) ; sb_1__0__mux_2level_tapbuf_size2_mem_0 mem_top_track_28 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( mux_2level_tapbuf_size3_mem_3_ccff_tail ) , @@ -73782,7 +76905,7 @@ sb_1__0__mux_2level_tapbuf_size8_0 mux_right_track_2 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_133 , SYNOPSYS_UNCONNECTED_134 , SYNOPSYS_UNCONNECTED_135 , SYNOPSYS_UNCONNECTED_136 } ) , .out ( chanx_right_out[1] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_209 ) ) ; + .p0 ( optlc_net_220 ) ) ; sb_1__0__mux_2level_tapbuf_size8_1 mux_right_track_4 ( .in ( { chany_top_in[1] , chany_top_in[12] , chany_top_in[23] , right_bottom_grid_pin_5_[0] , right_bottom_grid_pin_11_[0] , @@ -73792,7 +76915,7 @@ sb_1__0__mux_2level_tapbuf_size8_1 mux_right_track_4 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_137 , SYNOPSYS_UNCONNECTED_138 , SYNOPSYS_UNCONNECTED_139 , SYNOPSYS_UNCONNECTED_140 } ) , .out ( chanx_right_out[2] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_208 ) ) ; + .p0 ( optlc_net_219 ) ) ; sb_1__0__mux_2level_tapbuf_size8 mux_left_track_1 ( .in ( { chany_top_in[0] , chany_top_in[11] , chany_top_in[22] , chanx_left_out[4] , chanx_left_out[20] , left_bottom_grid_pin_1_[0] , @@ -73801,7 +76924,7 @@ sb_1__0__mux_2level_tapbuf_size8 mux_left_track_1 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_141 , SYNOPSYS_UNCONNECTED_142 , SYNOPSYS_UNCONNECTED_143 , SYNOPSYS_UNCONNECTED_144 } ) , .out ( chanx_left_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_212 ) ) ; + .p0 ( optlc_net_221 ) ) ; sb_1__0__mux_2level_tapbuf_size8_mem_0 mem_right_track_2 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( mux_2level_tapbuf_size7_mem_1_ccff_tail ) , @@ -73829,8 +76952,8 @@ sb_1__0__mux_2level_tapbuf_size10 mux_right_track_6 ( .sram ( mux_2level_tapbuf_size10_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_145 , SYNOPSYS_UNCONNECTED_146 , SYNOPSYS_UNCONNECTED_147 , SYNOPSYS_UNCONNECTED_148 } ) , - .out ( { aps_rename_505_ } ) , - .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_208 ) ) ; + .out ( { aps_rename_506_ } ) , + .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_219 ) ) ; sb_1__0__mux_2level_tapbuf_size10_mem mem_right_track_6 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( mux_2level_tapbuf_size8_mem_1_ccff_tail ) , @@ -73845,8 +76968,8 @@ sb_1__0__mux_2level_tapbuf_size9_0 mux_right_track_10 ( .sram ( mux_2level_tapbuf_size9_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_149 , SYNOPSYS_UNCONNECTED_150 , SYNOPSYS_UNCONNECTED_151 , SYNOPSYS_UNCONNECTED_152 } ) , - .out ( chanx_right_out[5] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_208 ) ) ; + .out ( { aps_rename_507_ } ) , + .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_220 ) ) ; sb_1__0__mux_2level_tapbuf_size9_1 mux_left_track_7 ( .in ( { chany_top_in[8] , chany_top_in[19] , chanx_left_out[9] , chanx_left_out[24] , left_bottom_grid_pin_1_[0] , @@ -73855,8 +76978,8 @@ sb_1__0__mux_2level_tapbuf_size9_1 mux_left_track_7 ( .sram ( mux_2level_tapbuf_size9_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_153 , SYNOPSYS_UNCONNECTED_154 , SYNOPSYS_UNCONNECTED_155 , SYNOPSYS_UNCONNECTED_156 } ) , - .out ( { aps_rename_506_ } ) , - .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_210 ) ) ; + .out ( chanx_left_out[3] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_221 ) ) ; sb_1__0__mux_2level_tapbuf_size9 mux_left_track_11 ( .in ( { chany_top_in[7] , chany_top_in[18] , chany_top_in[29] , chanx_left_out[11] , chanx_left_out[25] , left_bottom_grid_pin_3_[0] , @@ -73865,8 +76988,8 @@ sb_1__0__mux_2level_tapbuf_size9 mux_left_track_11 ( .sram ( mux_2level_tapbuf_size9_2_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_157 , SYNOPSYS_UNCONNECTED_158 , SYNOPSYS_UNCONNECTED_159 , SYNOPSYS_UNCONNECTED_160 } ) , - .out ( chanx_left_out[5] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_207 ) ) ; + .out ( { aps_rename_508_ } ) , + .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_223 ) ) ; sb_1__0__mux_2level_tapbuf_size9_mem_0 mem_right_track_10 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( mux_2level_tapbuf_size10_mem_0_ccff_tail ) , @@ -73885,24 +77008,24 @@ sb_1__0__mux_2level_tapbuf_size9_mem mem_left_track_11 ( .pReset ( pReset ) , .ccff_tail ( mux_2level_tapbuf_size9_mem_2_ccff_tail ) , .mem_out ( mux_2level_tapbuf_size9_2_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_209 ( .LO ( SYNOPSYS_UNCONNECTED_161 ) , - .HI ( optlc_net_207 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_219 ( .LO ( SYNOPSYS_UNCONNECTED_161 ) , + .HI ( optlc_net_217 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_8 pReset_FTB00 ( .A ( pReset_E_in ) , .X ( pReset[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_1 pReset_N_FTB01 ( .A ( pReset_E_in ) , - .X ( aps_rename_507_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .X ( aps_rename_509_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__bufbuf_16 pReset_W_FTB01 ( .A ( pReset_E_in ) , .X ( pReset_W_out ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_1 pReset_E_FTB01 ( .A ( pReset_E_in ) , - .X ( aps_rename_508_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_211 ( .LO ( SYNOPSYS_UNCONNECTED_162 ) , - .HI ( optlc_net_208 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .X ( aps_rename_510_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_223 ( .LO ( SYNOPSYS_UNCONNECTED_162 ) , + .HI ( optlc_net_218 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_1 prog_clk_0_FTB00 ( .A ( prog_clk_0_N_in ) , .X ( prog_clk[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_1 prog_clk_3_N_FTB01 ( .A ( prog_clk_3_S_in ) , - .X ( aps_rename_509_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .X ( aps_rename_511_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_1 clk_3_N_FTB01 ( .A ( clk_3_S_in ) , - .X ( aps_rename_510_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .X ( aps_rename_512_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_8 FTB_105__104 ( .A ( top_left_grid_pin_45_[0] ) , .X ( chany_top_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_8 FTB_106__105 ( .A ( chanx_right_in[3] ) , @@ -73948,7 +77071,7 @@ sky130_fd_sc_hd__buf_8 FTB_125__124 ( .A ( chanx_left_in[2] ) , sky130_fd_sc_hd__buf_8 FTB_126__125 ( .A ( chanx_left_in[3] ) , .X ( chanx_right_out[4] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_6 FTB_127__126 ( .A ( chanx_left_in[4] ) , - .X ( ropt_net_229 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .X ( ropt_net_242 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_8 FTB_128__127 ( .A ( chanx_left_in[5] ) , .X ( chany_top_out[26] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_8 FTB_129__128 ( .A ( chanx_left_in[6] ) , @@ -73995,7 +77118,7 @@ sky130_fd_sc_hd__inv_1 BINV_R_196 ( .A ( Test_en_S_in ) , .Y ( BUF_net_196 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__inv_8 BINV_R_197 ( .A ( BUF_net_198 ) , .Y ( pReset_N_out ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_198 ( .A ( aps_rename_507_ ) , +sky130_fd_sc_hd__inv_1 BINV_R_198 ( .A ( aps_rename_509_ ) , .Y ( BUF_net_198 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__inv_8 BINV_R_199 ( .A ( BUF_net_200 ) , .Y ( Reset_N_out ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -74003,27 +77126,35 @@ sky130_fd_sc_hd__inv_1 BINV_R_200 ( .A ( Reset_S_in ) , .Y ( BUF_net_200 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__inv_8 BINV_R_201 ( .A ( BUF_net_202 ) , .Y ( prog_clk_3_N_out ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_202 ( .A ( aps_rename_509_ ) , +sky130_fd_sc_hd__inv_1 BINV_R_202 ( .A ( aps_rename_511_ ) , .Y ( BUF_net_202 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__inv_8 BINV_R_203 ( .A ( BUF_net_204 ) , .Y ( clk_3_N_out ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_204 ( .A ( aps_rename_510_ ) , +sky130_fd_sc_hd__inv_1 BINV_R_204 ( .A ( aps_rename_512_ ) , .Y ( BUF_net_204 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_213 ( .LO ( SYNOPSYS_UNCONNECTED_163 ) , - .HI ( optlc_net_209 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_215 ( .LO ( SYNOPSYS_UNCONNECTED_164 ) , - .HI ( optlc_net_210 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_217 ( .LO ( SYNOPSYS_UNCONNECTED_165 ) , - .HI ( optlc_net_211 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_219 ( .LO ( SYNOPSYS_UNCONNECTED_166 ) , - .HI ( optlc_net_212 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_6 ZBUF_6_f_inst_220 ( .A ( aps_rename_505_ ) , +sky130_fd_sc_hd__conb_1 optlc_225 ( .LO ( SYNOPSYS_UNCONNECTED_163 ) , + .HI ( optlc_net_219 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_227 ( .LO ( SYNOPSYS_UNCONNECTED_164 ) , + .HI ( optlc_net_220 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_230 ( .LO ( SYNOPSYS_UNCONNECTED_165 ) , + .HI ( optlc_net_221 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_232 ( .LO ( SYNOPSYS_UNCONNECTED_166 ) , + .HI ( optlc_net_222 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_235 ( .LO ( SYNOPSYS_UNCONNECTED_167 ) , + .HI ( optlc_net_223 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_237 ( .LO ( SYNOPSYS_UNCONNECTED_168 ) , + .HI ( optlc_net_224 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_239 ( .LO ( SYNOPSYS_UNCONNECTED_169 ) , + .HI ( optlc_net_225 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 ZBUF_6_f_inst_240 ( .A ( aps_rename_506_ ) , .X ( chanx_right_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_6 ZBUF_6_f_inst_221 ( .A ( aps_rename_508_ ) , +sky130_fd_sc_hd__buf_6 ZBUF_6_f_inst_241 ( .A ( aps_rename_508_ ) , + .X ( chanx_left_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 ZBUF_6_f_inst_242 ( .A ( aps_rename_507_ ) , + .X ( chanx_right_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 ZBUF_6_f_inst_243 ( .A ( aps_rename_510_ ) , .X ( pReset_E_out ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_6 ZBUF_6_f_inst_222 ( .A ( aps_rename_506_ ) , - .X ( chanx_left_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_8 ropt_mt_inst_1431 ( .A ( ropt_net_229 ) , +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1451 ( .A ( ropt_net_242 ) , .X ( chany_top_out[27] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -74088,7 +77219,7 @@ input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__mux2_2 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) , +sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -74147,9 +77278,6 @@ wire [0:0] mux_2level_tapbuf_basis_input2_mem1_2_out ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( mux_2level_tapbuf_basis_input2_mem1_2_out[0] ) , .X ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; sb_0__2__mux_2level_tapbuf_basis_input2_mem1_57 mux_l1_in_0_ ( .in ( in[0:1] ) , .mem ( sram[0] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) , @@ -74168,6 +77296,11 @@ sb_0__2__mux_2level_tapbuf_basis_input2_mem1 mux_l2_in_0_ ( .mem_inv ( { SYNOPSYS_UNCONNECTED_4 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_2_out ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_100 ( .A ( BUF_net_101 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_101 ( + .A ( mux_2level_tapbuf_basis_input2_mem1_2_out[0] ) , .Y ( BUF_net_101 ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -74260,10 +77393,10 @@ sb_0__2__mux_2level_tapbuf_basis_input2_mem1_56 mux_l2_in_0_ ( .mem_inv ( { SYNOPSYS_UNCONNECTED_4 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_2_out ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_92 ( .A ( BUF_net_93 ) , .Y ( out[0] ) , +sky130_fd_sc_hd__inv_8 BINV_R_98 ( .A ( BUF_net_99 ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_93 ( - .A ( mux_2level_tapbuf_basis_input2_mem1_2_out[0] ) , .Y ( BUF_net_93 ) , +sky130_fd_sc_hd__inv_1 BINV_R_99 ( + .A ( mux_2level_tapbuf_basis_input2_mem1_2_out[0] ) , .Y ( BUF_net_99 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -74278,7 +77411,7 @@ output [0:1] mem_out ; input VDD ; input VSS ; -wire copt_net_111 ; +wire copt_net_129 ; supply1 VDD ; supply0 VSS ; @@ -74286,15 +77419,15 @@ sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( copt_net_111 ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( copt_net_129 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_6 FTB_45__44 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1289 ( .A ( copt_net_111 ) , - .X ( copt_net_109 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1290 ( .A ( copt_net_109 ) , - .X ( copt_net_110 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1291 ( .A ( copt_net_110 ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1311 ( .A ( copt_net_129 ) , + .X ( copt_net_127 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1312 ( .A ( copt_net_127 ) , + .X ( copt_net_128 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1313 ( .A ( copt_net_128 ) , .X ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -74975,9 +78108,6 @@ wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; sb_0__2__mux_2level_tapbuf_basis_input2_mem1_52 mux_l1_in_0_ ( .in ( in ) , .mem ( sram[0] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) , @@ -74990,6 +78120,9 @@ sb_0__2__mux_2level_tapbuf_basis_input2_mem1_53 mux_l2_in_0_ ( .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_97 ( + .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -75076,7 +78209,7 @@ input p0 ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__mux2_2 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , +sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -75115,9 +78248,6 @@ wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; sb_0__2__mux_2level_tapbuf_basis_input2_mem1_48 mux_l1_in_0_ ( .in ( in ) , .mem ( sram[0] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) , @@ -75130,6 +78260,11 @@ sb_0__2__mux_2level_tapbuf_basis_input2_mem1_49 mux_l2_in_0_ ( .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_95 ( .A ( BUF_net_96 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_96 ( + .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_96 ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -75255,9 +78390,6 @@ wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; sb_0__2__mux_2level_tapbuf_basis_input2_mem1_44 mux_l1_in_0_ ( .in ( in ) , .mem ( sram[0] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) , @@ -75270,6 +78402,9 @@ sb_0__2__mux_2level_tapbuf_basis_input2_mem1_45 mux_l2_in_0_ ( .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_94 ( + .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -75286,7 +78421,7 @@ input p0 ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__mux2_2 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , +sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -75395,6 +78530,9 @@ wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ; supply1 VDD ; supply0 VSS ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; sb_0__2__mux_2level_tapbuf_basis_input2_mem1_40 mux_l1_in_0_ ( .in ( in ) , .mem ( sram[0] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) , @@ -75407,11 +78545,6 @@ sb_0__2__mux_2level_tapbuf_basis_input2_mem1_41 mux_l2_in_0_ ( .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_6 BINV_R_94 ( .A ( BUF_net_95 ) , .Y ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_2 BINV_R_95 ( - .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_95 ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -75479,10 +78612,10 @@ sb_0__2__mux_2level_tapbuf_basis_input2_mem1_39 mux_l2_in_0_ ( .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_90 ( .A ( BUF_net_91 ) , .Y ( out[0] ) , +sky130_fd_sc_hd__inv_6 BINV_R_92 ( .A ( BUF_net_93 ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_91 ( - .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_91 ) , +sky130_fd_sc_hd__inv_2 BINV_R_93 ( + .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_93 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -75570,7 +78703,7 @@ input p0 ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__mux2_2 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , +sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -75609,9 +78742,6 @@ wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; sb_0__2__mux_2level_tapbuf_basis_input2_mem1_34 mux_l1_in_0_ ( .in ( in ) , .mem ( sram[0] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) , @@ -75624,6 +78754,11 @@ sb_0__2__mux_2level_tapbuf_basis_input2_mem1_35 mux_l2_in_0_ ( .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_90 ( .A ( BUF_net_91 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_91 ( + .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_91 ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -75710,7 +78845,7 @@ input p0 ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__mux2_2 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , +sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -75749,9 +78884,6 @@ wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; sb_0__2__mux_2level_tapbuf_basis_input2_mem1_30 mux_l1_in_0_ ( .in ( in ) , .mem ( sram[0] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) , @@ -75764,6 +78896,11 @@ sb_0__2__mux_2level_tapbuf_basis_input2_mem1_31 mux_l2_in_0_ ( .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_88 ( .A ( BUF_net_89 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_89 ( + .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_89 ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -75780,7 +78917,7 @@ input p0 ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__mux2_2 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , +sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -75819,9 +78956,6 @@ wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; sb_0__2__mux_2level_tapbuf_basis_input2_mem1_28 mux_l1_in_0_ ( .in ( in ) , .mem ( sram[0] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) , @@ -75834,6 +78968,11 @@ sb_0__2__mux_2level_tapbuf_basis_input2_mem1_29 mux_l2_in_0_ ( .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_87 ( + .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_87 ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_110 ( .A ( BUF_net_87 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -75850,7 +78989,7 @@ input p0 ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , +sky130_fd_sc_hd__mux2_2 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -75889,6 +79028,9 @@ wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ; supply1 VDD ; supply0 VSS ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; sb_0__2__mux_2level_tapbuf_basis_input2_mem1_26 mux_l1_in_0_ ( .in ( in ) , .mem ( sram[0] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) , @@ -75901,11 +79043,6 @@ sb_0__2__mux_2level_tapbuf_basis_input2_mem1_27 mux_l2_in_0_ ( .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_88 ( .A ( BUF_net_89 ) , .Y ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_89 ( - .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_89 ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -76043,10 +79180,10 @@ sb_0__2__mux_2level_tapbuf_basis_input2_mem1_23 mux_l2_in_0_ ( .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_86 ( .A ( BUF_net_87 ) , .Y ( out[0] ) , +sky130_fd_sc_hd__inv_2 BINV_R_85 ( + .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_85 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_87 ( - .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_87 ) , +sky130_fd_sc_hd__inv_6 BINV_R_108 ( .A ( BUF_net_85 ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -76115,10 +79252,10 @@ sb_0__2__mux_2level_tapbuf_basis_input2_mem1_21 mux_l2_in_0_ ( .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_6 BINV_R_84 ( .A ( BUF_net_85 ) , .Y ( out[0] ) , +sky130_fd_sc_hd__inv_6 BINV_R_104 ( .A ( BUF_net_105 ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_2 BINV_R_85 ( - .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_85 ) , +sky130_fd_sc_hd__inv_2 BINV_R_105 ( + .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_105 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -76175,9 +79312,6 @@ wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; sb_0__2__mux_2level_tapbuf_basis_input2_mem1_18 mux_l1_in_0_ ( .in ( in ) , .mem ( sram[0] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) , @@ -76190,6 +79324,11 @@ sb_0__2__mux_2level_tapbuf_basis_input2_mem1_19 mux_l2_in_0_ ( .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_83 ( + .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_83 ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_106 ( .A ( BUF_net_83 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -76257,10 +79396,10 @@ sb_0__2__mux_2level_tapbuf_basis_input2_mem1_17 mux_l2_in_0_ ( .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_82 ( .A ( BUF_net_83 ) , .Y ( out[0] ) , +sky130_fd_sc_hd__inv_6 BINV_R_80 ( .A ( BUF_net_81 ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_83 ( - .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_83 ) , +sky130_fd_sc_hd__inv_2 BINV_R_81 ( + .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_81 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -76457,6 +79596,9 @@ wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ; supply1 VDD ; supply0 VSS ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; sb_0__2__mux_2level_tapbuf_basis_input2_mem1_10 mux_l1_in_0_ ( .in ( in ) , .mem ( sram[0] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) , @@ -76469,11 +79611,6 @@ sb_0__2__mux_2level_tapbuf_basis_input2_mem1_11 mux_l2_in_0_ ( .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_80 ( .A ( BUF_net_81 ) , .Y ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_81 ( - .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_81 ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -76529,9 +79666,6 @@ wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; sb_0__2__mux_2level_tapbuf_basis_input2_mem1_8 mux_l1_in_0_ ( .in ( in ) , .mem ( sram[0] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) , @@ -76544,6 +79678,9 @@ sb_0__2__mux_2level_tapbuf_basis_input2_mem1_9 mux_l2_in_0_ ( .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_79 ( + .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -76599,6 +79736,9 @@ wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ; supply1 VDD ; supply0 VSS ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; sb_0__2__mux_2level_tapbuf_basis_input2_mem1_6 mux_l1_in_0_ ( .in ( in ) , .mem ( sram[0] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) , @@ -76611,11 +79751,6 @@ sb_0__2__mux_2level_tapbuf_basis_input2_mem1_7 mux_l2_in_0_ ( .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_6 BINV_R_78 ( .A ( BUF_net_79 ) , .Y ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_2 BINV_R_79 ( - .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_79 ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -76683,10 +79818,10 @@ sb_0__2__mux_2level_tapbuf_basis_input2_mem1_5 mux_l2_in_0_ ( .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_6 BINV_R_76 ( .A ( BUF_net_77 ) , .Y ( out[0] ) , +sky130_fd_sc_hd__inv_8 BINV_R_77 ( .A ( BUF_net_78 ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_2 BINV_R_77 ( - .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_77 ) , +sky130_fd_sc_hd__inv_1 BINV_R_78 ( + .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_78 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -76994,7 +80129,7 @@ input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ropt_net_180 ) , +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ropt_net_158 ) , .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , @@ -77008,24 +80143,24 @@ sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_1 FTB_13__12 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1280 ( .A ( ccff_head[0] ) , - .X ( copt_net_100 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1281 ( .A ( copt_net_100 ) , - .X ( copt_net_101 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1282 ( .A ( copt_net_101 ) , - .X ( copt_net_102 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1283 ( .A ( copt_net_102 ) , - .X ( copt_net_103 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1284 ( .A ( copt_net_103 ) , - .X ( copt_net_104 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1285 ( .A ( copt_net_104 ) , - .X ( copt_net_105 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1357 ( .A ( ropt_net_179 ) , - .X ( ropt_net_178 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1358 ( .A ( copt_net_105 ) , - .X ( ropt_net_179 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1359 ( .A ( ropt_net_178 ) , - .X ( ropt_net_180 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1302 ( .A ( ccff_head[0] ) , + .X ( copt_net_118 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1303 ( .A ( copt_net_118 ) , + .X ( copt_net_119 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1304 ( .A ( copt_net_119 ) , + .X ( copt_net_120 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1305 ( .A ( copt_net_120 ) , + .X ( copt_net_121 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1306 ( .A ( copt_net_121 ) , + .X ( copt_net_122 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1307 ( .A ( copt_net_122 ) , + .X ( copt_net_123 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1341 ( .A ( ropt_net_160 ) , + .X ( ropt_net_158 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1342 ( .A ( copt_net_123 ) , + .X ( ropt_net_159 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1343 ( .A ( ropt_net_159 ) , + .X ( ropt_net_160 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -77039,13 +80174,16 @@ input VDD ; input VSS ; input p0 ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -77058,13 +80196,16 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -77171,13 +80312,16 @@ input VDD ; input VSS ; input p0 ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -77190,13 +80334,16 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -77303,13 +80450,16 @@ input VDD ; input VSS ; input p0 ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -77322,13 +80472,16 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -77401,9 +80554,6 @@ wire [0:0] mux_2level_tapbuf_basis_input3_mem3_1_out ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .X ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; sb_0__2__local_encoder2to3_6 local_encoder2to3_0_ ( .addr ( sram[0:1] ) , .data ( local_encoder2to3_0_data ) , .data_inv ( local_encoder2to3_0_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; @@ -77422,6 +80572,11 @@ sb_0__2__mux_2level_tapbuf_basis_input3_mem3_7 mux_l2_in_0_ ( .mem_inv ( local_encoder2to3_1_data_inv ) , .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_75 ( .A ( BUF_net_76 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_76 ( + .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_76 ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -77435,13 +80590,16 @@ input VDD ; input VSS ; input p0 ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -77454,13 +80612,16 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -77533,6 +80694,9 @@ wire [0:0] mux_2level_tapbuf_basis_input3_mem3_1_out ; supply1 VDD ; supply0 VSS ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .X ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; sb_0__2__local_encoder2to3_4 local_encoder2to3_0_ ( .addr ( sram[0:1] ) , .data ( local_encoder2to3_0_data ) , .data_inv ( local_encoder2to3_0_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; @@ -77551,11 +80715,6 @@ sb_0__2__mux_2level_tapbuf_basis_input3_mem3_5 mux_l2_in_0_ ( .mem_inv ( local_encoder2to3_1_data_inv ) , .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_6 BINV_R_74 ( .A ( BUF_net_75 ) , .Y ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_75 ( - .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_75 ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -77569,13 +80728,16 @@ input VDD ; input VSS ; input p0 ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -77588,13 +80750,16 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -77701,13 +80866,16 @@ input VDD ; input VSS ; input p0 ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -77720,13 +80888,16 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -77817,8 +80988,10 @@ sb_0__2__mux_2level_tapbuf_basis_input3_mem3_1 mux_l2_in_0_ ( .mem_inv ( local_encoder2to3_1_data_inv ) , .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_73 ( - .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .X ( out[0] ) , +sky130_fd_sc_hd__inv_6 BINV_R_73 ( .A ( BUF_net_74 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_74 ( + .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_74 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -77856,8 +81029,6 @@ input prog_clk_0_E_in ; input VDD ; input VSS ; -wire ropt_net_134 ; -wire ropt_net_132 ; wire [0:0] prog_clk ; wire prog_clk_0 ; wire [0:1] mux_2level_tapbuf_size2_0_sram ; @@ -77941,7 +81112,7 @@ sb_0__2__mux_2level_tapbuf_size4_0 mux_right_track_0 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 , SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) , .out ( chanx_right_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_98 ) ) ; + .p0 ( optlc_net_114 ) ) ; sb_0__2__mux_2level_tapbuf_size4_1 mux_right_track_2 ( .in ( { right_bottom_grid_pin_36_[0] , right_bottom_grid_pin_39_[0] , right_bottom_grid_pin_42_[0] , chany_bottom_in[27] } ) , @@ -77949,7 +81120,7 @@ sb_0__2__mux_2level_tapbuf_size4_1 mux_right_track_2 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 , SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 } ) , .out ( chanx_right_out[1] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_96 ) ) ; + .p0 ( optlc_net_113 ) ) ; sb_0__2__mux_2level_tapbuf_size4_2 mux_right_track_4 ( .in ( { right_bottom_grid_pin_37_[0] , right_bottom_grid_pin_40_[0] , right_bottom_grid_pin_43_[0] , chany_bottom_in[26] } ) , @@ -77957,7 +81128,7 @@ sb_0__2__mux_2level_tapbuf_size4_2 mux_right_track_4 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_9 , SYNOPSYS_UNCONNECTED_10 , SYNOPSYS_UNCONNECTED_11 , SYNOPSYS_UNCONNECTED_12 } ) , .out ( chanx_right_out[2] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_96 ) ) ; + .p0 ( optlc_net_113 ) ) ; sb_0__2__mux_2level_tapbuf_size4_3 mux_right_track_6 ( .in ( { right_top_grid_pin_1_[0] , right_bottom_grid_pin_38_[0] , right_bottom_grid_pin_41_[0] , chany_bottom_in[25] } ) , @@ -77965,7 +81136,7 @@ sb_0__2__mux_2level_tapbuf_size4_3 mux_right_track_6 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 , SYNOPSYS_UNCONNECTED_15 , SYNOPSYS_UNCONNECTED_16 } ) , .out ( chanx_right_out[3] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_98 ) ) ; + .p0 ( optlc_net_114 ) ) ; sb_0__2__mux_2level_tapbuf_size4_4 mux_right_track_8 ( .in ( { right_bottom_grid_pin_36_[0] , right_bottom_grid_pin_39_[0] , right_bottom_grid_pin_42_[0] , chany_bottom_in[24] } ) , @@ -77973,7 +81144,7 @@ sb_0__2__mux_2level_tapbuf_size4_4 mux_right_track_8 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_17 , SYNOPSYS_UNCONNECTED_18 , SYNOPSYS_UNCONNECTED_19 , SYNOPSYS_UNCONNECTED_20 } ) , .out ( chanx_right_out[4] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_96 ) ) ; + .p0 ( optlc_net_114 ) ) ; sb_0__2__mux_2level_tapbuf_size4 mux_right_track_10 ( .in ( { right_bottom_grid_pin_37_[0] , right_bottom_grid_pin_40_[0] , right_bottom_grid_pin_43_[0] , chany_bottom_in[23] } ) , @@ -77981,7 +81152,7 @@ sb_0__2__mux_2level_tapbuf_size4 mux_right_track_10 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_21 , SYNOPSYS_UNCONNECTED_22 , SYNOPSYS_UNCONNECTED_23 , SYNOPSYS_UNCONNECTED_24 } ) , .out ( chanx_right_out[5] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_96 ) ) ; + .p0 ( optlc_net_113 ) ) ; sb_0__2__mux_2level_tapbuf_size4_mem_0 mem_right_track_0 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( mux_2level_tapbuf_size4_mem_0_ccff_tail ) , @@ -78022,163 +81193,163 @@ sb_0__2__mux_2level_tapbuf_size2_0 mux_right_track_12 ( .sram ( mux_2level_tapbuf_size2_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_25 , SYNOPSYS_UNCONNECTED_26 } ) , .out ( chanx_right_out[6] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_96 ) ) ; + .p0 ( optlc_net_116 ) ) ; sb_0__2__mux_2level_tapbuf_size2_1 mux_right_track_14 ( .in ( { right_bottom_grid_pin_36_[0] , chany_bottom_in[21] } ) , .sram ( mux_2level_tapbuf_size2_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_27 , SYNOPSYS_UNCONNECTED_28 } ) , .out ( chanx_right_out[7] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_96 ) ) ; + .p0 ( optlc_net_113 ) ) ; sb_0__2__mux_2level_tapbuf_size2_2 mux_right_track_16 ( .in ( { right_bottom_grid_pin_37_[0] , chany_bottom_in[20] } ) , .sram ( mux_2level_tapbuf_size2_2_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_29 , SYNOPSYS_UNCONNECTED_30 } ) , .out ( chanx_right_out[8] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_96 ) ) ; + .p0 ( optlc_net_115 ) ) ; sb_0__2__mux_2level_tapbuf_size2_3 mux_right_track_18 ( .in ( { right_bottom_grid_pin_38_[0] , chany_bottom_in[19] } ) , .sram ( mux_2level_tapbuf_size2_3_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_31 , SYNOPSYS_UNCONNECTED_32 } ) , .out ( chanx_right_out[9] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_96 ) ) ; + .p0 ( optlc_net_116 ) ) ; sb_0__2__mux_2level_tapbuf_size2_4 mux_right_track_20 ( .in ( { right_bottom_grid_pin_39_[0] , chany_bottom_in[18] } ) , .sram ( mux_2level_tapbuf_size2_4_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_33 , SYNOPSYS_UNCONNECTED_34 } ) , .out ( chanx_right_out[10] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_99 ) ) ; + .p0 ( optlc_net_115 ) ) ; sb_0__2__mux_2level_tapbuf_size2_5 mux_right_track_22 ( .in ( { right_bottom_grid_pin_40_[0] , chany_bottom_in[17] } ) , .sram ( mux_2level_tapbuf_size2_5_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_35 , SYNOPSYS_UNCONNECTED_36 } ) , .out ( chanx_right_out[11] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_97 ) ) ; + .p0 ( optlc_net_114 ) ) ; sb_0__2__mux_2level_tapbuf_size2_6 mux_right_track_24 ( .in ( { right_bottom_grid_pin_41_[0] , chany_bottom_in[16] } ) , .sram ( mux_2level_tapbuf_size2_6_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_37 , SYNOPSYS_UNCONNECTED_38 } ) , .out ( chanx_right_out[12] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_99 ) ) ; + .p0 ( optlc_net_114 ) ) ; sb_0__2__mux_2level_tapbuf_size2_7 mux_right_track_26 ( .in ( { right_bottom_grid_pin_42_[0] , chany_bottom_in[15] } ) , .sram ( mux_2level_tapbuf_size2_7_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_39 , SYNOPSYS_UNCONNECTED_40 } ) , .out ( chanx_right_out[13] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_99 ) ) ; + .p0 ( optlc_net_114 ) ) ; sb_0__2__mux_2level_tapbuf_size2_8 mux_right_track_30 ( .in ( { right_bottom_grid_pin_36_[0] , chany_bottom_in[13] } ) , .sram ( mux_2level_tapbuf_size2_8_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_41 , SYNOPSYS_UNCONNECTED_42 } ) , .out ( chanx_right_out[15] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_96 ) ) ; + .p0 ( optlc_net_117 ) ) ; sb_0__2__mux_2level_tapbuf_size2_9 mux_right_track_32 ( .in ( { right_bottom_grid_pin_37_[0] , chany_bottom_in[12] } ) , .sram ( mux_2level_tapbuf_size2_9_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_43 , SYNOPSYS_UNCONNECTED_44 } ) , .out ( chanx_right_out[16] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_97 ) ) ; + .p0 ( optlc_net_116 ) ) ; sb_0__2__mux_2level_tapbuf_size2_10 mux_right_track_34 ( .in ( { right_bottom_grid_pin_38_[0] , chany_bottom_in[11] } ) , .sram ( mux_2level_tapbuf_size2_10_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_45 , SYNOPSYS_UNCONNECTED_46 } ) , .out ( chanx_right_out[17] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_97 ) ) ; + .p0 ( optlc_net_116 ) ) ; sb_0__2__mux_2level_tapbuf_size2_11 mux_right_track_36 ( .in ( { right_bottom_grid_pin_39_[0] , chany_bottom_in[10] } ) , .sram ( mux_2level_tapbuf_size2_11_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_47 , SYNOPSYS_UNCONNECTED_48 } ) , .out ( chanx_right_out[18] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_99 ) ) ; + .p0 ( optlc_net_117 ) ) ; sb_0__2__mux_2level_tapbuf_size2_12 mux_right_track_38 ( .in ( { right_bottom_grid_pin_40_[0] , chany_bottom_in[9] } ) , .sram ( mux_2level_tapbuf_size2_12_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_49 , SYNOPSYS_UNCONNECTED_50 } ) , .out ( chanx_right_out[19] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_99 ) ) ; + .p0 ( optlc_net_117 ) ) ; sb_0__2__mux_2level_tapbuf_size2_13 mux_right_track_40 ( .in ( { right_bottom_grid_pin_41_[0] , chany_bottom_in[8] } ) , .sram ( mux_2level_tapbuf_size2_13_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_51 , SYNOPSYS_UNCONNECTED_52 } ) , .out ( chanx_right_out[20] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_99 ) ) ; + .p0 ( optlc_net_117 ) ) ; sb_0__2__mux_2level_tapbuf_size2_14 mux_right_track_42 ( .in ( { right_bottom_grid_pin_42_[0] , chany_bottom_in[7] } ) , .sram ( mux_2level_tapbuf_size2_14_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_53 , SYNOPSYS_UNCONNECTED_54 } ) , .out ( chanx_right_out[21] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_99 ) ) ; + .p0 ( optlc_net_116 ) ) ; sb_0__2__mux_2level_tapbuf_size2_15 mux_right_track_44 ( .in ( { right_top_grid_pin_1_[0] , chany_bottom_in[6] } ) , .sram ( mux_2level_tapbuf_size2_15_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_55 , SYNOPSYS_UNCONNECTED_56 } ) , .out ( chanx_right_out[22] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_99 ) ) ; + .p0 ( optlc_net_116 ) ) ; sb_0__2__mux_2level_tapbuf_size2_16 mux_right_track_46 ( .in ( { right_bottom_grid_pin_36_[0] , chany_bottom_in[5] } ) , .sram ( mux_2level_tapbuf_size2_16_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_57 , SYNOPSYS_UNCONNECTED_58 } ) , .out ( chanx_right_out[23] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_99 ) ) ; + .p0 ( optlc_net_117 ) ) ; sb_0__2__mux_2level_tapbuf_size2_17 mux_right_track_48 ( .in ( { right_bottom_grid_pin_37_[0] , chany_bottom_in[4] } ) , .sram ( mux_2level_tapbuf_size2_17_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_59 , SYNOPSYS_UNCONNECTED_60 } ) , .out ( chanx_right_out[24] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_99 ) ) ; + .p0 ( optlc_net_116 ) ) ; sb_0__2__mux_2level_tapbuf_size2_18 mux_right_track_50 ( .in ( { right_bottom_grid_pin_38_[0] , chany_bottom_in[3] } ) , .sram ( mux_2level_tapbuf_size2_18_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_61 , SYNOPSYS_UNCONNECTED_62 } ) , .out ( chanx_right_out[25] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_99 ) ) ; + .p0 ( optlc_net_115 ) ) ; sb_0__2__mux_2level_tapbuf_size2_19 mux_right_track_54 ( .in ( { right_bottom_grid_pin_40_[0] , chany_bottom_in[1] } ) , .sram ( mux_2level_tapbuf_size2_19_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_63 , SYNOPSYS_UNCONNECTED_64 } ) , .out ( chanx_right_out[27] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_98 ) ) ; + .p0 ( optlc_net_114 ) ) ; sb_0__2__mux_2level_tapbuf_size2_20 mux_right_track_56 ( .in ( { right_bottom_grid_pin_41_[0] , chany_bottom_in[0] } ) , .sram ( mux_2level_tapbuf_size2_20_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_65 , SYNOPSYS_UNCONNECTED_66 } ) , .out ( chanx_right_out[28] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_96 ) ) ; + .p0 ( optlc_net_114 ) ) ; sb_0__2__mux_2level_tapbuf_size2_21 mux_right_track_58 ( .in ( { right_bottom_grid_pin_42_[0] , chany_bottom_in[29] } ) , .sram ( mux_2level_tapbuf_size2_21_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_67 , SYNOPSYS_UNCONNECTED_68 } ) , .out ( chanx_right_out[29] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_99 ) ) ; + .p0 ( optlc_net_113 ) ) ; sb_0__2__mux_2level_tapbuf_size2_22 mux_bottom_track_1 ( .in ( { chanx_right_in[28] , bottom_left_grid_pin_1_[0] } ) , .sram ( mux_2level_tapbuf_size2_22_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_69 , SYNOPSYS_UNCONNECTED_70 } ) , .out ( chany_bottom_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_97 ) ) ; + .p0 ( optlc_net_112 ) ) ; sb_0__2__mux_2level_tapbuf_size2_23 mux_bottom_track_7 ( .in ( { chanx_right_in[25] , bottom_left_grid_pin_1_[0] } ) , .sram ( mux_2level_tapbuf_size2_23_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_71 , SYNOPSYS_UNCONNECTED_72 } ) , .out ( chany_bottom_out[3] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_97 ) ) ; + .p0 ( optlc_net_112 ) ) ; sb_0__2__mux_2level_tapbuf_size2_24 mux_bottom_track_13 ( .in ( { chanx_right_in[22] , bottom_left_grid_pin_1_[0] } ) , .sram ( mux_2level_tapbuf_size2_24_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_73 , SYNOPSYS_UNCONNECTED_74 } ) , .out ( chany_bottom_out[6] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_97 ) ) ; + .p0 ( optlc_net_112 ) ) ; sb_0__2__mux_2level_tapbuf_size2_25 mux_bottom_track_29 ( .in ( { chanx_right_in[14] , bottom_left_grid_pin_1_[0] } ) , .sram ( mux_2level_tapbuf_size2_25_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_75 , SYNOPSYS_UNCONNECTED_76 } ) , .out ( chany_bottom_out[14] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_97 ) ) ; + .p0 ( optlc_net_112 ) ) ; sb_0__2__mux_2level_tapbuf_size2 mux_bottom_track_45 ( .in ( { chanx_right_in[6] , bottom_left_grid_pin_1_[0] } ) , .sram ( mux_2level_tapbuf_size2_26_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_77 , SYNOPSYS_UNCONNECTED_78 } ) , .out ( chany_bottom_out[22] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_97 ) ) ; + .p0 ( optlc_net_112 ) ) ; sb_0__2__mux_2level_tapbuf_size2_mem_0 mem_right_track_12 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( mux_2level_tapbuf_size4_mem_5_ccff_tail ) , @@ -78346,14 +81517,14 @@ sb_0__2__mux_2level_tapbuf_size3_0 mux_right_track_28 ( .sram ( mux_2level_tapbuf_size3_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_79 , SYNOPSYS_UNCONNECTED_80 } ) , .out ( chanx_right_out[14] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_99 ) ) ; + .p0 ( optlc_net_115 ) ) ; sb_0__2__mux_2level_tapbuf_size3 mux_right_track_52 ( .in ( { right_bottom_grid_pin_39_[0] , right_bottom_grid_pin_43_[0] , chany_bottom_in[2] } ) , .sram ( mux_2level_tapbuf_size3_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_81 , SYNOPSYS_UNCONNECTED_82 } ) , .out ( chanx_right_out[26] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_96 ) ) ; + .p0 ( optlc_net_114 ) ) ; sb_0__2__mux_2level_tapbuf_size3_mem_0 mem_right_track_28 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( mux_2level_tapbuf_size2_mem_7_ccff_tail ) , @@ -78368,8 +81539,8 @@ sb_0__2__mux_2level_tapbuf_size3_mem mem_right_track_52 ( .pReset ( pReset ) , .VSS ( VSS ) ) ; sky130_fd_sc_hd__buf_8 pReset_FTB00 ( .A ( pReset_E_in ) , .X ( pReset[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_6 pReset_S_FTB01 ( .A ( pReset_E_in ) , - .X ( pReset_S_out ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_115 ( .LO ( SYNOPSYS_UNCONNECTED_83 ) , + .HI ( optlc_net_112 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_1 prog_clk_0_FTB00 ( .A ( prog_clk_0_E_in ) , .X ( prog_clk[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_8 FTB_48__47 ( .A ( chanx_right_in[0] ) , @@ -78392,16 +81563,16 @@ sky130_fd_sc_hd__buf_8 FTB_56__55 ( .A ( chanx_right_in[9] ) , .X ( chany_bottom_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_8 FTB_57__56 ( .A ( chanx_right_in[10] ) , .X ( chany_bottom_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_6 FTB_58__57 ( .A ( chanx_right_in[11] ) , - .X ( ropt_net_134 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_58__57 ( .A ( chanx_right_in[11] ) , + .X ( chany_bottom_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_8 FTB_59__58 ( .A ( chanx_right_in[12] ) , .X ( chany_bottom_out[16] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_8 FTB_60__59 ( .A ( chanx_right_in[13] ) , .X ( chany_bottom_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_8 FTB_61__60 ( .A ( chanx_right_in[15] ) , .X ( chany_bottom_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_6 FTB_62__61 ( .A ( chanx_right_in[16] ) , - .X ( ropt_net_132 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_62__61 ( .A ( chanx_right_in[16] ) , + .X ( chany_bottom_out[12] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_8 FTB_63__62 ( .A ( chanx_right_in[17] ) , .X ( chany_bottom_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_8 FTB_64__63 ( .A ( chanx_right_in[18] ) , @@ -78416,7 +81587,7 @@ sky130_fd_sc_hd__buf_8 FTB_68__67 ( .A ( chanx_right_in[23] ) , .X ( chany_bottom_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_8 FTB_69__68 ( .A ( chanx_right_in[24] ) , .X ( chany_bottom_out[4] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_8 FTB_70__69 ( .A ( chanx_right_in[26] ) , +sky130_fd_sc_hd__buf_6 FTB_70__69 ( .A ( chanx_right_in[26] ) , .X ( chany_bottom_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_8 FTB_71__70 ( .A ( chanx_right_in[27] ) , .X ( chany_bottom_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -78424,18 +81595,20 @@ sky130_fd_sc_hd__buf_8 FTB_72__71 ( .A ( chanx_right_in[29] ) , .X ( chany_bottom_out[29] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_6 FTB_73__72 ( .A ( SC_IN_TOP ) , .X ( SC_OUT_BOT ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_98 ( .LO ( SYNOPSYS_UNCONNECTED_83 ) , - .HI ( optlc_net_96 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_100 ( .LO ( SYNOPSYS_UNCONNECTED_84 ) , - .HI ( optlc_net_97 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_102 ( .LO ( SYNOPSYS_UNCONNECTED_85 ) , - .HI ( optlc_net_98 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_104 ( .LO ( SYNOPSYS_UNCONNECTED_86 ) , - .HI ( optlc_net_99 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_8 ropt_mt_inst_1311 ( .A ( ropt_net_132 ) , - .X ( chany_bottom_out[12] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_8 ropt_mt_inst_1313 ( .A ( ropt_net_134 ) , - .X ( chany_bottom_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_102 ( .A ( BUF_net_103 ) , .Y ( pReset_S_out ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_103 ( .A ( pReset_E_in ) , .Y ( BUF_net_103 ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_117 ( .LO ( SYNOPSYS_UNCONNECTED_84 ) , + .HI ( optlc_net_113 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_119 ( .LO ( SYNOPSYS_UNCONNECTED_85 ) , + .HI ( optlc_net_114 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_122 ( .LO ( SYNOPSYS_UNCONNECTED_86 ) , + .HI ( optlc_net_115 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_124 ( .LO ( SYNOPSYS_UNCONNECTED_87 ) , + .HI ( optlc_net_116 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_126 ( .LO ( SYNOPSYS_UNCONNECTED_88 ) , + .HI ( optlc_net_117 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -78695,10 +81868,10 @@ sb_0__1__mux_2level_tapbuf_basis_input2_mem1 mux_l2_in_0_ ( .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_216 ( .A ( BUF_net_217 ) , .Y ( out[0] ) , +sky130_fd_sc_hd__inv_8 BINV_R_209 ( .A ( BUF_net_210 ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_217 ( - .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_217 ) , +sky130_fd_sc_hd__inv_1 BINV_R_210 ( + .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_210 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -78837,10 +82010,10 @@ sb_0__1__mux_2level_tapbuf_basis_input2_mem1_41 mux_l2_in_0_ ( .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_214 ( .A ( BUF_net_215 ) , .Y ( out[0] ) , +sky130_fd_sc_hd__inv_8 BINV_R_201 ( .A ( BUF_net_202 ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_215 ( - .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_215 ) , +sky130_fd_sc_hd__inv_1 BINV_R_202 ( + .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_202 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -79049,10 +82222,10 @@ sb_0__1__mux_2level_tapbuf_basis_input2_mem1_35 mux_l2_in_0_ ( .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_212 ( .A ( BUF_net_213 ) , .Y ( out[0] ) , +sky130_fd_sc_hd__inv_8 BINV_R_199 ( .A ( BUF_net_200 ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_213 ( - .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_213 ) , +sky130_fd_sc_hd__inv_1 BINV_R_200 ( + .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_200 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -79121,10 +82294,10 @@ sb_0__1__mux_2level_tapbuf_basis_input2_mem1_33 mux_l2_in_0_ ( .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_210 ( .A ( BUF_net_211 ) , .Y ( out[0] ) , +sky130_fd_sc_hd__inv_8 BINV_R_197 ( .A ( BUF_net_198 ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_211 ( - .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_211 ) , +sky130_fd_sc_hd__inv_1 BINV_R_198 ( + .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_198 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -79181,9 +82354,6 @@ wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; sb_0__1__mux_2level_tapbuf_basis_input2_mem1_30 mux_l1_in_0_ ( .in ( in ) , .mem ( sram[0] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) , @@ -79196,6 +82366,11 @@ sb_0__1__mux_2level_tapbuf_basis_input2_mem1_31 mux_l2_in_0_ ( .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_195 ( .A ( BUF_net_196 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_196 ( + .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_196 ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -79641,7 +82816,7 @@ input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__mux2_2 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) , +sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -79718,8 +82893,10 @@ sb_0__1__mux_2level_tapbuf_basis_input2_mem1_23 mux_l2_in_0_ ( .mem_inv ( { SYNOPSYS_UNCONNECTED_4 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_2_out ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_209 ( - .A ( mux_2level_tapbuf_basis_input2_mem1_2_out[0] ) , .X ( out[0] ) , +sky130_fd_sc_hd__inv_8 BINV_R_193 ( .A ( BUF_net_194 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_194 ( + .A ( mux_2level_tapbuf_basis_input2_mem1_2_out[0] ) , .Y ( BUF_net_194 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -79795,6 +82972,9 @@ wire [0:0] mux_2level_tapbuf_basis_input2_mem1_2_out ; supply1 VDD ; supply0 VSS ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( mux_2level_tapbuf_basis_input2_mem1_2_out[0] ) , .X ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; sb_0__1__mux_2level_tapbuf_basis_input2_mem1_18 mux_l1_in_0_ ( .in ( in[0:1] ) , .mem ( sram[0] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) , @@ -79813,9 +82993,6 @@ sb_0__1__mux_2level_tapbuf_basis_input2_mem1_20 mux_l2_in_0_ ( .mem_inv ( { SYNOPSYS_UNCONNECTED_4 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_2_out ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_208 ( - .A ( mux_2level_tapbuf_basis_input2_mem1_2_out[0] ) , .X ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -79831,7 +83008,7 @@ input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__mux2_2 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) , +sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -79890,9 +83067,6 @@ wire [0:0] mux_2level_tapbuf_basis_input2_mem1_2_out ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( mux_2level_tapbuf_basis_input2_mem1_2_out[0] ) , .X ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; sb_0__1__mux_2level_tapbuf_basis_input2_mem1_15 mux_l1_in_0_ ( .in ( in[0:1] ) , .mem ( sram[0] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) , @@ -79911,6 +83085,11 @@ sb_0__1__mux_2level_tapbuf_basis_input2_mem1_17 mux_l2_in_0_ ( .mem_inv ( { SYNOPSYS_UNCONNECTED_4 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_2_out ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_213 ( .A ( BUF_net_214 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_214 ( + .A ( mux_2level_tapbuf_basis_input2_mem1_2_out[0] ) , .Y ( BUF_net_214 ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -79926,7 +83105,7 @@ input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__mux2_2 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) , +sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -79985,9 +83164,6 @@ wire [0:0] mux_2level_tapbuf_basis_input2_mem1_2_out ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( mux_2level_tapbuf_basis_input2_mem1_2_out[0] ) , .X ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; sb_0__1__mux_2level_tapbuf_basis_input2_mem1_12 mux_l1_in_0_ ( .in ( in[0:1] ) , .mem ( sram[0] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) , @@ -80006,6 +83182,11 @@ sb_0__1__mux_2level_tapbuf_basis_input2_mem1_14 mux_l2_in_0_ ( .mem_inv ( { SYNOPSYS_UNCONNECTED_4 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_2_out ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_191 ( .A ( BUF_net_192 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_192 ( + .A ( mux_2level_tapbuf_basis_input2_mem1_2_out[0] ) , .Y ( BUF_net_192 ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -80021,7 +83202,7 @@ input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__mux2_2 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) , +sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -80098,8 +83279,10 @@ sb_0__1__mux_2level_tapbuf_basis_input2_mem1_11 mux_l2_in_0_ ( .mem_inv ( { SYNOPSYS_UNCONNECTED_4 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_2_out ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_207 ( - .A ( mux_2level_tapbuf_basis_input2_mem1_2_out[0] ) , .X ( out[0] ) , +sky130_fd_sc_hd__inv_8 BINV_R_207 ( .A ( BUF_net_208 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_208 ( + .A ( mux_2level_tapbuf_basis_input2_mem1_2_out[0] ) , .Y ( BUF_net_208 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -80116,7 +83299,7 @@ input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) , +sky130_fd_sc_hd__mux2_2 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -80175,6 +83358,9 @@ wire [0:0] mux_2level_tapbuf_basis_input2_mem1_2_out ; supply1 VDD ; supply0 VSS ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( mux_2level_tapbuf_basis_input2_mem1_2_out[0] ) , .X ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; sb_0__1__mux_2level_tapbuf_basis_input2_mem1_6 mux_l1_in_0_ ( .in ( in[0:1] ) , .mem ( sram[0] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) , @@ -80193,11 +83379,6 @@ sb_0__1__mux_2level_tapbuf_basis_input2_mem1_8 mux_l2_in_0_ ( .mem_inv ( { SYNOPSYS_UNCONNECTED_4 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_2_out ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_205 ( .A ( BUF_net_206 ) , .Y ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_206 ( - .A ( mux_2level_tapbuf_basis_input2_mem1_2_out[0] ) , .Y ( BUF_net_206 ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -80272,6 +83453,9 @@ wire [0:0] mux_2level_tapbuf_basis_input2_mem1_2_out ; supply1 VDD ; supply0 VSS ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( mux_2level_tapbuf_basis_input2_mem1_2_out[0] ) , .X ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; sb_0__1__mux_2level_tapbuf_basis_input2_mem1_3 mux_l1_in_0_ ( .in ( in[0:1] ) , .mem ( sram[0] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) , @@ -80290,11 +83474,6 @@ sb_0__1__mux_2level_tapbuf_basis_input2_mem1_5 mux_l2_in_0_ ( .mem_inv ( { SYNOPSYS_UNCONNECTED_4 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_2_out ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_203 ( .A ( BUF_net_204 ) , .Y ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_204 ( - .A ( mux_2level_tapbuf_basis_input2_mem1_2_out[0] ) , .Y ( BUF_net_204 ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -80369,6 +83548,9 @@ wire [0:0] mux_2level_tapbuf_basis_input2_mem1_2_out ; supply1 VDD ; supply0 VSS ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( mux_2level_tapbuf_basis_input2_mem1_2_out[0] ) , .X ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; sb_0__1__mux_2level_tapbuf_basis_input2_mem1_0 mux_l1_in_0_ ( .in ( in[0:1] ) , .mem ( sram[0] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) , @@ -80387,11 +83569,6 @@ sb_0__1__mux_2level_tapbuf_basis_input2_mem1_2 mux_l2_in_0_ ( .mem_inv ( { SYNOPSYS_UNCONNECTED_4 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_2_out ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_201 ( .A ( BUF_net_202 ) , .Y ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_202 ( - .A ( mux_2level_tapbuf_basis_input2_mem1_2_out[0] ) , .Y ( BUF_net_202 ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -80765,13 +83942,16 @@ input VDD ; input VSS ; input p0 ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -80784,13 +83964,16 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -80863,6 +84046,9 @@ wire [0:0] mux_2level_tapbuf_basis_input3_mem3_1_out ; supply1 VDD ; supply0 VSS ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .X ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; sb_0__1__local_encoder2to3_62 local_encoder2to3_0_ ( .addr ( sram[0:1] ) , .data ( local_encoder2to3_0_data ) , .data_inv ( local_encoder2to3_0_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; @@ -80881,11 +84067,6 @@ sb_0__1__mux_2level_tapbuf_basis_input3_mem3 mux_l2_in_0_ ( .mem_inv ( local_encoder2to3_1_data_inv ) , .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_199 ( .A ( BUF_net_200 ) , .Y ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_200 ( - .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_200 ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -80899,13 +84080,16 @@ input VDD ; input VSS ; input p0 ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -80918,13 +84102,16 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -81031,13 +84218,16 @@ input VDD ; input VSS ; input p0 ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -81050,13 +84240,16 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -81129,9 +84322,6 @@ wire [0:0] mux_2level_tapbuf_basis_input3_mem3_1_out ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .X ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; sb_0__1__local_encoder2to3_58 local_encoder2to3_0_ ( .addr ( sram[0:1] ) , .data ( local_encoder2to3_0_data ) , .data_inv ( local_encoder2to3_0_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; @@ -81150,6 +84340,11 @@ sb_0__1__mux_2level_tapbuf_basis_input3_mem3_67 mux_l2_in_0_ ( .mem_inv ( local_encoder2to3_1_data_inv ) , .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_189 ( .A ( BUF_net_190 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_190 ( + .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_190 ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -81163,13 +84358,16 @@ input VDD ; input VSS ; input p0 ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -81182,13 +84380,16 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -81261,6 +84462,9 @@ wire [0:0] mux_2level_tapbuf_basis_input3_mem3_1_out ; supply1 VDD ; supply0 VSS ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .X ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; sb_0__1__local_encoder2to3_56 local_encoder2to3_0_ ( .addr ( sram[0:1] ) , .data ( local_encoder2to3_0_data ) , .data_inv ( local_encoder2to3_0_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; @@ -81279,11 +84483,6 @@ sb_0__1__mux_2level_tapbuf_basis_input3_mem3_65 mux_l2_in_0_ ( .mem_inv ( local_encoder2to3_1_data_inv ) , .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_197 ( .A ( BUF_net_198 ) , .Y ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_198 ( - .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_198 ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -81297,13 +84496,16 @@ input VDD ; input VSS ; input p0 ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -81316,13 +84518,16 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -81413,10 +84618,8 @@ sb_0__1__mux_2level_tapbuf_basis_input3_mem3_63 mux_l2_in_0_ ( .mem_inv ( local_encoder2to3_1_data_inv ) , .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_195 ( .A ( BUF_net_196 ) , .Y ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_196 ( - .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_196 ) , +sky130_fd_sc_hd__buf_6 BUFT_RR_188 ( + .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -81431,13 +84634,16 @@ input VDD ; input VSS ; input p0 ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -81450,13 +84656,16 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -81547,10 +84756,10 @@ sb_0__1__mux_2level_tapbuf_basis_input3_mem3_61 mux_l2_in_0_ ( .mem_inv ( local_encoder2to3_1_data_inv ) , .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_193 ( .A ( BUF_net_194 ) , .Y ( out[0] ) , +sky130_fd_sc_hd__inv_8 BINV_R_186 ( .A ( BUF_net_187 ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_194 ( - .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_194 ) , +sky130_fd_sc_hd__inv_1 BINV_R_187 ( + .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_187 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -81565,13 +84774,16 @@ input VDD ; input VSS ; input p0 ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -81584,13 +84796,16 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -81681,10 +84896,10 @@ sb_0__1__mux_2level_tapbuf_basis_input3_mem3_59 mux_l2_in_0_ ( .mem_inv ( local_encoder2to3_1_data_inv ) , .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_191 ( .A ( BUF_net_192 ) , .Y ( out[0] ) , +sky130_fd_sc_hd__inv_8 BINV_R_184 ( .A ( BUF_net_185 ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_192 ( - .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_192 ) , +sky130_fd_sc_hd__inv_1 BINV_R_185 ( + .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_185 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -81699,13 +84914,16 @@ input VDD ; input VSS ; input p0 ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -81718,13 +84936,16 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -81815,10 +85036,10 @@ sb_0__1__mux_2level_tapbuf_basis_input3_mem3_57 mux_l2_in_0_ ( .mem_inv ( local_encoder2to3_1_data_inv ) , .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_189 ( .A ( BUF_net_190 ) , .Y ( out[0] ) , +sky130_fd_sc_hd__inv_8 BINV_R_182 ( .A ( BUF_net_183 ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_190 ( - .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_190 ) , +sky130_fd_sc_hd__inv_1 BINV_R_183 ( + .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_183 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -81833,13 +85054,16 @@ input VDD ; input VSS ; input p0 ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -81852,13 +85076,16 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -81949,10 +85176,10 @@ sb_0__1__mux_2level_tapbuf_basis_input3_mem3_55 mux_l2_in_0_ ( .mem_inv ( local_encoder2to3_1_data_inv ) , .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_187 ( .A ( BUF_net_188 ) , .Y ( out[0] ) , +sky130_fd_sc_hd__inv_8 BINV_R_180 ( .A ( BUF_net_181 ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_188 ( - .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_188 ) , +sky130_fd_sc_hd__inv_1 BINV_R_181 ( + .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_181 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -81967,13 +85194,16 @@ input VDD ; input VSS ; input p0 ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -81986,13 +85216,16 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -82083,10 +85316,10 @@ sb_0__1__mux_2level_tapbuf_basis_input3_mem3_53 mux_l2_in_0_ ( .mem_inv ( local_encoder2to3_1_data_inv ) , .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_185 ( .A ( BUF_net_186 ) , .Y ( out[0] ) , +sky130_fd_sc_hd__inv_8 BINV_R_178 ( .A ( BUF_net_179 ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_186 ( - .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_186 ) , +sky130_fd_sc_hd__inv_1 BINV_R_179 ( + .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_179 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -82101,13 +85334,16 @@ input VDD ; input VSS ; input p0 ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -82120,13 +85356,16 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -82199,6 +85438,9 @@ wire [0:0] mux_2level_tapbuf_basis_input3_mem3_1_out ; supply1 VDD ; supply0 VSS ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .X ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; sb_0__1__local_encoder2to3_42 local_encoder2to3_0_ ( .addr ( sram[0:1] ) , .data ( local_encoder2to3_0_data ) , .data_inv ( local_encoder2to3_0_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; @@ -82217,9 +85459,6 @@ sb_0__1__mux_2level_tapbuf_basis_input3_mem3_51 mux_l2_in_0_ ( .mem_inv ( local_encoder2to3_1_data_inv ) , .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_184 ( - .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .X ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -82233,13 +85472,16 @@ input VDD ; input VSS ; input p0 ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -82252,13 +85494,16 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -82349,10 +85594,8 @@ sb_0__1__mux_2level_tapbuf_basis_input3_mem3_49 mux_l2_in_0_ ( .mem_inv ( local_encoder2to3_1_data_inv ) , .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_182 ( .A ( BUF_net_183 ) , .Y ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_183 ( - .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_183 ) , +sky130_fd_sc_hd__buf_6 BUFT_RR_177 ( + .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -82726,12 +85969,15 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -82745,13 +85991,16 @@ input VDD ; input VSS ; input p0 ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -82764,13 +86013,16 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -82844,9 +86096,6 @@ wire [0:0] mux_2level_tapbuf_basis_input3_mem3_1_out ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .X ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; sb_0__1__local_encoder2to3_38 local_encoder2to3_0_ ( .addr ( sram[0:1] ) , .data ( local_encoder2to3_0_data ) , .data_inv ( local_encoder2to3_0_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; @@ -82871,6 +86120,11 @@ sb_0__1__mux_2level_tapbuf_basis_input2_mem2 mux_l1_in_1_ ( .in ( in[3:4] ) , .mem_inv ( local_encoder2to3_0_data_inv[0:1] ) , .out ( mux_2level_tapbuf_basis_input2_mem2_0_out ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_205 ( .A ( BUF_net_206 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_206 ( + .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_206 ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -82883,12 +86137,15 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -82902,13 +86159,16 @@ input VDD ; input VSS ; input p0 ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -82921,13 +86181,16 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -83040,12 +86303,15 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -83059,13 +86325,16 @@ input VDD ; input VSS ; input p0 ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -83078,13 +86347,16 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -83182,10 +86454,10 @@ sb_0__1__mux_2level_tapbuf_basis_input2_mem2_9 mux_l1_in_1_ ( .mem_inv ( local_encoder2to3_0_data_inv[0:1] ) , .out ( mux_2level_tapbuf_basis_input2_mem2_0_out ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_180 ( .A ( BUF_net_181 ) , .Y ( out[0] ) , +sky130_fd_sc_hd__inv_8 BINV_R_175 ( .A ( BUF_net_176 ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_181 ( - .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_181 ) , +sky130_fd_sc_hd__inv_1 BINV_R_176 ( + .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_176 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -83199,12 +86471,15 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -83218,13 +86493,16 @@ input VDD ; input VSS ; input p0 ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -83237,13 +86515,16 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -83341,10 +86622,10 @@ sb_0__1__mux_2level_tapbuf_basis_input2_mem2_8 mux_l1_in_1_ ( .mem_inv ( local_encoder2to3_0_data_inv[0:1] ) , .out ( mux_2level_tapbuf_basis_input2_mem2_0_out ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_178 ( .A ( BUF_net_179 ) , .Y ( out[0] ) , +sky130_fd_sc_hd__inv_8 BINV_R_173 ( .A ( BUF_net_174 ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_179 ( - .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_179 ) , +sky130_fd_sc_hd__inv_1 BINV_R_174 ( + .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_174 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -83358,12 +86639,15 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -83377,13 +86661,16 @@ input VDD ; input VSS ; input p0 ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -83396,13 +86683,16 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -83515,12 +86805,15 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -83534,13 +86827,16 @@ input VDD ; input VSS ; input p0 ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -83553,13 +86849,16 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -83657,10 +86956,10 @@ sb_0__1__mux_2level_tapbuf_basis_input2_mem2_6 mux_l1_in_1_ ( .mem_inv ( local_encoder2to3_0_data_inv[0:1] ) , .out ( mux_2level_tapbuf_basis_input2_mem2_0_out ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_176 ( .A ( BUF_net_177 ) , .Y ( out[0] ) , +sky130_fd_sc_hd__inv_8 BINV_R_171 ( .A ( BUF_net_172 ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_177 ( - .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_177 ) , +sky130_fd_sc_hd__inv_1 BINV_R_172 ( + .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_172 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -83674,12 +86973,15 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -83693,13 +86995,16 @@ input VDD ; input VSS ; input p0 ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -83712,13 +87017,16 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -83816,10 +87124,10 @@ sb_0__1__mux_2level_tapbuf_basis_input2_mem2_5 mux_l1_in_1_ ( .mem_inv ( local_encoder2to3_0_data_inv[0:1] ) , .out ( mux_2level_tapbuf_basis_input2_mem2_0_out ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_174 ( .A ( BUF_net_175 ) , .Y ( out[0] ) , +sky130_fd_sc_hd__inv_8 BINV_R_169 ( .A ( BUF_net_170 ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_175 ( - .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_175 ) , +sky130_fd_sc_hd__inv_1 BINV_R_170 ( + .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_170 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -83833,12 +87141,15 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -83852,13 +87163,16 @@ input VDD ; input VSS ; input p0 ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -83871,13 +87185,16 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -83975,10 +87292,8 @@ sb_0__1__mux_2level_tapbuf_basis_input2_mem2_4 mux_l1_in_1_ ( .mem_inv ( local_encoder2to3_0_data_inv[0:1] ) , .out ( mux_2level_tapbuf_basis_input2_mem2_0_out ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_172 ( .A ( BUF_net_173 ) , .Y ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_173 ( - .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_173 ) , +sky130_fd_sc_hd__buf_6 BUFT_RR_168 ( + .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -83992,12 +87307,15 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -84011,13 +87329,16 @@ input VDD ; input VSS ; input p0 ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -84030,13 +87351,16 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -84110,9 +87434,6 @@ wire [0:0] mux_2level_tapbuf_basis_input3_mem3_1_out ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .X ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; sb_0__1__local_encoder2to3_22 local_encoder2to3_0_ ( .addr ( sram[0:1] ) , .data ( local_encoder2to3_0_data ) , .data_inv ( local_encoder2to3_0_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; @@ -84137,6 +87458,11 @@ sb_0__1__mux_2level_tapbuf_basis_input2_mem2_3 mux_l1_in_1_ ( .mem_inv ( local_encoder2to3_0_data_inv[0:1] ) , .out ( mux_2level_tapbuf_basis_input2_mem2_0_out ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_166 ( .A ( BUF_net_167 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_167 ( + .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_167 ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -84149,12 +87475,15 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -84168,13 +87497,16 @@ input VDD ; input VSS ; input p0 ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -84187,13 +87519,16 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -84291,10 +87626,10 @@ sb_0__1__mux_2level_tapbuf_basis_input2_mem2_2 mux_l1_in_1_ ( .mem_inv ( local_encoder2to3_0_data_inv[0:1] ) , .out ( mux_2level_tapbuf_basis_input2_mem2_0_out ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_170 ( .A ( BUF_net_171 ) , .Y ( out[0] ) , +sky130_fd_sc_hd__inv_8 BINV_R_164 ( .A ( BUF_net_165 ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_171 ( - .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_171 ) , +sky130_fd_sc_hd__inv_1 BINV_R_165 ( + .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_165 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -84308,12 +87643,15 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -84327,13 +87665,16 @@ input VDD ; input VSS ; input p0 ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -84346,13 +87687,16 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -84450,10 +87794,8 @@ sb_0__1__mux_2level_tapbuf_basis_input2_mem2_1 mux_l1_in_1_ ( .mem_inv ( local_encoder2to3_0_data_inv[0:1] ) , .out ( mux_2level_tapbuf_basis_input2_mem2_0_out ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_168 ( .A ( BUF_net_169 ) , .Y ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_169 ( - .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_169 ) , +sky130_fd_sc_hd__buf_6 BUFT_RR_163 ( + .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -84467,12 +87809,15 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -84486,13 +87831,16 @@ input VDD ; input VSS ; input p0 ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -84505,13 +87853,16 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -84609,10 +87960,10 @@ sb_0__1__mux_2level_tapbuf_basis_input2_mem2_0 mux_l1_in_1_ ( .mem_inv ( local_encoder2to3_0_data_inv[0:1] ) , .out ( mux_2level_tapbuf_basis_input2_mem2_0_out ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_218 ( .A ( BUF_net_219 ) , .Y ( out[0] ) , +sky130_fd_sc_hd__inv_8 BINV_R_203 ( .A ( BUF_net_204 ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_219 ( - .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_219 ) , +sky130_fd_sc_hd__inv_1 BINV_R_204 ( + .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_204 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -84840,7 +88191,7 @@ input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ropt_net_245 ) , +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ropt_net_236 ) , .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , @@ -84854,34 +88205,26 @@ sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_1 FTB_17__16 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1417 ( .A ( ccff_head[0] ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1412 ( .A ( ccff_head[0] ) , + .X ( copt_net_222 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1413 ( .A ( copt_net_224 ) , + .X ( copt_net_223 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1414 ( .A ( copt_net_222 ) , + .X ( copt_net_224 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1415 ( .A ( copt_net_226 ) , + .X ( copt_net_225 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1416 ( .A ( ropt_net_238 ) , + .X ( copt_net_226 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1417 ( .A ( copt_net_223 ) , .X ( copt_net_227 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1418 ( .A ( ropt_net_249 ) , - .X ( copt_net_228 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1419 ( .A ( copt_net_228 ) , - .X ( copt_net_229 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1420 ( .A ( copt_net_229 ) , - .X ( copt_net_230 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1421 ( .A ( ropt_net_248 ) , - .X ( copt_net_231 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1422 ( .A ( copt_net_230 ) , - .X ( copt_net_232 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1432 ( .A ( copt_net_231 ) , - .X ( ropt_net_243 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1433 ( .A ( ropt_net_243 ) , - .X ( ropt_net_244 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1434 ( .A ( ropt_net_246 ) , - .X ( ropt_net_245 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_2 ropt_h_inst_1435 ( .A ( ropt_net_244 ) , - .X ( ropt_net_246 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1436 ( .A ( copt_net_232 ) , - .X ( ropt_net_247 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1437 ( .A ( ropt_net_247 ) , - .X ( ropt_net_248 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1438 ( .A ( ropt_net_250 ) , - .X ( ropt_net_249 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_2 ropt_h_inst_1439 ( .A ( copt_net_227 ) , - .X ( ropt_net_250 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 ropt_h_inst_1426 ( .A ( ropt_net_239 ) , + .X ( ropt_net_236 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1427 ( .A ( copt_net_227 ) , + .X ( ropt_net_237 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1428 ( .A ( ropt_net_237 ) , + .X ( ropt_net_238 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 ropt_h_inst_1429 ( .A ( copt_net_225 ) , + .X ( ropt_net_239 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -84895,13 +88238,16 @@ input VDD ; input VSS ; input p0 ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -84914,13 +88260,16 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -84933,13 +88282,16 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -85013,6 +88365,9 @@ wire [0:0] mux_2level_tapbuf_basis_input3_mem3_2_out ; supply1 VDD ; supply0 VSS ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( mux_2level_tapbuf_basis_input3_mem3_2_out[0] ) , .X ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; sb_0__1__local_encoder2to3_14 local_encoder2to3_0_ ( .addr ( sram[0:1] ) , .data ( local_encoder2to3_0_data ) , .data_inv ( local_encoder2to3_0_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; @@ -85037,11 +88392,6 @@ sb_0__1__mux_2level_tapbuf_basis_input3_mem3_23 mux_l2_in_0_ ( .mem_inv ( local_encoder2to3_1_data_inv ) , .out ( mux_2level_tapbuf_basis_input3_mem3_2_out ) , .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_166 ( .A ( BUF_net_167 ) , .Y ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_167 ( - .A ( mux_2level_tapbuf_basis_input3_mem3_2_out[0] ) , .Y ( BUF_net_167 ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -85055,13 +88405,16 @@ input VDD ; input VSS ; input p0 ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -85074,13 +88427,16 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -85093,13 +88449,16 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -85197,10 +88556,10 @@ sb_0__1__mux_2level_tapbuf_basis_input3_mem3_20 mux_l2_in_0_ ( .mem_inv ( local_encoder2to3_1_data_inv ) , .out ( mux_2level_tapbuf_basis_input3_mem3_2_out ) , .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_164 ( .A ( BUF_net_165 ) , .Y ( out[0] ) , +sky130_fd_sc_hd__inv_8 BINV_R_161 ( .A ( BUF_net_162 ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_165 ( - .A ( mux_2level_tapbuf_basis_input3_mem3_2_out[0] ) , .Y ( BUF_net_165 ) , +sky130_fd_sc_hd__inv_1 BINV_R_162 ( + .A ( mux_2level_tapbuf_basis_input3_mem3_2_out[0] ) , .Y ( BUF_net_162 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -85215,13 +88574,16 @@ input VDD ; input VSS ; input p0 ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -85234,13 +88596,16 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -85253,13 +88618,16 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -85357,10 +88725,10 @@ sb_0__1__mux_2level_tapbuf_basis_input3_mem3_17 mux_l2_in_0_ ( .mem_inv ( local_encoder2to3_1_data_inv ) , .out ( mux_2level_tapbuf_basis_input3_mem3_2_out ) , .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_162 ( .A ( BUF_net_163 ) , .Y ( out[0] ) , +sky130_fd_sc_hd__inv_8 BINV_R_159 ( .A ( BUF_net_160 ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_163 ( - .A ( mux_2level_tapbuf_basis_input3_mem3_2_out[0] ) , .Y ( BUF_net_163 ) , +sky130_fd_sc_hd__inv_1 BINV_R_160 ( + .A ( mux_2level_tapbuf_basis_input3_mem3_2_out[0] ) , .Y ( BUF_net_160 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -85375,13 +88743,16 @@ input VDD ; input VSS ; input p0 ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -85394,13 +88765,16 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -85413,13 +88787,16 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -85517,10 +88894,10 @@ sb_0__1__mux_2level_tapbuf_basis_input3_mem3_14 mux_l2_in_0_ ( .mem_inv ( local_encoder2to3_1_data_inv ) , .out ( mux_2level_tapbuf_basis_input3_mem3_2_out ) , .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_160 ( .A ( BUF_net_161 ) , .Y ( out[0] ) , +sky130_fd_sc_hd__inv_8 BINV_R_157 ( .A ( BUF_net_158 ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_161 ( - .A ( mux_2level_tapbuf_basis_input3_mem3_2_out[0] ) , .Y ( BUF_net_161 ) , +sky130_fd_sc_hd__inv_1 BINV_R_158 ( + .A ( mux_2level_tapbuf_basis_input3_mem3_2_out[0] ) , .Y ( BUF_net_158 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -85535,13 +88912,16 @@ input VDD ; input VSS ; input p0 ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -85554,13 +88934,16 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -85573,13 +88956,16 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -85677,10 +89063,10 @@ sb_0__1__mux_2level_tapbuf_basis_input3_mem3_11 mux_l2_in_0_ ( .mem_inv ( local_encoder2to3_1_data_inv ) , .out ( mux_2level_tapbuf_basis_input3_mem3_2_out ) , .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_158 ( .A ( BUF_net_159 ) , .Y ( out[0] ) , +sky130_fd_sc_hd__inv_8 BINV_R_155 ( .A ( BUF_net_156 ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_159 ( - .A ( mux_2level_tapbuf_basis_input3_mem3_2_out[0] ) , .Y ( BUF_net_159 ) , +sky130_fd_sc_hd__inv_1 BINV_R_156 ( + .A ( mux_2level_tapbuf_basis_input3_mem3_2_out[0] ) , .Y ( BUF_net_156 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -85695,13 +89081,16 @@ input VDD ; input VSS ; input p0 ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -85714,13 +89103,16 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -85733,13 +89125,16 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -85813,6 +89208,9 @@ wire [0:0] mux_2level_tapbuf_basis_input3_mem3_2_out ; supply1 VDD ; supply0 VSS ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( mux_2level_tapbuf_basis_input3_mem3_2_out[0] ) , .X ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; sb_0__1__local_encoder2to3_4 local_encoder2to3_0_ ( .addr ( sram[0:1] ) , .data ( local_encoder2to3_0_data ) , .data_inv ( local_encoder2to3_0_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; @@ -85837,11 +89235,6 @@ sb_0__1__mux_2level_tapbuf_basis_input3_mem3_8 mux_l2_in_0_ ( .mem_inv ( local_encoder2to3_1_data_inv ) , .out ( mux_2level_tapbuf_basis_input3_mem3_2_out ) , .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_156 ( .A ( BUF_net_157 ) , .Y ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_157 ( - .A ( mux_2level_tapbuf_basis_input3_mem3_2_out[0] ) , .Y ( BUF_net_157 ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -85855,13 +89248,16 @@ input VDD ; input VSS ; input p0 ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -85874,13 +89270,16 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -85893,13 +89292,16 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -85997,8 +89399,10 @@ sb_0__1__mux_2level_tapbuf_basis_input3_mem3_5 mux_l2_in_0_ ( .mem_inv ( local_encoder2to3_1_data_inv ) , .out ( mux_2level_tapbuf_basis_input3_mem3_2_out ) , .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_155 ( - .A ( mux_2level_tapbuf_basis_input3_mem3_2_out[0] ) , .X ( out[0] ) , +sky130_fd_sc_hd__inv_8 BINV_R_153 ( .A ( BUF_net_154 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_154 ( + .A ( mux_2level_tapbuf_basis_input3_mem3_2_out[0] ) , .Y ( BUF_net_154 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -86013,13 +89417,16 @@ input VDD ; input VSS ; input p0 ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -86032,13 +89439,16 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -86051,13 +89461,16 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -86131,6 +89544,9 @@ wire [0:0] mux_2level_tapbuf_basis_input3_mem3_2_out ; supply1 VDD ; supply0 VSS ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( mux_2level_tapbuf_basis_input3_mem3_2_out[0] ) , .X ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; sb_0__1__local_encoder2to3_0 local_encoder2to3_0_ ( .addr ( sram[0:1] ) , .data ( local_encoder2to3_0_data ) , .data_inv ( local_encoder2to3_0_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; @@ -86155,11 +89571,6 @@ sb_0__1__mux_2level_tapbuf_basis_input3_mem3_2 mux_l2_in_0_ ( .mem_inv ( local_encoder2to3_1_data_inv ) , .out ( mux_2level_tapbuf_basis_input3_mem3_2_out ) , .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_153 ( .A ( BUF_net_154 ) , .Y ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_154 ( - .A ( mux_2level_tapbuf_basis_input3_mem3_2_out[0] ) , .Y ( BUF_net_154 ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -86309,7 +89720,7 @@ sb_0__1__mux_2level_tapbuf_size6_0 mux_top_track_0 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 , SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) , .out ( chany_top_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_220 ) ) ; + .p0 ( optlc_net_219 ) ) ; sb_0__1__mux_2level_tapbuf_size6_1 mux_top_track_6 ( .in ( { top_left_grid_pin_1_[0] , chanx_right_in[4] , chanx_right_in[15] , chanx_right_in[26] , chany_top_out[9] , chany_top_out[24] } ) , @@ -86317,7 +89728,7 @@ sb_0__1__mux_2level_tapbuf_size6_1 mux_top_track_6 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 , SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 } ) , .out ( chany_top_out[3] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_220 ) ) ; + .p0 ( optlc_net_215 ) ) ; sb_0__1__mux_2level_tapbuf_size6_2 mux_top_track_12 ( .in ( { top_left_grid_pin_1_[0] , chanx_right_in[6] , chanx_right_in[17] , chanx_right_in[28] , chany_top_out[12] , chany_top_out[27] } ) , @@ -86325,7 +89736,7 @@ sb_0__1__mux_2level_tapbuf_size6_2 mux_top_track_12 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_9 , SYNOPSYS_UNCONNECTED_10 , SYNOPSYS_UNCONNECTED_11 , SYNOPSYS_UNCONNECTED_12 } ) , .out ( chany_top_out[6] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_225 ) ) ; + .p0 ( optlc_net_219 ) ) ; sb_0__1__mux_2level_tapbuf_size6_3 mux_right_track_2 ( .in ( { chany_top_in[0] , chany_bottom_out[7] , right_bottom_grid_pin_37_[0] , right_bottom_grid_pin_40_[0] , @@ -86334,7 +89745,7 @@ sb_0__1__mux_2level_tapbuf_size6_3 mux_right_track_2 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 , SYNOPSYS_UNCONNECTED_15 , SYNOPSYS_UNCONNECTED_16 } ) , .out ( chanx_right_out[1] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_223 ) ) ; + .p0 ( optlc_net_215 ) ) ; sb_0__1__mux_2level_tapbuf_size6_4 mux_right_track_6 ( .in ( { chany_top_in[2] , chany_bottom_out[9] , right_bottom_grid_pin_36_[0] , right_bottom_grid_pin_39_[0] , @@ -86343,7 +89754,7 @@ sb_0__1__mux_2level_tapbuf_size6_4 mux_right_track_6 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_17 , SYNOPSYS_UNCONNECTED_18 , SYNOPSYS_UNCONNECTED_19 , SYNOPSYS_UNCONNECTED_20 } ) , .out ( chanx_right_out[3] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_222 ) ) ; + .p0 ( optlc_net_217 ) ) ; sb_0__1__mux_2level_tapbuf_size6_5 mux_right_track_8 ( .in ( { chany_top_in[4] , chany_bottom_out[11] , right_bottom_grid_pin_37_[0] , right_bottom_grid_pin_40_[0] , @@ -86352,7 +89763,7 @@ sb_0__1__mux_2level_tapbuf_size6_5 mux_right_track_8 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_21 , SYNOPSYS_UNCONNECTED_22 , SYNOPSYS_UNCONNECTED_23 , SYNOPSYS_UNCONNECTED_24 } ) , .out ( chanx_right_out[4] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_222 ) ) ; + .p0 ( optlc_net_217 ) ) ; sb_0__1__mux_2level_tapbuf_size6_6 mux_bottom_track_7 ( .in ( { chany_bottom_out[9] , chany_bottom_out[24] , chanx_right_in[6] , chanx_right_in[17] , chanx_right_in[28] , bottom_left_grid_pin_1_[0] } ) , @@ -86360,7 +89771,7 @@ sb_0__1__mux_2level_tapbuf_size6_6 mux_bottom_track_7 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_25 , SYNOPSYS_UNCONNECTED_26 , SYNOPSYS_UNCONNECTED_27 , SYNOPSYS_UNCONNECTED_28 } ) , .out ( chany_bottom_out[3] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_221 ) ) ; + .p0 ( optlc_net_220 ) ) ; sb_0__1__mux_2level_tapbuf_size6 mux_bottom_track_13 ( .in ( { chany_bottom_out[12] , chany_bottom_out[27] , chanx_right_in[4] , chanx_right_in[15] , chanx_right_in[26] , bottom_left_grid_pin_1_[0] } ) , @@ -86368,7 +89779,7 @@ sb_0__1__mux_2level_tapbuf_size6 mux_bottom_track_13 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_29 , SYNOPSYS_UNCONNECTED_30 , SYNOPSYS_UNCONNECTED_31 , SYNOPSYS_UNCONNECTED_32 } ) , .out ( chany_bottom_out[6] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_221 ) ) ; + .p0 ( optlc_net_216 ) ) ; sb_0__1__mux_2level_tapbuf_size6_mem_0 mem_top_track_0 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( mux_2level_tapbuf_size6_mem_0_ccff_tail ) , @@ -86423,7 +89834,7 @@ sb_0__1__mux_2level_tapbuf_size5_0 mux_top_track_2 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_33 , SYNOPSYS_UNCONNECTED_34 , SYNOPSYS_UNCONNECTED_35 , SYNOPSYS_UNCONNECTED_36 } ) , .out ( chany_top_out[1] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_220 ) ) ; + .p0 ( optlc_net_215 ) ) ; sb_0__1__mux_2level_tapbuf_size5_1 mux_top_track_4 ( .in ( { chanx_right_in[3] , chanx_right_in[14] , chanx_right_in[25] , chany_top_out[8] , chany_top_out[23] } ) , @@ -86431,7 +89842,7 @@ sb_0__1__mux_2level_tapbuf_size5_1 mux_top_track_4 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_37 , SYNOPSYS_UNCONNECTED_38 , SYNOPSYS_UNCONNECTED_39 , SYNOPSYS_UNCONNECTED_40 } ) , .out ( chany_top_out[2] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_220 ) ) ; + .p0 ( optlc_net_215 ) ) ; sb_0__1__mux_2level_tapbuf_size5_2 mux_top_track_10 ( .in ( { chanx_right_in[5] , chanx_right_in[16] , chanx_right_in[27] , chany_top_out[11] , chany_top_out[25] } ) , @@ -86439,7 +89850,7 @@ sb_0__1__mux_2level_tapbuf_size5_2 mux_top_track_10 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_41 , SYNOPSYS_UNCONNECTED_42 , SYNOPSYS_UNCONNECTED_43 , SYNOPSYS_UNCONNECTED_44 } ) , .out ( chany_top_out[5] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_222 ) ) ; + .p0 ( optlc_net_217 ) ) ; sb_0__1__mux_2level_tapbuf_size5_3 mux_top_track_20 ( .in ( { chanx_right_in[7] , chanx_right_in[18] , chanx_right_in[29] , chany_top_out[13] , chany_top_out[28] } ) , @@ -86447,7 +89858,7 @@ sb_0__1__mux_2level_tapbuf_size5_3 mux_top_track_20 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_45 , SYNOPSYS_UNCONNECTED_46 , SYNOPSYS_UNCONNECTED_47 , SYNOPSYS_UNCONNECTED_48 } ) , .out ( chany_top_out[10] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_225 ) ) ; + .p0 ( optlc_net_219 ) ) ; sb_0__1__mux_2level_tapbuf_size5_4 mux_right_track_0 ( .in ( { chany_bottom_out[4] , right_bottom_grid_pin_36_[0] , right_bottom_grid_pin_39_[0] , right_bottom_grid_pin_42_[0] , @@ -86456,7 +89867,7 @@ sb_0__1__mux_2level_tapbuf_size5_4 mux_right_track_0 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_49 , SYNOPSYS_UNCONNECTED_50 , SYNOPSYS_UNCONNECTED_51 , SYNOPSYS_UNCONNECTED_52 } ) , .out ( chanx_right_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_223 ) ) ; + .p0 ( optlc_net_215 ) ) ; sb_0__1__mux_2level_tapbuf_size5_5 mux_right_track_4 ( .in ( { chany_top_in[1] , chany_bottom_out[8] , right_bottom_grid_pin_38_[0] , right_bottom_grid_pin_41_[0] , @@ -86465,7 +89876,7 @@ sb_0__1__mux_2level_tapbuf_size5_5 mux_right_track_4 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_53 , SYNOPSYS_UNCONNECTED_54 , SYNOPSYS_UNCONNECTED_55 , SYNOPSYS_UNCONNECTED_56 } ) , .out ( chanx_right_out[2] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_222 ) ) ; + .p0 ( optlc_net_217 ) ) ; sb_0__1__mux_2level_tapbuf_size5_6 mux_right_track_10 ( .in ( { chany_top_in[5] , chany_bottom_out[12] , right_bottom_grid_pin_38_[0] , right_bottom_grid_pin_41_[0] , @@ -86474,7 +89885,7 @@ sb_0__1__mux_2level_tapbuf_size5_6 mux_right_track_10 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_57 , SYNOPSYS_UNCONNECTED_58 , SYNOPSYS_UNCONNECTED_59 , SYNOPSYS_UNCONNECTED_60 } ) , .out ( chanx_right_out[5] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_222 ) ) ; + .p0 ( optlc_net_217 ) ) ; sb_0__1__mux_2level_tapbuf_size5_7 mux_bottom_track_1 ( .in ( { chany_bottom_out[4] , chany_bottom_out[20] , chanx_right_in[9] , chanx_right_in[20] , bottom_left_grid_pin_1_[0] } ) , @@ -86490,7 +89901,7 @@ sb_0__1__mux_2level_tapbuf_size5_8 mux_bottom_track_5 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_65 , SYNOPSYS_UNCONNECTED_66 , SYNOPSYS_UNCONNECTED_67 , SYNOPSYS_UNCONNECTED_68 } ) , .out ( chany_bottom_out[2] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_225 ) ) ; + .p0 ( optlc_net_221 ) ) ; sb_0__1__mux_2level_tapbuf_size5_9 mux_bottom_track_11 ( .in ( { chany_bottom_out[11] , chany_bottom_out[25] , chanx_right_in[5] , chanx_right_in[16] , chanx_right_in[27] } ) , @@ -86498,7 +89909,7 @@ sb_0__1__mux_2level_tapbuf_size5_9 mux_bottom_track_11 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_69 , SYNOPSYS_UNCONNECTED_70 , SYNOPSYS_UNCONNECTED_71 , SYNOPSYS_UNCONNECTED_72 } ) , .out ( chany_bottom_out[5] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_221 ) ) ; + .p0 ( optlc_net_216 ) ) ; sb_0__1__mux_2level_tapbuf_size5_10 mux_bottom_track_21 ( .in ( { chany_bottom_out[13] , chany_bottom_out[28] , chanx_right_in[3] , chanx_right_in[14] , chanx_right_in[25] } ) , @@ -86506,7 +89917,7 @@ sb_0__1__mux_2level_tapbuf_size5_10 mux_bottom_track_21 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_73 , SYNOPSYS_UNCONNECTED_74 , SYNOPSYS_UNCONNECTED_75 , SYNOPSYS_UNCONNECTED_76 } ) , .out ( chany_bottom_out[10] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_224 ) ) ; + .p0 ( optlc_net_218 ) ) ; sb_0__1__mux_2level_tapbuf_size5 mux_bottom_track_29 ( .in ( { chany_bottom_out[15] , chany_bottom_out[29] , chanx_right_in[2] , chanx_right_in[13] , chanx_right_in[24] } ) , @@ -86514,7 +89925,7 @@ sb_0__1__mux_2level_tapbuf_size5 mux_bottom_track_29 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_77 , SYNOPSYS_UNCONNECTED_78 , SYNOPSYS_UNCONNECTED_79 , SYNOPSYS_UNCONNECTED_80 } ) , .out ( chany_bottom_out[14] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_224 ) ) ; + .p0 ( optlc_net_221 ) ) ; sb_0__1__mux_2level_tapbuf_size5_mem_0 mem_top_track_2 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( mux_2level_tapbuf_size6_mem_0_ccff_tail ) , @@ -86594,7 +90005,7 @@ sb_0__1__mux_2level_tapbuf_size4_0 mux_top_track_28 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_81 , SYNOPSYS_UNCONNECTED_82 , SYNOPSYS_UNCONNECTED_83 , SYNOPSYS_UNCONNECTED_84 } ) , .out ( chany_top_out[14] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_223 ) ) ; + .p0 ( optlc_net_221 ) ) ; sb_0__1__mux_2level_tapbuf_size4_1 mux_top_track_52 ( .in ( { chanx_right_in[0] , chanx_right_in[11] , chanx_right_in[22] , chany_top_out[19] } ) , @@ -86602,7 +90013,7 @@ sb_0__1__mux_2level_tapbuf_size4_1 mux_top_track_52 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_85 , SYNOPSYS_UNCONNECTED_86 , SYNOPSYS_UNCONNECTED_87 , SYNOPSYS_UNCONNECTED_88 } ) , .out ( chany_top_out[26] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_226 ) ) ; + .p0 ( optlc_net_217 ) ) ; sb_0__1__mux_2level_tapbuf_size4_2 mux_right_track_12 ( .in ( { chany_top_in[9] , chany_bottom_out[13] , right_bottom_grid_pin_36_[0] , chany_top_out[13] } ) , @@ -86610,7 +90021,7 @@ sb_0__1__mux_2level_tapbuf_size4_2 mux_right_track_12 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_89 , SYNOPSYS_UNCONNECTED_90 , SYNOPSYS_UNCONNECTED_91 , SYNOPSYS_UNCONNECTED_92 } ) , .out ( chanx_right_out[6] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_226 ) ) ; + .p0 ( optlc_net_219 ) ) ; sb_0__1__mux_2level_tapbuf_size4_3 mux_right_track_14 ( .in ( { chany_top_in[13] , chany_bottom_out[15] , right_bottom_grid_pin_37_[0] , chany_top_out[15] } ) , @@ -86618,7 +90029,7 @@ sb_0__1__mux_2level_tapbuf_size4_3 mux_right_track_14 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_93 , SYNOPSYS_UNCONNECTED_94 , SYNOPSYS_UNCONNECTED_95 , SYNOPSYS_UNCONNECTED_96 } ) , .out ( chanx_right_out[7] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_223 ) ) ; + .p0 ( optlc_net_219 ) ) ; sb_0__1__mux_2level_tapbuf_size4_4 mux_right_track_16 ( .in ( { chany_bottom_out[16] , chany_top_in[17] , right_bottom_grid_pin_38_[0] , chany_top_out[16] } ) , @@ -86626,7 +90037,7 @@ sb_0__1__mux_2level_tapbuf_size4_4 mux_right_track_16 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_97 , SYNOPSYS_UNCONNECTED_98 , SYNOPSYS_UNCONNECTED_99 , SYNOPSYS_UNCONNECTED_100 } ) , .out ( chanx_right_out[8] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_223 ) ) ; + .p0 ( optlc_net_219 ) ) ; sb_0__1__mux_2level_tapbuf_size4_5 mux_right_track_18 ( .in ( { chany_bottom_out[17] , chany_top_in[21] , right_bottom_grid_pin_39_[0] , chany_top_out[17] } ) , @@ -86634,7 +90045,7 @@ sb_0__1__mux_2level_tapbuf_size4_5 mux_right_track_18 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_101 , SYNOPSYS_UNCONNECTED_102 , SYNOPSYS_UNCONNECTED_103 , SYNOPSYS_UNCONNECTED_104 } ) , .out ( chanx_right_out[9] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_223 ) ) ; + .p0 ( optlc_net_219 ) ) ; sb_0__1__mux_2level_tapbuf_size4_6 mux_right_track_20 ( .in ( { chany_bottom_out[19] , chany_top_in[25] , right_bottom_grid_pin_40_[0] , chany_top_out[19] } ) , @@ -86642,7 +90053,7 @@ sb_0__1__mux_2level_tapbuf_size4_6 mux_right_track_20 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_105 , SYNOPSYS_UNCONNECTED_106 , SYNOPSYS_UNCONNECTED_107 , SYNOPSYS_UNCONNECTED_108 } ) , .out ( chanx_right_out[10] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_223 ) ) ; + .p0 ( optlc_net_215 ) ) ; sb_0__1__mux_2level_tapbuf_size4_7 mux_right_track_22 ( .in ( { chany_bottom_out[20] , chany_top_in[29] , right_bottom_grid_pin_41_[0] , chany_top_out[20] } ) , @@ -86650,7 +90061,7 @@ sb_0__1__mux_2level_tapbuf_size4_7 mux_right_track_22 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_109 , SYNOPSYS_UNCONNECTED_110 , SYNOPSYS_UNCONNECTED_111 , SYNOPSYS_UNCONNECTED_112 } ) , .out ( chanx_right_out[11] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_223 ) ) ; + .p0 ( optlc_net_215 ) ) ; sb_0__1__mux_2level_tapbuf_size4_8 mux_right_track_36 ( .in ( { chany_bottom_out[29] , right_bottom_grid_pin_40_[0] , chany_top_out[29] , chany_bottom_in[29] } ) , @@ -86658,7 +90069,7 @@ sb_0__1__mux_2level_tapbuf_size4_8 mux_right_track_36 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_113 , SYNOPSYS_UNCONNECTED_114 , SYNOPSYS_UNCONNECTED_115 , SYNOPSYS_UNCONNECTED_116 } ) , .out ( chanx_right_out[18] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_221 ) ) ; + .p0 ( optlc_net_218 ) ) ; sb_0__1__mux_2level_tapbuf_size4_9 mux_bottom_track_3 ( .in ( { chany_bottom_out[7] , chany_bottom_out[21] , chanx_right_in[8] , chanx_right_in[19] } ) , @@ -86666,7 +90077,7 @@ sb_0__1__mux_2level_tapbuf_size4_9 mux_bottom_track_3 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_117 , SYNOPSYS_UNCONNECTED_118 , SYNOPSYS_UNCONNECTED_119 , SYNOPSYS_UNCONNECTED_120 } ) , .out ( chany_bottom_out[1] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_225 ) ) ; + .p0 ( optlc_net_220 ) ) ; sb_0__1__mux_2level_tapbuf_size4_10 mux_bottom_track_37 ( .in ( { chany_bottom_out[16] , chanx_right_in[1] , chanx_right_in[12] , chanx_right_in[23] } ) , @@ -86674,7 +90085,7 @@ sb_0__1__mux_2level_tapbuf_size4_10 mux_bottom_track_37 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_121 , SYNOPSYS_UNCONNECTED_122 , SYNOPSYS_UNCONNECTED_123 , SYNOPSYS_UNCONNECTED_124 } ) , .out ( chany_bottom_out[18] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_224 ) ) ; + .p0 ( optlc_net_221 ) ) ; sb_0__1__mux_2level_tapbuf_size4 mux_bottom_track_45 ( .in ( { chany_bottom_out[17] , chanx_right_in[0] , chanx_right_in[11] , chanx_right_in[22] } ) , @@ -86682,7 +90093,7 @@ sb_0__1__mux_2level_tapbuf_size4 mux_bottom_track_45 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_125 , SYNOPSYS_UNCONNECTED_126 , SYNOPSYS_UNCONNECTED_127 , SYNOPSYS_UNCONNECTED_128 } ) , .out ( chany_bottom_out[22] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_224 ) ) ; + .p0 ( optlc_net_216 ) ) ; sb_0__1__mux_2level_tapbuf_size4_mem_0 mem_top_track_28 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( mux_2level_tapbuf_size5_mem_3_ccff_tail ) , @@ -86760,68 +90171,68 @@ sb_0__1__mux_2level_tapbuf_size3_0 mux_top_track_36 ( .sram ( mux_2level_tapbuf_size3_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_129 , SYNOPSYS_UNCONNECTED_130 } ) , .out ( chany_top_out[18] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_226 ) ) ; + .p0 ( optlc_net_221 ) ) ; sb_0__1__mux_2level_tapbuf_size3_1 mux_top_track_44 ( .in ( { chanx_right_in[10] , chanx_right_in[21] , chany_top_out[17] } ) , .sram ( mux_2level_tapbuf_size3_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_131 , SYNOPSYS_UNCONNECTED_132 } ) , .out ( chany_top_out[22] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_226 ) ) ; + .p0 ( optlc_net_221 ) ) ; sb_0__1__mux_2level_tapbuf_size3_2 mux_right_track_24 ( .in ( { chany_bottom_out[21] , right_bottom_grid_pin_42_[0] , chany_top_out[21] } ) , .sram ( mux_2level_tapbuf_size3_2_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_133 , SYNOPSYS_UNCONNECTED_134 } ) , .out ( chanx_right_out[12] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_225 ) ) ; + .p0 ( optlc_net_218 ) ) ; sb_0__1__mux_2level_tapbuf_size3_3 mux_right_track_26 ( .in ( { chany_bottom_out[23] , right_bottom_grid_pin_43_[0] , chany_top_out[23] } ) , .sram ( mux_2level_tapbuf_size3_3_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_135 , SYNOPSYS_UNCONNECTED_136 } ) , .out ( chanx_right_out[13] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_221 ) ) ; + .p0 ( optlc_net_218 ) ) ; sb_0__1__mux_2level_tapbuf_size3_4 mux_right_track_28 ( .in ( { chany_bottom_out[24] , right_bottom_grid_pin_36_[0] , chany_top_out[24] } ) , .sram ( mux_2level_tapbuf_size3_4_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_137 , SYNOPSYS_UNCONNECTED_138 } ) , .out ( chanx_right_out[14] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_221 ) ) ; + .p0 ( optlc_net_216 ) ) ; sb_0__1__mux_2level_tapbuf_size3_5 mux_right_track_30 ( .in ( { chany_bottom_out[25] , right_bottom_grid_pin_37_[0] , chany_top_out[25] } ) , .sram ( mux_2level_tapbuf_size3_5_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_139 , SYNOPSYS_UNCONNECTED_140 } ) , .out ( chanx_right_out[15] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_221 ) ) ; + .p0 ( optlc_net_216 ) ) ; sb_0__1__mux_2level_tapbuf_size3_6 mux_right_track_32 ( .in ( { chany_bottom_out[27] , right_bottom_grid_pin_38_[0] , chany_top_out[27] } ) , .sram ( mux_2level_tapbuf_size3_6_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_141 , SYNOPSYS_UNCONNECTED_142 } ) , .out ( chanx_right_out[16] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_221 ) ) ; + .p0 ( optlc_net_218 ) ) ; sb_0__1__mux_2level_tapbuf_size3_7 mux_right_track_34 ( .in ( { chany_bottom_out[28] , right_bottom_grid_pin_39_[0] , chany_top_out[28] } ) , .sram ( mux_2level_tapbuf_size3_7_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_143 , SYNOPSYS_UNCONNECTED_144 } ) , .out ( chanx_right_out[17] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_221 ) ) ; + .p0 ( optlc_net_218 ) ) ; sb_0__1__mux_2level_tapbuf_size3_8 mux_right_track_50 ( .in ( { right_bottom_grid_pin_39_[0] , right_bottom_grid_pin_43_[0] , chany_bottom_in[4] } ) , .sram ( mux_2level_tapbuf_size3_8_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_145 , SYNOPSYS_UNCONNECTED_146 } ) , .out ( chanx_right_out[25] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_221 ) ) ; + .p0 ( optlc_net_218 ) ) ; sb_0__1__mux_2level_tapbuf_size3 mux_bottom_track_53 ( .in ( { chany_bottom_out[19] , chanx_right_in[10] , chanx_right_in[21] } ) , .sram ( mux_2level_tapbuf_size3_9_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_147 , SYNOPSYS_UNCONNECTED_148 } ) , .out ( chany_bottom_out[26] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_224 ) ) ; + .p0 ( optlc_net_218 ) ) ; sb_0__1__mux_2level_tapbuf_size3_mem_0 mem_top_track_36 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( mux_2level_tapbuf_size4_mem_0_ccff_tail ) , @@ -86886,49 +90297,49 @@ sb_0__1__mux_2level_tapbuf_size2_0 mux_right_track_38 ( .sram ( mux_2level_tapbuf_size2_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_149 , SYNOPSYS_UNCONNECTED_150 } ) , .out ( chanx_right_out[19] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_221 ) ) ; + .p0 ( optlc_net_218 ) ) ; sb_0__1__mux_2level_tapbuf_size2_1 mux_right_track_40 ( .in ( { right_bottom_grid_pin_42_[0] , chany_bottom_in[21] } ) , .sram ( mux_2level_tapbuf_size2_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_151 , SYNOPSYS_UNCONNECTED_152 } ) , .out ( chanx_right_out[20] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_221 ) ) ; + .p0 ( optlc_net_218 ) ) ; sb_0__1__mux_2level_tapbuf_size2_2 mux_right_track_44 ( .in ( { right_bottom_grid_pin_36_[0] , chany_bottom_in[13] } ) , .sram ( mux_2level_tapbuf_size2_2_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_153 , SYNOPSYS_UNCONNECTED_154 } ) , .out ( chanx_right_out[22] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_221 ) ) ; + .p0 ( optlc_net_216 ) ) ; sb_0__1__mux_2level_tapbuf_size2_3 mux_right_track_46 ( .in ( { right_bottom_grid_pin_37_[0] , chany_bottom_in[9] } ) , .sram ( mux_2level_tapbuf_size2_3_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_155 , SYNOPSYS_UNCONNECTED_156 } ) , .out ( chanx_right_out[23] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_221 ) ) ; + .p0 ( optlc_net_216 ) ) ; sb_0__1__mux_2level_tapbuf_size2_4 mux_right_track_48 ( .in ( { right_bottom_grid_pin_38_[0] , chany_bottom_in[5] } ) , .sram ( mux_2level_tapbuf_size2_4_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_157 , SYNOPSYS_UNCONNECTED_158 } ) , .out ( chanx_right_out[24] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_221 ) ) ; + .p0 ( optlc_net_216 ) ) ; sb_0__1__mux_2level_tapbuf_size2_5 mux_right_track_52 ( .in ( { right_bottom_grid_pin_40_[0] , chany_bottom_in[2] } ) , .sram ( mux_2level_tapbuf_size2_5_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_159 , SYNOPSYS_UNCONNECTED_160 } ) , .out ( chanx_right_out[26] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_221 ) ) ; + .p0 ( optlc_net_218 ) ) ; sb_0__1__mux_2level_tapbuf_size2_6 mux_right_track_54 ( .in ( { right_bottom_grid_pin_41_[0] , chany_bottom_in[1] } ) , .sram ( mux_2level_tapbuf_size2_6_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_161 , SYNOPSYS_UNCONNECTED_162 } ) , .out ( chanx_right_out[27] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_221 ) ) ; + .p0 ( optlc_net_218 ) ) ; sb_0__1__mux_2level_tapbuf_size2 mux_right_track_56 ( .in ( { right_bottom_grid_pin_42_[0] , chany_bottom_in[0] } ) , .sram ( mux_2level_tapbuf_size2_7_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_163 , SYNOPSYS_UNCONNECTED_164 } ) , .out ( chanx_right_out[28] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_221 ) ) ; + .p0 ( optlc_net_218 ) ) ; sb_0__1__mux_2level_tapbuf_size2_mem_0 mem_right_track_38 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( mux_2level_tapbuf_size4_mem_8_ccff_tail ) , @@ -86979,8 +90390,8 @@ sb_0__1__mux_2level_tapbuf_size2_mem mem_right_track_56 ( .pReset ( pReset ) , .VSS ( VSS ) ) ; sky130_fd_sc_hd__buf_8 pReset_FTB00 ( .A ( pReset_E_in ) , .X ( pReset[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_6 pReset_S_FTB01 ( .A ( pReset_E_in ) , - .X ( pReset_S_out ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_217 ( .LO ( SYNOPSYS_UNCONNECTED_165 ) , + .HI ( optlc_net_215 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_1 prog_clk_0_FTB00 ( .A ( prog_clk_0_E_in ) , .X ( prog_clk[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_8 FTB_115__114 ( .A ( chany_top_in[3] ) , @@ -87061,20 +90472,22 @@ sky130_fd_sc_hd__buf_8 FTB_152__151 ( .A ( chany_bottom_in[27] ) , .X ( chany_top_out[28] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_8 FTB_153__152 ( .A ( chany_bottom_in[28] ) , .X ( chany_top_out[29] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_222 ( .LO ( SYNOPSYS_UNCONNECTED_165 ) , +sky130_fd_sc_hd__inv_8 BINV_R_211 ( .A ( BUF_net_212 ) , .Y ( pReset_S_out ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_212 ( .A ( pReset_E_in ) , .Y ( BUF_net_212 ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_219 ( .LO ( SYNOPSYS_UNCONNECTED_166 ) , + .HI ( optlc_net_216 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_221 ( .LO ( SYNOPSYS_UNCONNECTED_167 ) , + .HI ( optlc_net_217 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_224 ( .LO ( SYNOPSYS_UNCONNECTED_168 ) , + .HI ( optlc_net_218 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_226 ( .LO ( SYNOPSYS_UNCONNECTED_169 ) , + .HI ( optlc_net_219 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_228 ( .LO ( SYNOPSYS_UNCONNECTED_170 ) , .HI ( optlc_net_220 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_224 ( .LO ( SYNOPSYS_UNCONNECTED_166 ) , +sky130_fd_sc_hd__conb_1 optlc_230 ( .LO ( SYNOPSYS_UNCONNECTED_171 ) , .HI ( optlc_net_221 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_226 ( .LO ( SYNOPSYS_UNCONNECTED_167 ) , - .HI ( optlc_net_222 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_228 ( .LO ( SYNOPSYS_UNCONNECTED_168 ) , - .HI ( optlc_net_223 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_230 ( .LO ( SYNOPSYS_UNCONNECTED_169 ) , - .HI ( optlc_net_224 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_233 ( .LO ( SYNOPSYS_UNCONNECTED_170 ) , - .HI ( optlc_net_225 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_235 ( .LO ( SYNOPSYS_UNCONNECTED_171 ) , - .HI ( optlc_net_226 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -87221,6 +90634,9 @@ wire [0:0] mux_2level_tapbuf_basis_input2_mem1_2_out ; supply1 VDD ; supply0 VSS ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( mux_2level_tapbuf_basis_input2_mem1_2_out[0] ) , .X ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; sb_0__0__mux_2level_tapbuf_basis_input2_mem1_58 mux_l1_in_0_ ( .in ( in[0:1] ) , .mem ( sram[0] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) , @@ -87239,9 +90655,6 @@ sb_0__0__mux_2level_tapbuf_basis_input2_mem1 mux_l2_in_0_ ( .mem_inv ( { SYNOPSYS_UNCONNECTED_4 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_2_out ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_99 ( - .A ( mux_2level_tapbuf_basis_input2_mem1_2_out[0] ) , .X ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -87316,9 +90729,6 @@ wire [0:0] mux_2level_tapbuf_basis_input2_mem1_2_out ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( mux_2level_tapbuf_basis_input2_mem1_2_out[0] ) , .X ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; sb_0__0__mux_2level_tapbuf_basis_input2_mem1_55 mux_l1_in_0_ ( .in ( in[0:1] ) , .mem ( sram[0] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) , @@ -87337,6 +90747,9 @@ sb_0__0__mux_2level_tapbuf_basis_input2_mem1_57 mux_l2_in_0_ ( .mem_inv ( { SYNOPSYS_UNCONNECTED_4 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_2_out ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_100 ( + .A ( mux_2level_tapbuf_basis_input2_mem1_2_out[0] ) , .X ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -87411,9 +90824,6 @@ wire [0:0] mux_2level_tapbuf_basis_input2_mem1_2_out ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( mux_2level_tapbuf_basis_input2_mem1_2_out[0] ) , .X ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; sb_0__0__mux_2level_tapbuf_basis_input2_mem1_52 mux_l1_in_0_ ( .in ( in[0:1] ) , .mem ( sram[0] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) , @@ -87432,6 +90842,9 @@ sb_0__0__mux_2level_tapbuf_basis_input2_mem1_54 mux_l2_in_0_ ( .mem_inv ( { SYNOPSYS_UNCONNECTED_4 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_2_out ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_99 ( + .A ( mux_2level_tapbuf_basis_input2_mem1_2_out[0] ) , .X ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -87625,13 +91038,16 @@ input VDD ; input VSS ; input p0 ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -87644,13 +91060,16 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -87757,13 +91176,16 @@ input VDD ; input VSS ; input p0 ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -87776,13 +91198,16 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -87873,8 +91298,10 @@ sb_0__0__mux_2level_tapbuf_basis_input3_mem3_9 mux_l2_in_0_ ( .mem_inv ( local_encoder2to3_1_data_inv ) , .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_98 ( - .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .X ( out[0] ) , +sky130_fd_sc_hd__inv_8 BINV_R_97 ( .A ( BUF_net_98 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_98 ( + .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_98 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -87889,13 +91316,16 @@ input VDD ; input VSS ; input p0 ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -87908,13 +91338,16 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -88005,10 +91438,8 @@ sb_0__0__mux_2level_tapbuf_basis_input3_mem3_7 mux_l2_in_0_ ( .mem_inv ( local_encoder2to3_1_data_inv ) , .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_96 ( .A ( BUF_net_97 ) , .Y ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_97 ( - .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_97 ) , +sky130_fd_sc_hd__buf_6 BUFT_RR_96 ( + .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -88023,13 +91454,16 @@ input VDD ; input VSS ; input p0 ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -88042,13 +91476,16 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -88121,9 +91558,6 @@ wire [0:0] mux_2level_tapbuf_basis_input3_mem3_1_out ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .X ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; sb_0__0__local_encoder2to3_4 local_encoder2to3_0_ ( .addr ( sram[0:1] ) , .data ( local_encoder2to3_0_data ) , .data_inv ( local_encoder2to3_0_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; @@ -88142,6 +91576,11 @@ sb_0__0__mux_2level_tapbuf_basis_input3_mem3_5 mux_l2_in_0_ ( .mem_inv ( local_encoder2to3_1_data_inv ) , .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_94 ( .A ( BUF_net_95 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_95 ( + .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_95 ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -88155,13 +91594,16 @@ input VDD ; input VSS ; input p0 ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -88174,13 +91616,16 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -88253,6 +91698,9 @@ wire [0:0] mux_2level_tapbuf_basis_input3_mem3_1_out ; supply1 VDD ; supply0 VSS ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .X ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; sb_0__0__local_encoder2to3_2 local_encoder2to3_0_ ( .addr ( sram[0:1] ) , .data ( local_encoder2to3_0_data ) , .data_inv ( local_encoder2to3_0_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; @@ -88271,11 +91719,6 @@ sb_0__0__mux_2level_tapbuf_basis_input3_mem3_3 mux_l2_in_0_ ( .mem_inv ( local_encoder2to3_1_data_inv ) , .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_100 ( .A ( BUF_net_101 ) , .Y ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_101 ( - .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_101 ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -88289,13 +91732,16 @@ input VDD ; input VSS ; input p0 ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -88308,13 +91754,16 @@ output [0:0] out ; input VDD ; input VSS ; +wire [0:0] out_inv ; supply1 VDD ; supply0 VSS ; scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .Z ( out_inv[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -88405,10 +91854,8 @@ sb_0__0__mux_2level_tapbuf_basis_input3_mem3_1 mux_l2_in_0_ ( .mem_inv ( local_encoder2to3_1_data_inv ) , .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_94 ( .A ( BUF_net_95 ) , .Y ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_95 ( - .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_95 ) , +sky130_fd_sc_hd__buf_6 BUFT_RR_93 ( + .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -88423,7 +91870,6 @@ output [0:1] mem_out ; input VDD ; input VSS ; -wire copt_net_120 ; supply1 VDD ; supply0 VSS ; @@ -88431,16 +91877,16 @@ sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( copt_net_120 ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_6 FTB_26__25 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1300 ( .A ( copt_net_120 ) , - .X ( copt_net_118 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1301 ( .A ( copt_net_118 ) , - .X ( copt_net_119 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1302 ( .A ( copt_net_119 ) , - .X ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 FTB_26__25 ( .A ( ropt_net_183 ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 ropt_h_inst_1364 ( .A ( copt_net_117 ) , + .X ( ropt_net_183 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1297 ( .A ( mem_out[1] ) , + .X ( copt_net_116 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1298 ( .A ( copt_net_116 ) , + .X ( copt_net_117 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -89033,7 +92479,7 @@ input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ropt_net_157 ) , +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ropt_net_182 ) , .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , @@ -89041,24 +92487,26 @@ sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_1 FTB_1__0 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1291 ( .A ( copt_net_112 ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1289 ( .A ( ccff_head[0] ) , + .X ( copt_net_108 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1290 ( .A ( copt_net_108 ) , .X ( copt_net_109 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1292 ( .A ( copt_net_109 ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1291 ( .A ( copt_net_109 ) , .X ( copt_net_110 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1293 ( .A ( ccff_head[0] ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1292 ( .A ( copt_net_112 ) , .X ( copt_net_111 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1294 ( .A ( copt_net_111 ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1293 ( .A ( copt_net_110 ) , .X ( copt_net_112 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1295 ( .A ( copt_net_110 ) , +sky130_fd_sc_hd__buf_1 copt_h_inst_1294 ( .A ( copt_net_111 ) , .X ( copt_net_113 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1296 ( .A ( copt_net_113 ) , - .X ( copt_net_114 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1336 ( .A ( copt_net_114 ) , - .X ( ropt_net_155 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1337 ( .A ( ropt_net_155 ) , - .X ( ropt_net_156 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1338 ( .A ( ropt_net_156 ) , - .X ( ropt_net_157 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1360 ( .A ( ropt_net_180 ) , + .X ( ropt_net_179 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1361 ( .A ( copt_net_113 ) , + .X ( ropt_net_180 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1362 ( .A ( ropt_net_179 ) , + .X ( ropt_net_181 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1363 ( .A ( ropt_net_181 ) , + .X ( ropt_net_182 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -89075,7 +92523,7 @@ input p0 ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , +sky130_fd_sc_hd__mux2_2 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -89145,7 +92593,7 @@ input p0 ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , +sky130_fd_sc_hd__mux2_2 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -89266,10 +92714,10 @@ sb_0__0__mux_2level_tapbuf_basis_input2_mem1_47 mux_l2_in_0_ ( .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_102 ( .A ( BUF_net_103 ) , .Y ( out[0] ) , +sky130_fd_sc_hd__inv_8 BINV_R_91 ( .A ( BUF_net_92 ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_103 ( - .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_103 ) , +sky130_fd_sc_hd__inv_1 BINV_R_92 ( + .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_92 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -89326,9 +92774,6 @@ wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; sb_0__0__mux_2level_tapbuf_basis_input2_mem1_44 mux_l1_in_0_ ( .in ( in ) , .mem ( sram[0] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) , @@ -89341,6 +92786,11 @@ sb_0__0__mux_2level_tapbuf_basis_input2_mem1_45 mux_l2_in_0_ ( .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_89 ( .A ( BUF_net_90 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_90 ( + .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_90 ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -89396,6 +92846,9 @@ wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ; supply1 VDD ; supply0 VSS ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; sb_0__0__mux_2level_tapbuf_basis_input2_mem1_42 mux_l1_in_0_ ( .in ( in ) , .mem ( sram[0] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) , @@ -89408,11 +92861,6 @@ sb_0__0__mux_2level_tapbuf_basis_input2_mem1_43 mux_l2_in_0_ ( .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_92 ( .A ( BUF_net_93 ) , .Y ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_93 ( - .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_93 ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -89499,7 +92947,7 @@ input p0 ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , +sky130_fd_sc_hd__mux2_2 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -89569,7 +93017,7 @@ input p0 ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , +sky130_fd_sc_hd__mux2_2 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -89690,10 +93138,10 @@ sb_0__0__mux_2level_tapbuf_basis_input2_mem1_35 mux_l2_in_0_ ( .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_90 ( .A ( BUF_net_91 ) , .Y ( out[0] ) , +sky130_fd_sc_hd__inv_8 BINV_R_87 ( .A ( BUF_net_88 ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_91 ( - .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_91 ) , +sky130_fd_sc_hd__inv_1 BINV_R_88 ( + .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_88 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -89711,7 +93159,7 @@ input p0 ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , +sky130_fd_sc_hd__mux2_2 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -89832,10 +93280,10 @@ sb_0__0__mux_2level_tapbuf_basis_input2_mem1_31 mux_l2_in_0_ ( .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_88 ( .A ( BUF_net_89 ) , .Y ( out[0] ) , +sky130_fd_sc_hd__inv_8 BINV_R_101 ( .A ( BUF_net_102 ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_89 ( - .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_89 ) , +sky130_fd_sc_hd__inv_1 BINV_R_102 ( + .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_102 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -89853,7 +93301,7 @@ input p0 ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__mux2_2 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , +sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -89892,9 +93340,6 @@ wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; sb_0__0__mux_2level_tapbuf_basis_input2_mem1_28 mux_l1_in_0_ ( .in ( in ) , .mem ( sram[0] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) , @@ -89907,6 +93352,11 @@ sb_0__0__mux_2level_tapbuf_basis_input2_mem1_29 mux_l2_in_0_ ( .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_85 ( .A ( BUF_net_86 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_86 ( + .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_86 ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -89974,10 +93424,10 @@ sb_0__0__mux_2level_tapbuf_basis_input2_mem1_27 mux_l2_in_0_ ( .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_86 ( .A ( BUF_net_87 ) , .Y ( out[0] ) , +sky130_fd_sc_hd__inv_8 BINV_R_83 ( .A ( BUF_net_84 ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_87 ( - .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_87 ) , +sky130_fd_sc_hd__inv_1 BINV_R_84 ( + .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_84 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -90046,10 +93496,10 @@ sb_0__0__mux_2level_tapbuf_basis_input2_mem1_25 mux_l2_in_0_ ( .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_84 ( .A ( BUF_net_85 ) , .Y ( out[0] ) , +sky130_fd_sc_hd__inv_8 BINV_R_81 ( .A ( BUF_net_82 ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_85 ( - .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_85 ) , +sky130_fd_sc_hd__inv_1 BINV_R_82 ( + .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_82 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -90207,7 +93657,7 @@ input p0 ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__mux2_2 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , +sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -90258,8 +93708,10 @@ sb_0__0__mux_2level_tapbuf_basis_input2_mem1_19 mux_l2_in_0_ ( .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_83 ( - .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) , +sky130_fd_sc_hd__inv_8 BINV_R_79 ( .A ( BUF_net_80 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_80 ( + .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_80 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -90277,7 +93729,7 @@ input p0 ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__mux2_2 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , +sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -90316,6 +93768,9 @@ wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ; supply1 VDD ; supply0 VSS ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; sb_0__0__mux_2level_tapbuf_basis_input2_mem1_16 mux_l1_in_0_ ( .in ( in ) , .mem ( sram[0] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) , @@ -90328,9 +93783,6 @@ sb_0__0__mux_2level_tapbuf_basis_input2_mem1_17 mux_l2_in_0_ ( .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_82 ( - .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -90386,6 +93838,9 @@ wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ; supply1 VDD ; supply0 VSS ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; sb_0__0__mux_2level_tapbuf_basis_input2_mem1_14 mux_l1_in_0_ ( .in ( in ) , .mem ( sram[0] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) , @@ -90398,11 +93853,6 @@ sb_0__0__mux_2level_tapbuf_basis_input2_mem1_15 mux_l2_in_0_ ( .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_80 ( .A ( BUF_net_81 ) , .Y ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_81 ( - .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_81 ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -90458,9 +93908,6 @@ wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; sb_0__0__mux_2level_tapbuf_basis_input2_mem1_12 mux_l1_in_0_ ( .in ( in ) , .mem ( sram[0] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) , @@ -90473,6 +93920,11 @@ sb_0__0__mux_2level_tapbuf_basis_input2_mem1_13 mux_l2_in_0_ ( .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_77 ( .A ( BUF_net_78 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_78 ( + .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_78 ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -90489,7 +93941,7 @@ input p0 ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , +sky130_fd_sc_hd__mux2_2 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -90528,9 +93980,6 @@ wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; sb_0__0__mux_2level_tapbuf_basis_input2_mem1_10 mux_l1_in_0_ ( .in ( in ) , .mem ( sram[0] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) , @@ -90543,6 +93992,9 @@ sb_0__0__mux_2level_tapbuf_basis_input2_mem1_11 mux_l2_in_0_ ( .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_76 ( + .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -90598,6 +94050,9 @@ wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ; supply1 VDD ; supply0 VSS ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; sb_0__0__mux_2level_tapbuf_basis_input2_mem1_8 mux_l1_in_0_ ( .in ( in ) , .mem ( sram[0] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) , @@ -90610,11 +94065,6 @@ sb_0__0__mux_2level_tapbuf_basis_input2_mem1_9 mux_l2_in_0_ ( .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_78 ( .A ( BUF_net_79 ) , .Y ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_79 ( - .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_79 ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -90752,10 +94202,8 @@ sb_0__0__mux_2level_tapbuf_basis_input2_mem1_5 mux_l2_in_0_ ( .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_76 ( .A ( BUF_net_77 ) , .Y ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_77 ( - .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_77 ) , +sky130_fd_sc_hd__buf_6 BUFT_RR_75 ( + .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -90824,10 +94272,8 @@ sb_0__0__mux_2level_tapbuf_basis_input2_mem1_3 mux_l2_in_0_ ( .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_74 ( .A ( BUF_net_75 ) , .Y ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_75 ( - .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_75 ) , +sky130_fd_sc_hd__buf_6 BUFT_RR_74 ( + .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -90933,6 +94379,7 @@ input prog_clk_0_E_in ; input VDD ; input VSS ; +wire ropt_net_136 ; wire [0:0] prog_clk ; wire prog_clk_0 ; wire [0:1] mux_2level_tapbuf_size2_0_sram ; @@ -91014,25 +94461,25 @@ sb_0__0__mux_2level_tapbuf_size2_0 mux_top_track_0 ( .sram ( mux_2level_tapbuf_size2_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 } ) , .out ( chany_top_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_106 ) ) ; + .p0 ( optlc_net_103 ) ) ; sb_0__0__mux_2level_tapbuf_size2_1 mux_top_track_6 ( .in ( { top_left_grid_pin_1_[0] , chanx_right_in[4] } ) , .sram ( mux_2level_tapbuf_size2_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) , .out ( chany_top_out[3] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_106 ) ) ; + .p0 ( optlc_net_103 ) ) ; sb_0__0__mux_2level_tapbuf_size2_2 mux_top_track_12 ( .in ( { top_left_grid_pin_1_[0] , chanx_right_in[7] } ) , .sram ( mux_2level_tapbuf_size2_2_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 } ) , .out ( chany_top_out[6] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_106 ) ) ; + .p0 ( optlc_net_103 ) ) ; sb_0__0__mux_2level_tapbuf_size2_3 mux_top_track_28 ( .in ( { top_left_grid_pin_1_[0] , chanx_right_in[15] } ) , .sram ( mux_2level_tapbuf_size2_3_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 } ) , .out ( chany_top_out[14] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_105 ) ) ; + .p0 ( optlc_net_103 ) ) ; sb_0__0__mux_2level_tapbuf_size2_4 mux_top_track_44 ( .in ( { top_left_grid_pin_1_[0] , chanx_right_in[23] } ) , .sram ( mux_2level_tapbuf_size2_4_sram ) , @@ -91044,19 +94491,19 @@ sb_0__0__mux_2level_tapbuf_size2_5 mux_right_track_14 ( .sram ( mux_2level_tapbuf_size2_5_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_11 , SYNOPSYS_UNCONNECTED_12 } ) , .out ( chanx_right_out[7] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_108 ) ) ; + .p0 ( optlc_net_103 ) ) ; sb_0__0__mux_2level_tapbuf_size2_6 mux_right_track_16 ( .in ( { chany_top_in[7] , right_bottom_grid_pin_5_[0] } ) , .sram ( mux_2level_tapbuf_size2_6_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 } ) , .out ( chanx_right_out[8] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_104 ) ) ; + .p0 ( optlc_net_103 ) ) ; sb_0__0__mux_2level_tapbuf_size2_7 mux_right_track_18 ( .in ( { chany_top_in[8] , right_bottom_grid_pin_7_[0] } ) , .sram ( mux_2level_tapbuf_size2_7_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_15 , SYNOPSYS_UNCONNECTED_16 } ) , .out ( chanx_right_out[9] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_104 ) ) ; + .p0 ( optlc_net_103 ) ) ; sb_0__0__mux_2level_tapbuf_size2_8 mux_right_track_20 ( .in ( { chany_top_in[9] , right_bottom_grid_pin_9_[0] } ) , .sram ( mux_2level_tapbuf_size2_8_sram ) , @@ -91086,25 +94533,25 @@ sb_0__0__mux_2level_tapbuf_size2_12 mux_right_track_30 ( .sram ( mux_2level_tapbuf_size2_12_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_25 , SYNOPSYS_UNCONNECTED_26 } ) , .out ( chanx_right_out[15] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_104 ) ) ; + .p0 ( optlc_net_103 ) ) ; sb_0__0__mux_2level_tapbuf_size2_13 mux_right_track_32 ( .in ( { chany_top_in[15] , right_bottom_grid_pin_5_[0] } ) , .sram ( mux_2level_tapbuf_size2_13_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_27 , SYNOPSYS_UNCONNECTED_28 } ) , .out ( chanx_right_out[16] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_104 ) ) ; + .p0 ( optlc_net_103 ) ) ; sb_0__0__mux_2level_tapbuf_size2_14 mux_right_track_34 ( .in ( { chany_top_in[16] , right_bottom_grid_pin_7_[0] } ) , .sram ( mux_2level_tapbuf_size2_14_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_29 , SYNOPSYS_UNCONNECTED_30 } ) , .out ( chanx_right_out[17] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_104 ) ) ; + .p0 ( optlc_net_103 ) ) ; sb_0__0__mux_2level_tapbuf_size2_15 mux_right_track_36 ( .in ( { chany_top_in[17] , right_bottom_grid_pin_9_[0] } ) , .sram ( mux_2level_tapbuf_size2_15_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_31 , SYNOPSYS_UNCONNECTED_32 } ) , .out ( chanx_right_out[18] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_106 ) ) ; + .p0 ( optlc_net_103 ) ) ; sb_0__0__mux_2level_tapbuf_size2_16 mux_right_track_38 ( .in ( { chany_top_in[18] , right_bottom_grid_pin_11_[0] } ) , .sram ( mux_2level_tapbuf_size2_16_sram ) , @@ -91116,7 +94563,7 @@ sb_0__0__mux_2level_tapbuf_size2_17 mux_right_track_40 ( .sram ( mux_2level_tapbuf_size2_17_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_35 , SYNOPSYS_UNCONNECTED_36 } ) , .out ( chanx_right_out[20] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_105 ) ) ; + .p0 ( optlc_net_106 ) ) ; sb_0__0__mux_2level_tapbuf_size2_18 mux_right_track_42 ( .in ( { chany_top_in[20] , right_bottom_grid_pin_15_[0] } ) , .sram ( mux_2level_tapbuf_size2_18_sram ) , @@ -91134,13 +94581,13 @@ sb_0__0__mux_2level_tapbuf_size2_20 mux_right_track_48 ( .sram ( mux_2level_tapbuf_size2_20_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_41 , SYNOPSYS_UNCONNECTED_42 } ) , .out ( chanx_right_out[24] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_104 ) ) ; + .p0 ( optlc_net_105 ) ) ; sb_0__0__mux_2level_tapbuf_size2_21 mux_right_track_50 ( .in ( { chany_top_in[24] , right_bottom_grid_pin_7_[0] } ) , .sram ( mux_2level_tapbuf_size2_21_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_43 , SYNOPSYS_UNCONNECTED_44 } ) , .out ( chanx_right_out[25] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_104 ) ) ; + .p0 ( optlc_net_103 ) ) ; sb_0__0__mux_2level_tapbuf_size2_22 mux_right_track_52 ( .in ( { chany_top_in[25] , right_bottom_grid_pin_9_[0] } ) , .sram ( mux_2level_tapbuf_size2_22_sram ) , @@ -91152,7 +94599,7 @@ sb_0__0__mux_2level_tapbuf_size2_23 mux_right_track_54 ( .sram ( mux_2level_tapbuf_size2_23_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_47 , SYNOPSYS_UNCONNECTED_48 } ) , .out ( chanx_right_out[27] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_105 ) ) ; + .p0 ( optlc_net_106 ) ) ; sb_0__0__mux_2level_tapbuf_size2_24 mux_right_track_56 ( .in ( { chany_top_in[27] , right_bottom_grid_pin_13_[0] } ) , .sram ( mux_2level_tapbuf_size2_24_sram ) , @@ -91334,7 +94781,7 @@ sb_0__0__mux_2level_tapbuf_size4_1 mux_right_track_2 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_57 , SYNOPSYS_UNCONNECTED_58 , SYNOPSYS_UNCONNECTED_59 , SYNOPSYS_UNCONNECTED_60 } ) , .out ( chanx_right_out[1] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_108 ) ) ; + .p0 ( optlc_net_104 ) ) ; sb_0__0__mux_2level_tapbuf_size4_2 mux_right_track_4 ( .in ( { chany_top_in[1] , right_bottom_grid_pin_5_[0] , right_bottom_grid_pin_11_[0] , right_bottom_grid_pin_17_[0] } ) , @@ -91358,7 +94805,7 @@ sb_0__0__mux_2level_tapbuf_size4_4 mux_right_track_8 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_69 , SYNOPSYS_UNCONNECTED_70 , SYNOPSYS_UNCONNECTED_71 , SYNOPSYS_UNCONNECTED_72 } ) , .out ( chanx_right_out[4] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_108 ) ) ; + .p0 ( optlc_net_104 ) ) ; sb_0__0__mux_2level_tapbuf_size4 mux_right_track_10 ( .in ( { chany_top_in[4] , right_bottom_grid_pin_5_[0] , right_bottom_grid_pin_11_[0] , right_bottom_grid_pin_17_[0] } ) , @@ -91366,7 +94813,7 @@ sb_0__0__mux_2level_tapbuf_size4 mux_right_track_10 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_73 , SYNOPSYS_UNCONNECTED_74 , SYNOPSYS_UNCONNECTED_75 , SYNOPSYS_UNCONNECTED_76 } ) , .out ( chanx_right_out[5] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_108 ) ) ; + .p0 ( optlc_net_104 ) ) ; sb_0__0__mux_2level_tapbuf_size4_mem_0 mem_right_track_0 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( mux_2level_tapbuf_size2_mem_4_ccff_tail ) , @@ -91409,7 +94856,7 @@ sb_0__0__mux_2level_tapbuf_size3_0 mux_right_track_12 ( .sram ( mux_2level_tapbuf_size3_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_77 , SYNOPSYS_UNCONNECTED_78 } ) , .out ( chanx_right_out[6] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_108 ) ) ; + .p0 ( optlc_net_105 ) ) ; sb_0__0__mux_2level_tapbuf_size3_1 mux_right_track_28 ( .in ( { chany_top_in[13] , right_bottom_grid_pin_1_[0] , right_bottom_grid_pin_17_[0] } ) , @@ -91466,7 +94913,7 @@ sky130_fd_sc_hd__buf_8 FTB_56__55 ( .A ( chanx_right_in[11] ) , .X ( chany_top_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_8 FTB_57__56 ( .A ( chanx_right_in[12] ) , .X ( chany_top_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_8 FTB_58__57 ( .A ( chanx_right_in[13] ) , +sky130_fd_sc_hd__buf_6 FTB_58__57 ( .A ( chanx_right_in[13] ) , .X ( chany_top_out[12] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_8 FTB_59__58 ( .A ( chanx_right_in[14] ) , .X ( chany_top_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -91490,22 +94937,24 @@ sky130_fd_sc_hd__buf_8 FTB_68__67 ( .A ( chanx_right_in[25] ) , .X ( chany_top_out[24] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_6 FTB_69__68 ( .A ( chanx_right_in[26] ) , .X ( chany_top_out[25] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_8 FTB_70__69 ( .A ( chanx_right_in[27] ) , - .X ( chany_top_out[26] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 FTB_70__69 ( .A ( chanx_right_in[27] ) , + .X ( ropt_net_136 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_8 FTB_71__70 ( .A ( chanx_right_in[28] ) , .X ( chany_top_out[27] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_8 FTB_72__71 ( .A ( chanx_right_in[29] ) , .X ( chany_top_out[28] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_106 ( .LO ( SYNOPSYS_UNCONNECTED_83 ) , +sky130_fd_sc_hd__conb_1 optlc_105 ( .LO ( SYNOPSYS_UNCONNECTED_83 ) , + .HI ( optlc_net_103 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_107 ( .LO ( SYNOPSYS_UNCONNECTED_84 ) , .HI ( optlc_net_104 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_109 ( .LO ( SYNOPSYS_UNCONNECTED_84 ) , +sky130_fd_sc_hd__conb_1 optlc_109 ( .LO ( SYNOPSYS_UNCONNECTED_85 ) , .HI ( optlc_net_105 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_111 ( .LO ( SYNOPSYS_UNCONNECTED_85 ) , +sky130_fd_sc_hd__conb_1 optlc_111 ( .LO ( SYNOPSYS_UNCONNECTED_86 ) , .HI ( optlc_net_106 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_113 ( .LO ( SYNOPSYS_UNCONNECTED_86 ) , +sky130_fd_sc_hd__conb_1 optlc_113 ( .LO ( SYNOPSYS_UNCONNECTED_87 ) , .HI ( optlc_net_107 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_115 ( .LO ( SYNOPSYS_UNCONNECTED_87 ) , - .HI ( optlc_net_108 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1317 ( .A ( ropt_net_136 ) , + .X ( chany_top_out[26] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -91528,18 +94977,18 @@ sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_6 FTB_111__110 ( .A ( copt_net_248 ) , +sky130_fd_sc_hd__buf_6 FTB_111__110 ( .A ( copt_net_243 ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1706 ( .A ( copt_net_250 ) , - .X ( copt_net_246 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1707 ( .A ( copt_net_246 ) , - .X ( copt_net_247 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1708 ( .A ( copt_net_247 ) , - .X ( copt_net_248 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1709 ( .A ( mem_out[1] ) , - .X ( copt_net_249 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1710 ( .A ( copt_net_249 ) , - .X ( copt_net_250 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1596 ( .A ( mem_out[1] ) , + .X ( copt_net_239 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1597 ( .A ( copt_net_242 ) , + .X ( copt_net_240 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1598 ( .A ( copt_net_240 ) , + .X ( copt_net_241 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1599 ( .A ( copt_net_239 ) , + .X ( copt_net_242 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1600 ( .A ( copt_net_241 ) , + .X ( copt_net_243 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -91568,19 +95017,19 @@ endmodule module grid_clb_mux_1level_basis_input3_mem3 ( in , mem , mem_inv , out , - VDD , VSS , p0 ) ; + VDD , VSS , p3 ) ; input [0:2] in ; input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; input VDD ; input VSS ; -input p0 ; +input p3 ; supply1 VDD ; supply0 VSS ; -scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , +scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p3 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -91613,14 +95062,14 @@ endmodule module grid_clb_mux_1level_size2 ( in , sram , sram_inv , out , VDD , VSS , - p0 ) ; + p3 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; output [0:0] out ; input VDD ; input VSS ; -input p0 ; +input p3 ; wire [0:2] local_encoder2to3_0_data ; wire [0:2] local_encoder2to3_0_data_inv ; @@ -91639,7 +95088,7 @@ grid_clb_mux_1level_basis_input3_mem3 mux_l1_in_0_ ( .mem ( local_encoder2to3_0_data ) , .mem_inv ( local_encoder2to3_0_data_inv ) , .out ( mux_1level_basis_input3_mem3_0_out ) , .VDD ( VDD ) , - .VSS ( VSS ) , .p0 ( p0 ) ) ; + .VSS ( VSS ) , .p3 ( p3 ) ) ; endmodule @@ -91838,10 +95287,10 @@ grid_clb_mux_1level_tapbuf_basis_input3_mem3 mux_l1_in_0_ ( .mem_inv ( local_encoder2to3_0_data_inv ) , .out ( mux_1level_tapbuf_basis_input3_mem3_0_out ) , .VDD ( VDD ) , .VSS ( VSS ) , .p3 ( p3 ) ) ; -sky130_fd_sc_hd__inv_2 BINV_R_178 ( +sky130_fd_sc_hd__inv_8 BINV_R_177 ( .A ( mux_1level_tapbuf_basis_input3_mem3_0_out[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_179 ( +sky130_fd_sc_hd__inv_2 BINV_R_178 ( .A ( mux_1level_tapbuf_basis_input3_mem3_0_out[0] ) , .Y ( p_abuf0 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -91918,10 +95367,10 @@ grid_clb_mux_1level_tapbuf_basis_input3_mem3_14 mux_l1_in_0_ ( .mem_inv ( local_encoder2to3_0_data_inv ) , .out ( mux_1level_tapbuf_basis_input3_mem3_0_out ) , .VDD ( VDD ) , .VSS ( VSS ) , .p3 ( p3 ) ) ; -sky130_fd_sc_hd__inv_2 BINV_R_175 ( +sky130_fd_sc_hd__inv_2 BINV_R_174 ( .A ( mux_1level_tapbuf_basis_input3_mem3_0_out[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_176 ( +sky130_fd_sc_hd__inv_8 BINV_R_175 ( .A ( mux_1level_tapbuf_basis_input3_mem3_0_out[0] ) , .Y ( p_abuf0 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -91929,7 +95378,7 @@ endmodule module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff ( Test_en , ff_D , ff_DI , ff_reset , ff_Q , ff_clk , VDD , VSS , p_abuf0 , - p_abuf1 , p_abuf2 ) ; + p_abuf1 ) ; input [0:0] Test_en ; input [0:0] ff_D ; input [0:0] ff_DI ; @@ -91940,22 +95389,19 @@ input VDD ; input VSS ; output p_abuf0 ; output p_abuf1 ; -output p_abuf2 ; supply1 VDD ; supply0 VSS ; sky130_fd_sc_hd__sdfrtp_1 sky130_fd_sc_hd__sdfrtp_1_0_ ( .D ( ff_D[0] ) , .SCD ( ff_DI[0] ) , .SCE ( Test_en[0] ) , .CLK ( ff_clk[0] ) , - .RESET_B ( ff_reset[0] ) , .Q ( p_abuf2 ) , .VPWR ( VDD ) , + .RESET_B ( ff_reset[0] ) , .Q ( p_abuf1 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_2 BINV_R_129 ( .A ( BUF_net_132 ) , .Y ( ff_Q[0] ) , +sky130_fd_sc_hd__inv_8 BINV_R_129 ( .A ( BUF_net_131 ) , .Y ( ff_Q[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_130 ( .A ( BUF_net_132 ) , .Y ( p_abuf0 ) , +sky130_fd_sc_hd__inv_2 BINV_R_130 ( .A ( BUF_net_131 ) , .Y ( p_abuf0 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_131 ( .A ( BUF_net_132 ) , .Y ( p_abuf1 ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_132 ( .A ( p_abuf2 ) , .Y ( BUF_net_132 ) , +sky130_fd_sc_hd__inv_1 BINV_R_131 ( .A ( p_abuf1 ) , .Y ( BUF_net_131 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -92528,7 +95974,7 @@ module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric ( pReset , prog_clk , Test_en , fabric_in , fabric_reg_in , fabric_sc_in , fabric_cin , fabric_reset , fabric_clk , ccff_head , fabric_out , fabric_reg_out , fabric_sc_out , fabric_cout , ccff_tail , VDD , VSS , - p_abuf0 , p_abuf3 , p_abuf4 , p0 , p3 ) ; + p_abuf0 , p_abuf2 , p_abuf3 , p0 , p3 ) ; input [0:0] pReset ; input [0:0] prog_clk ; input [0:0] Test_en ; @@ -92547,8 +95993,8 @@ output [0:0] ccff_tail ; input VDD ; input VSS ; output p_abuf0 ; +output p_abuf2 ; output p_abuf3 ; -output p_abuf4 ; input p0 ; input p3 ; @@ -92588,8 +96034,7 @@ grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ .ff_DI ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ) , .ff_reset ( fabric_reset ) , .ff_Q ( fabric_sc_out ) , .ff_clk ( fabric_clk ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p_abuf0 ( aps_rename_506_ ) , .p_abuf1 ( p_abuf0 ) , - .p_abuf2 ( p_abuf2 ) ) ; + .p_abuf0 ( p_abuf0 ) , .p_abuf1 ( p_abuf1 ) ) ; grid_clb_mux_1level_tapbuf_size2_14 mux_fabric_out_0 ( .in ( { logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q[0] , @@ -92598,15 +96043,15 @@ grid_clb_mux_1level_tapbuf_size2_14 mux_fabric_out_0 ( .sram ( mux_1level_tapbuf_size2_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_2 , SYNOPSYS_UNCONNECTED_3 } ) , .out ( fabric_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p_abuf0 ( p_abuf3 ) , .p3 ( p3 ) ) ; + .p_abuf0 ( p_abuf2 ) , .p3 ( p3 ) ) ; grid_clb_mux_1level_tapbuf_size2 mux_fabric_out_1 ( - .in ( { aps_rename_506_ , + .in ( { p_abuf0 , logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] } ) , .sram ( mux_1level_tapbuf_size2_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_4 , SYNOPSYS_UNCONNECTED_5 } ) , .out ( fabric_out[1] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p_abuf0 ( p_abuf4 ) , .p3 ( p3 ) ) ; + .p_abuf0 ( p_abuf3 ) , .p3 ( p3 ) ) ; grid_clb_mux_1level_tapbuf_size2_mem_14 mem_fabric_out_0 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) , @@ -92619,7 +96064,7 @@ grid_clb_mux_1level_tapbuf_size2_mem mem_fabric_out_1 ( .pReset ( pReset ) , .ccff_tail ( mux_1level_tapbuf_size2_mem_1_ccff_tail ) , .mem_out ( mux_1level_tapbuf_size2_1_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sky130_fd_sc_hd__buf_6 FTB_112__111 ( .A ( p_abuf2 ) , +sky130_fd_sc_hd__buf_6 FTB_112__111 ( .A ( p_abuf1 ) , .X ( fabric_reg_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; grid_clb_mux_1level_size2_30 mux_ff_0_D_0 ( .in ( { @@ -92637,7 +96082,7 @@ grid_clb_mux_1level_size2 mux_ff_1_D_0 ( .sram ( mux_1level_size2_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_8 , SYNOPSYS_UNCONNECTED_9 } ) , .out ( mux_1level_size2_1_out ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( p0 ) ) ; + .p3 ( p3 ) ) ; grid_clb_mux_1level_size2_mem_30 mem_ff_0_D_0 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( mux_1level_tapbuf_size2_mem_1_ccff_tail ) , @@ -92689,8 +96134,8 @@ grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric logical_tile_c .ccff_head ( ccff_head ) , .fabric_out ( fle_out ) , .fabric_reg_out ( fle_reg_out ) , .fabric_sc_out ( fle_sc_out ) , .fabric_cout ( fle_cout ) , .ccff_tail ( ccff_tail ) , .VDD ( VDD ) , - .VSS ( VSS ) , .p_abuf0 ( p_abuf0 ) , .p_abuf3 ( p_abuf1 ) , - .p_abuf4 ( p_abuf2 ) , .p0 ( p0 ) , .p3 ( p3 ) ) ; + .VSS ( VSS ) , .p_abuf0 ( p_abuf0 ) , .p_abuf2 ( p_abuf1 ) , + .p_abuf3 ( p_abuf2 ) , .p0 ( p0 ) , .p3 ( p3 ) ) ; endmodule @@ -92743,19 +96188,19 @@ endmodule module grid_clb_mux_1level_basis_input3_mem3_27 ( in , mem , mem_inv , out , - VDD , VSS , p6 ) ; + VDD , VSS , p3 ) ; input [0:2] in ; input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; input VDD ; input VSS ; -input p6 ; +input p3 ; supply1 VDD ; supply0 VSS ; -scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p6 ) , +scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p3 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -92788,14 +96233,14 @@ endmodule module grid_clb_mux_1level_size2_27 ( in , sram , sram_inv , out , VDD , VSS , - p6 ) ; + p3 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; output [0:0] out ; input VDD ; input VSS ; -input p6 ; +input p3 ; wire [0:2] local_encoder2to3_0_data ; wire [0:2] local_encoder2to3_0_data_inv ; @@ -92814,24 +96259,24 @@ grid_clb_mux_1level_basis_input3_mem3_27 mux_l1_in_0_ ( .mem ( local_encoder2to3_0_data ) , .mem_inv ( local_encoder2to3_0_data_inv ) , .out ( mux_1level_basis_input3_mem3_0_out ) , .VDD ( VDD ) , - .VSS ( VSS ) , .p6 ( p6 ) ) ; + .VSS ( VSS ) , .p3 ( p3 ) ) ; endmodule module grid_clb_mux_1level_basis_input3_mem3_26 ( in , mem , mem_inv , out , - VDD , VSS , p6 ) ; + VDD , VSS , p0 ) ; input [0:2] in ; input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; input VDD ; input VSS ; -input p6 ; +input p0 ; supply1 VDD ; supply0 VSS ; -scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p6 ) , +scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -92864,14 +96309,14 @@ endmodule module grid_clb_mux_1level_size2_26 ( in , sram , sram_inv , out , VDD , VSS , - p6 ) ; + p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; output [0:0] out ; input VDD ; input VSS ; -input p6 ; +input p0 ; wire [0:2] local_encoder2to3_0_data ; wire [0:2] local_encoder2to3_0_data_inv ; @@ -92890,7 +96335,7 @@ grid_clb_mux_1level_basis_input3_mem3_26 mux_l1_in_0_ ( .mem ( local_encoder2to3_0_data ) , .mem_inv ( local_encoder2to3_0_data_inv ) , .out ( mux_1level_basis_input3_mem3_0_out ) , .VDD ( VDD ) , - .VSS ( VSS ) , .p6 ( p6 ) ) ; + .VSS ( VSS ) , .p0 ( p0 ) ) ; endmodule @@ -93013,10 +96458,10 @@ grid_clb_mux_1level_tapbuf_basis_input3_mem3_13 mux_l1_in_0_ ( .mem_inv ( local_encoder2to3_0_data_inv ) , .out ( mux_1level_tapbuf_basis_input3_mem3_0_out ) , .VDD ( VDD ) , .VSS ( VSS ) , .p3 ( p3 ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_172 ( +sky130_fd_sc_hd__inv_8 BINV_R_171 ( .A ( mux_1level_tapbuf_basis_input3_mem3_0_out[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_173 ( +sky130_fd_sc_hd__inv_1 BINV_R_172 ( .A ( mux_1level_tapbuf_basis_input3_mem3_0_out[0] ) , .Y ( p_abuf0 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -93093,10 +96538,10 @@ grid_clb_mux_1level_tapbuf_basis_input3_mem3_12 mux_l1_in_0_ ( .mem_inv ( local_encoder2to3_0_data_inv ) , .out ( mux_1level_tapbuf_basis_input3_mem3_0_out ) , .VDD ( VDD ) , .VSS ( VSS ) , .p3 ( p3 ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_169 ( +sky130_fd_sc_hd__inv_1 BINV_R_168 ( .A ( mux_1level_tapbuf_basis_input3_mem3_0_out[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_170 ( +sky130_fd_sc_hd__inv_8 BINV_R_169 ( .A ( mux_1level_tapbuf_basis_input3_mem3_0_out[0] ) , .Y ( p_abuf0 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -93269,19 +96714,19 @@ endmodule module grid_clb_mux_1level_basis_input3_mem3_24 ( in , mem , mem_inv , out , - VDD , VSS , p6 ) ; + VDD , VSS , p3 ) ; input [0:2] in ; input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; input VDD ; input VSS ; -input p6 ; +input p3 ; supply1 VDD ; supply0 VSS ; -scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p6 ) , +scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p3 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -93314,14 +96759,14 @@ endmodule module grid_clb_mux_1level_size2_24 ( in , sram , sram_inv , out , VDD , VSS , - p6 ) ; + p3 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; output [0:0] out ; input VDD ; input VSS ; -input p6 ; +input p3 ; wire [0:2] local_encoder2to3_0_data ; wire [0:2] local_encoder2to3_0_data_inv ; @@ -93340,7 +96785,7 @@ grid_clb_mux_1level_basis_input3_mem3_24 mux_l1_in_0_ ( .mem ( local_encoder2to3_0_data ) , .mem_inv ( local_encoder2to3_0_data_inv ) , .out ( mux_1level_basis_input3_mem3_0_out ) , .VDD ( VDD ) , - .VSS ( VSS ) , .p6 ( p6 ) ) ; + .VSS ( VSS ) , .p3 ( p3 ) ) ; endmodule @@ -93617,7 +97062,7 @@ endmodule module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_6 ( pReset , prog_clk , frac_logic_in , frac_logic_cin , ccff_head , - frac_logic_out , frac_logic_cout , ccff_tail , VDD , VSS , p3 , p6 ) ; + frac_logic_out , frac_logic_cout , ccff_tail , VDD , VSS , p3 ) ; input [0:0] pReset ; input [0:0] prog_clk ; input [0:3] frac_logic_in ; @@ -93629,7 +97074,6 @@ output [0:0] ccff_tail ; input VDD ; input VSS ; input p3 ; -input p6 ; wire [0:0] direct_interc_5_out ; wire [0:0] direct_interc_7_out ; @@ -93669,7 +97113,7 @@ grid_clb_mux_1level_size2_24 mux_frac_logic_out_0 ( } ) , .sram ( mux_1level_size2_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_2 , SYNOPSYS_UNCONNECTED_3 } ) , - .out ( frac_logic_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , .p6 ( p6 ) ) ; + .out ( frac_logic_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , .p3 ( p3 ) ) ; grid_clb_mux_1level_size2_25 mux_frac_lut4_0_in_2 ( .in ( { frac_logic_cin[0] , frac_logic_in[2] } ) , .sram ( mux_1level_size2_1_sram ) , @@ -93692,7 +97136,7 @@ module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_6 ( pReset , prog_clk , Test_en , fabric_in , fabric_reg_in , fabric_sc_in , fabric_cin , fabric_reset , fabric_clk , ccff_head , fabric_out , fabric_reg_out , fabric_sc_out , fabric_cout , ccff_tail , VDD , VSS , - p_abuf0 , p_abuf1 , p3 , p6 ) ; + p_abuf0 , p_abuf1 , p0 , p3 ) ; input [0:0] pReset ; input [0:0] prog_clk ; input [0:0] Test_en ; @@ -93712,8 +97156,8 @@ input VDD ; input VSS ; output p_abuf0 ; output p_abuf1 ; +input p0 ; input p3 ; -input p6 ; wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ; wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ; @@ -93740,7 +97184,7 @@ grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ .frac_logic_cout ( { SYNOPSYS_UNCONNECTED_1 } ) , .ccff_tail ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) , - .VDD ( VDD ) , .VSS ( VSS ) , .p3 ( p3 ) , .p6 ( p6 ) ) ; + .VDD ( VDD ) , .VSS ( VSS ) , .p3 ( p3 ) ) ; grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_12 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0 ( .Test_en ( Test_en ) , .ff_D ( mux_1level_size2_0_out ) , .ff_DI ( fabric_sc_in ) , .ff_reset ( fabric_reset ) , @@ -93789,7 +97233,7 @@ grid_clb_mux_1level_size2_26 mux_ff_0_D_0 ( .sram ( mux_1level_size2_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_6 , SYNOPSYS_UNCONNECTED_7 } ) , .out ( mux_1level_size2_0_out ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p6 ( p6 ) ) ; + .p0 ( p0 ) ) ; grid_clb_mux_1level_size2_27 mux_ff_1_D_0 ( .in ( { logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] , @@ -93798,7 +97242,7 @@ grid_clb_mux_1level_size2_27 mux_ff_1_D_0 ( .sram ( mux_1level_size2_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_8 , SYNOPSYS_UNCONNECTED_9 } ) , .out ( mux_1level_size2_1_out ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p6 ( p6 ) ) ; + .p3 ( p3 ) ) ; grid_clb_mux_1level_size2_mem_26 mem_ff_0_D_0 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( mux_1level_tapbuf_size2_mem_1_ccff_tail ) , @@ -93814,7 +97258,7 @@ endmodule module grid_clb_logical_tile_clb_mode_default__fle_6 ( pReset , prog_clk , Test_en , fle_in , fle_reg_in , fle_sc_in , fle_cin , fle_reset , fle_clk , ccff_head , fle_out , fle_reg_out , fle_sc_out , fle_cout , - ccff_tail , VDD , VSS , p_abuf0 , p_abuf1 , p3 , p6 ) ; + ccff_tail , VDD , VSS , p_abuf0 , p_abuf1 , p0 , p3 ) ; input [0:0] pReset ; input [0:0] prog_clk ; input [0:0] Test_en ; @@ -93834,8 +97278,8 @@ input VDD ; input VSS ; output p_abuf0 ; output p_abuf1 ; +input p0 ; input p3 ; -input p6 ; supply1 VDD ; supply0 VSS ; @@ -93850,7 +97294,7 @@ grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_6 logical_tile .fabric_reg_out ( fle_reg_out ) , .fabric_sc_out ( fle_sc_out ) , .fabric_cout ( { SYNOPSYS_UNCONNECTED_2 } ) , .ccff_tail ( ccff_tail ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p_abuf0 ( p_abuf0 ) , .p_abuf1 ( p_abuf1 ) , .p3 ( p3 ) , .p6 ( p6 ) ) ; + .p_abuf0 ( p_abuf0 ) , .p_abuf1 ( p_abuf1 ) , .p0 ( p0 ) , .p3 ( p3 ) ) ; endmodule @@ -93979,19 +97423,19 @@ endmodule module grid_clb_mux_1level_basis_input3_mem3_22 ( in , mem , mem_inv , out , - VDD , VSS , p6 ) ; + VDD , VSS , p0 ) ; input [0:2] in ; input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; input VDD ; input VSS ; -input p6 ; +input p0 ; supply1 VDD ; supply0 VSS ; -scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p6 ) , +scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -94024,14 +97468,14 @@ endmodule module grid_clb_mux_1level_size2_22 ( in , sram , sram_inv , out , VDD , VSS , - p6 ) ; + p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; output [0:0] out ; input VDD ; input VSS ; -input p6 ; +input p0 ; wire [0:2] local_encoder2to3_0_data ; wire [0:2] local_encoder2to3_0_data_inv ; @@ -94050,7 +97494,7 @@ grid_clb_mux_1level_basis_input3_mem3_22 mux_l1_in_0_ ( .mem ( local_encoder2to3_0_data ) , .mem_inv ( local_encoder2to3_0_data_inv ) , .out ( mux_1level_basis_input3_mem3_0_out ) , .VDD ( VDD ) , - .VSS ( VSS ) , .p6 ( p6 ) ) ; + .VSS ( VSS ) , .p0 ( p0 ) ) ; endmodule @@ -94103,19 +97547,19 @@ endmodule module grid_clb_mux_1level_tapbuf_basis_input3_mem3_11 ( in , mem , mem_inv , - out , VDD , VSS , p6 ) ; + out , VDD , VSS , p3 ) ; input [0:2] in ; input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; input VDD ; input VSS ; -input p6 ; +input p3 ; supply1 VDD ; supply0 VSS ; -scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p6 ) , +scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p3 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -94148,7 +97592,7 @@ endmodule module grid_clb_mux_1level_tapbuf_size2_11 ( in , sram , sram_inv , out , - VDD , VSS , p_abuf0 , p6 ) ; + VDD , VSS , p_abuf0 , p3 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -94156,7 +97600,7 @@ output [0:0] out ; input VDD ; input VSS ; output p_abuf0 ; -input p6 ; +input p3 ; wire [0:2] local_encoder2to3_0_data ; wire [0:2] local_encoder2to3_0_data_inv ; @@ -94172,30 +97616,30 @@ grid_clb_mux_1level_tapbuf_basis_input3_mem3_11 mux_l1_in_0_ ( .mem ( local_encoder2to3_0_data ) , .mem_inv ( local_encoder2to3_0_data_inv ) , .out ( mux_1level_tapbuf_basis_input3_mem3_0_out ) , .VDD ( VDD ) , - .VSS ( VSS ) , .p6 ( p6 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_166 ( + .VSS ( VSS ) , .p3 ( p3 ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_165 ( .A ( mux_1level_tapbuf_basis_input3_mem3_0_out[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_167 ( +sky130_fd_sc_hd__inv_8 BINV_R_166 ( .A ( mux_1level_tapbuf_basis_input3_mem3_0_out[0] ) , .Y ( p_abuf0 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module grid_clb_mux_1level_tapbuf_basis_input3_mem3_10 ( in , mem , mem_inv , - out , VDD , VSS , p6 ) ; + out , VDD , VSS , p3 ) ; input [0:2] in ; input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; input VDD ; input VSS ; -input p6 ; +input p3 ; supply1 VDD ; supply0 VSS ; -scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p6 ) , +scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p3 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -94228,7 +97672,7 @@ endmodule module grid_clb_mux_1level_tapbuf_size2_10 ( in , sram , sram_inv , out , - VDD , VSS , p_abuf0 , p6 ) ; + VDD , VSS , p_abuf0 , p3 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -94236,7 +97680,7 @@ output [0:0] out ; input VDD ; input VSS ; output p_abuf0 ; -input p6 ; +input p3 ; wire [0:2] local_encoder2to3_0_data ; wire [0:2] local_encoder2to3_0_data_inv ; @@ -94252,11 +97696,11 @@ grid_clb_mux_1level_tapbuf_basis_input3_mem3_10 mux_l1_in_0_ ( .mem ( local_encoder2to3_0_data ) , .mem_inv ( local_encoder2to3_0_data_inv ) , .out ( mux_1level_tapbuf_basis_input3_mem3_0_out ) , .VDD ( VDD ) , - .VSS ( VSS ) , .p6 ( p6 ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_163 ( + .VSS ( VSS ) , .p3 ( p3 ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_162 ( .A ( mux_1level_tapbuf_basis_input3_mem3_0_out[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_164 ( +sky130_fd_sc_hd__inv_8 BINV_R_163 ( .A ( mux_1level_tapbuf_basis_input3_mem3_0_out[0] ) , .Y ( p_abuf0 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -94851,7 +98295,7 @@ module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_5 ( pReset , prog_clk , Test_en , fabric_in , fabric_reg_in , fabric_sc_in , fabric_cin , fabric_reset , fabric_clk , ccff_head , fabric_out , fabric_reg_out , fabric_sc_out , fabric_cout , ccff_tail , VDD , VSS , - p_abuf0 , p_abuf1 , p6 ) ; + p_abuf0 , p_abuf1 , p0 , p3 , p6 ) ; input [0:0] pReset ; input [0:0] prog_clk ; input [0:0] Test_en ; @@ -94871,6 +98315,8 @@ input VDD ; input VSS ; output p_abuf0 ; output p_abuf1 ; +input p0 ; +input p3 ; input p6 ; wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ; @@ -94917,7 +98363,7 @@ grid_clb_mux_1level_tapbuf_size2_10 mux_fabric_out_0 ( .sram ( mux_1level_tapbuf_size2_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_2 , SYNOPSYS_UNCONNECTED_3 } ) , .out ( fabric_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p_abuf0 ( p_abuf0 ) , .p6 ( p6 ) ) ; + .p_abuf0 ( p_abuf0 ) , .p3 ( p3 ) ) ; grid_clb_mux_1level_tapbuf_size2_11 mux_fabric_out_1 ( .in ( { fabric_sc_out[0] , logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] @@ -94925,7 +98371,7 @@ grid_clb_mux_1level_tapbuf_size2_11 mux_fabric_out_1 ( .sram ( mux_1level_tapbuf_size2_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_4 , SYNOPSYS_UNCONNECTED_5 } ) , .out ( fabric_out[1] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p_abuf0 ( p_abuf1 ) , .p6 ( p6 ) ) ; + .p_abuf0 ( p_abuf1 ) , .p3 ( p3 ) ) ; grid_clb_mux_1level_tapbuf_size2_mem_10 mem_fabric_out_0 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) , @@ -94947,7 +98393,7 @@ grid_clb_mux_1level_size2_22 mux_ff_0_D_0 ( .sram ( mux_1level_size2_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_6 , SYNOPSYS_UNCONNECTED_7 } ) , .out ( mux_1level_size2_0_out ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p6 ( p6 ) ) ; + .p0 ( p0 ) ) ; grid_clb_mux_1level_size2_23 mux_ff_1_D_0 ( .in ( { logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] , @@ -94972,7 +98418,7 @@ endmodule module grid_clb_logical_tile_clb_mode_default__fle_5 ( pReset , prog_clk , Test_en , fle_in , fle_reg_in , fle_sc_in , fle_cin , fle_reset , fle_clk , ccff_head , fle_out , fle_reg_out , fle_sc_out , fle_cout , - ccff_tail , VDD , VSS , p_abuf0 , p_abuf1 , p6 ) ; + ccff_tail , VDD , VSS , p_abuf0 , p_abuf1 , p0 , p3 , p6 ) ; input [0:0] pReset ; input [0:0] prog_clk ; input [0:0] Test_en ; @@ -94992,6 +98438,8 @@ input VDD ; input VSS ; output p_abuf0 ; output p_abuf1 ; +input p0 ; +input p3 ; input p6 ; supply1 VDD ; @@ -95007,7 +98455,8 @@ grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_5 logical_tile .fabric_reg_out ( fle_reg_out ) , .fabric_sc_out ( fle_sc_out ) , .fabric_cout ( { SYNOPSYS_UNCONNECTED_2 } ) , .ccff_tail ( ccff_tail ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p_abuf0 ( p_abuf0 ) , .p_abuf1 ( p_abuf1 ) , .p6 ( p6 ) ) ; + .p_abuf0 ( p_abuf0 ) , .p_abuf1 ( p_abuf1 ) , .p0 ( p0 ) , .p3 ( p3 ) , + .p6 ( p6 ) ) ; endmodule @@ -95060,19 +98509,19 @@ endmodule module grid_clb_mux_1level_basis_input3_mem3_19 ( in , mem , mem_inv , out , - VDD , VSS , p0 ) ; + VDD , VSS , p6 ) ; input [0:2] in ; input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; input VDD ; input VSS ; -input p0 ; +input p6 ; supply1 VDD ; supply0 VSS ; -scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , +scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p6 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -95105,14 +98554,14 @@ endmodule module grid_clb_mux_1level_size2_19 ( in , sram , sram_inv , out , VDD , VSS , - p0 ) ; + p6 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; output [0:0] out ; input VDD ; input VSS ; -input p0 ; +input p6 ; wire [0:2] local_encoder2to3_0_data ; wire [0:2] local_encoder2to3_0_data_inv ; @@ -95131,24 +98580,24 @@ grid_clb_mux_1level_basis_input3_mem3_19 mux_l1_in_0_ ( .mem ( local_encoder2to3_0_data ) , .mem_inv ( local_encoder2to3_0_data_inv ) , .out ( mux_1level_basis_input3_mem3_0_out ) , .VDD ( VDD ) , - .VSS ( VSS ) , .p0 ( p0 ) ) ; + .VSS ( VSS ) , .p6 ( p6 ) ) ; endmodule module grid_clb_mux_1level_basis_input3_mem3_18 ( in , mem , mem_inv , out , - VDD , VSS , p0 ) ; + VDD , VSS , p6 ) ; input [0:2] in ; input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; input VDD ; input VSS ; -input p0 ; +input p6 ; supply1 VDD ; supply0 VSS ; -scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , +scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p6 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -95181,14 +98630,14 @@ endmodule module grid_clb_mux_1level_size2_18 ( in , sram , sram_inv , out , VDD , VSS , - p0 ) ; + p6 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; output [0:0] out ; input VDD ; input VSS ; -input p0 ; +input p6 ; wire [0:2] local_encoder2to3_0_data ; wire [0:2] local_encoder2to3_0_data_inv ; @@ -95207,7 +98656,7 @@ grid_clb_mux_1level_basis_input3_mem3_18 mux_l1_in_0_ ( .mem ( local_encoder2to3_0_data ) , .mem_inv ( local_encoder2to3_0_data_inv ) , .out ( mux_1level_basis_input3_mem3_0_out ) , .VDD ( VDD ) , - .VSS ( VSS ) , .p0 ( p0 ) ) ; + .VSS ( VSS ) , .p6 ( p6 ) ) ; endmodule @@ -95260,19 +98709,19 @@ endmodule module grid_clb_mux_1level_tapbuf_basis_input3_mem3_9 ( in , mem , mem_inv , - out , VDD , VSS , p0 ) ; + out , VDD , VSS , p6 ) ; input [0:2] in ; input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; input VDD ; input VSS ; -input p0 ; +input p6 ; supply1 VDD ; supply0 VSS ; -scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , +scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p6 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -95305,7 +98754,7 @@ endmodule module grid_clb_mux_1level_tapbuf_size2_9 ( in , sram , sram_inv , out , VDD , - VSS , p_abuf0 , p0 ) ; + VSS , p_abuf0 , p6 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -95313,7 +98762,7 @@ output [0:0] out ; input VDD ; input VSS ; output p_abuf0 ; -input p0 ; +input p6 ; wire [0:2] local_encoder2to3_0_data ; wire [0:2] local_encoder2to3_0_data_inv ; @@ -95329,30 +98778,30 @@ grid_clb_mux_1level_tapbuf_basis_input3_mem3_9 mux_l1_in_0_ ( .mem ( local_encoder2to3_0_data ) , .mem_inv ( local_encoder2to3_0_data_inv ) , .out ( mux_1level_tapbuf_basis_input3_mem3_0_out ) , .VDD ( VDD ) , - .VSS ( VSS ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_160 ( + .VSS ( VSS ) , .p6 ( p6 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_159 ( .A ( mux_1level_tapbuf_basis_input3_mem3_0_out[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_161 ( +sky130_fd_sc_hd__inv_1 BINV_R_160 ( .A ( mux_1level_tapbuf_basis_input3_mem3_0_out[0] ) , .Y ( p_abuf0 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module grid_clb_mux_1level_tapbuf_basis_input3_mem3_8 ( in , mem , mem_inv , - out , VDD , VSS , p0 ) ; + out , VDD , VSS , p6 ) ; input [0:2] in ; input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; input VDD ; input VSS ; -input p0 ; +input p6 ; supply1 VDD ; supply0 VSS ; -scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , +scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p6 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -95385,7 +98834,7 @@ endmodule module grid_clb_mux_1level_tapbuf_size2_8 ( in , sram , sram_inv , out , VDD , - VSS , p_abuf0 , p0 ) ; + VSS , p_abuf0 , p6 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -95393,7 +98842,7 @@ output [0:0] out ; input VDD ; input VSS ; output p_abuf0 ; -input p0 ; +input p6 ; wire [0:2] local_encoder2to3_0_data ; wire [0:2] local_encoder2to3_0_data_inv ; @@ -95409,11 +98858,11 @@ grid_clb_mux_1level_tapbuf_basis_input3_mem3_8 mux_l1_in_0_ ( .mem ( local_encoder2to3_0_data ) , .mem_inv ( local_encoder2to3_0_data_inv ) , .out ( mux_1level_tapbuf_basis_input3_mem3_0_out ) , .VDD ( VDD ) , - .VSS ( VSS ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_157 ( + .VSS ( VSS ) , .p6 ( p6 ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_156 ( .A ( mux_1level_tapbuf_basis_input3_mem3_0_out[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_158 ( +sky130_fd_sc_hd__inv_8 BINV_R_157 ( .A ( mux_1level_tapbuf_basis_input3_mem3_0_out[0] ) , .Y ( p_abuf0 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -95510,19 +98959,19 @@ endmodule module grid_clb_mux_1level_basis_input3_mem3_17 ( in , mem , mem_inv , out , - VDD , VSS , p0 ) ; + VDD , VSS , p6 ) ; input [0:2] in ; input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; input VDD ; input VSS ; -input p0 ; +input p6 ; supply1 VDD ; supply0 VSS ; -scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , +scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p6 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -95555,14 +99004,14 @@ endmodule module grid_clb_mux_1level_size2_17 ( in , sram , sram_inv , out , VDD , VSS , - p0 ) ; + p6 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; output [0:0] out ; input VDD ; input VSS ; -input p0 ; +input p6 ; wire [0:2] local_encoder2to3_0_data ; wire [0:2] local_encoder2to3_0_data_inv ; @@ -95581,24 +99030,24 @@ grid_clb_mux_1level_basis_input3_mem3_17 mux_l1_in_0_ ( .mem ( local_encoder2to3_0_data ) , .mem_inv ( local_encoder2to3_0_data_inv ) , .out ( mux_1level_basis_input3_mem3_0_out ) , .VDD ( VDD ) , - .VSS ( VSS ) , .p0 ( p0 ) ) ; + .VSS ( VSS ) , .p6 ( p6 ) ) ; endmodule module grid_clb_mux_1level_basis_input3_mem3_16 ( in , mem , mem_inv , out , - VDD , VSS , p0 ) ; + VDD , VSS , p6 ) ; input [0:2] in ; input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; input VDD ; input VSS ; -input p0 ; +input p6 ; supply1 VDD ; supply0 VSS ; -scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , +scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p6 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -95631,14 +99080,14 @@ endmodule module grid_clb_mux_1level_size2_16 ( in , sram , sram_inv , out , VDD , VSS , - p0 ) ; + p6 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; output [0:0] out ; input VDD ; input VSS ; -input p0 ; +input p6 ; wire [0:2] local_encoder2to3_0_data ; wire [0:2] local_encoder2to3_0_data_inv ; @@ -95657,7 +99106,7 @@ grid_clb_mux_1level_basis_input3_mem3_16 mux_l1_in_0_ ( .mem ( local_encoder2to3_0_data ) , .mem_inv ( local_encoder2to3_0_data_inv ) , .out ( mux_1level_basis_input3_mem3_0_out ) , .VDD ( VDD ) , - .VSS ( VSS ) , .p0 ( p0 ) ) ; + .VSS ( VSS ) , .p6 ( p6 ) ) ; endmodule @@ -95934,7 +99383,7 @@ endmodule module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_4 ( pReset , prog_clk , frac_logic_in , frac_logic_cin , ccff_head , - frac_logic_out , frac_logic_cout , ccff_tail , VDD , VSS , p0 ) ; + frac_logic_out , frac_logic_cout , ccff_tail , VDD , VSS , p6 ) ; input [0:0] pReset ; input [0:0] prog_clk ; input [0:3] frac_logic_in ; @@ -95945,7 +99394,7 @@ output [0:0] frac_logic_cout ; output [0:0] ccff_tail ; input VDD ; input VSS ; -input p0 ; +input p6 ; wire [0:0] direct_interc_5_out ; wire [0:0] direct_interc_7_out ; @@ -95985,13 +99434,13 @@ grid_clb_mux_1level_size2_16 mux_frac_logic_out_0 ( } ) , .sram ( mux_1level_size2_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_2 , SYNOPSYS_UNCONNECTED_3 } ) , - .out ( frac_logic_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) ) ; + .out ( frac_logic_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , .p6 ( p6 ) ) ; grid_clb_mux_1level_size2_17 mux_frac_lut4_0_in_2 ( .in ( { frac_logic_cin[0] , frac_logic_in[2] } ) , .sram ( mux_1level_size2_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_4 , SYNOPSYS_UNCONNECTED_5 } ) , .out ( mux_1level_size2_1_out ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( p0 ) ) ; + .p6 ( p6 ) ) ; grid_clb_mux_1level_size2_mem_16 mem_frac_logic_out_0 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ) , @@ -96008,7 +99457,7 @@ module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_4 ( pReset , prog_clk , Test_en , fabric_in , fabric_reg_in , fabric_sc_in , fabric_cin , fabric_reset , fabric_clk , ccff_head , fabric_out , fabric_reg_out , fabric_sc_out , fabric_cout , ccff_tail , VDD , VSS , - p_abuf0 , p_abuf1 , p0 ) ; + p_abuf0 , p_abuf1 , p6 ) ; input [0:0] pReset ; input [0:0] prog_clk ; input [0:0] Test_en ; @@ -96028,7 +99477,7 @@ input VDD ; input VSS ; output p_abuf0 ; output p_abuf1 ; -input p0 ; +input p6 ; wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ; wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ; @@ -96055,7 +99504,7 @@ grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ .frac_logic_cout ( { SYNOPSYS_UNCONNECTED_1 } ) , .ccff_tail ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) , - .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) ) ; + .VDD ( VDD ) , .VSS ( VSS ) , .p6 ( p6 ) ) ; grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_8 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0 ( .Test_en ( Test_en ) , .ff_D ( mux_1level_size2_0_out ) , .ff_DI ( fabric_sc_in ) , .ff_reset ( fabric_reset ) , @@ -96074,7 +99523,7 @@ grid_clb_mux_1level_tapbuf_size2_8 mux_fabric_out_0 ( .sram ( mux_1level_tapbuf_size2_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_2 , SYNOPSYS_UNCONNECTED_3 } ) , .out ( fabric_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p_abuf0 ( p_abuf0 ) , .p0 ( p0 ) ) ; + .p_abuf0 ( p_abuf0 ) , .p6 ( p6 ) ) ; grid_clb_mux_1level_tapbuf_size2_9 mux_fabric_out_1 ( .in ( { fabric_sc_out[0] , logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] @@ -96082,7 +99531,7 @@ grid_clb_mux_1level_tapbuf_size2_9 mux_fabric_out_1 ( .sram ( mux_1level_tapbuf_size2_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_4 , SYNOPSYS_UNCONNECTED_5 } ) , .out ( fabric_out[1] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p_abuf0 ( p_abuf1 ) , .p0 ( p0 ) ) ; + .p_abuf0 ( p_abuf1 ) , .p6 ( p6 ) ) ; grid_clb_mux_1level_tapbuf_size2_mem_8 mem_fabric_out_0 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) , @@ -96104,7 +99553,7 @@ grid_clb_mux_1level_size2_18 mux_ff_0_D_0 ( .sram ( mux_1level_size2_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_6 , SYNOPSYS_UNCONNECTED_7 } ) , .out ( mux_1level_size2_0_out ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( p0 ) ) ; + .p6 ( p6 ) ) ; grid_clb_mux_1level_size2_19 mux_ff_1_D_0 ( .in ( { logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] , @@ -96113,7 +99562,7 @@ grid_clb_mux_1level_size2_19 mux_ff_1_D_0 ( .sram ( mux_1level_size2_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_8 , SYNOPSYS_UNCONNECTED_9 } ) , .out ( mux_1level_size2_1_out ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( p0 ) ) ; + .p6 ( p6 ) ) ; grid_clb_mux_1level_size2_mem_18 mem_ff_0_D_0 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( mux_1level_tapbuf_size2_mem_1_ccff_tail ) , @@ -96129,7 +99578,7 @@ endmodule module grid_clb_logical_tile_clb_mode_default__fle_4 ( pReset , prog_clk , Test_en , fle_in , fle_reg_in , fle_sc_in , fle_cin , fle_reset , fle_clk , ccff_head , fle_out , fle_reg_out , fle_sc_out , fle_cout , - ccff_tail , VDD , VSS , p_abuf0 , p_abuf1 , p0 ) ; + ccff_tail , VDD , VSS , p_abuf0 , p_abuf1 , p6 ) ; input [0:0] pReset ; input [0:0] prog_clk ; input [0:0] Test_en ; @@ -96149,7 +99598,7 @@ input VDD ; input VSS ; output p_abuf0 ; output p_abuf1 ; -input p0 ; +input p6 ; supply1 VDD ; supply0 VSS ; @@ -96164,7 +99613,7 @@ grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_4 logical_tile .fabric_reg_out ( fle_reg_out ) , .fabric_sc_out ( fle_sc_out ) , .fabric_cout ( { SYNOPSYS_UNCONNECTED_2 } ) , .ccff_tail ( ccff_tail ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p_abuf0 ( p_abuf0 ) , .p_abuf1 ( p_abuf1 ) , .p0 ( p0 ) ) ; + .p_abuf0 ( p_abuf0 ) , .p_abuf1 ( p_abuf1 ) , .p6 ( p6 ) ) ; endmodule @@ -96217,19 +99666,19 @@ endmodule module grid_clb_mux_1level_basis_input3_mem3_15 ( in , mem , mem_inv , out , - VDD , VSS , p0 ) ; + VDD , VSS , p6 ) ; input [0:2] in ; input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; input VDD ; input VSS ; -input p0 ; +input p6 ; supply1 VDD ; supply0 VSS ; -scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , +scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p6 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -96262,14 +99711,14 @@ endmodule module grid_clb_mux_1level_size2_15 ( in , sram , sram_inv , out , VDD , VSS , - p0 ) ; + p6 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; output [0:0] out ; input VDD ; input VSS ; -input p0 ; +input p6 ; wire [0:2] local_encoder2to3_0_data ; wire [0:2] local_encoder2to3_0_data_inv ; @@ -96288,24 +99737,24 @@ grid_clb_mux_1level_basis_input3_mem3_15 mux_l1_in_0_ ( .mem ( local_encoder2to3_0_data ) , .mem_inv ( local_encoder2to3_0_data_inv ) , .out ( mux_1level_basis_input3_mem3_0_out ) , .VDD ( VDD ) , - .VSS ( VSS ) , .p0 ( p0 ) ) ; + .VSS ( VSS ) , .p6 ( p6 ) ) ; endmodule module grid_clb_mux_1level_basis_input3_mem3_14 ( in , mem , mem_inv , out , - VDD , VSS , p2 ) ; + VDD , VSS , p0 ) ; input [0:2] in ; input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; input VDD ; input VSS ; -input p2 ; +input p0 ; supply1 VDD ; supply0 VSS ; -scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p2 ) , +scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -96338,14 +99787,14 @@ endmodule module grid_clb_mux_1level_size2_14 ( in , sram , sram_inv , out , VDD , VSS , - p2 ) ; + p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; output [0:0] out ; input VDD ; input VSS ; -input p2 ; +input p0 ; wire [0:2] local_encoder2to3_0_data ; wire [0:2] local_encoder2to3_0_data_inv ; @@ -96364,7 +99813,7 @@ grid_clb_mux_1level_basis_input3_mem3_14 mux_l1_in_0_ ( .mem ( local_encoder2to3_0_data ) , .mem_inv ( local_encoder2to3_0_data_inv ) , .out ( mux_1level_basis_input3_mem3_0_out ) , .VDD ( VDD ) , - .VSS ( VSS ) , .p2 ( p2 ) ) ; + .VSS ( VSS ) , .p0 ( p0 ) ) ; endmodule @@ -96417,19 +99866,19 @@ endmodule module grid_clb_mux_1level_tapbuf_basis_input3_mem3_7 ( in , mem , mem_inv , - out , VDD , VSS , p0 ) ; + out , VDD , VSS , p6 ) ; input [0:2] in ; input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; input VDD ; input VSS ; -input p0 ; +input p6 ; supply1 VDD ; supply0 VSS ; -scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , +scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p6 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -96462,7 +99911,7 @@ endmodule module grid_clb_mux_1level_tapbuf_size2_7 ( in , sram , sram_inv , out , VDD , - VSS , p_abuf0 , p0 ) ; + VSS , p_abuf0 , p6 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -96470,7 +99919,7 @@ output [0:0] out ; input VDD ; input VSS ; output p_abuf0 ; -input p0 ; +input p6 ; wire [0:2] local_encoder2to3_0_data ; wire [0:2] local_encoder2to3_0_data_inv ; @@ -96486,30 +99935,30 @@ grid_clb_mux_1level_tapbuf_basis_input3_mem3_7 mux_l1_in_0_ ( .mem ( local_encoder2to3_0_data ) , .mem_inv ( local_encoder2to3_0_data_inv ) , .out ( mux_1level_tapbuf_basis_input3_mem3_0_out ) , .VDD ( VDD ) , - .VSS ( VSS ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_154 ( + .VSS ( VSS ) , .p6 ( p6 ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_153 ( .A ( mux_1level_tapbuf_basis_input3_mem3_0_out[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_155 ( +sky130_fd_sc_hd__inv_8 BINV_R_154 ( .A ( mux_1level_tapbuf_basis_input3_mem3_0_out[0] ) , .Y ( p_abuf0 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module grid_clb_mux_1level_tapbuf_basis_input3_mem3_6 ( in , mem , mem_inv , - out , VDD , VSS , p2 ) ; + out , VDD , VSS , p0 ) ; input [0:2] in ; input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; input VDD ; input VSS ; -input p2 ; +input p0 ; supply1 VDD ; supply0 VSS ; -scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p2 ) , +scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -96542,7 +99991,7 @@ endmodule module grid_clb_mux_1level_tapbuf_size2_6 ( in , sram , sram_inv , out , VDD , - VSS , p_abuf0 , p2 ) ; + VSS , p_abuf0 , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -96550,7 +99999,7 @@ output [0:0] out ; input VDD ; input VSS ; output p_abuf0 ; -input p2 ; +input p0 ; wire [0:2] local_encoder2to3_0_data ; wire [0:2] local_encoder2to3_0_data_inv ; @@ -96566,11 +100015,11 @@ grid_clb_mux_1level_tapbuf_basis_input3_mem3_6 mux_l1_in_0_ ( .mem ( local_encoder2to3_0_data ) , .mem_inv ( local_encoder2to3_0_data_inv ) , .out ( mux_1level_tapbuf_basis_input3_mem3_0_out ) , .VDD ( VDD ) , - .VSS ( VSS ) , .p2 ( p2 ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_151 ( + .VSS ( VSS ) , .p0 ( p0 ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_150 ( .A ( mux_1level_tapbuf_basis_input3_mem3_0_out[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_152 ( +sky130_fd_sc_hd__inv_8 BINV_R_151 ( .A ( mux_1level_tapbuf_basis_input3_mem3_0_out[0] ) , .Y ( p_abuf0 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -96667,19 +100116,19 @@ endmodule module grid_clb_mux_1level_basis_input3_mem3_13 ( in , mem , mem_inv , out , - VDD , VSS , p2 ) ; + VDD , VSS , p0 ) ; input [0:2] in ; input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; input VDD ; input VSS ; -input p2 ; +input p0 ; supply1 VDD ; supply0 VSS ; -scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p2 ) , +scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -96712,14 +100161,14 @@ endmodule module grid_clb_mux_1level_size2_13 ( in , sram , sram_inv , out , VDD , VSS , - p2 ) ; + p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; output [0:0] out ; input VDD ; input VSS ; -input p2 ; +input p0 ; wire [0:2] local_encoder2to3_0_data ; wire [0:2] local_encoder2to3_0_data_inv ; @@ -96738,24 +100187,24 @@ grid_clb_mux_1level_basis_input3_mem3_13 mux_l1_in_0_ ( .mem ( local_encoder2to3_0_data ) , .mem_inv ( local_encoder2to3_0_data_inv ) , .out ( mux_1level_basis_input3_mem3_0_out ) , .VDD ( VDD ) , - .VSS ( VSS ) , .p2 ( p2 ) ) ; + .VSS ( VSS ) , .p0 ( p0 ) ) ; endmodule module grid_clb_mux_1level_basis_input3_mem3_12 ( in , mem , mem_inv , out , - VDD , VSS , p2 ) ; + VDD , VSS , p0 ) ; input [0:2] in ; input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; input VDD ; input VSS ; -input p2 ; +input p0 ; supply1 VDD ; supply0 VSS ; -scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p2 ) , +scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -96788,14 +100237,14 @@ endmodule module grid_clb_mux_1level_size2_12 ( in , sram , sram_inv , out , VDD , VSS , - p2 ) ; + p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; output [0:0] out ; input VDD ; input VSS ; -input p2 ; +input p0 ; wire [0:2] local_encoder2to3_0_data ; wire [0:2] local_encoder2to3_0_data_inv ; @@ -96814,7 +100263,7 @@ grid_clb_mux_1level_basis_input3_mem3_12 mux_l1_in_0_ ( .mem ( local_encoder2to3_0_data ) , .mem_inv ( local_encoder2to3_0_data_inv ) , .out ( mux_1level_basis_input3_mem3_0_out ) , .VDD ( VDD ) , - .VSS ( VSS ) , .p2 ( p2 ) ) ; + .VSS ( VSS ) , .p0 ( p0 ) ) ; endmodule @@ -97091,7 +100540,7 @@ endmodule module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_3 ( pReset , prog_clk , frac_logic_in , frac_logic_cin , ccff_head , - frac_logic_out , frac_logic_cout , ccff_tail , VDD , VSS , p2 ) ; + frac_logic_out , frac_logic_cout , ccff_tail , VDD , VSS , p0 ) ; input [0:0] pReset ; input [0:0] prog_clk ; input [0:3] frac_logic_in ; @@ -97102,7 +100551,7 @@ output [0:0] frac_logic_cout ; output [0:0] ccff_tail ; input VDD ; input VSS ; -input p2 ; +input p0 ; wire [0:0] direct_interc_5_out ; wire [0:0] direct_interc_7_out ; @@ -97142,13 +100591,13 @@ grid_clb_mux_1level_size2_12 mux_frac_logic_out_0 ( } ) , .sram ( mux_1level_size2_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_2 , SYNOPSYS_UNCONNECTED_3 } ) , - .out ( frac_logic_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , .p2 ( p2 ) ) ; + .out ( frac_logic_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) ) ; grid_clb_mux_1level_size2_13 mux_frac_lut4_0_in_2 ( .in ( { frac_logic_cin[0] , frac_logic_in[2] } ) , .sram ( mux_1level_size2_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_4 , SYNOPSYS_UNCONNECTED_5 } ) , .out ( mux_1level_size2_1_out ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p2 ( p2 ) ) ; + .p0 ( p0 ) ) ; grid_clb_mux_1level_size2_mem_12 mem_frac_logic_out_0 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ) , @@ -97165,7 +100614,7 @@ module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_3 ( pReset , prog_clk , Test_en , fabric_in , fabric_reg_in , fabric_sc_in , fabric_cin , fabric_reset , fabric_clk , ccff_head , fabric_out , fabric_reg_out , fabric_sc_out , fabric_cout , ccff_tail , VDD , VSS , - p_abuf0 , p_abuf1 , p0 , p2 ) ; + p_abuf0 , p_abuf1 , p0 , p6 ) ; input [0:0] pReset ; input [0:0] prog_clk ; input [0:0] Test_en ; @@ -97186,7 +100635,7 @@ input VSS ; output p_abuf0 ; output p_abuf1 ; input p0 ; -input p2 ; +input p6 ; wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ; wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ; @@ -97213,7 +100662,7 @@ grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ .frac_logic_cout ( { SYNOPSYS_UNCONNECTED_1 } ) , .ccff_tail ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) , - .VDD ( VDD ) , .VSS ( VSS ) , .p2 ( p2 ) ) ; + .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) ) ; grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_6 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0 ( .Test_en ( Test_en ) , .ff_D ( mux_1level_size2_0_out ) , .ff_DI ( fabric_sc_in ) , .ff_reset ( fabric_reset ) , @@ -97232,7 +100681,7 @@ grid_clb_mux_1level_tapbuf_size2_6 mux_fabric_out_0 ( .sram ( mux_1level_tapbuf_size2_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_2 , SYNOPSYS_UNCONNECTED_3 } ) , .out ( fabric_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p_abuf0 ( p_abuf0 ) , .p2 ( p2 ) ) ; + .p_abuf0 ( p_abuf0 ) , .p0 ( p0 ) ) ; grid_clb_mux_1level_tapbuf_size2_7 mux_fabric_out_1 ( .in ( { fabric_sc_out[0] , logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] @@ -97240,7 +100689,7 @@ grid_clb_mux_1level_tapbuf_size2_7 mux_fabric_out_1 ( .sram ( mux_1level_tapbuf_size2_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_4 , SYNOPSYS_UNCONNECTED_5 } ) , .out ( fabric_out[1] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p_abuf0 ( p_abuf1 ) , .p0 ( p0 ) ) ; + .p_abuf0 ( p_abuf1 ) , .p6 ( p6 ) ) ; grid_clb_mux_1level_tapbuf_size2_mem_6 mem_fabric_out_0 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) , @@ -97262,7 +100711,7 @@ grid_clb_mux_1level_size2_14 mux_ff_0_D_0 ( .sram ( mux_1level_size2_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_6 , SYNOPSYS_UNCONNECTED_7 } ) , .out ( mux_1level_size2_0_out ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p2 ( p2 ) ) ; + .p0 ( p0 ) ) ; grid_clb_mux_1level_size2_15 mux_ff_1_D_0 ( .in ( { logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] , @@ -97271,7 +100720,7 @@ grid_clb_mux_1level_size2_15 mux_ff_1_D_0 ( .sram ( mux_1level_size2_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_8 , SYNOPSYS_UNCONNECTED_9 } ) , .out ( mux_1level_size2_1_out ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( p0 ) ) ; + .p6 ( p6 ) ) ; grid_clb_mux_1level_size2_mem_14 mem_ff_0_D_0 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( mux_1level_tapbuf_size2_mem_1_ccff_tail ) , @@ -97287,7 +100736,7 @@ endmodule module grid_clb_logical_tile_clb_mode_default__fle_3 ( pReset , prog_clk , Test_en , fle_in , fle_reg_in , fle_sc_in , fle_cin , fle_reset , fle_clk , ccff_head , fle_out , fle_reg_out , fle_sc_out , fle_cout , - ccff_tail , VDD , VSS , p_abuf0 , p_abuf1 , p0 , p2 ) ; + ccff_tail , VDD , VSS , p_abuf0 , p_abuf1 , p0 , p6 ) ; input [0:0] pReset ; input [0:0] prog_clk ; input [0:0] Test_en ; @@ -97308,7 +100757,7 @@ input VSS ; output p_abuf0 ; output p_abuf1 ; input p0 ; -input p2 ; +input p6 ; supply1 VDD ; supply0 VSS ; @@ -97323,7 +100772,7 @@ grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_3 logical_tile .fabric_reg_out ( fle_reg_out ) , .fabric_sc_out ( fle_sc_out ) , .fabric_cout ( { SYNOPSYS_UNCONNECTED_2 } ) , .ccff_tail ( ccff_tail ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p_abuf0 ( p_abuf0 ) , .p_abuf1 ( p_abuf1 ) , .p0 ( p0 ) , .p2 ( p2 ) ) ; + .p_abuf0 ( p_abuf0 ) , .p_abuf1 ( p_abuf1 ) , .p0 ( p0 ) , .p6 ( p6 ) ) ; endmodule @@ -97376,19 +100825,19 @@ endmodule module grid_clb_mux_1level_basis_input3_mem3_11 ( in , mem , mem_inv , out , - VDD , VSS , p2 ) ; + VDD , VSS , p4 ) ; input [0:2] in ; input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; input VDD ; input VSS ; -input p2 ; +input p4 ; supply1 VDD ; supply0 VSS ; -scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p2 ) , +scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p4 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -97421,14 +100870,14 @@ endmodule module grid_clb_mux_1level_size2_11 ( in , sram , sram_inv , out , VDD , VSS , - p2 ) ; + p4 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; output [0:0] out ; input VDD ; input VSS ; -input p2 ; +input p4 ; wire [0:2] local_encoder2to3_0_data ; wire [0:2] local_encoder2to3_0_data_inv ; @@ -97447,24 +100896,24 @@ grid_clb_mux_1level_basis_input3_mem3_11 mux_l1_in_0_ ( .mem ( local_encoder2to3_0_data ) , .mem_inv ( local_encoder2to3_0_data_inv ) , .out ( mux_1level_basis_input3_mem3_0_out ) , .VDD ( VDD ) , - .VSS ( VSS ) , .p2 ( p2 ) ) ; + .VSS ( VSS ) , .p4 ( p4 ) ) ; endmodule module grid_clb_mux_1level_basis_input3_mem3_10 ( in , mem , mem_inv , out , - VDD , VSS , p1 ) ; + VDD , VSS , p4 ) ; input [0:2] in ; input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; input VDD ; input VSS ; -input p1 ; +input p4 ; supply1 VDD ; supply0 VSS ; -scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p1 ) , +scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p4 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -97497,14 +100946,14 @@ endmodule module grid_clb_mux_1level_size2_10 ( in , sram , sram_inv , out , VDD , VSS , - p1 ) ; + p4 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; output [0:0] out ; input VDD ; input VSS ; -input p1 ; +input p4 ; wire [0:2] local_encoder2to3_0_data ; wire [0:2] local_encoder2to3_0_data_inv ; @@ -97523,7 +100972,7 @@ grid_clb_mux_1level_basis_input3_mem3_10 mux_l1_in_0_ ( .mem ( local_encoder2to3_0_data ) , .mem_inv ( local_encoder2to3_0_data_inv ) , .out ( mux_1level_basis_input3_mem3_0_out ) , .VDD ( VDD ) , - .VSS ( VSS ) , .p1 ( p1 ) ) ; + .VSS ( VSS ) , .p4 ( p4 ) ) ; endmodule @@ -97576,19 +101025,19 @@ endmodule module grid_clb_mux_1level_tapbuf_basis_input3_mem3_5 ( in , mem , mem_inv , - out , VDD , VSS , p2 ) ; + out , VDD , VSS , p4 ) ; input [0:2] in ; input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; input VDD ; input VSS ; -input p2 ; +input p4 ; supply1 VDD ; supply0 VSS ; -scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p2 ) , +scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p4 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -97621,7 +101070,7 @@ endmodule module grid_clb_mux_1level_tapbuf_size2_5 ( in , sram , sram_inv , out , VDD , - VSS , p_abuf0 , p2 ) ; + VSS , p_abuf0 , p4 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -97629,7 +101078,7 @@ output [0:0] out ; input VDD ; input VSS ; output p_abuf0 ; -input p2 ; +input p4 ; wire [0:2] local_encoder2to3_0_data ; wire [0:2] local_encoder2to3_0_data_inv ; @@ -97645,30 +101094,30 @@ grid_clb_mux_1level_tapbuf_basis_input3_mem3_5 mux_l1_in_0_ ( .mem ( local_encoder2to3_0_data ) , .mem_inv ( local_encoder2to3_0_data_inv ) , .out ( mux_1level_tapbuf_basis_input3_mem3_0_out ) , .VDD ( VDD ) , - .VSS ( VSS ) , .p2 ( p2 ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_148 ( + .VSS ( VSS ) , .p4 ( p4 ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_147 ( .A ( mux_1level_tapbuf_basis_input3_mem3_0_out[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_149 ( +sky130_fd_sc_hd__inv_8 BINV_R_148 ( .A ( mux_1level_tapbuf_basis_input3_mem3_0_out[0] ) , .Y ( p_abuf0 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module grid_clb_mux_1level_tapbuf_basis_input3_mem3_4 ( in , mem , mem_inv , - out , VDD , VSS , p1 ) ; + out , VDD , VSS , p4 ) ; input [0:2] in ; input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; input VDD ; input VSS ; -input p1 ; +input p4 ; supply1 VDD ; supply0 VSS ; -scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p1 ) , +scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p4 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -97701,7 +101150,7 @@ endmodule module grid_clb_mux_1level_tapbuf_size2_4 ( in , sram , sram_inv , out , VDD , - VSS , p_abuf0 , p1 ) ; + VSS , p_abuf0 , p4 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -97709,7 +101158,7 @@ output [0:0] out ; input VDD ; input VSS ; output p_abuf0 ; -input p1 ; +input p4 ; wire [0:2] local_encoder2to3_0_data ; wire [0:2] local_encoder2to3_0_data_inv ; @@ -97725,11 +101174,11 @@ grid_clb_mux_1level_tapbuf_basis_input3_mem3_4 mux_l1_in_0_ ( .mem ( local_encoder2to3_0_data ) , .mem_inv ( local_encoder2to3_0_data_inv ) , .out ( mux_1level_tapbuf_basis_input3_mem3_0_out ) , .VDD ( VDD ) , - .VSS ( VSS ) , .p1 ( p1 ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_145 ( + .VSS ( VSS ) , .p4 ( p4 ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_144 ( .A ( mux_1level_tapbuf_basis_input3_mem3_0_out[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_146 ( +sky130_fd_sc_hd__inv_8 BINV_R_145 ( .A ( mux_1level_tapbuf_basis_input3_mem3_0_out[0] ) , .Y ( p_abuf0 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -97826,19 +101275,19 @@ endmodule module grid_clb_mux_1level_basis_input3_mem3_9 ( in , mem , mem_inv , out , - VDD , VSS , p1 ) ; + VDD , VSS , p2 ) ; input [0:2] in ; input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; input VDD ; input VSS ; -input p1 ; +input p2 ; supply1 VDD ; supply0 VSS ; -scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p1 ) , +scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p2 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -97871,14 +101320,14 @@ endmodule module grid_clb_mux_1level_size2_9 ( in , sram , sram_inv , out , VDD , VSS , - p1 ) ; + p2 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; output [0:0] out ; input VDD ; input VSS ; -input p1 ; +input p2 ; wire [0:2] local_encoder2to3_0_data ; wire [0:2] local_encoder2to3_0_data_inv ; @@ -97897,7 +101346,7 @@ grid_clb_mux_1level_basis_input3_mem3_9 mux_l1_in_0_ ( .mem ( local_encoder2to3_0_data ) , .mem_inv ( local_encoder2to3_0_data_inv ) , .out ( mux_1level_basis_input3_mem3_0_out ) , .VDD ( VDD ) , - .VSS ( VSS ) , .p1 ( p1 ) ) ; + .VSS ( VSS ) , .p2 ( p2 ) ) ; endmodule @@ -98250,7 +101699,7 @@ endmodule module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_2 ( pReset , prog_clk , frac_logic_in , frac_logic_cin , ccff_head , - frac_logic_out , frac_logic_cout , ccff_tail , VDD , VSS , p1 , p2 ) ; + frac_logic_out , frac_logic_cout , ccff_tail , VDD , VSS , p2 ) ; input [0:0] pReset ; input [0:0] prog_clk ; input [0:3] frac_logic_in ; @@ -98261,7 +101710,6 @@ output [0:0] frac_logic_cout ; output [0:0] ccff_tail ; input VDD ; input VSS ; -input p1 ; input p2 ; wire [0:0] direct_interc_5_out ; @@ -98308,7 +101756,7 @@ grid_clb_mux_1level_size2_9 mux_frac_lut4_0_in_2 ( .sram ( mux_1level_size2_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_4 , SYNOPSYS_UNCONNECTED_5 } ) , .out ( mux_1level_size2_1_out ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p1 ( p1 ) ) ; + .p2 ( p2 ) ) ; grid_clb_mux_1level_size2_mem_8 mem_frac_logic_out_0 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ) , @@ -98325,7 +101773,7 @@ module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_2 ( pReset , prog_clk , Test_en , fabric_in , fabric_reg_in , fabric_sc_in , fabric_cin , fabric_reset , fabric_clk , ccff_head , fabric_out , fabric_reg_out , fabric_sc_out , fabric_cout , ccff_tail , VDD , VSS , - p_abuf0 , p_abuf1 , p1 , p2 ) ; + p_abuf0 , p_abuf1 , p2 , p4 ) ; input [0:0] pReset ; input [0:0] prog_clk ; input [0:0] Test_en ; @@ -98345,8 +101793,8 @@ input VDD ; input VSS ; output p_abuf0 ; output p_abuf1 ; -input p1 ; input p2 ; +input p4 ; wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ; wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ; @@ -98373,7 +101821,7 @@ grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ .frac_logic_cout ( { SYNOPSYS_UNCONNECTED_1 } ) , .ccff_tail ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) , - .VDD ( VDD ) , .VSS ( VSS ) , .p1 ( p1 ) , .p2 ( p2 ) ) ; + .VDD ( VDD ) , .VSS ( VSS ) , .p2 ( p2 ) ) ; grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_4 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0 ( .Test_en ( Test_en ) , .ff_D ( mux_1level_size2_0_out ) , .ff_DI ( fabric_sc_in ) , .ff_reset ( fabric_reset ) , @@ -98392,7 +101840,7 @@ grid_clb_mux_1level_tapbuf_size2_4 mux_fabric_out_0 ( .sram ( mux_1level_tapbuf_size2_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_2 , SYNOPSYS_UNCONNECTED_3 } ) , .out ( fabric_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p_abuf0 ( p_abuf0 ) , .p1 ( p1 ) ) ; + .p_abuf0 ( p_abuf0 ) , .p4 ( p4 ) ) ; grid_clb_mux_1level_tapbuf_size2_5 mux_fabric_out_1 ( .in ( { fabric_sc_out[0] , logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] @@ -98400,7 +101848,7 @@ grid_clb_mux_1level_tapbuf_size2_5 mux_fabric_out_1 ( .sram ( mux_1level_tapbuf_size2_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_4 , SYNOPSYS_UNCONNECTED_5 } ) , .out ( fabric_out[1] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p_abuf0 ( p_abuf1 ) , .p2 ( p2 ) ) ; + .p_abuf0 ( p_abuf1 ) , .p4 ( p4 ) ) ; grid_clb_mux_1level_tapbuf_size2_mem_4 mem_fabric_out_0 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) , @@ -98422,7 +101870,7 @@ grid_clb_mux_1level_size2_10 mux_ff_0_D_0 ( .sram ( mux_1level_size2_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_6 , SYNOPSYS_UNCONNECTED_7 } ) , .out ( mux_1level_size2_0_out ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p1 ( p1 ) ) ; + .p4 ( p4 ) ) ; grid_clb_mux_1level_size2_11 mux_ff_1_D_0 ( .in ( { logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] , @@ -98431,7 +101879,7 @@ grid_clb_mux_1level_size2_11 mux_ff_1_D_0 ( .sram ( mux_1level_size2_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_8 , SYNOPSYS_UNCONNECTED_9 } ) , .out ( mux_1level_size2_1_out ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p2 ( p2 ) ) ; + .p4 ( p4 ) ) ; grid_clb_mux_1level_size2_mem_10 mem_ff_0_D_0 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( mux_1level_tapbuf_size2_mem_1_ccff_tail ) , @@ -98447,7 +101895,7 @@ endmodule module grid_clb_logical_tile_clb_mode_default__fle_2 ( pReset , prog_clk , Test_en , fle_in , fle_reg_in , fle_sc_in , fle_cin , fle_reset , fle_clk , ccff_head , fle_out , fle_reg_out , fle_sc_out , fle_cout , - ccff_tail , VDD , VSS , p_abuf0 , p_abuf1 , p1 , p2 ) ; + ccff_tail , VDD , VSS , p_abuf0 , p_abuf1 , p2 , p4 ) ; input [0:0] pReset ; input [0:0] prog_clk ; input [0:0] Test_en ; @@ -98467,8 +101915,8 @@ input VDD ; input VSS ; output p_abuf0 ; output p_abuf1 ; -input p1 ; input p2 ; +input p4 ; supply1 VDD ; supply0 VSS ; @@ -98483,7 +101931,7 @@ grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_2 logical_tile .fabric_reg_out ( fle_reg_out ) , .fabric_sc_out ( fle_sc_out ) , .fabric_cout ( { SYNOPSYS_UNCONNECTED_2 } ) , .ccff_tail ( ccff_tail ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p_abuf0 ( p_abuf0 ) , .p_abuf1 ( p_abuf1 ) , .p1 ( p1 ) , .p2 ( p2 ) ) ; + .p_abuf0 ( p_abuf0 ) , .p_abuf1 ( p_abuf1 ) , .p2 ( p2 ) , .p4 ( p4 ) ) ; endmodule @@ -98536,19 +101984,19 @@ endmodule module grid_clb_mux_1level_basis_input3_mem3_7 ( in , mem , mem_inv , out , - VDD , VSS , p0 ) ; + VDD , VSS , p5 ) ; input [0:2] in ; input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; input VDD ; input VSS ; -input p0 ; +input p5 ; supply1 VDD ; supply0 VSS ; -scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , +scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p5 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -98581,14 +102029,14 @@ endmodule module grid_clb_mux_1level_size2_7 ( in , sram , sram_inv , out , VDD , VSS , - p0 ) ; + p5 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; output [0:0] out ; input VDD ; input VSS ; -input p0 ; +input p5 ; wire [0:2] local_encoder2to3_0_data ; wire [0:2] local_encoder2to3_0_data_inv ; @@ -98607,24 +102055,24 @@ grid_clb_mux_1level_basis_input3_mem3_7 mux_l1_in_0_ ( .mem ( local_encoder2to3_0_data ) , .mem_inv ( local_encoder2to3_0_data_inv ) , .out ( mux_1level_basis_input3_mem3_0_out ) , .VDD ( VDD ) , - .VSS ( VSS ) , .p0 ( p0 ) ) ; + .VSS ( VSS ) , .p5 ( p5 ) ) ; endmodule module grid_clb_mux_1level_basis_input3_mem3_6 ( in , mem , mem_inv , out , - VDD , VSS , p0 ) ; + VDD , VSS , p5 ) ; input [0:2] in ; input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; input VDD ; input VSS ; -input p0 ; +input p5 ; supply1 VDD ; supply0 VSS ; -scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , +scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p5 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -98657,14 +102105,14 @@ endmodule module grid_clb_mux_1level_size2_6 ( in , sram , sram_inv , out , VDD , VSS , - p0 ) ; + p5 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; output [0:0] out ; input VDD ; input VSS ; -input p0 ; +input p5 ; wire [0:2] local_encoder2to3_0_data ; wire [0:2] local_encoder2to3_0_data_inv ; @@ -98683,7 +102131,7 @@ grid_clb_mux_1level_basis_input3_mem3_6 mux_l1_in_0_ ( .mem ( local_encoder2to3_0_data ) , .mem_inv ( local_encoder2to3_0_data_inv ) , .out ( mux_1level_basis_input3_mem3_0_out ) , .VDD ( VDD ) , - .VSS ( VSS ) , .p0 ( p0 ) ) ; + .VSS ( VSS ) , .p5 ( p5 ) ) ; endmodule @@ -98736,19 +102184,19 @@ endmodule module grid_clb_mux_1level_tapbuf_basis_input3_mem3_3 ( in , mem , mem_inv , - out , VDD , VSS , p0 ) ; + out , VDD , VSS , p5 ) ; input [0:2] in ; input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; input VDD ; input VSS ; -input p0 ; +input p5 ; supply1 VDD ; supply0 VSS ; -scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , +scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p5 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -98781,7 +102229,7 @@ endmodule module grid_clb_mux_1level_tapbuf_size2_3 ( in , sram , sram_inv , out , VDD , - VSS , p_abuf0 , p0 ) ; + VSS , p_abuf0 , p5 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -98789,7 +102237,7 @@ output [0:0] out ; input VDD ; input VSS ; output p_abuf0 ; -input p0 ; +input p5 ; wire [0:2] local_encoder2to3_0_data ; wire [0:2] local_encoder2to3_0_data_inv ; @@ -98805,11 +102253,11 @@ grid_clb_mux_1level_tapbuf_basis_input3_mem3_3 mux_l1_in_0_ ( .mem ( local_encoder2to3_0_data ) , .mem_inv ( local_encoder2to3_0_data_inv ) , .out ( mux_1level_tapbuf_basis_input3_mem3_0_out ) , .VDD ( VDD ) , - .VSS ( VSS ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_142 ( + .VSS ( VSS ) , .p5 ( p5 ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_141 ( .A ( mux_1level_tapbuf_basis_input3_mem3_0_out[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_143 ( +sky130_fd_sc_hd__inv_8 BINV_R_142 ( .A ( mux_1level_tapbuf_basis_input3_mem3_0_out[0] ) , .Y ( p_abuf0 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -98886,10 +102334,10 @@ grid_clb_mux_1level_tapbuf_basis_input3_mem3_2 mux_l1_in_0_ ( .mem_inv ( local_encoder2to3_0_data_inv ) , .out ( mux_1level_tapbuf_basis_input3_mem3_0_out ) , .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_139 ( +sky130_fd_sc_hd__inv_1 BINV_R_138 ( .A ( mux_1level_tapbuf_basis_input3_mem3_0_out[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_140 ( +sky130_fd_sc_hd__inv_8 BINV_R_139 ( .A ( mux_1level_tapbuf_basis_input3_mem3_0_out[0] ) , .Y ( p_abuf0 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -98986,19 +102434,19 @@ endmodule module grid_clb_mux_1level_basis_input3_mem3_5 ( in , mem , mem_inv , out , - VDD , VSS , p5 ) ; + VDD , VSS , p1 ) ; input [0:2] in ; input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; input VDD ; input VSS ; -input p5 ; +input p1 ; supply1 VDD ; supply0 VSS ; -scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p5 ) , +scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p1 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -99031,14 +102479,14 @@ endmodule module grid_clb_mux_1level_size2_5 ( in , sram , sram_inv , out , VDD , VSS , - p5 ) ; + p1 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; output [0:0] out ; input VDD ; input VSS ; -input p5 ; +input p1 ; wire [0:2] local_encoder2to3_0_data ; wire [0:2] local_encoder2to3_0_data_inv ; @@ -99057,24 +102505,24 @@ grid_clb_mux_1level_basis_input3_mem3_5 mux_l1_in_0_ ( .mem ( local_encoder2to3_0_data ) , .mem_inv ( local_encoder2to3_0_data_inv ) , .out ( mux_1level_basis_input3_mem3_0_out ) , .VDD ( VDD ) , - .VSS ( VSS ) , .p5 ( p5 ) ) ; + .VSS ( VSS ) , .p1 ( p1 ) ) ; endmodule module grid_clb_mux_1level_basis_input3_mem3_4 ( in , mem , mem_inv , out , - VDD , VSS , p5 ) ; + VDD , VSS , p0 ) ; input [0:2] in ; input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; input VDD ; input VSS ; -input p5 ; +input p0 ; supply1 VDD ; supply0 VSS ; -scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p5 ) , +scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -99107,14 +102555,14 @@ endmodule module grid_clb_mux_1level_size2_4 ( in , sram , sram_inv , out , VDD , VSS , - p5 ) ; + p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; output [0:0] out ; input VDD ; input VSS ; -input p5 ; +input p0 ; wire [0:2] local_encoder2to3_0_data ; wire [0:2] local_encoder2to3_0_data_inv ; @@ -99133,7 +102581,7 @@ grid_clb_mux_1level_basis_input3_mem3_4 mux_l1_in_0_ ( .mem ( local_encoder2to3_0_data ) , .mem_inv ( local_encoder2to3_0_data_inv ) , .out ( mux_1level_basis_input3_mem3_0_out ) , .VDD ( VDD ) , - .VSS ( VSS ) , .p5 ( p5 ) ) ; + .VSS ( VSS ) , .p0 ( p0 ) ) ; endmodule @@ -99410,7 +102858,7 @@ endmodule module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_1 ( pReset , prog_clk , frac_logic_in , frac_logic_cin , ccff_head , - frac_logic_out , frac_logic_cout , ccff_tail , VDD , VSS , p5 ) ; + frac_logic_out , frac_logic_cout , ccff_tail , VDD , VSS , p0 , p1 ) ; input [0:0] pReset ; input [0:0] prog_clk ; input [0:3] frac_logic_in ; @@ -99421,7 +102869,8 @@ output [0:0] frac_logic_cout ; output [0:0] ccff_tail ; input VDD ; input VSS ; -input p5 ; +input p0 ; +input p1 ; wire [0:0] direct_interc_5_out ; wire [0:0] direct_interc_7_out ; @@ -99461,13 +102910,13 @@ grid_clb_mux_1level_size2_4 mux_frac_logic_out_0 ( } ) , .sram ( mux_1level_size2_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_2 , SYNOPSYS_UNCONNECTED_3 } ) , - .out ( frac_logic_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , .p5 ( p5 ) ) ; + .out ( frac_logic_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) ) ; grid_clb_mux_1level_size2_5 mux_frac_lut4_0_in_2 ( .in ( { frac_logic_cin[0] , frac_logic_in[2] } ) , .sram ( mux_1level_size2_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_4 , SYNOPSYS_UNCONNECTED_5 } ) , .out ( mux_1level_size2_1_out ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p5 ( p5 ) ) ; + .p1 ( p1 ) ) ; grid_clb_mux_1level_size2_mem_4 mem_frac_logic_out_0 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ) , @@ -99484,7 +102933,7 @@ module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_1 ( pReset , prog_clk , Test_en , fabric_in , fabric_reg_in , fabric_sc_in , fabric_cin , fabric_reset , fabric_clk , ccff_head , fabric_out , fabric_reg_out , fabric_sc_out , fabric_cout , ccff_tail , VDD , VSS , - p_abuf0 , p_abuf1 , p0 , p5 ) ; + p_abuf0 , p_abuf1 , p0 , p1 , p5 ) ; input [0:0] pReset ; input [0:0] prog_clk ; input [0:0] Test_en ; @@ -99505,6 +102954,7 @@ input VSS ; output p_abuf0 ; output p_abuf1 ; input p0 ; +input p1 ; input p5 ; wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ; @@ -99532,7 +102982,7 @@ grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ .frac_logic_cout ( { SYNOPSYS_UNCONNECTED_1 } ) , .ccff_tail ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) , - .VDD ( VDD ) , .VSS ( VSS ) , .p5 ( p5 ) ) ; + .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) , .p1 ( p1 ) ) ; grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_2 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0 ( .Test_en ( Test_en ) , .ff_D ( mux_1level_size2_0_out ) , .ff_DI ( fabric_sc_in ) , .ff_reset ( fabric_reset ) , @@ -99559,7 +103009,7 @@ grid_clb_mux_1level_tapbuf_size2_3 mux_fabric_out_1 ( .sram ( mux_1level_tapbuf_size2_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_4 , SYNOPSYS_UNCONNECTED_5 } ) , .out ( fabric_out[1] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p_abuf0 ( p_abuf1 ) , .p0 ( p0 ) ) ; + .p_abuf0 ( p_abuf1 ) , .p5 ( p5 ) ) ; grid_clb_mux_1level_tapbuf_size2_mem_2 mem_fabric_out_0 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) , @@ -99581,7 +103031,7 @@ grid_clb_mux_1level_size2_6 mux_ff_0_D_0 ( .sram ( mux_1level_size2_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_6 , SYNOPSYS_UNCONNECTED_7 } ) , .out ( mux_1level_size2_0_out ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( p0 ) ) ; + .p5 ( p5 ) ) ; grid_clb_mux_1level_size2_7 mux_ff_1_D_0 ( .in ( { logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] , @@ -99590,7 +103040,7 @@ grid_clb_mux_1level_size2_7 mux_ff_1_D_0 ( .sram ( mux_1level_size2_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_8 , SYNOPSYS_UNCONNECTED_9 } ) , .out ( mux_1level_size2_1_out ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( p0 ) ) ; + .p5 ( p5 ) ) ; grid_clb_mux_1level_size2_mem_6 mem_ff_0_D_0 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( mux_1level_tapbuf_size2_mem_1_ccff_tail ) , @@ -99606,7 +103056,7 @@ endmodule module grid_clb_logical_tile_clb_mode_default__fle_1 ( pReset , prog_clk , Test_en , fle_in , fle_reg_in , fle_sc_in , fle_cin , fle_reset , fle_clk , ccff_head , fle_out , fle_reg_out , fle_sc_out , fle_cout , - ccff_tail , VDD , VSS , p_abuf0 , p_abuf1 , p0 , p5 ) ; + ccff_tail , VDD , VSS , p_abuf0 , p_abuf1 , p0 , p1 , p5 ) ; input [0:0] pReset ; input [0:0] prog_clk ; input [0:0] Test_en ; @@ -99627,6 +103077,7 @@ input VSS ; output p_abuf0 ; output p_abuf1 ; input p0 ; +input p1 ; input p5 ; supply1 VDD ; @@ -99642,7 +103093,8 @@ grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_1 logical_tile .fabric_reg_out ( fle_reg_out ) , .fabric_sc_out ( fle_sc_out ) , .fabric_cout ( { SYNOPSYS_UNCONNECTED_2 } ) , .ccff_tail ( ccff_tail ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p_abuf0 ( p_abuf0 ) , .p_abuf1 ( p_abuf1 ) , .p0 ( p0 ) , .p5 ( p5 ) ) ; + .p_abuf0 ( p_abuf0 ) , .p_abuf1 ( p_abuf1 ) , .p0 ( p0 ) , .p1 ( p1 ) , + .p5 ( p5 ) ) ; endmodule @@ -99695,19 +103147,19 @@ endmodule module grid_clb_mux_1level_basis_input3_mem3_3 ( in , mem , mem_inv , out , - VDD , VSS , p1 ) ; + VDD , VSS , p5 ) ; input [0:2] in ; input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; input VDD ; input VSS ; -input p1 ; +input p5 ; supply1 VDD ; supply0 VSS ; -scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p1 ) , +scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p5 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -99740,14 +103192,14 @@ endmodule module grid_clb_mux_1level_size2_3 ( in , sram , sram_inv , out , VDD , VSS , - p1 ) ; + p5 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; output [0:0] out ; input VDD ; input VSS ; -input p1 ; +input p5 ; wire [0:2] local_encoder2to3_0_data ; wire [0:2] local_encoder2to3_0_data_inv ; @@ -99766,24 +103218,24 @@ grid_clb_mux_1level_basis_input3_mem3_3 mux_l1_in_0_ ( .mem ( local_encoder2to3_0_data ) , .mem_inv ( local_encoder2to3_0_data_inv ) , .out ( mux_1level_basis_input3_mem3_0_out ) , .VDD ( VDD ) , - .VSS ( VSS ) , .p1 ( p1 ) ) ; + .VSS ( VSS ) , .p5 ( p5 ) ) ; endmodule module grid_clb_mux_1level_basis_input3_mem3_2 ( in , mem , mem_inv , out , - VDD , VSS , p5 ) ; + VDD , VSS , p1 ) ; input [0:2] in ; input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; input VDD ; input VSS ; -input p5 ; +input p1 ; supply1 VDD ; supply0 VSS ; -scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p5 ) , +scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p1 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -99816,14 +103268,14 @@ endmodule module grid_clb_mux_1level_size2_2 ( in , sram , sram_inv , out , VDD , VSS , - p5 ) ; + p1 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; output [0:0] out ; input VDD ; input VSS ; -input p5 ; +input p1 ; wire [0:2] local_encoder2to3_0_data ; wire [0:2] local_encoder2to3_0_data_inv ; @@ -99842,7 +103294,7 @@ grid_clb_mux_1level_basis_input3_mem3_2 mux_l1_in_0_ ( .mem ( local_encoder2to3_0_data ) , .mem_inv ( local_encoder2to3_0_data_inv ) , .out ( mux_1level_basis_input3_mem3_0_out ) , .VDD ( VDD ) , - .VSS ( VSS ) , .p5 ( p5 ) ) ; + .VSS ( VSS ) , .p1 ( p1 ) ) ; endmodule @@ -99965,29 +103417,29 @@ grid_clb_mux_1level_tapbuf_basis_input3_mem3_1 mux_l1_in_0_ ( .mem_inv ( local_encoder2to3_0_data_inv ) , .out ( mux_1level_tapbuf_basis_input3_mem3_0_out ) , .VDD ( VDD ) , .VSS ( VSS ) , .p1 ( p1 ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_136 ( +sky130_fd_sc_hd__inv_1 BINV_R_135 ( .A ( mux_1level_tapbuf_basis_input3_mem3_0_out[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_137 ( +sky130_fd_sc_hd__inv_8 BINV_R_136 ( .A ( mux_1level_tapbuf_basis_input3_mem3_0_out[0] ) , .Y ( p_abuf0 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module grid_clb_mux_1level_tapbuf_basis_input3_mem3_0 ( in , mem , mem_inv , - out , VDD , VSS , p4 ) ; + out , VDD , VSS , p1 ) ; input [0:2] in ; input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; input VDD ; input VSS ; -input p4 ; +input p1 ; supply1 VDD ; supply0 VSS ; -scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p4 ) , +scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p1 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -100020,7 +103472,7 @@ endmodule module grid_clb_mux_1level_tapbuf_size2_0 ( in , sram , sram_inv , out , VDD , - VSS , p_abuf0 , p4 ) ; + VSS , p_abuf0 , p1 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -100028,7 +103480,7 @@ output [0:0] out ; input VDD ; input VSS ; output p_abuf0 ; -input p4 ; +input p1 ; wire [0:2] local_encoder2to3_0_data ; wire [0:2] local_encoder2to3_0_data_inv ; @@ -100044,11 +103496,11 @@ grid_clb_mux_1level_tapbuf_basis_input3_mem3_0 mux_l1_in_0_ ( .mem ( local_encoder2to3_0_data ) , .mem_inv ( local_encoder2to3_0_data_inv ) , .out ( mux_1level_tapbuf_basis_input3_mem3_0_out ) , .VDD ( VDD ) , - .VSS ( VSS ) , .p4 ( p4 ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_133 ( + .VSS ( VSS ) , .p1 ( p1 ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_132 ( .A ( mux_1level_tapbuf_basis_input3_mem3_0_out[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_134 ( +sky130_fd_sc_hd__inv_8 BINV_R_133 ( .A ( mux_1level_tapbuf_basis_input3_mem3_0_out[0] ) , .Y ( p_abuf0 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -100145,19 +103597,19 @@ endmodule module grid_clb_mux_1level_basis_input3_mem3_1 ( in , mem , mem_inv , out , - VDD , VSS , p4 ) ; + VDD , VSS , p2 ) ; input [0:2] in ; input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; input VDD ; input VSS ; -input p4 ; +input p2 ; supply1 VDD ; supply0 VSS ; -scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p4 ) , +scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p2 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -100190,14 +103642,14 @@ endmodule module grid_clb_mux_1level_size2_1 ( in , sram , sram_inv , out , VDD , VSS , - p4 ) ; + p2 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; output [0:0] out ; input VDD ; input VSS ; -input p4 ; +input p2 ; wire [0:2] local_encoder2to3_0_data ; wire [0:2] local_encoder2to3_0_data_inv ; @@ -100216,24 +103668,24 @@ grid_clb_mux_1level_basis_input3_mem3_1 mux_l1_in_0_ ( .mem ( local_encoder2to3_0_data ) , .mem_inv ( local_encoder2to3_0_data_inv ) , .out ( mux_1level_basis_input3_mem3_0_out ) , .VDD ( VDD ) , - .VSS ( VSS ) , .p4 ( p4 ) ) ; + .VSS ( VSS ) , .p2 ( p2 ) ) ; endmodule module grid_clb_mux_1level_basis_input3_mem3_0 ( in , mem , mem_inv , out , - VDD , VSS , p4 ) ; + VDD , VSS , p2 ) ; input [0:2] in ; input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; input VDD ; input VSS ; -input p4 ; +input p2 ; supply1 VDD ; supply0 VSS ; -scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p4 ) , +scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p2 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -100266,14 +103718,14 @@ endmodule module grid_clb_mux_1level_size2_0 ( in , sram , sram_inv , out , VDD , VSS , - p4 ) ; + p2 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; output [0:0] out ; input VDD ; input VSS ; -input p4 ; +input p2 ; wire [0:2] local_encoder2to3_0_data ; wire [0:2] local_encoder2to3_0_data_inv ; @@ -100292,7 +103744,7 @@ grid_clb_mux_1level_basis_input3_mem3_0 mux_l1_in_0_ ( .mem ( local_encoder2to3_0_data ) , .mem_inv ( local_encoder2to3_0_data_inv ) , .out ( mux_1level_basis_input3_mem3_0_out ) , .VDD ( VDD ) , - .VSS ( VSS ) , .p4 ( p4 ) ) ; + .VSS ( VSS ) , .p2 ( p2 ) ) ; endmodule @@ -100346,7 +103798,7 @@ input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ropt_net_252 ) , +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ropt_net_244 ) , .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , @@ -100399,20 +103851,20 @@ sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_16_ ( .D ( mem_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_1 FTB_1__0 ( .A ( mem_out[16] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1699 ( .A ( copt_net_242 ) , - .X ( copt_net_239 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1700 ( .A ( copt_net_239 ) , - .X ( copt_net_240 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1701 ( .A ( copt_net_244 ) , - .X ( copt_net_241 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1702 ( .A ( copt_net_243 ) , - .X ( copt_net_242 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1703 ( .A ( copt_net_241 ) , - .X ( copt_net_243 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1704 ( .A ( ccff_head[0] ) , - .X ( copt_net_244 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 ropt_h_inst_1712 ( .A ( copt_net_240 ) , - .X ( ropt_net_252 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1589 ( .A ( ccff_head[0] ) , + .X ( copt_net_232 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1590 ( .A ( copt_net_232 ) , + .X ( copt_net_233 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1591 ( .A ( copt_net_233 ) , + .X ( copt_net_234 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1592 ( .A ( copt_net_234 ) , + .X ( copt_net_235 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1593 ( .A ( copt_net_237 ) , + .X ( copt_net_236 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1594 ( .A ( copt_net_235 ) , + .X ( copt_net_237 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 ropt_h_inst_1601 ( .A ( copt_net_236 ) , + .X ( ropt_net_244 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -100583,7 +104035,7 @@ endmodule module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0 ( pReset , prog_clk , frac_logic_in , frac_logic_cin , ccff_head , - frac_logic_out , frac_logic_cout , ccff_tail , VDD , VSS , p4 ) ; + frac_logic_out , frac_logic_cout , ccff_tail , VDD , VSS , p2 ) ; input [0:0] pReset ; input [0:0] prog_clk ; input [0:3] frac_logic_in ; @@ -100594,7 +104046,7 @@ output [0:0] frac_logic_cout ; output [0:0] ccff_tail ; input VDD ; input VSS ; -input p4 ; +input p2 ; wire [0:0] direct_interc_5_out ; wire [0:0] direct_interc_7_out ; @@ -100634,13 +104086,13 @@ grid_clb_mux_1level_size2_0 mux_frac_logic_out_0 ( } ) , .sram ( mux_1level_size2_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_2 , SYNOPSYS_UNCONNECTED_3 } ) , - .out ( frac_logic_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , .p4 ( p4 ) ) ; + .out ( frac_logic_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , .p2 ( p2 ) ) ; grid_clb_mux_1level_size2_1 mux_frac_lut4_0_in_2 ( .in ( { frac_logic_cin[0] , frac_logic_in[2] } ) , .sram ( mux_1level_size2_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_4 , SYNOPSYS_UNCONNECTED_5 } ) , .out ( mux_1level_size2_1_out ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p4 ( p4 ) ) ; + .p2 ( p2 ) ) ; grid_clb_mux_1level_size2_mem_0 mem_frac_logic_out_0 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ) , @@ -100657,7 +104109,7 @@ module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_0 ( pReset , prog_clk , Test_en , fabric_in , fabric_reg_in , fabric_sc_in , fabric_cin , fabric_reset , fabric_clk , ccff_head , fabric_out , fabric_reg_out , fabric_sc_out , fabric_cout , ccff_tail , VDD , VSS , - p_abuf0 , p_abuf1 , p1 , p4 , p5 ) ; + p_abuf0 , p_abuf1 , p1 , p2 , p5 ) ; input [0:0] pReset ; input [0:0] prog_clk ; input [0:0] Test_en ; @@ -100678,7 +104130,7 @@ input VSS ; output p_abuf0 ; output p_abuf1 ; input p1 ; -input p4 ; +input p2 ; input p5 ; wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ; @@ -100706,7 +104158,7 @@ grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ .frac_logic_cout ( { SYNOPSYS_UNCONNECTED_1 } ) , .ccff_tail ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) , - .VDD ( VDD ) , .VSS ( VSS ) , .p4 ( p4 ) ) ; + .VDD ( VDD ) , .VSS ( VSS ) , .p2 ( p2 ) ) ; grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0 ( .Test_en ( Test_en ) , .ff_D ( mux_1level_size2_0_out ) , .ff_DI ( fabric_sc_in ) , .ff_reset ( fabric_reset ) , @@ -100725,7 +104177,7 @@ grid_clb_mux_1level_tapbuf_size2_0 mux_fabric_out_0 ( .sram ( mux_1level_tapbuf_size2_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_2 , SYNOPSYS_UNCONNECTED_3 } ) , .out ( fabric_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p_abuf0 ( p_abuf0 ) , .p4 ( p4 ) ) ; + .p_abuf0 ( p_abuf0 ) , .p1 ( p1 ) ) ; grid_clb_mux_1level_tapbuf_size2_1 mux_fabric_out_1 ( .in ( { fabric_sc_out[0] , logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] @@ -100755,7 +104207,7 @@ grid_clb_mux_1level_size2_2 mux_ff_0_D_0 ( .sram ( mux_1level_size2_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_6 , SYNOPSYS_UNCONNECTED_7 } ) , .out ( mux_1level_size2_0_out ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p5 ( p5 ) ) ; + .p1 ( p1 ) ) ; grid_clb_mux_1level_size2_3 mux_ff_1_D_0 ( .in ( { logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] , @@ -100764,7 +104216,7 @@ grid_clb_mux_1level_size2_3 mux_ff_1_D_0 ( .sram ( mux_1level_size2_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_8 , SYNOPSYS_UNCONNECTED_9 } ) , .out ( mux_1level_size2_1_out ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p1 ( p1 ) ) ; + .p5 ( p5 ) ) ; grid_clb_mux_1level_size2_mem_2 mem_ff_0_D_0 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( mux_1level_tapbuf_size2_mem_1_ccff_tail ) , @@ -100780,7 +104232,7 @@ endmodule module grid_clb_logical_tile_clb_mode_default__fle_0 ( pReset , prog_clk , Test_en , fle_in , fle_reg_in , fle_sc_in , fle_cin , fle_reset , fle_clk , ccff_head , fle_out , fle_reg_out , fle_sc_out , fle_cout , - ccff_tail , VDD , VSS , p_abuf0 , p_abuf1 , p1 , p4 , p5 ) ; + ccff_tail , VDD , VSS , p_abuf0 , p_abuf1 , p1 , p2 , p5 ) ; input [0:0] pReset ; input [0:0] prog_clk ; input [0:0] Test_en ; @@ -100801,7 +104253,7 @@ input VSS ; output p_abuf0 ; output p_abuf1 ; input p1 ; -input p4 ; +input p2 ; input p5 ; supply1 VDD ; @@ -100817,7 +104269,7 @@ grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_0 logical_tile .fabric_reg_out ( fle_reg_out ) , .fabric_sc_out ( fle_sc_out ) , .fabric_cout ( { SYNOPSYS_UNCONNECTED_2 } ) , .ccff_tail ( ccff_tail ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p_abuf0 ( p_abuf0 ) , .p_abuf1 ( p_abuf1 ) , .p1 ( p1 ) , .p4 ( p4 ) , + .p_abuf0 ( p_abuf0 ) , .p_abuf1 ( p_abuf1 ) , .p1 ( p1 ) , .p2 ( p2 ) , .p5 ( p5 ) ) ; endmodule @@ -100926,7 +104378,7 @@ grid_clb_logical_tile_clb_mode_default__fle_0 logical_tile_clb_mode_default__fle .fle_cout ( { SYNOPSYS_UNCONNECTED_2 } ) , .ccff_tail ( logical_tile_clb_mode_default__fle_0_ccff_tail ) , .VDD ( VDD ) , .VSS ( VSS ) , .p_abuf0 ( p_abuf1 ) , - .p_abuf1 ( p_abuf2 ) , .p1 ( p2 ) , .p4 ( p5 ) , .p5 ( p6 ) ) ; + .p_abuf1 ( p_abuf2 ) , .p1 ( p2 ) , .p2 ( p3 ) , .p5 ( p6 ) ) ; grid_clb_logical_tile_clb_mode_default__fle_1 logical_tile_clb_mode_default__fle_1 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , .fle_in ( { clb_I1[0] , clb_I1[1] , clb_I1i[0] , clb_I1i[1] } ) , @@ -100941,7 +104393,7 @@ grid_clb_logical_tile_clb_mode_default__fle_1 logical_tile_clb_mode_default__fle .fle_cout ( { SYNOPSYS_UNCONNECTED_4 } ) , .ccff_tail ( logical_tile_clb_mode_default__fle_1_ccff_tail ) , .VDD ( VDD ) , .VSS ( VSS ) , .p_abuf0 ( p_abuf3 ) , - .p_abuf1 ( p_abuf4 ) , .p0 ( p0 ) , .p5 ( p6 ) ) ; + .p_abuf1 ( p_abuf4 ) , .p0 ( p0 ) , .p1 ( p2 ) , .p5 ( p6 ) ) ; grid_clb_logical_tile_clb_mode_default__fle_2 logical_tile_clb_mode_default__fle_2 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , .fle_in ( { clb_I2[0] , clb_I2[1] , clb_I2i[0] , clb_I2i[1] } ) , @@ -100956,7 +104408,7 @@ grid_clb_logical_tile_clb_mode_default__fle_2 logical_tile_clb_mode_default__fle .fle_cout ( { SYNOPSYS_UNCONNECTED_6 } ) , .ccff_tail ( logical_tile_clb_mode_default__fle_2_ccff_tail ) , .VDD ( VDD ) , .VSS ( VSS ) , .p_abuf0 ( p_abuf5 ) , - .p_abuf1 ( p_abuf6 ) , .p1 ( p2 ) , .p2 ( p3 ) ) ; + .p_abuf1 ( p_abuf6 ) , .p2 ( p3 ) , .p4 ( p5 ) ) ; grid_clb_logical_tile_clb_mode_default__fle_3 logical_tile_clb_mode_default__fle_3 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , .fle_in ( { clb_I3[0] , clb_I3[1] , clb_I3i[0] , clb_I3i[1] } ) , @@ -100971,7 +104423,7 @@ grid_clb_logical_tile_clb_mode_default__fle_3 logical_tile_clb_mode_default__fle .fle_cout ( { SYNOPSYS_UNCONNECTED_8 } ) , .ccff_tail ( logical_tile_clb_mode_default__fle_3_ccff_tail ) , .VDD ( VDD ) , .VSS ( VSS ) , .p_abuf0 ( p_abuf7 ) , - .p_abuf1 ( p_abuf8 ) , .p0 ( p1 ) , .p2 ( p3 ) ) ; + .p_abuf1 ( p_abuf8 ) , .p0 ( p1 ) , .p6 ( p7 ) ) ; grid_clb_logical_tile_clb_mode_default__fle_4 logical_tile_clb_mode_default__fle_4 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , .fle_in ( { clb_I4[0] , clb_I4[1] , clb_I4i[0] , clb_I4i[1] } ) , @@ -100986,7 +104438,7 @@ grid_clb_logical_tile_clb_mode_default__fle_4 logical_tile_clb_mode_default__fle .fle_cout ( { SYNOPSYS_UNCONNECTED_10 } ) , .ccff_tail ( logical_tile_clb_mode_default__fle_4_ccff_tail ) , .VDD ( VDD ) , .VSS ( VSS ) , .p_abuf0 ( p_abuf9 ) , - .p_abuf1 ( p_abuf10 ) , .p0 ( p1 ) ) ; + .p_abuf1 ( p_abuf10 ) , .p6 ( p7 ) ) ; grid_clb_logical_tile_clb_mode_default__fle_5 logical_tile_clb_mode_default__fle_5 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , .fle_in ( { clb_I5[0] , clb_I5[1] , clb_I5i[0] , clb_I5i[1] } ) , @@ -101001,7 +104453,7 @@ grid_clb_logical_tile_clb_mode_default__fle_5 logical_tile_clb_mode_default__fle .fle_cout ( { SYNOPSYS_UNCONNECTED_12 } ) , .ccff_tail ( logical_tile_clb_mode_default__fle_5_ccff_tail ) , .VDD ( VDD ) , .VSS ( VSS ) , .p_abuf0 ( p_abuf11 ) , - .p_abuf1 ( p_abuf12 ) , .p6 ( p7 ) ) ; + .p_abuf1 ( p_abuf12 ) , .p0 ( p1 ) , .p3 ( p4 ) , .p6 ( p7 ) ) ; grid_clb_logical_tile_clb_mode_default__fle_6 logical_tile_clb_mode_default__fle_6 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , .fle_in ( { clb_I6[0] , clb_I6[1] , clb_I6i[0] , clb_I6i[1] } ) , @@ -101016,7 +104468,7 @@ grid_clb_logical_tile_clb_mode_default__fle_6 logical_tile_clb_mode_default__fle .fle_cout ( { SYNOPSYS_UNCONNECTED_14 } ) , .ccff_tail ( logical_tile_clb_mode_default__fle_6_ccff_tail ) , .VDD ( VDD ) , .VSS ( VSS ) , .p_abuf0 ( p_abuf13 ) , - .p_abuf1 ( p_abuf14 ) , .p3 ( p4 ) , .p6 ( p7 ) ) ; + .p_abuf1 ( p_abuf14 ) , .p0 ( p1 ) , .p3 ( p4 ) ) ; grid_clb_logical_tile_clb_mode_default__fle logical_tile_clb_mode_default__fle_7 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , .fle_in ( { clb_I7[0] , clb_I7[1] , clb_I7i[0] , clb_I7i[1] } ) , @@ -101029,7 +104481,7 @@ grid_clb_logical_tile_clb_mode_default__fle logical_tile_clb_mode_default__fle_7 .fle_reg_out ( clb_reg_out ) , .fle_sc_out ( clb_sc_out ) , .fle_cout ( clb_cout ) , .ccff_tail ( ccff_tail ) , .VDD ( VDD ) , .VSS ( VSS ) , .p_abuf0 ( p_abuf0 ) , .p_abuf1 ( p_abuf15 ) , - .p_abuf2 ( p_abuf16 ) , .p0 ( p0 ) , .p3 ( p4 ) ) ; + .p_abuf2 ( p_abuf16 ) , .p0 ( p1 ) , .p3 ( p4 ) ) ; endmodule @@ -101181,7 +104633,10 @@ input clk_0_S_in ; input VDD ; input VSS ; -wire p_abuf12 ; +wire p_abuf10 ; +wire p_abuf14 ; +wire p_abuf16 ; +wire p_abuf0 ; wire prog_clk_0 ; wire [0:0] prog_clk ; wire [0:0] clk ; @@ -101238,17 +104693,18 @@ grid_clb_logical_tile_clb_mode_clb_ logical_tile_clb_mode_clb__0 ( .clb_sc_in ( { SC_IN_BOT } ) , .clb_cin ( { SYNOPSYS_UNCONNECTED_1 } ) , .clb_reset ( Reset ) , .clb_clk ( clk ) , .ccff_head ( ccff_head ) , - .clb_O ( { aps_rename_507_ , aps_rename_508_ , aps_rename_509_ , - aps_rename_510_ , aps_rename_511_ , aps_rename_512_ , - aps_rename_513_ , aps_rename_514_ , aps_rename_515_ , - aps_rename_516_ , right_width_0_height_0__pin_46_lower[0] , - aps_rename_518_ , aps_rename_519_ , aps_rename_520_ , - aps_rename_521_ , aps_rename_522_ } ) , + .clb_O ( { aps_rename_506_ , aps_rename_507_ , aps_rename_508_ , + aps_rename_509_ , aps_rename_510_ , aps_rename_511_ , + aps_rename_512_ , aps_rename_513_ , + right_width_0_height_0__pin_44_lower[0] , aps_rename_515_ , + aps_rename_516_ , aps_rename_517_ , + right_width_0_height_0__pin_48_lower[0] , aps_rename_519_ , + right_width_0_height_0__pin_50_lower[0] , aps_rename_521_ } ) , .clb_reg_out ( bottom_width_0_height_0__pin_52_ ) , - .clb_sc_out ( { aps_rename_523_ } ) , + .clb_sc_out ( { SC_OUT_BOT } ) , .clb_cout ( bottom_width_0_height_0__pin_54_ ) , .ccff_tail ( ccff_tail ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p_abuf0 ( SC_OUT_BOT ) , + .p_abuf0 ( p_abuf0 ) , .p_abuf1 ( top_width_0_height_0__pin_37_lower[0] ) , .p_abuf2 ( top_width_0_height_0__pin_36_lower[0] ) , .p_abuf3 ( top_width_0_height_0__pin_39_lower[0] ) , @@ -101258,127 +104714,114 @@ grid_clb_logical_tile_clb_mode_clb_ logical_tile_clb_mode_clb__0 ( .p_abuf7 ( top_width_0_height_0__pin_43_lower[0] ) , .p_abuf8 ( top_width_0_height_0__pin_42_lower[0] ) , .p_abuf9 ( right_width_0_height_0__pin_45_lower[0] ) , - .p_abuf10 ( right_width_0_height_0__pin_44_lower[0] ) , + .p_abuf10 ( p_abuf10 ) , .p_abuf11 ( right_width_0_height_0__pin_47_lower[0] ) , - .p_abuf12 ( p_abuf12 ) , + .p_abuf12 ( right_width_0_height_0__pin_46_lower[0] ) , .p_abuf13 ( right_width_0_height_0__pin_49_lower[0] ) , - .p_abuf14 ( right_width_0_height_0__pin_48_lower[0] ) , + .p_abuf14 ( p_abuf14 ) , .p_abuf15 ( right_width_0_height_0__pin_51_lower[0] ) , - .p_abuf16 ( right_width_0_height_0__pin_50_lower[0] ) , - .p0 ( optlc_net_227 ) , .p1 ( optlc_net_228 ) , .p2 ( optlc_net_229 ) , - .p3 ( optlc_net_230 ) , .p4 ( optlc_net_231 ) , .p5 ( optlc_net_232 ) , - .p6 ( optlc_net_233 ) , .p7 ( optlc_net_234 ) ) ; + .p_abuf16 ( p_abuf16 ) , .p0 ( optlc_net_220 ) , .p1 ( optlc_net_221 ) , + .p2 ( optlc_net_222 ) , .p3 ( optlc_net_223 ) , .p4 ( optlc_net_224 ) , + .p5 ( optlc_net_225 ) , .p6 ( optlc_net_226 ) , .p7 ( optlc_net_227 ) ) ; sky130_fd_sc_hd__buf_2 Test_en_FTB00 ( .A ( Test_en_W_in ) , .X ( Test_en[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_1 Test_en_W_FTB01 ( .A ( Test_en_W_in ) , - .X ( net_net_181 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_1 Test_en_E_FTB01 ( .A ( Test_en_W_in ) , - .X ( net_net_182 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__bufbuf_16 Test_en_W_FTB01 ( .A ( Test_en_W_in ) , + .X ( Test_en_W_out ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__bufbuf_16 Test_en_E_FTB01 ( .A ( Test_en_W_in ) , + .X ( Test_en_E_out ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_8 pReset_FTB00 ( .A ( pReset_N_in ) , .X ( pReset[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_4 Reset_FTB00 ( .A ( Reset_W_in ) , .X ( Reset[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_1 Reset_W_FTB01 ( .A ( Reset_W_in ) , - .X ( aps_rename_524_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_1 Reset_E_FTB01 ( .A ( Reset_W_in ) , - .X ( aps_rename_525_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__bufbuf_16 Reset_W_FTB01 ( .A ( Reset_W_in ) , + .X ( Reset_W_out ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__bufbuf_16 Reset_E_FTB01 ( .A ( Reset_W_in ) , + .X ( Reset_E_out ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_6 prog_clk_0_FTB00 ( .A ( prog_clk_0_S_in ) , .X ( prog_clk_0 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__clkbuf_1 prog_clk_0_S_FTB01 ( .A ( prog_clk_0_S_in ) , - .X ( ctsbuf_net_1235 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_4 prog_clk_0_S_FTB01 ( .A ( prog_clk_0_S_in ) , + .X ( ctsbuf_net_1228 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__clkbuf_1 prog_clk_0_E_FTB01 ( .A ( prog_clk_0_S_in ) , - .X ( ctsbuf_net_2236 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .X ( ctsbuf_net_2229 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__clkbuf_1 prog_clk_0_W_FTB01 ( .A ( prog_clk_0_S_in ) , - .X ( ctsbuf_net_3237 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_4 prog_clk_0_N_FTB01 ( .A ( prog_clk_0_S_in ) , - .X ( ctsbuf_net_4238 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .X ( ctsbuf_net_3230 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__clkbuf_1 prog_clk_0_N_FTB01 ( .A ( prog_clk_0_S_in ) , + .X ( ctsbuf_net_4231 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_1 clk_0_FTB00 ( .A ( clk_0_S_in ) , .X ( clk[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_6 FTB_113__112 ( .A ( aps_rename_507_ ) , +sky130_fd_sc_hd__buf_6 FTB_113__112 ( .A ( aps_rename_506_ ) , .X ( top_width_0_height_0__pin_36_upper[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_6 FTB_114__113 ( .A ( aps_rename_508_ ) , +sky130_fd_sc_hd__buf_6 FTB_114__113 ( .A ( aps_rename_507_ ) , .X ( top_width_0_height_0__pin_37_upper[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_6 FTB_115__114 ( .A ( aps_rename_509_ ) , +sky130_fd_sc_hd__buf_6 FTB_115__114 ( .A ( aps_rename_508_ ) , .X ( top_width_0_height_0__pin_38_upper[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_6 FTB_116__115 ( .A ( aps_rename_510_ ) , +sky130_fd_sc_hd__buf_6 FTB_116__115 ( .A ( aps_rename_509_ ) , .X ( top_width_0_height_0__pin_39_upper[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_6 FTB_117__116 ( .A ( aps_rename_511_ ) , +sky130_fd_sc_hd__buf_6 FTB_117__116 ( .A ( aps_rename_510_ ) , .X ( top_width_0_height_0__pin_40_upper[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_6 FTB_118__117 ( .A ( aps_rename_512_ ) , +sky130_fd_sc_hd__buf_6 FTB_118__117 ( .A ( aps_rename_511_ ) , .X ( top_width_0_height_0__pin_41_upper[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_6 FTB_119__118 ( .A ( aps_rename_513_ ) , +sky130_fd_sc_hd__buf_6 FTB_119__118 ( .A ( aps_rename_512_ ) , .X ( top_width_0_height_0__pin_42_upper[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_6 FTB_120__119 ( .A ( aps_rename_514_ ) , +sky130_fd_sc_hd__buf_6 FTB_120__119 ( .A ( aps_rename_513_ ) , .X ( top_width_0_height_0__pin_43_upper[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_6 FTB_121__120 ( .A ( aps_rename_515_ ) , +sky130_fd_sc_hd__buf_6 FTB_121__120 ( .A ( p_abuf10 ) , .X ( right_width_0_height_0__pin_44_upper[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_6 FTB_122__121 ( .A ( aps_rename_516_ ) , +sky130_fd_sc_hd__buf_6 FTB_122__121 ( .A ( aps_rename_515_ ) , .X ( right_width_0_height_0__pin_45_upper[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_6 FTB_123__122 ( .A ( p_abuf12 ) , +sky130_fd_sc_hd__buf_6 FTB_123__122 ( .A ( aps_rename_516_ ) , .X ( right_width_0_height_0__pin_46_upper[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_6 FTB_124__123 ( .A ( aps_rename_518_ ) , +sky130_fd_sc_hd__buf_6 FTB_124__123 ( .A ( aps_rename_517_ ) , .X ( right_width_0_height_0__pin_47_upper[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_6 FTB_125__124 ( .A ( aps_rename_519_ ) , +sky130_fd_sc_hd__buf_6 FTB_125__124 ( .A ( p_abuf14 ) , .X ( right_width_0_height_0__pin_48_upper[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_6 FTB_126__125 ( .A ( aps_rename_520_ ) , +sky130_fd_sc_hd__buf_6 FTB_126__125 ( .A ( aps_rename_519_ ) , .X ( right_width_0_height_0__pin_49_upper[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_6 FTB_127__126 ( .A ( aps_rename_521_ ) , +sky130_fd_sc_hd__buf_6 FTB_127__126 ( .A ( p_abuf16 ) , .X ( right_width_0_height_0__pin_50_upper[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_6 FTB_128__127 ( .A ( aps_rename_522_ ) , +sky130_fd_sc_hd__buf_6 FTB_128__127 ( .A ( aps_rename_521_ ) , .X ( right_width_0_height_0__pin_51_upper[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_6 FTB_129__128 ( .A ( aps_rename_523_ ) , - .X ( SC_OUT_TOP ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_181 ( .A ( net_net_181 ) , - .X ( Test_en_W_out ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_182 ( .A ( net_net_182 ) , - .X ( Test_en_E_out ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_183 ( .A ( BUF_net_184 ) , .Y ( Reset_W_out ) , +sky130_fd_sc_hd__buf_6 FTB_129__128 ( .A ( p_abuf0 ) , .X ( SC_OUT_TOP ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_184 ( .A ( aps_rename_524_ ) , - .Y ( BUF_net_184 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_185 ( .A ( BUF_net_186 ) , .Y ( Reset_E_out ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_186 ( .A ( aps_rename_525_ ) , - .Y ( BUF_net_186 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_189 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , +sky130_fd_sc_hd__conb_1 optlc_182 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , + .HI ( optlc_net_220 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_184 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , + .HI ( optlc_net_221 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_186 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , + .HI ( optlc_net_222 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_188 ( .LO ( SYNOPSYS_UNCONNECTED_5 ) , + .HI ( optlc_net_223 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_190 ( .LO ( SYNOPSYS_UNCONNECTED_6 ) , + .HI ( optlc_net_224 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_192 ( .LO ( SYNOPSYS_UNCONNECTED_7 ) , + .HI ( optlc_net_225 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_194 ( .LO ( SYNOPSYS_UNCONNECTED_8 ) , + .HI ( optlc_net_226 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_196 ( .LO ( SYNOPSYS_UNCONNECTED_9 ) , .HI ( optlc_net_227 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_191 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , - .HI ( optlc_net_228 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_193 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , - .HI ( optlc_net_229 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_195 ( .LO ( SYNOPSYS_UNCONNECTED_5 ) , - .HI ( optlc_net_230 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_197 ( .LO ( SYNOPSYS_UNCONNECTED_6 ) , - .HI ( optlc_net_231 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_199 ( .LO ( SYNOPSYS_UNCONNECTED_7 ) , - .HI ( optlc_net_232 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_201 ( .LO ( SYNOPSYS_UNCONNECTED_8 ) , - .HI ( optlc_net_233 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_203 ( .LO ( SYNOPSYS_UNCONNECTED_9 ) , - .HI ( optlc_net_234 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_6 cts_buf_4181396 ( .A ( ctsbuf_net_1235 ) , +sky130_fd_sc_hd__buf_6 cts_buf_4181389 ( .A ( ctsbuf_net_1228 ) , .X ( prog_clk_0_S_out ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_6 cts_buf_4231401 ( .A ( ctsbuf_net_2236 ) , +sky130_fd_sc_hd__clkbuf_8 cts_buf_4231394 ( .A ( ctsbuf_net_2229 ) , .X ( prog_clk_0_E_out ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_6 cts_buf_4281406 ( .A ( ctsbuf_net_3237 ) , +sky130_fd_sc_hd__buf_6 cts_buf_4281399 ( .A ( ctsbuf_net_3230 ) , .X ( prog_clk_0_W_out ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_6 cts_buf_4331411 ( .A ( ctsbuf_net_4238 ) , +sky130_fd_sc_hd__buf_6 cts_buf_4331404 ( .A ( ctsbuf_net_4231 ) , .X ( prog_clk_0_N_out ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -101763,7 +105206,19 @@ module fpga_core ( pReset , prog_clk , Test_en , IO_ISOL_N , clk , Reset , p3478 , p3479 , p3480 , p3481 , p3482 , p3483 , p3484 , p3485 , p3486 , p3487 , p3488 , p3489 , p3490 , p3491 , p3492 , p3493 , p3494 , p3495 , p3496 , p3497 , p3498 , p3499 , p3500 , p3501 , p3502 , p3503 , p3504 , - p3505 , p3506 , p3507 , p3508 , p3509 ) ; + p3505 , p3506 , p3507 , p3508 , p3509 , p3510 , p3511 , p3512 , p3513 , + p3514 , p3515 , p3516 , p3517 , p3518 , p3519 , p3520 , p3521 , p3522 , + p3523 , p3524 , p3525 , p3526 , p3527 , p3528 , p3529 , p3530 , p3531 , + p3532 , p3533 , p3534 , p3535 , p3536 , p3537 , p3538 , p3539 , p3540 , + p3541 , p3542 , p3543 , p3544 , p3545 , p3546 , p3547 , p3548 , p3549 , + p3550 , p3551 , p3552 , p3553 , p3554 , p3555 , p3556 , p3557 , p3558 , + p3559 , p3560 , p3561 , p3562 , p3563 , p3564 , p3565 , p3566 , p3567 , + p3568 , p3569 , p3570 , p3571 , p3572 , p3573 , p3574 , p3575 , p3576 , + p3577 , p3578 , p3579 , p3580 , p3581 , p3582 , p3583 , p3584 , p3585 , + p3586 , p3587 , p3588 , p3589 , p3590 , p3591 , p3592 , p3593 , p3594 , + p3595 , p3596 , p3597 , p3598 , p3599 , p3600 , p3601 , p3602 , p3603 , + p3604 , p3605 , p3606 , p3607 , p3608 , p3609 , p3610 , p3611 , p3612 , + p3613 , p3614 , p3615 , p3616 , p3617 , p3618 , p3619 , p3620 ) ; input [0:0] pReset ; input [0:0] prog_clk ; input [0:0] Test_en ; @@ -105290,6 +108745,117 @@ input p3506 ; input p3507 ; input p3508 ; input p3509 ; +input p3510 ; +input p3511 ; +input p3512 ; +input p3513 ; +input p3514 ; +input p3515 ; +input p3516 ; +input p3517 ; +input p3518 ; +input p3519 ; +input p3520 ; +input p3521 ; +input p3522 ; +input p3523 ; +input p3524 ; +input p3525 ; +input p3526 ; +input p3527 ; +input p3528 ; +input p3529 ; +input p3530 ; +input p3531 ; +input p3532 ; +input p3533 ; +input p3534 ; +input p3535 ; +input p3536 ; +input p3537 ; +input p3538 ; +input p3539 ; +input p3540 ; +input p3541 ; +input p3542 ; +input p3543 ; +input p3544 ; +input p3545 ; +input p3546 ; +input p3547 ; +input p3548 ; +input p3549 ; +input p3550 ; +input p3551 ; +input p3552 ; +input p3553 ; +input p3554 ; +input p3555 ; +input p3556 ; +input p3557 ; +input p3558 ; +input p3559 ; +input p3560 ; +input p3561 ; +input p3562 ; +input p3563 ; +input p3564 ; +input p3565 ; +input p3566 ; +input p3567 ; +input p3568 ; +input p3569 ; +input p3570 ; +input p3571 ; +input p3572 ; +input p3573 ; +input p3574 ; +input p3575 ; +input p3576 ; +input p3577 ; +input p3578 ; +input p3579 ; +input p3580 ; +input p3581 ; +input p3582 ; +input p3583 ; +input p3584 ; +input p3585 ; +input p3586 ; +input p3587 ; +input p3588 ; +input p3589 ; +input p3590 ; +input p3591 ; +input p3592 ; +input p3593 ; +input p3594 ; +input p3595 ; +input p3596 ; +input p3597 ; +input p3598 ; +input p3599 ; +input p3600 ; +input p3601 ; +input p3602 ; +input p3603 ; +input p3604 ; +input p3605 ; +input p3606 ; +input p3607 ; +input p3608 ; +input p3609 ; +input p3610 ; +input p3611 ; +input p3612 ; +input p3613 ; +input p3614 ; +input p3615 ; +input p3616 ; +input p3617 ; +input p3618 ; +input p3619 ; +input p3620 ; wire [0:0] cbx_1__0__0_bottom_grid_pin_0_ ; wire [0:0] cbx_1__0__0_bottom_grid_pin_10_ ; @@ -131189,16 +134755,16 @@ sb_1__0_ sb_1__0_ ( .chanx_right_out ( sb_1__0__0_chanx_right_out ) , .chanx_left_out ( sb_1__0__0_chanx_left_out ) , .ccff_tail ( sb_1__0__0_ccff_tail ) , .SC_IN_TOP ( scff_Wires[26] ) , - .SC_OUT_TOP ( scff_Wires[27] ) , .Test_en_S_in ( p829 ) , + .SC_OUT_TOP ( scff_Wires[27] ) , .Test_en_S_in ( p1352 ) , .Test_en_N_out ( SYNOPSYS_UNCONNECTED_2055 ) , .pReset_S_in ( SYNOPSYS_UNCONNECTED_2056 ) , .pReset_E_in ( pResetWires[28] ) , .pReset_W_in ( SYNOPSYS_UNCONNECTED_2057 ) , .pReset_N_out ( pResetWires[27] ) , .pReset_W_out ( pResetWires[26] ) , - .pReset_E_out ( SYNOPSYS_UNCONNECTED_2058 ) , .Reset_S_in ( p829 ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_2058 ) , .Reset_S_in ( p1352 ) , .Reset_N_out ( SYNOPSYS_UNCONNECTED_2059 ) , - .prog_clk_0_N_in ( prog_clk_0_wires[2] ) , .prog_clk_3_S_in ( p829 ) , - .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_2060 ) , .clk_3_S_in ( p829 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[2] ) , .prog_clk_3_S_in ( p1352 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_2060 ) , .clk_3_S_in ( p1352 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_2061 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_1__0_ sb_2__0_ ( .pReset ( { SYNOPSYS_UNCONNECTED_2062 } ) , @@ -131235,17 +134801,17 @@ sb_1__0_ sb_2__0_ ( .chany_top_out ( sb_1__0__1_chany_top_out ) , .chanx_right_out ( sb_1__0__1_chanx_right_out ) , .chanx_left_out ( sb_1__0__1_chanx_left_out ) , - .ccff_tail ( sb_1__0__1_ccff_tail ) , .SC_IN_TOP ( p1229 ) , - .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_2063 ) , .Test_en_S_in ( p753 ) , + .ccff_tail ( sb_1__0__1_ccff_tail ) , .SC_IN_TOP ( p1155 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_2063 ) , .Test_en_S_in ( p1142 ) , .Test_en_N_out ( SYNOPSYS_UNCONNECTED_2064 ) , .pReset_S_in ( SYNOPSYS_UNCONNECTED_2065 ) , .pReset_E_in ( pResetWires[31] ) , .pReset_W_in ( SYNOPSYS_UNCONNECTED_2066 ) , .pReset_N_out ( pResetWires[30] ) , .pReset_W_out ( pResetWires[29] ) , - .pReset_E_out ( SYNOPSYS_UNCONNECTED_2067 ) , .Reset_S_in ( p753 ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_2067 ) , .Reset_S_in ( p1142 ) , .Reset_N_out ( SYNOPSYS_UNCONNECTED_2068 ) , - .prog_clk_0_N_in ( prog_clk_0_wires[65] ) , .prog_clk_3_S_in ( p753 ) , - .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_2069 ) , .clk_3_S_in ( p753 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[65] ) , .prog_clk_3_S_in ( p1142 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_2069 ) , .clk_3_S_in ( p1142 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_2070 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_1__0_ sb_3__0_ ( .pReset ( { SYNOPSYS_UNCONNECTED_2071 } ) , @@ -131283,16 +134849,16 @@ sb_1__0_ sb_3__0_ ( .chanx_right_out ( sb_1__0__2_chanx_right_out ) , .chanx_left_out ( sb_1__0__2_chanx_left_out ) , .ccff_tail ( sb_1__0__2_ccff_tail ) , .SC_IN_TOP ( scff_Wires[79] ) , - .SC_OUT_TOP ( scff_Wires[80] ) , .Test_en_S_in ( p1276 ) , + .SC_OUT_TOP ( scff_Wires[80] ) , .Test_en_S_in ( p1149 ) , .Test_en_N_out ( SYNOPSYS_UNCONNECTED_2072 ) , .pReset_S_in ( SYNOPSYS_UNCONNECTED_2073 ) , .pReset_E_in ( pResetWires[34] ) , .pReset_W_in ( SYNOPSYS_UNCONNECTED_2074 ) , .pReset_N_out ( pResetWires[33] ) , .pReset_W_out ( pResetWires[32] ) , - .pReset_E_out ( SYNOPSYS_UNCONNECTED_2075 ) , .Reset_S_in ( p1276 ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_2075 ) , .Reset_S_in ( p1149 ) , .Reset_N_out ( SYNOPSYS_UNCONNECTED_2076 ) , - .prog_clk_0_N_in ( prog_clk_0_wires[103] ) , .prog_clk_3_S_in ( p1276 ) , - .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_2077 ) , .clk_3_S_in ( p1276 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[103] ) , .prog_clk_3_S_in ( p1149 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_2077 ) , .clk_3_S_in ( p1149 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_2078 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_1__0_ sb_4__0_ ( .pReset ( { SYNOPSYS_UNCONNECTED_2079 } ) , @@ -131329,17 +134895,17 @@ sb_1__0_ sb_4__0_ ( .chany_top_out ( sb_1__0__3_chany_top_out ) , .chanx_right_out ( sb_1__0__3_chanx_right_out ) , .chanx_left_out ( sb_1__0__3_chanx_left_out ) , - .ccff_tail ( sb_1__0__3_ccff_tail ) , .SC_IN_TOP ( p1395 ) , - .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_2080 ) , .Test_en_S_in ( p1329 ) , + .ccff_tail ( sb_1__0__3_ccff_tail ) , .SC_IN_TOP ( p1309 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_2080 ) , .Test_en_S_in ( p1251 ) , .Test_en_N_out ( SYNOPSYS_UNCONNECTED_2081 ) , .pReset_S_in ( SYNOPSYS_UNCONNECTED_2082 ) , .pReset_E_in ( pResetWires[37] ) , .pReset_W_in ( SYNOPSYS_UNCONNECTED_2083 ) , .pReset_N_out ( pResetWires[36] ) , .pReset_W_out ( pResetWires[35] ) , - .pReset_E_out ( SYNOPSYS_UNCONNECTED_2084 ) , .Reset_S_in ( p1329 ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_2084 ) , .Reset_S_in ( p1251 ) , .Reset_N_out ( SYNOPSYS_UNCONNECTED_2085 ) , - .prog_clk_0_N_in ( prog_clk_0_wires[141] ) , .prog_clk_3_S_in ( p1329 ) , - .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_2086 ) , .clk_3_S_in ( p1329 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[141] ) , .prog_clk_3_S_in ( p1251 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_2086 ) , .clk_3_S_in ( p1251 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_2087 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_1__0_ sb_5__0_ ( .pReset ( { SYNOPSYS_UNCONNECTED_2088 } ) , @@ -131377,16 +134943,16 @@ sb_1__0_ sb_5__0_ ( .chanx_right_out ( sb_1__0__4_chanx_right_out ) , .chanx_left_out ( sb_1__0__4_chanx_left_out ) , .ccff_tail ( sb_1__0__4_ccff_tail ) , .SC_IN_TOP ( scff_Wires[132] ) , - .SC_OUT_TOP ( scff_Wires[133] ) , .Test_en_S_in ( p1210 ) , + .SC_OUT_TOP ( scff_Wires[133] ) , .Test_en_S_in ( p1141 ) , .Test_en_N_out ( SYNOPSYS_UNCONNECTED_2089 ) , .pReset_S_in ( SYNOPSYS_UNCONNECTED_2090 ) , .pReset_E_in ( pResetWires[40] ) , .pReset_W_in ( SYNOPSYS_UNCONNECTED_2091 ) , .pReset_N_out ( pResetWires[39] ) , .pReset_W_out ( pResetWires[38] ) , - .pReset_E_out ( SYNOPSYS_UNCONNECTED_2092 ) , .Reset_S_in ( p1210 ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_2092 ) , .Reset_S_in ( p1141 ) , .Reset_N_out ( SYNOPSYS_UNCONNECTED_2093 ) , - .prog_clk_0_N_in ( prog_clk_0_wires[179] ) , .prog_clk_3_S_in ( p1210 ) , - .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_2094 ) , .clk_3_S_in ( p1210 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[179] ) , .prog_clk_3_S_in ( p1481 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_2094 ) , .clk_3_S_in ( p1141 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_2095 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_1__0_ sb_6__0_ ( .pReset ( { SYNOPSYS_UNCONNECTED_2096 } ) , @@ -131423,7 +134989,7 @@ sb_1__0_ sb_6__0_ ( .chany_top_out ( sb_1__0__5_chany_top_out ) , .chanx_right_out ( sb_1__0__5_chanx_right_out ) , .chanx_left_out ( sb_1__0__5_chanx_left_out ) , - .ccff_tail ( sb_1__0__5_ccff_tail ) , .SC_IN_TOP ( p1330 ) , + .ccff_tail ( sb_1__0__5_ccff_tail ) , .SC_IN_TOP ( p1313 ) , .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_2097 ) , .Test_en_S_in ( Test_en[0] ) , .Test_en_N_out ( Test_enWires[1] ) , .pReset_S_in ( pReset[0] ) , .pReset_E_in ( SYNOPSYS_UNCONNECTED_2098 ) , @@ -131471,16 +135037,16 @@ sb_1__0_ sb_7__0_ ( .chanx_right_out ( sb_1__0__6_chanx_right_out ) , .chanx_left_out ( sb_1__0__6_chanx_left_out ) , .ccff_tail ( sb_1__0__6_ccff_tail ) , .SC_IN_TOP ( scff_Wires[185] ) , - .SC_OUT_TOP ( scff_Wires[186] ) , .Test_en_S_in ( p1165 ) , + .SC_OUT_TOP ( scff_Wires[186] ) , .Test_en_S_in ( p893 ) , .Test_en_N_out ( SYNOPSYS_UNCONNECTED_2101 ) , .pReset_S_in ( SYNOPSYS_UNCONNECTED_2102 ) , .pReset_E_in ( SYNOPSYS_UNCONNECTED_2103 ) , .pReset_W_in ( pResetWires[44] ) , .pReset_N_out ( pResetWires[45] ) , .pReset_W_out ( SYNOPSYS_UNCONNECTED_2104 ) , - .pReset_E_out ( pResetWires[46] ) , .Reset_S_in ( p1523 ) , + .pReset_E_out ( pResetWires[46] ) , .Reset_S_in ( p893 ) , .Reset_N_out ( SYNOPSYS_UNCONNECTED_2105 ) , - .prog_clk_0_N_in ( prog_clk_0_wires[255] ) , .prog_clk_3_S_in ( p1523 ) , - .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_2106 ) , .clk_3_S_in ( p1523 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[255] ) , .prog_clk_3_S_in ( p893 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_2106 ) , .clk_3_S_in ( p893 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_2107 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_1__0_ sb_8__0_ ( .pReset ( { SYNOPSYS_UNCONNECTED_2108 } ) , @@ -131517,17 +135083,17 @@ sb_1__0_ sb_8__0_ ( .chany_top_out ( sb_1__0__7_chany_top_out ) , .chanx_right_out ( sb_1__0__7_chanx_right_out ) , .chanx_left_out ( sb_1__0__7_chanx_left_out ) , - .ccff_tail ( sb_1__0__7_ccff_tail ) , .SC_IN_TOP ( p1461 ) , - .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_2109 ) , .Test_en_S_in ( p981 ) , + .ccff_tail ( sb_1__0__7_ccff_tail ) , .SC_IN_TOP ( p1448 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_2109 ) , .Test_en_S_in ( p1046 ) , .Test_en_N_out ( SYNOPSYS_UNCONNECTED_2110 ) , .pReset_S_in ( SYNOPSYS_UNCONNECTED_2111 ) , .pReset_E_in ( SYNOPSYS_UNCONNECTED_2112 ) , .pReset_W_in ( pResetWires[47] ) , .pReset_N_out ( pResetWires[48] ) , .pReset_W_out ( SYNOPSYS_UNCONNECTED_2113 ) , - .pReset_E_out ( pResetWires[49] ) , .Reset_S_in ( p981 ) , + .pReset_E_out ( pResetWires[49] ) , .Reset_S_in ( p1046 ) , .Reset_N_out ( SYNOPSYS_UNCONNECTED_2114 ) , - .prog_clk_0_N_in ( prog_clk_0_wires[293] ) , .prog_clk_3_S_in ( p981 ) , - .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_2115 ) , .clk_3_S_in ( p981 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[293] ) , .prog_clk_3_S_in ( p1046 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_2115 ) , .clk_3_S_in ( p1046 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_2116 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_1__0_ sb_9__0_ ( .pReset ( { SYNOPSYS_UNCONNECTED_2117 } ) , @@ -131565,16 +135131,16 @@ sb_1__0_ sb_9__0_ ( .chanx_right_out ( sb_1__0__8_chanx_right_out ) , .chanx_left_out ( sb_1__0__8_chanx_left_out ) , .ccff_tail ( sb_1__0__8_ccff_tail ) , .SC_IN_TOP ( scff_Wires[238] ) , - .SC_OUT_TOP ( scff_Wires[239] ) , .Test_en_S_in ( p1066 ) , + .SC_OUT_TOP ( scff_Wires[239] ) , .Test_en_S_in ( p813 ) , .Test_en_N_out ( SYNOPSYS_UNCONNECTED_2118 ) , .pReset_S_in ( SYNOPSYS_UNCONNECTED_2119 ) , .pReset_E_in ( SYNOPSYS_UNCONNECTED_2120 ) , .pReset_W_in ( pResetWires[50] ) , .pReset_N_out ( pResetWires[51] ) , .pReset_W_out ( SYNOPSYS_UNCONNECTED_2121 ) , - .pReset_E_out ( pResetWires[52] ) , .Reset_S_in ( p1066 ) , + .pReset_E_out ( pResetWires[52] ) , .Reset_S_in ( p813 ) , .Reset_N_out ( SYNOPSYS_UNCONNECTED_2122 ) , - .prog_clk_0_N_in ( prog_clk_0_wires[331] ) , .prog_clk_3_S_in ( p1066 ) , - .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_2123 ) , .clk_3_S_in ( p1066 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[331] ) , .prog_clk_3_S_in ( p1447 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_2123 ) , .clk_3_S_in ( p813 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_2124 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_1__0_ sb_10__0_ ( .pReset ( { SYNOPSYS_UNCONNECTED_2125 } ) , @@ -131611,17 +135177,17 @@ sb_1__0_ sb_10__0_ ( .chany_top_out ( sb_1__0__9_chany_top_out ) , .chanx_right_out ( sb_1__0__9_chanx_right_out ) , .chanx_left_out ( sb_1__0__9_chanx_left_out ) , - .ccff_tail ( sb_1__0__9_ccff_tail ) , .SC_IN_TOP ( p1181 ) , - .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_2126 ) , .Test_en_S_in ( p1086 ) , + .ccff_tail ( sb_1__0__9_ccff_tail ) , .SC_IN_TOP ( p1221 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_2126 ) , .Test_en_S_in ( p1477 ) , .Test_en_N_out ( SYNOPSYS_UNCONNECTED_2127 ) , .pReset_S_in ( SYNOPSYS_UNCONNECTED_2128 ) , .pReset_E_in ( SYNOPSYS_UNCONNECTED_2129 ) , .pReset_W_in ( pResetWires[53] ) , .pReset_N_out ( pResetWires[54] ) , .pReset_W_out ( SYNOPSYS_UNCONNECTED_2130 ) , - .pReset_E_out ( pResetWires[55] ) , .Reset_S_in ( p1086 ) , + .pReset_E_out ( pResetWires[55] ) , .Reset_S_in ( p1477 ) , .Reset_N_out ( SYNOPSYS_UNCONNECTED_2131 ) , - .prog_clk_0_N_in ( prog_clk_0_wires[369] ) , .prog_clk_3_S_in ( p1086 ) , - .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_2132 ) , .clk_3_S_in ( p1086 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[369] ) , .prog_clk_3_S_in ( p1084 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_2132 ) , .clk_3_S_in ( p1477 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_2133 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_1__0_ sb_11__0_ ( .pReset ( { SYNOPSYS_UNCONNECTED_2134 } ) , @@ -131659,16 +135225,16 @@ sb_1__0_ sb_11__0_ ( .chanx_right_out ( sb_1__0__10_chanx_right_out ) , .chanx_left_out ( sb_1__0__10_chanx_left_out ) , .ccff_tail ( sb_1__0__10_ccff_tail ) , .SC_IN_TOP ( scff_Wires[291] ) , - .SC_OUT_TOP ( scff_Wires[292] ) , .Test_en_S_in ( p1368 ) , + .SC_OUT_TOP ( scff_Wires[292] ) , .Test_en_S_in ( p1374 ) , .Test_en_N_out ( SYNOPSYS_UNCONNECTED_2135 ) , .pReset_S_in ( SYNOPSYS_UNCONNECTED_2136 ) , .pReset_E_in ( SYNOPSYS_UNCONNECTED_2137 ) , .pReset_W_in ( pResetWires[56] ) , .pReset_N_out ( pResetWires[57] ) , .pReset_W_out ( SYNOPSYS_UNCONNECTED_2138 ) , - .pReset_E_out ( pResetWires[58] ) , .Reset_S_in ( p1368 ) , + .pReset_E_out ( pResetWires[58] ) , .Reset_S_in ( p1374 ) , .Reset_N_out ( SYNOPSYS_UNCONNECTED_2139 ) , - .prog_clk_0_N_in ( prog_clk_0_wires[407] ) , .prog_clk_3_S_in ( p1368 ) , - .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_2140 ) , .clk_3_S_in ( p1368 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[407] ) , .prog_clk_3_S_in ( p1374 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_2140 ) , .clk_3_S_in ( p1374 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_2141 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_1__1_ sb_1__1_ ( .pReset ( { SYNOPSYS_UNCONNECTED_2142 } ) , @@ -131713,27 +135279,27 @@ sb_1__1_ sb_1__1_ ( .chanx_right_out ( sb_1__1__0_chanx_right_out ) , .chany_bottom_out ( sb_1__1__0_chany_bottom_out ) , .chanx_left_out ( sb_1__1__0_chanx_left_out ) , - .ccff_tail ( sb_1__1__0_ccff_tail ) , .Test_en_S_in ( p2487 ) , + .ccff_tail ( sb_1__1__0_ccff_tail ) , .Test_en_S_in ( p2787 ) , .Test_en_N_out ( SYNOPSYS_UNCONNECTED_2143 ) , .pReset_S_in ( SYNOPSYS_UNCONNECTED_2144 ) , .pReset_E_in ( pResetWires[66] ) , .pReset_W_in ( SYNOPSYS_UNCONNECTED_2145 ) , .pReset_N_out ( pResetWires[65] ) , .pReset_W_out ( pResetWires[62] ) , - .pReset_E_out ( SYNOPSYS_UNCONNECTED_2146 ) , .Reset_S_in ( p3360 ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_2146 ) , .Reset_S_in ( p2787 ) , .Reset_N_out ( SYNOPSYS_UNCONNECTED_2147 ) , .prog_clk_0_N_in ( prog_clk_0_wires[8] ) , .prog_clk_1_N_in ( prog_clk_2_wires[4] ) , .prog_clk_1_S_in ( SYNOPSYS_UNCONNECTED_2148 ) , .prog_clk_1_E_out ( prog_clk_1_wires[1] ) , - .prog_clk_1_W_out ( prog_clk_1_wires[2] ) , .prog_clk_2_N_in ( p3487 ) , - .prog_clk_2_E_in ( p1183 ) , .prog_clk_2_S_in ( p378 ) , - .prog_clk_2_W_in ( p1176 ) , + .prog_clk_1_W_out ( prog_clk_1_wires[2] ) , .prog_clk_2_N_in ( p3228 ) , + .prog_clk_2_E_in ( p437 ) , .prog_clk_2_S_in ( p76 ) , + .prog_clk_2_W_in ( p439 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_2149 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_2150 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_2151 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_2152 ) , - .prog_clk_3_W_in ( p2693 ) , .prog_clk_3_E_in ( p168 ) , - .prog_clk_3_S_in ( p1116 ) , .prog_clk_3_N_in ( p3483 ) , + .prog_clk_3_W_in ( p2990 ) , .prog_clk_3_E_in ( p674 ) , + .prog_clk_3_S_in ( p887 ) , .prog_clk_3_N_in ( p3191 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_2153 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_2154 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_2155 ) , @@ -131741,12 +135307,12 @@ sb_1__1_ sb_1__1_ ( .clk_1_N_in ( clk_2_wires[4] ) , .clk_1_S_in ( SYNOPSYS_UNCONNECTED_2157 ) , .clk_1_E_out ( clk_1_wires[1] ) , .clk_1_W_out ( clk_1_wires[2] ) , - .clk_2_N_in ( p3177 ) , .clk_2_E_in ( p986 ) , .clk_2_S_in ( p3340 ) , - .clk_2_W_in ( p2571 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_2158 ) , + .clk_2_N_in ( p3000 ) , .clk_2_E_in ( p117 ) , .clk_2_S_in ( p541 ) , + .clk_2_W_in ( p2868 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_2158 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_2159 ) , .clk_2_N_out ( SYNOPSYS_UNCONNECTED_2160 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_2161 ) , .clk_3_W_in ( p2693 ) , - .clk_3_E_in ( p858 ) , .clk_3_S_in ( p83 ) , .clk_3_N_in ( p3130 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_2161 ) , .clk_3_W_in ( p2975 ) , + .clk_3_E_in ( p962 ) , .clk_3_S_in ( p2672 ) , .clk_3_N_in ( p2922 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_2162 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_2163 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_2164 ) , @@ -131794,16 +135360,16 @@ sb_1__1_ sb_1__2_ ( .chanx_right_out ( sb_1__1__1_chanx_right_out ) , .chany_bottom_out ( sb_1__1__1_chany_bottom_out ) , .chanx_left_out ( sb_1__1__1_chanx_left_out ) , - .ccff_tail ( sb_1__1__1_ccff_tail ) , .Test_en_S_in ( p2944 ) , + .ccff_tail ( sb_1__1__1_ccff_tail ) , .Test_en_S_in ( p2997 ) , .Test_en_N_out ( SYNOPSYS_UNCONNECTED_2167 ) , .pReset_S_in ( SYNOPSYS_UNCONNECTED_2168 ) , .pReset_E_in ( pResetWires[115] ) , .pReset_W_in ( SYNOPSYS_UNCONNECTED_2169 ) , .pReset_N_out ( pResetWires[114] ) , .pReset_W_out ( pResetWires[111] ) , - .pReset_E_out ( SYNOPSYS_UNCONNECTED_2170 ) , .Reset_S_in ( p2944 ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_2170 ) , .Reset_S_in ( p2997 ) , .Reset_N_out ( SYNOPSYS_UNCONNECTED_2171 ) , - .prog_clk_0_N_in ( prog_clk_0_wires[13] ) , .prog_clk_1_N_in ( p1220 ) , - .prog_clk_1_S_in ( p383 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[13] ) , .prog_clk_1_N_in ( p1504 ) , + .prog_clk_1_S_in ( p519 ) , .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_2172 ) , .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_2173 ) , .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_2174 ) , @@ -131814,13 +135380,13 @@ sb_1__1_ sb_1__2_ ( .prog_clk_2_S_out ( prog_clk_2_wires[3] ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_2178 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_2179 ) , - .prog_clk_3_W_in ( p2150 ) , .prog_clk_3_E_in ( p238 ) , - .prog_clk_3_S_in ( p6 ) , .prog_clk_3_N_in ( p236 ) , + .prog_clk_3_W_in ( p1393 ) , .prog_clk_3_E_in ( p348 ) , + .prog_clk_3_S_in ( p545 ) , .prog_clk_3_N_in ( p114 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_2180 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_2181 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_2182 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_2183 ) , .clk_1_N_in ( p1220 ) , - .clk_1_S_in ( p106 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_2184 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_2183 ) , .clk_1_N_in ( p1504 ) , + .clk_1_S_in ( p1097 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_2184 ) , .clk_1_W_out ( SYNOPSYS_UNCONNECTED_2185 ) , .clk_2_N_in ( SYNOPSYS_UNCONNECTED_2186 ) , .clk_2_E_in ( clk_2_wires[1] ) , @@ -131829,8 +135395,8 @@ sb_1__1_ sb_1__2_ ( .clk_2_W_out ( SYNOPSYS_UNCONNECTED_2189 ) , .clk_2_S_out ( clk_2_wires[3] ) , .clk_2_N_out ( SYNOPSYS_UNCONNECTED_2190 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_2191 ) , .clk_3_W_in ( p2150 ) , - .clk_3_E_in ( p810 ) , .clk_3_S_in ( p2867 ) , .clk_3_N_in ( p625 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_2191 ) , .clk_3_W_in ( p1393 ) , + .clk_3_E_in ( p1748 ) , .clk_3_S_in ( p2876 ) , .clk_3_N_in ( p507 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_2192 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_2193 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_2194 ) , @@ -131878,27 +135444,27 @@ sb_1__1_ sb_1__3_ ( .chanx_right_out ( sb_1__1__2_chanx_right_out ) , .chany_bottom_out ( sb_1__1__2_chany_bottom_out ) , .chanx_left_out ( sb_1__1__2_chanx_left_out ) , - .ccff_tail ( sb_1__1__2_ccff_tail ) , .Test_en_S_in ( p3357 ) , + .ccff_tail ( sb_1__1__2_ccff_tail ) , .Test_en_S_in ( p1444 ) , .Test_en_N_out ( SYNOPSYS_UNCONNECTED_2197 ) , .pReset_S_in ( SYNOPSYS_UNCONNECTED_2198 ) , .pReset_E_in ( pResetWires[164] ) , .pReset_W_in ( SYNOPSYS_UNCONNECTED_2199 ) , .pReset_N_out ( pResetWires[163] ) , .pReset_W_out ( pResetWires[160] ) , - .pReset_E_out ( SYNOPSYS_UNCONNECTED_2200 ) , .Reset_S_in ( p3408 ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_2200 ) , .Reset_S_in ( p1444 ) , .Reset_N_out ( SYNOPSYS_UNCONNECTED_2201 ) , .prog_clk_0_N_in ( prog_clk_0_wires[18] ) , .prog_clk_1_N_in ( prog_clk_2_wires[11] ) , .prog_clk_1_S_in ( SYNOPSYS_UNCONNECTED_2202 ) , .prog_clk_1_E_out ( prog_clk_1_wires[8] ) , - .prog_clk_1_W_out ( prog_clk_1_wires[9] ) , .prog_clk_2_N_in ( p3466 ) , - .prog_clk_2_E_in ( p720 ) , .prog_clk_2_S_in ( p140 ) , - .prog_clk_2_W_in ( p264 ) , + .prog_clk_1_W_out ( prog_clk_1_wires[9] ) , .prog_clk_2_N_in ( p3553 ) , + .prog_clk_2_E_in ( p665 ) , .prog_clk_2_S_in ( p657 ) , + .prog_clk_2_W_in ( p884 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_2203 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_2204 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_2205 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_2206 ) , - .prog_clk_3_W_in ( p2239 ) , .prog_clk_3_E_in ( p279 ) , - .prog_clk_3_S_in ( p808 ) , .prog_clk_3_N_in ( p3461 ) , + .prog_clk_3_W_in ( p3016 ) , .prog_clk_3_E_in ( p627 ) , + .prog_clk_3_S_in ( p1233 ) , .prog_clk_3_N_in ( p3547 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_2207 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_2208 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_2209 ) , @@ -131906,12 +135472,12 @@ sb_1__1_ sb_1__3_ ( .clk_1_N_in ( clk_2_wires[11] ) , .clk_1_S_in ( SYNOPSYS_UNCONNECTED_2211 ) , .clk_1_E_out ( clk_1_wires[8] ) , .clk_1_W_out ( clk_1_wires[9] ) , - .clk_2_N_in ( p3358 ) , .clk_2_E_in ( p984 ) , .clk_2_S_in ( p3391 ) , - .clk_2_W_in ( p2043 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_2212 ) , + .clk_2_N_in ( p3270 ) , .clk_2_E_in ( p86 ) , .clk_2_S_in ( p1148 ) , + .clk_2_W_in ( p2902 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_2212 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_2213 ) , .clk_2_N_out ( SYNOPSYS_UNCONNECTED_2214 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_2215 ) , .clk_3_W_in ( p2239 ) , - .clk_3_E_in ( p796 ) , .clk_3_S_in ( p384 ) , .clk_3_N_in ( p3354 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_2215 ) , .clk_3_W_in ( p2543 ) , + .clk_3_E_in ( p1069 ) , .clk_3_S_in ( p286 ) , .clk_3_N_in ( p3176 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_2216 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_2217 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_2218 ) , @@ -131959,16 +135525,16 @@ sb_1__1_ sb_1__4_ ( .chanx_right_out ( sb_1__1__3_chanx_right_out ) , .chany_bottom_out ( sb_1__1__3_chany_bottom_out ) , .chanx_left_out ( sb_1__1__3_chanx_left_out ) , - .ccff_tail ( sb_1__1__3_ccff_tail ) , .Test_en_S_in ( p2972 ) , + .ccff_tail ( sb_1__1__3_ccff_tail ) , .Test_en_S_in ( p1966 ) , .Test_en_N_out ( SYNOPSYS_UNCONNECTED_2221 ) , .pReset_S_in ( SYNOPSYS_UNCONNECTED_2222 ) , .pReset_E_in ( pResetWires[213] ) , .pReset_W_in ( SYNOPSYS_UNCONNECTED_2223 ) , .pReset_N_out ( pResetWires[212] ) , .pReset_W_out ( pResetWires[209] ) , - .pReset_E_out ( SYNOPSYS_UNCONNECTED_2224 ) , .Reset_S_in ( p2972 ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_2224 ) , .Reset_S_in ( p1966 ) , .Reset_N_out ( SYNOPSYS_UNCONNECTED_2225 ) , - .prog_clk_0_N_in ( prog_clk_0_wires[23] ) , .prog_clk_1_N_in ( p1431 ) , - .prog_clk_1_S_in ( p222 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[23] ) , .prog_clk_1_N_in ( p1908 ) , + .prog_clk_1_S_in ( p177 ) , .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_2226 ) , .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_2227 ) , .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_2228 ) , @@ -131979,13 +135545,13 @@ sb_1__1_ sb_1__4_ ( .prog_clk_2_S_out ( prog_clk_2_wires[10] ) , .prog_clk_2_N_out ( prog_clk_2_wires[8] ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_2232 ) , - .prog_clk_3_W_in ( p2227 ) , .prog_clk_3_E_in ( p1192 ) , - .prog_clk_3_S_in ( p590 ) , .prog_clk_3_N_in ( p1671 ) , + .prog_clk_3_W_in ( p1971 ) , .prog_clk_3_E_in ( p855 ) , + .prog_clk_3_S_in ( p868 ) , .prog_clk_3_N_in ( p2089 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_2233 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_2234 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_2235 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_2236 ) , .clk_1_N_in ( p1431 ) , - .clk_1_S_in ( p498 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_2237 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_2236 ) , .clk_1_N_in ( p1908 ) , + .clk_1_S_in ( p1063 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_2237 ) , .clk_1_W_out ( SYNOPSYS_UNCONNECTED_2238 ) , .clk_2_N_in ( SYNOPSYS_UNCONNECTED_2239 ) , .clk_2_E_in ( clk_2_wires[6] ) , @@ -131993,8 +135559,8 @@ sb_1__1_ sb_1__4_ ( .clk_2_W_in ( SYNOPSYS_UNCONNECTED_2241 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_2242 ) , .clk_2_S_out ( clk_2_wires[10] ) , .clk_2_N_out ( clk_2_wires[8] ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_2243 ) , .clk_3_W_in ( p2227 ) , - .clk_3_E_in ( p1676 ) , .clk_3_S_in ( p2883 ) , .clk_3_N_in ( p353 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_2243 ) , .clk_3_W_in ( p1971 ) , + .clk_3_E_in ( p136 ) , .clk_3_S_in ( p1738 ) , .clk_3_N_in ( p1783 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_2244 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_2245 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_2246 ) , @@ -132042,40 +135608,40 @@ sb_1__1_ sb_1__5_ ( .chanx_right_out ( sb_1__1__4_chanx_right_out ) , .chany_bottom_out ( sb_1__1__4_chany_bottom_out ) , .chanx_left_out ( sb_1__1__4_chanx_left_out ) , - .ccff_tail ( sb_1__1__4_ccff_tail ) , .Test_en_S_in ( p2645 ) , + .ccff_tail ( sb_1__1__4_ccff_tail ) , .Test_en_S_in ( p1909 ) , .Test_en_N_out ( SYNOPSYS_UNCONNECTED_2249 ) , .pReset_S_in ( SYNOPSYS_UNCONNECTED_2250 ) , .pReset_E_in ( pResetWires[262] ) , .pReset_W_in ( SYNOPSYS_UNCONNECTED_2251 ) , .pReset_N_out ( pResetWires[261] ) , .pReset_W_out ( pResetWires[258] ) , - .pReset_E_out ( SYNOPSYS_UNCONNECTED_2252 ) , .Reset_S_in ( p3168 ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_2252 ) , .Reset_S_in ( p1909 ) , .Reset_N_out ( SYNOPSYS_UNCONNECTED_2253 ) , .prog_clk_0_N_in ( prog_clk_0_wires[28] ) , .prog_clk_1_N_in ( SYNOPSYS_UNCONNECTED_2254 ) , .prog_clk_1_S_in ( prog_clk_2_wires[9] ) , .prog_clk_1_E_out ( prog_clk_1_wires[15] ) , - .prog_clk_1_W_out ( prog_clk_1_wires[16] ) , .prog_clk_2_N_in ( p3432 ) , - .prog_clk_2_E_in ( p131 ) , .prog_clk_2_S_in ( p619 ) , - .prog_clk_2_W_in ( p990 ) , + .prog_clk_1_W_out ( prog_clk_1_wires[16] ) , .prog_clk_2_N_in ( p3577 ) , + .prog_clk_2_E_in ( p534 ) , .prog_clk_2_S_in ( p748 ) , + .prog_clk_2_W_in ( p516 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_2255 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_2256 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_2257 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_2258 ) , - .prog_clk_3_W_in ( p2226 ) , .prog_clk_3_E_in ( p1251 ) , - .prog_clk_3_S_in ( p1138 ) , .prog_clk_3_N_in ( p3418 ) , + .prog_clk_3_W_in ( p2793 ) , .prog_clk_3_E_in ( p210 ) , + .prog_clk_3_S_in ( p1120 ) , .prog_clk_3_N_in ( p3564 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_2259 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_2260 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_2261 ) , .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_2262 ) , .clk_1_N_in ( SYNOPSYS_UNCONNECTED_2263 ) , .clk_1_S_in ( clk_2_wires[9] ) , .clk_1_E_out ( clk_1_wires[15] ) , - .clk_1_W_out ( clk_1_wires[16] ) , .clk_2_N_in ( p3359 ) , - .clk_2_E_in ( p786 ) , .clk_2_S_in ( p3131 ) , .clk_2_W_in ( p1971 ) , + .clk_1_W_out ( clk_1_wires[16] ) , .clk_2_N_in ( p3134 ) , + .clk_2_E_in ( p585 ) , .clk_2_S_in ( p669 ) , .clk_2_W_in ( p3174 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_2264 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_2265 ) , .clk_2_N_out ( SYNOPSYS_UNCONNECTED_2266 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_2267 ) , .clk_3_W_in ( p2226 ) , - .clk_3_E_in ( p819 ) , .clk_3_S_in ( p552 ) , .clk_3_N_in ( p3351 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_2267 ) , .clk_3_W_in ( p3260 ) , + .clk_3_E_in ( p1062 ) , .clk_3_S_in ( p1697 ) , .clk_3_N_in ( p3091 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_2268 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_2269 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_2270 ) , @@ -132123,38 +135689,38 @@ sb_1__1_ sb_1__6_ ( .chanx_right_out ( sb_1__1__5_chanx_right_out ) , .chany_bottom_out ( sb_1__1__5_chany_bottom_out ) , .chanx_left_out ( sb_1__1__5_chanx_left_out ) , - .ccff_tail ( sb_1__1__5_ccff_tail ) , .Test_en_S_in ( p2476 ) , + .ccff_tail ( sb_1__1__5_ccff_tail ) , .Test_en_S_in ( p1849 ) , .Test_en_N_out ( SYNOPSYS_UNCONNECTED_2273 ) , .pReset_S_in ( SYNOPSYS_UNCONNECTED_2274 ) , .pReset_E_in ( pResetWires[311] ) , .pReset_W_in ( SYNOPSYS_UNCONNECTED_2275 ) , .pReset_N_out ( pResetWires[310] ) , .pReset_W_out ( pResetWires[307] ) , - .pReset_E_out ( SYNOPSYS_UNCONNECTED_2276 ) , .Reset_S_in ( p3453 ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_2276 ) , .Reset_S_in ( p1849 ) , .Reset_N_out ( SYNOPSYS_UNCONNECTED_2277 ) , - .prog_clk_0_N_in ( prog_clk_0_wires[33] ) , .prog_clk_1_N_in ( p1382 ) , - .prog_clk_1_S_in ( p924 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[33] ) , .prog_clk_1_N_in ( p2245 ) , + .prog_clk_1_S_in ( p300 ) , .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_2278 ) , .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_2279 ) , - .prog_clk_2_N_in ( p3467 ) , .prog_clk_2_E_in ( p1064 ) , - .prog_clk_2_S_in ( p1163 ) , .prog_clk_2_W_in ( p78 ) , + .prog_clk_2_N_in ( p1629 ) , .prog_clk_2_E_in ( p787 ) , + .prog_clk_2_S_in ( p23 ) , .prog_clk_2_W_in ( p142 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_2280 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_2281 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_2282 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_2283 ) , - .prog_clk_3_W_in ( p1836 ) , .prog_clk_3_E_in ( p181 ) , - .prog_clk_3_S_in ( p486 ) , .prog_clk_3_N_in ( p3458 ) , + .prog_clk_3_W_in ( p3355 ) , .prog_clk_3_E_in ( p968 ) , + .prog_clk_3_S_in ( p857 ) , .prog_clk_3_N_in ( p781 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_2284 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_2285 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_2286 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_2287 ) , .clk_1_N_in ( p1382 ) , - .clk_1_S_in ( p656 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_2288 ) , - .clk_1_W_out ( SYNOPSYS_UNCONNECTED_2289 ) , .clk_2_N_in ( p3110 ) , - .clk_2_E_in ( p840 ) , .clk_2_S_in ( p3445 ) , .clk_2_W_in ( p1703 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_2287 ) , .clk_1_N_in ( p2245 ) , + .clk_1_S_in ( p998 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_2288 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_2289 ) , .clk_2_N_in ( p3514 ) , + .clk_2_E_in ( p1152 ) , .clk_2_S_in ( p242 ) , .clk_2_W_in ( p3488 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_2290 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_2291 ) , .clk_2_N_out ( SYNOPSYS_UNCONNECTED_2292 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_2293 ) , .clk_3_W_in ( p1836 ) , - .clk_3_E_in ( p861 ) , .clk_3_S_in ( p1465 ) , .clk_3_N_in ( p3017 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_2293 ) , .clk_3_W_in ( p3501 ) , + .clk_3_E_in ( p81 ) , .clk_3_S_in ( p1765 ) , .clk_3_N_in ( p3492 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_2294 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_2295 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_2296 ) , @@ -132202,27 +135768,27 @@ sb_1__1_ sb_1__7_ ( .chanx_right_out ( sb_1__1__6_chanx_right_out ) , .chany_bottom_out ( sb_1__1__6_chany_bottom_out ) , .chanx_left_out ( sb_1__1__6_chanx_left_out ) , - .ccff_tail ( sb_1__1__6_ccff_tail ) , .Test_en_S_in ( p2928 ) , + .ccff_tail ( sb_1__1__6_ccff_tail ) , .Test_en_S_in ( p2195 ) , .Test_en_N_out ( SYNOPSYS_UNCONNECTED_2299 ) , .pReset_S_in ( SYNOPSYS_UNCONNECTED_2300 ) , .pReset_E_in ( pResetWires[360] ) , .pReset_W_in ( SYNOPSYS_UNCONNECTED_2301 ) , .pReset_N_out ( pResetWires[359] ) , .pReset_W_out ( pResetWires[356] ) , - .pReset_E_out ( SYNOPSYS_UNCONNECTED_2302 ) , .Reset_S_in ( p3318 ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_2302 ) , .Reset_S_in ( p2195 ) , .Reset_N_out ( SYNOPSYS_UNCONNECTED_2303 ) , .prog_clk_0_N_in ( prog_clk_0_wires[38] ) , .prog_clk_1_N_in ( prog_clk_2_wires[18] ) , .prog_clk_1_S_in ( SYNOPSYS_UNCONNECTED_2304 ) , .prog_clk_1_E_out ( prog_clk_1_wires[22] ) , - .prog_clk_1_W_out ( prog_clk_1_wires[23] ) , .prog_clk_2_N_in ( p3272 ) , - .prog_clk_2_E_in ( p944 ) , .prog_clk_2_S_in ( p23 ) , - .prog_clk_2_W_in ( p1226 ) , + .prog_clk_1_W_out ( prog_clk_1_wires[23] ) , .prog_clk_2_N_in ( p3408 ) , + .prog_clk_2_E_in ( p694 ) , .prog_clk_2_S_in ( p281 ) , + .prog_clk_2_W_in ( p850 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_2305 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_2306 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_2307 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_2308 ) , - .prog_clk_3_W_in ( p2515 ) , .prog_clk_3_E_in ( p313 ) , - .prog_clk_3_S_in ( p1221 ) , .prog_clk_3_N_in ( p3214 ) , + .prog_clk_3_W_in ( p2587 ) , .prog_clk_3_E_in ( p59 ) , + .prog_clk_3_S_in ( p902 ) , .prog_clk_3_N_in ( p3372 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_2309 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_2310 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_2311 ) , @@ -132230,12 +135796,12 @@ sb_1__1_ sb_1__7_ ( .clk_1_N_in ( clk_2_wires[18] ) , .clk_1_S_in ( SYNOPSYS_UNCONNECTED_2313 ) , .clk_1_E_out ( clk_1_wires[22] ) , .clk_1_W_out ( clk_1_wires[23] ) , - .clk_2_N_in ( p3264 ) , .clk_2_E_in ( p291 ) , .clk_2_S_in ( p3285 ) , - .clk_2_W_in ( p2330 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_2314 ) , + .clk_2_N_in ( p2812 ) , .clk_2_E_in ( p992 ) , .clk_2_S_in ( p479 ) , + .clk_2_W_in ( p3520 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_2314 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_2315 ) , .clk_2_N_out ( SYNOPSYS_UNCONNECTED_2316 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_2317 ) , .clk_3_W_in ( p2515 ) , - .clk_3_E_in ( p925 ) , .clk_3_S_in ( p454 ) , .clk_3_N_in ( p3235 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_2317 ) , .clk_3_W_in ( p3529 ) , + .clk_3_E_in ( p786 ) , .clk_3_S_in ( p2106 ) , .clk_3_N_in ( p2702 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_2318 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_2319 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_2320 ) , @@ -132283,16 +135849,16 @@ sb_1__1_ sb_1__8_ ( .chanx_right_out ( sb_1__1__7_chanx_right_out ) , .chany_bottom_out ( sb_1__1__7_chany_bottom_out ) , .chanx_left_out ( sb_1__1__7_chanx_left_out ) , - .ccff_tail ( sb_1__1__7_ccff_tail ) , .Test_en_S_in ( p3241 ) , + .ccff_tail ( sb_1__1__7_ccff_tail ) , .Test_en_S_in ( p2285 ) , .Test_en_N_out ( SYNOPSYS_UNCONNECTED_2323 ) , .pReset_S_in ( SYNOPSYS_UNCONNECTED_2324 ) , .pReset_E_in ( pResetWires[409] ) , .pReset_W_in ( SYNOPSYS_UNCONNECTED_2325 ) , .pReset_N_out ( pResetWires[408] ) , .pReset_W_out ( pResetWires[405] ) , - .pReset_E_out ( SYNOPSYS_UNCONNECTED_2326 ) , .Reset_S_in ( p3241 ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_2326 ) , .Reset_S_in ( p2285 ) , .Reset_N_out ( SYNOPSYS_UNCONNECTED_2327 ) , - .prog_clk_0_N_in ( prog_clk_0_wires[43] ) , .prog_clk_1_N_in ( p2138 ) , - .prog_clk_1_S_in ( p61 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[43] ) , .prog_clk_1_N_in ( p1503 ) , + .prog_clk_1_S_in ( p62 ) , .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_2328 ) , .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_2329 ) , .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_2330 ) , @@ -132303,13 +135869,13 @@ sb_1__1_ sb_1__8_ ( .prog_clk_2_S_out ( prog_clk_2_wires[17] ) , .prog_clk_2_N_out ( prog_clk_2_wires[15] ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_2334 ) , - .prog_clk_3_W_in ( p1190 ) , .prog_clk_3_E_in ( p234 ) , - .prog_clk_3_S_in ( p290 ) , .prog_clk_3_N_in ( p1647 ) , + .prog_clk_3_W_in ( p1628 ) , .prog_clk_3_E_in ( p187 ) , + .prog_clk_3_S_in ( p49 ) , .prog_clk_3_N_in ( p403 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_2335 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_2336 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_2337 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_2338 ) , .clk_1_N_in ( p2138 ) , - .clk_1_S_in ( p794 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_2339 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_2338 ) , .clk_1_N_in ( p1503 ) , + .clk_1_S_in ( p976 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_2339 ) , .clk_1_W_out ( SYNOPSYS_UNCONNECTED_2340 ) , .clk_2_N_in ( SYNOPSYS_UNCONNECTED_2341 ) , .clk_2_E_in ( clk_2_wires[13] ) , @@ -132317,8 +135883,8 @@ sb_1__1_ sb_1__8_ ( .clk_2_W_in ( SYNOPSYS_UNCONNECTED_2343 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_2344 ) , .clk_2_S_out ( clk_2_wires[17] ) , .clk_2_N_out ( clk_2_wires[15] ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_2345 ) , .clk_3_W_in ( p1190 ) , - .clk_3_E_in ( p1629 ) , .clk_3_S_in ( p3229 ) , .clk_3_N_in ( p1977 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_2345 ) , .clk_3_W_in ( p1628 ) , + .clk_3_E_in ( p825 ) , .clk_3_S_in ( p2093 ) , .clk_3_N_in ( p118 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_2346 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_2347 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_2348 ) , @@ -132366,40 +135932,40 @@ sb_1__1_ sb_1__9_ ( .chanx_right_out ( sb_1__1__8_chanx_right_out ) , .chany_bottom_out ( sb_1__1__8_chany_bottom_out ) , .chanx_left_out ( sb_1__1__8_chanx_left_out ) , - .ccff_tail ( sb_1__1__8_ccff_tail ) , .Test_en_S_in ( p3251 ) , + .ccff_tail ( sb_1__1__8_ccff_tail ) , .Test_en_S_in ( p2297 ) , .Test_en_N_out ( SYNOPSYS_UNCONNECTED_2351 ) , .pReset_S_in ( SYNOPSYS_UNCONNECTED_2352 ) , .pReset_E_in ( pResetWires[458] ) , .pReset_W_in ( SYNOPSYS_UNCONNECTED_2353 ) , .pReset_N_out ( pResetWires[457] ) , .pReset_W_out ( pResetWires[454] ) , - .pReset_E_out ( SYNOPSYS_UNCONNECTED_2354 ) , .Reset_S_in ( p3316 ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_2354 ) , .Reset_S_in ( p2297 ) , .Reset_N_out ( SYNOPSYS_UNCONNECTED_2355 ) , .prog_clk_0_N_in ( prog_clk_0_wires[48] ) , .prog_clk_1_N_in ( SYNOPSYS_UNCONNECTED_2356 ) , .prog_clk_1_S_in ( prog_clk_2_wires[16] ) , .prog_clk_1_E_out ( prog_clk_1_wires[29] ) , - .prog_clk_1_W_out ( prog_clk_1_wires[30] ) , .prog_clk_2_N_in ( p3074 ) , - .prog_clk_2_E_in ( p866 ) , .prog_clk_2_S_in ( p412 ) , - .prog_clk_2_W_in ( p1073 ) , + .prog_clk_1_W_out ( prog_clk_1_wires[30] ) , .prog_clk_2_N_in ( p3425 ) , + .prog_clk_2_E_in ( p422 ) , .prog_clk_2_S_in ( p594 ) , + .prog_clk_2_W_in ( p795 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_2357 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_2358 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_2359 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_2360 ) , - .prog_clk_3_W_in ( p2242 ) , .prog_clk_3_E_in ( p1030 ) , - .prog_clk_3_S_in ( p803 ) , .prog_clk_3_N_in ( p3023 ) , + .prog_clk_3_W_in ( p3004 ) , .prog_clk_3_E_in ( p1022 ) , + .prog_clk_3_S_in ( p573 ) , .prog_clk_3_N_in ( p3370 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_2361 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_2362 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_2363 ) , .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_2364 ) , .clk_1_N_in ( SYNOPSYS_UNCONNECTED_2365 ) , .clk_1_S_in ( clk_2_wires[16] ) , .clk_1_E_out ( clk_1_wires[29] ) , - .clk_1_W_out ( clk_1_wires[30] ) , .clk_2_N_in ( p2652 ) , - .clk_2_E_in ( p51 ) , .clk_2_S_in ( p3277 ) , .clk_2_W_in ( p1984 ) , + .clk_1_W_out ( clk_1_wires[30] ) , .clk_2_N_in ( p3598 ) , + .clk_2_E_in ( p1053 ) , .clk_2_S_in ( p279 ) , .clk_2_W_in ( p3611 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_2366 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_2367 ) , .clk_2_N_out ( SYNOPSYS_UNCONNECTED_2368 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_2369 ) , .clk_3_W_in ( p2242 ) , - .clk_3_E_in ( p671 ) , .clk_3_S_in ( p189 ) , .clk_3_N_in ( p2587 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_2369 ) , .clk_3_W_in ( p3613 ) , + .clk_3_E_in ( p273 ) , .clk_3_S_in ( p2091 ) , .clk_3_N_in ( p3593 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_2370 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_2371 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_2372 ) , @@ -132447,16 +136013,16 @@ sb_1__1_ sb_1__10_ ( .chanx_right_out ( sb_1__1__9_chanx_right_out ) , .chany_bottom_out ( sb_1__1__9_chany_bottom_out ) , .chanx_left_out ( sb_1__1__9_chanx_left_out ) , - .ccff_tail ( sb_1__1__9_ccff_tail ) , .Test_en_S_in ( p2650 ) , + .ccff_tail ( sb_1__1__9_ccff_tail ) , .Test_en_S_in ( p2504 ) , .Test_en_N_out ( SYNOPSYS_UNCONNECTED_2375 ) , .pReset_S_in ( SYNOPSYS_UNCONNECTED_2376 ) , .pReset_E_in ( pResetWires[507] ) , .pReset_W_in ( SYNOPSYS_UNCONNECTED_2377 ) , .pReset_N_out ( pResetWires[506] ) , .pReset_W_out ( pResetWires[503] ) , - .pReset_E_out ( SYNOPSYS_UNCONNECTED_2378 ) , .Reset_S_in ( p2650 ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_2378 ) , .Reset_S_in ( p2504 ) , .Reset_N_out ( SYNOPSYS_UNCONNECTED_2379 ) , - .prog_clk_0_N_in ( prog_clk_0_wires[53] ) , .prog_clk_1_N_in ( p1361 ) , - .prog_clk_1_S_in ( p869 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[53] ) , .prog_clk_1_N_in ( p1542 ) , + .prog_clk_1_S_in ( p880 ) , .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_2380 ) , .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_2381 ) , .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_2382 ) , @@ -132467,13 +136033,13 @@ sb_1__1_ sb_1__10_ ( .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_2386 ) , .prog_clk_2_N_out ( prog_clk_2_wires[22] ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_2387 ) , - .prog_clk_3_W_in ( p1476 ) , .prog_clk_3_E_in ( p348 ) , - .prog_clk_3_S_in ( p136 ) , .prog_clk_3_N_in ( p1637 ) , + .prog_clk_3_W_in ( p2351 ) , .prog_clk_3_E_in ( p799 ) , + .prog_clk_3_S_in ( p78 ) , .prog_clk_3_N_in ( p85 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_2388 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_2389 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_2390 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_2391 ) , .clk_1_N_in ( p1361 ) , - .clk_1_S_in ( p485 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_2392 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_2391 ) , .clk_1_N_in ( p1542 ) , + .clk_1_S_in ( p243 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_2392 ) , .clk_1_W_out ( SYNOPSYS_UNCONNECTED_2393 ) , .clk_2_N_in ( SYNOPSYS_UNCONNECTED_2394 ) , .clk_2_E_in ( clk_2_wires[20] ) , @@ -132482,8 +136048,8 @@ sb_1__1_ sb_1__10_ ( .clk_2_W_out ( SYNOPSYS_UNCONNECTED_2397 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_2398 ) , .clk_2_N_out ( clk_2_wires[22] ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_2399 ) , .clk_3_W_in ( p1476 ) , - .clk_3_E_in ( p795 ) , .clk_3_S_in ( p2577 ) , .clk_3_N_in ( p114 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_2399 ) , .clk_3_W_in ( p2351 ) , + .clk_3_E_in ( p127 ) , .clk_3_S_in ( p2443 ) , .clk_3_N_in ( p483 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_2400 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_2401 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_2402 ) , @@ -132531,40 +136097,40 @@ sb_1__1_ sb_1__11_ ( .chanx_right_out ( sb_1__1__10_chanx_right_out ) , .chany_bottom_out ( sb_1__1__10_chany_bottom_out ) , .chanx_left_out ( sb_1__1__10_chanx_left_out ) , - .ccff_tail ( sb_1__1__10_ccff_tail ) , .Test_en_S_in ( p3162 ) , + .ccff_tail ( sb_1__1__10_ccff_tail ) , .Test_en_S_in ( p2043 ) , .Test_en_N_out ( SYNOPSYS_UNCONNECTED_2405 ) , .pReset_S_in ( SYNOPSYS_UNCONNECTED_2406 ) , .pReset_E_in ( pResetWires[556] ) , .pReset_W_in ( SYNOPSYS_UNCONNECTED_2407 ) , .pReset_N_out ( pResetWires[555] ) , .pReset_W_out ( pResetWires[552] ) , - .pReset_E_out ( SYNOPSYS_UNCONNECTED_2408 ) , .Reset_S_in ( p3162 ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_2408 ) , .Reset_S_in ( p2043 ) , .Reset_N_out ( SYNOPSYS_UNCONNECTED_2409 ) , .prog_clk_0_N_in ( prog_clk_0_wires[58] ) , .prog_clk_1_N_in ( SYNOPSYS_UNCONNECTED_2410 ) , .prog_clk_1_S_in ( prog_clk_2_wires[23] ) , .prog_clk_1_E_out ( prog_clk_1_wires[36] ) , - .prog_clk_1_W_out ( prog_clk_1_wires[37] ) , .prog_clk_2_N_in ( p3456 ) , - .prog_clk_2_E_in ( p774 ) , .prog_clk_2_S_in ( p479 ) , - .prog_clk_2_W_in ( p8 ) , + .prog_clk_1_W_out ( prog_clk_1_wires[37] ) , .prog_clk_2_N_in ( p3585 ) , + .prog_clk_2_E_in ( p800 ) , .prog_clk_2_S_in ( p765 ) , + .prog_clk_2_W_in ( p150 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_2411 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_2412 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_2413 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_2414 ) , - .prog_clk_3_W_in ( p2494 ) , .prog_clk_3_E_in ( p1101 ) , - .prog_clk_3_S_in ( p1308 ) , .prog_clk_3_N_in ( p3444 ) , + .prog_clk_3_W_in ( p2638 ) , .prog_clk_3_E_in ( p8 ) , + .prog_clk_3_S_in ( p1200 ) , .prog_clk_3_N_in ( p3580 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_2415 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_2416 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_2417 ) , .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_2418 ) , .clk_1_N_in ( SYNOPSYS_UNCONNECTED_2419 ) , .clk_1_S_in ( clk_2_wires[23] ) , .clk_1_E_out ( clk_1_wires[36] ) , - .clk_1_W_out ( clk_1_wires[37] ) , .clk_2_N_in ( p2982 ) , - .clk_2_E_in ( p1194 ) , .clk_2_S_in ( p3132 ) , .clk_2_W_in ( p2288 ) , + .clk_1_W_out ( clk_1_wires[37] ) , .clk_2_N_in ( p3415 ) , + .clk_2_E_in ( p542 ) , .clk_2_S_in ( p1176 ) , .clk_2_W_in ( p2707 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_2420 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_2421 ) , .clk_2_N_out ( SYNOPSYS_UNCONNECTED_2422 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_2423 ) , .clk_3_W_in ( p2494 ) , - .clk_3_E_in ( p112 ) , .clk_3_S_in ( p1312 ) , .clk_3_N_in ( p2919 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_2423 ) , .clk_3_W_in ( p2856 ) , + .clk_3_E_in ( p828 ) , .clk_3_S_in ( p1699 ) , .clk_3_N_in ( p3374 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_2424 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_2425 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_2426 ) , @@ -132612,38 +136178,38 @@ sb_1__1_ sb_2__1_ ( .chanx_right_out ( sb_1__1__11_chanx_right_out ) , .chany_bottom_out ( sb_1__1__11_chany_bottom_out ) , .chanx_left_out ( sb_1__1__11_chanx_left_out ) , - .ccff_tail ( sb_1__1__11_ccff_tail ) , .Test_en_S_in ( p2659 ) , + .ccff_tail ( sb_1__1__11_ccff_tail ) , .Test_en_S_in ( p1654 ) , .Test_en_N_out ( SYNOPSYS_UNCONNECTED_2429 ) , .pReset_S_in ( SYNOPSYS_UNCONNECTED_2430 ) , .pReset_E_in ( pResetWires[70] ) , .pReset_W_in ( SYNOPSYS_UNCONNECTED_2431 ) , .pReset_N_out ( pResetWires[69] ) , .pReset_W_out ( pResetWires[67] ) , - .pReset_E_out ( SYNOPSYS_UNCONNECTED_2432 ) , .Reset_S_in ( p3267 ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_2432 ) , .Reset_S_in ( p1654 ) , .Reset_N_out ( SYNOPSYS_UNCONNECTED_2433 ) , - .prog_clk_0_N_in ( prog_clk_0_wires[68] ) , .prog_clk_1_N_in ( p1791 ) , - .prog_clk_1_S_in ( p836 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[68] ) , .prog_clk_1_N_in ( p1582 ) , + .prog_clk_1_S_in ( p60 ) , .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_2434 ) , .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_2435 ) , - .prog_clk_2_N_in ( p2258 ) , .prog_clk_2_E_in ( p877 ) , - .prog_clk_2_S_in ( p442 ) , .prog_clk_2_W_in ( p1214 ) , + .prog_clk_2_N_in ( p3410 ) , .prog_clk_2_E_in ( p290 ) , + .prog_clk_2_S_in ( p227 ) , .prog_clk_2_W_in ( p626 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_2436 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_2437 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_2438 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_2439 ) , - .prog_clk_3_W_in ( p2093 ) , .prog_clk_3_E_in ( p1218 ) , - .prog_clk_3_S_in ( p1124 ) , .prog_clk_3_N_in ( p1998 ) , + .prog_clk_3_W_in ( p2209 ) , .prog_clk_3_E_in ( p1123 ) , + .prog_clk_3_S_in ( p1146 ) , .prog_clk_3_N_in ( p3375 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_2440 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_2441 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_2442 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_2443 ) , .clk_1_N_in ( p1791 ) , - .clk_1_S_in ( p223 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_2444 ) , - .clk_1_W_out ( SYNOPSYS_UNCONNECTED_2445 ) , .clk_2_N_in ( p2702 ) , - .clk_2_E_in ( p129 ) , .clk_2_S_in ( p3209 ) , .clk_2_W_in ( p2036 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_2443 ) , .clk_1_N_in ( p1582 ) , + .clk_1_S_in ( p1101 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_2444 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_2445 ) , .clk_2_N_in ( p3513 ) , + .clk_2_E_in ( p33 ) , .clk_2_S_in ( p1095 ) , .clk_2_W_in ( p3612 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_2446 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_2447 ) , .clk_2_N_out ( SYNOPSYS_UNCONNECTED_2448 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_2449 ) , .clk_3_W_in ( p2093 ) , - .clk_3_E_in ( p634 ) , .clk_3_S_in ( p1082 ) , .clk_3_N_in ( p2555 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_2449 ) , .clk_3_W_in ( p3614 ) , + .clk_3_E_in ( p1079 ) , .clk_3_S_in ( p319 ) , .clk_3_N_in ( p3487 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_2450 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_2451 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_2452 ) , @@ -132691,16 +136257,16 @@ sb_1__1_ sb_2__2_ ( .chanx_right_out ( sb_1__1__12_chanx_right_out ) , .chany_bottom_out ( sb_1__1__12_chany_bottom_out ) , .chanx_left_out ( sb_1__1__12_chanx_left_out ) , - .ccff_tail ( sb_1__1__12_ccff_tail ) , .Test_en_S_in ( p2619 ) , + .ccff_tail ( sb_1__1__12_ccff_tail ) , .Test_en_S_in ( p1316 ) , .Test_en_N_out ( SYNOPSYS_UNCONNECTED_2455 ) , .pReset_S_in ( SYNOPSYS_UNCONNECTED_2456 ) , .pReset_E_in ( pResetWires[119] ) , .pReset_W_in ( SYNOPSYS_UNCONNECTED_2457 ) , .pReset_N_out ( pResetWires[118] ) , .pReset_W_out ( pResetWires[116] ) , - .pReset_E_out ( SYNOPSYS_UNCONNECTED_2458 ) , .Reset_S_in ( p2619 ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_2458 ) , .Reset_S_in ( p1316 ) , .Reset_N_out ( SYNOPSYS_UNCONNECTED_2459 ) , - .prog_clk_0_N_in ( prog_clk_0_wires[71] ) , .prog_clk_1_N_in ( p1941 ) , - .prog_clk_1_S_in ( p314 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[71] ) , .prog_clk_1_N_in ( p2284 ) , + .prog_clk_1_S_in ( p498 ) , .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_2460 ) , .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_2461 ) , .prog_clk_2_N_in ( prog_clk_3_wires[69] ) , @@ -132711,13 +136277,13 @@ sb_1__1_ sb_2__2_ ( .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_2465 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_2466 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_2467 ) , - .prog_clk_3_W_in ( p1796 ) , .prog_clk_3_E_in ( p62 ) , - .prog_clk_3_S_in ( p844 ) , .prog_clk_3_N_in ( p394 ) , + .prog_clk_3_W_in ( p1920 ) , .prog_clk_3_E_in ( p1119 ) , + .prog_clk_3_S_in ( p776 ) , .prog_clk_3_N_in ( p397 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_2468 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_2469 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_2470 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_2471 ) , .clk_1_N_in ( p1941 ) , - .clk_1_S_in ( p870 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_2472 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_2471 ) , .clk_1_N_in ( p2284 ) , + .clk_1_S_in ( p1156 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_2472 ) , .clk_1_W_out ( SYNOPSYS_UNCONNECTED_2473 ) , .clk_2_N_in ( clk_3_wires[69] ) , .clk_2_E_in ( SYNOPSYS_UNCONNECTED_2474 ) , @@ -132726,8 +136292,8 @@ sb_1__1_ sb_2__2_ ( .clk_2_W_out ( clk_2_wires[2] ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_2477 ) , .clk_2_N_out ( SYNOPSYS_UNCONNECTED_2478 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_2479 ) , .clk_3_W_in ( p1796 ) , - .clk_3_E_in ( p838 ) , .clk_3_S_in ( p2581 ) , .clk_3_N_in ( p1630 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_2479 ) , .clk_3_W_in ( p1920 ) , + .clk_3_E_in ( p379 ) , .clk_3_S_in ( p323 ) , .clk_3_N_in ( p2128 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_2480 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_2481 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_2482 ) , @@ -132775,20 +136341,20 @@ sb_1__1_ sb_2__3_ ( .chanx_right_out ( sb_1__1__13_chanx_right_out ) , .chany_bottom_out ( sb_1__1__13_chany_bottom_out ) , .chanx_left_out ( sb_1__1__13_chanx_left_out ) , - .ccff_tail ( sb_1__1__13_ccff_tail ) , .Test_en_S_in ( p2824 ) , + .ccff_tail ( sb_1__1__13_ccff_tail ) , .Test_en_S_in ( p2338 ) , .Test_en_N_out ( SYNOPSYS_UNCONNECTED_2485 ) , .pReset_S_in ( SYNOPSYS_UNCONNECTED_2486 ) , .pReset_E_in ( pResetWires[168] ) , .pReset_W_in ( SYNOPSYS_UNCONNECTED_2487 ) , .pReset_N_out ( pResetWires[167] ) , .pReset_W_out ( pResetWires[165] ) , - .pReset_E_out ( SYNOPSYS_UNCONNECTED_2488 ) , .Reset_S_in ( p3479 ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_2488 ) , .Reset_S_in ( p2338 ) , .Reset_N_out ( SYNOPSYS_UNCONNECTED_2489 ) , - .prog_clk_0_N_in ( prog_clk_0_wires[74] ) , .prog_clk_1_N_in ( p1616 ) , - .prog_clk_1_S_in ( p268 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[74] ) , .prog_clk_1_N_in ( p1227 ) , + .prog_clk_1_S_in ( p1281 ) , .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_2490 ) , .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_2491 ) , - .prog_clk_2_N_in ( p2669 ) , .prog_clk_2_E_in ( p1080 ) , - .prog_clk_2_S_in ( p653 ) , .prog_clk_2_W_in ( p792 ) , + .prog_clk_2_N_in ( p2584 ) , .prog_clk_2_E_in ( p593 ) , + .prog_clk_2_S_in ( p1762 ) , .prog_clk_2_W_in ( p342 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_2492 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_2493 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_2494 ) , @@ -132800,10 +136366,10 @@ sb_1__1_ sb_2__3_ ( .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_2499 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_2500 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_2501 ) , - .prog_clk_3_S_out ( prog_clk_3_wires[68] ) , .clk_1_N_in ( p1616 ) , - .clk_1_S_in ( p871 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_2502 ) , - .clk_1_W_out ( SYNOPSYS_UNCONNECTED_2503 ) , .clk_2_N_in ( p2669 ) , - .clk_2_E_in ( p211 ) , .clk_2_S_in ( p3473 ) , .clk_2_W_in ( p123 ) , + .prog_clk_3_S_out ( prog_clk_3_wires[68] ) , .clk_1_N_in ( p1227 ) , + .clk_1_S_in ( p139 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_2502 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_2503 ) , .clk_2_N_in ( p1392 ) , + .clk_2_E_in ( p818 ) , .clk_2_S_in ( p2064 ) , .clk_2_W_in ( p756 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_2504 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_2505 ) , .clk_2_N_out ( SYNOPSYS_UNCONNECTED_2506 ) , @@ -132859,16 +136425,16 @@ sb_1__1_ sb_2__4_ ( .chanx_right_out ( sb_1__1__14_chanx_right_out ) , .chany_bottom_out ( sb_1__1__14_chany_bottom_out ) , .chanx_left_out ( sb_1__1__14_chanx_left_out ) , - .ccff_tail ( sb_1__1__14_ccff_tail ) , .Test_en_S_in ( p1958 ) , + .ccff_tail ( sb_1__1__14_ccff_tail ) , .Test_en_S_in ( p1850 ) , .Test_en_N_out ( SYNOPSYS_UNCONNECTED_2515 ) , .pReset_S_in ( SYNOPSYS_UNCONNECTED_2516 ) , .pReset_E_in ( pResetWires[217] ) , .pReset_W_in ( SYNOPSYS_UNCONNECTED_2517 ) , .pReset_N_out ( pResetWires[216] ) , .pReset_W_out ( pResetWires[214] ) , - .pReset_E_out ( SYNOPSYS_UNCONNECTED_2518 ) , .Reset_S_in ( p1958 ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_2518 ) , .Reset_S_in ( p1850 ) , .Reset_N_out ( SYNOPSYS_UNCONNECTED_2519 ) , - .prog_clk_0_N_in ( prog_clk_0_wires[77] ) , .prog_clk_1_N_in ( p1358 ) , - .prog_clk_1_S_in ( p629 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[77] ) , .prog_clk_1_N_in ( p1886 ) , + .prog_clk_1_S_in ( p1704 ) , .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_2520 ) , .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_2521 ) , .prog_clk_2_N_in ( prog_clk_3_wires[59] ) , @@ -132886,8 +136452,8 @@ sb_1__1_ sb_2__4_ ( .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_2531 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_2532 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_2533 ) , - .prog_clk_3_S_out ( prog_clk_3_wires[64] ) , .clk_1_N_in ( p1358 ) , - .clk_1_S_in ( p1650 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_2534 ) , + .prog_clk_3_S_out ( prog_clk_3_wires[64] ) , .clk_1_N_in ( p1886 ) , + .clk_1_S_in ( p1171 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_2534 ) , .clk_1_W_out ( SYNOPSYS_UNCONNECTED_2535 ) , .clk_2_N_in ( clk_3_wires[59] ) , .clk_2_E_in ( SYNOPSYS_UNCONNECTED_2536 ) , @@ -132948,20 +136514,20 @@ sb_1__1_ sb_2__5_ ( .chanx_right_out ( sb_1__1__15_chanx_right_out ) , .chany_bottom_out ( sb_1__1__15_chany_bottom_out ) , .chanx_left_out ( sb_1__1__15_chanx_left_out ) , - .ccff_tail ( sb_1__1__15_ccff_tail ) , .Test_en_S_in ( p2666 ) , + .ccff_tail ( sb_1__1__15_ccff_tail ) , .Test_en_S_in ( p2583 ) , .Test_en_N_out ( SYNOPSYS_UNCONNECTED_2549 ) , .pReset_S_in ( SYNOPSYS_UNCONNECTED_2550 ) , .pReset_E_in ( pResetWires[266] ) , .pReset_W_in ( SYNOPSYS_UNCONNECTED_2551 ) , .pReset_N_out ( pResetWires[265] ) , .pReset_W_out ( pResetWires[263] ) , - .pReset_E_out ( SYNOPSYS_UNCONNECTED_2552 ) , .Reset_S_in ( p3176 ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_2552 ) , .Reset_S_in ( p2583 ) , .Reset_N_out ( SYNOPSYS_UNCONNECTED_2553 ) , - .prog_clk_0_N_in ( prog_clk_0_wires[80] ) , .prog_clk_1_N_in ( p1267 ) , - .prog_clk_1_S_in ( p676 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[80] ) , .prog_clk_1_N_in ( p1863 ) , + .prog_clk_1_S_in ( p75 ) , .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_2554 ) , .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_2555 ) , - .prog_clk_2_N_in ( p2849 ) , .prog_clk_2_E_in ( p342 ) , - .prog_clk_2_S_in ( p63 ) , .prog_clk_2_W_in ( p904 ) , + .prog_clk_2_N_in ( p1980 ) , .prog_clk_2_E_in ( p641 ) , + .prog_clk_2_S_in ( p1682 ) , .prog_clk_2_W_in ( p61 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_2556 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_2557 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_2558 ) , @@ -132973,10 +136539,10 @@ sb_1__1_ sb_2__5_ ( .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_2563 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_2564 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_2565 ) , - .prog_clk_3_S_out ( prog_clk_3_wires[58] ) , .clk_1_N_in ( p1267 ) , - .clk_1_S_in ( p315 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_2566 ) , - .clk_1_W_out ( SYNOPSYS_UNCONNECTED_2567 ) , .clk_2_N_in ( p2631 ) , - .clk_2_E_in ( p597 ) , .clk_2_S_in ( p3136 ) , .clk_2_W_in ( p609 ) , + .prog_clk_3_S_out ( prog_clk_3_wires[58] ) , .clk_1_N_in ( p1863 ) , + .clk_1_S_in ( p917 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_2566 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_2567 ) , .clk_2_N_in ( p1980 ) , + .clk_2_E_in ( p480 ) , .clk_2_S_in ( p2400 ) , .clk_2_W_in ( p863 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_2568 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_2569 ) , .clk_2_N_out ( SYNOPSYS_UNCONNECTED_2570 ) , @@ -133032,20 +136598,20 @@ sb_1__1_ sb_2__6_ ( .chanx_right_out ( sb_1__1__16_chanx_right_out ) , .chany_bottom_out ( sb_1__1__16_chany_bottom_out ) , .chanx_left_out ( sb_1__1__16_chanx_left_out ) , - .ccff_tail ( sb_1__1__16_ccff_tail ) , .Test_en_S_in ( p2123 ) , + .ccff_tail ( sb_1__1__16_ccff_tail ) , .Test_en_S_in ( p1969 ) , .Test_en_N_out ( SYNOPSYS_UNCONNECTED_2579 ) , .pReset_S_in ( SYNOPSYS_UNCONNECTED_2580 ) , .pReset_E_in ( pResetWires[315] ) , .pReset_W_in ( SYNOPSYS_UNCONNECTED_2581 ) , .pReset_N_out ( pResetWires[314] ) , .pReset_W_out ( pResetWires[312] ) , - .pReset_E_out ( SYNOPSYS_UNCONNECTED_2582 ) , .Reset_S_in ( p3274 ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_2582 ) , .Reset_S_in ( p1969 ) , .Reset_N_out ( SYNOPSYS_UNCONNECTED_2583 ) , - .prog_clk_0_N_in ( prog_clk_0_wires[83] ) , .prog_clk_1_N_in ( p1725 ) , - .prog_clk_1_S_in ( p139 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[83] ) , .prog_clk_1_N_in ( p1510 ) , + .prog_clk_1_S_in ( p680 ) , .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_2584 ) , .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_2585 ) , - .prog_clk_2_N_in ( p2225 ) , .prog_clk_2_E_in ( p1092 ) , - .prog_clk_2_S_in ( p782 ) , .prog_clk_2_W_in ( p1169 ) , + .prog_clk_2_N_in ( p2240 ) , .prog_clk_2_E_in ( p129 ) , + .prog_clk_2_S_in ( p1778 ) , .prog_clk_2_W_in ( p1037 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_2586 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_2587 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_2588 ) , @@ -133057,10 +136623,10 @@ sb_1__1_ sb_2__6_ ( .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_2593 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_2594 ) , .prog_clk_3_N_out ( prog_clk_3_wires[52] ) , - .prog_clk_3_S_out ( prog_clk_3_wires[54] ) , .clk_1_N_in ( p1725 ) , - .clk_1_S_in ( p594 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_2595 ) , - .clk_1_W_out ( SYNOPSYS_UNCONNECTED_2596 ) , .clk_2_N_in ( p1921 ) , - .clk_2_E_in ( p343 ) , .clk_2_S_in ( p3228 ) , .clk_2_W_in ( p133 ) , + .prog_clk_3_S_out ( prog_clk_3_wires[54] ) , .clk_1_N_in ( p1510 ) , + .clk_1_S_in ( p969 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_2595 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_2596 ) , .clk_2_N_in ( p2283 ) , + .clk_2_E_in ( p981 ) , .clk_2_S_in ( p1672 ) , .clk_2_W_in ( p343 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_2597 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_2598 ) , .clk_2_N_out ( SYNOPSYS_UNCONNECTED_2599 ) , @@ -133116,20 +136682,20 @@ sb_1__1_ sb_2__7_ ( .chanx_right_out ( sb_1__1__17_chanx_right_out ) , .chany_bottom_out ( sb_1__1__17_chany_bottom_out ) , .chanx_left_out ( sb_1__1__17_chanx_left_out ) , - .ccff_tail ( sb_1__1__17_ccff_tail ) , .Test_en_S_in ( p3100 ) , + .ccff_tail ( sb_1__1__17_ccff_tail ) , .Test_en_S_in ( p2001 ) , .Test_en_N_out ( SYNOPSYS_UNCONNECTED_2607 ) , .pReset_S_in ( SYNOPSYS_UNCONNECTED_2608 ) , .pReset_E_in ( pResetWires[364] ) , .pReset_W_in ( SYNOPSYS_UNCONNECTED_2609 ) , .pReset_N_out ( pResetWires[363] ) , .pReset_W_out ( pResetWires[361] ) , - .pReset_E_out ( SYNOPSYS_UNCONNECTED_2610 ) , .Reset_S_in ( p3377 ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_2610 ) , .Reset_S_in ( p2001 ) , .Reset_N_out ( SYNOPSYS_UNCONNECTED_2611 ) , - .prog_clk_0_N_in ( prog_clk_0_wires[86] ) , .prog_clk_1_N_in ( p1932 ) , - .prog_clk_1_S_in ( p241 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[86] ) , .prog_clk_1_N_in ( p1295 ) , + .prog_clk_1_S_in ( p1044 ) , .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_2612 ) , .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_2613 ) , - .prog_clk_2_N_in ( p2145 ) , .prog_clk_2_E_in ( p587 ) , - .prog_clk_2_S_in ( p618 ) , .prog_clk_2_W_in ( p1054 ) , + .prog_clk_2_N_in ( p2230 ) , .prog_clk_2_E_in ( p395 ) , + .prog_clk_2_S_in ( p52 ) , .prog_clk_2_W_in ( p774 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_2614 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_2615 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_2616 ) , @@ -133141,10 +136707,10 @@ sb_1__1_ sb_2__7_ ( .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_2621 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_2622 ) , .prog_clk_3_N_out ( prog_clk_3_wires[56] ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_2623 ) , .clk_1_N_in ( p1932 ) , - .clk_1_S_in ( p403 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_2624 ) , - .clk_1_W_out ( SYNOPSYS_UNCONNECTED_2625 ) , .clk_2_N_in ( p2191 ) , - .clk_2_E_in ( p911 ) , .clk_2_S_in ( p3348 ) , .clk_2_W_in ( p303 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_2623 ) , .clk_1_N_in ( p1295 ) , + .clk_1_S_in ( p260 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_2624 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_2625 ) , .clk_2_N_in ( p1478 ) , + .clk_2_E_in ( p819 ) , .clk_2_S_in ( p1659 ) , .clk_2_W_in ( p332 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_2626 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_2627 ) , .clk_2_N_out ( SYNOPSYS_UNCONNECTED_2628 ) , @@ -133200,16 +136766,16 @@ sb_1__1_ sb_2__8_ ( .chanx_right_out ( sb_1__1__18_chanx_right_out ) , .chany_bottom_out ( sb_1__1__18_chany_bottom_out ) , .chanx_left_out ( sb_1__1__18_chanx_left_out ) , - .ccff_tail ( sb_1__1__18_ccff_tail ) , .Test_en_S_in ( p1571 ) , + .ccff_tail ( sb_1__1__18_ccff_tail ) , .Test_en_S_in ( p1467 ) , .Test_en_N_out ( SYNOPSYS_UNCONNECTED_2637 ) , .pReset_S_in ( SYNOPSYS_UNCONNECTED_2638 ) , .pReset_E_in ( pResetWires[413] ) , .pReset_W_in ( SYNOPSYS_UNCONNECTED_2639 ) , .pReset_N_out ( pResetWires[412] ) , .pReset_W_out ( pResetWires[410] ) , - .pReset_E_out ( SYNOPSYS_UNCONNECTED_2640 ) , .Reset_S_in ( p1571 ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_2640 ) , .Reset_S_in ( p1467 ) , .Reset_N_out ( SYNOPSYS_UNCONNECTED_2641 ) , - .prog_clk_0_N_in ( prog_clk_0_wires[89] ) , .prog_clk_1_N_in ( p1394 ) , - .prog_clk_1_S_in ( p880 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[89] ) , .prog_clk_1_N_in ( p1919 ) , + .prog_clk_1_S_in ( p145 ) , .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_2642 ) , .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_2643 ) , .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_2644 ) , @@ -133227,8 +136793,8 @@ sb_1__1_ sb_2__8_ ( .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_2653 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_2654 ) , .prog_clk_3_N_out ( prog_clk_3_wires[62] ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_2655 ) , .clk_1_N_in ( p1394 ) , - .clk_1_S_in ( p252 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_2656 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_2655 ) , .clk_1_N_in ( p1919 ) , + .clk_1_S_in ( p1039 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_2656 ) , .clk_1_W_out ( SYNOPSYS_UNCONNECTED_2657 ) , .clk_2_N_in ( SYNOPSYS_UNCONNECTED_2658 ) , .clk_2_E_in ( SYNOPSYS_UNCONNECTED_2659 ) , @@ -133289,20 +136855,20 @@ sb_1__1_ sb_2__9_ ( .chanx_right_out ( sb_1__1__19_chanx_right_out ) , .chany_bottom_out ( sb_1__1__19_chany_bottom_out ) , .chanx_left_out ( sb_1__1__19_chanx_left_out ) , - .ccff_tail ( sb_1__1__19_ccff_tail ) , .Test_en_S_in ( p1864 ) , + .ccff_tail ( sb_1__1__19_ccff_tail ) , .Test_en_S_in ( p2525 ) , .Test_en_N_out ( SYNOPSYS_UNCONNECTED_2671 ) , .pReset_S_in ( SYNOPSYS_UNCONNECTED_2672 ) , .pReset_E_in ( pResetWires[462] ) , .pReset_W_in ( SYNOPSYS_UNCONNECTED_2673 ) , .pReset_N_out ( pResetWires[461] ) , .pReset_W_out ( pResetWires[459] ) , - .pReset_E_out ( SYNOPSYS_UNCONNECTED_2674 ) , .Reset_S_in ( p3452 ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_2674 ) , .Reset_S_in ( p2525 ) , .Reset_N_out ( SYNOPSYS_UNCONNECTED_2675 ) , - .prog_clk_0_N_in ( prog_clk_0_wires[92] ) , .prog_clk_1_N_in ( p1873 ) , - .prog_clk_1_S_in ( p912 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[92] ) , .prog_clk_1_N_in ( p1299 ) , + .prog_clk_1_S_in ( p1211 ) , .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_2676 ) , .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_2677 ) , - .prog_clk_2_N_in ( p2193 ) , .prog_clk_2_E_in ( p54 ) , - .prog_clk_2_S_in ( p533 ) , .prog_clk_2_W_in ( p204 ) , + .prog_clk_2_N_in ( p2809 ) , .prog_clk_2_E_in ( p538 ) , + .prog_clk_2_S_in ( p390 ) , .prog_clk_2_W_in ( p453 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_2678 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_2679 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_2680 ) , @@ -133314,10 +136880,10 @@ sb_1__1_ sb_2__9_ ( .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_2685 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_2686 ) , .prog_clk_3_N_out ( prog_clk_3_wires[66] ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_2687 ) , .clk_1_N_in ( p1873 ) , - .clk_1_S_in ( p173 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_2688 ) , - .clk_1_W_out ( SYNOPSYS_UNCONNECTED_2689 ) , .clk_2_N_in ( p2193 ) , - .clk_2_E_in ( p326 ) , .clk_2_S_in ( p3447 ) , .clk_2_W_in ( p1137 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_2687 ) , .clk_1_N_in ( p1299 ) , + .clk_1_S_in ( p214 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_2688 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_2689 ) , .clk_2_N_in ( p1650 ) , + .clk_2_E_in ( p659 ) , .clk_2_S_in ( p2395 ) , .clk_2_W_in ( p134 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_2690 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_2691 ) , .clk_2_N_out ( SYNOPSYS_UNCONNECTED_2692 ) , @@ -133373,16 +136939,16 @@ sb_1__1_ sb_2__10_ ( .chanx_right_out ( sb_1__1__20_chanx_right_out ) , .chany_bottom_out ( sb_1__1__20_chany_bottom_out ) , .chanx_left_out ( sb_1__1__20_chanx_left_out ) , - .ccff_tail ( sb_1__1__20_ccff_tail ) , .Test_en_S_in ( p2943 ) , + .ccff_tail ( sb_1__1__20_ccff_tail ) , .Test_en_S_in ( p2300 ) , .Test_en_N_out ( SYNOPSYS_UNCONNECTED_2701 ) , .pReset_S_in ( SYNOPSYS_UNCONNECTED_2702 ) , .pReset_E_in ( pResetWires[511] ) , .pReset_W_in ( SYNOPSYS_UNCONNECTED_2703 ) , .pReset_N_out ( pResetWires[510] ) , .pReset_W_out ( pResetWires[508] ) , - .pReset_E_out ( SYNOPSYS_UNCONNECTED_2704 ) , .Reset_S_in ( p2959 ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_2704 ) , .Reset_S_in ( p2300 ) , .Reset_N_out ( SYNOPSYS_UNCONNECTED_2705 ) , - .prog_clk_0_N_in ( prog_clk_0_wires[95] ) , .prog_clk_1_N_in ( p1385 ) , - .prog_clk_1_S_in ( p341 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[95] ) , .prog_clk_1_N_in ( p1429 ) , + .prog_clk_1_S_in ( p181 ) , .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_2706 ) , .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_2707 ) , .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_2708 ) , @@ -133393,13 +136959,13 @@ sb_1__1_ sb_2__10_ ( .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_2711 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_2712 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_2713 ) , - .prog_clk_3_W_in ( p1565 ) , .prog_clk_3_E_in ( p190 ) , - .prog_clk_3_S_in ( p1651 ) , .prog_clk_3_N_in ( p15 ) , + .prog_clk_3_W_in ( p1613 ) , .prog_clk_3_E_in ( p543 ) , + .prog_clk_3_S_in ( p246 ) , .prog_clk_3_N_in ( p152 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_2714 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_2715 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_2716 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_2717 ) , .clk_1_N_in ( p1385 ) , - .clk_1_S_in ( p908 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_2718 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_2717 ) , .clk_1_N_in ( p1429 ) , + .clk_1_S_in ( p1080 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_2718 ) , .clk_1_W_out ( SYNOPSYS_UNCONNECTED_2719 ) , .clk_2_N_in ( SYNOPSYS_UNCONNECTED_2720 ) , .clk_2_E_in ( SYNOPSYS_UNCONNECTED_2721 ) , @@ -133408,8 +136974,8 @@ sb_1__1_ sb_2__10_ ( .clk_2_W_out ( clk_2_wires[21] ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_2723 ) , .clk_2_N_out ( SYNOPSYS_UNCONNECTED_2724 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_2725 ) , .clk_3_W_in ( p1565 ) , - .clk_3_E_in ( p273 ) , .clk_3_S_in ( p2897 ) , .clk_3_N_in ( p540 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_2725 ) , .clk_3_W_in ( p1613 ) , + .clk_3_E_in ( p320 ) , .clk_3_S_in ( p2111 ) , .clk_3_N_in ( p677 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_2726 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_2727 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_2728 ) , @@ -133457,38 +137023,38 @@ sb_1__1_ sb_2__11_ ( .chanx_right_out ( sb_1__1__21_chanx_right_out ) , .chany_bottom_out ( sb_1__1__21_chany_bottom_out ) , .chanx_left_out ( sb_1__1__21_chanx_left_out ) , - .ccff_tail ( sb_1__1__21_ccff_tail ) , .Test_en_S_in ( p2625 ) , + .ccff_tail ( sb_1__1__21_ccff_tail ) , .Test_en_S_in ( p1648 ) , .Test_en_N_out ( SYNOPSYS_UNCONNECTED_2731 ) , .pReset_S_in ( SYNOPSYS_UNCONNECTED_2732 ) , .pReset_E_in ( pResetWires[560] ) , .pReset_W_in ( SYNOPSYS_UNCONNECTED_2733 ) , .pReset_N_out ( pResetWires[559] ) , .pReset_W_out ( pResetWires[557] ) , - .pReset_E_out ( SYNOPSYS_UNCONNECTED_2734 ) , .Reset_S_in ( p2625 ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_2734 ) , .Reset_S_in ( p1648 ) , .Reset_N_out ( SYNOPSYS_UNCONNECTED_2735 ) , - .prog_clk_0_N_in ( prog_clk_0_wires[98] ) , .prog_clk_1_N_in ( p2182 ) , - .prog_clk_1_S_in ( p239 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[98] ) , .prog_clk_1_N_in ( p2031 ) , + .prog_clk_1_S_in ( p830 ) , .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_2736 ) , .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_2737 ) , - .prog_clk_2_N_in ( p3356 ) , .prog_clk_2_E_in ( p1333 ) , - .prog_clk_2_S_in ( p1231 ) , .prog_clk_2_W_in ( p1291 ) , + .prog_clk_2_N_in ( p3504 ) , .prog_clk_2_E_in ( p508 ) , + .prog_clk_2_S_in ( p1332 ) , .prog_clk_2_W_in ( p865 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_2738 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_2739 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_2740 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_2741 ) , - .prog_clk_3_W_in ( p2848 ) , .prog_clk_3_E_in ( p145 ) , - .prog_clk_3_S_in ( p102 ) , .prog_clk_3_N_in ( p3345 ) , + .prog_clk_3_W_in ( p2369 ) , .prog_clk_3_E_in ( p158 ) , + .prog_clk_3_S_in ( p196 ) , .prog_clk_3_N_in ( p3477 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_2742 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_2743 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_2744 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_2745 ) , .clk_1_N_in ( p2182 ) , - .clk_1_S_in ( p1130 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_2746 ) , - .clk_1_W_out ( SYNOPSYS_UNCONNECTED_2747 ) , .clk_2_N_in ( p3488 ) , - .clk_2_E_in ( p888 ) , .clk_2_S_in ( p2530 ) , .clk_2_W_in ( p2728 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_2745 ) , .clk_1_N_in ( p2031 ) , + .clk_1_S_in ( p106 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_2746 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_2747 ) , .clk_2_N_in ( p2744 ) , + .clk_2_E_in ( p632 ) , .clk_2_S_in ( p351 ) , .clk_2_W_in ( p3516 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_2748 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_2749 ) , .clk_2_N_out ( SYNOPSYS_UNCONNECTED_2750 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_2751 ) , .clk_3_W_in ( p2848 ) , - .clk_3_E_in ( p971 ) , .clk_3_S_in ( p1246 ) , .clk_3_N_in ( p3484 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_2751 ) , .clk_3_W_in ( p3531 ) , + .clk_3_E_in ( p912 ) , .clk_3_S_in ( p1203 ) , .clk_3_N_in ( p2714 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_2752 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_2753 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_2754 ) , @@ -133536,27 +137102,27 @@ sb_1__1_ sb_3__1_ ( .chanx_right_out ( sb_1__1__22_chanx_right_out ) , .chany_bottom_out ( sb_1__1__22_chany_bottom_out ) , .chanx_left_out ( sb_1__1__22_chanx_left_out ) , - .ccff_tail ( sb_1__1__22_ccff_tail ) , .Test_en_S_in ( p2839 ) , + .ccff_tail ( sb_1__1__22_ccff_tail ) , .Test_en_S_in ( p2249 ) , .Test_en_N_out ( SYNOPSYS_UNCONNECTED_2757 ) , .pReset_S_in ( SYNOPSYS_UNCONNECTED_2758 ) , .pReset_E_in ( pResetWires[74] ) , .pReset_W_in ( SYNOPSYS_UNCONNECTED_2759 ) , .pReset_N_out ( pResetWires[73] ) , .pReset_W_out ( pResetWires[71] ) , - .pReset_E_out ( SYNOPSYS_UNCONNECTED_2760 ) , .Reset_S_in ( p3376 ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_2760 ) , .Reset_S_in ( p2316 ) , .Reset_N_out ( SYNOPSYS_UNCONNECTED_2761 ) , .prog_clk_0_N_in ( prog_clk_0_wires[106] ) , .prog_clk_1_N_in ( prog_clk_2_wires[30] ) , .prog_clk_1_S_in ( SYNOPSYS_UNCONNECTED_2762 ) , .prog_clk_1_E_out ( prog_clk_1_wires[43] ) , - .prog_clk_1_W_out ( prog_clk_1_wires[44] ) , .prog_clk_2_N_in ( p3071 ) , - .prog_clk_2_E_in ( p824 ) , .prog_clk_2_S_in ( p19 ) , - .prog_clk_2_W_in ( p1123 ) , + .prog_clk_1_W_out ( prog_clk_1_wires[44] ) , .prog_clk_2_N_in ( p3403 ) , + .prog_clk_2_E_in ( p155 ) , .prog_clk_2_S_in ( p816 ) , + .prog_clk_2_W_in ( p942 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_2763 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_2764 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_2765 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_2766 ) , - .prog_clk_3_W_in ( p2662 ) , .prog_clk_3_E_in ( p159 ) , - .prog_clk_3_S_in ( p1459 ) , .prog_clk_3_N_in ( p3044 ) , + .prog_clk_3_W_in ( p2756 ) , .prog_clk_3_E_in ( p872 ) , + .prog_clk_3_S_in ( p84 ) , .prog_clk_3_N_in ( p3380 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_2767 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_2768 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_2769 ) , @@ -133564,12 +137130,12 @@ sb_1__1_ sb_3__1_ ( .clk_1_N_in ( clk_2_wires[30] ) , .clk_1_S_in ( SYNOPSYS_UNCONNECTED_2771 ) , .clk_1_E_out ( clk_1_wires[43] ) , .clk_1_W_out ( clk_1_wires[44] ) , - .clk_2_N_in ( p3103 ) , .clk_2_E_in ( p1002 ) , .clk_2_S_in ( p3347 ) , - .clk_2_W_in ( p2590 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_2772 ) , + .clk_2_N_in ( p2027 ) , .clk_2_E_in ( p1190 ) , .clk_2_S_in ( p1150 ) , + .clk_2_W_in ( p3566 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_2772 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_2773 ) , .clk_2_N_out ( SYNOPSYS_UNCONNECTED_2774 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_2775 ) , .clk_3_W_in ( p2662 ) , - .clk_3_E_in ( p598 ) , .clk_3_S_in ( p681 ) , .clk_3_N_in ( p3029 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_2775 ) , .clk_3_W_in ( p3574 ) , + .clk_3_E_in ( p858 ) , .clk_3_S_in ( p2114 ) , .clk_3_N_in ( p1668 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_2776 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_2777 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_2778 ) , @@ -133617,16 +137183,16 @@ sb_1__1_ sb_3__2_ ( .chanx_right_out ( sb_1__1__23_chanx_right_out ) , .chany_bottom_out ( sb_1__1__23_chany_bottom_out ) , .chanx_left_out ( sb_1__1__23_chanx_left_out ) , - .ccff_tail ( sb_1__1__23_ccff_tail ) , .Test_en_S_in ( p2845 ) , + .ccff_tail ( sb_1__1__23_ccff_tail ) , .Test_en_S_in ( p2260 ) , .Test_en_N_out ( SYNOPSYS_UNCONNECTED_2781 ) , .pReset_S_in ( SYNOPSYS_UNCONNECTED_2782 ) , .pReset_E_in ( pResetWires[123] ) , .pReset_W_in ( SYNOPSYS_UNCONNECTED_2783 ) , .pReset_N_out ( pResetWires[122] ) , .pReset_W_out ( pResetWires[120] ) , - .pReset_E_out ( SYNOPSYS_UNCONNECTED_2784 ) , .Reset_S_in ( p2845 ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_2784 ) , .Reset_S_in ( p2260 ) , .Reset_N_out ( SYNOPSYS_UNCONNECTED_2785 ) , - .prog_clk_0_N_in ( prog_clk_0_wires[109] ) , .prog_clk_1_N_in ( p1558 ) , - .prog_clk_1_S_in ( p848 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[109] ) , .prog_clk_1_N_in ( p1872 ) , + .prog_clk_1_S_in ( p919 ) , .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_2786 ) , .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_2787 ) , .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_2788 ) , @@ -133637,13 +137203,13 @@ sb_1__1_ sb_3__2_ ( .prog_clk_2_S_out ( prog_clk_2_wires[29] ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_2792 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_2793 ) , - .prog_clk_3_W_in ( p1518 ) , .prog_clk_3_E_in ( p1026 ) , - .prog_clk_3_S_in ( p855 ) , .prog_clk_3_N_in ( p579 ) , + .prog_clk_3_W_in ( p1387 ) , .prog_clk_3_E_in ( p240 ) , + .prog_clk_3_S_in ( p35 ) , .prog_clk_3_N_in ( p220 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_2794 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_2795 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_2796 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_2797 ) , .clk_1_N_in ( p1558 ) , - .clk_1_S_in ( p81 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_2798 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_2797 ) , .clk_1_N_in ( p1872 ) , + .clk_1_S_in ( p606 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_2798 ) , .clk_1_W_out ( SYNOPSYS_UNCONNECTED_2799 ) , .clk_2_N_in ( SYNOPSYS_UNCONNECTED_2800 ) , .clk_2_E_in ( clk_2_wires[28] ) , @@ -133652,8 +137218,8 @@ sb_1__1_ sb_3__2_ ( .clk_2_W_out ( SYNOPSYS_UNCONNECTED_2803 ) , .clk_2_S_out ( clk_2_wires[29] ) , .clk_2_N_out ( SYNOPSYS_UNCONNECTED_2804 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_2805 ) , .clk_3_W_in ( p1518 ) , - .clk_3_E_in ( p325 ) , .clk_3_S_in ( p2739 ) , .clk_3_N_in ( p410 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_2805 ) , .clk_3_W_in ( p1387 ) , + .clk_3_E_in ( p961 ) , .clk_3_S_in ( p2107 ) , .clk_3_N_in ( p1718 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_2806 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_2807 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_2808 ) , @@ -133701,27 +137267,27 @@ sb_1__1_ sb_3__3_ ( .chanx_right_out ( sb_1__1__24_chanx_right_out ) , .chany_bottom_out ( sb_1__1__24_chany_bottom_out ) , .chanx_left_out ( sb_1__1__24_chanx_left_out ) , - .ccff_tail ( sb_1__1__24_ccff_tail ) , .Test_en_S_in ( p2442 ) , + .ccff_tail ( sb_1__1__24_ccff_tail ) , .Test_en_S_in ( p2346 ) , .Test_en_N_out ( SYNOPSYS_UNCONNECTED_2811 ) , .pReset_S_in ( SYNOPSYS_UNCONNECTED_2812 ) , .pReset_E_in ( pResetWires[172] ) , .pReset_W_in ( SYNOPSYS_UNCONNECTED_2813 ) , .pReset_N_out ( pResetWires[171] ) , .pReset_W_out ( pResetWires[169] ) , - .pReset_E_out ( SYNOPSYS_UNCONNECTED_2814 ) , .Reset_S_in ( p2442 ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_2814 ) , .Reset_S_in ( p2346 ) , .Reset_N_out ( SYNOPSYS_UNCONNECTED_2815 ) , .prog_clk_0_N_in ( prog_clk_0_wires[112] ) , .prog_clk_1_N_in ( prog_clk_2_wires[41] ) , .prog_clk_1_S_in ( SYNOPSYS_UNCONNECTED_2816 ) , .prog_clk_1_E_out ( prog_clk_1_wires[50] ) , - .prog_clk_1_W_out ( prog_clk_1_wires[51] ) , .prog_clk_2_N_in ( p3502 ) , - .prog_clk_2_E_in ( p35 ) , .prog_clk_2_S_in ( p1122 ) , - .prog_clk_2_W_in ( p1132 ) , + .prog_clk_1_W_out ( prog_clk_1_wires[51] ) , .prog_clk_2_N_in ( p3455 ) , + .prog_clk_2_E_in ( p935 ) , .prog_clk_2_S_in ( p361 ) , + .prog_clk_2_W_in ( p179 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_2817 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_2818 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_2819 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_2820 ) , - .prog_clk_3_W_in ( p2779 ) , .prog_clk_3_E_in ( p937 ) , - .prog_clk_3_S_in ( p200 ) , .prog_clk_3_N_in ( p3500 ) , + .prog_clk_3_W_in ( p2621 ) , .prog_clk_3_E_in ( p207 ) , + .prog_clk_3_S_in ( p1278 ) , .prog_clk_3_N_in ( p3444 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_2821 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_2822 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_2823 ) , @@ -133729,12 +137295,12 @@ sb_1__1_ sb_3__3_ ( .clk_1_N_in ( clk_2_wires[41] ) , .clk_1_S_in ( SYNOPSYS_UNCONNECTED_2825 ) , .clk_1_E_out ( clk_1_wires[50] ) , .clk_1_W_out ( clk_1_wires[51] ) , - .clk_2_N_in ( p3061 ) , .clk_2_E_in ( p502 ) , .clk_2_S_in ( p2310 ) , - .clk_2_W_in ( p2745 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_2826 ) , + .clk_2_N_in ( p3407 ) , .clk_2_E_in ( p647 ) , .clk_2_S_in ( p1177 ) , + .clk_2_W_in ( p3067 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_2826 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_2827 ) , .clk_2_N_out ( SYNOPSYS_UNCONNECTED_2828 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_2829 ) , .clk_3_W_in ( p2779 ) , - .clk_3_E_in ( p680 ) , .clk_3_S_in ( p1193 ) , .clk_3_N_in ( p3011 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_2829 ) , .clk_3_W_in ( p3106 ) , + .clk_3_E_in ( p598 ) , .clk_3_S_in ( p2135 ) , .clk_3_N_in ( p3391 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_2830 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_2831 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_2832 ) , @@ -133782,16 +137348,16 @@ sb_1__1_ sb_3__4_ ( .chanx_right_out ( sb_1__1__25_chanx_right_out ) , .chany_bottom_out ( sb_1__1__25_chany_bottom_out ) , .chanx_left_out ( sb_1__1__25_chanx_left_out ) , - .ccff_tail ( sb_1__1__25_ccff_tail ) , .Test_en_S_in ( p2408 ) , + .ccff_tail ( sb_1__1__25_ccff_tail ) , .Test_en_S_in ( p2184 ) , .Test_en_N_out ( SYNOPSYS_UNCONNECTED_2835 ) , .pReset_S_in ( SYNOPSYS_UNCONNECTED_2836 ) , .pReset_E_in ( pResetWires[221] ) , .pReset_W_in ( SYNOPSYS_UNCONNECTED_2837 ) , .pReset_N_out ( pResetWires[220] ) , .pReset_W_out ( pResetWires[218] ) , - .pReset_E_out ( SYNOPSYS_UNCONNECTED_2838 ) , .Reset_S_in ( p2408 ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_2838 ) , .Reset_S_in ( p2184 ) , .Reset_N_out ( SYNOPSYS_UNCONNECTED_2839 ) , - .prog_clk_0_N_in ( prog_clk_0_wires[115] ) , .prog_clk_1_N_in ( p2254 ) , - .prog_clk_1_S_in ( p1010 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[115] ) , .prog_clk_1_N_in ( p1994 ) , + .prog_clk_1_S_in ( p82 ) , .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_2840 ) , .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_2841 ) , .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_2842 ) , @@ -133802,13 +137368,13 @@ sb_1__1_ sb_3__4_ ( .prog_clk_2_S_out ( prog_clk_2_wires[40] ) , .prog_clk_2_N_out ( prog_clk_2_wires[38] ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_2846 ) , - .prog_clk_3_W_in ( p1613 ) , .prog_clk_3_E_in ( p778 ) , - .prog_clk_3_S_in ( p475 ) , .prog_clk_3_N_in ( p2026 ) , + .prog_clk_3_W_in ( p2202 ) , .prog_clk_3_E_in ( p189 ) , + .prog_clk_3_S_in ( p625 ) , .prog_clk_3_N_in ( p1032 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_2847 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_2848 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_2849 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_2850 ) , .clk_1_N_in ( p2254 ) , - .clk_1_S_in ( p116 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_2851 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_2850 ) , .clk_1_N_in ( p1994 ) , + .clk_1_S_in ( p1259 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_2851 ) , .clk_1_W_out ( SYNOPSYS_UNCONNECTED_2852 ) , .clk_2_N_in ( SYNOPSYS_UNCONNECTED_2853 ) , .clk_2_E_in ( clk_2_wires[37] ) , @@ -133816,8 +137382,8 @@ sb_1__1_ sb_3__4_ ( .clk_2_W_in ( SYNOPSYS_UNCONNECTED_2855 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_2856 ) , .clk_2_S_out ( clk_2_wires[40] ) , .clk_2_N_out ( clk_2_wires[38] ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_2857 ) , .clk_3_W_in ( p1613 ) , - .clk_3_E_in ( p1624 ) , .clk_3_S_in ( p2337 ) , .clk_3_N_in ( p1991 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_2857 ) , .clk_3_W_in ( p2202 ) , + .clk_3_E_in ( p1753 ) , .clk_3_S_in ( p2072 ) , .clk_3_N_in ( p1689 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_2858 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_2859 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_2860 ) , @@ -133865,40 +137431,40 @@ sb_1__1_ sb_3__5_ ( .chanx_right_out ( sb_1__1__26_chanx_right_out ) , .chany_bottom_out ( sb_1__1__26_chany_bottom_out ) , .chanx_left_out ( sb_1__1__26_chanx_left_out ) , - .ccff_tail ( sb_1__1__26_ccff_tail ) , .Test_en_S_in ( p2420 ) , + .ccff_tail ( sb_1__1__26_ccff_tail ) , .Test_en_S_in ( p2234 ) , .Test_en_N_out ( SYNOPSYS_UNCONNECTED_2863 ) , .pReset_S_in ( SYNOPSYS_UNCONNECTED_2864 ) , .pReset_E_in ( pResetWires[270] ) , .pReset_W_in ( SYNOPSYS_UNCONNECTED_2865 ) , .pReset_N_out ( pResetWires[269] ) , .pReset_W_out ( pResetWires[267] ) , - .pReset_E_out ( SYNOPSYS_UNCONNECTED_2866 ) , .Reset_S_in ( p3332 ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_2866 ) , .Reset_S_in ( p2234 ) , .Reset_N_out ( SYNOPSYS_UNCONNECTED_2867 ) , .prog_clk_0_N_in ( prog_clk_0_wires[118] ) , .prog_clk_1_N_in ( SYNOPSYS_UNCONNECTED_2868 ) , .prog_clk_1_S_in ( prog_clk_2_wires[39] ) , .prog_clk_1_E_out ( prog_clk_1_wires[57] ) , - .prog_clk_1_W_out ( prog_clk_1_wires[58] ) , .prog_clk_2_N_in ( p3406 ) , - .prog_clk_2_E_in ( p651 ) , .prog_clk_2_S_in ( p711 ) , - .prog_clk_2_W_in ( p495 ) , + .prog_clk_1_W_out ( prog_clk_1_wires[58] ) , .prog_clk_2_N_in ( p3161 ) , + .prog_clk_2_E_in ( p228 ) , .prog_clk_2_S_in ( p558 ) , + .prog_clk_2_W_in ( p949 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_2869 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_2870 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_2871 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_2872 ) , - .prog_clk_3_W_in ( p2783 ) , .prog_clk_3_E_in ( p1161 ) , - .prog_clk_3_S_in ( p1336 ) , .prog_clk_3_N_in ( p3379 ) , + .prog_clk_3_W_in ( p3027 ) , .prog_clk_3_E_in ( p685 ) , + .prog_clk_3_S_in ( p1264 ) , .prog_clk_3_N_in ( p3061 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_2873 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_2874 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_2875 ) , .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_2876 ) , .clk_1_N_in ( SYNOPSYS_UNCONNECTED_2877 ) , .clk_1_S_in ( clk_2_wires[39] ) , .clk_1_E_out ( clk_1_wires[57] ) , - .clk_1_W_out ( clk_1_wires[58] ) , .clk_2_N_in ( p1574 ) , - .clk_2_E_in ( p110 ) , .clk_2_S_in ( p3296 ) , .clk_2_W_in ( p2733 ) , + .clk_1_W_out ( clk_1_wires[58] ) , .clk_2_N_in ( p3102 ) , + .clk_2_E_in ( p562 ) , .clk_2_S_in ( p955 ) , .clk_2_W_in ( p3308 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_2878 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_2879 ) , .clk_2_N_out ( SYNOPSYS_UNCONNECTED_2880 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_2881 ) , .clk_3_W_in ( p2783 ) , - .clk_3_E_in ( p503 ) , .clk_3_S_in ( p1238 ) , .clk_3_N_in ( p367 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_2881 ) , .clk_3_W_in ( p3328 ) , + .clk_3_E_in ( p1198 ) , .clk_3_S_in ( p2077 ) , .clk_3_N_in ( p3069 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_2882 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_2883 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_2884 ) , @@ -133946,20 +137512,20 @@ sb_1__1_ sb_3__6_ ( .chanx_right_out ( sb_1__1__27_chanx_right_out ) , .chany_bottom_out ( sb_1__1__27_chany_bottom_out ) , .chanx_left_out ( sb_1__1__27_chanx_left_out ) , - .ccff_tail ( sb_1__1__27_ccff_tail ) , .Test_en_S_in ( p3097 ) , + .ccff_tail ( sb_1__1__27_ccff_tail ) , .Test_en_S_in ( p2622 ) , .Test_en_N_out ( SYNOPSYS_UNCONNECTED_2887 ) , .pReset_S_in ( SYNOPSYS_UNCONNECTED_2888 ) , .pReset_E_in ( pResetWires[319] ) , .pReset_W_in ( SYNOPSYS_UNCONNECTED_2889 ) , .pReset_N_out ( pResetWires[318] ) , .pReset_W_out ( pResetWires[316] ) , - .pReset_E_out ( SYNOPSYS_UNCONNECTED_2890 ) , .Reset_S_in ( p3429 ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_2890 ) , .Reset_S_in ( p2622 ) , .Reset_N_out ( SYNOPSYS_UNCONNECTED_2891 ) , - .prog_clk_0_N_in ( prog_clk_0_wires[121] ) , .prog_clk_1_N_in ( p1498 ) , - .prog_clk_1_S_in ( p1022 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[121] ) , .prog_clk_1_N_in ( p1652 ) , + .prog_clk_1_S_in ( p958 ) , .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_2892 ) , .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_2893 ) , - .prog_clk_2_N_in ( p1942 ) , .prog_clk_2_E_in ( p30 ) , - .prog_clk_2_S_in ( p364 ) , .prog_clk_2_W_in ( p1222 ) , + .prog_clk_2_N_in ( p2628 ) , .prog_clk_2_E_in ( p297 ) , + .prog_clk_2_S_in ( p404 ) , .prog_clk_2_W_in ( p954 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_2894 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_2895 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_2896 ) , @@ -133971,10 +137537,10 @@ sb_1__1_ sb_3__6_ ( .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_2901 ) , .prog_clk_3_W_out ( prog_clk_3_wires[50] ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_2902 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_2903 ) , .clk_1_N_in ( p1498 ) , - .clk_1_S_in ( p34 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_2904 ) , - .clk_1_W_out ( SYNOPSYS_UNCONNECTED_2905 ) , .clk_2_N_in ( p1942 ) , - .clk_2_E_in ( p1144 ) , .clk_2_S_in ( p3416 ) , .clk_2_W_in ( p338 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_2903 ) , .clk_1_N_in ( p1652 ) , + .clk_1_S_in ( p119 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_2904 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_2905 ) , .clk_2_N_in ( p2317 ) , + .clk_2_E_in ( p205 ) , .clk_2_S_in ( p2449 ) , .clk_2_W_in ( p413 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_2906 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_2907 ) , .clk_2_N_out ( SYNOPSYS_UNCONNECTED_2908 ) , @@ -134030,27 +137596,27 @@ sb_1__1_ sb_3__7_ ( .chanx_right_out ( sb_1__1__28_chanx_right_out ) , .chany_bottom_out ( sb_1__1__28_chany_bottom_out ) , .chanx_left_out ( sb_1__1__28_chanx_left_out ) , - .ccff_tail ( sb_1__1__28_ccff_tail ) , .Test_en_S_in ( p2409 ) , + .ccff_tail ( sb_1__1__28_ccff_tail ) , .Test_en_S_in ( p1973 ) , .Test_en_N_out ( SYNOPSYS_UNCONNECTED_2917 ) , .pReset_S_in ( SYNOPSYS_UNCONNECTED_2918 ) , .pReset_E_in ( pResetWires[368] ) , .pReset_W_in ( SYNOPSYS_UNCONNECTED_2919 ) , .pReset_N_out ( pResetWires[367] ) , .pReset_W_out ( pResetWires[365] ) , - .pReset_E_out ( SYNOPSYS_UNCONNECTED_2920 ) , .Reset_S_in ( p2409 ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_2920 ) , .Reset_S_in ( p1973 ) , .Reset_N_out ( SYNOPSYS_UNCONNECTED_2921 ) , .prog_clk_0_N_in ( prog_clk_0_wires[124] ) , .prog_clk_1_N_in ( prog_clk_2_wires[54] ) , .prog_clk_1_S_in ( SYNOPSYS_UNCONNECTED_2922 ) , .prog_clk_1_E_out ( prog_clk_1_wires[64] ) , - .prog_clk_1_W_out ( prog_clk_1_wires[65] ) , .prog_clk_2_N_in ( p2942 ) , - .prog_clk_2_E_in ( p126 ) , .prog_clk_2_S_in ( p700 ) , - .prog_clk_2_W_in ( p1275 ) , + .prog_clk_1_W_out ( prog_clk_1_wires[65] ) , .prog_clk_2_N_in ( p2555 ) , + .prog_clk_2_E_in ( p128 ) , .prog_clk_2_S_in ( p971 ) , + .prog_clk_2_W_in ( p299 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_2923 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_2924 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_2925 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_2926 ) , - .prog_clk_3_W_in ( p3245 ) , .prog_clk_3_E_in ( p1254 ) , - .prog_clk_3_S_in ( p481 ) , .prog_clk_3_N_in ( p2895 ) , + .prog_clk_3_W_in ( p2579 ) , .prog_clk_3_E_in ( p719 ) , + .prog_clk_3_S_in ( p131 ) , .prog_clk_3_N_in ( p2437 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_2927 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_2928 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_2929 ) , @@ -134058,12 +137624,12 @@ sb_1__1_ sb_3__7_ ( .clk_1_N_in ( clk_2_wires[54] ) , .clk_1_S_in ( SYNOPSYS_UNCONNECTED_2931 ) , .clk_1_E_out ( clk_1_wires[64] ) , .clk_1_W_out ( clk_1_wires[65] ) , - .clk_2_N_in ( p2818 ) , .clk_2_E_in ( p1045 ) , .clk_2_S_in ( p2311 ) , - .clk_2_W_in ( p3224 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_2932 ) , + .clk_2_N_in ( p2973 ) , .clk_2_E_in ( p34 ) , .clk_2_S_in ( p1262 ) , + .clk_2_W_in ( p3368 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_2932 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_2933 ) , .clk_2_N_out ( SYNOPSYS_UNCONNECTED_2934 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_2935 ) , .clk_3_W_in ( p3261 ) , - .clk_3_E_in ( p1036 ) , .clk_3_S_in ( p433 ) , .clk_3_N_in ( p2764 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_2935 ) , .clk_3_W_in ( p3419 ) , + .clk_3_E_in ( p1081 ) , .clk_3_S_in ( p1784 ) , .clk_3_N_in ( p2871 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_2936 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_2937 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_2938 ) , @@ -134111,16 +137677,16 @@ sb_1__1_ sb_3__8_ ( .chanx_right_out ( sb_1__1__29_chanx_right_out ) , .chany_bottom_out ( sb_1__1__29_chany_bottom_out ) , .chanx_left_out ( sb_1__1__29_chanx_left_out ) , - .ccff_tail ( sb_1__1__29_ccff_tail ) , .Test_en_S_in ( p2833 ) , + .ccff_tail ( sb_1__1__29_ccff_tail ) , .Test_en_S_in ( p2041 ) , .Test_en_N_out ( SYNOPSYS_UNCONNECTED_2941 ) , .pReset_S_in ( SYNOPSYS_UNCONNECTED_2942 ) , .pReset_E_in ( pResetWires[417] ) , .pReset_W_in ( SYNOPSYS_UNCONNECTED_2943 ) , .pReset_N_out ( pResetWires[416] ) , .pReset_W_out ( pResetWires[414] ) , - .pReset_E_out ( SYNOPSYS_UNCONNECTED_2944 ) , .Reset_S_in ( p2833 ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_2944 ) , .Reset_S_in ( p2041 ) , .Reset_N_out ( SYNOPSYS_UNCONNECTED_2945 ) , - .prog_clk_0_N_in ( prog_clk_0_wires[127] ) , .prog_clk_1_N_in ( p1908 ) , - .prog_clk_1_S_in ( p287 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[127] ) , .prog_clk_1_N_in ( p1554 ) , + .prog_clk_1_S_in ( p442 ) , .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_2946 ) , .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_2947 ) , .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_2948 ) , @@ -134131,13 +137697,13 @@ sb_1__1_ sb_3__8_ ( .prog_clk_2_S_out ( prog_clk_2_wires[53] ) , .prog_clk_2_N_out ( prog_clk_2_wires[51] ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_2952 ) , - .prog_clk_3_W_in ( p1477 ) , .prog_clk_3_E_in ( p154 ) , - .prog_clk_3_S_in ( p56 ) , .prog_clk_3_N_in ( p1727 ) , + .prog_clk_3_W_in ( p1489 ) , .prog_clk_3_E_in ( p502 ) , + .prog_clk_3_S_in ( p112 ) , .prog_clk_3_N_in ( p1678 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_2953 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_2954 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_2955 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_2956 ) , .clk_1_N_in ( p1908 ) , - .clk_1_S_in ( p1084 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_2957 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_2956 ) , .clk_1_N_in ( p1554 ) , + .clk_1_S_in ( p581 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_2957 ) , .clk_1_W_out ( SYNOPSYS_UNCONNECTED_2958 ) , .clk_2_N_in ( SYNOPSYS_UNCONNECTED_2959 ) , .clk_2_E_in ( clk_2_wires[50] ) , @@ -134145,8 +137711,8 @@ sb_1__1_ sb_3__8_ ( .clk_2_W_in ( SYNOPSYS_UNCONNECTED_2961 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_2962 ) , .clk_2_S_out ( clk_2_wires[53] ) , .clk_2_N_out ( clk_2_wires[51] ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_2963 ) , .clk_3_W_in ( p1477 ) , - .clk_3_E_in ( p1674 ) , .clk_3_S_in ( p2730 ) , .clk_3_N_in ( p1632 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_2963 ) , .clk_3_W_in ( p1489 ) , + .clk_3_E_in ( p1758 ) , .clk_3_S_in ( p1669 ) , .clk_3_N_in ( p869 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_2964 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_2965 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_2966 ) , @@ -134194,40 +137760,40 @@ sb_1__1_ sb_3__9_ ( .chanx_right_out ( sb_1__1__30_chanx_right_out ) , .chany_bottom_out ( sb_1__1__30_chany_bottom_out ) , .chanx_left_out ( sb_1__1__30_chanx_left_out ) , - .ccff_tail ( sb_1__1__30_ccff_tail ) , .Test_en_S_in ( p3188 ) , + .ccff_tail ( sb_1__1__30_ccff_tail ) , .Test_en_S_in ( p2312 ) , .Test_en_N_out ( SYNOPSYS_UNCONNECTED_2969 ) , .pReset_S_in ( SYNOPSYS_UNCONNECTED_2970 ) , .pReset_E_in ( pResetWires[466] ) , .pReset_W_in ( SYNOPSYS_UNCONNECTED_2971 ) , .pReset_N_out ( pResetWires[465] ) , .pReset_W_out ( pResetWires[463] ) , - .pReset_E_out ( SYNOPSYS_UNCONNECTED_2972 ) , .Reset_S_in ( p3409 ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_2972 ) , .Reset_S_in ( p2312 ) , .Reset_N_out ( SYNOPSYS_UNCONNECTED_2973 ) , .prog_clk_0_N_in ( prog_clk_0_wires[130] ) , .prog_clk_1_N_in ( SYNOPSYS_UNCONNECTED_2974 ) , .prog_clk_1_S_in ( prog_clk_2_wires[52] ) , .prog_clk_1_E_out ( prog_clk_1_wires[71] ) , - .prog_clk_1_W_out ( prog_clk_1_wires[72] ) , .prog_clk_2_N_in ( p3503 ) , - .prog_clk_2_E_in ( p788 ) , .prog_clk_2_S_in ( p726 ) , - .prog_clk_2_W_in ( p289 ) , + .prog_clk_1_W_out ( prog_clk_1_wires[72] ) , .prog_clk_2_N_in ( p3498 ) , + .prog_clk_2_E_in ( p494 ) , .prog_clk_2_S_in ( p1085 ) , + .prog_clk_2_W_in ( p876 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_2975 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_2976 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_2977 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_2978 ) , - .prog_clk_3_W_in ( p2504 ) , .prog_clk_3_E_in ( p1223 ) , - .prog_clk_3_S_in ( p1191 ) , .prog_clk_3_N_in ( p3501 ) , + .prog_clk_3_W_in ( p3003 ) , .prog_clk_3_E_in ( p237 ) , + .prog_clk_3_S_in ( p852 ) , .prog_clk_3_N_in ( p3490 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_2979 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_2980 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_2981 ) , .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_2982 ) , .clk_1_N_in ( SYNOPSYS_UNCONNECTED_2983 ) , .clk_1_S_in ( clk_2_wires[52] ) , .clk_1_E_out ( clk_1_wires[71] ) , - .clk_1_W_out ( clk_1_wires[72] ) , .clk_2_N_in ( p3425 ) , - .clk_2_E_in ( p958 ) , .clk_2_S_in ( p3381 ) , .clk_2_W_in ( p2332 ) , + .clk_1_W_out ( clk_1_wires[72] ) , .clk_2_N_in ( p3402 ) , + .clk_2_E_in ( p1125 ) , .clk_2_S_in ( p26 ) , .clk_2_W_in ( p3369 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_2984 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_2985 ) , .clk_2_N_out ( SYNOPSYS_UNCONNECTED_2986 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_2987 ) , .clk_3_W_in ( p2504 ) , - .clk_3_E_in ( p24 ) , .clk_3_S_in ( p1342 ) , .clk_3_N_in ( p3422 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_2987 ) , .clk_3_W_in ( p3411 ) , + .clk_3_E_in ( p607 ) , .clk_3_S_in ( p2124 ) , .clk_3_N_in ( p3386 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_2988 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_2989 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_2990 ) , @@ -134275,16 +137841,16 @@ sb_1__1_ sb_3__10_ ( .chanx_right_out ( sb_1__1__31_chanx_right_out ) , .chany_bottom_out ( sb_1__1__31_chany_bottom_out ) , .chanx_left_out ( sb_1__1__31_chanx_left_out ) , - .ccff_tail ( sb_1__1__31_ccff_tail ) , .Test_en_S_in ( p886 ) , + .ccff_tail ( sb_1__1__31_ccff_tail ) , .Test_en_S_in ( p1398 ) , .Test_en_N_out ( SYNOPSYS_UNCONNECTED_2993 ) , .pReset_S_in ( SYNOPSYS_UNCONNECTED_2994 ) , .pReset_E_in ( pResetWires[515] ) , .pReset_W_in ( SYNOPSYS_UNCONNECTED_2995 ) , .pReset_N_out ( pResetWires[514] ) , .pReset_W_out ( pResetWires[512] ) , - .pReset_E_out ( SYNOPSYS_UNCONNECTED_2996 ) , .Reset_S_in ( p886 ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_2996 ) , .Reset_S_in ( p1398 ) , .Reset_N_out ( SYNOPSYS_UNCONNECTED_2997 ) , - .prog_clk_0_N_in ( prog_clk_0_wires[133] ) , .prog_clk_1_N_in ( p2202 ) , - .prog_clk_1_S_in ( p141 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[133] ) , .prog_clk_1_N_in ( p1491 ) , + .prog_clk_1_S_in ( p1121 ) , .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_2998 ) , .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_2999 ) , .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_3000 ) , @@ -134295,13 +137861,13 @@ sb_1__1_ sb_3__10_ ( .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_3004 ) , .prog_clk_2_N_out ( prog_clk_2_wires[64] ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_3005 ) , - .prog_clk_3_W_in ( p1499 ) , .prog_clk_3_E_in ( p217 ) , - .prog_clk_3_S_in ( p825 ) , .prog_clk_3_N_in ( p2008 ) , + .prog_clk_3_W_in ( p1611 ) , .prog_clk_3_E_in ( p833 ) , + .prog_clk_3_S_in ( p815 ) , .prog_clk_3_N_in ( p445 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_3006 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_3007 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_3008 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_3009 ) , .clk_1_N_in ( p2202 ) , - .clk_1_S_in ( p1145 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_3010 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_3009 ) , .clk_1_N_in ( p1491 ) , + .clk_1_S_in ( p310 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_3010 ) , .clk_1_W_out ( SYNOPSYS_UNCONNECTED_3011 ) , .clk_2_N_in ( SYNOPSYS_UNCONNECTED_3012 ) , .clk_2_E_in ( clk_2_wires[63] ) , @@ -134310,8 +137876,8 @@ sb_1__1_ sb_3__10_ ( .clk_2_W_out ( SYNOPSYS_UNCONNECTED_3015 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_3016 ) , .clk_2_N_out ( clk_2_wires[64] ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_3017 ) , .clk_3_W_in ( p1499 ) , - .clk_3_E_in ( p1675 ) , .clk_3_S_in ( p826 ) , .clk_3_N_in ( p2049 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_3017 ) , .clk_3_W_in ( p1611 ) , + .clk_3_E_in ( p285 ) , .clk_3_S_in ( p629 ) , .clk_3_N_in ( p153 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_3018 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_3019 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_3020 ) , @@ -134359,40 +137925,40 @@ sb_1__1_ sb_3__11_ ( .chanx_right_out ( sb_1__1__32_chanx_right_out ) , .chany_bottom_out ( sb_1__1__32_chany_bottom_out ) , .chanx_left_out ( sb_1__1__32_chanx_left_out ) , - .ccff_tail ( sb_1__1__32_ccff_tail ) , .Test_en_S_in ( p2259 ) , + .ccff_tail ( sb_1__1__32_ccff_tail ) , .Test_en_S_in ( p2331 ) , .Test_en_N_out ( SYNOPSYS_UNCONNECTED_3023 ) , .pReset_S_in ( SYNOPSYS_UNCONNECTED_3024 ) , .pReset_E_in ( pResetWires[564] ) , .pReset_W_in ( SYNOPSYS_UNCONNECTED_3025 ) , .pReset_N_out ( pResetWires[563] ) , .pReset_W_out ( pResetWires[561] ) , - .pReset_E_out ( SYNOPSYS_UNCONNECTED_3026 ) , .Reset_S_in ( p3489 ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_3026 ) , .Reset_S_in ( p2331 ) , .Reset_N_out ( SYNOPSYS_UNCONNECTED_3027 ) , .prog_clk_0_N_in ( prog_clk_0_wires[136] ) , .prog_clk_1_N_in ( SYNOPSYS_UNCONNECTED_3028 ) , .prog_clk_1_S_in ( prog_clk_2_wires[65] ) , .prog_clk_1_E_out ( prog_clk_1_wires[78] ) , - .prog_clk_1_W_out ( prog_clk_1_wires[79] ) , .prog_clk_2_N_in ( p2948 ) , - .prog_clk_2_E_in ( p1189 ) , .prog_clk_2_S_in ( p60 ) , - .prog_clk_2_W_in ( p230 ) , + .prog_clk_1_W_out ( prog_clk_1_wires[79] ) , .prog_clk_2_N_in ( p3506 ) , + .prog_clk_2_E_in ( p637 ) , .prog_clk_2_S_in ( p1255 ) , + .prog_clk_2_W_in ( p910 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_3029 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_3030 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_3031 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_3032 ) , - .prog_clk_3_W_in ( p2460 ) , .prog_clk_3_E_in ( p142 ) , - .prog_clk_3_S_in ( p1384 ) , .prog_clk_3_N_in ( p2893 ) , + .prog_clk_3_W_in ( p2251 ) , .prog_clk_3_E_in ( p837 ) , + .prog_clk_3_S_in ( p236 ) , .prog_clk_3_N_in ( p3480 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_3033 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_3034 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_3035 ) , .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_3036 ) , .clk_1_N_in ( SYNOPSYS_UNCONNECTED_3037 ) , .clk_1_S_in ( clk_2_wires[65] ) , .clk_1_E_out ( clk_1_wires[78] ) , - .clk_1_W_out ( clk_1_wires[79] ) , .clk_2_N_in ( p1826 ) , - .clk_2_E_in ( p926 ) , .clk_2_S_in ( p3482 ) , .clk_2_W_in ( p2308 ) , + .clk_1_W_out ( clk_1_wires[79] ) , .clk_2_N_in ( p3469 ) , + .clk_2_E_in ( p1199 ) , .clk_2_S_in ( p1164 ) , .clk_2_W_in ( p3523 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_3038 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_3039 ) , .clk_2_N_out ( SYNOPSYS_UNCONNECTED_3040 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_3041 ) , .clk_3_W_in ( p2460 ) , - .clk_3_E_in ( p468 ) , .clk_3_S_in ( p561 ) , .clk_3_N_in ( p1735 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_3041 ) , .clk_3_W_in ( p3530 ) , + .clk_3_E_in ( p58 ) , .clk_3_S_in ( p2126 ) , .clk_3_N_in ( p3449 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_3042 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_3043 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_3044 ) , @@ -134440,38 +138006,38 @@ sb_1__1_ sb_4__1_ ( .chanx_right_out ( sb_1__1__33_chanx_right_out ) , .chany_bottom_out ( sb_1__1__33_chany_bottom_out ) , .chanx_left_out ( sb_1__1__33_chanx_left_out ) , - .ccff_tail ( sb_1__1__33_ccff_tail ) , .Test_en_S_in ( p2501 ) , + .ccff_tail ( sb_1__1__33_ccff_tail ) , .Test_en_S_in ( p2597 ) , .Test_en_N_out ( SYNOPSYS_UNCONNECTED_3047 ) , .pReset_S_in ( SYNOPSYS_UNCONNECTED_3048 ) , .pReset_E_in ( pResetWires[78] ) , .pReset_W_in ( SYNOPSYS_UNCONNECTED_3049 ) , .pReset_N_out ( pResetWires[77] ) , .pReset_W_out ( pResetWires[75] ) , - .pReset_E_out ( SYNOPSYS_UNCONNECTED_3050 ) , .Reset_S_in ( p3431 ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_3050 ) , .Reset_S_in ( p2529 ) , .Reset_N_out ( SYNOPSYS_UNCONNECTED_3051 ) , - .prog_clk_0_N_in ( prog_clk_0_wires[144] ) , .prog_clk_1_N_in ( p1514 ) , - .prog_clk_1_S_in ( p557 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[144] ) , .prog_clk_1_N_in ( p1184 ) , + .prog_clk_1_S_in ( p1138 ) , .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_3052 ) , .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_3053 ) , - .prog_clk_2_N_in ( p3499 ) , .prog_clk_2_E_in ( p425 ) , - .prog_clk_2_S_in ( p5 ) , .prog_clk_2_W_in ( p1012 ) , + .prog_clk_2_N_in ( p3539 ) , .prog_clk_2_E_in ( p731 ) , + .prog_clk_2_S_in ( p1178 ) , .prog_clk_2_W_in ( p217 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_3054 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_3055 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_3056 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_3057 ) , - .prog_clk_3_W_in ( p2609 ) , .prog_clk_3_E_in ( p1266 ) , - .prog_clk_3_S_in ( p1535 ) , .prog_clk_3_N_in ( p3497 ) , + .prog_clk_3_W_in ( p3268 ) , .prog_clk_3_E_in ( p6 ) , + .prog_clk_3_S_in ( p99 ) , .prog_clk_3_N_in ( p3528 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_3058 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_3059 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_3060 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_3061 ) , .clk_1_N_in ( p1514 ) , - .clk_1_S_in ( p103 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_3062 ) , - .clk_1_W_out ( SYNOPSYS_UNCONNECTED_3063 ) , .clk_2_N_in ( p3327 ) , - .clk_2_E_in ( p647 ) , .clk_2_S_in ( p3421 ) , .clk_2_W_in ( p2542 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_3061 ) , .clk_1_N_in ( p1184 ) , + .clk_1_S_in ( p475 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_3062 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_3063 ) , .clk_2_N_in ( p3535 ) , + .clk_2_E_in ( p862 ) , .clk_2_S_in ( p1302 ) , .clk_2_W_in ( p3197 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_3064 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_3065 ) , .clk_2_N_out ( SYNOPSYS_UNCONNECTED_3066 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_3067 ) , .clk_3_W_in ( p2609 ) , - .clk_3_E_in ( p406 ) , .clk_3_S_in ( p511 ) , .clk_3_N_in ( p3300 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_3067 ) , .clk_3_W_in ( p1936 ) , + .clk_3_E_in ( p1189 ) , .clk_3_S_in ( p2389 ) , .clk_3_N_in ( p3522 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_3068 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_3069 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_3070 ) , @@ -134519,16 +138085,16 @@ sb_1__1_ sb_4__2_ ( .chanx_right_out ( sb_1__1__34_chanx_right_out ) , .chany_bottom_out ( sb_1__1__34_chany_bottom_out ) , .chanx_left_out ( sb_1__1__34_chanx_left_out ) , - .ccff_tail ( sb_1__1__34_ccff_tail ) , .Test_en_S_in ( p2840 ) , + .ccff_tail ( sb_1__1__34_ccff_tail ) , .Test_en_S_in ( p2348 ) , .Test_en_N_out ( SYNOPSYS_UNCONNECTED_3073 ) , .pReset_S_in ( SYNOPSYS_UNCONNECTED_3074 ) , .pReset_E_in ( pResetWires[127] ) , .pReset_W_in ( SYNOPSYS_UNCONNECTED_3075 ) , .pReset_N_out ( pResetWires[126] ) , .pReset_W_out ( pResetWires[124] ) , - .pReset_E_out ( SYNOPSYS_UNCONNECTED_3076 ) , .Reset_S_in ( p2840 ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_3076 ) , .Reset_S_in ( p2348 ) , .Reset_N_out ( SYNOPSYS_UNCONNECTED_3077 ) , - .prog_clk_0_N_in ( prog_clk_0_wires[147] ) , .prog_clk_1_N_in ( p1824 ) , - .prog_clk_1_S_in ( p374 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[147] ) , .prog_clk_1_N_in ( p1541 ) , + .prog_clk_1_S_in ( p1114 ) , .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_3078 ) , .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_3079 ) , .prog_clk_2_N_in ( prog_clk_3_wires[25] ) , @@ -134538,14 +138104,14 @@ sb_1__1_ sb_4__2_ ( .prog_clk_2_W_out ( prog_clk_2_wires[27] ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_3083 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_3084 ) , - .prog_clk_2_E_out ( prog_clk_2_wires[25] ) , .prog_clk_3_W_in ( p2500 ) , - .prog_clk_3_E_in ( p596 ) , .prog_clk_3_S_in ( p117 ) , - .prog_clk_3_N_in ( p118 ) , + .prog_clk_2_E_out ( prog_clk_2_wires[25] ) , .prog_clk_3_W_in ( p1258 ) , + .prog_clk_3_E_in ( p532 ) , .prog_clk_3_S_in ( p107 ) , + .prog_clk_3_N_in ( p340 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_3085 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_3086 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_3087 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_3088 ) , .clk_1_N_in ( p1824 ) , - .clk_1_S_in ( p662 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_3089 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_3088 ) , .clk_1_N_in ( p1541 ) , + .clk_1_S_in ( p548 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_3089 ) , .clk_1_W_out ( SYNOPSYS_UNCONNECTED_3090 ) , .clk_2_N_in ( clk_3_wires[25] ) , .clk_2_E_in ( SYNOPSYS_UNCONNECTED_3091 ) , @@ -134554,8 +138120,8 @@ sb_1__1_ sb_4__2_ ( .clk_2_W_out ( clk_2_wires[27] ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_3094 ) , .clk_2_N_out ( SYNOPSYS_UNCONNECTED_3095 ) , - .clk_2_E_out ( clk_2_wires[25] ) , .clk_3_W_in ( p2500 ) , - .clk_3_E_in ( p1631 ) , .clk_3_S_in ( p2718 ) , .clk_3_N_in ( p1665 ) , + .clk_2_E_out ( clk_2_wires[25] ) , .clk_3_W_in ( p1258 ) , + .clk_3_E_in ( p1717 ) , .clk_3_S_in ( p2139 ) , .clk_3_N_in ( p845 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_3096 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_3097 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_3098 ) , @@ -134603,20 +138169,20 @@ sb_1__1_ sb_4__3_ ( .chanx_right_out ( sb_1__1__35_chanx_right_out ) , .chany_bottom_out ( sb_1__1__35_chany_bottom_out ) , .chanx_left_out ( sb_1__1__35_chanx_left_out ) , - .ccff_tail ( sb_1__1__35_ccff_tail ) , .Test_en_S_in ( p2843 ) , + .ccff_tail ( sb_1__1__35_ccff_tail ) , .Test_en_S_in ( p2024 ) , .Test_en_N_out ( SYNOPSYS_UNCONNECTED_3101 ) , .pReset_S_in ( SYNOPSYS_UNCONNECTED_3102 ) , .pReset_E_in ( pResetWires[176] ) , .pReset_W_in ( SYNOPSYS_UNCONNECTED_3103 ) , .pReset_N_out ( pResetWires[175] ) , .pReset_W_out ( pResetWires[173] ) , - .pReset_E_out ( SYNOPSYS_UNCONNECTED_3104 ) , .Reset_S_in ( p2985 ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_3104 ) , .Reset_S_in ( p2024 ) , .Reset_N_out ( SYNOPSYS_UNCONNECTED_3105 ) , - .prog_clk_0_N_in ( prog_clk_0_wires[150] ) , .prog_clk_1_N_in ( p1374 ) , - .prog_clk_1_S_in ( p543 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[150] ) , .prog_clk_1_N_in ( p1442 ) , + .prog_clk_1_S_in ( p1052 ) , .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_3106 ) , .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_3107 ) , - .prog_clk_2_N_in ( p2446 ) , .prog_clk_2_E_in ( p402 ) , - .prog_clk_2_S_in ( p1995 ) , .prog_clk_2_W_in ( p964 ) , + .prog_clk_2_N_in ( p1563 ) , .prog_clk_2_E_in ( p811 ) , + .prog_clk_2_S_in ( p201 ) , .prog_clk_2_W_in ( p1049 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_3108 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_3109 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_3110 ) , @@ -134628,10 +138194,10 @@ sb_1__1_ sb_4__3_ ( .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_3115 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_3116 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_3117 ) , - .prog_clk_3_S_out ( prog_clk_3_wires[24] ) , .clk_1_N_in ( p1374 ) , - .clk_1_S_in ( p149 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_3118 ) , - .clk_1_W_out ( SYNOPSYS_UNCONNECTED_3119 ) , .clk_2_N_in ( p1807 ) , - .clk_2_E_in ( p73 ) , .clk_2_S_in ( p2898 ) , .clk_2_W_in ( p92 ) , + .prog_clk_3_S_out ( prog_clk_3_wires[24] ) , .clk_1_N_in ( p1442 ) , + .clk_1_S_in ( p121 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_3118 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_3119 ) , .clk_2_N_in ( p1563 ) , + .clk_2_E_in ( p123 ) , .clk_2_S_in ( p1712 ) , .clk_2_W_in ( p492 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_3120 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_3121 ) , .clk_2_N_out ( SYNOPSYS_UNCONNECTED_3122 ) , @@ -134687,16 +138253,16 @@ sb_1__1_ sb_4__4_ ( .chanx_right_out ( sb_1__1__36_chanx_right_out ) , .chany_bottom_out ( sb_1__1__36_chany_bottom_out ) , .chanx_left_out ( sb_1__1__36_chanx_left_out ) , - .ccff_tail ( sb_1__1__36_ccff_tail ) , .Test_en_S_in ( p2102 ) , + .ccff_tail ( sb_1__1__36_ccff_tail ) , .Test_en_S_in ( p1954 ) , .Test_en_N_out ( SYNOPSYS_UNCONNECTED_3131 ) , .pReset_S_in ( SYNOPSYS_UNCONNECTED_3132 ) , .pReset_E_in ( pResetWires[225] ) , .pReset_W_in ( SYNOPSYS_UNCONNECTED_3133 ) , .pReset_N_out ( pResetWires[224] ) , .pReset_W_out ( pResetWires[222] ) , - .pReset_E_out ( SYNOPSYS_UNCONNECTED_3134 ) , .Reset_S_in ( p2102 ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_3134 ) , .Reset_S_in ( p1954 ) , .Reset_N_out ( SYNOPSYS_UNCONNECTED_3135 ) , - .prog_clk_0_N_in ( prog_clk_0_wires[153] ) , .prog_clk_1_N_in ( p1584 ) , - .prog_clk_1_S_in ( p1024 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[153] ) , .prog_clk_1_N_in ( p1029 ) , + .prog_clk_1_S_in ( p1754 ) , .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_3136 ) , .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_3137 ) , .prog_clk_2_N_in ( prog_clk_3_wires[15] ) , @@ -134714,8 +138280,8 @@ sb_1__1_ sb_4__4_ ( .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_3146 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_3147 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_3148 ) , - .prog_clk_3_S_out ( prog_clk_3_wires[20] ) , .clk_1_N_in ( p1584 ) , - .clk_1_S_in ( p1980 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_3149 ) , + .prog_clk_3_S_out ( prog_clk_3_wires[20] ) , .clk_1_N_in ( p1029 ) , + .clk_1_S_in ( p1054 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_3149 ) , .clk_1_W_out ( SYNOPSYS_UNCONNECTED_3150 ) , .clk_2_N_in ( clk_3_wires[15] ) , .clk_2_E_in ( SYNOPSYS_UNCONNECTED_3151 ) , @@ -134776,20 +138342,20 @@ sb_1__1_ sb_4__5_ ( .chanx_right_out ( sb_1__1__37_chanx_right_out ) , .chany_bottom_out ( sb_1__1__37_chany_bottom_out ) , .chanx_left_out ( sb_1__1__37_chanx_left_out ) , - .ccff_tail ( sb_1__1__37_ccff_tail ) , .Test_en_S_in ( p2859 ) , + .ccff_tail ( sb_1__1__37_ccff_tail ) , .Test_en_S_in ( p1968 ) , .Test_en_N_out ( SYNOPSYS_UNCONNECTED_3163 ) , .pReset_S_in ( SYNOPSYS_UNCONNECTED_3164 ) , .pReset_E_in ( pResetWires[274] ) , .pReset_W_in ( SYNOPSYS_UNCONNECTED_3165 ) , .pReset_N_out ( pResetWires[273] ) , .pReset_W_out ( pResetWires[271] ) , - .pReset_E_out ( SYNOPSYS_UNCONNECTED_3166 ) , .Reset_S_in ( p3101 ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_3166 ) , .Reset_S_in ( p1968 ) , .Reset_N_out ( SYNOPSYS_UNCONNECTED_3167 ) , - .prog_clk_0_N_in ( prog_clk_0_wires[156] ) , .prog_clk_1_N_in ( p1448 ) , - .prog_clk_1_S_in ( p192 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[156] ) , .prog_clk_1_N_in ( p1854 ) , + .prog_clk_1_S_in ( p163 ) , .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_3168 ) , .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_3169 ) , - .prog_clk_2_N_in ( p1600 ) , .prog_clk_2_E_in ( p900 ) , - .prog_clk_2_S_in ( p563 ) , .prog_clk_2_W_in ( p520 ) , + .prog_clk_2_N_in ( p2355 ) , .prog_clk_2_E_in ( p458 ) , + .prog_clk_2_S_in ( p768 ) , .prog_clk_2_W_in ( p311 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_3170 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_3171 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_3172 ) , @@ -134801,10 +138367,10 @@ sb_1__1_ sb_4__5_ ( .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_3177 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_3178 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_3179 ) , - .prog_clk_3_S_out ( prog_clk_3_wires[14] ) , .clk_1_N_in ( p1448 ) , - .clk_1_S_in ( p130 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_3180 ) , - .clk_1_W_out ( SYNOPSYS_UNCONNECTED_3181 ) , .clk_2_N_in ( p1501 ) , - .clk_2_E_in ( p508 ) , .clk_2_S_in ( p3021 ) , .clk_2_W_in ( p593 ) , + .prog_clk_3_S_out ( prog_clk_3_wires[14] ) , .clk_1_N_in ( p1854 ) , + .clk_1_S_in ( p959 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_3180 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_3181 ) , .clk_2_N_in ( p1915 ) , + .clk_2_E_in ( p820 ) , .clk_2_S_in ( p1725 ) , .clk_2_W_in ( p736 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_3182 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_3183 ) , .clk_2_N_out ( SYNOPSYS_UNCONNECTED_3184 ) , @@ -134860,20 +138426,20 @@ sb_1__1_ sb_4__6_ ( .chanx_right_out ( sb_1__1__38_chanx_right_out ) , .chany_bottom_out ( sb_1__1__38_chany_bottom_out ) , .chanx_left_out ( sb_1__1__38_chanx_left_out ) , - .ccff_tail ( sb_1__1__38_ccff_tail ) , .Test_en_S_in ( p2969 ) , + .ccff_tail ( sb_1__1__38_ccff_tail ) , .Test_en_S_in ( p1926 ) , .Test_en_N_out ( SYNOPSYS_UNCONNECTED_3193 ) , .pReset_S_in ( SYNOPSYS_UNCONNECTED_3194 ) , .pReset_E_in ( pResetWires[323] ) , .pReset_W_in ( SYNOPSYS_UNCONNECTED_3195 ) , .pReset_N_out ( pResetWires[322] ) , .pReset_W_out ( pResetWires[320] ) , - .pReset_E_out ( SYNOPSYS_UNCONNECTED_3196 ) , .Reset_S_in ( p3311 ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_3196 ) , .Reset_S_in ( p1926 ) , .Reset_N_out ( SYNOPSYS_UNCONNECTED_3197 ) , - .prog_clk_0_N_in ( prog_clk_0_wires[159] ) , .prog_clk_1_N_in ( p1553 ) , - .prog_clk_1_S_in ( p461 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[159] ) , .prog_clk_1_N_in ( p1831 ) , + .prog_clk_1_S_in ( p1136 ) , .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_3198 ) , .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_3199 ) , - .prog_clk_2_N_in ( p2646 ) , .prog_clk_2_E_in ( p1001 ) , - .prog_clk_2_S_in ( p125 ) , .prog_clk_2_W_in ( p304 ) , + .prog_clk_2_N_in ( p2567 ) , .prog_clk_2_E_in ( p247 ) , + .prog_clk_2_S_in ( p1807 ) , .prog_clk_2_W_in ( p1690 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_3200 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_3201 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_3202 ) , @@ -134885,10 +138451,10 @@ sb_1__1_ sb_4__6_ ( .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_3207 ) , .prog_clk_3_W_out ( prog_clk_3_wires[46] ) , .prog_clk_3_N_out ( prog_clk_3_wires[8] ) , - .prog_clk_3_S_out ( prog_clk_3_wires[10] ) , .clk_1_N_in ( p1553 ) , - .clk_1_S_in ( p355 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_3208 ) , - .clk_1_W_out ( SYNOPSYS_UNCONNECTED_3209 ) , .clk_2_N_in ( p2472 ) , - .clk_2_E_in ( p215 ) , .clk_2_S_in ( p3286 ) , .clk_2_W_in ( p1198 ) , + .prog_clk_3_S_out ( prog_clk_3_wires[10] ) , .clk_1_N_in ( p1831 ) , + .clk_1_S_in ( p93 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_3208 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_3209 ) , .clk_2_N_in ( p2578 ) , + .clk_2_E_in ( p140 ) , .clk_2_S_in ( p1687 ) , .clk_2_W_in ( p231 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_3210 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_3211 ) , .clk_2_N_out ( SYNOPSYS_UNCONNECTED_3212 ) , @@ -134943,20 +138509,20 @@ sb_1__1_ sb_4__7_ ( .chanx_right_out ( sb_1__1__39_chanx_right_out ) , .chany_bottom_out ( sb_1__1__39_chany_bottom_out ) , .chanx_left_out ( sb_1__1__39_chanx_left_out ) , - .ccff_tail ( sb_1__1__39_ccff_tail ) , .Test_en_S_in ( p2237 ) , + .ccff_tail ( sb_1__1__39_ccff_tail ) , .Test_en_S_in ( p2210 ) , .Test_en_N_out ( SYNOPSYS_UNCONNECTED_3219 ) , .pReset_S_in ( SYNOPSYS_UNCONNECTED_3220 ) , .pReset_E_in ( pResetWires[372] ) , .pReset_W_in ( SYNOPSYS_UNCONNECTED_3221 ) , .pReset_N_out ( pResetWires[371] ) , .pReset_W_out ( pResetWires[369] ) , - .pReset_E_out ( SYNOPSYS_UNCONNECTED_3222 ) , .Reset_S_in ( p3243 ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_3222 ) , .Reset_S_in ( p2210 ) , .Reset_N_out ( SYNOPSYS_UNCONNECTED_3223 ) , - .prog_clk_0_N_in ( prog_clk_0_wires[162] ) , .prog_clk_1_N_in ( p1487 ) , - .prog_clk_1_S_in ( p512 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[162] ) , .prog_clk_1_N_in ( p1301 ) , + .prog_clk_1_S_in ( p1168 ) , .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_3224 ) , .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_3225 ) , - .prog_clk_2_N_in ( p2847 ) , .prog_clk_2_E_in ( p1195 ) , - .prog_clk_2_S_in ( p2010 ) , .prog_clk_2_W_in ( p1083 ) , + .prog_clk_2_N_in ( p1866 ) , .prog_clk_2_E_in ( p670 ) , + .prog_clk_2_S_in ( p2059 ) , .prog_clk_2_W_in ( p180 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_3226 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_3227 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_3228 ) , @@ -134968,10 +138534,10 @@ sb_1__1_ sb_4__7_ ( .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_3233 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_3234 ) , .prog_clk_3_N_out ( prog_clk_3_wires[12] ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_3235 ) , .clk_1_N_in ( p1487 ) , - .clk_1_S_in ( p973 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_3236 ) , - .clk_1_W_out ( SYNOPSYS_UNCONNECTED_3237 ) , .clk_2_N_in ( p2174 ) , - .clk_2_E_in ( p235 ) , .clk_2_S_in ( p3221 ) , .clk_2_W_in ( p153 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_3235 ) , .clk_1_N_in ( p1301 ) , + .clk_1_S_in ( p375 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_3236 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_3237 ) , .clk_2_N_in ( p1866 ) , + .clk_2_E_in ( p307 ) , .clk_2_S_in ( p2169 ) , .clk_2_W_in ( p829 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_3238 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_3239 ) , .clk_2_N_out ( SYNOPSYS_UNCONNECTED_3240 ) , @@ -135027,16 +138593,16 @@ sb_1__1_ sb_4__8_ ( .chanx_right_out ( sb_1__1__40_chanx_right_out ) , .chany_bottom_out ( sb_1__1__40_chany_bottom_out ) , .chanx_left_out ( sb_1__1__40_chanx_left_out ) , - .ccff_tail ( sb_1__1__40_ccff_tail ) , .Test_en_S_in ( p1882 ) , + .ccff_tail ( sb_1__1__40_ccff_tail ) , .Test_en_S_in ( p1420 ) , .Test_en_N_out ( SYNOPSYS_UNCONNECTED_3249 ) , .pReset_S_in ( SYNOPSYS_UNCONNECTED_3250 ) , .pReset_E_in ( pResetWires[421] ) , .pReset_W_in ( SYNOPSYS_UNCONNECTED_3251 ) , .pReset_N_out ( pResetWires[420] ) , .pReset_W_out ( pResetWires[418] ) , - .pReset_E_out ( SYNOPSYS_UNCONNECTED_3252 ) , .Reset_S_in ( p1882 ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_3252 ) , .Reset_S_in ( p1420 ) , .Reset_N_out ( SYNOPSYS_UNCONNECTED_3253 ) , - .prog_clk_0_N_in ( prog_clk_0_wires[165] ) , .prog_clk_1_N_in ( p1849 ) , - .prog_clk_1_S_in ( p892 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[165] ) , .prog_clk_1_N_in ( p1495 ) , + .prog_clk_1_S_in ( p1197 ) , .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_3254 ) , .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_3255 ) , .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_3256 ) , @@ -135054,8 +138620,8 @@ sb_1__1_ sb_4__8_ ( .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_3264 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_3265 ) , .prog_clk_3_N_out ( prog_clk_3_wires[18] ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_3266 ) , .clk_1_N_in ( p1764 ) , - .clk_1_S_in ( p1654 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_3267 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_3266 ) , .clk_1_N_in ( p1495 ) , + .clk_1_S_in ( p166 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_3267 ) , .clk_1_W_out ( SYNOPSYS_UNCONNECTED_3268 ) , .clk_2_N_in ( SYNOPSYS_UNCONNECTED_3269 ) , .clk_2_E_in ( SYNOPSYS_UNCONNECTED_3270 ) , @@ -135116,20 +138682,20 @@ sb_1__1_ sb_4__9_ ( .chanx_right_out ( sb_1__1__41_chanx_right_out ) , .chany_bottom_out ( sb_1__1__41_chany_bottom_out ) , .chanx_left_out ( sb_1__1__41_chanx_left_out ) , - .ccff_tail ( sb_1__1__41_ccff_tail ) , .Test_en_S_in ( p2989 ) , + .ccff_tail ( sb_1__1__41_ccff_tail ) , .Test_en_S_in ( p2295 ) , .Test_en_N_out ( SYNOPSYS_UNCONNECTED_3281 ) , .pReset_S_in ( SYNOPSYS_UNCONNECTED_3282 ) , .pReset_E_in ( pResetWires[470] ) , .pReset_W_in ( SYNOPSYS_UNCONNECTED_3283 ) , .pReset_N_out ( pResetWires[469] ) , .pReset_W_out ( pResetWires[467] ) , - .pReset_E_out ( SYNOPSYS_UNCONNECTED_3284 ) , .Reset_S_in ( p2989 ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_3284 ) , .Reset_S_in ( p2295 ) , .Reset_N_out ( SYNOPSYS_UNCONNECTED_3285 ) , - .prog_clk_0_N_in ( prog_clk_0_wires[168] ) , .prog_clk_1_N_in ( p1335 ) , - .prog_clk_1_S_in ( p714 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[168] ) , .prog_clk_1_N_in ( p1631 ) , + .prog_clk_1_S_in ( p198 ) , .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_3286 ) , .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_3287 ) , - .prog_clk_2_N_in ( p2674 ) , .prog_clk_2_E_in ( p766 ) , - .prog_clk_2_S_in ( p1740 ) , .prog_clk_2_W_in ( p1089 ) , + .prog_clk_2_N_in ( p2550 ) , .prog_clk_2_E_in ( p706 ) , + .prog_clk_2_S_in ( p515 ) , .prog_clk_2_W_in ( p218 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_3288 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_3289 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_3290 ) , @@ -135141,10 +138707,10 @@ sb_1__1_ sb_4__9_ ( .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_3295 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_3296 ) , .prog_clk_3_N_out ( prog_clk_3_wires[22] ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_3297 ) , .clk_1_N_in ( p1335 ) , - .clk_1_S_in ( p298 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_3298 ) , - .clk_1_W_out ( SYNOPSYS_UNCONNECTED_3299 ) , .clk_2_N_in ( p2484 ) , - .clk_2_E_in ( p224 ) , .clk_2_S_in ( p2891 ) , .clk_2_W_in ( p295 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_3297 ) , .clk_1_N_in ( p1631 ) , + .clk_1_S_in ( p1096 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_3298 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_3299 ) , .clk_2_N_in ( p2550 ) , + .clk_2_E_in ( p48 ) , .clk_2_S_in ( p2082 ) , .clk_2_W_in ( p566 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_3300 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_3301 ) , .clk_2_N_out ( SYNOPSYS_UNCONNECTED_3302 ) , @@ -135200,16 +138766,16 @@ sb_1__1_ sb_4__10_ ( .chanx_right_out ( sb_1__1__42_chanx_right_out ) , .chany_bottom_out ( sb_1__1__42_chany_bottom_out ) , .chanx_left_out ( sb_1__1__42_chanx_left_out ) , - .ccff_tail ( sb_1__1__42_ccff_tail ) , .Test_en_S_in ( p2170 ) , + .ccff_tail ( sb_1__1__42_ccff_tail ) , .Test_en_S_in ( p2361 ) , .Test_en_N_out ( SYNOPSYS_UNCONNECTED_3311 ) , .pReset_S_in ( SYNOPSYS_UNCONNECTED_3312 ) , .pReset_E_in ( pResetWires[519] ) , .pReset_W_in ( SYNOPSYS_UNCONNECTED_3313 ) , .pReset_N_out ( pResetWires[518] ) , .pReset_W_out ( pResetWires[516] ) , - .pReset_E_out ( SYNOPSYS_UNCONNECTED_3314 ) , .Reset_S_in ( p2170 ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_3314 ) , .Reset_S_in ( p2361 ) , .Reset_N_out ( SYNOPSYS_UNCONNECTED_3315 ) , - .prog_clk_0_N_in ( prog_clk_0_wires[171] ) , .prog_clk_1_N_in ( p1403 ) , - .prog_clk_1_S_in ( p176 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[171] ) , .prog_clk_1_N_in ( p1984 ) , + .prog_clk_1_S_in ( p256 ) , .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_3316 ) , .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_3317 ) , .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_3318 ) , @@ -135219,14 +138785,14 @@ sb_1__1_ sb_4__10_ ( .prog_clk_2_W_out ( prog_clk_2_wires[62] ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_3321 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_3322 ) , - .prog_clk_2_E_out ( prog_clk_2_wires[60] ) , .prog_clk_3_W_in ( p1934 ) , - .prog_clk_3_E_in ( p249 ) , .prog_clk_3_S_in ( p328 ) , - .prog_clk_3_N_in ( p945 ) , + .prog_clk_2_E_out ( prog_clk_2_wires[60] ) , .prog_clk_3_W_in ( p1602 ) , + .prog_clk_3_E_in ( p726 ) , .prog_clk_3_S_in ( p363 ) , + .prog_clk_3_N_in ( p493 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_3323 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_3324 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_3325 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_3326 ) , .clk_1_N_in ( p1403 ) , - .clk_1_S_in ( p1099 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_3327 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_3326 ) , .clk_1_N_in ( p1984 ) , + .clk_1_S_in ( p990 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_3327 ) , .clk_1_W_out ( SYNOPSYS_UNCONNECTED_3328 ) , .clk_2_N_in ( SYNOPSYS_UNCONNECTED_3329 ) , .clk_2_E_in ( SYNOPSYS_UNCONNECTED_3330 ) , @@ -135235,8 +138801,8 @@ sb_1__1_ sb_4__10_ ( .clk_2_W_out ( clk_2_wires[62] ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_3332 ) , .clk_2_N_out ( SYNOPSYS_UNCONNECTED_3333 ) , - .clk_2_E_out ( clk_2_wires[60] ) , .clk_3_W_in ( p1934 ) , - .clk_3_E_in ( p1992 ) , .clk_3_S_in ( p1973 ) , .clk_3_N_in ( p97 ) , + .clk_2_E_out ( clk_2_wires[60] ) , .clk_3_W_in ( p1602 ) , + .clk_3_E_in ( p202 ) , .clk_3_S_in ( p2081 ) , .clk_3_N_in ( p1658 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_3334 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_3335 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_3336 ) , @@ -135284,38 +138850,38 @@ sb_1__1_ sb_4__11_ ( .chanx_right_out ( sb_1__1__43_chanx_right_out ) , .chany_bottom_out ( sb_1__1__43_chany_bottom_out ) , .chanx_left_out ( sb_1__1__43_chanx_left_out ) , - .ccff_tail ( sb_1__1__43_ccff_tail ) , .Test_en_S_in ( p3240 ) , + .ccff_tail ( sb_1__1__43_ccff_tail ) , .Test_en_S_in ( p2009 ) , .Test_en_N_out ( SYNOPSYS_UNCONNECTED_3339 ) , .pReset_S_in ( SYNOPSYS_UNCONNECTED_3340 ) , .pReset_E_in ( pResetWires[568] ) , .pReset_W_in ( SYNOPSYS_UNCONNECTED_3341 ) , .pReset_N_out ( pResetWires[567] ) , .pReset_W_out ( pResetWires[565] ) , - .pReset_E_out ( SYNOPSYS_UNCONNECTED_3342 ) , .Reset_S_in ( p3240 ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_3342 ) , .Reset_S_in ( p2009 ) , .Reset_N_out ( SYNOPSYS_UNCONNECTED_3343 ) , - .prog_clk_0_N_in ( prog_clk_0_wires[174] ) , .prog_clk_1_N_in ( p1848 ) , - .prog_clk_1_S_in ( p746 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[174] ) , .prog_clk_1_N_in ( p2228 ) , + .prog_clk_1_S_in ( p470 ) , .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_3344 ) , .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_3345 ) , - .prog_clk_2_N_in ( p3090 ) , .prog_clk_2_E_in ( p889 ) , - .prog_clk_2_S_in ( p494 ) , .prog_clk_2_W_in ( p1271 ) , + .prog_clk_2_N_in ( p3608 ) , .prog_clk_2_E_in ( p298 ) , + .prog_clk_2_S_in ( p600 ) , .prog_clk_2_W_in ( p115 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_3346 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_3347 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_3348 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_3349 ) , - .prog_clk_3_W_in ( p2668 ) , .prog_clk_3_E_in ( p426 ) , - .prog_clk_3_S_in ( p1340 ) , .prog_clk_3_N_in ( p3009 ) , + .prog_clk_3_W_in ( p2334 ) , .prog_clk_3_E_in ( p782 ) , + .prog_clk_3_S_in ( p1043 ) , .prog_clk_3_N_in ( p3606 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_3350 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_3351 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_3352 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_3353 ) , .clk_1_N_in ( p1848 ) , - .clk_1_S_in ( p459 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_3354 ) , - .clk_1_W_out ( SYNOPSYS_UNCONNECTED_3355 ) , .clk_2_N_in ( p3411 ) , - .clk_2_E_in ( p777 ) , .clk_2_S_in ( p3217 ) , .clk_2_W_in ( p2573 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_3353 ) , .clk_1_N_in ( p2228 ) , + .clk_1_S_in ( p1127 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_3354 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_3355 ) , .clk_2_N_in ( p3130 ) , + .clk_2_E_in ( p505 ) , .clk_2_S_in ( p182 ) , .clk_2_W_in ( p3549 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_3356 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_3357 ) , .clk_2_N_out ( SYNOPSYS_UNCONNECTED_3358 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_3359 ) , .clk_3_W_in ( p2668 ) , - .clk_3_E_in ( p523 ) , .clk_3_S_in ( p1262 ) , .clk_3_N_in ( p3390 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_3359 ) , .clk_3_W_in ( p3557 ) , + .clk_3_E_in ( p1195 ) , .clk_3_S_in ( p1688 ) , .clk_3_N_in ( p3093 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_3360 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_3361 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_3362 ) , @@ -135363,27 +138929,27 @@ sb_1__1_ sb_5__1_ ( .chanx_right_out ( sb_1__1__44_chanx_right_out ) , .chany_bottom_out ( sb_1__1__44_chany_bottom_out ) , .chanx_left_out ( sb_1__1__44_chanx_left_out ) , - .ccff_tail ( sb_1__1__44_ccff_tail ) , .Test_en_S_in ( p2496 ) , + .ccff_tail ( sb_1__1__44_ccff_tail ) , .Test_en_S_in ( p2633 ) , .Test_en_N_out ( SYNOPSYS_UNCONNECTED_3365 ) , .pReset_S_in ( SYNOPSYS_UNCONNECTED_3366 ) , .pReset_E_in ( pResetWires[82] ) , .pReset_W_in ( SYNOPSYS_UNCONNECTED_3367 ) , .pReset_N_out ( pResetWires[81] ) , .pReset_W_out ( pResetWires[79] ) , - .pReset_E_out ( SYNOPSYS_UNCONNECTED_3368 ) , .Reset_S_in ( p2496 ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_3368 ) , .Reset_S_in ( p2633 ) , .Reset_N_out ( SYNOPSYS_UNCONNECTED_3369 ) , .prog_clk_0_N_in ( prog_clk_0_wires[182] ) , .prog_clk_1_N_in ( prog_clk_2_wires[32] ) , .prog_clk_1_S_in ( SYNOPSYS_UNCONNECTED_3370 ) , .prog_clk_1_E_out ( prog_clk_1_wires[85] ) , - .prog_clk_1_W_out ( prog_clk_1_wires[86] ) , .prog_clk_2_N_in ( p3331 ) , - .prog_clk_2_E_in ( p1207 ) , .prog_clk_2_S_in ( p1242 ) , - .prog_clk_2_W_in ( p529 ) , + .prog_clk_1_W_out ( prog_clk_1_wires[86] ) , .prog_clk_2_N_in ( p2804 ) , + .prog_clk_2_E_in ( p135 ) , .prog_clk_2_S_in ( p715 ) , + .prog_clk_2_W_in ( p417 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_3371 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_3372 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_3373 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_3374 ) , - .prog_clk_3_W_in ( p3164 ) , .prog_clk_3_E_in ( p186 ) , - .prog_clk_3_S_in ( p654 ) , .prog_clk_3_N_in ( p3288 ) , + .prog_clk_3_W_in ( p2757 ) , .prog_clk_3_E_in ( p963 ) , + .prog_clk_3_S_in ( p1023 ) , .prog_clk_3_N_in ( p2656 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_3375 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_3376 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_3377 ) , @@ -135391,12 +138957,12 @@ sb_1__1_ sb_5__1_ ( .clk_1_N_in ( clk_2_wires[32] ) , .clk_1_S_in ( SYNOPSYS_UNCONNECTED_3379 ) , .clk_1_E_out ( clk_1_wires[85] ) , .clk_1_W_out ( clk_1_wires[86] ) , - .clk_2_N_in ( p3403 ) , .clk_2_E_in ( p865 ) , .clk_2_S_in ( p2346 ) , - .clk_2_W_in ( p3129 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_3380 ) , + .clk_2_N_in ( p3540 ) , .clk_2_E_in ( p308 ) , .clk_2_S_in ( p1381 ) , + .clk_2_W_in ( p3615 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_3380 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_3381 ) , .clk_2_N_out ( SYNOPSYS_UNCONNECTED_3382 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_3383 ) , .clk_3_W_in ( p3164 ) , - .clk_3_E_in ( p818 ) , .clk_3_S_in ( p276 ) , .clk_3_N_in ( p3393 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_3383 ) , .clk_3_W_in ( p3616 ) , + .clk_3_E_in ( p1202 ) , .clk_3_S_in ( p2397 ) , .clk_3_N_in ( p3525 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_3384 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_3385 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_3386 ) , @@ -135444,16 +139010,16 @@ sb_1__1_ sb_5__2_ ( .chanx_right_out ( sb_1__1__45_chanx_right_out ) , .chany_bottom_out ( sb_1__1__45_chany_bottom_out ) , .chanx_left_out ( sb_1__1__45_chanx_left_out ) , - .ccff_tail ( sb_1__1__45_ccff_tail ) , .Test_en_S_in ( p2938 ) , + .ccff_tail ( sb_1__1__45_ccff_tail ) , .Test_en_S_in ( p2222 ) , .Test_en_N_out ( SYNOPSYS_UNCONNECTED_3389 ) , .pReset_S_in ( SYNOPSYS_UNCONNECTED_3390 ) , .pReset_E_in ( pResetWires[131] ) , .pReset_W_in ( SYNOPSYS_UNCONNECTED_3391 ) , .pReset_N_out ( pResetWires[130] ) , .pReset_W_out ( pResetWires[128] ) , - .pReset_E_out ( SYNOPSYS_UNCONNECTED_3392 ) , .Reset_S_in ( p2938 ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_3392 ) , .Reset_S_in ( p2222 ) , .Reset_N_out ( SYNOPSYS_UNCONNECTED_3393 ) , - .prog_clk_0_N_in ( prog_clk_0_wires[185] ) , .prog_clk_1_N_in ( p1525 ) , - .prog_clk_1_S_in ( p501 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[185] ) , .prog_clk_1_N_in ( p1370 ) , + .prog_clk_1_S_in ( p605 ) , .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_3394 ) , .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_3395 ) , .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_3396 ) , @@ -135464,13 +139030,13 @@ sb_1__1_ sb_5__2_ ( .prog_clk_2_S_out ( prog_clk_2_wires[31] ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_3400 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_3401 ) , - .prog_clk_3_W_in ( p1867 ) , .prog_clk_3_E_in ( p841 ) , - .prog_clk_3_S_in ( p429 ) , .prog_clk_3_N_in ( p551 ) , + .prog_clk_3_W_in ( p1538 ) , .prog_clk_3_E_in ( p94 ) , + .prog_clk_3_S_in ( p808 ) , .prog_clk_3_N_in ( p456 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_3402 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_3403 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_3404 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_3405 ) , .clk_1_N_in ( p1525 ) , - .clk_1_S_in ( p39 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_3406 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_3405 ) , .clk_1_N_in ( p1370 ) , + .clk_1_S_in ( p9 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_3406 ) , .clk_1_W_out ( SYNOPSYS_UNCONNECTED_3407 ) , .clk_2_N_in ( SYNOPSYS_UNCONNECTED_3408 ) , .clk_2_E_in ( SYNOPSYS_UNCONNECTED_3409 ) , @@ -135479,8 +139045,8 @@ sb_1__1_ sb_5__2_ ( .clk_2_W_out ( SYNOPSYS_UNCONNECTED_3411 ) , .clk_2_S_out ( clk_2_wires[31] ) , .clk_2_N_out ( SYNOPSYS_UNCONNECTED_3412 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_3413 ) , .clk_3_W_in ( p1867 ) , - .clk_3_E_in ( p108 ) , .clk_3_S_in ( p2896 ) , .clk_3_N_in ( p300 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_3413 ) , .clk_3_W_in ( p1538 ) , + .clk_3_E_in ( p564 ) , .clk_3_S_in ( p2068 ) , .clk_3_N_in ( p728 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_3414 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_3415 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_3416 ) , @@ -135528,27 +139094,27 @@ sb_1__1_ sb_5__3_ ( .chanx_right_out ( sb_1__1__46_chanx_right_out ) , .chany_bottom_out ( sb_1__1__46_chany_bottom_out ) , .chanx_left_out ( sb_1__1__46_chanx_left_out ) , - .ccff_tail ( sb_1__1__46_ccff_tail ) , .Test_en_S_in ( p2495 ) , + .ccff_tail ( sb_1__1__46_ccff_tail ) , .Test_en_S_in ( p2252 ) , .Test_en_N_out ( SYNOPSYS_UNCONNECTED_3419 ) , .pReset_S_in ( SYNOPSYS_UNCONNECTED_3420 ) , .pReset_E_in ( pResetWires[180] ) , .pReset_W_in ( SYNOPSYS_UNCONNECTED_3421 ) , .pReset_N_out ( pResetWires[179] ) , .pReset_W_out ( pResetWires[177] ) , - .pReset_E_out ( SYNOPSYS_UNCONNECTED_3422 ) , .Reset_S_in ( p2495 ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_3422 ) , .Reset_S_in ( p2252 ) , .Reset_N_out ( SYNOPSYS_UNCONNECTED_3423 ) , .prog_clk_0_N_in ( prog_clk_0_wires[188] ) , .prog_clk_1_N_in ( prog_clk_2_wires[45] ) , .prog_clk_1_S_in ( SYNOPSYS_UNCONNECTED_3424 ) , .prog_clk_1_E_out ( prog_clk_1_wires[92] ) , - .prog_clk_1_W_out ( prog_clk_1_wires[93] ) , .prog_clk_2_N_in ( p3326 ) , - .prog_clk_2_E_in ( p203 ) , .prog_clk_2_S_in ( p843 ) , - .prog_clk_2_W_in ( p331 ) , + .prog_clk_1_W_out ( prog_clk_1_wires[93] ) , .prog_clk_2_N_in ( p3602 ) , + .prog_clk_2_E_in ( p443 ) , .prog_clk_2_S_in ( p193 ) , + .prog_clk_2_W_in ( p784 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_3425 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_3426 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_3427 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_3428 ) , - .prog_clk_3_W_in ( p3069 ) , .prog_clk_3_E_in ( p987 ) , - .prog_clk_3_S_in ( p452 ) , .prog_clk_3_N_in ( p3287 ) , + .prog_clk_3_W_in ( p2624 ) , .prog_clk_3_E_in ( p763 ) , + .prog_clk_3_S_in ( p1181 ) , .prog_clk_3_N_in ( p3600 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_3429 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_3430 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_3431 ) , @@ -135556,12 +139122,12 @@ sb_1__1_ sb_5__3_ ( .clk_1_N_in ( clk_2_wires[45] ) , .clk_1_S_in ( SYNOPSYS_UNCONNECTED_3433 ) , .clk_1_E_out ( clk_1_wires[92] ) , .clk_1_W_out ( clk_1_wires[93] ) , - .clk_2_N_in ( p3430 ) , .clk_2_E_in ( p522 ) , .clk_2_S_in ( p2342 ) , - .clk_2_W_in ( p3028 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_3434 ) , + .clk_2_N_in ( p3141 ) , .clk_2_E_in ( p1059 ) , .clk_2_S_in ( p934 ) , + .clk_2_W_in ( p2906 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_3434 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_3435 ) , .clk_2_N_out ( SYNOPSYS_UNCONNECTED_3436 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_3437 ) , .clk_3_W_in ( p3069 ) , - .clk_3_E_in ( p769 ) , .clk_3_S_in ( p221 ) , .clk_3_N_in ( p3420 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_3437 ) , .clk_3_W_in ( p3029 ) , + .clk_3_E_in ( p225 ) , .clk_3_S_in ( p2109 ) , .clk_3_N_in ( p3038 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_3438 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_3439 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_3440 ) , @@ -135609,16 +139175,16 @@ sb_1__1_ sb_5__4_ ( .chanx_right_out ( sb_1__1__47_chanx_right_out ) , .chany_bottom_out ( sb_1__1__47_chany_bottom_out ) , .chanx_left_out ( sb_1__1__47_chanx_left_out ) , - .ccff_tail ( sb_1__1__47_ccff_tail ) , .Test_en_S_in ( p2407 ) , + .ccff_tail ( sb_1__1__47_ccff_tail ) , .Test_en_S_in ( p2605 ) , .Test_en_N_out ( SYNOPSYS_UNCONNECTED_3443 ) , .pReset_S_in ( SYNOPSYS_UNCONNECTED_3444 ) , .pReset_E_in ( pResetWires[229] ) , .pReset_W_in ( SYNOPSYS_UNCONNECTED_3445 ) , .pReset_N_out ( pResetWires[228] ) , .pReset_W_out ( pResetWires[226] ) , - .pReset_E_out ( SYNOPSYS_UNCONNECTED_3446 ) , .Reset_S_in ( p2407 ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_3446 ) , .Reset_S_in ( p2605 ) , .Reset_N_out ( SYNOPSYS_UNCONNECTED_3447 ) , - .prog_clk_0_N_in ( prog_clk_0_wires[191] ) , .prog_clk_1_N_in ( p684 ) , - .prog_clk_1_S_in ( p872 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[191] ) , .prog_clk_1_N_in ( p1937 ) , + .prog_clk_1_S_in ( p318 ) , .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_3448 ) , .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_3449 ) , .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_3450 ) , @@ -135629,13 +139195,13 @@ sb_1__1_ sb_5__4_ ( .prog_clk_2_S_out ( prog_clk_2_wires[44] ) , .prog_clk_2_N_out ( prog_clk_2_wires[42] ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_3454 ) , - .prog_clk_3_W_in ( p1590 ) , .prog_clk_3_E_in ( p560 ) , - .prog_clk_3_S_in ( p733 ) , .prog_clk_3_N_in ( p2534 ) , + .prog_clk_3_W_in ( p1498 ) , .prog_clk_3_E_in ( p336 ) , + .prog_clk_3_S_in ( p37 ) , .prog_clk_3_N_in ( p1675 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_3455 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_3456 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_3457 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_3458 ) , .clk_1_N_in ( p684 ) , - .clk_1_S_in ( p262 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_3459 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_3458 ) , .clk_1_N_in ( p1937 ) , + .clk_1_S_in ( p750 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_3459 ) , .clk_1_W_out ( SYNOPSYS_UNCONNECTED_3460 ) , .clk_2_N_in ( SYNOPSYS_UNCONNECTED_3461 ) , .clk_2_E_in ( SYNOPSYS_UNCONNECTED_3462 ) , @@ -135643,8 +139209,8 @@ sb_1__1_ sb_5__4_ ( .clk_2_W_in ( clk_2_wires[35] ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_3464 ) , .clk_2_S_out ( clk_2_wires[44] ) , .clk_2_N_out ( clk_2_wires[42] ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_3465 ) , .clk_3_W_in ( p1590 ) , - .clk_3_E_in ( p996 ) , .clk_3_S_in ( p2286 ) , .clk_3_N_in ( p802 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_3465 ) , .clk_3_W_in ( p1498 ) , + .clk_3_E_in ( p294 ) , .clk_3_S_in ( p2405 ) , .clk_3_N_in ( p1757 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_3466 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_3467 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_3468 ) , @@ -135692,40 +139258,40 @@ sb_1__1_ sb_5__5_ ( .chanx_right_out ( sb_1__1__48_chanx_right_out ) , .chany_bottom_out ( sb_1__1__48_chany_bottom_out ) , .chanx_left_out ( sb_1__1__48_chanx_left_out ) , - .ccff_tail ( sb_1__1__48_ccff_tail ) , .Test_en_S_in ( p2816 ) , + .ccff_tail ( sb_1__1__48_ccff_tail ) , .Test_en_S_in ( p2528 ) , .Test_en_N_out ( SYNOPSYS_UNCONNECTED_3471 ) , .pReset_S_in ( SYNOPSYS_UNCONNECTED_3472 ) , .pReset_E_in ( pResetWires[278] ) , .pReset_W_in ( SYNOPSYS_UNCONNECTED_3473 ) , .pReset_N_out ( pResetWires[277] ) , .pReset_W_out ( pResetWires[275] ) , - .pReset_E_out ( SYNOPSYS_UNCONNECTED_3474 ) , .Reset_S_in ( p3307 ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_3474 ) , .Reset_S_in ( p2528 ) , .Reset_N_out ( SYNOPSYS_UNCONNECTED_3475 ) , .prog_clk_0_N_in ( prog_clk_0_wires[194] ) , .prog_clk_1_N_in ( SYNOPSYS_UNCONNECTED_3476 ) , .prog_clk_1_S_in ( prog_clk_2_wires[43] ) , .prog_clk_1_E_out ( prog_clk_1_wires[99] ) , - .prog_clk_1_W_out ( prog_clk_1_wires[100] ) , .prog_clk_2_N_in ( p3486 ) , - .prog_clk_2_E_in ( p613 ) , .prog_clk_2_S_in ( p1150 ) , - .prog_clk_2_W_in ( p3 ) , + .prog_clk_1_W_out ( prog_clk_1_wires[100] ) , .prog_clk_2_N_in ( p3417 ) , + .prog_clk_2_E_in ( p529 ) , .prog_clk_2_S_in ( p1261 ) , + .prog_clk_2_W_in ( p172 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_3477 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_3478 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_3479 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_3480 ) , - .prog_clk_3_W_in ( p2168 ) , .prog_clk_3_E_in ( p1378 ) , - .prog_clk_3_S_in ( p284 ) , .prog_clk_3_N_in ( p3485 ) , + .prog_clk_3_W_in ( p3342 ) , .prog_clk_3_E_in ( p996 ) , + .prog_clk_3_S_in ( p656 ) , .prog_clk_3_N_in ( p3363 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_3481 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_3482 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_3483 ) , .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_3484 ) , .clk_1_N_in ( SYNOPSYS_UNCONNECTED_3485 ) , .clk_1_S_in ( clk_2_wires[43] ) , .clk_1_E_out ( clk_1_wires[99] ) , - .clk_1_W_out ( clk_1_wires[100] ) , .clk_2_N_in ( p2037 ) , - .clk_2_E_in ( p992 ) , .clk_2_S_in ( p3290 ) , .clk_2_W_in ( p2018 ) , + .clk_1_W_out ( clk_1_wires[100] ) , .clk_2_N_in ( p3571 ) , + .clk_2_E_in ( p1007 ) , .clk_2_S_in ( p18 ) , .clk_2_W_in ( p3310 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_3486 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_3487 ) , .clk_2_N_out ( SYNOPSYS_UNCONNECTED_3488 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_3489 ) , .clk_3_W_in ( p2168 ) , - .clk_3_E_in ( p263 ) , .clk_3_S_in ( p66 ) , .clk_3_N_in ( p2073 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_3489 ) , .clk_3_W_in ( p2961 ) , + .clk_3_E_in ( p277 ) , .clk_3_S_in ( p2417 ) , .clk_3_N_in ( p3570 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_3490 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_3491 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_3492 ) , @@ -135773,20 +139339,20 @@ sb_1__1_ sb_5__6_ ( .chanx_right_out ( sb_1__1__49_chanx_right_out ) , .chany_bottom_out ( sb_1__1__49_chany_bottom_out ) , .chanx_left_out ( sb_1__1__49_chanx_left_out ) , - .ccff_tail ( sb_1__1__49_ccff_tail ) , .Test_en_S_in ( p2514 ) , + .ccff_tail ( sb_1__1__49_ccff_tail ) , .Test_en_S_in ( p1928 ) , .Test_en_N_out ( SYNOPSYS_UNCONNECTED_3495 ) , .pReset_S_in ( SYNOPSYS_UNCONNECTED_3496 ) , .pReset_E_in ( pResetWires[327] ) , .pReset_W_in ( SYNOPSYS_UNCONNECTED_3497 ) , .pReset_N_out ( pResetWires[326] ) , .pReset_W_out ( pResetWires[324] ) , - .pReset_E_out ( SYNOPSYS_UNCONNECTED_3498 ) , .Reset_S_in ( p2514 ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_3498 ) , .Reset_S_in ( p1928 ) , .Reset_N_out ( SYNOPSYS_UNCONNECTED_3499 ) , - .prog_clk_0_N_in ( prog_clk_0_wires[197] ) , .prog_clk_1_N_in ( p1346 ) , - .prog_clk_1_S_in ( p1078 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[197] ) , .prog_clk_1_N_in ( p2045 ) , + .prog_clk_1_S_in ( p4 ) , .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_3500 ) , .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_3501 ) , - .prog_clk_2_N_in ( p2846 ) , .prog_clk_2_E_in ( p537 ) , - .prog_clk_2_S_in ( p311 ) , .prog_clk_2_W_in ( p1357 ) , + .prog_clk_2_N_in ( p2535 ) , .prog_clk_2_E_in ( p501 ) , + .prog_clk_2_S_in ( p360 ) , .prog_clk_2_W_in ( p1714 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_3502 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_3503 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_3504 ) , @@ -135798,10 +139364,10 @@ sb_1__1_ sb_5__6_ ( .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_3509 ) , .prog_clk_3_W_out ( prog_clk_3_wires[6] ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_3510 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_3511 ) , .clk_1_N_in ( p1346 ) , - .clk_1_S_in ( p17 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_3512 ) , - .clk_1_W_out ( SYNOPSYS_UNCONNECTED_3513 ) , .clk_2_N_in ( p1510 ) , - .clk_2_E_in ( p202 ) , .clk_2_S_in ( p2273 ) , .clk_2_W_in ( p251 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_3511 ) , .clk_1_N_in ( p2045 ) , + .clk_1_S_in ( p1126 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_3512 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_3513 ) , .clk_2_N_in ( p2613 ) , + .clk_2_E_in ( p761 ) , .clk_2_S_in ( p1768 ) , .clk_2_W_in ( p660 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_3514 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_3515 ) , .clk_2_N_out ( SYNOPSYS_UNCONNECTED_3516 ) , @@ -135857,27 +139423,27 @@ sb_1__1_ sb_5__7_ ( .chanx_right_out ( sb_1__1__50_chanx_right_out ) , .chany_bottom_out ( sb_1__1__50_chany_bottom_out ) , .chanx_left_out ( sb_1__1__50_chanx_left_out ) , - .ccff_tail ( sb_1__1__50_ccff_tail ) , .Test_en_S_in ( p2699 ) , + .ccff_tail ( sb_1__1__50_ccff_tail ) , .Test_en_S_in ( p2207 ) , .Test_en_N_out ( SYNOPSYS_UNCONNECTED_3525 ) , .pReset_S_in ( SYNOPSYS_UNCONNECTED_3526 ) , .pReset_E_in ( pResetWires[376] ) , .pReset_W_in ( SYNOPSYS_UNCONNECTED_3527 ) , .pReset_N_out ( pResetWires[375] ) , .pReset_W_out ( pResetWires[373] ) , - .pReset_E_out ( SYNOPSYS_UNCONNECTED_3528 ) , .Reset_S_in ( p2620 ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_3528 ) , .Reset_S_in ( p2207 ) , .Reset_N_out ( SYNOPSYS_UNCONNECTED_3529 ) , .prog_clk_0_N_in ( prog_clk_0_wires[200] ) , .prog_clk_1_N_in ( prog_clk_2_wires[58] ) , .prog_clk_1_S_in ( SYNOPSYS_UNCONNECTED_3530 ) , .prog_clk_1_E_out ( prog_clk_1_wires[106] ) , - .prog_clk_1_W_out ( prog_clk_1_wires[107] ) , .prog_clk_2_N_in ( p3367 ) , - .prog_clk_2_E_in ( p1213 ) , .prog_clk_2_S_in ( p1279 ) , - .prog_clk_2_W_in ( p1011 ) , + .prog_clk_1_W_out ( prog_clk_1_wires[107] ) , .prog_clk_2_N_in ( p2825 ) , + .prog_clk_2_E_in ( p684 ) , .prog_clk_2_S_in ( p1185 ) , + .prog_clk_2_W_in ( p313 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_3531 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_3532 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_3533 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_3534 ) , - .prog_clk_3_W_in ( p2680 ) , .prog_clk_3_E_in ( p804 ) , - .prog_clk_3_S_in ( p578 ) , .prog_clk_3_N_in ( p3352 ) , + .prog_clk_3_W_in ( p3166 ) , .prog_clk_3_E_in ( p444 ) , + .prog_clk_3_S_in ( p278 ) , .prog_clk_3_N_in ( p2705 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_3535 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_3536 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_3537 ) , @@ -135885,12 +139451,12 @@ sb_1__1_ sb_5__7_ ( .clk_1_N_in ( clk_2_wires[58] ) , .clk_1_S_in ( SYNOPSYS_UNCONNECTED_3539 ) , .clk_1_E_out ( clk_1_wires[106] ) , .clk_1_W_out ( clk_1_wires[107] ) , - .clk_2_N_in ( p3465 ) , .clk_2_E_in ( p801 ) , .clk_2_S_in ( p2549 ) , - .clk_2_W_in ( p2570 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_3540 ) , + .clk_2_N_in ( p3272 ) , .clk_2_E_in ( p66 ) , .clk_2_S_in ( p1028 ) , + .clk_2_W_in ( p3054 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_3540 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_3541 ) , .clk_2_N_out ( SYNOPSYS_UNCONNECTED_3542 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_3543 ) , .clk_3_W_in ( p2680 ) , - .clk_3_E_in ( p530 ) , .clk_3_S_in ( p179 ) , .clk_3_N_in ( p3464 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_3543 ) , .clk_3_W_in ( p2949 ) , + .clk_3_E_in ( p1167 ) , .clk_3_S_in ( p2061 ) , .clk_3_N_in ( p3175 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_3544 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_3545 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_3546 ) , @@ -135938,16 +139504,16 @@ sb_1__1_ sb_5__8_ ( .chanx_right_out ( sb_1__1__51_chanx_right_out ) , .chany_bottom_out ( sb_1__1__51_chany_bottom_out ) , .chanx_left_out ( sb_1__1__51_chanx_left_out ) , - .ccff_tail ( sb_1__1__51_ccff_tail ) , .Test_en_S_in ( p2117 ) , + .ccff_tail ( sb_1__1__51_ccff_tail ) , .Test_en_S_in ( p2548 ) , .Test_en_N_out ( SYNOPSYS_UNCONNECTED_3549 ) , .pReset_S_in ( SYNOPSYS_UNCONNECTED_3550 ) , .pReset_E_in ( pResetWires[425] ) , .pReset_W_in ( SYNOPSYS_UNCONNECTED_3551 ) , .pReset_N_out ( pResetWires[424] ) , .pReset_W_out ( pResetWires[422] ) , - .pReset_E_out ( SYNOPSYS_UNCONNECTED_3552 ) , .Reset_S_in ( p2117 ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_3552 ) , .Reset_S_in ( p2548 ) , .Reset_N_out ( SYNOPSYS_UNCONNECTED_3553 ) , - .prog_clk_0_N_in ( prog_clk_0_wires[203] ) , .prog_clk_1_N_in ( p1338 ) , - .prog_clk_1_S_in ( p308 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[203] ) , .prog_clk_1_N_in ( p1852 ) , + .prog_clk_1_S_in ( p451 ) , .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_3554 ) , .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_3555 ) , .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_3556 ) , @@ -135958,13 +139524,13 @@ sb_1__1_ sb_5__8_ ( .prog_clk_2_S_out ( prog_clk_2_wires[57] ) , .prog_clk_2_N_out ( prog_clk_2_wires[55] ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_3560 ) , - .prog_clk_3_W_in ( p2417 ) , .prog_clk_3_E_in ( p87 ) , - .prog_clk_3_S_in ( p100 ) , .prog_clk_3_N_in ( p1677 ) , + .prog_clk_3_W_in ( p1526 ) , .prog_clk_3_E_in ( p365 ) , + .prog_clk_3_S_in ( p274 ) , .prog_clk_3_N_in ( p1791 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_3561 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_3562 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_3563 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_3564 ) , .clk_1_N_in ( p1338 ) , - .clk_1_S_in ( p789 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_3565 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_3564 ) , .clk_1_N_in ( p1852 ) , + .clk_1_S_in ( p1089 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_3565 ) , .clk_1_W_out ( SYNOPSYS_UNCONNECTED_3566 ) , .clk_2_N_in ( SYNOPSYS_UNCONNECTED_3567 ) , .clk_2_E_in ( SYNOPSYS_UNCONNECTED_3568 ) , @@ -135972,8 +139538,8 @@ sb_1__1_ sb_5__8_ ( .clk_2_W_in ( clk_2_wires[48] ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_3570 ) , .clk_2_S_out ( clk_2_wires[57] ) , .clk_2_N_out ( clk_2_wires[55] ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_3571 ) , .clk_3_W_in ( p2417 ) , - .clk_3_E_in ( p1015 ) , .clk_3_S_in ( p1978 ) , .clk_3_N_in ( p534 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_3571 ) , .clk_3_W_in ( p1526 ) , + .clk_3_E_in ( p103 ) , .clk_3_S_in ( p2385 ) , .clk_3_N_in ( p1710 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_3572 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_3573 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_3574 ) , @@ -136021,40 +139587,40 @@ sb_1__1_ sb_5__9_ ( .chanx_right_out ( sb_1__1__52_chanx_right_out ) , .chany_bottom_out ( sb_1__1__52_chany_bottom_out ) , .chanx_left_out ( sb_1__1__52_chanx_left_out ) , - .ccff_tail ( sb_1__1__52_ccff_tail ) , .Test_en_S_in ( p3083 ) , + .ccff_tail ( sb_1__1__52_ccff_tail ) , .Test_en_S_in ( p1829 ) , .Test_en_N_out ( SYNOPSYS_UNCONNECTED_3577 ) , .pReset_S_in ( SYNOPSYS_UNCONNECTED_3578 ) , .pReset_E_in ( pResetWires[474] ) , .pReset_W_in ( SYNOPSYS_UNCONNECTED_3579 ) , .pReset_N_out ( pResetWires[473] ) , .pReset_W_out ( pResetWires[471] ) , - .pReset_E_out ( SYNOPSYS_UNCONNECTED_3580 ) , .Reset_S_in ( p3192 ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_3580 ) , .Reset_S_in ( p1829 ) , .Reset_N_out ( SYNOPSYS_UNCONNECTED_3581 ) , .prog_clk_0_N_in ( prog_clk_0_wires[206] ) , .prog_clk_1_N_in ( SYNOPSYS_UNCONNECTED_3582 ) , .prog_clk_1_S_in ( prog_clk_2_wires[56] ) , .prog_clk_1_E_out ( prog_clk_1_wires[113] ) , - .prog_clk_1_W_out ( prog_clk_1_wires[114] ) , .prog_clk_2_N_in ( p3471 ) , - .prog_clk_2_E_in ( p1263 ) , .prog_clk_2_S_in ( p602 ) , - .prog_clk_2_W_in ( p1088 ) , + .prog_clk_1_W_out ( prog_clk_1_wires[114] ) , .prog_clk_2_N_in ( p3618 ) , + .prog_clk_2_E_in ( p269 ) , .prog_clk_2_S_in ( p987 ) , + .prog_clk_2_W_in ( p733 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_3583 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_3584 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_3585 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_3586 ) , - .prog_clk_3_W_in ( p2445 ) , .prog_clk_3_E_in ( p91 ) , - .prog_clk_3_S_in ( p1034 ) , .prog_clk_3_N_in ( p3463 ) , + .prog_clk_3_W_in ( p3274 ) , .prog_clk_3_E_in ( p686 ) , + .prog_clk_3_S_in ( p794 ) , .prog_clk_3_N_in ( p3617 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_3587 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_3588 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_3589 ) , .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_3590 ) , .clk_1_N_in ( SYNOPSYS_UNCONNECTED_3591 ) , .clk_1_S_in ( clk_2_wires[56] ) , .clk_1_E_out ( clk_1_wires[113] ) , - .clk_1_W_out ( clk_1_wires[114] ) , .clk_2_N_in ( p2584 ) , - .clk_2_E_in ( p742 ) , .clk_2_S_in ( p3138 ) , .clk_2_W_in ( p2331 ) , + .clk_1_W_out ( clk_1_wires[114] ) , .clk_2_N_in ( p3267 ) , + .clk_2_E_in ( p345 ) , .clk_2_S_in ( p923 ) , .clk_2_W_in ( p3190 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_3592 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_3593 ) , .clk_2_N_out ( SYNOPSYS_UNCONNECTED_3594 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_3595 ) , .clk_3_W_in ( p2445 ) , - .clk_3_E_in ( p1162 ) , .clk_3_S_in ( p1298 ) , .clk_3_N_in ( p2556 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_3595 ) , .clk_3_W_in ( p3024 ) , + .clk_3_E_in ( p938 ) , .clk_3_S_in ( p1667 ) , .clk_3_N_in ( p3217 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_3596 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_3597 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_3598 ) , @@ -136102,16 +139668,16 @@ sb_1__1_ sb_5__10_ ( .chanx_right_out ( sb_1__1__53_chanx_right_out ) , .chany_bottom_out ( sb_1__1__53_chany_bottom_out ) , .chanx_left_out ( sb_1__1__53_chanx_left_out ) , - .ccff_tail ( sb_1__1__53_ccff_tail ) , .Test_en_S_in ( p2467 ) , + .ccff_tail ( sb_1__1__53_ccff_tail ) , .Test_en_S_in ( p2221 ) , .Test_en_N_out ( SYNOPSYS_UNCONNECTED_3601 ) , .pReset_S_in ( SYNOPSYS_UNCONNECTED_3602 ) , .pReset_E_in ( pResetWires[523] ) , .pReset_W_in ( SYNOPSYS_UNCONNECTED_3603 ) , .pReset_N_out ( pResetWires[522] ) , .pReset_W_out ( pResetWires[520] ) , - .pReset_E_out ( SYNOPSYS_UNCONNECTED_3604 ) , .Reset_S_in ( p2467 ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_3604 ) , .Reset_S_in ( p2221 ) , .Reset_N_out ( SYNOPSYS_UNCONNECTED_3605 ) , - .prog_clk_0_N_in ( prog_clk_0_wires[209] ) , .prog_clk_1_N_in ( p1813 ) , - .prog_clk_1_S_in ( p457 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[209] ) , .prog_clk_1_N_in ( p1399 ) , + .prog_clk_1_S_in ( p1269 ) , .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_3606 ) , .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_3607 ) , .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_3608 ) , @@ -136122,13 +139688,13 @@ sb_1__1_ sb_5__10_ ( .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_3612 ) , .prog_clk_2_N_out ( prog_clk_2_wires[66] ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_3613 ) , - .prog_clk_3_W_in ( p1493 ) , .prog_clk_3_E_in ( p93 ) , - .prog_clk_3_S_in ( p7 ) , .prog_clk_3_N_in ( p728 ) , + .prog_clk_3_W_in ( p1903 ) , .prog_clk_3_E_in ( p305 ) , + .prog_clk_3_S_in ( p559 ) , .prog_clk_3_N_in ( p1683 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_3614 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_3615 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_3616 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_3617 ) , .clk_1_N_in ( p1813 ) , - .clk_1_S_in ( p417 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_3618 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_3617 ) , .clk_1_N_in ( p1399 ) , + .clk_1_S_in ( p654 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_3618 ) , .clk_1_W_out ( SYNOPSYS_UNCONNECTED_3619 ) , .clk_2_N_in ( SYNOPSYS_UNCONNECTED_3620 ) , .clk_2_E_in ( SYNOPSYS_UNCONNECTED_3621 ) , @@ -136137,8 +139703,8 @@ sb_1__1_ sb_5__10_ ( .clk_2_W_out ( SYNOPSYS_UNCONNECTED_3623 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_3624 ) , .clk_2_N_out ( clk_2_wires[66] ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_3625 ) , .clk_3_W_in ( p1493 ) , - .clk_3_E_in ( p790 ) , .clk_3_S_in ( p2278 ) , .clk_3_N_in ( p1642 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_3625 ) , .clk_3_W_in ( p1903 ) , + .clk_3_E_in ( p1025 ) , .clk_3_S_in ( p2117 ) , .clk_3_N_in ( p266 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_3626 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_3627 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_3628 ) , @@ -136186,40 +139752,40 @@ sb_1__1_ sb_5__11_ ( .chanx_right_out ( sb_1__1__54_chanx_right_out ) , .chany_bottom_out ( sb_1__1__54_chany_bottom_out ) , .chanx_left_out ( sb_1__1__54_chanx_left_out ) , - .ccff_tail ( sb_1__1__54_ccff_tail ) , .Test_en_S_in ( p2194 ) , + .ccff_tail ( sb_1__1__54_ccff_tail ) , .Test_en_S_in ( p2767 ) , .Test_en_N_out ( SYNOPSYS_UNCONNECTED_3631 ) , .pReset_S_in ( SYNOPSYS_UNCONNECTED_3632 ) , .pReset_E_in ( pResetWires[572] ) , .pReset_W_in ( SYNOPSYS_UNCONNECTED_3633 ) , .pReset_N_out ( pResetWires[571] ) , .pReset_W_out ( pResetWires[569] ) , - .pReset_E_out ( SYNOPSYS_UNCONNECTED_3634 ) , .Reset_S_in ( p2194 ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_3634 ) , .Reset_S_in ( p2767 ) , .Reset_N_out ( SYNOPSYS_UNCONNECTED_3635 ) , .prog_clk_0_N_in ( prog_clk_0_wires[212] ) , .prog_clk_1_N_in ( SYNOPSYS_UNCONNECTED_3636 ) , .prog_clk_1_S_in ( prog_clk_2_wires[67] ) , .prog_clk_1_E_out ( prog_clk_1_wires[120] ) , - .prog_clk_1_W_out ( prog_clk_1_wires[121] ) , .prog_clk_2_N_in ( p3451 ) , - .prog_clk_2_E_in ( p772 ) , .prog_clk_2_S_in ( p280 ) , - .prog_clk_2_W_in ( p351 ) , + .prog_clk_1_W_out ( prog_clk_1_wires[121] ) , .prog_clk_2_N_in ( p3414 ) , + .prog_clk_2_E_in ( p331 ) , .prog_clk_2_S_in ( p1312 ) , + .prog_clk_2_W_in ( p461 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_3637 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_3638 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_3639 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_3640 ) , - .prog_clk_3_W_in ( p2630 ) , .prog_clk_3_E_in ( p1273 ) , - .prog_clk_3_S_in ( p1349 ) , .prog_clk_3_N_in ( p3446 ) , + .prog_clk_3_W_in ( p2816 ) , .prog_clk_3_E_in ( p540 ) , + .prog_clk_3_S_in ( p653 ) , .prog_clk_3_N_in ( p3373 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_3641 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_3642 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_3643 ) , .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_3644 ) , .clk_1_N_in ( SYNOPSYS_UNCONNECTED_3645 ) , .clk_1_S_in ( clk_2_wires[67] ) , .clk_1_E_out ( clk_1_wires[120] ) , - .clk_1_W_out ( clk_1_wires[121] ) , .clk_2_N_in ( p3172 ) , - .clk_2_E_in ( p43 ) , .clk_2_S_in ( p1990 ) , .clk_2_W_in ( p2540 ) , + .clk_1_W_out ( clk_1_wires[121] ) , .clk_2_N_in ( p3232 ) , + .clk_2_E_in ( p394 ) , .clk_2_S_in ( p288 ) , .clk_2_W_in ( p3582 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_3646 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_3647 ) , .clk_2_N_out ( SYNOPSYS_UNCONNECTED_3648 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_3649 ) , .clk_3_W_in ( p2630 ) , - .clk_3_E_in ( p875 ) , .clk_3_S_in ( p225 ) , .clk_3_N_in ( p3144 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_3649 ) , .clk_3_W_in ( p3590 ) , + .clk_3_E_in ( p758 ) , .clk_3_S_in ( p2685 ) , .clk_3_N_in ( p3203 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_3650 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_3651 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_3652 ) , @@ -136274,12 +139840,12 @@ sb_1__1_ sb_6__1_ ( .pReset_N_out ( pResetWires[85] ) , .pReset_W_out ( pResetWires[83] ) , .pReset_E_out ( pResetWires[86] ) , .Reset_S_in ( ResetWires[2] ) , .Reset_N_out ( ResetWires[3] ) , - .prog_clk_0_N_in ( prog_clk_0_wires[220] ) , .prog_clk_1_N_in ( p1347 ) , - .prog_clk_1_S_in ( p178 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[220] ) , .prog_clk_1_N_in ( p1553 ) , + .prog_clk_1_S_in ( p1102 ) , .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_3657 ) , .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_3658 ) , - .prog_clk_2_N_in ( p1503 ) , .prog_clk_2_E_in ( p1100 ) , - .prog_clk_2_S_in ( p1999 ) , .prog_clk_2_W_in ( p205 ) , + .prog_clk_2_N_in ( p1270 ) , .prog_clk_2_E_in ( p306 ) , + .prog_clk_2_S_in ( p620 ) , .prog_clk_2_W_in ( p859 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_3659 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_3660 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_3661 ) , @@ -136291,10 +139857,10 @@ sb_1__1_ sb_6__1_ ( .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_3666 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_3667 ) , .prog_clk_3_N_out ( prog_clk_3_wires[92] ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_3668 ) , .clk_1_N_in ( p1347 ) , - .clk_1_S_in ( p630 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_3669 ) , - .clk_1_W_out ( SYNOPSYS_UNCONNECTED_3670 ) , .clk_2_N_in ( p1503 ) , - .clk_2_E_in ( p558 ) , .clk_2_S_in ( p695 ) , .clk_2_W_in ( p1153 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_3668 ) , .clk_1_N_in ( p1553 ) , + .clk_1_S_in ( p672 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_3669 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_3670 ) , .clk_2_N_in ( p1270 ) , + .clk_2_E_in ( p184 ) , .clk_2_S_in ( p95 ) , .clk_2_W_in ( p410 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_3671 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_3672 ) , .clk_2_N_out ( SYNOPSYS_UNCONNECTED_3673 ) , @@ -136357,12 +139923,12 @@ sb_1__1_ sb_6__2_ ( .pReset_N_out ( pResetWires[134] ) , .pReset_W_out ( pResetWires[132] ) , .pReset_E_out ( pResetWires[135] ) , .Reset_S_in ( ResetWires[4] ) , .Reset_N_out ( ResetWires[5] ) , - .prog_clk_0_N_in ( prog_clk_0_wires[223] ) , .prog_clk_1_N_in ( p1615 ) , - .prog_clk_1_S_in ( p86 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[223] ) , .prog_clk_1_N_in ( p1508 ) , + .prog_clk_1_S_in ( p317 ) , .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_3684 ) , .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_3685 ) , - .prog_clk_2_N_in ( p2696 ) , .prog_clk_2_E_in ( p377 ) , - .prog_clk_2_S_in ( p1668 ) , .prog_clk_2_W_in ( p1114 ) , + .prog_clk_2_N_in ( p2580 ) , .prog_clk_2_E_in ( p549 ) , + .prog_clk_2_S_in ( p89 ) , .prog_clk_2_W_in ( p409 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_3686 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_3687 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_3688 ) , @@ -136374,10 +139940,10 @@ sb_1__1_ sb_6__2_ ( .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_3693 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_3694 ) , .prog_clk_3_N_out ( prog_clk_3_wires[94] ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_3695 ) , .clk_1_N_in ( p1615 ) , - .clk_1_S_in ( p862 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_3696 ) , - .clk_1_W_out ( SYNOPSYS_UNCONNECTED_3697 ) , .clk_2_N_in ( p1940 ) , - .clk_2_E_in ( p704 ) , .clk_2_S_in ( p446 ) , .clk_2_W_in ( p296 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_3695 ) , .clk_1_N_in ( p1508 ) , + .clk_1_S_in ( p1188 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_3696 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_3697 ) , .clk_2_N_in ( p2580 ) , + .clk_2_E_in ( p556 ) , .clk_2_S_in ( p466 ) , .clk_2_W_in ( p209 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_3698 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_3699 ) , .clk_2_N_out ( SYNOPSYS_UNCONNECTED_3700 ) , @@ -136440,12 +140006,12 @@ sb_1__1_ sb_6__3_ ( .pReset_N_out ( pResetWires[183] ) , .pReset_W_out ( pResetWires[181] ) , .pReset_E_out ( pResetWires[184] ) , .Reset_S_in ( ResetWires[6] ) , .Reset_N_out ( ResetWires[7] ) , - .prog_clk_0_N_in ( prog_clk_0_wires[226] ) , .prog_clk_1_N_in ( p1550 ) , - .prog_clk_1_S_in ( p710 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[226] ) , .prog_clk_1_N_in ( p1567 ) , + .prog_clk_1_S_in ( p897 ) , .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_3711 ) , .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_3712 ) , - .prog_clk_2_N_in ( p1931 ) , .prog_clk_2_E_in ( p729 ) , - .prog_clk_2_S_in ( p1680 ) , .prog_clk_2_W_in ( p916 ) , + .prog_clk_2_N_in ( p3139 ) , .prog_clk_2_E_in ( p610 ) , + .prog_clk_2_S_in ( p783 ) , .prog_clk_2_W_in ( p264 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_3713 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_3714 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_3715 ) , @@ -136457,10 +140023,10 @@ sb_1__1_ sb_6__3_ ( .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_3720 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_3721 ) , .prog_clk_3_N_out ( prog_clk_3_wires[96] ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_3722 ) , .clk_1_N_in ( p1550 ) , - .clk_1_S_in ( p135 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_3723 ) , - .clk_1_W_out ( SYNOPSYS_UNCONNECTED_3724 ) , .clk_2_N_in ( p1931 ) , - .clk_2_E_in ( p74 ) , .clk_2_S_in ( p565 ) , .clk_2_W_in ( p247 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_3722 ) , .clk_1_N_in ( p1567 ) , + .clk_1_S_in ( p253 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_3723 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_3724 ) , .clk_2_N_in ( p1874 ) , + .clk_2_E_in ( p149 ) , .clk_2_S_in ( p283 ) , .clk_2_W_in ( p693 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_3725 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_3726 ) , .clk_2_N_out ( SYNOPSYS_UNCONNECTED_3727 ) , @@ -136523,12 +140089,12 @@ sb_1__1_ sb_6__4_ ( .pReset_N_out ( pResetWires[232] ) , .pReset_W_out ( pResetWires[230] ) , .pReset_E_out ( pResetWires[233] ) , .Reset_S_in ( ResetWires[8] ) , .Reset_N_out ( ResetWires[9] ) , - .prog_clk_0_N_in ( prog_clk_0_wires[229] ) , .prog_clk_1_N_in ( p1317 ) , - .prog_clk_1_S_in ( p96 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[229] ) , .prog_clk_1_N_in ( p1438 ) , + .prog_clk_1_S_in ( p206 ) , .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_3738 ) , .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_3739 ) , - .prog_clk_2_N_in ( p2949 ) , .prog_clk_2_E_in ( p706 ) , - .prog_clk_2_S_in ( p1670 ) , .prog_clk_2_W_in ( p201 ) , + .prog_clk_2_N_in ( p2213 ) , .prog_clk_2_E_in ( p377 ) , + .prog_clk_2_S_in ( p1772 ) , .prog_clk_2_W_in ( p235 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_3740 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_3741 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_3742 ) , @@ -136540,10 +140106,10 @@ sb_1__1_ sb_6__4_ ( .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_3747 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_3748 ) , .prog_clk_3_N_out ( prog_clk_3_wires[98] ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_3749 ) , .clk_1_N_in ( p1317 ) , - .clk_1_S_in ( p1075 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_3750 ) , - .clk_1_W_out ( SYNOPSYS_UNCONNECTED_3751 ) , .clk_2_N_in ( p2452 ) , - .clk_2_E_in ( p254 ) , .clk_2_S_in ( p431 ) , .clk_2_W_in ( p393 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_3749 ) , .clk_1_N_in ( p1438 ) , + .clk_1_S_in ( p578 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_3750 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_3751 ) , .clk_2_N_in ( p1277 ) , + .clk_2_E_in ( p233 ) , .clk_2_S_in ( p1686 ) , .clk_2_W_in ( p937 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_3752 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_3753 ) , .clk_2_N_out ( SYNOPSYS_UNCONNECTED_3754 ) , @@ -136607,12 +140173,12 @@ sb_1__1_ sb_6__5_ ( .pReset_N_out ( pResetWires[281] ) , .pReset_W_out ( pResetWires[279] ) , .pReset_E_out ( pResetWires[282] ) , .Reset_S_in ( ResetWires[10] ) , .Reset_N_out ( ResetWires[11] ) , - .prog_clk_0_N_in ( prog_clk_0_wires[232] ) , .prog_clk_1_N_in ( p1821 ) , - .prog_clk_1_S_in ( p1006 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[232] ) , .prog_clk_1_N_in ( p1458 ) , + .prog_clk_1_S_in ( p1159 ) , .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_3765 ) , .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_3766 ) , - .prog_clk_2_N_in ( p2804 ) , .prog_clk_2_E_in ( p399 ) , - .prog_clk_2_S_in ( p1673 ) , .prog_clk_2_W_in ( p310 ) , + .prog_clk_2_N_in ( p1878 ) , .prog_clk_2_E_in ( p592 ) , + .prog_clk_2_S_in ( p446 ) , .prog_clk_2_W_in ( p710 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_3767 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_3768 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_3769 ) , @@ -136624,10 +140190,10 @@ sb_1__1_ sb_6__5_ ( .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_3774 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_3775 ) , .prog_clk_3_N_out ( prog_clk_3_wires[100] ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_3776 ) , .clk_1_N_in ( p1821 ) , - .clk_1_S_in ( p432 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_3777 ) , - .clk_1_W_out ( SYNOPSYS_UNCONNECTED_3778 ) , .clk_2_N_in ( p2712 ) , - .clk_2_E_in ( p799 ) , .clk_2_S_in ( p483 ) , .clk_2_W_in ( p1168 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_3776 ) , .clk_1_N_in ( p1458 ) , + .clk_1_S_in ( p28 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_3777 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_3778 ) , .clk_2_N_in ( p1878 ) , + .clk_2_E_in ( p729 ) , .clk_2_S_in ( p704 ) , .clk_2_W_in ( p53 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_3779 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_3780 ) , .clk_2_N_out ( SYNOPSYS_UNCONNECTED_3781 ) , @@ -136691,12 +140257,12 @@ sb_1__1_ sb_6__6_ ( .pReset_N_out ( pResetWires[330] ) , .pReset_W_out ( pResetWires[328] ) , .pReset_E_out ( pResetWires[331] ) , .Reset_S_in ( ResetWires[12] ) , .Reset_N_out ( ResetWires[13] ) , - .prog_clk_0_N_in ( prog_clk_0_wires[235] ) , .prog_clk_1_N_in ( p1521 ) , - .prog_clk_1_S_in ( p773 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[235] ) , .prog_clk_1_N_in ( p1476 ) , + .prog_clk_1_S_in ( p1035 ) , .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_3792 ) , .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_3793 ) , - .prog_clk_2_N_in ( p1435 ) , .prog_clk_2_E_in ( p963 ) , - .prog_clk_2_S_in ( p2001 ) , .prog_clk_2_W_in ( p1666 ) , + .prog_clk_2_N_in ( p3011 ) , .prog_clk_2_E_in ( p709 ) , + .prog_clk_2_S_in ( p359 ) , .prog_clk_2_W_in ( p2053 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_3794 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_3795 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_3796 ) , @@ -136708,10 +140274,10 @@ sb_1__1_ sb_6__6_ ( .prog_clk_3_E_out ( prog_clk_3_wires[0] ) , .prog_clk_3_W_out ( prog_clk_3_wires[2] ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_3801 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_3802 ) , .clk_1_N_in ( p1521 ) , - .clk_1_S_in ( p365 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_3803 ) , - .clk_1_W_out ( SYNOPSYS_UNCONNECTED_3804 ) , .clk_2_N_in ( p1840 ) , - .clk_2_E_in ( p26 ) , .clk_2_S_in ( p390 ) , .clk_2_W_in ( p174 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_3802 ) , .clk_1_N_in ( p1476 ) , + .clk_1_S_in ( p98 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_3803 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_3804 ) , .clk_2_N_in ( p2015 ) , + .clk_2_E_in ( p272 ) , .clk_2_S_in ( p671 ) , .clk_2_W_in ( p617 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_3805 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_3806 ) , .clk_2_N_out ( SYNOPSYS_UNCONNECTED_3807 ) , @@ -136774,30 +140340,30 @@ sb_1__1_ sb_6__7_ ( .pReset_N_out ( pResetWires[379] ) , .pReset_W_out ( pResetWires[377] ) , .pReset_E_out ( pResetWires[380] ) , .Reset_S_in ( ResetWires[14] ) , .Reset_N_out ( ResetWires[15] ) , - .prog_clk_0_N_in ( prog_clk_0_wires[238] ) , .prog_clk_1_N_in ( p2161 ) , - .prog_clk_1_S_in ( p1170 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[238] ) , .prog_clk_1_N_in ( p1206 ) , + .prog_clk_1_S_in ( p560 ) , .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_3817 ) , .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_3818 ) , - .prog_clk_2_N_in ( p3435 ) , .prog_clk_2_E_in ( p887 ) , - .prog_clk_2_S_in ( p663 ) , .prog_clk_2_W_in ( p57 ) , + .prog_clk_2_N_in ( p3609 ) , .prog_clk_2_E_in ( p10 ) , + .prog_clk_2_S_in ( p293 ) , .prog_clk_2_W_in ( p270 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_3819 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_3820 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_3821 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_3822 ) , - .prog_clk_3_W_in ( p2465 ) , .prog_clk_3_E_in ( p1234 ) , - .prog_clk_3_S_in ( p1175 ) , .prog_clk_3_N_in ( p3423 ) , + .prog_clk_3_W_in ( p3341 ) , .prog_clk_3_E_in ( p635 ) , + .prog_clk_3_S_in ( p1107 ) , .prog_clk_3_N_in ( p3607 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_3823 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_3824 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_3825 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_3826 ) , .clk_1_N_in ( p2161 ) , - .clk_1_S_in ( p99 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_3827 ) , - .clk_1_W_out ( SYNOPSYS_UNCONNECTED_3828 ) , .clk_2_N_in ( p3494 ) , - .clk_2_E_in ( p113 ) , .clk_2_S_in ( p1072 ) , .clk_2_W_in ( p2282 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_3826 ) , .clk_1_N_in ( p1206 ) , + .clk_1_S_in ( p1027 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_3827 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_3828 ) , .clk_2_N_in ( p2833 ) , + .clk_2_E_in ( p1220 ) , .clk_2_S_in ( p922 ) , .clk_2_W_in ( p3379 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_3829 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_3830 ) , .clk_2_N_out ( SYNOPSYS_UNCONNECTED_3831 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_3832 ) , .clk_3_W_in ( p2465 ) , - .clk_3_E_in ( p883 ) , .clk_3_S_in ( p260 ) , .clk_3_N_in ( p3491 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_3832 ) , .clk_3_W_in ( p3398 ) , + .clk_3_E_in ( p392 ) , .clk_3_S_in ( p223 ) , .clk_3_N_in ( p2712 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_3833 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_3834 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_3835 ) , @@ -136853,30 +140419,30 @@ sb_1__1_ sb_6__8_ ( .pReset_N_out ( pResetWires[428] ) , .pReset_W_out ( pResetWires[426] ) , .pReset_E_out ( pResetWires[429] ) , .Reset_S_in ( ResetWires[16] ) , .Reset_N_out ( ResetWires[17] ) , - .prog_clk_0_N_in ( prog_clk_0_wires[241] ) , .prog_clk_1_N_in ( p1203 ) , - .prog_clk_1_S_in ( p228 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[241] ) , .prog_clk_1_N_in ( p2028 ) , + .prog_clk_1_S_in ( p1296 ) , .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_3840 ) , .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_3841 ) , - .prog_clk_2_N_in ( p3355 ) , .prog_clk_2_E_in ( p949 ) , - .prog_clk_2_S_in ( p283 ) , .prog_clk_2_W_in ( p1390 ) , + .prog_clk_2_N_in ( p3401 ) , .prog_clk_2_E_in ( p426 ) , + .prog_clk_2_S_in ( p1131 ) , .prog_clk_2_W_in ( p57 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_3842 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_3843 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_3844 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_3845 ) , - .prog_clk_3_W_in ( p2622 ) , .prog_clk_3_E_in ( p435 ) , - .prog_clk_3_S_in ( p956 ) , .prog_clk_3_N_in ( p3349 ) , + .prog_clk_3_W_in ( p2635 ) , .prog_clk_3_E_in ( p478 ) , + .prog_clk_3_S_in ( p408 ) , .prog_clk_3_N_in ( p3389 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_3846 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_3847 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_3848 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_3849 ) , .clk_1_N_in ( p1203 ) , - .clk_1_S_in ( p709 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_3850 ) , - .clk_1_W_out ( SYNOPSYS_UNCONNECTED_3851 ) , .clk_2_N_in ( p3075 ) , - .clk_2_E_in ( p712 ) , .clk_2_S_in ( p1282 ) , .clk_2_W_in ( p2531 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_3849 ) , .clk_1_N_in ( p2028 ) , + .clk_1_S_in ( p400 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_3850 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_3851 ) , .clk_2_N_in ( p3512 ) , + .clk_2_E_in ( p186 ) , .clk_2_S_in ( p1212 ) , .clk_2_W_in ( p3188 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_3852 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_3853 ) , .clk_2_N_out ( SYNOPSYS_UNCONNECTED_3854 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_3855 ) , .clk_3_W_in ( p2622 ) , - .clk_3_E_in ( p180 ) , .clk_3_S_in ( p717 ) , .clk_3_N_in ( p3026 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_3855 ) , .clk_3_W_in ( p3271 ) , + .clk_3_E_in ( p1099 ) , .clk_3_S_in ( p101 ) , .clk_3_N_in ( p3478 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_3856 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_3857 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_3858 ) , @@ -136932,30 +140498,30 @@ sb_1__1_ sb_6__9_ ( .pReset_N_out ( pResetWires[477] ) , .pReset_W_out ( pResetWires[475] ) , .pReset_E_out ( pResetWires[478] ) , .Reset_S_in ( ResetWires[18] ) , .Reset_N_out ( ResetWires[19] ) , - .prog_clk_0_N_in ( prog_clk_0_wires[244] ) , .prog_clk_1_N_in ( p1573 ) , - .prog_clk_1_S_in ( p258 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[244] ) , .prog_clk_1_N_in ( p1556 ) , + .prog_clk_1_S_in ( p947 ) , .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_3863 ) , .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_3864 ) , - .prog_clk_2_N_in ( p3455 ) , .prog_clk_2_E_in ( p968 ) , - .prog_clk_2_S_in ( p1303 ) , .prog_clk_2_W_in ( p269 ) , + .prog_clk_2_N_in ( p3559 ) , .prog_clk_2_E_in ( p321 ) , + .prog_clk_2_S_in ( p966 ) , .prog_clk_2_W_in ( p116 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_3865 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_3866 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_3867 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_3868 ) , - .prog_clk_3_W_in ( p2149 ) , .prog_clk_3_E_in ( p219 ) , - .prog_clk_3_S_in ( p686 ) , .prog_clk_3_N_in ( p3439 ) , + .prog_clk_3_W_in ( p3226 ) , .prog_clk_3_E_in ( p832 ) , + .prog_clk_3_S_in ( p553 ) , .prog_clk_3_N_in ( p3550 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_3869 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_3870 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_3871 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_3872 ) , .clk_1_N_in ( p1573 ) , - .clk_1_S_in ( p660 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_3873 ) , - .clk_1_W_out ( SYNOPSYS_UNCONNECTED_3874 ) , .clk_2_N_in ( p2703 ) , - .clk_2_E_in ( p416 ) , .clk_2_S_in ( p1444 ) , .clk_2_W_in ( p1972 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_3872 ) , .clk_1_N_in ( p1556 ) , + .clk_1_S_in ( p407 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_3873 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_3874 ) , .clk_2_N_in ( p3399 ) , + .clk_2_E_in ( p364 ) , .clk_2_S_in ( p289 ) , .clk_2_W_in ( p3186 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_3875 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_3876 ) , .clk_2_N_out ( SYNOPSYS_UNCONNECTED_3877 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_3878 ) , .clk_3_W_in ( p2149 ) , - .clk_3_E_in ( p162 ) , .clk_3_S_in ( p482 ) , .clk_3_N_in ( p2583 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_3878 ) , .clk_3_W_in ( p3256 ) , + .clk_3_E_in ( p1076 ) , .clk_3_S_in ( p1117 ) , .clk_3_N_in ( p3392 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_3879 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_3880 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_3881 ) , @@ -137011,30 +140577,30 @@ sb_1__1_ sb_6__10_ ( .pReset_N_out ( pResetWires[526] ) , .pReset_W_out ( pResetWires[524] ) , .pReset_E_out ( pResetWires[527] ) , .Reset_S_in ( ResetWires[20] ) , .Reset_N_out ( ResetWires[21] ) , - .prog_clk_0_N_in ( prog_clk_0_wires[247] ) , .prog_clk_1_N_in ( p1876 ) , - .prog_clk_1_S_in ( p554 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[247] ) , .prog_clk_1_N_in ( p1294 ) , + .prog_clk_1_S_in ( p1219 ) , .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_3886 ) , .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_3887 ) , - .prog_clk_2_N_in ( p2974 ) , .prog_clk_2_E_in ( p1352 ) , - .prog_clk_2_S_in ( p1241 ) , .prog_clk_2_W_in ( p212 ) , + .prog_clk_2_N_in ( p3351 ) , .prog_clk_2_E_in ( p40 ) , + .prog_clk_2_S_in ( p1019 ) , .prog_clk_2_W_in ( p932 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_3888 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_3889 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_3890 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_3891 ) , - .prog_clk_3_W_in ( p3073 ) , .prog_clk_3_E_in ( p1076 ) , - .prog_clk_3_S_in ( p77 ) , .prog_clk_3_N_in ( p2918 ) , + .prog_clk_3_W_in ( p2199 ) , .prog_clk_3_E_in ( p682 ) , + .prog_clk_3_S_in ( p197 ) , .prog_clk_3_N_in ( p3295 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_3892 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_3893 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_3894 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_3895 ) , .clk_1_N_in ( p1876 ) , - .clk_1_S_in ( p306 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_3896 ) , - .clk_1_W_out ( SYNOPSYS_UNCONNECTED_3897 ) , .clk_2_N_in ( p3268 ) , - .clk_2_E_in ( p589 ) , .clk_2_S_in ( p440 ) , .clk_2_W_in ( p3012 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_3895 ) , .clk_1_N_in ( p1294 ) , + .clk_1_S_in ( p90 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_3896 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_3897 ) , .clk_2_N_in ( p2018 ) , + .clk_2_E_in ( p580 ) , .clk_2_S_in ( p537 ) , .clk_2_W_in ( p3431 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_3898 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_3899 ) , .clk_2_N_out ( SYNOPSYS_UNCONNECTED_3900 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_3901 ) , .clk_3_W_in ( p3073 ) , - .clk_3_E_in ( p156 ) , .clk_3_S_in ( p1196 ) , .clk_3_N_in ( p3218 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_3901 ) , .clk_3_W_in ( p3473 ) , + .clk_3_E_in ( p1100 ) , .clk_3_S_in ( p1274 ) , .clk_3_N_in ( p1701 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_3902 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_3903 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_3904 ) , @@ -137090,30 +140656,30 @@ sb_1__1_ sb_6__11_ ( .pReset_N_out ( pResetWires[575] ) , .pReset_W_out ( pResetWires[573] ) , .pReset_E_out ( pResetWires[576] ) , .Reset_S_in ( ResetWires[22] ) , .Reset_N_out ( ResetWires[23] ) , - .prog_clk_0_N_in ( prog_clk_0_wires[250] ) , .prog_clk_1_N_in ( p1937 ) , - .prog_clk_1_S_in ( p998 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[250] ) , .prog_clk_1_N_in ( p1802 ) , + .prog_clk_1_S_in ( p974 ) , .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_3909 ) , .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_3910 ) , - .prog_clk_2_N_in ( p3505 ) , .prog_clk_2_E_in ( p1265 ) , - .prog_clk_2_S_in ( p1098 ) , .prog_clk_2_W_in ( p94 ) , + .prog_clk_2_N_in ( p3507 ) , .prog_clk_2_E_in ( p215 ) , + .prog_clk_2_S_in ( p1238 ) , .prog_clk_2_W_in ( p796 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_3911 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_3912 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_3913 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_3914 ) , - .prog_clk_3_W_in ( p2147 ) , .prog_clk_3_E_in ( p257 ) , - .prog_clk_3_S_in ( p182 ) , .prog_clk_3_N_in ( p3504 ) , + .prog_clk_3_W_in ( p3359 ) , .prog_clk_3_E_in ( p793 ) , + .prog_clk_3_S_in ( p531 ) , .prog_clk_3_N_in ( p3491 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_3915 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_3916 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_3917 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_3918 ) , .clk_1_N_in ( p1937 ) , - .clk_1_S_in ( p469 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_3919 ) , - .clk_1_W_out ( SYNOPSYS_UNCONNECTED_3920 ) , .clk_2_N_in ( p3092 ) , - .clk_2_E_in ( p807 ) , .clk_2_S_in ( p611 ) , .clk_2_W_in ( p2028 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_3918 ) , .clk_1_N_in ( p1802 ) , + .clk_1_S_in ( p92 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_3919 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_3920 ) , .clk_2_N_in ( p3129 ) , + .clk_2_E_in ( p738 ) , .clk_2_S_in ( p1133 ) , .clk_2_W_in ( p3305 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_3921 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_3922 ) , .clk_2_N_out ( SYNOPSYS_UNCONNECTED_3923 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_3924 ) , .clk_3_W_in ( p2147 ) , - .clk_3_E_in ( p577 ) , .clk_3_S_in ( p1118 ) , .clk_3_N_in ( p3038 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_3924 ) , .clk_3_W_in ( p3244 ) , + .clk_3_E_in ( p867 ) , .clk_3_S_in ( p412 ) , .clk_3_N_in ( p3059 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_3925 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_3926 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_3927 ) , @@ -137161,27 +140727,27 @@ sb_1__1_ sb_7__1_ ( .chanx_right_out ( sb_1__1__66_chanx_right_out ) , .chany_bottom_out ( sb_1__1__66_chany_bottom_out ) , .chanx_left_out ( sb_1__1__66_chanx_left_out ) , - .ccff_tail ( sb_1__1__66_ccff_tail ) , .Test_en_S_in ( p1292 ) , + .ccff_tail ( sb_1__1__66_ccff_tail ) , .Test_en_S_in ( p1625 ) , .Test_en_N_out ( SYNOPSYS_UNCONNECTED_3930 ) , .pReset_S_in ( SYNOPSYS_UNCONNECTED_3931 ) , .pReset_E_in ( SYNOPSYS_UNCONNECTED_3932 ) , .pReset_W_in ( pResetWires[87] ) , .pReset_N_out ( pResetWires[89] ) , .pReset_W_out ( SYNOPSYS_UNCONNECTED_3933 ) , - .pReset_E_out ( pResetWires[90] ) , .Reset_S_in ( p1292 ) , + .pReset_E_out ( pResetWires[90] ) , .Reset_S_in ( p1625 ) , .Reset_N_out ( SYNOPSYS_UNCONNECTED_3934 ) , .prog_clk_0_N_in ( prog_clk_0_wires[258] ) , .prog_clk_1_N_in ( prog_clk_2_wires[74] ) , .prog_clk_1_S_in ( SYNOPSYS_UNCONNECTED_3935 ) , .prog_clk_1_E_out ( prog_clk_1_wires[127] ) , - .prog_clk_1_W_out ( prog_clk_1_wires[128] ) , .prog_clk_2_N_in ( p3498 ) , - .prog_clk_2_E_in ( p70 ) , .prog_clk_2_S_in ( p1058 ) , - .prog_clk_2_W_in ( p1344 ) , + .prog_clk_1_W_out ( prog_clk_1_wires[128] ) , .prog_clk_2_N_in ( p3533 ) , + .prog_clk_2_E_in ( p36 ) , .prog_clk_2_S_in ( p972 ) , + .prog_clk_2_W_in ( p668 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_3936 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_3937 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_3938 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_3939 ) , - .prog_clk_3_W_in ( p2691 ) , .prog_clk_3_E_in ( p1033 ) , - .prog_clk_3_S_in ( p376 ) , .prog_clk_3_N_in ( p3496 ) , + .prog_clk_3_W_in ( p3149 ) , .prog_clk_3_E_in ( p324 ) , + .prog_clk_3_S_in ( p513 ) , .prog_clk_3_N_in ( p3517 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_3940 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_3941 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_3942 ) , @@ -137189,12 +140755,12 @@ sb_1__1_ sb_7__1_ ( .clk_1_N_in ( clk_2_wires[74] ) , .clk_1_S_in ( SYNOPSYS_UNCONNECTED_3944 ) , .clk_1_E_out ( clk_1_wires[127] ) , .clk_1_W_out ( clk_1_wires[128] ) , - .clk_2_N_in ( p2256 ) , .clk_2_E_in ( p1020 ) , .clk_2_S_in ( p1201 ) , - .clk_2_W_in ( p2533 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_3945 ) , + .clk_2_N_in ( p3620 ) , .clk_2_E_in ( p843 ) , .clk_2_S_in ( p649 ) , + .clk_2_W_in ( p3208 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_3945 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_3946 ) , .clk_2_N_out ( SYNOPSYS_UNCONNECTED_3947 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_3948 ) , .clk_3_W_in ( p2691 ) , - .clk_3_E_in ( p758 ) , .clk_3_S_in ( p261 ) , .clk_3_N_in ( p1989 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_3948 ) , .clk_3_W_in ( p3277 ) , + .clk_3_E_in ( p1118 ) , .clk_3_S_in ( p1016 ) , .clk_3_N_in ( p3619 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_3949 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_3950 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_3951 ) , @@ -137242,16 +140808,16 @@ sb_1__1_ sb_7__2_ ( .chanx_right_out ( sb_1__1__67_chanx_right_out ) , .chany_bottom_out ( sb_1__1__67_chany_bottom_out ) , .chanx_left_out ( sb_1__1__67_chanx_left_out ) , - .ccff_tail ( sb_1__1__67_ccff_tail ) , .Test_en_S_in ( p3099 ) , + .ccff_tail ( sb_1__1__67_ccff_tail ) , .Test_en_S_in ( p2520 ) , .Test_en_N_out ( SYNOPSYS_UNCONNECTED_3954 ) , .pReset_S_in ( SYNOPSYS_UNCONNECTED_3955 ) , .pReset_E_in ( SYNOPSYS_UNCONNECTED_3956 ) , .pReset_W_in ( pResetWires[136] ) , .pReset_N_out ( pResetWires[138] ) , .pReset_W_out ( SYNOPSYS_UNCONNECTED_3957 ) , - .pReset_E_out ( pResetWires[139] ) , .Reset_S_in ( p3099 ) , + .pReset_E_out ( pResetWires[139] ) , .Reset_S_in ( p2520 ) , .Reset_N_out ( SYNOPSYS_UNCONNECTED_3958 ) , - .prog_clk_0_N_in ( prog_clk_0_wires[261] ) , .prog_clk_1_N_in ( p1502 ) , - .prog_clk_1_S_in ( p381 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[261] ) , .prog_clk_1_N_in ( p1871 ) , + .prog_clk_1_S_in ( p334 ) , .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_3959 ) , .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_3960 ) , .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_3961 ) , @@ -137262,13 +140828,13 @@ sb_1__1_ sb_7__2_ ( .prog_clk_2_S_out ( prog_clk_2_wires[73] ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_3965 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_3966 ) , - .prog_clk_3_W_in ( p1872 ) , .prog_clk_3_E_in ( p806 ) , - .prog_clk_3_S_in ( p705 ) , .prog_clk_3_N_in ( p600 ) , + .prog_clk_3_W_in ( p1599 ) , .prog_clk_3_E_in ( p72 ) , + .prog_clk_3_S_in ( p878 ) , .prog_clk_3_N_in ( p716 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_3967 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_3968 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_3969 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_3970 ) , .clk_1_N_in ( p1502 ) , - .clk_1_S_in ( p434 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_3971 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_3970 ) , .clk_1_N_in ( p1871 ) , + .clk_1_S_in ( p1116 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_3971 ) , .clk_1_W_out ( SYNOPSYS_UNCONNECTED_3972 ) , .clk_2_N_in ( SYNOPSYS_UNCONNECTED_3973 ) , .clk_2_E_in ( clk_2_wires[72] ) , @@ -137277,8 +140843,8 @@ sb_1__1_ sb_7__2_ ( .clk_2_W_out ( SYNOPSYS_UNCONNECTED_3976 ) , .clk_2_S_out ( clk_2_wires[73] ) , .clk_2_N_out ( SYNOPSYS_UNCONNECTED_3977 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_3978 ) , .clk_3_W_in ( p1872 ) , - .clk_3_E_in ( p1987 ) , .clk_3_S_in ( p3025 ) , .clk_3_N_in ( p127 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_3978 ) , .clk_3_W_in ( p1599 ) , + .clk_3_E_in ( p691 ) , .clk_3_S_in ( p2429 ) , .clk_3_N_in ( p1663 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_3979 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_3980 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_3981 ) , @@ -137326,27 +140892,27 @@ sb_1__1_ sb_7__3_ ( .chanx_right_out ( sb_1__1__68_chanx_right_out ) , .chany_bottom_out ( sb_1__1__68_chany_bottom_out ) , .chanx_left_out ( sb_1__1__68_chanx_left_out ) , - .ccff_tail ( sb_1__1__68_ccff_tail ) , .Test_en_S_in ( p2642 ) , + .ccff_tail ( sb_1__1__68_ccff_tail ) , .Test_en_S_in ( p2021 ) , .Test_en_N_out ( SYNOPSYS_UNCONNECTED_3984 ) , .pReset_S_in ( SYNOPSYS_UNCONNECTED_3985 ) , .pReset_E_in ( SYNOPSYS_UNCONNECTED_3986 ) , .pReset_W_in ( pResetWires[185] ) , .pReset_N_out ( pResetWires[187] ) , .pReset_W_out ( SYNOPSYS_UNCONNECTED_3987 ) , - .pReset_E_out ( pResetWires[188] ) , .Reset_S_in ( p3173 ) , + .pReset_E_out ( pResetWires[188] ) , .Reset_S_in ( p2021 ) , .Reset_N_out ( SYNOPSYS_UNCONNECTED_3988 ) , .prog_clk_0_N_in ( prog_clk_0_wires[264] ) , .prog_clk_1_N_in ( prog_clk_2_wires[85] ) , .prog_clk_1_S_in ( SYNOPSYS_UNCONNECTED_3989 ) , .prog_clk_1_E_out ( prog_clk_1_wires[134] ) , - .prog_clk_1_W_out ( prog_clk_1_wires[135] ) , .prog_clk_2_N_in ( p3468 ) , - .prog_clk_2_E_in ( p948 ) , .prog_clk_2_S_in ( p1142 ) , - .prog_clk_2_W_in ( p170 ) , + .prog_clk_1_W_out ( prog_clk_1_wires[135] ) , .prog_clk_2_N_in ( p3603 ) , + .prog_clk_2_E_in ( p382 ) , .prog_clk_2_S_in ( p1038 ) , + .prog_clk_2_W_in ( p762 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_3990 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_3991 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_3992 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_3993 ) , - .prog_clk_3_W_in ( p2654 ) , .prog_clk_3_E_in ( p84 ) , - .prog_clk_3_S_in ( p621 ) , .prog_clk_3_N_in ( p3460 ) , + .prog_clk_3_W_in ( p3105 ) , .prog_clk_3_E_in ( p705 ) , + .prog_clk_3_S_in ( p226 ) , .prog_clk_3_N_in ( p3601 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_3994 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_3995 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_3996 ) , @@ -137354,12 +140920,12 @@ sb_1__1_ sb_7__3_ ( .clk_1_N_in ( clk_2_wires[85] ) , .clk_1_S_in ( SYNOPSYS_UNCONNECTED_3998 ) , .clk_1_E_out ( clk_1_wires[134] ) , .clk_1_W_out ( clk_1_wires[135] ) , - .clk_2_N_in ( p3495 ) , .clk_2_E_in ( p906 ) , .clk_2_S_in ( p3126 ) , - .clk_2_W_in ( p2546 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_3999 ) , + .clk_2_N_in ( p3154 ) , .clk_2_E_in ( p87 ) , .clk_2_S_in ( p275 ) , + .clk_2_W_in ( p3073 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_3999 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_4000 ) , .clk_2_N_out ( SYNOPSYS_UNCONNECTED_4001 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_4002 ) , .clk_3_W_in ( p2654 ) , - .clk_3_E_in ( p863 ) , .clk_3_S_in ( p388 ) , .clk_3_N_in ( p3492 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_4002 ) , .clk_3_W_in ( p3113 ) , + .clk_3_E_in ( p894 ) , .clk_3_S_in ( p1770 ) , .clk_3_N_in ( p3048 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_4003 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4004 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_4005 ) , @@ -137407,16 +140973,16 @@ sb_1__1_ sb_7__4_ ( .chanx_right_out ( sb_1__1__69_chanx_right_out ) , .chany_bottom_out ( sb_1__1__69_chany_bottom_out ) , .chanx_left_out ( sb_1__1__69_chanx_left_out ) , - .ccff_tail ( sb_1__1__69_ccff_tail ) , .Test_en_S_in ( p3322 ) , + .ccff_tail ( sb_1__1__69_ccff_tail ) , .Test_en_S_in ( p1651 ) , .Test_en_N_out ( SYNOPSYS_UNCONNECTED_4008 ) , .pReset_S_in ( SYNOPSYS_UNCONNECTED_4009 ) , .pReset_E_in ( SYNOPSYS_UNCONNECTED_4010 ) , .pReset_W_in ( pResetWires[234] ) , .pReset_N_out ( pResetWires[236] ) , .pReset_W_out ( SYNOPSYS_UNCONNECTED_4011 ) , - .pReset_E_out ( pResetWires[237] ) , .Reset_S_in ( p3325 ) , + .pReset_E_out ( pResetWires[237] ) , .Reset_S_in ( p1651 ) , .Reset_N_out ( SYNOPSYS_UNCONNECTED_4012 ) , - .prog_clk_0_N_in ( prog_clk_0_wires[267] ) , .prog_clk_1_N_in ( p2162 ) , - .prog_clk_1_S_in ( p650 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[267] ) , .prog_clk_1_N_in ( p1932 ) , + .prog_clk_1_S_in ( p956 ) , .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_4013 ) , .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_4014 ) , .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_4015 ) , @@ -137427,13 +140993,13 @@ sb_1__1_ sb_7__4_ ( .prog_clk_2_S_out ( prog_clk_2_wires[84] ) , .prog_clk_2_N_out ( prog_clk_2_wires[82] ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_4019 ) , - .prog_clk_3_W_in ( p1809 ) , .prog_clk_3_E_in ( p881 ) , - .prog_clk_3_S_in ( p46 ) , .prog_clk_3_N_in ( p1976 ) , + .prog_clk_3_W_in ( p2314 ) , .prog_clk_3_E_in ( p132 ) , + .prog_clk_3_S_in ( p3 ) , .prog_clk_3_N_in ( p2102 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_4020 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4021 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_4022 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_4023 ) , .clk_1_N_in ( p2162 ) , - .clk_1_S_in ( p163 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_4024 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_4023 ) , .clk_1_N_in ( p1932 ) , + .clk_1_S_in ( p252 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_4024 ) , .clk_1_W_out ( SYNOPSYS_UNCONNECTED_4025 ) , .clk_2_N_in ( SYNOPSYS_UNCONNECTED_4026 ) , .clk_2_E_in ( clk_2_wires[81] ) , @@ -137441,8 +141007,8 @@ sb_1__1_ sb_7__4_ ( .clk_2_W_in ( SYNOPSYS_UNCONNECTED_4028 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_4029 ) , .clk_2_S_out ( clk_2_wires[84] ) , .clk_2_N_out ( clk_2_wires[82] ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_4030 ) , .clk_3_W_in ( p1809 ) , - .clk_3_E_in ( p1702 ) , .clk_3_S_in ( p3292 ) , .clk_3_N_in ( p2021 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_4030 ) , .clk_3_W_in ( p2314 ) , + .clk_3_E_in ( p778 ) , .clk_3_S_in ( p797 ) , .clk_3_N_in ( p1773 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_4031 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4032 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_4033 ) , @@ -137490,40 +141056,40 @@ sb_1__1_ sb_7__5_ ( .chanx_right_out ( sb_1__1__70_chanx_right_out ) , .chany_bottom_out ( sb_1__1__70_chany_bottom_out ) , .chanx_left_out ( sb_1__1__70_chanx_left_out ) , - .ccff_tail ( sb_1__1__70_ccff_tail ) , .Test_en_S_in ( p2791 ) , + .ccff_tail ( sb_1__1__70_ccff_tail ) , .Test_en_S_in ( p2836 ) , .Test_en_N_out ( SYNOPSYS_UNCONNECTED_4036 ) , .pReset_S_in ( SYNOPSYS_UNCONNECTED_4037 ) , .pReset_E_in ( SYNOPSYS_UNCONNECTED_4038 ) , .pReset_W_in ( pResetWires[283] ) , .pReset_N_out ( pResetWires[285] ) , .pReset_W_out ( SYNOPSYS_UNCONNECTED_4039 ) , - .pReset_E_out ( pResetWires[286] ) , .Reset_S_in ( p2791 ) , + .pReset_E_out ( pResetWires[286] ) , .Reset_S_in ( p2836 ) , .Reset_N_out ( SYNOPSYS_UNCONNECTED_4040 ) , .prog_clk_0_N_in ( prog_clk_0_wires[270] ) , .prog_clk_1_N_in ( SYNOPSYS_UNCONNECTED_4041 ) , .prog_clk_1_S_in ( prog_clk_2_wires[83] ) , .prog_clk_1_E_out ( prog_clk_1_wires[141] ) , - .prog_clk_1_W_out ( prog_clk_1_wires[142] ) , .prog_clk_2_N_in ( p3434 ) , - .prog_clk_2_E_in ( p1260 ) , .prog_clk_2_S_in ( p583 ) , - .prog_clk_2_W_in ( p1070 ) , + .prog_clk_1_W_out ( prog_clk_1_wires[142] ) , .prog_clk_2_N_in ( p3604 ) , + .prog_clk_2_E_in ( p333 ) , .prog_clk_2_S_in ( p88 ) , + .prog_clk_2_W_in ( p19 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_4042 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_4043 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_4044 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_4045 ) , - .prog_clk_3_W_in ( p2617 ) , .prog_clk_3_E_in ( p797 ) , - .prog_clk_3_S_in ( p1186 ) , .prog_clk_3_N_in ( p3424 ) , + .prog_clk_3_W_in ( p2796 ) , .prog_clk_3_E_in ( p518 ) , + .prog_clk_3_S_in ( p944 ) , .prog_clk_3_N_in ( p3599 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_4046 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4047 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_4048 ) , .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_4049 ) , .clk_1_N_in ( SYNOPSYS_UNCONNECTED_4050 ) , .clk_1_S_in ( clk_2_wires[83] ) , .clk_1_E_out ( clk_1_wires[141] ) , - .clk_1_W_out ( clk_1_wires[142] ) , .clk_2_N_in ( p3204 ) , - .clk_2_E_in ( p18 ) , .clk_2_S_in ( p2736 ) , .clk_2_W_in ( p2544 ) , + .clk_1_W_out ( clk_1_wires[142] ) , .clk_2_N_in ( p3497 ) , + .clk_2_E_in ( p957 ) , .clk_2_S_in ( p1224 ) , .clk_2_W_in ( p3039 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_4051 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_4052 ) , .clk_2_N_out ( SYNOPSYS_UNCONNECTED_4053 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_4054 ) , .clk_3_W_in ( p2617 ) , - .clk_3_E_in ( p812 ) , .clk_3_S_in ( p11 ) , .clk_3_N_in ( p3153 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_4054 ) , .clk_3_W_in ( p3118 ) , + .clk_3_E_in ( p421 ) , .clk_3_S_in ( p2647 ) , .clk_3_N_in ( p3495 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_4055 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4056 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_4057 ) , @@ -137571,20 +141137,20 @@ sb_1__1_ sb_7__6_ ( .chanx_right_out ( sb_1__1__71_chanx_right_out ) , .chany_bottom_out ( sb_1__1__71_chany_bottom_out ) , .chanx_left_out ( sb_1__1__71_chanx_left_out ) , - .ccff_tail ( sb_1__1__71_ccff_tail ) , .Test_en_S_in ( p2947 ) , + .ccff_tail ( sb_1__1__71_ccff_tail ) , .Test_en_S_in ( p2212 ) , .Test_en_N_out ( SYNOPSYS_UNCONNECTED_4060 ) , .pReset_S_in ( SYNOPSYS_UNCONNECTED_4061 ) , .pReset_E_in ( SYNOPSYS_UNCONNECTED_4062 ) , .pReset_W_in ( pResetWires[332] ) , .pReset_N_out ( pResetWires[334] ) , .pReset_W_out ( SYNOPSYS_UNCONNECTED_4063 ) , - .pReset_E_out ( pResetWires[335] ) , .Reset_S_in ( p3323 ) , + .pReset_E_out ( pResetWires[335] ) , .Reset_S_in ( p2212 ) , .Reset_N_out ( SYNOPSYS_UNCONNECTED_4064 ) , - .prog_clk_0_N_in ( prog_clk_0_wires[273] ) , .prog_clk_1_N_in ( p1420 ) , - .prog_clk_1_S_in ( p516 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[273] ) , .prog_clk_1_N_in ( p1408 ) , + .prog_clk_1_S_in ( p42 ) , .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_4065 ) , .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_4066 ) , - .prog_clk_2_N_in ( p2497 ) , .prog_clk_2_E_in ( p845 ) , - .prog_clk_2_S_in ( p902 ) , .prog_clk_2_W_in ( p450 ) , + .prog_clk_2_N_in ( p1935 ) , .prog_clk_2_E_in ( p13 ) , + .prog_clk_2_S_in ( p744 ) , .prog_clk_2_W_in ( p860 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_4067 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_4068 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_4069 ) , @@ -137596,10 +141162,10 @@ sb_1__1_ sb_7__6_ ( .prog_clk_3_E_out ( prog_clk_3_wires[4] ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4074 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_4075 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_4076 ) , .clk_1_N_in ( p1420 ) , - .clk_1_S_in ( p915 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_4077 ) , - .clk_1_W_out ( SYNOPSYS_UNCONNECTED_4078 ) , .clk_2_N_in ( p2497 ) , - .clk_2_E_in ( p175 ) , .clk_2_S_in ( p3283 ) , .clk_2_W_in ( p137 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_4076 ) , .clk_1_N_in ( p1408 ) , + .clk_1_S_in ( p1266 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_4077 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_4078 ) , .clk_2_N_in ( p1449 ) , + .clk_2_E_in ( p630 ) , .clk_2_S_in ( p2097 ) , .clk_2_W_in ( p521 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_4079 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_4080 ) , .clk_2_N_out ( SYNOPSYS_UNCONNECTED_4081 ) , @@ -137655,27 +141221,27 @@ sb_1__1_ sb_7__7_ ( .chanx_right_out ( sb_1__1__72_chanx_right_out ) , .chany_bottom_out ( sb_1__1__72_chany_bottom_out ) , .chanx_left_out ( sb_1__1__72_chanx_left_out ) , - .ccff_tail ( sb_1__1__72_ccff_tail ) , .Test_en_S_in ( p3072 ) , + .ccff_tail ( sb_1__1__72_ccff_tail ) , .Test_en_S_in ( p1560 ) , .Test_en_N_out ( SYNOPSYS_UNCONNECTED_4090 ) , .pReset_S_in ( SYNOPSYS_UNCONNECTED_4091 ) , .pReset_E_in ( SYNOPSYS_UNCONNECTED_4092 ) , .pReset_W_in ( pResetWires[381] ) , .pReset_N_out ( pResetWires[383] ) , .pReset_W_out ( SYNOPSYS_UNCONNECTED_4093 ) , - .pReset_E_out ( pResetWires[384] ) , .Reset_S_in ( p3072 ) , + .pReset_E_out ( pResetWires[384] ) , .Reset_S_in ( p1560 ) , .Reset_N_out ( SYNOPSYS_UNCONNECTED_4094 ) , .prog_clk_0_N_in ( prog_clk_0_wires[276] ) , .prog_clk_1_N_in ( prog_clk_2_wires[98] ) , .prog_clk_1_S_in ( SYNOPSYS_UNCONNECTED_4095 ) , .prog_clk_1_E_out ( prog_clk_1_wires[148] ) , - .prog_clk_1_W_out ( prog_clk_1_wires[149] ) , .prog_clk_2_N_in ( p3433 ) , - .prog_clk_2_E_in ( p616 ) , .prog_clk_2_S_in ( p206 ) , - .prog_clk_2_W_in ( p1081 ) , + .prog_clk_1_W_out ( prog_clk_1_wires[149] ) , .prog_clk_2_N_in ( p3505 ) , + .prog_clk_2_E_in ( p584 ) , .prog_clk_2_S_in ( p1182 ) , + .prog_clk_2_W_in ( p804 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_4096 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_4097 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_4098 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_4099 ) , - .prog_clk_3_W_in ( p2387 ) , .prog_clk_3_E_in ( p1018 ) , - .prog_clk_3_S_in ( p985 ) , .prog_clk_3_N_in ( p3413 ) , + .prog_clk_3_W_in ( p2546 ) , .prog_clk_3_E_in ( p933 ) , + .prog_clk_3_S_in ( p386 ) , .prog_clk_3_N_in ( p3486 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_4100 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4101 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_4102 ) , @@ -137683,12 +141249,12 @@ sb_1__1_ sb_7__7_ ( .clk_1_N_in ( clk_2_wires[98] ) , .clk_1_S_in ( SYNOPSYS_UNCONNECTED_4104 ) , .clk_1_E_out ( clk_1_wires[148] ) , .clk_1_W_out ( clk_1_wires[149] ) , - .clk_2_N_in ( p3396 ) , .clk_2_E_in ( p580 ) , .clk_2_S_in ( p2999 ) , - .clk_2_W_in ( p2284 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_4105 ) , + .clk_2_N_in ( p3331 ) , .clk_2_E_in ( p126 ) , .clk_2_S_in ( p1248 ) , + .clk_2_W_in ( p3427 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_4105 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_4106 ) , .clk_2_N_out ( SYNOPSYS_UNCONNECTED_4107 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_4108 ) , .clk_3_W_in ( p2387 ) , - .clk_3_E_in ( p884 ) , .clk_3_S_in ( p1359 ) , .clk_3_N_in ( p3389 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_4108 ) , .clk_3_W_in ( p3463 ) , + .clk_3_E_in ( p1010 ) , .clk_3_S_in ( p790 ) , .clk_3_N_in ( p3294 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_4109 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4110 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_4111 ) , @@ -137736,16 +141302,16 @@ sb_1__1_ sb_7__8_ ( .chanx_right_out ( sb_1__1__73_chanx_right_out ) , .chany_bottom_out ( sb_1__1__73_chany_bottom_out ) , .chanx_left_out ( sb_1__1__73_chanx_left_out ) , - .ccff_tail ( sb_1__1__73_ccff_tail ) , .Test_en_S_in ( p2437 ) , + .ccff_tail ( sb_1__1__73_ccff_tail ) , .Test_en_S_in ( p1415 ) , .Test_en_N_out ( SYNOPSYS_UNCONNECTED_4114 ) , .pReset_S_in ( SYNOPSYS_UNCONNECTED_4115 ) , .pReset_E_in ( SYNOPSYS_UNCONNECTED_4116 ) , .pReset_W_in ( pResetWires[430] ) , .pReset_N_out ( pResetWires[432] ) , .pReset_W_out ( SYNOPSYS_UNCONNECTED_4117 ) , - .pReset_E_out ( pResetWires[433] ) , .Reset_S_in ( p2437 ) , + .pReset_E_out ( pResetWires[433] ) , .Reset_S_in ( p1415 ) , .Reset_N_out ( SYNOPSYS_UNCONNECTED_4118 ) , - .prog_clk_0_N_in ( prog_clk_0_wires[279] ) , .prog_clk_1_N_in ( p1853 ) , - .prog_clk_1_S_in ( p703 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[279] ) , .prog_clk_1_N_in ( p1307 ) , + .prog_clk_1_S_in ( p427 ) , .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_4119 ) , .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_4120 ) , .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_4121 ) , @@ -137756,13 +141322,13 @@ sb_1__1_ sb_7__8_ ( .prog_clk_2_S_out ( prog_clk_2_wires[97] ) , .prog_clk_2_N_out ( prog_clk_2_wires[95] ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_4125 ) , - .prog_clk_3_W_in ( p2263 ) , .prog_clk_3_E_in ( p959 ) , - .prog_clk_3_S_in ( p581 ) , .prog_clk_3_N_in ( p85 ) , + .prog_clk_3_W_in ( p1272 ) , .prog_clk_3_E_in ( p296 ) , + .prog_clk_3_S_in ( p151 ) , .prog_clk_3_N_in ( p449 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_4126 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4127 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_4128 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_4129 ) , .clk_1_N_in ( p1853 ) , - .clk_1_S_in ( p286 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_4130 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_4129 ) , .clk_1_N_in ( p1307 ) , + .clk_1_S_in ( p1093 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_4130 ) , .clk_1_W_out ( SYNOPSYS_UNCONNECTED_4131 ) , .clk_2_N_in ( SYNOPSYS_UNCONNECTED_4132 ) , .clk_2_E_in ( clk_2_wires[94] ) , @@ -137770,8 +141336,8 @@ sb_1__1_ sb_7__8_ ( .clk_2_W_in ( SYNOPSYS_UNCONNECTED_4134 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_4135 ) , .clk_2_S_out ( clk_2_wires[97] ) , .clk_2_N_out ( clk_2_wires[95] ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_4136 ) , .clk_3_W_in ( p2263 ) , - .clk_3_E_in ( p161 ) , .clk_3_S_in ( p2269 ) , .clk_3_N_in ( p1640 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_4136 ) , .clk_3_W_in ( p1272 ) , + .clk_3_E_in ( p703 ) , .clk_3_S_in ( p582 ) , .clk_3_N_in ( p47 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_4137 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4138 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_4139 ) , @@ -137819,40 +141385,40 @@ sb_1__1_ sb_7__9_ ( .chanx_right_out ( sb_1__1__74_chanx_right_out ) , .chany_bottom_out ( sb_1__1__74_chany_bottom_out ) , .chanx_left_out ( sb_1__1__74_chanx_left_out ) , - .ccff_tail ( sb_1__1__74_ccff_tail ) , .Test_en_S_in ( p3186 ) , + .ccff_tail ( sb_1__1__74_ccff_tail ) , .Test_en_S_in ( p1925 ) , .Test_en_N_out ( SYNOPSYS_UNCONNECTED_4142 ) , .pReset_S_in ( SYNOPSYS_UNCONNECTED_4143 ) , .pReset_E_in ( SYNOPSYS_UNCONNECTED_4144 ) , .pReset_W_in ( pResetWires[479] ) , .pReset_N_out ( pResetWires[481] ) , .pReset_W_out ( SYNOPSYS_UNCONNECTED_4145 ) , - .pReset_E_out ( pResetWires[482] ) , .Reset_S_in ( p3186 ) , + .pReset_E_out ( pResetWires[482] ) , .Reset_S_in ( p1925 ) , .Reset_N_out ( SYNOPSYS_UNCONNECTED_4146 ) , .prog_clk_0_N_in ( prog_clk_0_wires[282] ) , .prog_clk_1_N_in ( SYNOPSYS_UNCONNECTED_4147 ) , .prog_clk_1_S_in ( prog_clk_2_wires[96] ) , .prog_clk_1_E_out ( prog_clk_1_wires[155] ) , - .prog_clk_1_W_out ( prog_clk_1_wires[156] ) , .prog_clk_2_N_in ( p3095 ) , - .prog_clk_2_E_in ( p1188 ) , .prog_clk_2_S_in ( p1008 ) , - .prog_clk_2_W_in ( p1119 ) , + .prog_clk_1_W_out ( prog_clk_1_wires[156] ) , .prog_clk_2_N_in ( p1540 ) , + .prog_clk_2_E_in ( p609 ) , .prog_clk_2_S_in ( p826 ) , + .prog_clk_2_W_in ( p952 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_4148 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_4149 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_4150 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_4151 ) , - .prog_clk_3_W_in ( p2854 ) , .prog_clk_3_E_in ( p407 ) , - .prog_clk_3_S_in ( p471 ) , .prog_clk_3_N_in ( p3041 ) , + .prog_clk_3_W_in ( p2631 ) , .prog_clk_3_E_in ( p683 ) , + .prog_clk_3_S_in ( p983 ) , .prog_clk_3_N_in ( p583 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_4152 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4153 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_4154 ) , .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_4155 ) , .clk_1_N_in ( SYNOPSYS_UNCONNECTED_4156 ) , .clk_1_S_in ( clk_2_wires[96] ) , .clk_1_E_out ( clk_1_wires[155] ) , - .clk_1_W_out ( clk_1_wires[156] ) , .clk_2_N_in ( p3057 ) , - .clk_2_E_in ( p917 ) , .clk_2_S_in ( p3114 ) , .clk_2_W_in ( p2723 ) , + .clk_1_W_out ( clk_1_wires[156] ) , .clk_2_N_in ( p3572 ) , + .clk_2_E_in ( p1366 ) , .clk_2_S_in ( p1172 ) , .clk_2_W_in ( p3086 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_4157 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_4158 ) , .clk_2_N_out ( SYNOPSYS_UNCONNECTED_4159 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_4160 ) , .clk_3_W_in ( p2854 ) , - .clk_3_E_in ( p48 ) , .clk_3_S_in ( p240 ) , .clk_3_N_in ( p3015 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_4160 ) , .clk_3_W_in ( p3159 ) , + .clk_3_E_in ( p303 ) , .clk_3_S_in ( p1670 ) , .clk_3_N_in ( p3563 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_4161 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4162 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_4163 ) , @@ -137900,16 +141466,16 @@ sb_1__1_ sb_7__10_ ( .chanx_right_out ( sb_1__1__75_chanx_right_out ) , .chany_bottom_out ( sb_1__1__75_chany_bottom_out ) , .chanx_left_out ( sb_1__1__75_chanx_left_out ) , - .ccff_tail ( sb_1__1__75_ccff_tail ) , .Test_en_S_in ( p3050 ) , + .ccff_tail ( sb_1__1__75_ccff_tail ) , .Test_en_S_in ( p1552 ) , .Test_en_N_out ( SYNOPSYS_UNCONNECTED_4166 ) , .pReset_S_in ( SYNOPSYS_UNCONNECTED_4167 ) , .pReset_E_in ( SYNOPSYS_UNCONNECTED_4168 ) , .pReset_W_in ( pResetWires[528] ) , .pReset_N_out ( pResetWires[530] ) , .pReset_W_out ( SYNOPSYS_UNCONNECTED_4169 ) , - .pReset_E_out ( pResetWires[531] ) , .Reset_S_in ( p3068 ) , + .pReset_E_out ( pResetWires[531] ) , .Reset_S_in ( p1552 ) , .Reset_N_out ( SYNOPSYS_UNCONNECTED_4170 ) , - .prog_clk_0_N_in ( prog_clk_0_wires[285] ) , .prog_clk_1_N_in ( p1350 ) , - .prog_clk_1_S_in ( p923 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[285] ) , .prog_clk_1_N_in ( p1515 ) , + .prog_clk_1_S_in ( p388 ) , .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_4171 ) , .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_4172 ) , .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_4173 ) , @@ -137920,13 +141486,13 @@ sb_1__1_ sb_7__10_ ( .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_4177 ) , .prog_clk_2_N_out ( prog_clk_2_wires[108] ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_4178 ) , - .prog_clk_3_W_in ( p1253 ) , .prog_clk_3_E_in ( p784 ) , - .prog_clk_3_S_in ( p510 ) , .prog_clk_3_N_in ( p1622 ) , + .prog_clk_3_W_in ( p1645 ) , .prog_clk_3_E_in ( p170 ) , + .prog_clk_3_S_in ( p881 ) , .prog_clk_3_N_in ( p764 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_4179 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4180 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_4181 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_4182 ) , .clk_1_N_in ( p1350 ) , - .clk_1_S_in ( p37 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_4183 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_4182 ) , .clk_1_N_in ( p1515 ) , + .clk_1_S_in ( p1078 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_4183 ) , .clk_1_W_out ( SYNOPSYS_UNCONNECTED_4184 ) , .clk_2_N_in ( SYNOPSYS_UNCONNECTED_4185 ) , .clk_2_E_in ( clk_2_wires[107] ) , @@ -137935,8 +141501,8 @@ sb_1__1_ sb_7__10_ ( .clk_2_W_out ( SYNOPSYS_UNCONNECTED_4188 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_4189 ) , .clk_2_N_out ( clk_2_wires[108] ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_4190 ) , .clk_3_W_in ( p1253 ) , - .clk_3_E_in ( p1698 ) , .clk_3_S_in ( p3024 ) , .clk_3_N_in ( p197 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_4190 ) , .clk_3_W_in ( p1423 ) , + .clk_3_E_in ( p792 ) , .clk_3_S_in ( p717 ) , .clk_3_N_in ( p203 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_4191 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4192 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_4193 ) , @@ -137984,40 +141550,40 @@ sb_1__1_ sb_7__11_ ( .chanx_right_out ( sb_1__1__76_chanx_right_out ) , .chany_bottom_out ( sb_1__1__76_chany_bottom_out ) , .chanx_left_out ( sb_1__1__76_chanx_left_out ) , - .ccff_tail ( sb_1__1__76_ccff_tail ) , .Test_en_S_in ( p2633 ) , + .ccff_tail ( sb_1__1__76_ccff_tail ) , .Test_en_S_in ( p1549 ) , .Test_en_N_out ( SYNOPSYS_UNCONNECTED_4196 ) , .pReset_S_in ( SYNOPSYS_UNCONNECTED_4197 ) , .pReset_E_in ( SYNOPSYS_UNCONNECTED_4198 ) , .pReset_W_in ( pResetWires[577] ) , .pReset_N_out ( pResetWires[579] ) , .pReset_W_out ( SYNOPSYS_UNCONNECTED_4199 ) , - .pReset_E_out ( pResetWires[580] ) , .Reset_S_in ( p2633 ) , + .pReset_E_out ( pResetWires[580] ) , .Reset_S_in ( p1549 ) , .Reset_N_out ( SYNOPSYS_UNCONNECTED_4200 ) , .prog_clk_0_N_in ( prog_clk_0_wires[288] ) , .prog_clk_1_N_in ( SYNOPSYS_UNCONNECTED_4201 ) , .prog_clk_1_S_in ( prog_clk_2_wires[109] ) , .prog_clk_1_E_out ( prog_clk_1_wires[162] ) , - .prog_clk_1_W_out ( prog_clk_1_wires[163] ) , .prog_clk_2_N_in ( p3507 ) , - .prog_clk_2_E_in ( p38 ) , .prog_clk_2_S_in ( p1060 ) , - .prog_clk_2_W_in ( p555 ) , + .prog_clk_1_W_out ( prog_clk_1_wires[163] ) , .prog_clk_2_N_in ( p3534 ) , + .prog_clk_2_E_in ( p276 ) , .prog_clk_2_S_in ( p430 ) , + .prog_clk_2_W_in ( p687 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_4202 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_4203 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_4204 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_4205 ) , - .prog_clk_3_W_in ( p2522 ) , .prog_clk_3_E_in ( p715 ) , - .prog_clk_3_S_in ( p631 ) , .prog_clk_3_N_in ( p3506 ) , + .prog_clk_3_W_in ( p3240 ) , .prog_clk_3_E_in ( p810 ) , + .prog_clk_3_S_in ( p1009 ) , .prog_clk_3_N_in ( p3524 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_4206 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4207 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_4208 ) , .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_4209 ) , .clk_1_N_in ( SYNOPSYS_UNCONNECTED_4210 ) , .clk_1_S_in ( clk_2_wires[109] ) , .clk_1_E_out ( clk_1_wires[162] ) , - .clk_1_W_out ( clk_1_wires[163] ) , .clk_2_N_in ( p2937 ) , - .clk_2_E_in ( p1042 ) , .clk_2_S_in ( p2561 ) , .clk_2_W_in ( p2309 ) , + .clk_1_W_out ( clk_1_wires[163] ) , .clk_2_N_in ( p3461 ) , + .clk_2_E_in ( p1175 ) , .clk_2_S_in ( p441 ) , .clk_2_W_in ( p3282 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_4211 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_4212 ) , .clk_2_N_out ( SYNOPSYS_UNCONNECTED_4213 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_4214 ) , .clk_3_W_in ( p2522 ) , - .clk_3_E_in ( p966 ) , .clk_3_S_in ( p277 ) , .clk_3_N_in ( p2916 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_4214 ) , .clk_3_W_in ( p3360 ) , + .clk_3_E_in ( p476 ) , .clk_3_S_in ( p1194 ) , .clk_3_N_in ( p3440 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_4215 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4216 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_4217 ) , @@ -138065,38 +141631,38 @@ sb_1__1_ sb_8__1_ ( .chanx_right_out ( sb_1__1__77_chanx_right_out ) , .chany_bottom_out ( sb_1__1__77_chany_bottom_out ) , .chanx_left_out ( sb_1__1__77_chanx_left_out ) , - .ccff_tail ( sb_1__1__77_ccff_tail ) , .Test_en_S_in ( p3200 ) , + .ccff_tail ( sb_1__1__77_ccff_tail ) , .Test_en_S_in ( p1426 ) , .Test_en_N_out ( SYNOPSYS_UNCONNECTED_4220 ) , .pReset_S_in ( SYNOPSYS_UNCONNECTED_4221 ) , .pReset_E_in ( SYNOPSYS_UNCONNECTED_4222 ) , .pReset_W_in ( pResetWires[91] ) , .pReset_N_out ( pResetWires[93] ) , .pReset_W_out ( SYNOPSYS_UNCONNECTED_4223 ) , - .pReset_E_out ( pResetWires[94] ) , .Reset_S_in ( p3457 ) , + .pReset_E_out ( pResetWires[94] ) , .Reset_S_in ( p1426 ) , .Reset_N_out ( SYNOPSYS_UNCONNECTED_4224 ) , - .prog_clk_0_N_in ( prog_clk_0_wires[296] ) , .prog_clk_1_N_in ( p1389 ) , - .prog_clk_1_S_in ( p856 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[296] ) , .prog_clk_1_N_in ( p1581 ) , + .prog_clk_1_S_in ( p973 ) , .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_4225 ) , .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_4226 ) , - .prog_clk_2_N_in ( p3375 ) , .prog_clk_2_E_in ( p957 ) , - .prog_clk_2_S_in ( p121 ) , .prog_clk_2_W_in ( p373 ) , + .prog_clk_2_N_in ( p3542 ) , .prog_clk_2_E_in ( p374 ) , + .prog_clk_2_S_in ( p510 ) , .prog_clk_2_W_in ( p838 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_4227 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_4228 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_4229 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_4230 ) , - .prog_clk_3_W_in ( p1760 ) , .prog_clk_3_E_in ( p1016 ) , - .prog_clk_3_S_in ( p989 ) , .prog_clk_3_N_in ( p3336 ) , + .prog_clk_3_W_in ( p3128 ) , .prog_clk_3_E_in ( p823 ) , + .prog_clk_3_S_in ( p1098 ) , .prog_clk_3_N_in ( p3515 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_4231 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4232 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_4233 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_4234 ) , .clk_1_N_in ( p1389 ) , - .clk_1_S_in ( p332 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_4235 ) , - .clk_1_W_out ( SYNOPSYS_UNCONNECTED_4236 ) , .clk_2_N_in ( p3397 ) , - .clk_2_E_in ( p0 ) , .clk_2_S_in ( p3441 ) , .clk_2_W_in ( p1731 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_4234 ) , .clk_1_N_in ( p1581 ) , + .clk_1_S_in ( p330 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_4235 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_4236 ) , .clk_2_N_in ( p3261 ) , + .clk_2_E_in ( p0 ) , .clk_2_S_in ( p74 ) , .clk_2_W_in ( p3299 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_4237 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_4238 ) , .clk_2_N_out ( SYNOPSYS_UNCONNECTED_4239 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_4240 ) , .clk_3_W_in ( p1760 ) , - .clk_3_E_in ( p566 ) , .clk_3_S_in ( p847 ) , .clk_3_N_in ( p3388 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_4240 ) , .clk_3_W_in ( p3333 ) , + .clk_3_E_in ( p1057 ) , .clk_3_S_in ( p1341 ) , .clk_3_N_in ( p3181 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_4241 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4242 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_4243 ) , @@ -138144,16 +141710,16 @@ sb_1__1_ sb_8__2_ ( .chanx_right_out ( sb_1__1__78_chanx_right_out ) , .chany_bottom_out ( sb_1__1__78_chany_bottom_out ) , .chanx_left_out ( sb_1__1__78_chanx_left_out ) , - .ccff_tail ( sb_1__1__78_ccff_tail ) , .Test_en_S_in ( p1947 ) , + .ccff_tail ( sb_1__1__78_ccff_tail ) , .Test_en_S_in ( p2549 ) , .Test_en_N_out ( SYNOPSYS_UNCONNECTED_4246 ) , .pReset_S_in ( SYNOPSYS_UNCONNECTED_4247 ) , .pReset_E_in ( SYNOPSYS_UNCONNECTED_4248 ) , .pReset_W_in ( pResetWires[140] ) , .pReset_N_out ( pResetWires[142] ) , .pReset_W_out ( SYNOPSYS_UNCONNECTED_4249 ) , - .pReset_E_out ( pResetWires[143] ) , .Reset_S_in ( p1947 ) , + .pReset_E_out ( pResetWires[143] ) , .Reset_S_in ( p2549 ) , .Reset_N_out ( SYNOPSYS_UNCONNECTED_4250 ) , - .prog_clk_0_N_in ( prog_clk_0_wires[299] ) , .prog_clk_1_N_in ( p1620 ) , - .prog_clk_1_S_in ( p891 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[299] ) , .prog_clk_1_N_in ( p2321 ) , + .prog_clk_1_S_in ( p436 ) , .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_4251 ) , .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_4252 ) , .prog_clk_2_N_in ( prog_clk_3_wires[43] ) , @@ -138163,14 +141729,14 @@ sb_1__1_ sb_8__2_ ( .prog_clk_2_W_out ( prog_clk_2_wires[71] ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_4256 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_4257 ) , - .prog_clk_2_E_out ( prog_clk_2_wires[69] ) , .prog_clk_3_W_in ( p2152 ) , - .prog_clk_3_E_in ( p798 ) , .prog_clk_3_S_in ( p740 ) , - .prog_clk_3_N_in ( p699 ) , + .prog_clk_2_E_out ( prog_clk_2_wires[69] ) , .prog_clk_3_W_in ( p2047 ) , + .prog_clk_3_E_in ( p871 ) , .prog_clk_3_S_in ( p125 ) , + .prog_clk_3_N_in ( p788 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_4258 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4259 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_4260 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_4261 ) , .clk_1_N_in ( p1620 ) , - .clk_1_S_in ( p301 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_4262 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_4261 ) , .clk_1_N_in ( p2321 ) , + .clk_1_S_in ( p1106 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_4262 ) , .clk_1_W_out ( SYNOPSYS_UNCONNECTED_4263 ) , .clk_2_N_in ( clk_3_wires[43] ) , .clk_2_E_in ( SYNOPSYS_UNCONNECTED_4264 ) , @@ -138179,8 +141745,8 @@ sb_1__1_ sb_8__2_ ( .clk_2_W_out ( clk_2_wires[71] ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_4267 ) , .clk_2_N_out ( SYNOPSYS_UNCONNECTED_4268 ) , - .clk_2_E_out ( clk_2_wires[69] ) , .clk_3_W_in ( p2152 ) , - .clk_3_E_in ( p1634 ) , .clk_3_S_in ( p1720 ) , .clk_3_N_in ( p460 ) , + .clk_2_E_out ( clk_2_wires[69] ) , .clk_3_W_in ( p2047 ) , + .clk_3_E_in ( p341 ) , .clk_3_S_in ( p2377 ) , .clk_3_N_in ( p2122 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_4269 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4270 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_4271 ) , @@ -138228,20 +141794,20 @@ sb_1__1_ sb_8__3_ ( .chanx_right_out ( sb_1__1__79_chanx_right_out ) , .chany_bottom_out ( sb_1__1__79_chany_bottom_out ) , .chanx_left_out ( sb_1__1__79_chanx_left_out ) , - .ccff_tail ( sb_1__1__79_ccff_tail ) , .Test_en_S_in ( p2643 ) , + .ccff_tail ( sb_1__1__79_ccff_tail ) , .Test_en_S_in ( p2262 ) , .Test_en_N_out ( SYNOPSYS_UNCONNECTED_4274 ) , .pReset_S_in ( SYNOPSYS_UNCONNECTED_4275 ) , .pReset_E_in ( SYNOPSYS_UNCONNECTED_4276 ) , .pReset_W_in ( pResetWires[189] ) , .pReset_N_out ( pResetWires[191] ) , .pReset_W_out ( SYNOPSYS_UNCONNECTED_4277 ) , - .pReset_E_out ( pResetWires[192] ) , .Reset_S_in ( p2643 ) , + .pReset_E_out ( pResetWires[192] ) , .Reset_S_in ( p2262 ) , .Reset_N_out ( SYNOPSYS_UNCONNECTED_4278 ) , - .prog_clk_0_N_in ( prog_clk_0_wires[302] ) , .prog_clk_1_N_in ( p1509 ) , - .prog_clk_1_S_in ( p664 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[302] ) , .prog_clk_1_N_in ( p1601 ) , + .prog_clk_1_S_in ( p568 ) , .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_4279 ) , .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_4280 ) , - .prog_clk_2_N_in ( p2267 ) , .prog_clk_2_E_in ( p639 ) , - .prog_clk_2_S_in ( p1967 ) , .prog_clk_2_W_in ( p323 ) , + .prog_clk_2_N_in ( p2325 ) , .prog_clk_2_E_in ( p459 ) , + .prog_clk_2_S_in ( p1782 ) , .prog_clk_2_W_in ( p506 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_4281 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_4282 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_4283 ) , @@ -138253,10 +141819,10 @@ sb_1__1_ sb_8__3_ ( .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_4288 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4289 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_4290 ) , - .prog_clk_3_S_out ( prog_clk_3_wires[42] ) , .clk_1_N_in ( p1509 ) , - .clk_1_S_in ( p128 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_4291 ) , - .clk_1_W_out ( SYNOPSYS_UNCONNECTED_4292 ) , .clk_2_N_in ( p2267 ) , - .clk_2_E_in ( p265 ) , .clk_2_S_in ( p2564 ) , .clk_2_W_in ( p1185 ) , + .prog_clk_3_S_out ( prog_clk_3_wires[42] ) , .clk_1_N_in ( p1601 ) , + .clk_1_S_in ( p831 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_4291 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_4292 ) , .clk_2_N_in ( p1497 ) , + .clk_2_E_in ( p699 ) , .clk_2_S_in ( p2067 ) , .clk_2_W_in ( p885 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_4293 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_4294 ) , .clk_2_N_out ( SYNOPSYS_UNCONNECTED_4295 ) , @@ -138312,16 +141878,16 @@ sb_1__1_ sb_8__4_ ( .chanx_right_out ( sb_1__1__80_chanx_right_out ) , .chany_bottom_out ( sb_1__1__80_chany_bottom_out ) , .chanx_left_out ( sb_1__1__80_chanx_left_out ) , - .ccff_tail ( sb_1__1__80_ccff_tail ) , .Test_en_S_in ( p1822 ) , + .ccff_tail ( sb_1__1__80_ccff_tail ) , .Test_en_S_in ( p1902 ) , .Test_en_N_out ( SYNOPSYS_UNCONNECTED_4304 ) , .pReset_S_in ( SYNOPSYS_UNCONNECTED_4305 ) , .pReset_E_in ( SYNOPSYS_UNCONNECTED_4306 ) , .pReset_W_in ( pResetWires[238] ) , .pReset_N_out ( pResetWires[240] ) , .pReset_W_out ( SYNOPSYS_UNCONNECTED_4307 ) , - .pReset_E_out ( pResetWires[241] ) , .Reset_S_in ( p1822 ) , + .pReset_E_out ( pResetWires[241] ) , .Reset_S_in ( p1902 ) , .Reset_N_out ( SYNOPSYS_UNCONNECTED_4308 ) , - .prog_clk_0_N_in ( prog_clk_0_wires[305] ) , .prog_clk_1_N_in ( p1174 ) , - .prog_clk_1_S_in ( p509 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[305] ) , .prog_clk_1_N_in ( p1856 ) , + .prog_clk_1_S_in ( p1715 ) , .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_4309 ) , .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_4310 ) , .prog_clk_2_N_in ( prog_clk_3_wires[33] ) , @@ -138339,8 +141905,8 @@ sb_1__1_ sb_8__4_ ( .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_4319 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4320 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_4321 ) , - .prog_clk_3_S_out ( prog_clk_3_wires[38] ) , .clk_1_N_in ( p1174 ) , - .clk_1_S_in ( p1649 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_4322 ) , + .prog_clk_3_S_out ( prog_clk_3_wires[38] ) , .clk_1_N_in ( p1856 ) , + .clk_1_S_in ( p208 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_4322 ) , .clk_1_W_out ( SYNOPSYS_UNCONNECTED_4323 ) , .clk_2_N_in ( clk_3_wires[33] ) , .clk_2_E_in ( SYNOPSYS_UNCONNECTED_4324 ) , @@ -138401,20 +141967,20 @@ sb_1__1_ sb_8__5_ ( .chanx_right_out ( sb_1__1__81_chanx_right_out ) , .chany_bottom_out ( sb_1__1__81_chany_bottom_out ) , .chanx_left_out ( sb_1__1__81_chanx_left_out ) , - .ccff_tail ( sb_1__1__81_ccff_tail ) , .Test_en_S_in ( p2962 ) , + .ccff_tail ( sb_1__1__81_ccff_tail ) , .Test_en_S_in ( p2512 ) , .Test_en_N_out ( SYNOPSYS_UNCONNECTED_4336 ) , .pReset_S_in ( SYNOPSYS_UNCONNECTED_4337 ) , .pReset_E_in ( SYNOPSYS_UNCONNECTED_4338 ) , .pReset_W_in ( pResetWires[287] ) , .pReset_N_out ( pResetWires[289] ) , .pReset_W_out ( SYNOPSYS_UNCONNECTED_4339 ) , - .pReset_E_out ( pResetWires[290] ) , .Reset_S_in ( p3252 ) , + .pReset_E_out ( pResetWires[290] ) , .Reset_S_in ( p2512 ) , .Reset_N_out ( SYNOPSYS_UNCONNECTED_4340 ) , - .prog_clk_0_N_in ( prog_clk_0_wires[308] ) , .prog_clk_1_N_in ( p1748 ) , - .prog_clk_1_S_in ( p233 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[308] ) , .prog_clk_1_N_in ( p1617 ) , + .prog_clk_1_S_in ( p137 ) , .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_4341 ) , .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_4342 ) , - .prog_clk_2_N_in ( p1833 ) , .prog_clk_2_E_in ( p811 ) , - .prog_clk_2_S_in ( p1625 ) , .prog_clk_2_W_in ( p1164 ) , + .prog_clk_2_N_in ( p2484 ) , .prog_clk_2_E_in ( p486 ) , + .prog_clk_2_S_in ( p2055 ) , .prog_clk_2_W_in ( p827 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_4343 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_4344 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_4345 ) , @@ -138426,10 +141992,10 @@ sb_1__1_ sb_8__5_ ( .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_4350 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4351 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_4352 ) , - .prog_clk_3_S_out ( prog_clk_3_wires[32] ) , .clk_1_N_in ( p1748 ) , - .clk_1_S_in ( p910 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_4353 ) , - .clk_1_W_out ( SYNOPSYS_UNCONNECTED_4354 ) , .clk_2_N_in ( p1924 ) , - .clk_2_E_in ( p47 ) , .clk_2_S_in ( p3211 ) , .clk_2_W_in ( p389 ) , + .prog_clk_3_S_out ( prog_clk_3_wires[32] ) , .clk_1_N_in ( p1617 ) , + .clk_1_S_in ( p905 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_4353 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_4354 ) , .clk_2_N_in ( p1976 ) , + .clk_2_E_in ( p491 ) , .clk_2_S_in ( p2384 ) , .clk_2_W_in ( p304 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_4355 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_4356 ) , .clk_2_N_out ( SYNOPSYS_UNCONNECTED_4357 ) , @@ -138485,20 +142051,20 @@ sb_1__1_ sb_8__6_ ( .chanx_right_out ( sb_1__1__82_chanx_right_out ) , .chany_bottom_out ( sb_1__1__82_chany_bottom_out ) , .chanx_left_out ( sb_1__1__82_chanx_left_out ) , - .ccff_tail ( sb_1__1__82_ccff_tail ) , .Test_en_S_in ( p2206 ) , + .ccff_tail ( sb_1__1__82_ccff_tail ) , .Test_en_S_in ( p2516 ) , .Test_en_N_out ( SYNOPSYS_UNCONNECTED_4366 ) , .pReset_S_in ( SYNOPSYS_UNCONNECTED_4367 ) , .pReset_E_in ( SYNOPSYS_UNCONNECTED_4368 ) , .pReset_W_in ( pResetWires[336] ) , .pReset_N_out ( pResetWires[338] ) , .pReset_W_out ( SYNOPSYS_UNCONNECTED_4369 ) , - .pReset_E_out ( pResetWires[339] ) , .Reset_S_in ( p3107 ) , + .pReset_E_out ( pResetWires[339] ) , .Reset_S_in ( p2516 ) , .Reset_N_out ( SYNOPSYS_UNCONNECTED_4370 ) , - .prog_clk_0_N_in ( prog_clk_0_wires[311] ) , .prog_clk_1_N_in ( p1861 ) , - .prog_clk_1_S_in ( p144 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[311] ) , .prog_clk_1_N_in ( p1328 ) , + .prog_clk_1_S_in ( p43 ) , .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_4371 ) , .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_4372 ) , - .prog_clk_2_N_in ( p2957 ) , .prog_clk_2_E_in ( p294 ) , - .prog_clk_2_S_in ( p1661 ) , .prog_clk_2_W_in ( p386 ) , + .prog_clk_2_N_in ( p2046 ) , .prog_clk_2_E_in ( p512 ) , + .prog_clk_2_S_in ( p385 ) , .prog_clk_2_W_in ( p511 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_4373 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_4374 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_4375 ) , @@ -138510,10 +142076,10 @@ sb_1__1_ sb_8__6_ ( .prog_clk_3_E_out ( prog_clk_3_wires[44] ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4380 ) , .prog_clk_3_N_out ( prog_clk_3_wires[26] ) , - .prog_clk_3_S_out ( prog_clk_3_wires[28] ) , .clk_1_N_in ( p1861 ) , - .clk_1_S_in ( p839 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_4381 ) , - .clk_1_W_out ( SYNOPSYS_UNCONNECTED_4382 ) , .clk_2_N_in ( p2926 ) , - .clk_2_E_in ( p822 ) , .clk_2_S_in ( p3001 ) , .clk_2_W_in ( p1247 ) , + .prog_clk_3_S_out ( prog_clk_3_wires[28] ) , .clk_1_N_in ( p1328 ) , + .clk_1_S_in ( p1002 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_4381 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_4382 ) , .clk_2_N_in ( p2046 ) , + .clk_2_E_in ( p801 ) , .clk_2_S_in ( p2390 ) , .clk_2_W_in ( p370 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_4383 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_4384 ) , .clk_2_N_out ( SYNOPSYS_UNCONNECTED_4385 ) , @@ -138569,20 +142135,20 @@ sb_1__1_ sb_8__7_ ( .chanx_right_out ( sb_1__1__83_chanx_right_out ) , .chany_bottom_out ( sb_1__1__83_chany_bottom_out ) , .chanx_left_out ( sb_1__1__83_chanx_left_out ) , - .ccff_tail ( sb_1__1__83_ccff_tail ) , .Test_en_S_in ( p2136 ) , + .ccff_tail ( sb_1__1__83_ccff_tail ) , .Test_en_S_in ( p2523 ) , .Test_en_N_out ( SYNOPSYS_UNCONNECTED_4392 ) , .pReset_S_in ( SYNOPSYS_UNCONNECTED_4393 ) , .pReset_E_in ( SYNOPSYS_UNCONNECTED_4394 ) , .pReset_W_in ( pResetWires[385] ) , .pReset_N_out ( pResetWires[387] ) , .pReset_W_out ( SYNOPSYS_UNCONNECTED_4395 ) , - .pReset_E_out ( pResetWires[388] ) , .Reset_S_in ( p3271 ) , + .pReset_E_out ( pResetWires[388] ) , .Reset_S_in ( p2523 ) , .Reset_N_out ( SYNOPSYS_UNCONNECTED_4396 ) , - .prog_clk_0_N_in ( prog_clk_0_wires[314] ) , .prog_clk_1_N_in ( p1827 ) , - .prog_clk_1_S_in ( p868 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[314] ) , .prog_clk_1_N_in ( p1445 ) , + .prog_clk_1_S_in ( p1225 ) , .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_4397 ) , .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_4398 ) , - .prog_clk_2_N_in ( p2463 ) , .prog_clk_2_E_in ( p152 ) , - .prog_clk_2_S_in ( p1645 ) , .prog_clk_2_W_in ( p177 ) , + .prog_clk_2_N_in ( p2501 ) , .prog_clk_2_E_in ( p433 ) , + .prog_clk_2_S_in ( p387 ) , .prog_clk_2_W_in ( p171 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_4399 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_4400 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_4401 ) , @@ -138594,10 +142160,10 @@ sb_1__1_ sb_8__7_ ( .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_4406 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4407 ) , .prog_clk_3_N_out ( prog_clk_3_wires[30] ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_4408 ) , .clk_1_N_in ( p1827 ) , - .clk_1_S_in ( p507 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_4409 ) , - .clk_1_W_out ( SYNOPSYS_UNCONNECTED_4410 ) , .clk_2_N_in ( p2463 ) , - .clk_2_E_in ( p942 ) , .clk_2_S_in ( p3226 ) , .clk_2_W_in ( p528 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_4408 ) , .clk_1_N_in ( p1445 ) , + .clk_1_S_in ( p157 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_4409 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_4410 ) , .clk_2_N_in ( p2594 ) , + .clk_2_E_in ( p597 ) , .clk_2_S_in ( p2386 ) , .clk_2_W_in ( p590 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_4411 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_4412 ) , .clk_2_N_out ( SYNOPSYS_UNCONNECTED_4413 ) , @@ -138653,16 +142219,16 @@ sb_1__1_ sb_8__8_ ( .chanx_right_out ( sb_1__1__84_chanx_right_out ) , .chany_bottom_out ( sb_1__1__84_chany_bottom_out ) , .chanx_left_out ( sb_1__1__84_chanx_left_out ) , - .ccff_tail ( sb_1__1__84_ccff_tail ) , .Test_en_S_in ( p1491 ) , + .ccff_tail ( sb_1__1__84_ccff_tail ) , .Test_en_S_in ( p2323 ) , .Test_en_N_out ( SYNOPSYS_UNCONNECTED_4422 ) , .pReset_S_in ( SYNOPSYS_UNCONNECTED_4423 ) , .pReset_E_in ( SYNOPSYS_UNCONNECTED_4424 ) , .pReset_W_in ( pResetWires[434] ) , .pReset_N_out ( pResetWires[436] ) , .pReset_W_out ( SYNOPSYS_UNCONNECTED_4425 ) , - .pReset_E_out ( pResetWires[437] ) , .Reset_S_in ( p1491 ) , + .pReset_E_out ( pResetWires[437] ) , .Reset_S_in ( p2323 ) , .Reset_N_out ( SYNOPSYS_UNCONNECTED_4426 ) , - .prog_clk_0_N_in ( prog_clk_0_wires[317] ) , .prog_clk_1_N_in ( p1793 ) , - .prog_clk_1_S_in ( p165 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[317] ) , .prog_clk_1_N_in ( p1425 ) , + .prog_clk_1_S_in ( p2105 ) , .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_4427 ) , .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_4428 ) , .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_4429 ) , @@ -138680,8 +142246,8 @@ sb_1__1_ sb_8__8_ ( .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_4437 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4438 ) , .prog_clk_3_N_out ( prog_clk_3_wires[36] ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_4439 ) , .clk_1_N_in ( p1793 ) , - .clk_1_S_in ( p805 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_4440 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_4439 ) , .clk_1_N_in ( p1425 ) , + .clk_1_S_in ( p1187 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_4440 ) , .clk_1_W_out ( SYNOPSYS_UNCONNECTED_4441 ) , .clk_2_N_in ( SYNOPSYS_UNCONNECTED_4442 ) , .clk_2_E_in ( SYNOPSYS_UNCONNECTED_4443 ) , @@ -138742,20 +142308,20 @@ sb_1__1_ sb_8__9_ ( .chanx_right_out ( sb_1__1__85_chanx_right_out ) , .chany_bottom_out ( sb_1__1__85_chany_bottom_out ) , .chanx_left_out ( sb_1__1__85_chanx_left_out ) , - .ccff_tail ( sb_1__1__85_ccff_tail ) , .Test_en_S_in ( p2466 ) , + .ccff_tail ( sb_1__1__85_ccff_tail ) , .Test_en_S_in ( p2302 ) , .Test_en_N_out ( SYNOPSYS_UNCONNECTED_4454 ) , .pReset_S_in ( SYNOPSYS_UNCONNECTED_4455 ) , .pReset_E_in ( SYNOPSYS_UNCONNECTED_4456 ) , .pReset_W_in ( pResetWires[483] ) , .pReset_N_out ( pResetWires[485] ) , .pReset_W_out ( SYNOPSYS_UNCONNECTED_4457 ) , - .pReset_E_out ( pResetWires[486] ) , .Reset_S_in ( p2466 ) , + .pReset_E_out ( pResetWires[486] ) , .Reset_S_in ( p2302 ) , .Reset_N_out ( SYNOPSYS_UNCONNECTED_4458 ) , - .prog_clk_0_N_in ( prog_clk_0_wires[320] ) , .prog_clk_1_N_in ( p1563 ) , - .prog_clk_1_S_in ( p588 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[320] ) , .prog_clk_1_N_in ( p1486 ) , + .prog_clk_1_S_in ( p376 ) , .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_4459 ) , .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_4460 ) , - .prog_clk_2_N_in ( p2433 ) , .prog_clk_2_E_in ( p909 ) , - .prog_clk_2_S_in ( p2011 ) , .prog_clk_2_W_in ( p345 ) , + .prog_clk_2_N_in ( p1867 ) , .prog_clk_2_E_in ( p757 ) , + .prog_clk_2_S_in ( p791 ) , .prog_clk_2_W_in ( p165 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_4461 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_4462 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_4463 ) , @@ -138767,10 +142333,10 @@ sb_1__1_ sb_8__9_ ( .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_4468 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4469 ) , .prog_clk_3_N_out ( prog_clk_3_wires[40] ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_4470 ) , .clk_1_N_in ( p1563 ) , - .clk_1_S_in ( p1028 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_4471 ) , - .clk_1_W_out ( SYNOPSYS_UNCONNECTED_4472 ) , .clk_2_N_in ( p2121 ) , - .clk_2_E_in ( p115 ) , .clk_2_S_in ( p2307 ) , .clk_2_W_in ( p894 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_4470 ) , .clk_1_N_in ( p1486 ) , + .clk_1_S_in ( p848 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_4471 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_4472 ) , .clk_2_N_in ( p1867 ) , + .clk_2_E_in ( p814 ) , .clk_2_S_in ( p2116 ) , .clk_2_W_in ( p873 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_4473 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_4474 ) , .clk_2_N_out ( SYNOPSYS_UNCONNECTED_4475 ) , @@ -138826,16 +142392,16 @@ sb_1__1_ sb_8__10_ ( .chanx_right_out ( sb_1__1__86_chanx_right_out ) , .chany_bottom_out ( sb_1__1__86_chany_bottom_out ) , .chanx_left_out ( sb_1__1__86_chanx_left_out ) , - .ccff_tail ( sb_1__1__86_ccff_tail ) , .Test_en_S_in ( p1907 ) , + .ccff_tail ( sb_1__1__86_ccff_tail ) , .Test_en_S_in ( p2241 ) , .Test_en_N_out ( SYNOPSYS_UNCONNECTED_4484 ) , .pReset_S_in ( SYNOPSYS_UNCONNECTED_4485 ) , .pReset_E_in ( SYNOPSYS_UNCONNECTED_4486 ) , .pReset_W_in ( pResetWires[532] ) , .pReset_N_out ( pResetWires[534] ) , .pReset_W_out ( SYNOPSYS_UNCONNECTED_4487 ) , - .pReset_E_out ( pResetWires[535] ) , .Reset_S_in ( p1907 ) , + .pReset_E_out ( pResetWires[535] ) , .Reset_S_in ( p2241 ) , .Reset_N_out ( SYNOPSYS_UNCONNECTED_4488 ) , - .prog_clk_0_N_in ( prog_clk_0_wires[323] ) , .prog_clk_1_N_in ( p1562 ) , - .prog_clk_1_S_in ( p55 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[323] ) , .prog_clk_1_N_in ( p2264 ) , + .prog_clk_1_S_in ( p623 ) , .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_4489 ) , .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_4490 ) , .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_4491 ) , @@ -138845,14 +142411,14 @@ sb_1__1_ sb_8__10_ ( .prog_clk_2_W_out ( prog_clk_2_wires[106] ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_4494 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_4495 ) , - .prog_clk_2_E_out ( prog_clk_2_wires[104] ) , .prog_clk_3_W_in ( p2183 ) , - .prog_clk_3_E_in ( p1074 ) , .prog_clk_3_S_in ( p1969 ) , - .prog_clk_3_N_in ( p750 ) , + .prog_clk_2_E_out ( prog_clk_2_wires[104] ) , .prog_clk_3_W_in ( p1434 ) , + .prog_clk_3_E_in ( p20 ) , .prog_clk_3_S_in ( p2087 ) , + .prog_clk_3_N_in ( p468 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_4496 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4497 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_4498 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_4499 ) , .clk_1_N_in ( p1562 ) , - .clk_1_S_in ( p515 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_4500 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_4499 ) , .clk_1_N_in ( p2264 ) , + .clk_1_S_in ( p886 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_4500 ) , .clk_1_W_out ( SYNOPSYS_UNCONNECTED_4501 ) , .clk_2_N_in ( SYNOPSYS_UNCONNECTED_4502 ) , .clk_2_E_in ( SYNOPSYS_UNCONNECTED_4503 ) , @@ -138861,8 +142427,8 @@ sb_1__1_ sb_8__10_ ( .clk_2_W_out ( clk_2_wires[106] ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_4505 ) , .clk_2_N_out ( SYNOPSYS_UNCONNECTED_4506 ) , - .clk_2_E_out ( clk_2_wires[104] ) , .clk_3_W_in ( p2183 ) , - .clk_3_E_in ( p2009 ) , .clk_3_S_in ( p1730 ) , .clk_3_N_in ( p293 ) , + .clk_2_E_out ( clk_2_wires[104] ) , .clk_3_W_in ( p1434 ) , + .clk_3_E_in ( p916 ) , .clk_3_S_in ( p2150 ) , .clk_3_N_in ( p2118 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_4507 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4508 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_4509 ) , @@ -138910,38 +142476,38 @@ sb_1__1_ sb_8__11_ ( .chanx_right_out ( sb_1__1__87_chanx_right_out ) , .chany_bottom_out ( sb_1__1__87_chany_bottom_out ) , .chanx_left_out ( sb_1__1__87_chanx_left_out ) , - .ccff_tail ( sb_1__1__87_ccff_tail ) , .Test_en_S_in ( p2997 ) , + .ccff_tail ( sb_1__1__87_ccff_tail ) , .Test_en_S_in ( p1860 ) , .Test_en_N_out ( SYNOPSYS_UNCONNECTED_4512 ) , .pReset_S_in ( SYNOPSYS_UNCONNECTED_4513 ) , .pReset_E_in ( SYNOPSYS_UNCONNECTED_4514 ) , .pReset_W_in ( pResetWires[581] ) , .pReset_N_out ( pResetWires[583] ) , .pReset_W_out ( SYNOPSYS_UNCONNECTED_4515 ) , - .pReset_E_out ( pResetWires[584] ) , .Reset_S_in ( p3373 ) , + .pReset_E_out ( pResetWires[584] ) , .Reset_S_in ( p1860 ) , .Reset_N_out ( SYNOPSYS_UNCONNECTED_4516 ) , - .prog_clk_0_N_in ( prog_clk_0_wires[326] ) , .prog_clk_1_N_in ( p1539 ) , - .prog_clk_1_S_in ( p438 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[326] ) , .prog_clk_1_N_in ( p1473 ) , + .prog_clk_1_S_in ( p621 ) , .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_4517 ) , .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_4518 ) , - .prog_clk_2_N_in ( p3410 ) , .prog_clk_2_E_in ( p731 ) , - .prog_clk_2_S_in ( p1627 ) , .prog_clk_2_W_in ( p196 ) , + .prog_clk_2_N_in ( p3575 ) , .prog_clk_2_E_in ( p520 ) , + .prog_clk_2_S_in ( p1250 ) , .prog_clk_2_W_in ( p185 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_4519 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_4520 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_4521 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_4522 ) , - .prog_clk_3_W_in ( p3078 ) , .prog_clk_3_E_in ( p982 ) , - .prog_clk_3_S_in ( p339 ) , .prog_clk_3_N_in ( p3382 ) , + .prog_clk_3_W_in ( p2762 ) , .prog_clk_3_E_in ( p16 ) , + .prog_clk_3_S_in ( p7 ) , .prog_clk_3_N_in ( p3565 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_4523 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4524 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_4525 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_4526 ) , .clk_1_N_in ( p1539 ) , - .clk_1_S_in ( p993 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_4527 ) , - .clk_1_W_out ( SYNOPSYS_UNCONNECTED_4528 ) , .clk_2_N_in ( p3402 ) , - .clk_2_E_in ( p833 ) , .clk_2_S_in ( p3334 ) , .clk_2_W_in ( p3006 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_4526 ) , .clk_1_N_in ( p1473 ) , + .clk_1_S_in ( p730 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_4527 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_4528 ) , .clk_2_N_in ( p3589 ) , + .clk_2_E_in ( p1279 ) , .clk_2_S_in ( p1105 ) , .clk_2_W_in ( p3605 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_4529 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_4530 ) , .clk_2_N_out ( SYNOPSYS_UNCONNECTED_4531 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_4532 ) , .clk_3_W_in ( p3078 ) , - .clk_3_E_in ( p274 ) , .clk_3_S_in ( p14 ) , .clk_3_N_in ( p3394 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_4532 ) , .clk_3_W_in ( p3610 ) , + .clk_3_E_in ( p337 ) , .clk_3_S_in ( p1781 ) , .clk_3_N_in ( p3584 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_4533 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4534 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_4535 ) , @@ -138989,27 +142555,27 @@ sb_1__1_ sb_9__1_ ( .chanx_right_out ( sb_1__1__88_chanx_right_out ) , .chany_bottom_out ( sb_1__1__88_chany_bottom_out ) , .chanx_left_out ( sb_1__1__88_chanx_left_out ) , - .ccff_tail ( sb_1__1__88_ccff_tail ) , .Test_en_S_in ( p2936 ) , + .ccff_tail ( sb_1__1__88_ccff_tail ) , .Test_en_S_in ( p1545 ) , .Test_en_N_out ( SYNOPSYS_UNCONNECTED_4538 ) , .pReset_S_in ( SYNOPSYS_UNCONNECTED_4539 ) , .pReset_E_in ( SYNOPSYS_UNCONNECTED_4540 ) , .pReset_W_in ( pResetWires[95] ) , .pReset_N_out ( pResetWires[97] ) , .pReset_W_out ( SYNOPSYS_UNCONNECTED_4541 ) , - .pReset_E_out ( pResetWires[98] ) , .Reset_S_in ( p2936 ) , + .pReset_E_out ( pResetWires[98] ) , .Reset_S_in ( p1545 ) , .Reset_N_out ( SYNOPSYS_UNCONNECTED_4542 ) , .prog_clk_0_N_in ( prog_clk_0_wires[334] ) , .prog_clk_1_N_in ( prog_clk_2_wires[76] ) , .prog_clk_1_S_in ( SYNOPSYS_UNCONNECTED_4543 ) , .prog_clk_1_E_out ( prog_clk_1_wires[169] ) , - .prog_clk_1_W_out ( prog_clk_1_wires[170] ) , .prog_clk_2_N_in ( p3282 ) , - .prog_clk_2_E_in ( p370 ) , .prog_clk_2_S_in ( p1409 ) , - .prog_clk_2_W_in ( p58 ) , + .prog_clk_1_W_out ( prog_clk_1_wires[170] ) , .prog_clk_2_N_in ( p3509 ) , + .prog_clk_2_E_in ( p213 ) , .prog_clk_2_S_in ( p711 ) , + .prog_clk_2_W_in ( p292 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_4544 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_4545 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_4546 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_4547 ) , - .prog_clk_3_W_in ( p3062 ) , .prog_clk_3_E_in ( p1061 ) , - .prog_clk_3_S_in ( p188 ) , .prog_clk_3_N_in ( p3304 ) , + .prog_clk_3_W_in ( p2983 ) , .prog_clk_3_E_in ( p1066 ) , + .prog_clk_3_S_in ( p1306 ) , .prog_clk_3_N_in ( p3493 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_4548 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4549 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_4550 ) , @@ -139017,12 +142583,12 @@ sb_1__1_ sb_9__1_ ( .clk_1_N_in ( clk_2_wires[76] ) , .clk_1_S_in ( SYNOPSYS_UNCONNECTED_4552 ) , .clk_1_E_out ( clk_1_wires[169] ) , .clk_1_W_out ( clk_1_wires[170] ) , - .clk_2_N_in ( p3493 ) , .clk_2_E_in ( p157 ) , .clk_2_S_in ( p2878 ) , - .clk_2_W_in ( p3014 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_4553 ) , + .clk_2_N_in ( p2821 ) , .clk_2_E_in ( p1192 ) , .clk_2_S_in ( p55 ) , + .clk_2_W_in ( p3189 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_4553 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_4554 ) , .clk_2_N_out ( SYNOPSYS_UNCONNECTED_4555 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_4556 ) , .clk_3_W_in ( p3062 ) , - .clk_3_E_in ( p955 ) , .clk_3_S_in ( p1304 ) , .clk_3_N_in ( p3490 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_4556 ) , .clk_3_W_in ( p3249 ) , + .clk_3_E_in ( p326 ) , .clk_3_S_in ( p1143 ) , .clk_3_N_in ( p2655 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_4557 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4558 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_4559 ) , @@ -139070,16 +142636,16 @@ sb_1__1_ sb_9__2_ ( .chanx_right_out ( sb_1__1__89_chanx_right_out ) , .chany_bottom_out ( sb_1__1__89_chany_bottom_out ) , .chanx_left_out ( sb_1__1__89_chanx_left_out ) , - .ccff_tail ( sb_1__1__89_ccff_tail ) , .Test_en_S_in ( p2440 ) , + .ccff_tail ( sb_1__1__89_ccff_tail ) , .Test_en_S_in ( p1918 ) , .Test_en_N_out ( SYNOPSYS_UNCONNECTED_4562 ) , .pReset_S_in ( SYNOPSYS_UNCONNECTED_4563 ) , .pReset_E_in ( SYNOPSYS_UNCONNECTED_4564 ) , .pReset_W_in ( pResetWires[144] ) , .pReset_N_out ( pResetWires[146] ) , .pReset_W_out ( SYNOPSYS_UNCONNECTED_4565 ) , - .pReset_E_out ( pResetWires[147] ) , .Reset_S_in ( p2440 ) , + .pReset_E_out ( pResetWires[147] ) , .Reset_S_in ( p1918 ) , .Reset_N_out ( SYNOPSYS_UNCONNECTED_4566 ) , - .prog_clk_0_N_in ( prog_clk_0_wires[337] ) , .prog_clk_1_N_in ( p1903 ) , - .prog_clk_1_S_in ( p413 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[337] ) , .prog_clk_1_N_in ( p1462 ) , + .prog_clk_1_S_in ( p745 ) , .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_4567 ) , .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_4568 ) , .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_4569 ) , @@ -139090,13 +142656,13 @@ sb_1__1_ sb_9__2_ ( .prog_clk_2_S_out ( prog_clk_2_wires[75] ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_4573 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_4574 ) , - .prog_clk_3_W_in ( p1400 ) , .prog_clk_3_E_in ( p45 ) , - .prog_clk_3_S_in ( p646 ) , .prog_clk_3_N_in ( p763 ) , + .prog_clk_3_W_in ( p1636 ) , .prog_clk_3_E_in ( p851 ) , + .prog_clk_3_S_in ( p639 ) , .prog_clk_3_N_in ( p191 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_4575 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4576 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_4577 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_4578 ) , .clk_1_N_in ( p1903 ) , - .clk_1_S_in ( p1103 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_4579 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_4578 ) , .clk_1_N_in ( p1462 ) , + .clk_1_S_in ( p41 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_4579 ) , .clk_1_W_out ( SYNOPSYS_UNCONNECTED_4580 ) , .clk_2_N_in ( SYNOPSYS_UNCONNECTED_4581 ) , .clk_2_E_in ( SYNOPSYS_UNCONNECTED_4582 ) , @@ -139105,8 +142671,8 @@ sb_1__1_ sb_9__2_ ( .clk_2_W_out ( SYNOPSYS_UNCONNECTED_4584 ) , .clk_2_S_out ( clk_2_wires[75] ) , .clk_2_N_out ( SYNOPSYS_UNCONNECTED_4585 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_4586 ) , .clk_3_W_in ( p1400 ) , - .clk_3_E_in ( p821 ) , .clk_3_S_in ( p2336 ) , .clk_3_N_in ( p1633 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_4586 ) , .clk_3_W_in ( p1636 ) , + .clk_3_E_in ( p120 ) , .clk_3_S_in ( p1674 ) , .clk_3_N_in ( p753 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_4587 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4588 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_4589 ) , @@ -139154,27 +142720,27 @@ sb_1__1_ sb_9__3_ ( .chanx_right_out ( sb_1__1__90_chanx_right_out ) , .chany_bottom_out ( sb_1__1__90_chany_bottom_out ) , .chanx_left_out ( sb_1__1__90_chanx_left_out ) , - .ccff_tail ( sb_1__1__90_ccff_tail ) , .Test_en_S_in ( p3273 ) , + .ccff_tail ( sb_1__1__90_ccff_tail ) , .Test_en_S_in ( p1985 ) , .Test_en_N_out ( SYNOPSYS_UNCONNECTED_4592 ) , .pReset_S_in ( SYNOPSYS_UNCONNECTED_4593 ) , .pReset_E_in ( SYNOPSYS_UNCONNECTED_4594 ) , .pReset_W_in ( pResetWires[193] ) , .pReset_N_out ( pResetWires[195] ) , .pReset_W_out ( SYNOPSYS_UNCONNECTED_4595 ) , - .pReset_E_out ( pResetWires[196] ) , .Reset_S_in ( p3395 ) , + .pReset_E_out ( pResetWires[196] ) , .Reset_S_in ( p1985 ) , .Reset_N_out ( SYNOPSYS_UNCONNECTED_4596 ) , .prog_clk_0_N_in ( prog_clk_0_wires[340] ) , .prog_clk_1_N_in ( prog_clk_2_wires[89] ) , .prog_clk_1_S_in ( SYNOPSYS_UNCONNECTED_4597 ) , .prog_clk_1_E_out ( prog_clk_1_wires[176] ) , - .prog_clk_1_W_out ( prog_clk_1_wires[177] ) , .prog_clk_2_N_in ( p2379 ) , - .prog_clk_2_E_in ( p492 ) , .prog_clk_2_S_in ( p1270 ) , - .prog_clk_2_W_in ( p437 ) , + .prog_clk_1_W_out ( prog_clk_1_wires[177] ) , .prog_clk_2_N_in ( p3511 ) , + .prog_clk_2_E_in ( p347 ) , .prog_clk_2_S_in ( p195 ) , + .prog_clk_2_W_in ( p1012 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_4598 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_4599 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_4600 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_4601 ) , - .prog_clk_3_W_in ( p2204 ) , .prog_clk_3_E_in ( p1371 ) , - .prog_clk_3_S_in ( p640 ) , .prog_clk_3_N_in ( p2319 ) , + .prog_clk_3_W_in ( p3426 ) , .prog_clk_3_E_in ( p999 ) , + .prog_clk_3_S_in ( p1214 ) , .prog_clk_3_N_in ( p3479 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_4602 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4603 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_4604 ) , @@ -139182,12 +142748,12 @@ sb_1__1_ sb_9__3_ ( .clk_1_N_in ( clk_2_wires[89] ) , .clk_1_S_in ( SYNOPSYS_UNCONNECTED_4606 ) , .clk_1_E_out ( clk_1_wires[176] ) , .clk_1_W_out ( clk_1_wires[177] ) , - .clk_2_N_in ( p2265 ) , .clk_2_E_in ( p1053 ) , .clk_2_S_in ( p3380 ) , - .clk_2_W_in ( p2035 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_4607 ) , + .clk_2_N_in ( p3502 ) , .clk_2_E_in ( p551 ) , .clk_2_S_in ( p489 ) , + .clk_2_W_in ( p3521 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_4607 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_4608 ) , .clk_2_N_out ( SYNOPSYS_UNCONNECTED_4609 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_4610 ) , .clk_3_W_in ( p2204 ) , - .clk_3_E_in ( p147 ) , .clk_3_S_in ( p1326 ) , .clk_3_N_in ( p2048 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_4610 ) , .clk_3_W_in ( p3538 ) , + .clk_3_E_in ( p167 ) , .clk_3_S_in ( p1716 ) , .clk_3_N_in ( p3494 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_4611 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4612 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_4613 ) , @@ -139235,16 +142801,16 @@ sb_1__1_ sb_9__4_ ( .chanx_right_out ( sb_1__1__91_chanx_right_out ) , .chany_bottom_out ( sb_1__1__91_chany_bottom_out ) , .chanx_left_out ( sb_1__1__91_chanx_left_out ) , - .ccff_tail ( sb_1__1__91_ccff_tail ) , .Test_en_S_in ( p2836 ) , + .ccff_tail ( sb_1__1__91_ccff_tail ) , .Test_en_S_in ( p2801 ) , .Test_en_N_out ( SYNOPSYS_UNCONNECTED_4616 ) , .pReset_S_in ( SYNOPSYS_UNCONNECTED_4617 ) , .pReset_E_in ( SYNOPSYS_UNCONNECTED_4618 ) , .pReset_W_in ( pResetWires[242] ) , .pReset_N_out ( pResetWires[244] ) , .pReset_W_out ( SYNOPSYS_UNCONNECTED_4619 ) , - .pReset_E_out ( pResetWires[245] ) , .Reset_S_in ( p2836 ) , + .pReset_E_out ( pResetWires[245] ) , .Reset_S_in ( p2801 ) , .Reset_N_out ( SYNOPSYS_UNCONNECTED_4620 ) , - .prog_clk_0_N_in ( prog_clk_0_wires[343] ) , .prog_clk_1_N_in ( p1557 ) , - .prog_clk_1_S_in ( p832 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[343] ) , .prog_clk_1_N_in ( p2310 ) , + .prog_clk_1_S_in ( p1086 ) , .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_4621 ) , .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_4622 ) , .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_4623 ) , @@ -139255,13 +142821,13 @@ sb_1__1_ sb_9__4_ ( .prog_clk_2_S_out ( prog_clk_2_wires[88] ) , .prog_clk_2_N_out ( prog_clk_2_wires[86] ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_4627 ) , - .prog_clk_3_W_in ( p1614 ) , .prog_clk_3_E_in ( p744 ) , - .prog_clk_3_S_in ( p347 ) , .prog_clk_3_N_in ( p2017 ) , + .prog_clk_3_W_in ( p2218 ) , .prog_clk_3_E_in ( p812 ) , + .prog_clk_3_S_in ( p698 ) , .prog_clk_3_N_in ( p1803 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_4628 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4629 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_4630 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_4631 ) , .clk_1_N_in ( p1557 ) , - .clk_1_S_in ( p52 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_4632 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_4631 ) , .clk_1_N_in ( p2310 ) , + .clk_1_S_in ( p644 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_4632 ) , .clk_1_W_out ( SYNOPSYS_UNCONNECTED_4633 ) , .clk_2_N_in ( SYNOPSYS_UNCONNECTED_4634 ) , .clk_2_E_in ( SYNOPSYS_UNCONNECTED_4635 ) , @@ -139269,8 +142835,8 @@ sb_1__1_ sb_9__4_ ( .clk_2_W_in ( clk_2_wires[79] ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_4637 ) , .clk_2_S_out ( clk_2_wires[88] ) , .clk_2_N_out ( clk_2_wires[86] ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_4638 ) , .clk_3_W_in ( p1614 ) , - .clk_3_E_in ( p42 ) , .clk_3_S_in ( p2740 ) , .clk_3_N_in ( p361 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_4638 ) , .clk_3_W_in ( p2305 ) , + .clk_3_E_in ( p56 ) , .clk_3_S_in ( p2665 ) , .clk_3_N_in ( p2063 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_4639 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4640 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_4641 ) , @@ -139318,40 +142884,40 @@ sb_1__1_ sb_9__5_ ( .chanx_right_out ( sb_1__1__92_chanx_right_out ) , .chany_bottom_out ( sb_1__1__92_chany_bottom_out ) , .chanx_left_out ( sb_1__1__92_chanx_left_out ) , - .ccff_tail ( sb_1__1__92_ccff_tail ) , .Test_en_S_in ( p2826 ) , + .ccff_tail ( sb_1__1__92_ccff_tail ) , .Test_en_S_in ( p1956 ) , .Test_en_N_out ( SYNOPSYS_UNCONNECTED_4644 ) , .pReset_S_in ( SYNOPSYS_UNCONNECTED_4645 ) , .pReset_E_in ( SYNOPSYS_UNCONNECTED_4646 ) , .pReset_W_in ( pResetWires[291] ) , .pReset_N_out ( pResetWires[293] ) , .pReset_W_out ( SYNOPSYS_UNCONNECTED_4647 ) , - .pReset_E_out ( pResetWires[294] ) , .Reset_S_in ( p3407 ) , + .pReset_E_out ( pResetWires[294] ) , .Reset_S_in ( p1956 ) , .Reset_N_out ( SYNOPSYS_UNCONNECTED_4648 ) , .prog_clk_0_N_in ( prog_clk_0_wires[346] ) , .prog_clk_1_N_in ( SYNOPSYS_UNCONNECTED_4649 ) , .prog_clk_1_S_in ( prog_clk_2_wires[87] ) , .prog_clk_1_E_out ( prog_clk_1_wires[183] ) , - .prog_clk_1_W_out ( prog_clk_1_wires[184] ) , .prog_clk_2_N_in ( p3509 ) , - .prog_clk_2_E_in ( p830 ) , .prog_clk_2_S_in ( p713 ) , - .prog_clk_2_W_in ( p195 ) , + .prog_clk_1_W_out ( prog_clk_1_wires[184] ) , .prog_clk_2_N_in ( p3157 ) , + .prog_clk_2_E_in ( p577 ) , .prog_clk_2_S_in ( p432 ) , + .prog_clk_2_W_in ( p50 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_4650 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_4651 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_4652 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_4653 ) , - .prog_clk_3_W_in ( p2708 ) , .prog_clk_3_E_in ( p281 ) , - .prog_clk_3_S_in ( p1331 ) , .prog_clk_3_N_in ( p3508 ) , + .prog_clk_3_W_in ( p3474 ) , .prog_clk_3_E_in ( p821 ) , + .prog_clk_3_S_in ( p1253 ) , .prog_clk_3_N_in ( p3047 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_4654 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4655 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_4656 ) , .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_4657 ) , .clk_1_N_in ( SYNOPSYS_UNCONNECTED_4658 ) , .clk_1_S_in ( clk_2_wires[87] ) , .clk_1_E_out ( clk_1_wires[183] ) , - .clk_1_W_out ( clk_1_wires[184] ) , .clk_2_N_in ( p1960 ) , - .clk_2_E_in ( p1031 ) , .clk_2_S_in ( p3387 ) , .clk_2_W_in ( p2566 ) , + .clk_1_W_out ( clk_1_wires[184] ) , .clk_2_N_in ( p3412 ) , + .clk_2_E_in ( p712 ) , .clk_2_S_in ( p473 ) , .clk_2_W_in ( p3442 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_4659 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_4660 ) , .clk_2_N_out ( SYNOPSYS_UNCONNECTED_4661 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_4662 ) , .clk_3_W_in ( p2708 ) , - .clk_3_E_in ( p1129 ) , .clk_3_S_in ( p318 ) , .clk_3_N_in ( p1713 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_4662 ) , .clk_3_W_in ( p3347 ) , + .clk_3_E_in ( p160 ) , .clk_3_S_in ( p1691 ) , .clk_3_N_in ( p3371 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_4663 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4664 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_4665 ) , @@ -139399,20 +142965,20 @@ sb_1__1_ sb_9__6_ ( .chanx_right_out ( sb_1__1__93_chanx_right_out ) , .chany_bottom_out ( sb_1__1__93_chany_bottom_out ) , .chanx_left_out ( sb_1__1__93_chanx_left_out ) , - .ccff_tail ( sb_1__1__93_ccff_tail ) , .Test_en_S_in ( p2965 ) , + .ccff_tail ( sb_1__1__93_ccff_tail ) , .Test_en_S_in ( p1547 ) , .Test_en_N_out ( SYNOPSYS_UNCONNECTED_4668 ) , .pReset_S_in ( SYNOPSYS_UNCONNECTED_4669 ) , .pReset_E_in ( SYNOPSYS_UNCONNECTED_4670 ) , .pReset_W_in ( pResetWires[340] ) , .pReset_N_out ( pResetWires[342] ) , .pReset_W_out ( SYNOPSYS_UNCONNECTED_4671 ) , - .pReset_E_out ( pResetWires[343] ) , .Reset_S_in ( p2965 ) , + .pReset_E_out ( pResetWires[343] ) , .Reset_S_in ( p1547 ) , .Reset_N_out ( SYNOPSYS_UNCONNECTED_4672 ) , - .prog_clk_0_N_in ( prog_clk_0_wires[349] ) , .prog_clk_1_N_in ( p1956 ) , - .prog_clk_1_S_in ( p297 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[349] ) , .prog_clk_1_N_in ( p1877 ) , + .prog_clk_1_S_in ( p1160 ) , .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_4673 ) , .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_4674 ) , - .prog_clk_2_N_in ( p2122 ) , .prog_clk_2_E_in ( p1151 ) , - .prog_clk_2_S_in ( p455 ) , .prog_clk_2_W_in ( p907 ) , + .prog_clk_2_N_in ( p1952 ) , .prog_clk_2_E_in ( p667 ) , + .prog_clk_2_S_in ( p39 ) , .prog_clk_2_W_in ( p743 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_4675 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_4676 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_4677 ) , @@ -139424,10 +142990,10 @@ sb_1__1_ sb_9__6_ ( .prog_clk_3_E_out ( prog_clk_3_wires[48] ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4682 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_4683 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_4684 ) , .clk_1_N_in ( p1956 ) , - .clk_1_S_in ( p75 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_4685 ) , - .clk_1_W_out ( SYNOPSYS_UNCONNECTED_4686 ) , .clk_2_N_in ( p1766 ) , - .clk_2_E_in ( p337 ) , .clk_2_S_in ( p2871 ) , .clk_2_W_in ( p216 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_4684 ) , .clk_1_N_in ( p1877 ) , + .clk_1_S_in ( p454 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_4685 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_4686 ) , .clk_2_N_in ( p1952 ) , + .clk_2_E_in ( p267 ) , .clk_2_S_in ( p724 ) , .clk_2_W_in ( p258 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_4687 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_4688 ) , .clk_2_N_out ( SYNOPSYS_UNCONNECTED_4689 ) , @@ -139483,27 +143049,27 @@ sb_1__1_ sb_9__7_ ( .chanx_right_out ( sb_1__1__94_chanx_right_out ) , .chany_bottom_out ( sb_1__1__94_chany_bottom_out ) , .chanx_left_out ( sb_1__1__94_chanx_left_out ) , - .ccff_tail ( sb_1__1__94_ccff_tail ) , .Test_en_S_in ( p3160 ) , + .ccff_tail ( sb_1__1__94_ccff_tail ) , .Test_en_S_in ( p2344 ) , .Test_en_N_out ( SYNOPSYS_UNCONNECTED_4698 ) , .pReset_S_in ( SYNOPSYS_UNCONNECTED_4699 ) , .pReset_E_in ( SYNOPSYS_UNCONNECTED_4700 ) , .pReset_W_in ( pResetWires[389] ) , .pReset_N_out ( pResetWires[391] ) , .pReset_W_out ( SYNOPSYS_UNCONNECTED_4701 ) , - .pReset_E_out ( pResetWires[392] ) , .Reset_S_in ( p3160 ) , + .pReset_E_out ( pResetWires[392] ) , .Reset_S_in ( p2344 ) , .Reset_N_out ( SYNOPSYS_UNCONNECTED_4702 ) , .prog_clk_0_N_in ( prog_clk_0_wires[352] ) , .prog_clk_1_N_in ( prog_clk_2_wires[102] ) , .prog_clk_1_S_in ( SYNOPSYS_UNCONNECTED_4703 ) , .prog_clk_1_E_out ( prog_clk_1_wires[190] ) , - .prog_clk_1_W_out ( prog_clk_1_wires[191] ) , .prog_clk_2_N_in ( p3454 ) , - .prog_clk_2_E_in ( p724 ) , .prog_clk_2_S_in ( p752 ) , - .prog_clk_2_W_in ( p256 ) , + .prog_clk_1_W_out ( prog_clk_1_wires[191] ) , .prog_clk_2_N_in ( p3573 ) , + .prog_clk_2_E_in ( p565 ) , .prog_clk_2_S_in ( p1336 ) , + .prog_clk_2_W_in ( p339 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_4704 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_4705 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_4706 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_4707 ) , - .prog_clk_3_W_in ( p2475 ) , .prog_clk_3_E_in ( p95 ) , - .prog_clk_3_S_in ( p1046 ) , .prog_clk_3_N_in ( p3440 ) , + .prog_clk_3_W_in ( p2630 ) , .prog_clk_3_E_in ( p1113 ) , + .prog_clk_3_S_in ( p595 ) , .prog_clk_3_N_in ( p3569 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_4708 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4709 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_4710 ) , @@ -139511,12 +143077,12 @@ sb_1__1_ sb_9__7_ ( .clk_1_N_in ( clk_2_wires[102] ) , .clk_1_S_in ( SYNOPSYS_UNCONNECTED_4712 ) , .clk_1_E_out ( clk_1_wires[190] ) , .clk_1_W_out ( clk_1_wires[191] ) , - .clk_2_N_in ( p3308 ) , .clk_2_E_in ( p1063 ) , .clk_2_S_in ( p3125 ) , - .clk_2_W_in ( p2297 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_4713 ) , + .clk_2_N_in ( p2819 ) , .clk_2_E_in ( p219 ) , .clk_2_S_in ( p1031 ) , + .clk_2_W_in ( p2431 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_4713 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_4714 ) , .clk_2_N_out ( SYNOPSYS_UNCONNECTED_4715 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_4716 ) , .clk_3_W_in ( p2475 ) , - .clk_3_E_in ( p1087 ) , .clk_3_S_in ( p1269 ) , .clk_3_N_in ( p3301 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_4716 ) , .clk_3_W_in ( p1326 ) , + .clk_3_E_in ( p1056 ) , .clk_3_S_in ( p2136 ) , .clk_3_N_in ( p2660 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_4717 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4718 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_4719 ) , @@ -139564,16 +143130,16 @@ sb_1__1_ sb_9__8_ ( .chanx_right_out ( sb_1__1__95_chanx_right_out ) , .chany_bottom_out ( sb_1__1__95_chany_bottom_out ) , .chanx_left_out ( sb_1__1__95_chanx_left_out ) , - .ccff_tail ( sb_1__1__95_ccff_tail ) , .Test_en_S_in ( p3082 ) , + .ccff_tail ( sb_1__1__95_ccff_tail ) , .Test_en_S_in ( p2313 ) , .Test_en_N_out ( SYNOPSYS_UNCONNECTED_4722 ) , .pReset_S_in ( SYNOPSYS_UNCONNECTED_4723 ) , .pReset_E_in ( SYNOPSYS_UNCONNECTED_4724 ) , .pReset_W_in ( pResetWires[438] ) , .pReset_N_out ( pResetWires[440] ) , .pReset_W_out ( SYNOPSYS_UNCONNECTED_4725 ) , - .pReset_E_out ( pResetWires[441] ) , .Reset_S_in ( p3082 ) , + .pReset_E_out ( pResetWires[441] ) , .Reset_S_in ( p2313 ) , .Reset_N_out ( SYNOPSYS_UNCONNECTED_4726 ) , - .prog_clk_0_N_in ( prog_clk_0_wires[355] ) , .prog_clk_1_N_in ( p1416 ) , - .prog_clk_1_S_in ( p591 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[355] ) , .prog_clk_1_N_in ( p2011 ) , + .prog_clk_1_S_in ( p96 ) , .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_4727 ) , .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_4728 ) , .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_4729 ) , @@ -139584,13 +143150,13 @@ sb_1__1_ sb_9__8_ ( .prog_clk_2_S_out ( prog_clk_2_wires[101] ) , .prog_clk_2_N_out ( prog_clk_2_wires[99] ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_4733 ) , - .prog_clk_3_W_in ( p1868 ) , .prog_clk_3_E_in ( p897 ) , - .prog_clk_3_S_in ( p575 ) , .prog_clk_3_N_in ( p169 ) , + .prog_clk_3_W_in ( p1433 ) , .prog_clk_3_E_in ( p130 ) , + .prog_clk_3_S_in ( p576 ) , .prog_clk_3_N_in ( p405 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_4734 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4735 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_4736 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_4737 ) , .clk_1_N_in ( p1416 ) , - .clk_1_S_in ( p893 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_4738 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_4737 ) , .clk_1_N_in ( p2011 ) , + .clk_1_S_in ( p875 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_4738 ) , .clk_1_W_out ( SYNOPSYS_UNCONNECTED_4739 ) , .clk_2_N_in ( SYNOPSYS_UNCONNECTED_4740 ) , .clk_2_E_in ( SYNOPSYS_UNCONNECTED_4741 ) , @@ -139598,8 +143164,8 @@ sb_1__1_ sb_9__8_ ( .clk_2_W_in ( clk_2_wires[92] ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_4743 ) , .clk_2_S_out ( clk_2_wires[101] ) , .clk_2_N_out ( clk_2_wires[99] ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_4744 ) , .clk_3_W_in ( p1868 ) , - .clk_3_E_in ( p321 ) , .clk_3_S_in ( p3018 ) , .clk_3_N_in ( p674 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_4744 ) , .clk_3_W_in ( p1433 ) , + .clk_3_E_in ( p967 ) , .clk_3_S_in ( p2104 ) , .clk_3_N_in ( p1680 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_4745 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4746 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_4747 ) , @@ -139647,40 +143213,40 @@ sb_1__1_ sb_9__9_ ( .chanx_right_out ( sb_1__1__96_chanx_right_out ) , .chany_bottom_out ( sb_1__1__96_chany_bottom_out ) , .chanx_left_out ( sb_1__1__96_chanx_left_out ) , - .ccff_tail ( sb_1__1__96_ccff_tail ) , .Test_en_S_in ( p2511 ) , + .ccff_tail ( sb_1__1__96_ccff_tail ) , .Test_en_S_in ( p1318 ) , .Test_en_N_out ( SYNOPSYS_UNCONNECTED_4750 ) , .pReset_S_in ( SYNOPSYS_UNCONNECTED_4751 ) , .pReset_E_in ( SYNOPSYS_UNCONNECTED_4752 ) , .pReset_W_in ( pResetWires[487] ) , .pReset_N_out ( pResetWires[489] ) , .pReset_W_out ( SYNOPSYS_UNCONNECTED_4753 ) , - .pReset_E_out ( pResetWires[490] ) , .Reset_S_in ( p2511 ) , + .pReset_E_out ( pResetWires[490] ) , .Reset_S_in ( p1318 ) , .Reset_N_out ( SYNOPSYS_UNCONNECTED_4754 ) , .prog_clk_0_N_in ( prog_clk_0_wires[358] ) , .prog_clk_1_N_in ( SYNOPSYS_UNCONNECTED_4755 ) , .prog_clk_1_S_in ( prog_clk_2_wires[100] ) , .prog_clk_1_E_out ( prog_clk_1_wires[197] ) , - .prog_clk_1_W_out ( prog_clk_1_wires[198] ) , .prog_clk_2_N_in ( p3470 ) , - .prog_clk_2_E_in ( p545 ) , .prog_clk_2_S_in ( p439 ) , - .prog_clk_2_W_in ( p536 ) , + .prog_clk_1_W_out ( prog_clk_1_wires[198] ) , .prog_clk_2_N_in ( p3248 ) , + .prog_clk_2_E_in ( p536 ) , .prog_clk_2_S_in ( p678 ) , + .prog_clk_2_W_in ( p903 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_4756 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_4757 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_4758 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_4759 ) , - .prog_clk_3_W_in ( p2683 ) , .prog_clk_3_E_in ( p1215 ) , - .prog_clk_3_S_in ( p1450 ) , .prog_clk_3_N_in ( p3462 ) , + .prog_clk_3_W_in ( p2311 ) , .prog_clk_3_E_in ( p544 ) , + .prog_clk_3_S_in ( p1077 ) , .prog_clk_3_N_in ( p3195 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_4760 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4761 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_4762 ) , .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_4763 ) , .clk_1_N_in ( SYNOPSYS_UNCONNECTED_4764 ) , .clk_1_S_in ( clk_2_wires[100] ) , .clk_1_E_out ( clk_1_wires[197] ) , - .clk_1_W_out ( clk_1_wires[198] ) , .clk_2_N_in ( p3370 ) , - .clk_2_E_in ( p927 ) , .clk_2_S_in ( p2318 ) , .clk_2_W_in ( p2537 ) , + .clk_1_W_out ( clk_1_wires[198] ) , .clk_2_N_in ( p2074 ) , + .clk_2_E_in ( p69 ) , .clk_2_S_in ( p159 ) , .clk_2_W_in ( p3438 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_4765 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_4766 ) , .clk_2_N_out ( SYNOPSYS_UNCONNECTED_4767 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_4768 ) , .clk_3_W_in ( p2683 ) , - .clk_3_E_in ( p335 ) , .clk_3_S_in ( p1332 ) , .clk_3_N_in ( p3343 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_4768 ) , .clk_3_W_in ( p3458 ) , + .clk_3_E_in ( p1231 ) , .clk_3_S_in ( p1144 ) , .clk_3_N_in ( p2198 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_4769 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4770 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_4771 ) , @@ -139728,16 +143294,16 @@ sb_1__1_ sb_9__10_ ( .chanx_right_out ( sb_1__1__97_chanx_right_out ) , .chany_bottom_out ( sb_1__1__97_chany_bottom_out ) , .chanx_left_out ( sb_1__1__97_chanx_left_out ) , - .ccff_tail ( sb_1__1__97_ccff_tail ) , .Test_en_S_in ( p2967 ) , + .ccff_tail ( sb_1__1__97_ccff_tail ) , .Test_en_S_in ( p1942 ) , .Test_en_N_out ( SYNOPSYS_UNCONNECTED_4774 ) , .pReset_S_in ( SYNOPSYS_UNCONNECTED_4775 ) , .pReset_E_in ( SYNOPSYS_UNCONNECTED_4776 ) , .pReset_W_in ( pResetWires[536] ) , .pReset_N_out ( pResetWires[538] ) , .pReset_W_out ( SYNOPSYS_UNCONNECTED_4777 ) , - .pReset_E_out ( pResetWires[539] ) , .Reset_S_in ( p2967 ) , + .pReset_E_out ( pResetWires[539] ) , .Reset_S_in ( p1942 ) , .Reset_N_out ( SYNOPSYS_UNCONNECTED_4778 ) , - .prog_clk_0_N_in ( prog_clk_0_wires[361] ) , .prog_clk_1_N_in ( p1328 ) , - .prog_clk_1_S_in ( p1019 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[361] ) , .prog_clk_1_N_in ( p1961 ) , + .prog_clk_1_S_in ( p751 ) , .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_4779 ) , .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_4780 ) , .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_4781 ) , @@ -139748,13 +143314,13 @@ sb_1__1_ sb_9__10_ ( .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_4785 ) , .prog_clk_2_N_out ( prog_clk_2_wires[110] ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_4786 ) , - .prog_clk_3_W_in ( p1556 ) , .prog_clk_3_E_in ( p760 ) , - .prog_clk_3_S_in ( p368 ) , .prog_clk_3_N_in ( p765 ) , + .prog_clk_3_W_in ( p1898 ) , .prog_clk_3_E_in ( p624 ) , + .prog_clk_3_S_in ( p147 ) , .prog_clk_3_N_in ( p367 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_4787 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4788 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_4789 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_4790 ) , .clk_1_N_in ( p1328 ) , - .clk_1_S_in ( p104 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_4791 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_4790 ) , .clk_1_N_in ( p1961 ) , + .clk_1_S_in ( p415 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_4791 ) , .clk_1_W_out ( SYNOPSYS_UNCONNECTED_4792 ) , .clk_2_N_in ( SYNOPSYS_UNCONNECTED_4793 ) , .clk_2_E_in ( SYNOPSYS_UNCONNECTED_4794 ) , @@ -139763,8 +143329,8 @@ sb_1__1_ sb_9__10_ ( .clk_2_W_out ( SYNOPSYS_UNCONNECTED_4796 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_4797 ) , .clk_2_N_out ( clk_2_wires[110] ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_4798 ) , .clk_3_W_in ( p1556 ) , - .clk_3_E_in ( p210 ) , .clk_3_S_in ( p2869 ) , .clk_3_N_in ( p395 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_4798 ) , .clk_3_W_in ( p1898 ) , + .clk_3_E_in ( p393 ) , .clk_3_S_in ( p1709 ) , .clk_3_N_in ( p1721 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_4799 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4800 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_4801 ) , @@ -139812,40 +143378,40 @@ sb_1__1_ sb_9__11_ ( .chanx_right_out ( sb_1__1__98_chanx_right_out ) , .chany_bottom_out ( sb_1__1__98_chany_bottom_out ) , .chanx_left_out ( sb_1__1__98_chanx_left_out ) , - .ccff_tail ( sb_1__1__98_ccff_tail ) , .Test_en_S_in ( p2151 ) , + .ccff_tail ( sb_1__1__98_ccff_tail ) , .Test_en_S_in ( p2558 ) , .Test_en_N_out ( SYNOPSYS_UNCONNECTED_4804 ) , .pReset_S_in ( SYNOPSYS_UNCONNECTED_4805 ) , .pReset_E_in ( SYNOPSYS_UNCONNECTED_4806 ) , .pReset_W_in ( pResetWires[585] ) , .pReset_N_out ( pResetWires[587] ) , .pReset_W_out ( SYNOPSYS_UNCONNECTED_4807 ) , - .pReset_E_out ( pResetWires[588] ) , .Reset_S_in ( p3478 ) , + .pReset_E_out ( pResetWires[588] ) , .Reset_S_in ( p2558 ) , .Reset_N_out ( SYNOPSYS_UNCONNECTED_4808 ) , .prog_clk_0_N_in ( prog_clk_0_wires[364] ) , .prog_clk_1_N_in ( SYNOPSYS_UNCONNECTED_4809 ) , .prog_clk_1_S_in ( prog_clk_2_wires[111] ) , .prog_clk_1_E_out ( prog_clk_1_wires[204] ) , - .prog_clk_1_W_out ( prog_clk_1_wires[205] ) , .prog_clk_2_N_in ( p3469 ) , - .prog_clk_2_E_in ( p929 ) , .prog_clk_2_S_in ( p478 ) , - .prog_clk_2_W_in ( p524 ) , + .prog_clk_1_W_out ( prog_clk_1_wires[205] ) , .prog_clk_2_N_in ( p2515 ) , + .prog_clk_2_E_in ( p474 ) , .prog_clk_2_S_in ( p174 ) , + .prog_clk_2_W_in ( p221 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_4810 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_4811 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_4812 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_4813 ) , - .prog_clk_3_W_in ( p1851 ) , .prog_clk_3_E_in ( p214 ) , - .prog_clk_3_S_in ( p754 ) , .prog_clk_3_N_in ( p3459 ) , + .prog_clk_3_W_in ( p2040 ) , .prog_clk_3_E_in ( p888 ) , + .prog_clk_3_S_in ( p1128 ) , .prog_clk_3_N_in ( p2467 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_4814 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4815 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_4816 ) , .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_4817 ) , .clk_1_N_in ( SYNOPSYS_UNCONNECTED_4818 ) , .clk_1_S_in ( clk_2_wires[111] ) , .clk_1_E_out ( clk_1_wires[204] ) , - .clk_1_W_out ( clk_1_wires[205] ) , .clk_2_N_in ( p3098 ) , - .clk_2_E_in ( p913 ) , .clk_2_S_in ( p3474 ) , .clk_2_W_in ( p1704 ) , + .clk_1_W_out ( clk_1_wires[205] ) , .clk_2_N_in ( p3556 ) , + .clk_2_E_in ( p108 ) , .clk_2_S_in ( p931 ) , .clk_2_W_in ( p2913 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_4819 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_4820 ) , .clk_2_N_out ( SYNOPSYS_UNCONNECTED_4821 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_4822 ) , .clk_3_W_in ( p1851 ) , - .clk_3_E_in ( p873 ) , .clk_3_S_in ( p1386 ) , .clk_3_N_in ( p3004 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_4822 ) , .clk_3_W_in ( p2993 ) , + .clk_3_E_in ( p1247 ) , .clk_3_S_in ( p2383 ) , .clk_3_N_in ( p3551 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_4823 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4824 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_4825 ) , @@ -139893,38 +143459,38 @@ sb_1__1_ sb_10__1_ ( .chanx_right_out ( sb_1__1__99_chanx_right_out ) , .chany_bottom_out ( sb_1__1__99_chany_bottom_out ) , .chanx_left_out ( sb_1__1__99_chanx_left_out ) , - .ccff_tail ( sb_1__1__99_ccff_tail ) , .Test_en_S_in ( p2490 ) , + .ccff_tail ( sb_1__1__99_ccff_tail ) , .Test_en_S_in ( p1357 ) , .Test_en_N_out ( SYNOPSYS_UNCONNECTED_4828 ) , .pReset_S_in ( SYNOPSYS_UNCONNECTED_4829 ) , .pReset_E_in ( SYNOPSYS_UNCONNECTED_4830 ) , .pReset_W_in ( pResetWires[99] ) , .pReset_N_out ( pResetWires[101] ) , .pReset_W_out ( SYNOPSYS_UNCONNECTED_4831 ) , - .pReset_E_out ( pResetWires[102] ) , .Reset_S_in ( p2388 ) , + .pReset_E_out ( pResetWires[102] ) , .Reset_S_in ( p1357 ) , .Reset_N_out ( SYNOPSYS_UNCONNECTED_4832 ) , - .prog_clk_0_N_in ( prog_clk_0_wires[372] ) , .prog_clk_1_N_in ( p1841 ) , - .prog_clk_1_S_in ( p1079 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[372] ) , .prog_clk_1_N_in ( p1838 ) , + .prog_clk_1_S_in ( p1072 ) , .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_4833 ) , .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_4834 ) , - .prog_clk_2_N_in ( p3371 ) , .prog_clk_2_E_in ( p827 ) , - .prog_clk_2_S_in ( p658 ) , .prog_clk_2_W_in ( p1268 ) , + .prog_clk_2_N_in ( p3503 ) , .prog_clk_2_E_in ( p953 ) , + .prog_clk_2_S_in ( p844 ) , .prog_clk_2_W_in ( p232 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_4835 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_4836 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_4837 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_4838 ) , - .prog_clk_3_W_in ( p2934 ) , .prog_clk_3_E_in ( p1152 ) , - .prog_clk_3_S_in ( p1187 ) , .prog_clk_3_N_in ( p3342 ) , + .prog_clk_3_W_in ( p1993 ) , .prog_clk_3_E_in ( p561 ) , + .prog_clk_3_S_in ( p46 ) , .prog_clk_3_N_in ( p3483 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_4839 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4840 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_4841 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_4842 ) , .clk_1_N_in ( p1841 ) , - .clk_1_S_in ( p208 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_4843 ) , - .clk_1_W_out ( SYNOPSYS_UNCONNECTED_4844 ) , .clk_2_N_in ( p2695 ) , - .clk_2_E_in ( p708 ) , .clk_2_S_in ( p2334 ) , .clk_2_W_in ( p2875 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_4842 ) , .clk_1_N_in ( p1838 ) , + .clk_1_S_in ( p419 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_4843 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_4844 ) , .clk_2_N_in ( p3532 ) , + .clk_2_E_in ( p807 ) , .clk_2_S_in ( p773 ) , .clk_2_W_in ( p3293 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_4845 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_4846 ) , .clk_2_N_out ( SYNOPSYS_UNCONNECTED_4847 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_4848 ) , .clk_3_W_in ( p2934 ) , - .clk_3_E_in ( p28 ) , .clk_3_S_in ( p1408 ) , .clk_3_N_in ( p2557 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_4848 ) , .clk_3_W_in ( p3338 ) , + .clk_3_E_in ( p29 ) , .clk_3_S_in ( p1124 ) , .clk_3_N_in ( p3519 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_4849 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4850 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_4851 ) , @@ -139972,16 +143538,16 @@ sb_1__1_ sb_10__2_ ( .chanx_right_out ( sb_1__1__100_chanx_right_out ) , .chany_bottom_out ( sb_1__1__100_chany_bottom_out ) , .chanx_left_out ( sb_1__1__100_chanx_left_out ) , - .ccff_tail ( sb_1__1__100_ccff_tail ) , .Test_en_S_in ( p2505 ) , + .ccff_tail ( sb_1__1__100_ccff_tail ) , .Test_en_S_in ( p2007 ) , .Test_en_N_out ( SYNOPSYS_UNCONNECTED_4854 ) , .pReset_S_in ( SYNOPSYS_UNCONNECTED_4855 ) , .pReset_E_in ( SYNOPSYS_UNCONNECTED_4856 ) , .pReset_W_in ( pResetWires[148] ) , .pReset_N_out ( pResetWires[150] ) , .pReset_W_out ( SYNOPSYS_UNCONNECTED_4857 ) , - .pReset_E_out ( pResetWires[151] ) , .Reset_S_in ( p2505 ) , + .pReset_E_out ( pResetWires[151] ) , .Reset_S_in ( p2007 ) , .Reset_N_out ( SYNOPSYS_UNCONNECTED_4858 ) , - .prog_clk_0_N_in ( prog_clk_0_wires[375] ) , .prog_clk_1_N_in ( p1913 ) , - .prog_clk_1_S_in ( p231 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[375] ) , .prog_clk_1_N_in ( p2290 ) , + .prog_clk_1_S_in ( p557 ) , .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_4859 ) , .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_4860 ) , .prog_clk_2_N_in ( prog_clk_3_wires[87] ) , @@ -139991,14 +143557,14 @@ sb_1__1_ sb_10__2_ ( .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_4864 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_4865 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_4866 ) , - .prog_clk_2_E_out ( prog_clk_2_wires[114] ) , .prog_clk_3_W_in ( p1451 ) , - .prog_clk_3_E_in ( p397 ) , .prog_clk_3_S_in ( p666 ) , - .prog_clk_3_N_in ( p109 ) , + .prog_clk_2_E_out ( prog_clk_2_wires[114] ) , .prog_clk_3_W_in ( p1432 ) , + .prog_clk_3_E_in ( p110 ) , .prog_clk_3_S_in ( p572 ) , + .prog_clk_3_N_in ( p780 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_4867 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4868 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_4869 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_4870 ) , .clk_1_N_in ( p1829 ) , - .clk_1_S_in ( p967 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_4871 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_4870 ) , .clk_1_N_in ( p2290 ) , + .clk_1_S_in ( p946 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_4871 ) , .clk_1_W_out ( SYNOPSYS_UNCONNECTED_4872 ) , .clk_2_N_in ( clk_3_wires[87] ) , .clk_2_E_in ( SYNOPSYS_UNCONNECTED_4873 ) , @@ -140007,8 +143573,8 @@ sb_1__1_ sb_10__2_ ( .clk_2_W_out ( SYNOPSYS_UNCONNECTED_4876 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_4877 ) , .clk_2_N_out ( SYNOPSYS_UNCONNECTED_4878 ) , - .clk_2_E_out ( clk_2_wires[114] ) , .clk_3_W_in ( p1451 ) , - .clk_3_E_in ( p1069 ) , .clk_3_S_in ( p2317 ) , .clk_3_N_in ( p1681 ) , + .clk_2_E_out ( clk_2_wires[114] ) , .clk_3_W_in ( p1432 ) , + .clk_3_E_in ( p1673 ) , .clk_3_S_in ( p1760 ) , .clk_3_N_in ( p2100 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_4879 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4880 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_4881 ) , @@ -140056,20 +143622,20 @@ sb_1__1_ sb_10__3_ ( .chanx_right_out ( sb_1__1__101_chanx_right_out ) , .chany_bottom_out ( sb_1__1__101_chany_bottom_out ) , .chanx_left_out ( sb_1__1__101_chanx_left_out ) , - .ccff_tail ( sb_1__1__101_ccff_tail ) , .Test_en_S_in ( p2931 ) , + .ccff_tail ( sb_1__1__101_ccff_tail ) , .Test_en_S_in ( p1137 ) , .Test_en_N_out ( SYNOPSYS_UNCONNECTED_4884 ) , .pReset_S_in ( SYNOPSYS_UNCONNECTED_4885 ) , .pReset_E_in ( SYNOPSYS_UNCONNECTED_4886 ) , .pReset_W_in ( pResetWires[197] ) , .pReset_N_out ( pResetWires[199] ) , .pReset_W_out ( SYNOPSYS_UNCONNECTED_4887 ) , - .pReset_E_out ( pResetWires[200] ) , .Reset_S_in ( p3249 ) , + .pReset_E_out ( pResetWires[200] ) , .Reset_S_in ( p1137 ) , .Reset_N_out ( SYNOPSYS_UNCONNECTED_4888 ) , - .prog_clk_0_N_in ( prog_clk_0_wires[378] ) , .prog_clk_1_N_in ( p1846 ) , - .prog_clk_1_S_in ( p527 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[378] ) , .prog_clk_1_N_in ( p1580 ) , + .prog_clk_1_S_in ( p1217 ) , .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_4889 ) , .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_4890 ) , - .prog_clk_2_N_in ( p2991 ) , .prog_clk_2_E_in ( p928 ) , - .prog_clk_2_S_in ( p1653 ) , .prog_clk_2_W_in ( p1180 ) , + .prog_clk_2_N_in ( p1949 ) , .prog_clk_2_E_in ( p1034 ) , + .prog_clk_2_S_in ( p1792 ) , .prog_clk_2_W_in ( p368 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_4891 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_4892 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_4893 ) , @@ -140081,10 +143647,10 @@ sb_1__1_ sb_10__3_ ( .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_4898 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4899 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_4900 ) , - .prog_clk_3_S_out ( prog_clk_3_wires[86] ) , .clk_1_N_in ( p1846 ) , - .clk_1_S_in ( p401 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_4901 ) , - .clk_1_W_out ( SYNOPSYS_UNCONNECTED_4902 ) , .clk_2_N_in ( p2694 ) , - .clk_2_E_in ( p513 ) , .clk_2_S_in ( p3215 ) , .clk_2_W_in ( p29 ) , + .prog_clk_3_S_out ( prog_clk_3_wires[86] ) , .clk_1_N_in ( p1580 ) , + .clk_1_S_in ( p463 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_4901 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_4902 ) , .clk_2_N_in ( p1949 ) , + .clk_2_E_in ( p424 ) , .clk_2_S_in ( p1702 ) , .clk_2_W_in ( p839 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_4903 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_4904 ) , .clk_2_N_out ( SYNOPSYS_UNCONNECTED_4905 ) , @@ -140140,16 +143706,16 @@ sb_1__1_ sb_10__4_ ( .chanx_right_out ( sb_1__1__102_chanx_right_out ) , .chany_bottom_out ( sb_1__1__102_chany_bottom_out ) , .chanx_left_out ( sb_1__1__102_chanx_left_out ) , - .ccff_tail ( sb_1__1__102_ccff_tail ) , .Test_en_S_in ( p1810 ) , + .ccff_tail ( sb_1__1__102_ccff_tail ) , .Test_en_S_in ( p1931 ) , .Test_en_N_out ( SYNOPSYS_UNCONNECTED_4914 ) , .pReset_S_in ( SYNOPSYS_UNCONNECTED_4915 ) , .pReset_E_in ( SYNOPSYS_UNCONNECTED_4916 ) , .pReset_W_in ( pResetWires[246] ) , .pReset_N_out ( pResetWires[248] ) , .pReset_W_out ( SYNOPSYS_UNCONNECTED_4917 ) , - .pReset_E_out ( pResetWires[249] ) , .Reset_S_in ( p1810 ) , + .pReset_E_out ( pResetWires[249] ) , .Reset_S_in ( p1931 ) , .Reset_N_out ( SYNOPSYS_UNCONNECTED_4918 ) , - .prog_clk_0_N_in ( prog_clk_0_wires[381] ) , .prog_clk_1_N_in ( p1520 ) , - .prog_clk_1_S_in ( p158 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[381] ) , .prog_clk_1_N_in ( p1362 ) , + .prog_clk_1_S_in ( p1677 ) , .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_4919 ) , .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_4920 ) , .prog_clk_2_N_in ( prog_clk_3_wires[77] ) , @@ -140167,8 +143733,8 @@ sb_1__1_ sb_10__4_ ( .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_4930 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4931 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_4932 ) , - .prog_clk_3_S_out ( prog_clk_3_wires[82] ) , .clk_1_N_in ( p1520 ) , - .clk_1_S_in ( p1655 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_4933 ) , + .prog_clk_3_S_out ( prog_clk_3_wires[82] ) , .clk_1_N_in ( p1362 ) , + .clk_1_S_in ( p759 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_4933 ) , .clk_1_W_out ( SYNOPSYS_UNCONNECTED_4934 ) , .clk_2_N_in ( clk_3_wires[77] ) , .clk_2_E_in ( SYNOPSYS_UNCONNECTED_4935 ) , @@ -140229,20 +143795,20 @@ sb_1__1_ sb_10__5_ ( .chanx_right_out ( sb_1__1__103_chanx_right_out ) , .chany_bottom_out ( sb_1__1__103_chany_bottom_out ) , .chanx_left_out ( sb_1__1__103_chanx_left_out ) , - .ccff_tail ( sb_1__1__103_ccff_tail ) , .Test_en_S_in ( p2634 ) , + .ccff_tail ( sb_1__1__103_ccff_tail ) , .Test_en_S_in ( p1953 ) , .Test_en_N_out ( SYNOPSYS_UNCONNECTED_4948 ) , .pReset_S_in ( SYNOPSYS_UNCONNECTED_4949 ) , .pReset_E_in ( SYNOPSYS_UNCONNECTED_4950 ) , .pReset_W_in ( pResetWires[295] ) , .pReset_N_out ( pResetWires[297] ) , .pReset_W_out ( SYNOPSYS_UNCONNECTED_4951 ) , - .pReset_E_out ( pResetWires[298] ) , .Reset_S_in ( p2634 ) , + .pReset_E_out ( pResetWires[298] ) , .Reset_S_in ( p1953 ) , .Reset_N_out ( SYNOPSYS_UNCONNECTED_4952 ) , - .prog_clk_0_N_in ( prog_clk_0_wires[384] ) , .prog_clk_1_N_in ( p2154 ) , - .prog_clk_1_S_in ( p725 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[384] ) , .prog_clk_1_N_in ( p1590 ) , + .prog_clk_1_S_in ( p1061 ) , .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_4953 ) , .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_4954 ) , - .prog_clk_2_N_in ( p2607 ) , .prog_clk_2_E_in ( p379 ) , - .prog_clk_2_S_in ( p1965 ) , .prog_clk_2_W_in ( p227 ) , + .prog_clk_2_N_in ( p3006 ) , .prog_clk_2_E_in ( p263 ) , + .prog_clk_2_S_in ( p396 ) , .prog_clk_2_W_in ( p615 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_4955 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_4956 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_4957 ) , @@ -140254,10 +143820,10 @@ sb_1__1_ sb_10__5_ ( .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_4962 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4963 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_4964 ) , - .prog_clk_3_S_out ( prog_clk_3_wires[76] ) , .clk_1_N_in ( p2154 ) , - .clk_1_S_in ( p359 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_4965 ) , - .clk_1_W_out ( SYNOPSYS_UNCONNECTED_4966 ) , .clk_2_N_in ( p2607 ) , - .clk_2_E_in ( p635 ) , .clk_2_S_in ( p2554 ) , .clk_2_W_in ( p816 ) , + .prog_clk_3_S_out ( prog_clk_3_wires[76] ) , .clk_1_N_in ( p1590 ) , + .clk_1_S_in ( p111 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_4965 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_4966 ) , .clk_2_N_in ( p2775 ) , + .clk_2_E_in ( p602 ) , .clk_2_S_in ( p1692 ) , .clk_2_W_in ( p315 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_4967 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_4968 ) , .clk_2_N_out ( SYNOPSYS_UNCONNECTED_4969 ) , @@ -140313,20 +143879,20 @@ sb_1__1_ sb_10__6_ ( .chanx_right_out ( sb_1__1__104_chanx_right_out ) , .chany_bottom_out ( sb_1__1__104_chany_bottom_out ) , .chanx_left_out ( sb_1__1__104_chanx_left_out ) , - .ccff_tail ( sb_1__1__104_ccff_tail ) , .Test_en_S_in ( p2775 ) , + .ccff_tail ( sb_1__1__104_ccff_tail ) , .Test_en_S_in ( p2265 ) , .Test_en_N_out ( SYNOPSYS_UNCONNECTED_4978 ) , .pReset_S_in ( SYNOPSYS_UNCONNECTED_4979 ) , .pReset_E_in ( SYNOPSYS_UNCONNECTED_4980 ) , .pReset_W_in ( pResetWires[344] ) , .pReset_N_out ( pResetWires[346] ) , .pReset_W_out ( SYNOPSYS_UNCONNECTED_4981 ) , - .pReset_E_out ( pResetWires[347] ) , .Reset_S_in ( p2775 ) , + .pReset_E_out ( pResetWires[347] ) , .Reset_S_in ( p2265 ) , .Reset_N_out ( SYNOPSYS_UNCONNECTED_4982 ) , - .prog_clk_0_N_in ( prog_clk_0_wires[387] ) , .prog_clk_1_N_in ( p1337 ) , - .prog_clk_1_S_in ( p307 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[387] ) , .prog_clk_1_N_in ( p1400 ) , + .prog_clk_1_S_in ( p870 ) , .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_4983 ) , .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_4984 ) , - .prog_clk_2_N_in ( p2209 ) , .prog_clk_2_E_in ( p1052 ) , - .prog_clk_2_S_in ( p1694 ) , .prog_clk_2_W_in ( p346 ) , + .prog_clk_2_N_in ( p2577 ) , .prog_clk_2_E_in ( p24 ) , + .prog_clk_2_S_in ( p358 ) , .prog_clk_2_W_in ( p495 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_4985 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_4986 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_4987 ) , @@ -140338,10 +143904,10 @@ sb_1__1_ sb_10__6_ ( .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_4992 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4993 ) , .prog_clk_3_N_out ( prog_clk_3_wires[70] ) , - .prog_clk_3_S_out ( prog_clk_3_wires[72] ) , .clk_1_N_in ( p1337 ) , - .clk_1_S_in ( p1025 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_4994 ) , - .clk_1_W_out ( SYNOPSYS_UNCONNECTED_4995 ) , .clk_2_N_in ( p2209 ) , - .clk_2_E_in ( p448 ) , .clk_2_S_in ( p2743 ) , .clk_2_W_in ( p1228 ) , + .prog_clk_3_S_out ( prog_clk_3_wires[72] ) , .clk_1_N_in ( p1400 ) , + .clk_1_S_in ( p141 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_4994 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_4995 ) , .clk_2_N_in ( p1191 ) , + .clk_2_E_in ( p898 ) , .clk_2_S_in ( p2101 ) , .clk_2_W_in ( p68 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_4996 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_4997 ) , .clk_2_N_out ( SYNOPSYS_UNCONNECTED_4998 ) , @@ -140397,20 +143963,20 @@ sb_1__1_ sb_10__7_ ( .chanx_right_out ( sb_1__1__105_chanx_right_out ) , .chany_bottom_out ( sb_1__1__105_chany_bottom_out ) , .chanx_left_out ( sb_1__1__105_chanx_left_out ) , - .ccff_tail ( sb_1__1__105_ccff_tail ) , .Test_en_S_in ( p2637 ) , + .ccff_tail ( sb_1__1__105_ccff_tail ) , .Test_en_S_in ( p1603 ) , .Test_en_N_out ( SYNOPSYS_UNCONNECTED_5006 ) , .pReset_S_in ( SYNOPSYS_UNCONNECTED_5007 ) , .pReset_E_in ( SYNOPSYS_UNCONNECTED_5008 ) , .pReset_W_in ( pResetWires[393] ) , .pReset_N_out ( pResetWires[395] ) , .pReset_W_out ( SYNOPSYS_UNCONNECTED_5009 ) , - .pReset_E_out ( pResetWires[396] ) , .Reset_S_in ( p3275 ) , + .pReset_E_out ( pResetWires[396] ) , .Reset_S_in ( p1603 ) , .Reset_N_out ( SYNOPSYS_UNCONNECTED_5010 ) , - .prog_clk_0_N_in ( prog_clk_0_wires[390] ) , .prog_clk_1_N_in ( p1926 ) , - .prog_clk_1_S_in ( p253 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[390] ) , .prog_clk_1_N_in ( p1566 ) , + .prog_clk_1_S_in ( p372 ) , .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_5011 ) , .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_5012 ) , - .prog_clk_2_N_in ( p2796 ) , .prog_clk_2_E_in ( p837 ) , - .prog_clk_2_S_in ( p360 ) , .prog_clk_2_W_in ( p409 ) , + .prog_clk_2_N_in ( p1573 ) , .prog_clk_2_E_in ( p503 ) , + .prog_clk_2_S_in ( p440 ) , .prog_clk_2_W_in ( p985 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5013 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_5014 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_5015 ) , @@ -140422,10 +143988,10 @@ sb_1__1_ sb_10__7_ ( .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5020 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5021 ) , .prog_clk_3_N_out ( prog_clk_3_wires[74] ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_5022 ) , .clk_1_N_in ( p1926 ) , - .clk_1_S_in ( p1280 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_5023 ) , - .clk_1_W_out ( SYNOPSYS_UNCONNECTED_5024 ) , .clk_2_N_in ( p2776 ) , - .clk_2_E_in ( p350 ) , .clk_2_S_in ( p3212 ) , .clk_2_W_in ( p53 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_5022 ) , .clk_1_N_in ( p1566 ) , + .clk_1_S_in ( p900 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_5023 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_5024 ) , .clk_2_N_in ( p1573 ) , + .clk_2_E_in ( p316 ) , .clk_2_S_in ( p346 ) , .clk_2_W_in ( p362 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5025 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_5026 ) , .clk_2_N_out ( SYNOPSYS_UNCONNECTED_5027 ) , @@ -140481,16 +144047,16 @@ sb_1__1_ sb_10__8_ ( .chanx_right_out ( sb_1__1__106_chanx_right_out ) , .chany_bottom_out ( sb_1__1__106_chany_bottom_out ) , .chanx_left_out ( sb_1__1__106_chanx_left_out ) , - .ccff_tail ( sb_1__1__106_ccff_tail ) , .Test_en_S_in ( p1891 ) , + .ccff_tail ( sb_1__1__106_ccff_tail ) , .Test_en_S_in ( p1910 ) , .Test_en_N_out ( SYNOPSYS_UNCONNECTED_5036 ) , .pReset_S_in ( SYNOPSYS_UNCONNECTED_5037 ) , .pReset_E_in ( SYNOPSYS_UNCONNECTED_5038 ) , .pReset_W_in ( pResetWires[442] ) , .pReset_N_out ( pResetWires[444] ) , .pReset_W_out ( SYNOPSYS_UNCONNECTED_5039 ) , - .pReset_E_out ( pResetWires[445] ) , .Reset_S_in ( p1891 ) , + .pReset_E_out ( pResetWires[445] ) , .Reset_S_in ( p1910 ) , .Reset_N_out ( SYNOPSYS_UNCONNECTED_5040 ) , - .prog_clk_0_N_in ( prog_clk_0_wires[393] ) , .prog_clk_1_N_in ( p2113 ) , - .prog_clk_1_S_in ( p309 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[393] ) , .prog_clk_1_N_in ( p1638 ) , + .prog_clk_1_S_in ( p1661 ) , .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_5041 ) , .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_5042 ) , .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_5043 ) , @@ -140508,8 +144074,8 @@ sb_1__1_ sb_10__8_ ( .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5052 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5053 ) , .prog_clk_3_N_out ( prog_clk_3_wires[80] ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_5054 ) , .clk_1_N_in ( p2113 ) , - .clk_1_S_in ( p1687 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_5055 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_5054 ) , .clk_1_N_in ( p1638 ) , + .clk_1_S_in ( p755 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_5055 ) , .clk_1_W_out ( SYNOPSYS_UNCONNECTED_5056 ) , .clk_2_N_in ( SYNOPSYS_UNCONNECTED_5057 ) , .clk_2_E_in ( SYNOPSYS_UNCONNECTED_5058 ) , @@ -140570,20 +144136,20 @@ sb_1__1_ sb_10__9_ ( .chanx_right_out ( sb_1__1__107_chanx_right_out ) , .chany_bottom_out ( sb_1__1__107_chany_bottom_out ) , .chanx_left_out ( sb_1__1__107_chanx_left_out ) , - .ccff_tail ( sb_1__1__107_ccff_tail ) , .Test_en_S_in ( p2710 ) , + .ccff_tail ( sb_1__1__107_ccff_tail ) , .Test_en_S_in ( p1842 ) , .Test_en_N_out ( SYNOPSYS_UNCONNECTED_5070 ) , .pReset_S_in ( SYNOPSYS_UNCONNECTED_5071 ) , .pReset_E_in ( SYNOPSYS_UNCONNECTED_5072 ) , .pReset_W_in ( pResetWires[491] ) , .pReset_N_out ( pResetWires[493] ) , .pReset_W_out ( SYNOPSYS_UNCONNECTED_5073 ) , - .pReset_E_out ( pResetWires[494] ) , .Reset_S_in ( p2676 ) , + .pReset_E_out ( pResetWires[494] ) , .Reset_S_in ( p1842 ) , .Reset_N_out ( SYNOPSYS_UNCONNECTED_5074 ) , - .prog_clk_0_N_in ( prog_clk_0_wires[396] ) , .prog_clk_1_N_in ( p1470 ) , - .prog_clk_1_S_in ( p167 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[396] ) , .prog_clk_1_N_in ( p1471 ) , + .prog_clk_1_S_in ( p725 ) , .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_5075 ) , .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_5076 ) , - .prog_clk_2_N_in ( p1843 ) , .prog_clk_2_E_in ( p553 ) , - .prog_clk_2_S_in ( p1657 ) , .prog_clk_2_W_in ( p36 ) , + .prog_clk_2_N_in ( p2941 ) , .prog_clk_2_E_in ( p490 ) , + .prog_clk_2_S_in ( p1774 ) , .prog_clk_2_W_in ( p638 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5077 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_5078 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_5079 ) , @@ -140595,10 +144161,10 @@ sb_1__1_ sb_10__9_ ( .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5084 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5085 ) , .prog_clk_3_N_out ( prog_clk_3_wires[84] ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_5086 ) , .clk_1_N_in ( p1470 ) , - .clk_1_S_in ( p756 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_5087 ) , - .clk_1_W_out ( SYNOPSYS_UNCONNECTED_5088 ) , .clk_2_N_in ( p1925 ) , - .clk_2_E_in ( p333 ) , .clk_2_S_in ( p2543 ) , .clk_2_W_in ( p1134 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_5086 ) , .clk_1_N_in ( p1471 ) , + .clk_1_S_in ( p259 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_5087 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_5088 ) , .clk_2_N_in ( p2211 ) , + .clk_2_E_in ( p380 ) , .clk_2_S_in ( p1681 ) , .clk_2_W_in ( p176 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5089 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_5090 ) , .clk_2_N_out ( SYNOPSYS_UNCONNECTED_5091 ) , @@ -140654,16 +144220,16 @@ sb_1__1_ sb_10__10_ ( .chanx_right_out ( sb_1__1__108_chanx_right_out ) , .chany_bottom_out ( sb_1__1__108_chany_bottom_out ) , .chanx_left_out ( sb_1__1__108_chanx_left_out ) , - .ccff_tail ( sb_1__1__108_ccff_tail ) , .Test_en_S_in ( p2821 ) , + .ccff_tail ( sb_1__1__108_ccff_tail ) , .Test_en_S_in ( p1428 ) , .Test_en_N_out ( SYNOPSYS_UNCONNECTED_5100 ) , .pReset_S_in ( SYNOPSYS_UNCONNECTED_5101 ) , .pReset_E_in ( SYNOPSYS_UNCONNECTED_5102 ) , .pReset_W_in ( pResetWires[540] ) , .pReset_N_out ( pResetWires[542] ) , .pReset_W_out ( SYNOPSYS_UNCONNECTED_5103 ) , - .pReset_E_out ( pResetWires[543] ) , .Reset_S_in ( p2821 ) , + .pReset_E_out ( pResetWires[543] ) , .Reset_S_in ( p1428 ) , .Reset_N_out ( SYNOPSYS_UNCONNECTED_5104 ) , - .prog_clk_0_N_in ( prog_clk_0_wires[399] ) , .prog_clk_1_N_in ( p1471 ) , - .prog_clk_1_S_in ( p67 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[399] ) , .prog_clk_1_N_in ( p1885 ) , + .prog_clk_1_S_in ( p71 ) , .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_5105 ) , .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_5106 ) , .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_5107 ) , @@ -140673,14 +144239,14 @@ sb_1__1_ sb_10__10_ ( .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5110 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_5111 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_5112 ) , - .prog_clk_2_E_out ( prog_clk_2_wires[133] ) , .prog_clk_3_W_in ( p1579 ) , - .prog_clk_3_E_in ( p1155 ) , .prog_clk_3_S_in ( p1994 ) , - .prog_clk_3_N_in ( p40 ) , + .prog_clk_2_E_out ( prog_clk_2_wires[133] ) , .prog_clk_3_W_in ( p1287 ) , + .prog_clk_3_E_in ( p1026 ) , .prog_clk_3_S_in ( p418 ) , + .prog_clk_3_N_in ( p38 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5113 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5114 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_5115 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_5116 ) , .clk_1_N_in ( p1471 ) , - .clk_1_S_in ( p1004 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_5117 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_5116 ) , .clk_1_N_in ( p1885 ) , + .clk_1_S_in ( p1216 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_5117 ) , .clk_1_W_out ( SYNOPSYS_UNCONNECTED_5118 ) , .clk_2_N_in ( SYNOPSYS_UNCONNECTED_5119 ) , .clk_2_E_in ( SYNOPSYS_UNCONNECTED_5120 ) , @@ -140689,8 +144255,8 @@ sb_1__1_ sb_10__10_ ( .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5122 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_5123 ) , .clk_2_N_out ( SYNOPSYS_UNCONNECTED_5124 ) , - .clk_2_E_out ( clk_2_wires[133] ) , .clk_3_W_in ( p1579 ) , - .clk_3_E_in ( p1659 ) , .clk_3_S_in ( p2748 ) , .clk_3_N_in ( p730 ) , + .clk_2_E_out ( clk_2_wires[133] ) , .clk_3_W_in ( p1287 ) , + .clk_3_E_in ( p329 ) , .clk_3_S_in ( p701 ) , .clk_3_N_in ( p1749 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5125 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5126 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_5127 ) , @@ -140738,38 +144304,38 @@ sb_1__1_ sb_10__11_ ( .chanx_right_out ( sb_1__1__109_chanx_right_out ) , .chany_bottom_out ( sb_1__1__109_chany_bottom_out ) , .chanx_left_out ( sb_1__1__109_chanx_left_out ) , - .ccff_tail ( sb_1__1__109_ccff_tail ) , .Test_en_S_in ( p1845 ) , + .ccff_tail ( sb_1__1__109_ccff_tail ) , .Test_en_S_in ( p1995 ) , .Test_en_N_out ( SYNOPSYS_UNCONNECTED_5130 ) , .pReset_S_in ( SYNOPSYS_UNCONNECTED_5131 ) , .pReset_E_in ( SYNOPSYS_UNCONNECTED_5132 ) , .pReset_W_in ( pResetWires[589] ) , .pReset_N_out ( pResetWires[591] ) , .pReset_W_out ( SYNOPSYS_UNCONNECTED_5133 ) , - .pReset_E_out ( pResetWires[592] ) , .Reset_S_in ( p3093 ) , + .pReset_E_out ( pResetWires[592] ) , .Reset_S_in ( p1995 ) , .Reset_N_out ( SYNOPSYS_UNCONNECTED_5134 ) , - .prog_clk_0_N_in ( prog_clk_0_wires[402] ) , .prog_clk_1_N_in ( p1915 ) , - .prog_clk_1_S_in ( p641 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[402] ) , .prog_clk_1_N_in ( p2036 ) , + .prog_clk_1_S_in ( p64 ) , .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_5135 ) , .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_5136 ) , - .prog_clk_2_N_in ( p3320 ) , .prog_clk_2_E_in ( p80 ) , - .prog_clk_2_S_in ( p1356 ) , .prog_clk_2_W_in ( p151 ) , + .prog_clk_2_N_in ( p3471 ) , .prog_clk_2_E_in ( p434 ) , + .prog_clk_2_S_in ( p989 ) , .prog_clk_2_W_in ( p928 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5137 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_5138 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_5139 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5140 ) , - .prog_clk_3_W_in ( p2614 ) , .prog_clk_3_E_in ( p1345 ) , - .prog_clk_3_S_in ( p691 ) , .prog_clk_3_N_in ( p3284 ) , + .prog_clk_3_W_in ( p1615 ) , .prog_clk_3_E_in ( p700 ) , + .prog_clk_3_S_in ( p628 ) , .prog_clk_3_N_in ( p3441 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5141 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5142 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_5143 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_5144 ) , .clk_1_N_in ( p1915 ) , - .clk_1_S_in ( p1057 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_5145 ) , - .clk_1_W_out ( SYNOPSYS_UNCONNECTED_5146 ) , .clk_2_N_in ( p3159 ) , - .clk_2_E_in ( p767 ) , .clk_2_S_in ( p3035 ) , .clk_2_W_in ( p2551 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_5144 ) , .clk_1_N_in ( p2036 ) , + .clk_1_S_in ( p1112 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_5145 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_5146 ) , .clk_2_N_in ( p3334 ) , + .clk_2_E_in ( p67 ) , .clk_2_S_in ( p1218 ) , .clk_2_W_in ( p2682 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5147 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_5148 ) , .clk_2_N_out ( SYNOPSYS_UNCONNECTED_5149 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5150 ) , .clk_3_W_in ( p2614 ) , - .clk_3_E_in ( p623 ) , .clk_3_S_in ( p1321 ) , .clk_3_N_in ( p3123 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5150 ) , .clk_3_W_in ( p2779 ) , + .clk_3_E_in ( p1139 ) , .clk_3_S_in ( p1726 ) , .clk_3_N_in ( p3315 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5151 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5152 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_5153 ) , @@ -140817,27 +144383,27 @@ sb_1__1_ sb_11__1_ ( .chanx_right_out ( sb_1__1__110_chanx_right_out ) , .chany_bottom_out ( sb_1__1__110_chany_bottom_out ) , .chanx_left_out ( sb_1__1__110_chanx_left_out ) , - .ccff_tail ( sb_1__1__110_ccff_tail ) , .Test_en_S_in ( p2635 ) , + .ccff_tail ( sb_1__1__110_ccff_tail ) , .Test_en_S_in ( p2570 ) , .Test_en_N_out ( SYNOPSYS_UNCONNECTED_5156 ) , .pReset_S_in ( SYNOPSYS_UNCONNECTED_5157 ) , .pReset_E_in ( SYNOPSYS_UNCONNECTED_5158 ) , .pReset_W_in ( pResetWires[103] ) , .pReset_N_out ( pResetWires[105] ) , .pReset_W_out ( SYNOPSYS_UNCONNECTED_5159 ) , - .pReset_E_out ( pResetWires[106] ) , .Reset_S_in ( p3427 ) , + .pReset_E_out ( pResetWires[106] ) , .Reset_S_in ( p2570 ) , .Reset_N_out ( SYNOPSYS_UNCONNECTED_5160 ) , .prog_clk_0_N_in ( prog_clk_0_wires[410] ) , .prog_clk_1_N_in ( prog_clk_2_wires[116] ) , .prog_clk_1_S_in ( SYNOPSYS_UNCONNECTED_5161 ) , .prog_clk_1_E_out ( prog_clk_1_wires[211] ) , - .prog_clk_1_W_out ( prog_clk_1_wires[212] ) , .prog_clk_2_N_in ( p3401 ) , - .prog_clk_2_E_in ( p64 ) , .prog_clk_2_S_in ( p292 ) , - .prog_clk_2_W_in ( p1149 ) , + .prog_clk_1_W_out ( prog_clk_1_wires[212] ) , .prog_clk_2_N_in ( p3586 ) , + .prog_clk_2_E_in ( p401 ) , .prog_clk_2_S_in ( p1173 ) , + .prog_clk_2_W_in ( p836 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5162 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_5163 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_5164 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5165 ) , - .prog_clk_3_W_in ( p2992 ) , .prog_clk_3_E_in ( p1248 ) , - .prog_clk_3_S_in ( p544 ) , .prog_clk_3_N_in ( p3378 ) , + .prog_clk_3_W_in ( p2598 ) , .prog_clk_3_E_in ( p747 ) , + .prog_clk_3_S_in ( p63 ) , .prog_clk_3_N_in ( p3581 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5166 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5167 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_5168 ) , @@ -140845,12 +144411,12 @@ sb_1__1_ sb_11__1_ ( .clk_1_N_in ( clk_2_wires[116] ) , .clk_1_S_in ( SYNOPSYS_UNCONNECTED_5170 ) , .clk_1_E_out ( clk_1_wires[211] ) , .clk_1_W_out ( clk_1_wires[212] ) , - .clk_2_N_in ( p1544 ) , .clk_2_E_in ( p978 ) , .clk_2_S_in ( p3412 ) , - .clk_2_W_in ( p2889 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5171 ) , + .clk_2_N_in ( p3465 ) , .clk_2_E_in ( p5 ) , .clk_2_S_in ( p1067 ) , + .clk_2_W_in ( p3583 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5171 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_5172 ) , .clk_2_N_out ( SYNOPSYS_UNCONNECTED_5173 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5174 ) , .clk_3_W_in ( p2992 ) , - .clk_3_E_in ( p1071 ) , .clk_3_S_in ( p209 ) , .clk_3_N_in ( p312 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5174 ) , .clk_3_W_in ( p3587 ) , + .clk_3_E_in ( p849 ) , .clk_3_S_in ( p2388 ) , .clk_3_N_in ( p3437 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5175 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5176 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_5177 ) , @@ -140898,16 +144464,16 @@ sb_1__1_ sb_11__2_ ( .chanx_right_out ( sb_1__1__111_chanx_right_out ) , .chany_bottom_out ( sb_1__1__111_chany_bottom_out ) , .chanx_left_out ( sb_1__1__111_chanx_left_out ) , - .ccff_tail ( sb_1__1__111_ccff_tail ) , .Test_en_S_in ( p2112 ) , + .ccff_tail ( sb_1__1__111_ccff_tail ) , .Test_en_S_in ( p2354 ) , .Test_en_N_out ( SYNOPSYS_UNCONNECTED_5180 ) , .pReset_S_in ( SYNOPSYS_UNCONNECTED_5181 ) , .pReset_E_in ( SYNOPSYS_UNCONNECTED_5182 ) , .pReset_W_in ( pResetWires[152] ) , .pReset_N_out ( pResetWires[154] ) , .pReset_W_out ( SYNOPSYS_UNCONNECTED_5183 ) , - .pReset_E_out ( pResetWires[155] ) , .Reset_S_in ( p2112 ) , + .pReset_E_out ( pResetWires[155] ) , .Reset_S_in ( p2354 ) , .Reset_N_out ( SYNOPSYS_UNCONNECTED_5184 ) , - .prog_clk_0_N_in ( prog_clk_0_wires[413] ) , .prog_clk_1_N_in ( p1506 ) , - .prog_clk_1_S_in ( p352 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[413] ) , .prog_clk_1_N_in ( p1978 ) , + .prog_clk_1_S_in ( p940 ) , .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_5185 ) , .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_5186 ) , .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_5187 ) , @@ -140918,13 +144484,13 @@ sb_1__1_ sb_11__2_ ( .prog_clk_2_S_out ( prog_clk_2_wires[115] ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_5191 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5192 ) , - .prog_clk_3_W_in ( p1859 ) , .prog_clk_3_E_in ( p857 ) , - .prog_clk_3_S_in ( p302 ) , .prog_clk_3_N_in ( p408 ) , + .prog_clk_3_W_in ( p1999 ) , .prog_clk_3_E_in ( p70 ) , + .prog_clk_3_S_in ( p673 ) , .prog_clk_3_N_in ( p156 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5193 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5194 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_5195 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_5196 ) , .clk_1_N_in ( p1506 ) , - .clk_1_S_in ( p1017 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_5197 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_5196 ) , .clk_1_N_in ( p1978 ) , + .clk_1_S_in ( p229 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_5197 ) , .clk_1_W_out ( SYNOPSYS_UNCONNECTED_5198 ) , .clk_2_N_in ( SYNOPSYS_UNCONNECTED_5199 ) , .clk_2_E_in ( SYNOPSYS_UNCONNECTED_5200 ) , @@ -140933,8 +144499,8 @@ sb_1__1_ sb_11__2_ ( .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5202 ) , .clk_2_S_out ( clk_2_wires[115] ) , .clk_2_N_out ( SYNOPSYS_UNCONNECTED_5203 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5204 ) , .clk_3_W_in ( p1859 ) , - .clk_3_E_in ( p356 ) , .clk_3_S_in ( p1983 ) , .clk_3_N_in ( p143 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5204 ) , .clk_3_W_in ( p1999 ) , + .clk_3_E_in ( p882 ) , .clk_3_S_in ( p2088 ) , .clk_3_N_in ( p1763 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5205 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5206 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_5207 ) , @@ -140982,27 +144548,27 @@ sb_1__1_ sb_11__3_ ( .chanx_right_out ( sb_1__1__112_chanx_right_out ) , .chany_bottom_out ( sb_1__1__112_chany_bottom_out ) , .chanx_left_out ( sb_1__1__112_chanx_left_out ) , - .ccff_tail ( sb_1__1__112_ccff_tail ) , .Test_en_S_in ( p2410 ) , + .ccff_tail ( sb_1__1__112_ccff_tail ) , .Test_en_S_in ( p1858 ) , .Test_en_N_out ( SYNOPSYS_UNCONNECTED_5210 ) , .pReset_S_in ( SYNOPSYS_UNCONNECTED_5211 ) , .pReset_E_in ( SYNOPSYS_UNCONNECTED_5212 ) , .pReset_W_in ( pResetWires[201] ) , .pReset_N_out ( pResetWires[203] ) , .pReset_W_out ( SYNOPSYS_UNCONNECTED_5213 ) , - .pReset_E_out ( pResetWires[204] ) , .Reset_S_in ( p3199 ) , + .pReset_E_out ( pResetWires[204] ) , .Reset_S_in ( p1858 ) , .Reset_N_out ( SYNOPSYS_UNCONNECTED_5214 ) , .prog_clk_0_N_in ( prog_clk_0_wires[416] ) , .prog_clk_1_N_in ( prog_clk_2_wires[123] ) , .prog_clk_1_S_in ( SYNOPSYS_UNCONNECTED_5215 ) , .prog_clk_1_E_out ( prog_clk_1_wires[218] ) , - .prog_clk_1_W_out ( prog_clk_1_wires[219] ) , .prog_clk_2_N_in ( p3270 ) , - .prog_clk_2_E_in ( p895 ) , .prog_clk_2_S_in ( p1211 ) , - .prog_clk_2_W_in ( p4 ) , + .prog_clk_1_W_out ( prog_clk_1_wires[219] ) , .prog_clk_2_N_in ( p3588 ) , + .prog_clk_2_E_in ( p907 ) , .prog_clk_2_S_in ( p866 ) , + .prog_clk_2_W_in ( p254 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5216 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_5217 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_5218 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5219 ) , - .prog_clk_3_W_in ( p2853 ) , .prog_clk_3_E_in ( p71 ) , - .prog_clk_3_S_in ( p246 ) , .prog_clk_3_N_in ( p3219 ) , + .prog_clk_3_W_in ( p3151 ) , .prog_clk_3_E_in ( p664 ) , + .prog_clk_3_S_in ( p1385 ) , .prog_clk_3_N_in ( p3579 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5220 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5221 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_5222 ) , @@ -141010,12 +144576,12 @@ sb_1__1_ sb_11__3_ ( .clk_1_N_in ( clk_2_wires[123] ) , .clk_1_S_in ( SYNOPSYS_UNCONNECTED_5224 ) , .clk_1_E_out ( clk_1_wires[218] ) , .clk_1_W_out ( clk_1_wires[219] ) , - .clk_2_N_in ( p3202 ) , .clk_2_E_in ( p947 ) , .clk_2_S_in ( p3121 ) , - .clk_2_W_in ( p2719 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5225 ) , + .clk_2_N_in ( p3595 ) , .clk_2_E_in ( p1241 ) , .clk_2_S_in ( p535 ) , + .clk_2_W_in ( p3064 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5225 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_5226 ) , .clk_2_N_out ( SYNOPSYS_UNCONNECTED_5227 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5228 ) , .clk_3_W_in ( p2853 ) , - .clk_3_E_in ( p723 ) , .clk_3_S_in ( p943 ) , .clk_3_N_in ( p3128 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5228 ) , .clk_3_W_in ( p3135 ) , + .clk_3_E_in ( p138 ) , .clk_3_S_in ( p1706 ) , .clk_3_N_in ( p3592 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5229 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5230 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_5231 ) , @@ -141063,16 +144629,16 @@ sb_1__1_ sb_11__4_ ( .chanx_right_out ( sb_1__1__113_chanx_right_out ) , .chany_bottom_out ( sb_1__1__113_chany_bottom_out ) , .chanx_left_out ( sb_1__1__113_chanx_left_out ) , - .ccff_tail ( sb_1__1__113_ccff_tail ) , .Test_en_S_in ( p2424 ) , + .ccff_tail ( sb_1__1__113_ccff_tail ) , .Test_en_S_in ( p2834 ) , .Test_en_N_out ( SYNOPSYS_UNCONNECTED_5234 ) , .pReset_S_in ( SYNOPSYS_UNCONNECTED_5235 ) , .pReset_E_in ( SYNOPSYS_UNCONNECTED_5236 ) , .pReset_W_in ( pResetWires[250] ) , .pReset_N_out ( pResetWires[252] ) , .pReset_W_out ( SYNOPSYS_UNCONNECTED_5237 ) , - .pReset_E_out ( pResetWires[253] ) , .Reset_S_in ( p2424 ) , + .pReset_E_out ( pResetWires[253] ) , .Reset_S_in ( p2834 ) , .Reset_N_out ( SYNOPSYS_UNCONNECTED_5238 ) , - .prog_clk_0_N_in ( prog_clk_0_wires[419] ) , .prog_clk_1_N_in ( p1567 ) , - .prog_clk_1_S_in ( p441 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[419] ) , .prog_clk_1_N_in ( p1459 ) , + .prog_clk_1_S_in ( p1122 ) , .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_5239 ) , .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_5240 ) , .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_5241 ) , @@ -141083,13 +144649,13 @@ sb_1__1_ sb_11__4_ ( .prog_clk_2_S_out ( prog_clk_2_wires[122] ) , .prog_clk_2_N_out ( prog_clk_2_wires[120] ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5245 ) , - .prog_clk_3_W_in ( p2426 ) , .prog_clk_3_E_in ( p764 ) , - .prog_clk_3_S_in ( p514 ) , .prog_clk_3_N_in ( p546 ) , + .prog_clk_3_W_in ( p2559 ) , .prog_clk_3_E_in ( p216 ) , + .prog_clk_3_S_in ( p918 ) , .prog_clk_3_N_in ( p777 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5246 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5247 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_5248 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_5249 ) , .clk_1_N_in ( p1567 ) , - .clk_1_S_in ( p617 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_5250 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_5249 ) , .clk_1_N_in ( p1459 ) , + .clk_1_S_in ( p73 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_5250 ) , .clk_1_W_out ( SYNOPSYS_UNCONNECTED_5251 ) , .clk_2_N_in ( SYNOPSYS_UNCONNECTED_5252 ) , .clk_2_E_in ( SYNOPSYS_UNCONNECTED_5253 ) , @@ -141097,8 +144663,8 @@ sb_1__1_ sb_11__4_ ( .clk_2_W_in ( clk_2_wires[118] ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5255 ) , .clk_2_S_out ( clk_2_wires[122] ) , .clk_2_N_out ( clk_2_wires[120] ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5256 ) , .clk_3_W_in ( p2426 ) , - .clk_3_E_in ( p248 ) , .clk_3_S_in ( p2289 ) , .clk_3_N_in ( p255 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5256 ) , .clk_3_W_in ( p2559 ) , + .clk_3_E_in ( p1048 ) , .clk_3_S_in ( p2669 ) , .clk_3_N_in ( p350 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5257 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5258 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_5259 ) , @@ -141146,40 +144712,40 @@ sb_1__1_ sb_11__5_ ( .chanx_right_out ( sb_1__1__114_chanx_right_out ) , .chany_bottom_out ( sb_1__1__114_chany_bottom_out ) , .chanx_left_out ( sb_1__1__114_chanx_left_out ) , - .ccff_tail ( sb_1__1__114_ccff_tail ) , .Test_en_S_in ( p3321 ) , + .ccff_tail ( sb_1__1__114_ccff_tail ) , .Test_en_S_in ( p2267 ) , .Test_en_N_out ( SYNOPSYS_UNCONNECTED_5262 ) , .pReset_S_in ( SYNOPSYS_UNCONNECTED_5263 ) , .pReset_E_in ( SYNOPSYS_UNCONNECTED_5264 ) , .pReset_W_in ( pResetWires[299] ) , .pReset_N_out ( pResetWires[301] ) , .pReset_W_out ( SYNOPSYS_UNCONNECTED_5265 ) , - .pReset_E_out ( pResetWires[302] ) , .Reset_S_in ( p3428 ) , + .pReset_E_out ( pResetWires[302] ) , .Reset_S_in ( p2267 ) , .Reset_N_out ( SYNOPSYS_UNCONNECTED_5266 ) , .prog_clk_0_N_in ( prog_clk_0_wires[422] ) , .prog_clk_1_N_in ( SYNOPSYS_UNCONNECTED_5267 ) , .prog_clk_1_S_in ( prog_clk_2_wires[121] ) , .prog_clk_1_E_out ( prog_clk_1_wires[225] ) , - .prog_clk_1_W_out ( prog_clk_1_wires[226] ) , .prog_clk_2_N_in ( p2658 ) , - .prog_clk_2_E_in ( p1160 ) , .prog_clk_2_S_in ( p101 ) , - .prog_clk_2_W_in ( p1208 ) , + .prog_clk_1_W_out ( prog_clk_1_wires[226] ) , .prog_clk_2_N_in ( p2781 ) , + .prog_clk_2_E_in ( p690 ) , .prog_clk_2_S_in ( p1276 ) , + .prog_clk_2_W_in ( p754 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5268 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_5269 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_5270 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5271 ) , - .prog_clk_3_W_in ( p2922 ) , .prog_clk_3_E_in ( p780 ) , - .prog_clk_3_S_in ( p1412 ) , .prog_clk_3_N_in ( p2575 ) , + .prog_clk_3_W_in ( p2996 ) , .prog_clk_3_E_in ( p1003 ) , + .prog_clk_3_S_in ( p175 ) , .prog_clk_3_N_in ( p2718 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5272 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5273 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_5274 ) , .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_5275 ) , .clk_1_N_in ( SYNOPSYS_UNCONNECTED_5276 ) , .clk_1_S_in ( clk_2_wires[121] ) , .clk_1_E_out ( clk_1_wires[225] ) , - .clk_1_W_out ( clk_1_wires[226] ) , .clk_2_N_in ( p3313 ) , - .clk_2_E_in ( p166 ) , .clk_2_S_in ( p3417 ) , .clk_2_W_in ( p2866 ) , + .clk_1_W_out ( clk_1_wires[226] ) , .clk_2_N_in ( p3554 ) , + .clk_2_E_in ( p840 ) , .clk_2_S_in ( p1260 ) , .clk_2_W_in ( p3568 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5277 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_5278 ) , .clk_2_N_out ( SYNOPSYS_UNCONNECTED_5279 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5280 ) , .clk_3_W_in ( p2922 ) , - .clk_3_E_in ( p584 ) , .clk_3_S_in ( p941 ) , .clk_3_N_in ( p3294 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5280 ) , .clk_3_W_in ( p3578 ) , + .clk_3_E_in ( p105 ) , .clk_3_S_in ( p2069 ) , .clk_3_N_in ( p3543 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5281 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5282 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_5283 ) , @@ -141227,38 +144793,38 @@ sb_1__1_ sb_11__6_ ( .chanx_right_out ( sb_1__1__115_chanx_right_out ) , .chany_bottom_out ( sb_1__1__115_chany_bottom_out ) , .chanx_left_out ( sb_1__1__115_chanx_left_out ) , - .ccff_tail ( sb_1__1__115_ccff_tail ) , .Test_en_S_in ( p2924 ) , + .ccff_tail ( sb_1__1__115_ccff_tail ) , .Test_en_S_in ( p2051 ) , .Test_en_N_out ( SYNOPSYS_UNCONNECTED_5286 ) , .pReset_S_in ( SYNOPSYS_UNCONNECTED_5287 ) , .pReset_E_in ( SYNOPSYS_UNCONNECTED_5288 ) , .pReset_W_in ( pResetWires[348] ) , .pReset_N_out ( pResetWires[350] ) , .pReset_W_out ( SYNOPSYS_UNCONNECTED_5289 ) , - .pReset_E_out ( pResetWires[351] ) , .Reset_S_in ( p2924 ) , + .pReset_E_out ( pResetWires[351] ) , .Reset_S_in ( p2051 ) , .Reset_N_out ( SYNOPSYS_UNCONNECTED_5290 ) , - .prog_clk_0_N_in ( prog_clk_0_wires[425] ) , .prog_clk_1_N_in ( p1136 ) , - .prog_clk_1_S_in ( p1043 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[425] ) , .prog_clk_1_N_in ( p1621 ) , + .prog_clk_1_S_in ( p411 ) , .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_5291 ) , .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_5292 ) , - .prog_clk_2_N_in ( p3374 ) , .prog_clk_2_E_in ( p1013 ) , - .prog_clk_2_S_in ( p213 ) , .prog_clk_2_W_in ( p938 ) , + .prog_clk_2_N_in ( p3464 ) , .prog_clk_2_E_in ( p249 ) , + .prog_clk_2_S_in ( p1158 ) , .prog_clk_2_W_in ( p1064 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5293 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_5294 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_5295 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5296 ) , - .prog_clk_3_W_in ( p2416 ) , .prog_clk_3_E_in ( p305 ) , - .prog_clk_3_S_in ( p1398 ) , .prog_clk_3_N_in ( p3333 ) , + .prog_clk_3_W_in ( p2521 ) , .prog_clk_3_E_in ( p554 ) , + .prog_clk_3_S_in ( p527 ) , .prog_clk_3_N_in ( p3429 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5297 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5298 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_5299 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_5300 ) , .clk_1_N_in ( p1136 ) , - .clk_1_S_in ( p505 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_5301 ) , - .clk_1_W_out ( SYNOPSYS_UNCONNECTED_5302 ) , .clk_2_N_in ( p3058 ) , - .clk_2_E_in ( p991 ) , .clk_2_S_in ( p2902 ) , .clk_2_W_in ( p2281 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_5300 ) , .clk_1_N_in ( p1621 ) , + .clk_1_S_in ( p1147 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_5301 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_5302 ) , .clk_2_N_in ( p3596 ) , + .clk_2_E_in ( p122 ) , .clk_2_S_in ( p1288 ) , .clk_2_W_in ( p3032 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5303 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_5304 ) , .clk_2_N_out ( SYNOPSYS_UNCONNECTED_5305 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5306 ) , .clk_3_W_in ( p2416 ) , - .clk_3_E_in ( p854 ) , .clk_3_S_in ( p1290 ) , .clk_3_N_in ( p3036 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5306 ) , .clk_3_W_in ( p3140 ) , + .clk_3_E_in ( p1108 ) , .clk_3_S_in ( p1771 ) , .clk_3_N_in ( p3594 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5307 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5308 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_5309 ) , @@ -141306,27 +144872,27 @@ sb_1__1_ sb_11__7_ ( .chanx_right_out ( sb_1__1__116_chanx_right_out ) , .chany_bottom_out ( sb_1__1__116_chany_bottom_out ) , .chanx_left_out ( sb_1__1__116_chanx_left_out ) , - .ccff_tail ( sb_1__1__116_ccff_tail ) , .Test_en_S_in ( p2988 ) , + .ccff_tail ( sb_1__1__116_ccff_tail ) , .Test_en_S_in ( p2617 ) , .Test_en_N_out ( SYNOPSYS_UNCONNECTED_5312 ) , .pReset_S_in ( SYNOPSYS_UNCONNECTED_5313 ) , .pReset_E_in ( SYNOPSYS_UNCONNECTED_5314 ) , .pReset_W_in ( pResetWires[397] ) , .pReset_N_out ( pResetWires[399] ) , .pReset_W_out ( SYNOPSYS_UNCONNECTED_5315 ) , - .pReset_E_out ( pResetWires[400] ) , .Reset_S_in ( p2988 ) , + .pReset_E_out ( pResetWires[400] ) , .Reset_S_in ( p2617 ) , .Reset_N_out ( SYNOPSYS_UNCONNECTED_5316 ) , .prog_clk_0_N_in ( prog_clk_0_wires[428] ) , .prog_clk_1_N_in ( prog_clk_2_wires[130] ) , .prog_clk_1_S_in ( SYNOPSYS_UNCONNECTED_5317 ) , .prog_clk_1_E_out ( prog_clk_1_wires[232] ) , - .prog_clk_1_W_out ( prog_clk_1_wires[233] ) , .prog_clk_2_N_in ( p3436 ) , - .prog_clk_2_E_in ( p1141 ) , .prog_clk_2_S_in ( p535 ) , - .prog_clk_2_W_in ( p1140 ) , + .prog_clk_1_W_out ( prog_clk_1_wires[233] ) , .prog_clk_2_N_in ( p3597 ) , + .prog_clk_2_E_in ( p248 ) , .prog_clk_2_S_in ( p708 ) , + .prog_clk_2_W_in ( p640 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5318 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_5319 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_5320 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5321 ) , - .prog_clk_3_W_in ( p2187 ) , .prog_clk_3_E_in ( p105 ) , - .prog_clk_3_S_in ( p1107 ) , .prog_clk_3_N_in ( p3415 ) , + .prog_clk_3_W_in ( p3321 ) , .prog_clk_3_E_in ( p477 ) , + .prog_clk_3_S_in ( p1071 ) , .prog_clk_3_N_in ( p3591 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5322 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5323 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_5324 ) , @@ -141334,12 +144900,12 @@ sb_1__1_ sb_11__7_ ( .clk_1_N_in ( clk_2_wires[130] ) , .clk_1_S_in ( SYNOPSYS_UNCONNECTED_5326 ) , .clk_1_E_out ( clk_1_wires[232] ) , .clk_1_W_out ( clk_1_wires[233] ) , - .clk_2_N_in ( p2164 ) , .clk_2_E_in ( p683 ) , .clk_2_S_in ( p2888 ) , - .clk_2_W_in ( p2016 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5327 ) , + .clk_2_N_in ( p1502 ) , .clk_2_E_in ( p312 ) , .clk_2_S_in ( p977 ) , + .clk_2_W_in ( p3304 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5327 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_5328 ) , .clk_2_N_out ( SYNOPSYS_UNCONNECTED_5329 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5330 ) , .clk_3_W_in ( p2187 ) , - .clk_3_E_in ( p659 ) , .clk_3_S_in ( p1377 ) , .clk_3_N_in ( p1970 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5330 ) , .clk_3_W_in ( p2759 ) , + .clk_3_E_in ( p975 ) , .clk_3_S_in ( p2411 ) , .clk_3_N_in ( p517 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5331 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5332 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_5333 ) , @@ -141387,16 +144953,16 @@ sb_1__1_ sb_11__8_ ( .chanx_right_out ( sb_1__1__117_chanx_right_out ) , .chany_bottom_out ( sb_1__1__117_chany_bottom_out ) , .chanx_left_out ( sb_1__1__117_chanx_left_out ) , - .ccff_tail ( sb_1__1__117_ccff_tail ) , .Test_en_S_in ( p2394 ) , + .ccff_tail ( sb_1__1__117_ccff_tail ) , .Test_en_S_in ( p1304 ) , .Test_en_N_out ( SYNOPSYS_UNCONNECTED_5336 ) , .pReset_S_in ( SYNOPSYS_UNCONNECTED_5337 ) , .pReset_E_in ( SYNOPSYS_UNCONNECTED_5338 ) , .pReset_W_in ( pResetWires[446] ) , .pReset_N_out ( pResetWires[448] ) , .pReset_W_out ( SYNOPSYS_UNCONNECTED_5339 ) , - .pReset_E_out ( pResetWires[449] ) , .Reset_S_in ( p2394 ) , + .pReset_E_out ( pResetWires[449] ) , .Reset_S_in ( p1304 ) , .Reset_N_out ( SYNOPSYS_UNCONNECTED_5340 ) , - .prog_clk_0_N_in ( prog_clk_0_wires[431] ) , .prog_clk_1_N_in ( p1795 ) , - .prog_clk_1_S_in ( p547 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[431] ) , .prog_clk_1_N_in ( p1945 ) , + .prog_clk_1_S_in ( p982 ) , .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_5341 ) , .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_5342 ) , .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_5343 ) , @@ -141407,13 +144973,13 @@ sb_1__1_ sb_11__8_ ( .prog_clk_2_S_out ( prog_clk_2_wires[129] ) , .prog_clk_2_N_out ( prog_clk_2_wires[127] ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5347 ) , - .prog_clk_3_W_in ( p2438 ) , .prog_clk_3_E_in ( p191 ) , - .prog_clk_3_S_in ( p823 ) , .prog_clk_3_N_in ( p1658 ) , + .prog_clk_3_W_in ( p2023 ) , .prog_clk_3_E_in ( p846 ) , + .prog_clk_3_S_in ( p723 ) , .prog_clk_3_N_in ( p1724 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5348 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5349 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_5350 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_5351 ) , .clk_1_N_in ( p1795 ) , - .clk_1_S_in ( p447 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_5352 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_5351 ) , .clk_1_N_in ( p1945 ) , + .clk_1_S_in ( p448 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_5352 ) , .clk_1_W_out ( SYNOPSYS_UNCONNECTED_5353 ) , .clk_2_N_in ( SYNOPSYS_UNCONNECTED_5354 ) , .clk_2_E_in ( SYNOPSYS_UNCONNECTED_5355 ) , @@ -141421,8 +144987,8 @@ sb_1__1_ sb_11__8_ ( .clk_2_W_in ( clk_2_wires[125] ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5357 ) , .clk_2_S_out ( clk_2_wires[129] ) , .clk_2_N_out ( clk_2_wires[127] ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5358 ) , .clk_3_W_in ( p2438 ) , - .clk_3_E_in ( p953 ) , .clk_3_S_in ( p2287 ) , .clk_3_N_in ( p1718 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5358 ) , .clk_3_W_in ( p2023 ) , + .clk_3_E_in ( p280 ) , .clk_3_S_in ( p555 ) , .clk_3_N_in ( p1665 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5359 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5360 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_5361 ) , @@ -141470,40 +145036,40 @@ sb_1__1_ sb_11__9_ ( .chanx_right_out ( sb_1__1__118_chanx_right_out ) , .chany_bottom_out ( sb_1__1__118_chany_bottom_out ) , .chanx_left_out ( sb_1__1__118_chanx_left_out ) , - .ccff_tail ( sb_1__1__118_ccff_tail ) , .Test_en_S_in ( p2397 ) , + .ccff_tail ( sb_1__1__118_ccff_tail ) , .Test_en_S_in ( p2037 ) , .Test_en_N_out ( SYNOPSYS_UNCONNECTED_5364 ) , .pReset_S_in ( SYNOPSYS_UNCONNECTED_5365 ) , .pReset_E_in ( SYNOPSYS_UNCONNECTED_5366 ) , .pReset_W_in ( pResetWires[495] ) , .pReset_N_out ( pResetWires[497] ) , .pReset_W_out ( SYNOPSYS_UNCONNECTED_5367 ) , - .pReset_E_out ( pResetWires[498] ) , .Reset_S_in ( p3089 ) , + .pReset_E_out ( pResetWires[498] ) , .Reset_S_in ( p2037 ) , .Reset_N_out ( SYNOPSYS_UNCONNECTED_5368 ) , .prog_clk_0_N_in ( prog_clk_0_wires[434] ) , .prog_clk_1_N_in ( SYNOPSYS_UNCONNECTED_5369 ) , .prog_clk_1_S_in ( prog_clk_2_wires[128] ) , .prog_clk_1_E_out ( prog_clk_1_wires[239] ) , - .prog_clk_1_W_out ( prog_clk_1_wires[240] ) , .prog_clk_2_N_in ( p3481 ) , - .prog_clk_2_E_in ( p1277 ) , .prog_clk_2_S_in ( p667 ) , - .prog_clk_2_W_in ( p82 ) , + .prog_clk_1_W_out ( prog_clk_1_wires[240] ) , .prog_clk_2_N_in ( p3273 ) , + .prog_clk_2_E_in ( p11 ) , .prog_clk_2_S_in ( p1210 ) , + .prog_clk_2_W_in ( p612 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5370 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_5371 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_5372 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5373 ) , - .prog_clk_3_W_in ( p2981 ) , .prog_clk_3_E_in ( p997 ) , - .prog_clk_3_S_in ( p1110 ) , .prog_clk_3_N_in ( p3475 ) , + .prog_clk_3_W_in ( p3349 ) , .prog_clk_3_E_in ( p550 ) , + .prog_clk_3_S_in ( p452 ) , .prog_clk_3_N_in ( p3173 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5374 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5375 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_5376 ) , .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_5377 ) , .clk_1_N_in ( SYNOPSYS_UNCONNECTED_5378 ) , .clk_1_S_in ( clk_2_wires[128] ) , .clk_1_E_out ( clk_1_wires[239] ) , - .clk_1_W_out ( clk_1_wires[240] ) , .clk_2_N_in ( p2835 ) , - .clk_2_E_in ( p484 ) , .clk_2_S_in ( p3020 ) , .clk_2_W_in ( p2899 ) , + .clk_1_W_out ( clk_1_wires[240] ) , .clk_2_N_in ( p3561 ) , + .clk_2_E_in ( p245 ) , .clk_2_S_in ( p1325 ) , .clk_2_W_in ( p3548 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5379 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_5380 ) , .clk_2_N_out ( SYNOPSYS_UNCONNECTED_5381 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5382 ) , .clk_3_W_in ( p2981 ) , - .clk_3_E_in ( p122 ) , .clk_3_S_in ( p419 ) , .clk_3_N_in ( p2735 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5382 ) , .clk_3_W_in ( p3562 ) , + .clk_3_E_in ( p1222 ) , .clk_3_S_in ( p1743 ) , .clk_3_N_in ( p3552 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5383 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5384 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_5385 ) , @@ -141551,16 +145117,16 @@ sb_1__1_ sb_11__10_ ( .chanx_right_out ( sb_1__1__119_chanx_right_out ) , .chany_bottom_out ( sb_1__1__119_chany_bottom_out ) , .chanx_left_out ( sb_1__1__119_chanx_left_out ) , - .ccff_tail ( sb_1__1__119_ccff_tail ) , .Test_en_S_in ( p3094 ) , + .ccff_tail ( sb_1__1__119_ccff_tail ) , .Test_en_S_in ( p2266 ) , .Test_en_N_out ( SYNOPSYS_UNCONNECTED_5388 ) , .pReset_S_in ( SYNOPSYS_UNCONNECTED_5389 ) , .pReset_E_in ( SYNOPSYS_UNCONNECTED_5390 ) , .pReset_W_in ( pResetWires[544] ) , .pReset_N_out ( pResetWires[546] ) , .pReset_W_out ( SYNOPSYS_UNCONNECTED_5391 ) , - .pReset_E_out ( pResetWires[547] ) , .Reset_S_in ( p3094 ) , + .pReset_E_out ( pResetWires[547] ) , .Reset_S_in ( p2266 ) , .Reset_N_out ( SYNOPSYS_UNCONNECTED_5392 ) , - .prog_clk_0_N_in ( prog_clk_0_wires[437] ) , .prog_clk_1_N_in ( p1586 ) , - .prog_clk_1_S_in ( p453 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[437] ) , .prog_clk_1_N_in ( p2258 ) , + .prog_clk_1_S_in ( p1204 ) , .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_5393 ) , .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_5394 ) , .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_5395 ) , @@ -141571,13 +145137,13 @@ sb_1__1_ sb_11__10_ ( .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_5399 ) , .prog_clk_2_N_out ( prog_clk_2_wires[134] ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5400 ) , - .prog_clk_3_W_in ( p1555 ) , .prog_clk_3_E_in ( p385 ) , - .prog_clk_3_S_in ( p172 ) , .prog_clk_3_N_in ( p878 ) , + .prog_clk_3_W_in ( p1957 ) , .prog_clk_3_E_in ( p51 ) , + .prog_clk_3_S_in ( p338 ) , .prog_clk_3_N_in ( p587 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5401 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5402 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_5403 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_5404 ) , .clk_1_N_in ( p1586 ) , - .clk_1_S_in ( p20 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_5405 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_5404 ) , .clk_1_N_in ( p2258 ) , + .clk_1_S_in ( p178 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_5405 ) , .clk_1_W_out ( SYNOPSYS_UNCONNECTED_5406 ) , .clk_2_N_in ( SYNOPSYS_UNCONNECTED_5407 ) , .clk_2_E_in ( SYNOPSYS_UNCONNECTED_5408 ) , @@ -141586,8 +145152,8 @@ sb_1__1_ sb_11__10_ ( .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5410 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_5411 ) , .clk_2_N_out ( clk_2_wires[134] ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5412 ) , .clk_3_W_in ( p1555 ) , - .clk_3_E_in ( p550 ) , .clk_3_S_in ( p3030 ) , .clk_3_N_in ( p336 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5412 ) , .clk_3_W_in ( p1957 ) , + .clk_3_E_in ( p514 ) , .clk_3_S_in ( p2120 ) , .clk_3_N_in ( p2070 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5413 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5414 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_5415 ) , @@ -141635,40 +145201,40 @@ sb_1__1_ sb_11__11_ ( .chanx_right_out ( sb_1__1__120_chanx_right_out ) , .chany_bottom_out ( sb_1__1__120_chany_bottom_out ) , .chanx_left_out ( sb_1__1__120_chanx_left_out ) , - .ccff_tail ( sb_1__1__120_ccff_tail ) , .Test_en_S_in ( p2803 ) , + .ccff_tail ( sb_1__1__120_ccff_tail ) , .Test_en_S_in ( p2224 ) , .Test_en_N_out ( SYNOPSYS_UNCONNECTED_5418 ) , .pReset_S_in ( SYNOPSYS_UNCONNECTED_5419 ) , .pReset_E_in ( SYNOPSYS_UNCONNECTED_5420 ) , .pReset_W_in ( pResetWires[593] ) , .pReset_N_out ( pResetWires[595] ) , .pReset_W_out ( SYNOPSYS_UNCONNECTED_5421 ) , - .pReset_E_out ( pResetWires[596] ) , .Reset_S_in ( p3054 ) , + .pReset_E_out ( pResetWires[596] ) , .Reset_S_in ( p2224 ) , .Reset_N_out ( SYNOPSYS_UNCONNECTED_5422 ) , .prog_clk_0_N_in ( prog_clk_0_wires[440] ) , .prog_clk_1_N_in ( SYNOPSYS_UNCONNECTED_5423 ) , .prog_clk_1_S_in ( prog_clk_2_wires[135] ) , .prog_clk_1_E_out ( prog_clk_1_wires[246] ) , - .prog_clk_1_W_out ( prog_clk_1_wires[247] ) , .prog_clk_2_N_in ( p3480 ) , - .prog_clk_2_E_in ( p68 ) , .prog_clk_2_S_in ( p363 ) , - .prog_clk_2_W_in ( p1050 ) , + .prog_clk_1_W_out ( prog_clk_1_wires[247] ) , .prog_clk_2_N_in ( p3164 ) , + .prog_clk_2_E_in ( p357 ) , .prog_clk_2_S_in ( p1036 ) , + .prog_clk_2_W_in ( p302 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5424 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_5425 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_5426 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5427 ) , - .prog_clk_3_W_in ( p2698 ) , .prog_clk_3_E_in ( p783 ) , - .prog_clk_3_S_in ( p1301 ) , .prog_clk_3_N_in ( p3472 ) , + .prog_clk_3_W_in ( p2981 ) , .prog_clk_3_E_in ( p265 ) , + .prog_clk_3_S_in ( p645 ) , .prog_clk_3_N_in ( p3062 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5428 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5429 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_5430 ) , .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_5431 ) , .clk_1_N_in ( SYNOPSYS_UNCONNECTED_5432 ) , .clk_1_S_in ( clk_2_wires[135] ) , .clk_1_E_out ( clk_1_wires[246] ) , - .clk_1_W_out ( clk_1_wires[247] ) , .clk_2_N_in ( p2964 ) , - .clk_2_E_in ( p1159 ) , .clk_2_S_in ( p3019 ) , .clk_2_W_in ( p2558 ) , + .clk_1_W_out ( clk_1_wires[247] ) , .clk_2_N_in ( p3002 ) , + .clk_2_E_in ( p1268 ) , .clk_2_S_in ( p1284 ) , .clk_2_W_in ( p3031 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5433 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_5434 ) , .clk_2_N_out ( SYNOPSYS_UNCONNECTED_5435 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5436 ) , .clk_3_W_in ( p2698 ) , - .clk_3_E_in ( p864 ) , .clk_3_S_in ( p690 ) , .clk_3_N_in ( p2911 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5436 ) , .clk_3_W_in ( p3120 ) , + .clk_3_E_in ( p522 ) , .clk_3_S_in ( p2058 ) , .clk_3_N_in ( p2865 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5437 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5438 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_5439 ) , @@ -141708,7 +145274,7 @@ sb_1__2_ sb_1__12_ ( .chanx_right_out ( sb_1__12__0_chanx_right_out ) , .chany_bottom_out ( sb_1__12__0_chany_bottom_out ) , .chanx_left_out ( sb_1__12__0_chanx_left_out ) , - .ccff_tail ( sb_1__12__0_ccff_tail ) , .SC_IN_BOT ( p1216 ) , + .ccff_tail ( sb_1__12__0_ccff_tail ) , .SC_IN_BOT ( p1338 ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_5442 ) , .pReset_S_in ( SYNOPSYS_UNCONNECTED_5443 ) , .pReset_E_in ( pResetWires[604] ) , @@ -141794,7 +145360,7 @@ sb_1__2_ sb_3__12_ ( .chanx_right_out ( sb_1__12__2_chanx_right_out ) , .chany_bottom_out ( sb_1__12__2_chany_bottom_out ) , .chanx_left_out ( sb_1__12__2_chanx_left_out ) , - .ccff_tail ( sb_1__12__2_ccff_tail ) , .SC_IN_BOT ( p1272 ) , + .ccff_tail ( sb_1__12__2_ccff_tail ) , .SC_IN_BOT ( p1257 ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_5451 ) , .pReset_S_in ( SYNOPSYS_UNCONNECTED_5452 ) , .pReset_E_in ( pResetWires[610] ) , @@ -141880,7 +145446,7 @@ sb_1__2_ sb_5__12_ ( .chanx_right_out ( sb_1__12__4_chanx_right_out ) , .chany_bottom_out ( sb_1__12__4_chany_bottom_out ) , .chanx_left_out ( sb_1__12__4_chanx_left_out ) , - .ccff_tail ( sb_1__12__4_ccff_tail ) , .SC_IN_BOT ( p1462 ) , + .ccff_tail ( sb_1__12__4_ccff_tail ) , .SC_IN_BOT ( p1412 ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_5460 ) , .pReset_S_in ( SYNOPSYS_UNCONNECTED_5461 ) , .pReset_E_in ( pResetWires[616] ) , @@ -141964,7 +145530,7 @@ sb_1__2_ sb_7__12_ ( .chanx_right_out ( sb_1__12__6_chanx_right_out ) , .chany_bottom_out ( sb_1__12__6_chany_bottom_out ) , .chanx_left_out ( sb_1__12__6_chanx_left_out ) , - .ccff_tail ( sb_1__12__6_ccff_tail ) , .SC_IN_BOT ( p1524 ) , + .ccff_tail ( sb_1__12__6_ccff_tail ) , .SC_IN_BOT ( p1384 ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_5468 ) , .pReset_S_in ( SYNOPSYS_UNCONNECTED_5469 ) , .pReset_E_in ( SYNOPSYS_UNCONNECTED_5470 ) , @@ -142050,7 +145616,7 @@ sb_1__2_ sb_9__12_ ( .chanx_right_out ( sb_1__12__8_chanx_right_out ) , .chany_bottom_out ( sb_1__12__8_chany_bottom_out ) , .chanx_left_out ( sb_1__12__8_chanx_left_out ) , - .ccff_tail ( sb_1__12__8_ccff_tail ) , .SC_IN_BOT ( p1396 ) , + .ccff_tail ( sb_1__12__8_ccff_tail ) , .SC_IN_BOT ( p1360 ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_5477 ) , .pReset_S_in ( SYNOPSYS_UNCONNECTED_5478 ) , .pReset_E_in ( SYNOPSYS_UNCONNECTED_5479 ) , @@ -142136,7 +145702,7 @@ sb_1__2_ sb_11__12_ ( .chanx_right_out ( sb_1__12__10_chanx_right_out ) , .chany_bottom_out ( sb_1__12__10_chany_bottom_out ) , .chanx_left_out ( sb_1__12__10_chanx_left_out ) , - .ccff_tail ( sb_1__12__10_ccff_tail ) , .SC_IN_BOT ( p1310 ) , + .ccff_tail ( sb_1__12__10_ccff_tail ) , .SC_IN_BOT ( p1480 ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_5486 ) , .pReset_S_in ( SYNOPSYS_UNCONNECTED_5487 ) , .pReset_E_in ( SYNOPSYS_UNCONNECTED_5488 ) , @@ -142666,7 +146232,7 @@ cbx_1__0_ cbx_1__0_ ( .top_width_0_height_0__pin_17_upper ( grid_io_bottom_11_top_width_0_height_0__pin_17_upper ) , .top_width_0_height_0__pin_17_lower ( grid_io_bottom_11_top_width_0_height_0__pin_17_lower ) , .SC_IN_TOP ( scff_Wires[25] ) , .SC_OUT_BOT ( scff_Wires[26] ) , - .SC_IN_BOT ( p1495 ) , .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_5504 ) , + .SC_IN_BOT ( p1011 ) , .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_5504 ) , .pReset_E_in ( pResetWires[26] ) , .pReset_W_in ( SYNOPSYS_UNCONNECTED_5505 ) , .pReset_W_out ( pResetWires[25] ) , @@ -142720,7 +146286,7 @@ cbx_1__0_ cbx_2__0_ ( .top_width_0_height_0__pin_15_lower ( grid_io_bottom_10_top_width_0_height_0__pin_15_lower ) , .top_width_0_height_0__pin_17_upper ( grid_io_bottom_10_top_width_0_height_0__pin_17_upper ) , .top_width_0_height_0__pin_17_lower ( grid_io_bottom_10_top_width_0_height_0__pin_17_lower ) , - .SC_IN_TOP ( p1229 ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_5508 ) , + .SC_IN_TOP ( p1608 ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_5508 ) , .SC_IN_BOT ( scff_Wires[27] ) , .SC_OUT_TOP ( scff_Wires[28] ) , .pReset_E_in ( pResetWires[29] ) , .pReset_W_in ( SYNOPSYS_UNCONNECTED_5509 ) , @@ -142777,7 +146343,7 @@ cbx_1__0_ cbx_3__0_ ( .top_width_0_height_0__pin_17_upper ( grid_io_bottom_9_top_width_0_height_0__pin_17_upper ) , .top_width_0_height_0__pin_17_lower ( grid_io_bottom_9_top_width_0_height_0__pin_17_lower ) , .SC_IN_TOP ( scff_Wires[78] ) , .SC_OUT_BOT ( scff_Wires[79] ) , - .SC_IN_BOT ( p1391 ) , .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_5513 ) , + .SC_IN_BOT ( p1622 ) , .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_5513 ) , .pReset_E_in ( pResetWires[32] ) , .pReset_W_in ( SYNOPSYS_UNCONNECTED_5514 ) , .pReset_W_out ( pResetWires[31] ) , @@ -142832,7 +146398,7 @@ cbx_1__0_ cbx_4__0_ ( .top_width_0_height_0__pin_15_lower ( grid_io_bottom_8_top_width_0_height_0__pin_15_lower ) , .top_width_0_height_0__pin_17_upper ( grid_io_bottom_8_top_width_0_height_0__pin_17_upper ) , .top_width_0_height_0__pin_17_lower ( grid_io_bottom_8_top_width_0_height_0__pin_17_lower ) , - .SC_IN_TOP ( p1395 ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_5518 ) , + .SC_IN_TOP ( p1309 ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_5518 ) , .SC_IN_BOT ( scff_Wires[80] ) , .SC_OUT_TOP ( scff_Wires[81] ) , .pReset_E_in ( pResetWires[35] ) , .pReset_W_in ( SYNOPSYS_UNCONNECTED_5519 ) , @@ -142889,7 +146455,7 @@ cbx_1__0_ cbx_5__0_ ( .top_width_0_height_0__pin_17_upper ( grid_io_bottom_7_top_width_0_height_0__pin_17_upper ) , .top_width_0_height_0__pin_17_lower ( grid_io_bottom_7_top_width_0_height_0__pin_17_lower ) , .SC_IN_TOP ( scff_Wires[131] ) , .SC_OUT_BOT ( scff_Wires[132] ) , - .SC_IN_BOT ( p1429 ) , .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_5523 ) , + .SC_IN_BOT ( p1555 ) , .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_5523 ) , .pReset_E_in ( pResetWires[38] ) , .pReset_W_in ( SYNOPSYS_UNCONNECTED_5524 ) , .pReset_W_out ( pResetWires[37] ) , @@ -142944,7 +146510,7 @@ cbx_1__0_ cbx_6__0_ ( .top_width_0_height_0__pin_15_lower ( grid_io_bottom_6_top_width_0_height_0__pin_15_lower ) , .top_width_0_height_0__pin_17_upper ( grid_io_bottom_6_top_width_0_height_0__pin_17_upper ) , .top_width_0_height_0__pin_17_lower ( grid_io_bottom_6_top_width_0_height_0__pin_17_lower ) , - .SC_IN_TOP ( p1330 ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_5528 ) , + .SC_IN_TOP ( p1246 ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_5528 ) , .SC_IN_BOT ( scff_Wires[133] ) , .SC_OUT_TOP ( scff_Wires[134] ) , .pReset_E_in ( pResetWires[41] ) , .pReset_W_in ( SYNOPSYS_UNCONNECTED_5529 ) , @@ -143001,7 +146567,7 @@ cbx_1__0_ cbx_7__0_ ( .top_width_0_height_0__pin_17_upper ( grid_io_bottom_5_top_width_0_height_0__pin_17_upper ) , .top_width_0_height_0__pin_17_lower ( grid_io_bottom_5_top_width_0_height_0__pin_17_lower ) , .SC_IN_TOP ( scff_Wires[184] ) , .SC_OUT_BOT ( scff_Wires[185] ) , - .SC_IN_BOT ( p1819 ) , .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_5533 ) , + .SC_IN_BOT ( p1228 ) , .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_5533 ) , .pReset_E_in ( SYNOPSYS_UNCONNECTED_5534 ) , .pReset_W_in ( pResetWires[43] ) , .pReset_W_out ( SYNOPSYS_UNCONNECTED_5535 ) , @@ -143056,7 +146622,7 @@ cbx_1__0_ cbx_8__0_ ( .top_width_0_height_0__pin_15_lower ( grid_io_bottom_4_top_width_0_height_0__pin_15_lower ) , .top_width_0_height_0__pin_17_upper ( grid_io_bottom_4_top_width_0_height_0__pin_17_upper ) , .top_width_0_height_0__pin_17_lower ( grid_io_bottom_4_top_width_0_height_0__pin_17_lower ) , - .SC_IN_TOP ( p1461 ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_5538 ) , + .SC_IN_TOP ( p1448 ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_5538 ) , .SC_IN_BOT ( scff_Wires[186] ) , .SC_OUT_TOP ( scff_Wires[187] ) , .pReset_E_in ( SYNOPSYS_UNCONNECTED_5539 ) , .pReset_W_in ( pResetWires[46] ) , @@ -143113,7 +146679,7 @@ cbx_1__0_ cbx_9__0_ ( .top_width_0_height_0__pin_17_upper ( grid_io_bottom_3_top_width_0_height_0__pin_17_upper ) , .top_width_0_height_0__pin_17_lower ( grid_io_bottom_3_top_width_0_height_0__pin_17_lower ) , .SC_IN_TOP ( scff_Wires[237] ) , .SC_OUT_BOT ( scff_Wires[238] ) , - .SC_IN_BOT ( p1316 ) , .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_5543 ) , + .SC_IN_BOT ( p1837 ) , .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_5543 ) , .pReset_E_in ( SYNOPSYS_UNCONNECTED_5544 ) , .pReset_W_in ( pResetWires[49] ) , .pReset_W_out ( SYNOPSYS_UNCONNECTED_5545 ) , @@ -143168,7 +146734,7 @@ cbx_1__0_ cbx_10__0_ ( .top_width_0_height_0__pin_15_lower ( grid_io_bottom_2_top_width_0_height_0__pin_15_lower ) , .top_width_0_height_0__pin_17_upper ( grid_io_bottom_2_top_width_0_height_0__pin_17_upper ) , .top_width_0_height_0__pin_17_lower ( grid_io_bottom_2_top_width_0_height_0__pin_17_lower ) , - .SC_IN_TOP ( p1181 ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_5548 ) , + .SC_IN_TOP ( p1221 ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_5548 ) , .SC_IN_BOT ( scff_Wires[239] ) , .SC_OUT_TOP ( scff_Wires[240] ) , .pReset_E_in ( SYNOPSYS_UNCONNECTED_5549 ) , .pReset_W_in ( pResetWires[52] ) , @@ -143225,7 +146791,7 @@ cbx_1__0_ cbx_11__0_ ( .top_width_0_height_0__pin_17_upper ( grid_io_bottom_1_top_width_0_height_0__pin_17_upper ) , .top_width_0_height_0__pin_17_lower ( grid_io_bottom_1_top_width_0_height_0__pin_17_lower ) , .SC_IN_TOP ( scff_Wires[290] ) , .SC_OUT_BOT ( scff_Wires[291] ) , - .SC_IN_BOT ( p1800 ) , .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_5553 ) , + .SC_IN_BOT ( p1290 ) , .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_5553 ) , .pReset_E_in ( SYNOPSYS_UNCONNECTED_5554 ) , .pReset_W_in ( pResetWires[55] ) , .pReset_W_out ( SYNOPSYS_UNCONNECTED_5555 ) , @@ -143280,7 +146846,7 @@ cbx_1__0_ cbx_12__0_ ( .top_width_0_height_0__pin_15_lower ( grid_io_bottom_0_top_width_0_height_0__pin_15_lower ) , .top_width_0_height_0__pin_17_upper ( grid_io_bottom_0_top_width_0_height_0__pin_17_upper ) , .top_width_0_height_0__pin_17_lower ( grid_io_bottom_0_top_width_0_height_0__pin_17_lower ) , - .SC_IN_TOP ( p1418 ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_5558 ) , + .SC_IN_TOP ( p1529 ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_5558 ) , .SC_IN_BOT ( scff_Wires[292] ) , .SC_OUT_TOP ( scff_Wires[293] ) , .pReset_E_in ( SYNOPSYS_UNCONNECTED_5559 ) , .pReset_W_in ( pResetWires[58] ) , @@ -143313,7 +146879,7 @@ cbx_1__1_ cbx_1__1_ ( .bottom_grid_pin_14_ ( cbx_1__1__0_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__0_bottom_grid_pin_15_ ) , .ccff_tail ( cbx_1__1__0_ccff_tail ) , .SC_IN_TOP ( scff_Wires[22] ) , - .SC_OUT_BOT ( scff_Wires[23] ) , .SC_IN_BOT ( p1388 ) , + .SC_OUT_BOT ( scff_Wires[23] ) , .SC_IN_BOT ( p1963 ) , .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_5563 ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[0] ) , .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[0] ) , @@ -143328,19 +146894,19 @@ cbx_1__1_ cbx_1__1_ ( .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_5566 ) , .prog_clk_1_E_in ( prog_clk_1_wires[2] ) , .prog_clk_1_N_out ( prog_clk_1_wires[3] ) , - .prog_clk_1_S_out ( prog_clk_1_wires[4] ) , .prog_clk_2_E_in ( p1411 ) , - .prog_clk_2_W_in ( p366 ) , + .prog_clk_1_S_out ( prog_clk_1_wires[4] ) , .prog_clk_2_E_in ( p3241 ) , + .prog_clk_2_W_in ( p1657 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5567 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5568 ) , - .prog_clk_3_W_in ( p2715 ) , .prog_clk_3_E_in ( p1415 ) , + .prog_clk_3_W_in ( p1870 ) , .prog_clk_3_E_in ( p3179 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5569 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5570 ) , .clk_1_W_in ( SYNOPSYS_UNCONNECTED_5571 ) , .clk_1_E_in ( clk_1_wires[2] ) , .clk_1_N_out ( clk_1_wires[3] ) , - .clk_1_S_out ( clk_1_wires[4] ) , .clk_2_E_in ( p1411 ) , - .clk_2_W_in ( p2580 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5572 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5573 ) , .clk_3_W_in ( p2094 ) , - .clk_3_E_in ( p90 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5574 ) , + .clk_1_S_out ( clk_1_wires[4] ) , .clk_2_E_in ( p2243 ) , + .clk_2_W_in ( p2119 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5572 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5573 ) , .clk_3_W_in ( p2246 ) , + .clk_3_E_in ( p2171 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5574 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5575 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; cbx_1__1_ cbx_1__2_ ( .pReset ( { SYNOPSYS_UNCONNECTED_5576 } ) , @@ -143366,7 +146932,7 @@ cbx_1__1_ cbx_1__2_ ( .bottom_grid_pin_14_ ( cbx_1__1__1_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__1_bottom_grid_pin_15_ ) , .ccff_tail ( cbx_1__1__1_ccff_tail ) , .SC_IN_TOP ( scff_Wires[20] ) , - .SC_OUT_BOT ( scff_Wires[21] ) , .SC_IN_BOT ( p2247 ) , + .SC_OUT_BOT ( scff_Wires[21] ) , .SC_IN_BOT ( p2637 ) , .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_5577 ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[1] ) , .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[1] ) , @@ -143377,21 +146943,21 @@ cbx_1__1_ cbx_1__2_ ( .pReset_W_out ( pResetWires[110] ) , .pReset_S_out ( pResetWires[112] ) , .pReset_E_out ( SYNOPSYS_UNCONNECTED_5579 ) , .prog_clk_0_N_in ( prog_clk_0_wires[11] ) , - .prog_clk_0_W_out ( prog_clk_0_wires[10] ) , .prog_clk_1_W_in ( p2842 ) , - .prog_clk_1_E_in ( p2005 ) , + .prog_clk_0_W_out ( prog_clk_0_wires[10] ) , .prog_clk_1_W_in ( p1561 ) , + .prog_clk_1_E_in ( p2379 ) , .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_5580 ) , .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_5581 ) , - .prog_clk_2_E_in ( p2684 ) , .prog_clk_2_W_in ( p2760 ) , + .prog_clk_2_E_in ( p2625 ) , .prog_clk_2_W_in ( p3382 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5582 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5583 ) , - .prog_clk_3_W_in ( p2685 ) , .prog_clk_3_E_in ( p518 ) , + .prog_clk_3_W_in ( p3405 ) , .prog_clk_3_E_in ( p2471 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5584 ) , - .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5585 ) , .clk_1_W_in ( p1466 ) , - .clk_1_E_in ( p2076 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_5586 ) , - .clk_1_S_out ( SYNOPSYS_UNCONNECTED_5587 ) , .clk_2_E_in ( p2684 ) , - .clk_2_W_in ( p2560 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5588 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5589 ) , .clk_3_W_in ( p1783 ) , - .clk_3_E_in ( p2579 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5590 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5585 ) , .clk_1_W_in ( p2591 ) , + .clk_1_E_in ( p574 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_5586 ) , + .clk_1_S_out ( SYNOPSYS_UNCONNECTED_5587 ) , .clk_2_E_in ( p2965 ) , + .clk_2_W_in ( p3198 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5588 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5589 ) , .clk_3_W_in ( p3259 ) , + .clk_3_E_in ( p2859 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5590 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5591 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; cbx_1__1_ cbx_1__3_ ( .pReset ( { SYNOPSYS_UNCONNECTED_5592 } ) , @@ -143417,7 +146983,7 @@ cbx_1__1_ cbx_1__3_ ( .bottom_grid_pin_14_ ( cbx_1__1__2_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__2_bottom_grid_pin_15_ ) , .ccff_tail ( cbx_1__1__2_ccff_tail ) , .SC_IN_TOP ( scff_Wires[18] ) , - .SC_OUT_BOT ( scff_Wires[19] ) , .SC_IN_BOT ( p1530 ) , + .SC_OUT_BOT ( scff_Wires[19] ) , .SC_IN_BOT ( p1368 ) , .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_5593 ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[2] ) , .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[2] ) , @@ -143432,19 +146998,19 @@ cbx_1__1_ cbx_1__3_ ( .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_5596 ) , .prog_clk_1_E_in ( prog_clk_1_wires[9] ) , .prog_clk_1_N_out ( prog_clk_1_wires[10] ) , - .prog_clk_1_S_out ( prog_clk_1_wires[11] ) , .prog_clk_2_E_in ( p2808 ) , - .prog_clk_2_W_in ( p1236 ) , + .prog_clk_1_S_out ( prog_clk_1_wires[11] ) , .prog_clk_2_E_in ( p3541 ) , + .prog_clk_2_W_in ( p2141 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5597 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5598 ) , - .prog_clk_3_W_in ( p3165 ) , .prog_clk_3_E_in ( p1369 ) , + .prog_clk_3_W_in ( p2324 ) , .prog_clk_3_E_in ( p3518 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5599 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5600 ) , .clk_1_W_in ( SYNOPSYS_UNCONNECTED_5601 ) , .clk_1_E_in ( clk_1_wires[9] ) , .clk_1_N_out ( clk_1_wires[10] ) , - .clk_1_S_out ( clk_1_wires[11] ) , .clk_2_E_in ( p2808 ) , - .clk_2_W_in ( p3145 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5602 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5603 ) , .clk_3_W_in ( p1785 ) , - .clk_3_E_in ( p2753 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5604 ) , + .clk_1_S_out ( clk_1_wires[11] ) , .clk_2_E_in ( p2216 ) , + .clk_2_W_in ( p2921 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5602 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5603 ) , .clk_3_W_in ( p2982 ) , + .clk_3_E_in ( p2057 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5604 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5605 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; cbx_1__1_ cbx_1__4_ ( .pReset ( { SYNOPSYS_UNCONNECTED_5606 } ) , @@ -143470,7 +147036,7 @@ cbx_1__1_ cbx_1__4_ ( .bottom_grid_pin_14_ ( cbx_1__1__3_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__3_bottom_grid_pin_15_ ) , .ccff_tail ( cbx_1__1__3_ccff_tail ) , .SC_IN_TOP ( scff_Wires[16] ) , - .SC_OUT_BOT ( scff_Wires[17] ) , .SC_IN_BOT ( p1944 ) , + .SC_OUT_BOT ( scff_Wires[17] ) , .SC_IN_BOT ( p1439 ) , .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_5607 ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[3] ) , .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[3] ) , @@ -143481,21 +147047,21 @@ cbx_1__1_ cbx_1__4_ ( .pReset_W_out ( pResetWires[208] ) , .pReset_S_out ( pResetWires[210] ) , .pReset_E_out ( SYNOPSYS_UNCONNECTED_5609 ) , .prog_clk_0_N_in ( prog_clk_0_wires[21] ) , - .prog_clk_0_W_out ( prog_clk_0_wires[20] ) , .prog_clk_1_W_in ( p2825 ) , - .prog_clk_1_E_in ( p1997 ) , + .prog_clk_0_W_out ( prog_clk_0_wires[20] ) , .prog_clk_1_W_in ( p1597 ) , + .prog_clk_1_E_in ( p190 ) , .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_5610 ) , .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_5611 ) , - .prog_clk_2_E_in ( p2115 ) , .prog_clk_2_W_in ( p2773 ) , + .prog_clk_2_E_in ( p2585 ) , .prog_clk_2_W_in ( p3101 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5612 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5613 ) , - .prog_clk_3_W_in ( p3190 ) , .prog_clk_3_E_in ( p1040 ) , + .prog_clk_3_W_in ( p3051 ) , .prog_clk_3_E_in ( p2416 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5614 ) , - .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5615 ) , .clk_1_W_in ( p1322 ) , - .clk_1_E_in ( p1732 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_5616 ) , - .clk_1_S_out ( SYNOPSYS_UNCONNECTED_5617 ) , .clk_2_E_in ( p2115 ) , - .clk_2_W_in ( p3137 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5618 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5619 ) , .clk_3_W_in ( p2471 ) , - .clk_3_E_in ( p2077 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5620 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5615 ) , .clk_1_W_in ( p1941 ) , + .clk_1_E_in ( p1818 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_5616 ) , + .clk_1_S_out ( SYNOPSYS_UNCONNECTED_5617 ) , .clk_2_E_in ( p3234 ) , + .clk_2_W_in ( p3367 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5618 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5619 ) , .clk_3_W_in ( p3404 ) , + .clk_3_E_in ( p3219 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5620 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5621 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; cbx_1__1_ cbx_1__5_ ( .pReset ( { SYNOPSYS_UNCONNECTED_5622 } ) , @@ -143521,7 +147087,7 @@ cbx_1__1_ cbx_1__5_ ( .bottom_grid_pin_14_ ( cbx_1__1__4_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__4_bottom_grid_pin_15_ ) , .ccff_tail ( cbx_1__1__4_ccff_tail ) , .SC_IN_TOP ( scff_Wires[14] ) , - .SC_OUT_BOT ( scff_Wires[15] ) , .SC_IN_BOT ( p1912 ) , + .SC_OUT_BOT ( scff_Wires[15] ) , .SC_IN_BOT ( p1234 ) , .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_5623 ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[4] ) , .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[4] ) , @@ -143536,19 +147102,19 @@ cbx_1__1_ cbx_1__5_ ( .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_5626 ) , .prog_clk_1_E_in ( prog_clk_1_wires[16] ) , .prog_clk_1_N_out ( prog_clk_1_wires[17] ) , - .prog_clk_1_S_out ( prog_clk_1_wires[18] ) , .prog_clk_2_E_in ( p2488 ) , - .prog_clk_2_W_in ( p184 ) , + .prog_clk_1_S_out ( prog_clk_1_wires[18] ) , .prog_clk_2_E_in ( p2850 ) , + .prog_clk_2_W_in ( p1799 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5627 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5628 ) , - .prog_clk_3_W_in ( p1938 ) , .prog_clk_3_E_in ( p1311 ) , + .prog_clk_3_W_in ( p1981 ) , .prog_clk_3_E_in ( p2645 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5629 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5630 ) , .clk_1_W_in ( SYNOPSYS_UNCONNECTED_5631 ) , .clk_1_E_in ( clk_1_wires[16] ) , .clk_1_N_out ( clk_1_wires[17] ) , - .clk_1_S_out ( clk_1_wires[18] ) , .clk_2_E_in ( p2488 ) , - .clk_2_W_in ( p2356 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5632 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5633 ) , .clk_3_W_in ( p2461 ) , - .clk_3_E_in ( p2335 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5634 ) , + .clk_1_S_out ( clk_1_wires[18] ) , .clk_2_E_in ( p1815 ) , + .clk_2_W_in ( p3077 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5632 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5633 ) , .clk_3_W_in ( p3155 ) , + .clk_3_E_in ( p1825 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5634 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5635 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; cbx_1__1_ cbx_1__6_ ( .pReset ( { SYNOPSYS_UNCONNECTED_5636 } ) , @@ -143574,7 +147140,7 @@ cbx_1__1_ cbx_1__6_ ( .bottom_grid_pin_14_ ( cbx_1__1__5_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__5_bottom_grid_pin_15_ ) , .ccff_tail ( cbx_1__1__5_ccff_tail ) , .SC_IN_TOP ( scff_Wires[12] ) , - .SC_OUT_BOT ( scff_Wires[13] ) , .SC_IN_BOT ( p1802 ) , + .SC_OUT_BOT ( scff_Wires[13] ) , .SC_IN_BOT ( p1196 ) , .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_5637 ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[5] ) , .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[5] ) , @@ -143585,21 +147151,21 @@ cbx_1__1_ cbx_1__6_ ( .pReset_W_out ( pResetWires[306] ) , .pReset_S_out ( pResetWires[308] ) , .pReset_E_out ( SYNOPSYS_UNCONNECTED_5639 ) , .prog_clk_0_N_in ( prog_clk_0_wires[31] ) , - .prog_clk_0_W_out ( prog_clk_0_wires[30] ) , .prog_clk_1_W_in ( p2189 ) , - .prog_clk_1_E_in ( p879 ) , + .prog_clk_0_W_out ( prog_clk_0_wires[30] ) , .prog_clk_1_W_in ( p1864 ) , + .prog_clk_1_E_in ( p727 ) , .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_5640 ) , .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_5641 ) , - .prog_clk_2_E_in ( p1568 ) , .prog_clk_2_W_in ( p2090 ) , + .prog_clk_2_E_in ( p3114 ) , .prog_clk_2_W_in ( p2861 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5642 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5643 ) , - .prog_clk_3_W_in ( p2146 ) , .prog_clk_3_E_in ( p414 ) , + .prog_clk_3_W_in ( p2998 ) , .prog_clk_3_E_in ( p3097 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5644 ) , - .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5645 ) , .clk_1_W_in ( p1353 ) , - .clk_1_E_in ( p1690 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_5646 ) , - .clk_1_S_out ( SYNOPSYS_UNCONNECTED_5647 ) , .clk_2_E_in ( p1568 ) , - .clk_2_W_in ( p2277 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5648 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5649 ) , .clk_3_W_in ( p2386 ) , - .clk_3_E_in ( p1255 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5650 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5645 ) , .clk_1_W_in ( p2561 ) , + .clk_1_E_in ( p662 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_5646 ) , + .clk_1_S_out ( SYNOPSYS_UNCONNECTED_5647 ) , .clk_2_E_in ( p3162 ) , + .clk_2_W_in ( p3385 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5648 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5649 ) , .clk_3_W_in ( p3418 ) , + .clk_3_E_in ( p3081 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5650 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5651 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; cbx_1__1_ cbx_1__7_ ( .pReset ( { SYNOPSYS_UNCONNECTED_5652 } ) , @@ -143625,7 +147191,7 @@ cbx_1__1_ cbx_1__7_ ( .bottom_grid_pin_14_ ( cbx_1__1__6_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__6_bottom_grid_pin_15_ ) , .ccff_tail ( cbx_1__1__6_ccff_tail ) , .SC_IN_TOP ( scff_Wires[10] ) , - .SC_OUT_BOT ( scff_Wires[11] ) , .SC_IN_BOT ( p1313 ) , + .SC_OUT_BOT ( scff_Wires[11] ) , .SC_IN_BOT ( p1475 ) , .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_5653 ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[6] ) , .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[6] ) , @@ -143640,19 +147206,19 @@ cbx_1__1_ cbx_1__7_ ( .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_5656 ) , .prog_clk_1_E_in ( prog_clk_1_wires[23] ) , .prog_clk_1_N_out ( prog_clk_1_wires[24] ) , - .prog_clk_1_S_out ( prog_clk_1_wires[25] ) , .prog_clk_2_E_in ( p2932 ) , - .prog_clk_2_W_in ( p320 ) , + .prog_clk_1_S_out ( prog_clk_1_wires[25] ) , .prog_clk_2_E_in ( p2813 ) , + .prog_clk_2_W_in ( p3383 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5657 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5658 ) , - .prog_clk_3_W_in ( p2392 ) , .prog_clk_3_E_in ( p573 ) , + .prog_clk_3_W_in ( p3409 ) , .prog_clk_3_E_in ( p2724 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5659 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5660 ) , .clk_1_W_in ( SYNOPSYS_UNCONNECTED_5661 ) , .clk_1_E_in ( clk_1_wires[23] ) , .clk_1_N_out ( clk_1_wires[24] ) , - .clk_1_S_out ( clk_1_wires[25] ) , .clk_2_E_in ( p2932 ) , - .clk_2_W_in ( p2357 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5662 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5663 ) , .clk_3_W_in ( p2492 ) , - .clk_3_E_in ( p2915 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5664 ) , + .clk_1_S_out ( clk_1_wires[25] ) , .clk_2_E_in ( p2939 ) , + .clk_2_W_in ( p3316 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5662 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5663 ) , .clk_3_W_in ( p3353 ) , + .clk_3_E_in ( p2928 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5664 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5665 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; cbx_1__1_ cbx_1__8_ ( .pReset ( { SYNOPSYS_UNCONNECTED_5666 } ) , @@ -143678,7 +147244,7 @@ cbx_1__1_ cbx_1__8_ ( .bottom_grid_pin_14_ ( cbx_1__1__7_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__7_bottom_grid_pin_15_ ) , .ccff_tail ( cbx_1__1__7_ccff_tail ) , .SC_IN_TOP ( scff_Wires[8] ) , - .SC_OUT_BOT ( scff_Wires[9] ) , .SC_IN_BOT ( p1909 ) , + .SC_OUT_BOT ( scff_Wires[9] ) , .SC_IN_BOT ( p1627 ) , .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_5667 ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[7] ) , .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[7] ) , @@ -143689,21 +147255,21 @@ cbx_1__1_ cbx_1__8_ ( .pReset_W_out ( pResetWires[404] ) , .pReset_S_out ( pResetWires[406] ) , .pReset_E_out ( SYNOPSYS_UNCONNECTED_5669 ) , .prog_clk_0_N_in ( prog_clk_0_wires[41] ) , - .prog_clk_0_W_out ( prog_clk_0_wires[40] ) , .prog_clk_1_W_in ( p1419 ) , - .prog_clk_1_E_in ( p421 ) , + .prog_clk_0_W_out ( prog_clk_0_wires[40] ) , .prog_clk_1_W_in ( p1596 ) , + .prog_clk_1_E_in ( p575 ) , .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_5670 ) , .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_5671 ) , - .prog_clk_2_E_in ( p2439 ) , .prog_clk_2_W_in ( p920 ) , + .prog_clk_2_E_in ( p3252 ) , .prog_clk_2_W_in ( p3193 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5672 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5673 ) , - .prog_clk_3_W_in ( p3109 ) , .prog_clk_3_E_in ( p626 ) , + .prog_clk_3_W_in ( p3222 ) , .prog_clk_3_E_in ( p3178 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5674 ) , - .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5675 ) , .clk_1_W_in ( p1289 ) , - .clk_1_E_in ( p1685 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_5676 ) , - .clk_1_S_out ( SYNOPSYS_UNCONNECTED_5677 ) , .clk_2_E_in ( p2439 ) , - .clk_2_W_in ( p3033 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5678 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5679 ) , .clk_3_W_in ( p1469 ) , - .clk_3_E_in ( p2343 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5680 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5675 ) , .clk_1_W_in ( p2020 ) , + .clk_1_E_in ( p1058 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_5676 ) , + .clk_1_S_out ( SYNOPSYS_UNCONNECTED_5677 ) , .clk_2_E_in ( p1132 ) , + .clk_2_W_in ( p3450 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5678 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5679 ) , .clk_3_W_in ( p3470 ) , + .clk_3_E_in ( p1267 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5680 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5681 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; cbx_1__1_ cbx_1__9_ ( .pReset ( { SYNOPSYS_UNCONNECTED_5682 } ) , @@ -143729,7 +147295,7 @@ cbx_1__1_ cbx_1__9_ ( .bottom_grid_pin_14_ ( cbx_1__1__8_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__8_bottom_grid_pin_15_ ) , .ccff_tail ( cbx_1__1__8_ccff_tail ) , .SC_IN_TOP ( scff_Wires[6] ) , - .SC_OUT_BOT ( scff_Wires[7] ) , .SC_IN_BOT ( p1511 ) , + .SC_OUT_BOT ( scff_Wires[7] ) , .SC_IN_BOT ( p1417 ) , .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_5683 ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[8] ) , .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[8] ) , @@ -143744,19 +147310,19 @@ cbx_1__1_ cbx_1__9_ ( .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_5686 ) , .prog_clk_1_E_in ( prog_clk_1_wires[30] ) , .prog_clk_1_N_out ( prog_clk_1_wires[31] ) , - .prog_clk_1_S_out ( prog_clk_1_wires[32] ) , .prog_clk_2_E_in ( p2118 ) , - .prog_clk_2_W_in ( p567 ) , + .prog_clk_1_S_out ( prog_clk_1_wires[32] ) , .prog_clk_2_E_in ( p2966 ) , + .prog_clk_2_W_in ( p3284 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5687 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5688 ) , - .prog_clk_3_W_in ( p2441 ) , .prog_clk_3_E_in ( p1392 ) , + .prog_clk_3_W_in ( p3337 ) , .prog_clk_3_E_in ( p2930 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5689 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5690 ) , .clk_1_W_in ( SYNOPSYS_UNCONNECTED_5691 ) , .clk_1_E_in ( clk_1_wires[30] ) , .clk_1_N_out ( clk_1_wires[31] ) , - .clk_1_S_out ( clk_1_wires[32] ) , .clk_2_E_in ( p2118 ) , - .clk_2_W_in ( p3140 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5692 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5693 ) , .clk_3_W_in ( p3187 ) , - .clk_3_E_in ( p2069 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5694 ) , + .clk_1_S_out ( clk_1_wires[32] ) , .clk_2_E_in ( p1469 ) , + .clk_2_W_in ( p2914 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5692 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5693 ) , .clk_3_W_in ( p2948 ) , + .clk_3_E_in ( p161 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5694 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5695 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; cbx_1__1_ cbx_1__10_ ( .pReset ( { SYNOPSYS_UNCONNECTED_5696 } ) , @@ -143782,7 +147348,7 @@ cbx_1__1_ cbx_1__10_ ( .bottom_grid_pin_14_ ( cbx_1__1__9_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__9_bottom_grid_pin_15_ ) , .ccff_tail ( cbx_1__1__9_ccff_tail ) , .SC_IN_TOP ( scff_Wires[4] ) , - .SC_OUT_BOT ( scff_Wires[5] ) , .SC_IN_BOT ( p1803 ) , + .SC_OUT_BOT ( scff_Wires[5] ) , .SC_IN_BOT ( p1518 ) , .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_5697 ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[9] ) , .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[9] ) , @@ -143793,21 +147359,21 @@ cbx_1__1_ cbx_1__10_ ( .pReset_W_out ( pResetWires[502] ) , .pReset_S_out ( pResetWires[504] ) , .pReset_E_out ( SYNOPSYS_UNCONNECTED_5699 ) , .prog_clk_0_N_in ( prog_clk_0_wires[51] ) , - .prog_clk_0_W_out ( prog_clk_0_wires[50] ) , .prog_clk_1_W_in ( p2157 ) , - .prog_clk_1_E_in ( p1085 ) , + .prog_clk_0_W_out ( prog_clk_0_wires[50] ) , .prog_clk_1_W_in ( p1315 ) , + .prog_clk_1_E_in ( p789 ) , .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_5700 ) , .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_5701 ) , - .prog_clk_2_E_in ( p1575 ) , .prog_clk_2_W_in ( p2106 ) , + .prog_clk_2_E_in ( p2798 ) , .prog_clk_2_W_in ( p2729 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5702 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5703 ) , - .prog_clk_3_W_in ( p2933 ) , .prog_clk_3_E_in ( p612 ) , + .prog_clk_3_W_in ( p2797 ) , .prog_clk_3_E_in ( p2739 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5704 ) , - .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5705 ) , .clk_1_W_in ( p1496 ) , - .clk_1_E_in ( p1719 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_5706 ) , - .clk_1_S_out ( SYNOPSYS_UNCONNECTED_5707 ) , .clk_2_E_in ( p1575 ) , - .clk_2_W_in ( p2905 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5708 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5709 ) , .clk_3_W_in ( p2502 ) , - .clk_3_E_in ( p1397 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5710 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5705 ) , .clk_1_W_in ( p1821 ) , + .clk_1_E_in ( p2178 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_5706 ) , + .clk_1_S_out ( SYNOPSYS_UNCONNECTED_5707 ) , .clk_2_E_in ( p2742 ) , + .clk_2_W_in ( p3209 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5708 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5709 ) , .clk_3_W_in ( p3254 ) , + .clk_3_E_in ( p2663 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5710 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5711 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; cbx_1__1_ cbx_1__11_ ( .pReset ( { SYNOPSYS_UNCONNECTED_5712 } ) , @@ -143833,7 +147399,7 @@ cbx_1__1_ cbx_1__11_ ( .bottom_grid_pin_14_ ( cbx_1__1__10_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__10_bottom_grid_pin_15_ ) , .ccff_tail ( cbx_1__1__10_ccff_tail ) , .SC_IN_TOP ( scff_Wires[2] ) , - .SC_OUT_BOT ( scff_Wires[3] ) , .SC_IN_BOT ( p1552 ) , + .SC_OUT_BOT ( scff_Wires[3] ) , .SC_IN_BOT ( p1646 ) , .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_5713 ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[10] ) , .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[10] ) , @@ -143848,19 +147414,19 @@ cbx_1__1_ cbx_1__11_ ( .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_5716 ) , .prog_clk_1_E_in ( prog_clk_1_wires[37] ) , .prog_clk_1_N_out ( prog_clk_1_wires[38] ) , - .prog_clk_1_S_out ( prog_clk_1_wires[39] ) , .prog_clk_2_E_in ( p2266 ) , - .prog_clk_2_W_in ( p132 ) , + .prog_clk_1_S_out ( prog_clk_1_wires[39] ) , .prog_clk_2_E_in ( p2999 ) , + .prog_clk_2_W_in ( p2683 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5717 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5718 ) , - .prog_clk_3_W_in ( p2478 ) , .prog_clk_3_E_in ( p1209 ) , + .prog_clk_3_W_in ( p2828 ) , .prog_clk_3_E_in ( p2910 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5719 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5720 ) , .clk_1_W_in ( SYNOPSYS_UNCONNECTED_5721 ) , .clk_1_E_in ( clk_1_wires[37] ) , .clk_1_N_out ( clk_1_wires[38] ) , - .clk_1_S_out ( clk_1_wires[39] ) , .clk_2_E_in ( p2266 ) , - .clk_2_W_in ( p2749 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5722 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5723 ) , .clk_3_W_in ( p2838 ) , - .clk_3_E_in ( p2082 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5724 ) , + .clk_1_S_out ( clk_1_wires[39] ) , .clk_2_E_in ( p2200 ) , + .clk_2_W_in ( p2398 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5722 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5723 ) , .clk_3_W_in ( p2634 ) , + .clk_3_E_in ( p2164 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5724 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5725 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; cbx_1__1_ cbx_2__1_ ( .pReset ( { SYNOPSYS_UNCONNECTED_5726 } ) , @@ -143885,7 +147451,7 @@ cbx_1__1_ cbx_2__1_ ( .bottom_grid_pin_13_ ( cbx_1__1__11_bottom_grid_pin_13_ ) , .bottom_grid_pin_14_ ( cbx_1__1__11_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__11_bottom_grid_pin_15_ ) , - .ccff_tail ( cbx_1__1__11_ccff_tail ) , .SC_IN_TOP ( p1910 ) , + .ccff_tail ( cbx_1__1__11_ccff_tail ) , .SC_IN_TOP ( p2048 ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_5727 ) , .SC_IN_BOT ( scff_Wires[29] ) , .SC_OUT_TOP ( scff_Wires[30] ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[11] ) , @@ -143901,20 +147467,20 @@ cbx_1__1_ cbx_2__1_ ( .prog_clk_1_W_in ( prog_clk_1_wires[1] ) , .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_5731 ) , .prog_clk_1_N_out ( prog_clk_1_wires[5] ) , - .prog_clk_1_S_out ( prog_clk_1_wires[6] ) , .prog_clk_2_E_in ( p2473 ) , - .prog_clk_2_W_in ( p874 ) , + .prog_clk_1_S_out ( prog_clk_1_wires[6] ) , .prog_clk_2_E_in ( p2852 ) , + .prog_clk_2_W_in ( p3210 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5732 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5733 ) , - .prog_clk_3_W_in ( p3242 ) , .prog_clk_3_E_in ( p1767 ) , + .prog_clk_3_W_in ( p3275 ) , .prog_clk_3_E_in ( p2727 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5734 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5735 ) , .clk_1_W_in ( clk_1_wires[1] ) , .clk_1_E_in ( SYNOPSYS_UNCONNECTED_5736 ) , .clk_1_N_out ( clk_1_wires[5] ) , .clk_1_S_out ( clk_1_wires[6] ) , - .clk_2_E_in ( p2473 ) , .clk_2_W_in ( p3232 ) , + .clk_2_E_in ( p1577 ) , .clk_2_W_in ( p2932 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5737 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5738 ) , .clk_3_W_in ( p2403 ) , - .clk_3_E_in ( p2324 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5739 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5738 ) , .clk_3_W_in ( p3007 ) , + .clk_3_E_in ( p874 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5739 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5740 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; cbx_1__1_ cbx_2__2_ ( .pReset ( { SYNOPSYS_UNCONNECTED_5741 } ) , @@ -143939,7 +147505,7 @@ cbx_1__1_ cbx_2__2_ ( .bottom_grid_pin_13_ ( cbx_1__1__12_bottom_grid_pin_13_ ) , .bottom_grid_pin_14_ ( cbx_1__1__12_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__12_bottom_grid_pin_15_ ) , - .ccff_tail ( cbx_1__1__12_ccff_tail ) , .SC_IN_TOP ( p2224 ) , + .ccff_tail ( cbx_1__1__12_ccff_tail ) , .SC_IN_TOP ( p2339 ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_5742 ) , .SC_IN_BOT ( scff_Wires[31] ) , .SC_OUT_TOP ( scff_Wires[32] ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[12] ) , @@ -143952,23 +147518,23 @@ cbx_1__1_ cbx_2__2_ ( .pReset_E_out ( SYNOPSYS_UNCONNECTED_5744 ) , .prog_clk_0_N_in ( prog_clk_0_wires[69] ) , .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_5745 ) , - .prog_clk_1_W_in ( p1288 ) , .prog_clk_1_E_in ( p1623 ) , + .prog_clk_1_W_in ( p1331 ) , .prog_clk_1_E_in ( p633 ) , .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_5746 ) , .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_5747 ) , .prog_clk_2_E_in ( prog_clk_2_wires[2] ) , .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_5748 ) , .prog_clk_2_W_out ( prog_clk_2_wires[1] ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5749 ) , - .prog_clk_3_W_in ( p1288 ) , .prog_clk_3_E_in ( p2045 ) , + .prog_clk_3_W_in ( p1887 ) , .prog_clk_3_E_in ( p2142 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5750 ) , - .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5751 ) , .clk_1_W_in ( p1605 ) , - .clk_1_E_in ( p148 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_5752 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5751 ) , .clk_1_W_in ( p1887 ) , + .clk_1_E_in ( p1736 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_5752 ) , .clk_1_S_out ( SYNOPSYS_UNCONNECTED_5753 ) , .clk_2_E_in ( clk_2_wires[2] ) , .clk_2_W_in ( SYNOPSYS_UNCONNECTED_5754 ) , .clk_2_W_out ( clk_2_wires[1] ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5755 ) , .clk_3_W_in ( p1288 ) , - .clk_3_E_in ( p1751 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5756 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5755 ) , .clk_3_W_in ( p1887 ) , + .clk_3_E_in ( p1817 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5756 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5757 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; cbx_1__1_ cbx_2__3_ ( .pReset ( { SYNOPSYS_UNCONNECTED_5758 } ) , @@ -143993,7 +147559,7 @@ cbx_1__1_ cbx_2__3_ ( .bottom_grid_pin_13_ ( cbx_1__1__13_bottom_grid_pin_13_ ) , .bottom_grid_pin_14_ ( cbx_1__1__13_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__13_bottom_grid_pin_15_ ) , - .ccff_tail ( cbx_1__1__13_ccff_tail ) , .SC_IN_TOP ( p1475 ) , + .ccff_tail ( cbx_1__1__13_ccff_tail ) , .SC_IN_TOP ( p1881 ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_5759 ) , .SC_IN_BOT ( scff_Wires[33] ) , .SC_OUT_TOP ( scff_Wires[34] ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[13] ) , @@ -144009,20 +147575,20 @@ cbx_1__1_ cbx_2__3_ ( .prog_clk_1_W_in ( prog_clk_1_wires[8] ) , .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_5763 ) , .prog_clk_1_N_out ( prog_clk_1_wires[12] ) , - .prog_clk_1_S_out ( prog_clk_1_wires[13] ) , .prog_clk_2_E_in ( p2455 ) , - .prog_clk_2_W_in ( p814 ) , + .prog_clk_1_S_out ( prog_clk_1_wires[13] ) , .prog_clk_2_E_in ( p3250 ) , + .prog_clk_2_W_in ( p3365 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5764 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5765 ) , - .prog_clk_3_W_in ( p2841 ) , .prog_clk_3_E_in ( p542 ) , + .prog_clk_3_W_in ( p3400 ) , .prog_clk_3_E_in ( p3201 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5766 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5767 ) , .clk_1_W_in ( clk_1_wires[8] ) , .clk_1_E_in ( SYNOPSYS_UNCONNECTED_5768 ) , .clk_1_N_out ( clk_1_wires[12] ) , .clk_1_S_out ( clk_1_wires[13] ) , - .clk_2_E_in ( p2455 ) , .clk_2_W_in ( p2762 ) , + .clk_2_E_in ( p2352 ) , .clk_2_W_in ( p2936 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5769 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5770 ) , .clk_3_W_in ( p2176 ) , - .clk_3_E_in ( p2344 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5771 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5770 ) , .clk_3_W_in ( p2968 ) , + .clk_3_E_in ( p2185 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5771 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5772 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; cbx_1__1_ cbx_2__4_ ( .pReset ( { SYNOPSYS_UNCONNECTED_5773 } ) , @@ -144047,7 +147613,7 @@ cbx_1__1_ cbx_2__4_ ( .bottom_grid_pin_13_ ( cbx_1__1__14_bottom_grid_pin_13_ ) , .bottom_grid_pin_14_ ( cbx_1__1__14_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__14_bottom_grid_pin_15_ ) , - .ccff_tail ( cbx_1__1__14_ccff_tail ) , .SC_IN_TOP ( p1452 ) , + .ccff_tail ( cbx_1__1__14_ccff_tail ) , .SC_IN_TOP ( p1551 ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_5774 ) , .SC_IN_BOT ( scff_Wires[35] ) , .SC_OUT_TOP ( scff_Wires[36] ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[14] ) , @@ -144060,23 +147626,23 @@ cbx_1__1_ cbx_2__4_ ( .pReset_E_out ( SYNOPSYS_UNCONNECTED_5776 ) , .prog_clk_0_N_in ( prog_clk_0_wires[75] ) , .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_5777 ) , - .prog_clk_1_W_in ( p1927 ) , .prog_clk_1_E_in ( p649 ) , + .prog_clk_1_W_in ( p1557 ) , .prog_clk_1_E_in ( p854 ) , .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_5778 ) , .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_5779 ) , .prog_clk_2_E_in ( prog_clk_2_wires[7] ) , .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_5780 ) , .prog_clk_2_W_out ( prog_clk_2_wires[6] ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5781 ) , - .prog_clk_3_W_in ( p1927 ) , .prog_clk_3_E_in ( p1104 ) , + .prog_clk_3_W_in ( p1340 ) , .prog_clk_3_E_in ( p741 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5782 ) , - .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5783 ) , .clk_1_W_in ( p1776 ) , - .clk_1_E_in ( p569 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_5784 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5783 ) , .clk_1_W_in ( p1340 ) , + .clk_1_E_in ( p354 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_5784 ) , .clk_1_S_out ( SYNOPSYS_UNCONNECTED_5785 ) , .clk_2_E_in ( clk_2_wires[7] ) , .clk_2_W_in ( SYNOPSYS_UNCONNECTED_5786 ) , .clk_2_W_out ( clk_2_wires[6] ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5787 ) , .clk_3_W_in ( p1927 ) , - .clk_3_E_in ( p13 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5788 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5787 ) , .clk_3_W_in ( p1465 ) , + .clk_3_E_in ( p1047 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5788 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5789 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; cbx_1__1_ cbx_2__5_ ( .pReset ( { SYNOPSYS_UNCONNECTED_5790 } ) , @@ -144101,7 +147667,7 @@ cbx_1__1_ cbx_2__5_ ( .bottom_grid_pin_13_ ( cbx_1__1__15_bottom_grid_pin_13_ ) , .bottom_grid_pin_14_ ( cbx_1__1__15_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__15_bottom_grid_pin_15_ ) , - .ccff_tail ( cbx_1__1__15_ccff_tail ) , .SC_IN_TOP ( p2210 ) , + .ccff_tail ( cbx_1__1__15_ccff_tail ) , .SC_IN_TOP ( p1323 ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_5791 ) , .SC_IN_BOT ( scff_Wires[37] ) , .SC_OUT_TOP ( scff_Wires[38] ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[15] ) , @@ -144117,20 +147683,20 @@ cbx_1__1_ cbx_2__5_ ( .prog_clk_1_W_in ( prog_clk_1_wires[15] ) , .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_5795 ) , .prog_clk_1_N_out ( prog_clk_1_wires[19] ) , - .prog_clk_1_S_out ( prog_clk_1_wires[20] ) , .prog_clk_2_E_in ( p1443 ) , - .prog_clk_2_W_in ( p470 ) , + .prog_clk_1_S_out ( prog_clk_1_wires[20] ) , .prog_clk_2_E_in ( p3148 ) , + .prog_clk_2_W_in ( p2490 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5796 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5797 ) , - .prog_clk_3_W_in ( p1945 ) , .prog_clk_3_E_in ( p1985 ) , + .prog_clk_3_W_in ( p2554 ) , .prog_clk_3_E_in ( p3085 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5798 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5799 ) , .clk_1_W_in ( clk_1_wires[15] ) , .clk_1_E_in ( SYNOPSYS_UNCONNECTED_5800 ) , .clk_1_N_out ( clk_1_wires[19] ) , .clk_1_S_out ( clk_1_wires[20] ) , - .clk_2_E_in ( p1443 ) , .clk_2_W_in ( p1717 ) , + .clk_2_E_in ( p2227 ) , .clk_2_W_in ( p3527 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5801 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5802 ) , .clk_3_W_in ( p1576 ) , - .clk_3_E_in ( p975 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5803 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5802 ) , .clk_3_W_in ( p3537 ) , + .clk_3_E_in ( p2167 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5803 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5804 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; cbx_1__1_ cbx_2__6_ ( .pReset ( { SYNOPSYS_UNCONNECTED_5805 } ) , @@ -144155,7 +147721,7 @@ cbx_1__1_ cbx_2__6_ ( .bottom_grid_pin_13_ ( cbx_1__1__16_bottom_grid_pin_13_ ) , .bottom_grid_pin_14_ ( cbx_1__1__16_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__16_bottom_grid_pin_15_ ) , - .ccff_tail ( cbx_1__1__16_ccff_tail ) , .SC_IN_TOP ( p2186 ) , + .ccff_tail ( cbx_1__1__16_ccff_tail ) , .SC_IN_TOP ( p1208 ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_5806 ) , .SC_IN_BOT ( scff_Wires[39] ) , .SC_OUT_TOP ( scff_Wires[40] ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[16] ) , @@ -144168,20 +147734,20 @@ cbx_1__1_ cbx_2__6_ ( .pReset_E_out ( SYNOPSYS_UNCONNECTED_5808 ) , .prog_clk_0_N_in ( prog_clk_0_wires[81] ) , .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_5809 ) , - .prog_clk_1_W_in ( p2788 ) , .prog_clk_1_E_in ( p472 ) , + .prog_clk_1_W_in ( p1343 ) , .prog_clk_1_E_in ( p571 ) , .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_5810 ) , .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_5811 ) , - .prog_clk_2_E_in ( p1875 ) , .prog_clk_2_W_in ( p2755 ) , + .prog_clk_2_E_in ( p3476 ) , .prog_clk_2_W_in ( p2462 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5812 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5813 ) , - .prog_clk_3_W_in ( p3364 ) , .prog_clk_3_E_in ( p2015 ) , + .prog_clk_3_W_in ( p2619 ) , .prog_clk_3_E_in ( p3451 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5814 ) , - .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5815 ) , .clk_1_W_in ( p1768 ) , - .clk_1_E_in ( p846 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_5816 ) , - .clk_1_S_out ( SYNOPSYS_UNCONNECTED_5817 ) , .clk_2_E_in ( p1875 ) , - .clk_2_W_in ( p3353 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5818 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5819 ) , .clk_3_W_in ( p2632 ) , - .clk_3_E_in ( p1741 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5820 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5815 ) , .clk_1_W_in ( p2544 ) , + .clk_1_E_in ( p805 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_5816 ) , + .clk_1_S_out ( SYNOPSYS_UNCONNECTED_5817 ) , .clk_2_E_in ( p2498 ) , + .clk_2_W_in ( p3430 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5818 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5819 ) , .clk_3_W_in ( p3454 ) , + .clk_3_E_in ( p2447 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5820 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5821 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; cbx_1__1_ cbx_2__7_ ( .pReset ( { SYNOPSYS_UNCONNECTED_5822 } ) , @@ -144206,7 +147772,7 @@ cbx_1__1_ cbx_2__7_ ( .bottom_grid_pin_13_ ( cbx_1__1__17_bottom_grid_pin_13_ ) , .bottom_grid_pin_14_ ( cbx_1__1__17_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__17_bottom_grid_pin_15_ ) , - .ccff_tail ( cbx_1__1__17_ccff_tail ) , .SC_IN_TOP ( p2100 ) , + .ccff_tail ( cbx_1__1__17_ccff_tail ) , .SC_IN_TOP ( p2004 ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_5823 ) , .SC_IN_BOT ( scff_Wires[41] ) , .SC_OUT_TOP ( scff_Wires[42] ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[17] ) , @@ -144222,20 +147788,20 @@ cbx_1__1_ cbx_2__7_ ( .prog_clk_1_W_in ( prog_clk_1_wires[22] ) , .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_5827 ) , .prog_clk_1_N_out ( prog_clk_1_wires[26] ) , - .prog_clk_1_S_out ( prog_clk_1_wires[27] ) , .prog_clk_2_E_in ( p1855 ) , - .prog_clk_2_W_in ( p1090 ) , + .prog_clk_1_S_out ( prog_clk_1_wires[27] ) , .prog_clk_2_E_in ( p3325 ) , + .prog_clk_2_W_in ( p3204 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5828 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5829 ) , - .prog_clk_3_W_in ( p2780 ) , .prog_clk_3_E_in ( p1981 ) , + .prog_clk_3_W_in ( p3225 ) , .prog_clk_3_E_in ( p3306 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5830 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5831 ) , .clk_1_W_in ( clk_1_wires[22] ) , .clk_1_E_in ( SYNOPSYS_UNCONNECTED_5832 ) , .clk_1_N_out ( clk_1_wires[26] ) , .clk_1_S_out ( clk_1_wires[27] ) , - .clk_2_E_in ( p1855 ) , .clk_2_W_in ( p3043 ) , + .clk_2_E_in ( p2571 ) , .clk_2_W_in ( p2934 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5833 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5834 ) , .clk_3_W_in ( p3055 ) , - .clk_3_E_in ( p1773 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5835 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5834 ) , .clk_3_W_in ( p2952 ) , + .clk_3_E_in ( p2464 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5835 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5836 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; cbx_1__1_ cbx_2__8_ ( .pReset ( { SYNOPSYS_UNCONNECTED_5837 } ) , @@ -144260,7 +147826,7 @@ cbx_1__1_ cbx_2__8_ ( .bottom_grid_pin_13_ ( cbx_1__1__18_bottom_grid_pin_13_ ) , .bottom_grid_pin_14_ ( cbx_1__1__18_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__18_bottom_grid_pin_15_ ) , - .ccff_tail ( cbx_1__1__18_ccff_tail ) , .SC_IN_TOP ( p1759 ) , + .ccff_tail ( cbx_1__1__18_ccff_tail ) , .SC_IN_TOP ( p1612 ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_5838 ) , .SC_IN_BOT ( scff_Wires[43] ) , .SC_OUT_TOP ( scff_Wires[44] ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[18] ) , @@ -144273,23 +147839,23 @@ cbx_1__1_ cbx_2__8_ ( .pReset_E_out ( SYNOPSYS_UNCONNECTED_5840 ) , .prog_clk_0_N_in ( prog_clk_0_wires[87] ) , .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_5841 ) , - .prog_clk_1_W_in ( p1825 ) , .prog_clk_1_E_in ( p411 ) , + .prog_clk_1_W_in ( p1484 ) , .prog_clk_1_E_in ( p655 ) , .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_5842 ) , .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_5843 ) , .prog_clk_2_E_in ( prog_clk_2_wires[14] ) , .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_5844 ) , .prog_clk_2_W_out ( prog_clk_2_wires[13] ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5845 ) , - .prog_clk_3_W_in ( p1825 ) , .prog_clk_3_E_in ( p1712 ) , + .prog_clk_3_W_in ( p1655 ) , .prog_clk_3_E_in ( p1070 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5846 ) , - .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5847 ) , .clk_1_W_in ( p1534 ) , - .clk_1_E_in ( p465 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_5848 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5847 ) , .clk_1_W_in ( p1335 ) , + .clk_1_E_in ( p255 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_5848 ) , .clk_1_S_out ( SYNOPSYS_UNCONNECTED_5849 ) , .clk_2_E_in ( clk_2_wires[14] ) , .clk_2_W_in ( SYNOPSYS_UNCONNECTED_5850 ) , .clk_2_W_out ( clk_2_wires[13] ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5851 ) , .clk_3_W_in ( p1825 ) , - .clk_3_E_in ( p1287 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5852 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5851 ) , .clk_3_W_in ( p371 ) , + .clk_3_E_in ( p528 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5852 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5853 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; cbx_1__1_ cbx_2__9_ ( .pReset ( { SYNOPSYS_UNCONNECTED_5854 } ) , @@ -144314,7 +147880,7 @@ cbx_1__1_ cbx_2__9_ ( .bottom_grid_pin_13_ ( cbx_1__1__19_bottom_grid_pin_13_ ) , .bottom_grid_pin_14_ ( cbx_1__1__19_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__19_bottom_grid_pin_15_ ) , - .ccff_tail ( cbx_1__1__19_ccff_tail ) , .SC_IN_TOP ( p1526 ) , + .ccff_tail ( cbx_1__1__19_ccff_tail ) , .SC_IN_TOP ( p1305 ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_5855 ) , .SC_IN_BOT ( scff_Wires[45] ) , .SC_OUT_TOP ( scff_Wires[46] ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[19] ) , @@ -144330,20 +147896,20 @@ cbx_1__1_ cbx_2__9_ ( .prog_clk_1_W_in ( prog_clk_1_wires[29] ) , .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_5859 ) , .prog_clk_1_N_out ( prog_clk_1_wires[33] ) , - .prog_clk_1_S_out ( prog_clk_1_wires[34] ) , .prog_clk_2_E_in ( p2809 ) , - .prog_clk_2_W_in ( p1225 ) , + .prog_clk_1_S_out ( prog_clk_1_wires[34] ) , .prog_clk_2_E_in ( p3165 ) , + .prog_clk_2_W_in ( p2673 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5860 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5861 ) , - .prog_clk_3_W_in ( p3449 ) , .prog_clk_3_E_in ( p672 ) , + .prog_clk_3_W_in ( p2760 ) , .prog_clk_3_E_in ( p3083 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5862 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5863 ) , .clk_1_W_in ( clk_1_wires[29] ) , .clk_1_E_in ( SYNOPSYS_UNCONNECTED_5864 ) , .clk_1_N_out ( clk_1_wires[33] ) , .clk_1_S_out ( clk_1_wires[34] ) , - .clk_2_E_in ( p2809 ) , .clk_2_W_in ( p3443 ) , + .clk_2_E_in ( p1591 ) , .clk_2_W_in ( p2428 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5865 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5866 ) , .clk_3_W_in ( p1929 ) , - .clk_3_E_in ( p2758 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5867 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5866 ) , .clk_3_W_in ( p2524 ) , + .clk_3_E_in ( p1087 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5867 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5868 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; cbx_1__1_ cbx_2__10_ ( .pReset ( { SYNOPSYS_UNCONNECTED_5869 } ) , @@ -144368,7 +147934,7 @@ cbx_1__1_ cbx_2__10_ ( .bottom_grid_pin_13_ ( cbx_1__1__20_bottom_grid_pin_13_ ) , .bottom_grid_pin_14_ ( cbx_1__1__20_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__20_bottom_grid_pin_15_ ) , - .ccff_tail ( cbx_1__1__20_ccff_tail ) , .SC_IN_TOP ( p2158 ) , + .ccff_tail ( cbx_1__1__20_ccff_tail ) , .SC_IN_TOP ( p1991 ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_5870 ) , .SC_IN_BOT ( scff_Wires[47] ) , .SC_OUT_TOP ( scff_Wires[48] ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[20] ) , @@ -144381,23 +147947,23 @@ cbx_1__1_ cbx_2__10_ ( .pReset_E_out ( SYNOPSYS_UNCONNECTED_5872 ) , .prog_clk_0_N_in ( prog_clk_0_wires[93] ) , .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_5873 ) , - .prog_clk_1_W_in ( p1607 ) , .prog_clk_1_E_in ( p921 ) , + .prog_clk_1_W_in ( p1506 ) , .prog_clk_1_E_in ( p803 ) , .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_5874 ) , .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_5875 ) , .prog_clk_2_E_in ( prog_clk_2_wires[21] ) , .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_5876 ) , .prog_clk_2_W_out ( prog_clk_2_wires[20] ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5877 ) , - .prog_clk_3_W_in ( p1527 ) , .prog_clk_3_E_in ( p2047 ) , + .prog_clk_3_W_in ( p1604 ) , .prog_clk_3_E_in ( p1769 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5878 ) , - .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5879 ) , .clk_1_W_in ( p1422 ) , - .clk_1_E_in ( p380 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_5880 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5879 ) , .clk_1_W_in ( p1604 ) , + .clk_1_E_in ( p530 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_5880 ) , .clk_1_S_out ( SYNOPSYS_UNCONNECTED_5881 ) , .clk_2_E_in ( clk_2_wires[21] ) , .clk_2_W_in ( SYNOPSYS_UNCONNECTED_5882 ) , .clk_2_W_out ( clk_2_wires[20] ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5883 ) , .clk_3_W_in ( p1527 ) , - .clk_3_E_in ( p1320 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5884 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5883 ) , .clk_3_W_in ( p1604 ) , + .clk_3_E_in ( p15 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5884 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5885 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; cbx_1__1_ cbx_2__11_ ( .pReset ( { SYNOPSYS_UNCONNECTED_5886 } ) , @@ -144422,7 +147988,7 @@ cbx_1__1_ cbx_2__11_ ( .bottom_grid_pin_13_ ( cbx_1__1__21_bottom_grid_pin_13_ ) , .bottom_grid_pin_14_ ( cbx_1__1__21_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__21_bottom_grid_pin_15_ ) , - .ccff_tail ( cbx_1__1__21_ccff_tail ) , .SC_IN_TOP ( p1787 ) , + .ccff_tail ( cbx_1__1__21_ccff_tail ) , .SC_IN_TOP ( p1454 ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_5887 ) , .SC_IN_BOT ( scff_Wires[49] ) , .SC_OUT_TOP ( scff_Wires[50] ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[21] ) , @@ -144438,20 +148004,20 @@ cbx_1__1_ cbx_2__11_ ( .prog_clk_1_W_in ( prog_clk_1_wires[36] ) , .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_5891 ) , .prog_clk_1_N_out ( prog_clk_1_wires[40] ) , - .prog_clk_1_S_out ( prog_clk_1_wires[41] ) , .prog_clk_2_E_in ( p1939 ) , - .prog_clk_2_W_in ( p751 ) , + .prog_clk_1_S_out ( prog_clk_1_wires[41] ) , .prog_clk_2_E_in ( p3131 ) , + .prog_clk_2_W_in ( p2917 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5892 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5893 ) , - .prog_clk_3_W_in ( p2700 ) , .prog_clk_3_E_in ( p1765 ) , + .prog_clk_3_W_in ( p2974 ) , .prog_clk_3_E_in ( p3035 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5894 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5895 ) , .clk_1_W_in ( clk_1_wires[36] ) , .clk_1_E_in ( SYNOPSYS_UNCONNECTED_5896 ) , .clk_1_N_out ( clk_1_wires[40] ) , .clk_1_S_out ( clk_1_wires[41] ) , - .clk_2_E_in ( p1939 ) , .clk_2_W_in ( p2894 ) , + .clk_2_E_in ( p2248 ) , .clk_2_W_in ( p3177 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5897 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5898 ) , .clk_3_W_in ( p2940 ) , - .clk_3_E_in ( p1697 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5899 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5898 ) , .clk_3_W_in ( p3262 ) , + .clk_3_E_in ( p2205 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5899 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5900 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; cbx_1__1_ cbx_3__1_ ( .pReset ( { SYNOPSYS_UNCONNECTED_5901 } ) , @@ -144477,7 +148043,7 @@ cbx_1__1_ cbx_3__1_ ( .bottom_grid_pin_14_ ( cbx_1__1__22_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__22_bottom_grid_pin_15_ ) , .ccff_tail ( cbx_1__1__22_ccff_tail ) , .SC_IN_TOP ( scff_Wires[75] ) , - .SC_OUT_BOT ( scff_Wires[76] ) , .SC_IN_BOT ( p1327 ) , + .SC_OUT_BOT ( scff_Wires[76] ) , .SC_IN_BOT ( p1435 ) , .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_5902 ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[22] ) , .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[22] ) , @@ -144492,19 +148058,19 @@ cbx_1__1_ cbx_3__1_ ( .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_5906 ) , .prog_clk_1_E_in ( prog_clk_1_wires[44] ) , .prog_clk_1_N_out ( prog_clk_1_wires[45] ) , - .prog_clk_1_S_out ( prog_clk_1_wires[46] ) , .prog_clk_2_E_in ( p2647 ) , - .prog_clk_2_W_in ( p1182 ) , + .prog_clk_1_S_out ( prog_clk_1_wires[46] ) , .prog_clk_2_E_in ( p2795 ) , + .prog_clk_2_W_in ( p2496 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5907 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5908 ) , - .prog_clk_3_W_in ( p3317 ) , .prog_clk_3_E_in ( p972 ) , + .prog_clk_3_W_in ( p2538 ) , .prog_clk_3_E_in ( p2731 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5909 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5910 ) , .clk_1_W_in ( SYNOPSYS_UNCONNECTED_5911 ) , .clk_1_E_in ( clk_1_wires[44] ) , .clk_1_N_out ( clk_1_wires[45] ) , - .clk_1_S_out ( clk_1_wires[46] ) , .clk_2_E_in ( p2647 ) , - .clk_2_W_in ( p3295 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5912 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5913 ) , .clk_3_W_in ( p2628 ) , - .clk_3_E_in ( p2525 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5914 ) , + .clk_1_S_out ( clk_1_wires[46] ) , .clk_2_E_in ( p2247 ) , + .clk_2_W_in ( p3289 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5912 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5913 ) , .clk_3_W_in ( p3348 ) , + .clk_3_E_in ( p2170 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5914 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5915 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; cbx_1__1_ cbx_3__2_ ( .pReset ( { SYNOPSYS_UNCONNECTED_5916 } ) , @@ -144530,7 +148096,7 @@ cbx_1__1_ cbx_3__2_ ( .bottom_grid_pin_14_ ( cbx_1__1__23_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__23_bottom_grid_pin_15_ ) , .ccff_tail ( cbx_1__1__23_ccff_tail ) , .SC_IN_TOP ( scff_Wires[73] ) , - .SC_OUT_BOT ( scff_Wires[74] ) , .SC_IN_BOT ( p1570 ) , + .SC_OUT_BOT ( scff_Wires[74] ) , .SC_IN_BOT ( p1924 ) , .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_5917 ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[23] ) , .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[23] ) , @@ -144542,20 +148108,20 @@ cbx_1__1_ cbx_3__2_ ( .pReset_E_out ( SYNOPSYS_UNCONNECTED_5919 ) , .prog_clk_0_N_in ( prog_clk_0_wires[107] ) , .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_5920 ) , - .prog_clk_1_W_in ( p2689 ) , .prog_clk_1_E_in ( p716 ) , + .prog_clk_1_W_in ( p1310 ) , .prog_clk_1_E_in ( p1779 ) , .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_5921 ) , .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_5922 ) , - .prog_clk_2_E_in ( p1786 ) , .prog_clk_2_W_in ( p2593 ) , + .prog_clk_2_E_in ( p2945 ) , .prog_clk_2_W_in ( p2112 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5923 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5924 ) , - .prog_clk_3_W_in ( p3477 ) , .prog_clk_3_E_in ( p1126 ) , + .prog_clk_3_W_in ( p1533 ) , .prog_clk_3_E_in ( p2908 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5925 ) , - .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5926 ) , .clk_1_W_in ( p1486 ) , - .clk_1_E_in ( p2 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_5927 ) , - .clk_1_S_out ( SYNOPSYS_UNCONNECTED_5928 ) , .clk_2_E_in ( p1786 ) , - .clk_2_W_in ( p3476 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5929 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5930 ) , .clk_3_W_in ( p2811 ) , - .clk_3_E_in ( p1738 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5931 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5926 ) , .clk_1_W_in ( p2193 ) , + .clk_1_E_in ( p211 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_5927 ) , + .clk_1_S_out ( SYNOPSYS_UNCONNECTED_5928 ) , .clk_2_E_in ( p1828 ) , + .clk_2_W_in ( p3436 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5929 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5930 ) , .clk_3_W_in ( p3466 ) , + .clk_3_E_in ( p1705 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5931 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5932 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; cbx_1__1_ cbx_3__3_ ( .pReset ( { SYNOPSYS_UNCONNECTED_5933 } ) , @@ -144581,7 +148147,7 @@ cbx_1__1_ cbx_3__3_ ( .bottom_grid_pin_14_ ( cbx_1__1__24_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__24_bottom_grid_pin_15_ ) , .ccff_tail ( cbx_1__1__24_ccff_tail ) , .SC_IN_TOP ( scff_Wires[71] ) , - .SC_OUT_BOT ( scff_Wires[72] ) , .SC_IN_BOT ( p1370 ) , + .SC_OUT_BOT ( scff_Wires[72] ) , .SC_IN_BOT ( p1494 ) , .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_5934 ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[24] ) , .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[24] ) , @@ -144596,19 +148162,19 @@ cbx_1__1_ cbx_3__3_ ( .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_5938 ) , .prog_clk_1_E_in ( prog_clk_1_wires[51] ) , .prog_clk_1_N_out ( prog_clk_1_wires[52] ) , - .prog_clk_1_S_out ( prog_clk_1_wires[53] ) , .prog_clk_2_E_in ( p2110 ) , - .prog_clk_2_W_in ( p668 ) , + .prog_clk_1_S_out ( prog_clk_1_wires[53] ) , .prog_clk_2_E_in ( p2959 ) , + .prog_clk_2_W_in ( p3366 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5939 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5940 ) , - .prog_clk_3_W_in ( p2640 ) , .prog_clk_3_E_in ( p299 ) , + .prog_clk_3_W_in ( p3422 ) , .prog_clk_3_E_in ( p2929 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5941 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5942 ) , .clk_1_W_in ( SYNOPSYS_UNCONNECTED_5943 ) , .clk_1_E_in ( clk_1_wires[51] ) , .clk_1_N_out ( clk_1_wires[52] ) , - .clk_1_S_out ( clk_1_wires[53] ) , .clk_2_E_in ( p2110 ) , - .clk_2_W_in ( p2586 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5944 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5945 ) , .clk_3_W_in ( p2709 ) , - .clk_3_E_in ( p1966 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5946 ) , + .clk_1_S_out ( clk_1_wires[53] ) , .clk_2_E_in ( p1499 ) , + .clk_2_W_in ( p2488 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5944 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5945 ) , .clk_3_W_in ( p2493 ) , + .clk_3_E_in ( p1090 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5946 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5947 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; cbx_1__1_ cbx_3__4_ ( .pReset ( { SYNOPSYS_UNCONNECTED_5948 } ) , @@ -144634,7 +148200,7 @@ cbx_1__1_ cbx_3__4_ ( .bottom_grid_pin_14_ ( cbx_1__1__25_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__25_bottom_grid_pin_15_ ) , .ccff_tail ( cbx_1__1__25_ccff_tail ) , .SC_IN_TOP ( scff_Wires[69] ) , - .SC_OUT_BOT ( scff_Wires[70] ) , .SC_IN_BOT ( p1517 ) , + .SC_OUT_BOT ( scff_Wires[70] ) , .SC_IN_BOT ( p1249 ) , .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_5949 ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[25] ) , .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[25] ) , @@ -144646,20 +148212,20 @@ cbx_1__1_ cbx_3__4_ ( .pReset_E_out ( SYNOPSYS_UNCONNECTED_5951 ) , .prog_clk_0_N_in ( prog_clk_0_wires[113] ) , .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_5952 ) , - .prog_clk_1_W_in ( p1604 ) , .prog_clk_1_E_in ( p692 ) , + .prog_clk_1_W_in ( p1531 ) , .prog_clk_1_E_in ( p464 ) , .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_5953 ) , .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_5954 ) , - .prog_clk_2_E_in ( p1828 ) , .prog_clk_2_W_in ( p387 ) , + .prog_clk_2_E_in ( p2698 ) , .prog_clk_2_W_in ( p3448 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5955 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5956 ) , - .prog_clk_3_W_in ( p1962 ) , .prog_clk_3_E_in ( p120 ) , + .prog_clk_3_W_in ( p3472 ) , .prog_clk_3_E_in ( p2737 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5957 ) , - .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5958 ) , .clk_1_W_in ( p1372 ) , - .clk_1_E_in ( p669 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_5959 ) , - .clk_1_S_out ( SYNOPSYS_UNCONNECTED_5960 ) , .clk_2_E_in ( p1828 ) , - .clk_2_W_in ( p2721 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5961 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5962 ) , .clk_3_W_in ( p2795 ) , - .clk_3_E_in ( p1688 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5963 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5958 ) , .clk_1_W_in ( p2805 ) , + .clk_1_E_in ( p2174 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_5959 ) , + .clk_1_S_out ( SYNOPSYS_UNCONNECTED_5960 ) , .clk_2_E_in ( p2292 ) , + .clk_2_W_in ( p3489 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5961 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5962 ) , .clk_3_W_in ( p3510 ) , + .clk_3_E_in ( p2151 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5963 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5964 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; cbx_1__1_ cbx_3__5_ ( .pReset ( { SYNOPSYS_UNCONNECTED_5965 } ) , @@ -144685,7 +148251,7 @@ cbx_1__1_ cbx_3__5_ ( .bottom_grid_pin_14_ ( cbx_1__1__26_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__26_bottom_grid_pin_15_ ) , .ccff_tail ( cbx_1__1__26_ccff_tail ) , .SC_IN_TOP ( scff_Wires[67] ) , - .SC_OUT_BOT ( scff_Wires[68] ) , .SC_IN_BOT ( p1319 ) , + .SC_OUT_BOT ( scff_Wires[68] ) , .SC_IN_BOT ( p1490 ) , .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_5966 ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[26] ) , .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[26] ) , @@ -144700,19 +148266,19 @@ cbx_1__1_ cbx_3__5_ ( .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_5970 ) , .prog_clk_1_E_in ( prog_clk_1_wires[58] ) , .prog_clk_1_N_out ( prog_clk_1_wires[59] ) , - .prog_clk_1_S_out ( prog_clk_1_wires[60] ) , .prog_clk_2_E_in ( p2682 ) , - .prog_clk_2_W_in ( p1005 ) , + .prog_clk_1_S_out ( prog_clk_1_wires[60] ) , .prog_clk_2_E_in ( p3453 ) , + .prog_clk_2_W_in ( p2715 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5971 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5972 ) , - .prog_clk_3_W_in ( p3077 ) , .prog_clk_3_E_in ( p979 ) , + .prog_clk_3_W_in ( p2761 ) , .prog_clk_3_E_in ( p3433 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5973 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5974 ) , .clk_1_W_in ( SYNOPSYS_UNCONNECTED_5975 ) , .clk_1_E_in ( clk_1_wires[58] ) , .clk_1_N_out ( clk_1_wires[59] ) , - .clk_1_S_out ( clk_1_wires[60] ) , .clk_2_E_in ( p2682 ) , - .clk_2_W_in ( p3000 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5976 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5977 ) , .clk_3_W_in ( p3060 ) , - .clk_3_E_in ( p2595 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5978 ) , + .clk_1_S_out ( clk_1_wires[60] ) , .clk_2_E_in ( p1424 ) , + .clk_2_W_in ( p3435 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5976 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5977 ) , .clk_3_W_in ( p3475 ) , + .clk_3_E_in ( p1017 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5978 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5979 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; cbx_1__1_ cbx_3__6_ ( .pReset ( { SYNOPSYS_UNCONNECTED_5980 } ) , @@ -144738,7 +148304,7 @@ cbx_1__1_ cbx_3__6_ ( .bottom_grid_pin_14_ ( cbx_1__1__27_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__27_bottom_grid_pin_15_ ) , .ccff_tail ( cbx_1__1__27_ccff_tail ) , .SC_IN_TOP ( scff_Wires[65] ) , - .SC_OUT_BOT ( scff_Wires[66] ) , .SC_IN_BOT ( p2253 ) , + .SC_OUT_BOT ( scff_Wires[66] ) , .SC_IN_BOT ( p1240 ) , .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_5981 ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[27] ) , .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[27] ) , @@ -144750,19 +148316,19 @@ cbx_1__1_ cbx_3__6_ ( .pReset_E_out ( SYNOPSYS_UNCONNECTED_5983 ) , .prog_clk_0_N_in ( prog_clk_0_wires[119] ) , .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_5984 ) , - .prog_clk_1_W_in ( p1585 ) , .prog_clk_1_E_in ( p474 ) , + .prog_clk_1_W_in ( p1367 ) , .prog_clk_1_E_in ( p257 ) , .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_5985 ) , .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_5986 ) , - .prog_clk_2_E_in ( p1091 ) , .prog_clk_2_W_in ( p1314 ) , + .prog_clk_2_E_in ( p1388 ) , .prog_clk_2_W_in ( p2670 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5987 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5988 ) , .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_5989 ) , .prog_clk_3_E_in ( prog_clk_3_wires[50] ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5990 ) , - .prog_clk_3_W_out ( prog_clk_3_wires[51] ) , .clk_1_W_in ( p1428 ) , - .clk_1_E_in ( p1996 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_5991 ) , - .clk_1_S_out ( SYNOPSYS_UNCONNECTED_5992 ) , .clk_2_E_in ( p1091 ) , - .clk_2_W_in ( p652 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5993 ) , + .prog_clk_3_W_out ( prog_clk_3_wires[51] ) , .clk_1_W_in ( p2838 ) , + .clk_1_E_in ( p853 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_5991 ) , + .clk_1_S_out ( SYNOPSYS_UNCONNECTED_5992 ) , .clk_2_E_in ( p1451 ) , + .clk_2_W_in ( p930 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5993 ) , .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5994 ) , .clk_3_W_in ( SYNOPSYS_UNCONNECTED_5995 ) , .clk_3_E_in ( clk_3_wires[50] ) , @@ -144792,7 +148358,7 @@ cbx_1__1_ cbx_3__7_ ( .bottom_grid_pin_14_ ( cbx_1__1__28_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__28_bottom_grid_pin_15_ ) , .ccff_tail ( cbx_1__1__28_ccff_tail ) , .SC_IN_TOP ( scff_Wires[63] ) , - .SC_OUT_BOT ( scff_Wires[64] ) , .SC_IN_BOT ( p1285 ) , + .SC_OUT_BOT ( scff_Wires[64] ) , .SC_IN_BOT ( p1450 ) , .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_5998 ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[28] ) , .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[28] ) , @@ -144807,19 +148373,19 @@ cbx_1__1_ cbx_3__7_ ( .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_6002 ) , .prog_clk_1_E_in ( prog_clk_1_wires[65] ) , .prog_clk_1_N_out ( prog_clk_1_wires[66] ) , - .prog_clk_1_S_out ( prog_clk_1_wires[67] ) , .prog_clk_2_E_in ( p2422 ) , - .prog_clk_2_W_in ( p834 ) , + .prog_clk_1_S_out ( prog_clk_1_wires[67] ) , .prog_clk_2_E_in ( p2353 ) , + .prog_clk_2_W_in ( p3300 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6003 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6004 ) , - .prog_clk_3_W_in ( p2771 ) , .prog_clk_3_E_in ( p1274 ) , + .prog_clk_3_W_in ( p3320 ) , .prog_clk_3_E_in ( p2182 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6005 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6006 ) , .clk_1_W_in ( SYNOPSYS_UNCONNECTED_6007 ) , .clk_1_E_in ( clk_1_wires[65] ) , .clk_1_N_out ( clk_1_wires[66] ) , - .clk_1_S_out ( clk_1_wires[67] ) , .clk_2_E_in ( p2422 ) , - .clk_2_W_in ( p2892 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6008 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6009 ) , .clk_3_W_in ( p2994 ) , - .clk_3_E_in ( p2333 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6010 ) , + .clk_1_S_out ( clk_1_wires[67] ) , .clk_2_E_in ( p3019 ) , + .clk_2_W_in ( p3434 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6008 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6009 ) , .clk_3_W_in ( p3460 ) , + .clk_3_E_in ( p2920 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6010 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6011 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; cbx_1__1_ cbx_3__8_ ( .pReset ( { SYNOPSYS_UNCONNECTED_6012 } ) , @@ -144845,7 +148411,7 @@ cbx_1__1_ cbx_3__8_ ( .bottom_grid_pin_14_ ( cbx_1__1__29_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__29_bottom_grid_pin_15_ ) , .ccff_tail ( cbx_1__1__29_ccff_tail ) , .SC_IN_TOP ( scff_Wires[61] ) , - .SC_OUT_BOT ( scff_Wires[62] ) , .SC_IN_BOT ( p1490 ) , + .SC_OUT_BOT ( scff_Wires[62] ) , .SC_IN_BOT ( p2257 ) , .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_6013 ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[29] ) , .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[29] ) , @@ -144857,20 +148423,20 @@ cbx_1__1_ cbx_3__8_ ( .pReset_E_out ( SYNOPSYS_UNCONNECTED_6015 ) , .prog_clk_0_N_in ( prog_clk_0_wires[125] ) , .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6016 ) , - .prog_clk_1_W_in ( p2648 ) , .prog_clk_1_E_in ( p146 ) , + .prog_clk_1_W_in ( p1201 ) , .prog_clk_1_E_in ( p2147 ) , .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_6017 ) , .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_6018 ) , - .prog_clk_2_E_in ( p2248 ) , .prog_clk_2_W_in ( p2606 ) , + .prog_clk_2_E_in ( p3255 ) , .prog_clk_2_W_in ( p2186 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6019 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6020 ) , - .prog_clk_3_W_in ( p2211 ) , .prog_clk_3_E_in ( p687 ) , + .prog_clk_3_W_in ( p2026 ) , .prog_clk_3_E_in ( p3196 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6021 ) , - .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6022 ) , .clk_1_W_in ( p1770 ) , - .clk_1_E_in ( p637 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_6023 ) , - .clk_1_S_out ( SYNOPSYS_UNCONNECTED_6024 ) , .clk_2_E_in ( p2248 ) , - .clk_2_W_in ( p2909 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6025 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6026 ) , .clk_3_W_in ( p2986 ) , - .clk_3_E_in ( p2068 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6027 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6022 ) , .clk_1_W_in ( p2356 ) , + .clk_1_E_in ( p994 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_6023 ) , + .clk_1_S_out ( SYNOPSYS_UNCONNECTED_6024 ) , .clk_2_E_in ( p3025 ) , + .clk_2_W_in ( p3076 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6025 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6026 ) , .clk_3_W_in ( p3109 ) , + .clk_3_E_in ( p2935 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6027 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6028 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; cbx_1__1_ cbx_3__9_ ( .pReset ( { SYNOPSYS_UNCONNECTED_6029 } ) , @@ -144896,7 +148462,7 @@ cbx_1__1_ cbx_3__9_ ( .bottom_grid_pin_14_ ( cbx_1__1__30_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__30_bottom_grid_pin_15_ ) , .ccff_tail ( cbx_1__1__30_ccff_tail ) , .SC_IN_TOP ( scff_Wires[59] ) , - .SC_OUT_BOT ( scff_Wires[60] ) , .SC_IN_BOT ( p1566 ) , + .SC_OUT_BOT ( scff_Wires[60] ) , .SC_IN_BOT ( p1375 ) , .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_6030 ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[30] ) , .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[30] ) , @@ -144911,19 +148477,19 @@ cbx_1__1_ cbx_3__9_ ( .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_6034 ) , .prog_clk_1_E_in ( prog_clk_1_wires[72] ) , .prog_clk_1_N_out ( prog_clk_1_wires[73] ) , - .prog_clk_1_S_out ( prog_clk_1_wires[74] ) , .prog_clk_2_E_in ( p1850 ) , - .prog_clk_2_W_in ( p449 ) , + .prog_clk_1_S_out ( prog_clk_1_wires[74] ) , .prog_clk_2_E_in ( p2766 ) , + .prog_clk_2_W_in ( p2690 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6035 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6036 ) , - .prog_clk_3_W_in ( p3437 ) , .prog_clk_3_E_in ( p954 ) , + .prog_clk_3_W_in ( p2831 ) , .prog_clk_3_E_in ( p2649 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6037 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6038 ) , .clk_1_W_in ( SYNOPSYS_UNCONNECTED_6039 ) , .clk_1_E_in ( clk_1_wires[72] ) , .clk_1_N_out ( clk_1_wires[73] ) , - .clk_1_S_out ( clk_1_wires[74] ) , .clk_2_E_in ( p1850 ) , - .clk_2_W_in ( p3419 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6040 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6041 ) , .clk_3_W_in ( p2692 ) , - .clk_3_E_in ( p1742 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6042 ) , + .clk_1_S_out ( clk_1_wires[74] ) , .clk_2_E_in ( p1418 ) , + .clk_2_W_in ( p3312 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6040 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6041 ) , .clk_3_W_in ( p3322 ) , + .clk_3_E_in ( p1151 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6042 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6043 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; cbx_1__1_ cbx_3__10_ ( .pReset ( { SYNOPSYS_UNCONNECTED_6044 } ) , @@ -144949,7 +148515,7 @@ cbx_1__1_ cbx_3__10_ ( .bottom_grid_pin_14_ ( cbx_1__1__31_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__31_bottom_grid_pin_15_ ) , .ccff_tail ( cbx_1__1__31_ccff_tail ) , .SC_IN_TOP ( scff_Wires[57] ) , - .SC_OUT_BOT ( scff_Wires[58] ) , .SC_IN_BOT ( p1456 ) , + .SC_OUT_BOT ( scff_Wires[58] ) , .SC_IN_BOT ( p1129 ) , .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_6045 ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[31] ) , .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[31] ) , @@ -144961,20 +148527,20 @@ cbx_1__1_ cbx_3__10_ ( .pReset_E_out ( SYNOPSYS_UNCONNECTED_6047 ) , .prog_clk_0_N_in ( prog_clk_0_wires[131] ) , .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6048 ) , - .prog_clk_1_W_in ( p2817 ) , .prog_clk_1_E_in ( p980 ) , + .prog_clk_1_W_in ( p1365 ) , .prog_clk_1_E_in ( p469 ) , .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_6049 ) , .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_6050 ) , - .prog_clk_2_E_in ( p1499 ) , .prog_clk_2_W_in ( p2759 ) , + .prog_clk_2_E_in ( p2522 ) , .prog_clk_2_W_in ( p2881 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6051 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6052 ) , - .prog_clk_3_W_in ( p2234 ) , .prog_clk_3_E_in ( p571 ) , + .prog_clk_3_W_in ( p2987 ) , .prog_clk_3_E_in ( p2492 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6053 ) , - .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6054 ) , .clk_1_W_in ( p1445 ) , - .clk_1_E_in ( p398 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_6055 ) , - .clk_1_S_out ( SYNOPSYS_UNCONNECTED_6056 ) , .clk_2_E_in ( p1499 ) , - .clk_2_W_in ( p2095 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6057 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6058 ) , .clk_3_W_in ( p2192 ) , - .clk_3_E_in ( p1106 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6059 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6054 ) , .clk_1_W_in ( p2575 ) , + .clk_1_E_in ( p1088 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_6055 ) , + .clk_1_S_out ( SYNOPSYS_UNCONNECTED_6056 ) , .clk_2_E_in ( p2513 ) , + .clk_2_W_in ( p3212 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6057 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6058 ) , .clk_3_W_in ( p3265 ) , + .clk_3_E_in ( p2392 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6059 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6060 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; cbx_1__1_ cbx_3__11_ ( .pReset ( { SYNOPSYS_UNCONNECTED_6061 } ) , @@ -145000,7 +148566,7 @@ cbx_1__1_ cbx_3__11_ ( .bottom_grid_pin_14_ ( cbx_1__1__32_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__32_bottom_grid_pin_15_ ) , .ccff_tail ( cbx_1__1__32_ccff_tail ) , .SC_IN_TOP ( scff_Wires[55] ) , - .SC_OUT_BOT ( scff_Wires[56] ) , .SC_IN_BOT ( p1489 ) , + .SC_OUT_BOT ( scff_Wires[56] ) , .SC_IN_BOT ( p1880 ) , .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_6062 ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[32] ) , .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[32] ) , @@ -145015,19 +148581,19 @@ cbx_1__1_ cbx_3__11_ ( .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_6066 ) , .prog_clk_1_E_in ( prog_clk_1_wires[79] ) , .prog_clk_1_N_out ( prog_clk_1_wires[80] ) , - .prog_clk_1_S_out ( prog_clk_1_wires[81] ) , .prog_clk_2_E_in ( p1581 ) , - .prog_clk_2_W_in ( p1166 ) , + .prog_clk_1_S_out ( prog_clk_1_wires[81] ) , .prog_clk_2_E_in ( p2802 ) , + .prog_clk_2_W_in ( p3283 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6067 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6068 ) , - .prog_clk_3_W_in ( p3259 ) , .prog_clk_3_E_in ( p745 ) , + .prog_clk_3_W_in ( p3323 ) , .prog_clk_3_E_in ( p2704 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6069 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6070 ) , .clk_1_W_in ( SYNOPSYS_UNCONNECTED_6071 ) , .clk_1_E_in ( clk_1_wires[79] ) , .clk_1_N_out ( clk_1_wires[80] ) , - .clk_1_S_out ( clk_1_wires[81] ) , .clk_2_E_in ( p1581 ) , - .clk_2_W_in ( p3234 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6072 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6073 ) , .clk_3_W_in ( p2789 ) , - .clk_3_E_in ( p1205 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6074 ) , + .clk_1_S_out ( clk_1_wires[81] ) , .clk_2_E_in ( p2822 ) , + .clk_2_W_in ( p2483 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6072 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6073 ) , .clk_3_W_in ( p2556 ) , + .clk_3_E_in ( p2735 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6074 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6075 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; cbx_1__1_ cbx_4__1_ ( .pReset ( { SYNOPSYS_UNCONNECTED_6076 } ) , @@ -145052,7 +148618,7 @@ cbx_1__1_ cbx_4__1_ ( .bottom_grid_pin_13_ ( cbx_1__1__33_bottom_grid_pin_13_ ) , .bottom_grid_pin_14_ ( cbx_1__1__33_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__33_bottom_grid_pin_15_ ) , - .ccff_tail ( cbx_1__1__33_ccff_tail ) , .SC_IN_TOP ( p1007 ) , + .ccff_tail ( cbx_1__1__33_ccff_tail ) , .SC_IN_TOP ( p1379 ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_6077 ) , .SC_IN_BOT ( scff_Wires[82] ) , .SC_OUT_TOP ( scff_Wires[83] ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[33] ) , @@ -145068,20 +148634,20 @@ cbx_1__1_ cbx_4__1_ ( .prog_clk_1_W_in ( prog_clk_1_wires[43] ) , .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_6081 ) , .prog_clk_1_N_out ( prog_clk_1_wires[47] ) , - .prog_clk_1_S_out ( prog_clk_1_wires[48] ) , .prog_clk_2_E_in ( p2513 ) , - .prog_clk_2_W_in ( p815 ) , + .prog_clk_1_S_out ( prog_clk_1_wires[48] ) , .prog_clk_2_E_in ( p3263 ) , + .prog_clk_2_W_in ( p842 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6082 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6083 ) , - .prog_clk_3_W_in ( p3085 ) , .prog_clk_3_E_in ( p787 ) , + .prog_clk_3_W_in ( p1329 ) , .prog_clk_3_E_in ( p3215 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6084 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6085 ) , .clk_1_W_in ( clk_1_wires[43] ) , .clk_1_E_in ( SYNOPSYS_UNCONNECTED_6086 ) , .clk_1_N_out ( clk_1_wires[47] ) , .clk_1_S_out ( clk_1_wires[48] ) , - .clk_2_E_in ( p2513 ) , .clk_2_W_in ( p3003 ) , + .clk_2_E_in ( p2629 ) , .clk_2_W_in ( p3040 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6087 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6088 ) , .clk_3_W_in ( p2777 ) , - .clk_3_E_in ( p2275 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6089 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6088 ) , .clk_3_W_in ( p3163 ) , + .clk_3_E_in ( p2480 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6089 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6090 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; cbx_1__1_ cbx_4__2_ ( .pReset ( { SYNOPSYS_UNCONNECTED_6091 } ) , @@ -145106,7 +148672,7 @@ cbx_1__1_ cbx_4__2_ ( .bottom_grid_pin_13_ ( cbx_1__1__34_bottom_grid_pin_13_ ) , .bottom_grid_pin_14_ ( cbx_1__1__34_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__34_bottom_grid_pin_15_ ) , - .ccff_tail ( cbx_1__1__34_ccff_tail ) , .SC_IN_TOP ( p2133 ) , + .ccff_tail ( cbx_1__1__34_ccff_tail ) , .SC_IN_TOP ( p1441 ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_6092 ) , .SC_IN_BOT ( scff_Wires[84] ) , .SC_OUT_TOP ( scff_Wires[85] ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[34] ) , @@ -145119,23 +148685,23 @@ cbx_1__1_ cbx_4__2_ ( .pReset_E_out ( SYNOPSYS_UNCONNECTED_6094 ) , .prog_clk_0_N_in ( prog_clk_0_wires[145] ) , .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6095 ) , - .prog_clk_1_W_in ( p1421 ) , .prog_clk_1_E_in ( p2359 ) , + .prog_clk_1_W_in ( p1492 ) , .prog_clk_1_E_in ( p104 ) , .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_6096 ) , .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_6097 ) , .prog_clk_2_E_in ( prog_clk_2_wires[27] ) , .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_6098 ) , .prog_clk_2_W_out ( prog_clk_2_wires[28] ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6099 ) , - .prog_clk_3_W_in ( p1421 ) , .prog_clk_3_E_in ( p2088 ) , + .prog_clk_3_W_in ( p1391 ) , .prog_clk_3_E_in ( p352 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6100 ) , - .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6101 ) , .clk_1_W_in ( p1500 ) , - .clk_1_E_in ( p615 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_6102 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6101 ) , .clk_1_W_in ( p1391 ) , + .clk_1_E_in ( p806 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_6102 ) , .clk_1_S_out ( SYNOPSYS_UNCONNECTED_6103 ) , .clk_2_E_in ( clk_2_wires[27] ) , .clk_2_W_in ( SYNOPSYS_UNCONNECTED_6104 ) , .clk_2_W_out ( clk_2_wires[28] ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6105 ) , .clk_3_W_in ( p1421 ) , - .clk_3_E_in ( p2285 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6106 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6105 ) , .clk_3_W_in ( p1391 ) , + .clk_3_E_in ( p1230 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6106 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6107 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; cbx_1__1_ cbx_4__3_ ( .pReset ( { SYNOPSYS_UNCONNECTED_6108 } ) , @@ -145160,7 +148726,7 @@ cbx_1__1_ cbx_4__3_ ( .bottom_grid_pin_13_ ( cbx_1__1__35_bottom_grid_pin_13_ ) , .bottom_grid_pin_14_ ( cbx_1__1__35_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__35_bottom_grid_pin_15_ ) , - .ccff_tail ( cbx_1__1__35_ccff_tail ) , .SC_IN_TOP ( p1577 ) , + .ccff_tail ( cbx_1__1__35_ccff_tail ) , .SC_IN_TOP ( p1548 ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_6109 ) , .SC_IN_BOT ( scff_Wires[86] ) , .SC_OUT_TOP ( scff_Wires[87] ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[35] ) , @@ -145176,20 +148742,20 @@ cbx_1__1_ cbx_4__3_ ( .prog_clk_1_W_in ( prog_clk_1_wires[50] ) , .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_6113 ) , .prog_clk_1_N_out ( prog_clk_1_wires[54] ) , - .prog_clk_1_S_out ( prog_clk_1_wires[55] ) , .prog_clk_2_E_in ( p2443 ) , - .prog_clk_2_W_in ( p1318 ) , + .prog_clk_1_S_out ( prog_clk_1_wires[55] ) , .prog_clk_2_E_in ( p2219 ) , + .prog_clk_2_W_in ( p3066 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6114 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6115 ) , - .prog_clk_3_W_in ( p2802 ) , .prog_clk_3_E_in ( p72 ) , + .prog_clk_3_W_in ( p3146 ) , .prog_clk_3_E_in ( p2153 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6116 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6117 ) , .clk_1_W_in ( clk_1_wires[50] ) , .clk_1_E_in ( SYNOPSYS_UNCONNECTED_6118 ) , .clk_1_N_out ( clk_1_wires[54] ) , .clk_1_S_out ( clk_1_wires[55] ) , - .clk_2_E_in ( p2443 ) , .clk_2_W_in ( p2750 ) , + .clk_2_E_in ( p2250 ) , .clk_2_W_in ( p1806 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6119 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6120 ) , .clk_3_W_in ( p1847 ) , - .clk_3_E_in ( p2279 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6121 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6120 ) , .clk_3_W_in ( p2002 ) , + .clk_3_E_in ( p2083 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6121 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6122 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; cbx_1__1_ cbx_4__4_ ( .pReset ( { SYNOPSYS_UNCONNECTED_6123 } ) , @@ -145214,7 +148780,7 @@ cbx_1__1_ cbx_4__4_ ( .bottom_grid_pin_13_ ( cbx_1__1__36_bottom_grid_pin_13_ ) , .bottom_grid_pin_14_ ( cbx_1__1__36_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__36_bottom_grid_pin_15_ ) , - .ccff_tail ( cbx_1__1__36_ccff_tail ) , .SC_IN_TOP ( p1885 ) , + .ccff_tail ( cbx_1__1__36_ccff_tail ) , .SC_IN_TOP ( p2574 ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_6124 ) , .SC_IN_BOT ( scff_Wires[88] ) , .SC_OUT_TOP ( scff_Wires[89] ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[36] ) , @@ -145227,23 +148793,23 @@ cbx_1__1_ cbx_4__4_ ( .pReset_E_out ( SYNOPSYS_UNCONNECTED_6126 ) , .prog_clk_0_N_in ( prog_clk_0_wires[151] ) , .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6127 ) , - .prog_clk_1_W_in ( p1794 ) , .prog_clk_1_E_in ( p340 ) , + .prog_clk_1_W_in ( p1205 ) , .prog_clk_1_E_in ( p241 ) , .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_6128 ) , .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_6129 ) , .prog_clk_2_E_in ( prog_clk_2_wires[36] ) , .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_6130 ) , .prog_clk_2_W_out ( prog_clk_2_wires[37] ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6131 ) , - .prog_clk_3_W_in ( p1878 ) , .prog_clk_3_E_in ( p1715 ) , + .prog_clk_3_W_in ( p1840 ) , .prog_clk_3_E_in ( p2432 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6132 ) , - .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6133 ) , .clk_1_W_in ( p1133 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6133 ) , .clk_1_W_in ( p1840 ) , .clk_1_E_in ( p688 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_6134 ) , .clk_1_S_out ( SYNOPSYS_UNCONNECTED_6135 ) , .clk_2_E_in ( clk_2_wires[36] ) , .clk_2_W_in ( SYNOPSYS_UNCONNECTED_6136 ) , .clk_2_W_out ( clk_2_wires[37] ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6137 ) , .clk_3_W_in ( p1878 ) , - .clk_3_E_in ( p1184 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6138 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6137 ) , .clk_3_W_in ( p1840 ) , + .clk_3_E_in ( p194 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6138 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6139 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; cbx_1__1_ cbx_4__5_ ( .pReset ( { SYNOPSYS_UNCONNECTED_6140 } ) , @@ -145268,7 +148834,7 @@ cbx_1__1_ cbx_4__5_ ( .bottom_grid_pin_13_ ( cbx_1__1__37_bottom_grid_pin_13_ ) , .bottom_grid_pin_14_ ( cbx_1__1__37_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__37_bottom_grid_pin_15_ ) , - .ccff_tail ( cbx_1__1__37_ccff_tail ) , .SC_IN_TOP ( p2431 ) , + .ccff_tail ( cbx_1__1__37_ccff_tail ) , .SC_IN_TOP ( p1578 ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_6141 ) , .SC_IN_BOT ( scff_Wires[90] ) , .SC_OUT_TOP ( scff_Wires[91] ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[37] ) , @@ -145284,20 +148850,20 @@ cbx_1__1_ cbx_4__5_ ( .prog_clk_1_W_in ( prog_clk_1_wires[57] ) , .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_6145 ) , .prog_clk_1_N_out ( prog_clk_1_wires[61] ) , - .prog_clk_1_S_out ( prog_clk_1_wires[62] ) , .prog_clk_2_E_in ( p2181 ) , - .prog_clk_2_W_in ( p1219 ) , + .prog_clk_1_S_out ( prog_clk_1_wires[62] ) , .prog_clk_2_E_in ( p3023 ) , + .prog_clk_2_W_in ( p2451 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6146 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6147 ) , - .prog_clk_3_W_in ( p3400 ) , .prog_clk_3_E_in ( p2301 ) , + .prog_clk_3_W_in ( p2615 ) , .prog_clk_3_E_in ( p2863 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6148 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6149 ) , .clk_1_W_in ( clk_1_wires[57] ) , .clk_1_E_in ( SYNOPSYS_UNCONNECTED_6150 ) , .clk_1_N_out ( clk_1_wires[61] ) , .clk_1_S_out ( clk_1_wires[62] ) , - .clk_2_E_in ( p2201 ) , .clk_2_W_in ( p3392 ) , + .clk_2_E_in ( p3167 ) , .clk_2_W_in ( p2709 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6151 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6152 ) , .clk_3_W_in ( p2850 ) , - .clk_3_E_in ( p2060 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6153 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6152 ) , .clk_3_W_in ( p2788 ) , + .clk_3_E_in ( p3063 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6153 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6154 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; cbx_1__1_ cbx_4__6_ ( .pReset ( { SYNOPSYS_UNCONNECTED_6155 } ) , @@ -145322,7 +148888,7 @@ cbx_1__1_ cbx_4__6_ ( .bottom_grid_pin_13_ ( cbx_1__1__38_bottom_grid_pin_13_ ) , .bottom_grid_pin_14_ ( cbx_1__1__38_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__38_bottom_grid_pin_15_ ) , - .ccff_tail ( cbx_1__1__38_ccff_tail ) , .SC_IN_TOP ( p1299 ) , + .ccff_tail ( cbx_1__1__38_ccff_tail ) , .SC_IN_TOP ( p1543 ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_6156 ) , .SC_IN_BOT ( scff_Wires[92] ) , .SC_OUT_TOP ( scff_Wires[93] ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[38] ) , @@ -145335,19 +148901,19 @@ cbx_1__1_ cbx_4__6_ ( .pReset_E_out ( SYNOPSYS_UNCONNECTED_6158 ) , .prog_clk_0_N_in ( prog_clk_0_wires[157] ) , .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6159 ) , - .prog_clk_1_W_in ( p2468 ) , .prog_clk_1_E_in ( p831 ) , + .prog_clk_1_W_in ( p1193 ) , .prog_clk_1_E_in ( p435 ) , .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_6160 ) , .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_6161 ) , - .prog_clk_2_E_in ( p1299 ) , .prog_clk_2_W_in ( p2338 ) , + .prog_clk_2_E_in ( p1997 ) , .prog_clk_2_W_in ( p2406 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6162 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6163 ) , .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_6164 ) , .prog_clk_3_E_in ( prog_clk_3_wires[46] ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6165 ) , - .prog_clk_3_W_out ( prog_clk_3_wires[47] ) , .clk_1_W_in ( p1472 ) , - .clk_1_E_in ( p601 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_6166 ) , - .clk_1_S_out ( SYNOPSYS_UNCONNECTED_6167 ) , .clk_2_E_in ( p1299 ) , - .clk_2_W_in ( p1302 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6168 ) , + .prog_clk_3_W_out ( prog_clk_3_wires[47] ) , .clk_1_W_in ( p2596 ) , + .clk_1_E_in ( p658 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_6166 ) , + .clk_1_S_out ( SYNOPSYS_UNCONNECTED_6167 ) , .clk_2_E_in ( p1997 ) , + .clk_2_W_in ( p899 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6168 ) , .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6169 ) , .clk_3_W_in ( SYNOPSYS_UNCONNECTED_6170 ) , .clk_3_E_in ( clk_3_wires[46] ) , @@ -145376,7 +148942,7 @@ cbx_1__1_ cbx_4__7_ ( .bottom_grid_pin_13_ ( cbx_1__1__39_bottom_grid_pin_13_ ) , .bottom_grid_pin_14_ ( cbx_1__1__39_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__39_bottom_grid_pin_15_ ) , - .ccff_tail ( cbx_1__1__39_ccff_tail ) , .SC_IN_TOP ( p2389 ) , + .ccff_tail ( cbx_1__1__39_ccff_tail ) , .SC_IN_TOP ( p1501 ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_6173 ) , .SC_IN_BOT ( scff_Wires[94] ) , .SC_OUT_TOP ( scff_Wires[95] ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[39] ) , @@ -145392,20 +148958,20 @@ cbx_1__1_ cbx_4__7_ ( .prog_clk_1_W_in ( prog_clk_1_wires[64] ) , .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_6177 ) , .prog_clk_1_N_out ( prog_clk_1_wires[68] ) , - .prog_clk_1_S_out ( prog_clk_1_wires[69] ) , .prog_clk_2_E_in ( p2421 ) , - .prog_clk_2_W_in ( p266 ) , + .prog_clk_1_S_out ( prog_clk_1_wires[69] ) , .prog_clk_2_E_in ( p2306 ) , + .prog_clk_2_W_in ( p2722 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6178 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6179 ) , - .prog_clk_3_W_in ( p2963 ) , .prog_clk_3_E_in ( p2304 ) , + .prog_clk_3_W_in ( p2832 ) , .prog_clk_3_E_in ( p2145 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6180 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6181 ) , .clk_1_W_in ( clk_1_wires[64] ) , .clk_1_E_in ( SYNOPSYS_UNCONNECTED_6182 ) , .clk_1_N_out ( clk_1_wires[68] ) , .clk_1_S_out ( clk_1_wires[69] ) , - .clk_2_E_in ( p2421 ) , .clk_2_W_in ( p3002 ) , + .clk_2_E_in ( p1933 ) , .clk_2_W_in ( p3296 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6183 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6184 ) , .clk_3_W_in ( p3053 ) , - .clk_3_E_in ( p2385 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6185 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6184 ) , .clk_3_W_in ( p3358 ) , + .clk_3_E_in ( p1813 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6185 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6186 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; cbx_1__1_ cbx_4__8_ ( .pReset ( { SYNOPSYS_UNCONNECTED_6187 } ) , @@ -145430,7 +148996,7 @@ cbx_1__1_ cbx_4__8_ ( .bottom_grid_pin_13_ ( cbx_1__1__40_bottom_grid_pin_13_ ) , .bottom_grid_pin_14_ ( cbx_1__1__40_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__40_bottom_grid_pin_15_ ) , - .ccff_tail ( cbx_1__1__40_ccff_tail ) , .SC_IN_TOP ( p1792 ) , + .ccff_tail ( cbx_1__1__40_ccff_tail ) , .SC_IN_TOP ( p1174 ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_6188 ) , .SC_IN_BOT ( scff_Wires[96] ) , .SC_OUT_TOP ( scff_Wires[97] ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[40] ) , @@ -145443,23 +149009,23 @@ cbx_1__1_ cbx_4__8_ ( .pReset_E_out ( SYNOPSYS_UNCONNECTED_6190 ) , .prog_clk_0_N_in ( prog_clk_0_wires[163] ) , .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6191 ) , - .prog_clk_1_W_in ( p1871 ) , .prog_clk_1_E_in ( p10 ) , + .prog_clk_1_W_in ( p721 ) , .prog_clk_1_E_in ( p746 ) , .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_6192 ) , .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_6193 ) , .prog_clk_2_E_in ( prog_clk_2_wires[49] ) , .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_6194 ) , .prog_clk_2_W_out ( prog_clk_2_wires[50] ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6195 ) , - .prog_clk_3_W_in ( p1817 ) , .prog_clk_3_E_in ( p1708 ) , + .prog_clk_3_W_in ( p1964 ) , .prog_clk_3_E_in ( p964 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6196 ) , - .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6197 ) , .clk_1_W_in ( p1407 ) , - .clk_1_E_in ( p531 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_6198 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6197 ) , .clk_1_W_in ( p1875 ) , + .clk_1_E_in ( p414 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_6198 ) , .clk_1_S_out ( SYNOPSYS_UNCONNECTED_6199 ) , .clk_2_E_in ( clk_2_wires[49] ) , .clk_2_W_in ( SYNOPSYS_UNCONNECTED_6200 ) , .clk_2_W_out ( clk_2_wires[50] ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6201 ) , .clk_3_W_in ( p1817 ) , - .clk_3_E_in ( p762 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6202 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6201 ) , .clk_3_W_in ( p1964 ) , + .clk_3_E_in ( p603 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6202 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6203 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; cbx_1__1_ cbx_4__9_ ( .pReset ( { SYNOPSYS_UNCONNECTED_6204 } ) , @@ -145484,7 +149050,7 @@ cbx_1__1_ cbx_4__9_ ( .bottom_grid_pin_13_ ( cbx_1__1__41_bottom_grid_pin_13_ ) , .bottom_grid_pin_14_ ( cbx_1__1__41_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__41_bottom_grid_pin_15_ ) , - .ccff_tail ( cbx_1__1__41_ccff_tail ) , .SC_IN_TOP ( p2091 ) , + .ccff_tail ( cbx_1__1__41_ccff_tail ) , .SC_IN_TOP ( p1411 ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_6205 ) , .SC_IN_BOT ( scff_Wires[98] ) , .SC_OUT_TOP ( scff_Wires[99] ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[41] ) , @@ -145500,20 +149066,20 @@ cbx_1__1_ cbx_4__9_ ( .prog_clk_1_W_in ( prog_clk_1_wires[71] ) , .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_6209 ) , .prog_clk_1_N_out ( prog_clk_1_wires[75] ) , - .prog_clk_1_S_out ( prog_clk_1_wires[76] ) , .prog_clk_2_E_in ( p2444 ) , - .prog_clk_2_W_in ( p1148 ) , + .prog_clk_1_S_out ( prog_clk_1_wires[76] ) , .prog_clk_2_E_in ( p3361 ) , + .prog_clk_2_W_in ( p3485 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6210 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6211 ) , - .prog_clk_3_W_in ( p1516 ) , .prog_clk_3_E_in ( p1993 ) , + .prog_clk_3_W_in ( p3499 ) , .prog_clk_3_E_in ( p3286 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6212 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6213 ) , .clk_1_W_in ( clk_1_wires[71] ) , .clk_1_E_in ( SYNOPSYS_UNCONNECTED_6214 ) , .clk_1_N_out ( clk_1_wires[75] ) , .clk_1_S_out ( clk_1_wires[76] ) , - .clk_2_E_in ( p2444 ) , .clk_2_W_in ( p2906 ) , + .clk_2_E_in ( p2839 ) , .clk_2_W_in ( p2076 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6215 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6216 ) , .clk_3_W_in ( p2970 ) , - .clk_3_E_in ( p2321 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6217 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6216 ) , .clk_3_W_in ( p2329 ) , + .clk_3_E_in ( p2740 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6217 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6218 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; cbx_1__1_ cbx_4__10_ ( .pReset ( { SYNOPSYS_UNCONNECTED_6219 } ) , @@ -145538,7 +149104,7 @@ cbx_1__1_ cbx_4__10_ ( .bottom_grid_pin_13_ ( cbx_1__1__42_bottom_grid_pin_13_ ) , .bottom_grid_pin_14_ ( cbx_1__1__42_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__42_bottom_grid_pin_15_ ) , - .ccff_tail ( cbx_1__1__42_ccff_tail ) , .SC_IN_TOP ( p1425 ) , + .ccff_tail ( cbx_1__1__42_ccff_tail ) , .SC_IN_TOP ( p1130 ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_6220 ) , .SC_IN_BOT ( scff_Wires[100] ) , .SC_OUT_TOP ( scff_Wires[101] ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[42] ) , @@ -145551,23 +149117,23 @@ cbx_1__1_ cbx_4__10_ ( .pReset_E_out ( SYNOPSYS_UNCONNECTED_6222 ) , .prog_clk_0_N_in ( prog_clk_0_wires[169] ) , .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6223 ) , - .prog_clk_1_W_in ( p1799 ) , .prog_clk_1_E_in ( p1643 ) , + .prog_clk_1_W_in ( p1282 ) , .prog_clk_1_E_in ( p676 ) , .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_6224 ) , .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_6225 ) , .prog_clk_2_E_in ( prog_clk_2_wires[62] ) , .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_6226 ) , .prog_clk_2_W_out ( prog_clk_2_wires[63] ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6227 ) , - .prog_clk_3_W_in ( p1799 ) , .prog_clk_3_E_in ( p860 ) , + .prog_clk_3_W_in ( p1223 ) , .prog_clk_3_E_in ( p1005 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6228 ) , - .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6229 ) , .clk_1_W_in ( p1383 ) , - .clk_1_E_in ( p354 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_6230 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6229 ) , .clk_1_W_in ( p1223 ) , + .clk_1_E_in ( p1004 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_6230 ) , .clk_1_S_out ( SYNOPSYS_UNCONNECTED_6231 ) , .clk_2_E_in ( clk_2_wires[62] ) , .clk_2_W_in ( SYNOPSYS_UNCONNECTED_6232 ) , .clk_2_W_out ( clk_2_wires[63] ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6233 ) , .clk_3_W_in ( p1799 ) , - .clk_3_E_in ( p1747 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6234 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6233 ) , .clk_3_W_in ( p1223 ) , + .clk_3_E_in ( p12 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6234 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6235 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; cbx_1__1_ cbx_4__11_ ( .pReset ( { SYNOPSYS_UNCONNECTED_6236 } ) , @@ -145592,7 +149158,7 @@ cbx_1__1_ cbx_4__11_ ( .bottom_grid_pin_13_ ( cbx_1__1__43_bottom_grid_pin_13_ ) , .bottom_grid_pin_14_ ( cbx_1__1__43_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__43_bottom_grid_pin_15_ ) , - .ccff_tail ( cbx_1__1__43_ccff_tail ) , .SC_IN_TOP ( p1884 ) , + .ccff_tail ( cbx_1__1__43_ccff_tail ) , .SC_IN_TOP ( p1916 ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_6237 ) , .SC_IN_BOT ( scff_Wires[102] ) , .SC_OUT_TOP ( scff_Wires[103] ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[43] ) , @@ -145608,20 +149174,20 @@ cbx_1__1_ cbx_4__11_ ( .prog_clk_1_W_in ( prog_clk_1_wires[78] ) , .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_6241 ) , .prog_clk_1_N_out ( prog_clk_1_wires[82] ) , - .prog_clk_1_S_out ( prog_clk_1_wires[83] ) , .prog_clk_2_E_in ( p1442 ) , - .prog_clk_2_W_in ( p1257 ) , + .prog_clk_1_S_out ( prog_clk_1_wires[83] ) , .prog_clk_2_E_in ( p2814 ) , + .prog_clk_2_W_in ( p802 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6242 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6243 ) , - .prog_clk_3_W_in ( p3169 ) , .prog_clk_3_E_in ( p1636 ) , + .prog_clk_3_W_in ( p1239 ) , .prog_clk_3_E_in ( p2716 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6244 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6245 ) , .clk_1_W_in ( clk_1_wires[78] ) , .clk_1_E_in ( SYNOPSYS_UNCONNECTED_6246 ) , .clk_1_N_out ( clk_1_wires[82] ) , .clk_1_S_out ( clk_1_wires[83] ) , - .clk_2_E_in ( p1442 ) , .clk_2_W_in ( p3143 ) , + .clk_2_E_in ( p2824 ) , .clk_2_W_in ( p3447 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6247 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6248 ) , .clk_3_W_in ( p1806 ) , - .clk_3_E_in ( p250 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6249 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6248 ) , .clk_3_W_in ( p3456 ) , + .clk_3_E_in ( p2738 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6249 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6250 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; cbx_1__1_ cbx_5__1_ ( .pReset ( { SYNOPSYS_UNCONNECTED_6251 } ) , @@ -145647,7 +149213,7 @@ cbx_1__1_ cbx_5__1_ ( .bottom_grid_pin_14_ ( cbx_1__1__44_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__44_bottom_grid_pin_15_ ) , .ccff_tail ( cbx_1__1__44_ccff_tail ) , .SC_IN_TOP ( scff_Wires[128] ) , - .SC_OUT_BOT ( scff_Wires[129] ) , .SC_IN_BOT ( p1404 ) , + .SC_OUT_BOT ( scff_Wires[129] ) , .SC_IN_BOT ( p1346 ) , .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_6252 ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[44] ) , .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[44] ) , @@ -145662,19 +149228,19 @@ cbx_1__1_ cbx_5__1_ ( .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_6256 ) , .prog_clk_1_E_in ( prog_clk_1_wires[86] ) , .prog_clk_1_N_out ( prog_clk_1_wires[87] ) , - .prog_clk_1_S_out ( prog_clk_1_wires[88] ) , .prog_clk_2_E_in ( p2612 ) , - .prog_clk_2_W_in ( p1250 ) , + .prog_clk_1_S_out ( prog_clk_1_wires[88] ) , .prog_clk_2_E_in ( p3243 ) , + .prog_clk_2_W_in ( p3192 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6257 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6258 ) , - .prog_clk_3_W_in ( p3244 ) , .prog_clk_3_E_in ( p1038 ) , + .prog_clk_3_W_in ( p3279 ) , .prog_clk_3_E_in ( p3184 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6259 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6260 ) , .clk_1_W_in ( SYNOPSYS_UNCONNECTED_6261 ) , .clk_1_E_in ( clk_1_wires[86] ) , .clk_1_N_out ( clk_1_wires[87] ) , - .clk_1_S_out ( clk_1_wires[88] ) , .clk_2_E_in ( p2612 ) , - .clk_2_W_in ( p3231 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6262 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6263 ) , .clk_3_W_in ( p2653 ) , - .clk_3_E_in ( p2598 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6264 ) , + .clk_1_S_out ( clk_1_wires[88] ) , .clk_2_E_in ( p1624 ) , + .clk_2_W_in ( p3362 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6262 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6263 ) , .clk_3_W_in ( p3396 ) , + .clk_3_E_in ( p284 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6264 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6265 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; cbx_1__1_ cbx_5__2_ ( .pReset ( { SYNOPSYS_UNCONNECTED_6266 } ) , @@ -145700,7 +149266,7 @@ cbx_1__1_ cbx_5__2_ ( .bottom_grid_pin_14_ ( cbx_1__1__45_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__45_bottom_grid_pin_15_ ) , .ccff_tail ( cbx_1__1__45_ccff_tail ) , .SC_IN_TOP ( scff_Wires[126] ) , - .SC_OUT_BOT ( scff_Wires[127] ) , .SC_IN_BOT ( p1457 ) , + .SC_OUT_BOT ( scff_Wires[127] ) , .SC_IN_BOT ( p2280 ) , .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_6267 ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[45] ) , .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[45] ) , @@ -145712,23 +149278,23 @@ cbx_1__1_ cbx_5__2_ ( .pReset_E_out ( SYNOPSYS_UNCONNECTED_6269 ) , .prog_clk_0_N_in ( prog_clk_0_wires[183] ) , .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6270 ) , - .prog_clk_1_W_in ( p1870 ) , .prog_clk_1_E_in ( p1711 ) , + .prog_clk_1_W_in ( p1500 ) , .prog_clk_1_E_in ( p2092 ) , .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_6271 ) , .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_6272 ) , .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_6273 ) , .prog_clk_2_W_in ( prog_clk_2_wires[25] ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6274 ) , - .prog_clk_2_E_out ( prog_clk_2_wires[26] ) , .prog_clk_3_W_in ( p1919 ) , - .prog_clk_3_E_in ( p952 ) , + .prog_clk_2_E_out ( prog_clk_2_wires[26] ) , .prog_clk_3_W_in ( p1990 ) , + .prog_clk_3_E_in ( p906 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6275 ) , - .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6276 ) , .clk_1_W_in ( p1167 ) , - .clk_1_E_in ( p636 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_6277 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6276 ) , .clk_1_W_in ( p1934 ) , + .clk_1_E_in ( p927 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_6277 ) , .clk_1_S_out ( SYNOPSYS_UNCONNECTED_6278 ) , .clk_2_E_in ( SYNOPSYS_UNCONNECTED_6279 ) , .clk_2_W_in ( clk_2_wires[25] ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6280 ) , - .clk_2_E_out ( clk_2_wires[26] ) , .clk_3_W_in ( p1919 ) , - .clk_3_E_in ( p1749 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6281 ) , + .clk_2_E_out ( clk_2_wires[26] ) , .clk_3_W_in ( p1990 ) , + .clk_3_E_in ( p244 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6281 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6282 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; cbx_1__1_ cbx_5__3_ ( .pReset ( { SYNOPSYS_UNCONNECTED_6283 } ) , @@ -145754,7 +149320,7 @@ cbx_1__1_ cbx_5__3_ ( .bottom_grid_pin_14_ ( cbx_1__1__46_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__46_bottom_grid_pin_15_ ) , .ccff_tail ( cbx_1__1__46_ccff_tail ) , .SC_IN_TOP ( scff_Wires[124] ) , - .SC_OUT_BOT ( scff_Wires[125] ) , .SC_IN_BOT ( p1769 ) , + .SC_OUT_BOT ( scff_Wires[125] ) , .SC_IN_BOT ( p1616 ) , .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_6284 ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[46] ) , .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[46] ) , @@ -145769,19 +149335,19 @@ cbx_1__1_ cbx_5__3_ ( .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_6288 ) , .prog_clk_1_E_in ( prog_clk_1_wires[93] ) , .prog_clk_1_N_out ( prog_clk_1_wires[94] ) , - .prog_clk_1_S_out ( prog_clk_1_wires[95] ) , .prog_clk_2_E_in ( p1492 ) , - .prog_clk_2_W_in ( p734 ) , + .prog_clk_1_S_out ( prog_clk_1_wires[95] ) , .prog_clk_2_E_in ( p3015 ) , + .prog_clk_2_W_in ( p3378 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6289 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6290 ) , - .prog_clk_3_W_in ( p2774 ) , .prog_clk_3_E_in ( p592 ) , + .prog_clk_3_W_in ( p3421 ) , .prog_clk_3_E_in ( p2891 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6291 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6292 ) , .clk_1_W_in ( SYNOPSYS_UNCONNECTED_6293 ) , .clk_1_E_in ( clk_1_wires[93] ) , .clk_1_N_out ( clk_1_wires[94] ) , - .clk_1_S_out ( clk_1_wires[95] ) , .clk_2_E_in ( p1492 ) , - .clk_2_W_in ( p2870 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6294 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6295 ) , .clk_3_W_in ( p2995 ) , - .clk_3_E_in ( p1067 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6296 ) , + .clk_1_S_out ( clk_1_wires[95] ) , .clk_2_E_in ( p2526 ) , + .clk_2_W_in ( p3317 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6294 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6295 ) , .clk_3_W_in ( p3336 ) , + .clk_3_E_in ( p2476 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6296 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6297 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; cbx_1__1_ cbx_5__4_ ( .pReset ( { SYNOPSYS_UNCONNECTED_6298 } ) , @@ -145807,7 +149373,7 @@ cbx_1__1_ cbx_5__4_ ( .bottom_grid_pin_14_ ( cbx_1__1__47_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__47_bottom_grid_pin_15_ ) , .ccff_tail ( cbx_1__1__47_ccff_tail ) , .SC_IN_TOP ( scff_Wires[122] ) , - .SC_OUT_BOT ( scff_Wires[123] ) , .SC_IN_BOT ( p1790 ) , + .SC_OUT_BOT ( scff_Wires[123] ) , .SC_IN_BOT ( p1576 ) , .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_6299 ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[47] ) , .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[47] ) , @@ -145819,23 +149385,23 @@ cbx_1__1_ cbx_5__4_ ( .pReset_E_out ( SYNOPSYS_UNCONNECTED_6301 ) , .prog_clk_0_N_in ( prog_clk_0_wires[189] ) , .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6302 ) , - .prog_clk_1_W_in ( p1224 ) , .prog_clk_1_E_in ( p319 ) , + .prog_clk_1_W_in ( p1457 ) , .prog_clk_1_E_in ( p622 ) , .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_6303 ) , .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_6304 ) , .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_6305 ) , .prog_clk_2_W_in ( prog_clk_2_wires[34] ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6306 ) , - .prog_clk_2_E_out ( prog_clk_2_wires[35] ) , .prog_clk_3_W_in ( p1224 ) , - .prog_clk_3_E_in ( p244 ) , + .prog_clk_2_E_out ( prog_clk_2_wires[35] ) , .prog_clk_3_W_in ( p1041 ) , + .prog_clk_3_E_in ( p984 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6307 ) , - .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6308 ) , .clk_1_W_in ( p1528 ) , - .clk_1_E_in ( p1714 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_6309 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6308 ) , .clk_1_W_in ( p1041 ) , + .clk_1_E_in ( p604 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_6309 ) , .clk_1_S_out ( SYNOPSYS_UNCONNECTED_6310 ) , .clk_2_E_in ( SYNOPSYS_UNCONNECTED_6311 ) , .clk_2_W_in ( clk_2_wires[34] ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6312 ) , - .clk_2_E_out ( clk_2_wires[35] ) , .clk_3_W_in ( p1224 ) , - .clk_3_E_in ( p1156 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6313 ) , + .clk_2_E_out ( clk_2_wires[35] ) , .clk_3_W_in ( p1041 ) , + .clk_3_E_in ( p328 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6313 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6314 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; cbx_1__1_ cbx_5__5_ ( .pReset ( { SYNOPSYS_UNCONNECTED_6315 } ) , @@ -145861,7 +149427,7 @@ cbx_1__1_ cbx_5__5_ ( .bottom_grid_pin_14_ ( cbx_1__1__48_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__48_bottom_grid_pin_15_ ) , .ccff_tail ( cbx_1__1__48_ccff_tail ) , .SC_IN_TOP ( scff_Wires[120] ) , - .SC_OUT_BOT ( scff_Wires[121] ) , .SC_IN_BOT ( p1351 ) , + .SC_OUT_BOT ( scff_Wires[121] ) , .SC_IN_BOT ( p1350 ) , .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_6316 ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[48] ) , .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[48] ) , @@ -145876,19 +149442,19 @@ cbx_1__1_ cbx_5__5_ ( .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_6320 ) , .prog_clk_1_E_in ( prog_clk_1_wires[100] ) , .prog_clk_1_N_out ( prog_clk_1_wires[101] ) , - .prog_clk_1_S_out ( prog_clk_1_wires[102] ) , .prog_clk_2_E_in ( p1900 ) , - .prog_clk_2_W_in ( p270 ) , + .prog_clk_1_S_out ( prog_clk_1_wires[102] ) , .prog_clk_2_E_in ( p3397 ) , + .prog_clk_2_W_in ( p1800 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6321 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6322 ) , - .prog_clk_3_W_in ( p2167 ) , .prog_clk_3_E_in ( p1217 ) , + .prog_clk_3_W_in ( p2049 ) , .prog_clk_3_E_in ( p3377 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6323 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6324 ) , .clk_1_W_in ( SYNOPSYS_UNCONNECTED_6325 ) , .clk_1_E_in ( clk_1_wires[100] ) , .clk_1_N_out ( clk_1_wires[101] ) , - .clk_1_S_out ( clk_1_wires[102] ) , .clk_2_E_in ( p1900 ) , - .clk_2_W_in ( p2056 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6326 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6327 ) , .clk_3_W_in ( p1569 ) , - .clk_3_E_in ( p1695 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6328 ) , + .clk_1_S_out ( clk_1_wires[102] ) , .clk_2_E_in ( p2551 ) , + .clk_2_W_in ( p3482 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6326 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6327 ) , .clk_3_W_in ( p3508 ) , + .clk_3_E_in ( p2455 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6328 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6329 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; cbx_1__1_ cbx_5__6_ ( .pReset ( { SYNOPSYS_UNCONNECTED_6330 } ) , @@ -145914,7 +149480,7 @@ cbx_1__1_ cbx_5__6_ ( .bottom_grid_pin_14_ ( cbx_1__1__49_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__49_bottom_grid_pin_15_ ) , .ccff_tail ( cbx_1__1__49_ccff_tail ) , .SC_IN_TOP ( scff_Wires[118] ) , - .SC_OUT_BOT ( scff_Wires[119] ) , .SC_IN_BOT ( p1249 ) , + .SC_OUT_BOT ( scff_Wires[119] ) , .SC_IN_BOT ( p1483 ) , .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_6331 ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[49] ) , .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[49] ) , @@ -145926,19 +149492,19 @@ cbx_1__1_ cbx_5__6_ ( .pReset_E_out ( SYNOPSYS_UNCONNECTED_6333 ) , .prog_clk_0_N_in ( prog_clk_0_wires[195] ) , .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6334 ) , - .prog_clk_1_W_in ( p1354 ) , .prog_clk_1_E_in ( p620 ) , + .prog_clk_1_W_in ( p1342 ) , .prog_clk_1_E_in ( p327 ) , .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_6335 ) , .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_6336 ) , - .prog_clk_2_E_in ( p1393 ) , .prog_clk_2_W_in ( p50 ) , + .prog_clk_2_E_in ( p1843 ) , .prog_clk_2_W_in ( p1766 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6337 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6338 ) , .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_6339 ) , .prog_clk_3_E_in ( prog_clk_3_wires[6] ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6340 ) , - .prog_clk_3_W_out ( prog_clk_3_wires[7] ) , .clk_1_W_in ( p1154 ) , - .clk_1_E_in ( p633 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_6341 ) , - .clk_1_S_out ( SYNOPSYS_UNCONNECTED_6342 ) , .clk_2_E_in ( p1393 ) , - .clk_2_W_in ( p960 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6343 ) , + .prog_clk_3_W_out ( prog_clk_3_wires[7] ) , .clk_1_W_in ( p2000 ) , + .clk_1_E_in ( p734 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_6341 ) , + .clk_1_S_out ( SYNOPSYS_UNCONNECTED_6342 ) , .clk_2_E_in ( p1921 ) , + .clk_2_W_in ( p749 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6343 ) , .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6344 ) , .clk_3_W_in ( SYNOPSYS_UNCONNECTED_6345 ) , .clk_3_E_in ( clk_3_wires[6] ) , @@ -145968,7 +149534,7 @@ cbx_1__1_ cbx_5__7_ ( .bottom_grid_pin_14_ ( cbx_1__1__50_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__50_bottom_grid_pin_15_ ) , .ccff_tail ( cbx_1__1__50_ccff_tail ) , .SC_IN_TOP ( scff_Wires[116] ) , - .SC_OUT_BOT ( scff_Wires[117] ) , .SC_IN_BOT ( p1325 ) , + .SC_OUT_BOT ( scff_Wires[117] ) , .SC_IN_BOT ( p1153 ) , .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_6348 ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[50] ) , .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[50] ) , @@ -145983,19 +149549,19 @@ cbx_1__1_ cbx_5__7_ ( .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_6352 ) , .prog_clk_1_E_in ( prog_clk_1_wires[107] ) , .prog_clk_1_N_out ( prog_clk_1_wires[108] ) , - .prog_clk_1_S_out ( prog_clk_1_wires[109] ) , .prog_clk_2_E_in ( p1811 ) , - .prog_clk_2_W_in ( p1139 ) , + .prog_clk_1_S_out ( prog_clk_1_wires[109] ) , .prog_clk_2_E_in ( p2818 ) , + .prog_clk_2_W_in ( p2666 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6353 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6354 ) , - .prog_clk_3_W_in ( p3329 ) , .prog_clk_3_E_in ( p1055 ) , + .prog_clk_3_W_in ( p2791 ) , .prog_clk_3_E_in ( p2667 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6355 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6356 ) , .clk_1_W_in ( SYNOPSYS_UNCONNECTED_6357 ) , .clk_1_E_in ( clk_1_wires[107] ) , .clk_1_N_out ( clk_1_wires[108] ) , - .clk_1_S_out ( clk_1_wires[109] ) , .clk_2_E_in ( p1811 ) , - .clk_2_W_in ( p3297 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6358 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6359 ) , .clk_3_W_in ( p2120 ) , - .clk_3_E_in ( p1689 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6360 ) , + .clk_1_S_out ( clk_1_wires[109] ) , .clk_2_E_in ( p1609 ) , + .clk_2_W_in ( p2407 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6358 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6359 ) , .clk_3_W_in ( p2618 ) , + .clk_3_E_in ( p268 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6360 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6361 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; cbx_1__1_ cbx_5__8_ ( .pReset ( { SYNOPSYS_UNCONNECTED_6362 } ) , @@ -146021,7 +149587,7 @@ cbx_1__1_ cbx_5__8_ ( .bottom_grid_pin_14_ ( cbx_1__1__51_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__51_bottom_grid_pin_15_ ) , .ccff_tail ( cbx_1__1__51_ccff_tail ) , .SC_IN_TOP ( scff_Wires[114] ) , - .SC_OUT_BOT ( scff_Wires[115] ) , .SC_IN_BOT ( p1200 ) , + .SC_OUT_BOT ( scff_Wires[115] ) , .SC_IN_BOT ( p1586 ) , .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_6363 ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[51] ) , .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[51] ) , @@ -146033,23 +149599,23 @@ cbx_1__1_ cbx_5__8_ ( .pReset_E_out ( SYNOPSYS_UNCONNECTED_6365 ) , .prog_clk_0_N_in ( prog_clk_0_wires[201] ) , .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6366 ) , - .prog_clk_1_W_in ( p1447 ) , .prog_clk_1_E_in ( p2354 ) , + .prog_clk_1_W_in ( p924 ) , .prog_clk_1_E_in ( p533 ) , .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_6367 ) , .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_6368 ) , .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_6369 ) , .prog_clk_2_W_in ( prog_clk_2_wires[47] ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6370 ) , - .prog_clk_2_E_out ( prog_clk_2_wires[48] ) , .prog_clk_3_W_in ( p1447 ) , - .prog_clk_3_E_in ( p1281 ) , + .prog_clk_2_E_out ( prog_clk_2_wires[48] ) , .prog_clk_3_W_in ( p1353 ) , + .prog_clk_3_E_in ( p914 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6371 ) , - .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6372 ) , .clk_1_W_in ( p1365 ) , - .clk_1_E_in ( p237 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_6373 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6372 ) , .clk_1_W_in ( p1353 ) , + .clk_1_E_in ( p911 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_6373 ) , .clk_1_S_out ( SYNOPSYS_UNCONNECTED_6374 ) , .clk_2_E_in ( SYNOPSYS_UNCONNECTED_6375 ) , .clk_2_W_in ( clk_2_wires[47] ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6376 ) , - .clk_2_E_out ( clk_2_wires[48] ) , .clk_3_W_in ( p1447 ) , - .clk_3_E_in ( p2302 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6377 ) , + .clk_2_E_out ( clk_2_wires[48] ) , .clk_3_W_in ( p1353 ) , + .clk_3_E_in ( p369 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6377 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6378 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; cbx_1__1_ cbx_5__9_ ( .pReset ( { SYNOPSYS_UNCONNECTED_6379 } ) , @@ -146075,7 +149641,7 @@ cbx_1__1_ cbx_5__9_ ( .bottom_grid_pin_14_ ( cbx_1__1__52_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__52_bottom_grid_pin_15_ ) , .ccff_tail ( cbx_1__1__52_ccff_tail ) , .SC_IN_TOP ( scff_Wires[112] ) , - .SC_OUT_BOT ( scff_Wires[113] ) , .SC_IN_BOT ( p1519 ) , + .SC_OUT_BOT ( scff_Wires[113] ) , .SC_IN_BOT ( p1358 ) , .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_6380 ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[52] ) , .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[52] ) , @@ -146090,19 +149656,19 @@ cbx_1__1_ cbx_5__9_ ( .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_6384 ) , .prog_clk_1_E_in ( prog_clk_1_wires[114] ) , .prog_clk_1_N_out ( prog_clk_1_wires[115] ) , - .prog_clk_1_S_out ( prog_clk_1_wires[116] ) , .prog_clk_2_E_in ( p1564 ) , - .prog_clk_2_W_in ( p371 ) , + .prog_clk_1_S_out ( prog_clk_1_wires[116] ) , .prog_clk_2_E_in ( p3098 ) , + .prog_clk_2_W_in ( p1103 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6385 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6386 ) , - .prog_clk_3_W_in ( p2105 ) , .prog_clk_3_E_in ( p1202 ) , + .prog_clk_3_W_in ( p1291 ) , .prog_clk_3_E_in ( p3065 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6387 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6388 ) , .clk_1_W_in ( SYNOPSYS_UNCONNECTED_6389 ) , .clk_1_E_in ( clk_1_wires[114] ) , .clk_1_N_out ( clk_1_wires[115] ) , - .clk_1_S_out ( clk_1_wires[116] ) , .clk_2_E_in ( p1564 ) , - .clk_2_W_in ( p2526 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6390 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6391 ) , .clk_3_W_in ( p2711 ) , - .clk_3_E_in ( p396 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6392 ) , + .clk_1_S_out ( clk_1_wires[116] ) , .clk_2_E_in ( p2269 ) , + .clk_2_W_in ( p2401 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6390 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6391 ) , .clk_3_W_in ( p2612 ) , + .clk_3_E_in ( p2166 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6392 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6393 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; cbx_1__1_ cbx_5__10_ ( .pReset ( { SYNOPSYS_UNCONNECTED_6394 } ) , @@ -146128,7 +149694,7 @@ cbx_1__1_ cbx_5__10_ ( .bottom_grid_pin_14_ ( cbx_1__1__53_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__53_bottom_grid_pin_15_ ) , .ccff_tail ( cbx_1__1__53_ccff_tail ) , .SC_IN_TOP ( scff_Wires[110] ) , - .SC_OUT_BOT ( scff_Wires[111] ) , .SC_IN_BOT ( p1062 ) , + .SC_OUT_BOT ( scff_Wires[111] ) , .SC_IN_BOT ( p1967 ) , .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_6395 ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[53] ) , .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[53] ) , @@ -146140,23 +149706,23 @@ cbx_1__1_ cbx_5__10_ ( .pReset_E_out ( SYNOPSYS_UNCONNECTED_6397 ) , .prog_clk_0_N_in ( prog_clk_0_wires[207] ) , .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6398 ) , - .prog_clk_1_W_in ( p2111 ) , .prog_clk_1_E_in ( p632 ) , + .prog_clk_1_W_in ( p1364 ) , .prog_clk_1_E_in ( p1734 ) , .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_6399 ) , .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_6400 ) , .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_6401 ) , .prog_clk_2_W_in ( prog_clk_2_wires[60] ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6402 ) , - .prog_clk_2_E_out ( prog_clk_2_wires[61] ) , .prog_clk_3_W_in ( p2128 ) , - .prog_clk_3_E_in ( p187 ) , + .prog_clk_2_E_out ( prog_clk_2_wires[61] ) , .prog_clk_3_W_in ( p1319 ) , + .prog_clk_3_E_in ( p1094 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6403 ) , - .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6404 ) , .clk_1_W_in ( p1432 ) , - .clk_1_E_in ( p473 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_6405 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6404 ) , .clk_1_W_in ( p1319 ) , + .clk_1_E_in ( p1744 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_6405 ) , .clk_1_S_out ( SYNOPSYS_UNCONNECTED_6406 ) , .clk_2_E_in ( SYNOPSYS_UNCONNECTED_6407 ) , .clk_2_W_in ( clk_2_wires[60] ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6408 ) , - .clk_2_E_out ( clk_2_wires[61] ) , .clk_3_W_in ( p2128 ) , - .clk_3_E_in ( p1278 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6409 ) , + .clk_2_E_out ( clk_2_wires[61] ) , .clk_3_W_in ( p1319 ) , + .clk_3_E_in ( p1767 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6409 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6410 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; cbx_1__1_ cbx_5__11_ ( .pReset ( { SYNOPSYS_UNCONNECTED_6411 } ) , @@ -146182,7 +149748,7 @@ cbx_1__1_ cbx_5__11_ ( .bottom_grid_pin_14_ ( cbx_1__1__54_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__54_bottom_grid_pin_15_ ) , .ccff_tail ( cbx_1__1__54_ccff_tail ) , .SC_IN_TOP ( scff_Wires[108] ) , - .SC_OUT_BOT ( scff_Wires[109] ) , .SC_IN_BOT ( p1436 ) , + .SC_OUT_BOT ( scff_Wires[109] ) , .SC_IN_BOT ( p1289 ) , .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_6412 ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[54] ) , .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[54] ) , @@ -146197,19 +149763,19 @@ cbx_1__1_ cbx_5__11_ ( .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_6416 ) , .prog_clk_1_E_in ( prog_clk_1_wires[121] ) , .prog_clk_1_N_out ( prog_clk_1_wires[122] ) , - .prog_clk_1_S_out ( prog_clk_1_wires[123] ) , .prog_clk_2_E_in ( p2241 ) , - .prog_clk_2_W_in ( p757 ) , + .prog_clk_1_S_out ( prog_clk_1_wires[123] ) , .prog_clk_2_E_in ( p2810 ) , + .prog_clk_2_W_in ( p3446 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6417 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6418 ) , - .prog_clk_3_W_in ( p3201 ) , .prog_clk_3_E_in ( p207 ) , + .prog_clk_3_W_in ( p3457 ) , .prog_clk_3_E_in ( p2736 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6419 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6420 ) , .clk_1_W_in ( SYNOPSYS_UNCONNECTED_6421 ) , .clk_1_E_in ( clk_1_wires[121] ) , .clk_1_N_out ( clk_1_wires[122] ) , - .clk_1_S_out ( clk_1_wires[123] ) , .clk_2_E_in ( p2241 ) , - .clk_2_W_in ( p3116 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6422 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6423 ) , .clk_3_W_in ( p2830 ) , - .clk_3_E_in ( p2020 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6424 ) , + .clk_1_S_out ( clk_1_wires[123] ) , .clk_2_E_in ( p3013 ) , + .clk_2_W_in ( p951 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6422 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6423 ) , .clk_3_W_in ( p1349 ) , + .clk_3_E_in ( p2911 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6424 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6425 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; cbx_1__1_ cbx_6__1_ ( .pReset ( { SYNOPSYS_UNCONNECTED_6426 } ) , @@ -146234,7 +149800,7 @@ cbx_1__1_ cbx_6__1_ ( .bottom_grid_pin_13_ ( cbx_1__1__55_bottom_grid_pin_13_ ) , .bottom_grid_pin_14_ ( cbx_1__1__55_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__55_bottom_grid_pin_15_ ) , - .ccff_tail ( cbx_1__1__55_ccff_tail ) , .SC_IN_TOP ( p1930 ) , + .ccff_tail ( cbx_1__1__55_ccff_tail ) , .SC_IN_TOP ( p1996 ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_6427 ) , .SC_IN_BOT ( scff_Wires[135] ) , .SC_OUT_TOP ( scff_Wires[136] ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[55] ) , @@ -146250,20 +149816,20 @@ cbx_1__1_ cbx_6__1_ ( .prog_clk_1_W_in ( prog_clk_1_wires[85] ) , .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_6431 ) , .prog_clk_1_N_out ( prog_clk_1_wires[89] ) , - .prog_clk_1_S_out ( prog_clk_1_wires[90] ) , .prog_clk_2_E_in ( p1529 ) , - .prog_clk_2_W_in ( p562 ) , + .prog_clk_1_S_out ( prog_clk_1_wires[90] ) , .prog_clk_2_E_in ( p1846 ) , + .prog_clk_2_W_in ( p3211 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6432 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6433 ) , - .prog_clk_3_W_in ( p2215 ) , .prog_clk_3_E_in ( p1644 ) , + .prog_clk_3_W_in ( p3278 ) , .prog_clk_3_E_in ( p1785 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6434 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6435 ) , .clk_1_W_in ( clk_1_wires[85] ) , .clk_1_E_in ( SYNOPSYS_UNCONNECTED_6436 ) , .clk_1_N_out ( clk_1_wires[89] ) , .clk_1_S_out ( clk_1_wires[90] ) , - .clk_2_E_in ( p1529 ) , .clk_2_W_in ( p2910 ) , + .clk_2_E_in ( p2786 ) , .clk_2_W_in ( p2933 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6437 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6438 ) , .clk_3_W_in ( p2939 ) , - .clk_3_E_in ( p79 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6439 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6438 ) , .clk_3_W_in ( p2986 ) , + .clk_3_E_in ( p2664 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6439 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6440 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; cbx_1__1_ cbx_6__2_ ( .pReset ( { SYNOPSYS_UNCONNECTED_6441 } ) , @@ -146288,7 +149854,7 @@ cbx_1__1_ cbx_6__2_ ( .bottom_grid_pin_13_ ( cbx_1__1__56_bottom_grid_pin_13_ ) , .bottom_grid_pin_14_ ( cbx_1__1__56_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__56_bottom_grid_pin_15_ ) , - .ccff_tail ( cbx_1__1__56_ccff_tail ) , .SC_IN_TOP ( p1922 ) , + .ccff_tail ( cbx_1__1__56_ccff_tail ) , .SC_IN_TOP ( p1855 ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_6442 ) , .SC_IN_BOT ( scff_Wires[137] ) , .SC_OUT_TOP ( scff_Wires[138] ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[56] ) , @@ -146301,20 +149867,20 @@ cbx_1__1_ cbx_6__2_ ( .pReset_E_out ( SYNOPSYS_UNCONNECTED_6444 ) , .prog_clk_0_N_in ( prog_clk_0_wires[221] ) , .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6445 ) , - .prog_clk_1_W_in ( p2398 ) , .prog_clk_1_E_in ( p930 ) , + .prog_clk_1_W_in ( p1421 ) , .prog_clk_1_E_in ( p271 ) , .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_6446 ) , .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_6447 ) , - .prog_clk_2_E_in ( p2235 ) , .prog_clk_2_W_in ( p2292 ) , + .prog_clk_2_E_in ( p3030 ) , .prog_clk_2_W_in ( p2895 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6448 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6449 ) , - .prog_clk_3_W_in ( p3108 ) , .prog_clk_3_E_in ( p1726 ) , + .prog_clk_3_W_in ( p3017 ) , .prog_clk_3_E_in ( p2893 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6450 ) , - .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6451 ) , .clk_1_W_in ( p1111 ) , - .clk_1_E_in ( p476 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_6452 ) , - .clk_1_S_out ( SYNOPSYS_UNCONNECTED_6453 ) , .clk_2_E_in ( p2235 ) , - .clk_2_W_in ( p3016 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6454 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6455 ) , .clk_3_W_in ( p2180 ) , - .clk_3_E_in ( p2042 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6456 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6451 ) , .clk_1_W_in ( p1509 ) , + .clk_1_E_in ( p817 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_6452 ) , + .clk_1_S_out ( SYNOPSYS_UNCONNECTED_6453 ) , .clk_2_E_in ( p2333 ) , + .clk_2_W_in ( p2475 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6454 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6455 ) , .clk_3_W_in ( p2636 ) , + .clk_3_E_in ( p2079 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6456 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6457 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; cbx_1__1_ cbx_6__3_ ( .pReset ( { SYNOPSYS_UNCONNECTED_6458 } ) , @@ -146339,7 +149905,7 @@ cbx_1__1_ cbx_6__3_ ( .bottom_grid_pin_13_ ( cbx_1__1__57_bottom_grid_pin_13_ ) , .bottom_grid_pin_14_ ( cbx_1__1__57_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__57_bottom_grid_pin_15_ ) , - .ccff_tail ( cbx_1__1__57_ccff_tail ) , .SC_IN_TOP ( p2626 ) , + .ccff_tail ( cbx_1__1__57_ccff_tail ) , .SC_IN_TOP ( p1443 ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_6459 ) , .SC_IN_BOT ( scff_Wires[139] ) , .SC_OUT_TOP ( scff_Wires[140] ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[57] ) , @@ -146355,20 +149921,20 @@ cbx_1__1_ cbx_6__3_ ( .prog_clk_1_W_in ( prog_clk_1_wires[92] ) , .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_6463 ) , .prog_clk_1_N_out ( prog_clk_1_wires[96] ) , - .prog_clk_1_S_out ( prog_clk_1_wires[97] ) , .prog_clk_2_E_in ( p1865 ) , - .prog_clk_2_W_in ( p698 ) , + .prog_clk_1_S_out ( prog_clk_1_wires[97] ) , .prog_clk_2_E_in ( p2363 ) , + .prog_clk_2_W_in ( p1797 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6464 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6465 ) , - .prog_clk_3_W_in ( p3310 ) , .prog_clk_3_E_in ( p2550 ) , + .prog_clk_3_W_in ( p1923 ) , .prog_clk_3_E_in ( p2134 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6466 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6467 ) , .clk_1_W_in ( clk_1_wires[92] ) , .clk_1_E_in ( SYNOPSYS_UNCONNECTED_6468 ) , .clk_1_N_out ( clk_1_wires[96] ) , .clk_1_S_out ( clk_1_wires[97] ) , - .clk_2_E_in ( p1865 ) , .clk_2_W_in ( p3281 ) , + .clk_2_E_in ( p2299 ) , .clk_2_W_in ( p2394 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6469 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6470 ) , .clk_3_W_in ( p3194 ) , - .clk_3_E_in ( p1736 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6471 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6470 ) , .clk_3_W_in ( p2627 ) , + .clk_3_E_in ( p2175 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6471 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6472 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; cbx_1__1_ cbx_6__4_ ( .pReset ( { SYNOPSYS_UNCONNECTED_6473 } ) , @@ -146393,7 +149959,7 @@ cbx_1__1_ cbx_6__4_ ( .bottom_grid_pin_13_ ( cbx_1__1__58_bottom_grid_pin_13_ ) , .bottom_grid_pin_14_ ( cbx_1__1__58_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__58_bottom_grid_pin_15_ ) , - .ccff_tail ( cbx_1__1__58_ccff_tail ) , .SC_IN_TOP ( p2130 ) , + .ccff_tail ( cbx_1__1__58_ccff_tail ) , .SC_IN_TOP ( p1273 ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_6474 ) , .SC_IN_BOT ( scff_Wires[141] ) , .SC_OUT_TOP ( scff_Wires[142] ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[58] ) , @@ -146406,20 +149972,20 @@ cbx_1__1_ cbx_6__4_ ( .pReset_E_out ( SYNOPSYS_UNCONNECTED_6476 ) , .prog_clk_0_N_in ( prog_clk_0_wires[227] ) , .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6477 ) , - .prog_clk_1_W_in ( p2436 ) , .prog_clk_1_E_in ( p673 ) , + .prog_clk_1_W_in ( p1232 ) , .prog_clk_1_E_in ( p596 ) , .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_6478 ) , .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_6479 ) , - .prog_clk_2_E_in ( p842 ) , .prog_clk_2_W_in ( p2381 ) , + .prog_clk_2_E_in ( p2259 ) , .prog_clk_2_W_in ( p3183 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6480 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6481 ) , - .prog_clk_3_W_in ( p3051 ) , .prog_clk_3_E_in ( p2044 ) , + .prog_clk_3_W_in ( p3231 ) , .prog_clk_3_E_in ( p2084 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6482 ) , - .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6483 ) , .clk_1_W_in ( p1293 ) , - .clk_1_E_in ( p890 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_6484 ) , - .clk_1_S_out ( SYNOPSYS_UNCONNECTED_6485 ) , .clk_2_E_in ( p842 ) , - .clk_2_W_in ( p3008 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6486 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6487 ) , .clk_3_W_in ( p2236 ) , - .clk_3_E_in ( p727 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6488 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6483 ) , .clk_1_W_in ( p1308 ) , + .clk_1_E_in ( p97 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_6484 ) , + .clk_1_S_out ( SYNOPSYS_UNCONNECTED_6485 ) , .clk_2_E_in ( p3171 ) , + .clk_2_W_in ( p3301 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6486 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6487 ) , .clk_3_W_in ( p3343 ) , + .clk_3_E_in ( p3041 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6488 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6489 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; cbx_1__1_ cbx_6__5_ ( .pReset ( { SYNOPSYS_UNCONNECTED_6490 } ) , @@ -146444,7 +150010,7 @@ cbx_1__1_ cbx_6__5_ ( .bottom_grid_pin_13_ ( cbx_1__1__59_bottom_grid_pin_13_ ) , .bottom_grid_pin_14_ ( cbx_1__1__59_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__59_bottom_grid_pin_15_ ) , - .ccff_tail ( cbx_1__1__59_ccff_tail ) , .SC_IN_TOP ( p2413 ) , + .ccff_tail ( cbx_1__1__59_ccff_tail ) , .SC_IN_TOP ( p1559 ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_6491 ) , .SC_IN_BOT ( scff_Wires[143] ) , .SC_OUT_TOP ( scff_Wires[144] ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[59] ) , @@ -146460,20 +150026,20 @@ cbx_1__1_ cbx_6__5_ ( .prog_clk_1_W_in ( prog_clk_1_wires[99] ) , .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_6495 ) , .prog_clk_1_N_out ( prog_clk_1_wires[103] ) , - .prog_clk_1_S_out ( prog_clk_1_wires[104] ) , .prog_clk_2_E_in ( p2675 ) , - .prog_clk_2_W_in ( p939 ) , + .prog_clk_1_S_out ( prog_clk_1_wires[104] ) , .prog_clk_2_E_in ( p1505 ) , + .prog_clk_2_W_in ( p2658 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6496 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6497 ) , - .prog_clk_3_W_in ( p3063 ) , .prog_clk_3_E_in ( p2384 ) , + .prog_clk_3_W_in ( p2750 ) , .prog_clk_3_E_in ( p618 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6498 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6499 ) , .clk_1_W_in ( clk_1_wires[99] ) , .clk_1_E_in ( SYNOPSYS_UNCONNECTED_6500 ) , .clk_1_N_out ( clk_1_wires[103] ) , .clk_1_S_out ( clk_1_wires[104] ) , - .clk_2_E_in ( p2675 ) , .clk_2_W_in ( p3022 ) , + .clk_2_E_in ( p1958 ) , .clk_2_W_in ( p3087 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6501 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6502 ) , .clk_3_W_in ( p2983 ) , - .clk_3_E_in ( p2569 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6503 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6502 ) , .clk_3_W_in ( p3122 ) , + .clk_3_E_in ( p1742 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6503 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6504 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; cbx_1__1_ cbx_6__6_ ( .pReset ( { SYNOPSYS_UNCONNECTED_6505 } ) , @@ -146498,7 +150064,7 @@ cbx_1__1_ cbx_6__6_ ( .bottom_grid_pin_13_ ( cbx_1__1__60_bottom_grid_pin_13_ ) , .bottom_grid_pin_14_ ( cbx_1__1__60_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__60_bottom_grid_pin_15_ ) , - .ccff_tail ( cbx_1__1__60_ccff_tail ) , .SC_IN_TOP ( p1835 ) , + .ccff_tail ( cbx_1__1__60_ccff_tail ) , .SC_IN_TOP ( p2017 ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_6506 ) , .SC_IN_BOT ( scff_Wires[145] ) , .SC_OUT_TOP ( scff_Wires[146] ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[60] ) , @@ -146511,19 +150077,19 @@ cbx_1__1_ cbx_6__6_ ( .pReset_E_out ( SYNOPSYS_UNCONNECTED_6508 ) , .prog_clk_0_N_in ( prog_clk_0_wires[233] ) , .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6509 ) , - .prog_clk_1_W_in ( p1858 ) , .prog_clk_1_E_in ( p677 ) , + .prog_clk_1_W_in ( p1626 ) , .prog_clk_1_E_in ( p499 ) , .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_6510 ) , .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_6511 ) , - .prog_clk_2_E_in ( p1835 ) , .prog_clk_2_W_in ( p1683 ) , + .prog_clk_2_E_in ( p2206 ) , .prog_clk_2_W_in ( p1731 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6512 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6513 ) , .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_6514 ) , .prog_clk_3_E_in ( prog_clk_3_wires[2] ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6515 ) , - .prog_clk_3_W_out ( prog_clk_3_wires[3] ) , .clk_1_W_in ( p1426 ) , - .clk_1_E_in ( p532 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_6516 ) , - .clk_1_S_out ( SYNOPSYS_UNCONNECTED_6517 ) , .clk_2_E_in ( p1835 ) , - .clk_2_W_in ( p1109 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6518 ) , + .prog_clk_3_W_out ( prog_clk_3_wires[3] ) , .clk_1_W_in ( p2030 ) , + .clk_1_E_in ( p200 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_6516 ) , + .clk_1_S_out ( SYNOPSYS_UNCONNECTED_6517 ) , .clk_2_E_in ( p2239 ) , + .clk_2_W_in ( p943 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6518 ) , .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6519 ) , .clk_3_W_in ( SYNOPSYS_UNCONNECTED_6520 ) , .clk_3_E_in ( clk_3_wires[2] ) , @@ -146552,7 +150118,7 @@ cbx_1__1_ cbx_6__7_ ( .bottom_grid_pin_13_ ( cbx_1__1__61_bottom_grid_pin_13_ ) , .bottom_grid_pin_14_ ( cbx_1__1__61_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__61_bottom_grid_pin_15_ ) , - .ccff_tail ( cbx_1__1__61_ccff_tail ) , .SC_IN_TOP ( p2649 ) , + .ccff_tail ( cbx_1__1__61_ccff_tail ) , .SC_IN_TOP ( p2256 ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_6523 ) , .SC_IN_BOT ( scff_Wires[147] ) , .SC_OUT_TOP ( scff_Wires[148] ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[61] ) , @@ -146568,20 +150134,20 @@ cbx_1__1_ cbx_6__7_ ( .prog_clk_1_W_in ( prog_clk_1_wires[106] ) , .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_6527 ) , .prog_clk_1_N_out ( prog_clk_1_wires[110] ) , - .prog_clk_1_S_out ( prog_clk_1_wires[111] ) , .prog_clk_2_E_in ( p1559 ) , - .prog_clk_2_W_in ( p988 ) , + .prog_clk_1_S_out ( prog_clk_1_wires[111] ) , .prog_clk_2_E_in ( p2620 ) , + .prog_clk_2_W_in ( p2444 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6528 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6529 ) , - .prog_clk_3_W_in ( p1954 ) , .prog_clk_3_E_in ( p2535 ) , + .prog_clk_3_W_in ( p2614 ) , .prog_clk_3_E_in ( p2489 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6530 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6531 ) , .clk_1_W_in ( clk_1_wires[106] ) , .clk_1_E_in ( SYNOPSYS_UNCONNECTED_6532 ) , .clk_1_N_out ( clk_1_wires[110] ) , .clk_1_S_out ( clk_1_wires[111] ) , - .clk_2_E_in ( p1559 ) , .clk_2_W_in ( p1628 ) , + .clk_2_E_in ( p2846 ) , .clk_2_W_in ( p2677 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6533 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6534 ) , .clk_3_W_in ( p1341 ) , - .clk_3_E_in ( p549 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6535 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6534 ) , .clk_3_W_in ( p2848 ) , + .clk_3_E_in ( p2726 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6535 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6536 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; cbx_1__1_ cbx_6__8_ ( .pReset ( { SYNOPSYS_UNCONNECTED_6537 } ) , @@ -146606,7 +150172,7 @@ cbx_1__1_ cbx_6__8_ ( .bottom_grid_pin_13_ ( cbx_1__1__62_bottom_grid_pin_13_ ) , .bottom_grid_pin_14_ ( cbx_1__1__62_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__62_bottom_grid_pin_15_ ) , - .ccff_tail ( cbx_1__1__62_ccff_tail ) , .SC_IN_TOP ( p1538 ) , + .ccff_tail ( cbx_1__1__62_ccff_tail ) , .SC_IN_TOP ( p2006 ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_6538 ) , .SC_IN_BOT ( scff_Wires[149] ) , .SC_OUT_TOP ( scff_Wires[150] ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[62] ) , @@ -146619,20 +150185,20 @@ cbx_1__1_ cbx_6__8_ ( .pReset_E_out ( SYNOPSYS_UNCONNECTED_6540 ) , .prog_clk_0_N_in ( prog_clk_0_wires[239] ) , .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6541 ) , - .prog_clk_1_W_in ( p2447 ) , .prog_clk_1_E_in ( p218 ) , + .prog_clk_1_W_in ( p1407 ) , .prog_clk_1_E_in ( p552 ) , .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_6542 ) , .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_6543 ) , - .prog_clk_2_E_in ( p1943 ) , .prog_clk_2_W_in ( p2371 ) , + .prog_clk_2_E_in ( p3329 ) , .prog_clk_2_W_in ( p2700 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6544 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6545 ) , - .prog_clk_3_W_in ( p1619 ) , .prog_clk_3_E_in ( p1041 ) , + .prog_clk_3_W_in ( p2777 ) , .prog_clk_3_E_in ( p3288 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6546 ) , - .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6547 ) , .clk_1_W_in ( p994 ) , - .clk_1_E_in ( p624 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_6548 ) , - .clk_1_S_out ( SYNOPSYS_UNCONNECTED_6549 ) , .clk_2_E_in ( p1943 ) , - .clk_2_W_in ( p2738 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6550 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6551 ) , .clk_3_W_in ( p2781 ) , - .clk_3_E_in ( p1722 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6552 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6547 ) , .clk_1_W_in ( p1550 ) , + .clk_1_E_in ( p697 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_6548 ) , + .clk_1_S_out ( SYNOPSYS_UNCONNECTED_6549 ) , .clk_2_E_in ( p1588 ) , + .clk_2_W_in ( p3185 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6550 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6551 ) , .clk_3_W_in ( p3237 ) , + .clk_3_E_in ( p929 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6552 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6553 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; cbx_1__1_ cbx_6__9_ ( .pReset ( { SYNOPSYS_UNCONNECTED_6554 } ) , @@ -146657,7 +150223,7 @@ cbx_1__1_ cbx_6__9_ ( .bottom_grid_pin_13_ ( cbx_1__1__63_bottom_grid_pin_13_ ) , .bottom_grid_pin_14_ ( cbx_1__1__63_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__63_bottom_grid_pin_15_ ) , - .ccff_tail ( cbx_1__1__63_ccff_tail ) , .SC_IN_TOP ( p2199 ) , + .ccff_tail ( cbx_1__1__63_ccff_tail ) , .SC_IN_TOP ( p1321 ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_6555 ) , .SC_IN_BOT ( scff_Wires[151] ) , .SC_OUT_TOP ( scff_Wires[152] ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[63] ) , @@ -146673,20 +150239,20 @@ cbx_1__1_ cbx_6__9_ ( .prog_clk_1_W_in ( prog_clk_1_wires[113] ) , .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_6559 ) , .prog_clk_1_N_out ( prog_clk_1_wires[117] ) , - .prog_clk_1_S_out ( prog_clk_1_wires[118] ) , .prog_clk_2_E_in ( p2155 ) , - .prog_clk_2_W_in ( p430 ) , + .prog_clk_1_S_out ( prog_clk_1_wires[118] ) , .prog_clk_2_E_in ( p2641 ) , + .prog_clk_2_W_in ( p2717 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6560 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6561 ) , - .prog_clk_3_W_in ( p3312 ) , .prog_clk_3_E_in ( p2078 ) , + .prog_clk_3_W_in ( p2851 ) , .prog_clk_3_E_in ( p2423 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6562 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6563 ) , .clk_1_W_in ( clk_1_wires[113] ) , .clk_1_E_in ( SYNOPSYS_UNCONNECTED_6564 ) , .clk_1_N_out ( clk_1_wires[117] ) , .clk_1_S_out ( clk_1_wires[118] ) , - .clk_2_E_in ( p2155 ) , .clk_2_W_in ( p3280 ) , + .clk_2_E_in ( p2229 ) , .clk_2_W_in ( p3443 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6565 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6566 ) , .clk_3_W_in ( p2251 ) , - .clk_3_E_in ( p2059 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6567 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6566 ) , .clk_3_W_in ( p3459 ) , + .clk_3_E_in ( p2176 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6567 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6568 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; cbx_1__1_ cbx_6__10_ ( .pReset ( { SYNOPSYS_UNCONNECTED_6569 } ) , @@ -146711,7 +150277,7 @@ cbx_1__1_ cbx_6__10_ ( .bottom_grid_pin_13_ ( cbx_1__1__64_bottom_grid_pin_13_ ) , .bottom_grid_pin_14_ ( cbx_1__1__64_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__64_bottom_grid_pin_15_ ) , - .ccff_tail ( cbx_1__1__64_ccff_tail ) , .SC_IN_TOP ( p2219 ) , + .ccff_tail ( cbx_1__1__64_ccff_tail ) , .SC_IN_TOP ( p1380 ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_6570 ) , .SC_IN_BOT ( scff_Wires[153] ) , .SC_OUT_TOP ( scff_Wires[154] ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[64] ) , @@ -146724,20 +150290,20 @@ cbx_1__1_ cbx_6__10_ ( .pReset_E_out ( SYNOPSYS_UNCONNECTED_6572 ) , .prog_clk_0_N_in ( prog_clk_0_wires[245] ) , .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6573 ) , - .prog_clk_1_W_in ( p1815 ) , .prog_clk_1_E_in ( p119 ) , + .prog_clk_1_W_in ( p1530 ) , .prog_clk_1_E_in ( p124 ) , .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_6574 ) , .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_6575 ) , - .prog_clk_2_E_in ( p1405 ) , .prog_clk_2_W_in ( p1743 ) , + .prog_clk_2_E_in ( p2970 ) , .prog_clk_2_W_in ( p1790 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6576 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6577 ) , - .prog_clk_3_W_in ( p2629 ) , .prog_clk_3_E_in ( p2053 ) , + .prog_clk_3_W_in ( p1992 ) , .prog_clk_3_E_in ( p2924 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6578 ) , - .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6579 ) , .clk_1_W_in ( p1483 ) , - .clk_1_E_in ( p665 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_6580 ) , - .clk_1_S_out ( SYNOPSYS_UNCONNECTED_6581 ) , .clk_2_E_in ( p1405 ) , - .clk_2_W_in ( p2572 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6582 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6583 ) , .clk_3_W_in ( p2429 ) , - .clk_3_E_in ( p1021 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6584 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6579 ) , .clk_1_W_in ( p1940 ) , + .clk_1_E_in ( p222 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_6580 ) , + .clk_1_S_out ( SYNOPSYS_UNCONNECTED_6581 ) , .clk_2_E_in ( p1814 ) , + .clk_2_W_in ( p1719 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6582 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6583 ) , .clk_3_W_in ( p1970 ) , + .clk_3_E_in ( p1824 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6584 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6585 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; cbx_1__1_ cbx_6__11_ ( .pReset ( { SYNOPSYS_UNCONNECTED_6586 } ) , @@ -146762,7 +150328,7 @@ cbx_1__1_ cbx_6__11_ ( .bottom_grid_pin_13_ ( cbx_1__1__65_bottom_grid_pin_13_ ) , .bottom_grid_pin_14_ ( cbx_1__1__65_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__65_bottom_grid_pin_15_ ) , - .ccff_tail ( cbx_1__1__65_ccff_tail ) , .SC_IN_TOP ( p2171 ) , + .ccff_tail ( cbx_1__1__65_ccff_tail ) , .SC_IN_TOP ( p2373 ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_6587 ) , .SC_IN_BOT ( scff_Wires[155] ) , .SC_OUT_TOP ( scff_Wires[156] ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[65] ) , @@ -146778,20 +150344,20 @@ cbx_1__1_ cbx_6__11_ ( .prog_clk_1_W_in ( prog_clk_1_wires[120] ) , .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_6591 ) , .prog_clk_1_N_out ( prog_clk_1_wires[124] ) , - .prog_clk_1_S_out ( prog_clk_1_wires[125] ) , .prog_clk_2_E_in ( p2701 ) , - .prog_clk_2_W_in ( p693 ) , + .prog_clk_1_S_out ( prog_clk_1_wires[125] ) , .prog_clk_2_E_in ( p3147 ) , + .prog_clk_2_W_in ( p3297 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6592 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6593 ) , - .prog_clk_3_W_in ( p3104 ) , .prog_clk_3_E_in ( p2014 ) , + .prog_clk_3_W_in ( p3357 ) , .prog_clk_3_E_in ( p3060 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6594 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6595 ) , .clk_1_W_in ( clk_1_wires[120] ) , .clk_1_E_in ( SYNOPSYS_UNCONNECTED_6596 ) , .clk_1_N_out ( clk_1_wires[124] ) , .clk_1_S_out ( clk_1_wires[125] ) , - .clk_2_E_in ( p2701 ) , .clk_2_W_in ( p3042 ) , + .clk_2_E_in ( p3152 ) , .clk_2_W_in ( p2479 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6597 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6598 ) , .clk_3_W_in ( p2618 ) , - .clk_3_E_in ( p2567 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6599 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6598 ) , .clk_3_W_in ( p2527 ) , + .clk_3_E_in ( p3099 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6599 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6600 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; cbx_1__1_ cbx_7__1_ ( .pReset ( { SYNOPSYS_UNCONNECTED_6601 } ) , @@ -146817,7 +150383,7 @@ cbx_1__1_ cbx_7__1_ ( .bottom_grid_pin_14_ ( cbx_1__1__66_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__66_bottom_grid_pin_15_ ) , .ccff_tail ( cbx_1__1__66_ccff_tail ) , .SC_IN_TOP ( scff_Wires[181] ) , - .SC_OUT_BOT ( scff_Wires[182] ) , .SC_IN_BOT ( p2222 ) , + .SC_OUT_BOT ( scff_Wires[182] ) , .SC_IN_BOT ( p1595 ) , .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_6602 ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[66] ) , .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[66] ) , @@ -146832,19 +150398,19 @@ cbx_1__1_ cbx_7__1_ ( .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_6606 ) , .prog_clk_1_E_in ( prog_clk_1_wires[128] ) , .prog_clk_1_N_out ( prog_clk_1_wires[129] ) , - .prog_clk_1_S_out ( prog_clk_1_wires[130] ) , .prog_clk_2_E_in ( p1543 ) , - .prog_clk_2_W_in ( p1051 ) , + .prog_clk_1_S_out ( prog_clk_1_wires[130] ) , .prog_clk_2_E_in ( p3142 ) , + .prog_clk_2_W_in ( p3545 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6607 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6608 ) , - .prog_clk_3_W_in ( p3399 ) , .prog_clk_3_E_in ( p585 ) , + .prog_clk_3_W_in ( p3558 ) , .prog_clk_3_E_in ( p3092 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6609 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6610 ) , .clk_1_W_in ( SYNOPSYS_UNCONNECTED_6611 ) , .clk_1_E_in ( clk_1_wires[128] ) , .clk_1_N_out ( clk_1_wires[129] ) , - .clk_1_S_out ( clk_1_wires[130] ) , .clk_2_E_in ( p1543 ) , - .clk_2_W_in ( p3386 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6612 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6613 ) , .clk_3_W_in ( p3076 ) , - .clk_3_E_in ( p27 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6614 ) , + .clk_1_S_out ( clk_1_wires[130] ) , .clk_2_E_in ( p2293 ) , + .clk_2_W_in ( p2470 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6612 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6613 ) , .clk_3_W_in ( p2519 ) , + .clk_3_E_in ( p2078 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6614 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6615 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; cbx_1__1_ cbx_7__2_ ( .pReset ( { SYNOPSYS_UNCONNECTED_6616 } ) , @@ -146870,7 +150436,7 @@ cbx_1__1_ cbx_7__2_ ( .bottom_grid_pin_14_ ( cbx_1__1__67_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__67_bottom_grid_pin_15_ ) , .ccff_tail ( cbx_1__1__67_ccff_tail ) , .SC_IN_TOP ( scff_Wires[179] ) , - .SC_OUT_BOT ( scff_Wires[180] ) , .SC_IN_BOT ( p2129 ) , + .SC_OUT_BOT ( scff_Wires[180] ) , .SC_IN_BOT ( p2203 ) , .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_6617 ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[67] ) , .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[67] ) , @@ -146882,20 +150448,20 @@ cbx_1__1_ cbx_7__2_ ( .pReset_S_out ( pResetWires[137] ) , .pReset_E_out ( pResetWires[136] ) , .prog_clk_0_N_in ( prog_clk_0_wires[259] ) , .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6620 ) , - .prog_clk_1_W_in ( p1243 ) , .prog_clk_1_E_in ( p1621 ) , + .prog_clk_1_W_in ( p1440 ) , .prog_clk_1_E_in ( p2080 ) , .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_6621 ) , .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_6622 ) , - .prog_clk_2_E_in ( p2454 ) , .prog_clk_2_W_in ( p1157 ) , + .prog_clk_2_E_in ( p2530 ) , .prog_clk_2_W_in ( p3071 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6623 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6624 ) , - .prog_clk_3_W_in ( p2697 ) , .prog_clk_3_E_in ( p134 ) , + .prog_clk_3_W_in ( p3138 ) , .prog_clk_3_E_in ( p2481 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6625 ) , - .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6626 ) , .clk_1_W_in ( p1609 ) , - .clk_1_E_in ( p2000 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_6627 ) , - .clk_1_S_out ( SYNOPSYS_UNCONNECTED_6628 ) , .clk_2_E_in ( p2454 ) , - .clk_2_W_in ( p2742 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6629 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6630 ) , .clk_3_W_in ( p2862 ) , - .clk_3_E_in ( p2271 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6631 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6626 ) , .clk_1_W_in ( p1653 ) , + .clk_1_E_in ( p148 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_6627 ) , + .clk_1_S_out ( SYNOPSYS_UNCONNECTED_6628 ) , .clk_2_E_in ( p2854 ) , + .clk_2_W_in ( p2873 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6629 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6630 ) , .clk_3_W_in ( p2984 ) , + .clk_3_E_in ( p2681 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6631 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6632 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; cbx_1__1_ cbx_7__3_ ( .pReset ( { SYNOPSYS_UNCONNECTED_6633 } ) , @@ -146921,7 +150487,7 @@ cbx_1__1_ cbx_7__3_ ( .bottom_grid_pin_14_ ( cbx_1__1__68_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__68_bottom_grid_pin_15_ ) , .ccff_tail ( cbx_1__1__68_ccff_tail ) , .SC_IN_TOP ( scff_Wires[177] ) , - .SC_OUT_BOT ( scff_Wires[178] ) , .SC_IN_BOT ( p1261 ) , + .SC_OUT_BOT ( scff_Wires[178] ) , .SC_IN_BOT ( p1207 ) , .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_6634 ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[68] ) , .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[68] ) , @@ -146936,19 +150502,19 @@ cbx_1__1_ cbx_7__3_ ( .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_6638 ) , .prog_clk_1_E_in ( prog_clk_1_wires[135] ) , .prog_clk_1_N_out ( prog_clk_1_wires[136] ) , - .prog_clk_1_S_out ( prog_clk_1_wires[137] ) , .prog_clk_2_E_in ( p2218 ) , - .prog_clk_2_W_in ( p564 ) , + .prog_clk_1_S_out ( prog_clk_1_wires[137] ) , .prog_clk_2_E_in ( p2770 ) , + .prog_clk_2_W_in ( p3291 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6639 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6640 ) , - .prog_clk_3_W_in ( p3166 ) , .prog_clk_3_E_in ( p1171 ) , + .prog_clk_3_W_in ( p3335 ) , .prog_clk_3_E_in ( p2706 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6641 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6642 ) , .clk_1_W_in ( SYNOPSYS_UNCONNECTED_6643 ) , .clk_1_E_in ( clk_1_wires[135] ) , .clk_1_N_out ( clk_1_wires[136] ) , - .clk_1_S_out ( clk_1_wires[137] ) , .clk_2_E_in ( p2218 ) , - .clk_2_W_in ( p3142 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6644 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6645 ) , .clk_3_W_in ( p2973 ) , - .clk_3_E_in ( p2079 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6646 ) , + .clk_1_S_out ( clk_1_wires[137] ) , .clk_2_E_in ( p2294 ) , + .clk_2_W_in ( p2456 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6644 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6645 ) , .clk_3_W_in ( p2491 ) , + .clk_3_E_in ( p2096 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6646 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6647 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; cbx_1__1_ cbx_7__4_ ( .pReset ( { SYNOPSYS_UNCONNECTED_6648 } ) , @@ -146974,7 +150540,7 @@ cbx_1__1_ cbx_7__4_ ( .bottom_grid_pin_14_ ( cbx_1__1__69_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__69_bottom_grid_pin_15_ ) , .ccff_tail ( cbx_1__1__69_ccff_tail ) , .SC_IN_TOP ( scff_Wires[175] ) , - .SC_OUT_BOT ( scff_Wires[176] ) , .SC_IN_BOT ( p1814 ) , + .SC_OUT_BOT ( scff_Wires[176] ) , .SC_IN_BOT ( p1614 ) , .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_6649 ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[69] ) , .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[69] ) , @@ -146986,20 +150552,20 @@ cbx_1__1_ cbx_7__4_ ( .pReset_S_out ( pResetWires[235] ) , .pReset_E_out ( pResetWires[234] ) , .prog_clk_0_N_in ( prog_clk_0_wires[265] ) , .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6652 ) , - .prog_clk_1_W_in ( p2159 ) , .prog_clk_1_E_in ( p1709 ) , + .prog_clk_1_W_in ( p1571 ) , .prog_clk_1_E_in ( p425 ) , .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_6653 ) , .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_6654 ) , - .prog_clk_2_E_in ( p2245 ) , .prog_clk_2_W_in ( p2075 ) , + .prog_clk_2_E_in ( p3229 ) , .prog_clk_2_W_in ( p3439 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6655 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6656 ) , - .prog_clk_3_W_in ( p3253 ) , .prog_clk_3_E_in ( p1178 ) , + .prog_clk_3_W_in ( p3462 ) , .prog_clk_3_E_in ( p3205 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6657 ) , - .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6658 ) , .clk_1_W_in ( p1540 ) , - .clk_1_E_in ( p1700 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_6659 ) , - .clk_1_S_out ( SYNOPSYS_UNCONNECTED_6660 ) , .clk_2_E_in ( p2216 ) , - .clk_2_W_in ( p3233 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6661 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6662 ) , .clk_3_W_in ( p2243 ) , - .clk_3_E_in ( p2027 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6663 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6658 ) , .clk_1_W_in ( p1285 ) , + .clk_1_E_in ( p2066 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_6659 ) , + .clk_1_S_out ( SYNOPSYS_UNCONNECTED_6660 ) , .clk_2_E_in ( p2508 ) , + .clk_2_W_in ( p2874 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6661 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6662 ) , .clk_3_W_in ( p2971 ) , + .clk_3_E_in ( p2375 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6663 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6664 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; cbx_1__1_ cbx_7__5_ ( .pReset ( { SYNOPSYS_UNCONNECTED_6665 } ) , @@ -147025,7 +150591,7 @@ cbx_1__1_ cbx_7__5_ ( .bottom_grid_pin_14_ ( cbx_1__1__70_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__70_bottom_grid_pin_15_ ) , .ccff_tail ( cbx_1__1__70_ccff_tail ) , .SC_IN_TOP ( scff_Wires[173] ) , - .SC_OUT_BOT ( scff_Wires[174] ) , .SC_IN_BOT ( p1854 ) , + .SC_OUT_BOT ( scff_Wires[174] ) , .SC_IN_BOT ( p1897 ) , .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_6666 ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[70] ) , .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[70] ) , @@ -147040,19 +150606,19 @@ cbx_1__1_ cbx_7__5_ ( .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_6670 ) , .prog_clk_1_E_in ( prog_clk_1_wires[142] ) , .prog_clk_1_N_out ( prog_clk_1_wires[143] ) , - .prog_clk_1_S_out ( prog_clk_1_wires[144] ) , .prog_clk_2_E_in ( p1823 ) , - .prog_clk_2_W_in ( p194 ) , + .prog_clk_1_S_out ( prog_clk_1_wires[144] ) , .prog_clk_2_E_in ( p2991 ) , + .prog_clk_2_W_in ( p1745 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6671 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6672 ) , - .prog_clk_3_W_in ( p3328 ) , .prog_clk_3_E_in ( p467 ) , + .prog_clk_3_W_in ( p1847 ) , .prog_clk_3_E_in ( p2858 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6673 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6674 ) , .clk_1_W_in ( SYNOPSYS_UNCONNECTED_6675 ) , .clk_1_E_in ( clk_1_wires[142] ) , .clk_1_N_out ( clk_1_wires[143] ) , - .clk_1_S_out ( clk_1_wires[144] ) , .clk_2_E_in ( p1823 ) , - .clk_2_W_in ( p3298 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6676 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6677 ) , .clk_3_W_in ( p2790 ) , - .clk_3_E_in ( p1701 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6678 ) , + .clk_1_S_out ( clk_1_wires[144] ) , .clk_2_E_in ( p2536 ) , + .clk_2_W_in ( p3053 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6676 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6677 ) , .clk_3_W_in ( p3168 ) , + .clk_3_E_in ( p2453 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6678 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6679 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; cbx_1__1_ cbx_7__6_ ( .pReset ( { SYNOPSYS_UNCONNECTED_6680 } ) , @@ -147078,7 +150644,7 @@ cbx_1__1_ cbx_7__6_ ( .bottom_grid_pin_14_ ( cbx_1__1__71_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__71_bottom_grid_pin_15_ ) , .ccff_tail ( cbx_1__1__71_ccff_tail ) , .SC_IN_TOP ( scff_Wires[171] ) , - .SC_OUT_BOT ( scff_Wires[172] ) , .SC_IN_BOT ( p1902 ) , + .SC_OUT_BOT ( scff_Wires[172] ) , .SC_IN_BOT ( p720 ) , .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_6681 ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[71] ) , .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[71] ) , @@ -147090,19 +150656,19 @@ cbx_1__1_ cbx_7__6_ ( .pReset_S_out ( pResetWires[333] ) , .pReset_E_out ( pResetWires[332] ) , .prog_clk_0_N_in ( prog_clk_0_wires[271] ) , .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6684 ) , - .prog_clk_1_W_in ( p2636 ) , .prog_clk_1_E_in ( p404 ) , + .prog_clk_1_W_in ( p1300 ) , .prog_clk_1_E_in ( p402 ) , .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_6685 ) , .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_6686 ) , - .prog_clk_2_E_in ( p1348 ) , .prog_clk_2_W_in ( p2585 ) , + .prog_clk_2_E_in ( p1422 ) , .prog_clk_2_W_in ( p2127 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6687 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6688 ) , .prog_clk_3_W_in ( prog_clk_3_wires[0] ) , .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_6689 ) , .prog_clk_3_E_out ( prog_clk_3_wires[1] ) , - .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6690 ) , .clk_1_W_in ( p1439 ) , - .clk_1_E_in ( p1678 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_6691 ) , - .clk_1_S_out ( SYNOPSYS_UNCONNECTED_6692 ) , .clk_2_E_in ( p1348 ) , - .clk_2_W_in ( p329 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6693 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6690 ) , .clk_1_W_in ( p2358 ) , + .clk_1_E_in ( p199 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_6691 ) , + .clk_1_S_out ( SYNOPSYS_UNCONNECTED_6692 ) , .clk_2_E_in ( p1422 ) , + .clk_2_W_in ( p675 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6693 ) , .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6694 ) , .clk_3_W_in ( clk_3_wires[0] ) , .clk_3_E_in ( SYNOPSYS_UNCONNECTED_6695 ) , @@ -147132,7 +150698,7 @@ cbx_1__1_ cbx_7__7_ ( .bottom_grid_pin_14_ ( cbx_1__1__72_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__72_bottom_grid_pin_15_ ) , .ccff_tail ( cbx_1__1__72_ccff_tail ) , .SC_IN_TOP ( scff_Wires[169] ) , - .SC_OUT_BOT ( scff_Wires[170] ) , .SC_IN_BOT ( p1283 ) , + .SC_OUT_BOT ( scff_Wires[170] ) , .SC_IN_BOT ( p920 ) , .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_6698 ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[72] ) , .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[72] ) , @@ -147147,19 +150713,19 @@ cbx_1__1_ cbx_7__7_ ( .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_6702 ) , .prog_clk_1_E_in ( prog_clk_1_wires[149] ) , .prog_clk_1_N_out ( prog_clk_1_wires[150] ) , - .prog_clk_1_S_out ( prog_clk_1_wires[151] ) , .prog_clk_2_E_in ( p1522 ) , - .prog_clk_2_W_in ( p480 ) , + .prog_clk_1_S_out ( prog_clk_1_wires[151] ) , .prog_clk_2_E_in ( p2340 ) , + .prog_clk_2_W_in ( p2701 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6703 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6704 ) , - .prog_clk_3_W_in ( p3448 ) , .prog_clk_3_E_in ( p914 ) , + .prog_clk_3_W_in ( p2751 ) , .prog_clk_3_E_in ( p2125 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6705 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6706 ) , .clk_1_W_in ( SYNOPSYS_UNCONNECTED_6707 ) , .clk_1_E_in ( clk_1_wires[149] ) , .clk_1_N_out ( clk_1_wires[150] ) , - .clk_1_S_out ( clk_1_wires[151] ) , .clk_2_E_in ( p1522 ) , - .clk_2_W_in ( p3438 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6708 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6709 ) , .clk_3_W_in ( p2980 ) , - .clk_3_E_in ( p608 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6710 ) , + .clk_1_S_out ( clk_1_wires[151] ) , .clk_2_E_in ( p2309 ) , + .clk_2_W_in ( p2163 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6708 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6709 ) , .clk_3_W_in ( p2336 ) , + .clk_3_E_in ( p2140 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6710 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6711 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; cbx_1__1_ cbx_7__8_ ( .pReset ( { SYNOPSYS_UNCONNECTED_6712 } ) , @@ -147185,7 +150751,7 @@ cbx_1__1_ cbx_7__8_ ( .bottom_grid_pin_14_ ( cbx_1__1__73_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__73_bottom_grid_pin_15_ ) , .ccff_tail ( cbx_1__1__73_ccff_tail ) , .SC_IN_TOP ( scff_Wires[167] ) , - .SC_OUT_BOT ( scff_Wires[168] ) , .SC_IN_BOT ( p2198 ) , + .SC_OUT_BOT ( scff_Wires[168] ) , .SC_IN_BOT ( p2039 ) , .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_6713 ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[73] ) , .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[73] ) , @@ -147197,20 +150763,20 @@ cbx_1__1_ cbx_7__8_ ( .pReset_S_out ( pResetWires[431] ) , .pReset_E_out ( pResetWires[430] ) , .prog_clk_0_N_in ( prog_clk_0_wires[277] ) , .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6716 ) , - .prog_clk_1_W_in ( p2485 ) , .prog_clk_1_E_in ( p2051 ) , + .prog_clk_1_W_in ( p1394 ) , .prog_clk_1_E_in ( p1684 ) , .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_6717 ) , .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_6718 ) , - .prog_clk_2_E_in ( p2126 ) , .prog_clk_2_W_in ( p2361 ) , + .prog_clk_2_E_in ( p2976 ) , .prog_clk_2_W_in ( p2090 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6719 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6720 ) , - .prog_clk_3_W_in ( p3362 ) , .prog_clk_3_E_in ( p1244 ) , + .prog_clk_3_W_in ( p2194 ) , .prog_clk_3_E_in ( p2907 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6721 ) , - .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6722 ) , .clk_1_W_in ( p1513 ) , - .clk_1_E_in ( p1982 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_6723 ) , - .clk_1_S_out ( SYNOPSYS_UNCONNECTED_6724 ) , .clk_2_E_in ( p2126 ) , - .clk_2_W_in ( p3341 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6725 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6726 ) , .clk_3_W_in ( p2470 ) , - .clk_3_E_in ( p2007 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6727 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6722 ) , .clk_1_W_in ( p2350 ) , + .clk_1_E_in ( p406 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_6723 ) , + .clk_1_S_out ( SYNOPSYS_UNCONNECTED_6724 ) , .clk_2_E_in ( p2238 ) , + .clk_2_W_in ( p2438 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6725 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6726 ) , .clk_3_W_in ( p2589 ) , + .clk_3_E_in ( p2132 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6727 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6728 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; cbx_1__1_ cbx_7__9_ ( .pReset ( { SYNOPSYS_UNCONNECTED_6729 } ) , @@ -147236,7 +150802,7 @@ cbx_1__1_ cbx_7__9_ ( .bottom_grid_pin_14_ ( cbx_1__1__74_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__74_bottom_grid_pin_15_ ) , .ccff_tail ( cbx_1__1__74_ccff_tail ) , .SC_IN_TOP ( scff_Wires[165] ) , - .SC_OUT_BOT ( scff_Wires[166] ) , .SC_IN_BOT ( p1402 ) , + .SC_OUT_BOT ( scff_Wires[166] ) , .SC_IN_BOT ( p1579 ) , .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_6730 ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[74] ) , .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[74] ) , @@ -147251,19 +150817,19 @@ cbx_1__1_ cbx_7__9_ ( .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_6734 ) , .prog_clk_1_E_in ( prog_clk_1_wires[156] ) , .prog_clk_1_N_out ( prog_clk_1_wires[157] ) , - .prog_clk_1_S_out ( prog_clk_1_wires[158] ) , .prog_clk_2_E_in ( p1488 ) , - .prog_clk_2_W_in ( p1105 ) , + .prog_clk_1_S_out ( prog_clk_1_wires[158] ) , .prog_clk_2_E_in ( p3233 ) , + .prog_clk_2_W_in ( p3057 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6735 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6736 ) , - .prog_clk_3_W_in ( p3096 ) , .prog_clk_3_E_in ( p976 ) , + .prog_clk_3_W_in ( p3119 ) , .prog_clk_3_E_in ( p3213 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6737 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6738 ) , .clk_1_W_in ( SYNOPSYS_UNCONNECTED_6739 ) , .clk_1_E_in ( clk_1_wires[156] ) , .clk_1_N_out ( clk_1_wires[157] ) , - .clk_1_S_out ( clk_1_wires[158] ) , .clk_2_E_in ( p1488 ) , - .clk_2_W_in ( p3027 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6740 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6741 ) , .clk_3_W_in ( p3066 ) , - .clk_3_E_in ( p627 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6742 ) , + .clk_1_S_out ( clk_1_wires[158] ) , .clk_2_E_in ( p2214 ) , + .clk_2_W_in ( p2473 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6740 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6741 ) , .clk_3_W_in ( p2537 ) , + .clk_3_E_in ( p2158 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6742 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6743 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; cbx_1__1_ cbx_7__10_ ( .pReset ( { SYNOPSYS_UNCONNECTED_6744 } ) , @@ -147289,7 +150855,7 @@ cbx_1__1_ cbx_7__10_ ( .bottom_grid_pin_14_ ( cbx_1__1__75_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__75_bottom_grid_pin_15_ ) , .ccff_tail ( cbx_1__1__75_ccff_tail ) , .SC_IN_TOP ( scff_Wires[163] ) , - .SC_OUT_BOT ( scff_Wires[164] ) , .SC_IN_BOT ( p1227 ) , + .SC_OUT_BOT ( scff_Wires[164] ) , .SC_IN_BOT ( p1534 ) , .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_6745 ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[75] ) , .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[75] ) , @@ -147301,20 +150867,20 @@ cbx_1__1_ cbx_7__10_ ( .pReset_S_out ( pResetWires[529] ) , .pReset_E_out ( pResetWires[528] ) , .prog_clk_0_N_in ( prog_clk_0_wires[283] ) , .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6748 ) , - .prog_clk_1_W_in ( p2483 ) , .prog_clk_1_E_in ( p614 ) , + .prog_clk_1_W_in ( p1369 ) , .prog_clk_1_E_in ( p471 ) , .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_6749 ) , .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_6750 ) , - .prog_clk_2_E_in ( p1464 ) , .prog_clk_2_W_in ( p2315 ) , + .prog_clk_2_E_in ( p2988 ) , .prog_clk_2_W_in ( p3050 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6751 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6752 ) , - .prog_clk_3_W_in ( p2956 ) , .prog_clk_3_E_in ( p1172 ) , + .prog_clk_3_W_in ( p2052 ) , .prog_clk_3_E_in ( p2909 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6753 ) , - .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6754 ) , .clk_1_W_in ( p1798 ) , - .clk_1_E_in ( p160 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_6755 ) , - .clk_1_S_out ( SYNOPSYS_UNCONNECTED_6756 ) , .clk_2_E_in ( p1464 ) , - .clk_2_W_in ( p2885 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6757 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6758 ) , .clk_3_W_in ( p2399 ) , - .clk_3_E_in ( p185 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6759 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6754 ) , .clk_1_W_in ( p3100 ) , + .clk_1_E_in ( p563 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_6755 ) , + .clk_1_S_out ( SYNOPSYS_UNCONNECTED_6756 ) , .clk_2_E_in ( p2273 ) , + .clk_2_W_in ( p3214 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6757 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6758 ) , .clk_3_W_in ( p3236 ) , + .clk_3_E_in ( p2137 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6759 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6760 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; cbx_1__1_ cbx_7__11_ ( .pReset ( { SYNOPSYS_UNCONNECTED_6761 } ) , @@ -147340,7 +150906,7 @@ cbx_1__1_ cbx_7__11_ ( .bottom_grid_pin_14_ ( cbx_1__1__76_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__76_bottom_grid_pin_15_ ) , .ccff_tail ( cbx_1__1__76_ccff_tail ) , .SC_IN_TOP ( scff_Wires[161] ) , - .SC_OUT_BOT ( scff_Wires[162] ) , .SC_IN_BOT ( p1608 ) , + .SC_OUT_BOT ( scff_Wires[162] ) , .SC_IN_BOT ( p1183 ) , .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_6762 ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[76] ) , .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[76] ) , @@ -147355,19 +150921,19 @@ cbx_1__1_ cbx_7__11_ ( .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_6766 ) , .prog_clk_1_E_in ( prog_clk_1_wires[163] ) , .prog_clk_1_N_out ( prog_clk_1_wires[164] ) , - .prog_clk_1_S_out ( prog_clk_1_wires[165] ) , .prog_clk_2_E_in ( p2453 ) , - .prog_clk_2_W_in ( p1029 ) , + .prog_clk_1_S_out ( prog_clk_1_wires[165] ) , .prog_clk_2_E_in ( p2803 ) , + .prog_clk_2_W_in ( p3309 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6767 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6768 ) , - .prog_clk_3_W_in ( p3306 ) , .prog_clk_3_E_in ( p1158 ) , + .prog_clk_3_W_in ( p3326 ) , .prog_clk_3_E_in ( p2688 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6769 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6770 ) , .clk_1_W_in ( SYNOPSYS_UNCONNECTED_6771 ) , .clk_1_E_in ( clk_1_wires[163] ) , .clk_1_N_out ( clk_1_wires[164] ) , - .clk_1_S_out ( clk_1_wires[165] ) , .clk_2_E_in ( p2453 ) , - .clk_2_W_in ( p3278 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6772 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6773 ) , .clk_3_W_in ( p2616 ) , - .clk_3_E_in ( p2373 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6774 ) , + .clk_1_S_out ( clk_1_wires[165] ) , .clk_2_E_in ( p2342 ) , + .clk_2_W_in ( p2454 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6772 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6773 ) , .clk_3_W_in ( p2566 ) , + .clk_3_E_in ( p2187 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6774 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6775 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; cbx_1__1_ cbx_8__1_ ( .pReset ( { SYNOPSYS_UNCONNECTED_6776 } ) , @@ -147392,7 +150958,7 @@ cbx_1__1_ cbx_8__1_ ( .bottom_grid_pin_13_ ( cbx_1__1__77_bottom_grid_pin_13_ ) , .bottom_grid_pin_14_ ( cbx_1__1__77_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__77_bottom_grid_pin_15_ ) , - .ccff_tail ( cbx_1__1__77_ccff_tail ) , .SC_IN_TOP ( p1879 ) , + .ccff_tail ( cbx_1__1__77_ccff_tail ) , .SC_IN_TOP ( p1583 ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_6777 ) , .SC_IN_BOT ( scff_Wires[188] ) , .SC_OUT_TOP ( scff_Wires[189] ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[77] ) , @@ -147408,20 +150974,20 @@ cbx_1__1_ cbx_8__1_ ( .prog_clk_1_W_in ( prog_clk_1_wires[127] ) , .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_6781 ) , .prog_clk_1_N_out ( prog_clk_1_wires[131] ) , - .prog_clk_1_S_out ( prog_clk_1_wires[132] ) , .prog_clk_2_E_in ( p1424 ) , - .prog_clk_2_W_in ( p1230 ) , + .prog_clk_1_S_out ( prog_clk_1_wires[132] ) , .prog_clk_2_E_in ( p2964 ) , + .prog_clk_2_W_in ( p2183 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6782 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6783 ) , - .prog_clk_3_W_in ( p670 ) , .prog_clk_3_E_in ( p1667 ) , + .prog_clk_3_W_in ( p2232 ) , .prog_clk_3_E_in ( p2878 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6784 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6785 ) , .clk_1_W_in ( clk_1_wires[127] ) , .clk_1_E_in ( SYNOPSYS_UNCONNECTED_6786 ) , .clk_1_N_out ( clk_1_wires[131] ) , .clk_1_S_out ( clk_1_wires[132] ) , - .clk_2_E_in ( p1424 ) , .clk_2_W_in ( p2582 ) , + .clk_2_E_in ( p2778 ) , .clk_2_W_in ( p3303 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6787 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6788 ) , .clk_3_W_in ( p2678 ) , - .clk_3_E_in ( p193 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6789 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6788 ) , .clk_3_W_in ( p3330 ) , + .clk_3_E_in ( p2680 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6789 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6790 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; cbx_1__1_ cbx_8__2_ ( .pReset ( { SYNOPSYS_UNCONNECTED_6791 } ) , @@ -147446,7 +151012,7 @@ cbx_1__1_ cbx_8__2_ ( .bottom_grid_pin_13_ ( cbx_1__1__78_bottom_grid_pin_13_ ) , .bottom_grid_pin_14_ ( cbx_1__1__78_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__78_bottom_grid_pin_15_ ) , - .ccff_tail ( cbx_1__1__78_ccff_tail ) , .SC_IN_TOP ( p1928 ) , + .ccff_tail ( cbx_1__1__78_ccff_tail ) , .SC_IN_TOP ( p1517 ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_6792 ) , .SC_IN_BOT ( scff_Wires[190] ) , .SC_OUT_TOP ( scff_Wires[191] ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[78] ) , @@ -147459,23 +151025,23 @@ cbx_1__1_ cbx_8__2_ ( .pReset_S_out ( pResetWires[141] ) , .pReset_E_out ( pResetWires[140] ) , .prog_clk_0_N_in ( prog_clk_0_wires[297] ) , .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6795 ) , - .prog_clk_1_W_in ( p1121 ) , .prog_clk_1_E_in ( p2025 ) , + .prog_clk_1_W_in ( p1060 ) , .prog_clk_1_E_in ( p204 ) , .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_6796 ) , .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_6797 ) , .prog_clk_2_E_in ( prog_clk_2_wires[71] ) , .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_6798 ) , .prog_clk_2_W_out ( prog_clk_2_wires[72] ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6799 ) , - .prog_clk_3_W_in ( p1121 ) , .prog_clk_3_E_in ( p1679 ) , + .prog_clk_3_W_in ( p1562 ) , .prog_clk_3_E_in ( p936 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6800 ) , - .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6801 ) , .clk_1_W_in ( p1121 ) , - .clk_1_E_in ( p98 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_6802 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6801 ) , .clk_1_W_in ( p1452 ) , + .clk_1_E_in ( p1671 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_6802 ) , .clk_1_S_out ( SYNOPSYS_UNCONNECTED_6803 ) , .clk_2_E_in ( clk_2_wires[71] ) , .clk_2_W_in ( SYNOPSYS_UNCONNECTED_6804 ) , .clk_2_W_out ( clk_2_wires[72] ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6805 ) , .clk_3_W_in ( p2230 ) , - .clk_3_E_in ( p2022 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6806 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6805 ) , .clk_3_W_in ( p1562 ) , + .clk_3_E_in ( p1793 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6806 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6807 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; cbx_1__1_ cbx_8__3_ ( .pReset ( { SYNOPSYS_UNCONNECTED_6808 } ) , @@ -147500,7 +151066,7 @@ cbx_1__1_ cbx_8__3_ ( .bottom_grid_pin_13_ ( cbx_1__1__79_bottom_grid_pin_13_ ) , .bottom_grid_pin_14_ ( cbx_1__1__79_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__79_bottom_grid_pin_15_ ) , - .ccff_tail ( cbx_1__1__79_ccff_tail ) , .SC_IN_TOP ( p2378 ) , + .ccff_tail ( cbx_1__1__79_ccff_tail ) , .SC_IN_TOP ( p1922 ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_6809 ) , .SC_IN_BOT ( scff_Wires[192] ) , .SC_OUT_TOP ( scff_Wires[193] ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[79] ) , @@ -147516,20 +151082,20 @@ cbx_1__1_ cbx_8__3_ ( .prog_clk_1_W_in ( prog_clk_1_wires[134] ) , .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_6813 ) , .prog_clk_1_N_out ( prog_clk_1_wires[138] ) , - .prog_clk_1_S_out ( prog_clk_1_wires[139] ) , .prog_clk_2_E_in ( p1235 ) , - .prog_clk_2_W_in ( p648 ) , + .prog_clk_1_S_out ( prog_clk_1_wires[139] ) , .prog_clk_2_E_in ( p2514 ) , + .prog_clk_2_W_in ( p3207 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6814 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6815 ) , - .prog_clk_3_W_in ( p2705 ) , .prog_clk_3_E_in ( p2349 ) , + .prog_clk_3_W_in ( p3245 ) , .prog_clk_3_E_in ( p2486 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6816 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6817 ) , .clk_1_W_in ( clk_1_wires[134] ) , .clk_1_E_in ( SYNOPSYS_UNCONNECTED_6818 ) , .clk_1_N_out ( clk_1_wires[138] ) , .clk_1_S_out ( clk_1_wires[139] ) , - .clk_2_E_in ( p1235 ) , .clk_2_W_in ( p2578 ) , + .clk_2_E_in ( p2754 ) , .clk_2_W_in ( p2393 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6819 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6820 ) , .clk_3_W_in ( p2393 ) , - .clk_3_E_in ( p1237 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6821 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6820 ) , .clk_3_W_in ( p2565 ) , + .clk_3_E_in ( p2691 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6821 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6822 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; cbx_1__1_ cbx_8__4_ ( .pReset ( { SYNOPSYS_UNCONNECTED_6823 } ) , @@ -147554,7 +151120,7 @@ cbx_1__1_ cbx_8__4_ ( .bottom_grid_pin_13_ ( cbx_1__1__80_bottom_grid_pin_13_ ) , .bottom_grid_pin_14_ ( cbx_1__1__80_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__80_bottom_grid_pin_15_ ) , - .ccff_tail ( cbx_1__1__80_ccff_tail ) , .SC_IN_TOP ( p1551 ) , + .ccff_tail ( cbx_1__1__80_ccff_tail ) , .SC_IN_TOP ( p1893 ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_6824 ) , .SC_IN_BOT ( scff_Wires[194] ) , .SC_OUT_TOP ( scff_Wires[195] ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[80] ) , @@ -147567,23 +151133,23 @@ cbx_1__1_ cbx_8__4_ ( .pReset_S_out ( pResetWires[239] ) , .pReset_E_out ( pResetWires[238] ) , .prog_clk_0_N_in ( prog_clk_0_wires[303] ) , .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6827 ) , - .prog_clk_1_W_in ( p1920 ) , .prog_clk_1_E_in ( p685 ) , + .prog_clk_1_W_in ( p1453 ) , .prog_clk_1_E_in ( p295 ) , .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_6828 ) , .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_6829 ) , .prog_clk_2_E_in ( prog_clk_2_wires[80] ) , .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_6830 ) , .prog_clk_2_W_out ( prog_clk_2_wires[81] ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6831 ) , - .prog_clk_3_W_in ( p1801 ) , .prog_clk_3_E_in ( p1294 ) , + .prog_clk_3_W_in ( p1275 ) , .prog_clk_3_E_in ( p1739 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6832 ) , - .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6833 ) , .clk_1_W_in ( p1468 ) , - .clk_1_E_in ( p556 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_6834 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6833 ) , .clk_1_W_in ( p1169 ) , + .clk_1_E_in ( p631 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_6834 ) , .clk_1_S_out ( SYNOPSYS_UNCONNECTED_6835 ) , .clk_2_E_in ( clk_2_wires[80] ) , .clk_2_W_in ( SYNOPSYS_UNCONNECTED_6836 ) , .clk_2_W_out ( clk_2_wires[81] ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6837 ) , .clk_3_W_in ( p1801 ) , - .clk_3_E_in ( p358 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6838 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6837 ) , .clk_3_W_in ( p1275 ) , + .clk_3_E_in ( p1015 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6838 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6839 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; cbx_1__1_ cbx_8__5_ ( .pReset ( { SYNOPSYS_UNCONNECTED_6840 } ) , @@ -147608,7 +151174,7 @@ cbx_1__1_ cbx_8__5_ ( .bottom_grid_pin_13_ ( cbx_1__1__81_bottom_grid_pin_13_ ) , .bottom_grid_pin_14_ ( cbx_1__1__81_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__81_bottom_grid_pin_15_ ) , - .ccff_tail ( cbx_1__1__81_ccff_tail ) , .SC_IN_TOP ( p1898 ) , + .ccff_tail ( cbx_1__1__81_ccff_tail ) , .SC_IN_TOP ( p2368 ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_6841 ) , .SC_IN_BOT ( scff_Wires[196] ) , .SC_OUT_TOP ( scff_Wires[197] ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[81] ) , @@ -147624,20 +151190,20 @@ cbx_1__1_ cbx_8__5_ ( .prog_clk_1_W_in ( prog_clk_1_wires[141] ) , .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_6845 ) , .prog_clk_1_N_out ( prog_clk_1_wires[145] ) , - .prog_clk_1_S_out ( prog_clk_1_wires[146] ) , .prog_clk_2_E_in ( p1950 ) , - .prog_clk_2_W_in ( p521 ) , + .prog_clk_1_S_out ( prog_clk_1_wires[146] ) , .prog_clk_2_E_in ( p2962 ) , + .prog_clk_2_W_in ( p2191 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6846 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6847 ) , - .prog_clk_3_W_in ( p2610 ) , .prog_clk_3_E_in ( p1763 ) , + .prog_clk_3_W_in ( p2303 ) , .prog_clk_3_E_in ( p2897 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6848 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6849 ) , .clk_1_W_in ( clk_1_wires[141] ) , .clk_1_E_in ( SYNOPSYS_UNCONNECTED_6850 ) , .clk_1_N_out ( clk_1_wires[145] ) , .clk_1_S_out ( clk_1_wires[146] ) , - .clk_2_E_in ( p1950 ) , .clk_2_W_in ( p3149 ) , + .clk_2_E_in ( p1895 ) , .clk_2_W_in ( p2095 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6851 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6852 ) , .clk_3_W_in ( p3182 ) , - .clk_3_E_in ( p1662 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6853 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6852 ) , .clk_3_W_in ( p2276 ) , + .clk_3_E_in ( p1693 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6853 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6854 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; cbx_1__1_ cbx_8__6_ ( .pReset ( { SYNOPSYS_UNCONNECTED_6855 } ) , @@ -147662,7 +151228,7 @@ cbx_1__1_ cbx_8__6_ ( .bottom_grid_pin_13_ ( cbx_1__1__82_bottom_grid_pin_13_ ) , .bottom_grid_pin_14_ ( cbx_1__1__82_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__82_bottom_grid_pin_15_ ) , - .ccff_tail ( cbx_1__1__82_ccff_tail ) , .SC_IN_TOP ( p1592 ) , + .ccff_tail ( cbx_1__1__82_ccff_tail ) , .SC_IN_TOP ( p1514 ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_6856 ) , .SC_IN_BOT ( scff_Wires[198] ) , .SC_OUT_TOP ( scff_Wires[199] ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[82] ) , @@ -147675,19 +151241,19 @@ cbx_1__1_ cbx_8__6_ ( .pReset_S_out ( pResetWires[337] ) , .pReset_E_out ( pResetWires[336] ) , .prog_clk_0_N_in ( prog_clk_0_wires[309] ) , .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6859 ) , - .prog_clk_1_W_in ( p2414 ) , .prog_clk_1_E_in ( p466 ) , + .prog_clk_1_W_in ( p809 ) , .prog_clk_1_E_in ( p589 ) , .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_6860 ) , .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_6861 ) , - .prog_clk_2_E_in ( p1597 ) , .prog_clk_2_W_in ( p2323 ) , + .prog_clk_2_E_in ( p1414 ) , .prog_clk_2_W_in ( p2113 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6862 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6863 ) , .prog_clk_3_W_in ( prog_clk_3_wires[4] ) , .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_6864 ) , .prog_clk_3_E_out ( prog_clk_3_wires[5] ) , - .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6865 ) , .clk_1_W_in ( p1360 ) , - .clk_1_E_in ( p285 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_6866 ) , - .clk_1_S_out ( SYNOPSYS_UNCONNECTED_6867 ) , .clk_2_E_in ( p1597 ) , - .clk_2_W_in ( p1135 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6868 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6865 ) , .clk_1_W_in ( p2301 ) , + .clk_1_E_in ( p356 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_6866 ) , + .clk_1_S_out ( SYNOPSYS_UNCONNECTED_6867 ) , .clk_2_E_in ( p1414 ) , + .clk_2_W_in ( p798 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6868 ) , .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6869 ) , .clk_3_W_in ( clk_3_wires[4] ) , .clk_3_E_in ( SYNOPSYS_UNCONNECTED_6870 ) , @@ -147716,7 +151282,7 @@ cbx_1__1_ cbx_8__7_ ( .bottom_grid_pin_13_ ( cbx_1__1__83_bottom_grid_pin_13_ ) , .bottom_grid_pin_14_ ( cbx_1__1__83_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__83_bottom_grid_pin_15_ ) , - .ccff_tail ( cbx_1__1__83_ccff_tail ) , .SC_IN_TOP ( p2135 ) , + .ccff_tail ( cbx_1__1__83_ccff_tail ) , .SC_IN_TOP ( p1474 ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_6873 ) , .SC_IN_BOT ( scff_Wires[200] ) , .SC_OUT_TOP ( scff_Wires[201] ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[83] ) , @@ -147732,20 +151298,20 @@ cbx_1__1_ cbx_8__7_ ( .prog_clk_1_W_in ( prog_clk_1_wires[148] ) , .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_6877 ) , .prog_clk_1_N_out ( prog_clk_1_wires[152] ) , - .prog_clk_1_S_out ( prog_clk_1_wires[153] ) , .prog_clk_2_E_in ( p1830 ) , - .prog_clk_2_W_in ( p882 ) , + .prog_clk_1_S_out ( prog_clk_1_wires[153] ) , .prog_clk_2_E_in ( p1986 ) , + .prog_clk_2_W_in ( p3526 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6878 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6879 ) , - .prog_clk_3_W_in ( p3309 ) , .prog_clk_3_E_in ( p2033 ) , + .prog_clk_3_W_in ( p3536 ) , .prog_clk_3_E_in ( p1737 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6880 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6881 ) , .clk_1_W_in ( clk_1_wires[148] ) , .clk_1_E_in ( SYNOPSYS_UNCONNECTED_6882 ) , .clk_1_N_out ( clk_1_wires[152] ) , .clk_1_S_out ( clk_1_wires[153] ) , - .clk_2_E_in ( p1830 ) , .clk_2_W_in ( p3291 ) , + .clk_2_E_in ( p1979 ) , .clk_2_W_in ( p3544 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6883 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6884 ) , .clk_3_W_in ( p2987 ) , - .clk_3_E_in ( p1672 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6885 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6884 ) , .clk_3_W_in ( p3555 ) , + .clk_3_E_in ( p1752 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6885 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6886 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; cbx_1__1_ cbx_8__8_ ( .pReset ( { SYNOPSYS_UNCONNECTED_6887 } ) , @@ -147770,7 +151336,7 @@ cbx_1__1_ cbx_8__8_ ( .bottom_grid_pin_13_ ( cbx_1__1__84_bottom_grid_pin_13_ ) , .bottom_grid_pin_14_ ( cbx_1__1__84_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__84_bottom_grid_pin_15_ ) , - .ccff_tail ( cbx_1__1__84_ccff_tail ) , .SC_IN_TOP ( p2706 ) , + .ccff_tail ( cbx_1__1__84_ccff_tail ) , .SC_IN_TOP ( p1383 ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_6888 ) , .SC_IN_BOT ( scff_Wires[202] ) , .SC_OUT_TOP ( scff_Wires[203] ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[84] ) , @@ -147783,23 +151349,23 @@ cbx_1__1_ cbx_8__8_ ( .pReset_S_out ( pResetWires[435] ) , .pReset_E_out ( pResetWires[434] ) , .prog_clk_0_N_in ( prog_clk_0_wires[315] ) , .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6891 ) , - .prog_clk_1_W_in ( p962 ) , .prog_clk_1_E_in ( p675 ) , + .prog_clk_1_W_in ( p1633 ) , .prog_clk_1_E_in ( p384 ) , .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_6892 ) , .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_6893 ) , .prog_clk_2_E_in ( prog_clk_2_wires[93] ) , .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_6894 ) , .prog_clk_2_W_out ( prog_clk_2_wires[94] ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6895 ) , - .prog_clk_3_W_in ( p962 ) , .prog_clk_3_E_in ( p2539 ) , + .prog_clk_3_W_in ( p1361 ) , .prog_clk_3_E_in ( p948 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6896 ) , - .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6897 ) , .clk_1_W_in ( p1355 ) , - .clk_1_E_in ( p199 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_6898 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6897 ) , .clk_1_W_in ( p1361 ) , + .clk_1_E_in ( p772 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_6898 ) , .clk_1_S_out ( SYNOPSYS_UNCONNECTED_6899 ) , .clk_2_E_in ( clk_2_wires[93] ) , .clk_2_W_in ( SYNOPSYS_UNCONNECTED_6900 ) , .clk_2_W_out ( clk_2_wires[94] ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6901 ) , .clk_3_W_in ( p962 ) , - .clk_3_E_in ( p539 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6902 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6901 ) , .clk_3_W_in ( p1361 ) , + .clk_3_E_in ( p504 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6902 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6903 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; cbx_1__1_ cbx_8__9_ ( .pReset ( { SYNOPSYS_UNCONNECTED_6904 } ) , @@ -147824,7 +151390,7 @@ cbx_1__1_ cbx_8__9_ ( .bottom_grid_pin_13_ ( cbx_1__1__85_bottom_grid_pin_13_ ) , .bottom_grid_pin_14_ ( cbx_1__1__85_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__85_bottom_grid_pin_15_ ) , - .ccff_tail ( cbx_1__1__85_ccff_tail ) , .SC_IN_TOP ( p1589 ) , + .ccff_tail ( cbx_1__1__85_ccff_tail ) , .SC_IN_TOP ( p2360 ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_6905 ) , .SC_IN_BOT ( scff_Wires[204] ) , .SC_OUT_TOP ( scff_Wires[205] ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[85] ) , @@ -147840,20 +151406,20 @@ cbx_1__1_ cbx_8__9_ ( .prog_clk_1_W_in ( prog_clk_1_wires[155] ) , .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_6909 ) , .prog_clk_1_N_out ( prog_clk_1_wires[159] ) , - .prog_clk_1_S_out ( prog_clk_1_wires[160] ) , .prog_clk_2_E_in ( p1780 ) , - .prog_clk_2_W_in ( p1056 ) , + .prog_clk_1_S_out ( prog_clk_1_wires[160] ) , .prog_clk_2_E_in ( p2274 ) , + .prog_clk_2_W_in ( p2648 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6910 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6911 ) , - .prog_clk_3_W_in ( p3254 ) , .prog_clk_3_E_in ( p655 ) , + .prog_clk_3_W_in ( p2753 ) , .prog_clk_3_E_in ( p2161 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6912 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6913 ) , .clk_1_W_in ( clk_1_wires[155] ) , .clk_1_E_in ( SYNOPSYS_UNCONNECTED_6914 ) , .clk_1_N_out ( clk_1_wires[159] ) , .clk_1_S_out ( clk_1_wires[160] ) , - .clk_2_E_in ( p1780 ) , .clk_2_W_in ( p3216 ) , + .clk_2_E_in ( p2553 ) , .clk_2_W_in ( p2149 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6915 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6916 ) , .clk_3_W_in ( p1905 ) , - .clk_3_E_in ( p1710 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6917 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6916 ) , .clk_3_W_in ( p2367 ) , + .clk_3_E_in ( p2380 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6917 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6918 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; cbx_1__1_ cbx_8__10_ ( .pReset ( { SYNOPSYS_UNCONNECTED_6919 } ) , @@ -147878,7 +151444,7 @@ cbx_1__1_ cbx_8__10_ ( .bottom_grid_pin_13_ ( cbx_1__1__86_bottom_grid_pin_13_ ) , .bottom_grid_pin_14_ ( cbx_1__1__86_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__86_bottom_grid_pin_15_ ) , - .ccff_tail ( cbx_1__1__86_ccff_tail ) , .SC_IN_TOP ( p2165 ) , + .ccff_tail ( cbx_1__1__86_ccff_tail ) , .SC_IN_TOP ( p2225 ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_6920 ) , .SC_IN_BOT ( scff_Wires[206] ) , .SC_OUT_TOP ( scff_Wires[207] ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[86] ) , @@ -147891,23 +151457,23 @@ cbx_1__1_ cbx_8__10_ ( .pReset_S_out ( pResetWires[533] ) , .pReset_E_out ( pResetWires[532] ) , .prog_clk_0_N_in ( prog_clk_0_wires[321] ) , .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6923 ) , - .prog_clk_1_W_in ( p1804 ) , .prog_clk_1_E_in ( p2058 ) , + .prog_clk_1_W_in ( p1347 ) , .prog_clk_1_E_in ( p702 ) , .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_6924 ) , .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_6925 ) , .prog_clk_2_E_in ( prog_clk_2_wires[106] ) , .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_6926 ) , .prog_clk_2_W_out ( prog_clk_2_wires[107] ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6927 ) , - .prog_clk_3_W_in ( p1959 ) , .prog_clk_3_E_in ( p2081 ) , + .prog_clk_3_W_in ( p1600 ) , .prog_clk_3_E_in ( p2131 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6928 ) , - .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6929 ) , .clk_1_W_in ( p1410 ) , - .clk_1_E_in ( p599 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_6930 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6929 ) , .clk_1_W_in ( p1324 ) , + .clk_1_E_in ( p100 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_6930 ) , .clk_1_S_out ( SYNOPSYS_UNCONNECTED_6931 ) , .clk_2_E_in ( clk_2_wires[106] ) , .clk_2_W_in ( SYNOPSYS_UNCONNECTED_6932 ) , .clk_2_W_out ( clk_2_wires[107] ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6933 ) , .clk_3_W_in ( p1959 ) , - .clk_3_E_in ( p1964 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6934 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6933 ) , .clk_3_W_in ( p1600 ) , + .clk_3_E_in ( p546 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6934 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6935 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; cbx_1__1_ cbx_8__11_ ( .pReset ( { SYNOPSYS_UNCONNECTED_6936 } ) , @@ -147932,7 +151498,7 @@ cbx_1__1_ cbx_8__11_ ( .bottom_grid_pin_13_ ( cbx_1__1__87_bottom_grid_pin_13_ ) , .bottom_grid_pin_14_ ( cbx_1__1__87_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__87_bottom_grid_pin_15_ ) , - .ccff_tail ( cbx_1__1__87_ccff_tail ) , .SC_IN_TOP ( p2491 ) , + .ccff_tail ( cbx_1__1__87_ccff_tail ) , .SC_IN_TOP ( p1876 ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_6937 ) , .SC_IN_BOT ( scff_Wires[208] ) , .SC_OUT_TOP ( scff_Wires[209] ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[87] ) , @@ -147948,20 +151514,20 @@ cbx_1__1_ cbx_8__11_ ( .prog_clk_1_W_in ( prog_clk_1_wires[162] ) , .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_6941 ) , .prog_clk_1_N_out ( prog_clk_1_wires[166] ) , - .prog_clk_1_S_out ( prog_clk_1_wires[167] ) , .prog_clk_2_E_in ( p2402 ) , - .prog_clk_2_W_in ( p242 ) , + .prog_clk_1_S_out ( prog_clk_1_wires[167] ) , .prog_clk_2_E_in ( p3121 ) , + .prog_clk_2_W_in ( p3484 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6942 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6943 ) , - .prog_clk_3_W_in ( p2482 ) , .prog_clk_3_E_in ( p2364 ) , + .prog_clk_3_W_in ( p3496 ) , .prog_clk_3_E_in ( p3079 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6944 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6945 ) , .clk_1_W_in ( clk_1_wires[162] ) , .clk_1_E_in ( SYNOPSYS_UNCONNECTED_6946 ) , .clk_1_N_out ( clk_1_wires[166] ) , .clk_1_S_out ( clk_1_wires[167] ) , - .clk_2_E_in ( p2402 ) , .clk_2_W_in ( p2339 ) , + .clk_2_E_in ( p2755 ) , .clk_2_W_in ( p2433 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6947 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6948 ) , .clk_3_W_in ( p2506 ) , - .clk_3_E_in ( p2270 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6949 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6948 ) , .clk_3_W_in ( p2568 ) , + .clk_3_E_in ( p2692 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6949 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6950 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; cbx_1__1_ cbx_9__1_ ( .pReset ( { SYNOPSYS_UNCONNECTED_6951 } ) , @@ -147987,7 +151553,7 @@ cbx_1__1_ cbx_9__1_ ( .bottom_grid_pin_14_ ( cbx_1__1__88_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__88_bottom_grid_pin_15_ ) , .ccff_tail ( cbx_1__1__88_ccff_tail ) , .SC_IN_TOP ( scff_Wires[234] ) , - .SC_OUT_BOT ( scff_Wires[235] ) , .SC_IN_BOT ( p946 ) , + .SC_OUT_BOT ( scff_Wires[235] ) , .SC_IN_BOT ( p1237 ) , .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_6952 ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[88] ) , .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[88] ) , @@ -148002,19 +151568,19 @@ cbx_1__1_ cbx_9__1_ ( .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_6956 ) , .prog_clk_1_E_in ( prog_clk_1_wires[170] ) , .prog_clk_1_N_out ( prog_clk_1_wires[171] ) , - .prog_clk_1_S_out ( prog_clk_1_wires[172] ) , .prog_clk_2_E_in ( p1816 ) , - .prog_clk_2_W_in ( p643 ) , + .prog_clk_1_S_out ( prog_clk_1_wires[172] ) , .prog_clk_2_E_in ( p3009 ) , + .prog_clk_2_W_in ( p3037 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6957 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6958 ) , - .prog_clk_3_W_in ( p2673 ) , .prog_clk_3_E_in ( p427 ) , + .prog_clk_3_W_in ( p3150 ) , .prog_clk_3_E_in ( p2862 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6959 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6960 ) , .clk_1_W_in ( SYNOPSYS_UNCONNECTED_6961 ) , .clk_1_E_in ( clk_1_wires[170] ) , .clk_1_N_out ( clk_1_wires[171] ) , - .clk_1_S_out ( clk_1_wires[172] ) , .clk_2_E_in ( p1816 ) , - .clk_2_W_in ( p2761 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6962 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6963 ) , .clk_3_W_in ( p2787 ) , - .clk_3_E_in ( p1706 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6964 ) , + .clk_1_S_out ( clk_1_wires[172] ) , .clk_2_E_in ( p2835 ) , + .clk_2_W_in ( p3381 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6962 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6963 ) , .clk_3_W_in ( p3423 ) , + .clk_3_E_in ( p2713 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6964 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6965 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; cbx_1__1_ cbx_9__2_ ( .pReset ( { SYNOPSYS_UNCONNECTED_6966 } ) , @@ -148040,7 +151606,7 @@ cbx_1__1_ cbx_9__2_ ( .bottom_grid_pin_14_ ( cbx_1__1__89_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__89_bottom_grid_pin_15_ ) , .ccff_tail ( cbx_1__1__89_ccff_tail ) , .SC_IN_TOP ( scff_Wires[232] ) , - .SC_OUT_BOT ( scff_Wires[233] ) , .SC_IN_BOT ( p1832 ) , + .SC_OUT_BOT ( scff_Wires[233] ) , .SC_IN_BOT ( p1536 ) , .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_6967 ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[89] ) , .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[89] ) , @@ -148052,23 +151618,23 @@ cbx_1__1_ cbx_9__2_ ( .pReset_S_out ( pResetWires[145] ) , .pReset_E_out ( pResetWires[144] ) , .prog_clk_0_N_in ( prog_clk_0_wires[335] ) , .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6970 ) , - .prog_clk_1_W_in ( p1887 ) , .prog_clk_1_E_in ( p451 ) , + .prog_clk_1_W_in ( p1271 ) , .prog_clk_1_E_in ( p634 ) , .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_6971 ) , .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_6972 ) , .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_6973 ) , .prog_clk_2_W_in ( prog_clk_2_wires[69] ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6974 ) , - .prog_clk_2_E_out ( prog_clk_2_wires[70] ) , .prog_clk_3_W_in ( p1887 ) , - .prog_clk_3_E_in ( p1027 ) , + .prog_clk_2_E_out ( prog_clk_2_wires[70] ) , .prog_clk_3_W_in ( p1635 ) , + .prog_clk_3_E_in ( p173 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6975 ) , - .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6976 ) , .clk_1_W_in ( p1430 ) , - .clk_1_E_in ( p1682 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_6977 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6976 ) , .clk_1_W_in ( p1493 ) , + .clk_1_E_in ( p608 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_6977 ) , .clk_1_S_out ( SYNOPSYS_UNCONNECTED_6978 ) , .clk_2_E_in ( SYNOPSYS_UNCONNECTED_6979 ) , .clk_2_W_in ( clk_2_wires[69] ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6980 ) , - .clk_2_E_out ( clk_2_wires[70] ) , .clk_3_W_in ( p1887 ) , - .clk_3_E_in ( p164 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6981 ) , + .clk_2_E_out ( clk_2_wires[70] ) , .clk_3_W_in ( p1635 ) , + .clk_3_E_in ( p945 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6981 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6982 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; cbx_1__1_ cbx_9__3_ ( .pReset ( { SYNOPSYS_UNCONNECTED_6983 } ) , @@ -148094,7 +151660,7 @@ cbx_1__1_ cbx_9__3_ ( .bottom_grid_pin_14_ ( cbx_1__1__90_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__90_bottom_grid_pin_15_ ) , .ccff_tail ( cbx_1__1__90_ccff_tail ) , .SC_IN_TOP ( scff_Wires[230] ) , - .SC_OUT_BOT ( scff_Wires[231] ) , .SC_IN_BOT ( p1533 ) , + .SC_OUT_BOT ( scff_Wires[231] ) , .SC_IN_BOT ( p1456 ) , .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_6984 ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[90] ) , .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[90] ) , @@ -148109,19 +151675,19 @@ cbx_1__1_ cbx_9__3_ ( .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_6988 ) , .prog_clk_1_E_in ( prog_clk_1_wires[177] ) , .prog_clk_1_N_out ( prog_clk_1_wires[178] ) , - .prog_clk_1_S_out ( prog_clk_1_wires[179] ) , .prog_clk_2_E_in ( p2605 ) , - .prog_clk_2_W_in ( p977 ) , + .prog_clk_1_S_out ( prog_clk_1_wires[179] ) , .prog_clk_2_E_in ( p3345 ) , + .prog_clk_2_W_in ( p2686 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6989 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6990 ) , - .prog_clk_3_W_in ( p3248 ) , .prog_clk_3_E_in ( p817 ) , + .prog_clk_3_W_in ( p2780 ) , .prog_clk_3_E_in ( p3281 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6991 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6992 ) , .clk_1_W_in ( SYNOPSYS_UNCONNECTED_6993 ) , .clk_1_E_in ( clk_1_wires[177] ) , .clk_1_N_out ( clk_1_wires[178] ) , - .clk_1_S_out ( clk_1_wires[179] ) , .clk_2_E_in ( p2605 ) , - .clk_2_W_in ( p3230 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6994 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6995 ) , .clk_3_W_in ( p2229 ) , - .clk_3_E_in ( p2568 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6996 ) , + .clk_1_S_out ( clk_1_wires[179] ) , .clk_2_E_in ( p1404 ) , + .clk_2_W_in ( p83 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6994 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6995 ) , .clk_3_W_in ( p1311 ) , + .clk_3_E_in ( p779 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6996 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6997 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; cbx_1__1_ cbx_9__4_ ( .pReset ( { SYNOPSYS_UNCONNECTED_6998 } ) , @@ -148147,7 +151713,7 @@ cbx_1__1_ cbx_9__4_ ( .bottom_grid_pin_14_ ( cbx_1__1__91_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__91_bottom_grid_pin_15_ ) , .ccff_tail ( cbx_1__1__91_ccff_tail ) , .SC_IN_TOP ( scff_Wires[228] ) , - .SC_OUT_BOT ( scff_Wires[229] ) , .SC_IN_BOT ( p1449 ) , + .SC_OUT_BOT ( scff_Wires[229] ) , .SC_IN_BOT ( p1841 ) , .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_6999 ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[91] ) , .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[91] ) , @@ -148159,23 +151725,23 @@ cbx_1__1_ cbx_9__4_ ( .pReset_S_out ( pResetWires[243] ) , .pReset_E_out ( pResetWires[242] ) , .prog_clk_0_N_in ( prog_clk_0_wires[341] ) , .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_7002 ) , - .prog_clk_1_W_in ( p1549 ) , .prog_clk_1_E_in ( p150 ) , + .prog_clk_1_W_in ( p1145 ) , .prog_clk_1_E_in ( p1676 ) , .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_7003 ) , .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_7004 ) , .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_7005 ) , .prog_clk_2_W_in ( prog_clk_2_wires[78] ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_7006 ) , - .prog_clk_2_E_out ( prog_clk_2_wires[79] ) , .prog_clk_3_W_in ( p809 ) , - .prog_clk_3_E_in ( p1212 ) , + .prog_clk_2_E_out ( prog_clk_2_wires[79] ) , .prog_clk_3_W_in ( p1263 ) , + .prog_clk_3_E_in ( p465 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_7007 ) , - .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_7008 ) , .clk_1_W_in ( p1482 ) , - .clk_1_E_in ( p489 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_7009 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_7008 ) , .clk_1_W_in ( p1263 ) , + .clk_1_E_in ( p2162 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_7009 ) , .clk_1_S_out ( SYNOPSYS_UNCONNECTED_7010 ) , .clk_2_E_in ( SYNOPSYS_UNCONNECTED_7011 ) , .clk_2_W_in ( clk_2_wires[78] ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7012 ) , - .clk_2_E_out ( clk_2_wires[79] ) , .clk_3_W_in ( p809 ) , - .clk_3_E_in ( p526 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7013 ) , + .clk_2_E_out ( clk_2_wires[79] ) , .clk_3_W_in ( p1263 ) , + .clk_3_E_in ( p2086 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7013 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7014 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; cbx_1__1_ cbx_9__5_ ( .pReset ( { SYNOPSYS_UNCONNECTED_7015 } ) , @@ -148201,7 +151767,7 @@ cbx_1__1_ cbx_9__5_ ( .bottom_grid_pin_14_ ( cbx_1__1__92_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__92_bottom_grid_pin_15_ ) , .ccff_tail ( cbx_1__1__92_ccff_tail ) , .SC_IN_TOP ( scff_Wires[226] ) , - .SC_OUT_BOT ( scff_Wires[227] ) , .SC_IN_BOT ( p1611 ) , + .SC_OUT_BOT ( scff_Wires[227] ) , .SC_IN_BOT ( p1511 ) , .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_7016 ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[92] ) , .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[92] ) , @@ -148216,19 +151782,19 @@ cbx_1__1_ cbx_9__5_ ( .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_7020 ) , .prog_clk_1_E_in ( prog_clk_1_wires[184] ) , .prog_clk_1_N_out ( prog_clk_1_wires[185] ) , - .prog_clk_1_S_out ( prog_clk_1_wires[186] ) , .prog_clk_2_E_in ( p1598 ) , - .prog_clk_2_W_in ( p415 ) , + .prog_clk_1_S_out ( prog_clk_1_wires[186] ) , .prog_clk_2_E_in ( p2855 ) , + .prog_clk_2_W_in ( p696 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_7021 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_7022 ) , - .prog_clk_3_W_in ( p3366 ) , .prog_clk_3_E_in ( p1245 ) , + .prog_clk_3_W_in ( p1213 ) , .prog_clk_3_E_in ( p2657 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_7023 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_7024 ) , .clk_1_W_in ( SYNOPSYS_UNCONNECTED_7025 ) , .clk_1_E_in ( clk_1_wires[184] ) , .clk_1_N_out ( clk_1_wires[185] ) , - .clk_1_S_out ( clk_1_wires[186] ) , .clk_2_E_in ( p1598 ) , - .clk_2_W_in ( p3338 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7026 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7027 ) , .clk_3_W_in ( p2778 ) , - .clk_3_E_in ( p487 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7028 ) , + .clk_1_S_out ( clk_1_wires[186] ) , .clk_2_E_in ( p2330 ) , + .clk_2_W_in ( p1777 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7026 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7027 ) , .clk_3_W_in ( p2019 ) , + .clk_3_E_in ( p2177 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7028 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7029 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; cbx_1__1_ cbx_9__6_ ( .pReset ( { SYNOPSYS_UNCONNECTED_7030 } ) , @@ -148254,7 +151820,7 @@ cbx_1__1_ cbx_9__6_ ( .bottom_grid_pin_14_ ( cbx_1__1__93_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__93_bottom_grid_pin_15_ ) , .ccff_tail ( cbx_1__1__93_ccff_tail ) , .SC_IN_TOP ( scff_Wires[224] ) , - .SC_OUT_BOT ( scff_Wires[225] ) , .SC_IN_BOT ( p1587 ) , + .SC_OUT_BOT ( scff_Wires[225] ) , .SC_IN_BOT ( p1314 ) , .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_7031 ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[93] ) , .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[93] ) , @@ -148266,19 +151832,19 @@ cbx_1__1_ cbx_9__6_ ( .pReset_S_out ( pResetWires[341] ) , .pReset_E_out ( pResetWires[340] ) , .prog_clk_0_N_in ( prog_clk_0_wires[347] ) , .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_7034 ) , - .prog_clk_1_W_in ( p1599 ) , .prog_clk_1_E_in ( p747 ) , + .prog_clk_1_W_in ( p1322 ) , .prog_clk_1_E_in ( p431 ) , .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_7035 ) , .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_7036 ) , - .prog_clk_2_E_in ( p1379 ) , .prog_clk_2_W_in ( p1048 ) , + .prog_clk_2_E_in ( p1482 ) , .prog_clk_2_W_in ( p2434 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_7037 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_7038 ) , .prog_clk_3_W_in ( prog_clk_3_wires[44] ) , .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_7039 ) , .prog_clk_3_E_out ( prog_clk_3_wires[45] ) , - .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_7040 ) , .clk_1_W_in ( p1494 ) , - .clk_1_E_in ( p586 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_7041 ) , - .clk_1_S_out ( SYNOPSYS_UNCONNECTED_7042 ) , .clk_2_E_in ( p1379 ) , - .clk_2_W_in ( p506 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7043 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_7040 ) , .clk_1_W_in ( p2632 ) , + .clk_1_E_in ( p901 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_7041 ) , + .clk_1_S_out ( SYNOPSYS_UNCONNECTED_7042 ) , .clk_2_E_in ( p1482 ) , + .clk_2_W_in ( p238 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7043 ) , .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7044 ) , .clk_3_W_in ( clk_3_wires[44] ) , .clk_3_E_in ( SYNOPSYS_UNCONNECTED_7045 ) , @@ -148308,7 +151874,7 @@ cbx_1__1_ cbx_9__7_ ( .bottom_grid_pin_14_ ( cbx_1__1__94_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__94_bottom_grid_pin_15_ ) , .ccff_tail ( cbx_1__1__94_ccff_tail ) , .SC_IN_TOP ( scff_Wires[222] ) , - .SC_OUT_BOT ( scff_Wires[223] ) , .SC_IN_BOT ( p1606 ) , + .SC_OUT_BOT ( scff_Wires[223] ) , .SC_IN_BOT ( p1532 ) , .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_7048 ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[94] ) , .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[94] ) , @@ -148323,19 +151889,19 @@ cbx_1__1_ cbx_9__7_ ( .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_7052 ) , .prog_clk_1_E_in ( prog_clk_1_wires[191] ) , .prog_clk_1_N_out ( prog_clk_1_wires[192] ) , - .prog_clk_1_S_out ( prog_clk_1_wires[193] ) , .prog_clk_2_E_in ( p1797 ) , - .prog_clk_2_W_in ( p605 ) , + .prog_clk_1_S_out ( prog_clk_1_wires[193] ) , .prog_clk_2_E_in ( p2957 ) , + .prog_clk_2_W_in ( p1662 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_7053 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_7054 ) , - .prog_clk_3_W_in ( p3161 ) , .prog_clk_3_E_in ( p1095 ) , + .prog_clk_3_W_in ( p1975 ) , .prog_clk_3_E_in ( p2882 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_7055 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_7056 ) , .clk_1_W_in ( SYNOPSYS_UNCONNECTED_7057 ) , .clk_1_E_in ( clk_1_wires[191] ) , .clk_1_N_out ( clk_1_wires[192] ) , - .clk_1_S_out ( clk_1_wires[193] ) , .clk_2_E_in ( p1797 ) , - .clk_2_W_in ( p3118 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7058 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7059 ) , .clk_3_W_in ( p2996 ) , - .clk_3_E_in ( p1684 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7060 ) , + .clk_1_S_out ( clk_1_wires[193] ) , .clk_2_E_in ( p2288 ) , + .clk_2_W_in ( p3200 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7058 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7059 ) , .clk_3_W_in ( p3235 ) , + .clk_3_E_in ( p2172 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7060 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7061 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; cbx_1__1_ cbx_9__8_ ( .pReset ( { SYNOPSYS_UNCONNECTED_7062 } ) , @@ -148361,7 +151927,7 @@ cbx_1__1_ cbx_9__8_ ( .bottom_grid_pin_14_ ( cbx_1__1__95_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__95_bottom_grid_pin_15_ ) , .ccff_tail ( cbx_1__1__95_ccff_tail ) , .SC_IN_TOP ( scff_Wires[220] ) , - .SC_OUT_BOT ( scff_Wires[221] ) , .SC_IN_BOT ( p1839 ) , + .SC_OUT_BOT ( scff_Wires[221] ) , .SC_IN_BOT ( p1371 ) , .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_7063 ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[95] ) , .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[95] ) , @@ -148373,23 +151939,23 @@ cbx_1__1_ cbx_9__8_ ( .pReset_S_out ( pResetWires[439] ) , .pReset_E_out ( pResetWires[438] ) , .prog_clk_0_N_in ( prog_clk_0_wires[353] ) , .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_7066 ) , - .prog_clk_1_W_in ( p1324 ) , .prog_clk_1_E_in ( p1652 ) , + .prog_clk_1_W_in ( p1140 ) , .prog_clk_1_E_in ( p500 ) , .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_7067 ) , .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_7068 ) , .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_7069 ) , .prog_clk_2_W_in ( prog_clk_2_wires[91] ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_7070 ) , - .prog_clk_2_E_out ( prog_clk_2_wires[92] ) , .prog_clk_3_W_in ( p1595 ) , - .prog_clk_3_E_in ( p1112 ) , + .prog_clk_2_E_out ( prog_clk_2_wires[92] ) , .prog_clk_3_W_in ( p1021 ) , + .prog_clk_3_E_in ( p909 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_7071 ) , - .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_7072 ) , .clk_1_W_in ( p1414 ) , - .clk_1_E_in ( p1723 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_7073 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_7072 ) , .clk_1_W_in ( p1021 ) , + .clk_1_E_in ( p739 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_7073 ) , .clk_1_S_out ( SYNOPSYS_UNCONNECTED_7074 ) , .clk_2_E_in ( SYNOPSYS_UNCONNECTED_7075 ) , .clk_2_W_in ( clk_2_wires[91] ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7076 ) , - .clk_2_E_out ( clk_2_wires[92] ) , .clk_3_W_in ( p1595 ) , - .clk_3_E_in ( p1734 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7077 ) , + .clk_2_E_out ( clk_2_wires[92] ) , .clk_3_W_in ( p1021 ) , + .clk_3_E_in ( p1 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7077 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7078 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; cbx_1__1_ cbx_9__9_ ( .pReset ( { SYNOPSYS_UNCONNECTED_7079 } ) , @@ -148415,7 +151981,7 @@ cbx_1__1_ cbx_9__9_ ( .bottom_grid_pin_14_ ( cbx_1__1__96_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__96_bottom_grid_pin_15_ ) , .ccff_tail ( cbx_1__1__96_ccff_tail ) , .SC_IN_TOP ( scff_Wires[218] ) , - .SC_OUT_BOT ( scff_Wires[219] ) , .SC_IN_BOT ( p1334 ) , + .SC_OUT_BOT ( scff_Wires[219] ) , .SC_IN_BOT ( p1641 ) , .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_7080 ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[96] ) , .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[96] ) , @@ -148430,19 +151996,19 @@ cbx_1__1_ cbx_9__9_ ( .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_7084 ) , .prog_clk_1_E_in ( prog_clk_1_wires[198] ) , .prog_clk_1_N_out ( prog_clk_1_wires[199] ) , - .prog_clk_1_S_out ( prog_clk_1_wires[200] ) , .prog_clk_2_E_in ( p1 ) , - .prog_clk_2_W_in ( p155 ) , + .prog_clk_1_S_out ( prog_clk_1_wires[200] ) , .prog_clk_2_E_in ( p2817 ) , + .prog_clk_2_W_in ( p1811 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_7085 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_7086 ) , - .prog_clk_3_W_in ( p3324 ) , .prog_clk_3_E_in ( p918 ) , + .prog_clk_3_W_in ( p1982 ) , .prog_clk_3_E_in ( p2652 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_7087 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_7088 ) , .clk_1_W_in ( SYNOPSYS_UNCONNECTED_7089 ) , .clk_1_E_in ( clk_1_wires[198] ) , .clk_1_N_out ( clk_1_wires[199] ) , - .clk_1_S_out ( clk_1_wires[200] ) , .clk_2_E_in ( p1 ) , - .clk_2_W_in ( p3293 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7090 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7091 ) , .clk_3_W_in ( p2395 ) , - .clk_3_E_in ( p697 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7092 ) , + .clk_1_S_out ( clk_1_wires[200] ) , .clk_2_E_in ( p2607 ) , + .clk_2_W_in ( p2708 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7090 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7091 ) , .clk_3_W_in ( p2840 ) , + .clk_3_E_in ( p2478 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7092 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7093 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; cbx_1__1_ cbx_9__10_ ( .pReset ( { SYNOPSYS_UNCONNECTED_7094 } ) , @@ -148468,7 +152034,7 @@ cbx_1__1_ cbx_9__10_ ( .bottom_grid_pin_14_ ( cbx_1__1__97_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__97_bottom_grid_pin_15_ ) , .ccff_tail ( cbx_1__1__97_ccff_tail ) , .SC_IN_TOP ( scff_Wires[216] ) , - .SC_OUT_BOT ( scff_Wires[217] ) , .SC_IN_BOT ( p719 ) , + .SC_OUT_BOT ( scff_Wires[217] ) , .SC_IN_BOT ( p1320 ) , .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_7095 ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[97] ) , .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[97] ) , @@ -148480,23 +152046,23 @@ cbx_1__1_ cbx_9__10_ ( .pReset_S_out ( pResetWires[537] ) , .pReset_E_out ( pResetWires[536] ) , .prog_clk_0_N_in ( prog_clk_0_wires[359] ) , .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_7098 ) , - .prog_clk_1_W_in ( p2195 ) , .prog_clk_1_E_in ( p610 ) , + .prog_clk_1_W_in ( p1488 ) , .prog_clk_1_E_in ( p455 ) , .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_7099 ) , .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_7100 ) , .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_7101 ) , .prog_clk_2_W_in ( prog_clk_2_wires[104] ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_7102 ) , - .prog_clk_2_E_out ( prog_clk_2_wires[105] ) , .prog_clk_3_W_in ( p2169 ) , - .prog_clk_3_E_in ( p500 ) , + .prog_clk_2_E_out ( prog_clk_2_wires[105] ) , .prog_clk_3_W_in ( p1386 ) , + .prog_clk_3_E_in ( p1065 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_7103 ) , - .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_7104 ) , .clk_1_W_in ( p1417 ) , - .clk_1_E_in ( p436 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_7105 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_7104 ) , .clk_1_W_in ( p1386 ) , + .clk_1_E_in ( p1810 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_7105 ) , .clk_1_S_out ( SYNOPSYS_UNCONNECTED_7106 ) , .clk_2_E_in ( SYNOPSYS_UNCONNECTED_7107 ) , .clk_2_W_in ( clk_2_wires[104] ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7108 ) , - .clk_2_E_out ( clk_2_wires[105] ) , .clk_3_W_in ( p2169 ) , - .clk_3_E_in ( p1127 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7109 ) , + .clk_2_E_out ( clk_2_wires[105] ) , .clk_3_W_in ( p1386 ) , + .clk_3_E_in ( p1656 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7109 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7110 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; cbx_1__1_ cbx_9__11_ ( .pReset ( { SYNOPSYS_UNCONNECTED_7111 } ) , @@ -148522,7 +152088,7 @@ cbx_1__1_ cbx_9__11_ ( .bottom_grid_pin_14_ ( cbx_1__1__98_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__98_bottom_grid_pin_15_ ) , .ccff_tail ( cbx_1__1__98_ccff_tail ) , .SC_IN_TOP ( scff_Wires[214] ) , - .SC_OUT_BOT ( scff_Wires[215] ) , .SC_IN_BOT ( p1844 ) , + .SC_OUT_BOT ( scff_Wires[215] ) , .SC_IN_BOT ( p1845 ) , .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_7112 ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[98] ) , .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[98] ) , @@ -148537,19 +152103,19 @@ cbx_1__1_ cbx_9__11_ ( .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_7116 ) , .prog_clk_1_E_in ( prog_clk_1_wires[205] ) , .prog_clk_1_N_out ( prog_clk_1_wires[206] ) , - .prog_clk_1_S_out ( prog_clk_1_wires[207] ) , .prog_clk_2_E_in ( p1537 ) , - .prog_clk_2_W_in ( p1206 ) , + .prog_clk_1_S_out ( prog_clk_1_wires[207] ) , .prog_clk_2_E_in ( p3468 ) , + .prog_clk_2_W_in ( p2459 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_7117 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_7118 ) , - .prog_clk_3_W_in ( p3181 ) , .prog_clk_3_E_in ( p1197 ) , + .prog_clk_3_W_in ( p2603 ) , .prog_clk_3_E_in ( p3428 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_7119 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_7120 ) , .clk_1_W_in ( SYNOPSYS_UNCONNECTED_7121 ) , .clk_1_E_in ( clk_1_wires[205] ) , .clk_1_N_out ( clk_1_wires[206] ) , - .clk_1_S_out ( clk_1_wires[207] ) , .clk_2_E_in ( p1537 ) , - .clk_2_W_in ( p3146 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7122 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7123 ) , .clk_3_W_in ( p2390 ) , - .clk_3_E_in ( p259 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7124 ) , + .clk_1_S_out ( clk_1_wires[207] ) , .clk_2_E_in ( p2510 ) , + .clk_2_W_in ( p3072 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7122 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7123 ) , .clk_3_W_in ( p3169 ) , + .clk_3_E_in ( p2474 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7124 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7125 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; cbx_1__1_ cbx_10__1_ ( .pReset ( { SYNOPSYS_UNCONNECTED_7126 } ) , @@ -148574,7 +152140,7 @@ cbx_1__1_ cbx_10__1_ ( .bottom_grid_pin_13_ ( cbx_1__1__99_bottom_grid_pin_13_ ) , .bottom_grid_pin_14_ ( cbx_1__1__99_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__99_bottom_grid_pin_15_ ) , - .ccff_tail ( cbx_1__1__99_ccff_tail ) , .SC_IN_TOP ( p1541 ) , + .ccff_tail ( cbx_1__1__99_ccff_tail ) , .SC_IN_TOP ( p1254 ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_7127 ) , .SC_IN_BOT ( scff_Wires[241] ) , .SC_OUT_TOP ( scff_Wires[242] ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[99] ) , @@ -148590,20 +152156,20 @@ cbx_1__1_ cbx_10__1_ ( .prog_clk_1_W_in ( prog_clk_1_wires[169] ) , .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_7131 ) , .prog_clk_1_N_out ( prog_clk_1_wires[173] ) , - .prog_clk_1_S_out ( prog_clk_1_wires[174] ) , .prog_clk_2_E_in ( p2175 ) , - .prog_clk_2_W_in ( p1775 ) , + .prog_clk_1_S_out ( prog_clk_1_wires[174] ) , .prog_clk_2_E_in ( p2626 ) , + .prog_clk_2_W_in ( p3224 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_7132 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_7133 ) , - .prog_clk_3_W_in ( p3198 ) , .prog_clk_3_E_in ( p1305 ) , + .prog_clk_3_W_in ( p3238 ) , .prog_clk_3_E_in ( p2499 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_7134 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_7135 ) , .clk_1_W_in ( clk_1_wires[169] ) , .clk_1_E_in ( SYNOPSYS_UNCONNECTED_7136 ) , .clk_1_N_out ( clk_1_wires[173] ) , .clk_1_S_out ( clk_1_wires[174] ) , - .clk_2_E_in ( p2175 ) , .clk_2_W_in ( p3156 ) , + .clk_2_E_in ( p1265 ) , .clk_2_W_in ( p3393 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7137 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7138 ) , .clk_3_W_in ( p2644 ) , - .clk_3_E_in ( p2099 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7139 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7138 ) , .clk_3_W_in ( p3406 ) , + .clk_3_E_in ( p1605 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7139 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7140 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; cbx_1__1_ cbx_10__2_ ( .pReset ( { SYNOPSYS_UNCONNECTED_7141 } ) , @@ -148628,7 +152194,7 @@ cbx_1__1_ cbx_10__2_ ( .bottom_grid_pin_13_ ( cbx_1__1__100_bottom_grid_pin_13_ ) , .bottom_grid_pin_14_ ( cbx_1__1__100_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__100_bottom_grid_pin_15_ ) , - .ccff_tail ( cbx_1__1__100_ccff_tail ) , .SC_IN_TOP ( p1771 ) , + .ccff_tail ( cbx_1__1__100_ccff_tail ) , .SC_IN_TOP ( p1819 ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_7142 ) , .SC_IN_BOT ( scff_Wires[243] ) , .SC_OUT_TOP ( scff_Wires[244] ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[100] ) , @@ -148641,20 +152207,20 @@ cbx_1__1_ cbx_10__2_ ( .pReset_S_out ( pResetWires[149] ) , .pReset_E_out ( pResetWires[148] ) , .prog_clk_0_N_in ( prog_clk_0_wires[373] ) , .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_7145 ) , - .prog_clk_1_W_in ( p2231 ) , .prog_clk_1_E_in ( p1258 ) , + .prog_clk_1_W_in ( p1430 ) , .prog_clk_1_E_in ( p1179 ) , .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_7146 ) , .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_7147 ) , - .prog_clk_2_E_in ( p2681 ) , .prog_clk_2_W_in ( p2080 ) , + .prog_clk_2_E_in ( p1819 ) , .prog_clk_2_W_in ( p3390 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_7148 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_7149 ) , - .prog_clk_3_W_in ( p2367 ) , .prog_clk_3_E_in ( p1890 ) , + .prog_clk_3_W_in ( p3424 ) , .prog_clk_3_E_in ( p1930 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_7150 ) , - .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_7151 ) , .clk_1_W_in ( p1286 ) , - .clk_1_E_in ( p867 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_7152 ) , - .clk_1_S_out ( SYNOPSYS_UNCONNECTED_7153 ) , .clk_2_E_in ( p2681 ) , - .clk_2_W_in ( p2493 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7154 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7155 ) , .clk_3_W_in ( p2419 ) , - .clk_3_E_in ( p2604 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7156 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_7151 ) , .clk_1_W_in ( p2289 ) , + .clk_1_E_in ( p1373 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_7152 ) , + .clk_1_S_out ( SYNOPSYS_UNCONNECTED_7153 ) , .clk_2_E_in ( p1521 ) , + .clk_2_W_in ( p2938 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7154 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7155 ) , .clk_3_W_in ( p2946 ) , + .clk_3_E_in ( p428 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7156 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7157 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; cbx_1__1_ cbx_10__3_ ( .pReset ( { SYNOPSYS_UNCONNECTED_7158 } ) , @@ -148679,7 +152245,7 @@ cbx_1__1_ cbx_10__3_ ( .bottom_grid_pin_13_ ( cbx_1__1__101_bottom_grid_pin_13_ ) , .bottom_grid_pin_14_ ( cbx_1__1__101_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__101_bottom_grid_pin_15_ ) , - .ccff_tail ( cbx_1__1__101_ccff_tail ) , .SC_IN_TOP ( p1880 ) , + .ccff_tail ( cbx_1__1__101_ccff_tail ) , .SC_IN_TOP ( p1861 ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_7159 ) , .SC_IN_BOT ( scff_Wires[245] ) , .SC_OUT_TOP ( scff_Wires[246] ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[101] ) , @@ -148695,20 +152261,20 @@ cbx_1__1_ cbx_10__3_ ( .prog_clk_1_W_in ( prog_clk_1_wires[176] ) , .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_7163 ) , .prog_clk_1_N_out ( prog_clk_1_wires[180] ) , - .prog_clk_1_S_out ( prog_clk_1_wires[181] ) , .prog_clk_2_E_in ( p2451 ) , - .prog_clk_2_W_in ( p1343 ) , + .prog_clk_1_S_out ( prog_clk_1_wires[181] ) , .prog_clk_2_E_in ( p2190 ) , + .prog_clk_2_W_in ( p3220 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_7164 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_7165 ) , - .prog_clk_3_W_in ( p2822 ) , .prog_clk_3_E_in ( p1779 ) , + .prog_clk_3_W_in ( p3269 ) , .prog_clk_3_E_in ( p2365 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_7166 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_7167 ) , .clk_1_W_in ( clk_1_wires[176] ) , .clk_1_E_in ( SYNOPSYS_UNCONNECTED_7168 ) , .clk_1_N_out ( clk_1_wires[180] ) , .clk_1_S_out ( clk_1_wires[181] ) , - .clk_2_E_in ( p2451 ) , .clk_2_W_in ( p2769 ) , + .clk_2_E_in ( p2189 ) , .clk_2_W_in ( p2925 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7169 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7170 ) , .clk_3_W_in ( p1952 ) , - .clk_3_E_in ( p2347 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7171 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7170 ) , .clk_3_W_in ( p2979 ) , + .clk_3_E_in ( p2156 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7171 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7172 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; cbx_1__1_ cbx_10__4_ ( .pReset ( { SYNOPSYS_UNCONNECTED_7173 } ) , @@ -148733,7 +152299,7 @@ cbx_1__1_ cbx_10__4_ ( .bottom_grid_pin_13_ ( cbx_1__1__102_bottom_grid_pin_13_ ) , .bottom_grid_pin_14_ ( cbx_1__1__102_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__102_bottom_grid_pin_15_ ) , - .ccff_tail ( cbx_1__1__102_ccff_tail ) , .SC_IN_TOP ( p2427 ) , + .ccff_tail ( cbx_1__1__102_ccff_tail ) , .SC_IN_TOP ( p1610 ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_7174 ) , .SC_IN_BOT ( scff_Wires[247] ) , .SC_OUT_TOP ( scff_Wires[248] ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[102] ) , @@ -148746,20 +152312,20 @@ cbx_1__1_ cbx_10__4_ ( .pReset_S_out ( pResetWires[247] ) , .pReset_E_out ( pResetWires[246] ) , .prog_clk_0_N_in ( prog_clk_0_wires[379] ) , .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_7177 ) , - .prog_clk_1_W_in ( p2613 ) , .prog_clk_1_E_in ( p1096 ) , + .prog_clk_1_W_in ( p1516 ) , .prog_clk_1_E_in ( p847 ) , .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_7178 ) , .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_7179 ) , - .prog_clk_2_E_in ( p1914 ) , .prog_clk_2_W_in ( p2611 ) , + .prog_clk_2_E_in ( p1959 ) , .prog_clk_2_W_in ( p3206 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_7180 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_7181 ) , - .prog_clk_3_W_in ( p3183 ) , .prog_clk_3_E_in ( p2360 ) , + .prog_clk_3_W_in ( p3247 ) , .prog_clk_3_E_in ( p1761 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_7182 ) , - .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_7183 ) , .clk_1_W_in ( p1591 ) , - .clk_1_E_in ( p779 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_7184 ) , - .clk_1_S_out ( SYNOPSYS_UNCONNECTED_7185 ) , .clk_2_E_in ( p1914 ) , - .clk_2_W_in ( p3148 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7186 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7187 ) , .clk_3_W_in ( p2178 ) , - .clk_3_E_in ( p1756 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7188 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_7183 ) , .clk_1_W_in ( p2271 ) , + .clk_1_E_in ( p1050 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_7184 ) , + .clk_1_S_out ( SYNOPSYS_UNCONNECTED_7185 ) , .clk_2_E_in ( p2794 ) , + .clk_2_W_in ( p3103 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7186 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7187 ) , .clk_3_W_in ( p3112 ) , + .clk_3_E_in ( p2733 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7188 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7189 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; cbx_1__1_ cbx_10__5_ ( .pReset ( { SYNOPSYS_UNCONNECTED_7190 } ) , @@ -148784,7 +152350,7 @@ cbx_1__1_ cbx_10__5_ ( .bottom_grid_pin_13_ ( cbx_1__1__103_bottom_grid_pin_13_ ) , .bottom_grid_pin_14_ ( cbx_1__1__103_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__103_bottom_grid_pin_15_ ) , - .ccff_tail ( cbx_1__1__103_ccff_tail ) , .SC_IN_TOP ( p2108 ) , + .ccff_tail ( cbx_1__1__103_ccff_tail ) , .SC_IN_TOP ( p2244 ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_7191 ) , .SC_IN_BOT ( scff_Wires[249] ) , .SC_OUT_TOP ( scff_Wires[250] ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[103] ) , @@ -148800,20 +152366,20 @@ cbx_1__1_ cbx_10__5_ ( .prog_clk_1_W_in ( prog_clk_1_wires[183] ) , .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_7195 ) , .prog_clk_1_N_out ( prog_clk_1_wires[187] ) , - .prog_clk_1_S_out ( prog_clk_1_wires[188] ) , .prog_clk_2_E_in ( p2142 ) , - .prog_clk_2_W_in ( p1047 ) , + .prog_clk_1_S_out ( prog_clk_1_wires[188] ) , .prog_clk_2_E_in ( p3020 ) , + .prog_clk_2_W_in ( p2495 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_7196 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_7197 ) , - .prog_clk_3_W_in ( p3052 ) , .prog_clk_3_E_in ( p2072 ) , + .prog_clk_3_W_in ( p2608 ) , .prog_clk_3_E_in ( p2931 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_7198 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_7199 ) , .clk_1_W_in ( clk_1_wires[183] ) , .clk_1_E_in ( SYNOPSYS_UNCONNECTED_7200 ) , .clk_1_N_out ( clk_1_wires[187] ) , .clk_1_S_out ( clk_1_wires[188] ) , - .clk_2_E_in ( p2142 ) , .clk_2_W_in ( p3049 ) , + .clk_2_E_in ( p2327 ) , .clk_2_W_in ( p2426 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7201 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7202 ) , .clk_3_W_in ( p1808 ) , - .clk_3_E_in ( p2213 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7203 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7202 ) , .clk_3_W_in ( p2576 ) , + .clk_3_E_in ( p2144 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7203 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7204 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; cbx_1__1_ cbx_10__6_ ( .pReset ( { SYNOPSYS_UNCONNECTED_7205 } ) , @@ -148838,7 +152404,7 @@ cbx_1__1_ cbx_10__6_ ( .bottom_grid_pin_13_ ( cbx_1__1__104_bottom_grid_pin_13_ ) , .bottom_grid_pin_14_ ( cbx_1__1__104_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__104_bottom_grid_pin_15_ ) , - .ccff_tail ( cbx_1__1__104_ccff_tail ) , .SC_IN_TOP ( p1531 ) , + .ccff_tail ( cbx_1__1__104_ccff_tail ) , .SC_IN_TOP ( p1479 ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_7206 ) , .SC_IN_BOT ( scff_Wires[251] ) , .SC_OUT_TOP ( scff_Wires[252] ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[104] ) , @@ -148851,19 +152417,19 @@ cbx_1__1_ cbx_10__6_ ( .pReset_S_out ( pResetWires[345] ) , .pReset_E_out ( pResetWires[344] ) , .prog_clk_0_N_in ( prog_clk_0_wires[385] ) , .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_7209 ) , - .prog_clk_1_W_in ( p1610 ) , .prog_clk_1_E_in ( p1108 ) , + .prog_clk_1_W_in ( p1512 ) , .prog_clk_1_E_in ( p1000 ) , .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_7210 ) , .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_7211 ) , - .prog_clk_2_E_in ( p1531 ) , .prog_clk_2_W_in ( p1376 ) , + .prog_clk_2_E_in ( p1649 ) , .prog_clk_2_W_in ( p2168 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_7212 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_7213 ) , .prog_clk_3_W_in ( prog_clk_3_wires[48] ) , .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_7214 ) , .prog_clk_3_E_out ( prog_clk_3_wires[49] ) , - .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_7215 ) , .clk_1_W_in ( p1588 ) , - .clk_1_E_in ( p1131 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_7216 ) , - .clk_1_S_out ( SYNOPSYS_UNCONNECTED_7217 ) , .clk_2_E_in ( p1531 ) , - .clk_2_W_in ( p898 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7218 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_7215 ) , .clk_1_W_in ( p2296 ) , + .clk_1_E_in ( p769 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_7216 ) , + .clk_1_S_out ( SYNOPSYS_UNCONNECTED_7217 ) , .clk_2_E_in ( p1344 ) , + .clk_2_W_in ( p1235 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7218 ) , .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7219 ) , .clk_3_W_in ( clk_3_wires[48] ) , .clk_3_E_in ( SYNOPSYS_UNCONNECTED_7220 ) , @@ -148892,7 +152458,7 @@ cbx_1__1_ cbx_10__7_ ( .bottom_grid_pin_13_ ( cbx_1__1__105_bottom_grid_pin_13_ ) , .bottom_grid_pin_14_ ( cbx_1__1__105_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__105_bottom_grid_pin_15_ ) , - .ccff_tail ( cbx_1__1__105_ccff_tail ) , .SC_IN_TOP ( p1454 ) , + .ccff_tail ( cbx_1__1__105_ccff_tail ) , .SC_IN_TOP ( p1539 ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_7223 ) , .SC_IN_BOT ( scff_Wires[253] ) , .SC_OUT_TOP ( scff_Wires[254] ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[105] ) , @@ -148908,20 +152474,20 @@ cbx_1__1_ cbx_10__7_ ( .prog_clk_1_W_in ( prog_clk_1_wires[190] ) , .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_7227 ) , .prog_clk_1_N_out ( prog_clk_1_wires[194] ) , - .prog_clk_1_S_out ( prog_clk_1_wires[195] ) , .prog_clk_2_E_in ( p2418 ) , - .prog_clk_2_W_in ( p1729 ) , + .prog_clk_1_S_out ( prog_clk_1_wires[195] ) , .prog_clk_2_E_in ( p3251 ) , + .prog_clk_2_W_in ( p1068 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_7228 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_7229 ) , - .prog_clk_3_W_in ( p3106 ) , .prog_clk_3_E_in ( p849 ) , + .prog_clk_3_W_in ( p1410 ) , .prog_clk_3_E_in ( p3202 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_7230 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_7231 ) , .clk_1_W_in ( clk_1_wires[190] ) , .clk_1_E_in ( SYNOPSYS_UNCONNECTED_7232 ) , .clk_1_N_out ( clk_1_wires[194] ) , .clk_1_S_out ( clk_1_wires[195] ) , - .clk_2_E_in ( p2418 ) , .clk_2_W_in ( p3046 ) , + .clk_2_E_in ( p2507 ) , .clk_2_W_in ( p3218 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7233 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7234 ) , .clk_3_W_in ( p1805 ) , - .clk_3_E_in ( p2368 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7235 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7234 ) , .clk_3_W_in ( p3246 ) , + .clk_3_E_in ( p2506 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7235 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7236 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; cbx_1__1_ cbx_10__8_ ( .pReset ( { SYNOPSYS_UNCONNECTED_7237 } ) , @@ -148946,7 +152512,7 @@ cbx_1__1_ cbx_10__8_ ( .bottom_grid_pin_13_ ( cbx_1__1__106_bottom_grid_pin_13_ ) , .bottom_grid_pin_14_ ( cbx_1__1__106_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__106_bottom_grid_pin_15_ ) , - .ccff_tail ( cbx_1__1__106_ccff_tail ) , .SC_IN_TOP ( p1856 ) , + .ccff_tail ( cbx_1__1__106_ccff_tail ) , .SC_IN_TOP ( p2268 ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_7238 ) , .SC_IN_BOT ( scff_Wires[255] ) , .SC_OUT_TOP ( scff_Wires[256] ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[106] ) , @@ -148959,20 +152525,20 @@ cbx_1__1_ cbx_10__8_ ( .pReset_S_out ( pResetWires[443] ) , .pReset_E_out ( pResetWires[442] ) , .prog_clk_0_N_in ( prog_clk_0_wires[391] ) , .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_7241 ) , - .prog_clk_1_W_in ( p2516 ) , .prog_clk_1_E_in ( p462 ) , + .prog_clk_1_W_in ( p1513 ) , .prog_clk_1_E_in ( p462 ) , .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_7242 ) , .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_7243 ) , - .prog_clk_2_E_in ( p2863 ) , .prog_clk_2_W_in ( p2316 ) , + .prog_clk_2_E_in ( p3395 ) , .prog_clk_2_W_in ( p3314 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_7244 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_7245 ) , - .prog_clk_3_W_in ( p3330 ) , .prog_clk_3_E_in ( p1693 ) , + .prog_clk_3_W_in ( p3340 ) , .prog_clk_3_E_in ( p3376 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_7246 ) , - .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_7247 ) , .clk_1_W_in ( p1820 ) , - .clk_1_E_in ( p678 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_7248 ) , - .clk_1_S_out ( SYNOPSYS_UNCONNECTED_7249 ) , .clk_2_E_in ( p2863 ) , - .clk_2_W_in ( p3302 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7250 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7251 ) , .clk_3_W_in ( p2238 ) , - .clk_3_E_in ( p2751 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7252 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_7247 ) , .clk_1_W_in ( p1134 ) , + .clk_1_E_in ( p619 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_7248 ) , + .clk_1_S_out ( SYNOPSYS_UNCONNECTED_7249 ) , .clk_2_E_in ( p2748 ) , + .clk_2_W_in ( p3049 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7250 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7251 ) , .clk_3_W_in ( p3144 ) , + .clk_3_E_in ( p2745 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7252 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7253 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; cbx_1__1_ cbx_10__9_ ( .pReset ( { SYNOPSYS_UNCONNECTED_7254 } ) , @@ -148997,7 +152563,7 @@ cbx_1__1_ cbx_10__9_ ( .bottom_grid_pin_13_ ( cbx_1__1__107_bottom_grid_pin_13_ ) , .bottom_grid_pin_14_ ( cbx_1__1__107_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__107_bottom_grid_pin_15_ ) , - .ccff_tail ( cbx_1__1__107_ccff_tail ) , .SC_IN_TOP ( p2244 ) , + .ccff_tail ( cbx_1__1__107_ccff_tail ) , .SC_IN_TOP ( p1988 ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_7255 ) , .SC_IN_BOT ( scff_Wires[257] ) , .SC_OUT_TOP ( scff_Wires[258] ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[107] ) , @@ -149013,20 +152579,20 @@ cbx_1__1_ cbx_10__9_ ( .prog_clk_1_W_in ( prog_clk_1_wires[197] ) , .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_7259 ) , .prog_clk_1_N_out ( prog_clk_1_wires[201] ) , - .prog_clk_1_S_out ( prog_clk_1_wires[202] ) , .prog_clk_2_E_in ( p1479 ) , - .prog_clk_2_W_in ( p689 ) , + .prog_clk_1_S_out ( prog_clk_1_wires[202] ) , .prog_clk_2_E_in ( p1988 ) , + .prog_clk_2_W_in ( p2487 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_7260 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_7261 ) , - .prog_clk_3_W_in ( p1423 ) , .prog_clk_3_E_in ( p2050 ) , + .prog_clk_3_W_in ( p2599 ) , .prog_clk_3_E_in ( p1794 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_7262 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_7263 ) , .clk_1_W_in ( clk_1_wires[197] ) , .clk_1_E_in ( SYNOPSYS_UNCONNECTED_7264 ) , .clk_1_N_out ( clk_1_wires[201] ) , .clk_1_S_out ( clk_1_wires[202] ) , - .clk_2_E_in ( p1479 ) , .clk_2_W_in ( p2917 ) , + .clk_2_E_in ( p1827 ) , .clk_2_W_in ( p1833 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7265 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7266 ) , .clk_3_W_in ( p2952 ) , - .clk_3_E_in ( p1315 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7267 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7266 ) , .clk_3_W_in ( p1948 ) , + .clk_3_E_in ( p1873 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7267 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7268 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; cbx_1__1_ cbx_10__10_ ( .pReset ( { SYNOPSYS_UNCONNECTED_7269 } ) , @@ -149051,7 +152617,7 @@ cbx_1__1_ cbx_10__10_ ( .bottom_grid_pin_13_ ( cbx_1__1__108_bottom_grid_pin_13_ ) , .bottom_grid_pin_14_ ( cbx_1__1__108_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__108_bottom_grid_pin_15_ ) , - .ccff_tail ( cbx_1__1__108_ccff_tail ) , .SC_IN_TOP ( p1239 ) , + .ccff_tail ( cbx_1__1__108_ccff_tail ) , .SC_IN_TOP ( p1487 ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_7270 ) , .SC_IN_BOT ( scff_Wires[259] ) , .SC_OUT_TOP ( scff_Wires[260] ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[108] ) , @@ -149064,20 +152630,20 @@ cbx_1__1_ cbx_10__10_ ( .pReset_S_out ( pResetWires[541] ) , .pReset_E_out ( pResetWires[540] ) , .prog_clk_0_N_in ( prog_clk_0_wires[397] ) , .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_7273 ) , - .prog_clk_1_W_in ( p1233 ) , .prog_clk_1_E_in ( p1037 ) , + .prog_clk_1_W_in ( p1157 ) , .prog_clk_1_E_in ( p993 ) , .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_7274 ) , .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_7275 ) , - .prog_clk_2_E_in ( p1583 ) , .prog_clk_2_W_in ( p1373 ) , + .prog_clk_2_E_in ( p1293 ) , .prog_clk_2_W_in ( p1389 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_7276 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_7277 ) , - .prog_clk_3_W_in ( p1373 ) , .prog_clk_3_E_in ( p1239 ) , + .prog_clk_3_W_in ( p1389 ) , .prog_clk_3_E_in ( p1293 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_7278 ) , - .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_7279 ) , .clk_1_W_in ( p1467 ) , - .clk_1_E_in ( p853 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_7280 ) , - .clk_1_S_out ( SYNOPSYS_UNCONNECTED_7281 ) , .clk_2_E_in ( p1583 ) , - .clk_2_W_in ( p1373 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7282 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7283 ) , .clk_3_W_in ( p1373 ) , - .clk_3_E_in ( p1239 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7284 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_7279 ) , .clk_1_W_in ( p1389 ) , + .clk_1_E_in ( p835 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_7280 ) , + .clk_1_S_out ( SYNOPSYS_UNCONNECTED_7281 ) , .clk_2_E_in ( p1507 ) , + .clk_2_W_in ( p1389 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7282 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7283 ) , .clk_3_W_in ( p1389 ) , + .clk_3_E_in ( p1507 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7284 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7285 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; cbx_1__1_ cbx_10__11_ ( .pReset ( { SYNOPSYS_UNCONNECTED_7286 } ) , @@ -149102,7 +152668,7 @@ cbx_1__1_ cbx_10__11_ ( .bottom_grid_pin_13_ ( cbx_1__1__109_bottom_grid_pin_13_ ) , .bottom_grid_pin_14_ ( cbx_1__1__109_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__109_bottom_grid_pin_15_ ) , - .ccff_tail ( cbx_1__1__109_ccff_tail ) , .SC_IN_TOP ( p2125 ) , + .ccff_tail ( cbx_1__1__109_ccff_tail ) , .SC_IN_TOP ( p1485 ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_7287 ) , .SC_IN_BOT ( scff_Wires[261] ) , .SC_OUT_TOP ( scff_Wires[262] ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[109] ) , @@ -149118,20 +152684,20 @@ cbx_1__1_ cbx_10__11_ ( .prog_clk_1_W_in ( prog_clk_1_wires[204] ) , .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_7291 ) , .prog_clk_1_N_out ( prog_clk_1_wires[208] ) , - .prog_clk_1_S_out ( prog_clk_1_wires[209] ) , .prog_clk_2_E_in ( p1963 ) , - .prog_clk_2_W_in ( p1746 ) , + .prog_clk_1_S_out ( prog_clk_1_wires[209] ) , .prog_clk_2_E_in ( p1485 ) , + .prog_clk_2_W_in ( p1166 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_7292 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_7293 ) , - .prog_clk_3_W_in ( p3045 ) , .prog_clk_3_E_in ( p2125 ) , + .prog_clk_3_W_in ( p1166 ) , .prog_clk_3_E_in ( p1485 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_7294 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_7295 ) , .clk_1_W_in ( clk_1_wires[204] ) , .clk_1_E_in ( SYNOPSYS_UNCONNECTED_7296 ) , .clk_1_N_out ( clk_1_wires[208] ) , .clk_1_S_out ( clk_1_wires[209] ) , - .clk_2_E_in ( p1963 ) , .clk_2_W_in ( p3045 ) , + .clk_2_E_in ( p2196 ) , .clk_2_W_in ( p1244 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7297 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7298 ) , .clk_3_W_in ( p3070 ) , - .clk_3_E_in ( p2104 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7299 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7298 ) , .clk_3_W_in ( p1244 ) , + .clk_3_E_in ( p2235 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7299 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7300 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; cbx_1__1_ cbx_11__1_ ( .pReset ( { SYNOPSYS_UNCONNECTED_7301 } ) , @@ -149157,7 +152723,7 @@ cbx_1__1_ cbx_11__1_ ( .bottom_grid_pin_14_ ( cbx_1__1__110_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__110_bottom_grid_pin_15_ ) , .ccff_tail ( cbx_1__1__110_ccff_tail ) , .SC_IN_TOP ( scff_Wires[287] ) , - .SC_OUT_BOT ( scff_Wires[288] ) , .SC_IN_BOT ( p1433 ) , + .SC_OUT_BOT ( scff_Wires[288] ) , .SC_IN_BOT ( p1594 ) , .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_7302 ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[110] ) , .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[110] ) , @@ -149172,19 +152738,19 @@ cbx_1__1_ cbx_11__1_ ( .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_7306 ) , .prog_clk_1_E_in ( prog_clk_1_wires[212] ) , .prog_clk_1_N_out ( prog_clk_1_wires[213] ) , - .prog_clk_1_S_out ( prog_clk_1_wires[214] ) , .prog_clk_2_E_in ( p1901 ) , - .prog_clk_2_W_in ( p813 ) , + .prog_clk_1_S_out ( prog_clk_1_wires[214] ) , .prog_clk_2_E_in ( p2332 ) , + .prog_clk_2_W_in ( p2725 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_7307 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_7308 ) , - .prog_clk_3_W_in ( p2660 ) , .prog_clk_3_E_in ( p1896 ) , + .prog_clk_3_W_in ( p2773 ) , .prog_clk_3_E_in ( p2188 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_7309 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_7310 ) , .clk_1_W_in ( SYNOPSYS_UNCONNECTED_7311 ) , .clk_1_E_in ( clk_1_wires[212] ) , .clk_1_N_out ( clk_1_wires[213] ) , - .clk_1_S_out ( clk_1_wires[214] ) , .clk_2_E_in ( p1901 ) , - .clk_2_W_in ( p2914 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7312 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7313 ) , .clk_3_W_in ( p2951 ) , - .clk_3_E_in ( p1752 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7314 ) , + .clk_1_S_out ( clk_1_wires[214] ) , .clk_2_E_in ( p1317 ) , + .clk_2_W_in ( p1082 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7312 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7313 ) , .clk_3_W_in ( p1592 ) , + .clk_3_E_in ( p689 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7314 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7315 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; cbx_1__1_ cbx_11__2_ ( .pReset ( { SYNOPSYS_UNCONNECTED_7316 } ) , @@ -149210,7 +152776,7 @@ cbx_1__1_ cbx_11__2_ ( .bottom_grid_pin_14_ ( cbx_1__1__111_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__111_bottom_grid_pin_15_ ) , .ccff_tail ( cbx_1__1__111_ccff_tail ) , .SC_IN_TOP ( scff_Wires[285] ) , - .SC_OUT_BOT ( scff_Wires[286] ) , .SC_IN_BOT ( p2127 ) , + .SC_OUT_BOT ( scff_Wires[286] ) , .SC_IN_BOT ( p1464 ) , .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_7317 ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[111] ) , .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[111] ) , @@ -149222,23 +152788,23 @@ cbx_1__1_ cbx_11__2_ ( .pReset_S_out ( pResetWires[153] ) , .pReset_E_out ( pResetWires[152] ) , .prog_clk_0_N_in ( prog_clk_0_wires[411] ) , .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_7320 ) , - .prog_clk_1_W_in ( p1399 ) , .prog_clk_1_E_in ( p1737 ) , + .prog_clk_1_W_in ( p1162 ) , .prog_clk_1_E_in ( p718 ) , .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_7321 ) , .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_7322 ) , .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_7323 ) , .prog_clk_2_W_in ( prog_clk_2_wires[114] ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_7324 ) , - .prog_clk_2_E_out ( prog_clk_2_wires[113] ) , .prog_clk_3_W_in ( p1413 ) , - .prog_clk_3_E_in ( p1339 ) , + .prog_clk_2_E_out ( prog_clk_2_wires[113] ) , .prog_clk_3_W_in ( p1162 ) , + .prog_clk_3_E_in ( p722 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_7325 ) , - .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_7326 ) , .clk_1_W_in ( p1453 ) , - .clk_1_E_in ( p2066 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_7327 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_7326 ) , .clk_1_W_in ( p1162 ) , + .clk_1_E_in ( p1848 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_7327 ) , .clk_1_S_out ( SYNOPSYS_UNCONNECTED_7328 ) , .clk_2_E_in ( SYNOPSYS_UNCONNECTED_7329 ) , .clk_2_W_in ( clk_2_wires[114] ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7330 ) , - .clk_2_E_out ( clk_2_wires[113] ) , .clk_3_W_in ( p1413 ) , - .clk_3_E_in ( p1724 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7331 ) , + .clk_2_E_out ( clk_2_wires[113] ) , .clk_3_W_in ( p1851 ) , + .clk_3_E_in ( p1764 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7331 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7332 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; cbx_1__1_ cbx_11__3_ ( .pReset ( { SYNOPSYS_UNCONNECTED_7333 } ) , @@ -149264,7 +152830,7 @@ cbx_1__1_ cbx_11__3_ ( .bottom_grid_pin_14_ ( cbx_1__1__112_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__112_bottom_grid_pin_15_ ) , .ccff_tail ( cbx_1__1__112_ccff_tail ) , .SC_IN_TOP ( scff_Wires[283] ) , - .SC_OUT_BOT ( scff_Wires[284] ) , .SC_IN_BOT ( p1603 ) , + .SC_OUT_BOT ( scff_Wires[284] ) , .SC_IN_BOT ( p2022 ) , .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_7334 ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[112] ) , .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[112] ) , @@ -149279,19 +152845,19 @@ cbx_1__1_ cbx_11__3_ ( .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_7338 ) , .prog_clk_1_E_in ( prog_clk_1_wires[219] ) , .prog_clk_1_N_out ( prog_clk_1_wires[220] ) , - .prog_clk_1_S_out ( prog_clk_1_wires[221] ) , .prog_clk_2_E_in ( p2507 ) , - .prog_clk_2_W_in ( p1204 ) , + .prog_clk_1_S_out ( prog_clk_1_wires[221] ) , .prog_clk_2_E_in ( p2236 ) , + .prog_clk_2_W_in ( p3034 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_7339 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_7340 ) , - .prog_clk_3_W_in ( p2953 ) , .prog_clk_3_E_in ( p607 ) , + .prog_clk_3_W_in ( p3143 ) , .prog_clk_3_E_in ( p2181 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_7341 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_7342 ) , .clk_1_W_in ( SYNOPSYS_UNCONNECTED_7343 ) , .clk_1_E_in ( clk_1_wires[219] ) , .clk_1_N_out ( clk_1_wires[220] ) , - .clk_1_S_out ( clk_1_wires[221] ) , .clk_2_E_in ( p2507 ) , - .clk_2_W_in ( p2913 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7344 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7345 ) , .clk_3_W_in ( p1888 ) , - .clk_3_E_in ( p2383 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7346 ) , + .clk_1_S_out ( clk_1_wires[221] ) , .clk_2_E_in ( p2042 ) , + .clk_2_W_in ( p2734 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7344 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7345 ) , .clk_3_W_in ( p2676 ) , + .clk_3_E_in ( p1786 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7346 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7347 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; cbx_1__1_ cbx_11__4_ ( .pReset ( { SYNOPSYS_UNCONNECTED_7348 } ) , @@ -149317,7 +152883,7 @@ cbx_1__1_ cbx_11__4_ ( .bottom_grid_pin_14_ ( cbx_1__1__113_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__113_bottom_grid_pin_15_ ) , .ccff_tail ( cbx_1__1__113_ccff_tail ) , .SC_IN_TOP ( scff_Wires[281] ) , - .SC_OUT_BOT ( scff_Wires[282] ) , .SC_IN_BOT ( p1143 ) , + .SC_OUT_BOT ( scff_Wires[282] ) , .SC_IN_BOT ( p1974 ) , .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_7349 ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[113] ) , .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[113] ) , @@ -149329,23 +152895,23 @@ cbx_1__1_ cbx_11__4_ ( .pReset_S_out ( pResetWires[251] ) , .pReset_E_out ( pResetWires[250] ) , .prog_clk_0_N_in ( prog_clk_0_wires[417] ) , .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_7352 ) , - .prog_clk_1_W_in ( p1504 ) , .prog_clk_1_E_in ( p2380 ) , + .prog_clk_1_W_in ( p1333 ) , .prog_clk_1_E_in ( p1835 ) , .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_7353 ) , .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_7354 ) , .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_7355 ) , .prog_clk_2_W_in ( prog_clk_2_wires[119] ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_7356 ) , - .prog_clk_2_E_out ( prog_clk_2_wires[118] ) , .prog_clk_3_W_in ( p1306 ) , - .prog_clk_3_E_in ( p541 ) , + .prog_clk_2_E_out ( prog_clk_2_wires[118] ) , .prog_clk_3_W_in ( p1243 ) , + .prog_clk_3_E_in ( p1242 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_7357 ) , - .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_7358 ) , .clk_1_W_in ( p1473 ) , - .clk_1_E_in ( p1023 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_7359 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_7358 ) , .clk_1_W_in ( p1243 ) , + .clk_1_E_in ( p2477 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_7359 ) , .clk_1_S_out ( SYNOPSYS_UNCONNECTED_7360 ) , .clk_2_E_in ( SYNOPSYS_UNCONNECTED_7361 ) , .clk_2_W_in ( clk_2_wires[119] ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7362 ) , - .clk_2_E_out ( clk_2_wires[118] ) , .clk_3_W_in ( p1306 ) , - .clk_3_E_in ( p2276 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7363 ) , + .clk_2_E_out ( clk_2_wires[118] ) , .clk_3_W_in ( p1243 ) , + .clk_3_E_in ( p2457 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7363 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7364 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; cbx_1__1_ cbx_11__5_ ( .pReset ( { SYNOPSYS_UNCONNECTED_7365 } ) , @@ -149371,7 +152937,7 @@ cbx_1__1_ cbx_11__5_ ( .bottom_grid_pin_14_ ( cbx_1__1__114_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__114_bottom_grid_pin_15_ ) , .ccff_tail ( cbx_1__1__114_ccff_tail ) , .SC_IN_TOP ( scff_Wires[279] ) , - .SC_OUT_BOT ( scff_Wires[280] ) , .SC_IN_BOT ( p2144 ) , + .SC_OUT_BOT ( scff_Wires[280] ) , .SC_IN_BOT ( p1372 ) , .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_7366 ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[114] ) , .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[114] ) , @@ -149386,19 +152952,19 @@ cbx_1__1_ cbx_11__5_ ( .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_7370 ) , .prog_clk_1_E_in ( prog_clk_1_wires[226] ) , .prog_clk_1_N_out ( prog_clk_1_wires[227] ) , - .prog_clk_1_S_out ( prog_clk_1_wires[228] ) , .prog_clk_2_E_in ( p2450 ) , - .prog_clk_2_W_in ( p1252 ) , + .prog_clk_1_S_out ( prog_clk_1_wires[228] ) , .prog_clk_2_E_in ( p3117 ) , + .prog_clk_2_W_in ( p3364 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_7371 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_7372 ) , - .prog_clk_3_W_in ( p2925 ) , .prog_clk_3_E_in ( p974 ) , + .prog_clk_3_W_in ( p3420 ) , .prog_clk_3_E_in ( p3094 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_7373 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_7374 ) , .clk_1_W_in ( SYNOPSYS_UNCONNECTED_7375 ) , .clk_1_E_in ( clk_1_wires[226] ) , .clk_1_N_out ( clk_1_wires[227] ) , - .clk_1_S_out ( clk_1_wires[228] ) , .clk_2_E_in ( p2450 ) , - .clk_2_W_in ( p2920 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7376 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7377 ) , .clk_3_W_in ( p2663 ) , - .clk_3_E_in ( p2377 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7378 ) , + .clk_1_S_out ( clk_1_wires[228] ) , .clk_2_E_in ( p1998 ) , + .clk_2_W_in ( p1402 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7376 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7377 ) , .clk_3_W_in ( p1045 ) , + .clk_3_E_in ( p1830 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7378 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7379 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; cbx_1__1_ cbx_11__6_ ( .pReset ( { SYNOPSYS_UNCONNECTED_7380 } ) , @@ -149424,7 +152990,7 @@ cbx_1__1_ cbx_11__6_ ( .bottom_grid_pin_14_ ( cbx_1__1__115_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__115_bottom_grid_pin_15_ ) , .ccff_tail ( cbx_1__1__115_ccff_tail ) , .SC_IN_TOP ( scff_Wires[277] ) , - .SC_OUT_BOT ( scff_Wires[278] ) , .SC_IN_BOT ( p1102 ) , + .SC_OUT_BOT ( scff_Wires[278] ) , .SC_IN_BOT ( p1585 ) , .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_7381 ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[115] ) , .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[115] ) , @@ -149436,20 +153002,20 @@ cbx_1__1_ cbx_11__6_ ( .pReset_S_out ( pResetWires[349] ) , .pReset_E_out ( pResetWires[348] ) , .prog_clk_0_N_in ( prog_clk_0_wires[423] ) , .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_7384 ) , - .prog_clk_1_W_in ( p2434 ) , .prog_clk_1_E_in ( p770 ) , + .prog_clk_1_W_in ( p1376 ) , .prog_clk_1_E_in ( p614 ) , .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_7385 ) , .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_7386 ) , - .prog_clk_2_E_in ( p2512 ) , .prog_clk_2_W_in ( p2348 ) , + .prog_clk_2_E_in ( p1896 ) , .prog_clk_2_W_in ( p2743 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_7387 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_7388 ) , - .prog_clk_3_W_in ( p1881 ) , .prog_clk_3_E_in ( p1375 ) , + .prog_clk_3_W_in ( p2776 ) , .prog_clk_3_E_in ( p1834 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_7389 ) , - .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_7390 ) , .clk_1_W_in ( p1946 ) , - .clk_1_E_in ( p464 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_7391 ) , - .clk_1_S_out ( SYNOPSYS_UNCONNECTED_7392 ) , .clk_2_E_in ( p2512 ) , - .clk_2_W_in ( p2757 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7393 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7394 ) , .clk_3_W_in ( p2820 ) , - .clk_3_E_in ( p2375 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7395 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_7390 ) , .clk_1_W_in ( p2799 ) , + .clk_1_E_in ( p1135 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_7391 ) , + .clk_1_S_out ( SYNOPSYS_UNCONNECTED_7392 ) , .clk_2_E_in ( p1983 ) , + .clk_2_W_in ( p2915 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7393 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7394 ) , .clk_3_W_in ( p2977 ) , + .clk_3_E_in ( p1660 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7395 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7396 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; cbx_1__1_ cbx_11__7_ ( .pReset ( { SYNOPSYS_UNCONNECTED_7397 } ) , @@ -149475,7 +153041,7 @@ cbx_1__1_ cbx_11__7_ ( .bottom_grid_pin_14_ ( cbx_1__1__116_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__116_bottom_grid_pin_15_ ) , .ccff_tail ( cbx_1__1__116_ccff_tail ) , .SC_IN_TOP ( scff_Wires[275] ) , - .SC_OUT_BOT ( scff_Wires[276] ) , .SC_IN_BOT ( p1427 ) , + .SC_OUT_BOT ( scff_Wires[276] ) , .SC_IN_BOT ( p1355 ) , .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_7398 ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[116] ) , .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[116] ) , @@ -149490,19 +153056,19 @@ cbx_1__1_ cbx_11__7_ ( .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_7402 ) , .prog_clk_1_E_in ( prog_clk_1_wires[233] ) , .prog_clk_1_N_out ( prog_clk_1_wires[234] ) , - .prog_clk_1_S_out ( prog_clk_1_wires[235] ) , .prog_clk_2_E_in ( p1892 ) , - .prog_clk_2_W_in ( p1177 ) , + .prog_clk_1_S_out ( prog_clk_1_wires[235] ) , .prog_clk_2_E_in ( p3339 ) , + .prog_clk_2_W_in ( p2860 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_7403 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_7404 ) , - .prog_clk_3_W_in ( p3250 ) , .prog_clk_3_E_in ( p1146 ) , + .prog_clk_3_W_in ( p2947 ) , .prog_clk_3_E_in ( p3318 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_7405 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_7406 ) , .clk_1_W_in ( SYNOPSYS_UNCONNECTED_7407 ) , .clk_1_E_in ( clk_1_wires[233] ) , .clk_1_N_out ( clk_1_wires[234] ) , - .clk_1_S_out ( clk_1_wires[235] ) , .clk_2_E_in ( p1892 ) , - .clk_2_W_in ( p3236 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7408 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7409 ) , .clk_3_W_in ( p2686 ) , - .clk_3_E_in ( p1781 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7410 ) , + .clk_1_S_out ( clk_1_wires[235] ) , .clk_2_E_in ( p2590 ) , + .clk_2_W_in ( p3445 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7408 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7409 ) , .clk_3_W_in ( p3467 ) , + .clk_3_E_in ( p2500 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7410 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7411 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; cbx_1__1_ cbx_11__8_ ( .pReset ( { SYNOPSYS_UNCONNECTED_7412 } ) , @@ -149528,7 +153094,7 @@ cbx_1__1_ cbx_11__8_ ( .bottom_grid_pin_14_ ( cbx_1__1__117_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__117_bottom_grid_pin_15_ ) , .ccff_tail ( cbx_1__1__117_ccff_tail ) , .SC_IN_TOP ( scff_Wires[273] ) , - .SC_OUT_BOT ( scff_Wires[274] ) , .SC_IN_BOT ( p1601 ) , + .SC_OUT_BOT ( scff_Wires[274] ) , .SC_IN_BOT ( p2282 ) , .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_7413 ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[117] ) , .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[117] ) , @@ -149540,23 +153106,23 @@ cbx_1__1_ cbx_11__8_ ( .pReset_S_out ( pResetWires[447] ) , .pReset_E_out ( pResetWires[446] ) , .prog_clk_0_N_in ( prog_clk_0_wires[429] ) , .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_7416 ) , - .prog_clk_1_W_in ( p444 ) , .prog_clk_1_E_in ( p2358 ) , + .prog_clk_1_W_in ( p1620 ) , .prog_clk_1_E_in ( p2110 ) , .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_7417 ) , .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_7418 ) , .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_7419 ) , .prog_clk_2_W_in ( prog_clk_2_wires[126] ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_7420 ) , - .prog_clk_2_E_out ( prog_clk_2_wires[125] ) , .prog_clk_3_W_in ( p1460 ) , - .prog_clk_3_E_in ( p316 ) , + .prog_clk_2_E_out ( prog_clk_2_wires[125] ) , .prog_clk_3_W_in ( p1339 ) , + .prog_clk_3_E_in ( p1186 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_7421 ) , - .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_7422 ) , .clk_1_W_in ( p1284 ) , - .clk_1_E_in ( p423 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_7423 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_7422 ) , .clk_1_W_in ( p1104 ) , + .clk_1_E_in ( p1809 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_7423 ) , .clk_1_S_out ( SYNOPSYS_UNCONNECTED_7424 ) , .clk_2_E_in ( SYNOPSYS_UNCONNECTED_7425 ) , .clk_2_W_in ( clk_2_wires[126] ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7426 ) , - .clk_2_E_out ( clk_2_wires[125] ) , .clk_3_W_in ( p1460 ) , - .clk_3_E_in ( p2345 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7427 ) , + .clk_2_E_out ( clk_2_wires[125] ) , .clk_3_W_in ( p1339 ) , + .clk_3_E_in ( p1720 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7427 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7428 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; cbx_1__1_ cbx_11__9_ ( .pReset ( { SYNOPSYS_UNCONNECTED_7429 } ) , @@ -149582,7 +153148,7 @@ cbx_1__1_ cbx_11__9_ ( .bottom_grid_pin_14_ ( cbx_1__1__118_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__118_bottom_grid_pin_15_ ) , .ccff_tail ( cbx_1__1__118_ccff_tail ) , .SC_IN_TOP ( scff_Wires[271] ) , - .SC_OUT_BOT ( scff_Wires[272] ) , .SC_IN_BOT ( p1009 ) , + .SC_OUT_BOT ( scff_Wires[272] ) , .SC_IN_BOT ( p1377 ) , .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_7430 ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[118] ) , .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[118] ) , @@ -149597,19 +153163,19 @@ cbx_1__1_ cbx_11__9_ ( .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_7434 ) , .prog_clk_1_E_in ( prog_clk_1_wires[240] ) , .prog_clk_1_N_out ( prog_clk_1_wires[241] ) , - .prog_clk_1_S_out ( prog_clk_1_wires[242] ) , .prog_clk_2_E_in ( p1777 ) , - .prog_clk_2_W_in ( p1240 ) , + .prog_clk_1_S_out ( prog_clk_1_wires[242] ) , .prog_clk_2_E_in ( p2328 ) , + .prog_clk_2_W_in ( p3307 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_7435 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_7436 ) , - .prog_clk_3_W_in ( p3398 ) , .prog_clk_3_E_in ( p1381 ) , + .prog_clk_3_W_in ( p3352 ) , .prog_clk_3_E_in ( p2065 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_7437 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_7438 ) , .clk_1_W_in ( SYNOPSYS_UNCONNECTED_7439 ) , .clk_1_E_in ( clk_1_wires[240] ) , .clk_1_N_out ( clk_1_wires[241] ) , - .clk_1_S_out ( clk_1_wires[242] ) , .clk_2_E_in ( p1777 ) , - .clk_2_W_in ( p3385 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7440 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7441 ) , .clk_3_W_in ( p2521 ) , - .clk_3_E_in ( p1626 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7442 ) , + .clk_1_S_out ( clk_1_wires[242] ) , .clk_2_E_in ( p2595 ) , + .clk_2_W_in ( p3221 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7440 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7441 ) , .clk_3_W_in ( p3230 ) , + .clk_3_E_in ( p2482 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7442 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7443 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; cbx_1__1_ cbx_11__10_ ( .pReset ( { SYNOPSYS_UNCONNECTED_7444 } ) , @@ -149635,7 +153201,7 @@ cbx_1__1_ cbx_11__10_ ( .bottom_grid_pin_14_ ( cbx_1__1__119_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__119_bottom_grid_pin_15_ ) , .ccff_tail ( cbx_1__1__119_ccff_tail ) , .SC_IN_TOP ( scff_Wires[269] ) , - .SC_OUT_BOT ( scff_Wires[270] ) , .SC_IN_BOT ( p1077 ) , + .SC_OUT_BOT ( scff_Wires[270] ) , .SC_IN_BOT ( p1987 ) , .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_7445 ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[119] ) , .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[119] ) , @@ -149647,23 +153213,23 @@ cbx_1__1_ cbx_11__10_ ( .pReset_S_out ( pResetWires[545] ) , .pReset_E_out ( pResetWires[544] ) , .prog_clk_0_N_in ( prog_clk_0_wires[435] ) , .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_7448 ) , - .prog_clk_1_W_in ( p1874 ) , .prog_clk_1_E_in ( p497 ) , + .prog_clk_1_W_in ( p1298 ) , .prog_clk_1_E_in ( p1756 ) , .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_7449 ) , .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_7450 ) , .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_7451 ) , .prog_clk_2_W_in ( prog_clk_2_wires[133] ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_7452 ) , - .prog_clk_2_E_out ( prog_clk_2_wires[132] ) , .prog_clk_3_W_in ( p1874 ) , - .prog_clk_3_E_in ( p961 ) , + .prog_clk_2_E_out ( prog_clk_2_wires[132] ) , .prog_clk_3_W_in ( p1109 ) , + .prog_clk_3_E_in ( p601 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_7453 ) , - .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_7454 ) , .clk_1_W_in ( p1837 ) , - .clk_1_E_in ( p722 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_7455 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_7454 ) , .clk_1_W_in ( p1109 ) , + .clk_1_E_in ( p1820 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_7455 ) , .clk_1_S_out ( SYNOPSYS_UNCONNECTED_7456 ) , .clk_2_E_in ( SYNOPSYS_UNCONNECTED_7457 ) , .clk_2_W_in ( clk_2_wires[133] ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7458 ) , - .clk_2_E_out ( clk_2_wires[132] ) , .clk_3_W_in ( p1874 ) , - .clk_3_E_in ( p1481 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7459 ) , + .clk_2_E_out ( clk_2_wires[132] ) , .clk_3_W_in ( p1109 ) , + .clk_3_E_in ( p1795 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7459 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7460 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; cbx_1__1_ cbx_11__11_ ( .pReset ( { SYNOPSYS_UNCONNECTED_7461 } ) , @@ -149689,7 +153255,7 @@ cbx_1__1_ cbx_11__11_ ( .bottom_grid_pin_14_ ( cbx_1__1__120_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__120_bottom_grid_pin_15_ ) , .ccff_tail ( cbx_1__1__120_ccff_tail ) , .SC_IN_TOP ( scff_Wires[267] ) , - .SC_OUT_BOT ( scff_Wires[268] ) , .SC_IN_BOT ( p1300 ) , + .SC_OUT_BOT ( scff_Wires[268] ) , .SC_IN_BOT ( p1413 ) , .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_7462 ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[120] ) , .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[120] ) , @@ -149704,19 +153270,19 @@ cbx_1__1_ cbx_11__11_ ( .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_7466 ) , .prog_clk_1_E_in ( prog_clk_1_wires[247] ) , .prog_clk_1_N_out ( prog_clk_1_wires[248] ) , - .prog_clk_1_S_out ( prog_clk_1_wires[249] ) , .prog_clk_2_E_in ( p2107 ) , - .prog_clk_2_W_in ( p718 ) , + .prog_clk_1_S_out ( prog_clk_1_wires[249] ) , .prog_clk_2_E_in ( p3145 ) , + .prog_clk_2_W_in ( p1832 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_7467 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_7468 ) , - .prog_clk_3_W_in ( p1894 ) , .prog_clk_3_E_in ( p1232 ) , + .prog_clk_3_W_in ( p1889 ) , .prog_clk_3_E_in ( p3096 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_7469 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_7470 ) , .clk_1_W_in ( SYNOPSYS_UNCONNECTED_7471 ) , .clk_1_E_in ( clk_1_wires[247] ) , .clk_1_N_out ( clk_1_wires[248] ) , - .clk_1_S_out ( clk_1_wires[249] ) , .clk_2_E_in ( p2107 ) , - .clk_2_W_in ( p2369 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7472 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7473 ) , .clk_3_W_in ( p2428 ) , - .clk_3_E_in ( p2086 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7474 ) , + .clk_1_S_out ( clk_1_wires[249] ) , .clk_2_E_in ( p2534 ) , + .clk_2_W_in ( p3546 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7472 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7473 ) , .clk_3_W_in ( p3560 ) , + .clk_3_E_in ( p2502 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7474 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7475 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; cbx_1__1_ cbx_12__1_ ( .pReset ( { SYNOPSYS_UNCONNECTED_7476 } ) , @@ -149741,7 +153307,7 @@ cbx_1__1_ cbx_12__1_ ( .bottom_grid_pin_13_ ( cbx_1__1__121_bottom_grid_pin_13_ ) , .bottom_grid_pin_14_ ( cbx_1__1__121_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__121_bottom_grid_pin_15_ ) , - .ccff_tail ( cbx_1__1__121_ccff_tail ) , .SC_IN_TOP ( p1446 ) , + .ccff_tail ( cbx_1__1__121_ccff_tail ) , .SC_IN_TOP ( p1907 ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_7477 ) , .SC_IN_BOT ( scff_Wires[294] ) , .SC_OUT_TOP ( scff_Wires[295] ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[121] ) , @@ -149757,20 +153323,20 @@ cbx_1__1_ cbx_12__1_ ( .prog_clk_1_W_in ( prog_clk_1_wires[211] ) , .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_7481 ) , .prog_clk_1_N_out ( prog_clk_1_wires[215] ) , - .prog_clk_1_S_out ( prog_clk_1_wires[216] ) , .prog_clk_2_E_in ( p2185 ) , - .prog_clk_2_W_in ( p1323 ) , + .prog_clk_1_S_out ( prog_clk_1_wires[216] ) , .prog_clk_2_E_in ( p2764 ) , + .prog_clk_2_W_in ( p3033 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_7482 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_7483 ) , - .prog_clk_3_W_in ( p2325 ) , .prog_clk_3_E_in ( p1380 ) , + .prog_clk_3_W_in ( p3160 ) , .prog_clk_3_E_in ( p2728 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_7484 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_7485 ) , .clk_1_W_in ( clk_1_wires[211] ) , .clk_1_E_in ( SYNOPSYS_UNCONNECTED_7486 ) , .clk_1_N_out ( clk_1_wires[215] ) , .clk_1_S_out ( clk_1_wires[216] ) , - .clk_2_E_in ( p2185 ) , .clk_2_W_in ( p2401 ) , + .clk_2_E_in ( p2533 ) , .clk_2_W_in ( p3313 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7487 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7488 ) , .clk_3_W_in ( p1546 ) , - .clk_3_E_in ( p2054 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7489 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7488 ) , .clk_3_W_in ( p3319 ) , + .clk_3_E_in ( p2441 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7489 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7490 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; cbx_1__1_ cbx_12__2_ ( .pReset ( { SYNOPSYS_UNCONNECTED_7491 } ) , @@ -149795,7 +153361,7 @@ cbx_1__1_ cbx_12__2_ ( .bottom_grid_pin_13_ ( cbx_1__1__122_bottom_grid_pin_13_ ) , .bottom_grid_pin_14_ ( cbx_1__1__122_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__122_bottom_grid_pin_15_ ) , - .ccff_tail ( cbx_1__1__122_ccff_tail ) , .SC_IN_TOP ( p1593 ) , + .ccff_tail ( cbx_1__1__122_ccff_tail ) , .SC_IN_TOP ( p1965 ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_7492 ) , .SC_IN_BOT ( scff_Wires[296] ) , .SC_OUT_TOP ( scff_Wires[297] ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[122] ) , @@ -149808,20 +153374,20 @@ cbx_1__1_ cbx_12__2_ ( .pReset_S_out ( pResetWires[157] ) , .pReset_E_out ( pResetWires[156] ) , .prog_clk_0_N_in ( prog_clk_0_wires[449] ) , .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_7495 ) , - .prog_clk_1_W_in ( p2188 ) , .prog_clk_1_E_in ( p1117 ) , + .prog_clk_1_W_in ( p1226 ) , .prog_clk_1_E_in ( p325 ) , .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_7496 ) , .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_7497 ) , - .prog_clk_2_E_in ( p1774 ) , .prog_clk_2_W_in ( p2085 ) , + .prog_clk_2_E_in ( p1944 ) , .prog_clk_2_W_in ( p2430 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_7498 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_7499 ) , - .prog_clk_3_W_in ( p2464 ) , .prog_clk_3_E_in ( p1582 ) , + .prog_clk_3_W_in ( p2517 ) , .prog_clk_3_E_in ( p1708 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_7500 ) , - .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_7501 ) , .clk_1_W_in ( p1093 ) , - .clk_1_E_in ( p1000 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_7502 ) , - .clk_1_S_out ( SYNOPSYS_UNCONNECTED_7503 ) , .clk_2_E_in ( p1774 ) , - .clk_2_W_in ( p3037 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7504 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7505 ) , .clk_3_W_in ( p3111 ) , - .clk_3_E_in ( p1707 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7506 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_7501 ) , .clk_1_W_in ( p1891 ) , + .clk_1_E_in ( p586 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_7502 ) , + .clk_1_S_out ( SYNOPSYS_UNCONNECTED_7503 ) , .clk_2_E_in ( p2741 ) , + .clk_2_W_in ( p3070 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7504 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7505 ) , .clk_3_W_in ( p3115 ) , + .clk_3_E_in ( p2684 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7506 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7507 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; cbx_1__1_ cbx_12__3_ ( .pReset ( { SYNOPSYS_UNCONNECTED_7508 } ) , @@ -149846,7 +153412,7 @@ cbx_1__1_ cbx_12__3_ ( .bottom_grid_pin_13_ ( cbx_1__1__123_bottom_grid_pin_13_ ) , .bottom_grid_pin_14_ ( cbx_1__1__123_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__123_bottom_grid_pin_15_ ) , - .ccff_tail ( cbx_1__1__123_ccff_tail ) , .SC_IN_TOP ( p1515 ) , + .ccff_tail ( cbx_1__1__123_ccff_tail ) , .SC_IN_TOP ( p1527 ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_7509 ) , .SC_IN_BOT ( scff_Wires[298] ) , .SC_OUT_TOP ( scff_Wires[299] ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[123] ) , @@ -149862,20 +153428,20 @@ cbx_1__1_ cbx_12__3_ ( .prog_clk_1_W_in ( prog_clk_1_wires[218] ) , .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_7513 ) , .prog_clk_1_N_out ( prog_clk_1_wires[222] ) , - .prog_clk_1_S_out ( prog_clk_1_wires[223] ) , .prog_clk_2_E_in ( p1458 ) , - .prog_clk_2_W_in ( p970 ) , + .prog_clk_1_S_out ( prog_clk_1_wires[223] ) , .prog_clk_2_E_in ( p2969 ) , + .prog_clk_2_W_in ( p3481 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_7514 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_7515 ) , - .prog_clk_3_W_in ( p3450 ) , .prog_clk_3_E_in ( p935 ) , + .prog_clk_3_W_in ( p3500 ) , .prog_clk_3_E_in ( p2903 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_7516 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_7517 ) , .clk_1_W_in ( clk_1_wires[218] ) , .clk_1_E_in ( SYNOPSYS_UNCONNECTED_7518 ) , .clk_1_N_out ( clk_1_wires[222] ) , .clk_1_S_out ( clk_1_wires[223] ) , - .clk_2_E_in ( p1458 ) , .clk_2_W_in ( p3442 ) , + .clk_2_E_in ( p1884 ) , .clk_2_W_in ( p2494 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7519 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7520 ) , .clk_3_W_in ( p2793 ) , - .clk_3_E_in ( p604 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7521 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7520 ) , .clk_3_W_in ( p2592 ) , + .clk_3_E_in ( p1839 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7521 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7522 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; cbx_1__1_ cbx_12__4_ ( .pReset ( { SYNOPSYS_UNCONNECTED_7523 } ) , @@ -149900,7 +153466,7 @@ cbx_1__1_ cbx_12__4_ ( .bottom_grid_pin_13_ ( cbx_1__1__124_bottom_grid_pin_13_ ) , .bottom_grid_pin_14_ ( cbx_1__1__124_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__124_bottom_grid_pin_15_ ) , - .ccff_tail ( cbx_1__1__124_ccff_tail ) , .SC_IN_TOP ( p1862 ) , + .ccff_tail ( cbx_1__1__124_ccff_tail ) , .SC_IN_TOP ( p1939 ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_7524 ) , .SC_IN_BOT ( scff_Wires[300] ) , .SC_OUT_TOP ( scff_Wires[301] ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[124] ) , @@ -149913,20 +153479,20 @@ cbx_1__1_ cbx_12__4_ ( .pReset_S_out ( pResetWires[255] ) , .pReset_E_out ( pResetWires[254] ) , .prog_clk_0_N_in ( prog_clk_0_wires[455] ) , .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_7527 ) , - .prog_clk_1_W_in ( p2179 ) , .prog_clk_1_E_in ( p919 ) , + .prog_clk_1_W_in ( p1382 ) , .prog_clk_1_E_in ( p482 ) , .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_7528 ) , .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_7529 ) , - .prog_clk_2_E_in ( p1877 ) , .prog_clk_2_W_in ( p2101 ) , + .prog_clk_2_E_in ( p3018 ) , .prog_clk_2_W_in ( p3089 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_7530 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_7531 ) , - .prog_clk_3_W_in ( p3239 ) , .prog_clk_3_E_in ( p1757 ) , + .prog_clk_3_W_in ( p3125 ) , .prog_clk_3_E_in ( p2927 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_7532 ) , - .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_7533 ) , .clk_1_W_in ( p1542 ) , - .clk_1_E_in ( p517 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_7534 ) , - .clk_1_S_out ( SYNOPSYS_UNCONNECTED_7535 ) , .clk_2_E_in ( p1877 ) , - .clk_2_W_in ( p3210 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7536 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7537 ) , .clk_3_W_in ( p2855 ) , - .clk_3_E_in ( p1664 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7538 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_7533 ) , .clk_1_W_in ( p2349 ) , + .clk_1_E_in ( p547 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_7534 ) , + .clk_1_S_out ( SYNOPSYS_UNCONNECTED_7535 ) , .clk_2_E_in ( p2844 ) , + .clk_2_W_in ( p2889 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7536 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7537 ) , .clk_3_W_in ( p2955 ) , + .clk_3_E_in ( p2710 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7538 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7539 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; cbx_1__1_ cbx_12__5_ ( .pReset ( { SYNOPSYS_UNCONNECTED_7540 } ) , @@ -149951,7 +153517,7 @@ cbx_1__1_ cbx_12__5_ ( .bottom_grid_pin_13_ ( cbx_1__1__125_bottom_grid_pin_13_ ) , .bottom_grid_pin_14_ ( cbx_1__1__125_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__125_bottom_grid_pin_15_ ) , - .ccff_tail ( cbx_1__1__125_ccff_tail ) , .SC_IN_TOP ( p2132 ) , + .ccff_tail ( cbx_1__1__125_ccff_tail ) , .SC_IN_TOP ( p1904 ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_7541 ) , .SC_IN_BOT ( scff_Wires[302] ) , .SC_OUT_TOP ( scff_Wires[303] ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[125] ) , @@ -149967,20 +153533,20 @@ cbx_1__1_ cbx_12__5_ ( .prog_clk_1_W_in ( prog_clk_1_wires[225] ) , .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_7545 ) , .prog_clk_1_N_out ( prog_clk_1_wires[229] ) , - .prog_clk_1_S_out ( prog_clk_1_wires[230] ) , .prog_clk_2_E_in ( p2651 ) , - .prog_clk_2_W_in ( p548 ) , + .prog_clk_1_S_out ( prog_clk_1_wires[230] ) , .prog_clk_2_E_in ( p3416 ) , + .prog_clk_2_W_in ( p3567 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_7546 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_7547 ) , - .prog_clk_3_W_in ( p3314 ) , .prog_clk_3_E_in ( p2040 ) , + .prog_clk_3_W_in ( p3576 ) , .prog_clk_3_E_in ( p3388 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_7548 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_7549 ) , .clk_1_W_in ( clk_1_wires[225] ) , .clk_1_E_in ( SYNOPSYS_UNCONNECTED_7550 ) , .clk_1_N_out ( clk_1_wires[229] ) , .clk_1_S_out ( clk_1_wires[230] ) , - .clk_2_E_in ( p2651 ) , .clk_2_W_in ( p3303 ) , + .clk_2_E_in ( p2800 ) , .clk_2_W_in ( p1823 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7551 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7552 ) , .clk_3_W_in ( p2812 ) , - .clk_3_E_in ( p2576 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7553 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7552 ) , .clk_3_W_in ( p2016 ) , + .clk_3_E_in ( p2730 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7553 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7554 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; cbx_1__1_ cbx_12__6_ ( .pReset ( { SYNOPSYS_UNCONNECTED_7555 } ) , @@ -150005,7 +153571,7 @@ cbx_1__1_ cbx_12__6_ ( .bottom_grid_pin_13_ ( cbx_1__1__126_bottom_grid_pin_13_ ) , .bottom_grid_pin_14_ ( cbx_1__1__126_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__126_bottom_grid_pin_15_ ) , - .ccff_tail ( cbx_1__1__126_ccff_tail ) , .SC_IN_TOP ( p2124 ) , + .ccff_tail ( cbx_1__1__126_ccff_tail ) , .SC_IN_TOP ( p1632 ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_7556 ) , .SC_IN_BOT ( scff_Wires[304] ) , .SC_OUT_TOP ( scff_Wires[305] ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[126] ) , @@ -150018,20 +153584,20 @@ cbx_1__1_ cbx_12__6_ ( .pReset_S_out ( pResetWires[353] ) , .pReset_E_out ( pResetWires[352] ) , .prog_clk_0_N_in ( prog_clk_0_wires[461] ) , .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_7559 ) , - .prog_clk_1_W_in ( p2411 ) , .prog_clk_1_E_in ( p9 ) , + .prog_clk_1_W_in ( p1327 ) , .prog_clk_1_E_in ( p861 ) , .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_7560 ) , .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_7561 ) , - .prog_clk_2_E_in ( p1692 ) , .prog_clk_2_W_in ( p2370 ) , + .prog_clk_2_E_in ( p2345 ) , .prog_clk_2_W_in ( p3082 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_7562 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_7563 ) , - .prog_clk_3_W_in ( p3405 ) , .prog_clk_3_E_in ( p2064 ) , + .prog_clk_3_W_in ( p3124 ) , .prog_clk_3_E_in ( p2180 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_7564 ) , - .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_7565 ) , .clk_1_W_in ( p1561 ) , - .clk_1_E_in ( p418 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_7566 ) , - .clk_1_S_out ( SYNOPSYS_UNCONNECTED_7567 ) , .clk_2_E_in ( p1692 ) , - .clk_2_W_in ( p3383 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7568 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7569 ) , .clk_3_W_in ( p3067 ) , - .clk_3_E_in ( p1745 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7570 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_7565 ) , .clk_1_W_in ( p1209 ) , + .clk_1_E_in ( p980 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_7566 ) , + .clk_1_S_out ( SYNOPSYS_UNCONNECTED_7567 ) , .clk_2_E_in ( p2563 ) , + .clk_2_W_in ( p2918 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7568 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7569 ) , .clk_3_W_in ( p2995 ) , + .clk_3_E_in ( p2463 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7570 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7571 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; cbx_1__1_ cbx_12__7_ ( .pReset ( { SYNOPSYS_UNCONNECTED_7572 } ) , @@ -150056,7 +153622,7 @@ cbx_1__1_ cbx_12__7_ ( .bottom_grid_pin_13_ ( cbx_1__1__127_bottom_grid_pin_13_ ) , .bottom_grid_pin_14_ ( cbx_1__1__127_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__127_bottom_grid_pin_15_ ) , - .ccff_tail ( cbx_1__1__127_ccff_tail ) , .SC_IN_TOP ( p2255 ) , + .ccff_tail ( cbx_1__1__127_ccff_tail ) , .SC_IN_TOP ( p2277 ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_7573 ) , .SC_IN_BOT ( scff_Wires[306] ) , .SC_OUT_TOP ( scff_Wires[307] ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[127] ) , @@ -150072,20 +153638,20 @@ cbx_1__1_ cbx_12__7_ ( .prog_clk_1_W_in ( prog_clk_1_wires[232] ) , .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_7577 ) , .prog_clk_1_N_out ( prog_clk_1_wires[236] ) , - .prog_clk_1_S_out ( prog_clk_1_wires[237] ) , .prog_clk_2_E_in ( p2798 ) , - .prog_clk_2_W_in ( p791 ) , + .prog_clk_1_S_out ( prog_clk_1_wires[237] ) , .prog_clk_2_E_in ( p2826 ) , + .prog_clk_2_W_in ( p2440 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_7578 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_7579 ) , - .prog_clk_3_W_in ( p2968 ) , .prog_clk_3_E_in ( p2006 ) , + .prog_clk_3_W_in ( p2497 ) , .prog_clk_3_E_in ( p2674 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_7580 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_7581 ) , .clk_1_W_in ( clk_1_wires[232] ) , .clk_1_E_in ( SYNOPSYS_UNCONNECTED_7582 ) , .clk_1_N_out ( clk_1_wires[236] ) , .clk_1_S_out ( clk_1_wires[237] ) , - .clk_2_E_in ( p2798 ) , .clk_2_W_in ( p2868 ) , + .clk_2_E_in ( p2366 ) , .clk_2_W_in ( p3311 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7583 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7584 ) , .clk_3_W_in ( p2687 ) , - .clk_3_E_in ( p2766 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7585 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7584 ) , .clk_3_W_in ( p3356 ) , + .clk_3_E_in ( p2192 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7585 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7586 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; cbx_1__1_ cbx_12__8_ ( .pReset ( { SYNOPSYS_UNCONNECTED_7587 } ) , @@ -150110,7 +153676,7 @@ cbx_1__1_ cbx_12__8_ ( .bottom_grid_pin_13_ ( cbx_1__1__128_bottom_grid_pin_13_ ) , .bottom_grid_pin_14_ ( cbx_1__1__128_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__128_bottom_grid_pin_15_ ) , - .ccff_tail ( cbx_1__1__128_ccff_tail ) , .SC_IN_TOP ( p2688 ) , + .ccff_tail ( cbx_1__1__128_ccff_tail ) , .SC_IN_TOP ( p1905 ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_7588 ) , .SC_IN_BOT ( scff_Wires[308] ) , .SC_OUT_TOP ( scff_Wires[309] ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[128] ) , @@ -150123,20 +153689,20 @@ cbx_1__1_ cbx_12__8_ ( .pReset_S_out ( pResetWires[451] ) , .pReset_E_out ( pResetWires[450] ) , .prog_clk_0_N_in ( prog_clk_0_wires[467] ) , .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_7591 ) , - .prog_clk_1_W_in ( p2508 ) , .prog_clk_1_E_in ( p771 ) , + .prog_clk_1_W_in ( p1165 ) , .prog_clk_1_E_in ( p960 ) , .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_7592 ) , .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_7593 ) , - .prog_clk_2_E_in ( p2432 ) , .prog_clk_2_W_in ( p2320 ) , + .prog_clk_2_E_in ( p2034 ) , .prog_clk_2_W_in ( p1729 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_7594 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_7595 ) , - .prog_clk_3_W_in ( p2713 ) , .prog_clk_3_E_in ( p2548 ) , + .prog_clk_3_W_in ( p1960 ) , .prog_clk_3_E_in ( p1707 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_7596 ) , - .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_7597 ) , .clk_1_W_in ( p1363 ) , - .clk_1_E_in ( p272 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_7598 ) , - .clk_1_S_out ( SYNOPSYS_UNCONNECTED_7599 ) , .clk_2_E_in ( p2432 ) , - .clk_2_W_in ( p2608 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7600 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7601 ) , .clk_3_W_in ( p2591 ) , - .clk_3_E_in ( p2353 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7602 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_7597 ) , .clk_1_W_in ( p1427 ) , + .clk_1_E_in ( p381 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_7598 ) , + .clk_1_S_out ( SYNOPSYS_UNCONNECTED_7599 ) , .clk_2_E_in ( p1647 ) , + .clk_2_W_in ( p3432 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7600 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7601 ) , .clk_3_W_in ( p3452 ) , + .clk_3_E_in ( p1115 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7602 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7603 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; cbx_1__1_ cbx_12__9_ ( .pReset ( { SYNOPSYS_UNCONNECTED_7604 } ) , @@ -150161,7 +153727,7 @@ cbx_1__1_ cbx_12__9_ ( .bottom_grid_pin_13_ ( cbx_1__1__129_bottom_grid_pin_13_ ) , .bottom_grid_pin_14_ ( cbx_1__1__129_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__129_bottom_grid_pin_15_ ) , - .ccff_tail ( cbx_1__1__129_ccff_tail ) , .SC_IN_TOP ( p1406 ) , + .ccff_tail ( cbx_1__1__129_ccff_tail ) , .SC_IN_TOP ( p1348 ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_7605 ) , .SC_IN_BOT ( scff_Wires[310] ) , .SC_OUT_TOP ( scff_Wires[311] ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[129] ) , @@ -150177,20 +153743,20 @@ cbx_1__1_ cbx_12__9_ ( .prog_clk_1_W_in ( prog_clk_1_wires[239] ) , .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_7609 ) , .prog_clk_1_N_out ( prog_clk_1_wires[243] ) , - .prog_clk_1_S_out ( prog_clk_1_wires[244] ) , .prog_clk_2_E_in ( p2190 ) , - .prog_clk_2_W_in ( p679 ) , + .prog_clk_1_S_out ( prog_clk_1_wires[244] ) , .prog_clk_2_E_in ( p1728 ) , + .prog_clk_2_W_in ( p3216 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_7610 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_7611 ) , - .prog_clk_3_W_in ( p2861 ) , .prog_clk_3_E_in ( p1264 ) , + .prog_clk_3_W_in ( p3276 ) , .prog_clk_3_E_in ( p1869 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_7612 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_7613 ) , .clk_1_W_in ( clk_1_wires[239] ) , .clk_1_E_in ( SYNOPSYS_UNCONNECTED_7614 ) , .clk_1_N_out ( clk_1_wires[243] ) , .clk_1_S_out ( clk_1_wires[244] ) , - .clk_2_E_in ( p2190 ) , .clk_2_W_in ( p2904 ) , + .clk_2_E_in ( p2547 ) , .clk_2_W_in ( p3068 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7615 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7616 ) , .clk_3_W_in ( p2923 ) , - .clk_3_E_in ( p2029 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7617 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7616 ) , .clk_3_W_in ( p3132 ) , + .clk_3_E_in ( p2408 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7617 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7618 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; cbx_1__1_ cbx_12__10_ ( .pReset ( { SYNOPSYS_UNCONNECTED_7619 } ) , @@ -150215,7 +153781,7 @@ cbx_1__1_ cbx_12__10_ ( .bottom_grid_pin_13_ ( cbx_1__1__130_bottom_grid_pin_13_ ) , .bottom_grid_pin_14_ ( cbx_1__1__130_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__130_bottom_grid_pin_15_ ) , - .ccff_tail ( cbx_1__1__130_ccff_tail ) , .SC_IN_TOP ( p2252 ) , + .ccff_tail ( cbx_1__1__130_ccff_tail ) , .SC_IN_TOP ( p965 ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_7620 ) , .SC_IN_BOT ( scff_Wires[312] ) , .SC_OUT_TOP ( scff_Wires[313] ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[130] ) , @@ -150228,20 +153794,20 @@ cbx_1__1_ cbx_12__10_ ( .pReset_S_out ( pResetWires[549] ) , .pReset_E_out ( pResetWires[548] ) , .prog_clk_0_N_in ( prog_clk_0_wires[473] ) , .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_7623 ) , - .prog_clk_1_W_in ( p2366 ) , .prog_clk_1_E_in ( p405 ) , + .prog_clk_1_W_in ( p1356 ) , .prog_clk_1_E_in ( p941 ) , .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_7624 ) , .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_7625 ) , - .prog_clk_2_E_in ( p2600 ) , .prog_clk_2_W_in ( p2391 ) , + .prog_clk_2_E_in ( p2980 ) , .prog_clk_2_W_in ( p3223 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_7626 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_7627 ) , - .prog_clk_3_W_in ( p3319 ) , .prog_clk_3_E_in ( p2119 ) , + .prog_clk_3_W_in ( p3227 ) , .prog_clk_3_E_in ( p2904 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_7628 ) , - .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_7629 ) , .clk_1_W_in ( p1401 ) , - .clk_1_E_in ( p628 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_7630 ) , - .clk_1_S_out ( SYNOPSYS_UNCONNECTED_7631 ) , .clk_2_E_in ( p2600 ) , - .clk_2_W_in ( p3279 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7632 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7633 ) , .clk_3_W_in ( p3246 ) , - .clk_3_E_in ( p2562 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7634 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_7629 ) , .clk_1_W_in ( p1395 ) , + .clk_1_E_in ( p1236 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_7630 ) , + .clk_1_S_out ( SYNOPSYS_UNCONNECTED_7631 ) , .clk_2_E_in ( p2347 ) , + .clk_2_W_in ( p3387 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7632 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7633 ) , .clk_3_W_in ( p3413 ) , + .clk_3_E_in ( p2103 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7634 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7635 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; cbx_1__1_ cbx_12__11_ ( .pReset ( { SYNOPSYS_UNCONNECTED_7636 } ) , @@ -150266,7 +153832,7 @@ cbx_1__1_ cbx_12__11_ ( .bottom_grid_pin_13_ ( cbx_1__1__131_bottom_grid_pin_13_ ) , .bottom_grid_pin_14_ ( cbx_1__1__131_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__131_bottom_grid_pin_15_ ) , - .ccff_tail ( cbx_1__1__131_ccff_tail ) , .SC_IN_TOP ( p2114 ) , + .ccff_tail ( cbx_1__1__131_ccff_tail ) , .SC_IN_TOP ( p2231 ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_7637 ) , .SC_IN_BOT ( scff_Wires[314] ) , .SC_OUT_TOP ( scff_Wires[315] ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[131] ) , @@ -150282,20 +153848,20 @@ cbx_1__1_ cbx_12__11_ ( .prog_clk_1_W_in ( prog_clk_1_wires[246] ) , .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_7641 ) , .prog_clk_1_N_out ( prog_clk_1_wires[250] ) , - .prog_clk_1_S_out ( prog_clk_1_wires[251] ) , .prog_clk_2_E_in ( p2480 ) , - .prog_clk_2_W_in ( p1256 ) , + .prog_clk_1_S_out ( prog_clk_1_wires[251] ) , .prog_clk_2_E_in ( p2604 ) , + .prog_clk_2_W_in ( p2926 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_7642 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_7643 ) , - .prog_clk_3_W_in ( p2509 ) , .prog_clk_3_E_in ( p1974 ) , + .prog_clk_3_W_in ( p3012 ) , .prog_clk_3_E_in ( p2445 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_7644 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_7645 ) , .clk_1_W_in ( clk_1_wires[246] ) , .clk_1_E_in ( SYNOPSYS_UNCONNECTED_7646 ) , .clk_1_N_out ( clk_1_wires[250] ) , .clk_1_S_out ( clk_1_wires[251] ) , - .clk_2_E_in ( p2480 ) , .clk_2_W_in ( p2720 ) , + .clk_2_E_in ( p2847 ) , .clk_2_W_in ( p3199 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7647 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7648 ) , .clk_3_W_in ( p2823 ) , - .clk_3_E_in ( p2274 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7649 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7648 ) , .clk_3_W_in ( p3266 ) , + .clk_3_E_in ( p2693 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7649 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7650 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; cbx_1__2_ cbx_1__12_ ( .pReset ( { SYNOPSYS_UNCONNECTED_7651 } ) , @@ -150329,7 +153895,7 @@ cbx_1__2_ cbx_1__12_ ( .bottom_width_0_height_0__pin_1_upper ( grid_io_top_0_bottom_width_0_height_0__pin_1_upper ) , .bottom_width_0_height_0__pin_1_lower ( grid_io_top_0_bottom_width_0_height_0__pin_1_lower ) , .SC_IN_TOP ( scff_Wires[0] ) , .SC_OUT_BOT ( scff_Wires[1] ) , - .SC_IN_BOT ( p1216 ) , .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_7652 ) , + .SC_IN_BOT ( p1338 ) , .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_7652 ) , .pReset_E_in ( pResetWires[601] ) , .pReset_W_in ( SYNOPSYS_UNCONNECTED_7653 ) , .pReset_W_out ( pResetWires[600] ) , .pReset_S_out ( pResetWires[602] ) , @@ -150367,7 +153933,7 @@ cbx_1__2_ cbx_2__12_ ( .bottom_width_0_height_0__pin_0_ ( cbx_1__12__1_top_grid_pin_0_ ) , .bottom_width_0_height_0__pin_1_upper ( grid_io_top_1_bottom_width_0_height_0__pin_1_upper ) , .bottom_width_0_height_0__pin_1_lower ( grid_io_top_1_bottom_width_0_height_0__pin_1_lower ) , - .SC_IN_TOP ( p1789 ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_7656 ) , + .SC_IN_TOP ( p1639 ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_7656 ) , .SC_IN_BOT ( scff_Wires[51] ) , .SC_OUT_TOP ( scff_Wires[52] ) , .pReset_E_in ( pResetWires[605] ) , .pReset_W_in ( SYNOPSYS_UNCONNECTED_7657 ) , @@ -150408,7 +153974,7 @@ cbx_1__2_ cbx_3__12_ ( .bottom_width_0_height_0__pin_1_upper ( grid_io_top_2_bottom_width_0_height_0__pin_1_upper ) , .bottom_width_0_height_0__pin_1_lower ( grid_io_top_2_bottom_width_0_height_0__pin_1_lower ) , .SC_IN_TOP ( scff_Wires[53] ) , .SC_OUT_BOT ( scff_Wires[54] ) , - .SC_IN_BOT ( p1272 ) , .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_7661 ) , + .SC_IN_BOT ( p1606 ) , .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_7661 ) , .pReset_E_in ( pResetWires[608] ) , .pReset_W_in ( SYNOPSYS_UNCONNECTED_7662 ) , .pReset_W_out ( pResetWires[607] ) , .pReset_S_out ( pResetWires[609] ) , @@ -150447,7 +154013,7 @@ cbx_1__2_ cbx_4__12_ ( .bottom_width_0_height_0__pin_0_ ( cbx_1__12__3_top_grid_pin_0_ ) , .bottom_width_0_height_0__pin_1_upper ( grid_io_top_3_bottom_width_0_height_0__pin_1_upper ) , .bottom_width_0_height_0__pin_1_lower ( grid_io_top_3_bottom_width_0_height_0__pin_1_lower ) , - .SC_IN_TOP ( p1618 ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_7666 ) , + .SC_IN_TOP ( p1397 ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_7666 ) , .SC_IN_BOT ( scff_Wires[104] ) , .SC_OUT_TOP ( scff_Wires[105] ) , .pReset_E_in ( pResetWires[611] ) , .pReset_W_in ( SYNOPSYS_UNCONNECTED_7667 ) , @@ -150488,7 +154054,7 @@ cbx_1__2_ cbx_5__12_ ( .bottom_width_0_height_0__pin_1_upper ( grid_io_top_4_bottom_width_0_height_0__pin_1_upper ) , .bottom_width_0_height_0__pin_1_lower ( grid_io_top_4_bottom_width_0_height_0__pin_1_lower ) , .SC_IN_TOP ( scff_Wires[106] ) , .SC_OUT_BOT ( scff_Wires[107] ) , - .SC_IN_BOT ( p1199 ) , .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_7671 ) , + .SC_IN_BOT ( p1412 ) , .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_7671 ) , .pReset_E_in ( pResetWires[614] ) , .pReset_W_in ( SYNOPSYS_UNCONNECTED_7672 ) , .pReset_W_out ( pResetWires[613] ) , .pReset_S_out ( pResetWires[615] ) , @@ -150527,7 +154093,7 @@ cbx_1__2_ cbx_6__12_ ( .bottom_width_0_height_0__pin_0_ ( cbx_1__12__5_top_grid_pin_0_ ) , .bottom_width_0_height_0__pin_1_upper ( grid_io_top_5_bottom_width_0_height_0__pin_1_upper ) , .bottom_width_0_height_0__pin_1_lower ( grid_io_top_5_bottom_width_0_height_0__pin_1_lower ) , - .SC_IN_TOP ( p1560 ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_7676 ) , + .SC_IN_TOP ( p1252 ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_7676 ) , .SC_IN_BOT ( scff_Wires[157] ) , .SC_OUT_TOP ( scff_Wires[158] ) , .pReset_E_in ( pResetWires[617] ) , .pReset_W_in ( SYNOPSYS_UNCONNECTED_7677 ) , @@ -150568,7 +154134,7 @@ cbx_1__2_ cbx_7__12_ ( .bottom_width_0_height_0__pin_1_upper ( grid_io_top_6_bottom_width_0_height_0__pin_1_upper ) , .bottom_width_0_height_0__pin_1_lower ( grid_io_top_6_bottom_width_0_height_0__pin_1_lower ) , .SC_IN_TOP ( scff_Wires[159] ) , .SC_OUT_BOT ( scff_Wires[160] ) , - .SC_IN_BOT ( p1307 ) , .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_7681 ) , + .SC_IN_BOT ( p1461 ) , .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_7681 ) , .pReset_E_in ( SYNOPSYS_UNCONNECTED_7682 ) , .pReset_W_in ( pResetWires[619] ) , .pReset_W_out ( SYNOPSYS_UNCONNECTED_7683 ) , @@ -150607,7 +154173,7 @@ cbx_1__2_ cbx_8__12_ ( .bottom_width_0_height_0__pin_0_ ( cbx_1__12__7_top_grid_pin_0_ ) , .bottom_width_0_height_0__pin_1_upper ( grid_io_top_7_bottom_width_0_height_0__pin_1_upper ) , .bottom_width_0_height_0__pin_1_lower ( grid_io_top_7_bottom_width_0_height_0__pin_1_lower ) , - .SC_IN_TOP ( p1438 ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_7686 ) , + .SC_IN_TOP ( p1565 ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_7686 ) , .SC_IN_BOT ( scff_Wires[210] ) , .SC_OUT_TOP ( scff_Wires[211] ) , .pReset_E_in ( SYNOPSYS_UNCONNECTED_7687 ) , .pReset_W_in ( pResetWires[622] ) , @@ -150648,7 +154214,7 @@ cbx_1__2_ cbx_9__12_ ( .bottom_width_0_height_0__pin_1_upper ( grid_io_top_8_bottom_width_0_height_0__pin_1_upper ) , .bottom_width_0_height_0__pin_1_lower ( grid_io_top_8_bottom_width_0_height_0__pin_1_lower ) , .SC_IN_TOP ( scff_Wires[212] ) , .SC_OUT_BOT ( scff_Wires[213] ) , - .SC_IN_BOT ( p1396 ) , .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_7691 ) , + .SC_IN_BOT ( p1360 ) , .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_7691 ) , .pReset_E_in ( SYNOPSYS_UNCONNECTED_7692 ) , .pReset_W_in ( pResetWires[625] ) , .pReset_W_out ( SYNOPSYS_UNCONNECTED_7693 ) , @@ -150687,7 +154253,7 @@ cbx_1__2_ cbx_10__12_ ( .bottom_width_0_height_0__pin_0_ ( cbx_1__12__9_top_grid_pin_0_ ) , .bottom_width_0_height_0__pin_1_upper ( grid_io_top_9_bottom_width_0_height_0__pin_1_upper ) , .bottom_width_0_height_0__pin_1_lower ( grid_io_top_9_bottom_width_0_height_0__pin_1_lower ) , - .SC_IN_TOP ( p1434 ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_7696 ) , + .SC_IN_TOP ( p1642 ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_7696 ) , .SC_IN_BOT ( scff_Wires[263] ) , .SC_OUT_TOP ( scff_Wires[264] ) , .pReset_E_in ( SYNOPSYS_UNCONNECTED_7697 ) , .pReset_W_in ( pResetWires[628] ) , @@ -150728,7 +154294,7 @@ cbx_1__2_ cbx_11__12_ ( .bottom_width_0_height_0__pin_1_upper ( grid_io_top_10_bottom_width_0_height_0__pin_1_upper ) , .bottom_width_0_height_0__pin_1_lower ( grid_io_top_10_bottom_width_0_height_0__pin_1_lower ) , .SC_IN_TOP ( scff_Wires[265] ) , .SC_OUT_BOT ( scff_Wires[266] ) , - .SC_IN_BOT ( p1310 ) , .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_7701 ) , + .SC_IN_BOT ( p1480 ) , .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_7701 ) , .pReset_E_in ( SYNOPSYS_UNCONNECTED_7702 ) , .pReset_W_in ( pResetWires[631] ) , .pReset_W_out ( SYNOPSYS_UNCONNECTED_7703 ) , @@ -150767,7 +154333,7 @@ cbx_1__2_ cbx_12__12_ ( .bottom_width_0_height_0__pin_0_ ( cbx_1__12__11_top_grid_pin_0_ ) , .bottom_width_0_height_0__pin_1_upper ( grid_io_top_11_bottom_width_0_height_0__pin_1_upper ) , .bottom_width_0_height_0__pin_1_lower ( grid_io_top_11_bottom_width_0_height_0__pin_1_lower ) , - .SC_IN_TOP ( p1784 ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_7706 ) , + .SC_IN_TOP ( p1354 ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_7706 ) , .SC_IN_BOT ( scff_Wires[316] ) , .SC_OUT_TOP ( scff_Wires[317] ) , .pReset_E_in ( SYNOPSYS_UNCONNECTED_7707 ) , .pReset_W_in ( pResetWires[634] ) , @@ -151021,15 +154587,15 @@ cby_1__1_ cby_1__1_ ( .prog_clk_0_W_in ( prog_clk_0_wires[1] ) , .prog_clk_0_S_out ( prog_clk_0_wires[2] ) , .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_7732 ) , - .prog_clk_2_N_in ( p1955 ) , .prog_clk_2_S_in ( p775 ) , + .prog_clk_2_N_in ( p2253 ) , .prog_clk_2_S_in ( p663 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_7733 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_7734 ) , - .prog_clk_3_S_in ( p2955 ) , .prog_clk_3_N_in ( p1656 ) , + .prog_clk_3_S_in ( p2279 ) , .prog_clk_3_N_in ( p2062 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_7735 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_7736 ) , .clk_2_N_in ( p2139 ) , - .clk_2_S_in ( p3344 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_7737 ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_7738 ) , .clk_3_S_in ( p3363 ) , - .clk_3_N_in ( p2013 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_7739 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_7736 ) , .clk_2_N_in ( p1330 ) , + .clk_2_S_in ( p3056 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_7737 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_7738 ) , .clk_3_S_in ( p3137 ) , + .clk_3_N_in ( p1110 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_7739 ) , .clk_3_S_out ( SYNOPSYS_UNCONNECTED_7740 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; cby_1__1_ cby_1__2_ ( .pReset ( { SYNOPSYS_UNCONNECTED_7741 } ) , @@ -151076,14 +154642,14 @@ cby_1__1_ cby_1__2_ ( .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_7752 ) , .prog_clk_2_S_out ( prog_clk_2_wires[4] ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_7753 ) , - .prog_clk_3_S_in ( p1866 ) , .prog_clk_3_N_in ( p835 ) , + .prog_clk_3_S_in ( p2035 ) , .prog_clk_3_N_in ( p389 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_7754 ) , .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_7755 ) , .clk_2_N_in ( clk_2_wires[3] ) , .clk_2_S_in ( SYNOPSYS_UNCONNECTED_7756 ) , .clk_2_S_out ( clk_2_wires[4] ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_7757 ) , .clk_3_S_in ( p1866 ) , - .clk_3_N_in ( p89 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_7758 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_7757 ) , .clk_3_S_in ( p2035 ) , + .clk_3_N_in ( p883 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_7758 ) , .clk_3_S_out ( SYNOPSYS_UNCONNECTED_7759 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; cby_1__1_ cby_1__3_ ( .pReset ( { SYNOPSYS_UNCONNECTED_7760 } ) , @@ -151126,15 +154692,15 @@ cby_1__1_ cby_1__3_ ( .prog_clk_0_W_in ( prog_clk_0_wires[12] ) , .prog_clk_0_S_out ( prog_clk_0_wires[13] ) , .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_7770 ) , - .prog_clk_2_N_in ( p3171 ) , .prog_clk_2_S_in ( p934 ) , + .prog_clk_2_N_in ( p2275 ) , .prog_clk_2_S_in ( p679 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_7771 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_7772 ) , - .prog_clk_3_S_in ( p2665 ) , .prog_clk_3_N_in ( p3152 ) , + .prog_clk_3_S_in ( p2958 ) , .prog_clk_3_N_in ( p2155 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_7773 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_7774 ) , .clk_2_N_in ( p2960 ) , - .clk_2_S_in ( p2732 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_7775 ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_7776 ) , .clk_3_S_in ( p2814 ) , - .clk_3_N_in ( p2879 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_7777 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_7774 ) , .clk_2_N_in ( p3001 ) , + .clk_2_S_in ( p2892 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_7775 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_7776 ) , .clk_3_S_in ( p2956 ) , + .clk_3_N_in ( p2905 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_7777 ) , .clk_3_S_out ( SYNOPSYS_UNCONNECTED_7778 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; cby_1__1_ cby_1__4_ ( .pReset ( { SYNOPSYS_UNCONNECTED_7779 } ) , @@ -151181,14 +154747,14 @@ cby_1__1_ cby_1__4_ ( .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_7790 ) , .prog_clk_2_S_out ( prog_clk_2_wires[11] ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_7791 ) , - .prog_clk_3_S_in ( p2097 ) , .prog_clk_3_N_in ( p220 ) , + .prog_clk_3_S_in ( p1640 ) , .prog_clk_3_N_in ( p423 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_7792 ) , .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_7793 ) , .clk_2_N_in ( clk_2_wires[10] ) , .clk_2_S_in ( SYNOPSYS_UNCONNECTED_7794 ) , .clk_2_S_out ( clk_2_wires[11] ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_7795 ) , .clk_3_S_in ( p2097 ) , - .clk_3_N_in ( p490 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_7796 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_7795 ) , .clk_3_S_in ( p1640 ) , + .clk_3_N_in ( p950 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_7796 ) , .clk_3_S_out ( SYNOPSYS_UNCONNECTED_7797 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; cby_1__1_ cby_1__5_ ( .pReset ( { SYNOPSYS_UNCONNECTED_7798 } ) , @@ -151234,15 +154800,15 @@ cby_1__1_ cby_1__5_ ( .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_7809 ) , .prog_clk_2_S_in ( prog_clk_2_wires[8] ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_7810 ) , - .prog_clk_2_N_out ( prog_clk_2_wires[9] ) , .prog_clk_3_S_in ( p1951 ) , - .prog_clk_3_N_in ( p25 ) , + .prog_clk_2_N_out ( prog_clk_2_wires[9] ) , .prog_clk_3_S_in ( p2304 ) , + .prog_clk_3_N_in ( p91 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_7811 ) , .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_7812 ) , .clk_2_N_in ( SYNOPSYS_UNCONNECTED_7813 ) , .clk_2_S_in ( clk_2_wires[8] ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_7814 ) , - .clk_2_N_out ( clk_2_wires[9] ) , .clk_3_S_in ( p1834 ) , - .clk_3_N_in ( p682 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_7815 ) , + .clk_2_N_out ( clk_2_wires[9] ) , .clk_3_S_in ( p2304 ) , + .clk_3_N_in ( p1092 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_7815 ) , .clk_3_S_out ( SYNOPSYS_UNCONNECTED_7816 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; cby_1__1_ cby_1__6_ ( .pReset ( { SYNOPSYS_UNCONNECTED_7817 } ) , @@ -151285,15 +154851,15 @@ cby_1__1_ cby_1__6_ ( .prog_clk_0_W_in ( prog_clk_0_wires[27] ) , .prog_clk_0_S_out ( prog_clk_0_wires[28] ) , .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_7827 ) , - .prog_clk_2_N_in ( p2435 ) , .prog_clk_2_S_in ( p519 ) , + .prog_clk_2_N_in ( p2569 ) , .prog_clk_2_S_in ( p864 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_7828 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_7829 ) , - .prog_clk_3_S_in ( p2479 ) , .prog_clk_3_N_in ( p2365 ) , + .prog_clk_3_S_in ( p2642 ) , .prog_clk_3_N_in ( p2466 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_7830 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_7831 ) , .clk_2_N_in ( p3262 ) , - .clk_2_S_in ( p2355 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_7832 ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_7833 ) , .clk_3_S_in ( p1512 ) , - .clk_3_N_in ( p3222 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_7834 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_7831 ) , .clk_2_N_in ( p2586 ) , + .clk_2_S_in ( p3084 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_7832 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_7833 ) , .clk_3_S_in ( p3111 ) , + .clk_3_N_in ( p2415 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_7834 ) , .clk_3_S_out ( SYNOPSYS_UNCONNECTED_7835 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; cby_1__1_ cby_1__7_ ( .pReset ( { SYNOPSYS_UNCONNECTED_7836 } ) , @@ -151336,15 +154902,15 @@ cby_1__1_ cby_1__7_ ( .prog_clk_0_W_in ( prog_clk_0_wires[32] ) , .prog_clk_0_S_out ( prog_clk_0_wires[33] ) , .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_7846 ) , - .prog_clk_2_N_in ( p2449 ) , .prog_clk_2_S_in ( p488 ) , + .prog_clk_2_N_in ( p1523 ) , .prog_clk_2_S_in ( p570 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_7847 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_7848 ) , - .prog_clk_3_S_in ( p3372 ) , .prog_clk_3_N_in ( p2363 ) , + .prog_clk_3_S_in ( p1955 ) , .prog_clk_3_N_in ( p162 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_7849 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_7850 ) , .clk_2_N_in ( p2930 ) , - .clk_2_S_in ( p3337 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_7851 ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_7852 ) , .clk_3_S_in ( p2827 ) , - .clk_3_N_in ( p2908 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_7853 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_7850 ) , .clk_2_N_in ( p1900 ) , + .clk_2_S_in ( p2381 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_7851 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_7852 ) , .clk_3_S_in ( p2581 ) , + .clk_3_N_in ( p1730 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_7853 ) , .clk_3_S_out ( SYNOPSYS_UNCONNECTED_7854 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; cby_1__1_ cby_1__8_ ( .pReset ( { SYNOPSYS_UNCONNECTED_7855 } ) , @@ -151391,14 +154957,14 @@ cby_1__1_ cby_1__8_ ( .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_7866 ) , .prog_clk_2_S_out ( prog_clk_2_wires[18] ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_7867 ) , - .prog_clk_3_S_in ( p1602 ) , .prog_clk_3_N_in ( p1128 ) , + .prog_clk_3_S_in ( p1607 ) , .prog_clk_3_N_in ( p636 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_7868 ) , .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_7869 ) , .clk_2_N_in ( clk_2_wires[17] ) , .clk_2_S_in ( SYNOPSYS_UNCONNECTED_7870 ) , .clk_2_S_out ( clk_2_wires[18] ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_7871 ) , .clk_3_S_in ( p1602 ) , - .clk_3_N_in ( p491 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_7872 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_7871 ) , .clk_3_S_in ( p1607 ) , + .clk_3_N_in ( p1091 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_7872 ) , .clk_3_S_out ( SYNOPSYS_UNCONNECTED_7873 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; cby_1__1_ cby_1__9_ ( .pReset ( { SYNOPSYS_UNCONNECTED_7874 } ) , @@ -151444,15 +155010,15 @@ cby_1__1_ cby_1__9_ ( .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_7885 ) , .prog_clk_2_S_in ( prog_clk_2_wires[15] ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_7886 ) , - .prog_clk_2_N_out ( prog_clk_2_wires[16] ) , .prog_clk_3_S_in ( p1899 ) , - .prog_clk_3_N_in ( p445 ) , + .prog_clk_2_N_out ( prog_clk_2_wires[16] ) , .prog_clk_3_S_in ( p1337 ) , + .prog_clk_3_N_in ( p27 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_7887 ) , .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_7888 ) , .clk_2_N_in ( SYNOPSYS_UNCONNECTED_7889 ) , .clk_2_S_in ( clk_2_wires[15] ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_7890 ) , - .clk_2_N_out ( clk_2_wires[16] ) , .clk_3_S_in ( p1899 ) , - .clk_3_N_in ( p922 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_7891 ) , + .clk_2_N_out ( clk_2_wires[16] ) , .clk_3_S_in ( p1337 ) , + .clk_3_N_in ( p1170 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_7891 ) , .clk_3_S_out ( SYNOPSYS_UNCONNECTED_7892 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; cby_1__1_ cby_1__10_ ( .pReset ( { SYNOPSYS_UNCONNECTED_7893 } ) , @@ -151495,15 +155061,15 @@ cby_1__1_ cby_1__10_ ( .prog_clk_0_W_in ( prog_clk_0_wires[47] ) , .prog_clk_0_S_out ( prog_clk_0_wires[48] ) , .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_7903 ) , - .prog_clk_2_N_in ( p2860 ) , .prog_clk_2_S_in ( p876 ) , + .prog_clk_2_N_in ( p1390 ) , .prog_clk_2_S_in ( p908 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_7904 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_7905 ) , - .prog_clk_3_S_in ( p1545 ) , .prog_clk_3_N_in ( p2767 ) , + .prog_clk_3_S_in ( p3008 ) , .prog_clk_3_N_in ( p1008 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_7906 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_7907 ) , .clk_2_N_in ( p3064 ) , - .clk_2_S_in ( p3289 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_7908 ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_7909 ) , .clk_3_S_in ( p3315 ) , - .clk_3_N_in ( p3007 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_7910 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_7907 ) , .clk_2_N_in ( p2943 ) , + .clk_2_S_in ( p2883 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_7908 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_7909 ) , .clk_3_S_in ( p2278 ) , + .clk_3_N_in ( p2870 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_7910 ) , .clk_3_S_out ( SYNOPSYS_UNCONNECTED_7911 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; cby_1__1_ cby_1__11_ ( .pReset ( { SYNOPSYS_UNCONNECTED_7912 } ) , @@ -151549,15 +155115,15 @@ cby_1__1_ cby_1__11_ ( .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_7923 ) , .prog_clk_2_S_in ( prog_clk_2_wires[22] ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_7924 ) , - .prog_clk_2_N_out ( prog_clk_2_wires[23] ) , .prog_clk_3_S_in ( p1906 ) , - .prog_clk_3_N_in ( p138 ) , + .prog_clk_2_N_out ( prog_clk_2_wires[23] ) , .prog_clk_3_S_in ( p1546 ) , + .prog_clk_3_N_in ( p509 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_7925 ) , .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_7926 ) , .clk_2_N_in ( SYNOPSYS_UNCONNECTED_7927 ) , .clk_2_S_in ( clk_2_wires[22] ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_7928 ) , - .clk_2_N_out ( clk_2_wires[23] ) , .clk_3_S_in ( p1906 ) , - .clk_3_N_in ( p776 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_7929 ) , + .clk_2_N_out ( clk_2_wires[23] ) , .clk_3_S_in ( p1546 ) , + .clk_3_N_in ( p526 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_7929 ) , .clk_3_S_out ( SYNOPSYS_UNCONNECTED_7930 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; cby_1__1_ cby_1__12_ ( .pReset ( { SYNOPSYS_UNCONNECTED_7931 } ) , @@ -151599,16 +155165,16 @@ cby_1__1_ cby_1__12_ ( .Reset_E_out ( SYNOPSYS_UNCONNECTED_7940 ) , .prog_clk_0_W_in ( prog_clk_0_wires[57] ) , .prog_clk_0_S_out ( prog_clk_0_wires[58] ) , - .prog_clk_0_N_out ( prog_clk_0_wires[60] ) , .prog_clk_2_N_in ( p2831 ) , - .prog_clk_2_S_in ( p391 ) , + .prog_clk_0_N_out ( prog_clk_0_wires[60] ) , .prog_clk_2_N_in ( p2774 ) , + .prog_clk_2_S_in ( p1040 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_7941 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_7942 ) , - .prog_clk_3_S_in ( p2430 ) , .prog_clk_3_N_in ( p2726 ) , + .prog_clk_3_S_in ( p2837 ) , .prog_clk_3_N_in ( p2646 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_7943 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_7944 ) , .clk_2_N_in ( p3260 ) , - .clk_2_S_in ( p2283 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_7945 ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_7946 ) , .clk_3_S_in ( p2519 ) , - .clk_3_N_in ( p3223 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_7947 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_7944 ) , .clk_2_N_in ( p2562 ) , + .clk_2_S_in ( p2720 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_7945 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_7946 ) , .clk_3_S_in ( p349 ) , + .clk_3_N_in ( p2435 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_7947 ) , .clk_3_S_out ( SYNOPSYS_UNCONNECTED_7948 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; cby_1__1_ cby_2__1_ ( .pReset ( { SYNOPSYS_UNCONNECTED_7949 } ) , @@ -151651,15 +155217,15 @@ cby_1__1_ cby_2__1_ ( .prog_clk_0_W_in ( prog_clk_0_wires[64] ) , .prog_clk_0_S_out ( prog_clk_0_wires[65] ) , .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_7959 ) , - .prog_clk_2_N_in ( p2834 ) , .prog_clk_2_S_in ( p638 ) , + .prog_clk_2_N_in ( p1695 ) , .prog_clk_2_S_in ( p707 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_7960 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_7961 ) , - .prog_clk_3_S_in ( p2166 ) , .prog_clk_3_N_in ( p2765 ) , + .prog_clk_3_S_in ( p2944 ) , .prog_clk_3_N_in ( p1812 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_7962 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_7963 ) , .clk_2_N_in ( p2184 ) , - .clk_2_S_in ( p2538 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_7964 ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_7965 ) , .clk_3_S_in ( p2667 ) , - .clk_3_N_in ( p2046 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_7966 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_7963 ) , .clk_2_N_in ( p3242 ) , + .clk_2_S_in ( p2884 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_7964 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_7965 ) , .clk_3_S_in ( p2518 ) , + .clk_3_N_in ( p3172 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_7966 ) , .clk_3_S_out ( SYNOPSYS_UNCONNECTED_7967 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; cby_1__1_ cby_2__2_ ( .pReset ( { SYNOPSYS_UNCONNECTED_7968 } ) , @@ -151702,15 +155268,15 @@ cby_1__1_ cby_2__2_ ( .prog_clk_0_W_in ( prog_clk_0_wires[67] ) , .prog_clk_0_S_out ( prog_clk_0_wires[68] ) , .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_7978 ) , - .prog_clk_2_N_in ( p2406 ) , .prog_clk_2_S_in ( p1044 ) , + .prog_clk_2_N_in ( p2747 ) , .prog_clk_2_S_in ( p309 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_7979 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_7980 ) , - .prog_clk_3_S_in ( p2486 ) , .prog_clk_3_N_in ( p2376 ) , + .prog_clk_3_S_in ( p2843 ) , .prog_clk_3_N_in ( p2659 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_7981 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_7982 ) , .clk_2_N_in ( p3174 ) , - .clk_2_S_in ( p2291 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_7983 ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_7984 ) , .clk_3_S_in ( p1933 ) , - .clk_3_N_in ( p3120 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_7985 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_7982 ) , .clk_2_N_in ( p2545 ) , + .clk_2_S_in ( p3043 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_7983 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_7984 ) , .clk_3_S_in ( p3133 ) , + .clk_3_N_in ( p2418 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_7985 ) , .clk_3_S_out ( SYNOPSYS_UNCONNECTED_7986 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; cby_1__1_ cby_2__3_ ( .pReset ( { SYNOPSYS_UNCONNECTED_7987 } ) , @@ -151753,14 +155319,14 @@ cby_1__1_ cby_2__3_ ( .prog_clk_0_W_in ( prog_clk_0_wires[70] ) , .prog_clk_0_S_out ( prog_clk_0_wires[71] ) , .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_7997 ) , - .prog_clk_2_N_in ( p1484 ) , .prog_clk_2_S_in ( p820 ) , + .prog_clk_2_N_in ( p1946 ) , .prog_clk_2_S_in ( p785 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_7998 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_7999 ) , .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_8000 ) , .prog_clk_3_N_in ( prog_clk_3_wires[68] ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_8001 ) , - .prog_clk_3_S_out ( prog_clk_3_wires[69] ) , .clk_2_N_in ( p1484 ) , - .clk_2_S_in ( p375 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8002 ) , + .prog_clk_3_S_out ( prog_clk_3_wires[69] ) , .clk_2_N_in ( p1946 ) , + .clk_2_S_in ( p2 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8002 ) , .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8003 ) , .clk_3_S_in ( SYNOPSYS_UNCONNECTED_8004 ) , .clk_3_N_in ( clk_3_wires[68] ) , @@ -151807,14 +155373,14 @@ cby_1__1_ cby_2__4_ ( .prog_clk_0_W_in ( prog_clk_0_wires[73] ) , .prog_clk_0_S_out ( prog_clk_0_wires[74] ) , .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_8016 ) , - .prog_clk_2_N_in ( p1497 ) , .prog_clk_2_S_in ( p2596 ) , + .prog_clk_2_N_in ( p1292 ) , .prog_clk_2_S_in ( p335 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_8017 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_8018 ) , .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_8019 ) , .prog_clk_3_N_in ( prog_clk_3_wires[64] ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_8020 ) , - .prog_clk_3_S_out ( prog_clk_3_wires[65] ) , .clk_2_N_in ( p1497 ) , - .clk_2_S_in ( p2523 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8021 ) , + .prog_clk_3_S_out ( prog_clk_3_wires[65] ) , .clk_2_N_in ( p1292 ) , + .clk_2_S_in ( p2442 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8021 ) , .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8022 ) , .clk_3_S_in ( SYNOPSYS_UNCONNECTED_8023 ) , .clk_3_N_in ( clk_3_wires[64] ) , @@ -151861,14 +155427,14 @@ cby_1__1_ cby_2__5_ ( .prog_clk_0_W_in ( prog_clk_0_wires[76] ) , .prog_clk_0_S_out ( prog_clk_0_wires[77] ) , .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_8035 ) , - .prog_clk_2_N_in ( p1113 ) , .prog_clk_2_S_in ( p232 ) , + .prog_clk_2_N_in ( p1883 ) , .prog_clk_2_S_in ( p1747 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_8036 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_8037 ) , .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_8038 ) , .prog_clk_3_N_in ( prog_clk_3_wires[58] ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_8039 ) , - .prog_clk_3_S_out ( prog_clk_3_wires[59] ) , .clk_2_N_in ( p1113 ) , - .clk_2_S_in ( p330 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8040 ) , + .prog_clk_3_S_out ( prog_clk_3_wires[59] ) , .clk_2_N_in ( p1883 ) , + .clk_2_S_in ( p890 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8040 ) , .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8041 ) , .clk_3_S_in ( SYNOPSYS_UNCONNECTED_8042 ) , .clk_3_N_in ( clk_3_wires[58] ) , @@ -151915,14 +155481,14 @@ cby_1__1_ cby_2__6_ ( .prog_clk_0_W_in ( prog_clk_0_wires[79] ) , .prog_clk_0_S_out ( prog_clk_0_wires[80] ) , .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_8054 ) , - .prog_clk_2_N_in ( p1572 ) , .prog_clk_2_S_in ( p2599 ) , + .prog_clk_2_N_in ( p1914 ) , .prog_clk_2_S_in ( p1787 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_8055 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_8056 ) , .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_8057 ) , .prog_clk_3_N_in ( prog_clk_3_wires[54] ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_8058 ) , - .prog_clk_3_S_out ( prog_clk_3_wires[55] ) , .clk_2_N_in ( p1572 ) , - .clk_2_S_in ( p2741 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8059 ) , + .prog_clk_3_S_out ( prog_clk_3_wires[55] ) , .clk_2_N_in ( p1789 ) , + .clk_2_S_in ( p1746 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8059 ) , .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8060 ) , .clk_3_S_in ( SYNOPSYS_UNCONNECTED_8061 ) , .clk_3_N_in ( clk_3_wires[54] ) , @@ -151969,14 +155535,14 @@ cby_1__1_ cby_2__7_ ( .prog_clk_0_W_in ( prog_clk_0_wires[82] ) , .prog_clk_0_S_out ( prog_clk_0_wires[83] ) , .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_8073 ) , - .prog_clk_2_N_in ( p1594 ) , .prog_clk_2_S_in ( p1691 ) , + .prog_clk_2_N_in ( p1378 ) , .prog_clk_2_S_in ( p2143 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_8074 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_8075 ) , .prog_clk_3_S_in ( prog_clk_3_wires[52] ) , .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_8076 ) , .prog_clk_3_N_out ( prog_clk_3_wires[53] ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8077 ) , .clk_2_N_in ( p1594 ) , - .clk_2_S_in ( p2003 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8078 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8077 ) , .clk_2_N_in ( p1524 ) , + .clk_2_S_in ( p2073 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8078 ) , .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8079 ) , .clk_3_S_in ( clk_3_wires[52] ) , .clk_3_N_in ( SYNOPSYS_UNCONNECTED_8080 ) , @@ -152023,14 +155589,14 @@ cby_1__1_ cby_2__8_ ( .prog_clk_0_W_in ( prog_clk_0_wires[85] ) , .prog_clk_0_S_out ( prog_clk_0_wires[86] ) , .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_8092 ) , - .prog_clk_2_N_in ( p1297 ) , .prog_clk_2_S_in ( p2070 ) , + .prog_clk_2_N_in ( p991 ) , .prog_clk_2_S_in ( p168 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_8093 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_8094 ) , .prog_clk_3_S_in ( prog_clk_3_wires[56] ) , .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_8095 ) , .prog_clk_3_N_out ( prog_clk_3_wires[57] ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8096 ) , .clk_2_N_in ( p1297 ) , - .clk_2_S_in ( p1975 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8097 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8096 ) , .clk_2_N_in ( p1460 ) , + .clk_2_S_in ( p2129 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8097 ) , .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8098 ) , .clk_3_S_in ( clk_3_wires[56] ) , .clk_3_N_in ( SYNOPSYS_UNCONNECTED_8099 ) , @@ -152077,14 +155643,14 @@ cby_1__1_ cby_2__9_ ( .prog_clk_0_W_in ( prog_clk_0_wires[88] ) , .prog_clk_0_S_out ( prog_clk_0_wires[89] ) , .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_8111 ) , - .prog_clk_2_N_in ( p1362 ) , .prog_clk_2_S_in ( p443 ) , + .prog_clk_2_N_in ( p1416 ) , .prog_clk_2_S_in ( p1679 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_8112 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_8113 ) , .prog_clk_3_S_in ( prog_clk_3_wires[62] ) , .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_8114 ) , .prog_clk_3_N_out ( prog_clk_3_wires[63] ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8115 ) , .clk_2_N_in ( p1362 ) , - .clk_2_S_in ( p828 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8116 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8115 ) , .clk_2_N_in ( p1363 ) , + .clk_2_S_in ( p44 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8116 ) , .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8117 ) , .clk_3_S_in ( clk_3_wires[62] ) , .clk_3_N_in ( SYNOPSYS_UNCONNECTED_8118 ) , @@ -152131,14 +155697,14 @@ cby_1__1_ cby_2__10_ ( .prog_clk_0_W_in ( prog_clk_0_wires[91] ) , .prog_clk_0_S_out ( prog_clk_0_wires[92] ) , .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_8130 ) , - .prog_clk_2_N_in ( p1883 ) , .prog_clk_2_S_in ( p2074 ) , + .prog_clk_2_N_in ( p1359 ) , .prog_clk_2_S_in ( p988 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_8131 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_8132 ) , .prog_clk_3_S_in ( prog_clk_3_wires[66] ) , .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_8133 ) , .prog_clk_3_N_out ( prog_clk_3_wires[67] ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8134 ) , .clk_2_N_in ( p1883 ) , - .clk_2_S_in ( p2019 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8135 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8134 ) , .clk_2_N_in ( p1359 ) , + .clk_2_S_in ( p2697 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8135 ) , .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8136 ) , .clk_3_S_in ( clk_3_wires[66] ) , .clk_3_N_in ( SYNOPSYS_UNCONNECTED_8137 ) , @@ -152185,15 +155751,15 @@ cby_1__1_ cby_2__11_ ( .prog_clk_0_W_in ( prog_clk_0_wires[94] ) , .prog_clk_0_S_out ( prog_clk_0_wires[95] ) , .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_8149 ) , - .prog_clk_2_N_in ( p2096 ) , .prog_clk_2_S_in ( p800 ) , + .prog_clk_2_N_in ( p2025 ) , .prog_clk_2_S_in ( p1042 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_8150 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_8151 ) , - .prog_clk_3_S_in ( p2979 ) , .prog_clk_3_N_in ( p2067 ) , + .prog_clk_3_S_in ( p2532 ) , .prog_clk_3_N_in ( p1733 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_8152 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8153 ) , .clk_2_N_in ( p2807 ) , - .clk_2_S_in ( p2872 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8154 ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8155 ) , .clk_3_S_in ( p2819 ) , - .clk_3_N_in ( p2747 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8156 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8153 ) , .clk_2_N_in ( p3239 ) , + .clk_2_S_in ( p2425 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8154 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8155 ) , .clk_3_S_in ( p2033 ) , + .clk_3_N_in ( p3180 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8156 ) , .clk_3_S_out ( SYNOPSYS_UNCONNECTED_8157 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; cby_1__1_ cby_2__12_ ( .pReset ( { SYNOPSYS_UNCONNECTED_8158 } ) , @@ -152235,16 +155801,16 @@ cby_1__1_ cby_2__12_ ( .Reset_E_out ( SYNOPSYS_UNCONNECTED_8167 ) , .prog_clk_0_W_in ( prog_clk_0_wires[97] ) , .prog_clk_0_S_out ( prog_clk_0_wires[98] ) , - .prog_clk_0_N_out ( prog_clk_0_wires[100] ) , .prog_clk_2_N_in ( p2196 ) , - .prog_clk_2_S_in ( p901 ) , + .prog_clk_0_N_out ( prog_clk_0_wires[100] ) , .prog_clk_2_N_in ( p2204 ) , + .prog_clk_2_S_in ( p366 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_8168 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_8169 ) , - .prog_clk_3_S_in ( p2805 ) , .prog_clk_3_N_in ( p1968 ) , + .prog_clk_3_S_in ( p2639 ) , .prog_clk_3_N_in ( p2060 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_8170 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8171 ) , .clk_2_N_in ( p3080 ) , - .clk_2_S_in ( p3034 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8172 ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8173 ) , .clk_3_S_in ( p3087 ) , - .clk_3_N_in ( p2998 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8174 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8171 ) , .clk_2_N_in ( p2503 ) , + .clk_2_S_in ( p2472 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8172 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8173 ) , .clk_3_S_in ( p1989 ) , + .clk_3_N_in ( p2387 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8174 ) , .clk_3_S_out ( SYNOPSYS_UNCONNECTED_8175 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; cby_1__1_ cby_3__1_ ( .pReset ( { SYNOPSYS_UNCONNECTED_8176 } ) , @@ -152287,15 +155853,15 @@ cby_1__1_ cby_3__1_ ( .prog_clk_0_W_in ( prog_clk_0_wires[102] ) , .prog_clk_0_S_out ( prog_clk_0_wires[103] ) , .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_8186 ) , - .prog_clk_2_N_in ( p2262 ) , .prog_clk_2_S_in ( p793 ) , + .prog_clk_2_N_in ( p1857 ) , .prog_clk_2_S_in ( p45 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_8187 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_8188 ) , - .prog_clk_3_S_in ( p2257 ) , .prog_clk_3_N_in ( p2038 ) , + .prog_clk_3_S_in ( p2038 ) , .prog_clk_3_N_in ( p1755 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_8189 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8190 ) , .clk_2_N_in ( p2800 ) , - .clk_2_S_in ( p1988 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8191 ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8192 ) , .clk_3_S_in ( p1886 ) , - .clk_3_N_in ( p2716 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8193 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8190 ) , .clk_2_N_in ( p2752 ) , + .clk_2_S_in ( p3182 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8191 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8192 ) , .clk_3_S_in ( p3264 ) , + .clk_3_N_in ( p2654 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8193 ) , .clk_3_S_out ( SYNOPSYS_UNCONNECTED_8194 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; cby_1__1_ cby_3__2_ ( .pReset ( { SYNOPSYS_UNCONNECTED_8195 } ) , @@ -152342,14 +155908,14 @@ cby_1__1_ cby_3__2_ ( .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_8206 ) , .prog_clk_2_S_out ( prog_clk_2_wires[30] ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_8207 ) , - .prog_clk_3_S_in ( p2109 ) , .prog_clk_3_N_in ( p344 ) , + .prog_clk_3_S_in ( p2237 ) , .prog_clk_3_N_in ( p666 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_8208 ) , .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8209 ) , .clk_2_N_in ( clk_2_wires[29] ) , .clk_2_S_in ( SYNOPSYS_UNCONNECTED_8210 ) , .clk_2_S_out ( clk_2_wires[30] ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8211 ) , .clk_3_S_in ( p2109 ) , - .clk_3_N_in ( p738 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8212 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8211 ) , .clk_3_S_in ( p2237 ) , + .clk_3_N_in ( p970 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8212 ) , .clk_3_S_out ( SYNOPSYS_UNCONNECTED_8213 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; cby_1__1_ cby_3__3_ ( .pReset ( { SYNOPSYS_UNCONNECTED_8214 } ) , @@ -152392,15 +155958,15 @@ cby_1__1_ cby_3__3_ ( .prog_clk_0_W_in ( prog_clk_0_wires[108] ) , .prog_clk_0_S_out ( prog_clk_0_wires[109] ) , .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_8224 ) , - .prog_clk_2_N_in ( p1911 ) , .prog_clk_2_S_in ( p743 ) , + .prog_clk_2_N_in ( p2783 ) , .prog_clk_2_S_in ( p457 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_8225 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_8226 ) , - .prog_clk_3_S_in ( p2797 ) , .prog_clk_3_N_in ( p1638 ) , + .prog_clk_3_S_in ( p1575 ) , .prog_clk_3_N_in ( p2651 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_8227 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8228 ) , .clk_2_N_in ( p2400 ) , - .clk_2_S_in ( p2725 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8229 ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8230 ) , .clk_3_S_in ( p2268 ) , - .clk_3_N_in ( p2322 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8231 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8228 ) , .clk_2_N_in ( p2790 ) , + .clk_2_S_in ( p3044 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8229 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8230 ) , .clk_3_S_in ( p3127 ) , + .clk_3_N_in ( p2721 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8231 ) , .clk_3_S_out ( SYNOPSYS_UNCONNECTED_8232 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; cby_1__1_ cby_3__4_ ( .pReset ( { SYNOPSYS_UNCONNECTED_8233 } ) , @@ -152447,14 +156013,14 @@ cby_1__1_ cby_3__4_ ( .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_8244 ) , .prog_clk_2_S_out ( prog_clk_2_wires[41] ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_8245 ) , - .prog_clk_3_S_in ( p1547 ) , .prog_clk_3_N_in ( p369 ) , + .prog_clk_3_S_in ( p895 ) , .prog_clk_3_N_in ( p497 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_8246 ) , .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8247 ) , .clk_2_N_in ( clk_2_wires[40] ) , .clk_2_S_in ( SYNOPSYS_UNCONNECTED_8248 ) , .clk_2_S_out ( clk_2_wires[41] ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8249 ) , .clk_3_S_in ( p1547 ) , - .clk_3_N_in ( p198 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8250 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8249 ) , .clk_3_S_in ( p895 ) , + .clk_3_N_in ( p429 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8250 ) , .clk_3_S_out ( SYNOPSYS_UNCONNECTED_8251 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; cby_1__1_ cby_3__5_ ( .pReset ( { SYNOPSYS_UNCONNECTED_8252 } ) , @@ -152500,15 +156066,15 @@ cby_1__1_ cby_3__5_ ( .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_8263 ) , .prog_clk_2_S_in ( prog_clk_2_wires[38] ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_8264 ) , - .prog_clk_2_N_out ( prog_clk_2_wires[39] ) , .prog_clk_3_S_in ( p2131 ) , - .prog_clk_3_N_in ( p606 ) , + .prog_clk_2_N_out ( prog_clk_2_wires[39] ) , .prog_clk_3_S_in ( p1520 ) , + .prog_clk_3_N_in ( p642 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_8265 ) , .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8266 ) , .clk_2_N_in ( SYNOPSYS_UNCONNECTED_8267 ) , .clk_2_S_in ( clk_2_wires[38] ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8268 ) , - .clk_2_N_out ( clk_2_wires[39] ) , .clk_3_S_in ( p2131 ) , - .clk_3_N_in ( p88 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8269 ) , + .clk_2_N_out ( clk_2_wires[39] ) , .clk_3_S_in ( p1520 ) , + .clk_3_N_in ( p1215 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8269 ) , .clk_3_S_out ( SYNOPSYS_UNCONNECTED_8270 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; cby_1__1_ cby_3__6_ ( .pReset ( { SYNOPSYS_UNCONNECTED_8271 } ) , @@ -152551,15 +156117,15 @@ cby_1__1_ cby_3__6_ ( .prog_clk_0_W_in ( prog_clk_0_wires[117] ) , .prog_clk_0_S_out ( prog_clk_0_wires[118] ) , .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_8281 ) , - .prog_clk_2_N_in ( p1366 ) , .prog_clk_2_S_in ( p349 ) , + .prog_clk_2_N_in ( p2827 ) , .prog_clk_2_S_in ( p588 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_8282 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_8283 ) , - .prog_clk_3_S_in ( p2423 ) , .prog_clk_3_N_in ( p768 ) , + .prog_clk_3_S_in ( p1403 ) , .prog_clk_3_N_in ( p2703 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_8284 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8285 ) , .clk_2_N_in ( p2412 ) , - .clk_2_S_in ( p3237 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8286 ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8287 ) , .clk_3_S_in ( p3256 ) , - .clk_3_N_in ( p2351 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8288 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8285 ) , .clk_2_N_in ( p2963 ) , + .clk_2_S_in ( p2867 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8286 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8287 ) , .clk_3_S_in ( p2940 ) , + .clk_3_N_in ( p2866 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8288 ) , .clk_3_S_out ( SYNOPSYS_UNCONNECTED_8289 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; cby_1__1_ cby_3__7_ ( .pReset ( { SYNOPSYS_UNCONNECTED_8290 } ) , @@ -152602,15 +156168,15 @@ cby_1__1_ cby_3__7_ ( .prog_clk_0_W_in ( prog_clk_0_wires[120] ) , .prog_clk_0_S_out ( prog_clk_0_wires[121] ) , .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_8300 ) , - .prog_clk_2_N_in ( p2704 ) , .prog_clk_2_S_in ( p1750 ) , + .prog_clk_2_N_in ( p2003 ) , .prog_clk_2_S_in ( p2160 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_8301 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_8302 ) , - .prog_clk_3_S_in ( p1480 ) , .prog_clk_3_N_in ( p2553 ) , + .prog_clk_3_S_in ( p3170 ) , .prog_clk_3_N_in ( p1723 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_8303 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8304 ) , .clk_2_N_in ( p2707 ) , - .clk_2_S_in ( p2541 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8305 ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8306 ) , .clk_3_S_in ( p2641 ) , - .clk_3_N_in ( p2602 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8307 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8304 ) , .clk_2_N_in ( p2985 ) , + .clk_2_S_in ( p3055 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8305 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8306 ) , .clk_3_S_in ( p3153 ) , + .clk_3_N_in ( p2896 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8307 ) , .clk_3_S_out ( SYNOPSYS_UNCONNECTED_8308 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; cby_1__1_ cby_3__8_ ( .pReset ( { SYNOPSYS_UNCONNECTED_8309 } ) , @@ -152657,14 +156223,14 @@ cby_1__1_ cby_3__8_ ( .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_8320 ) , .prog_clk_2_S_out ( prog_clk_2_wires[54] ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_8321 ) , - .prog_clk_3_S_in ( p1474 ) , .prog_clk_3_N_in ( p576 ) , + .prog_clk_3_S_in ( p1455 ) , .prog_clk_3_N_in ( p1033 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_8322 ) , .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8323 ) , .clk_2_N_in ( clk_2_wires[53] ) , .clk_2_S_in ( SYNOPSYS_UNCONNECTED_8324 ) , .clk_2_S_out ( clk_2_wires[54] ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8325 ) , .clk_3_S_in ( p1474 ) , - .clk_3_N_in ( p885 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8326 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8325 ) , .clk_3_S_in ( p1455 ) , + .clk_3_N_in ( p752 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8326 ) , .clk_3_S_out ( SYNOPSYS_UNCONNECTED_8327 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; cby_1__1_ cby_3__9_ ( .pReset ( { SYNOPSYS_UNCONNECTED_8328 } ) , @@ -152710,15 +156276,15 @@ cby_1__1_ cby_3__9_ ( .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_8339 ) , .prog_clk_2_S_in ( prog_clk_2_wires[51] ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_8340 ) , - .prog_clk_2_N_out ( prog_clk_2_wires[52] ) , .prog_clk_3_S_in ( p1758 ) , - .prog_clk_3_N_in ( p525 ) , + .prog_clk_2_N_out ( prog_clk_2_wires[52] ) , .prog_clk_3_S_in ( p2014 ) , + .prog_clk_3_N_in ( p539 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_8341 ) , .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8342 ) , .clk_2_N_in ( SYNOPSYS_UNCONNECTED_8343 ) , .clk_2_S_in ( clk_2_wires[51] ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8344 ) , - .clk_2_N_out ( clk_2_wires[52] ) , .clk_3_S_in ( p1758 ) , - .clk_3_N_in ( p936 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8345 ) , + .clk_2_N_out ( clk_2_wires[52] ) , .clk_3_S_in ( p2014 ) , + .clk_3_N_in ( p652 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8345 ) , .clk_3_S_out ( SYNOPSYS_UNCONNECTED_8346 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; cby_1__1_ cby_3__10_ ( .pReset ( { SYNOPSYS_UNCONNECTED_8347 } ) , @@ -152761,15 +156327,15 @@ cby_1__1_ cby_3__10_ ( .prog_clk_0_W_in ( prog_clk_0_wires[129] ) , .prog_clk_0_S_out ( prog_clk_0_wires[130] ) , .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_8357 ) , - .prog_clk_2_N_in ( p2153 ) , .prog_clk_2_S_in ( p603 ) , + .prog_clk_2_N_in ( p2270 ) , .prog_clk_2_S_in ( p524 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_8358 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_8359 ) , - .prog_clk_3_S_in ( p2197 ) , .prog_clk_3_N_in ( p2057 ) , + .prog_clk_3_S_in ( p3028 ) , .prog_clk_3_N_in ( p2173 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_8360 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8361 ) , .clk_2_N_in ( p2382 ) , - .clk_2_S_in ( p3335 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8362 ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8363 ) , .clk_3_S_in ( p3361 ) , - .clk_3_N_in ( p2314 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8364 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8361 ) , .clk_2_N_in ( p2785 ) , + .clk_2_S_in ( p2872 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8362 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8363 ) , .clk_3_S_in ( p1525 ) , + .clk_3_N_in ( p2678 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8364 ) , .clk_3_S_out ( SYNOPSYS_UNCONNECTED_8365 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; cby_1__1_ cby_3__11_ ( .pReset ( { SYNOPSYS_UNCONNECTED_8366 } ) , @@ -152815,15 +156381,15 @@ cby_1__1_ cby_3__11_ ( .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_8377 ) , .prog_clk_2_S_in ( prog_clk_2_wires[64] ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_8378 ) , - .prog_clk_2_N_out ( prog_clk_2_wires[65] ) , .prog_clk_3_S_in ( p2160 ) , - .prog_clk_3_N_in ( p903 ) , + .prog_clk_2_N_out ( prog_clk_2_wires[65] ) , .prog_clk_3_S_in ( p1472 ) , + .prog_clk_3_N_in ( p760 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_8379 ) , .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8380 ) , .clk_2_N_in ( SYNOPSYS_UNCONNECTED_8381 ) , .clk_2_S_in ( clk_2_wires[64] ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8382 ) , - .clk_2_N_out ( clk_2_wires[65] ) , .clk_3_S_in ( p2160 ) , - .clk_3_N_in ( p572 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8383 ) , + .clk_2_N_out ( clk_2_wires[65] ) , .clk_3_S_in ( p1472 ) , + .clk_3_N_in ( p525 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8383 ) , .clk_3_S_out ( SYNOPSYS_UNCONNECTED_8384 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; cby_1__1_ cby_3__12_ ( .pReset ( { SYNOPSYS_UNCONNECTED_8385 } ) , @@ -152865,16 +156431,16 @@ cby_1__1_ cby_3__12_ ( .Reset_E_out ( SYNOPSYS_UNCONNECTED_8394 ) , .prog_clk_0_W_in ( prog_clk_0_wires[135] ) , .prog_clk_0_S_out ( prog_clk_0_wires[136] ) , - .prog_clk_0_N_out ( prog_clk_0_wires[138] ) , .prog_clk_2_N_in ( p2462 ) , - .prog_clk_2_S_in ( p707 ) , + .prog_clk_0_N_out ( prog_clk_0_wires[138] ) , .prog_clk_2_N_in ( p1836 ) , + .prog_clk_2_S_in ( p1024 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_8395 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_8396 ) , - .prog_clk_3_S_in ( p3247 ) , .prog_clk_3_N_in ( p2298 ) , + .prog_clk_3_S_in ( p3394 ) , .prog_clk_3_N_in ( p1740 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_8397 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8398 ) , .clk_2_N_in ( p3203 ) , - .clk_2_S_in ( p3299 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8399 ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8400 ) , .clk_3_S_in ( p3305 ) , - .clk_3_N_in ( p3113 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8401 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8398 ) , .clk_2_N_in ( p3095 ) , + .clk_2_S_in ( p3384 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8399 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8400 ) , .clk_3_S_in ( p1853 ) , + .clk_3_N_in ( p3074 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8401 ) , .clk_3_S_out ( SYNOPSYS_UNCONNECTED_8402 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; cby_1__1_ cby_4__1_ ( .pReset ( { SYNOPSYS_UNCONNECTED_8403 } ) , @@ -152917,15 +156483,15 @@ cby_1__1_ cby_4__1_ ( .prog_clk_0_W_in ( prog_clk_0_wires[140] ) , .prog_clk_0_S_out ( prog_clk_0_wires[141] ) , .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_8413 ) , - .prog_clk_2_N_in ( p2950 ) , .prog_clk_2_S_in ( p372 ) , + .prog_clk_2_N_in ( p2326 ) , .prog_clk_2_S_in ( p79 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_8414 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_8415 ) , - .prog_clk_3_S_in ( p2671 ) , .prog_clk_3_N_in ( p2877 ) , + .prog_clk_3_S_in ( p2829 ) , .prog_clk_3_N_in ( p2179 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_8416 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8417 ) , .clk_2_N_in ( p3255 ) , - .clk_2_S_in ( p2903 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8418 ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8419 ) , .clk_3_S_in ( p2946 ) , - .clk_3_N_in ( p3207 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8420 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8417 ) , .clk_2_N_in ( p2359 ) , + .clk_2_S_in ( p2661 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8418 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8419 ) , .clk_3_S_in ( p2606 ) , + .clk_3_N_in ( p2130 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8420 ) , .clk_3_S_out ( SYNOPSYS_UNCONNECTED_8421 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; cby_1__1_ cby_4__2_ ( .pReset ( { SYNOPSYS_UNCONNECTED_8422 } ) , @@ -152968,15 +156534,15 @@ cby_1__1_ cby_4__2_ ( .prog_clk_0_W_in ( prog_clk_0_wires[143] ) , .prog_clk_0_S_out ( prog_clk_0_wires[144] ) , .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_8432 ) , - .prog_clk_2_N_in ( p2228 ) , .prog_clk_2_S_in ( p282 ) , + .prog_clk_2_N_in ( p2254 ) , .prog_clk_2_S_in ( p995 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_8433 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_8434 ) , - .prog_clk_3_S_in ( p1935 ) , .prog_clk_3_N_in ( p2062 ) , + .prog_clk_3_S_in ( p3021 ) , .prog_clk_3_N_in ( p2075 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_8435 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8436 ) , .clk_2_N_in ( p2012 ) , - .clk_2_S_in ( p3151 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8437 ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8438 ) , .clk_3_S_in ( p3170 ) , - .clk_3_N_in ( p2083 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8439 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8436 ) , .clk_2_N_in ( p3126 ) , + .clk_2_S_in ( p2923 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8437 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8438 ) , .clk_3_S_in ( p2967 ) , + .clk_3_N_in ( p3036 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8439 ) , .clk_3_S_out ( SYNOPSYS_UNCONNECTED_8440 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; cby_1__1_ cby_4__3_ ( .pReset ( { SYNOPSYS_UNCONNECTED_8441 } ) , @@ -153019,14 +156585,14 @@ cby_1__1_ cby_4__3_ ( .prog_clk_0_W_in ( prog_clk_0_wires[146] ) , .prog_clk_0_S_out ( prog_clk_0_wires[147] ) , .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_8451 ) , - .prog_clk_2_N_in ( p2240 ) , .prog_clk_2_S_in ( p661 ) , + .prog_clk_2_N_in ( p1564 ) , .prog_clk_2_S_in ( p344 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_8452 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_8453 ) , .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_8454 ) , .prog_clk_3_N_in ( prog_clk_3_wires[24] ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_8455 ) , - .prog_clk_3_S_out ( prog_clk_3_wires[25] ) , .clk_2_N_in ( p2240 ) , - .clk_2_S_in ( p1059 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8456 ) , + .prog_clk_3_S_out ( prog_clk_3_wires[25] ) , .clk_2_N_in ( p1564 ) , + .clk_2_S_in ( p1083 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8456 ) , .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8457 ) , .clk_3_S_in ( SYNOPSYS_UNCONNECTED_8458 ) , .clk_3_N_in ( clk_3_wires[24] ) , @@ -153073,14 +156639,14 @@ cby_1__1_ cby_4__4_ ( .prog_clk_0_W_in ( prog_clk_0_wires[149] ) , .prog_clk_0_S_out ( prog_clk_0_wires[150] ) , .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_8470 ) , - .prog_clk_2_N_in ( p1596 ) , .prog_clk_2_S_in ( p1663 ) , + .prog_clk_2_N_in ( p1280 ) , .prog_clk_2_S_in ( p892 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_8471 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_8472 ) , .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_8473 ) , .prog_clk_3_N_in ( prog_clk_3_wires[20] ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_8474 ) , - .prog_clk_3_S_out ( prog_clk_3_wires[21] ) , .clk_2_N_in ( p1596 ) , - .clk_2_S_in ( p2313 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8475 ) , + .prog_clk_3_S_out ( prog_clk_3_wires[21] ) , .clk_2_N_in ( p1280 ) , + .clk_2_S_in ( p212 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8475 ) , .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8476 ) , .clk_3_S_in ( SYNOPSYS_UNCONNECTED_8477 ) , .clk_3_N_in ( clk_3_wires[20] ) , @@ -153127,14 +156693,14 @@ cby_1__1_ cby_4__5_ ( .prog_clk_0_W_in ( prog_clk_0_wires[152] ) , .prog_clk_0_S_out ( prog_clk_0_wires[153] ) , .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_8489 ) , - .prog_clk_2_N_in ( p1367 ) , .prog_clk_2_S_in ( p271 ) , + .prog_clk_2_N_in ( p1630 ) , .prog_clk_2_S_in ( p322 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_8490 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_8491 ) , .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_8492 ) , .prog_clk_3_N_in ( prog_clk_3_wires[14] ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_8493 ) , - .prog_clk_3_S_out ( prog_clk_3_wires[15] ) , .clk_2_N_in ( p1367 ) , - .clk_2_S_in ( p761 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8494 ) , + .prog_clk_3_S_out ( prog_clk_3_wires[15] ) , .clk_2_N_in ( p1630 ) , + .clk_2_S_in ( p1006 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8494 ) , .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8495 ) , .clk_3_S_in ( SYNOPSYS_UNCONNECTED_8496 ) , .clk_3_N_in ( clk_3_wires[14] ) , @@ -153181,14 +156747,14 @@ cby_1__1_ cby_4__6_ ( .prog_clk_0_W_in ( prog_clk_0_wires[155] ) , .prog_clk_0_S_out ( prog_clk_0_wires[156] ) , .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_8508 ) , - .prog_clk_2_N_in ( p1296 ) , .prog_clk_2_S_in ( p327 ) , + .prog_clk_2_N_in ( p2044 ) , .prog_clk_2_S_in ( p1775 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_8509 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_8510 ) , .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_8511 ) , .prog_clk_3_N_in ( prog_clk_3_wires[10] ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_8512 ) , - .prog_clk_3_S_out ( prog_clk_3_wires[11] ) , .clk_2_N_in ( p1296 ) , - .clk_2_S_in ( p456 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8513 ) , + .prog_clk_3_S_out ( prog_clk_3_wires[11] ) , .clk_2_N_in ( p2044 ) , + .clk_2_S_in ( p2099 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8513 ) , .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8514 ) , .clk_3_S_in ( SYNOPSYS_UNCONNECTED_8515 ) , .clk_3_N_in ( clk_3_wires[10] ) , @@ -153235,14 +156801,14 @@ cby_1__1_ cby_4__7_ ( .prog_clk_0_W_in ( prog_clk_0_wires[158] ) , .prog_clk_0_S_out ( prog_clk_0_wires[159] ) , .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_8527 ) , - .prog_clk_2_N_in ( p2223 ) , .prog_clk_2_S_in ( p2372 ) , + .prog_clk_2_N_in ( p2320 ) , .prog_clk_2_S_in ( p2409 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_8528 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_8529 ) , .prog_clk_3_S_in ( prog_clk_3_wires[8] ) , .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_8530 ) , .prog_clk_3_N_out ( prog_clk_3_wires[9] ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8531 ) , .clk_2_N_in ( p2223 ) , - .clk_2_S_in ( p2536 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8532 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8531 ) , .clk_2_N_in ( p2217 ) , + .clk_2_S_in ( p2469 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8532 ) , .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8533 ) , .clk_3_S_in ( clk_3_wires[8] ) , .clk_3_N_in ( SYNOPSYS_UNCONNECTED_8534 ) , @@ -153289,14 +156855,14 @@ cby_1__1_ cby_4__8_ ( .prog_clk_0_W_in ( prog_clk_0_wires[161] ) , .prog_clk_0_S_out ( prog_clk_0_wires[162] ) , .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_8546 ) , - .prog_clk_2_N_in ( p538 ) , .prog_clk_2_S_in ( p1979 ) , + .prog_clk_2_N_in ( p1256 ) , .prog_clk_2_S_in ( p1664 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_8547 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_8548 ) , .prog_clk_3_S_in ( prog_clk_3_wires[12] ) , .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_8549 ) , .prog_clk_3_N_out ( prog_clk_3_wires[13] ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8550 ) , .clk_2_N_in ( p538 ) , - .clk_2_S_in ( p2754 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8551 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8550 ) , .clk_2_N_in ( p1256 ) , + .clk_2_S_in ( p1727 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8551 ) , .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8552 ) , .clk_3_S_in ( clk_3_wires[12] ) , .clk_3_N_in ( SYNOPSYS_UNCONNECTED_8553 ) , @@ -153343,14 +156909,14 @@ cby_1__1_ cby_4__9_ ( .prog_clk_0_W_in ( prog_clk_0_wires[164] ) , .prog_clk_0_S_out ( prog_clk_0_wires[165] ) , .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_8565 ) , - .prog_clk_2_N_in ( p1904 ) , .prog_clk_2_S_in ( p1696 ) , + .prog_clk_2_N_in ( p1436 ) , .prog_clk_2_S_in ( p109 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_8566 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_8567 ) , .prog_clk_3_S_in ( prog_clk_3_wires[18] ) , .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_8568 ) , .prog_clk_3_N_out ( prog_clk_3_wires[19] ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8569 ) , .clk_2_N_in ( p1904 ) , - .clk_2_S_in ( p595 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8570 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8569 ) , .clk_2_N_in ( p1637 ) , + .clk_2_S_in ( p692 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8570 ) , .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8571 ) , .clk_3_S_in ( clk_3_wires[18] ) , .clk_3_N_in ( SYNOPSYS_UNCONNECTED_8572 ) , @@ -153397,14 +156963,14 @@ cby_1__1_ cby_4__10_ ( .prog_clk_0_W_in ( prog_clk_0_wires[167] ) , .prog_clk_0_S_out ( prog_clk_0_wires[168] ) , .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_8584 ) , - .prog_clk_2_N_in ( p1179 ) , .prog_clk_2_S_in ( p2306 ) , + .prog_clk_2_N_in ( p1111 ) , .prog_clk_2_S_in ( p2413 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_8585 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_8586 ) , .prog_clk_3_S_in ( prog_clk_3_wires[22] ) , .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_8587 ) , .prog_clk_3_N_out ( prog_clk_3_wires[23] ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8588 ) , .clk_2_N_in ( p1179 ) , - .clk_2_S_in ( p2545 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8589 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8588 ) , .clk_2_N_in ( p1111 ) , + .clk_2_S_in ( p2448 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8589 ) , .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8590 ) , .clk_3_S_in ( clk_3_wires[22] ) , .clk_3_N_in ( SYNOPSYS_UNCONNECTED_8591 ) , @@ -153451,15 +157017,15 @@ cby_1__1_ cby_4__11_ ( .prog_clk_0_W_in ( prog_clk_0_wires[170] ) , .prog_clk_0_S_out ( prog_clk_0_wires[171] ) , .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_8603 ) , - .prog_clk_2_N_in ( p2503 ) , .prog_clk_2_S_in ( p931 ) , + .prog_clk_2_N_in ( p2539 ) , .prog_clk_2_S_in ( p591 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_8604 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_8605 ) , - .prog_clk_3_S_in ( p1772 ) , .prog_clk_3_N_in ( p2293 ) , + .prog_clk_3_S_in ( p2792 ) , .prog_clk_3_N_in ( p2399 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_8606 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8607 ) , .clk_2_N_in ( p3079 ) , - .clk_2_S_in ( p2280 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8608 ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8609 ) , .clk_3_S_in ( p2498 ) , - .clk_3_N_in ( p3031 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8610 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8607 ) , .clk_2_N_in ( p1892 ) , + .clk_2_S_in ( p3302 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8608 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8609 ) , .clk_3_S_in ( p3350 ) , + .clk_3_N_in ( p1776 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8610 ) , .clk_3_S_out ( SYNOPSYS_UNCONNECTED_8611 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; cby_1__1_ cby_4__12_ ( .pReset ( { SYNOPSYS_UNCONNECTED_8612 } ) , @@ -153501,16 +157067,16 @@ cby_1__1_ cby_4__12_ ( .Reset_E_out ( SYNOPSYS_UNCONNECTED_8621 ) , .prog_clk_0_W_in ( prog_clk_0_wires[173] ) , .prog_clk_0_S_out ( prog_clk_0_wires[174] ) , - .prog_clk_0_N_out ( prog_clk_0_wires[176] ) , .prog_clk_2_N_in ( p1762 ) , - .prog_clk_2_S_in ( p622 ) , + .prog_clk_0_N_out ( prog_clk_0_wires[176] ) , .prog_clk_2_N_in ( p1862 ) , + .prog_clk_2_S_in ( p133 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_8622 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_8623 ) , - .prog_clk_3_S_in ( p2404 ) , .prog_clk_3_N_in ( p1754 ) , + .prog_clk_3_S_in ( p1868 ) , .prog_clk_3_N_in ( p1788 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_8624 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8625 ) , .clk_2_N_in ( p2396 ) , - .clk_2_S_in ( p2326 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8626 ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8627 ) , .clk_3_S_in ( p2415 ) , - .clk_3_N_in ( p2303 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8628 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8625 ) , .clk_2_N_in ( p2972 ) , + .clk_2_S_in ( p2468 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8626 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8627 ) , .clk_3_S_in ( p2600 ) , + .clk_3_N_in ( p2898 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8628 ) , .clk_3_S_out ( SYNOPSYS_UNCONNECTED_8629 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; cby_1__1_ cby_5__1_ ( .pReset ( { SYNOPSYS_UNCONNECTED_8630 } ) , @@ -153553,15 +157119,15 @@ cby_1__1_ cby_5__1_ ( .prog_clk_0_W_in ( prog_clk_0_wires[178] ) , .prog_clk_0_S_out ( prog_clk_0_wires[179] ) , .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_8640 ) , - .prog_clk_2_N_in ( p1869 ) , .prog_clk_2_S_in ( p41 ) , + .prog_clk_2_N_in ( p1901 ) , .prog_clk_2_S_in ( p17 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_8641 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_8642 ) , - .prog_clk_3_S_in ( p2976 ) , .prog_clk_3_N_in ( p1669 ) , + .prog_clk_3_S_in ( p2830 ) , .prog_clk_3_N_in ( p1666 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_8643 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8644 ) , .clk_2_N_in ( p2425 ) , - .clk_2_S_in ( p2881 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8645 ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8646 ) , .clk_3_S_in ( p2261 ) , - .clk_3_N_in ( p2299 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8647 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8644 ) , .clk_2_N_in ( p2242 ) , + .clk_2_S_in ( p2679 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8645 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8646 ) , .clk_3_S_in ( p2298 ) , + .clk_3_N_in ( p2146 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8647 ) , .clk_3_S_out ( SYNOPSYS_UNCONNECTED_8648 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; cby_1__1_ cby_5__2_ ( .pReset ( { SYNOPSYS_UNCONNECTED_8649 } ) , @@ -153608,14 +157174,14 @@ cby_1__1_ cby_5__2_ ( .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_8660 ) , .prog_clk_2_S_out ( prog_clk_2_wires[32] ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_8661 ) , - .prog_clk_3_S_in ( p2177 ) , .prog_clk_3_N_in ( p1115 ) , + .prog_clk_3_S_in ( p1917 ) , .prog_clk_3_N_in ( p399 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_8662 ) , .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8663 ) , .clk_2_N_in ( clk_2_wires[31] ) , .clk_2_S_in ( SYNOPSYS_UNCONNECTED_8664 ) , .clk_2_S_out ( clk_2_wires[32] ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8665 ) , .clk_3_S_in ( p2177 ) , - .clk_3_N_in ( p644 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8666 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8665 ) , .clk_3_S_in ( p1917 ) , + .clk_3_N_in ( p611 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8666 ) , .clk_3_S_out ( SYNOPSYS_UNCONNECTED_8667 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; cby_1__1_ cby_5__3_ ( .pReset ( { SYNOPSYS_UNCONNECTED_8668 } ) , @@ -153658,15 +157224,15 @@ cby_1__1_ cby_5__3_ ( .prog_clk_0_W_in ( prog_clk_0_wires[184] ) , .prog_clk_0_S_out ( prog_clk_0_wires[185] ) , .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_8678 ) , - .prog_clk_2_N_in ( p1863 ) , .prog_clk_2_S_in ( p400 ) , + .prog_clk_2_N_in ( p2286 ) , .prog_clk_2_S_in ( p496 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_8679 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_8680 ) , - .prog_clk_3_S_in ( p2852 ) , .prog_clk_3_N_in ( p1635 ) , + .prog_clk_3_S_in ( p1406 ) , .prog_clk_3_N_in ( p2159 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_8681 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8682 ) , .clk_2_N_in ( p2801 ) , - .clk_2_S_in ( p3112 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8683 ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8684 ) , .clk_3_S_in ( p3179 ) , - .clk_3_N_in ( p2722 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8685 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8682 ) , .clk_2_N_in ( p2769 ) , + .clk_2_S_in ( p1741 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8683 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8684 ) , .clk_3_S_in ( p1890 ) , + .clk_3_N_in ( p2687 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8685 ) , .clk_3_S_out ( SYNOPSYS_UNCONNECTED_8686 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; cby_1__1_ cby_5__4_ ( .pReset ( { SYNOPSYS_UNCONNECTED_8687 } ) , @@ -153713,14 +157279,14 @@ cby_1__1_ cby_5__4_ ( .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_8698 ) , .prog_clk_2_S_out ( prog_clk_2_wires[45] ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_8699 ) , - .prog_clk_3_S_in ( p1507 ) , .prog_clk_3_N_in ( p16 ) , + .prog_clk_3_S_in ( p1623 ) , .prog_clk_3_N_in ( p484 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_8700 ) , .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8701 ) , .clk_2_N_in ( clk_2_wires[44] ) , .clk_2_S_in ( SYNOPSYS_UNCONNECTED_8702 ) , .clk_2_S_out ( clk_2_wires[45] ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8703 ) , .clk_3_S_in ( p1507 ) , - .clk_3_N_in ( p642 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8704 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8703 ) , .clk_3_S_in ( p1623 ) , + .clk_3_N_in ( p822 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8704 ) , .clk_3_S_out ( SYNOPSYS_UNCONNECTED_8705 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; cby_1__1_ cby_5__5_ ( .pReset ( { SYNOPSYS_UNCONNECTED_8706 } ) , @@ -153766,15 +157332,15 @@ cby_1__1_ cby_5__5_ ( .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_8717 ) , .prog_clk_2_S_in ( prog_clk_2_wires[42] ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_8718 ) , - .prog_clk_2_N_out ( prog_clk_2_wires[43] ) , .prog_clk_3_S_in ( p2661 ) , - .prog_clk_3_N_in ( p582 ) , + .prog_clk_2_N_out ( prog_clk_2_wires[43] ) , .prog_clk_3_S_in ( p1888 ) , + .prog_clk_3_N_in ( p1180 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_8719 ) , .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8720 ) , .clk_2_N_in ( SYNOPSYS_UNCONNECTED_8721 ) , .clk_2_S_in ( clk_2_wires[42] ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8722 ) , - .clk_2_N_out ( clk_2_wires[43] ) , .clk_3_S_in ( p2661 ) , - .clk_3_N_in ( p1003 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8723 ) , + .clk_2_N_out ( clk_2_wires[43] ) , .clk_3_S_in ( p1888 ) , + .clk_3_N_in ( p488 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8723 ) , .clk_3_S_out ( SYNOPSYS_UNCONNECTED_8724 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; cby_1__1_ cby_5__6_ ( .pReset ( { SYNOPSYS_UNCONNECTED_8725 } ) , @@ -153817,15 +157383,15 @@ cby_1__1_ cby_5__6_ ( .prog_clk_0_W_in ( prog_clk_0_wires[193] ) , .prog_clk_0_S_out ( prog_clk_0_wires[194] ) , .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_8735 ) , - .prog_clk_2_N_in ( p2457 ) , .prog_clk_2_S_in ( p950 ) , + .prog_clk_2_N_in ( p2808 ) , .prog_clk_2_S_in ( p523 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_8736 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_8737 ) , - .prog_clk_3_S_in ( p2832 ) , .prog_clk_3_N_in ( p2341 ) , + .prog_clk_3_S_in ( p3107 ) , .prog_clk_3_N_in ( p2671 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_8738 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8739 ) , .clk_2_N_in ( p3191 ) , - .clk_2_S_in ( p3040 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8740 ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8741 ) , .clk_3_S_in ( p3081 ) , - .clk_3_N_in ( p3124 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8742 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8739 ) , .clk_2_N_in ( p2807 ) , + .clk_2_S_in ( p3046 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8740 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8741 ) , .clk_3_S_in ( p2541 ) , + .clk_3_N_in ( p2732 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8742 ) , .clk_3_S_out ( SYNOPSYS_UNCONNECTED_8743 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; cby_1__1_ cby_5__7_ ( .pReset ( { SYNOPSYS_UNCONNECTED_8744 } ) , @@ -153868,15 +157434,15 @@ cby_1__1_ cby_5__7_ ( .prog_clk_0_W_in ( prog_clk_0_wires[196] ) , .prog_clk_0_S_out ( prog_clk_0_wires[197] ) , .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_8754 ) , - .prog_clk_2_N_in ( p2799 ) , .prog_clk_2_S_in ( p275 ) , + .prog_clk_2_N_in ( p1468 ) , .prog_clk_2_S_in ( p2376 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_8755 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_8756 ) , - .prog_clk_3_S_in ( p2098 ) , .prog_clk_3_N_in ( p2729 ) , + .prog_clk_3_S_in ( p2593 ) , .prog_clk_3_N_in ( p373 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_8757 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8758 ) , .clk_2_N_in ( p3197 ) , - .clk_2_S_in ( p2756 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8759 ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8760 ) , .clk_3_S_in ( p2837 ) , - .clk_3_N_in ( p3141 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8761 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8758 ) , .clk_2_N_in ( p2343 ) , + .clk_2_S_in ( p2460 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8759 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8760 ) , .clk_3_S_in ( p2564 ) , + .clk_3_N_in ( p2085 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8761 ) , .clk_3_S_out ( SYNOPSYS_UNCONNECTED_8762 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; cby_1__1_ cby_5__8_ ( .pReset ( { SYNOPSYS_UNCONNECTED_8763 } ) , @@ -153923,14 +157489,14 @@ cby_1__1_ cby_5__8_ ( .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_8774 ) , .prog_clk_2_S_out ( prog_clk_2_wires[58] ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_8775 ) , - .prog_clk_3_S_in ( p1889 ) , .prog_clk_3_N_in ( p721 ) , + .prog_clk_3_S_in ( p1977 ) , .prog_clk_3_N_in ( p25 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_8776 ) , .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8777 ) , .clk_2_N_in ( clk_2_wires[57] ) , .clk_2_S_in ( SYNOPSYS_UNCONNECTED_8778 ) , .clk_2_S_out ( clk_2_wires[58] ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8779 ) , .clk_3_S_in ( p1889 ) , - .clk_3_N_in ( p759 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8780 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8779 ) , .clk_3_S_in ( p1977 ) , + .clk_3_N_in ( p613 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8780 ) , .clk_3_S_out ( SYNOPSYS_UNCONNECTED_8781 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; cby_1__1_ cby_5__9_ ( .pReset ( { SYNOPSYS_UNCONNECTED_8782 } ) , @@ -153976,15 +157542,15 @@ cby_1__1_ cby_5__9_ ( .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_8793 ) , .prog_clk_2_S_in ( prog_clk_2_wires[55] ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_8794 ) , - .prog_clk_2_N_out ( prog_clk_2_wires[56] ) , .prog_clk_3_S_in ( p1753 ) , + .prog_clk_2_N_out ( prog_clk_2_wires[56] ) , .prog_clk_3_S_in ( p1951 ) , .prog_clk_3_N_in ( p21 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_8795 ) , .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8796 ) , .clk_2_N_in ( SYNOPSYS_UNCONNECTED_8797 ) , .clk_2_S_in ( clk_2_wires[55] ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8798 ) , - .clk_2_N_out ( clk_2_wires[56] ) , .clk_3_S_in ( p1753 ) , - .clk_3_N_in ( p1147 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8799 ) , + .clk_2_N_out ( clk_2_wires[56] ) , .clk_3_S_in ( p1822 ) , + .clk_3_N_in ( p926 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8799 ) , .clk_3_S_out ( SYNOPSYS_UNCONNECTED_8800 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; cby_1__1_ cby_5__10_ ( .pReset ( { SYNOPSYS_UNCONNECTED_8801 } ) , @@ -154027,15 +157593,15 @@ cby_1__1_ cby_5__10_ ( .prog_clk_0_W_in ( prog_clk_0_wires[205] ) , .prog_clk_0_S_out ( prog_clk_0_wires[206] ) , .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_8811 ) , - .prog_clk_2_N_in ( p2927 ) , .prog_clk_2_S_in ( p65 ) , + .prog_clk_2_N_in ( p2255 ) , .prog_clk_2_S_in ( p695 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_8812 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_8813 ) , - .prog_clk_3_S_in ( p2655 ) , .prog_clk_3_N_in ( p2882 ) , + .prog_clk_3_S_in ( p2315 ) , .prog_clk_3_N_in ( p2054 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_8814 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8815 ) , .clk_2_N_in ( p3276 ) , - .clk_2_S_in ( p2588 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8816 ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8817 ) , .clk_3_S_in ( p2233 ) , - .clk_3_N_in ( p3220 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8818 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8815 ) , .clk_2_N_in ( p2540 ) , + .clk_2_S_in ( p3088 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8816 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8817 ) , .clk_3_S_in ( p3123 ) , + .clk_3_N_in ( p2446 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8818 ) , .clk_3_S_out ( SYNOPSYS_UNCONNECTED_8819 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; cby_1__1_ cby_5__11_ ( .pReset ( { SYNOPSYS_UNCONNECTED_8820 } ) , @@ -154081,15 +157647,15 @@ cby_1__1_ cby_5__11_ ( .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_8831 ) , .prog_clk_2_S_in ( prog_clk_2_wires[66] ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_8832 ) , - .prog_clk_2_N_out ( prog_clk_2_wires[67] ) , .prog_clk_3_S_in ( p1554 ) , - .prog_clk_3_N_in ( p59 ) , + .prog_clk_2_N_out ( prog_clk_2_wires[67] ) , .prog_clk_3_S_in ( p1912 ) , + .prog_clk_3_N_in ( p1018 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_8833 ) , .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8834 ) , .clk_2_N_in ( SYNOPSYS_UNCONNECTED_8835 ) , .clk_2_S_in ( clk_2_wires[66] ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8836 ) , - .clk_2_N_out ( clk_2_wires[67] ) , .clk_3_S_in ( p1554 ) , - .clk_3_N_in ( p696 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8837 ) , + .clk_2_N_out ( clk_2_wires[67] ) , .clk_3_S_in ( p1912 ) , + .clk_3_N_in ( p183 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8837 ) , .clk_3_S_out ( SYNOPSYS_UNCONNECTED_8838 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; cby_1__1_ cby_5__12_ ( .pReset ( { SYNOPSYS_UNCONNECTED_8839 } ) , @@ -154131,16 +157697,16 @@ cby_1__1_ cby_5__12_ ( .Reset_E_out ( SYNOPSYS_UNCONNECTED_8848 ) , .prog_clk_0_W_in ( prog_clk_0_wires[211] ) , .prog_clk_0_S_out ( prog_clk_0_wires[212] ) , - .prog_clk_0_N_out ( prog_clk_0_wires[214] ) , .prog_clk_2_N_in ( p2794 ) , - .prog_clk_2_S_in ( p694 ) , + .prog_clk_0_N_out ( prog_clk_0_wires[214] ) , .prog_clk_2_N_in ( p1537 ) , + .prog_clk_2_S_in ( p487 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_8849 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_8850 ) , - .prog_clk_3_S_in ( p2929 ) , .prog_clk_3_N_in ( p2734 ) , + .prog_clk_3_S_in ( p1911 ) , .prog_clk_3_N_in ( p1075 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_8851 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8852 ) , .clk_2_N_in ( p2456 ) , - .clk_2_S_in ( p3346 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8853 ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8854 ) , .clk_3_S_in ( p3368 ) , - .clk_3_N_in ( p2295 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8855 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8852 ) , .clk_2_N_in ( p2640 ) , + .clk_2_S_in ( p2450 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8853 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8854 ) , .clk_3_S_in ( p2572 ) , + .clk_3_N_in ( p2436 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8855 ) , .clk_3_S_out ( SYNOPSYS_UNCONNECTED_8856 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; cby_1__1_ cby_6__1_ ( .pReset ( { SYNOPSYS_UNCONNECTED_8857 } ) , @@ -154179,14 +157745,14 @@ cby_1__1_ cby_6__1_ ( .prog_clk_0_W_in ( prog_clk_0_wires[216] ) , .prog_clk_0_S_out ( prog_clk_0_wires[217] ) , .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_8862 ) , - .prog_clk_2_N_in ( p1755 ) , .prog_clk_2_S_in ( p334 ) , + .prog_clk_2_N_in ( p1572 ) , .prog_clk_2_S_in ( p889 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_8863 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_8864 ) , .prog_clk_3_S_in ( prog_clk_3_wires[90] ) , .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_8865 ) , .prog_clk_3_N_out ( prog_clk_3_wires[89] ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8866 ) , .clk_2_N_in ( p1755 ) , - .clk_2_S_in ( p1686 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8867 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8866 ) , .clk_2_N_in ( p1572 ) , + .clk_2_S_in ( p378 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8867 ) , .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8868 ) , .clk_3_S_in ( clk_3_wires[90] ) , .clk_3_N_in ( SYNOPSYS_UNCONNECTED_8869 ) , @@ -154229,14 +157795,14 @@ cby_1__1_ cby_6__2_ ( .prog_clk_0_W_in ( prog_clk_0_wires[219] ) , .prog_clk_0_S_out ( prog_clk_0_wires[220] ) , .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_8876 ) , - .prog_clk_2_N_in ( p1957 ) , .prog_clk_2_S_in ( p739 ) , + .prog_clk_2_N_in ( p1528 ) , .prog_clk_2_S_in ( p438 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_8877 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_8878 ) , .prog_clk_3_S_in ( prog_clk_3_wires[92] ) , .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_8879 ) , .prog_clk_3_N_out ( prog_clk_3_wires[91] ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8880 ) , .clk_2_N_in ( p1953 ) , - .clk_2_S_in ( p392 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8881 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8880 ) , .clk_2_N_in ( p1528 ) , + .clk_2_S_in ( p1020 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8881 ) , .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8882 ) , .clk_3_S_in ( clk_3_wires[92] ) , .clk_3_N_in ( SYNOPSYS_UNCONNECTED_8883 ) , @@ -154279,14 +157845,14 @@ cby_1__1_ cby_6__3_ ( .prog_clk_0_W_in ( prog_clk_0_wires[222] ) , .prog_clk_0_S_out ( prog_clk_0_wires[223] ) , .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_8890 ) , - .prog_clk_2_N_in ( p1936 ) , .prog_clk_2_S_in ( p1744 ) , + .prog_clk_2_N_in ( p1574 ) , .prog_clk_2_S_in ( p2420 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_8891 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_8892 ) , .prog_clk_3_S_in ( prog_clk_3_wires[94] ) , .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_8893 ) , .prog_clk_3_N_out ( prog_clk_3_wires[93] ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8894 ) , .clk_2_N_in ( p1936 ) , - .clk_2_S_in ( p2532 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8895 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8894 ) , .clk_2_N_in ( p1574 ) , + .clk_2_S_in ( p2402 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8895 ) , .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8896 ) , .clk_3_S_in ( clk_3_wires[94] ) , .clk_3_N_in ( SYNOPSYS_UNCONNECTED_8897 ) , @@ -154329,14 +157895,14 @@ cby_1__1_ cby_6__4_ ( .prog_clk_0_W_in ( prog_clk_0_wires[225] ) , .prog_clk_0_S_out ( prog_clk_0_wires[226] ) , .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_8904 ) , - .prog_clk_2_N_in ( p1818 ) , .prog_clk_2_S_in ( p1639 ) , + .prog_clk_2_N_in ( p1947 ) , .prog_clk_2_S_in ( p1805 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_8905 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_8906 ) , .prog_clk_3_S_in ( prog_clk_3_wires[96] ) , .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_8907 ) , .prog_clk_3_N_out ( prog_clk_3_wires[95] ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8908 ) , .clk_2_N_in ( p1818 ) , - .clk_2_S_in ( p1733 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8909 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8908 ) , .clk_2_N_in ( p2008 ) , + .clk_2_S_in ( p3052 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8909 ) , .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8910 ) , .clk_3_S_in ( clk_3_wires[96] ) , .clk_3_N_in ( SYNOPSYS_UNCONNECTED_8911 ) , @@ -154380,14 +157946,14 @@ cby_1__1_ cby_6__5_ ( .prog_clk_0_W_in ( prog_clk_0_wires[228] ) , .prog_clk_0_S_out ( prog_clk_0_wires[229] ) , .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_8918 ) , - .prog_clk_2_N_in ( p1916 ) , .prog_clk_2_S_in ( p2352 ) , + .prog_clk_2_N_in ( p1297 ) , .prog_clk_2_S_in ( p169 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_8919 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_8920 ) , .prog_clk_3_S_in ( prog_clk_3_wires[98] ) , .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_8921 ) , .prog_clk_3_N_out ( prog_clk_3_wires[97] ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8922 ) , .clk_2_N_in ( p1916 ) , - .clk_2_S_in ( p2907 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8923 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8922 ) , .clk_2_N_in ( p1297 ) , + .clk_2_S_in ( p2094 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8923 ) , .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8924 ) , .clk_3_S_in ( clk_3_wires[98] ) , .clk_3_N_in ( SYNOPSYS_UNCONNECTED_8925 ) , @@ -154431,14 +157997,14 @@ cby_1__1_ cby_6__6_ ( .prog_clk_0_W_in ( prog_clk_0_wires[231] ) , .prog_clk_0_S_out ( prog_clk_0_wires[232] ) , .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_8932 ) , - .prog_clk_2_N_in ( p2141 ) , .prog_clk_2_S_in ( p2597 ) , + .prog_clk_2_N_in ( p1419 ) , .prog_clk_2_S_in ( p1798 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_8933 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_8934 ) , .prog_clk_3_S_in ( prog_clk_3_wires[100] ) , .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_8935 ) , .prog_clk_3_N_out ( prog_clk_3_wires[99] ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8936 ) , .clk_2_N_in ( p2205 ) , - .clk_2_S_in ( p2752 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8937 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8936 ) , .clk_2_N_in ( p1419 ) , + .clk_2_S_in ( p1713 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8937 ) , .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8938 ) , .clk_3_S_in ( clk_3_wires[100] ) , .clk_3_N_in ( SYNOPSYS_UNCONNECTED_8939 ) , @@ -154482,15 +158048,15 @@ cby_1__1_ cby_6__7_ ( .prog_clk_0_W_in ( prog_clk_0_wires[234] ) , .prog_clk_0_S_out ( prog_clk_0_wires[235] ) , .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_8946 ) , - .prog_clk_2_N_in ( p2448 ) , .prog_clk_2_S_in ( p1728 ) , + .prog_clk_2_N_in ( p1334 ) , .prog_clk_2_S_in ( p1694 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_8947 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_8948 ) , - .prog_clk_3_S_in ( p1435 ) , .prog_clk_3_N_in ( p2350 ) , + .prog_clk_3_S_in ( p2746 ) , .prog_clk_3_N_in ( p737 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_8949 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8950 ) , .clk_2_N_in ( p2459 ) , - .clk_2_S_in ( p2884 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8951 ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8952 ) , .clk_3_S_in ( p2977 ) , - .clk_3_N_in ( p2327 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8953 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8950 ) , .clk_2_N_in ( p3332 ) , + .clk_2_S_in ( p2888 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8951 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8952 ) , .clk_3_S_in ( p2370 ) , + .clk_3_N_in ( p3287 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8953 ) , .clk_3_S_out ( SYNOPSYS_UNCONNECTED_8954 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; cby_1__1_ cby_6__8_ ( .pReset ( { SYNOPSYS_UNCONNECTED_8955 } ) , @@ -154530,15 +158096,15 @@ cby_1__1_ cby_6__8_ ( .prog_clk_0_W_in ( prog_clk_0_wires[237] ) , .prog_clk_0_S_out ( prog_clk_0_wires[238] ) , .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_8960 ) , - .prog_clk_2_N_in ( p1478 ) , .prog_clk_2_S_in ( p737 ) , + .prog_clk_2_N_in ( p2233 ) , .prog_clk_2_S_in ( p735 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_8961 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_8962 ) , - .prog_clk_3_S_in ( p2615 ) , .prog_clk_3_N_in ( p645 ) , + .prog_clk_3_S_in ( p3010 ) , .prog_clk_3_N_in ( p2157 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_8963 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8964 ) , .clk_2_N_in ( p3189 ) , - .clk_2_S_in ( p2768 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8965 ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8966 ) , .clk_3_S_in ( p2851 ) , - .clk_3_N_in ( p3117 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8967 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8964 ) , .clk_2_N_in ( p3104 ) , + .clk_2_S_in ( p2887 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8965 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8966 ) , .clk_3_S_in ( p1879 ) , + .clk_3_N_in ( p3042 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8967 ) , .clk_3_S_out ( SYNOPSYS_UNCONNECTED_8968 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; cby_1__1_ cby_6__9_ ( .pReset ( { SYNOPSYS_UNCONNECTED_8969 } ) , @@ -154578,15 +158144,15 @@ cby_1__1_ cby_6__9_ ( .prog_clk_0_W_in ( prog_clk_0_wires[240] ) , .prog_clk_0_S_out ( prog_clk_0_wires[241] ) , .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_8974 ) , - .prog_clk_2_N_in ( p2489 ) , .prog_clk_2_S_in ( p357 ) , + .prog_clk_2_N_in ( p2560 ) , .prog_clk_2_S_in ( p54 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_8975 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_8976 ) , - .prog_clk_3_S_in ( p2958 ) , .prog_clk_3_N_in ( p2294 ) , + .prog_clk_3_S_in ( p2509 ) , .prog_clk_3_N_in ( p2427 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_8977 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8978 ) , .clk_2_N_in ( p2639 ) , - .clk_2_S_in ( p2886 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8979 ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8980 ) , .clk_3_S_in ( p2857 ) , - .clk_3_N_in ( p2574 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8981 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8978 ) , .clk_2_N_in ( p2337 ) , + .clk_2_S_in ( p3090 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8979 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8980 ) , .clk_3_S_in ( p3156 ) , + .clk_3_N_in ( p2098 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8981 ) , .clk_3_S_out ( SYNOPSYS_UNCONNECTED_8982 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; cby_1__1_ cby_6__10_ ( .pReset ( { SYNOPSYS_UNCONNECTED_8983 } ) , @@ -154626,15 +158192,15 @@ cby_1__1_ cby_6__10_ ( .prog_clk_0_W_in ( prog_clk_0_wires[243] ) , .prog_clk_0_S_out ( prog_clk_0_wires[244] ) , .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_8988 ) , - .prog_clk_2_N_in ( p2264 ) , .prog_clk_2_S_in ( p226 ) , + .prog_clk_2_N_in ( p1943 ) , .prog_clk_2_S_in ( p230 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_8989 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_8990 ) , - .prog_clk_3_S_in ( p2624 ) , .prog_clk_3_N_in ( p2084 ) , + .prog_clk_3_S_in ( p2542 ) , .prog_clk_3_N_in ( p1796 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_8991 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8992 ) , .clk_2_N_in ( p3196 ) , - .clk_2_S_in ( p3005 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8993 ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8994 ) , .clk_3_S_in ( p3086 ) , - .clk_3_N_in ( p3127 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8995 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8992 ) , .clk_2_N_in ( p3258 ) , + .clk_2_S_in ( p2465 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8993 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8994 ) , .clk_3_S_in ( p2291 ) , + .clk_3_N_in ( p3194 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8995 ) , .clk_3_S_out ( SYNOPSYS_UNCONNECTED_8996 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; cby_1__1_ cby_6__11_ ( .pReset ( { SYNOPSYS_UNCONNECTED_8997 } ) , @@ -154674,15 +158240,15 @@ cby_1__1_ cby_6__11_ ( .prog_clk_0_W_in ( prog_clk_0_wires[246] ) , .prog_clk_0_S_out ( prog_clk_0_wires[247] ) , .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_9002 ) , - .prog_clk_2_N_in ( p2458 ) , .prog_clk_2_S_in ( p382 ) , + .prog_clk_2_N_in ( p1894 ) , .prog_clk_2_S_in ( p460 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_9003 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_9004 ) , - .prog_clk_3_S_in ( p3102 ) , .prog_clk_3_N_in ( p2305 ) , + .prog_clk_3_S_in ( p2012 ) , .prog_clk_3_N_in ( p1711 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_9005 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9006 ) , .clk_2_N_in ( p3369 ) , - .clk_2_S_in ( p3039 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9007 ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9008 ) , .clk_3_S_in ( p1782 ) , - .clk_3_N_in ( p3350 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9009 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9006 ) , .clk_2_N_in ( p2374 ) , + .clk_2_S_in ( p2424 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9007 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9008 ) , .clk_3_S_in ( p2531 ) , + .clk_3_N_in ( p2115 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9009 ) , .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9010 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; cby_1__1_ cby_6__12_ ( .pReset ( { SYNOPSYS_UNCONNECTED_9011 } ) , @@ -154721,16 +158287,16 @@ cby_1__1_ cby_6__12_ ( .Reset_W_out ( ResetWires[275] ) , .Reset_E_out ( ResetWires[277] ) , .prog_clk_0_W_in ( prog_clk_0_wires[249] ) , .prog_clk_0_S_out ( prog_clk_0_wires[250] ) , - .prog_clk_0_N_out ( prog_clk_0_wires[252] ) , .prog_clk_2_N_in ( p2203 ) , - .prog_clk_2_S_in ( p999 ) , + .prog_clk_0_N_out ( prog_clk_0_wires[252] ) , .prog_clk_2_N_in ( p2281 ) , + .prog_clk_2_S_in ( p287 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_9018 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_9019 ) , - .prog_clk_3_S_in ( p3091 ) , .prog_clk_3_N_in ( p2041 ) , + .prog_clk_3_S_in ( p2371 ) , .prog_clk_3_N_in ( p2165 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_9020 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9021 ) , .clk_2_N_in ( p3257 ) , - .clk_2_S_in ( p3225 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9022 ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9023 ) , .clk_3_S_in ( p3269 ) , - .clk_3_N_in ( p3206 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9024 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9021 ) , .clk_2_N_in ( p2978 ) , + .clk_2_S_in ( p3078 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9022 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9023 ) , .clk_3_S_in ( p3110 ) , + .clk_3_N_in ( p2886 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9024 ) , .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9025 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; cby_1__1_ cby_7__1_ ( .pReset ( { SYNOPSYS_UNCONNECTED_9026 } ) , @@ -154772,15 +158338,15 @@ cby_1__1_ cby_7__1_ ( .prog_clk_0_W_in ( prog_clk_0_wires[254] ) , .prog_clk_0_S_out ( prog_clk_0_wires[255] ) , .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_9036 ) , - .prog_clk_2_N_in ( p2249 ) , .prog_clk_2_S_in ( p49 ) , + .prog_clk_2_N_in ( p1906 ) , .prog_clk_2_S_in ( p646 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_9037 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_9038 ) , - .prog_clk_3_S_in ( p2784 ) , .prog_clk_3_N_in ( p2002 ) , + .prog_clk_3_S_in ( p2811 ) , .prog_clk_3_N_in ( p1722 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_9039 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9040 ) , .clk_2_N_in ( p3175 ) , - .clk_2_S_in ( p2727 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9041 ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9042 ) , .clk_3_S_in ( p2806 ) , - .clk_3_N_in ( p3133 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9043 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9040 ) , .clk_2_N_in ( p1558 ) , + .clk_2_S_in ( p2675 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9041 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9042 ) , .clk_3_S_in ( p2557 ) , + .clk_3_N_in ( p1013 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9043 ) , .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9044 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; cby_1__1_ cby_7__2_ ( .pReset ( { SYNOPSYS_UNCONNECTED_9045 } ) , @@ -154826,14 +158392,14 @@ cby_1__1_ cby_7__2_ ( .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_9056 ) , .prog_clk_2_S_out ( prog_clk_2_wires[74] ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_9057 ) , - .prog_clk_3_S_in ( p1548 ) , .prog_clk_3_N_in ( p1097 ) , + .prog_clk_3_S_in ( p1882 ) , .prog_clk_3_N_in ( p599 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_9058 ) , .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9059 ) , .clk_2_N_in ( clk_2_wires[73] ) , .clk_2_S_in ( SYNOPSYS_UNCONNECTED_9060 ) , .clk_2_S_out ( clk_2_wires[74] ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9061 ) , .clk_3_S_in ( p1548 ) , - .clk_3_N_in ( p111 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9062 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9061 ) , .clk_3_S_in ( p1882 ) , + .clk_3_N_in ( p113 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9062 ) , .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9063 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; cby_1__1_ cby_7__3_ ( .pReset ( { SYNOPSYS_UNCONNECTED_9064 } ) , @@ -154875,15 +158441,15 @@ cby_1__1_ cby_7__3_ ( .prog_clk_0_W_in ( prog_clk_0_wires[260] ) , .prog_clk_0_S_out ( prog_clk_0_wires[261] ) , .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_9074 ) , - .prog_clk_2_N_in ( p1508 ) , .prog_clk_2_S_in ( p741 ) , + .prog_clk_2_N_in ( p1519 ) , .prog_clk_2_S_in ( p30 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_9075 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_9076 ) , - .prog_clk_3_S_in ( p3193 ) , .prog_clk_3_N_in ( p31 ) , + .prog_clk_3_S_in ( p2357 ) , .prog_clk_3_N_in ( p732 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_9077 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9078 ) , .clk_2_N_in ( p2672 ) , - .clk_2_S_in ( p3134 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9079 ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9080 ) , .clk_3_S_in ( p2792 ) , - .clk_3_N_in ( p2594 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9081 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9078 ) , .clk_2_N_in ( p2960 ) , + .clk_2_S_in ( p2694 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9079 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9080 ) , .clk_3_S_in ( p2823 ) , + .clk_3_N_in ( p2894 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9081 ) , .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9082 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; cby_1__1_ cby_7__4_ ( .pReset ( { SYNOPSYS_UNCONNECTED_9083 } ) , @@ -154929,14 +158495,14 @@ cby_1__1_ cby_7__4_ ( .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_9094 ) , .prog_clk_2_S_out ( prog_clk_2_wires[85] ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_9095 ) , - .prog_clk_3_S_in ( p1812 ) , .prog_clk_3_N_in ( p748 ) , + .prog_clk_3_S_in ( p1927 ) , .prog_clk_3_N_in ( p742 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_9096 ) , .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9097 ) , .clk_2_N_in ( clk_2_wires[84] ) , .clk_2_S_in ( SYNOPSYS_UNCONNECTED_9098 ) , .clk_2_S_out ( clk_2_wires[85] ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9099 ) , .clk_3_S_in ( p1812 ) , - .clk_3_N_in ( p362 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9100 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9099 ) , .clk_3_S_in ( p1927 ) , + .clk_3_N_in ( p1074 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9100 ) , .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9101 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; cby_1__1_ cby_7__5_ ( .pReset ( { SYNOPSYS_UNCONNECTED_9102 } ) , @@ -154981,15 +158547,15 @@ cby_1__1_ cby_7__5_ ( .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_9113 ) , .prog_clk_2_S_in ( prog_clk_2_wires[82] ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_9114 ) , - .prog_clk_2_N_out ( prog_clk_2_wires[83] ) , .prog_clk_3_S_in ( p2163 ) , - .prog_clk_3_N_in ( p1014 ) , + .prog_clk_2_N_out ( prog_clk_2_wires[83] ) , .prog_clk_3_S_in ( p2322 ) , + .prog_clk_3_N_in ( p1073 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_9115 ) , .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9116 ) , .clk_2_N_in ( SYNOPSYS_UNCONNECTED_9117 ) , .clk_2_S_in ( clk_2_wires[82] ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9118 ) , - .clk_2_N_out ( clk_2_wires[83] ) , .clk_3_S_in ( p2163 ) , - .clk_3_N_in ( p559 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9119 ) , + .clk_2_N_out ( clk_2_wires[83] ) , .clk_3_S_in ( p2322 ) , + .clk_3_N_in ( p398 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9119 ) , .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9120 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; cby_1__1_ cby_7__6_ ( .pReset ( { SYNOPSYS_UNCONNECTED_9121 } ) , @@ -155031,15 +158597,15 @@ cby_1__1_ cby_7__6_ ( .prog_clk_0_W_in ( prog_clk_0_wires[269] ) , .prog_clk_0_S_out ( prog_clk_0_wires[270] ) , .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_9131 ) , - .prog_clk_2_N_in ( p2156 ) , .prog_clk_2_S_in ( p1035 ) , + .prog_clk_2_N_in ( p2013 ) , .prog_clk_2_S_in ( p481 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_9132 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_9133 ) , - .prog_clk_3_S_in ( p2214 ) , .prog_clk_3_N_in ( p2032 ) , + .prog_clk_3_S_in ( p2552 ) , .prog_clk_3_N_in ( p1759 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_9134 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9135 ) , .clk_2_N_in ( p3167 ) , - .clk_2_S_in ( p3414 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9136 ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9137 ) , .clk_3_S_in ( p3426 ) , - .clk_3_N_in ( p3150 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9138 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9135 ) , .clk_2_N_in ( p3324 ) , + .clk_2_S_in ( p3080 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9136 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9137 ) , .clk_3_S_in ( p3116 ) , + .clk_3_N_in ( p3292 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9138 ) , .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9139 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; cby_1__1_ cby_7__7_ ( .pReset ( { SYNOPSYS_UNCONNECTED_9140 } ) , @@ -155081,15 +158647,15 @@ cby_1__1_ cby_7__7_ ( .prog_clk_0_W_in ( prog_clk_0_wires[272] ) , .prog_clk_0_S_out ( prog_clk_0_wires[273] ) , .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_9150 ) , - .prog_clk_2_N_in ( p2714 ) , .prog_clk_2_S_in ( p2290 ) , + .prog_clk_2_N_in ( p1245 ) , .prog_clk_2_S_in ( p355 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_9151 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_9152 ) , - .prog_clk_3_S_in ( p2477 ) , .prog_clk_3_N_in ( p2592 ) , + .prog_clk_3_S_in ( p3344 ) , .prog_clk_3_N_in ( p65 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_9153 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9154 ) , .clk_2_N_in ( p2670 ) , - .clk_2_S_in ( p2362 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9155 ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9156 ) , .clk_3_S_in ( p2173 ) , - .clk_3_N_in ( p2563 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9157 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9154 ) , .clk_2_N_in ( p2771 ) , + .clk_2_S_in ( p3280 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9155 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9156 ) , .clk_3_S_in ( p3253 ) , + .clk_3_N_in ( p2695 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9157 ) , .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9158 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; cby_1__1_ cby_7__8_ ( .pReset ( { SYNOPSYS_UNCONNECTED_9159 } ) , @@ -155135,14 +158701,14 @@ cby_1__1_ cby_7__8_ ( .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_9170 ) , .prog_clk_2_S_out ( prog_clk_2_wires[98] ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_9171 ) , - .prog_clk_3_S_in ( p2143 ) , .prog_clk_3_N_in ( p76 ) , + .prog_clk_3_S_in ( p1154 ) , .prog_clk_3_N_in ( p681 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_9172 ) , .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9173 ) , .clk_2_N_in ( clk_2_wires[97] ) , .clk_2_S_in ( SYNOPSYS_UNCONNECTED_9174 ) , .clk_2_S_out ( clk_2_wires[98] ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9175 ) , .clk_3_S_in ( p2143 ) , - .clk_3_N_in ( p995 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9176 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9175 ) , .clk_3_S_in ( p1154 ) , + .clk_3_N_in ( p353 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9176 ) , .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9177 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; cby_1__1_ cby_7__9_ ( .pReset ( { SYNOPSYS_UNCONNECTED_9178 } ) , @@ -155187,15 +158753,15 @@ cby_1__1_ cby_7__9_ ( .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_9189 ) , .prog_clk_2_S_in ( prog_clk_2_wires[95] ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_9190 ) , - .prog_clk_2_N_out ( prog_clk_2_wires[96] ) , .prog_clk_3_S_in ( p1536 ) , - .prog_clk_3_N_in ( p422 ) , + .prog_clk_2_N_out ( prog_clk_2_wires[96] ) , .prog_clk_3_S_in ( p1496 ) , + .prog_clk_3_N_in ( p997 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_9191 ) , .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9192 ) , .clk_2_N_in ( SYNOPSYS_UNCONNECTED_9193 ) , .clk_2_S_in ( clk_2_wires[95] ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9194 ) , - .clk_2_N_out ( clk_2_wires[96] ) , .clk_3_S_in ( p1536 ) , - .clk_3_N_in ( p951 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9195 ) , + .clk_2_N_out ( clk_2_wires[96] ) , .clk_3_S_in ( p1496 ) , + .clk_3_N_in ( p80 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9195 ) , .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9196 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; cby_1__1_ cby_7__10_ ( .pReset ( { SYNOPSYS_UNCONNECTED_9197 } ) , @@ -155237,15 +158803,15 @@ cby_1__1_ cby_7__10_ ( .prog_clk_0_W_in ( prog_clk_0_wires[281] ) , .prog_clk_0_S_out ( prog_clk_0_wires[282] ) , .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_9207 ) , - .prog_clk_2_N_in ( p2260 ) , .prog_clk_2_S_in ( p933 ) , + .prog_clk_2_N_in ( p2223 ) , .prog_clk_2_S_in ( p1055 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_9208 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_9209 ) , - .prog_clk_3_S_in ( p2844 ) , .prog_clk_3_N_in ( p2034 ) , + .prog_clk_3_S_in ( p2789 ) , .prog_clk_3_N_in ( p2154 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_9210 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9211 ) , .clk_2_N_in ( p1505 ) , - .clk_2_S_in ( p2763 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9212 ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9213 ) , .clk_3_S_in ( p2517 ) , - .clk_3_N_in ( p288 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9214 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9211 ) , .clk_2_N_in ( p2953 ) , + .clk_2_S_in ( p2696 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9212 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9213 ) , .clk_3_S_in ( p2319 ) , + .clk_3_N_in ( p2890 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9214 ) , .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9215 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; cby_1__1_ cby_7__11_ ( .pReset ( { SYNOPSYS_UNCONNECTED_9216 } ) , @@ -155290,15 +158856,15 @@ cby_1__1_ cby_7__11_ ( .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_9227 ) , .prog_clk_2_S_in ( prog_clk_2_wires[108] ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_9228 ) , - .prog_clk_2_N_out ( prog_clk_2_wires[109] ) , .prog_clk_3_S_in ( p1961 ) , - .prog_clk_3_N_in ( p755 ) , + .prog_clk_2_N_out ( prog_clk_2_wires[109] ) , .prog_clk_3_S_in ( p1405 ) , + .prog_clk_3_N_in ( p714 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_9229 ) , .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9230 ) , .clk_2_N_in ( SYNOPSYS_UNCONNECTED_9231 ) , .clk_2_S_in ( clk_2_wires[108] ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9232 ) , - .clk_2_N_out ( clk_2_wires[109] ) , .clk_3_S_in ( p1961 ) , - .clk_3_N_in ( p732 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9233 ) , + .clk_2_N_out ( clk_2_wires[109] ) , .clk_3_S_in ( p1405 ) , + .clk_3_N_in ( p234 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9233 ) , .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9234 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; cby_1__1_ cby_7__12_ ( .pReset ( { SYNOPSYS_UNCONNECTED_9235 } ) , @@ -155339,16 +158905,16 @@ cby_1__1_ cby_7__12_ ( .Reset_E_out ( ResetWires[279] ) , .prog_clk_0_W_in ( prog_clk_0_wires[287] ) , .prog_clk_0_S_out ( prog_clk_0_wires[288] ) , - .prog_clk_0_N_out ( prog_clk_0_wires[290] ) , .prog_clk_2_N_in ( p2481 ) , - .prog_clk_2_S_in ( p850 ) , + .prog_clk_0_N_out ( prog_clk_0_wires[290] ) , .prog_clk_2_N_in ( p1229 ) , + .prog_clk_2_S_in ( p650 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_9245 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_9246 ) , - .prog_clk_3_S_in ( p1831 ) , .prog_clk_3_N_in ( p2329 ) , + .prog_clk_3_S_in ( p2511 ) , .prog_clk_3_N_in ( p383 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_9247 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9248 ) , .clk_2_N_in ( p2638 ) , - .clk_2_S_in ( p3119 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9249 ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9250 ) , .clk_3_S_in ( p3158 ) , - .clk_3_N_in ( p2552 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9251 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9248 ) , .clk_2_N_in ( p2937 ) , + .clk_2_S_in ( p2422 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9249 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9250 ) , .clk_3_S_in ( p2582 ) , + .clk_3_N_in ( p2899 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9251 ) , .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9252 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; cby_1__1_ cby_8__1_ ( .pReset ( { SYNOPSYS_UNCONNECTED_9253 } ) , @@ -155390,15 +158956,15 @@ cby_1__1_ cby_8__1_ ( .prog_clk_0_W_in ( prog_clk_0_wires[292] ) , .prog_clk_0_S_out ( prog_clk_0_wires[293] ) , .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_9263 ) , - .prog_clk_2_N_in ( p1440 ) , .prog_clk_2_S_in ( p267 ) , + .prog_clk_2_N_in ( p1470 ) , .prog_clk_2_S_in ( p391 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_9264 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_9265 ) , - .prog_clk_3_S_in ( p2945 ) , .prog_clk_3_N_in ( p1125 ) , + .prog_clk_3_S_in ( p2573 ) , .prog_clk_3_N_in ( p904 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_9266 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9267 ) , .clk_2_N_in ( p2966 ) , - .clk_2_S_in ( p3147 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9268 ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9269 ) , .clk_3_S_in ( p3184 ) , - .clk_3_N_in ( p2876 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9270 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9267 ) , .clk_2_N_in ( p1618 ) , + .clk_2_S_in ( p2414 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9268 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9269 ) , .clk_3_S_in ( p2318 ) , + .clk_3_N_in ( p314 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9270 ) , .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9271 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; cby_1__1_ cby_8__2_ ( .pReset ( { SYNOPSYS_UNCONNECTED_9272 } ) , @@ -155440,15 +159006,15 @@ cby_1__1_ cby_8__2_ ( .prog_clk_0_W_in ( prog_clk_0_wires[295] ) , .prog_clk_0_S_out ( prog_clk_0_wires[296] ) , .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_9282 ) , - .prog_clk_2_N_in ( p1578 ) , .prog_clk_2_S_in ( p107 ) , + .prog_clk_2_N_in ( p2307 ) , .prog_clk_2_S_in ( p146 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_9283 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_9284 ) , - .prog_clk_3_S_in ( p3065 ) , .prog_clk_3_N_in ( p124 ) , + .prog_clk_3_S_in ( p2841 ) , .prog_clk_3_N_in ( p2056 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_9285 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9286 ) , .clk_2_N_in ( p3088 ) , - .clk_2_S_in ( p3047 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9287 ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9288 ) , .clk_3_S_in ( p3105 ) , - .clk_3_N_in ( p3010 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9289 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9286 ) , .clk_2_N_in ( p3257 ) , + .clk_2_S_in ( p3075 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9287 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9288 ) , .clk_3_S_in ( p3136 ) , + .clk_3_N_in ( p3187 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9289 ) , .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9290 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; cby_1__1_ cby_8__3_ ( .pReset ( { SYNOPSYS_UNCONNECTED_9291 } ) , @@ -155490,14 +159056,14 @@ cby_1__1_ cby_8__3_ ( .prog_clk_0_W_in ( prog_clk_0_wires[298] ) , .prog_clk_0_S_out ( prog_clk_0_wires[299] ) , .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_9301 ) , - .prog_clk_2_N_in ( p2250 ) , .prog_clk_2_S_in ( p749 ) , + .prog_clk_2_N_in ( p1859 ) , .prog_clk_2_S_in ( p420 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_9302 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_9303 ) , .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_9304 ) , .prog_clk_3_N_in ( prog_clk_3_wires[42] ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_9305 ) , - .prog_clk_3_S_out ( prog_clk_3_wires[43] ) , .clk_2_N_in ( p2250 ) , - .clk_2_S_in ( p33 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9306 ) , + .prog_clk_3_S_out ( prog_clk_3_wires[43] ) , .clk_2_N_in ( p1859 ) , + .clk_2_S_in ( p32 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9306 ) , .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9307 ) , .clk_3_S_in ( SYNOPSYS_UNCONNECTED_9308 ) , .clk_3_N_in ( clk_3_wires[42] ) , @@ -155543,14 +159109,14 @@ cby_1__1_ cby_8__4_ ( .prog_clk_0_W_in ( prog_clk_0_wires[301] ) , .prog_clk_0_S_out ( prog_clk_0_wires[302] ) , .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_9320 ) , - .prog_clk_2_N_in ( p1364 ) , .prog_clk_2_S_in ( p2063 ) , + .prog_clk_2_N_in ( p1283 ) , .prog_clk_2_S_in ( p447 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_9321 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_9322 ) , .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_9323 ) , .prog_clk_3_N_in ( prog_clk_3_wires[38] ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_9324 ) , - .prog_clk_3_S_out ( prog_clk_3_wires[39] ) , .clk_2_N_in ( p1364 ) , - .clk_2_S_in ( p2024 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9325 ) , + .prog_clk_3_S_out ( prog_clk_3_wires[39] ) , .clk_2_N_in ( p1283 ) , + .clk_2_S_in ( p2108 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9325 ) , .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9326 ) , .clk_3_S_in ( SYNOPSYS_UNCONNECTED_9327 ) , .clk_3_N_in ( clk_3_wires[38] ) , @@ -155596,14 +159162,14 @@ cby_1__1_ cby_8__5_ ( .prog_clk_0_W_in ( prog_clk_0_wires[304] ) , .prog_clk_0_S_out ( prog_clk_0_wires[305] ) , .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_9339 ) , - .prog_clk_2_N_in ( p1860 ) , .prog_clk_2_S_in ( p32 ) , + .prog_clk_2_N_in ( p2261 ) , .prog_clk_2_S_in ( p1700 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_9340 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_9341 ) , .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_9342 ) , .prog_clk_3_N_in ( prog_clk_3_wires[32] ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_9343 ) , - .prog_clk_3_S_out ( prog_clk_3_wires[33] ) , .clk_2_N_in ( p1860 ) , - .clk_2_S_in ( p940 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9344 ) , + .prog_clk_3_S_out ( prog_clk_3_wires[33] ) , .clk_2_N_in ( p2197 ) , + .clk_2_S_in ( p31 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9344 ) , .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9345 ) , .clk_3_S_in ( SYNOPSYS_UNCONNECTED_9346 ) , .clk_3_N_in ( clk_3_wires[32] ) , @@ -155649,14 +159215,14 @@ cby_1__1_ cby_8__6_ ( .prog_clk_0_W_in ( prog_clk_0_wires[307] ) , .prog_clk_0_S_out ( prog_clk_0_wires[308] ) , .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_9358 ) , - .prog_clk_2_N_in ( p1949 ) , .prog_clk_2_S_in ( p1739 ) , + .prog_clk_2_N_in ( p1396 ) , .prog_clk_2_S_in ( p1735 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_9359 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_9360 ) , .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_9361 ) , .prog_clk_3_N_in ( prog_clk_3_wires[28] ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_9362 ) , - .prog_clk_3_S_out ( prog_clk_3_wires[29] ) , .clk_2_N_in ( p1949 ) , - .clk_2_S_in ( p1646 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9363 ) , + .prog_clk_3_S_out ( prog_clk_3_wires[29] ) , .clk_2_N_in ( p1396 ) , + .clk_2_S_in ( p2421 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9363 ) , .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9364 ) , .clk_3_S_in ( SYNOPSYS_UNCONNECTED_9365 ) , .clk_3_N_in ( clk_3_wires[28] ) , @@ -155702,14 +159268,14 @@ cby_1__1_ cby_8__7_ ( .prog_clk_0_W_in ( prog_clk_0_wires[310] ) , .prog_clk_0_S_out ( prog_clk_0_wires[311] ) , .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_9377 ) , - .prog_clk_2_N_in ( p1778 ) , .prog_clk_2_S_in ( p2887 ) , + .prog_clk_2_N_in ( p1522 ) , .prog_clk_2_S_in ( p1808 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_9378 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_9379 ) , .prog_clk_3_S_in ( prog_clk_3_wires[26] ) , .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_9380 ) , .prog_clk_3_N_out ( prog_clk_3_wires[27] ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9381 ) , .clk_2_N_in ( p1778 ) , - .clk_2_S_in ( p2912 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9382 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9381 ) , .clk_2_N_in ( p1522 ) , + .clk_2_S_in ( p1698 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9382 ) , .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9383 ) , .clk_3_S_in ( clk_3_wires[26] ) , .clk_3_N_in ( SYNOPSYS_UNCONNECTED_9384 ) , @@ -155755,14 +159321,14 @@ cby_1__1_ cby_8__8_ ( .prog_clk_0_W_in ( prog_clk_0_wires[313] ) , .prog_clk_0_S_out ( prog_clk_0_wires[314] ) , .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_9396 ) , - .prog_clk_2_N_in ( p1387 ) , .prog_clk_2_S_in ( p2272 ) , + .prog_clk_2_N_in ( p1431 ) , .prog_clk_2_S_in ( p2378 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_9397 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_9398 ) , .prog_clk_3_S_in ( prog_clk_3_wires[30] ) , .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_9399 ) , .prog_clk_3_N_out ( prog_clk_3_wires[31] ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9400 ) , .clk_2_N_in ( p1387 ) , - .clk_2_S_in ( p2340 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9401 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9400 ) , .clk_2_N_in ( p1431 ) , + .clk_2_S_in ( p2458 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9401 ) , .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9402 ) , .clk_3_S_in ( clk_3_wires[30] ) , .clk_3_N_in ( SYNOPSYS_UNCONNECTED_9403 ) , @@ -155808,14 +159374,14 @@ cby_1__1_ cby_8__9_ ( .prog_clk_0_W_in ( prog_clk_0_wires[316] ) , .prog_clk_0_S_out ( prog_clk_0_wires[317] ) , .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_9415 ) , - .prog_clk_2_N_in ( p2207 ) , .prog_clk_2_S_in ( p1648 ) , + .prog_clk_2_N_in ( p1644 ) , .prog_clk_2_S_in ( p144 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_9416 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_9417 ) , .prog_clk_3_S_in ( prog_clk_3_wires[36] ) , .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_9418 ) , .prog_clk_3_N_out ( prog_clk_3_wires[37] ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9419 ) , .clk_2_N_in ( p2207 ) , - .clk_2_S_in ( p851 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9420 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9419 ) , .clk_2_N_in ( p1644 ) , + .clk_2_S_in ( p567 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9420 ) , .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9421 ) , .clk_3_S_in ( clk_3_wires[36] ) , .clk_3_N_in ( SYNOPSYS_UNCONNECTED_9422 ) , @@ -155861,14 +159427,14 @@ cby_1__1_ cby_8__10_ ( .prog_clk_0_W_in ( prog_clk_0_wires[319] ) , .prog_clk_0_S_out ( prog_clk_0_wires[320] ) , .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_9434 ) , - .prog_clk_2_N_in ( p2103 ) , .prog_clk_2_S_in ( p2071 ) , + .prog_clk_2_N_in ( p2372 ) , .prog_clk_2_S_in ( p1732 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_9435 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_9436 ) , .prog_clk_3_S_in ( prog_clk_3_wires[40] ) , .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_9437 ) , .prog_clk_3_N_out ( prog_clk_3_wires[41] ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9438 ) , .clk_2_N_in ( p2103 ) , - .clk_2_S_in ( p2312 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9439 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9438 ) , .clk_2_N_in ( p2208 ) , + .clk_2_S_in ( p1780 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9439 ) , .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9440 ) , .clk_3_S_in ( clk_3_wires[40] ) , .clk_3_N_in ( SYNOPSYS_UNCONNECTED_9441 ) , @@ -155914,15 +159480,15 @@ cby_1__1_ cby_8__11_ ( .prog_clk_0_W_in ( prog_clk_0_wires[322] ) , .prog_clk_0_S_out ( prog_clk_0_wires[323] ) , .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_9453 ) , - .prog_clk_2_N_in ( p1857 ) , .prog_clk_2_S_in ( p570 ) , + .prog_clk_2_N_in ( p2215 ) , .prog_clk_2_S_in ( p834 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_9454 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_9455 ) , - .prog_clk_3_S_in ( p3205 ) , .prog_clk_3_N_in ( p1705 ) , + .prog_clk_3_S_in ( p2845 ) , .prog_clk_3_N_in ( p2121 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_9456 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9457 ) , .clk_2_N_in ( p2621 ) , - .clk_2_S_in ( p3135 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9458 ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9459 ) , .clk_3_S_in ( p2474 ) , - .clk_3_N_in ( p2527 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9460 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9457 ) , .clk_2_N_in ( p2032 ) , + .clk_2_S_in ( p2879 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9458 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9459 ) , .clk_3_S_in ( p2992 ) , + .clk_3_N_in ( p1703 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9460 ) , .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9461 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; cby_1__1_ cby_8__12_ ( .pReset ( { SYNOPSYS_UNCONNECTED_9462 } ) , @@ -155963,16 +159529,16 @@ cby_1__1_ cby_8__12_ ( .Reset_E_out ( ResetWires[281] ) , .prog_clk_0_W_in ( prog_clk_0_wires[325] ) , .prog_clk_0_S_out ( prog_clk_0_wires[326] ) , - .prog_clk_0_N_out ( prog_clk_0_wires[328] ) , .prog_clk_2_N_in ( p2677 ) , - .prog_clk_2_S_in ( p229 ) , + .prog_clk_0_N_out ( prog_clk_0_wires[328] ) , .prog_clk_2_N_in ( p2588 ) , + .prog_clk_2_S_in ( p282 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_9472 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_9473 ) , - .prog_clk_3_S_in ( p2469 ) , .prog_clk_3_N_in ( p2589 ) , + .prog_clk_3_S_in ( p2806 ) , .prog_clk_3_N_in ( p2419 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_9474 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9475 ) , .clk_2_N_in ( p2785 ) , - .clk_2_S_in ( p2296 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9476 ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9477 ) , .clk_3_S_in ( p2510 ) , - .clk_3_N_in ( p2737 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9478 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9475 ) , .clk_2_N_in ( p1899 ) , + .clk_2_S_in ( p3298 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9476 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9477 ) , .clk_3_S_in ( p3327 ) , + .clk_3_N_in ( p1816 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9478 ) , .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9479 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; cby_1__1_ cby_9__1_ ( .pReset ( { SYNOPSYS_UNCONNECTED_9480 } ) , @@ -156014,15 +159580,15 @@ cby_1__1_ cby_9__1_ ( .prog_clk_0_W_in ( prog_clk_0_wires[330] ) , .prog_clk_0_S_out ( prog_clk_0_wires[331] ) , .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_9490 ) , - .prog_clk_2_N_in ( p2679 ) , .prog_clk_2_S_in ( p905 ) , + .prog_clk_2_N_in ( p2272 ) , .prog_clk_2_S_in ( p467 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_9491 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_9492 ) , - .prog_clk_3_S_in ( p1852 ) , .prog_clk_3_N_in ( p2565 ) , + .prog_clk_3_S_in ( p3346 ) , .prog_clk_3_N_in ( p2148 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_9493 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9494 ) , .clk_2_N_in ( p2499 ) , - .clk_2_S_in ( p1986 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9495 ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9496 ) , .clk_3_S_in ( p2208 ) , - .clk_3_N_in ( p2300 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9497 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9494 ) , .clk_2_N_in ( p3108 ) , + .clk_2_S_in ( p3285 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9495 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9496 ) , .clk_3_S_in ( p2857 ) , + .clk_3_N_in ( p3045 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9497 ) , .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9498 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; cby_1__1_ cby_9__2_ ( .pReset ( { SYNOPSYS_UNCONNECTED_9499 } ) , @@ -156068,14 +159634,14 @@ cby_1__1_ cby_9__2_ ( .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_9510 ) , .prog_clk_2_S_out ( prog_clk_2_wires[76] ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_9511 ) , - .prog_clk_3_S_in ( p1617 ) , .prog_clk_3_N_in ( p69 ) , + .prog_clk_3_S_in ( p2201 ) , .prog_clk_3_N_in ( p841 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_9512 ) , .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9513 ) , .clk_2_N_in ( clk_2_wires[75] ) , .clk_2_S_in ( SYNOPSYS_UNCONNECTED_9514 ) , .clk_2_S_out ( clk_2_wires[76] ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9515 ) , .clk_3_S_in ( p1617 ) , - .clk_3_N_in ( p701 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9516 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9515 ) , .clk_3_S_in ( p2201 ) , + .clk_3_N_in ( p291 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9516 ) , .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9517 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; cby_1__1_ cby_9__3_ ( .pReset ( { SYNOPSYS_UNCONNECTED_9518 } ) , @@ -156117,15 +159683,15 @@ cby_1__1_ cby_9__3_ ( .prog_clk_0_W_in ( prog_clk_0_wires[336] ) , .prog_clk_0_S_out ( prog_clk_0_wires[337] ) , .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_9528 ) , - .prog_clk_2_N_in ( p2200 ) , .prog_clk_2_S_in ( p245 ) , + .prog_clk_2_N_in ( p2611 ) , .prog_clk_2_S_in ( p569 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_9529 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_9530 ) , - .prog_clk_3_S_in ( p2810 ) , .prog_clk_3_N_in ( p2004 ) , + .prog_clk_3_S_in ( p2335 ) , .prog_clk_3_N_in ( p2404 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_9531 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9532 ) , .clk_2_N_in ( p3157 ) , - .clk_2_S_in ( p3122 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9533 ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9534 ) , .clk_3_S_in ( p3163 ) , - .clk_3_N_in ( p3154 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9535 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9532 ) , .clk_2_N_in ( p2815 ) , + .clk_2_S_in ( p2699 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9533 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9534 ) , .clk_3_S_in ( p2782 ) , + .clk_3_N_in ( p2644 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9535 ) , .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9536 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; cby_1__1_ cby_9__4_ ( .pReset ( { SYNOPSYS_UNCONNECTED_9537 } ) , @@ -156171,14 +159737,14 @@ cby_1__1_ cby_9__4_ ( .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_9548 ) , .prog_clk_2_S_out ( prog_clk_2_wires[89] ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_9549 ) , - .prog_clk_3_S_in ( p1259 ) , .prog_clk_3_N_in ( p1039 ) , + .prog_clk_3_S_in ( p2364 ) , .prog_clk_3_N_in ( p915 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_9550 ) , .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9551 ) , .clk_2_N_in ( clk_2_wires[88] ) , .clk_2_S_in ( SYNOPSYS_UNCONNECTED_9552 ) , .clk_2_S_out ( clk_2_wires[89] ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9553 ) , .clk_3_S_in ( p1259 ) , - .clk_3_N_in ( p322 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9554 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9553 ) , .clk_3_S_in ( p2364 ) , + .clk_3_N_in ( p856 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9554 ) , .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9555 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; cby_1__1_ cby_9__5_ ( .pReset ( { SYNOPSYS_UNCONNECTED_9556 } ) , @@ -156223,15 +159789,15 @@ cby_1__1_ cby_9__5_ ( .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_9567 ) , .prog_clk_2_S_in ( prog_clk_2_wires[86] ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_9568 ) , - .prog_clk_2_N_out ( prog_clk_2_wires[87] ) , .prog_clk_3_S_in ( p2140 ) , - .prog_clk_3_N_in ( p12 ) , + .prog_clk_2_N_out ( prog_clk_2_wires[87] ) , .prog_clk_3_S_in ( p1972 ) , + .prog_clk_3_N_in ( p921 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_9569 ) , .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9570 ) , .clk_2_N_in ( SYNOPSYS_UNCONNECTED_9571 ) , .clk_2_S_in ( clk_2_wires[86] ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9572 ) , - .clk_2_N_out ( clk_2_wires[87] ) , .clk_3_S_in ( p2140 ) , - .clk_3_N_in ( p859 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9573 ) , + .clk_2_N_out ( clk_2_wires[87] ) , .clk_3_S_in ( p1972 ) , + .clk_3_N_in ( p14 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9573 ) , .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9574 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; cby_1__1_ cby_9__6_ ( .pReset ( { SYNOPSYS_UNCONNECTED_9575 } ) , @@ -156273,15 +159839,15 @@ cby_1__1_ cby_9__6_ ( .prog_clk_0_W_in ( prog_clk_0_wires[345] ) , .prog_clk_0_S_out ( prog_clk_0_wires[346] ) , .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_9585 ) , - .prog_clk_2_N_in ( p2232 ) , .prog_clk_2_S_in ( p428 ) , + .prog_clk_2_N_in ( p2765 ) , .prog_clk_2_S_in ( p261 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_9586 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_9587 ) , - .prog_clk_3_S_in ( p2935 ) , .prog_clk_3_N_in ( p2055 ) , + .prog_clk_3_S_in ( p2050 ) , .prog_clk_3_N_in ( p2650 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_9588 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9589 ) , .clk_2_N_in ( p2978 ) , - .clk_2_S_in ( p2874 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9590 ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9591 ) , .clk_3_S_in ( p2137 ) , - .clk_3_N_in ( p2900 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9592 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9589 ) , .clk_2_N_in ( p2308 ) , + .clk_2_S_in ( p2403 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9590 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9591 ) , .clk_3_S_in ( p2610 ) , + .clk_3_N_in ( p2152 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9592 ) , .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9593 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; cby_1__1_ cby_9__7_ ( .pReset ( { SYNOPSYS_UNCONNECTED_9594 } ) , @@ -156323,15 +159889,15 @@ cby_1__1_ cby_9__7_ ( .prog_clk_0_W_in ( prog_clk_0_wires[348] ) , .prog_clk_0_S_out ( prog_clk_0_wires[349] ) , .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_9604 ) , - .prog_clk_2_N_in ( p2990 ) , .prog_clk_2_S_in ( p1660 ) , + .prog_clk_2_N_in ( p2505 ) , .prog_clk_2_S_in ( p1801 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_9605 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_9606 ) , - .prog_clk_3_S_in ( p2656 ) , .prog_clk_3_N_in ( p2921 ) , + .prog_clk_3_S_in ( p2772 ) , .prog_clk_3_N_in ( p2391 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_9607 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9608 ) , .clk_2_N_in ( p2961 ) , - .clk_2_S_in ( p2717 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9609 ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9610 ) , .clk_3_S_in ( p2782 ) , - .clk_3_N_in ( p2873 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9611 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9608 ) , .clk_2_N_in ( p3005 ) , + .clk_2_S_in ( p2662 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9609 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9610 ) , .clk_3_S_in ( p2749 ) , + .clk_3_N_in ( p2900 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9611 ) , .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9612 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; cby_1__1_ cby_9__8_ ( .pReset ( { SYNOPSYS_UNCONNECTED_9613 } ) , @@ -156377,14 +159943,14 @@ cby_1__1_ cby_9__8_ ( .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_9624 ) , .prog_clk_2_S_out ( prog_clk_2_wires[102] ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_9625 ) , - .prog_clk_3_S_in ( p1842 ) , .prog_clk_3_N_in ( p278 ) , + .prog_clk_3_S_in ( p1303 ) , .prog_clk_3_N_in ( p1014 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_9626 ) , .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9627 ) , .clk_2_N_in ( clk_2_wires[101] ) , .clk_2_S_in ( SYNOPSYS_UNCONNECTED_9628 ) , .clk_2_S_out ( clk_2_wires[102] ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9629 ) , .clk_3_S_in ( p1842 ) , - .clk_3_N_in ( p499 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9630 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9629 ) , .clk_3_S_in ( p1303 ) , + .clk_3_N_in ( p143 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9630 ) , .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9631 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; cby_1__1_ cby_9__9_ ( .pReset ( { SYNOPSYS_UNCONNECTED_9632 } ) , @@ -156429,15 +159995,15 @@ cby_1__1_ cby_9__9_ ( .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_9643 ) , .prog_clk_2_S_in ( prog_clk_2_wires[99] ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_9644 ) , - .prog_clk_2_N_out ( prog_clk_2_wires[100] ) , .prog_clk_3_S_in ( p1463 ) , - .prog_clk_3_N_in ( p785 ) , + .prog_clk_2_N_out ( prog_clk_2_wires[100] ) , .prog_clk_3_S_in ( p1643 ) , + .prog_clk_3_N_in ( p164 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_9645 ) , .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9646 ) , .clk_2_N_in ( SYNOPSYS_UNCONNECTED_9647 ) , .clk_2_S_in ( clk_2_wires[99] ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9648 ) , - .clk_2_N_out ( clk_2_wires[100] ) , .clk_3_S_in ( p1463 ) , - .clk_3_N_in ( p896 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9649 ) , + .clk_2_N_out ( clk_2_wires[100] ) , .clk_3_S_in ( p1643 ) , + .clk_3_N_in ( p913 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9649 ) , .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9650 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; cby_1__1_ cby_9__10_ ( .pReset ( { SYNOPSYS_UNCONNECTED_9651 } ) , @@ -156479,15 +160045,15 @@ cby_1__1_ cby_9__10_ ( .prog_clk_0_W_in ( prog_clk_0_wires[357] ) , .prog_clk_0_S_out ( prog_clk_0_wires[358] ) , .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_9661 ) , - .prog_clk_2_N_in ( p1173 ) , .prog_clk_2_S_in ( p424 ) , + .prog_clk_2_N_in ( p1401 ) , .prog_clk_2_S_in ( p251 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_9662 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_9663 ) , - .prog_clk_3_S_in ( p2815 ) , .prog_clk_3_N_in ( p1068 ) , + .prog_clk_3_S_in ( p2263 ) , .prog_clk_3_N_in ( p740 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_9664 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9665 ) , .clk_2_N_in ( p2828 ) , - .clk_2_S_in ( p2880 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9666 ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9667 ) , .clk_3_S_in ( p2941 ) , - .clk_3_N_in ( p2746 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9668 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9665 ) , .clk_2_N_in ( p2623 ) , + .clk_2_S_in ( p2653 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9666 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9667 ) , .clk_3_S_in ( p2763 ) , + .clk_3_N_in ( p2412 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9668 ) , .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9669 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; cby_1__1_ cby_9__11_ ( .pReset ( { SYNOPSYS_UNCONNECTED_9670 } ) , @@ -156532,15 +160098,15 @@ cby_1__1_ cby_9__11_ ( .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_9681 ) , .prog_clk_2_S_in ( prog_clk_2_wires[110] ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_9682 ) , - .prog_clk_2_N_out ( prog_clk_2_wires[111] ) , .prog_clk_3_S_in ( p1580 ) , - .prog_clk_3_N_in ( p420 ) , + .prog_clk_2_N_out ( prog_clk_2_wires[111] ) , .prog_clk_3_S_in ( p1286 ) , + .prog_clk_3_N_in ( p651 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_9683 ) , .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9684 ) , .clk_2_N_in ( SYNOPSYS_UNCONNECTED_9685 ) , .clk_2_S_in ( clk_2_wires[110] ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9686 ) , - .clk_2_N_out ( clk_2_wires[111] ) , .clk_3_S_in ( p1580 ) , - .clk_3_N_in ( p493 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9687 ) , + .clk_2_N_out ( clk_2_wires[111] ) , .clk_3_S_in ( p1286 ) , + .clk_3_N_in ( p775 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9687 ) , .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9688 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; cby_1__1_ cby_9__12_ ( .pReset ( { SYNOPSYS_UNCONNECTED_9689 } ) , @@ -156581,16 +160147,16 @@ cby_1__1_ cby_9__12_ ( .Reset_E_out ( ResetWires[283] ) , .prog_clk_0_W_in ( prog_clk_0_wires[363] ) , .prog_clk_0_S_out ( prog_clk_0_wires[364] ) , - .prog_clk_0_N_out ( prog_clk_0_wires[366] ) , .prog_clk_2_N_in ( p2786 ) , - .prog_clk_2_S_in ( p463 ) , + .prog_clk_0_N_out ( prog_clk_0_wires[366] ) , .prog_clk_2_N_in ( p1593 ) , + .prog_clk_2_S_in ( p472 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_9699 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_9700 ) , - .prog_clk_3_S_in ( p3266 ) , .prog_clk_3_N_in ( p2772 ) , + .prog_clk_3_S_in ( p3026 ) , .prog_clk_3_N_in ( p770 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_9701 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9702 ) , .clk_2_N_in ( p3059 ) , - .clk_2_S_in ( p3238 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9703 ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9704 ) , .clk_3_S_in ( p3195 ) , - .clk_3_N_in ( p3032 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9705 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9702 ) , .clk_2_N_in ( p1929 ) , + .clk_2_S_in ( p2916 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9703 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9704 ) , .clk_3_S_in ( p2758 ) , + .clk_3_N_in ( p1685 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9705 ) , .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9706 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; cby_1__1_ cby_10__1_ ( .pReset ( { SYNOPSYS_UNCONNECTED_9707 } ) , @@ -156632,15 +160198,15 @@ cby_1__1_ cby_10__1_ ( .prog_clk_0_W_in ( prog_clk_0_wires[368] ) , .prog_clk_0_S_out ( prog_clk_0_wires[369] ) , .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_9717 ) , - .prog_clk_2_N_in ( p1788 ) , .prog_clk_2_S_in ( p171 ) , + .prog_clk_2_N_in ( p1865 ) , .prog_clk_2_S_in ( p643 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_9718 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_9719 ) , - .prog_clk_3_S_in ( p2217 ) , .prog_clk_3_N_in ( p1716 ) , + .prog_clk_3_S_in ( p2341 ) , .prog_clk_3_N_in ( p1804 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_9720 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9721 ) , .clk_2_N_in ( p2627 ) , - .clk_2_S_in ( p2031 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9722 ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9723 ) , .clk_3_S_in ( p2221 ) , - .clk_3_N_in ( p2524 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9724 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9721 ) , .clk_2_N_in ( p3354 ) , + .clk_2_S_in ( p2123 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9722 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9723 ) , .clk_3_S_in ( p2029 ) , + .clk_3_N_in ( p3290 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9724 ) , .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9725 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; cby_1__1_ cby_10__2_ ( .pReset ( { SYNOPSYS_UNCONNECTED_9726 } ) , @@ -156682,15 +160248,15 @@ cby_1__1_ cby_10__2_ ( .prog_clk_0_W_in ( prog_clk_0_wires[371] ) , .prog_clk_0_S_out ( prog_clk_0_wires[372] ) , .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_9736 ) , - .prog_clk_2_N_in ( p2148 ) , .prog_clk_2_S_in ( p932 ) , + .prog_clk_2_N_in ( p1619 ) , .prog_clk_2_S_in ( p301 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_9737 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_9738 ) , - .prog_clk_3_S_in ( p2664 ) , .prog_clk_3_N_in ( p2089 ) , + .prog_clk_3_S_in ( p2609 ) , .prog_clk_3_N_in ( p154 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_9739 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9740 ) , .clk_2_N_in ( p2856 ) , - .clk_2_S_in ( p2603 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9741 ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9742 ) , .clk_3_S_in ( p2116 ) , - .clk_3_N_in ( p2744 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9743 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9740 ) , .clk_2_N_in ( p3158 ) , + .clk_2_S_in ( p2668 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9741 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9742 ) , .clk_3_S_in ( p2853 ) , + .clk_3_N_in ( p3058 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9743 ) , .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9744 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; cby_1__1_ cby_10__3_ ( .pReset ( { SYNOPSYS_UNCONNECTED_9745 } ) , @@ -156732,14 +160298,14 @@ cby_1__1_ cby_10__3_ ( .prog_clk_0_W_in ( prog_clk_0_wires[374] ) , .prog_clk_0_S_out ( prog_clk_0_wires[375] ) , .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_9755 ) , - .prog_clk_2_N_in ( p1918 ) , .prog_clk_2_S_in ( p1065 ) , + .prog_clk_2_N_in ( p1913 ) , .prog_clk_2_S_in ( p648 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_9756 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_9757 ) , .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_9758 ) , .prog_clk_3_N_in ( prog_clk_3_wires[86] ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_9759 ) , - .prog_clk_3_S_out ( prog_clk_3_wires[87] ) , .clk_2_N_in ( p1838 ) , - .clk_2_S_in ( p736 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9760 ) , + .prog_clk_3_S_out ( prog_clk_3_wires[87] ) , .clk_2_N_in ( p1913 ) , + .clk_2_S_in ( p896 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9760 ) , .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9761 ) , .clk_3_S_in ( SYNOPSYS_UNCONNECTED_9762 ) , .clk_3_N_in ( clk_3_wires[86] ) , @@ -156785,14 +160351,14 @@ cby_1__1_ cby_10__4_ ( .prog_clk_0_W_in ( prog_clk_0_wires[377] ) , .prog_clk_0_S_out ( prog_clk_0_wires[378] ) , .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_9774 ) , - .prog_clk_2_N_in ( p1437 ) , .prog_clk_2_S_in ( p2559 ) , + .prog_clk_2_N_in ( p1437 ) , .prog_clk_2_S_in ( p1696 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_9775 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_9776 ) , .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_9777 ) , .prog_clk_3_N_in ( prog_clk_3_wires[82] ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_9778 ) , .prog_clk_3_S_out ( prog_clk_3_wires[83] ) , .clk_2_N_in ( p1437 ) , - .clk_2_S_in ( p2864 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9779 ) , + .clk_2_S_in ( p1826 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9779 ) , .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9780 ) , .clk_3_S_in ( SYNOPSYS_UNCONNECTED_9781 ) , .clk_3_N_in ( clk_3_wires[82] ) , @@ -156838,14 +160404,14 @@ cby_1__1_ cby_10__5_ ( .prog_clk_0_W_in ( prog_clk_0_wires[380] ) , .prog_clk_0_S_out ( prog_clk_0_wires[381] ) , .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_9793 ) , - .prog_clk_2_N_in ( p1120 ) , .prog_clk_2_S_in ( p317 ) , + .prog_clk_2_N_in ( p1446 ) , .prog_clk_2_S_in ( p891 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_9794 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_9795 ) , .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_9796 ) , .prog_clk_3_N_in ( prog_clk_3_wires[76] ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_9797 ) , - .prog_clk_3_S_out ( prog_clk_3_wires[77] ) , .clk_2_N_in ( p1120 ) , - .clk_2_S_in ( p899 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9798 ) , + .prog_clk_3_S_out ( prog_clk_3_wires[77] ) , .clk_2_N_in ( p1446 ) , + .clk_2_S_in ( p77 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9798 ) , .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9799 ) , .clk_3_S_in ( SYNOPSYS_UNCONNECTED_9800 ) , .clk_3_N_in ( clk_3_wires[76] ) , @@ -156891,14 +160457,14 @@ cby_1__1_ cby_10__6_ ( .prog_clk_0_W_in ( prog_clk_0_wires[383] ) , .prog_clk_0_S_out ( prog_clk_0_wires[384] ) , .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_9812 ) , - .prog_clk_2_N_in ( p1897 ) , .prog_clk_2_S_in ( p2528 ) , + .prog_clk_2_N_in ( p1466 ) , .prog_clk_2_S_in ( p2719 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_9813 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_9814 ) , .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_9815 ) , .prog_clk_3_N_in ( prog_clk_3_wires[72] ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_9816 ) , - .prog_clk_3_S_out ( prog_clk_3_wires[73] ) , .clk_2_N_in ( p1917 ) , - .clk_2_S_in ( p2601 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9817 ) , + .prog_clk_3_S_out ( prog_clk_3_wires[73] ) , .clk_2_N_in ( p1466 ) , + .clk_2_S_in ( p2875 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9817 ) , .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9818 ) , .clk_3_S_in ( SYNOPSYS_UNCONNECTED_9819 ) , .clk_3_N_in ( clk_3_wires[72] ) , @@ -156944,14 +160510,14 @@ cby_1__1_ cby_10__7_ ( .prog_clk_0_W_in ( prog_clk_0_wires[386] ) , .prog_clk_0_S_out ( prog_clk_0_wires[387] ) , .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_9831 ) , - .prog_clk_2_N_in ( p1532 ) , .prog_clk_2_S_in ( p2087 ) , + .prog_clk_2_N_in ( p1569 ) , .prog_clk_2_S_in ( p416 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_9832 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_9833 ) , .prog_clk_3_S_in ( prog_clk_3_wires[70] ) , .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_9834 ) , .prog_clk_3_N_out ( prog_clk_3_wires[71] ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9835 ) , .clk_2_N_in ( p1532 ) , - .clk_2_S_in ( p2030 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9836 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9835 ) , .clk_2_N_in ( p1569 ) , + .clk_2_S_in ( p2396 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9836 ) , .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9837 ) , .clk_3_S_in ( clk_3_wires[70] ) , .clk_3_N_in ( SYNOPSYS_UNCONNECTED_9838 ) , @@ -156997,14 +160563,14 @@ cby_1__1_ cby_10__8_ ( .prog_clk_0_W_in ( prog_clk_0_wires[389] ) , .prog_clk_0_S_out ( prog_clk_0_wires[390] ) , .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_9850 ) , - .prog_clk_2_N_in ( p1612 ) , .prog_clk_2_S_in ( p2731 ) , + .prog_clk_2_N_in ( p1544 ) , .prog_clk_2_S_in ( p250 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_9851 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_9852 ) , .prog_clk_3_S_in ( prog_clk_3_wires[74] ) , .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_9853 ) , .prog_clk_3_N_out ( prog_clk_3_wires[75] ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9854 ) , .clk_2_N_in ( p1612 ) , - .clk_2_S_in ( p2770 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9855 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9854 ) , .clk_2_N_in ( p1544 ) , + .clk_2_S_in ( p824 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9855 ) , .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9856 ) , .clk_3_S_in ( clk_3_wires[74] ) , .clk_3_N_in ( SYNOPSYS_UNCONNECTED_9857 ) , @@ -157050,14 +160616,14 @@ cby_1__1_ cby_10__9_ ( .prog_clk_0_W_in ( prog_clk_0_wires[392] ) , .prog_clk_0_S_out ( prog_clk_0_wires[393] ) , .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_9869 ) , - .prog_clk_2_N_in ( p1923 ) , .prog_clk_2_S_in ( p2039 ) , + .prog_clk_2_N_in ( p1950 ) , .prog_clk_2_S_in ( p450 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_9870 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_9871 ) , .prog_clk_3_S_in ( prog_clk_3_wires[80] ) , .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_9872 ) , .prog_clk_3_N_out ( prog_clk_3_wires[81] ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9873 ) , .clk_2_N_in ( p1923 ) , - .clk_2_S_in ( p702 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9874 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9873 ) , .clk_2_N_in ( p1950 ) , + .clk_2_S_in ( p224 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9874 ) , .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9875 ) , .clk_3_S_in ( clk_3_wires[80] ) , .clk_3_N_in ( SYNOPSYS_UNCONNECTED_9876 ) , @@ -157103,14 +160669,14 @@ cby_1__1_ cby_10__10_ ( .prog_clk_0_W_in ( prog_clk_0_wires[395] ) , .prog_clk_0_S_out ( prog_clk_0_wires[396] ) , .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_9888 ) , - .prog_clk_2_N_in ( p2134 ) , .prog_clk_2_S_in ( p1641 ) , + .prog_clk_2_N_in ( p1345 ) , .prog_clk_2_S_in ( p2071 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_9889 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_9890 ) , .prog_clk_3_S_in ( prog_clk_3_wires[84] ) , .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_9891 ) , .prog_clk_3_N_out ( prog_clk_3_wires[85] ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9892 ) , .clk_2_N_in ( p2134 ) , - .clk_2_S_in ( p1721 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9893 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9892 ) , .clk_2_N_in ( p1345 ) , + .clk_2_S_in ( p2877 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9893 ) , .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9894 ) , .clk_3_S_in ( clk_3_wires[84] ) , .clk_3_N_in ( SYNOPSYS_UNCONNECTED_9895 ) , @@ -157156,15 +160722,15 @@ cby_1__1_ cby_10__11_ ( .prog_clk_0_W_in ( prog_clk_0_wires[398] ) , .prog_clk_0_S_out ( prog_clk_0_wires[399] ) , .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_9907 ) , - .prog_clk_2_N_in ( p2520 ) , .prog_clk_2_S_in ( p735 ) , + .prog_clk_2_N_in ( p1634 ) , .prog_clk_2_S_in ( p661 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_9908 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_9909 ) , - .prog_clk_3_S_in ( p2813 ) , .prog_clk_3_N_in ( p2328 ) , + .prog_clk_3_S_in ( p2954 ) , .prog_clk_3_N_in ( p939 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_9910 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9911 ) , .clk_2_N_in ( p2220 ) , - .clk_2_S_in ( p3115 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9912 ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9913 ) , .clk_3_S_in ( p3185 ) , - .clk_3_N_in ( p2023 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9914 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9911 ) , .clk_2_N_in ( p2601 ) , + .clk_2_S_in ( p2864 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9912 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9913 ) , .clk_3_S_in ( p2820 ) , + .clk_3_N_in ( p2382 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9914 ) , .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9915 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; cby_1__1_ cby_10__12_ ( .pReset ( { SYNOPSYS_UNCONNECTED_9916 } ) , @@ -157205,16 +160771,16 @@ cby_1__1_ cby_10__12_ ( .Reset_E_out ( ResetWires[285] ) , .prog_clk_0_W_in ( prog_clk_0_wires[401] ) , .prog_clk_0_S_out ( prog_clk_0_wires[402] ) , - .prog_clk_0_N_out ( prog_clk_0_wires[404] ) , .prog_clk_2_N_in ( p2405 ) , - .prog_clk_2_S_in ( p504 ) , + .prog_clk_0_N_out ( prog_clk_0_wires[404] ) , .prog_clk_2_N_in ( p1962 ) , + .prog_clk_2_S_in ( p1030 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_9926 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_9927 ) , - .prog_clk_3_S_in ( p2971 ) , .prog_clk_3_N_in ( p2374 ) , + .prog_clk_3_S_in ( p1584 ) , .prog_clk_3_N_in ( p1751 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_9928 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9929 ) , .clk_2_N_in ( p2954 ) , - .clk_2_S_in ( p3155 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9930 ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9931 ) , .clk_3_S_in ( p3180 ) , - .clk_3_N_in ( p2865 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9932 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9929 ) , .clk_2_N_in ( p2643 ) , + .clk_2_S_in ( p2410 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9930 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9931 ) , .clk_3_S_in ( p2485 ) , + .clk_3_N_in ( p2439 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9932 ) , .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9933 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; cby_1__1_ cby_11__1_ ( .pReset ( { SYNOPSYS_UNCONNECTED_9934 } ) , @@ -157256,15 +160822,15 @@ cby_1__1_ cby_11__1_ ( .prog_clk_0_W_in ( prog_clk_0_wires[406] ) , .prog_clk_0_S_out ( prog_clk_0_wires[407] ) , .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_9944 ) , - .prog_clk_2_N_in ( p2246 ) , .prog_clk_2_S_in ( p657 ) , + .prog_clk_2_N_in ( p2220 ) , .prog_clk_2_S_in ( p1001 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_9945 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_9946 ) , - .prog_clk_3_S_in ( p2829 ) , .prog_clk_3_N_in ( p2052 ) , + .prog_clk_3_S_in ( p2226 ) , .prog_clk_3_N_in ( p2133 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_9947 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9948 ) , .clk_2_N_in ( p3258 ) , - .clk_2_S_in ( p2724 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9949 ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9950 ) , .clk_3_S_in ( p1485 ) , - .clk_3_N_in ( p3213 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9951 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9948 ) , .clk_2_N_in ( p1570 ) , + .clk_2_S_in ( p2885 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9949 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9950 ) , .clk_3_S_in ( p2989 ) , + .clk_3_N_in ( p879 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9951 ) , .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9952 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; cby_1__1_ cby_11__2_ ( .pReset ( { SYNOPSYS_UNCONNECTED_9953 } ) , @@ -157310,14 +160876,14 @@ cby_1__1_ cby_11__2_ ( .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_9964 ) , .prog_clk_2_S_out ( prog_clk_2_wires[116] ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_9965 ) , - .prog_clk_3_S_in ( p1309 ) , .prog_clk_3_N_in ( p44 ) , + .prog_clk_3_S_in ( p2005 ) , .prog_clk_3_N_in ( p192 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_9966 ) , .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9967 ) , .clk_2_N_in ( clk_2_wires[115] ) , .clk_2_S_in ( SYNOPSYS_UNCONNECTED_9968 ) , .clk_2_S_out ( clk_2_wires[116] ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9969 ) , .clk_3_S_in ( p1309 ) , - .clk_3_N_in ( p477 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9970 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9969 ) , .clk_3_S_in ( p2005 ) , + .clk_3_N_in ( p979 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9970 ) , .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9971 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; cby_1__1_ cby_11__3_ ( .pReset ( { SYNOPSYS_UNCONNECTED_9972 } ) , @@ -157359,15 +160925,15 @@ cby_1__1_ cby_11__3_ ( .prog_clk_0_W_in ( prog_clk_0_wires[412] ) , .prog_clk_0_S_out ( prog_clk_0_wires[413] ) , .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_9982 ) , - .prog_clk_2_N_in ( p2984 ) , .prog_clk_2_S_in ( p568 ) , + .prog_clk_2_N_in ( p1844 ) , .prog_clk_2_S_in ( p925 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_9983 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_9984 ) , - .prog_clk_3_S_in ( p2172 ) , .prog_clk_3_N_in ( p2901 ) , + .prog_clk_3_S_in ( p2010 ) , .prog_clk_3_N_in ( p1750 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_9985 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9986 ) , .clk_2_N_in ( p3404 ) , - .clk_2_S_in ( p3139 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9987 ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9988 ) , .clk_3_S_in ( p3178 ) , - .clk_3_N_in ( p3384 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9989 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9986 ) , .clk_2_N_in ( p2994 ) , + .clk_2_S_in ( p2138 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9987 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9988 ) , .clk_3_S_in ( p2287 ) , + .clk_3_N_in ( p2880 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9989 ) , .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9990 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; cby_1__1_ cby_11__4_ ( .pReset ( { SYNOPSYS_UNCONNECTED_9991 } ) , @@ -157413,14 +160979,14 @@ cby_1__1_ cby_11__4_ ( .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_10002 ) , .prog_clk_2_S_out ( prog_clk_2_wires[123] ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_10003 ) , - .prog_clk_3_S_in ( p1761 ) , .prog_clk_3_N_in ( p183 ) , + .prog_clk_3_S_in ( p1409 ) , .prog_clk_3_N_in ( p188 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_10004 ) , .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_10005 ) , .clk_2_N_in ( clk_2_wires[122] ) , .clk_2_S_in ( SYNOPSYS_UNCONNECTED_10006 ) , .clk_2_S_out ( clk_2_wires[123] ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_10007 ) , .clk_3_S_in ( p1761 ) , - .clk_3_N_in ( p1032 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_10008 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_10007 ) , .clk_3_S_in ( p1409 ) , + .clk_3_N_in ( p767 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_10008 ) , .clk_3_S_out ( SYNOPSYS_UNCONNECTED_10009 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; cby_1__1_ cby_11__5_ ( @@ -157466,15 +161032,15 @@ cby_1__1_ cby_11__5_ ( .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_10021 ) , .prog_clk_2_S_in ( prog_clk_2_wires[120] ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_10022 ) , - .prog_clk_2_N_out ( prog_clk_2_wires[121] ) , .prog_clk_3_S_in ( p1441 ) , - .prog_clk_3_N_in ( p969 ) , + .prog_clk_2_N_out ( prog_clk_2_wires[121] ) , .prog_clk_3_S_in ( p1161 ) , + .prog_clk_3_N_in ( p579 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_10023 ) , .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_10024 ) , .clk_2_N_in ( SYNOPSYS_UNCONNECTED_10025 ) , .clk_2_S_in ( clk_2_wires[120] ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_10026 ) , - .clk_2_N_out ( clk_2_wires[121] ) , .clk_3_S_in ( p1441 ) , - .clk_3_N_in ( p1049 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_10027 ) , + .clk_2_N_out ( clk_2_wires[121] ) , .clk_3_S_in ( p1589 ) , + .clk_3_N_in ( p485 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_10027 ) , .clk_3_S_out ( SYNOPSYS_UNCONNECTED_10028 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; cby_1__1_ cby_11__6_ ( @@ -157517,15 +161083,15 @@ cby_1__1_ cby_11__6_ ( .prog_clk_0_W_in ( prog_clk_0_wires[421] ) , .prog_clk_0_S_out ( prog_clk_0_wires[422] ) , .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_10039 ) , - .prog_clk_2_N_in ( p1895 ) , .prog_clk_2_S_in ( p781 ) , + .prog_clk_2_N_in ( p2768 ) , .prog_clk_2_S_in ( p262 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_10040 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_10041 ) , - .prog_clk_3_S_in ( p2518 ) , .prog_clk_3_N_in ( p1699 ) , + .prog_clk_3_S_in ( p2849 ) , .prog_clk_3_N_in ( p2723 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_10042 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_10043 ) , .clk_2_N_in ( p2212 ) , - .clk_2_S_in ( p3339 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_10044 ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_10045 ) , .clk_3_S_in ( p3365 ) , - .clk_3_N_in ( p2065 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_10046 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_10043 ) , .clk_2_N_in ( p2942 ) , + .clk_2_S_in ( p2711 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_10044 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_10045 ) , .clk_3_S_in ( p1587 ) , + .clk_3_N_in ( p2869 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_10046 ) , .clk_3_S_out ( SYNOPSYS_UNCONNECTED_10047 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; cby_1__1_ cby_11__7_ ( @@ -157568,15 +161134,15 @@ cby_1__1_ cby_11__7_ ( .prog_clk_0_W_in ( prog_clk_0_wires[424] ) , .prog_clk_0_S_out ( prog_clk_0_wires[425] ) , .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_10058 ) , - .prog_clk_2_N_in ( p2092 ) , .prog_clk_2_S_in ( p458 ) , + .prog_clk_2_N_in ( p1351 ) , .prog_clk_2_S_in ( p766 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_10059 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_10060 ) , - .prog_clk_3_S_in ( p2690 ) , .prog_clk_3_N_in ( p2061 ) , + .prog_clk_3_S_in ( p2950 ) , .prog_clk_3_N_in ( p1163 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_10061 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_10062 ) , .clk_2_N_in ( p2657 ) , - .clk_2_S_in ( p3048 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_10063 ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_10064 ) , .clk_3_S_in ( p3084 ) , - .clk_3_N_in ( p2547 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_10065 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_10062 ) , .clk_2_N_in ( p3014 ) , + .clk_2_S_in ( p2919 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_10063 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_10064 ) , .clk_3_S_in ( p2951 ) , + .clk_3_N_in ( p2912 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_10065 ) , .clk_3_S_out ( SYNOPSYS_UNCONNECTED_10066 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; cby_1__1_ cby_11__8_ ( @@ -157623,14 +161189,14 @@ cby_1__1_ cby_11__8_ ( .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_10078 ) , .prog_clk_2_S_out ( prog_clk_2_wires[130] ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_10079 ) , - .prog_clk_3_S_in ( p1893 ) , .prog_clk_3_N_in ( p574 ) , + .prog_clk_3_S_in ( p1568 ) , .prog_clk_3_N_in ( p1051 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_10080 ) , .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_10081 ) , .clk_2_N_in ( clk_2_wires[129] ) , .clk_2_S_in ( SYNOPSYS_UNCONNECTED_10082 ) , .clk_2_S_out ( clk_2_wires[130] ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_10083 ) , .clk_3_S_in ( p1893 ) , - .clk_3_N_in ( p983 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_10084 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_10083 ) , .clk_3_S_in ( p1568 ) , + .clk_3_N_in ( p239 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_10084 ) , .clk_3_S_out ( SYNOPSYS_UNCONNECTED_10085 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; cby_1__1_ cby_11__9_ ( @@ -157676,15 +161242,15 @@ cby_1__1_ cby_11__9_ ( .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_10097 ) , .prog_clk_2_S_in ( prog_clk_2_wires[127] ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_10098 ) , - .prog_clk_2_N_out ( prog_clk_2_wires[128] ) , .prog_clk_3_S_in ( p1948 ) , - .prog_clk_3_N_in ( p1094 ) , + .prog_clk_2_N_out ( prog_clk_2_wires[128] ) , .prog_clk_3_S_in ( p1938 ) , + .prog_clk_3_N_in ( p713 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_10099 ) , .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_10100 ) , .clk_2_N_in ( SYNOPSYS_UNCONNECTED_10101 ) , .clk_2_S_in ( clk_2_wires[127] ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_10102 ) , - .clk_2_N_out ( clk_2_wires[128] ) , .clk_3_S_in ( p1948 ) , - .clk_3_N_in ( p243 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_10103 ) , + .clk_2_N_out ( clk_2_wires[128] ) , .clk_3_S_in ( p1938 ) , + .clk_3_N_in ( p102 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_10103 ) , .clk_3_S_out ( SYNOPSYS_UNCONNECTED_10104 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; cby_1__1_ cby_11__10_ ( @@ -157727,15 +161293,15 @@ cby_1__1_ cby_11__10_ ( .prog_clk_0_W_in ( prog_clk_0_wires[433] ) , .prog_clk_0_S_out ( prog_clk_0_wires[434] ) , .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_10115 ) , - .prog_clk_2_N_in ( p2975 ) , .prog_clk_2_S_in ( p324 ) , + .prog_clk_2_N_in ( p1535 ) , .prog_clk_2_S_in ( p877 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_10116 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_10117 ) , - .prog_clk_3_S_in ( p2858 ) , .prog_clk_3_N_in ( p2890 ) , + .prog_clk_3_S_in ( p2784 ) , .prog_clk_3_N_in ( p986 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_10118 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_10119 ) , .clk_2_N_in ( p3263 ) , - .clk_2_S_in ( p3208 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_10120 ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_10121 ) , .clk_3_S_in ( p3265 ) , - .clk_3_N_in ( p3227 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_10122 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_10119 ) , .clk_2_N_in ( p2602 ) , + .clk_2_S_in ( p2689 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_10120 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_10121 ) , .clk_3_S_in ( p2842 ) , + .clk_3_N_in ( p2452 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_10122 ) , .clk_3_S_out ( SYNOPSYS_UNCONNECTED_10123 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; cby_1__1_ cby_11__11_ ( @@ -157781,15 +161347,15 @@ cby_1__1_ cby_11__11_ ( .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_10135 ) , .prog_clk_2_S_in ( prog_clk_2_wires[134] ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_10136 ) , - .prog_clk_2_N_out ( prog_clk_2_wires[135] ) , .prog_clk_3_S_in ( p1295 ) , - .prog_clk_3_N_in ( p852 ) , + .prog_clk_2_N_out ( prog_clk_2_wires[135] ) , .prog_clk_3_S_in ( p1463 ) , + .prog_clk_3_N_in ( p978 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_10137 ) , .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_10138 ) , .clk_2_N_in ( SYNOPSYS_UNCONNECTED_10139 ) , .clk_2_S_in ( clk_2_wires[134] ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_10140 ) , - .clk_2_N_out ( clk_2_wires[135] ) , .clk_3_S_in ( p1295 ) , - .clk_3_N_in ( p22 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_10141 ) , + .clk_2_N_out ( clk_2_wires[135] ) , .clk_3_S_in ( p1463 ) , + .clk_3_N_in ( p771 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_10141 ) , .clk_3_S_out ( SYNOPSYS_UNCONNECTED_10142 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; cby_1__1_ cby_11__12_ ( @@ -157831,16 +161397,16 @@ cby_1__1_ cby_11__12_ ( .Reset_E_out ( ResetWires[287] ) , .prog_clk_0_W_in ( prog_clk_0_wires[439] ) , .prog_clk_0_S_out ( prog_clk_0_wires[440] ) , - .prog_clk_0_N_out ( prog_clk_0_wires[442] ) , .prog_clk_2_N_in ( p1455 ) , - .prog_clk_2_S_in ( p496 ) , + .prog_clk_0_N_out ( prog_clk_0_wires[442] ) , .prog_clk_2_N_in ( p1598 ) , + .prog_clk_2_S_in ( p616 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_10153 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_10154 ) , - .prog_clk_3_S_in ( p2993 ) , .prog_clk_3_N_in ( p965 ) , + .prog_clk_3_S_in ( p2362 ) , .prog_clk_3_N_in ( p22 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_10155 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_10156 ) , .clk_2_N_in ( p2623 ) , - .clk_2_S_in ( p3013 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_10157 ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_10158 ) , .clk_3_S_in ( p3056 ) , - .clk_3_N_in ( p2529 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_10159 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_10156 ) , .clk_2_N_in ( p3022 ) , + .clk_2_S_in ( p2461 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_10157 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_10158 ) , .clk_3_S_in ( p2616 ) , + .clk_3_N_in ( p2901 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_10159 ) , .clk_3_S_out ( SYNOPSYS_UNCONNECTED_10160 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; cby_2__1_ cby_12__1_ ( @@ -158281,15 +161847,15 @@ endmodule module fpga_top ( vdda1 , vdda2 , vssa1 , vssa2 , vccd1 , vccd2 , vssd1 , vssd2 , wb_clk_i , wb_rst_i , wbs_stb_i , wbs_cyc_i , wbs_we_i , wbs_sel_i , wbs_dat_i , wbs_adr_i , wbs_ack_o , wbs_dat_o , la_data_in , - la_data_out , la_oen , io_in , io_out , io_oeb , VDD , VSS , - analog_io_0_ , analog_io_10_ , analog_io_11_ , analog_io_12_ , - analog_io_13_ , analog_io_14_ , analog_io_15_ , analog_io_16_ , - analog_io_17_ , analog_io_18_ , analog_io_19_ , analog_io_1_ , - analog_io_20_ , analog_io_21_ , analog_io_22_ , analog_io_23_ , - analog_io_24_ , analog_io_25_ , analog_io_26_ , analog_io_27_ , - analog_io_28_ , analog_io_29_ , analog_io_2_ , analog_io_30_ , - analog_io_3_ , analog_io_4_ , analog_io_5_ , analog_io_6_ , analog_io_7_ , - analog_io_8_ , analog_io_9_ , user_clock2 ) ; + la_data_out , la_oen , io_in , io_out , io_oeb , analog_io_0_ , + analog_io_10_ , analog_io_11_ , analog_io_12_ , analog_io_13_ , + analog_io_14_ , analog_io_15_ , analog_io_16_ , analog_io_17_ , + analog_io_18_ , analog_io_19_ , analog_io_1_ , analog_io_20_ , + analog_io_21_ , analog_io_22_ , analog_io_23_ , analog_io_24_ , + analog_io_25_ , analog_io_26_ , analog_io_27_ , analog_io_28_ , + analog_io_29_ , analog_io_2_ , analog_io_30_ , analog_io_3_ , + analog_io_4_ , analog_io_5_ , analog_io_6_ , analog_io_7_ , analog_io_8_ , + analog_io_9_ , user_clock2 , VDD , VSS ) ; inout vdda1 ; inout vdda2 ; inout vssa1 ; @@ -158314,8 +161880,6 @@ input [127:0] la_oen ; input [37:0] io_in ; output [37:0] io_out ; output [37:0] io_oeb ; -input VDD ; -input VSS ; inout analog_io_0_ ; inout analog_io_10_ ; inout analog_io_11_ ; @@ -158348,6 +161912,8 @@ inout analog_io_7_ ; inout analog_io_8_ ; inout analog_io_9_ ; input user_clock2 ; +input VDD ; +input VSS ; wire [0:143] gfpga_pad_EMBEDDED_IO_HD_SOC_IN ; wire [0:143] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ; @@ -161105,7 +164671,62 @@ fpga_core fpga_core_uut ( .pReset ( io_in[3] ) , .prog_clk ( io_in[37] ) , .p3503 ( optlc_net_3523 ) , .p3504 ( optlc_net_3524 ) , .p3505 ( optlc_net_3525 ) , .p3506 ( optlc_net_3526 ) , .p3507 ( optlc_net_3527 ) , .p3508 ( optlc_net_3528 ) , - .p3509 ( optlc_net_3529 ) ) ; + .p3509 ( optlc_net_3529 ) , .p3510 ( optlc_net_3530 ) , + .p3511 ( optlc_net_3531 ) , .p3512 ( optlc_net_3532 ) , + .p3513 ( optlc_net_3533 ) , .p3514 ( optlc_net_3534 ) , + .p3515 ( optlc_net_3535 ) , .p3516 ( optlc_net_3536 ) , + .p3517 ( optlc_net_3537 ) , .p3518 ( optlc_net_3538 ) , + .p3519 ( optlc_net_3539 ) , .p3520 ( optlc_net_3540 ) , + .p3521 ( optlc_net_3541 ) , .p3522 ( optlc_net_3542 ) , + .p3523 ( optlc_net_3543 ) , .p3524 ( optlc_net_3544 ) , + .p3525 ( optlc_net_3545 ) , .p3526 ( optlc_net_3546 ) , + .p3527 ( optlc_net_3547 ) , .p3528 ( optlc_net_3548 ) , + .p3529 ( optlc_net_3549 ) , .p3530 ( optlc_net_3550 ) , + .p3531 ( optlc_net_3551 ) , .p3532 ( optlc_net_3552 ) , + .p3533 ( optlc_net_3553 ) , .p3534 ( optlc_net_3554 ) , + .p3535 ( optlc_net_3555 ) , .p3536 ( optlc_net_3556 ) , + .p3537 ( optlc_net_3557 ) , .p3538 ( optlc_net_3558 ) , + .p3539 ( optlc_net_3559 ) , .p3540 ( optlc_net_3560 ) , + .p3541 ( optlc_net_3561 ) , .p3542 ( optlc_net_3562 ) , + .p3543 ( optlc_net_3563 ) , .p3544 ( optlc_net_3564 ) , + .p3545 ( optlc_net_3565 ) , .p3546 ( optlc_net_3566 ) , + .p3547 ( optlc_net_3567 ) , .p3548 ( optlc_net_3568 ) , + .p3549 ( optlc_net_3569 ) , .p3550 ( optlc_net_3570 ) , + .p3551 ( optlc_net_3571 ) , .p3552 ( optlc_net_3572 ) , + .p3553 ( optlc_net_3573 ) , .p3554 ( optlc_net_3574 ) , + .p3555 ( optlc_net_3575 ) , .p3556 ( optlc_net_3576 ) , + .p3557 ( optlc_net_3577 ) , .p3558 ( optlc_net_3578 ) , + .p3559 ( optlc_net_3579 ) , .p3560 ( optlc_net_3580 ) , + .p3561 ( optlc_net_3581 ) , .p3562 ( optlc_net_3582 ) , + .p3563 ( optlc_net_3583 ) , .p3564 ( optlc_net_3584 ) , + .p3565 ( optlc_net_3585 ) , .p3566 ( optlc_net_3586 ) , + .p3567 ( optlc_net_3587 ) , .p3568 ( optlc_net_3588 ) , + .p3569 ( optlc_net_3589 ) , .p3570 ( optlc_net_3590 ) , + .p3571 ( optlc_net_3591 ) , .p3572 ( optlc_net_3592 ) , + .p3573 ( optlc_net_3593 ) , .p3574 ( optlc_net_3594 ) , + .p3575 ( optlc_net_3595 ) , .p3576 ( optlc_net_3596 ) , + .p3577 ( optlc_net_3597 ) , .p3578 ( optlc_net_3598 ) , + .p3579 ( optlc_net_3599 ) , .p3580 ( optlc_net_3600 ) , + .p3581 ( optlc_net_3601 ) , .p3582 ( optlc_net_3602 ) , + .p3583 ( optlc_net_3603 ) , .p3584 ( optlc_net_3604 ) , + .p3585 ( optlc_net_3605 ) , .p3586 ( optlc_net_3606 ) , + .p3587 ( optlc_net_3607 ) , .p3588 ( optlc_net_3608 ) , + .p3589 ( optlc_net_3609 ) , .p3590 ( optlc_net_3610 ) , + .p3591 ( optlc_net_3611 ) , .p3592 ( optlc_net_3612 ) , + .p3593 ( optlc_net_3613 ) , .p3594 ( optlc_net_3614 ) , + .p3595 ( optlc_net_3615 ) , .p3596 ( optlc_net_3616 ) , + .p3597 ( optlc_net_3617 ) , .p3598 ( optlc_net_3618 ) , + .p3599 ( optlc_net_3619 ) , .p3600 ( optlc_net_3620 ) , + .p3601 ( optlc_net_3621 ) , .p3602 ( optlc_net_3622 ) , + .p3603 ( optlc_net_3623 ) , .p3604 ( optlc_net_3624 ) , + .p3605 ( optlc_net_3625 ) , .p3606 ( optlc_net_3626 ) , + .p3607 ( optlc_net_3627 ) , .p3608 ( optlc_net_3628 ) , + .p3609 ( optlc_net_3629 ) , .p3610 ( optlc_net_3630 ) , + .p3611 ( optlc_net_3631 ) , .p3612 ( optlc_net_3632 ) , + .p3613 ( optlc_net_3633 ) , .p3614 ( optlc_net_3634 ) , + .p3615 ( optlc_net_3635 ) , .p3616 ( optlc_net_3636 ) , + .p3617 ( optlc_net_3637 ) , .p3618 ( optlc_net_3638 ) , + .p3619 ( optlc_net_3639 ) , .p3620 ( optlc_net_3640 ) ) ; sky130_fd_sc_hd__conb_1 optlc_0 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , .HI ( io_oeb[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__conb_1 optlc_1 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , @@ -161148,2595 +164769,2595 @@ sky130_fd_sc_hd__conb_1 optlc_19 ( .LO ( io_out[37] ) , .HI ( SYNOPSYS_UNCONNECTED_21 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__conb_1 optlc_21 ( .LO ( optlc_net_20 ) , .HI ( SYNOPSYS_UNCONNECTED_22 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_23 ( .LO ( optlc_net_21 ) , +sky130_fd_sc_hd__conb_1 optlc_22 ( .LO ( optlc_net_21 ) , .HI ( SYNOPSYS_UNCONNECTED_23 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_24 ( .LO ( optlc_net_22 ) , +sky130_fd_sc_hd__conb_1 optlc_23 ( .LO ( optlc_net_22 ) , .HI ( SYNOPSYS_UNCONNECTED_24 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_25 ( .LO ( optlc_net_23 ) , +sky130_fd_sc_hd__conb_1 optlc_24 ( .LO ( optlc_net_23 ) , .HI ( SYNOPSYS_UNCONNECTED_25 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_26 ( .LO ( optlc_net_24 ) , +sky130_fd_sc_hd__conb_1 optlc_25 ( .LO ( optlc_net_24 ) , .HI ( SYNOPSYS_UNCONNECTED_26 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_27 ( .LO ( optlc_net_25 ) , +sky130_fd_sc_hd__conb_1 optlc_26 ( .LO ( optlc_net_25 ) , .HI ( SYNOPSYS_UNCONNECTED_27 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_28 ( .LO ( optlc_net_26 ) , +sky130_fd_sc_hd__conb_1 optlc_27 ( .LO ( optlc_net_26 ) , .HI ( SYNOPSYS_UNCONNECTED_28 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_29 ( .LO ( optlc_net_27 ) , +sky130_fd_sc_hd__conb_1 optlc_28 ( .LO ( optlc_net_27 ) , .HI ( SYNOPSYS_UNCONNECTED_29 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_30 ( .LO ( optlc_net_28 ) , +sky130_fd_sc_hd__conb_1 optlc_29 ( .LO ( optlc_net_28 ) , .HI ( SYNOPSYS_UNCONNECTED_30 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_31 ( .LO ( optlc_net_29 ) , +sky130_fd_sc_hd__conb_1 optlc_30 ( .LO ( optlc_net_29 ) , .HI ( SYNOPSYS_UNCONNECTED_31 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_32 ( .LO ( optlc_net_30 ) , +sky130_fd_sc_hd__conb_1 optlc_31 ( .LO ( optlc_net_30 ) , .HI ( SYNOPSYS_UNCONNECTED_32 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_33 ( .LO ( optlc_net_31 ) , +sky130_fd_sc_hd__conb_1 optlc_32 ( .LO ( optlc_net_31 ) , .HI ( SYNOPSYS_UNCONNECTED_33 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_34 ( .LO ( optlc_net_32 ) , +sky130_fd_sc_hd__conb_1 optlc_33 ( .LO ( optlc_net_32 ) , .HI ( SYNOPSYS_UNCONNECTED_34 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_35 ( .LO ( optlc_net_33 ) , +sky130_fd_sc_hd__conb_1 optlc_34 ( .LO ( optlc_net_33 ) , .HI ( SYNOPSYS_UNCONNECTED_35 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_36 ( .LO ( optlc_net_34 ) , +sky130_fd_sc_hd__conb_1 optlc_35 ( .LO ( optlc_net_34 ) , .HI ( SYNOPSYS_UNCONNECTED_36 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_37 ( .LO ( optlc_net_35 ) , +sky130_fd_sc_hd__conb_1 optlc_36 ( .LO ( optlc_net_35 ) , .HI ( SYNOPSYS_UNCONNECTED_37 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_38 ( .LO ( optlc_net_36 ) , +sky130_fd_sc_hd__conb_1 optlc_37 ( .LO ( optlc_net_36 ) , .HI ( SYNOPSYS_UNCONNECTED_38 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_39 ( .LO ( optlc_net_37 ) , +sky130_fd_sc_hd__conb_1 optlc_38 ( .LO ( optlc_net_37 ) , .HI ( SYNOPSYS_UNCONNECTED_39 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_40 ( .LO ( optlc_net_38 ) , +sky130_fd_sc_hd__conb_1 optlc_39 ( .LO ( optlc_net_38 ) , .HI ( SYNOPSYS_UNCONNECTED_40 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_41 ( .LO ( optlc_net_39 ) , +sky130_fd_sc_hd__conb_1 optlc_40 ( .LO ( optlc_net_39 ) , .HI ( SYNOPSYS_UNCONNECTED_41 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_42 ( .LO ( optlc_net_40 ) , +sky130_fd_sc_hd__conb_1 optlc_41 ( .LO ( optlc_net_40 ) , .HI ( SYNOPSYS_UNCONNECTED_42 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_43 ( .LO ( optlc_net_41 ) , +sky130_fd_sc_hd__conb_1 optlc_42 ( .LO ( optlc_net_41 ) , .HI ( SYNOPSYS_UNCONNECTED_43 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_44 ( .LO ( optlc_net_42 ) , +sky130_fd_sc_hd__conb_1 optlc_43 ( .LO ( optlc_net_42 ) , .HI ( SYNOPSYS_UNCONNECTED_44 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_45 ( .LO ( optlc_net_43 ) , +sky130_fd_sc_hd__conb_1 optlc_44 ( .LO ( optlc_net_43 ) , .HI ( SYNOPSYS_UNCONNECTED_45 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_46 ( .LO ( optlc_net_44 ) , +sky130_fd_sc_hd__conb_1 optlc_45 ( .LO ( optlc_net_44 ) , .HI ( SYNOPSYS_UNCONNECTED_46 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_47 ( .LO ( optlc_net_45 ) , +sky130_fd_sc_hd__conb_1 optlc_46 ( .LO ( optlc_net_45 ) , .HI ( SYNOPSYS_UNCONNECTED_47 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_48 ( .LO ( optlc_net_46 ) , +sky130_fd_sc_hd__conb_1 optlc_47 ( .LO ( optlc_net_46 ) , .HI ( SYNOPSYS_UNCONNECTED_48 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_49 ( .LO ( optlc_net_47 ) , +sky130_fd_sc_hd__conb_1 optlc_48 ( .LO ( optlc_net_47 ) , .HI ( SYNOPSYS_UNCONNECTED_49 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_50 ( .LO ( optlc_net_48 ) , +sky130_fd_sc_hd__conb_1 optlc_49 ( .LO ( optlc_net_48 ) , .HI ( SYNOPSYS_UNCONNECTED_50 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_51 ( .LO ( optlc_net_49 ) , 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optlc_406 ( .LO ( optlc_net_404 ) , +sky130_fd_sc_hd__conb_1 optlc_405 ( .LO ( optlc_net_404 ) , .HI ( SYNOPSYS_UNCONNECTED_406 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_407 ( .LO ( optlc_net_405 ) , +sky130_fd_sc_hd__conb_1 optlc_406 ( .LO ( optlc_net_405 ) , .HI ( SYNOPSYS_UNCONNECTED_407 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_408 ( .LO ( optlc_net_406 ) , +sky130_fd_sc_hd__conb_1 optlc_407 ( .LO ( optlc_net_406 ) , .HI ( SYNOPSYS_UNCONNECTED_408 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_409 ( .LO ( optlc_net_407 ) , +sky130_fd_sc_hd__conb_1 optlc_408 ( .LO ( optlc_net_407 ) , .HI ( SYNOPSYS_UNCONNECTED_409 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_410 ( .LO ( optlc_net_408 ) , +sky130_fd_sc_hd__conb_1 optlc_409 ( .LO ( optlc_net_408 ) , .HI ( SYNOPSYS_UNCONNECTED_410 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_411 ( .LO ( optlc_net_409 ) , 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optlc_net_414 ) , .HI ( SYNOPSYS_UNCONNECTED_416 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_417 ( .LO ( optlc_net_415 ) , +sky130_fd_sc_hd__conb_1 optlc_416 ( .LO ( optlc_net_415 ) , .HI ( SYNOPSYS_UNCONNECTED_417 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_418 ( .LO ( optlc_net_416 ) , +sky130_fd_sc_hd__conb_1 optlc_417 ( .LO ( optlc_net_416 ) , .HI ( SYNOPSYS_UNCONNECTED_418 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_419 ( .LO ( optlc_net_417 ) , +sky130_fd_sc_hd__conb_1 optlc_418 ( .LO ( optlc_net_417 ) , .HI ( SYNOPSYS_UNCONNECTED_419 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_420 ( .LO ( optlc_net_418 ) , +sky130_fd_sc_hd__conb_1 optlc_419 ( .LO ( optlc_net_418 ) , .HI ( SYNOPSYS_UNCONNECTED_420 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_421 ( .LO ( optlc_net_419 ) , +sky130_fd_sc_hd__conb_1 optlc_420 ( .LO ( optlc_net_419 ) , .HI ( SYNOPSYS_UNCONNECTED_421 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_422 ( .LO ( optlc_net_420 ) , +sky130_fd_sc_hd__conb_1 optlc_421 ( .LO ( optlc_net_420 ) , .HI ( SYNOPSYS_UNCONNECTED_422 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_423 ( .LO ( optlc_net_421 ) , +sky130_fd_sc_hd__conb_1 optlc_422 ( .LO ( optlc_net_421 ) , .HI ( SYNOPSYS_UNCONNECTED_423 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_424 ( .LO ( optlc_net_422 ) , +sky130_fd_sc_hd__conb_1 optlc_423 ( .LO ( optlc_net_422 ) , .HI ( SYNOPSYS_UNCONNECTED_424 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_425 ( .LO ( optlc_net_423 ) , +sky130_fd_sc_hd__conb_1 optlc_424 ( .LO ( optlc_net_423 ) , .HI ( SYNOPSYS_UNCONNECTED_425 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_426 ( .LO ( optlc_net_424 ) , +sky130_fd_sc_hd__conb_1 optlc_425 ( .LO ( optlc_net_424 ) , .HI ( SYNOPSYS_UNCONNECTED_426 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_427 ( .LO ( optlc_net_425 ) , +sky130_fd_sc_hd__conb_1 optlc_426 ( .LO ( optlc_net_425 ) , .HI ( SYNOPSYS_UNCONNECTED_427 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_428 ( .LO ( optlc_net_426 ) , +sky130_fd_sc_hd__conb_1 optlc_427 ( .LO ( optlc_net_426 ) , .HI ( SYNOPSYS_UNCONNECTED_428 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_429 ( .LO ( optlc_net_427 ) , +sky130_fd_sc_hd__conb_1 optlc_428 ( .LO ( optlc_net_427 ) , .HI ( SYNOPSYS_UNCONNECTED_429 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_430 ( .LO ( optlc_net_428 ) , +sky130_fd_sc_hd__conb_1 optlc_429 ( .LO ( optlc_net_428 ) , .HI ( SYNOPSYS_UNCONNECTED_430 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_431 ( .LO ( optlc_net_429 ) , +sky130_fd_sc_hd__conb_1 optlc_430 ( .LO ( optlc_net_429 ) , .HI ( SYNOPSYS_UNCONNECTED_431 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_432 ( .LO ( optlc_net_430 ) , +sky130_fd_sc_hd__conb_1 optlc_431 ( .LO ( optlc_net_430 ) , .HI ( SYNOPSYS_UNCONNECTED_432 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_433 ( .LO ( optlc_net_431 ) , +sky130_fd_sc_hd__conb_1 optlc_432 ( .LO ( optlc_net_431 ) , .HI ( SYNOPSYS_UNCONNECTED_433 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_434 ( .LO ( optlc_net_432 ) , +sky130_fd_sc_hd__conb_1 optlc_433 ( .LO ( optlc_net_432 ) , .HI ( SYNOPSYS_UNCONNECTED_434 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_435 ( .LO ( optlc_net_433 ) , +sky130_fd_sc_hd__conb_1 optlc_434 ( .LO ( optlc_net_433 ) , .HI ( SYNOPSYS_UNCONNECTED_435 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_436 ( .LO ( optlc_net_434 ) , +sky130_fd_sc_hd__conb_1 optlc_435 ( .LO ( optlc_net_434 ) , .HI ( SYNOPSYS_UNCONNECTED_436 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_437 ( .LO ( optlc_net_435 ) , +sky130_fd_sc_hd__conb_1 optlc_436 ( .LO ( optlc_net_435 ) , .HI ( SYNOPSYS_UNCONNECTED_437 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_438 ( .LO ( optlc_net_436 ) , +sky130_fd_sc_hd__conb_1 optlc_437 ( .LO ( optlc_net_436 ) , .HI ( SYNOPSYS_UNCONNECTED_438 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_439 ( .LO ( optlc_net_437 ) , +sky130_fd_sc_hd__conb_1 optlc_438 ( .LO ( optlc_net_437 ) , .HI ( SYNOPSYS_UNCONNECTED_439 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_440 ( .LO ( optlc_net_438 ) , +sky130_fd_sc_hd__conb_1 optlc_439 ( .LO ( optlc_net_438 ) , .HI ( SYNOPSYS_UNCONNECTED_440 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_441 ( .LO ( optlc_net_439 ) , +sky130_fd_sc_hd__conb_1 optlc_440 ( .LO ( optlc_net_439 ) , .HI ( SYNOPSYS_UNCONNECTED_441 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_442 ( .LO ( optlc_net_440 ) , +sky130_fd_sc_hd__conb_1 optlc_441 ( .LO ( optlc_net_440 ) , .HI ( SYNOPSYS_UNCONNECTED_442 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_443 ( .LO ( optlc_net_441 ) , +sky130_fd_sc_hd__conb_1 optlc_442 ( .LO ( optlc_net_441 ) , .HI ( SYNOPSYS_UNCONNECTED_443 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_444 ( .LO ( optlc_net_442 ) , +sky130_fd_sc_hd__conb_1 optlc_443 ( .LO ( optlc_net_442 ) , .HI ( SYNOPSYS_UNCONNECTED_444 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_445 ( .LO ( optlc_net_443 ) , +sky130_fd_sc_hd__conb_1 optlc_444 ( .LO ( optlc_net_443 ) , .HI ( SYNOPSYS_UNCONNECTED_445 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_446 ( .LO ( optlc_net_444 ) , +sky130_fd_sc_hd__conb_1 optlc_445 ( .LO ( optlc_net_444 ) , .HI ( SYNOPSYS_UNCONNECTED_446 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_447 ( .LO ( optlc_net_445 ) , +sky130_fd_sc_hd__conb_1 optlc_446 ( .LO ( optlc_net_445 ) , .HI ( SYNOPSYS_UNCONNECTED_447 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_448 ( .LO ( optlc_net_446 ) , +sky130_fd_sc_hd__conb_1 optlc_447 ( .LO ( optlc_net_446 ) , .HI ( SYNOPSYS_UNCONNECTED_448 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_449 ( .LO ( optlc_net_447 ) , +sky130_fd_sc_hd__conb_1 optlc_448 ( .LO ( optlc_net_447 ) , .HI ( SYNOPSYS_UNCONNECTED_449 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_450 ( .LO ( optlc_net_448 ) , +sky130_fd_sc_hd__conb_1 optlc_449 ( .LO ( optlc_net_448 ) , .HI ( SYNOPSYS_UNCONNECTED_450 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_451 ( .LO ( optlc_net_449 ) , +sky130_fd_sc_hd__conb_1 optlc_450 ( .LO ( optlc_net_449 ) , .HI ( SYNOPSYS_UNCONNECTED_451 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_452 ( .LO ( optlc_net_450 ) , +sky130_fd_sc_hd__conb_1 optlc_451 ( .LO ( optlc_net_450 ) , .HI ( SYNOPSYS_UNCONNECTED_452 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_453 ( .LO ( optlc_net_451 ) , +sky130_fd_sc_hd__conb_1 optlc_452 ( .LO ( optlc_net_451 ) , .HI ( SYNOPSYS_UNCONNECTED_453 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_454 ( .LO ( optlc_net_452 ) , +sky130_fd_sc_hd__conb_1 optlc_453 ( .LO ( optlc_net_452 ) , .HI ( SYNOPSYS_UNCONNECTED_454 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_455 ( .LO ( optlc_net_453 ) , +sky130_fd_sc_hd__conb_1 optlc_454 ( .LO ( optlc_net_453 ) , .HI ( SYNOPSYS_UNCONNECTED_455 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_456 ( .LO ( optlc_net_454 ) , +sky130_fd_sc_hd__conb_1 optlc_455 ( .LO ( optlc_net_454 ) , .HI ( SYNOPSYS_UNCONNECTED_456 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_457 ( .LO ( optlc_net_455 ) , +sky130_fd_sc_hd__conb_1 optlc_456 ( .LO ( optlc_net_455 ) , .HI ( SYNOPSYS_UNCONNECTED_457 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_458 ( .LO ( optlc_net_456 ) , +sky130_fd_sc_hd__conb_1 optlc_457 ( .LO ( optlc_net_456 ) , .HI ( SYNOPSYS_UNCONNECTED_458 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_459 ( .LO ( optlc_net_457 ) , +sky130_fd_sc_hd__conb_1 optlc_458 ( .LO ( optlc_net_457 ) , .HI ( SYNOPSYS_UNCONNECTED_459 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_460 ( .LO ( optlc_net_458 ) , +sky130_fd_sc_hd__conb_1 optlc_459 ( .LO ( optlc_net_458 ) , .HI ( SYNOPSYS_UNCONNECTED_460 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_461 ( .LO ( optlc_net_459 ) , +sky130_fd_sc_hd__conb_1 optlc_460 ( .LO ( optlc_net_459 ) , .HI ( SYNOPSYS_UNCONNECTED_461 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_462 ( .LO ( optlc_net_460 ) , +sky130_fd_sc_hd__conb_1 optlc_461 ( .LO ( optlc_net_460 ) , .HI ( SYNOPSYS_UNCONNECTED_462 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_463 ( .LO ( optlc_net_461 ) , +sky130_fd_sc_hd__conb_1 optlc_462 ( .LO ( optlc_net_461 ) , .HI ( SYNOPSYS_UNCONNECTED_463 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_464 ( .LO ( optlc_net_462 ) , +sky130_fd_sc_hd__conb_1 optlc_463 ( .LO ( optlc_net_462 ) , .HI ( SYNOPSYS_UNCONNECTED_464 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_465 ( .LO ( optlc_net_463 ) , +sky130_fd_sc_hd__conb_1 optlc_464 ( .LO ( optlc_net_463 ) , .HI ( SYNOPSYS_UNCONNECTED_465 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_466 ( .LO ( optlc_net_464 ) , +sky130_fd_sc_hd__conb_1 optlc_465 ( .LO ( optlc_net_464 ) , .HI ( SYNOPSYS_UNCONNECTED_466 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_467 ( .LO ( optlc_net_465 ) , +sky130_fd_sc_hd__conb_1 optlc_466 ( .LO ( optlc_net_465 ) , .HI ( SYNOPSYS_UNCONNECTED_467 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_468 ( .LO ( optlc_net_466 ) , +sky130_fd_sc_hd__conb_1 optlc_467 ( .LO ( optlc_net_466 ) , .HI ( SYNOPSYS_UNCONNECTED_468 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_469 ( .LO ( optlc_net_467 ) , +sky130_fd_sc_hd__conb_1 optlc_468 ( .LO ( optlc_net_467 ) , .HI ( SYNOPSYS_UNCONNECTED_469 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_470 ( .LO ( optlc_net_468 ) , +sky130_fd_sc_hd__conb_1 optlc_469 ( .LO ( optlc_net_468 ) , .HI ( SYNOPSYS_UNCONNECTED_470 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_471 ( .LO ( optlc_net_469 ) , +sky130_fd_sc_hd__conb_1 optlc_470 ( .LO ( optlc_net_469 ) , .HI ( SYNOPSYS_UNCONNECTED_471 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_472 ( .LO ( optlc_net_470 ) , +sky130_fd_sc_hd__conb_1 optlc_471 ( .LO ( optlc_net_470 ) , .HI ( SYNOPSYS_UNCONNECTED_472 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_473 ( .LO ( optlc_net_471 ) , +sky130_fd_sc_hd__conb_1 optlc_472 ( .LO ( optlc_net_471 ) , .HI ( SYNOPSYS_UNCONNECTED_473 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_474 ( .LO ( optlc_net_472 ) , +sky130_fd_sc_hd__conb_1 optlc_473 ( .LO ( optlc_net_472 ) , .HI ( SYNOPSYS_UNCONNECTED_474 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_475 ( .LO ( optlc_net_473 ) , +sky130_fd_sc_hd__conb_1 optlc_474 ( .LO ( optlc_net_473 ) , .HI ( SYNOPSYS_UNCONNECTED_475 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_476 ( .LO ( optlc_net_474 ) , +sky130_fd_sc_hd__conb_1 optlc_475 ( .LO ( optlc_net_474 ) , .HI ( SYNOPSYS_UNCONNECTED_476 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_477 ( .LO ( optlc_net_475 ) , +sky130_fd_sc_hd__conb_1 optlc_476 ( .LO ( optlc_net_475 ) , .HI ( SYNOPSYS_UNCONNECTED_477 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_478 ( .LO ( optlc_net_476 ) , +sky130_fd_sc_hd__conb_1 optlc_477 ( .LO ( optlc_net_476 ) , .HI ( SYNOPSYS_UNCONNECTED_478 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_479 ( .LO ( optlc_net_477 ) , +sky130_fd_sc_hd__conb_1 optlc_478 ( .LO ( optlc_net_477 ) , .HI ( SYNOPSYS_UNCONNECTED_479 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_480 ( .LO ( optlc_net_478 ) , +sky130_fd_sc_hd__conb_1 optlc_479 ( .LO ( optlc_net_478 ) , .HI ( SYNOPSYS_UNCONNECTED_480 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_481 ( .LO ( optlc_net_479 ) , +sky130_fd_sc_hd__conb_1 optlc_480 ( .LO ( optlc_net_479 ) , .HI ( SYNOPSYS_UNCONNECTED_481 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_482 ( .LO ( optlc_net_480 ) , +sky130_fd_sc_hd__conb_1 optlc_481 ( .LO ( optlc_net_480 ) , .HI ( SYNOPSYS_UNCONNECTED_482 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_483 ( .LO ( optlc_net_481 ) , +sky130_fd_sc_hd__conb_1 optlc_482 ( .LO ( optlc_net_481 ) , .HI ( SYNOPSYS_UNCONNECTED_483 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_484 ( .LO ( optlc_net_482 ) , +sky130_fd_sc_hd__conb_1 optlc_483 ( .LO ( optlc_net_482 ) , .HI ( SYNOPSYS_UNCONNECTED_484 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_485 ( .LO ( optlc_net_483 ) , +sky130_fd_sc_hd__conb_1 optlc_484 ( .LO ( optlc_net_483 ) , .HI ( SYNOPSYS_UNCONNECTED_485 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_486 ( .LO ( optlc_net_484 ) , +sky130_fd_sc_hd__conb_1 optlc_485 ( .LO ( optlc_net_484 ) , .HI ( SYNOPSYS_UNCONNECTED_486 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_487 ( .LO ( optlc_net_485 ) , +sky130_fd_sc_hd__conb_1 optlc_486 ( .LO ( optlc_net_485 ) , .HI ( SYNOPSYS_UNCONNECTED_487 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_488 ( .LO ( optlc_net_486 ) , +sky130_fd_sc_hd__conb_1 optlc_487 ( .LO ( optlc_net_486 ) , .HI ( SYNOPSYS_UNCONNECTED_488 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_489 ( .LO ( optlc_net_487 ) , +sky130_fd_sc_hd__conb_1 optlc_488 ( .LO ( optlc_net_487 ) , .HI ( SYNOPSYS_UNCONNECTED_489 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_490 ( .LO ( optlc_net_488 ) , +sky130_fd_sc_hd__conb_1 optlc_489 ( .LO ( optlc_net_488 ) , .HI ( SYNOPSYS_UNCONNECTED_490 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_491 ( .LO ( optlc_net_489 ) , +sky130_fd_sc_hd__conb_1 optlc_490 ( .LO ( optlc_net_489 ) , .HI ( SYNOPSYS_UNCONNECTED_491 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_492 ( .LO ( optlc_net_490 ) , +sky130_fd_sc_hd__conb_1 optlc_491 ( .LO ( optlc_net_490 ) , .HI ( SYNOPSYS_UNCONNECTED_492 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_493 ( .LO ( optlc_net_491 ) , +sky130_fd_sc_hd__conb_1 optlc_492 ( .LO ( optlc_net_491 ) , .HI ( SYNOPSYS_UNCONNECTED_493 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_494 ( .LO ( optlc_net_492 ) , +sky130_fd_sc_hd__conb_1 optlc_493 ( .LO ( optlc_net_492 ) , .HI ( SYNOPSYS_UNCONNECTED_494 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_495 ( .LO ( optlc_net_493 ) , +sky130_fd_sc_hd__conb_1 optlc_494 ( .LO ( optlc_net_493 ) , .HI ( SYNOPSYS_UNCONNECTED_495 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_496 ( .LO ( optlc_net_494 ) , +sky130_fd_sc_hd__conb_1 optlc_495 ( .LO ( optlc_net_494 ) , .HI ( SYNOPSYS_UNCONNECTED_496 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_497 ( .LO ( optlc_net_495 ) , +sky130_fd_sc_hd__conb_1 optlc_496 ( .LO ( optlc_net_495 ) , .HI ( SYNOPSYS_UNCONNECTED_497 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_498 ( .LO ( optlc_net_496 ) , +sky130_fd_sc_hd__conb_1 optlc_497 ( .LO ( optlc_net_496 ) , .HI ( SYNOPSYS_UNCONNECTED_498 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_499 ( .LO ( optlc_net_497 ) , +sky130_fd_sc_hd__conb_1 optlc_498 ( .LO ( optlc_net_497 ) , .HI ( SYNOPSYS_UNCONNECTED_499 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_500 ( .LO ( optlc_net_498 ) , +sky130_fd_sc_hd__conb_1 optlc_499 ( .LO ( optlc_net_498 ) , .HI ( SYNOPSYS_UNCONNECTED_500 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_501 ( .LO ( optlc_net_499 ) , +sky130_fd_sc_hd__conb_1 optlc_500 ( .LO ( optlc_net_499 ) , .HI ( SYNOPSYS_UNCONNECTED_501 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_502 ( .LO ( optlc_net_500 ) , +sky130_fd_sc_hd__conb_1 optlc_501 ( .LO ( optlc_net_500 ) , .HI ( SYNOPSYS_UNCONNECTED_502 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_503 ( .LO ( optlc_net_501 ) , +sky130_fd_sc_hd__conb_1 optlc_502 ( .LO ( optlc_net_501 ) , .HI ( SYNOPSYS_UNCONNECTED_503 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_504 ( .LO ( optlc_net_502 ) , +sky130_fd_sc_hd__conb_1 optlc_503 ( .LO ( optlc_net_502 ) , .HI ( SYNOPSYS_UNCONNECTED_504 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_505 ( .LO ( optlc_net_503 ) , +sky130_fd_sc_hd__conb_1 optlc_504 ( .LO ( optlc_net_503 ) , .HI ( SYNOPSYS_UNCONNECTED_505 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_506 ( .LO ( optlc_net_504 ) , +sky130_fd_sc_hd__conb_1 optlc_505 ( .LO ( optlc_net_504 ) , .HI ( SYNOPSYS_UNCONNECTED_506 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_507 ( .LO ( optlc_net_505 ) , +sky130_fd_sc_hd__conb_1 optlc_506 ( .LO ( optlc_net_505 ) , .HI ( SYNOPSYS_UNCONNECTED_507 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_508 ( .LO ( optlc_net_506 ) , +sky130_fd_sc_hd__conb_1 optlc_507 ( .LO ( optlc_net_506 ) , .HI ( SYNOPSYS_UNCONNECTED_508 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_509 ( .LO ( optlc_net_507 ) , +sky130_fd_sc_hd__conb_1 optlc_508 ( .LO ( optlc_net_507 ) , .HI ( SYNOPSYS_UNCONNECTED_509 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_510 ( .LO ( optlc_net_508 ) , +sky130_fd_sc_hd__conb_1 optlc_509 ( .LO ( optlc_net_508 ) , .HI ( SYNOPSYS_UNCONNECTED_510 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_511 ( .LO ( optlc_net_509 ) , +sky130_fd_sc_hd__conb_1 optlc_510 ( .LO ( optlc_net_509 ) , .HI ( SYNOPSYS_UNCONNECTED_511 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_512 ( .LO ( optlc_net_510 ) , +sky130_fd_sc_hd__conb_1 optlc_511 ( .LO ( optlc_net_510 ) , .HI ( SYNOPSYS_UNCONNECTED_512 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_513 ( .LO ( optlc_net_511 ) , +sky130_fd_sc_hd__conb_1 optlc_512 ( .LO ( optlc_net_511 ) , .HI ( SYNOPSYS_UNCONNECTED_513 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_514 ( .LO ( optlc_net_512 ) , +sky130_fd_sc_hd__conb_1 optlc_513 ( .LO ( optlc_net_512 ) , .HI ( SYNOPSYS_UNCONNECTED_514 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_515 ( .LO ( optlc_net_513 ) , +sky130_fd_sc_hd__conb_1 optlc_514 ( .LO ( optlc_net_513 ) , .HI ( SYNOPSYS_UNCONNECTED_515 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_516 ( .LO ( optlc_net_514 ) , +sky130_fd_sc_hd__conb_1 optlc_515 ( .LO ( optlc_net_514 ) , .HI ( SYNOPSYS_UNCONNECTED_516 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_517 ( .LO ( optlc_net_515 ) , +sky130_fd_sc_hd__conb_1 optlc_516 ( .LO ( optlc_net_515 ) , .HI ( SYNOPSYS_UNCONNECTED_517 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_518 ( .LO ( optlc_net_516 ) , +sky130_fd_sc_hd__conb_1 optlc_517 ( .LO ( optlc_net_516 ) , .HI ( SYNOPSYS_UNCONNECTED_518 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_519 ( .LO ( optlc_net_517 ) , +sky130_fd_sc_hd__conb_1 optlc_518 ( .LO ( optlc_net_517 ) , .HI ( SYNOPSYS_UNCONNECTED_519 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_520 ( .LO ( optlc_net_518 ) , +sky130_fd_sc_hd__conb_1 optlc_519 ( .LO ( optlc_net_518 ) , .HI ( SYNOPSYS_UNCONNECTED_520 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_521 ( .LO ( optlc_net_519 ) , +sky130_fd_sc_hd__conb_1 optlc_520 ( .LO ( optlc_net_519 ) , .HI ( SYNOPSYS_UNCONNECTED_521 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_522 ( .LO ( optlc_net_520 ) , +sky130_fd_sc_hd__conb_1 optlc_521 ( .LO ( optlc_net_520 ) , .HI ( SYNOPSYS_UNCONNECTED_522 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_523 ( .LO ( optlc_net_521 ) , +sky130_fd_sc_hd__conb_1 optlc_522 ( .LO ( optlc_net_521 ) , .HI ( SYNOPSYS_UNCONNECTED_523 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_524 ( .LO ( optlc_net_522 ) , +sky130_fd_sc_hd__conb_1 optlc_523 ( .LO ( optlc_net_522 ) , .HI ( SYNOPSYS_UNCONNECTED_524 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_525 ( .LO ( optlc_net_523 ) , +sky130_fd_sc_hd__conb_1 optlc_524 ( .LO ( optlc_net_523 ) , .HI ( SYNOPSYS_UNCONNECTED_525 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_526 ( .LO ( optlc_net_524 ) , +sky130_fd_sc_hd__conb_1 optlc_525 ( .LO ( optlc_net_524 ) , .HI ( SYNOPSYS_UNCONNECTED_526 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_527 ( .LO ( optlc_net_525 ) , +sky130_fd_sc_hd__conb_1 optlc_526 ( .LO ( optlc_net_525 ) , .HI ( SYNOPSYS_UNCONNECTED_527 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_528 ( .LO ( optlc_net_526 ) , +sky130_fd_sc_hd__conb_1 optlc_527 ( .LO ( optlc_net_526 ) , .HI ( SYNOPSYS_UNCONNECTED_528 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_529 ( .LO ( optlc_net_527 ) , +sky130_fd_sc_hd__conb_1 optlc_528 ( .LO ( optlc_net_527 ) , .HI ( SYNOPSYS_UNCONNECTED_529 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_530 ( .LO ( optlc_net_528 ) , +sky130_fd_sc_hd__conb_1 optlc_529 ( .LO ( optlc_net_528 ) , .HI ( SYNOPSYS_UNCONNECTED_530 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_531 ( .LO ( optlc_net_529 ) , +sky130_fd_sc_hd__conb_1 optlc_530 ( .LO ( optlc_net_529 ) , .HI ( SYNOPSYS_UNCONNECTED_531 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_532 ( .LO ( optlc_net_530 ) , +sky130_fd_sc_hd__conb_1 optlc_531 ( .LO ( optlc_net_530 ) , .HI ( SYNOPSYS_UNCONNECTED_532 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_533 ( .LO ( optlc_net_531 ) , +sky130_fd_sc_hd__conb_1 optlc_532 ( .LO ( optlc_net_531 ) , .HI ( SYNOPSYS_UNCONNECTED_533 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_534 ( .LO ( optlc_net_532 ) , +sky130_fd_sc_hd__conb_1 optlc_533 ( .LO ( optlc_net_532 ) , .HI ( SYNOPSYS_UNCONNECTED_534 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_535 ( .LO ( optlc_net_533 ) , +sky130_fd_sc_hd__conb_1 optlc_534 ( .LO ( optlc_net_533 ) , .HI ( SYNOPSYS_UNCONNECTED_535 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_536 ( .LO ( optlc_net_534 ) , +sky130_fd_sc_hd__conb_1 optlc_535 ( .LO ( optlc_net_534 ) , .HI ( SYNOPSYS_UNCONNECTED_536 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_537 ( .LO ( optlc_net_535 ) , +sky130_fd_sc_hd__conb_1 optlc_536 ( .LO ( optlc_net_535 ) , .HI ( SYNOPSYS_UNCONNECTED_537 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_538 ( .LO ( optlc_net_536 ) , +sky130_fd_sc_hd__conb_1 optlc_537 ( .LO ( optlc_net_536 ) , .HI ( SYNOPSYS_UNCONNECTED_538 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_539 ( .LO ( optlc_net_537 ) , +sky130_fd_sc_hd__conb_1 optlc_538 ( .LO ( optlc_net_537 ) , .HI ( SYNOPSYS_UNCONNECTED_539 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_540 ( .LO ( optlc_net_538 ) , +sky130_fd_sc_hd__conb_1 optlc_539 ( .LO ( optlc_net_538 ) , .HI ( SYNOPSYS_UNCONNECTED_540 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_541 ( .LO ( optlc_net_539 ) , +sky130_fd_sc_hd__conb_1 optlc_540 ( .LO ( optlc_net_539 ) , .HI ( SYNOPSYS_UNCONNECTED_541 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_542 ( .LO ( optlc_net_540 ) , +sky130_fd_sc_hd__conb_1 optlc_541 ( .LO ( optlc_net_540 ) , .HI ( SYNOPSYS_UNCONNECTED_542 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_543 ( .LO ( optlc_net_541 ) , +sky130_fd_sc_hd__conb_1 optlc_542 ( .LO ( optlc_net_541 ) , .HI ( SYNOPSYS_UNCONNECTED_543 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_544 ( .LO ( optlc_net_542 ) , +sky130_fd_sc_hd__conb_1 optlc_543 ( .LO ( optlc_net_542 ) , .HI ( SYNOPSYS_UNCONNECTED_544 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_545 ( .LO ( optlc_net_543 ) , +sky130_fd_sc_hd__conb_1 optlc_544 ( .LO ( optlc_net_543 ) , .HI ( SYNOPSYS_UNCONNECTED_545 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_546 ( .LO ( optlc_net_544 ) , +sky130_fd_sc_hd__conb_1 optlc_545 ( .LO ( optlc_net_544 ) , .HI ( SYNOPSYS_UNCONNECTED_546 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_547 ( .LO ( optlc_net_545 ) , +sky130_fd_sc_hd__conb_1 optlc_546 ( .LO ( optlc_net_545 ) , .HI ( SYNOPSYS_UNCONNECTED_547 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_548 ( .LO ( optlc_net_546 ) , +sky130_fd_sc_hd__conb_1 optlc_547 ( .LO ( optlc_net_546 ) , .HI ( SYNOPSYS_UNCONNECTED_548 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_549 ( .LO ( optlc_net_547 ) , +sky130_fd_sc_hd__conb_1 optlc_548 ( .LO ( optlc_net_547 ) , .HI ( SYNOPSYS_UNCONNECTED_549 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_550 ( .LO ( optlc_net_548 ) , +sky130_fd_sc_hd__conb_1 optlc_549 ( .LO ( optlc_net_548 ) , .HI ( SYNOPSYS_UNCONNECTED_550 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_551 ( .LO ( optlc_net_549 ) , +sky130_fd_sc_hd__conb_1 optlc_550 ( .LO ( optlc_net_549 ) , .HI ( SYNOPSYS_UNCONNECTED_551 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_552 ( .LO ( optlc_net_550 ) , +sky130_fd_sc_hd__conb_1 optlc_551 ( .LO ( optlc_net_550 ) , .HI ( SYNOPSYS_UNCONNECTED_552 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_553 ( .LO ( optlc_net_551 ) , +sky130_fd_sc_hd__conb_1 optlc_552 ( .LO ( optlc_net_551 ) , .HI ( SYNOPSYS_UNCONNECTED_553 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_554 ( .LO ( optlc_net_552 ) , +sky130_fd_sc_hd__conb_1 optlc_553 ( .LO ( optlc_net_552 ) , .HI ( SYNOPSYS_UNCONNECTED_554 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_555 ( .LO ( optlc_net_553 ) , +sky130_fd_sc_hd__conb_1 optlc_554 ( .LO ( optlc_net_553 ) , .HI ( SYNOPSYS_UNCONNECTED_555 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_556 ( .LO ( optlc_net_554 ) , +sky130_fd_sc_hd__conb_1 optlc_555 ( .LO ( optlc_net_554 ) , .HI ( SYNOPSYS_UNCONNECTED_556 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_557 ( .LO ( optlc_net_555 ) , +sky130_fd_sc_hd__conb_1 optlc_556 ( .LO ( optlc_net_555 ) , .HI ( SYNOPSYS_UNCONNECTED_557 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_558 ( .LO ( optlc_net_556 ) , +sky130_fd_sc_hd__conb_1 optlc_557 ( .LO ( optlc_net_556 ) , .HI ( SYNOPSYS_UNCONNECTED_558 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_559 ( .LO ( optlc_net_557 ) , +sky130_fd_sc_hd__conb_1 optlc_558 ( .LO ( optlc_net_557 ) , .HI ( SYNOPSYS_UNCONNECTED_559 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_561 ( .LO ( optlc_net_558 ) , +sky130_fd_sc_hd__conb_1 optlc_559 ( .LO ( optlc_net_558 ) , .HI ( SYNOPSYS_UNCONNECTED_560 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_562 ( .LO ( optlc_net_559 ) , +sky130_fd_sc_hd__conb_1 optlc_560 ( .LO ( optlc_net_559 ) , .HI ( SYNOPSYS_UNCONNECTED_561 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_563 ( .LO ( optlc_net_560 ) , +sky130_fd_sc_hd__conb_1 optlc_561 ( .LO ( optlc_net_560 ) , .HI ( SYNOPSYS_UNCONNECTED_562 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_564 ( .LO ( optlc_net_561 ) , +sky130_fd_sc_hd__conb_1 optlc_562 ( .LO ( optlc_net_561 ) , .HI ( SYNOPSYS_UNCONNECTED_563 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_565 ( .LO ( optlc_net_562 ) , +sky130_fd_sc_hd__conb_1 optlc_563 ( .LO ( optlc_net_562 ) , .HI ( SYNOPSYS_UNCONNECTED_564 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_566 ( .LO ( optlc_net_563 ) , +sky130_fd_sc_hd__conb_1 optlc_564 ( .LO ( optlc_net_563 ) , .HI ( SYNOPSYS_UNCONNECTED_565 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_567 ( .LO ( optlc_net_564 ) , +sky130_fd_sc_hd__conb_1 optlc_565 ( .LO ( optlc_net_564 ) , .HI ( SYNOPSYS_UNCONNECTED_566 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_568 ( .LO ( optlc_net_565 ) , +sky130_fd_sc_hd__conb_1 optlc_566 ( .LO ( optlc_net_565 ) , .HI ( SYNOPSYS_UNCONNECTED_567 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_569 ( .LO ( optlc_net_566 ) , +sky130_fd_sc_hd__conb_1 optlc_567 ( .LO ( optlc_net_566 ) , .HI ( SYNOPSYS_UNCONNECTED_568 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_570 ( .LO ( optlc_net_567 ) , +sky130_fd_sc_hd__conb_1 optlc_568 ( .LO ( optlc_net_567 ) , .HI ( SYNOPSYS_UNCONNECTED_569 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_571 ( .LO ( optlc_net_568 ) , +sky130_fd_sc_hd__conb_1 optlc_569 ( .LO ( optlc_net_568 ) , .HI ( SYNOPSYS_UNCONNECTED_570 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_572 ( .LO ( optlc_net_569 ) , +sky130_fd_sc_hd__conb_1 optlc_570 ( .LO ( optlc_net_569 ) , .HI ( SYNOPSYS_UNCONNECTED_571 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_573 ( .LO ( optlc_net_570 ) , +sky130_fd_sc_hd__conb_1 optlc_571 ( .LO ( optlc_net_570 ) , .HI ( SYNOPSYS_UNCONNECTED_572 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_574 ( .LO ( optlc_net_571 ) , +sky130_fd_sc_hd__conb_1 optlc_572 ( .LO ( optlc_net_571 ) , .HI ( SYNOPSYS_UNCONNECTED_573 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_575 ( .LO ( optlc_net_572 ) , +sky130_fd_sc_hd__conb_1 optlc_573 ( .LO ( optlc_net_572 ) , .HI ( SYNOPSYS_UNCONNECTED_574 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_576 ( .LO ( optlc_net_573 ) , +sky130_fd_sc_hd__conb_1 optlc_574 ( .LO ( optlc_net_573 ) , .HI ( SYNOPSYS_UNCONNECTED_575 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_577 ( .LO ( optlc_net_574 ) , +sky130_fd_sc_hd__conb_1 optlc_575 ( .LO ( optlc_net_574 ) , .HI ( SYNOPSYS_UNCONNECTED_576 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_578 ( .LO ( optlc_net_575 ) , +sky130_fd_sc_hd__conb_1 optlc_576 ( .LO ( optlc_net_575 ) , .HI ( SYNOPSYS_UNCONNECTED_577 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_579 ( .LO ( optlc_net_576 ) , +sky130_fd_sc_hd__conb_1 optlc_577 ( .LO ( optlc_net_576 ) , .HI ( SYNOPSYS_UNCONNECTED_578 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_580 ( .LO ( optlc_net_577 ) , +sky130_fd_sc_hd__conb_1 optlc_578 ( .LO ( optlc_net_577 ) , .HI ( SYNOPSYS_UNCONNECTED_579 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_581 ( .LO ( optlc_net_578 ) , +sky130_fd_sc_hd__conb_1 optlc_579 ( .LO ( optlc_net_578 ) , .HI ( SYNOPSYS_UNCONNECTED_580 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_582 ( .LO ( optlc_net_579 ) , +sky130_fd_sc_hd__conb_1 optlc_580 ( .LO ( optlc_net_579 ) , .HI ( SYNOPSYS_UNCONNECTED_581 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_583 ( .LO ( optlc_net_580 ) , +sky130_fd_sc_hd__conb_1 optlc_581 ( .LO ( optlc_net_580 ) , .HI ( SYNOPSYS_UNCONNECTED_582 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_584 ( .LO ( optlc_net_581 ) , +sky130_fd_sc_hd__conb_1 optlc_582 ( .LO ( optlc_net_581 ) , .HI ( SYNOPSYS_UNCONNECTED_583 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_585 ( .LO ( optlc_net_582 ) , +sky130_fd_sc_hd__conb_1 optlc_583 ( .LO ( optlc_net_582 ) , .HI ( SYNOPSYS_UNCONNECTED_584 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_586 ( .LO ( optlc_net_583 ) , +sky130_fd_sc_hd__conb_1 optlc_584 ( .LO ( optlc_net_583 ) , .HI ( SYNOPSYS_UNCONNECTED_585 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_587 ( .LO ( optlc_net_584 ) , +sky130_fd_sc_hd__conb_1 optlc_585 ( .LO ( optlc_net_584 ) , .HI ( SYNOPSYS_UNCONNECTED_586 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_588 ( .LO ( optlc_net_585 ) , +sky130_fd_sc_hd__conb_1 optlc_586 ( .LO ( optlc_net_585 ) , .HI ( SYNOPSYS_UNCONNECTED_587 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_589 ( .LO ( optlc_net_586 ) , +sky130_fd_sc_hd__conb_1 optlc_587 ( .LO ( optlc_net_586 ) , .HI ( SYNOPSYS_UNCONNECTED_588 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_590 ( .LO ( optlc_net_587 ) , +sky130_fd_sc_hd__conb_1 optlc_588 ( .LO ( optlc_net_587 ) , .HI ( SYNOPSYS_UNCONNECTED_589 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_591 ( .LO ( optlc_net_588 ) , +sky130_fd_sc_hd__conb_1 optlc_589 ( .LO ( optlc_net_588 ) , .HI ( SYNOPSYS_UNCONNECTED_590 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_592 ( .LO ( optlc_net_589 ) , +sky130_fd_sc_hd__conb_1 optlc_590 ( .LO ( optlc_net_589 ) , .HI ( SYNOPSYS_UNCONNECTED_591 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_593 ( .LO ( optlc_net_590 ) , +sky130_fd_sc_hd__conb_1 optlc_591 ( .LO ( optlc_net_590 ) , .HI ( SYNOPSYS_UNCONNECTED_592 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_594 ( .LO ( optlc_net_591 ) , +sky130_fd_sc_hd__conb_1 optlc_592 ( .LO ( optlc_net_591 ) , .HI ( SYNOPSYS_UNCONNECTED_593 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_595 ( .LO ( optlc_net_592 ) , +sky130_fd_sc_hd__conb_1 optlc_593 ( .LO ( optlc_net_592 ) , .HI ( SYNOPSYS_UNCONNECTED_594 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_596 ( .LO ( optlc_net_593 ) , +sky130_fd_sc_hd__conb_1 optlc_594 ( .LO ( optlc_net_593 ) , .HI ( SYNOPSYS_UNCONNECTED_595 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_597 ( .LO ( optlc_net_594 ) , +sky130_fd_sc_hd__conb_1 optlc_595 ( .LO ( optlc_net_594 ) , .HI ( SYNOPSYS_UNCONNECTED_596 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_598 ( .LO ( optlc_net_595 ) , +sky130_fd_sc_hd__conb_1 optlc_596 ( .LO ( optlc_net_595 ) , .HI ( SYNOPSYS_UNCONNECTED_597 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_599 ( .LO ( optlc_net_596 ) , +sky130_fd_sc_hd__conb_1 optlc_597 ( .LO ( optlc_net_596 ) , .HI ( SYNOPSYS_UNCONNECTED_598 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_600 ( .LO ( optlc_net_597 ) , +sky130_fd_sc_hd__conb_1 optlc_598 ( .LO ( optlc_net_597 ) , .HI ( SYNOPSYS_UNCONNECTED_599 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_601 ( .LO ( optlc_net_598 ) , +sky130_fd_sc_hd__conb_1 optlc_599 ( .LO ( optlc_net_598 ) , .HI ( SYNOPSYS_UNCONNECTED_600 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_602 ( .LO ( optlc_net_599 ) , +sky130_fd_sc_hd__conb_1 optlc_600 ( .LO ( optlc_net_599 ) , .HI ( SYNOPSYS_UNCONNECTED_601 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_603 ( .LO ( optlc_net_600 ) , +sky130_fd_sc_hd__conb_1 optlc_601 ( .LO ( optlc_net_600 ) , .HI ( SYNOPSYS_UNCONNECTED_602 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_604 ( .LO ( optlc_net_601 ) , +sky130_fd_sc_hd__conb_1 optlc_602 ( .LO ( optlc_net_601 ) , .HI ( SYNOPSYS_UNCONNECTED_603 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_605 ( .LO ( optlc_net_602 ) , +sky130_fd_sc_hd__conb_1 optlc_603 ( .LO ( optlc_net_602 ) , .HI ( SYNOPSYS_UNCONNECTED_604 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_606 ( .LO ( optlc_net_603 ) , +sky130_fd_sc_hd__conb_1 optlc_604 ( .LO ( optlc_net_603 ) , .HI ( SYNOPSYS_UNCONNECTED_605 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_607 ( .LO ( optlc_net_604 ) , +sky130_fd_sc_hd__conb_1 optlc_605 ( .LO ( optlc_net_604 ) , .HI ( SYNOPSYS_UNCONNECTED_606 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_608 ( .LO ( optlc_net_605 ) , +sky130_fd_sc_hd__conb_1 optlc_606 ( .LO ( optlc_net_605 ) , .HI ( SYNOPSYS_UNCONNECTED_607 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_609 ( .LO ( optlc_net_606 ) , +sky130_fd_sc_hd__conb_1 optlc_607 ( .LO ( optlc_net_606 ) , .HI ( SYNOPSYS_UNCONNECTED_608 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_610 ( .LO ( optlc_net_607 ) , +sky130_fd_sc_hd__conb_1 optlc_608 ( .LO ( optlc_net_607 ) , .HI ( SYNOPSYS_UNCONNECTED_609 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_611 ( .LO ( optlc_net_608 ) , +sky130_fd_sc_hd__conb_1 optlc_609 ( .LO ( optlc_net_608 ) , .HI ( SYNOPSYS_UNCONNECTED_610 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_612 ( .LO ( optlc_net_609 ) , +sky130_fd_sc_hd__conb_1 optlc_610 ( .LO ( optlc_net_609 ) , .HI ( SYNOPSYS_UNCONNECTED_611 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_613 ( .LO ( optlc_net_610 ) , +sky130_fd_sc_hd__conb_1 optlc_611 ( .LO ( optlc_net_610 ) , .HI ( SYNOPSYS_UNCONNECTED_612 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_614 ( .LO ( optlc_net_611 ) , +sky130_fd_sc_hd__conb_1 optlc_612 ( .LO ( optlc_net_611 ) , .HI ( SYNOPSYS_UNCONNECTED_613 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_615 ( .LO ( optlc_net_612 ) , +sky130_fd_sc_hd__conb_1 optlc_613 ( .LO ( optlc_net_612 ) , .HI ( SYNOPSYS_UNCONNECTED_614 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_616 ( .LO ( optlc_net_613 ) , +sky130_fd_sc_hd__conb_1 optlc_614 ( .LO ( optlc_net_613 ) , .HI ( SYNOPSYS_UNCONNECTED_615 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_617 ( .LO ( optlc_net_614 ) , +sky130_fd_sc_hd__conb_1 optlc_615 ( .LO ( optlc_net_614 ) , .HI ( SYNOPSYS_UNCONNECTED_616 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_618 ( .LO ( optlc_net_615 ) , +sky130_fd_sc_hd__conb_1 optlc_616 ( .LO ( optlc_net_615 ) , .HI ( SYNOPSYS_UNCONNECTED_617 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_619 ( .LO ( optlc_net_616 ) , +sky130_fd_sc_hd__conb_1 optlc_617 ( .LO ( optlc_net_616 ) , .HI ( SYNOPSYS_UNCONNECTED_618 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_620 ( .LO ( optlc_net_617 ) , +sky130_fd_sc_hd__conb_1 optlc_618 ( .LO ( optlc_net_617 ) , .HI ( SYNOPSYS_UNCONNECTED_619 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_621 ( .LO ( optlc_net_618 ) , +sky130_fd_sc_hd__conb_1 optlc_619 ( .LO ( optlc_net_618 ) , .HI ( SYNOPSYS_UNCONNECTED_620 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_622 ( .LO ( optlc_net_619 ) , +sky130_fd_sc_hd__conb_1 optlc_620 ( .LO ( optlc_net_619 ) , .HI ( SYNOPSYS_UNCONNECTED_621 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_623 ( .LO ( optlc_net_620 ) , +sky130_fd_sc_hd__conb_1 optlc_621 ( .LO ( optlc_net_620 ) , .HI ( SYNOPSYS_UNCONNECTED_622 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_624 ( .LO ( optlc_net_621 ) , +sky130_fd_sc_hd__conb_1 optlc_622 ( .LO ( optlc_net_621 ) , .HI ( SYNOPSYS_UNCONNECTED_623 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_625 ( .LO ( optlc_net_622 ) , +sky130_fd_sc_hd__conb_1 optlc_623 ( .LO ( optlc_net_622 ) , .HI ( SYNOPSYS_UNCONNECTED_624 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_626 ( .LO ( optlc_net_623 ) , +sky130_fd_sc_hd__conb_1 optlc_624 ( .LO ( optlc_net_623 ) , .HI ( SYNOPSYS_UNCONNECTED_625 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_627 ( .LO ( optlc_net_624 ) , +sky130_fd_sc_hd__conb_1 optlc_625 ( .LO ( optlc_net_624 ) , .HI ( SYNOPSYS_UNCONNECTED_626 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_628 ( .LO ( optlc_net_625 ) , +sky130_fd_sc_hd__conb_1 optlc_626 ( .LO ( optlc_net_625 ) , .HI ( SYNOPSYS_UNCONNECTED_627 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_629 ( .LO ( optlc_net_626 ) , +sky130_fd_sc_hd__conb_1 optlc_627 ( .LO ( optlc_net_626 ) , .HI ( SYNOPSYS_UNCONNECTED_628 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_630 ( .LO ( optlc_net_627 ) , +sky130_fd_sc_hd__conb_1 optlc_628 ( .LO ( optlc_net_627 ) , .HI ( SYNOPSYS_UNCONNECTED_629 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_631 ( .LO ( optlc_net_628 ) , +sky130_fd_sc_hd__conb_1 optlc_629 ( .LO ( optlc_net_628 ) , .HI ( SYNOPSYS_UNCONNECTED_630 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_632 ( .LO ( optlc_net_629 ) , +sky130_fd_sc_hd__conb_1 optlc_630 ( .LO ( optlc_net_629 ) , .HI ( SYNOPSYS_UNCONNECTED_631 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_633 ( .LO ( optlc_net_630 ) , +sky130_fd_sc_hd__conb_1 optlc_631 ( .LO ( optlc_net_630 ) , .HI ( SYNOPSYS_UNCONNECTED_632 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_634 ( .LO ( optlc_net_631 ) , +sky130_fd_sc_hd__conb_1 optlc_632 ( .LO ( optlc_net_631 ) , .HI ( SYNOPSYS_UNCONNECTED_633 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_635 ( .LO ( optlc_net_632 ) , +sky130_fd_sc_hd__conb_1 optlc_633 ( .LO ( optlc_net_632 ) , .HI ( SYNOPSYS_UNCONNECTED_634 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_636 ( .LO ( optlc_net_633 ) , +sky130_fd_sc_hd__conb_1 optlc_634 ( .LO ( optlc_net_633 ) , .HI ( SYNOPSYS_UNCONNECTED_635 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_637 ( .LO ( optlc_net_634 ) , +sky130_fd_sc_hd__conb_1 optlc_635 ( .LO ( optlc_net_634 ) , .HI ( SYNOPSYS_UNCONNECTED_636 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_638 ( .LO ( optlc_net_635 ) , +sky130_fd_sc_hd__conb_1 optlc_636 ( .LO ( optlc_net_635 ) , .HI ( SYNOPSYS_UNCONNECTED_637 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_639 ( .LO ( optlc_net_636 ) , +sky130_fd_sc_hd__conb_1 optlc_637 ( .LO ( optlc_net_636 ) , .HI ( SYNOPSYS_UNCONNECTED_638 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_640 ( .LO ( optlc_net_637 ) , +sky130_fd_sc_hd__conb_1 optlc_638 ( .LO ( optlc_net_637 ) , .HI ( SYNOPSYS_UNCONNECTED_639 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_641 ( .LO ( optlc_net_638 ) , +sky130_fd_sc_hd__conb_1 optlc_639 ( .LO ( optlc_net_638 ) , .HI ( SYNOPSYS_UNCONNECTED_640 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_642 ( .LO ( optlc_net_639 ) , +sky130_fd_sc_hd__conb_1 optlc_640 ( .LO ( optlc_net_639 ) , .HI ( SYNOPSYS_UNCONNECTED_641 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_643 ( .LO ( optlc_net_640 ) , +sky130_fd_sc_hd__conb_1 optlc_641 ( .LO ( optlc_net_640 ) , .HI ( SYNOPSYS_UNCONNECTED_642 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_644 ( .LO ( optlc_net_641 ) , +sky130_fd_sc_hd__conb_1 optlc_642 ( .LO ( optlc_net_641 ) , .HI ( SYNOPSYS_UNCONNECTED_643 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_645 ( .LO ( optlc_net_642 ) , +sky130_fd_sc_hd__conb_1 optlc_643 ( .LO ( optlc_net_642 ) , .HI ( SYNOPSYS_UNCONNECTED_644 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_646 ( .LO ( optlc_net_643 ) , +sky130_fd_sc_hd__conb_1 optlc_644 ( .LO ( optlc_net_643 ) , .HI ( SYNOPSYS_UNCONNECTED_645 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_647 ( .LO ( optlc_net_644 ) , +sky130_fd_sc_hd__conb_1 optlc_645 ( .LO ( optlc_net_644 ) , .HI ( SYNOPSYS_UNCONNECTED_646 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_648 ( .LO ( optlc_net_645 ) , +sky130_fd_sc_hd__conb_1 optlc_646 ( .LO ( optlc_net_645 ) , .HI ( SYNOPSYS_UNCONNECTED_647 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_649 ( .LO ( optlc_net_646 ) , +sky130_fd_sc_hd__conb_1 optlc_647 ( .LO ( optlc_net_646 ) , .HI ( SYNOPSYS_UNCONNECTED_648 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_650 ( .LO ( optlc_net_647 ) , +sky130_fd_sc_hd__conb_1 optlc_648 ( .LO ( optlc_net_647 ) , .HI ( SYNOPSYS_UNCONNECTED_649 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_651 ( .LO ( optlc_net_648 ) , +sky130_fd_sc_hd__conb_1 optlc_649 ( .LO ( optlc_net_648 ) , .HI ( SYNOPSYS_UNCONNECTED_650 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_652 ( .LO ( optlc_net_649 ) , +sky130_fd_sc_hd__conb_1 optlc_650 ( .LO ( optlc_net_649 ) , .HI ( SYNOPSYS_UNCONNECTED_651 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_653 ( .LO ( optlc_net_650 ) , +sky130_fd_sc_hd__conb_1 optlc_651 ( .LO ( optlc_net_650 ) , .HI ( SYNOPSYS_UNCONNECTED_652 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_654 ( .LO ( optlc_net_651 ) , +sky130_fd_sc_hd__conb_1 optlc_652 ( .LO ( optlc_net_651 ) , .HI ( SYNOPSYS_UNCONNECTED_653 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_655 ( .LO ( optlc_net_652 ) , +sky130_fd_sc_hd__conb_1 optlc_653 ( .LO ( optlc_net_652 ) , .HI ( SYNOPSYS_UNCONNECTED_654 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_656 ( .LO ( optlc_net_653 ) , +sky130_fd_sc_hd__conb_1 optlc_654 ( .LO ( optlc_net_653 ) , .HI ( SYNOPSYS_UNCONNECTED_655 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_657 ( .LO ( optlc_net_654 ) , +sky130_fd_sc_hd__conb_1 optlc_655 ( .LO ( optlc_net_654 ) , .HI ( SYNOPSYS_UNCONNECTED_656 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_658 ( .LO ( optlc_net_655 ) , +sky130_fd_sc_hd__conb_1 optlc_656 ( .LO ( optlc_net_655 ) , .HI ( SYNOPSYS_UNCONNECTED_657 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_659 ( .LO ( optlc_net_656 ) , +sky130_fd_sc_hd__conb_1 optlc_657 ( .LO ( optlc_net_656 ) , .HI ( SYNOPSYS_UNCONNECTED_658 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_660 ( .LO ( optlc_net_657 ) , +sky130_fd_sc_hd__conb_1 optlc_658 ( .LO ( optlc_net_657 ) , .HI ( SYNOPSYS_UNCONNECTED_659 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_661 ( .LO ( optlc_net_658 ) , +sky130_fd_sc_hd__conb_1 optlc_659 ( .LO ( optlc_net_658 ) , .HI ( SYNOPSYS_UNCONNECTED_660 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_662 ( .LO ( optlc_net_659 ) , +sky130_fd_sc_hd__conb_1 optlc_660 ( .LO ( optlc_net_659 ) , .HI ( SYNOPSYS_UNCONNECTED_661 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_663 ( .LO ( optlc_net_660 ) , +sky130_fd_sc_hd__conb_1 optlc_661 ( .LO ( optlc_net_660 ) , .HI ( SYNOPSYS_UNCONNECTED_662 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_664 ( .LO ( optlc_net_661 ) , +sky130_fd_sc_hd__conb_1 optlc_662 ( .LO ( optlc_net_661 ) , .HI ( SYNOPSYS_UNCONNECTED_663 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_665 ( .LO ( optlc_net_662 ) , +sky130_fd_sc_hd__conb_1 optlc_663 ( .LO ( optlc_net_662 ) , .HI ( SYNOPSYS_UNCONNECTED_664 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_666 ( .LO ( optlc_net_663 ) , +sky130_fd_sc_hd__conb_1 optlc_664 ( .LO ( optlc_net_663 ) , .HI ( SYNOPSYS_UNCONNECTED_665 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_667 ( .LO ( optlc_net_664 ) , +sky130_fd_sc_hd__conb_1 optlc_665 ( .LO ( optlc_net_664 ) , .HI ( SYNOPSYS_UNCONNECTED_666 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_668 ( .LO ( optlc_net_665 ) , +sky130_fd_sc_hd__conb_1 optlc_666 ( .LO ( optlc_net_665 ) , .HI ( SYNOPSYS_UNCONNECTED_667 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_669 ( .LO ( optlc_net_666 ) , +sky130_fd_sc_hd__conb_1 optlc_667 ( .LO ( optlc_net_666 ) , .HI ( SYNOPSYS_UNCONNECTED_668 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_670 ( .LO ( optlc_net_667 ) , +sky130_fd_sc_hd__conb_1 optlc_668 ( .LO ( optlc_net_667 ) , .HI ( SYNOPSYS_UNCONNECTED_669 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_671 ( .LO ( optlc_net_668 ) , +sky130_fd_sc_hd__conb_1 optlc_669 ( .LO ( optlc_net_668 ) , .HI ( SYNOPSYS_UNCONNECTED_670 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_672 ( .LO ( optlc_net_669 ) , +sky130_fd_sc_hd__conb_1 optlc_670 ( .LO ( optlc_net_669 ) , .HI ( SYNOPSYS_UNCONNECTED_671 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_673 ( .LO ( optlc_net_670 ) , +sky130_fd_sc_hd__conb_1 optlc_671 ( .LO ( optlc_net_670 ) , .HI ( SYNOPSYS_UNCONNECTED_672 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_674 ( .LO ( optlc_net_671 ) , +sky130_fd_sc_hd__conb_1 optlc_672 ( .LO ( optlc_net_671 ) , .HI ( SYNOPSYS_UNCONNECTED_673 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_675 ( .LO ( optlc_net_672 ) , +sky130_fd_sc_hd__conb_1 optlc_673 ( .LO ( optlc_net_672 ) , .HI ( SYNOPSYS_UNCONNECTED_674 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_676 ( .LO ( optlc_net_673 ) , +sky130_fd_sc_hd__conb_1 optlc_674 ( .LO ( optlc_net_673 ) , .HI ( SYNOPSYS_UNCONNECTED_675 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_677 ( .LO ( optlc_net_674 ) , +sky130_fd_sc_hd__conb_1 optlc_675 ( .LO ( optlc_net_674 ) , .HI ( SYNOPSYS_UNCONNECTED_676 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_678 ( .LO ( optlc_net_675 ) , +sky130_fd_sc_hd__conb_1 optlc_676 ( .LO ( optlc_net_675 ) , .HI ( SYNOPSYS_UNCONNECTED_677 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_679 ( .LO ( optlc_net_676 ) , +sky130_fd_sc_hd__conb_1 optlc_677 ( .LO ( optlc_net_676 ) , .HI ( SYNOPSYS_UNCONNECTED_678 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_680 ( .LO ( optlc_net_677 ) , +sky130_fd_sc_hd__conb_1 optlc_678 ( .LO ( optlc_net_677 ) , .HI ( SYNOPSYS_UNCONNECTED_679 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_681 ( .LO ( optlc_net_678 ) , +sky130_fd_sc_hd__conb_1 optlc_679 ( .LO ( optlc_net_678 ) , .HI ( SYNOPSYS_UNCONNECTED_680 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_682 ( .LO ( optlc_net_679 ) , +sky130_fd_sc_hd__conb_1 optlc_680 ( .LO ( optlc_net_679 ) , .HI ( SYNOPSYS_UNCONNECTED_681 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_683 ( .LO ( optlc_net_680 ) , +sky130_fd_sc_hd__conb_1 optlc_681 ( .LO ( optlc_net_680 ) , .HI ( SYNOPSYS_UNCONNECTED_682 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_684 ( .LO ( optlc_net_681 ) , +sky130_fd_sc_hd__conb_1 optlc_682 ( .LO ( optlc_net_681 ) , .HI ( SYNOPSYS_UNCONNECTED_683 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_685 ( .LO ( optlc_net_682 ) , +sky130_fd_sc_hd__conb_1 optlc_683 ( .LO ( optlc_net_682 ) , .HI ( SYNOPSYS_UNCONNECTED_684 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_686 ( .LO ( optlc_net_683 ) , +sky130_fd_sc_hd__conb_1 optlc_684 ( .LO ( optlc_net_683 ) , .HI ( SYNOPSYS_UNCONNECTED_685 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_687 ( .LO ( optlc_net_684 ) , +sky130_fd_sc_hd__conb_1 optlc_685 ( .LO ( optlc_net_684 ) , .HI ( SYNOPSYS_UNCONNECTED_686 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_688 ( .LO ( optlc_net_685 ) , +sky130_fd_sc_hd__conb_1 optlc_686 ( .LO ( optlc_net_685 ) , .HI ( SYNOPSYS_UNCONNECTED_687 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_689 ( .LO ( optlc_net_686 ) , +sky130_fd_sc_hd__conb_1 optlc_687 ( .LO ( optlc_net_686 ) , .HI ( SYNOPSYS_UNCONNECTED_688 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_690 ( .LO ( optlc_net_687 ) , +sky130_fd_sc_hd__conb_1 optlc_688 ( .LO ( optlc_net_687 ) , .HI ( SYNOPSYS_UNCONNECTED_689 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_691 ( .LO ( optlc_net_688 ) , +sky130_fd_sc_hd__conb_1 optlc_689 ( .LO ( optlc_net_688 ) , .HI ( SYNOPSYS_UNCONNECTED_690 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_692 ( .LO ( optlc_net_689 ) , +sky130_fd_sc_hd__conb_1 optlc_690 ( .LO ( optlc_net_689 ) , .HI ( SYNOPSYS_UNCONNECTED_691 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_693 ( .LO ( optlc_net_690 ) , +sky130_fd_sc_hd__conb_1 optlc_691 ( .LO ( optlc_net_690 ) , .HI ( SYNOPSYS_UNCONNECTED_692 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_694 ( .LO ( optlc_net_691 ) , +sky130_fd_sc_hd__conb_1 optlc_692 ( .LO ( optlc_net_691 ) , .HI ( SYNOPSYS_UNCONNECTED_693 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_695 ( .LO ( optlc_net_692 ) , +sky130_fd_sc_hd__conb_1 optlc_693 ( .LO ( optlc_net_692 ) , .HI ( SYNOPSYS_UNCONNECTED_694 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_696 ( .LO ( optlc_net_693 ) , +sky130_fd_sc_hd__conb_1 optlc_694 ( .LO ( optlc_net_693 ) , .HI ( SYNOPSYS_UNCONNECTED_695 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_697 ( .LO ( optlc_net_694 ) , +sky130_fd_sc_hd__conb_1 optlc_695 ( .LO ( optlc_net_694 ) , .HI ( SYNOPSYS_UNCONNECTED_696 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_698 ( .LO ( optlc_net_695 ) , +sky130_fd_sc_hd__conb_1 optlc_696 ( .LO ( optlc_net_695 ) , .HI ( SYNOPSYS_UNCONNECTED_697 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_699 ( .LO ( optlc_net_696 ) , +sky130_fd_sc_hd__conb_1 optlc_697 ( .LO ( optlc_net_696 ) , .HI ( SYNOPSYS_UNCONNECTED_698 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_700 ( .LO ( optlc_net_697 ) , +sky130_fd_sc_hd__conb_1 optlc_698 ( .LO ( optlc_net_697 ) , .HI ( SYNOPSYS_UNCONNECTED_699 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_701 ( .LO ( optlc_net_698 ) , +sky130_fd_sc_hd__conb_1 optlc_699 ( .LO ( optlc_net_698 ) , .HI ( SYNOPSYS_UNCONNECTED_700 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_702 ( .LO ( optlc_net_699 ) , +sky130_fd_sc_hd__conb_1 optlc_700 ( .LO ( optlc_net_699 ) , .HI ( SYNOPSYS_UNCONNECTED_701 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_703 ( .LO ( optlc_net_700 ) , +sky130_fd_sc_hd__conb_1 optlc_701 ( .LO ( optlc_net_700 ) , .HI ( SYNOPSYS_UNCONNECTED_702 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_704 ( .LO ( optlc_net_701 ) , +sky130_fd_sc_hd__conb_1 optlc_702 ( .LO ( optlc_net_701 ) , .HI ( SYNOPSYS_UNCONNECTED_703 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_705 ( .LO ( optlc_net_702 ) , +sky130_fd_sc_hd__conb_1 optlc_703 ( .LO ( optlc_net_702 ) , .HI ( SYNOPSYS_UNCONNECTED_704 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_706 ( .LO ( optlc_net_703 ) , +sky130_fd_sc_hd__conb_1 optlc_704 ( .LO ( optlc_net_703 ) , .HI ( SYNOPSYS_UNCONNECTED_705 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_708 ( .LO ( optlc_net_704 ) , +sky130_fd_sc_hd__conb_1 optlc_705 ( .LO ( optlc_net_704 ) , .HI ( SYNOPSYS_UNCONNECTED_706 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_709 ( .LO ( optlc_net_705 ) , +sky130_fd_sc_hd__conb_1 optlc_706 ( .LO ( optlc_net_705 ) , .HI ( SYNOPSYS_UNCONNECTED_707 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_710 ( .LO ( optlc_net_706 ) , +sky130_fd_sc_hd__conb_1 optlc_707 ( .LO ( optlc_net_706 ) , .HI ( SYNOPSYS_UNCONNECTED_708 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_711 ( .LO ( optlc_net_707 ) , +sky130_fd_sc_hd__conb_1 optlc_708 ( .LO ( optlc_net_707 ) , .HI ( SYNOPSYS_UNCONNECTED_709 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_712 ( .LO ( optlc_net_708 ) , +sky130_fd_sc_hd__conb_1 optlc_709 ( .LO ( optlc_net_708 ) , .HI ( SYNOPSYS_UNCONNECTED_710 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_713 ( .LO ( optlc_net_709 ) , +sky130_fd_sc_hd__conb_1 optlc_710 ( .LO ( optlc_net_709 ) , .HI ( SYNOPSYS_UNCONNECTED_711 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_714 ( .LO ( optlc_net_710 ) , +sky130_fd_sc_hd__conb_1 optlc_711 ( .LO ( optlc_net_710 ) , .HI ( SYNOPSYS_UNCONNECTED_712 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_715 ( .LO ( optlc_net_711 ) , +sky130_fd_sc_hd__conb_1 optlc_712 ( .LO ( optlc_net_711 ) , .HI ( SYNOPSYS_UNCONNECTED_713 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_716 ( .LO ( optlc_net_712 ) , +sky130_fd_sc_hd__conb_1 optlc_713 ( .LO ( optlc_net_712 ) , .HI ( SYNOPSYS_UNCONNECTED_714 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_717 ( .LO ( optlc_net_713 ) , +sky130_fd_sc_hd__conb_1 optlc_714 ( .LO ( optlc_net_713 ) , .HI ( SYNOPSYS_UNCONNECTED_715 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_718 ( .LO ( optlc_net_714 ) , +sky130_fd_sc_hd__conb_1 optlc_715 ( .LO ( optlc_net_714 ) , .HI ( SYNOPSYS_UNCONNECTED_716 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_719 ( .LO ( optlc_net_715 ) , +sky130_fd_sc_hd__conb_1 optlc_716 ( .LO ( optlc_net_715 ) , .HI ( SYNOPSYS_UNCONNECTED_717 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_720 ( .LO ( optlc_net_716 ) , +sky130_fd_sc_hd__conb_1 optlc_717 ( .LO ( optlc_net_716 ) , .HI ( SYNOPSYS_UNCONNECTED_718 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_721 ( .LO ( optlc_net_717 ) , +sky130_fd_sc_hd__conb_1 optlc_718 ( .LO ( optlc_net_717 ) , .HI ( SYNOPSYS_UNCONNECTED_719 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_722 ( .LO ( optlc_net_718 ) , +sky130_fd_sc_hd__conb_1 optlc_719 ( .LO ( optlc_net_718 ) , .HI ( SYNOPSYS_UNCONNECTED_720 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_723 ( .LO ( optlc_net_719 ) , +sky130_fd_sc_hd__conb_1 optlc_720 ( .LO ( optlc_net_719 ) , .HI ( SYNOPSYS_UNCONNECTED_721 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_724 ( .LO ( optlc_net_720 ) , +sky130_fd_sc_hd__conb_1 optlc_721 ( .LO ( optlc_net_720 ) , .HI ( SYNOPSYS_UNCONNECTED_722 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_725 ( .LO ( optlc_net_721 ) , +sky130_fd_sc_hd__conb_1 optlc_722 ( .LO ( optlc_net_721 ) , .HI ( SYNOPSYS_UNCONNECTED_723 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_726 ( .LO ( optlc_net_722 ) , +sky130_fd_sc_hd__conb_1 optlc_723 ( .LO ( optlc_net_722 ) , .HI ( SYNOPSYS_UNCONNECTED_724 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_727 ( .LO ( optlc_net_723 ) , +sky130_fd_sc_hd__conb_1 optlc_724 ( .LO ( optlc_net_723 ) , .HI ( SYNOPSYS_UNCONNECTED_725 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_728 ( .LO ( optlc_net_724 ) , +sky130_fd_sc_hd__conb_1 optlc_725 ( .LO ( optlc_net_724 ) , .HI ( SYNOPSYS_UNCONNECTED_726 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_729 ( .LO ( optlc_net_725 ) , +sky130_fd_sc_hd__conb_1 optlc_726 ( .LO ( optlc_net_725 ) , .HI ( SYNOPSYS_UNCONNECTED_727 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_730 ( .LO ( optlc_net_726 ) , +sky130_fd_sc_hd__conb_1 optlc_727 ( .LO ( optlc_net_726 ) , .HI ( SYNOPSYS_UNCONNECTED_728 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_731 ( .LO ( optlc_net_727 ) , +sky130_fd_sc_hd__conb_1 optlc_728 ( .LO ( optlc_net_727 ) , .HI ( SYNOPSYS_UNCONNECTED_729 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_732 ( .LO ( optlc_net_728 ) , +sky130_fd_sc_hd__conb_1 optlc_729 ( .LO ( optlc_net_728 ) , .HI ( SYNOPSYS_UNCONNECTED_730 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_733 ( .LO ( optlc_net_729 ) , +sky130_fd_sc_hd__conb_1 optlc_730 ( .LO ( optlc_net_729 ) , .HI ( SYNOPSYS_UNCONNECTED_731 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_734 ( .LO ( optlc_net_730 ) , +sky130_fd_sc_hd__conb_1 optlc_731 ( .LO ( optlc_net_730 ) , .HI ( SYNOPSYS_UNCONNECTED_732 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_735 ( .LO ( optlc_net_731 ) , +sky130_fd_sc_hd__conb_1 optlc_732 ( .LO ( optlc_net_731 ) , .HI ( SYNOPSYS_UNCONNECTED_733 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_736 ( .LO ( optlc_net_732 ) , +sky130_fd_sc_hd__conb_1 optlc_733 ( .LO ( optlc_net_732 ) , .HI ( SYNOPSYS_UNCONNECTED_734 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_737 ( .LO ( optlc_net_733 ) , +sky130_fd_sc_hd__conb_1 optlc_734 ( .LO ( optlc_net_733 ) , .HI ( SYNOPSYS_UNCONNECTED_735 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_738 ( .LO ( optlc_net_734 ) , +sky130_fd_sc_hd__conb_1 optlc_735 ( .LO ( optlc_net_734 ) , .HI ( SYNOPSYS_UNCONNECTED_736 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_739 ( .LO ( optlc_net_735 ) , +sky130_fd_sc_hd__conb_1 optlc_736 ( .LO ( optlc_net_735 ) , .HI ( SYNOPSYS_UNCONNECTED_737 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_740 ( .LO ( optlc_net_736 ) , +sky130_fd_sc_hd__conb_1 optlc_737 ( .LO ( optlc_net_736 ) , .HI ( SYNOPSYS_UNCONNECTED_738 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_741 ( .LO ( optlc_net_737 ) , +sky130_fd_sc_hd__conb_1 optlc_738 ( .LO ( optlc_net_737 ) , .HI ( SYNOPSYS_UNCONNECTED_739 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_742 ( .LO ( optlc_net_738 ) , +sky130_fd_sc_hd__conb_1 optlc_739 ( .LO ( optlc_net_738 ) , .HI ( SYNOPSYS_UNCONNECTED_740 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_743 ( .LO ( optlc_net_739 ) , +sky130_fd_sc_hd__conb_1 optlc_740 ( .LO ( optlc_net_739 ) , .HI ( SYNOPSYS_UNCONNECTED_741 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_744 ( .LO ( optlc_net_740 ) , +sky130_fd_sc_hd__conb_1 optlc_741 ( .LO ( optlc_net_740 ) , .HI ( SYNOPSYS_UNCONNECTED_742 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_745 ( .LO ( optlc_net_741 ) , +sky130_fd_sc_hd__conb_1 optlc_742 ( .LO ( optlc_net_741 ) , .HI ( SYNOPSYS_UNCONNECTED_743 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_746 ( .LO ( optlc_net_742 ) , +sky130_fd_sc_hd__conb_1 optlc_743 ( .LO ( optlc_net_742 ) , .HI ( SYNOPSYS_UNCONNECTED_744 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_747 ( .LO ( optlc_net_743 ) , +sky130_fd_sc_hd__conb_1 optlc_744 ( .LO ( optlc_net_743 ) , .HI ( SYNOPSYS_UNCONNECTED_745 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_748 ( .LO ( optlc_net_744 ) , +sky130_fd_sc_hd__conb_1 optlc_745 ( .LO ( optlc_net_744 ) , .HI ( SYNOPSYS_UNCONNECTED_746 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_749 ( .LO ( optlc_net_745 ) , +sky130_fd_sc_hd__conb_1 optlc_746 ( .LO ( optlc_net_745 ) , .HI ( SYNOPSYS_UNCONNECTED_747 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_750 ( .LO ( optlc_net_746 ) , +sky130_fd_sc_hd__conb_1 optlc_747 ( .LO ( optlc_net_746 ) , .HI ( SYNOPSYS_UNCONNECTED_748 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_751 ( .LO ( optlc_net_747 ) , +sky130_fd_sc_hd__conb_1 optlc_748 ( .LO ( optlc_net_747 ) , .HI ( SYNOPSYS_UNCONNECTED_749 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_752 ( .LO ( optlc_net_748 ) , +sky130_fd_sc_hd__conb_1 optlc_749 ( .LO ( optlc_net_748 ) , .HI ( SYNOPSYS_UNCONNECTED_750 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_753 ( .LO ( optlc_net_749 ) , +sky130_fd_sc_hd__conb_1 optlc_750 ( .LO ( optlc_net_749 ) , .HI ( SYNOPSYS_UNCONNECTED_751 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_754 ( .LO ( optlc_net_750 ) , +sky130_fd_sc_hd__conb_1 optlc_751 ( .LO ( optlc_net_750 ) , .HI ( SYNOPSYS_UNCONNECTED_752 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_755 ( .LO ( optlc_net_751 ) , +sky130_fd_sc_hd__conb_1 optlc_752 ( .LO ( optlc_net_751 ) , .HI ( SYNOPSYS_UNCONNECTED_753 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_756 ( .LO ( optlc_net_752 ) , +sky130_fd_sc_hd__conb_1 optlc_753 ( .LO ( optlc_net_752 ) , .HI ( SYNOPSYS_UNCONNECTED_754 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_757 ( .LO ( optlc_net_753 ) , +sky130_fd_sc_hd__conb_1 optlc_754 ( .LO ( optlc_net_753 ) , .HI ( SYNOPSYS_UNCONNECTED_755 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_758 ( .LO ( optlc_net_754 ) , +sky130_fd_sc_hd__conb_1 optlc_755 ( .LO ( optlc_net_754 ) , .HI ( SYNOPSYS_UNCONNECTED_756 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_759 ( .LO ( optlc_net_755 ) , +sky130_fd_sc_hd__conb_1 optlc_756 ( .LO ( optlc_net_755 ) , .HI ( SYNOPSYS_UNCONNECTED_757 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_760 ( .LO ( optlc_net_756 ) , +sky130_fd_sc_hd__conb_1 optlc_757 ( .LO ( optlc_net_756 ) , .HI ( SYNOPSYS_UNCONNECTED_758 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_761 ( .LO ( optlc_net_757 ) , +sky130_fd_sc_hd__conb_1 optlc_758 ( .LO ( optlc_net_757 ) , .HI ( SYNOPSYS_UNCONNECTED_759 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_762 ( .LO ( optlc_net_758 ) , +sky130_fd_sc_hd__conb_1 optlc_759 ( .LO ( optlc_net_758 ) , .HI ( SYNOPSYS_UNCONNECTED_760 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_763 ( .LO ( optlc_net_759 ) , +sky130_fd_sc_hd__conb_1 optlc_760 ( .LO ( optlc_net_759 ) , .HI ( SYNOPSYS_UNCONNECTED_761 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_764 ( .LO ( optlc_net_760 ) , +sky130_fd_sc_hd__conb_1 optlc_761 ( .LO ( optlc_net_760 ) , .HI ( SYNOPSYS_UNCONNECTED_762 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_765 ( .LO ( optlc_net_761 ) , +sky130_fd_sc_hd__conb_1 optlc_762 ( .LO ( optlc_net_761 ) , .HI ( SYNOPSYS_UNCONNECTED_763 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_766 ( .LO ( optlc_net_762 ) , +sky130_fd_sc_hd__conb_1 optlc_763 ( .LO ( optlc_net_762 ) , .HI ( SYNOPSYS_UNCONNECTED_764 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_767 ( .LO ( optlc_net_763 ) , +sky130_fd_sc_hd__conb_1 optlc_764 ( .LO ( optlc_net_763 ) , .HI ( SYNOPSYS_UNCONNECTED_765 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_768 ( .LO ( optlc_net_764 ) , +sky130_fd_sc_hd__conb_1 optlc_765 ( .LO ( optlc_net_764 ) , .HI ( SYNOPSYS_UNCONNECTED_766 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_769 ( .LO ( optlc_net_765 ) , +sky130_fd_sc_hd__conb_1 optlc_766 ( .LO ( optlc_net_765 ) , .HI ( SYNOPSYS_UNCONNECTED_767 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_770 ( .LO ( optlc_net_766 ) , +sky130_fd_sc_hd__conb_1 optlc_767 ( .LO ( optlc_net_766 ) , .HI ( SYNOPSYS_UNCONNECTED_768 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_771 ( .LO ( optlc_net_767 ) , +sky130_fd_sc_hd__conb_1 optlc_768 ( .LO ( optlc_net_767 ) , .HI ( SYNOPSYS_UNCONNECTED_769 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_772 ( .LO ( optlc_net_768 ) , +sky130_fd_sc_hd__conb_1 optlc_769 ( .LO ( optlc_net_768 ) , .HI ( SYNOPSYS_UNCONNECTED_770 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_773 ( .LO ( optlc_net_769 ) , +sky130_fd_sc_hd__conb_1 optlc_770 ( .LO ( optlc_net_769 ) , .HI ( SYNOPSYS_UNCONNECTED_771 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_774 ( .LO ( optlc_net_770 ) , +sky130_fd_sc_hd__conb_1 optlc_771 ( .LO ( optlc_net_770 ) , .HI ( SYNOPSYS_UNCONNECTED_772 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_775 ( .LO ( optlc_net_771 ) , +sky130_fd_sc_hd__conb_1 optlc_772 ( .LO ( optlc_net_771 ) , .HI ( SYNOPSYS_UNCONNECTED_773 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_776 ( .LO ( optlc_net_772 ) , +sky130_fd_sc_hd__conb_1 optlc_773 ( .LO ( optlc_net_772 ) , .HI ( SYNOPSYS_UNCONNECTED_774 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_778 ( .LO ( optlc_net_773 ) , +sky130_fd_sc_hd__conb_1 optlc_774 ( .LO ( optlc_net_773 ) , .HI ( SYNOPSYS_UNCONNECTED_775 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_779 ( .LO ( optlc_net_774 ) , +sky130_fd_sc_hd__conb_1 optlc_775 ( .LO ( optlc_net_774 ) , .HI ( SYNOPSYS_UNCONNECTED_776 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_780 ( .LO ( optlc_net_775 ) , +sky130_fd_sc_hd__conb_1 optlc_776 ( .LO ( optlc_net_775 ) , .HI ( SYNOPSYS_UNCONNECTED_777 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_781 ( .LO ( optlc_net_776 ) , +sky130_fd_sc_hd__conb_1 optlc_777 ( .LO ( optlc_net_776 ) , .HI ( SYNOPSYS_UNCONNECTED_778 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_782 ( .LO ( optlc_net_777 ) , +sky130_fd_sc_hd__conb_1 optlc_778 ( .LO ( optlc_net_777 ) , .HI ( SYNOPSYS_UNCONNECTED_779 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_783 ( .LO ( optlc_net_778 ) , +sky130_fd_sc_hd__conb_1 optlc_779 ( .LO ( optlc_net_778 ) , .HI ( SYNOPSYS_UNCONNECTED_780 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_784 ( .LO ( optlc_net_779 ) , +sky130_fd_sc_hd__conb_1 optlc_780 ( .LO ( optlc_net_779 ) , .HI ( SYNOPSYS_UNCONNECTED_781 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_785 ( .LO ( optlc_net_780 ) , +sky130_fd_sc_hd__conb_1 optlc_781 ( .LO ( optlc_net_780 ) , .HI ( SYNOPSYS_UNCONNECTED_782 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_786 ( .LO ( optlc_net_781 ) , +sky130_fd_sc_hd__conb_1 optlc_782 ( .LO ( optlc_net_781 ) , .HI ( SYNOPSYS_UNCONNECTED_783 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_787 ( .LO ( optlc_net_782 ) , +sky130_fd_sc_hd__conb_1 optlc_783 ( .LO ( optlc_net_782 ) , .HI ( SYNOPSYS_UNCONNECTED_784 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_788 ( .LO ( optlc_net_783 ) , +sky130_fd_sc_hd__conb_1 optlc_784 ( .LO ( optlc_net_783 ) , .HI ( SYNOPSYS_UNCONNECTED_785 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_789 ( .LO ( optlc_net_784 ) , +sky130_fd_sc_hd__conb_1 optlc_785 ( .LO ( optlc_net_784 ) , .HI ( SYNOPSYS_UNCONNECTED_786 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_790 ( .LO ( optlc_net_785 ) , +sky130_fd_sc_hd__conb_1 optlc_786 ( .LO ( optlc_net_785 ) , .HI ( SYNOPSYS_UNCONNECTED_787 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_791 ( .LO ( optlc_net_786 ) , +sky130_fd_sc_hd__conb_1 optlc_787 ( .LO ( optlc_net_786 ) , .HI ( SYNOPSYS_UNCONNECTED_788 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_792 ( .LO ( optlc_net_787 ) , +sky130_fd_sc_hd__conb_1 optlc_788 ( .LO ( optlc_net_787 ) , .HI ( SYNOPSYS_UNCONNECTED_789 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_793 ( .LO ( optlc_net_788 ) , +sky130_fd_sc_hd__conb_1 optlc_789 ( .LO ( optlc_net_788 ) , .HI ( SYNOPSYS_UNCONNECTED_790 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_794 ( .LO ( optlc_net_789 ) , +sky130_fd_sc_hd__conb_1 optlc_790 ( .LO ( optlc_net_789 ) , .HI ( SYNOPSYS_UNCONNECTED_791 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_795 ( .LO ( optlc_net_790 ) , +sky130_fd_sc_hd__conb_1 optlc_791 ( .LO ( optlc_net_790 ) , .HI ( SYNOPSYS_UNCONNECTED_792 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_796 ( .LO ( optlc_net_791 ) , +sky130_fd_sc_hd__conb_1 optlc_792 ( .LO ( optlc_net_791 ) , .HI ( SYNOPSYS_UNCONNECTED_793 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_797 ( .LO ( optlc_net_792 ) , +sky130_fd_sc_hd__conb_1 optlc_793 ( .LO ( optlc_net_792 ) , .HI ( SYNOPSYS_UNCONNECTED_794 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_798 ( .LO ( optlc_net_793 ) , +sky130_fd_sc_hd__conb_1 optlc_794 ( .LO ( optlc_net_793 ) , .HI ( SYNOPSYS_UNCONNECTED_795 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_799 ( .LO ( optlc_net_794 ) , +sky130_fd_sc_hd__conb_1 optlc_795 ( .LO ( optlc_net_794 ) , .HI ( SYNOPSYS_UNCONNECTED_796 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_800 ( .LO ( optlc_net_795 ) , +sky130_fd_sc_hd__conb_1 optlc_796 ( .LO ( optlc_net_795 ) , .HI ( SYNOPSYS_UNCONNECTED_797 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_801 ( .LO ( optlc_net_796 ) , +sky130_fd_sc_hd__conb_1 optlc_797 ( .LO ( optlc_net_796 ) , .HI ( SYNOPSYS_UNCONNECTED_798 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_802 ( .LO ( optlc_net_797 ) , +sky130_fd_sc_hd__conb_1 optlc_798 ( .LO ( optlc_net_797 ) , .HI ( SYNOPSYS_UNCONNECTED_799 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_803 ( .LO ( optlc_net_798 ) , +sky130_fd_sc_hd__conb_1 optlc_799 ( .LO ( optlc_net_798 ) , .HI ( SYNOPSYS_UNCONNECTED_800 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_804 ( .LO ( optlc_net_799 ) , +sky130_fd_sc_hd__conb_1 optlc_800 ( .LO ( optlc_net_799 ) , .HI ( SYNOPSYS_UNCONNECTED_801 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_805 ( .LO ( optlc_net_800 ) , +sky130_fd_sc_hd__conb_1 optlc_801 ( .LO ( optlc_net_800 ) , .HI ( SYNOPSYS_UNCONNECTED_802 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_806 ( .LO ( optlc_net_801 ) , +sky130_fd_sc_hd__conb_1 optlc_802 ( .LO ( optlc_net_801 ) , .HI ( SYNOPSYS_UNCONNECTED_803 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_807 ( .LO ( optlc_net_802 ) , +sky130_fd_sc_hd__conb_1 optlc_803 ( .LO ( optlc_net_802 ) , .HI ( SYNOPSYS_UNCONNECTED_804 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_808 ( .LO ( optlc_net_803 ) , +sky130_fd_sc_hd__conb_1 optlc_804 ( .LO ( optlc_net_803 ) , .HI ( SYNOPSYS_UNCONNECTED_805 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_809 ( .LO ( optlc_net_804 ) , +sky130_fd_sc_hd__conb_1 optlc_805 ( .LO ( optlc_net_804 ) , .HI ( SYNOPSYS_UNCONNECTED_806 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_810 ( .LO ( optlc_net_805 ) , +sky130_fd_sc_hd__conb_1 optlc_806 ( .LO ( optlc_net_805 ) , .HI ( SYNOPSYS_UNCONNECTED_807 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_811 ( .LO ( optlc_net_806 ) , +sky130_fd_sc_hd__conb_1 optlc_807 ( .LO ( optlc_net_806 ) , .HI ( SYNOPSYS_UNCONNECTED_808 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_812 ( .LO ( optlc_net_807 ) , +sky130_fd_sc_hd__conb_1 optlc_808 ( .LO ( optlc_net_807 ) , .HI ( SYNOPSYS_UNCONNECTED_809 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_813 ( .LO ( optlc_net_808 ) , +sky130_fd_sc_hd__conb_1 optlc_809 ( .LO ( optlc_net_808 ) , .HI ( SYNOPSYS_UNCONNECTED_810 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_814 ( .LO ( optlc_net_809 ) , +sky130_fd_sc_hd__conb_1 optlc_810 ( .LO ( optlc_net_809 ) , .HI ( SYNOPSYS_UNCONNECTED_811 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_815 ( .LO ( optlc_net_810 ) , +sky130_fd_sc_hd__conb_1 optlc_811 ( .LO ( optlc_net_810 ) , .HI ( SYNOPSYS_UNCONNECTED_812 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_816 ( .LO ( optlc_net_811 ) , +sky130_fd_sc_hd__conb_1 optlc_812 ( .LO ( optlc_net_811 ) , .HI ( SYNOPSYS_UNCONNECTED_813 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_817 ( .LO ( optlc_net_812 ) , +sky130_fd_sc_hd__conb_1 optlc_813 ( .LO ( optlc_net_812 ) , .HI ( SYNOPSYS_UNCONNECTED_814 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_818 ( .LO ( optlc_net_813 ) , +sky130_fd_sc_hd__conb_1 optlc_814 ( .LO ( optlc_net_813 ) , .HI ( SYNOPSYS_UNCONNECTED_815 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_819 ( .LO ( optlc_net_814 ) , +sky130_fd_sc_hd__conb_1 optlc_815 ( .LO ( optlc_net_814 ) , .HI ( SYNOPSYS_UNCONNECTED_816 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_820 ( .LO ( optlc_net_815 ) , +sky130_fd_sc_hd__conb_1 optlc_816 ( .LO ( optlc_net_815 ) , .HI ( SYNOPSYS_UNCONNECTED_817 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_821 ( .LO ( optlc_net_816 ) , +sky130_fd_sc_hd__conb_1 optlc_817 ( .LO ( optlc_net_816 ) , .HI ( SYNOPSYS_UNCONNECTED_818 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_822 ( .LO ( optlc_net_817 ) , +sky130_fd_sc_hd__conb_1 optlc_818 ( .LO ( optlc_net_817 ) , .HI ( SYNOPSYS_UNCONNECTED_819 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_823 ( .LO ( optlc_net_818 ) , +sky130_fd_sc_hd__conb_1 optlc_819 ( .LO ( optlc_net_818 ) , .HI ( SYNOPSYS_UNCONNECTED_820 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_824 ( .LO ( optlc_net_819 ) , +sky130_fd_sc_hd__conb_1 optlc_820 ( .LO ( optlc_net_819 ) , .HI ( SYNOPSYS_UNCONNECTED_821 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_825 ( .LO ( optlc_net_820 ) , +sky130_fd_sc_hd__conb_1 optlc_821 ( .LO ( optlc_net_820 ) , .HI ( SYNOPSYS_UNCONNECTED_822 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_826 ( .LO ( optlc_net_821 ) , +sky130_fd_sc_hd__conb_1 optlc_822 ( .LO ( optlc_net_821 ) , .HI ( SYNOPSYS_UNCONNECTED_823 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_827 ( .LO ( optlc_net_822 ) , +sky130_fd_sc_hd__conb_1 optlc_823 ( .LO ( optlc_net_822 ) , .HI ( SYNOPSYS_UNCONNECTED_824 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_828 ( .LO ( optlc_net_823 ) , +sky130_fd_sc_hd__conb_1 optlc_824 ( .LO ( optlc_net_823 ) , .HI ( SYNOPSYS_UNCONNECTED_825 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_829 ( .LO ( optlc_net_824 ) , +sky130_fd_sc_hd__conb_1 optlc_825 ( .LO ( optlc_net_824 ) , .HI ( SYNOPSYS_UNCONNECTED_826 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_830 ( .LO ( optlc_net_825 ) , +sky130_fd_sc_hd__conb_1 optlc_826 ( .LO ( optlc_net_825 ) , .HI ( SYNOPSYS_UNCONNECTED_827 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_831 ( .LO ( optlc_net_826 ) , +sky130_fd_sc_hd__conb_1 optlc_827 ( .LO ( optlc_net_826 ) , .HI ( SYNOPSYS_UNCONNECTED_828 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_832 ( .LO ( optlc_net_827 ) , +sky130_fd_sc_hd__conb_1 optlc_828 ( .LO ( optlc_net_827 ) , .HI ( SYNOPSYS_UNCONNECTED_829 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_833 ( .LO ( optlc_net_828 ) , +sky130_fd_sc_hd__conb_1 optlc_829 ( .LO ( optlc_net_828 ) , .HI ( SYNOPSYS_UNCONNECTED_830 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_835 ( .LO ( optlc_net_829 ) , +sky130_fd_sc_hd__conb_1 optlc_830 ( .LO ( optlc_net_829 ) , .HI ( SYNOPSYS_UNCONNECTED_831 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_836 ( .LO ( optlc_net_830 ) , +sky130_fd_sc_hd__conb_1 optlc_831 ( .LO ( optlc_net_830 ) , .HI ( SYNOPSYS_UNCONNECTED_832 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_837 ( .LO ( optlc_net_831 ) , +sky130_fd_sc_hd__conb_1 optlc_832 ( .LO ( optlc_net_831 ) , .HI ( SYNOPSYS_UNCONNECTED_833 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_838 ( .LO ( optlc_net_832 ) , +sky130_fd_sc_hd__conb_1 optlc_833 ( .LO ( optlc_net_832 ) , .HI ( SYNOPSYS_UNCONNECTED_834 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_839 ( .LO ( optlc_net_833 ) , +sky130_fd_sc_hd__conb_1 optlc_835 ( .LO ( optlc_net_833 ) , .HI ( SYNOPSYS_UNCONNECTED_835 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_840 ( .LO ( optlc_net_834 ) , +sky130_fd_sc_hd__conb_1 optlc_836 ( .LO ( optlc_net_834 ) , .HI ( SYNOPSYS_UNCONNECTED_836 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_841 ( .LO ( optlc_net_835 ) , +sky130_fd_sc_hd__conb_1 optlc_837 ( .LO ( optlc_net_835 ) , .HI ( SYNOPSYS_UNCONNECTED_837 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_842 ( .LO ( optlc_net_836 ) , +sky130_fd_sc_hd__conb_1 optlc_838 ( .LO ( optlc_net_836 ) , .HI ( SYNOPSYS_UNCONNECTED_838 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_843 ( .LO ( optlc_net_837 ) , +sky130_fd_sc_hd__conb_1 optlc_839 ( .LO ( optlc_net_837 ) , .HI ( SYNOPSYS_UNCONNECTED_839 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_844 ( .LO ( optlc_net_838 ) , +sky130_fd_sc_hd__conb_1 optlc_840 ( .LO ( optlc_net_838 ) , .HI ( SYNOPSYS_UNCONNECTED_840 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_845 ( .LO ( optlc_net_839 ) , +sky130_fd_sc_hd__conb_1 optlc_841 ( .LO ( optlc_net_839 ) , .HI ( SYNOPSYS_UNCONNECTED_841 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_846 ( .LO ( optlc_net_840 ) , +sky130_fd_sc_hd__conb_1 optlc_842 ( .LO ( optlc_net_840 ) , .HI ( SYNOPSYS_UNCONNECTED_842 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_847 ( .LO ( optlc_net_841 ) , +sky130_fd_sc_hd__conb_1 optlc_843 ( .LO ( optlc_net_841 ) , .HI ( SYNOPSYS_UNCONNECTED_843 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_848 ( .LO ( optlc_net_842 ) , +sky130_fd_sc_hd__conb_1 optlc_844 ( .LO ( optlc_net_842 ) , .HI ( SYNOPSYS_UNCONNECTED_844 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_849 ( .LO ( optlc_net_843 ) , +sky130_fd_sc_hd__conb_1 optlc_845 ( .LO ( optlc_net_843 ) , .HI ( SYNOPSYS_UNCONNECTED_845 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_850 ( .LO ( optlc_net_844 ) , +sky130_fd_sc_hd__conb_1 optlc_846 ( .LO ( optlc_net_844 ) , .HI ( SYNOPSYS_UNCONNECTED_846 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_851 ( .LO ( optlc_net_845 ) , +sky130_fd_sc_hd__conb_1 optlc_847 ( .LO ( optlc_net_845 ) , .HI ( SYNOPSYS_UNCONNECTED_847 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_852 ( .LO ( optlc_net_846 ) , +sky130_fd_sc_hd__conb_1 optlc_848 ( .LO ( optlc_net_846 ) , .HI ( SYNOPSYS_UNCONNECTED_848 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_853 ( .LO ( optlc_net_847 ) , +sky130_fd_sc_hd__conb_1 optlc_849 ( .LO ( optlc_net_847 ) , .HI ( SYNOPSYS_UNCONNECTED_849 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_854 ( .LO ( optlc_net_848 ) , +sky130_fd_sc_hd__conb_1 optlc_850 ( .LO ( optlc_net_848 ) , .HI ( SYNOPSYS_UNCONNECTED_850 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_856 ( .LO ( optlc_net_849 ) , +sky130_fd_sc_hd__conb_1 optlc_851 ( .LO ( optlc_net_849 ) , .HI ( SYNOPSYS_UNCONNECTED_851 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_857 ( .LO ( optlc_net_850 ) , +sky130_fd_sc_hd__conb_1 optlc_852 ( .LO ( optlc_net_850 ) , .HI ( SYNOPSYS_UNCONNECTED_852 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_858 ( .LO ( optlc_net_851 ) , +sky130_fd_sc_hd__conb_1 optlc_853 ( .LO ( optlc_net_851 ) , .HI ( SYNOPSYS_UNCONNECTED_853 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_859 ( .LO ( optlc_net_852 ) , +sky130_fd_sc_hd__conb_1 optlc_854 ( .LO ( optlc_net_852 ) , .HI ( SYNOPSYS_UNCONNECTED_854 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_860 ( .LO ( optlc_net_853 ) , +sky130_fd_sc_hd__conb_1 optlc_855 ( .LO ( optlc_net_853 ) , .HI ( SYNOPSYS_UNCONNECTED_855 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_861 ( .LO ( optlc_net_854 ) , +sky130_fd_sc_hd__conb_1 optlc_856 ( .LO ( optlc_net_854 ) , .HI ( SYNOPSYS_UNCONNECTED_856 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_862 ( .LO ( optlc_net_855 ) , +sky130_fd_sc_hd__conb_1 optlc_857 ( .LO ( optlc_net_855 ) , .HI ( SYNOPSYS_UNCONNECTED_857 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_863 ( .LO ( optlc_net_856 ) , +sky130_fd_sc_hd__conb_1 optlc_858 ( .LO ( optlc_net_856 ) , .HI ( SYNOPSYS_UNCONNECTED_858 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_864 ( .LO ( optlc_net_857 ) , +sky130_fd_sc_hd__conb_1 optlc_859 ( .LO ( optlc_net_857 ) , .HI ( SYNOPSYS_UNCONNECTED_859 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_865 ( .LO ( optlc_net_858 ) , +sky130_fd_sc_hd__conb_1 optlc_860 ( .LO ( optlc_net_858 ) , .HI ( SYNOPSYS_UNCONNECTED_860 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_866 ( .LO ( optlc_net_859 ) , +sky130_fd_sc_hd__conb_1 optlc_861 ( .LO ( optlc_net_859 ) , .HI ( SYNOPSYS_UNCONNECTED_861 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_867 ( .LO ( optlc_net_860 ) , +sky130_fd_sc_hd__conb_1 optlc_862 ( .LO ( optlc_net_860 ) , .HI ( SYNOPSYS_UNCONNECTED_862 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_868 ( .LO ( optlc_net_861 ) , +sky130_fd_sc_hd__conb_1 optlc_863 ( .LO ( optlc_net_861 ) , .HI ( SYNOPSYS_UNCONNECTED_863 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_870 ( .LO ( optlc_net_862 ) , +sky130_fd_sc_hd__conb_1 optlc_864 ( .LO ( optlc_net_862 ) , .HI ( SYNOPSYS_UNCONNECTED_864 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_871 ( .LO ( optlc_net_863 ) , +sky130_fd_sc_hd__conb_1 optlc_865 ( .LO ( optlc_net_863 ) , .HI ( SYNOPSYS_UNCONNECTED_865 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_872 ( .LO ( optlc_net_864 ) , +sky130_fd_sc_hd__conb_1 optlc_866 ( .LO ( optlc_net_864 ) , .HI ( SYNOPSYS_UNCONNECTED_866 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_873 ( .LO ( optlc_net_865 ) , +sky130_fd_sc_hd__conb_1 optlc_867 ( .LO ( optlc_net_865 ) , .HI ( SYNOPSYS_UNCONNECTED_867 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_874 ( .LO ( optlc_net_866 ) , +sky130_fd_sc_hd__conb_1 optlc_868 ( .LO ( optlc_net_866 ) , .HI ( SYNOPSYS_UNCONNECTED_868 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_875 ( .LO ( optlc_net_867 ) , +sky130_fd_sc_hd__conb_1 optlc_869 ( .LO ( optlc_net_867 ) , .HI ( SYNOPSYS_UNCONNECTED_869 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_876 ( .LO ( optlc_net_868 ) , +sky130_fd_sc_hd__conb_1 optlc_870 ( .LO ( optlc_net_868 ) , .HI ( SYNOPSYS_UNCONNECTED_870 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_877 ( .LO ( optlc_net_869 ) , +sky130_fd_sc_hd__conb_1 optlc_871 ( .LO ( optlc_net_869 ) , .HI ( SYNOPSYS_UNCONNECTED_871 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_878 ( .LO ( optlc_net_870 ) , +sky130_fd_sc_hd__conb_1 optlc_872 ( .LO ( optlc_net_870 ) , .HI ( SYNOPSYS_UNCONNECTED_872 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_879 ( .LO ( optlc_net_871 ) , +sky130_fd_sc_hd__conb_1 optlc_873 ( .LO ( optlc_net_871 ) , .HI ( SYNOPSYS_UNCONNECTED_873 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_880 ( .LO ( optlc_net_872 ) , +sky130_fd_sc_hd__conb_1 optlc_874 ( .LO ( optlc_net_872 ) , .HI ( SYNOPSYS_UNCONNECTED_874 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_881 ( .LO ( optlc_net_873 ) , +sky130_fd_sc_hd__conb_1 optlc_875 ( .LO ( optlc_net_873 ) , .HI ( SYNOPSYS_UNCONNECTED_875 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_882 ( .LO ( optlc_net_874 ) , +sky130_fd_sc_hd__conb_1 optlc_876 ( .LO ( optlc_net_874 ) , .HI ( SYNOPSYS_UNCONNECTED_876 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_883 ( .LO ( optlc_net_875 ) , +sky130_fd_sc_hd__conb_1 optlc_877 ( .LO ( optlc_net_875 ) , .HI ( SYNOPSYS_UNCONNECTED_877 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_884 ( .LO ( optlc_net_876 ) , +sky130_fd_sc_hd__conb_1 optlc_878 ( .LO ( optlc_net_876 ) , .HI ( SYNOPSYS_UNCONNECTED_878 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_885 ( .LO ( optlc_net_877 ) , +sky130_fd_sc_hd__conb_1 optlc_879 ( .LO ( optlc_net_877 ) , .HI ( SYNOPSYS_UNCONNECTED_879 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_886 ( .LO ( optlc_net_878 ) , +sky130_fd_sc_hd__conb_1 optlc_880 ( .LO ( optlc_net_878 ) , .HI ( SYNOPSYS_UNCONNECTED_880 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_887 ( .LO ( optlc_net_879 ) , +sky130_fd_sc_hd__conb_1 optlc_881 ( .LO ( optlc_net_879 ) , .HI ( SYNOPSYS_UNCONNECTED_881 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_888 ( .LO ( optlc_net_880 ) , +sky130_fd_sc_hd__conb_1 optlc_882 ( .LO ( optlc_net_880 ) , .HI ( SYNOPSYS_UNCONNECTED_882 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_889 ( .LO ( optlc_net_881 ) , +sky130_fd_sc_hd__conb_1 optlc_883 ( .LO ( optlc_net_881 ) , .HI ( SYNOPSYS_UNCONNECTED_883 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_890 ( .LO ( optlc_net_882 ) , +sky130_fd_sc_hd__conb_1 optlc_884 ( .LO ( optlc_net_882 ) , .HI ( SYNOPSYS_UNCONNECTED_884 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_891 ( .LO ( optlc_net_883 ) , +sky130_fd_sc_hd__conb_1 optlc_885 ( .LO ( optlc_net_883 ) , .HI ( SYNOPSYS_UNCONNECTED_885 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_892 ( .LO ( optlc_net_884 ) , +sky130_fd_sc_hd__conb_1 optlc_886 ( .LO ( optlc_net_884 ) , .HI ( SYNOPSYS_UNCONNECTED_886 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_893 ( .LO ( optlc_net_885 ) , +sky130_fd_sc_hd__conb_1 optlc_887 ( .LO ( optlc_net_885 ) , .HI ( SYNOPSYS_UNCONNECTED_887 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_894 ( .LO ( optlc_net_886 ) , +sky130_fd_sc_hd__conb_1 optlc_888 ( .LO ( optlc_net_886 ) , .HI ( SYNOPSYS_UNCONNECTED_888 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_895 ( .LO ( optlc_net_887 ) , +sky130_fd_sc_hd__conb_1 optlc_889 ( .LO ( optlc_net_887 ) , .HI ( SYNOPSYS_UNCONNECTED_889 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_896 ( .LO ( optlc_net_888 ) , +sky130_fd_sc_hd__conb_1 optlc_890 ( .LO ( optlc_net_888 ) , .HI ( SYNOPSYS_UNCONNECTED_890 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_897 ( .LO ( optlc_net_889 ) , +sky130_fd_sc_hd__conb_1 optlc_891 ( .LO ( optlc_net_889 ) , .HI ( SYNOPSYS_UNCONNECTED_891 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_898 ( .LO ( optlc_net_890 ) , +sky130_fd_sc_hd__conb_1 optlc_892 ( .LO ( optlc_net_890 ) , .HI ( SYNOPSYS_UNCONNECTED_892 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_899 ( .LO ( optlc_net_891 ) , +sky130_fd_sc_hd__conb_1 optlc_893 ( .LO ( optlc_net_891 ) , .HI ( SYNOPSYS_UNCONNECTED_893 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_900 ( .LO ( optlc_net_892 ) , +sky130_fd_sc_hd__conb_1 optlc_894 ( .LO ( optlc_net_892 ) , .HI ( SYNOPSYS_UNCONNECTED_894 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_901 ( .LO ( optlc_net_893 ) , +sky130_fd_sc_hd__conb_1 optlc_895 ( .LO ( optlc_net_893 ) , .HI ( SYNOPSYS_UNCONNECTED_895 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_902 ( .LO ( optlc_net_894 ) , +sky130_fd_sc_hd__conb_1 optlc_896 ( .LO ( optlc_net_894 ) , .HI ( SYNOPSYS_UNCONNECTED_896 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_903 ( .LO ( optlc_net_895 ) , +sky130_fd_sc_hd__conb_1 optlc_897 ( .LO ( optlc_net_895 ) , .HI ( SYNOPSYS_UNCONNECTED_897 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_904 ( .LO ( optlc_net_896 ) , +sky130_fd_sc_hd__conb_1 optlc_898 ( .LO ( optlc_net_896 ) , .HI ( SYNOPSYS_UNCONNECTED_898 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_905 ( .LO ( optlc_net_897 ) , +sky130_fd_sc_hd__conb_1 optlc_899 ( .LO ( optlc_net_897 ) , .HI ( SYNOPSYS_UNCONNECTED_899 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_906 ( .LO ( optlc_net_898 ) , +sky130_fd_sc_hd__conb_1 optlc_900 ( .LO ( optlc_net_898 ) , .HI ( SYNOPSYS_UNCONNECTED_900 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_907 ( .LO ( optlc_net_899 ) , +sky130_fd_sc_hd__conb_1 optlc_901 ( .LO ( optlc_net_899 ) , .HI ( SYNOPSYS_UNCONNECTED_901 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_908 ( .LO ( optlc_net_900 ) , +sky130_fd_sc_hd__conb_1 optlc_902 ( .LO ( optlc_net_900 ) , .HI ( SYNOPSYS_UNCONNECTED_902 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_909 ( .LO ( optlc_net_901 ) , +sky130_fd_sc_hd__conb_1 optlc_903 ( .LO ( optlc_net_901 ) , .HI ( SYNOPSYS_UNCONNECTED_903 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_910 ( .LO ( optlc_net_902 ) , +sky130_fd_sc_hd__conb_1 optlc_904 ( .LO ( optlc_net_902 ) , .HI ( SYNOPSYS_UNCONNECTED_904 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_911 ( .LO ( optlc_net_903 ) , +sky130_fd_sc_hd__conb_1 optlc_905 ( .LO ( optlc_net_903 ) , .HI ( SYNOPSYS_UNCONNECTED_905 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_912 ( .LO ( optlc_net_904 ) , +sky130_fd_sc_hd__conb_1 optlc_906 ( .LO ( optlc_net_904 ) , .HI ( SYNOPSYS_UNCONNECTED_906 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_913 ( .LO ( optlc_net_905 ) , +sky130_fd_sc_hd__conb_1 optlc_907 ( .LO ( optlc_net_905 ) , .HI ( SYNOPSYS_UNCONNECTED_907 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_915 ( .LO ( optlc_net_906 ) , +sky130_fd_sc_hd__conb_1 optlc_908 ( .LO ( optlc_net_906 ) , .HI ( SYNOPSYS_UNCONNECTED_908 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_916 ( .LO ( optlc_net_907 ) , +sky130_fd_sc_hd__conb_1 optlc_909 ( .LO ( optlc_net_907 ) , .HI ( SYNOPSYS_UNCONNECTED_909 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_917 ( .LO ( optlc_net_908 ) , +sky130_fd_sc_hd__conb_1 optlc_910 ( .LO ( optlc_net_908 ) , .HI ( SYNOPSYS_UNCONNECTED_910 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_918 ( .LO ( optlc_net_909 ) , +sky130_fd_sc_hd__conb_1 optlc_911 ( .LO ( optlc_net_909 ) , .HI ( SYNOPSYS_UNCONNECTED_911 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_919 ( .LO ( optlc_net_910 ) , +sky130_fd_sc_hd__conb_1 optlc_912 ( .LO ( optlc_net_910 ) , .HI ( SYNOPSYS_UNCONNECTED_912 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_920 ( .LO ( optlc_net_911 ) , +sky130_fd_sc_hd__conb_1 optlc_913 ( .LO ( optlc_net_911 ) , .HI ( SYNOPSYS_UNCONNECTED_913 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_921 ( .LO ( optlc_net_912 ) , +sky130_fd_sc_hd__conb_1 optlc_914 ( .LO ( optlc_net_912 ) , .HI ( SYNOPSYS_UNCONNECTED_914 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_922 ( .LO ( optlc_net_913 ) , +sky130_fd_sc_hd__conb_1 optlc_916 ( .LO ( optlc_net_913 ) , .HI ( SYNOPSYS_UNCONNECTED_915 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_923 ( .LO ( optlc_net_914 ) , +sky130_fd_sc_hd__conb_1 optlc_917 ( .LO ( optlc_net_914 ) , .HI ( SYNOPSYS_UNCONNECTED_916 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_924 ( .LO ( optlc_net_915 ) , +sky130_fd_sc_hd__conb_1 optlc_919 ( .LO ( optlc_net_915 ) , .HI ( SYNOPSYS_UNCONNECTED_917 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_925 ( .LO ( optlc_net_916 ) , +sky130_fd_sc_hd__conb_1 optlc_920 ( .LO ( optlc_net_916 ) , .HI ( SYNOPSYS_UNCONNECTED_918 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_926 ( .LO ( optlc_net_917 ) , +sky130_fd_sc_hd__conb_1 optlc_921 ( .LO ( optlc_net_917 ) , .HI ( SYNOPSYS_UNCONNECTED_919 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_927 ( .LO ( optlc_net_918 ) , +sky130_fd_sc_hd__conb_1 optlc_922 ( .LO ( optlc_net_918 ) , .HI ( SYNOPSYS_UNCONNECTED_920 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_928 ( .LO ( optlc_net_919 ) , +sky130_fd_sc_hd__conb_1 optlc_923 ( .LO ( optlc_net_919 ) , .HI ( SYNOPSYS_UNCONNECTED_921 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_929 ( .LO ( optlc_net_920 ) , +sky130_fd_sc_hd__conb_1 optlc_924 ( .LO ( optlc_net_920 ) , .HI ( SYNOPSYS_UNCONNECTED_922 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_930 ( .LO ( optlc_net_921 ) , +sky130_fd_sc_hd__conb_1 optlc_925 ( .LO ( optlc_net_921 ) , .HI ( SYNOPSYS_UNCONNECTED_923 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_931 ( .LO ( optlc_net_922 ) , +sky130_fd_sc_hd__conb_1 optlc_926 ( .LO ( optlc_net_922 ) , .HI ( SYNOPSYS_UNCONNECTED_924 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_932 ( .LO ( optlc_net_923 ) , +sky130_fd_sc_hd__conb_1 optlc_927 ( .LO ( optlc_net_923 ) , .HI ( SYNOPSYS_UNCONNECTED_925 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 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+sky130_fd_sc_hd__conb_1 optlc_1460 ( .LO ( optlc_net_1396 ) , .HI ( SYNOPSYS_UNCONNECTED_1398 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_1460 ( .LO ( optlc_net_1397 ) , +sky130_fd_sc_hd__conb_1 optlc_1461 ( .LO ( optlc_net_1397 ) , .HI ( SYNOPSYS_UNCONNECTED_1399 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_1461 ( .LO ( optlc_net_1398 ) , +sky130_fd_sc_hd__conb_1 optlc_1462 ( .LO ( optlc_net_1398 ) , .HI ( SYNOPSYS_UNCONNECTED_1400 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__conb_1 optlc_1463 ( .LO ( optlc_net_1399 ) , .HI ( SYNOPSYS_UNCONNECTED_1401 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -163910,23 +167531,23 @@ sky130_fd_sc_hd__conb_1 optlc_1464 ( .LO ( optlc_net_1400 ) , .HI ( SYNOPSYS_UNCONNECTED_1402 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__conb_1 optlc_1465 ( .LO ( optlc_net_1401 ) , .HI ( SYNOPSYS_UNCONNECTED_1403 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_1467 ( .LO ( optlc_net_1402 ) , +sky130_fd_sc_hd__conb_1 optlc_1466 ( .LO ( optlc_net_1402 ) , .HI ( SYNOPSYS_UNCONNECTED_1404 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_1468 ( .LO ( optlc_net_1403 ) , +sky130_fd_sc_hd__conb_1 optlc_1467 ( .LO ( optlc_net_1403 ) , .HI ( SYNOPSYS_UNCONNECTED_1405 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_1469 ( .LO ( optlc_net_1404 ) , +sky130_fd_sc_hd__conb_1 optlc_1468 ( .LO ( optlc_net_1404 ) , .HI ( SYNOPSYS_UNCONNECTED_1406 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_1471 ( .LO ( optlc_net_1405 ) , +sky130_fd_sc_hd__conb_1 optlc_1469 ( .LO ( optlc_net_1405 ) , .HI ( SYNOPSYS_UNCONNECTED_1407 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_1472 ( .LO ( optlc_net_1406 ) , +sky130_fd_sc_hd__conb_1 optlc_1471 ( .LO ( optlc_net_1406 ) , .HI ( SYNOPSYS_UNCONNECTED_1408 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_1474 ( .LO ( optlc_net_1407 ) , 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( VSS ) ) ; sky130_fd_sc_hd__conb_1 optlc_1482 ( .LO ( optlc_net_1413 ) , .HI ( SYNOPSYS_UNCONNECTED_1415 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_1484 ( .LO ( optlc_net_1414 ) , +sky130_fd_sc_hd__conb_1 optlc_1483 ( .LO ( optlc_net_1414 ) , .HI ( SYNOPSYS_UNCONNECTED_1416 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_1486 ( .LO ( optlc_net_1415 ) , +sky130_fd_sc_hd__conb_1 optlc_1484 ( .LO ( optlc_net_1415 ) , .HI ( SYNOPSYS_UNCONNECTED_1417 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_1488 ( .LO ( optlc_net_1416 ) , +sky130_fd_sc_hd__conb_1 optlc_1486 ( .LO ( optlc_net_1416 ) , .HI ( SYNOPSYS_UNCONNECTED_1418 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_1489 ( .LO ( optlc_net_1417 ) , +sky130_fd_sc_hd__conb_1 optlc_1487 ( .LO ( optlc_net_1417 ) , .HI ( SYNOPSYS_UNCONNECTED_1419 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_1490 ( .LO ( optlc_net_1418 ) , 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SYNOPSYS_UNCONNECTED_1922 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_2161 ( .LO ( optlc_net_1921 ) , +sky130_fd_sc_hd__conb_1 optlc_2131 ( .LO ( optlc_net_1921 ) , .HI ( SYNOPSYS_UNCONNECTED_1923 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_2162 ( .LO ( optlc_net_1922 ) , +sky130_fd_sc_hd__conb_1 optlc_2133 ( .LO ( optlc_net_1922 ) , .HI ( SYNOPSYS_UNCONNECTED_1924 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_2164 ( .LO ( optlc_net_1923 ) , +sky130_fd_sc_hd__conb_1 optlc_2135 ( .LO ( optlc_net_1923 ) , .HI ( SYNOPSYS_UNCONNECTED_1925 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_2166 ( .LO ( optlc_net_1924 ) , +sky130_fd_sc_hd__conb_1 optlc_2136 ( .LO ( optlc_net_1924 ) , .HI ( SYNOPSYS_UNCONNECTED_1926 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_2167 ( .LO ( optlc_net_1925 ) , +sky130_fd_sc_hd__conb_1 optlc_2137 ( .LO ( optlc_net_1925 ) , .HI ( SYNOPSYS_UNCONNECTED_1927 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_2169 ( .LO ( optlc_net_1926 ) , +sky130_fd_sc_hd__conb_1 optlc_2138 ( .LO ( optlc_net_1926 ) , .HI ( SYNOPSYS_UNCONNECTED_1928 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_2171 ( .LO ( optlc_net_1927 ) , +sky130_fd_sc_hd__conb_1 optlc_2139 ( .LO ( optlc_net_1927 ) , .HI ( SYNOPSYS_UNCONNECTED_1929 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_2173 ( .LO ( optlc_net_1928 ) , +sky130_fd_sc_hd__conb_1 optlc_2141 ( .LO ( optlc_net_1928 ) , .HI ( SYNOPSYS_UNCONNECTED_1930 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_2174 ( .LO ( optlc_net_1929 ) , +sky130_fd_sc_hd__conb_1 optlc_2143 ( .LO ( optlc_net_1929 ) , .HI ( SYNOPSYS_UNCONNECTED_1931 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_2175 ( .LO ( optlc_net_1930 ) , +sky130_fd_sc_hd__conb_1 optlc_2145 ( .LO ( optlc_net_1930 ) , .HI ( SYNOPSYS_UNCONNECTED_1932 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_2176 ( .LO ( optlc_net_1931 ) , +sky130_fd_sc_hd__conb_1 optlc_2146 ( .LO ( optlc_net_1931 ) , .HI ( SYNOPSYS_UNCONNECTED_1933 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_2177 ( .LO ( optlc_net_1932 ) , +sky130_fd_sc_hd__conb_1 optlc_2148 ( .LO ( optlc_net_1932 ) , .HI ( SYNOPSYS_UNCONNECTED_1934 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_2178 ( .LO ( optlc_net_1933 ) , +sky130_fd_sc_hd__conb_1 optlc_2150 ( .LO ( optlc_net_1933 ) , .HI ( SYNOPSYS_UNCONNECTED_1935 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_2180 ( .LO ( optlc_net_1934 ) , +sky130_fd_sc_hd__conb_1 optlc_2151 ( .LO ( optlc_net_1934 ) , .HI ( SYNOPSYS_UNCONNECTED_1936 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_2182 ( .LO ( optlc_net_1935 ) , +sky130_fd_sc_hd__conb_1 optlc_2152 ( .LO ( optlc_net_1935 ) , .HI ( SYNOPSYS_UNCONNECTED_1937 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_2184 ( .LO ( optlc_net_1936 ) , +sky130_fd_sc_hd__conb_1 optlc_2153 ( .LO ( optlc_net_1936 ) , .HI ( SYNOPSYS_UNCONNECTED_1938 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_2185 ( .LO ( optlc_net_1937 ) , +sky130_fd_sc_hd__conb_1 optlc_2155 ( .LO ( optlc_net_1937 ) , .HI ( SYNOPSYS_UNCONNECTED_1939 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_2186 ( .LO ( optlc_net_1938 ) , +sky130_fd_sc_hd__conb_1 optlc_2157 ( .LO ( optlc_net_1938 ) , .HI ( SYNOPSYS_UNCONNECTED_1940 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_2188 ( .LO ( optlc_net_1939 ) , +sky130_fd_sc_hd__conb_1 optlc_2159 ( .LO ( optlc_net_1939 ) , .HI ( SYNOPSYS_UNCONNECTED_1941 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_2189 ( .LO ( optlc_net_1940 ) , +sky130_fd_sc_hd__conb_1 optlc_2161 ( .LO ( optlc_net_1940 ) , .HI ( SYNOPSYS_UNCONNECTED_1942 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_2190 ( .LO ( optlc_net_1941 ) , +sky130_fd_sc_hd__conb_1 optlc_2162 ( .LO ( optlc_net_1941 ) , .HI ( SYNOPSYS_UNCONNECTED_1943 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_2191 ( .LO ( optlc_net_1942 ) , +sky130_fd_sc_hd__conb_1 optlc_2163 ( .LO ( optlc_net_1942 ) , .HI ( SYNOPSYS_UNCONNECTED_1944 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_2193 ( .LO ( optlc_net_1943 ) , +sky130_fd_sc_hd__conb_1 optlc_2164 ( .LO ( optlc_net_1943 ) , .HI ( SYNOPSYS_UNCONNECTED_1945 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_2194 ( .LO ( optlc_net_1944 ) , +sky130_fd_sc_hd__conb_1 optlc_2165 ( .LO ( optlc_net_1944 ) , .HI ( SYNOPSYS_UNCONNECTED_1946 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_2195 ( .LO ( optlc_net_1945 ) , +sky130_fd_sc_hd__conb_1 optlc_2167 ( .LO ( optlc_net_1945 ) , .HI ( SYNOPSYS_UNCONNECTED_1947 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_2197 ( .LO ( optlc_net_1946 ) , +sky130_fd_sc_hd__conb_1 optlc_2169 ( .LO ( optlc_net_1946 ) , .HI ( SYNOPSYS_UNCONNECTED_1948 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_2199 ( .LO ( optlc_net_1947 ) , +sky130_fd_sc_hd__conb_1 optlc_2171 ( .LO ( optlc_net_1947 ) , .HI ( SYNOPSYS_UNCONNECTED_1949 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_2200 ( .LO ( optlc_net_1948 ) , +sky130_fd_sc_hd__conb_1 optlc_2173 ( .LO ( optlc_net_1948 ) , .HI ( SYNOPSYS_UNCONNECTED_1950 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_2201 ( .LO ( optlc_net_1949 ) , +sky130_fd_sc_hd__conb_1 optlc_2174 ( .LO ( optlc_net_1949 ) , .HI ( SYNOPSYS_UNCONNECTED_1951 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_2202 ( .LO ( optlc_net_1950 ) , +sky130_fd_sc_hd__conb_1 optlc_2175 ( .LO ( optlc_net_1950 ) , .HI ( SYNOPSYS_UNCONNECTED_1952 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_2204 ( .LO ( optlc_net_1951 ) , +sky130_fd_sc_hd__conb_1 optlc_2177 ( .LO ( optlc_net_1951 ) , .HI ( SYNOPSYS_UNCONNECTED_1953 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_2206 ( .LO ( optlc_net_1952 ) , +sky130_fd_sc_hd__conb_1 optlc_2179 ( .LO ( optlc_net_1952 ) , .HI ( SYNOPSYS_UNCONNECTED_1954 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_2207 ( .LO ( optlc_net_1953 ) , +sky130_fd_sc_hd__conb_1 optlc_2180 ( .LO ( optlc_net_1953 ) , .HI ( SYNOPSYS_UNCONNECTED_1955 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_2209 ( .LO ( optlc_net_1954 ) , +sky130_fd_sc_hd__conb_1 optlc_2181 ( .LO ( optlc_net_1954 ) , .HI ( SYNOPSYS_UNCONNECTED_1956 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_2210 ( .LO ( optlc_net_1955 ) , +sky130_fd_sc_hd__conb_1 optlc_2182 ( .LO ( optlc_net_1955 ) , .HI ( SYNOPSYS_UNCONNECTED_1957 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_2212 ( .LO ( optlc_net_1956 ) , +sky130_fd_sc_hd__conb_1 optlc_2183 ( .LO ( optlc_net_1956 ) , .HI ( SYNOPSYS_UNCONNECTED_1958 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_2214 ( .LO ( optlc_net_1957 ) , +sky130_fd_sc_hd__conb_1 optlc_2185 ( .LO ( optlc_net_1957 ) , .HI ( SYNOPSYS_UNCONNECTED_1959 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_2215 ( .LO ( optlc_net_1958 ) , +sky130_fd_sc_hd__conb_1 optlc_2187 ( .LO ( optlc_net_1958 ) , .HI ( SYNOPSYS_UNCONNECTED_1960 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_2217 ( .LO ( optlc_net_1959 ) , +sky130_fd_sc_hd__conb_1 optlc_2188 ( .LO ( optlc_net_1959 ) , .HI ( SYNOPSYS_UNCONNECTED_1961 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_2218 ( .LO ( optlc_net_1960 ) , +sky130_fd_sc_hd__conb_1 optlc_2189 ( .LO ( optlc_net_1960 ) , .HI ( SYNOPSYS_UNCONNECTED_1962 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_2220 ( .LO ( optlc_net_1961 ) , +sky130_fd_sc_hd__conb_1 optlc_2190 ( .LO ( optlc_net_1961 ) , .HI ( SYNOPSYS_UNCONNECTED_1963 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_2222 ( .LO ( optlc_net_1962 ) , +sky130_fd_sc_hd__conb_1 optlc_2192 ( .LO ( optlc_net_1962 ) , .HI ( SYNOPSYS_UNCONNECTED_1964 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_2224 ( .LO ( optlc_net_1963 ) , +sky130_fd_sc_hd__conb_1 optlc_2193 ( .LO ( optlc_net_1963 ) , .HI ( SYNOPSYS_UNCONNECTED_1965 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_2225 ( .LO ( optlc_net_1964 ) , +sky130_fd_sc_hd__conb_1 optlc_2194 ( .LO ( optlc_net_1964 ) , .HI ( SYNOPSYS_UNCONNECTED_1966 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_2226 ( .LO ( optlc_net_1965 ) , +sky130_fd_sc_hd__conb_1 optlc_2196 ( .LO ( optlc_net_1965 ) , .HI ( SYNOPSYS_UNCONNECTED_1967 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_2227 ( .LO ( optlc_net_1966 ) , +sky130_fd_sc_hd__conb_1 optlc_2198 ( .LO ( optlc_net_1966 ) , .HI ( SYNOPSYS_UNCONNECTED_1968 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_2229 ( .LO ( optlc_net_1967 ) , +sky130_fd_sc_hd__conb_1 optlc_2199 ( .LO ( optlc_net_1967 ) , .HI ( SYNOPSYS_UNCONNECTED_1969 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_2231 ( .LO ( optlc_net_1968 ) , +sky130_fd_sc_hd__conb_1 optlc_2200 ( .LO ( optlc_net_1968 ) , .HI ( SYNOPSYS_UNCONNECTED_1970 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_2233 ( .LO ( optlc_net_1969 ) , +sky130_fd_sc_hd__conb_1 optlc_2202 ( .LO ( optlc_net_1969 ) , .HI ( SYNOPSYS_UNCONNECTED_1971 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_2235 ( .LO ( optlc_net_1970 ) , +sky130_fd_sc_hd__conb_1 optlc_2204 ( .LO ( optlc_net_1970 ) , .HI ( SYNOPSYS_UNCONNECTED_1972 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_2236 ( .LO ( optlc_net_1971 ) , +sky130_fd_sc_hd__conb_1 optlc_2205 ( .LO ( optlc_net_1971 ) , .HI ( SYNOPSYS_UNCONNECTED_1973 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_2237 ( .LO ( optlc_net_1972 ) , +sky130_fd_sc_hd__conb_1 optlc_2207 ( .LO ( optlc_net_1972 ) , .HI ( SYNOPSYS_UNCONNECTED_1974 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_2238 ( .LO ( optlc_net_1973 ) , +sky130_fd_sc_hd__conb_1 optlc_2209 ( .LO ( optlc_net_1973 ) , .HI ( SYNOPSYS_UNCONNECTED_1975 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_2239 ( .LO ( optlc_net_1974 ) , +sky130_fd_sc_hd__conb_1 optlc_2211 ( .LO ( optlc_net_1974 ) , .HI ( SYNOPSYS_UNCONNECTED_1976 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_2240 ( .LO ( optlc_net_1975 ) , +sky130_fd_sc_hd__conb_1 optlc_2212 ( .LO ( optlc_net_1975 ) , .HI ( SYNOPSYS_UNCONNECTED_1977 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_2242 ( .LO ( optlc_net_1976 ) , +sky130_fd_sc_hd__conb_1 optlc_2214 ( .LO ( optlc_net_1976 ) , .HI ( SYNOPSYS_UNCONNECTED_1978 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_2243 ( .LO ( optlc_net_1977 ) , +sky130_fd_sc_hd__conb_1 optlc_2216 ( .LO ( optlc_net_1977 ) , .HI ( SYNOPSYS_UNCONNECTED_1979 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_2245 ( .LO ( optlc_net_1978 ) , +sky130_fd_sc_hd__conb_1 optlc_2217 ( .LO ( optlc_net_1978 ) , .HI ( SYNOPSYS_UNCONNECTED_1980 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_2247 ( .LO ( optlc_net_1979 ) , +sky130_fd_sc_hd__conb_1 optlc_2218 ( .LO ( optlc_net_1979 ) , .HI ( SYNOPSYS_UNCONNECTED_1981 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_2248 ( .LO ( optlc_net_1980 ) , +sky130_fd_sc_hd__conb_1 optlc_2219 ( .LO ( optlc_net_1980 ) , .HI ( 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SYNOPSYS_UNCONNECTED_3523 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_3982 ( .LO ( optlc_net_3522 ) , +sky130_fd_sc_hd__conb_1 optlc_3873 ( .LO ( optlc_net_3522 ) , .HI ( SYNOPSYS_UNCONNECTED_3524 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_3983 ( .LO ( optlc_net_3523 ) , +sky130_fd_sc_hd__conb_1 optlc_3874 ( .LO ( optlc_net_3523 ) , .HI ( SYNOPSYS_UNCONNECTED_3525 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_3984 ( .LO ( optlc_net_3524 ) , +sky130_fd_sc_hd__conb_1 optlc_3875 ( .LO ( optlc_net_3524 ) , .HI ( SYNOPSYS_UNCONNECTED_3526 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_3985 ( .LO ( optlc_net_3525 ) , +sky130_fd_sc_hd__conb_1 optlc_3876 ( .LO ( optlc_net_3525 ) , .HI ( SYNOPSYS_UNCONNECTED_3527 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_3986 ( .LO ( optlc_net_3526 ) , +sky130_fd_sc_hd__conb_1 optlc_3877 ( .LO ( optlc_net_3526 ) , .HI ( SYNOPSYS_UNCONNECTED_3528 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_3987 ( .LO ( optlc_net_3527 ) , +sky130_fd_sc_hd__conb_1 optlc_3878 ( .LO ( optlc_net_3527 ) , .HI ( SYNOPSYS_UNCONNECTED_3529 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_3988 ( .LO ( optlc_net_3528 ) , +sky130_fd_sc_hd__conb_1 optlc_3879 ( .LO ( optlc_net_3528 ) , .HI ( SYNOPSYS_UNCONNECTED_3530 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_3989 ( .LO ( optlc_net_3529 ) , +sky130_fd_sc_hd__conb_1 optlc_3880 ( .LO ( optlc_net_3529 ) , .HI ( SYNOPSYS_UNCONNECTED_3531 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3881 ( .LO ( optlc_net_3530 ) , + .HI ( SYNOPSYS_UNCONNECTED_3532 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3882 ( .LO ( optlc_net_3531 ) , + .HI ( SYNOPSYS_UNCONNECTED_3533 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3883 ( .LO ( optlc_net_3532 ) , + .HI ( SYNOPSYS_UNCONNECTED_3534 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3884 ( .LO ( optlc_net_3533 ) , + .HI ( SYNOPSYS_UNCONNECTED_3535 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3885 ( .LO ( optlc_net_3534 ) , + .HI ( SYNOPSYS_UNCONNECTED_3536 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3886 ( .LO ( optlc_net_3535 ) , + .HI ( SYNOPSYS_UNCONNECTED_3537 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3887 ( .LO ( optlc_net_3536 ) , + .HI ( SYNOPSYS_UNCONNECTED_3538 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3888 ( .LO ( optlc_net_3537 ) , + .HI ( SYNOPSYS_UNCONNECTED_3539 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3889 ( .LO ( optlc_net_3538 ) , + .HI ( SYNOPSYS_UNCONNECTED_3540 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3890 ( .LO ( optlc_net_3539 ) , + .HI ( SYNOPSYS_UNCONNECTED_3541 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3891 ( .LO ( optlc_net_3540 ) , + .HI ( SYNOPSYS_UNCONNECTED_3542 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3892 ( .LO ( optlc_net_3541 ) , + .HI ( SYNOPSYS_UNCONNECTED_3543 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3893 ( .LO ( optlc_net_3542 ) , + .HI ( SYNOPSYS_UNCONNECTED_3544 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3894 ( .LO ( optlc_net_3543 ) , + .HI ( SYNOPSYS_UNCONNECTED_3545 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3895 ( .LO ( optlc_net_3544 ) , + .HI ( SYNOPSYS_UNCONNECTED_3546 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3896 ( .LO ( optlc_net_3545 ) , + .HI ( SYNOPSYS_UNCONNECTED_3547 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3897 ( .LO ( optlc_net_3546 ) , + .HI ( SYNOPSYS_UNCONNECTED_3548 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3898 ( .LO ( optlc_net_3547 ) , + .HI ( SYNOPSYS_UNCONNECTED_3549 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3899 ( .LO ( optlc_net_3548 ) , + .HI ( SYNOPSYS_UNCONNECTED_3550 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3900 ( .LO ( optlc_net_3549 ) , + .HI ( SYNOPSYS_UNCONNECTED_3551 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3901 ( .LO ( optlc_net_3550 ) , + .HI ( SYNOPSYS_UNCONNECTED_3552 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3902 ( .LO ( optlc_net_3551 ) , + .HI ( SYNOPSYS_UNCONNECTED_3553 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3903 ( .LO ( optlc_net_3552 ) , + .HI ( SYNOPSYS_UNCONNECTED_3554 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3904 ( .LO ( optlc_net_3553 ) , + .HI ( SYNOPSYS_UNCONNECTED_3555 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3905 ( .LO ( optlc_net_3554 ) , + .HI ( SYNOPSYS_UNCONNECTED_3556 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3906 ( .LO ( optlc_net_3555 ) , + .HI ( SYNOPSYS_UNCONNECTED_3557 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3907 ( .LO ( optlc_net_3556 ) , + .HI ( SYNOPSYS_UNCONNECTED_3558 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3908 ( .LO ( optlc_net_3557 ) , + .HI ( SYNOPSYS_UNCONNECTED_3559 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3909 ( .LO ( optlc_net_3558 ) , + .HI ( SYNOPSYS_UNCONNECTED_3560 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3910 ( .LO ( optlc_net_3559 ) , + .HI ( SYNOPSYS_UNCONNECTED_3561 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3911 ( .LO ( optlc_net_3560 ) , + .HI ( SYNOPSYS_UNCONNECTED_3562 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3912 ( .LO ( optlc_net_3561 ) , + .HI ( SYNOPSYS_UNCONNECTED_3563 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3913 ( .LO ( optlc_net_3562 ) , + .HI ( SYNOPSYS_UNCONNECTED_3564 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3914 ( .LO ( optlc_net_3563 ) , + .HI ( SYNOPSYS_UNCONNECTED_3565 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3915 ( .LO ( optlc_net_3564 ) , + .HI ( SYNOPSYS_UNCONNECTED_3566 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3916 ( .LO ( optlc_net_3565 ) , + .HI ( SYNOPSYS_UNCONNECTED_3567 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3917 ( .LO ( optlc_net_3566 ) , + .HI ( SYNOPSYS_UNCONNECTED_3568 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3918 ( .LO ( optlc_net_3567 ) , + .HI ( SYNOPSYS_UNCONNECTED_3569 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3919 ( .LO ( optlc_net_3568 ) , + .HI ( SYNOPSYS_UNCONNECTED_3570 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3920 ( .LO ( optlc_net_3569 ) , + .HI ( SYNOPSYS_UNCONNECTED_3571 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3921 ( .LO ( optlc_net_3570 ) , + .HI ( SYNOPSYS_UNCONNECTED_3572 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3922 ( .LO ( optlc_net_3571 ) , + .HI ( SYNOPSYS_UNCONNECTED_3573 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3923 ( .LO ( optlc_net_3572 ) , + .HI ( SYNOPSYS_UNCONNECTED_3574 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3924 ( .LO ( optlc_net_3573 ) , + .HI ( SYNOPSYS_UNCONNECTED_3575 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3925 ( .LO ( optlc_net_3574 ) , + .HI ( SYNOPSYS_UNCONNECTED_3576 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3926 ( .LO ( optlc_net_3575 ) , + .HI ( SYNOPSYS_UNCONNECTED_3577 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3927 ( .LO ( optlc_net_3576 ) , + .HI ( SYNOPSYS_UNCONNECTED_3578 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3928 ( .LO ( optlc_net_3577 ) , + .HI ( SYNOPSYS_UNCONNECTED_3579 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3929 ( .LO ( optlc_net_3578 ) , + .HI ( SYNOPSYS_UNCONNECTED_3580 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3930 ( .LO ( optlc_net_3579 ) , + .HI ( SYNOPSYS_UNCONNECTED_3581 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3931 ( .LO ( optlc_net_3580 ) , + .HI ( SYNOPSYS_UNCONNECTED_3582 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3932 ( .LO ( optlc_net_3581 ) , + .HI ( SYNOPSYS_UNCONNECTED_3583 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3933 ( .LO ( optlc_net_3582 ) , + .HI ( SYNOPSYS_UNCONNECTED_3584 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3934 ( .LO ( optlc_net_3583 ) , + .HI ( SYNOPSYS_UNCONNECTED_3585 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3935 ( .LO ( optlc_net_3584 ) , + .HI ( SYNOPSYS_UNCONNECTED_3586 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3936 ( .LO ( optlc_net_3585 ) , + .HI ( SYNOPSYS_UNCONNECTED_3587 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3937 ( .LO ( optlc_net_3586 ) , + .HI ( SYNOPSYS_UNCONNECTED_3588 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3938 ( .LO ( optlc_net_3587 ) , + .HI ( SYNOPSYS_UNCONNECTED_3589 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3939 ( .LO ( optlc_net_3588 ) , + .HI ( SYNOPSYS_UNCONNECTED_3590 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3940 ( .LO ( optlc_net_3589 ) , + .HI ( SYNOPSYS_UNCONNECTED_3591 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3941 ( .LO ( optlc_net_3590 ) , + .HI ( SYNOPSYS_UNCONNECTED_3592 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3942 ( .LO ( optlc_net_3591 ) , + .HI ( SYNOPSYS_UNCONNECTED_3593 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3943 ( .LO ( optlc_net_3592 ) , + .HI ( SYNOPSYS_UNCONNECTED_3594 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3944 ( .LO ( optlc_net_3593 ) , + .HI ( SYNOPSYS_UNCONNECTED_3595 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3945 ( .LO ( optlc_net_3594 ) , + .HI ( SYNOPSYS_UNCONNECTED_3596 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3946 ( .LO ( optlc_net_3595 ) , + .HI ( SYNOPSYS_UNCONNECTED_3597 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3947 ( .LO ( optlc_net_3596 ) , + .HI ( SYNOPSYS_UNCONNECTED_3598 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3948 ( .LO ( optlc_net_3597 ) , + .HI ( SYNOPSYS_UNCONNECTED_3599 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3949 ( .LO ( optlc_net_3598 ) , + .HI ( SYNOPSYS_UNCONNECTED_3600 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3950 ( .LO ( optlc_net_3599 ) , + .HI ( SYNOPSYS_UNCONNECTED_3601 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3951 ( .LO ( optlc_net_3600 ) , + .HI ( SYNOPSYS_UNCONNECTED_3602 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3952 ( .LO ( optlc_net_3601 ) , + .HI ( SYNOPSYS_UNCONNECTED_3603 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3953 ( .LO ( optlc_net_3602 ) , + .HI ( SYNOPSYS_UNCONNECTED_3604 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3954 ( .LO ( optlc_net_3603 ) , + .HI ( SYNOPSYS_UNCONNECTED_3605 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3955 ( .LO ( optlc_net_3604 ) , + .HI ( SYNOPSYS_UNCONNECTED_3606 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3956 ( .LO ( optlc_net_3605 ) , + .HI ( SYNOPSYS_UNCONNECTED_3607 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3957 ( .LO ( optlc_net_3606 ) , + .HI ( SYNOPSYS_UNCONNECTED_3608 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3958 ( .LO ( optlc_net_3607 ) , + .HI ( SYNOPSYS_UNCONNECTED_3609 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3959 ( .LO ( optlc_net_3608 ) , + .HI ( SYNOPSYS_UNCONNECTED_3610 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3960 ( .LO ( optlc_net_3609 ) , + .HI ( SYNOPSYS_UNCONNECTED_3611 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3961 ( .LO ( optlc_net_3610 ) , + .HI ( SYNOPSYS_UNCONNECTED_3612 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3962 ( .LO ( optlc_net_3611 ) , + .HI ( SYNOPSYS_UNCONNECTED_3613 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3963 ( .LO ( optlc_net_3612 ) , + .HI ( SYNOPSYS_UNCONNECTED_3614 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3964 ( .LO ( optlc_net_3613 ) , + .HI ( SYNOPSYS_UNCONNECTED_3615 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3965 ( .LO ( optlc_net_3614 ) , + .HI ( SYNOPSYS_UNCONNECTED_3616 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3966 ( .LO ( optlc_net_3615 ) , + .HI ( SYNOPSYS_UNCONNECTED_3617 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3967 ( .LO ( optlc_net_3616 ) , + .HI ( SYNOPSYS_UNCONNECTED_3618 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3968 ( .LO ( optlc_net_3617 ) , + .HI ( SYNOPSYS_UNCONNECTED_3619 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3969 ( .LO ( optlc_net_3618 ) , + .HI ( SYNOPSYS_UNCONNECTED_3620 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3970 ( .LO ( optlc_net_3619 ) , + .HI ( SYNOPSYS_UNCONNECTED_3621 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3971 ( .LO ( optlc_net_3620 ) , + .HI ( SYNOPSYS_UNCONNECTED_3622 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3972 ( .LO ( optlc_net_3621 ) , + .HI ( SYNOPSYS_UNCONNECTED_3623 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3973 ( .LO ( optlc_net_3622 ) , + .HI ( SYNOPSYS_UNCONNECTED_3624 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3974 ( .LO ( optlc_net_3623 ) , + .HI ( SYNOPSYS_UNCONNECTED_3625 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3975 ( .LO ( optlc_net_3624 ) , + .HI ( SYNOPSYS_UNCONNECTED_3626 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3976 ( .LO ( optlc_net_3625 ) , + .HI ( SYNOPSYS_UNCONNECTED_3627 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3977 ( .LO ( optlc_net_3626 ) , + .HI ( SYNOPSYS_UNCONNECTED_3628 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3978 ( .LO ( optlc_net_3627 ) , + .HI ( SYNOPSYS_UNCONNECTED_3629 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3979 ( .LO ( optlc_net_3628 ) , + .HI ( SYNOPSYS_UNCONNECTED_3630 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3980 ( .LO ( optlc_net_3629 ) , + .HI ( SYNOPSYS_UNCONNECTED_3631 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3981 ( .LO ( optlc_net_3630 ) , + .HI ( SYNOPSYS_UNCONNECTED_3632 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3982 ( .LO ( optlc_net_3631 ) , + .HI ( SYNOPSYS_UNCONNECTED_3633 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3983 ( .LO ( optlc_net_3632 ) , + .HI ( SYNOPSYS_UNCONNECTED_3634 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3984 ( .LO ( optlc_net_3633 ) , + .HI ( SYNOPSYS_UNCONNECTED_3635 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3985 ( .LO ( optlc_net_3634 ) , + .HI ( SYNOPSYS_UNCONNECTED_3636 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3986 ( .LO ( optlc_net_3635 ) , + .HI ( SYNOPSYS_UNCONNECTED_3637 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3987 ( .LO ( optlc_net_3636 ) , + .HI ( SYNOPSYS_UNCONNECTED_3638 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3988 ( .LO ( optlc_net_3637 ) , + .HI ( SYNOPSYS_UNCONNECTED_3639 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3989 ( .LO ( optlc_net_3638 ) , + .HI ( SYNOPSYS_UNCONNECTED_3640 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3990 ( .LO ( optlc_net_3639 ) , + .HI ( SYNOPSYS_UNCONNECTED_3641 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3991 ( .LO ( optlc_net_3640 ) , + .HI ( SYNOPSYS_UNCONNECTED_3642 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule diff --git a/FPGA1212_SOFA_CHD_PNR/fpga_top/fpga_top_icv_in_design.nominal_25.spef.bz2 b/FPGA1212_SOFA_CHD_PNR/fpga_top/fpga_top_icv_in_design.nominal_25.spef.bz2 deleted file mode 100644 index 358c8e3..0000000 Binary files a/FPGA1212_SOFA_CHD_PNR/fpga_top/fpga_top_icv_in_design.nominal_25.spef.bz2 and /dev/null differ diff --git a/FPGA1212_SOFA_CHD_PNR/fpga_top/fpga_top_icv_in_design.nominal_25.spef.gz b/FPGA1212_SOFA_CHD_PNR/fpga_top/fpga_top_icv_in_design.nominal_25.spef.gz new file mode 100644 index 0000000..7bfd76c Binary files /dev/null and b/FPGA1212_SOFA_CHD_PNR/fpga_top/fpga_top_icv_in_design.nominal_25.spef.gz differ diff --git a/FPGA1212_SOFA_CHD_PNR/fpga_top/fpga_top_icv_in_design.pt.v b/FPGA1212_SOFA_CHD_PNR/fpga_top/fpga_top_icv_in_design.pt.v index 27cf555..20eecc8 100644 --- a/FPGA1212_SOFA_CHD_PNR/fpga_top/fpga_top_icv_in_design.pt.v +++ b/FPGA1212_SOFA_CHD_PNR/fpga_top/fpga_top_icv_in_design.pt.v @@ -12,18 +12,10 @@ input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:0] mem_out ; -wire copt_net_114 ; +assign ccff_tail[0] = mem_out[0] ; sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( copt_net_114 ) ) ; -sky130_fd_sc_hd__buf_6 FTB_18__17 ( .A ( copt_net_116 ) , - .X ( ccff_tail[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1354 ( .A ( copt_net_114 ) , - .X ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1355 ( .A ( mem_out[0] ) , - .X ( copt_net_115 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1356 ( .A ( copt_net_115 ) , - .X ( copt_net_116 ) ) ; + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; endmodule @@ -38,16 +30,12 @@ input FPGA_DIR ; input IO_ISOL_N ; sky130_fd_sc_hd__or2b_4 ISOL_EN_GATE ( .A ( FPGA_DIR ) , .B_N ( IO_ISOL_N ) , - .X ( aps_rename_510_ ) ) ; -sky130_fd_sc_hd__inv_1 INV_SOC_DIR ( .A ( aps_rename_510_ ) , - .Y ( SOC_DIR_N ) ) ; + .X ( SOC_DIR ) ) ; +sky130_fd_sc_hd__inv_1 INV_SOC_DIR ( .A ( SOC_DIR ) , .Y ( SOC_DIR_N ) ) ; sky130_fd_sc_hd__ebufn_4 IN_PROTECT_GATE ( .A ( SOC_IN ) , .TE_B ( SOC_DIR_N ) , .Z ( FPGA_IN ) ) ; sky130_fd_sc_hd__ebufn_4 OUT_PROTECT_GATE ( .A ( FPGA_OUT ) , - .TE_B ( aps_rename_510_ ) , .Z ( SOC_OUT ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_81 ( .A ( aps_rename_510_ ) , - .Y ( BUF_net_81 ) ) ; -sky130_fd_sc_hd__inv_6 BINV_R_80 ( .A ( BUF_net_81 ) , .Y ( SOC_DIR ) ) ; + .TE_B ( SOC_DIR ) , .Z ( SOC_OUT ) ) ; endmodule @@ -113,6 +101,8 @@ input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; +assign ccff_tail[0] = mem_out[3] ; + sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , @@ -121,7 +111,6 @@ sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__buf_1 FTB_17__16 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -133,6 +122,8 @@ input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; +assign ccff_tail[0] = mem_out[3] ; + sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , @@ -141,7 +132,6 @@ sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__buf_1 FTB_16__15 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -153,6 +143,8 @@ input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; +assign ccff_tail[0] = mem_out[3] ; + sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , @@ -161,7 +153,6 @@ sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__buf_1 FTB_15__14 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -173,6 +164,8 @@ input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; +assign ccff_tail[0] = mem_out[3] ; + sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , @@ -181,7 +174,6 @@ sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__buf_1 FTB_14__13 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -193,6 +185,8 @@ input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; +assign ccff_tail[0] = mem_out[3] ; + sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , @@ -201,7 +195,6 @@ sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__buf_1 FTB_13__12 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -213,6 +206,8 @@ input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; +assign ccff_tail[0] = mem_out[3] ; + sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , @@ -221,7 +216,6 @@ sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__buf_1 FTB_12__11 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -233,6 +227,8 @@ input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; +assign ccff_tail[0] = mem_out[3] ; + sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , @@ -241,7 +237,6 @@ sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__buf_1 FTB_11__10 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -253,6 +248,8 @@ input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; +assign ccff_tail[0] = mem_out[3] ; + sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , @@ -261,7 +258,6 @@ sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__buf_1 FTB_10__9 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -271,26 +267,34 @@ input [0:1] mem ; input [0:1] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule -module cby_2__1__mux_2level_basis_input4_mem4 ( in , mem , mem_inv , out , - p0 ) ; +module cby_2__1__mux_2level_basis_input4_mem4 ( in , mem , mem_inv , out ) ; input [0:3] in ; input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; -input p0 ; + +wire [0:0] out_inv ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; -scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( p0 ) , + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; +scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -300,12 +304,20 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; -scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; +scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( ZINV_1377_17 ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; +sky130_fd_sc_hd__clkinv_1 ZINV_1377_inst_1023 ( .A ( in[2] ) , + .Y ( ZINV_1377_17 ) ) ; endmodule @@ -315,12 +327,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -337,7 +355,7 @@ sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ; sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , .Y ( data_inv[2] ) ) ; sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ; -sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ; +sky130_fd_sc_hd__clkinv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ; sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ; sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , .Y ( data_inv[3] ) ) ; @@ -357,20 +375,20 @@ sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ; sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , .Y ( data_inv[2] ) ) ; sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ; -sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ; +sky130_fd_sc_hd__clkinv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ; sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ; sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , .Y ( data_inv[3] ) ) ; endmodule -module cby_2__1__mux_2level_size10 ( in , sram , sram_inv , out , p0 ) ; +module cby_2__1__mux_2level_size10 ( in , sram , sram_inv , out ) ; input [0:9] in ; input [0:3] sram ; input [0:3] sram_inv ; output [0:0] out ; -input p0 ; +wire [0:0] const1_0_const1 ; wire [0:3] local_encoder2to4_0_data ; wire [0:3] local_encoder2to4_0_data_inv ; wire [0:3] local_encoder2to4_1_data ; @@ -381,7 +399,7 @@ wire [0:0] mux_2level_basis_input4_mem4_1_out ; wire [0:0] mux_2level_basis_input4_mem4_2_out ; sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_1_0_ ( - .A ( mux_2level_basis_input4_mem4_2_out[0] ) , .X ( net_net_95 ) ) ; + .A ( mux_2level_basis_input4_mem4_2_out[0] ) , .X ( out[0] ) ) ; cby_2__1__local_encoder2to4_32 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , .data ( local_encoder2to4_0_data ) , .data_inv ( local_encoder2to4_0_data_inv ) ) ; @@ -399,15 +417,14 @@ cby_2__1__mux_2level_basis_input4_mem4_58 mux_l1_in_1_ ( .in ( in[4:7] ) , cby_2__1__mux_2level_basis_input4_mem4 mux_l2_in_0_ ( .in ( { mux_2level_basis_input4_mem4_0_out[0] , mux_2level_basis_input4_mem4_1_out[0] , - mux_2level_basis_input2_mem2_0_out[0] , SYNOPSYS_UNCONNECTED_1 } ) , + mux_2level_basis_input2_mem2_0_out[0] , const1_0_const1[0] } ) , .mem ( local_encoder2to4_1_data ) , .mem_inv ( local_encoder2to4_1_data_inv ) , - .out ( mux_2level_basis_input4_mem4_2_out ) , .p0 ( p0 ) ) ; + .out ( mux_2level_basis_input4_mem4_2_out ) ) ; cby_2__1__mux_2level_basis_input2_mem2 mux_l1_in_2_ ( .in ( in[8:9] ) , .mem ( local_encoder2to4_0_data[0:1] ) , .mem_inv ( local_encoder2to4_0_data_inv[0:1] ) , .out ( mux_2level_basis_input2_mem2_0_out ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_95 ( .A ( net_net_95 ) , .X ( out[0] ) ) ; endmodule @@ -417,26 +434,34 @@ input [0:1] mem ; input [0:1] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule -module cby_2__1__mux_2level_basis_input4_mem4_56 ( in , mem , mem_inv , out , - p0 ) ; +module cby_2__1__mux_2level_basis_input4_mem4_56 ( in , mem , mem_inv , out ) ; input [0:3] in ; input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; -input p0 ; + +wire [0:0] out_inv ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; -scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( p0 ) , + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; +scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -446,12 +471,19 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; -scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; +scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( ZINV_4_16 ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; +sky130_fd_sc_hd__clkinv_1 ZINV_4_inst_1004 ( .A ( in[3] ) , .Y ( ZINV_4_16 ) ) ; endmodule @@ -461,12 +493,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -483,7 +521,7 @@ sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ; sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , .Y ( data_inv[2] ) ) ; sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ; -sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ; +sky130_fd_sc_hd__clkinv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ; sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ; sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , .Y ( data_inv[3] ) ) ; @@ -503,20 +541,20 @@ sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ; sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , .Y ( data_inv[2] ) ) ; sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ; -sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ; +sky130_fd_sc_hd__clkinv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ; sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ; sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , .Y ( data_inv[3] ) ) ; endmodule -module cby_2__1__mux_2level_size10_6 ( in , sram , sram_inv , out , p0 ) ; +module cby_2__1__mux_2level_size10_6 ( in , sram , sram_inv , out ) ; input [0:9] in ; input [0:3] sram ; input [0:3] sram_inv ; output [0:0] out ; -input p0 ; +wire [0:0] const1_0_const1 ; wire [0:3] local_encoder2to4_0_data ; wire [0:3] local_encoder2to4_0_data_inv ; wire [0:3] local_encoder2to4_1_data ; @@ -527,7 +565,7 @@ wire [0:0] mux_2level_basis_input4_mem4_1_out ; wire [0:0] mux_2level_basis_input4_mem4_2_out ; sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_1_0_ ( - .A ( mux_2level_basis_input4_mem4_2_out[0] ) , .X ( net_net_94 ) ) ; + .A ( mux_2level_basis_input4_mem4_2_out[0] ) , .X ( out[0] ) ) ; cby_2__1__local_encoder2to4_30 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , .data ( local_encoder2to4_0_data ) , .data_inv ( local_encoder2to4_0_data_inv ) ) ; @@ -545,15 +583,14 @@ cby_2__1__mux_2level_basis_input4_mem4_55 mux_l1_in_1_ ( .in ( in[4:7] ) , cby_2__1__mux_2level_basis_input4_mem4_56 mux_l2_in_0_ ( .in ( { mux_2level_basis_input4_mem4_0_out[0] , mux_2level_basis_input4_mem4_1_out[0] , - mux_2level_basis_input2_mem2_0_out[0] , SYNOPSYS_UNCONNECTED_1 } ) , + mux_2level_basis_input2_mem2_0_out[0] , const1_0_const1[0] } ) , .mem ( local_encoder2to4_1_data ) , .mem_inv ( local_encoder2to4_1_data_inv ) , - .out ( mux_2level_basis_input4_mem4_2_out ) , .p0 ( p0 ) ) ; + .out ( mux_2level_basis_input4_mem4_2_out ) ) ; cby_2__1__mux_2level_basis_input2_mem2_6 mux_l1_in_2_ ( .in ( in[8:9] ) , .mem ( local_encoder2to4_0_data[0:1] ) , .mem_inv ( local_encoder2to4_0_data_inv[0:1] ) , .out ( mux_2level_basis_input2_mem2_0_out ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_94 ( .A ( net_net_94 ) , .X ( out[0] ) ) ; endmodule @@ -563,26 +600,34 @@ input [0:1] mem ; input [0:1] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule -module cby_2__1__mux_2level_basis_input4_mem4_53 ( in , mem , mem_inv , out , - p0 ) ; +module cby_2__1__mux_2level_basis_input4_mem4_53 ( in , mem , mem_inv , out ) ; input [0:3] in ; input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; -input p0 ; + +wire [0:0] out_inv ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; -scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( p0 ) , + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; +scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -592,12 +637,20 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; -scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; +scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( ZINV_24_11 ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; +sky130_fd_sc_hd__clkinv_1 ZINV_24_inst_961 ( .A ( in[2] ) , + .Y ( ZINV_24_11 ) ) ; endmodule @@ -607,12 +660,19 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; -scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , +wire [0:0] out_inv ; + +scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( ZINV_17_3 ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; +sky130_fd_sc_hd__clkinv_1 ZINV_17_inst_910 ( .A ( in[0] ) , .Y ( ZINV_17_3 ) ) ; endmodule @@ -629,7 +689,7 @@ sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ; sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , .Y ( data_inv[2] ) ) ; sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ; -sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ; +sky130_fd_sc_hd__clkinv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ; sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ; sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , .Y ( data_inv[3] ) ) ; @@ -649,20 +709,20 @@ sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ; sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , .Y ( data_inv[2] ) ) ; sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ; -sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ; +sky130_fd_sc_hd__clkinv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ; sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ; sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , .Y ( data_inv[3] ) ) ; endmodule -module cby_2__1__mux_2level_size10_5 ( in , sram , sram_inv , out , p0 ) ; +module cby_2__1__mux_2level_size10_5 ( in , sram , sram_inv , out ) ; input [0:9] in ; input [0:3] sram ; input [0:3] sram_inv ; output [0:0] out ; -input p0 ; +wire [0:0] const1_0_const1 ; wire [0:3] local_encoder2to4_0_data ; wire [0:3] local_encoder2to4_0_data_inv ; wire [0:3] local_encoder2to4_1_data ; @@ -673,7 +733,7 @@ wire [0:0] mux_2level_basis_input4_mem4_1_out ; wire [0:0] mux_2level_basis_input4_mem4_2_out ; sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_1_0_ ( - .A ( mux_2level_basis_input4_mem4_2_out[0] ) , .X ( aps_rename_509_ ) ) ; + .A ( mux_2level_basis_input4_mem4_2_out[0] ) , .X ( out[0] ) ) ; cby_2__1__local_encoder2to4_28 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , .data ( local_encoder2to4_0_data ) , .data_inv ( local_encoder2to4_0_data_inv ) ) ; @@ -691,17 +751,14 @@ cby_2__1__mux_2level_basis_input4_mem4_52 mux_l1_in_1_ ( .in ( in[4:7] ) , cby_2__1__mux_2level_basis_input4_mem4_53 mux_l2_in_0_ ( .in ( { mux_2level_basis_input4_mem4_0_out[0] , mux_2level_basis_input4_mem4_1_out[0] , - mux_2level_basis_input2_mem2_0_out[0] , SYNOPSYS_UNCONNECTED_1 } ) , + mux_2level_basis_input2_mem2_0_out[0] , const1_0_const1[0] } ) , .mem ( local_encoder2to4_1_data ) , .mem_inv ( local_encoder2to4_1_data_inv ) , - .out ( mux_2level_basis_input4_mem4_2_out ) , .p0 ( p0 ) ) ; + .out ( mux_2level_basis_input4_mem4_2_out ) ) ; cby_2__1__mux_2level_basis_input2_mem2_5 mux_l1_in_2_ ( .in ( in[8:9] ) , .mem ( local_encoder2to4_0_data[0:1] ) , .mem_inv ( local_encoder2to4_0_data_inv[0:1] ) , .out ( mux_2level_basis_input2_mem2_0_out ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_92 ( .A ( BUF_net_93 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_93 ( .A ( aps_rename_509_ ) , - .Y ( BUF_net_93 ) ) ; endmodule @@ -711,26 +768,34 @@ input [0:1] mem ; input [0:1] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule -module cby_2__1__mux_2level_basis_input4_mem4_50 ( in , mem , mem_inv , out , - p0 ) ; +module cby_2__1__mux_2level_basis_input4_mem4_50 ( in , mem , mem_inv , out ) ; input [0:3] in ; input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; -input p0 ; + +wire [0:0] out_inv ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; -scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( p0 ) , + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; +scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -740,12 +805,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -755,12 +826,20 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; -scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , +wire [0:0] out_inv ; + +scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( ZINV_10_0 ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; -scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; +scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( ZINV_10_1 ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; +sky130_fd_sc_hd__clkinv_1 ZINV_10_inst_883 ( .A ( in[1] ) , .Y ( ZINV_10_0 ) ) ; +sky130_fd_sc_hd__clkinv_1 ZINV_10_inst_895 ( .A ( in[3] ) , .Y ( ZINV_10_1 ) ) ; endmodule @@ -777,7 +856,7 @@ sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ; sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , .Y ( data_inv[2] ) ) ; sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ; -sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ; +sky130_fd_sc_hd__clkinv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ; sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ; sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , .Y ( data_inv[3] ) ) ; @@ -797,20 +876,20 @@ sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ; sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , .Y ( data_inv[2] ) ) ; sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ; -sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ; +sky130_fd_sc_hd__clkinv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ; sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ; sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , .Y ( data_inv[3] ) ) ; endmodule -module cby_2__1__mux_2level_size10_4 ( in , sram , sram_inv , out , p0 ) ; +module cby_2__1__mux_2level_size10_4 ( in , sram , sram_inv , out ) ; input [0:9] in ; input [0:3] sram ; input [0:3] sram_inv ; output [0:0] out ; -input p0 ; +wire [0:0] const1_0_const1 ; wire [0:3] local_encoder2to4_0_data ; wire [0:3] local_encoder2to4_0_data_inv ; wire [0:3] local_encoder2to4_1_data ; @@ -820,7 +899,7 @@ wire [0:0] mux_2level_basis_input4_mem4_0_out ; wire [0:0] mux_2level_basis_input4_mem4_1_out ; wire [0:0] mux_2level_basis_input4_mem4_2_out ; -sky130_fd_sc_hd__bufbuf_16 sky130_fd_sc_hd__buf_1_0_ ( +sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_1_0_ ( .A ( mux_2level_basis_input4_mem4_2_out[0] ) , .X ( out[0] ) ) ; cby_2__1__local_encoder2to4_26 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , .data ( local_encoder2to4_0_data ) , @@ -839,10 +918,10 @@ cby_2__1__mux_2level_basis_input4_mem4_49 mux_l1_in_1_ ( .in ( in[4:7] ) , cby_2__1__mux_2level_basis_input4_mem4_50 mux_l2_in_0_ ( .in ( { mux_2level_basis_input4_mem4_0_out[0] , mux_2level_basis_input4_mem4_1_out[0] , - mux_2level_basis_input2_mem2_0_out[0] , SYNOPSYS_UNCONNECTED_1 } ) , + mux_2level_basis_input2_mem2_0_out[0] , const1_0_const1[0] } ) , .mem ( local_encoder2to4_1_data ) , .mem_inv ( local_encoder2to4_1_data_inv ) , - .out ( mux_2level_basis_input4_mem4_2_out ) , .p0 ( p0 ) ) ; + .out ( mux_2level_basis_input4_mem4_2_out ) ) ; cby_2__1__mux_2level_basis_input2_mem2_4 mux_l1_in_2_ ( .in ( in[8:9] ) , .mem ( local_encoder2to4_0_data[0:1] ) , .mem_inv ( local_encoder2to4_0_data_inv[0:1] ) , @@ -856,26 +935,35 @@ input [0:1] mem ; input [0:1] mem_inv ; output [0:0] out ; -scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , +wire [0:0] out_inv ; + +scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( ZINV_7_5 ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; +sky130_fd_sc_hd__clkinv_1 ZINV_7_inst_932 ( .A ( in[1] ) , .Y ( ZINV_7_5 ) ) ; endmodule -module cby_2__1__mux_2level_basis_input4_mem4_47 ( in , mem , mem_inv , out , - p0 ) ; +module cby_2__1__mux_2level_basis_input4_mem4_47 ( in , mem , mem_inv , out ) ; input [0:3] in ; input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; -input p0 ; + +wire [0:0] out_inv ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; -scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( p0 ) , + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; +scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -885,12 +973,19 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; -scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; +scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( ZINV_4_9 ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; +sky130_fd_sc_hd__clkinv_1 ZINV_4_inst_949 ( .A ( in[3] ) , .Y ( ZINV_4_9 ) ) ; endmodule @@ -900,12 +995,19 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; -scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , +wire [0:0] out_inv ; + +scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( ZINV_10_2 ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; +sky130_fd_sc_hd__clkinv_1 ZINV_10_inst_904 ( .A ( in[1] ) , .Y ( ZINV_10_2 ) ) ; endmodule @@ -922,7 +1024,7 @@ sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ; sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , .Y ( data_inv[2] ) ) ; sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ; -sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ; +sky130_fd_sc_hd__clkinv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ; sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ; sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , .Y ( data_inv[3] ) ) ; @@ -942,20 +1044,20 @@ sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ; sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , .Y ( data_inv[2] ) ) ; sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ; -sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ; +sky130_fd_sc_hd__clkinv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ; sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ; sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , .Y ( data_inv[3] ) ) ; endmodule -module cby_2__1__mux_2level_size10_3 ( in , sram , sram_inv , out , p0 ) ; +module cby_2__1__mux_2level_size10_3 ( in , sram , sram_inv , out ) ; input [0:9] in ; input [0:3] sram ; input [0:3] sram_inv ; output [0:0] out ; -input p0 ; +wire [0:0] const1_0_const1 ; wire [0:3] local_encoder2to4_0_data ; wire [0:3] local_encoder2to4_0_data_inv ; wire [0:3] local_encoder2to4_1_data ; @@ -965,7 +1067,7 @@ wire [0:0] mux_2level_basis_input4_mem4_0_out ; wire [0:0] mux_2level_basis_input4_mem4_1_out ; wire [0:0] mux_2level_basis_input4_mem4_2_out ; -sky130_fd_sc_hd__bufbuf_16 sky130_fd_sc_hd__buf_1_0_ ( +sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_1_0_ ( .A ( mux_2level_basis_input4_mem4_2_out[0] ) , .X ( out[0] ) ) ; cby_2__1__local_encoder2to4_24 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , .data ( local_encoder2to4_0_data ) , @@ -984,10 +1086,10 @@ cby_2__1__mux_2level_basis_input4_mem4_46 mux_l1_in_1_ ( .in ( in[4:7] ) , cby_2__1__mux_2level_basis_input4_mem4_47 mux_l2_in_0_ ( .in ( { mux_2level_basis_input4_mem4_0_out[0] , mux_2level_basis_input4_mem4_1_out[0] , - mux_2level_basis_input2_mem2_0_out[0] , SYNOPSYS_UNCONNECTED_1 } ) , + mux_2level_basis_input2_mem2_0_out[0] , const1_0_const1[0] } ) , .mem ( local_encoder2to4_1_data ) , .mem_inv ( local_encoder2to4_1_data_inv ) , - .out ( mux_2level_basis_input4_mem4_2_out ) , .p0 ( p0 ) ) ; + .out ( mux_2level_basis_input4_mem4_2_out ) ) ; cby_2__1__mux_2level_basis_input2_mem2_3 mux_l1_in_2_ ( .in ( in[8:9] ) , .mem ( local_encoder2to4_0_data[0:1] ) , .mem_inv ( local_encoder2to4_0_data_inv[0:1] ) , @@ -1001,26 +1103,36 @@ input [0:1] mem ; input [0:1] mem_inv ; output [0:0] out ; -scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , +wire [0:0] out_inv ; + +scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( ZINV_368_3 ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; +sky130_fd_sc_hd__clkinv_1 ZINV_368_inst_912 ( .A ( in[1] ) , + .Y ( ZINV_368_3 ) ) ; endmodule -module cby_2__1__mux_2level_basis_input4_mem4_44 ( in , mem , mem_inv , out , - p0 ) ; +module cby_2__1__mux_2level_basis_input4_mem4_44 ( in , mem , mem_inv , out ) ; input [0:3] in ; input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; -input p0 ; + +wire [0:0] out_inv ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; -scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( p0 ) , + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; +scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -1030,12 +1142,21 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; -scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , - .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; +scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( ZINV_200_17 ) , + .Q2 ( ZINV_4_10 ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , + .S0 ( mem[2] ) , .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; +sky130_fd_sc_hd__clkinv_1 ZINV_4_inst_952 ( .A ( in[3] ) , .Y ( ZINV_4_10 ) ) ; +sky130_fd_sc_hd__clkinv_1 ZINV_200_inst_1016 ( .A ( in[2] ) , + .Y ( ZINV_200_17 ) ) ; endmodule @@ -1045,12 +1166,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -1067,7 +1194,7 @@ sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ; sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , .Y ( data_inv[2] ) ) ; sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ; -sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ; +sky130_fd_sc_hd__clkinv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ; sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ; sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , .Y ( data_inv[3] ) ) ; @@ -1087,20 +1214,20 @@ sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ; sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , .Y ( data_inv[2] ) ) ; sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ; -sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ; +sky130_fd_sc_hd__clkinv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ; sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ; sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , .Y ( data_inv[3] ) ) ; endmodule -module cby_2__1__mux_2level_size10_2 ( in , sram , sram_inv , out , p0 ) ; +module cby_2__1__mux_2level_size10_2 ( in , sram , sram_inv , out ) ; input [0:9] in ; input [0:3] sram ; input [0:3] sram_inv ; output [0:0] out ; -input p0 ; +wire [0:0] const1_0_const1 ; wire [0:3] local_encoder2to4_0_data ; wire [0:3] local_encoder2to4_0_data_inv ; wire [0:3] local_encoder2to4_1_data ; @@ -1110,7 +1237,7 @@ wire [0:0] mux_2level_basis_input4_mem4_0_out ; wire [0:0] mux_2level_basis_input4_mem4_1_out ; wire [0:0] mux_2level_basis_input4_mem4_2_out ; -sky130_fd_sc_hd__bufbuf_16 sky130_fd_sc_hd__buf_1_0_ ( +sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_1_0_ ( .A ( mux_2level_basis_input4_mem4_2_out[0] ) , .X ( out[0] ) ) ; cby_2__1__local_encoder2to4_22 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , .data ( local_encoder2to4_0_data ) , @@ -1129,10 +1256,10 @@ cby_2__1__mux_2level_basis_input4_mem4_43 mux_l1_in_1_ ( .in ( in[4:7] ) , cby_2__1__mux_2level_basis_input4_mem4_44 mux_l2_in_0_ ( .in ( { mux_2level_basis_input4_mem4_0_out[0] , mux_2level_basis_input4_mem4_1_out[0] , - mux_2level_basis_input2_mem2_0_out[0] , SYNOPSYS_UNCONNECTED_1 } ) , + mux_2level_basis_input2_mem2_0_out[0] , const1_0_const1[0] } ) , .mem ( local_encoder2to4_1_data ) , .mem_inv ( local_encoder2to4_1_data_inv ) , - .out ( mux_2level_basis_input4_mem4_2_out ) , .p0 ( p0 ) ) ; + .out ( mux_2level_basis_input4_mem4_2_out ) ) ; cby_2__1__mux_2level_basis_input2_mem2_2 mux_l1_in_2_ ( .in ( in[8:9] ) , .mem ( local_encoder2to4_0_data[0:1] ) , .mem_inv ( local_encoder2to4_0_data_inv[0:1] ) , @@ -1146,26 +1273,34 @@ input [0:1] mem ; input [0:1] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule -module cby_2__1__mux_2level_basis_input4_mem4_41 ( in , mem , mem_inv , out , - p0 ) ; +module cby_2__1__mux_2level_basis_input4_mem4_41 ( in , mem , mem_inv , out ) ; input [0:3] in ; input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; -input p0 ; + +wire [0:0] out_inv ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; -scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( p0 ) , + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; +scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -1175,12 +1310,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -1190,12 +1331,20 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; -scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , +wire [0:0] out_inv ; + +scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( ZINV_4_0 ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; -scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; +scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( ZINV_14_0 ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; +sky130_fd_sc_hd__clkinv_1 ZINV_4_inst_878 ( .A ( in[0] ) , .Y ( ZINV_4_0 ) ) ; +sky130_fd_sc_hd__clkinv_1 ZINV_14_inst_886 ( .A ( in[2] ) , .Y ( ZINV_14_0 ) ) ; endmodule @@ -1212,7 +1361,7 @@ sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ; sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , .Y ( data_inv[2] ) ) ; sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ; -sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ; +sky130_fd_sc_hd__clkinv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ; sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ; sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , .Y ( data_inv[3] ) ) ; @@ -1232,20 +1381,20 @@ sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ; sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , .Y ( data_inv[2] ) ) ; sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ; -sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ; +sky130_fd_sc_hd__clkinv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ; sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ; sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , .Y ( data_inv[3] ) ) ; endmodule -module cby_2__1__mux_2level_size10_1 ( in , sram , sram_inv , out , p0 ) ; +module cby_2__1__mux_2level_size10_1 ( in , sram , sram_inv , out ) ; input [0:9] in ; input [0:3] sram ; input [0:3] sram_inv ; output [0:0] out ; -input p0 ; +wire [0:0] const1_0_const1 ; wire [0:3] local_encoder2to4_0_data ; wire [0:3] local_encoder2to4_0_data_inv ; wire [0:3] local_encoder2to4_1_data ; @@ -1255,7 +1404,7 @@ wire [0:0] mux_2level_basis_input4_mem4_0_out ; wire [0:0] mux_2level_basis_input4_mem4_1_out ; wire [0:0] mux_2level_basis_input4_mem4_2_out ; -sky130_fd_sc_hd__bufbuf_16 sky130_fd_sc_hd__buf_1_0_ ( +sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_1_0_ ( .A ( mux_2level_basis_input4_mem4_2_out[0] ) , .X ( out[0] ) ) ; cby_2__1__local_encoder2to4_20 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , .data ( local_encoder2to4_0_data ) , @@ -1274,10 +1423,10 @@ cby_2__1__mux_2level_basis_input4_mem4_40 mux_l1_in_1_ ( .in ( in[4:7] ) , cby_2__1__mux_2level_basis_input4_mem4_41 mux_l2_in_0_ ( .in ( { mux_2level_basis_input4_mem4_0_out[0] , mux_2level_basis_input4_mem4_1_out[0] , - mux_2level_basis_input2_mem2_0_out[0] , SYNOPSYS_UNCONNECTED_1 } ) , + mux_2level_basis_input2_mem2_0_out[0] , const1_0_const1[0] } ) , .mem ( local_encoder2to4_1_data ) , .mem_inv ( local_encoder2to4_1_data_inv ) , - .out ( mux_2level_basis_input4_mem4_2_out ) , .p0 ( p0 ) ) ; + .out ( mux_2level_basis_input4_mem4_2_out ) ) ; cby_2__1__mux_2level_basis_input2_mem2_1 mux_l1_in_2_ ( .in ( in[8:9] ) , .mem ( local_encoder2to4_0_data[0:1] ) , .mem_inv ( local_encoder2to4_0_data_inv[0:1] ) , @@ -1291,26 +1440,37 @@ input [0:1] mem ; input [0:1] mem_inv ; output [0:0] out ; -scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , - .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; +wire [0:0] out_inv ; + +scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( ZINV_4_14 ) , + .Q2 ( ZINV_810_17 ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , + .S0 ( mem[0] ) , .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; +sky130_fd_sc_hd__clkinv_1 ZINV_4_inst_978 ( .A ( in[0] ) , .Y ( ZINV_4_14 ) ) ; +sky130_fd_sc_hd__clkinv_1 ZINV_810_inst_1034 ( .A ( in[1] ) , + .Y ( ZINV_810_17 ) ) ; endmodule -module cby_2__1__mux_2level_basis_input4_mem4_38 ( in , mem , mem_inv , out , - p0 ) ; +module cby_2__1__mux_2level_basis_input4_mem4_38 ( in , mem , mem_inv , out ) ; input [0:3] in ; input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; -input p0 ; + +wire [0:0] out_inv ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; -scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( p0 ) , + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; +scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -1320,12 +1480,19 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; -scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , +wire [0:0] out_inv ; + +scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( ZINV_4_15 ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; +sky130_fd_sc_hd__clkinv_1 ZINV_4_inst_994 ( .A ( in[0] ) , .Y ( ZINV_4_15 ) ) ; endmodule @@ -1335,12 +1502,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -1357,7 +1530,7 @@ sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ; sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , .Y ( data_inv[2] ) ) ; sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ; -sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ; +sky130_fd_sc_hd__clkinv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ; sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ; sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , .Y ( data_inv[3] ) ) ; @@ -1377,20 +1550,20 @@ sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ; sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , .Y ( data_inv[2] ) ) ; sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ; -sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ; +sky130_fd_sc_hd__clkinv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ; sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ; sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , .Y ( data_inv[3] ) ) ; endmodule -module cby_2__1__mux_2level_size10_0 ( in , sram , sram_inv , out , p0 ) ; +module cby_2__1__mux_2level_size10_0 ( in , sram , sram_inv , out ) ; input [0:9] in ; input [0:3] sram ; input [0:3] sram_inv ; output [0:0] out ; -input p0 ; +wire [0:0] const1_0_const1 ; wire [0:3] local_encoder2to4_0_data ; wire [0:3] local_encoder2to4_0_data_inv ; wire [0:3] local_encoder2to4_1_data ; @@ -1400,7 +1573,7 @@ wire [0:0] mux_2level_basis_input4_mem4_0_out ; wire [0:0] mux_2level_basis_input4_mem4_1_out ; wire [0:0] mux_2level_basis_input4_mem4_2_out ; -sky130_fd_sc_hd__bufbuf_16 sky130_fd_sc_hd__buf_1_0_ ( +sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_1_0_ ( .A ( mux_2level_basis_input4_mem4_2_out[0] ) , .X ( out[0] ) ) ; cby_2__1__local_encoder2to4_18 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , .data ( local_encoder2to4_0_data ) , @@ -1419,10 +1592,10 @@ cby_2__1__mux_2level_basis_input4_mem4_37 mux_l1_in_1_ ( .in ( in[4:7] ) , cby_2__1__mux_2level_basis_input4_mem4_38 mux_l2_in_0_ ( .in ( { mux_2level_basis_input4_mem4_0_out[0] , mux_2level_basis_input4_mem4_1_out[0] , - mux_2level_basis_input2_mem2_0_out[0] , SYNOPSYS_UNCONNECTED_1 } ) , + mux_2level_basis_input2_mem2_0_out[0] , const1_0_const1[0] } ) , .mem ( local_encoder2to4_1_data ) , .mem_inv ( local_encoder2to4_1_data_inv ) , - .out ( mux_2level_basis_input4_mem4_2_out ) , .p0 ( p0 ) ) ; + .out ( mux_2level_basis_input4_mem4_2_out ) ) ; cby_2__1__mux_2level_basis_input2_mem2_0 mux_l1_in_2_ ( .in ( in[8:9] ) , .mem ( local_encoder2to4_0_data[0:1] ) , .mem_inv ( local_encoder2to4_0_data_inv[0:1] ) , @@ -1438,6 +1611,8 @@ input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; +assign ccff_tail[0] = mem_out[3] ; + sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , @@ -1446,7 +1621,6 @@ sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__buf_1 FTB_9__8 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -1458,6 +1632,8 @@ input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; +assign ccff_tail[0] = mem_out[3] ; + sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , @@ -1466,7 +1642,6 @@ sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__buf_1 FTB_8__7 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -1478,6 +1653,8 @@ input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; +assign ccff_tail[0] = mem_out[3] ; + sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , @@ -1486,7 +1663,6 @@ sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__buf_1 FTB_7__6 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -1498,6 +1674,8 @@ input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; +assign ccff_tail[0] = mem_out[3] ; + sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , @@ -1506,7 +1684,6 @@ sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__buf_1 FTB_6__5 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -1518,6 +1695,8 @@ input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; +assign ccff_tail[0] = mem_out[3] ; + sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , @@ -1526,7 +1705,6 @@ sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__buf_1 FTB_5__4 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -1538,6 +1716,8 @@ input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; +assign ccff_tail[0] = mem_out[3] ; + sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , @@ -1546,7 +1726,6 @@ sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__buf_1 FTB_4__3 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -1558,6 +1737,8 @@ input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; +assign ccff_tail[0] = mem_out[3] ; + sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , @@ -1566,7 +1747,6 @@ sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__buf_1 FTB_3__2 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -1578,6 +1758,8 @@ input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; +assign ccff_tail[0] = mem_out[3] ; + sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , @@ -1586,7 +1768,6 @@ sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__buf_1 FTB_2__1 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -1598,7 +1779,9 @@ input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( copt_net_106 ) , +assign ccff_tail[0] = mem_out[3] ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ropt_net_6 ) , .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; @@ -1606,44 +1789,31 @@ sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__buf_1 FTB_1__0 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1346 ( .A ( copt_net_117 ) , - .X ( copt_net_106 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1347 ( .A ( ccff_head[0] ) , - .X ( copt_net_107 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1348 ( .A ( copt_net_107 ) , - .X ( copt_net_108 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1349 ( .A ( ropt_net_121 ) , - .X ( copt_net_109 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1350 ( .A ( copt_net_108 ) , - .X ( copt_net_110 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 copt_h_inst_1357 ( .A ( ropt_net_119 ) , - .X ( copt_net_117 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1358 ( .A ( copt_net_109 ) , - .X ( ropt_net_118 ) ) ; -sky130_fd_sc_hd__buf_2 ropt_h_inst_1359 ( .A ( ropt_net_118 ) , - .X ( ropt_net_119 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1360 ( .A ( copt_net_110 ) , - .X ( ropt_net_120 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1361 ( .A ( ropt_net_120 ) , - .X ( ropt_net_121 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1044 ( .A ( ccff_head[0] ) , + .X ( ropt_net_5 ) ) ; +sky130_fd_sc_hd__clkbuf_2 ropt_h_inst_1045 ( .A ( ropt_net_5 ) , + .X ( ropt_net_6 ) ) ; endmodule -module cby_2__1__mux_2level_basis_input4_mem4_35 ( in , mem , mem_inv , out , - p0 ) ; +module cby_2__1__mux_2level_basis_input4_mem4_35 ( in , mem , mem_inv , out ) ; input [0:3] in ; input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; -input p0 ; + +wire [0:0] out_inv ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; -scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( p0 ) , + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; +scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -1653,12 +1823,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -1668,12 +1844,20 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; -scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; +scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( ZINV_11_12 ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; +sky130_fd_sc_hd__clkinv_1 ZINV_11_inst_968 ( .A ( in[2] ) , + .Y ( ZINV_11_12 ) ) ; endmodule @@ -1683,12 +1867,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -1705,7 +1895,7 @@ sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ; sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , .Y ( data_inv[2] ) ) ; sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ; -sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ; +sky130_fd_sc_hd__clkinv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ; sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ; sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , .Y ( data_inv[3] ) ) ; @@ -1725,20 +1915,20 @@ sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ; sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , .Y ( data_inv[2] ) ) ; sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ; -sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ; +sky130_fd_sc_hd__clkinv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ; sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ; sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , .Y ( data_inv[3] ) ) ; endmodule -module cby_2__1__mux_2level_size12 ( in , sram , sram_inv , out , p0 ) ; +module cby_2__1__mux_2level_size12 ( in , sram , sram_inv , out ) ; input [0:11] in ; input [0:3] sram ; input [0:3] sram_inv ; output [0:0] out ; -input p0 ; +wire [0:0] const1_0_const1 ; wire [0:3] local_encoder2to4_0_data ; wire [0:3] local_encoder2to4_0_data_inv ; wire [0:3] local_encoder2to4_1_data ; @@ -1749,7 +1939,7 @@ wire [0:0] mux_2level_basis_input4_mem4_2_out ; wire [0:0] mux_2level_basis_input4_mem4_3_out ; sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_1_0_ ( - .A ( mux_2level_basis_input4_mem4_3_out[0] ) , .X ( aps_rename_508_ ) ) ; + .A ( mux_2level_basis_input4_mem4_3_out[0] ) , .X ( out[0] ) ) ; cby_2__1__local_encoder2to4_16 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , .data ( local_encoder2to4_0_data ) , .data_inv ( local_encoder2to4_0_data_inv ) ) ; @@ -1771,30 +1961,31 @@ cby_2__1__mux_2level_basis_input4_mem4_34 mux_l1_in_2_ ( .in ( in[8:11] ) , cby_2__1__mux_2level_basis_input4_mem4_35 mux_l2_in_0_ ( .in ( { mux_2level_basis_input4_mem4_0_out[0] , mux_2level_basis_input4_mem4_1_out[0] , - mux_2level_basis_input4_mem4_2_out[0] , SYNOPSYS_UNCONNECTED_1 } ) , + mux_2level_basis_input4_mem4_2_out[0] , const1_0_const1[0] } ) , .mem ( local_encoder2to4_1_data ) , .mem_inv ( local_encoder2to4_1_data_inv ) , - .out ( mux_2level_basis_input4_mem4_3_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_90 ( .A ( BUF_net_91 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_91 ( .A ( aps_rename_508_ ) , - .Y ( BUF_net_91 ) ) ; + .out ( mux_2level_basis_input4_mem4_3_out ) ) ; endmodule -module cby_2__1__mux_2level_basis_input4_mem4_31 ( in , mem , mem_inv , out , - p0 ) ; +module cby_2__1__mux_2level_basis_input4_mem4_31 ( in , mem , mem_inv , out ) ; input [0:3] in ; input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; -input p0 ; + +wire [0:0] out_inv ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; -scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( p0 ) , + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; +scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -1804,12 +1995,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -1819,12 +2016,20 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; -scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , +wire [0:0] out_inv ; + +scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( ZINV_7_4 ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; -scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; +scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( ZINV_7_6 ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; +sky130_fd_sc_hd__clkinv_1 ZINV_7_inst_922 ( .A ( in[0] ) , .Y ( ZINV_7_4 ) ) ; +sky130_fd_sc_hd__clkinv_1 ZINV_7_inst_935 ( .A ( in[2] ) , .Y ( ZINV_7_6 ) ) ; endmodule @@ -1834,12 +2039,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -1856,7 +2067,7 @@ sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ; sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , .Y ( data_inv[2] ) ) ; sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ; -sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ; +sky130_fd_sc_hd__clkinv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ; sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ; sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , .Y ( data_inv[3] ) ) ; @@ -1876,20 +2087,20 @@ sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ; sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , .Y ( data_inv[2] ) ) ; sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ; -sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ; +sky130_fd_sc_hd__clkinv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ; sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ; sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , .Y ( data_inv[3] ) ) ; endmodule -module cby_2__1__mux_2level_size12_7 ( in , sram , sram_inv , out , p0 ) ; +module cby_2__1__mux_2level_size12_7 ( in , sram , sram_inv , out ) ; input [0:11] in ; input [0:3] sram ; input [0:3] sram_inv ; output [0:0] out ; -input p0 ; +wire [0:0] const1_0_const1 ; wire [0:3] local_encoder2to4_0_data ; wire [0:3] local_encoder2to4_0_data_inv ; wire [0:3] local_encoder2to4_1_data ; @@ -1899,7 +2110,7 @@ wire [0:0] mux_2level_basis_input4_mem4_1_out ; wire [0:0] mux_2level_basis_input4_mem4_2_out ; wire [0:0] mux_2level_basis_input4_mem4_3_out ; -sky130_fd_sc_hd__bufbuf_16 sky130_fd_sc_hd__buf_1_0_ ( +sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_1_0_ ( .A ( mux_2level_basis_input4_mem4_3_out[0] ) , .X ( out[0] ) ) ; cby_2__1__local_encoder2to4_14 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , .data ( local_encoder2to4_0_data ) , @@ -1922,27 +2133,31 @@ cby_2__1__mux_2level_basis_input4_mem4_30 mux_l1_in_2_ ( .in ( in[8:11] ) , cby_2__1__mux_2level_basis_input4_mem4_31 mux_l2_in_0_ ( .in ( { mux_2level_basis_input4_mem4_0_out[0] , mux_2level_basis_input4_mem4_1_out[0] , - mux_2level_basis_input4_mem4_2_out[0] , SYNOPSYS_UNCONNECTED_1 } ) , + mux_2level_basis_input4_mem4_2_out[0] , const1_0_const1[0] } ) , .mem ( local_encoder2to4_1_data ) , .mem_inv ( local_encoder2to4_1_data_inv ) , - .out ( mux_2level_basis_input4_mem4_3_out ) , .p0 ( p0 ) ) ; + .out ( mux_2level_basis_input4_mem4_3_out ) ) ; endmodule -module cby_2__1__mux_2level_basis_input4_mem4_27 ( in , mem , mem_inv , out , - p0 ) ; +module cby_2__1__mux_2level_basis_input4_mem4_27 ( in , mem , mem_inv , out ) ; input [0:3] in ; input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; -input p0 ; + +wire [0:0] out_inv ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; -scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( p0 ) , + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; +scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -1952,12 +2167,19 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; -scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , +wire [0:0] out_inv ; + +scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( ZINV_7_3 ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; +sky130_fd_sc_hd__clkinv_1 ZINV_7_inst_919 ( .A ( in[0] ) , .Y ( ZINV_7_3 ) ) ; endmodule @@ -1967,12 +2189,19 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; -scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , +wire [0:0] out_inv ; + +scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( ZINV_4_3 ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; +sky130_fd_sc_hd__clkinv_1 ZINV_4_inst_916 ( .A ( in[0] ) , .Y ( ZINV_4_3 ) ) ; endmodule @@ -1982,12 +2211,19 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; -scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , +wire [0:0] out_inv ; + +scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( ZINV_10_3 ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; +sky130_fd_sc_hd__clkinv_1 ZINV_10_inst_907 ( .A ( in[0] ) , .Y ( ZINV_10_3 ) ) ; endmodule @@ -2004,7 +2240,7 @@ sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ; sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , .Y ( data_inv[2] ) ) ; sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ; -sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ; +sky130_fd_sc_hd__clkinv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ; sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ; sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , .Y ( data_inv[3] ) ) ; @@ -2024,20 +2260,20 @@ sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ; sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , .Y ( data_inv[2] ) ) ; sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ; -sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ; +sky130_fd_sc_hd__clkinv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ; sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ; sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , .Y ( data_inv[3] ) ) ; endmodule -module cby_2__1__mux_2level_size12_6 ( in , sram , sram_inv , out , p0 ) ; +module cby_2__1__mux_2level_size12_6 ( in , sram , sram_inv , out ) ; input [0:11] in ; input [0:3] sram ; input [0:3] sram_inv ; output [0:0] out ; -input p0 ; +wire [0:0] const1_0_const1 ; wire [0:3] local_encoder2to4_0_data ; wire [0:3] local_encoder2to4_0_data_inv ; wire [0:3] local_encoder2to4_1_data ; @@ -2048,7 +2284,7 @@ wire [0:0] mux_2level_basis_input4_mem4_2_out ; wire [0:0] mux_2level_basis_input4_mem4_3_out ; sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_1_0_ ( - .A ( mux_2level_basis_input4_mem4_3_out[0] ) , .X ( aps_rename_507_ ) ) ; + .A ( mux_2level_basis_input4_mem4_3_out[0] ) , .X ( out[0] ) ) ; cby_2__1__local_encoder2to4_12 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , .data ( local_encoder2to4_0_data ) , .data_inv ( local_encoder2to4_0_data_inv ) ) ; @@ -2070,30 +2306,31 @@ cby_2__1__mux_2level_basis_input4_mem4_26 mux_l1_in_2_ ( .in ( in[8:11] ) , cby_2__1__mux_2level_basis_input4_mem4_27 mux_l2_in_0_ ( .in ( { mux_2level_basis_input4_mem4_0_out[0] , mux_2level_basis_input4_mem4_1_out[0] , - mux_2level_basis_input4_mem4_2_out[0] , SYNOPSYS_UNCONNECTED_1 } ) , + mux_2level_basis_input4_mem4_2_out[0] , const1_0_const1[0] } ) , .mem ( local_encoder2to4_1_data ) , .mem_inv ( local_encoder2to4_1_data_inv ) , - .out ( mux_2level_basis_input4_mem4_3_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_6 BINV_R_88 ( .A ( BUF_net_89 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_89 ( .A ( aps_rename_507_ ) , - .Y ( BUF_net_89 ) ) ; + .out ( mux_2level_basis_input4_mem4_3_out ) ) ; endmodule -module cby_2__1__mux_2level_basis_input4_mem4_23 ( in , mem , mem_inv , out , - p0 ) ; +module cby_2__1__mux_2level_basis_input4_mem4_23 ( in , mem , mem_inv , out ) ; input [0:3] in ; input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; -input p0 ; + +wire [0:0] out_inv ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; -scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( p0 ) , + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; +scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -2103,12 +2340,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -2118,12 +2361,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -2133,12 +2382,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -2155,7 +2410,7 @@ sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ; sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , .Y ( data_inv[2] ) ) ; sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ; -sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ; +sky130_fd_sc_hd__clkinv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ; sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ; sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , .Y ( data_inv[3] ) ) ; @@ -2175,20 +2430,20 @@ sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ; sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , .Y ( data_inv[2] ) ) ; sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ; -sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ; +sky130_fd_sc_hd__clkinv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ; sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ; sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , .Y ( data_inv[3] ) ) ; endmodule -module cby_2__1__mux_2level_size12_5 ( in , sram , sram_inv , out , p0 ) ; +module cby_2__1__mux_2level_size12_5 ( in , sram , sram_inv , out ) ; input [0:11] in ; input [0:3] sram ; input [0:3] sram_inv ; output [0:0] out ; -input p0 ; +wire [0:0] const1_0_const1 ; wire [0:3] local_encoder2to4_0_data ; wire [0:3] local_encoder2to4_0_data_inv ; wire [0:3] local_encoder2to4_1_data ; @@ -2199,7 +2454,7 @@ wire [0:0] mux_2level_basis_input4_mem4_2_out ; wire [0:0] mux_2level_basis_input4_mem4_3_out ; sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_1_0_ ( - .A ( mux_2level_basis_input4_mem4_3_out[0] ) , .X ( aps_rename_506_ ) ) ; + .A ( mux_2level_basis_input4_mem4_3_out[0] ) , .X ( out[0] ) ) ; cby_2__1__local_encoder2to4_10 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , .data ( local_encoder2to4_0_data ) , .data_inv ( local_encoder2to4_0_data_inv ) ) ; @@ -2221,30 +2476,31 @@ cby_2__1__mux_2level_basis_input4_mem4_22 mux_l1_in_2_ ( .in ( in[8:11] ) , cby_2__1__mux_2level_basis_input4_mem4_23 mux_l2_in_0_ ( .in ( { mux_2level_basis_input4_mem4_0_out[0] , mux_2level_basis_input4_mem4_1_out[0] , - mux_2level_basis_input4_mem4_2_out[0] , SYNOPSYS_UNCONNECTED_1 } ) , + mux_2level_basis_input4_mem4_2_out[0] , const1_0_const1[0] } ) , .mem ( local_encoder2to4_1_data ) , .mem_inv ( local_encoder2to4_1_data_inv ) , - .out ( mux_2level_basis_input4_mem4_3_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_86 ( .A ( BUF_net_87 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_87 ( .A ( aps_rename_506_ ) , - .Y ( BUF_net_87 ) ) ; + .out ( mux_2level_basis_input4_mem4_3_out ) ) ; endmodule -module cby_2__1__mux_2level_basis_input4_mem4_19 ( in , mem , mem_inv , out , - p0 ) ; +module cby_2__1__mux_2level_basis_input4_mem4_19 ( in , mem , mem_inv , out ) ; input [0:3] in ; input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; -input p0 ; + +wire [0:0] out_inv ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; -scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( p0 ) , + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; +scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -2254,12 +2510,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -2269,12 +2531,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -2284,12 +2552,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -2306,7 +2580,7 @@ sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ; sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , .Y ( data_inv[2] ) ) ; sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ; -sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ; +sky130_fd_sc_hd__clkinv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ; sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ; sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , .Y ( data_inv[3] ) ) ; @@ -2326,20 +2600,20 @@ sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ; sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , .Y ( data_inv[2] ) ) ; sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ; -sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ; +sky130_fd_sc_hd__clkinv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ; sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ; sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , .Y ( data_inv[3] ) ) ; endmodule -module cby_2__1__mux_2level_size12_4 ( in , sram , sram_inv , out , p0 ) ; +module cby_2__1__mux_2level_size12_4 ( in , sram , sram_inv , out ) ; input [0:11] in ; input [0:3] sram ; input [0:3] sram_inv ; output [0:0] out ; -input p0 ; +wire [0:0] const1_0_const1 ; wire [0:3] local_encoder2to4_0_data ; wire [0:3] local_encoder2to4_0_data_inv ; wire [0:3] local_encoder2to4_1_data ; @@ -2350,7 +2624,7 @@ wire [0:0] mux_2level_basis_input4_mem4_2_out ; wire [0:0] mux_2level_basis_input4_mem4_3_out ; sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_1_0_ ( - .A ( mux_2level_basis_input4_mem4_3_out[0] ) , .X ( aps_rename_505_ ) ) ; + .A ( mux_2level_basis_input4_mem4_3_out[0] ) , .X ( out[0] ) ) ; cby_2__1__local_encoder2to4_8 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , .data ( local_encoder2to4_0_data ) , .data_inv ( local_encoder2to4_0_data_inv ) ) ; @@ -2372,30 +2646,31 @@ cby_2__1__mux_2level_basis_input4_mem4_18 mux_l1_in_2_ ( .in ( in[8:11] ) , cby_2__1__mux_2level_basis_input4_mem4_19 mux_l2_in_0_ ( .in ( { mux_2level_basis_input4_mem4_0_out[0] , mux_2level_basis_input4_mem4_1_out[0] , - mux_2level_basis_input4_mem4_2_out[0] , SYNOPSYS_UNCONNECTED_1 } ) , + mux_2level_basis_input4_mem4_2_out[0] , const1_0_const1[0] } ) , .mem ( local_encoder2to4_1_data ) , .mem_inv ( local_encoder2to4_1_data_inv ) , - .out ( mux_2level_basis_input4_mem4_3_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_84 ( .A ( BUF_net_85 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_85 ( .A ( aps_rename_505_ ) , - .Y ( BUF_net_85 ) ) ; + .out ( mux_2level_basis_input4_mem4_3_out ) ) ; endmodule -module cby_2__1__mux_2level_basis_input4_mem4_15 ( in , mem , mem_inv , out , - p0 ) ; +module cby_2__1__mux_2level_basis_input4_mem4_15 ( in , mem , mem_inv , out ) ; input [0:3] in ; input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; -input p0 ; + +wire [0:0] out_inv ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; -scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( p0 ) , + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; +scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -2405,12 +2680,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -2420,12 +2701,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -2435,12 +2722,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -2457,7 +2750,7 @@ sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ; sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , .Y ( data_inv[2] ) ) ; sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ; -sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ; +sky130_fd_sc_hd__clkinv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ; sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ; sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , .Y ( data_inv[3] ) ) ; @@ -2477,20 +2770,20 @@ sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ; sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , .Y ( data_inv[2] ) ) ; sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ; -sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ; +sky130_fd_sc_hd__clkinv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ; sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ; sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , .Y ( data_inv[3] ) ) ; endmodule -module cby_2__1__mux_2level_size12_3 ( in , sram , sram_inv , out , p0 ) ; +module cby_2__1__mux_2level_size12_3 ( in , sram , sram_inv , out ) ; input [0:11] in ; input [0:3] sram ; input [0:3] sram_inv ; output [0:0] out ; -input p0 ; +wire [0:0] const1_0_const1 ; wire [0:3] local_encoder2to4_0_data ; wire [0:3] local_encoder2to4_0_data_inv ; wire [0:3] local_encoder2to4_1_data ; @@ -2501,7 +2794,7 @@ wire [0:0] mux_2level_basis_input4_mem4_2_out ; wire [0:0] mux_2level_basis_input4_mem4_3_out ; sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_1_0_ ( - .A ( mux_2level_basis_input4_mem4_3_out[0] ) , .X ( net_net_83 ) ) ; + .A ( mux_2level_basis_input4_mem4_3_out[0] ) , .X ( out[0] ) ) ; cby_2__1__local_encoder2to4_6 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , .data ( local_encoder2to4_0_data ) , .data_inv ( local_encoder2to4_0_data_inv ) ) ; @@ -2523,28 +2816,31 @@ cby_2__1__mux_2level_basis_input4_mem4_14 mux_l1_in_2_ ( .in ( in[8:11] ) , cby_2__1__mux_2level_basis_input4_mem4_15 mux_l2_in_0_ ( .in ( { mux_2level_basis_input4_mem4_0_out[0] , mux_2level_basis_input4_mem4_1_out[0] , - mux_2level_basis_input4_mem4_2_out[0] , SYNOPSYS_UNCONNECTED_1 } ) , + mux_2level_basis_input4_mem4_2_out[0] , const1_0_const1[0] } ) , .mem ( local_encoder2to4_1_data ) , .mem_inv ( local_encoder2to4_1_data_inv ) , - .out ( mux_2level_basis_input4_mem4_3_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_83 ( .A ( net_net_83 ) , .X ( out[0] ) ) ; + .out ( mux_2level_basis_input4_mem4_3_out ) ) ; endmodule -module cby_2__1__mux_2level_basis_input4_mem4_11 ( in , mem , mem_inv , out , - p0 ) ; +module cby_2__1__mux_2level_basis_input4_mem4_11 ( in , mem , mem_inv , out ) ; input [0:3] in ; input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; -input p0 ; + +wire [0:0] out_inv ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; -scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( p0 ) , + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; +scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -2554,12 +2850,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -2569,12 +2871,21 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; -scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , +wire [0:0] out_inv ; + +scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( ZINV_7_7 ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; -scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; +scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( ZINV_11_13 ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; +sky130_fd_sc_hd__clkinv_1 ZINV_7_inst_939 ( .A ( in[1] ) , .Y ( ZINV_7_7 ) ) ; +sky130_fd_sc_hd__clkinv_1 ZINV_11_inst_971 ( .A ( in[3] ) , + .Y ( ZINV_11_13 ) ) ; endmodule @@ -2584,12 +2895,19 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; -scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , +wire [0:0] out_inv ; + +scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( ZINV_13_0 ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; +sky130_fd_sc_hd__clkinv_1 ZINV_13_inst_889 ( .A ( in[1] ) , .Y ( ZINV_13_0 ) ) ; endmodule @@ -2606,7 +2924,7 @@ sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ; sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , .Y ( data_inv[2] ) ) ; sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ; -sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ; +sky130_fd_sc_hd__clkinv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ; sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ; sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , .Y ( data_inv[3] ) ) ; @@ -2626,20 +2944,20 @@ sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ; sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , .Y ( data_inv[2] ) ) ; sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ; -sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ; +sky130_fd_sc_hd__clkinv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ; sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ; sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , .Y ( data_inv[3] ) ) ; endmodule -module cby_2__1__mux_2level_size12_2 ( in , sram , sram_inv , out , p0 ) ; +module cby_2__1__mux_2level_size12_2 ( in , sram , sram_inv , out ) ; input [0:11] in ; input [0:3] sram ; input [0:3] sram_inv ; output [0:0] out ; -input p0 ; +wire [0:0] const1_0_const1 ; wire [0:3] local_encoder2to4_0_data ; wire [0:3] local_encoder2to4_0_data_inv ; wire [0:3] local_encoder2to4_1_data ; @@ -2649,7 +2967,7 @@ wire [0:0] mux_2level_basis_input4_mem4_1_out ; wire [0:0] mux_2level_basis_input4_mem4_2_out ; wire [0:0] mux_2level_basis_input4_mem4_3_out ; -sky130_fd_sc_hd__bufbuf_16 sky130_fd_sc_hd__buf_1_0_ ( +sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_1_0_ ( .A ( mux_2level_basis_input4_mem4_3_out[0] ) , .X ( out[0] ) ) ; cby_2__1__local_encoder2to4_4 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , .data ( local_encoder2to4_0_data ) , @@ -2672,27 +2990,31 @@ cby_2__1__mux_2level_basis_input4_mem4_10 mux_l1_in_2_ ( .in ( in[8:11] ) , cby_2__1__mux_2level_basis_input4_mem4_11 mux_l2_in_0_ ( .in ( { mux_2level_basis_input4_mem4_0_out[0] , mux_2level_basis_input4_mem4_1_out[0] , - mux_2level_basis_input4_mem4_2_out[0] , SYNOPSYS_UNCONNECTED_1 } ) , + mux_2level_basis_input4_mem4_2_out[0] , const1_0_const1[0] } ) , .mem ( local_encoder2to4_1_data ) , .mem_inv ( local_encoder2to4_1_data_inv ) , - .out ( mux_2level_basis_input4_mem4_3_out ) , .p0 ( p0 ) ) ; + .out ( mux_2level_basis_input4_mem4_3_out ) ) ; endmodule -module cby_2__1__mux_2level_basis_input4_mem4_7 ( in , mem , mem_inv , out , - p0 ) ; +module cby_2__1__mux_2level_basis_input4_mem4_7 ( in , mem , mem_inv , out ) ; input [0:3] in ; input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; -input p0 ; + +wire [0:0] out_inv ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; -scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( p0 ) , + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; +scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -2702,12 +3024,22 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; -scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , +wire [0:0] out_inv ; + +scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( ZINV_11_14 ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; -scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; +scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( ZINV_191_1 ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; +sky130_fd_sc_hd__clkinv_1 ZINV_191_inst_898 ( .A ( in[3] ) , + .Y ( ZINV_191_1 ) ) ; +sky130_fd_sc_hd__clkinv_1 ZINV_11_inst_990 ( .A ( in[1] ) , + .Y ( ZINV_11_14 ) ) ; endmodule @@ -2717,12 +3049,19 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; -scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; +scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( ZINV_4_11 ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; +sky130_fd_sc_hd__clkinv_1 ZINV_4_inst_957 ( .A ( in[3] ) , .Y ( ZINV_4_11 ) ) ; endmodule @@ -2732,12 +3071,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -2754,7 +3099,7 @@ sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ; sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , .Y ( data_inv[2] ) ) ; sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ; -sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ; +sky130_fd_sc_hd__clkinv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ; sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ; sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , .Y ( data_inv[3] ) ) ; @@ -2774,20 +3119,20 @@ sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ; sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , .Y ( data_inv[2] ) ) ; sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ; -sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ; +sky130_fd_sc_hd__clkinv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ; sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ; sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , .Y ( data_inv[3] ) ) ; endmodule -module cby_2__1__mux_2level_size12_1 ( in , sram , sram_inv , out , p0 ) ; +module cby_2__1__mux_2level_size12_1 ( in , sram , sram_inv , out ) ; input [0:11] in ; input [0:3] sram ; input [0:3] sram_inv ; output [0:0] out ; -input p0 ; +wire [0:0] const1_0_const1 ; wire [0:3] local_encoder2to4_0_data ; wire [0:3] local_encoder2to4_0_data_inv ; wire [0:3] local_encoder2to4_1_data ; @@ -2797,7 +3142,7 @@ wire [0:0] mux_2level_basis_input4_mem4_1_out ; wire [0:0] mux_2level_basis_input4_mem4_2_out ; wire [0:0] mux_2level_basis_input4_mem4_3_out ; -sky130_fd_sc_hd__bufbuf_16 sky130_fd_sc_hd__buf_1_0_ ( +sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_1_0_ ( .A ( mux_2level_basis_input4_mem4_3_out[0] ) , .X ( out[0] ) ) ; cby_2__1__local_encoder2to4_2 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , .data ( local_encoder2to4_0_data ) , @@ -2820,27 +3165,31 @@ cby_2__1__mux_2level_basis_input4_mem4_6 mux_l1_in_2_ ( .in ( in[8:11] ) , cby_2__1__mux_2level_basis_input4_mem4_7 mux_l2_in_0_ ( .in ( { mux_2level_basis_input4_mem4_0_out[0] , mux_2level_basis_input4_mem4_1_out[0] , - mux_2level_basis_input4_mem4_2_out[0] , SYNOPSYS_UNCONNECTED_1 } ) , + mux_2level_basis_input4_mem4_2_out[0] , const1_0_const1[0] } ) , .mem ( local_encoder2to4_1_data ) , .mem_inv ( local_encoder2to4_1_data_inv ) , - .out ( mux_2level_basis_input4_mem4_3_out ) , .p0 ( p0 ) ) ; + .out ( mux_2level_basis_input4_mem4_3_out ) ) ; endmodule -module cby_2__1__mux_2level_basis_input4_mem4_3 ( in , mem , mem_inv , out , - p0 ) ; +module cby_2__1__mux_2level_basis_input4_mem4_3 ( in , mem , mem_inv , out ) ; input [0:3] in ; input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; -input p0 ; + +wire [0:0] out_inv ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; -scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( p0 ) , + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; +scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -2850,12 +3199,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -2865,12 +3220,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -2880,12 +3241,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -2902,7 +3269,7 @@ sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ; sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , .Y ( data_inv[2] ) ) ; sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ; -sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ; +sky130_fd_sc_hd__clkinv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ; sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ; sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , .Y ( data_inv[3] ) ) ; @@ -2922,20 +3289,20 @@ sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ; sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , .Y ( data_inv[2] ) ) ; sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ; -sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ; +sky130_fd_sc_hd__clkinv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ; sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ; sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , .Y ( data_inv[3] ) ) ; endmodule -module cby_2__1__mux_2level_size12_0 ( in , sram , sram_inv , out , p0 ) ; +module cby_2__1__mux_2level_size12_0 ( in , sram , sram_inv , out ) ; input [0:11] in ; input [0:3] sram ; input [0:3] sram_inv ; output [0:0] out ; -input p0 ; +wire [0:0] const1_0_const1 ; wire [0:3] local_encoder2to4_0_data ; wire [0:3] local_encoder2to4_0_data_inv ; wire [0:3] local_encoder2to4_1_data ; @@ -2946,7 +3313,7 @@ wire [0:0] mux_2level_basis_input4_mem4_2_out ; wire [0:0] mux_2level_basis_input4_mem4_3_out ; sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_1_0_ ( - .A ( mux_2level_basis_input4_mem4_3_out[0] ) , .X ( net_net_82 ) ) ; + .A ( mux_2level_basis_input4_mem4_3_out[0] ) , .X ( out[0] ) ) ; cby_2__1__local_encoder2to4_0 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , .data ( local_encoder2to4_0_data ) , .data_inv ( local_encoder2to4_0_data_inv ) ) ; @@ -2968,11 +3335,10 @@ cby_2__1__mux_2level_basis_input4_mem4_2 mux_l1_in_2_ ( .in ( in[8:11] ) , cby_2__1__mux_2level_basis_input4_mem4_3 mux_l2_in_0_ ( .in ( { mux_2level_basis_input4_mem4_0_out[0] , mux_2level_basis_input4_mem4_1_out[0] , - mux_2level_basis_input4_mem4_2_out[0] , SYNOPSYS_UNCONNECTED_1 } ) , + mux_2level_basis_input4_mem4_2_out[0] , const1_0_const1[0] } ) , .mem ( local_encoder2to4_1_data ) , .mem_inv ( local_encoder2to4_1_data_inv ) , - .out ( mux_2level_basis_input4_mem4_3_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_82 ( .A ( net_net_82 ) , .X ( out[0] ) ) ; + .out ( mux_2level_basis_input4_mem4_3_out ) ) ; endmodule @@ -3059,90 +3425,99 @@ wire [0:0] mux_2level_size12_mem_5_ccff_tail ; wire [0:0] mux_2level_size12_mem_6_ccff_tail ; wire [0:0] mux_2level_size12_mem_7_ccff_tail ; wire [0:0] mux_2level_size12_mem_8_ccff_tail ; +wire [0:3] mux_left_ipin_0_undriven_sram_inv ; +wire [0:3] mux_right_ipin_0_undriven_sram_inv ; +wire [0:3] mux_right_ipin_10_undriven_sram_inv ; +wire [0:3] mux_right_ipin_11_undriven_sram_inv ; +wire [0:3] mux_right_ipin_12_undriven_sram_inv ; +wire [0:3] mux_right_ipin_13_undriven_sram_inv ; +wire [0:3] mux_right_ipin_14_undriven_sram_inv ; +wire [0:3] mux_right_ipin_15_undriven_sram_inv ; +wire [0:3] mux_right_ipin_1_undriven_sram_inv ; +wire [0:3] mux_right_ipin_2_undriven_sram_inv ; +wire [0:3] mux_right_ipin_3_undriven_sram_inv ; +wire [0:3] mux_right_ipin_4_undriven_sram_inv ; +wire [0:3] mux_right_ipin_5_undriven_sram_inv ; +wire [0:3] mux_right_ipin_6_undriven_sram_inv ; +wire [0:3] mux_right_ipin_7_undriven_sram_inv ; +wire [0:3] mux_right_ipin_8_undriven_sram_inv ; +wire [0:3] mux_right_ipin_9_undriven_sram_inv ; +assign left_width_0_height_0__pin_1_lower[0] = left_width_0_height_0__pin_1_upper[0] ; assign prog_clk_0 = prog_clk[0] ; cby_2__1__mux_2level_size12_0 mux_left_ipin_0 ( - .in ( { chany_top_out[0] , chany_bottom_out[0] , chany_top_out[3] , - chany_bottom_out[3] , chany_top_out[6] , chany_bottom_out[6] , - chany_top_out[12] , chany_bottom_out[12] , chany_top_out[18] , - chany_bottom_out[18] , chany_top_out[24] , chany_bottom_out[24] } ) , - .sram ( mux_2level_size12_0_sram ) , - .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 , - SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) , - .out ( right_grid_pin_0_ ) , .p0 ( optlc_net_101 ) ) ; + .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[3] , + ZINV_195_0 , chany_bottom_in[6] , chany_top_in[6] , + chany_top_out[12] , chany_top_in[12] , chany_bottom_in[18] , + chany_top_in[18] , chany_bottom_in[24] , chany_top_in[24] } ) , + .sram ( mux_2level_size12_0_sram ) , + .sram_inv ( mux_left_ipin_0_undriven_sram_inv ) , + .out ( { ZBUF_660_f_17 } ) ) ; cby_2__1__mux_2level_size12_1 mux_right_ipin_0 ( - .in ( { chany_top_out[1] , chany_bottom_out[1] , chany_top_out[4] , - chany_bottom_out[4] , chany_top_out[7] , chany_bottom_out[7] , - chany_top_out[13] , chany_bottom_out[13] , chany_top_out[19] , - chany_bottom_out[19] , chany_top_out[25] , chany_bottom_out[25] } ) , - .sram ( mux_2level_size12_1_sram ) , - .sram_inv ( { SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 , - SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 } ) , - .out ( left_grid_pin_16_ ) , .p0 ( optlc_net_98 ) ) ; + .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[4] , + chany_top_in[4] , chany_bottom_in[7] , chany_bottom_out[7] , + chany_bottom_in[13] , ZINV_62_11 , chany_bottom_in[19] , ZINV_69_15 , + chany_bottom_in[25] , ZINV_267_1 } ) , + .sram ( mux_2level_size12_1_sram ) , + .sram_inv ( mux_right_ipin_0_undriven_sram_inv ) , + .out ( left_grid_pin_16_ ) ) ; cby_2__1__mux_2level_size12_2 mux_right_ipin_2 ( - .in ( { chany_top_out[0] , chany_bottom_out[0] , chany_top_out[3] , - chany_bottom_out[3] , chany_top_out[9] , chany_bottom_out[9] , - chany_top_out[15] , chany_bottom_out[15] , chany_top_out[21] , - chany_bottom_out[21] , chany_top_out[27] , chany_bottom_out[27] } ) , - .sram ( mux_2level_size12_2_sram ) , - .sram_inv ( { SYNOPSYS_UNCONNECTED_9 , SYNOPSYS_UNCONNECTED_10 , - SYNOPSYS_UNCONNECTED_11 , SYNOPSYS_UNCONNECTED_12 } ) , - .out ( left_grid_pin_18_ ) , .p0 ( optlc_net_99 ) ) ; + .in ( { chany_bottom_in[0] , ZINV_71_0 , chany_bottom_in[3] , ZINV_195_0 , + chany_bottom_in[9] , ZINV_65_7 , chany_bottom_in[15] , ZINV_69_14 , + chany_bottom_in[21] , chany_bottom_out[21] , chany_bottom_in[27] , + chany_top_in[27] } ) , + .sram ( mux_2level_size12_2_sram ) , + .sram_inv ( mux_right_ipin_2_undriven_sram_inv ) , + .out ( left_grid_pin_18_ ) ) ; cby_2__1__mux_2level_size12_3 mux_right_ipin_4 ( - .in ( { chany_top_out[2] , chany_bottom_out[2] , chany_top_out[5] , - chany_bottom_out[5] , chany_top_out[11] , chany_bottom_out[11] , - chany_top_out[17] , chany_bottom_out[17] , chany_top_out[23] , - chany_bottom_out[23] , chany_top_out[29] , chany_bottom_out[29] } ) , - .sram ( mux_2level_size12_3_sram ) , - .sram_inv ( { SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 , - SYNOPSYS_UNCONNECTED_15 , SYNOPSYS_UNCONNECTED_16 } ) , - .out ( left_grid_pin_20_ ) , .p0 ( optlc_net_98 ) ) ; + .in ( { chany_bottom_in[2] , chany_top_in[2] , ZINV_157_1 , + chany_top_in[5] , chany_bottom_in[11] , chany_top_in[11] , + chany_bottom_in[17] , chany_top_in[17] , chany_bottom_in[23] , + chany_top_in[23] , chany_bottom_in[29] , chany_top_in[29] } ) , + .sram ( mux_2level_size12_3_sram ) , + .sram_inv ( mux_right_ipin_4_undriven_sram_inv ) , + .out ( left_grid_pin_20_ ) ) ; cby_2__1__mux_2level_size12_4 mux_right_ipin_6 ( - .in ( { chany_top_out[1] , chany_bottom_out[1] , chany_top_out[4] , - chany_bottom_out[4] , chany_top_out[7] , chany_bottom_out[7] , - chany_top_out[13] , chany_bottom_out[13] , chany_top_out[19] , - chany_bottom_out[19] , chany_top_out[25] , chany_bottom_out[25] } ) , - .sram ( mux_2level_size12_4_sram ) , - .sram_inv ( { SYNOPSYS_UNCONNECTED_17 , SYNOPSYS_UNCONNECTED_18 , - SYNOPSYS_UNCONNECTED_19 , SYNOPSYS_UNCONNECTED_20 } ) , - .out ( left_grid_pin_22_ ) , .p0 ( optlc_net_100 ) ) ; + .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[4] , + chany_top_in[4] , chany_bottom_in[7] , chany_top_in[7] , + chany_bottom_in[13] , chany_top_in[13] , chany_bottom_in[19] , + chany_top_in[19] , chany_bottom_in[25] , chany_top_in[25] } ) , + .sram ( mux_2level_size12_4_sram ) , + .sram_inv ( mux_right_ipin_6_undriven_sram_inv ) , + .out ( left_grid_pin_22_ ) ) ; cby_2__1__mux_2level_size12_5 mux_right_ipin_8 ( - .in ( { chany_top_out[0] , chany_bottom_out[0] , chany_top_out[3] , - chany_bottom_out[3] , chany_top_out[9] , chany_bottom_out[9] , - chany_top_out[15] , chany_bottom_out[15] , chany_top_out[21] , - chany_bottom_out[21] , chany_top_out[27] , chany_bottom_out[27] } ) , - .sram ( mux_2level_size12_5_sram ) , - .sram_inv ( { SYNOPSYS_UNCONNECTED_21 , SYNOPSYS_UNCONNECTED_22 , - SYNOPSYS_UNCONNECTED_23 , SYNOPSYS_UNCONNECTED_24 } ) , - .out ( left_grid_pin_24_ ) , .p0 ( optlc_net_99 ) ) ; + .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[3] , + ZINV_195_0 , chany_bottom_in[9] , chany_top_in[9] , + chany_bottom_in[15] , chany_top_in[15] , chany_bottom_in[21] , + chany_bottom_out[21] , chany_bottom_in[27] , chany_top_in[27] } ) , + .sram ( mux_2level_size12_5_sram ) , + .sram_inv ( mux_right_ipin_8_undriven_sram_inv ) , + .out ( { ZBUF_274_f_16 } ) ) ; cby_2__1__mux_2level_size12_6 mux_right_ipin_10 ( - .in ( { chany_top_out[2] , chany_bottom_out[2] , chany_top_out[5] , - chany_bottom_out[5] , chany_top_out[11] , chany_bottom_out[11] , - chany_top_out[17] , chany_bottom_out[17] , chany_top_out[23] , - chany_bottom_out[23] , chany_top_out[29] , chany_bottom_out[29] } ) , - .sram ( mux_2level_size12_6_sram ) , - .sram_inv ( { SYNOPSYS_UNCONNECTED_25 , SYNOPSYS_UNCONNECTED_26 , - SYNOPSYS_UNCONNECTED_27 , SYNOPSYS_UNCONNECTED_28 } ) , - .out ( left_grid_pin_26_ ) , .p0 ( optlc_net_102 ) ) ; + .in ( { ZINV_68_3 , chany_top_in[2] , ZINV_157_1 , chany_top_in[5] , + ZINV_62_3 , chany_top_in[11] , ZINV_19_4 , chany_top_in[17] , + ZINV_65_3 , chany_top_in[23] , chany_bottom_in[29] , + chany_top_in[29] } ) , + .sram ( mux_2level_size12_6_sram ) , + .sram_inv ( mux_right_ipin_10_undriven_sram_inv ) , + .out ( left_grid_pin_26_ ) ) ; cby_2__1__mux_2level_size12_7 mux_right_ipin_12 ( - .in ( { chany_top_out[1] , chany_bottom_out[1] , chany_top_out[4] , - chany_bottom_out[4] , chany_top_out[7] , chany_bottom_out[7] , - chany_top_out[13] , chany_bottom_out[13] , chany_top_out[19] , - chany_bottom_out[19] , chany_top_out[25] , chany_bottom_out[25] } ) , - .sram ( mux_2level_size12_7_sram ) , - .sram_inv ( { SYNOPSYS_UNCONNECTED_29 , SYNOPSYS_UNCONNECTED_30 , - SYNOPSYS_UNCONNECTED_31 , SYNOPSYS_UNCONNECTED_32 } ) , - .out ( left_grid_pin_28_ ) , .p0 ( optlc_net_100 ) ) ; + .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[4] , + chany_top_in[4] , ZINV_65_4 , chany_top_in[7] , ZINV_65_6 , + chany_top_in[13] , chany_bottom_in[19] , chany_top_in[19] , + chany_bottom_in[25] , chany_top_in[25] } ) , + .sram ( mux_2level_size12_7_sram ) , + .sram_inv ( mux_right_ipin_12_undriven_sram_inv ) , + .out ( { ropt_net_3 } ) ) ; cby_2__1__mux_2level_size12 mux_right_ipin_14 ( - .in ( { chany_top_out[0] , chany_bottom_out[0] , chany_top_out[3] , - chany_bottom_out[3] , chany_top_out[9] , chany_bottom_out[9] , - chany_top_out[15] , chany_bottom_out[15] , chany_top_out[21] , - chany_bottom_out[21] , chany_top_out[27] , chany_bottom_out[27] } ) , - .sram ( mux_2level_size12_8_sram ) , - .sram_inv ( { SYNOPSYS_UNCONNECTED_33 , SYNOPSYS_UNCONNECTED_34 , - SYNOPSYS_UNCONNECTED_35 , SYNOPSYS_UNCONNECTED_36 } ) , - .out ( left_grid_pin_30_ ) , .p0 ( optlc_net_99 ) ) ; + .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[3] , + ZINV_195_0 , chany_bottom_in[9] , chany_top_in[9] , ZINV_69_13 , + chany_top_in[15] , chany_bottom_in[21] , chany_bottom_out[21] , + chany_bottom_in[27] , chany_top_in[27] } ) , + .sram ( mux_2level_size12_8_sram ) , + .sram_inv ( mux_right_ipin_14_undriven_sram_inv ) , + .out ( { ZBUF_7_f_17 } ) ) ; cby_2__1__mux_2level_size12_mem_0 mem_left_ipin_0 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( mux_2level_size12_mem_0_ccff_tail ) , @@ -3188,77 +3563,63 @@ cby_2__1__mux_2level_size12_mem mem_right_ipin_14 ( .pReset ( pReset ) , .ccff_tail ( mux_2level_size12_mem_8_ccff_tail ) , .mem_out ( mux_2level_size12_8_sram ) ) ; cby_2__1__mux_2level_size10_0 mux_right_ipin_1 ( - .in ( { chany_top_out[2] , chany_bottom_out[2] , chany_top_out[5] , - chany_bottom_out[5] , chany_top_out[8] , chany_bottom_out[8] , - chany_top_out[17] , chany_bottom_out[17] , chany_top_out[26] , - chany_bottom_out[26] } ) , - .sram ( mux_2level_size10_0_sram ) , - .sram_inv ( { SYNOPSYS_UNCONNECTED_37 , SYNOPSYS_UNCONNECTED_38 , - SYNOPSYS_UNCONNECTED_39 , SYNOPSYS_UNCONNECTED_40 } ) , - .out ( left_grid_pin_17_ ) , .p0 ( optlc_net_100 ) ) ; + .in ( { chany_bottom_in[2] , chany_top_in[2] , ZINV_157_1 , + chany_top_in[5] , ZINV_62_15 , chany_top_in[8] , ZINV_19_4 , + chany_top_in[17] , ZINV_62_14 , ZINV_892_f_17 } ) , + .sram ( mux_2level_size10_0_sram ) , + .sram_inv ( mux_right_ipin_1_undriven_sram_inv ) , + .out ( left_grid_pin_17_ ) ) ; cby_2__1__mux_2level_size10_1 mux_right_ipin_3 ( - .in ( { chany_top_out[1] , chany_bottom_out[1] , chany_top_out[4] , - chany_bottom_out[4] , chany_top_out[10] , chany_bottom_out[10] , - chany_top_out[19] , chany_bottom_out[19] , chany_top_out[28] , - chany_bottom_out[28] } ) , - .sram ( mux_2level_size10_1_sram ) , - .sram_inv ( { SYNOPSYS_UNCONNECTED_41 , SYNOPSYS_UNCONNECTED_42 , - SYNOPSYS_UNCONNECTED_43 , SYNOPSYS_UNCONNECTED_44 } ) , - .out ( left_grid_pin_19_ ) , .p0 ( optlc_net_100 ) ) ; + .in ( { ZINV_62_0 , chany_top_in[1] , ZINV_72_0 , chany_top_in[4] , + chany_bottom_in[10] , chany_top_in[10] , chany_bottom_in[19] , + chany_top_in[19] , chany_top_out[28] , chany_top_in[28] } ) , + .sram ( mux_2level_size10_1_sram ) , + .sram_inv ( mux_right_ipin_3_undriven_sram_inv ) , + .out ( { ropt_net_2 } ) ) ; cby_2__1__mux_2level_size10_2 mux_right_ipin_5 ( - .in ( { chany_top_out[0] , chany_bottom_out[0] , chany_top_out[3] , - chany_bottom_out[3] , chany_top_out[6] , chany_bottom_out[6] , - chany_top_out[12] , chany_bottom_out[12] , chany_top_out[21] , - chany_bottom_out[21] } ) , - .sram ( mux_2level_size10_2_sram ) , - .sram_inv ( { SYNOPSYS_UNCONNECTED_45 , SYNOPSYS_UNCONNECTED_46 , - SYNOPSYS_UNCONNECTED_47 , SYNOPSYS_UNCONNECTED_48 } ) , - .out ( left_grid_pin_21_ ) , .p0 ( optlc_net_99 ) ) ; + .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[3] , + ZINV_195_0 , chany_bottom_in[6] , chany_top_in[6] , ZINV_241_17 , + ZINV_62_10 , chany_bottom_in[21] , ZINV_423_3 } ) , + .sram ( mux_2level_size10_2_sram ) , + .sram_inv ( mux_right_ipin_5_undriven_sram_inv ) , + .out ( left_grid_pin_21_ ) ) ; cby_2__1__mux_2level_size10_3 mux_right_ipin_7 ( - .in ( { chany_top_out[2] , chany_bottom_out[2] , chany_top_out[5] , - chany_bottom_out[5] , chany_top_out[8] , chany_bottom_out[8] , - chany_top_out[14] , chany_bottom_out[14] , chany_top_out[23] , - chany_bottom_out[23] } ) , - .sram ( mux_2level_size10_3_sram ) , - .sram_inv ( { SYNOPSYS_UNCONNECTED_49 , SYNOPSYS_UNCONNECTED_50 , - SYNOPSYS_UNCONNECTED_51 , SYNOPSYS_UNCONNECTED_52 } ) , - .out ( left_grid_pin_23_ ) , .p0 ( optlc_net_98 ) ) ; + .in ( { chany_bottom_in[2] , ZINV_68_2 , ZINV_157_1 , chany_top_in[5] , + chany_bottom_in[8] , chany_top_in[8] , chany_bottom_in[14] , + ZINV_62_9 , chany_bottom_in[23] , ZINV_65_5 } ) , + .sram ( mux_2level_size10_3_sram ) , + .sram_inv ( mux_right_ipin_7_undriven_sram_inv ) , + .out ( left_grid_pin_23_ ) ) ; cby_2__1__mux_2level_size10_4 mux_right_ipin_9 ( - .in ( { chany_top_out[1] , chany_bottom_out[1] , chany_top_out[4] , - chany_bottom_out[4] , chany_top_out[10] , chany_bottom_out[10] , - chany_top_out[16] , chany_bottom_out[16] , chany_top_out[25] , - chany_bottom_out[25] } ) , - .sram ( mux_2level_size10_4_sram ) , - .sram_inv ( { SYNOPSYS_UNCONNECTED_53 , SYNOPSYS_UNCONNECTED_54 , - SYNOPSYS_UNCONNECTED_55 , SYNOPSYS_UNCONNECTED_56 } ) , - .out ( left_grid_pin_25_ ) , .p0 ( optlc_net_98 ) ) ; + .in ( { chany_bottom_in[1] , ZINV_68_0 , chany_bottom_in[4] , ZINV_68_1 , + chany_bottom_in[10] , chany_bottom_out[10] , chany_bottom_in[16] , + chany_top_in[16] , chany_bottom_in[25] , chany_bottom_out[25] } ) , + .sram ( mux_2level_size10_4_sram ) , + .sram_inv ( mux_right_ipin_9_undriven_sram_inv ) , + .out ( { ZBUF_275_f_17 } ) ) ; cby_2__1__mux_2level_size10_5 mux_right_ipin_11 ( - .in ( { chany_top_out[0] , chany_bottom_out[0] , chany_top_out[3] , - chany_bottom_out[3] , chany_top_out[12] , chany_bottom_out[12] , - chany_top_out[18] , chany_bottom_out[18] , chany_top_out[27] , - chany_bottom_out[27] } ) , - .sram ( mux_2level_size10_5_sram ) , - .sram_inv ( { SYNOPSYS_UNCONNECTED_57 , SYNOPSYS_UNCONNECTED_58 , - SYNOPSYS_UNCONNECTED_59 , SYNOPSYS_UNCONNECTED_60 } ) , - .out ( left_grid_pin_27_ ) , .p0 ( optlc_net_103 ) ) ; + .in ( { ZINV_75_3 , chany_top_in[0] , chany_bottom_in[3] , ZINV_195_0 , + chany_top_out[12] , chany_top_in[12] , ZINV_69_12 , chany_top_in[18] , + chany_bottom_in[27] , chany_top_in[27] } ) , + .sram ( mux_2level_size10_5_sram ) , + .sram_inv ( mux_right_ipin_11_undriven_sram_inv ) , + .out ( { ZBUF_275_f_16 } ) ) ; cby_2__1__mux_2level_size10_6 mux_right_ipin_13 ( - .in ( { chany_top_out[2] , chany_bottom_out[2] , chany_top_out[5] , - chany_bottom_out[5] , chany_top_out[14] , chany_bottom_out[14] , - chany_top_out[20] , chany_bottom_out[20] , chany_top_out[29] , - chany_bottom_out[29] } ) , - .sram ( mux_2level_size10_6_sram ) , - .sram_inv ( { SYNOPSYS_UNCONNECTED_61 , SYNOPSYS_UNCONNECTED_62 , - SYNOPSYS_UNCONNECTED_63 , SYNOPSYS_UNCONNECTED_64 } ) , - .out ( left_grid_pin_29_ ) , .p0 ( optlc_net_100 ) ) ; + .in ( { chany_bottom_in[2] , chany_top_in[2] , ZINV_157_1 , + chany_top_in[5] , chany_bottom_in[14] , chany_top_in[14] , + chany_bottom_in[20] , ZINV_62_16 , chany_bottom_in[29] , + chany_top_in[29] } ) , + .sram ( mux_2level_size10_6_sram ) , + .sram_inv ( mux_right_ipin_13_undriven_sram_inv ) , + .out ( left_grid_pin_29_ ) ) ; cby_2__1__mux_2level_size10 mux_right_ipin_15 ( - .in ( { chany_top_out[1] , chany_bottom_out[1] , chany_top_out[4] , - chany_bottom_out[4] , chany_top_out[7] , chany_bottom_out[7] , - chany_top_out[16] , chany_bottom_out[16] , chany_top_out[22] , - chany_bottom_out[22] } ) , - .sram ( mux_2level_size10_7_sram ) , - .sram_inv ( { SYNOPSYS_UNCONNECTED_65 , SYNOPSYS_UNCONNECTED_66 , - SYNOPSYS_UNCONNECTED_67 , SYNOPSYS_UNCONNECTED_68 } ) , - .out ( left_grid_pin_31_ ) , .p0 ( optlc_net_100 ) ) ; + .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[4] , + chany_top_in[4] , chany_bottom_in[7] , chany_top_in[7] , + ZINV_1458_f_17 , chany_top_in[16] , chany_top_out[22] , + chany_top_in[22] } ) , + .sram ( mux_2level_size10_7_sram ) , + .sram_inv ( mux_right_ipin_15_undriven_sram_inv ) , + .out ( left_grid_pin_31_ ) ) ; cby_2__1__mux_2level_size10_mem_0 mem_right_ipin_1 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( mux_2level_size12_mem_1_ccff_tail ) , @@ -3306,154 +3667,229 @@ cby_2__1__logical_tile_io_mode_io_ logical_tile_io_mode_io__0 ( .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ) , .io_outpad ( left_width_0_height_0__pin_0_ ) , .ccff_head ( { ccff_tail_mid } ) , - .io_inpad ( left_width_0_height_0__pin_1_lower ) , + .io_inpad ( left_width_0_height_0__pin_1_upper ) , .ccff_tail ( ccff_tail ) ) ; sky130_fd_sc_hd__buf_8 pReset_FTB00 ( .A ( pReset_S_in ) , .X ( pReset[0] ) ) ; -sky130_fd_sc_hd__buf_1 prog_clk_0_FTB00 ( .A ( prog_clk_0_W_in ) , +sky130_fd_sc_hd__buf_16 prog_clk_0_FTB00 ( .A ( prog_clk_0_W_in ) , .X ( prog_clk[0] ) ) ; sky130_fd_sc_hd__clkbuf_1 prog_clk_0_S_FTB01 ( .A ( prog_clk_0_W_in ) , - .X ( ctsbuf_net_1104 ) ) ; + .X ( ctsbuf_net_10 ) ) ; sky130_fd_sc_hd__clkbuf_1 prog_clk_0_N_FTB01 ( .A ( prog_clk_0_W_in ) , - .X ( ctsbuf_net_2105 ) ) ; -sky130_fd_sc_hd__buf_8 FTB_19__18 ( .A ( chany_bottom_in[0] ) , - .X ( chany_top_out[0] ) ) ; -sky130_fd_sc_hd__buf_8 FTB_20__19 ( .A ( chany_bottom_in[1] ) , - .X ( chany_top_out[1] ) ) ; -sky130_fd_sc_hd__buf_8 FTB_21__20 ( .A ( chany_bottom_in[2] ) , - .X ( chany_top_out[2] ) ) ; -sky130_fd_sc_hd__buf_8 FTB_22__21 ( .A ( chany_bottom_in[3] ) , - .X ( chany_top_out[3] ) ) ; -sky130_fd_sc_hd__buf_8 FTB_23__22 ( .A ( chany_bottom_in[4] ) , - .X ( chany_top_out[4] ) ) ; -sky130_fd_sc_hd__buf_8 FTB_24__23 ( .A ( chany_bottom_in[5] ) , - .X ( chany_top_out[5] ) ) ; -sky130_fd_sc_hd__buf_8 FTB_25__24 ( .A ( chany_bottom_in[6] ) , - .X ( chany_top_out[6] ) ) ; -sky130_fd_sc_hd__buf_8 FTB_26__25 ( .A ( chany_bottom_in[7] ) , - .X ( chany_top_out[7] ) ) ; -sky130_fd_sc_hd__buf_8 FTB_27__26 ( .A ( chany_bottom_in[8] ) , - .X ( chany_top_out[8] ) ) ; -sky130_fd_sc_hd__buf_8 FTB_28__27 ( .A ( chany_bottom_in[9] ) , - .X ( chany_top_out[9] ) ) ; -sky130_fd_sc_hd__buf_8 FTB_29__28 ( .A ( chany_bottom_in[10] ) , - .X ( chany_top_out[10] ) ) ; -sky130_fd_sc_hd__buf_8 FTB_30__29 ( .A ( chany_bottom_in[11] ) , - .X ( chany_top_out[11] ) ) ; -sky130_fd_sc_hd__buf_8 FTB_31__30 ( .A ( chany_bottom_in[12] ) , - .X ( chany_top_out[12] ) ) ; -sky130_fd_sc_hd__buf_8 FTB_32__31 ( .A ( chany_bottom_in[13] ) , - .X ( chany_top_out[13] ) ) ; -sky130_fd_sc_hd__buf_8 FTB_33__32 ( .A ( chany_bottom_in[14] ) , - .X ( chany_top_out[14] ) ) ; -sky130_fd_sc_hd__buf_8 FTB_34__33 ( .A ( chany_bottom_in[15] ) , - .X ( chany_top_out[15] ) ) ; -sky130_fd_sc_hd__buf_8 FTB_35__34 ( .A ( chany_bottom_in[16] ) , - .X ( chany_top_out[16] ) ) ; -sky130_fd_sc_hd__buf_8 FTB_36__35 ( .A ( chany_bottom_in[17] ) , - .X ( chany_top_out[17] ) ) ; -sky130_fd_sc_hd__buf_8 FTB_37__36 ( .A ( chany_bottom_in[18] ) , - .X ( chany_top_out[18] ) ) ; -sky130_fd_sc_hd__buf_8 FTB_38__37 ( .A ( chany_bottom_in[19] ) , - .X ( chany_top_out[19] ) ) ; -sky130_fd_sc_hd__buf_8 FTB_39__38 ( .A ( chany_bottom_in[20] ) , - .X ( chany_top_out[20] ) ) ; -sky130_fd_sc_hd__buf_8 FTB_40__39 ( .A ( chany_bottom_in[21] ) , - .X ( chany_top_out[21] ) ) ; -sky130_fd_sc_hd__buf_8 FTB_41__40 ( .A ( chany_bottom_in[22] ) , - .X ( chany_top_out[22] ) ) ; -sky130_fd_sc_hd__buf_8 FTB_42__41 ( .A ( chany_bottom_in[23] ) , - .X ( chany_top_out[23] ) ) ; -sky130_fd_sc_hd__buf_8 FTB_43__42 ( .A ( chany_bottom_in[24] ) , - .X ( chany_top_out[24] ) ) ; -sky130_fd_sc_hd__buf_8 FTB_44__43 ( .A ( chany_bottom_in[25] ) , - .X ( chany_top_out[25] ) ) ; -sky130_fd_sc_hd__buf_8 FTB_45__44 ( .A ( chany_bottom_in[26] ) , - .X ( chany_top_out[26] ) ) ; -sky130_fd_sc_hd__buf_8 FTB_46__45 ( .A ( chany_bottom_in[27] ) , - .X ( chany_top_out[27] ) ) ; -sky130_fd_sc_hd__buf_8 FTB_47__46 ( .A ( chany_bottom_in[28] ) , - .X ( chany_top_out[28] ) ) ; -sky130_fd_sc_hd__buf_8 FTB_48__47 ( .A ( chany_bottom_in[29] ) , - .X ( chany_top_out[29] ) ) ; -sky130_fd_sc_hd__buf_8 FTB_49__48 ( .A ( chany_top_in[0] ) , - .X ( chany_bottom_out[0] ) ) ; -sky130_fd_sc_hd__buf_8 FTB_50__49 ( .A ( chany_top_in[1] ) , - .X ( chany_bottom_out[1] ) ) ; -sky130_fd_sc_hd__buf_8 FTB_51__50 ( .A ( chany_top_in[2] ) , - .X ( chany_bottom_out[2] ) ) ; -sky130_fd_sc_hd__buf_8 FTB_52__51 ( .A ( chany_top_in[3] ) , - .X ( chany_bottom_out[3] ) ) ; -sky130_fd_sc_hd__buf_8 FTB_53__52 ( .A ( chany_top_in[4] ) , - .X ( chany_bottom_out[4] ) ) ; -sky130_fd_sc_hd__buf_8 FTB_54__53 ( .A ( chany_top_in[5] ) , - .X ( chany_bottom_out[5] ) ) ; -sky130_fd_sc_hd__buf_8 FTB_55__54 ( .A ( chany_top_in[6] ) , - .X ( chany_bottom_out[6] ) ) ; -sky130_fd_sc_hd__buf_8 FTB_56__55 ( .A ( chany_top_in[7] ) , - .X ( chany_bottom_out[7] ) ) ; -sky130_fd_sc_hd__buf_8 FTB_57__56 ( .A ( chany_top_in[8] ) , - .X ( chany_bottom_out[8] ) ) ; -sky130_fd_sc_hd__buf_8 FTB_58__57 ( .A ( chany_top_in[9] ) , - .X ( chany_bottom_out[9] ) ) ; -sky130_fd_sc_hd__buf_8 FTB_59__58 ( .A ( chany_top_in[10] ) , - .X ( chany_bottom_out[10] ) ) ; -sky130_fd_sc_hd__buf_8 FTB_60__59 ( .A ( chany_top_in[11] ) , - .X ( chany_bottom_out[11] ) ) ; -sky130_fd_sc_hd__buf_8 FTB_61__60 ( .A ( chany_top_in[12] ) , - .X ( chany_bottom_out[12] ) ) ; -sky130_fd_sc_hd__buf_8 FTB_62__61 ( .A ( chany_top_in[13] ) , - .X ( chany_bottom_out[13] ) ) ; -sky130_fd_sc_hd__buf_8 FTB_63__62 ( .A ( chany_top_in[14] ) , - .X ( chany_bottom_out[14] ) ) ; -sky130_fd_sc_hd__buf_8 FTB_64__63 ( .A ( chany_top_in[15] ) , - .X ( chany_bottom_out[15] ) ) ; -sky130_fd_sc_hd__buf_8 FTB_65__64 ( .A ( chany_top_in[16] ) , - .X ( chany_bottom_out[16] ) ) ; -sky130_fd_sc_hd__buf_8 FTB_66__65 ( .A ( chany_top_in[17] ) , - .X ( chany_bottom_out[17] ) ) ; -sky130_fd_sc_hd__buf_8 FTB_67__66 ( .A ( chany_top_in[18] ) , - .X ( chany_bottom_out[18] ) ) ; -sky130_fd_sc_hd__buf_8 FTB_68__67 ( .A ( chany_top_in[19] ) , - .X ( chany_bottom_out[19] ) ) ; -sky130_fd_sc_hd__buf_8 FTB_69__68 ( .A ( chany_top_in[20] ) , - .X ( chany_bottom_out[20] ) ) ; -sky130_fd_sc_hd__buf_8 FTB_70__69 ( .A ( chany_top_in[21] ) , - .X ( chany_bottom_out[21] ) ) ; -sky130_fd_sc_hd__buf_8 FTB_71__70 ( .A ( chany_top_in[22] ) , - .X ( chany_bottom_out[22] ) ) ; -sky130_fd_sc_hd__buf_8 FTB_72__71 ( .A ( chany_top_in[23] ) , - .X ( chany_bottom_out[23] ) ) ; -sky130_fd_sc_hd__buf_8 FTB_73__72 ( .A ( chany_top_in[24] ) , - .X ( chany_bottom_out[24] ) ) ; -sky130_fd_sc_hd__buf_8 FTB_74__73 ( .A ( chany_top_in[25] ) , - .X ( chany_bottom_out[25] ) ) ; -sky130_fd_sc_hd__buf_8 FTB_75__74 ( .A ( chany_top_in[26] ) , - .X ( chany_bottom_out[26] ) ) ; -sky130_fd_sc_hd__buf_8 FTB_76__75 ( .A ( chany_top_in[27] ) , - .X ( chany_bottom_out[27] ) ) ; -sky130_fd_sc_hd__buf_8 FTB_77__76 ( .A ( chany_top_in[28] ) , - .X ( chany_bottom_out[28] ) ) ; -sky130_fd_sc_hd__buf_8 FTB_78__77 ( .A ( chany_top_in[29] ) , - .X ( chany_bottom_out[29] ) ) ; -sky130_fd_sc_hd__buf_6 FTB_79__78 ( - .A ( left_width_0_height_0__pin_1_lower[0] ) , - .X ( left_width_0_height_0__pin_1_upper[0] ) ) ; -sky130_fd_sc_hd__conb_1 optlc_99 ( .LO ( SYNOPSYS_UNCONNECTED_69 ) , - .HI ( optlc_net_98 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_102 ( .LO ( SYNOPSYS_UNCONNECTED_70 ) , - .HI ( optlc_net_99 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_104 ( .LO ( SYNOPSYS_UNCONNECTED_71 ) , - .HI ( optlc_net_100 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_105 ( .LO ( SYNOPSYS_UNCONNECTED_72 ) , - .HI ( optlc_net_101 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_107 ( .LO ( SYNOPSYS_UNCONNECTED_73 ) , - .HI ( optlc_net_102 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_108 ( .LO ( SYNOPSYS_UNCONNECTED_74 ) , - .HI ( optlc_net_103 ) ) ; -sky130_fd_sc_hd__buf_6 cts_buf_3651248 ( .A ( ctsbuf_net_1104 ) , + .X ( ctsbuf_net_21 ) ) ; +sky130_fd_sc_hd__clkinv_4 ZINV_10_inst_877 ( .A ( ZINV_62_0 ) , + .Y ( chany_top_out[1] ) ) ; +sky130_fd_sc_hd__buf_6 cts_buf_429755 ( .A ( ctsbuf_net_10 ) , .X ( prog_clk_0_S_out ) ) ; -sky130_fd_sc_hd__buf_6 cts_buf_3701253 ( .A ( ctsbuf_net_2105 ) , +sky130_fd_sc_hd__clkbuf_8 cts_buf_434760 ( .A ( ctsbuf_net_21 ) , .X ( prog_clk_0_N_out ) ) ; +sky130_fd_sc_hd__clkinv_1 ZINV_62_inst_879 ( .A ( chany_bottom_in[1] ) , + .Y ( ZINV_62_0 ) ) ; +sky130_fd_sc_hd__buf_6 ZBUF_18_f_inst_881 ( .A ( chany_bottom_in[3] ) , + .X ( chany_top_out[3] ) ) ; +sky130_fd_sc_hd__clkinv_4 ZINV_16_inst_882 ( .A ( ZINV_68_0 ) , + .Y ( chany_bottom_out[1] ) ) ; +sky130_fd_sc_hd__clkinv_1 ZINV_68_inst_884 ( .A ( chany_top_in[1] ) , + .Y ( ZINV_68_0 ) ) ; +sky130_fd_sc_hd__clkinv_4 ZINV_20_inst_885 ( .A ( ZINV_72_0 ) , + .Y ( chany_top_out[4] ) ) ; +sky130_fd_sc_hd__clkinv_1 ZINV_72_inst_887 ( .A ( chany_bottom_in[4] ) , + .Y ( ZINV_72_0 ) ) ; +sky130_fd_sc_hd__clkinv_4 ZINV_19_inst_888 ( .A ( ZINV_71_0 ) , + .Y ( chany_bottom_out[0] ) ) ; +sky130_fd_sc_hd__clkinv_1 ZINV_71_inst_890 ( .A ( chany_top_in[0] ) , + .Y ( ZINV_71_0 ) ) ; +sky130_fd_sc_hd__inv_1 ZINV_205_inst_891 ( .A ( ZINV_267_0 ) , + .Y ( ropt_net_4 ) ) ; +sky130_fd_sc_hd__inv_1 ZINV_195_inst_892 ( .A ( ZINV_267_0 ) , + .Y ( ZINV_195_0 ) ) ; +sky130_fd_sc_hd__clkinv_1 ZINV_267_inst_893 ( .A ( chany_top_in[3] ) , + .Y ( ZINV_267_0 ) ) ; +sky130_fd_sc_hd__clkinv_4 ZINV_16_inst_894 ( .A ( ZINV_68_1 ) , + .Y ( chany_bottom_out[4] ) ) ; +sky130_fd_sc_hd__clkinv_1 ZINV_68_inst_896 ( .A ( chany_top_in[4] ) , + .Y ( ZINV_68_1 ) ) ; +sky130_fd_sc_hd__clkinv_4 ZINV_215_inst_897 ( .A ( ZINV_267_1 ) , + .Y ( chany_bottom_out[25] ) ) ; +sky130_fd_sc_hd__clkinv_1 ZINV_267_inst_899 ( .A ( chany_top_in[25] ) , + .Y ( ZINV_267_1 ) ) ; +sky130_fd_sc_hd__clkinv_4 ZINV_166_inst_900 ( .A ( ZINV_252_1 ) , + .Y ( chany_top_out[5] ) ) ; +sky130_fd_sc_hd__inv_1 ZINV_157_inst_901 ( .A ( ZINV_252_1 ) , + .Y ( ZINV_157_1 ) ) ; +sky130_fd_sc_hd__clkinv_1 ZINV_252_inst_902 ( .A ( chany_bottom_in[5] ) , + .Y ( ZINV_252_1 ) ) ; +sky130_fd_sc_hd__clkinv_4 ZINV_16_inst_903 ( .A ( ZINV_68_2 ) , + .Y ( chany_bottom_out[2] ) ) ; +sky130_fd_sc_hd__clkinv_1 ZINV_68_inst_905 ( .A ( chany_top_in[2] ) , + .Y ( ZINV_68_2 ) ) ; +sky130_fd_sc_hd__clkinv_4 ZINV_16_inst_906 ( .A ( ZINV_68_3 ) , + .Y ( chany_top_out[2] ) ) ; +sky130_fd_sc_hd__clkinv_1 ZINV_68_inst_908 ( .A ( chany_bottom_in[2] ) , + .Y ( ZINV_68_3 ) ) ; +sky130_fd_sc_hd__clkinv_4 ZINV_23_inst_909 ( .A ( ZINV_75_3 ) , + .Y ( chany_top_out[0] ) ) ; +sky130_fd_sc_hd__clkinv_1 ZINV_75_inst_911 ( .A ( chany_bottom_in[0] ) , + .Y ( ZINV_75_3 ) ) ; +sky130_fd_sc_hd__inv_8 ZINV_346_inst_913 ( .A ( ZINV_423_3 ) , + .Y ( chany_bottom_out[21] ) ) ; +sky130_fd_sc_hd__clkinv_1 ZINV_423_inst_914 ( .A ( chany_top_in[21] ) , + .Y ( ZINV_423_3 ) ) ; +sky130_fd_sc_hd__clkinv_4 ZINV_10_inst_915 ( .A ( ZINV_62_3 ) , + .Y ( chany_top_out[11] ) ) ; +sky130_fd_sc_hd__clkinv_1 ZINV_62_inst_917 ( .A ( chany_bottom_in[11] ) , + .Y ( ZINV_62_3 ) ) ; +sky130_fd_sc_hd__clkinv_4 ZINV_13_inst_918 ( .A ( ZINV_65_3 ) , + .Y ( chany_top_out[23] ) ) ; +sky130_fd_sc_hd__clkinv_1 ZINV_65_inst_920 ( .A ( chany_bottom_in[23] ) , + .Y ( ZINV_65_3 ) ) ; +sky130_fd_sc_hd__clkinv_4 ZINV_13_inst_921 ( .A ( ZINV_65_4 ) , + .Y ( chany_top_out[7] ) ) ; +sky130_fd_sc_hd__clkinv_1 ZINV_65_inst_923 ( .A ( chany_bottom_in[7] ) , + .Y ( ZINV_65_4 ) ) ; +sky130_fd_sc_hd__buf_6 ZBUF_11_f_inst_924 ( .A ( chany_bottom_in[27] ) , + .X ( chany_top_out[27] ) ) ; +sky130_fd_sc_hd__inv_8 ZINV_25_inst_925 ( .A ( ZINV_77_4 ) , + .Y ( chany_top_out[17] ) ) ; +sky130_fd_sc_hd__clkinv_1 ZINV_19_inst_926 ( .A ( ZINV_77_4 ) , + .Y ( ZINV_19_4 ) ) ; +sky130_fd_sc_hd__clkinv_1 ZINV_77_inst_927 ( .A ( chany_bottom_in[17] ) , + .Y ( ZINV_77_4 ) ) ; +sky130_fd_sc_hd__buf_6 ZBUF_14_f_inst_928 ( .A ( chany_top_in[5] ) , + .X ( chany_bottom_out[5] ) ) ; +sky130_fd_sc_hd__buf_6 ZBUF_18_f_inst_929 ( .A ( chany_top_in[27] ) , + .X ( chany_bottom_out[27] ) ) ; +sky130_fd_sc_hd__buf_6 ZBUF_11_f_inst_930 ( .A ( chany_bottom_in[19] ) , + .X ( chany_top_out[19] ) ) ; +sky130_fd_sc_hd__clkinv_4 ZINV_13_inst_931 ( .A ( ZINV_65_5 ) , + .Y ( chany_bottom_out[23] ) ) ; +sky130_fd_sc_hd__clkinv_1 ZINV_65_inst_933 ( .A ( chany_top_in[23] ) , + .Y ( ZINV_65_5 ) ) ; +sky130_fd_sc_hd__clkinv_4 ZINV_13_inst_934 ( .A ( ZINV_65_6 ) , + .Y ( chany_top_out[13] ) ) ; +sky130_fd_sc_hd__clkinv_1 ZINV_65_inst_936 ( .A ( chany_bottom_in[13] ) , + .Y ( ZINV_65_6 ) ) ; +sky130_fd_sc_hd__buf_6 ZBUF_15_f_inst_937 ( .A ( chany_bottom_in[25] ) , + .X ( chany_top_out[25] ) ) ; +sky130_fd_sc_hd__clkinv_4 ZINV_13_inst_938 ( .A ( ZINV_65_7 ) , + .Y ( chany_bottom_out[9] ) ) ; +sky130_fd_sc_hd__clkinv_1 ZINV_65_inst_940 ( .A ( chany_top_in[9] ) , + .Y ( ZINV_65_7 ) ) ; +sky130_fd_sc_hd__buf_6 ZBUF_11_f_inst_941 ( .A ( chany_bottom_in[6] ) , + .X ( chany_top_out[6] ) ) ; +sky130_fd_sc_hd__buf_6 ZBUF_15_f_inst_942 ( .A ( chany_top_in[11] ) , + .X ( chany_bottom_out[11] ) ) ; +sky130_fd_sc_hd__clkbuf_8 ZBUF_14_f_inst_943 ( .A ( chany_bottom_in[14] ) , + .X ( chany_top_out[14] ) ) ; +sky130_fd_sc_hd__buf_6 ZBUF_14_f_inst_944 ( .A ( chany_bottom_in[21] ) , + .X ( chany_top_out[21] ) ) ; +sky130_fd_sc_hd__buf_6 ZBUF_8_f_inst_945 ( .A ( chany_bottom_in[29] ) , + .X ( chany_top_out[29] ) ) ; +sky130_fd_sc_hd__buf_6 ZBUF_11_f_inst_946 ( .A ( chany_bottom_in[10] ) , + .X ( chany_top_out[10] ) ) ; +sky130_fd_sc_hd__buf_6 ZBUF_8_f_inst_947 ( .A ( chany_top_in[8] ) , + .X ( chany_bottom_out[8] ) ) ; +sky130_fd_sc_hd__clkinv_4 ZINV_10_inst_948 ( .A ( ZINV_62_9 ) , + .Y ( chany_bottom_out[14] ) ) ; +sky130_fd_sc_hd__clkinv_1 ZINV_62_inst_950 ( .A ( chany_top_in[14] ) , + .Y ( ZINV_62_9 ) ) ; +sky130_fd_sc_hd__clkinv_4 ZINV_10_inst_951 ( .A ( ZINV_62_10 ) , + .Y ( chany_bottom_out[12] ) ) ; +sky130_fd_sc_hd__clkinv_1 ZINV_62_inst_953 ( .A ( chany_top_in[12] ) , + .Y ( ZINV_62_10 ) ) ; +sky130_fd_sc_hd__buf_6 ZBUF_8_f_inst_955 ( .A ( chany_top_in[29] ) , + .X ( chany_bottom_out[29] ) ) ; +sky130_fd_sc_hd__clkinv_4 ZINV_10_inst_956 ( .A ( ZINV_62_11 ) , + .Y ( chany_bottom_out[13] ) ) ; +sky130_fd_sc_hd__clkinv_1 ZINV_62_inst_958 ( .A ( chany_top_in[13] ) , + .Y ( ZINV_62_11 ) ) ; +sky130_fd_sc_hd__buf_6 ZBUF_15_f_inst_959 ( .A ( chany_top_in[16] ) , + .X ( chany_bottom_out[16] ) ) ; +sky130_fd_sc_hd__clkinv_4 ZINV_10_inst_962 ( .A ( ZINV_69_12 ) , + .Y ( chany_top_out[18] ) ) ; +sky130_fd_sc_hd__clkinv_1 ZINV_69_inst_963 ( .A ( chany_bottom_in[18] ) , + .Y ( ZINV_69_12 ) ) ; +sky130_fd_sc_hd__clkinv_4 ZINV_17_inst_967 ( .A ( ZINV_69_13 ) , + .Y ( chany_top_out[15] ) ) ; +sky130_fd_sc_hd__clkinv_1 ZINV_69_inst_969 ( .A ( chany_bottom_in[15] ) , + .Y ( ZINV_69_13 ) ) ; +sky130_fd_sc_hd__clkinv_4 ZINV_17_inst_970 ( .A ( ZINV_69_14 ) , + .Y ( chany_bottom_out[15] ) ) ; +sky130_fd_sc_hd__clkinv_1 ZINV_69_inst_972 ( .A ( chany_top_in[15] ) , + .Y ( ZINV_69_14 ) ) ; +sky130_fd_sc_hd__buf_6 ZBUF_9_f_inst_976 ( .A ( chany_top_in[28] ) , + .X ( chany_bottom_out[28] ) ) ; +sky130_fd_sc_hd__inv_8 ZINV_10_inst_977 ( .A ( ZINV_62_14 ) , + .Y ( chany_top_out[26] ) ) ; +sky130_fd_sc_hd__clkinv_1 ZINV_62_inst_979 ( .A ( chany_bottom_in[26] ) , + .Y ( ZINV_62_14 ) ) ; +sky130_fd_sc_hd__clkinv_4 ZINV_824_f_inst_986 ( .A ( ZINV_833_14 ) , + .Y ( chany_bottom_out[22] ) ) ; +sky130_fd_sc_hd__clkinv_1 ZINV_833_inst_987 ( .A ( chany_top_in[22] ) , + .Y ( ZINV_833_14 ) ) ; +sky130_fd_sc_hd__clkinv_4 ZINV_17_inst_989 ( .A ( ZINV_69_15 ) , + .Y ( chany_bottom_out[19] ) ) ; +sky130_fd_sc_hd__clkinv_1 ZINV_69_inst_991 ( .A ( chany_top_in[19] ) , + .Y ( ZINV_69_15 ) ) ; +sky130_fd_sc_hd__clkinv_4 ZINV_10_inst_993 ( .A ( ZINV_62_15 ) , + .Y ( chany_top_out[8] ) ) ; +sky130_fd_sc_hd__clkinv_1 ZINV_62_inst_995 ( .A ( chany_bottom_in[8] ) , + .Y ( ZINV_62_15 ) ) ; +sky130_fd_sc_hd__buf_6 ZBUF_8_f_inst_999 ( .A ( chany_top_in[18] ) , + .X ( chany_bottom_out[18] ) ) ; +sky130_fd_sc_hd__clkinv_4 ZINV_10_inst_1003 ( .A ( ZINV_62_16 ) , + .Y ( chany_bottom_out[20] ) ) ; +sky130_fd_sc_hd__clkinv_1 ZINV_62_inst_1005 ( .A ( chany_top_in[20] ) , + .Y ( ZINV_62_16 ) ) ; +sky130_fd_sc_hd__buf_6 ZBUF_275_f_inst_1009 ( .A ( ZBUF_275_f_16 ) , + .X ( left_grid_pin_27_[0] ) ) ; +sky130_fd_sc_hd__buf_6 ZBUF_274_f_inst_1010 ( .A ( ZBUF_274_f_16 ) , + .X ( left_grid_pin_24_[0] ) ) ; +sky130_fd_sc_hd__buf_6 ZBUF_275_f_inst_1011 ( .A ( ZBUF_275_f_17 ) , + .X ( left_grid_pin_25_[0] ) ) ; +sky130_fd_sc_hd__buf_6 ZBUF_7_f_inst_1013 ( .A ( ZBUF_7_f_17 ) , + .X ( left_grid_pin_30_[0] ) ) ; +sky130_fd_sc_hd__inv_8 ZINV_182_inst_1017 ( .A ( ZINV_241_17 ) , + .Y ( chany_top_out[12] ) ) ; +sky130_fd_sc_hd__clkinv_1 ZINV_241_inst_1018 ( .A ( chany_bottom_in[12] ) , + .Y ( ZINV_241_17 ) ) ; +sky130_fd_sc_hd__buf_6 ZBUF_1030_f_inst_1019 ( .A ( chany_top_in[17] ) , + .X ( chany_bottom_out[17] ) ) ; +sky130_fd_sc_hd__buf_6 ZBUF_815_f_inst_1021 ( .A ( chany_bottom_in[20] ) , + .X ( chany_top_out[20] ) ) ; +sky130_fd_sc_hd__clkinv_4 ZINV_1383_inst_1022 ( .A ( ZINV_1458_f_17 ) , + .Y ( chany_top_out[16] ) ) ; +sky130_fd_sc_hd__clkinv_1 ZINV_1458_f_inst_1024 ( .A ( chany_bottom_in[16] ) , + .Y ( ZINV_1458_f_17 ) ) ; +sky130_fd_sc_hd__buf_6 ZBUF_826_f_inst_1025 ( .A ( chany_top_in[24] ) , + .X ( chany_bottom_out[24] ) ) ; +sky130_fd_sc_hd__buf_6 ZBUF_1105_f_inst_1027 ( .A ( chany_top_in[6] ) , + .X ( chany_bottom_out[6] ) ) ; +sky130_fd_sc_hd__clkinv_4 ZINV_1528_f_inst_1029 ( .A ( ZINV_1537_17 ) , + .Y ( chany_bottom_out[7] ) ) ; +sky130_fd_sc_hd__clkinv_1 ZINV_1537_inst_1030 ( .A ( chany_top_in[7] ) , + .Y ( ZINV_1537_17 ) ) ; +sky130_fd_sc_hd__buf_6 ZBUF_1011_f_inst_1031 ( .A ( chany_bottom_in[9] ) , + .X ( chany_top_out[9] ) ) ; +sky130_fd_sc_hd__buf_6 ZBUF_1267_f_inst_1032 ( .A ( chany_top_in[10] ) , + .X ( chany_bottom_out[10] ) ) ; +sky130_fd_sc_hd__clkinv_4 ZINV_816_inst_1033 ( .A ( ZINV_892_f_17 ) , + .Y ( chany_bottom_out[26] ) ) ; +sky130_fd_sc_hd__clkinv_1 ZINV_892_f_inst_1035 ( .A ( chany_top_in[26] ) , + .Y ( ZINV_892_f_17 ) ) ; +sky130_fd_sc_hd__buf_6 ZBUF_338_f_inst_1036 ( .A ( chany_bottom_in[24] ) , + .X ( chany_top_out[24] ) ) ; +sky130_fd_sc_hd__clkbuf_8 ZBUF_301_f_inst_1037 ( .A ( chany_bottom_in[22] ) , + .X ( chany_top_out[22] ) ) ; +sky130_fd_sc_hd__buf_6 ZBUF_529_f_inst_1038 ( .A ( chany_bottom_in[28] ) , + .X ( chany_top_out[28] ) ) ; +sky130_fd_sc_hd__buf_6 ZBUF_660_f_inst_1039 ( .A ( ZBUF_660_f_17 ) , + .X ( right_grid_pin_0_[0] ) ) ; +sky130_fd_sc_hd__buf_4 ropt_mt_inst_1040 ( .A ( ropt_net_2 ) , + .X ( left_grid_pin_19_[0] ) ) ; +sky130_fd_sc_hd__buf_4 ropt_mt_inst_1041 ( .A ( ropt_net_3 ) , + .X ( left_grid_pin_28_[0] ) ) ; +sky130_fd_sc_hd__buf_6 ropt_mt_inst_1043 ( .A ( ropt_net_4 ) , + .X ( chany_bottom_out[3] ) ) ; endmodule @@ -3465,8 +3901,6 @@ input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -wire copt_net_121 ; - sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , @@ -3474,15 +3908,11 @@ sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( copt_net_121 ) ) ; -sky130_fd_sc_hd__buf_6 FTB_16__15 ( .A ( copt_net_126 ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_6 FTB_16__15 ( .A ( copt_net_105 ) , .X ( ccff_tail[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1371 ( .A ( copt_net_121 ) , - .X ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1372 ( .A ( mem_out[3] ) , - .X ( copt_net_122 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1376 ( .A ( copt_net_122 ) , - .X ( copt_net_126 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1342 ( .A ( mem_out[3] ) , + .X ( copt_net_105 ) ) ; endmodule @@ -3632,9 +4062,13 @@ input [0:1] mem ; input [0:1] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -3646,12 +4080,18 @@ input [0:3] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -3661,12 +4101,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -3676,12 +4122,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -3742,7 +4194,7 @@ wire [0:0] mux_2level_basis_input4_mem4_1_out ; wire [0:0] mux_2level_basis_input4_mem4_2_out ; sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_1_0_ ( - .A ( mux_2level_basis_input4_mem4_2_out[0] ) , .X ( aps_rename_512_ ) ) ; + .A ( mux_2level_basis_input4_mem4_2_out[0] ) , .X ( out[0] ) ) ; cby_1__1__local_encoder2to4_30 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , .data ( local_encoder2to4_0_data ) , .data_inv ( local_encoder2to4_0_data_inv ) ) ; @@ -3768,9 +4220,6 @@ cby_1__1__mux_2level_basis_input2_mem2 mux_l1_in_2_ ( .in ( in[8:9] ) , .mem ( local_encoder2to4_0_data[0:1] ) , .mem_inv ( local_encoder2to4_0_data_inv[0:1] ) , .out ( mux_2level_basis_input2_mem2_0_out ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_93 ( .A ( BUF_net_94 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_94 ( .A ( aps_rename_512_ ) , - .Y ( BUF_net_94 ) ) ; endmodule @@ -3780,9 +4229,13 @@ input [0:1] mem ; input [0:1] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -3794,12 +4247,18 @@ input [0:3] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -3809,12 +4268,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -3824,12 +4289,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -3889,7 +4360,7 @@ wire [0:0] mux_2level_basis_input4_mem4_0_out ; wire [0:0] mux_2level_basis_input4_mem4_1_out ; wire [0:0] mux_2level_basis_input4_mem4_2_out ; -sky130_fd_sc_hd__bufbuf_16 sky130_fd_sc_hd__buf_1_0_ ( +sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_1_0_ ( .A ( mux_2level_basis_input4_mem4_2_out[0] ) , .X ( out[0] ) ) ; cby_1__1__local_encoder2to4_28 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , .data ( local_encoder2to4_0_data ) , @@ -3925,9 +4396,13 @@ input [0:1] mem ; input [0:1] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -3939,12 +4414,18 @@ input [0:3] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -3954,12 +4435,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -3969,12 +4456,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -4035,7 +4528,7 @@ wire [0:0] mux_2level_basis_input4_mem4_1_out ; wire [0:0] mux_2level_basis_input4_mem4_2_out ; sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_1_0_ ( - .A ( mux_2level_basis_input4_mem4_2_out[0] ) , .X ( out[0] ) ) ; + .A ( mux_2level_basis_input4_mem4_2_out[0] ) , .X ( net_net_88 ) ) ; cby_1__1__local_encoder2to4_26 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , .data ( local_encoder2to4_0_data ) , .data_inv ( local_encoder2to4_0_data_inv ) ) ; @@ -4061,6 +4554,7 @@ cby_1__1__mux_2level_basis_input2_mem2_5 mux_l1_in_2_ ( .in ( in[8:9] ) , .mem ( local_encoder2to4_0_data[0:1] ) , .mem_inv ( local_encoder2to4_0_data_inv[0:1] ) , .out ( mux_2level_basis_input2_mem2_0_out ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_88 ( .A ( net_net_88 ) , .X ( out[0] ) ) ; endmodule @@ -4070,9 +4564,13 @@ input [0:1] mem ; input [0:1] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -4084,12 +4582,18 @@ input [0:3] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -4099,12 +4603,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -4114,12 +4624,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -4180,7 +4696,7 @@ wire [0:0] mux_2level_basis_input4_mem4_1_out ; wire [0:0] mux_2level_basis_input4_mem4_2_out ; sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_1_0_ ( - .A ( mux_2level_basis_input4_mem4_2_out[0] ) , .X ( aps_rename_511_ ) ) ; + .A ( mux_2level_basis_input4_mem4_2_out[0] ) , .X ( aps_rename_510_ ) ) ; cby_1__1__local_encoder2to4_24 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , .data ( local_encoder2to4_0_data ) , .data_inv ( local_encoder2to4_0_data_inv ) ) ; @@ -4206,9 +4722,9 @@ cby_1__1__mux_2level_basis_input2_mem2_4 mux_l1_in_2_ ( .in ( in[8:9] ) , .mem ( local_encoder2to4_0_data[0:1] ) , .mem_inv ( local_encoder2to4_0_data_inv[0:1] ) , .out ( mux_2level_basis_input2_mem2_0_out ) ) ; -sky130_fd_sc_hd__inv_6 BINV_R_104 ( .A ( BUF_net_105 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_105 ( .A ( aps_rename_511_ ) , - .Y ( BUF_net_105 ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_86 ( .A ( BUF_net_87 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_87 ( .A ( aps_rename_510_ ) , + .Y ( BUF_net_87 ) ) ; endmodule @@ -4218,9 +4734,13 @@ input [0:1] mem ; input [0:1] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -4232,12 +4752,18 @@ input [0:3] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -4247,12 +4773,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -4262,12 +4794,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -4363,9 +4901,13 @@ input [0:1] mem ; input [0:1] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -4377,12 +4919,18 @@ input [0:3] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -4392,12 +4940,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -4407,12 +4961,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -4508,9 +5068,13 @@ input [0:1] mem ; input [0:1] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -4522,12 +5086,18 @@ input [0:3] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -4537,12 +5107,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -4552,12 +5128,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -4618,7 +5200,7 @@ wire [0:0] mux_2level_basis_input4_mem4_1_out ; wire [0:0] mux_2level_basis_input4_mem4_2_out ; sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_1_0_ ( - .A ( mux_2level_basis_input4_mem4_2_out[0] ) , .X ( aps_rename_510_ ) ) ; + .A ( mux_2level_basis_input4_mem4_2_out[0] ) , .X ( aps_rename_509_ ) ) ; cby_1__1__local_encoder2to4_18 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , .data ( local_encoder2to4_0_data ) , .data_inv ( local_encoder2to4_0_data_inv ) ) ; @@ -4644,9 +5226,9 @@ cby_1__1__mux_2level_basis_input2_mem2_1 mux_l1_in_2_ ( .in ( in[8:9] ) , .mem ( local_encoder2to4_0_data[0:1] ) , .mem_inv ( local_encoder2to4_0_data_inv[0:1] ) , .out ( mux_2level_basis_input2_mem2_0_out ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_89 ( .A ( BUF_net_90 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_90 ( .A ( aps_rename_510_ ) , - .Y ( BUF_net_90 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_84 ( .A ( BUF_net_85 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_85 ( .A ( aps_rename_509_ ) , + .Y ( BUF_net_85 ) ) ; endmodule @@ -4656,9 +5238,13 @@ input [0:1] mem ; input [0:1] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -4670,12 +5256,18 @@ input [0:3] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -4685,12 +5277,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -4700,12 +5298,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -4766,7 +5370,7 @@ wire [0:0] mux_2level_basis_input4_mem4_1_out ; wire [0:0] mux_2level_basis_input4_mem4_2_out ; sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_1_0_ ( - .A ( mux_2level_basis_input4_mem4_2_out[0] ) , .X ( aps_rename_509_ ) ) ; + .A ( mux_2level_basis_input4_mem4_2_out[0] ) , .X ( aps_rename_508_ ) ) ; cby_1__1__local_encoder2to4_16 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , .data ( local_encoder2to4_0_data ) , .data_inv ( local_encoder2to4_0_data_inv ) ) ; @@ -4792,9 +5396,7 @@ cby_1__1__mux_2level_basis_input2_mem2_0 mux_l1_in_2_ ( .in ( in[8:9] ) , .mem ( local_encoder2to4_0_data[0:1] ) , .mem_inv ( local_encoder2to4_0_data_inv[0:1] ) , .out ( mux_2level_basis_input2_mem2_0_out ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_87 ( .A ( BUF_net_88 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_88 ( .A ( aps_rename_509_ ) , - .Y ( BUF_net_88 ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_94 ( .A ( aps_rename_508_ ) , .X ( out[0] ) ) ; endmodule @@ -4946,7 +5548,7 @@ input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ropt_net_132 ) , +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; @@ -4955,24 +5557,6 @@ sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__buf_1 FTB_1__0 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1364 ( .A ( ropt_net_133 ) , - .X ( copt_net_114 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1365 ( .A ( copt_net_116 ) , - .X ( copt_net_115 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1366 ( .A ( copt_net_114 ) , - .X ( copt_net_116 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1367 ( .A ( ccff_head[0] ) , - .X ( copt_net_117 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1374 ( .A ( copt_net_115 ) , - .X ( copt_net_124 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 copt_h_inst_1375 ( .A ( copt_net_124 ) , - .X ( copt_net_125 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1380 ( .A ( copt_net_125 ) , - .X ( ropt_net_131 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1381 ( .A ( ropt_net_131 ) , - .X ( ropt_net_132 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 ropt_h_inst_1382 ( .A ( copt_net_117 ) , - .X ( ropt_net_133 ) ) ; endmodule @@ -4984,12 +5568,18 @@ input [0:3] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -4999,12 +5589,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -5014,12 +5610,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -5029,12 +5631,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -5094,7 +5702,7 @@ wire [0:0] mux_2level_basis_input4_mem4_1_out ; wire [0:0] mux_2level_basis_input4_mem4_2_out ; wire [0:0] mux_2level_basis_input4_mem4_3_out ; -sky130_fd_sc_hd__bufbuf_16 sky130_fd_sc_hd__buf_1_0_ ( +sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_1_0_ ( .A ( mux_2level_basis_input4_mem4_3_out[0] ) , .X ( out[0] ) ) ; cby_1__1__local_encoder2to4_14 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , .data ( local_encoder2to4_0_data ) , @@ -5132,12 +5740,18 @@ input [0:3] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -5147,12 +5761,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -5162,12 +5782,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -5177,12 +5803,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -5243,7 +5875,7 @@ wire [0:0] mux_2level_basis_input4_mem4_2_out ; wire [0:0] mux_2level_basis_input4_mem4_3_out ; sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_1_0_ ( - .A ( mux_2level_basis_input4_mem4_3_out[0] ) , .X ( aps_rename_508_ ) ) ; + .A ( mux_2level_basis_input4_mem4_3_out[0] ) , .X ( out[0] ) ) ; cby_1__1__local_encoder2to4_12 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , .data ( local_encoder2to4_0_data ) , .data_inv ( local_encoder2to4_0_data_inv ) ) ; @@ -5269,9 +5901,6 @@ cby_1__1__mux_2level_basis_input4_mem4_27 mux_l2_in_0_ ( .mem ( local_encoder2to4_1_data ) , .mem_inv ( local_encoder2to4_1_data_inv ) , .out ( mux_2level_basis_input4_mem4_3_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_85 ( .A ( BUF_net_86 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_86 ( .A ( aps_rename_508_ ) , - .Y ( BUF_net_86 ) ) ; endmodule @@ -5283,12 +5912,18 @@ input [0:3] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -5298,12 +5933,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -5313,12 +5954,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -5328,12 +5975,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -5394,7 +6047,7 @@ wire [0:0] mux_2level_basis_input4_mem4_2_out ; wire [0:0] mux_2level_basis_input4_mem4_3_out ; sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_1_0_ ( - .A ( mux_2level_basis_input4_mem4_3_out[0] ) , .X ( net_net_84 ) ) ; + .A ( mux_2level_basis_input4_mem4_3_out[0] ) , .X ( aps_rename_507_ ) ) ; cby_1__1__local_encoder2to4_10 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , .data ( local_encoder2to4_0_data ) , .data_inv ( local_encoder2to4_0_data_inv ) ) ; @@ -5420,7 +6073,9 @@ cby_1__1__mux_2level_basis_input4_mem4_23 mux_l2_in_0_ ( .mem ( local_encoder2to4_1_data ) , .mem_inv ( local_encoder2to4_1_data_inv ) , .out ( mux_2level_basis_input4_mem4_3_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_84 ( .A ( net_net_84 ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_80 ( .A ( BUF_net_81 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_81 ( .A ( aps_rename_507_ ) , + .Y ( BUF_net_81 ) ) ; endmodule @@ -5432,12 +6087,18 @@ input [0:3] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -5447,12 +6108,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -5462,12 +6129,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -5477,12 +6150,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -5543,7 +6222,7 @@ wire [0:0] mux_2level_basis_input4_mem4_2_out ; wire [0:0] mux_2level_basis_input4_mem4_3_out ; sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_1_0_ ( - .A ( mux_2level_basis_input4_mem4_3_out[0] ) , .X ( aps_rename_507_ ) ) ; + .A ( mux_2level_basis_input4_mem4_3_out[0] ) , .X ( aps_rename_506_ ) ) ; cby_1__1__local_encoder2to4_8 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , .data ( local_encoder2to4_0_data ) , .data_inv ( local_encoder2to4_0_data_inv ) ) ; @@ -5569,9 +6248,9 @@ cby_1__1__mux_2level_basis_input4_mem4_19 mux_l2_in_0_ ( .mem ( local_encoder2to4_1_data ) , .mem_inv ( local_encoder2to4_1_data_inv ) , .out ( mux_2level_basis_input4_mem4_3_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_82 ( .A ( BUF_net_83 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_83 ( .A ( aps_rename_507_ ) , - .Y ( BUF_net_83 ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_78 ( .A ( BUF_net_79 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_79 ( .A ( aps_rename_506_ ) , + .Y ( BUF_net_79 ) ) ; endmodule @@ -5583,12 +6262,18 @@ input [0:3] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -5598,12 +6283,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -5613,12 +6304,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -5628,12 +6325,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -5693,8 +6396,8 @@ wire [0:0] mux_2level_basis_input4_mem4_1_out ; wire [0:0] mux_2level_basis_input4_mem4_2_out ; wire [0:0] mux_2level_basis_input4_mem4_3_out ; -sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_1_0_ ( - .A ( mux_2level_basis_input4_mem4_3_out[0] ) , .X ( net_net_81 ) ) ; +sky130_fd_sc_hd__bufbuf_16 sky130_fd_sc_hd__buf_1_0_ ( + .A ( mux_2level_basis_input4_mem4_3_out[0] ) , .X ( out[0] ) ) ; cby_1__1__local_encoder2to4_6 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , .data ( local_encoder2to4_0_data ) , .data_inv ( local_encoder2to4_0_data_inv ) ) ; @@ -5720,7 +6423,6 @@ cby_1__1__mux_2level_basis_input4_mem4_15 mux_l2_in_0_ ( .mem ( local_encoder2to4_1_data ) , .mem_inv ( local_encoder2to4_1_data_inv ) , .out ( mux_2level_basis_input4_mem4_3_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_81 ( .A ( net_net_81 ) , .X ( out[0] ) ) ; endmodule @@ -5732,12 +6434,18 @@ input [0:3] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -5747,12 +6455,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -5762,12 +6476,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -5777,12 +6497,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -5842,8 +6568,8 @@ wire [0:0] mux_2level_basis_input4_mem4_1_out ; wire [0:0] mux_2level_basis_input4_mem4_2_out ; wire [0:0] mux_2level_basis_input4_mem4_3_out ; -sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_1_0_ ( - .A ( mux_2level_basis_input4_mem4_3_out[0] ) , .X ( aps_rename_506_ ) ) ; +sky130_fd_sc_hd__bufbuf_16 sky130_fd_sc_hd__buf_1_0_ ( + .A ( mux_2level_basis_input4_mem4_3_out[0] ) , .X ( out[0] ) ) ; cby_1__1__local_encoder2to4_4 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , .data ( local_encoder2to4_0_data ) , .data_inv ( local_encoder2to4_0_data_inv ) ) ; @@ -5869,9 +6595,6 @@ cby_1__1__mux_2level_basis_input4_mem4_11 mux_l2_in_0_ ( .mem ( local_encoder2to4_1_data ) , .mem_inv ( local_encoder2to4_1_data_inv ) , .out ( mux_2level_basis_input4_mem4_3_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_79 ( .A ( BUF_net_80 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_80 ( .A ( aps_rename_506_ ) , - .Y ( BUF_net_80 ) ) ; endmodule @@ -5883,12 +6606,18 @@ input [0:3] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -5898,12 +6627,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -5913,12 +6648,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -5928,12 +6669,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -6020,7 +6767,9 @@ cby_1__1__mux_2level_basis_input4_mem4_7 mux_l2_in_0_ ( .mem ( local_encoder2to4_1_data ) , .mem_inv ( local_encoder2to4_1_data_inv ) , .out ( mux_2level_basis_input4_mem4_3_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_101 ( .A ( aps_rename_505_ ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_76 ( .A ( BUF_net_77 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_77 ( .A ( aps_rename_505_ ) , + .Y ( BUF_net_77 ) ) ; endmodule @@ -6032,12 +6781,18 @@ input [0:3] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -6047,12 +6802,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -6062,12 +6823,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -6077,12 +6844,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -6143,7 +6916,7 @@ wire [0:0] mux_2level_basis_input4_mem4_2_out ; wire [0:0] mux_2level_basis_input4_mem4_3_out ; sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_1_0_ ( - .A ( mux_2level_basis_input4_mem4_3_out[0] ) , .X ( net_net_76 ) ) ; + .A ( mux_2level_basis_input4_mem4_3_out[0] ) , .X ( out[0] ) ) ; cby_1__1__local_encoder2to4_0 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , .data ( local_encoder2to4_0_data ) , .data_inv ( local_encoder2to4_0_data_inv ) ) ; @@ -6169,7 +6942,6 @@ cby_1__1__mux_2level_basis_input4_mem4_3 mux_l2_in_0_ ( .mem ( local_encoder2to4_1_data ) , .mem_inv ( local_encoder2to4_1_data_inv ) , .out ( mux_2level_basis_input4_mem4_3_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_76 ( .A ( net_net_76 ) , .X ( out[0] ) ) ; endmodule @@ -6245,8 +7017,6 @@ input clk_3_N_in ; output clk_3_N_out ; output clk_3_S_out ; -wire ropt_net_130 ; -wire ropt_net_129 ; wire [0:0] prog_clk ; wire prog_clk_0 ; wire [0:3] mux_2level_size10_0_sram ; @@ -6299,7 +7069,7 @@ cby_1__1__mux_2level_size12_0 mux_right_ipin_0 ( .sram ( mux_2level_size12_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 , SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) , - .out ( left_grid_pin_16_ ) , .p0 ( optlc_net_110 ) ) ; + .out ( left_grid_pin_16_ ) , .p0 ( optlc_net_99 ) ) ; cby_1__1__mux_2level_size12_1 mux_right_ipin_2 ( .in ( { chany_top_out[2] , chany_bottom_out[2] , chany_top_out[5] , chany_bottom_out[5] , chany_top_out[8] , chany_bottom_out[8] , @@ -6308,7 +7078,7 @@ cby_1__1__mux_2level_size12_1 mux_right_ipin_2 ( .sram ( mux_2level_size12_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 , SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 } ) , - .out ( left_grid_pin_18_ ) , .p0 ( optlc_net_107 ) ) ; + .out ( left_grid_pin_18_ ) , .p0 ( optlc_net_100 ) ) ; cby_1__1__mux_2level_size12_2 mux_right_ipin_4 ( .in ( { chany_top_out[1] , chany_bottom_out[1] , chany_top_out[4] , chany_bottom_out[4] , chany_top_out[10] , chany_bottom_out[10] , @@ -6317,7 +7087,7 @@ cby_1__1__mux_2level_size12_2 mux_right_ipin_4 ( .sram ( mux_2level_size12_2_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_9 , SYNOPSYS_UNCONNECTED_10 , SYNOPSYS_UNCONNECTED_11 , SYNOPSYS_UNCONNECTED_12 } ) , - .out ( left_grid_pin_20_ ) , .p0 ( optlc_net_109 ) ) ; + .out ( left_grid_pin_20_ ) , .p0 ( optlc_net_99 ) ) ; cby_1__1__mux_2level_size12_3 mux_right_ipin_6 ( .in ( { chany_top_out[0] , chany_bottom_out[0] , chany_top_out[3] , chany_bottom_out[3] , chany_top_out[6] , chany_bottom_out[6] , @@ -6326,7 +7096,7 @@ cby_1__1__mux_2level_size12_3 mux_right_ipin_6 ( .sram ( mux_2level_size12_3_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 , SYNOPSYS_UNCONNECTED_15 , SYNOPSYS_UNCONNECTED_16 } ) , - .out ( left_grid_pin_22_ ) , .p0 ( optlc_net_110 ) ) ; + .out ( left_grid_pin_22_ ) , .p0 ( optlc_net_101 ) ) ; cby_1__1__mux_2level_size12_4 mux_right_ipin_8 ( .in ( { chany_top_out[2] , chany_bottom_out[2] , chany_top_out[5] , chany_bottom_out[5] , chany_top_out[8] , chany_bottom_out[8] , @@ -6335,7 +7105,7 @@ cby_1__1__mux_2level_size12_4 mux_right_ipin_8 ( .sram ( mux_2level_size12_4_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_17 , SYNOPSYS_UNCONNECTED_18 , SYNOPSYS_UNCONNECTED_19 , SYNOPSYS_UNCONNECTED_20 } ) , - .out ( left_grid_pin_24_ ) , .p0 ( optlc_net_108 ) ) ; + .out ( left_grid_pin_24_ ) , .p0 ( optlc_net_100 ) ) ; cby_1__1__mux_2level_size12_5 mux_right_ipin_10 ( .in ( { chany_top_out[1] , chany_bottom_out[1] , chany_top_out[4] , chany_bottom_out[4] , chany_top_out[10] , chany_bottom_out[10] , @@ -6344,7 +7114,7 @@ cby_1__1__mux_2level_size12_5 mux_right_ipin_10 ( .sram ( mux_2level_size12_5_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_21 , SYNOPSYS_UNCONNECTED_22 , SYNOPSYS_UNCONNECTED_23 , SYNOPSYS_UNCONNECTED_24 } ) , - .out ( left_grid_pin_26_ ) , .p0 ( optlc_net_106 ) ) ; + .out ( left_grid_pin_26_ ) , .p0 ( optlc_net_102 ) ) ; cby_1__1__mux_2level_size12_6 mux_right_ipin_12 ( .in ( { chany_top_out[0] , chany_bottom_out[0] , chany_top_out[3] , chany_bottom_out[3] , chany_top_out[6] , chany_bottom_out[6] , @@ -6353,7 +7123,7 @@ cby_1__1__mux_2level_size12_6 mux_right_ipin_12 ( .sram ( mux_2level_size12_6_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_25 , SYNOPSYS_UNCONNECTED_26 , SYNOPSYS_UNCONNECTED_27 , SYNOPSYS_UNCONNECTED_28 } ) , - .out ( left_grid_pin_28_ ) , .p0 ( optlc_net_110 ) ) ; + .out ( left_grid_pin_28_ ) , .p0 ( optlc_net_101 ) ) ; cby_1__1__mux_2level_size12 mux_right_ipin_14 ( .in ( { chany_top_out[2] , chany_bottom_out[2] , chany_top_out[5] , chany_bottom_out[5] , chany_top_out[8] , chany_bottom_out[8] , @@ -6362,7 +7132,7 @@ cby_1__1__mux_2level_size12 mux_right_ipin_14 ( .sram ( mux_2level_size12_7_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_29 , SYNOPSYS_UNCONNECTED_30 , SYNOPSYS_UNCONNECTED_31 , SYNOPSYS_UNCONNECTED_32 } ) , - .out ( left_grid_pin_30_ ) , .p0 ( optlc_net_108 ) ) ; + .out ( left_grid_pin_30_ ) , .p0 ( optlc_net_101 ) ) ; cby_1__1__mux_2level_size12_mem_0 mem_right_ipin_0 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( mux_2level_size12_mem_0_ccff_tail ) , @@ -6410,7 +7180,7 @@ cby_1__1__mux_2level_size10_0 mux_right_ipin_1 ( .sram ( mux_2level_size10_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_33 , SYNOPSYS_UNCONNECTED_34 , SYNOPSYS_UNCONNECTED_35 , SYNOPSYS_UNCONNECTED_36 } ) , - .out ( left_grid_pin_17_ ) , .p0 ( optlc_net_108 ) ) ; + .out ( left_grid_pin_17_ ) , .p0 ( optlc_net_101 ) ) ; cby_1__1__mux_2level_size10_1 mux_right_ipin_3 ( .in ( { chany_top_out[0] , chany_bottom_out[0] , chany_top_out[3] , chany_bottom_out[3] , chany_top_out[9] , chany_bottom_out[9] , @@ -6419,7 +7189,7 @@ cby_1__1__mux_2level_size10_1 mux_right_ipin_3 ( .sram ( mux_2level_size10_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_37 , SYNOPSYS_UNCONNECTED_38 , SYNOPSYS_UNCONNECTED_39 , SYNOPSYS_UNCONNECTED_40 } ) , - .out ( left_grid_pin_19_ ) , .p0 ( optlc_net_108 ) ) ; + .out ( left_grid_pin_19_ ) , .p0 ( optlc_net_100 ) ) ; cby_1__1__mux_2level_size10_2 mux_right_ipin_5 ( .in ( { chany_top_out[2] , chany_bottom_out[2] , chany_top_out[5] , chany_bottom_out[5] , chany_top_out[11] , chany_bottom_out[11] , @@ -6428,7 +7198,7 @@ cby_1__1__mux_2level_size10_2 mux_right_ipin_5 ( .sram ( mux_2level_size10_2_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_41 , SYNOPSYS_UNCONNECTED_42 , SYNOPSYS_UNCONNECTED_43 , SYNOPSYS_UNCONNECTED_44 } ) , - .out ( left_grid_pin_21_ ) , .p0 ( optlc_net_109 ) ) ; + .out ( left_grid_pin_21_ ) , .p0 ( optlc_net_99 ) ) ; cby_1__1__mux_2level_size10_3 mux_right_ipin_7 ( .in ( { chany_top_out[1] , chany_bottom_out[1] , chany_top_out[4] , chany_bottom_out[4] , chany_top_out[7] , chany_bottom_out[7] , @@ -6437,7 +7207,7 @@ cby_1__1__mux_2level_size10_3 mux_right_ipin_7 ( .sram ( mux_2level_size10_3_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_45 , SYNOPSYS_UNCONNECTED_46 , SYNOPSYS_UNCONNECTED_47 , SYNOPSYS_UNCONNECTED_48 } ) , - .out ( left_grid_pin_23_ ) , .p0 ( optlc_net_109 ) ) ; + .out ( left_grid_pin_23_ ) , .p0 ( optlc_net_99 ) ) ; cby_1__1__mux_2level_size10_4 mux_right_ipin_9 ( .in ( { chany_top_out[0] , chany_bottom_out[0] , chany_top_out[3] , chany_bottom_out[3] , chany_top_out[9] , chany_bottom_out[9] , @@ -6446,7 +7216,7 @@ cby_1__1__mux_2level_size10_4 mux_right_ipin_9 ( .sram ( mux_2level_size10_4_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_49 , SYNOPSYS_UNCONNECTED_50 , SYNOPSYS_UNCONNECTED_51 , SYNOPSYS_UNCONNECTED_52 } ) , - .out ( left_grid_pin_25_ ) , .p0 ( optlc_net_106 ) ) ; + .out ( left_grid_pin_25_ ) , .p0 ( optlc_net_100 ) ) ; cby_1__1__mux_2level_size10_5 mux_right_ipin_11 ( .in ( { chany_top_out[2] , chany_bottom_out[2] , chany_top_out[5] , chany_bottom_out[5] , chany_top_out[11] , chany_bottom_out[11] , @@ -6455,8 +7225,7 @@ cby_1__1__mux_2level_size10_5 mux_right_ipin_11 ( .sram ( mux_2level_size10_5_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_53 , SYNOPSYS_UNCONNECTED_54 , SYNOPSYS_UNCONNECTED_55 , SYNOPSYS_UNCONNECTED_56 } ) , - .out ( { ropt_net_128 } ) , - .p0 ( optlc_net_109 ) ) ; + .out ( left_grid_pin_27_ ) , .p0 ( optlc_net_101 ) ) ; cby_1__1__mux_2level_size10_6 mux_right_ipin_13 ( .in ( { chany_top_out[1] , chany_bottom_out[1] , chany_top_out[4] , chany_bottom_out[4] , chany_top_out[13] , chany_bottom_out[13] , @@ -6465,7 +7234,7 @@ cby_1__1__mux_2level_size10_6 mux_right_ipin_13 ( .sram ( mux_2level_size10_6_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_57 , SYNOPSYS_UNCONNECTED_58 , SYNOPSYS_UNCONNECTED_59 , SYNOPSYS_UNCONNECTED_60 } ) , - .out ( left_grid_pin_29_ ) , .p0 ( optlc_net_106 ) ) ; + .out ( left_grid_pin_29_ ) , .p0 ( optlc_net_99 ) ) ; cby_1__1__mux_2level_size10 mux_right_ipin_15 ( .in ( { chany_top_out[0] , chany_bottom_out[0] , chany_top_out[3] , chany_bottom_out[3] , chany_top_out[6] , chany_bottom_out[6] , @@ -6474,7 +7243,7 @@ cby_1__1__mux_2level_size10 mux_right_ipin_15 ( .sram ( mux_2level_size10_7_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_61 , SYNOPSYS_UNCONNECTED_62 , SYNOPSYS_UNCONNECTED_63 , SYNOPSYS_UNCONNECTED_64 } ) , - .out ( left_grid_pin_31_ ) , .p0 ( optlc_net_111 ) ) ; + .out ( left_grid_pin_31_ ) , .p0 ( optlc_net_102 ) ) ; cby_1__1__mux_2level_size10_mem_0 mem_right_ipin_1 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( mux_2level_size12_mem_0_ccff_tail ) , @@ -6514,43 +7283,43 @@ cby_1__1__mux_2level_size10_mem mem_right_ipin_15 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( mux_2level_size12_mem_7_ccff_tail ) , .ccff_tail ( ccff_tail ) , .mem_out ( mux_2level_size10_7_sram ) ) ; -sky130_fd_sc_hd__bufbuf_16 Test_en_N_FTB01 ( .A ( Test_en_E_in ) , - .X ( Test_en_N_out ) ) ; -sky130_fd_sc_hd__bufbuf_16 Test_en_W_FTB01 ( .A ( Test_en_E_in ) , +sky130_fd_sc_hd__buf_1 Test_en_N_FTB01 ( .A ( Test_en_E_in ) , + .X ( net_net_89 ) ) ; +sky130_fd_sc_hd__buf_4 Test_en_W_FTB01 ( .A ( Test_en_E_in ) , .X ( Test_en_W_out ) ) ; sky130_fd_sc_hd__bufbuf_16 Test_en_E_FTB01 ( .A ( Test_en_E_in ) , .X ( Test_en_E_out ) ) ; sky130_fd_sc_hd__buf_8 pReset_FTB00 ( .A ( pReset_S_in ) , .X ( pReset[0] ) ) ; -sky130_fd_sc_hd__conb_1 optlc_109 ( .LO ( SYNOPSYS_UNCONNECTED_65 ) , - .HI ( optlc_net_106 ) ) ; -sky130_fd_sc_hd__buf_1 Reset_N_FTB01 ( .A ( Reset_E_in ) , - .X ( aps_rename_513_ ) ) ; -sky130_fd_sc_hd__bufbuf_16 Reset_W_FTB01 ( .A ( Reset_E_in ) , +sky130_fd_sc_hd__conb_1 optlc_98 ( .LO ( SYNOPSYS_UNCONNECTED_65 ) , + .HI ( optlc_net_99 ) ) ; +sky130_fd_sc_hd__bufbuf_16 Reset_N_FTB01 ( .A ( Reset_E_in ) , + .X ( Reset_N_out ) ) ; +sky130_fd_sc_hd__buf_4 Reset_W_FTB01 ( .A ( Reset_E_in ) , .X ( Reset_W_out ) ) ; sky130_fd_sc_hd__bufbuf_16 Reset_E_FTB01 ( .A ( Reset_E_in ) , .X ( Reset_E_out ) ) ; -sky130_fd_sc_hd__buf_1 prog_clk_0_FTB00 ( .A ( prog_clk_0_W_in ) , +sky130_fd_sc_hd__buf_16 prog_clk_0_FTB00 ( .A ( prog_clk_0_W_in ) , .X ( prog_clk[0] ) ) ; sky130_fd_sc_hd__clkbuf_1 prog_clk_0_S_FTB01 ( .A ( prog_clk_0_W_in ) , - .X ( ctsbuf_net_1112 ) ) ; + .X ( ctsbuf_net_1103 ) ) ; sky130_fd_sc_hd__clkbuf_1 prog_clk_0_N_FTB01 ( .A ( prog_clk_0_W_in ) , - .X ( ctsbuf_net_2113 ) ) ; -sky130_fd_sc_hd__buf_1 prog_clk_2_S_FTB01 ( .A ( prog_clk_2_S_in ) , - .X ( aps_rename_514_ ) ) ; -sky130_fd_sc_hd__buf_1 prog_clk_2_N_FTB01 ( .A ( prog_clk_2_S_in ) , - .X ( aps_rename_515_ ) ) ; -sky130_fd_sc_hd__buf_1 prog_clk_3_N_FTB01 ( .A ( prog_clk_3_N_in ) , - .X ( aps_rename_516_ ) ) ; -sky130_fd_sc_hd__buf_1 prog_clk_3_S_FTB01 ( .A ( prog_clk_3_N_in ) , - .X ( aps_rename_517_ ) ) ; -sky130_fd_sc_hd__buf_1 clk_2_S_FTB01 ( .A ( clk_2_S_in ) , - .X ( aps_rename_518_ ) ) ; -sky130_fd_sc_hd__buf_1 clk_2_N_FTB01 ( .A ( clk_2_S_in ) , - .X ( aps_rename_519_ ) ) ; -sky130_fd_sc_hd__buf_1 clk_3_N_FTB01 ( .A ( clk_3_N_in ) , - .X ( aps_rename_520_ ) ) ; -sky130_fd_sc_hd__buf_1 clk_3_S_FTB01 ( .A ( clk_3_N_in ) , - .X ( aps_rename_521_ ) ) ; + .X ( ctsbuf_net_2104 ) ) ; +sky130_fd_sc_hd__buf_4 prog_clk_2_S_FTB01 ( .A ( prog_clk_2_S_in ) , + .X ( prog_clk_2_S_out ) ) ; +sky130_fd_sc_hd__bufbuf_16 prog_clk_2_N_FTB01 ( .A ( prog_clk_2_S_in ) , + .X ( prog_clk_2_N_out ) ) ; +sky130_fd_sc_hd__bufbuf_16 prog_clk_3_N_FTB01 ( .A ( prog_clk_3_N_in ) , + .X ( prog_clk_3_N_out ) ) ; +sky130_fd_sc_hd__buf_4 prog_clk_3_S_FTB01 ( .A ( prog_clk_3_N_in ) , + .X ( prog_clk_3_S_out ) ) ; +sky130_fd_sc_hd__buf_4 clk_2_S_FTB01 ( .A ( clk_2_S_in ) , + .X ( clk_2_S_out ) ) ; +sky130_fd_sc_hd__bufbuf_16 clk_2_N_FTB01 ( .A ( clk_2_S_in ) , + .X ( clk_2_N_out ) ) ; +sky130_fd_sc_hd__bufbuf_16 clk_3_N_FTB01 ( .A ( clk_3_N_in ) , + .X ( clk_3_N_out ) ) ; +sky130_fd_sc_hd__buf_4 clk_3_S_FTB01 ( .A ( clk_3_N_in ) , + .X ( clk_3_S_out ) ) ; sky130_fd_sc_hd__buf_8 FTB_17__16 ( .A ( chany_bottom_in[0] ) , .X ( chany_top_out[0] ) ) ; sky130_fd_sc_hd__buf_8 FTB_18__17 ( .A ( chany_bottom_in[1] ) , @@ -6598,7 +7367,7 @@ sky130_fd_sc_hd__buf_8 FTB_38__37 ( .A ( chany_bottom_in[21] ) , sky130_fd_sc_hd__buf_8 FTB_39__38 ( .A ( chany_bottom_in[22] ) , .X ( chany_top_out[22] ) ) ; sky130_fd_sc_hd__buf_6 FTB_40__39 ( .A ( chany_bottom_in[23] ) , - .X ( ropt_net_130 ) ) ; + .X ( chany_top_out[23] ) ) ; sky130_fd_sc_hd__buf_8 FTB_41__40 ( .A ( chany_bottom_in[24] ) , .X ( chany_top_out[24] ) ) ; sky130_fd_sc_hd__buf_8 FTB_42__41 ( .A ( chany_bottom_in[25] ) , @@ -6658,7 +7427,7 @@ sky130_fd_sc_hd__buf_8 FTB_68__67 ( .A ( chany_top_in[21] ) , sky130_fd_sc_hd__buf_8 FTB_69__68 ( .A ( chany_top_in[22] ) , .X ( chany_bottom_out[22] ) ) ; sky130_fd_sc_hd__buf_6 FTB_70__69 ( .A ( chany_top_in[23] ) , - .X ( ropt_net_129 ) ) ; + .X ( chany_bottom_out[23] ) ) ; sky130_fd_sc_hd__buf_8 FTB_71__70 ( .A ( chany_top_in[24] ) , .X ( chany_bottom_out[24] ) ) ; sky130_fd_sc_hd__buf_8 FTB_72__71 ( .A ( chany_top_in[25] ) , @@ -6671,48 +7440,19 @@ sky130_fd_sc_hd__buf_8 FTB_75__74 ( .A ( chany_top_in[28] ) , .X ( chany_bottom_out[28] ) ) ; sky130_fd_sc_hd__buf_8 FTB_76__75 ( .A ( chany_top_in[29] ) , .X ( chany_bottom_out[29] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_95 ( .A ( BUF_net_96 ) , .Y ( pReset_N_out ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_96 ( .A ( pReset_S_in ) , .Y ( BUF_net_96 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_97 ( .A ( BUF_net_98 ) , .Y ( Reset_N_out ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_98 ( .A ( aps_rename_513_ ) , - .Y ( BUF_net_98 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_99 ( .A ( BUF_net_100 ) , .Y ( clk_3_N_out ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_100 ( .A ( aps_rename_520_ ) , - .Y ( BUF_net_100 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_110 ( .LO ( SYNOPSYS_UNCONNECTED_66 ) , - .HI ( optlc_net_107 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_114 ( .LO ( SYNOPSYS_UNCONNECTED_67 ) , - .HI ( optlc_net_108 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_116 ( .LO ( SYNOPSYS_UNCONNECTED_68 ) , - .HI ( optlc_net_109 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_118 ( .LO ( SYNOPSYS_UNCONNECTED_69 ) , - .HI ( optlc_net_110 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_119 ( .LO ( SYNOPSYS_UNCONNECTED_70 ) , - .HI ( optlc_net_111 ) ) ; -sky130_fd_sc_hd__buf_6 ZBUF_4_f_inst_120 ( .A ( aps_rename_521_ ) , - .X ( clk_3_S_out ) ) ; -sky130_fd_sc_hd__buf_6 ZBUF_4_f_inst_121 ( .A ( aps_rename_517_ ) , - .X ( prog_clk_3_S_out ) ) ; -sky130_fd_sc_hd__buf_6 ZBUF_4_f_inst_122 ( .A ( aps_rename_519_ ) , - .X ( clk_2_N_out ) ) ; -sky130_fd_sc_hd__buf_6 ZBUF_4_f_inst_123 ( .A ( aps_rename_515_ ) , - .X ( prog_clk_2_N_out ) ) ; -sky130_fd_sc_hd__buf_6 ZBUF_4_f_inst_124 ( .A ( aps_rename_516_ ) , - .X ( prog_clk_3_N_out ) ) ; -sky130_fd_sc_hd__buf_6 ZBUF_4_f_inst_125 ( .A ( aps_rename_514_ ) , - .X ( prog_clk_2_S_out ) ) ; -sky130_fd_sc_hd__buf_6 ZBUF_4_f_inst_126 ( .A ( aps_rename_518_ ) , - .X ( clk_2_S_out ) ) ; -sky130_fd_sc_hd__buf_6 ropt_mt_inst_1377 ( .A ( ropt_net_128 ) , - .X ( left_grid_pin_27_[0] ) ) ; -sky130_fd_sc_hd__buf_6 cts_buf_3651266 ( .A ( ctsbuf_net_1112 ) , +sky130_fd_sc_hd__buf_6 BUFT_RR_89 ( .A ( net_net_89 ) , .X ( Test_en_N_out ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_90 ( .A ( BUF_net_91 ) , .Y ( pReset_N_out ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_91 ( .A ( pReset_S_in ) , .Y ( BUF_net_91 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_100 ( .LO ( SYNOPSYS_UNCONNECTED_66 ) , + .HI ( optlc_net_100 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_102 ( .LO ( SYNOPSYS_UNCONNECTED_67 ) , + .HI ( optlc_net_101 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_104 ( .LO ( SYNOPSYS_UNCONNECTED_68 ) , + .HI ( optlc_net_102 ) ) ; +sky130_fd_sc_hd__buf_6 cts_buf_3651244 ( .A ( ctsbuf_net_1103 ) , .X ( prog_clk_0_S_out ) ) ; -sky130_fd_sc_hd__clkbuf_8 cts_buf_3701271 ( .A ( ctsbuf_net_2113 ) , +sky130_fd_sc_hd__clkbuf_8 cts_buf_3701249 ( .A ( ctsbuf_net_2104 ) , .X ( prog_clk_0_N_out ) ) ; -sky130_fd_sc_hd__buf_8 ropt_mt_inst_1378 ( .A ( ropt_net_129 ) , - .X ( chany_bottom_out[23] ) ) ; -sky130_fd_sc_hd__buf_8 ropt_mt_inst_1379 ( .A ( ropt_net_130 ) , - .X ( chany_top_out[23] ) ) ; endmodule @@ -6724,21 +7464,23 @@ input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:0] mem_out ; +wire copt_net_73 ; + sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__buf_6 FTB_2__1 ( .A ( copt_net_78 ) , .X ( ccff_tail[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1224 ( .A ( copt_net_76 ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( copt_net_73 ) ) ; +sky130_fd_sc_hd__buf_6 FTB_2__1 ( .A ( mem_out[0] ) , .X ( ccff_tail[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1223 ( .A ( copt_net_74 ) , + .X ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1224 ( .A ( copt_net_75 ) , .X ( copt_net_74 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1225 ( .A ( copt_net_74 ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1225 ( .A ( copt_net_76 ) , .X ( copt_net_75 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1226 ( .A ( mem_out[0] ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1226 ( .A ( copt_net_78 ) , .X ( copt_net_76 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1227 ( .A ( copt_net_79 ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1227 ( .A ( copt_net_73 ) , .X ( copt_net_77 ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1228 ( .A ( copt_net_77 ) , .X ( copt_net_78 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1229 ( .A ( copt_net_75 ) , - .X ( copt_net_79 ) ) ; endmodule @@ -6828,7 +7570,7 @@ input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( copt_net_73 ) , +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( copt_net_72 ) , .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; @@ -6837,18 +7579,18 @@ sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__buf_1 FTB_1__0 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1218 ( .A ( ccff_head[0] ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1217 ( .A ( ccff_head[0] ) , + .X ( copt_net_67 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1218 ( .A ( copt_net_69 ) , .X ( copt_net_68 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1219 ( .A ( copt_net_68 ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1219 ( .A ( copt_net_71 ) , .X ( copt_net_69 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1220 ( .A ( copt_net_69 ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1220 ( .A ( copt_net_67 ) , .X ( copt_net_70 ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1221 ( .A ( copt_net_70 ) , .X ( copt_net_71 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1222 ( .A ( copt_net_71 ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1222 ( .A ( copt_net_68 ) , .X ( copt_net_72 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1223 ( .A ( copt_net_72 ) , - .X ( copt_net_73 ) ) ; endmodule @@ -6860,12 +7602,18 @@ input [0:3] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -6875,12 +7623,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -6890,12 +7644,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -6905,12 +7665,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -6970,8 +7736,8 @@ wire [0:0] mux_2level_basis_input4_mem4_1_out ; wire [0:0] mux_2level_basis_input4_mem4_2_out ; wire [0:0] mux_2level_basis_input4_mem4_3_out ; -sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_1_0_ ( - .A ( mux_2level_basis_input4_mem4_3_out[0] ) , .X ( net_net_66 ) ) ; +sky130_fd_sc_hd__bufbuf_16 sky130_fd_sc_hd__buf_1_0_ ( + .A ( mux_2level_basis_input4_mem4_3_out[0] ) , .X ( out[0] ) ) ; cby_0__1__local_encoder2to4_0 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , .data ( local_encoder2to4_0_data ) , .data_inv ( local_encoder2to4_0_data_inv ) ) ; @@ -6997,7 +7763,6 @@ cby_0__1__mux_2level_basis_input4_mem4 mux_l2_in_0_ ( .mem ( local_encoder2to4_1_data ) , .mem_inv ( local_encoder2to4_1_data_inv ) , .out ( mux_2level_basis_input4_mem4_3_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_66 ( .A ( net_net_66 ) , .X ( out[0] ) ) ; endmodule @@ -7025,30 +7790,27 @@ output [0:0] right_width_0_height_0__pin_1_lower ; input pReset_N_in ; input prog_clk_0_E_in ; -wire ropt_net_149 ; -wire ropt_net_145 ; -wire ropt_net_129 ; -wire ropt_net_147 ; -wire ropt_net_152 ; -wire ropt_net_151 ; -wire ropt_net_142 ; -wire ropt_net_138 ; -wire ropt_net_133 ; -wire ropt_net_137 ; -wire ropt_net_130 ; -wire ropt_net_134 ; -wire ropt_net_140 ; -wire ropt_net_144 ; +wire ropt_net_122 ; wire ropt_net_135 ; -wire ropt_net_136 ; -wire ropt_net_139 ; -wire ropt_net_132 ; -wire ropt_net_150 ; -wire ropt_net_143 ; -wire ropt_net_131 ; -wire ropt_net_126 ; -wire ropt_net_127 ; wire ropt_net_128 ; +wire ropt_net_121 ; +wire ropt_net_139 ; +wire ropt_net_129 ; +wire ropt_net_134 ; +wire ropt_net_133 ; +wire ropt_net_132 ; +wire ropt_net_138 ; +wire ropt_net_123 ; +wire ropt_net_141 ; +wire ropt_net_126 ; +wire ropt_net_120 ; +wire ropt_net_125 ; +wire ropt_net_130 ; +wire ropt_net_131 ; +wire ropt_net_140 ; +wire ropt_net_137 ; +wire ropt_net_124 ; +wire ropt_net_127 ; wire [0:0] prog_clk ; wire prog_clk_0 ; wire [0:3] mux_2level_size12_0_sram ; @@ -7063,7 +7825,7 @@ cby_0__1__mux_2level_size12 mux_right_ipin_0 ( .sram ( mux_2level_size12_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 , SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) , - .out ( left_grid_pin_0_ ) , .p0 ( optlc_net_67 ) ) ; + .out ( left_grid_pin_0_ ) , .p0 ( optlc_net_66 ) ) ; cby_0__1__mux_2level_size12_mem mem_right_ipin_0 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( { ccff_tail_mid } ) , @@ -7082,177 +7844,171 @@ sky130_fd_sc_hd__buf_1 prog_clk_0_FTB00 ( .A ( prog_clk_0_E_in ) , .X ( prog_clk[0] ) ) ; sky130_fd_sc_hd__buf_8 FTB_3__2 ( .A ( chany_bottom_in[0] ) , .X ( chany_top_out[0] ) ) ; -sky130_fd_sc_hd__buf_6 FTB_4__3 ( .A ( chany_bottom_in[1] ) , - .X ( ropt_net_149 ) ) ; -sky130_fd_sc_hd__buf_8 FTB_5__4 ( .A ( chany_bottom_in[2] ) , - .X ( chany_top_out[2] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_4__3 ( .A ( chany_bottom_in[1] ) , + .X ( chany_top_out[1] ) ) ; +sky130_fd_sc_hd__buf_6 FTB_5__4 ( .A ( chany_bottom_in[2] ) , + .X ( ropt_net_122 ) ) ; sky130_fd_sc_hd__buf_8 FTB_6__5 ( .A ( chany_bottom_in[3] ) , .X ( chany_top_out[3] ) ) ; -sky130_fd_sc_hd__buf_8 FTB_7__6 ( .A ( chany_bottom_in[4] ) , - .X ( chany_top_out[4] ) ) ; -sky130_fd_sc_hd__buf_8 FTB_8__7 ( .A ( chany_bottom_in[5] ) , - .X ( chany_top_out[5] ) ) ; +sky130_fd_sc_hd__buf_6 FTB_7__6 ( .A ( chany_bottom_in[4] ) , + .X ( ropt_net_135 ) ) ; +sky130_fd_sc_hd__buf_6 FTB_8__7 ( .A ( chany_bottom_in[5] ) , + .X ( ropt_net_128 ) ) ; sky130_fd_sc_hd__buf_8 FTB_9__8 ( .A ( chany_bottom_in[6] ) , .X ( chany_top_out[6] ) ) ; -sky130_fd_sc_hd__buf_8 FTB_10__9 ( .A ( chany_bottom_in[7] ) , +sky130_fd_sc_hd__buf_6 FTB_10__9 ( .A ( chany_bottom_in[7] ) , .X ( chany_top_out[7] ) ) ; -sky130_fd_sc_hd__buf_6 FTB_11__10 ( .A ( chany_bottom_in[8] ) , - .X ( ropt_net_145 ) ) ; -sky130_fd_sc_hd__buf_6 FTB_12__11 ( .A ( chany_bottom_in[9] ) , - .X ( ropt_net_129 ) ) ; +sky130_fd_sc_hd__buf_8 FTB_11__10 ( .A ( chany_bottom_in[8] ) , + .X ( chany_top_out[8] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_12__11 ( .A ( chany_bottom_in[9] ) , + .X ( chany_top_out[9] ) ) ; sky130_fd_sc_hd__buf_8 FTB_13__12 ( .A ( chany_bottom_in[10] ) , .X ( chany_top_out[10] ) ) ; sky130_fd_sc_hd__buf_6 FTB_14__13 ( .A ( chany_bottom_in[11] ) , .X ( chany_top_out[11] ) ) ; sky130_fd_sc_hd__buf_8 FTB_15__14 ( .A ( chany_bottom_in[12] ) , .X ( chany_top_out[12] ) ) ; -sky130_fd_sc_hd__buf_8 FTB_16__15 ( .A ( chany_bottom_in[13] ) , - .X ( chany_top_out[13] ) ) ; +sky130_fd_sc_hd__buf_6 FTB_16__15 ( .A ( chany_bottom_in[13] ) , + .X ( ropt_net_121 ) ) ; sky130_fd_sc_hd__buf_8 FTB_17__16 ( .A ( chany_bottom_in[14] ) , .X ( chany_top_out[14] ) ) ; sky130_fd_sc_hd__buf_8 FTB_18__17 ( .A ( chany_bottom_in[15] ) , .X ( chany_top_out[15] ) ) ; -sky130_fd_sc_hd__buf_8 FTB_19__18 ( .A ( chany_bottom_in[16] ) , +sky130_fd_sc_hd__buf_6 FTB_19__18 ( .A ( chany_bottom_in[16] ) , .X ( chany_top_out[16] ) ) ; sky130_fd_sc_hd__buf_6 FTB_20__19 ( .A ( chany_bottom_in[17] ) , - .X ( ropt_net_147 ) ) ; + .X ( ropt_net_139 ) ) ; sky130_fd_sc_hd__buf_8 FTB_21__20 ( .A ( chany_bottom_in[18] ) , .X ( chany_top_out[18] ) ) ; sky130_fd_sc_hd__buf_6 FTB_22__21 ( .A ( chany_bottom_in[19] ) , - .X ( ropt_net_152 ) ) ; + .X ( chany_top_out[19] ) ) ; sky130_fd_sc_hd__buf_6 FTB_23__22 ( .A ( chany_bottom_in[20] ) , - .X ( ropt_net_151 ) ) ; + .X ( chany_top_out[20] ) ) ; sky130_fd_sc_hd__buf_8 FTB_24__23 ( .A ( chany_bottom_in[21] ) , .X ( chany_top_out[21] ) ) ; sky130_fd_sc_hd__buf_6 FTB_25__24 ( .A ( chany_bottom_in[22] ) , - .X ( ropt_net_142 ) ) ; -sky130_fd_sc_hd__buf_6 FTB_26__25 ( .A ( chany_bottom_in[23] ) , - .X ( ropt_net_138 ) ) ; + .X ( ropt_net_129 ) ) ; +sky130_fd_sc_hd__buf_8 FTB_26__25 ( .A ( chany_bottom_in[23] ) , + .X ( chany_top_out[23] ) ) ; sky130_fd_sc_hd__buf_8 FTB_27__26 ( .A ( chany_bottom_in[24] ) , .X ( chany_top_out[24] ) ) ; sky130_fd_sc_hd__buf_6 FTB_28__27 ( .A ( chany_bottom_in[25] ) , - .X ( ropt_net_133 ) ) ; + .X ( ropt_net_134 ) ) ; sky130_fd_sc_hd__buf_6 FTB_29__28 ( .A ( chany_bottom_in[26] ) , - .X ( ropt_net_137 ) ) ; + .X ( ropt_net_133 ) ) ; sky130_fd_sc_hd__buf_8 FTB_30__29 ( .A ( chany_bottom_in[27] ) , .X ( chany_top_out[27] ) ) ; -sky130_fd_sc_hd__buf_8 FTB_31__30 ( .A ( chany_bottom_in[28] ) , +sky130_fd_sc_hd__buf_6 FTB_31__30 ( .A ( chany_bottom_in[28] ) , .X ( chany_top_out[28] ) ) ; -sky130_fd_sc_hd__buf_6 FTB_32__31 ( .A ( chany_bottom_in[29] ) , - .X ( ropt_net_130 ) ) ; +sky130_fd_sc_hd__buf_8 FTB_32__31 ( .A ( chany_bottom_in[29] ) , + .X ( chany_top_out[29] ) ) ; sky130_fd_sc_hd__buf_8 FTB_33__32 ( .A ( chany_top_in[0] ) , .X ( chany_bottom_out[0] ) ) ; -sky130_fd_sc_hd__buf_6 FTB_34__33 ( .A ( chany_top_in[1] ) , - .X ( ropt_net_134 ) ) ; +sky130_fd_sc_hd__buf_8 FTB_34__33 ( .A ( chany_top_in[1] ) , + .X ( chany_bottom_out[1] ) ) ; sky130_fd_sc_hd__buf_6 FTB_35__34 ( .A ( chany_top_in[2] ) , - .X ( ropt_net_140 ) ) ; + .X ( ropt_net_132 ) ) ; sky130_fd_sc_hd__buf_8 FTB_36__35 ( .A ( chany_top_in[3] ) , .X ( chany_bottom_out[3] ) ) ; sky130_fd_sc_hd__buf_8 FTB_37__36 ( .A ( chany_top_in[4] ) , .X ( chany_bottom_out[4] ) ) ; -sky130_fd_sc_hd__buf_8 FTB_38__37 ( .A ( chany_top_in[5] ) , - .X ( chany_bottom_out[5] ) ) ; +sky130_fd_sc_hd__buf_6 FTB_38__37 ( .A ( chany_top_in[5] ) , + .X ( ropt_net_138 ) ) ; sky130_fd_sc_hd__buf_8 FTB_39__38 ( .A ( chany_top_in[6] ) , .X ( chany_bottom_out[6] ) ) ; sky130_fd_sc_hd__buf_6 FTB_40__39 ( .A ( chany_top_in[7] ) , - .X ( ropt_net_144 ) ) ; -sky130_fd_sc_hd__buf_8 FTB_41__40 ( .A ( chany_top_in[8] ) , + .X ( ropt_net_123 ) ) ; +sky130_fd_sc_hd__buf_6 FTB_41__40 ( .A ( chany_top_in[8] ) , .X ( chany_bottom_out[8] ) ) ; -sky130_fd_sc_hd__buf_8 FTB_42__41 ( .A ( chany_top_in[9] ) , - .X ( chany_bottom_out[9] ) ) ; +sky130_fd_sc_hd__buf_6 FTB_42__41 ( .A ( chany_top_in[9] ) , + .X ( ropt_net_141 ) ) ; sky130_fd_sc_hd__buf_6 FTB_43__42 ( .A ( chany_top_in[10] ) , - .X ( ropt_net_135 ) ) ; + .X ( ropt_net_126 ) ) ; sky130_fd_sc_hd__buf_8 FTB_44__43 ( .A ( chany_top_in[11] ) , .X ( chany_bottom_out[11] ) ) ; sky130_fd_sc_hd__buf_8 FTB_45__44 ( .A ( chany_top_in[12] ) , .X ( chany_bottom_out[12] ) ) ; sky130_fd_sc_hd__buf_6 FTB_46__45 ( .A ( chany_top_in[13] ) , - .X ( ropt_net_136 ) ) ; + .X ( ropt_net_120 ) ) ; sky130_fd_sc_hd__buf_6 FTB_47__46 ( .A ( chany_top_in[14] ) , - .X ( ropt_net_139 ) ) ; -sky130_fd_sc_hd__buf_8 FTB_48__47 ( .A ( chany_top_in[15] ) , - .X ( chany_bottom_out[15] ) ) ; + .X ( ropt_net_125 ) ) ; +sky130_fd_sc_hd__buf_6 FTB_48__47 ( .A ( chany_top_in[15] ) , + .X ( ropt_net_130 ) ) ; sky130_fd_sc_hd__buf_6 FTB_49__48 ( .A ( chany_top_in[16] ) , - .X ( chany_bottom_out[16] ) ) ; + .X ( ropt_net_131 ) ) ; sky130_fd_sc_hd__buf_8 FTB_50__49 ( .A ( chany_top_in[17] ) , .X ( chany_bottom_out[17] ) ) ; sky130_fd_sc_hd__buf_8 FTB_51__50 ( .A ( chany_top_in[18] ) , .X ( chany_bottom_out[18] ) ) ; -sky130_fd_sc_hd__buf_6 FTB_52__51 ( .A ( chany_top_in[19] ) , - .X ( ropt_net_132 ) ) ; +sky130_fd_sc_hd__buf_8 FTB_52__51 ( .A ( chany_top_in[19] ) , + .X ( chany_bottom_out[19] ) ) ; sky130_fd_sc_hd__buf_6 FTB_53__52 ( .A ( chany_top_in[20] ) , - .X ( ropt_net_150 ) ) ; + .X ( ropt_net_140 ) ) ; sky130_fd_sc_hd__buf_8 FTB_54__53 ( .A ( chany_top_in[21] ) , .X ( chany_bottom_out[21] ) ) ; sky130_fd_sc_hd__buf_6 FTB_55__54 ( .A ( chany_top_in[22] ) , - .X ( ropt_net_143 ) ) ; -sky130_fd_sc_hd__buf_8 FTB_56__55 ( .A ( chany_top_in[23] ) , - .X ( chany_bottom_out[23] ) ) ; + .X ( ropt_net_137 ) ) ; +sky130_fd_sc_hd__buf_6 FTB_56__55 ( .A ( chany_top_in[23] ) , + .X ( ropt_net_124 ) ) ; sky130_fd_sc_hd__buf_8 FTB_57__56 ( .A ( chany_top_in[24] ) , .X ( chany_bottom_out[24] ) ) ; sky130_fd_sc_hd__buf_6 FTB_58__57 ( .A ( chany_top_in[25] ) , - .X ( ropt_net_131 ) ) ; -sky130_fd_sc_hd__buf_6 FTB_59__58 ( .A ( chany_top_in[26] ) , - .X ( ropt_net_126 ) ) ; -sky130_fd_sc_hd__buf_6 FTB_60__59 ( .A ( chany_top_in[27] ) , .X ( ropt_net_127 ) ) ; +sky130_fd_sc_hd__buf_8 FTB_59__58 ( .A ( chany_top_in[26] ) , + .X ( chany_bottom_out[26] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_60__59 ( .A ( chany_top_in[27] ) , + .X ( chany_bottom_out[27] ) ) ; sky130_fd_sc_hd__buf_8 FTB_61__60 ( .A ( chany_top_in[28] ) , .X ( chany_bottom_out[28] ) ) ; -sky130_fd_sc_hd__buf_6 FTB_62__61 ( .A ( chany_top_in[29] ) , - .X ( ropt_net_128 ) ) ; +sky130_fd_sc_hd__buf_8 FTB_62__61 ( .A ( chany_top_in[29] ) , + .X ( chany_bottom_out[29] ) ) ; sky130_fd_sc_hd__buf_6 FTB_63__62 ( .A ( right_width_0_height_0__pin_1_lower[0] ) , .X ( right_width_0_height_0__pin_1_upper[0] ) ) ; -sky130_fd_sc_hd__conb_1 optlc_68 ( .LO ( SYNOPSYS_UNCONNECTED_5 ) , - .HI ( optlc_net_67 ) ) ; -sky130_fd_sc_hd__buf_8 ropt_mt_inst_1276 ( .A ( ropt_net_126 ) , - .X ( chany_bottom_out[26] ) ) ; -sky130_fd_sc_hd__buf_8 ropt_mt_inst_1277 ( .A ( ropt_net_127 ) , - .X ( chany_bottom_out[27] ) ) ; -sky130_fd_sc_hd__buf_8 ropt_mt_inst_1278 ( .A ( ropt_net_128 ) , - .X ( chany_bottom_out[29] ) ) ; -sky130_fd_sc_hd__buf_8 ropt_mt_inst_1279 ( .A ( ropt_net_129 ) , - .X ( chany_top_out[9] ) ) ; -sky130_fd_sc_hd__buf_8 ropt_mt_inst_1280 ( .A ( ropt_net_130 ) , - .X ( chany_top_out[29] ) ) ; -sky130_fd_sc_hd__buf_8 ropt_mt_inst_1281 ( .A ( ropt_net_131 ) , - .X ( chany_bottom_out[25] ) ) ; -sky130_fd_sc_hd__buf_8 ropt_mt_inst_1282 ( .A ( ropt_net_132 ) , - .X ( chany_bottom_out[19] ) ) ; -sky130_fd_sc_hd__buf_8 ropt_mt_inst_1283 ( .A ( ropt_net_133 ) , - .X ( chany_top_out[25] ) ) ; -sky130_fd_sc_hd__buf_8 ropt_mt_inst_1284 ( .A ( ropt_net_134 ) , - .X ( chany_bottom_out[1] ) ) ; -sky130_fd_sc_hd__buf_8 ropt_mt_inst_1285 ( .A ( ropt_net_135 ) , - .X ( chany_bottom_out[10] ) ) ; -sky130_fd_sc_hd__buf_8 ropt_mt_inst_1286 ( .A ( ropt_net_136 ) , +sky130_fd_sc_hd__conb_1 optlc_67 ( .LO ( SYNOPSYS_UNCONNECTED_5 ) , + .HI ( optlc_net_66 ) ) ; +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1270 ( .A ( ropt_net_120 ) , .X ( chany_bottom_out[13] ) ) ; -sky130_fd_sc_hd__buf_8 ropt_mt_inst_1287 ( .A ( ropt_net_137 ) , - .X ( chany_top_out[26] ) ) ; -sky130_fd_sc_hd__buf_8 ropt_mt_inst_1288 ( .A ( ropt_net_138 ) , - .X ( chany_top_out[23] ) ) ; -sky130_fd_sc_hd__buf_8 ropt_mt_inst_1289 ( .A ( ropt_net_139 ) , - .X ( chany_bottom_out[14] ) ) ; -sky130_fd_sc_hd__buf_8 ropt_mt_inst_1290 ( .A ( ropt_net_140 ) , - .X ( chany_bottom_out[2] ) ) ; -sky130_fd_sc_hd__buf_8 ropt_mt_inst_1292 ( .A ( ropt_net_142 ) , - .X ( chany_top_out[22] ) ) ; -sky130_fd_sc_hd__buf_8 ropt_mt_inst_1293 ( .A ( ropt_net_143 ) , - .X ( chany_bottom_out[22] ) ) ; -sky130_fd_sc_hd__buf_8 ropt_mt_inst_1294 ( .A ( ropt_net_144 ) , +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1271 ( .A ( ropt_net_121 ) , + .X ( chany_top_out[13] ) ) ; +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1272 ( .A ( ropt_net_122 ) , + .X ( chany_top_out[2] ) ) ; +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1273 ( .A ( ropt_net_123 ) , .X ( chany_bottom_out[7] ) ) ; -sky130_fd_sc_hd__buf_8 ropt_mt_inst_1295 ( .A ( ropt_net_145 ) , - .X ( chany_top_out[8] ) ) ; -sky130_fd_sc_hd__buf_8 ropt_mt_inst_1297 ( .A ( ropt_net_147 ) , +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1274 ( .A ( ropt_net_124 ) , + .X ( chany_bottom_out[23] ) ) ; +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1275 ( .A ( ropt_net_125 ) , + .X ( chany_bottom_out[14] ) ) ; +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1276 ( .A ( ropt_net_126 ) , + .X ( chany_bottom_out[10] ) ) ; +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1277 ( .A ( ropt_net_127 ) , + .X ( chany_bottom_out[25] ) ) ; +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1278 ( .A ( ropt_net_128 ) , + .X ( chany_top_out[5] ) ) ; +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1279 ( .A ( ropt_net_129 ) , + .X ( chany_top_out[22] ) ) ; +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1280 ( .A ( ropt_net_130 ) , + .X ( chany_bottom_out[15] ) ) ; +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1281 ( .A ( ropt_net_131 ) , + .X ( chany_bottom_out[16] ) ) ; +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1282 ( .A ( ropt_net_132 ) , + .X ( chany_bottom_out[2] ) ) ; +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1283 ( .A ( ropt_net_133 ) , + .X ( chany_top_out[26] ) ) ; +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1284 ( .A ( ropt_net_134 ) , + .X ( chany_top_out[25] ) ) ; +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1285 ( .A ( ropt_net_135 ) , + .X ( chany_top_out[4] ) ) ; +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1287 ( .A ( ropt_net_137 ) , + .X ( chany_bottom_out[22] ) ) ; +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1288 ( .A ( ropt_net_138 ) , + .X ( chany_bottom_out[5] ) ) ; +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1289 ( .A ( ropt_net_139 ) , .X ( chany_top_out[17] ) ) ; -sky130_fd_sc_hd__buf_8 ropt_mt_inst_1299 ( .A ( ropt_net_149 ) , - .X ( chany_top_out[1] ) ) ; -sky130_fd_sc_hd__buf_8 ropt_mt_inst_1300 ( .A ( ropt_net_150 ) , +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1290 ( .A ( ropt_net_140 ) , .X ( chany_bottom_out[20] ) ) ; -sky130_fd_sc_hd__buf_8 ropt_mt_inst_1301 ( .A ( ropt_net_151 ) , - .X ( chany_top_out[20] ) ) ; -sky130_fd_sc_hd__buf_8 ropt_mt_inst_1302 ( .A ( ropt_net_152 ) , - .X ( chany_top_out[19] ) ) ; +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1291 ( .A ( ropt_net_141 ) , + .X ( chany_bottom_out[9] ) ) ; endmodule @@ -7264,17 +8020,9 @@ input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:0] mem_out ; -wire copt_net_138 ; - sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( copt_net_138 ) ) ; + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; sky130_fd_sc_hd__buf_6 FTB_18__17 ( .A ( mem_out[0] ) , .X ( ccff_tail[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1374 ( .A ( copt_net_138 ) , - .X ( copt_net_137 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1376 ( .A ( copt_net_140 ) , - .X ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1377 ( .A ( copt_net_137 ) , - .X ( copt_net_140 ) ) ; endmodule @@ -7289,15 +8037,16 @@ input FPGA_DIR ; input IO_ISOL_N ; sky130_fd_sc_hd__nand2b_1 ISOL_EN_GATE ( .A_N ( FPGA_DIR ) , - .B ( IO_ISOL_N ) , .Y ( aps_rename_516_ ) ) ; -sky130_fd_sc_hd__inv_1 INV_SOC_DIR ( .A ( BUF_net_81 ) , .Y ( SOC_DIR_N ) ) ; + .B ( IO_ISOL_N ) , .Y ( aps_rename_515_ ) ) ; +sky130_fd_sc_hd__inv_1 INV_SOC_DIR ( .A ( aps_rename_515_ ) , + .Y ( SOC_DIR_N ) ) ; sky130_fd_sc_hd__ebufn_4 IN_PROTECT_GATE ( .A ( SOC_IN ) , .TE_B ( SOC_DIR_N ) , .Z ( FPGA_IN ) ) ; sky130_fd_sc_hd__ebufn_4 OUT_PROTECT_GATE ( .A ( FPGA_OUT ) , - .TE_B ( BUF_net_81 ) , .Z ( SOC_OUT ) ) ; -sky130_fd_sc_hd__inv_4 BINV_R_81 ( .A ( BUF_net_83 ) , .Y ( BUF_net_81 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_82 ( .A ( BUF_net_83 ) , .Y ( SOC_DIR ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_83 ( .A ( aps_rename_516_ ) , + .TE_B ( BUF_net_82 ) , .Z ( SOC_OUT ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_81 ( .A ( BUF_net_83 ) , .Y ( SOC_DIR ) ) ; +sky130_fd_sc_hd__inv_4 BINV_R_82 ( .A ( BUF_net_83 ) , .Y ( BUF_net_82 ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_83 ( .A ( aps_rename_515_ ) , .Y ( BUF_net_83 ) ) ; endmodule @@ -7522,9 +8271,13 @@ input [0:1] mem ; input [0:1] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -7536,12 +8289,18 @@ input [0:3] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -7551,12 +8310,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -7566,12 +8331,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -7632,7 +8403,7 @@ wire [0:0] mux_2level_basis_input4_mem4_1_out ; wire [0:0] mux_2level_basis_input4_mem4_2_out ; sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_1_0_ ( - .A ( mux_2level_basis_input4_mem4_2_out[0] ) , .X ( out[0] ) ) ; + .A ( mux_2level_basis_input4_mem4_2_out[0] ) , .X ( aps_rename_514_ ) ) ; cbx_1__2__local_encoder2to4_32 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , .data ( local_encoder2to4_0_data ) , .data_inv ( local_encoder2to4_0_data_inv ) ) ; @@ -7658,6 +8429,9 @@ cbx_1__2__mux_2level_basis_input2_mem2 mux_l1_in_2_ ( .in ( in[8:9] ) , .mem ( local_encoder2to4_0_data[0:1] ) , .mem_inv ( local_encoder2to4_0_data_inv[0:1] ) , .out ( mux_2level_basis_input2_mem2_0_out ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_95 ( .A ( aps_rename_514_ ) , + .Y ( BUF_net_95 ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_101 ( .A ( BUF_net_95 ) , .Y ( out[0] ) ) ; endmodule @@ -7667,9 +8441,13 @@ input [0:1] mem ; input [0:1] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -7681,12 +8459,18 @@ input [0:3] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -7696,12 +8480,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -7711,12 +8501,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -7777,7 +8573,7 @@ wire [0:0] mux_2level_basis_input4_mem4_1_out ; wire [0:0] mux_2level_basis_input4_mem4_2_out ; sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_1_0_ ( - .A ( mux_2level_basis_input4_mem4_2_out[0] ) , .X ( aps_rename_515_ ) ) ; + .A ( mux_2level_basis_input4_mem4_2_out[0] ) , .X ( out[0] ) ) ; cbx_1__2__local_encoder2to4_30 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , .data ( local_encoder2to4_0_data ) , .data_inv ( local_encoder2to4_0_data_inv ) ) ; @@ -7803,9 +8599,6 @@ cbx_1__2__mux_2level_basis_input2_mem2_6 mux_l1_in_2_ ( .in ( in[8:9] ) , .mem ( local_encoder2to4_0_data[0:1] ) , .mem_inv ( local_encoder2to4_0_data_inv[0:1] ) , .out ( mux_2level_basis_input2_mem2_0_out ) ) ; -sky130_fd_sc_hd__inv_2 BINV_R_106 ( .A ( aps_rename_515_ ) , - .Y ( BUF_net_106 ) ) ; -sky130_fd_sc_hd__inv_6 BINV_R_115 ( .A ( BUF_net_106 ) , .Y ( out[0] ) ) ; endmodule @@ -7815,9 +8608,13 @@ input [0:1] mem ; input [0:1] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -7829,12 +8626,18 @@ input [0:3] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -7844,12 +8647,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -7859,12 +8668,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -7925,7 +8740,7 @@ wire [0:0] mux_2level_basis_input4_mem4_1_out ; wire [0:0] mux_2level_basis_input4_mem4_2_out ; sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_1_0_ ( - .A ( mux_2level_basis_input4_mem4_2_out[0] ) , .X ( aps_rename_514_ ) ) ; + .A ( mux_2level_basis_input4_mem4_2_out[0] ) , .X ( aps_rename_513_ ) ) ; cbx_1__2__local_encoder2to4_28 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , .data ( local_encoder2to4_0_data ) , .data_inv ( local_encoder2to4_0_data_inv ) ) ; @@ -7951,9 +8766,9 @@ cbx_1__2__mux_2level_basis_input2_mem2_5 mux_l1_in_2_ ( .in ( in[8:9] ) , .mem ( local_encoder2to4_0_data[0:1] ) , .mem_inv ( local_encoder2to4_0_data_inv[0:1] ) , .out ( mux_2level_basis_input2_mem2_0_out ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_103 ( .A ( BUF_net_104 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_4 BINV_R_104 ( .A ( aps_rename_514_ ) , - .Y ( BUF_net_104 ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_92 ( .A ( BUF_net_93 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_93 ( .A ( aps_rename_513_ ) , + .Y ( BUF_net_93 ) ) ; endmodule @@ -7963,9 +8778,13 @@ input [0:1] mem ; input [0:1] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -7977,12 +8796,18 @@ input [0:3] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -7992,12 +8817,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -8007,12 +8838,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -8073,7 +8910,7 @@ wire [0:0] mux_2level_basis_input4_mem4_1_out ; wire [0:0] mux_2level_basis_input4_mem4_2_out ; sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_1_0_ ( - .A ( mux_2level_basis_input4_mem4_2_out[0] ) , .X ( aps_rename_513_ ) ) ; + .A ( mux_2level_basis_input4_mem4_2_out[0] ) , .X ( aps_rename_512_ ) ) ; cbx_1__2__local_encoder2to4_26 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , .data ( local_encoder2to4_0_data ) , .data_inv ( local_encoder2to4_0_data_inv ) ) ; @@ -8099,9 +8936,9 @@ cbx_1__2__mux_2level_basis_input2_mem2_4 mux_l1_in_2_ ( .in ( in[8:9] ) , .mem ( local_encoder2to4_0_data[0:1] ) , .mem_inv ( local_encoder2to4_0_data_inv[0:1] ) , .out ( mux_2level_basis_input2_mem2_0_out ) ) ; -sky130_fd_sc_hd__inv_2 BINV_R_102 ( .A ( aps_rename_513_ ) , - .Y ( BUF_net_102 ) ) ; -sky130_fd_sc_hd__inv_6 BINV_R_119 ( .A ( BUF_net_102 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_109 ( .A ( BUF_net_110 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_4 BINV_R_110 ( .A ( aps_rename_512_ ) , + .Y ( BUF_net_110 ) ) ; endmodule @@ -8111,9 +8948,13 @@ input [0:1] mem ; input [0:1] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -8125,12 +8966,18 @@ input [0:3] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -8140,12 +8987,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -8155,12 +9008,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -8256,9 +9115,13 @@ input [0:1] mem ; input [0:1] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -8270,12 +9133,18 @@ input [0:3] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -8285,12 +9154,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -8300,12 +9175,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -8366,7 +9247,7 @@ wire [0:0] mux_2level_basis_input4_mem4_1_out ; wire [0:0] mux_2level_basis_input4_mem4_2_out ; sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_1_0_ ( - .A ( mux_2level_basis_input4_mem4_2_out[0] ) , .X ( aps_rename_512_ ) ) ; + .A ( mux_2level_basis_input4_mem4_2_out[0] ) , .X ( out[0] ) ) ; cbx_1__2__local_encoder2to4_22 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , .data ( local_encoder2to4_0_data ) , .data_inv ( local_encoder2to4_0_data_inv ) ) ; @@ -8392,9 +9273,6 @@ cbx_1__2__mux_2level_basis_input2_mem2_2 mux_l1_in_2_ ( .in ( in[8:9] ) , .mem ( local_encoder2to4_0_data[0:1] ) , .mem_inv ( local_encoder2to4_0_data_inv[0:1] ) , .out ( mux_2level_basis_input2_mem2_0_out ) ) ; -sky130_fd_sc_hd__inv_4 BINV_R_123 ( .A ( BUF_net_124 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_4 BINV_R_124 ( .A ( aps_rename_512_ ) , - .Y ( BUF_net_124 ) ) ; endmodule @@ -8404,9 +9282,13 @@ input [0:1] mem ; input [0:1] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -8418,12 +9300,18 @@ input [0:3] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -8433,12 +9321,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -8448,12 +9342,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -8549,9 +9449,13 @@ input [0:1] mem ; input [0:1] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -8563,12 +9467,18 @@ input [0:3] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -8578,12 +9488,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -8593,12 +9509,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -8685,9 +9607,9 @@ cbx_1__2__mux_2level_basis_input2_mem2_0 mux_l1_in_2_ ( .in ( in[8:9] ) , .mem ( local_encoder2to4_0_data[0:1] ) , .mem_inv ( local_encoder2to4_0_data_inv[0:1] ) , .out ( mux_2level_basis_input2_mem2_0_out ) ) ; -sky130_fd_sc_hd__inv_2 BINV_R_98 ( .A ( aps_rename_511_ ) , - .Y ( BUF_net_98 ) ) ; -sky130_fd_sc_hd__inv_4 BINV_R_117 ( .A ( BUF_net_98 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_91 ( .A ( aps_rename_511_ ) , + .Y ( BUF_net_91 ) ) ; +sky130_fd_sc_hd__inv_4 BINV_R_98 ( .A ( BUF_net_91 ) , .Y ( out[0] ) ) ; endmodule @@ -8859,7 +9781,7 @@ input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ropt_net_146 ) , +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( copt_net_122 ) , .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; @@ -8868,26 +9790,8 @@ sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__buf_1 FTB_1__0 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1367 ( .A ( copt_net_133 ) , - .X ( copt_net_130 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1368 ( .A ( ropt_net_147 ) , - .X ( copt_net_131 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1369 ( .A ( copt_net_130 ) , - .X ( copt_net_132 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1370 ( .A ( ccff_head[0] ) , - .X ( copt_net_133 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1371 ( .A ( copt_net_131 ) , - .X ( copt_net_134 ) ) ; -sky130_fd_sc_hd__buf_1 copt_h_inst_1372 ( .A ( copt_net_132 ) , - .X ( copt_net_135 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1379 ( .A ( ropt_net_145 ) , - .X ( ropt_net_144 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1380 ( .A ( copt_net_134 ) , - .X ( ropt_net_145 ) ) ; -sky130_fd_sc_hd__buf_4 ropt_h_inst_1381 ( .A ( ropt_net_144 ) , - .X ( ropt_net_146 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1382 ( .A ( copt_net_135 ) , - .X ( ropt_net_147 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 copt_h_inst_1359 ( .A ( ccff_head[0] ) , + .X ( copt_net_122 ) ) ; endmodule @@ -8899,12 +9803,18 @@ input [0:3] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -8914,12 +9824,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -8929,12 +9845,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -8944,12 +9866,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -9010,7 +9938,7 @@ wire [0:0] mux_2level_basis_input4_mem4_2_out ; wire [0:0] mux_2level_basis_input4_mem4_3_out ; sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_1_0_ ( - .A ( mux_2level_basis_input4_mem4_3_out[0] ) , .X ( aps_rename_510_ ) ) ; + .A ( mux_2level_basis_input4_mem4_3_out[0] ) , .X ( out[0] ) ) ; cbx_1__2__local_encoder2to4_16 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , .data ( local_encoder2to4_0_data ) , .data_inv ( local_encoder2to4_0_data_inv ) ) ; @@ -9036,9 +9964,6 @@ cbx_1__2__mux_2level_basis_input4_mem4_35 mux_l2_in_0_ ( .mem ( local_encoder2to4_1_data ) , .mem_inv ( local_encoder2to4_1_data_inv ) , .out ( mux_2level_basis_input4_mem4_3_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_95 ( .A ( BUF_net_96 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_96 ( .A ( aps_rename_510_ ) , - .Y ( BUF_net_96 ) ) ; endmodule @@ -9050,12 +9975,18 @@ input [0:3] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -9065,12 +9996,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -9080,12 +10017,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -9095,12 +10038,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -9161,7 +10110,7 @@ wire [0:0] mux_2level_basis_input4_mem4_2_out ; wire [0:0] mux_2level_basis_input4_mem4_3_out ; sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_1_0_ ( - .A ( mux_2level_basis_input4_mem4_3_out[0] ) , .X ( net_net_94 ) ) ; + .A ( mux_2level_basis_input4_mem4_3_out[0] ) , .X ( aps_rename_510_ ) ) ; cbx_1__2__local_encoder2to4_14 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , .data ( local_encoder2to4_0_data ) , .data_inv ( local_encoder2to4_0_data_inv ) ) ; @@ -9187,7 +10136,9 @@ cbx_1__2__mux_2level_basis_input4_mem4_31 mux_l2_in_0_ ( .mem ( local_encoder2to4_1_data ) , .mem_inv ( local_encoder2to4_1_data_inv ) , .out ( mux_2level_basis_input4_mem4_3_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_94 ( .A ( net_net_94 ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_89 ( .A ( aps_rename_510_ ) , + .Y ( BUF_net_89 ) ) ; +sky130_fd_sc_hd__inv_4 BINV_R_113 ( .A ( BUF_net_89 ) , .Y ( out[0] ) ) ; endmodule @@ -9199,12 +10150,18 @@ input [0:3] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -9214,12 +10171,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -9229,12 +10192,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -9244,12 +10213,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -9336,9 +10311,9 @@ cbx_1__2__mux_2level_basis_input4_mem4_27 mux_l2_in_0_ ( .mem ( local_encoder2to4_1_data ) , .mem_inv ( local_encoder2to4_1_data_inv ) , .out ( mux_2level_basis_input4_mem4_3_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_2 BINV_R_93 ( .A ( aps_rename_509_ ) , - .Y ( BUF_net_93 ) ) ; -sky130_fd_sc_hd__inv_6 BINV_R_111 ( .A ( BUF_net_93 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_87 ( .A ( aps_rename_509_ ) , + .Y ( BUF_net_87 ) ) ; +sky130_fd_sc_hd__inv_4 BINV_R_111 ( .A ( BUF_net_87 ) , .Y ( out[0] ) ) ; endmodule @@ -9350,12 +10325,18 @@ input [0:3] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -9365,12 +10346,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -9380,12 +10367,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -9395,12 +10388,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -9487,9 +10486,9 @@ cbx_1__2__mux_2level_basis_input4_mem4_23 mux_l2_in_0_ ( .mem ( local_encoder2to4_1_data ) , .mem_inv ( local_encoder2to4_1_data_inv ) , .out ( mux_2level_basis_input4_mem4_3_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_2 BINV_R_91 ( .A ( aps_rename_508_ ) , - .Y ( BUF_net_91 ) ) ; -sky130_fd_sc_hd__inv_4 BINV_R_109 ( .A ( BUF_net_91 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_107 ( .A ( BUF_net_108 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_4 BINV_R_108 ( .A ( aps_rename_508_ ) , + .Y ( BUF_net_108 ) ) ; endmodule @@ -9501,12 +10500,18 @@ input [0:3] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -9516,12 +10521,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -9531,12 +10542,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -9546,12 +10563,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -9638,9 +10661,9 @@ cbx_1__2__mux_2level_basis_input4_mem4_19 mux_l2_in_0_ ( .mem ( local_encoder2to4_1_data ) , .mem_inv ( local_encoder2to4_1_data_inv ) , .out ( mux_2level_basis_input4_mem4_3_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_4 BINV_R_121 ( .A ( BUF_net_122 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_4 BINV_R_122 ( .A ( aps_rename_507_ ) , - .Y ( BUF_net_122 ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_85 ( .A ( aps_rename_507_ ) , + .Y ( BUF_net_85 ) ) ; +sky130_fd_sc_hd__inv_4 BINV_R_96 ( .A ( BUF_net_85 ) , .Y ( out[0] ) ) ; endmodule @@ -9652,12 +10675,18 @@ input [0:3] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -9667,12 +10696,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -9682,12 +10717,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -9697,12 +10738,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -9800,12 +10847,18 @@ input [0:3] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -9815,12 +10868,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -9830,12 +10889,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -9845,12 +10910,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -9937,9 +11008,9 @@ cbx_1__2__mux_2level_basis_input4_mem4_11 mux_l2_in_0_ ( .mem ( local_encoder2to4_1_data ) , .mem_inv ( local_encoder2to4_1_data_inv ) , .out ( mux_2level_basis_input4_mem4_3_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_86 ( .A ( BUF_net_87 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_87 ( .A ( aps_rename_506_ ) , - .Y ( BUF_net_87 ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_105 ( .A ( BUF_net_106 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_4 BINV_R_106 ( .A ( aps_rename_506_ ) , + .Y ( BUF_net_106 ) ) ; endmodule @@ -9951,12 +11022,18 @@ input [0:3] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -9966,12 +11043,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -9981,12 +11064,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -9996,12 +11085,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -10062,7 +11157,7 @@ wire [0:0] mux_2level_basis_input4_mem4_2_out ; wire [0:0] mux_2level_basis_input4_mem4_3_out ; sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_1_0_ ( - .A ( mux_2level_basis_input4_mem4_3_out[0] ) , .X ( out[0] ) ) ; + .A ( mux_2level_basis_input4_mem4_3_out[0] ) , .X ( aps_rename_505_ ) ) ; cbx_1__2__local_encoder2to4_2 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , .data ( local_encoder2to4_0_data ) , .data_inv ( local_encoder2to4_0_data_inv ) ) ; @@ -10088,6 +11183,9 @@ cbx_1__2__mux_2level_basis_input4_mem4_7 mux_l2_in_0_ ( .mem ( local_encoder2to4_1_data ) , .mem_inv ( local_encoder2to4_1_data_inv ) , .out ( mux_2level_basis_input4_mem4_3_out ) , .p0 ( p0 ) ) ; +sky130_fd_sc_hd__inv_12 BINV_R_103 ( .A ( BUF_net_104 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_4 BINV_R_104 ( .A ( aps_rename_505_ ) , + .Y ( BUF_net_104 ) ) ; endmodule @@ -10099,12 +11197,18 @@ input [0:3] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -10114,12 +11218,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -10129,12 +11239,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -10144,12 +11260,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -10210,7 +11332,7 @@ wire [0:0] mux_2level_basis_input4_mem4_2_out ; wire [0:0] mux_2level_basis_input4_mem4_3_out ; sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_1_0_ ( - .A ( mux_2level_basis_input4_mem4_3_out[0] ) , .X ( aps_rename_505_ ) ) ; + .A ( mux_2level_basis_input4_mem4_3_out[0] ) , .X ( out[0] ) ) ; cbx_1__2__local_encoder2to4_0 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , .data ( local_encoder2to4_0_data ) , .data_inv ( local_encoder2to4_0_data_inv ) ) ; @@ -10236,9 +11358,6 @@ cbx_1__2__mux_2level_basis_input4_mem4_3 mux_l2_in_0_ ( .mem ( local_encoder2to4_1_data ) , .mem_inv ( local_encoder2to4_1_data_inv ) , .out ( mux_2level_basis_input4_mem4_3_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_84 ( .A ( BUF_net_85 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_85 ( .A ( aps_rename_505_ ) , - .Y ( BUF_net_85 ) ) ; endmodule @@ -10345,7 +11464,7 @@ cbx_1__2__mux_2level_size12_0 mux_bottom_ipin_0 ( .sram ( mux_2level_size12_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 , SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) , - .out ( top_grid_pin_0_ ) , .p0 ( optlc_net_126 ) ) ; + .out ( top_grid_pin_0_ ) , .p0 ( optlc_net_120 ) ) ; cbx_1__2__mux_2level_size12_1 mux_top_ipin_0 ( .in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[4] , chanx_left_out[4] , chanx_right_out[7] , chanx_left_out[7] , @@ -10354,7 +11473,7 @@ cbx_1__2__mux_2level_size12_1 mux_top_ipin_0 ( .sram ( mux_2level_size12_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 , SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 } ) , - .out ( bottom_grid_pin_0_ ) , .p0 ( optlc_net_127 ) ) ; + .out ( bottom_grid_pin_0_ ) , .p0 ( optlc_net_119 ) ) ; cbx_1__2__mux_2level_size12_2 mux_top_ipin_2 ( .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[3] , chanx_left_out[3] , chanx_right_out[9] , chanx_left_out[9] , @@ -10363,7 +11482,7 @@ cbx_1__2__mux_2level_size12_2 mux_top_ipin_2 ( .sram ( mux_2level_size12_2_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_9 , SYNOPSYS_UNCONNECTED_10 , SYNOPSYS_UNCONNECTED_11 , SYNOPSYS_UNCONNECTED_12 } ) , - .out ( bottom_grid_pin_2_ ) , .p0 ( optlc_net_126 ) ) ; + .out ( bottom_grid_pin_2_ ) , .p0 ( optlc_net_118 ) ) ; cbx_1__2__mux_2level_size12_3 mux_top_ipin_4 ( .in ( { chanx_right_out[2] , chanx_left_out[2] , chanx_right_out[5] , chanx_left_out[5] , chanx_right_out[11] , chanx_left_out[11] , @@ -10372,7 +11491,7 @@ cbx_1__2__mux_2level_size12_3 mux_top_ipin_4 ( .sram ( mux_2level_size12_3_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 , SYNOPSYS_UNCONNECTED_15 , SYNOPSYS_UNCONNECTED_16 } ) , - .out ( bottom_grid_pin_4_ ) , .p0 ( optlc_net_125 ) ) ; + .out ( bottom_grid_pin_4_ ) , .p0 ( optlc_net_116 ) ) ; cbx_1__2__mux_2level_size12_4 mux_top_ipin_6 ( .in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[4] , chanx_left_out[4] , chanx_right_out[7] , chanx_left_out[7] , @@ -10381,7 +11500,7 @@ cbx_1__2__mux_2level_size12_4 mux_top_ipin_6 ( .sram ( mux_2level_size12_4_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_17 , SYNOPSYS_UNCONNECTED_18 , SYNOPSYS_UNCONNECTED_19 , SYNOPSYS_UNCONNECTED_20 } ) , - .out ( bottom_grid_pin_6_ ) , .p0 ( optlc_net_128 ) ) ; + .out ( bottom_grid_pin_6_ ) , .p0 ( optlc_net_119 ) ) ; cbx_1__2__mux_2level_size12_5 mux_top_ipin_8 ( .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[3] , chanx_left_out[3] , chanx_right_out[9] , chanx_left_out[9] , @@ -10390,8 +11509,7 @@ cbx_1__2__mux_2level_size12_5 mux_top_ipin_8 ( .sram ( mux_2level_size12_5_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_21 , SYNOPSYS_UNCONNECTED_22 , SYNOPSYS_UNCONNECTED_23 , SYNOPSYS_UNCONNECTED_24 } ) , - .out ( { ropt_net_150 } ) , - .p0 ( optlc_net_126 ) ) ; + .out ( bottom_grid_pin_8_ ) , .p0 ( optlc_net_117 ) ) ; cbx_1__2__mux_2level_size12_6 mux_top_ipin_10 ( .in ( { chanx_right_out[2] , chanx_left_out[2] , chanx_right_out[5] , chanx_left_out[5] , chanx_right_out[11] , chanx_left_out[11] , @@ -10400,7 +11518,7 @@ cbx_1__2__mux_2level_size12_6 mux_top_ipin_10 ( .sram ( mux_2level_size12_6_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_25 , SYNOPSYS_UNCONNECTED_26 , SYNOPSYS_UNCONNECTED_27 , SYNOPSYS_UNCONNECTED_28 } ) , - .out ( bottom_grid_pin_10_ ) , .p0 ( optlc_net_125 ) ) ; + .out ( bottom_grid_pin_10_ ) , .p0 ( optlc_net_116 ) ) ; cbx_1__2__mux_2level_size12_7 mux_top_ipin_12 ( .in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[4] , chanx_left_out[4] , chanx_right_out[7] , chanx_left_out[7] , @@ -10409,7 +11527,7 @@ cbx_1__2__mux_2level_size12_7 mux_top_ipin_12 ( .sram ( mux_2level_size12_7_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_29 , SYNOPSYS_UNCONNECTED_30 , SYNOPSYS_UNCONNECTED_31 , SYNOPSYS_UNCONNECTED_32 } ) , - .out ( bottom_grid_pin_12_ ) , .p0 ( optlc_net_127 ) ) ; + .out ( bottom_grid_pin_12_ ) , .p0 ( optlc_net_120 ) ) ; cbx_1__2__mux_2level_size12 mux_top_ipin_14 ( .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[3] , chanx_left_out[3] , chanx_right_out[9] , chanx_left_out[9] , @@ -10418,7 +11536,8 @@ cbx_1__2__mux_2level_size12 mux_top_ipin_14 ( .sram ( mux_2level_size12_8_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_33 , SYNOPSYS_UNCONNECTED_34 , SYNOPSYS_UNCONNECTED_35 , SYNOPSYS_UNCONNECTED_36 } ) , - .out ( bottom_grid_pin_14_ ) , .p0 ( optlc_net_126 ) ) ; + .out ( { ropt_net_123 } ) , + .p0 ( optlc_net_118 ) ) ; cbx_1__2__mux_2level_size12_mem_0 mem_bottom_ipin_0 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( mux_2level_size12_mem_0_ccff_tail ) , @@ -10471,8 +11590,7 @@ cbx_1__2__mux_2level_size10_0 mux_top_ipin_1 ( .sram ( mux_2level_size10_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_37 , SYNOPSYS_UNCONNECTED_38 , SYNOPSYS_UNCONNECTED_39 , SYNOPSYS_UNCONNECTED_40 } ) , - .out ( { ropt_net_149 } ) , - .p0 ( optlc_net_127 ) ) ; + .out ( bottom_grid_pin_1_ ) , .p0 ( optlc_net_119 ) ) ; cbx_1__2__mux_2level_size10_1 mux_top_ipin_3 ( .in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[4] , chanx_left_out[4] , chanx_right_out[10] , chanx_left_out[10] , @@ -10481,7 +11599,7 @@ cbx_1__2__mux_2level_size10_1 mux_top_ipin_3 ( .sram ( mux_2level_size10_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_41 , SYNOPSYS_UNCONNECTED_42 , SYNOPSYS_UNCONNECTED_43 , SYNOPSYS_UNCONNECTED_44 } ) , - .out ( bottom_grid_pin_3_ ) , .p0 ( optlc_net_125 ) ) ; + .out ( bottom_grid_pin_3_ ) , .p0 ( optlc_net_120 ) ) ; cbx_1__2__mux_2level_size10_2 mux_top_ipin_5 ( .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[3] , chanx_left_out[3] , chanx_right_out[6] , chanx_left_out[6] , @@ -10490,7 +11608,7 @@ cbx_1__2__mux_2level_size10_2 mux_top_ipin_5 ( .sram ( mux_2level_size10_2_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_45 , SYNOPSYS_UNCONNECTED_46 , SYNOPSYS_UNCONNECTED_47 , SYNOPSYS_UNCONNECTED_48 } ) , - .out ( bottom_grid_pin_5_ ) , .p0 ( optlc_net_128 ) ) ; + .out ( bottom_grid_pin_5_ ) , .p0 ( optlc_net_120 ) ) ; cbx_1__2__mux_2level_size10_3 mux_top_ipin_7 ( .in ( { chanx_right_out[2] , chanx_left_out[2] , chanx_right_out[5] , chanx_left_out[5] , chanx_right_out[8] , chanx_left_out[8] , @@ -10499,7 +11617,7 @@ cbx_1__2__mux_2level_size10_3 mux_top_ipin_7 ( .sram ( mux_2level_size10_3_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_49 , SYNOPSYS_UNCONNECTED_50 , SYNOPSYS_UNCONNECTED_51 , SYNOPSYS_UNCONNECTED_52 } ) , - .out ( bottom_grid_pin_7_ ) , .p0 ( optlc_net_127 ) ) ; + .out ( bottom_grid_pin_7_ ) , .p0 ( optlc_net_116 ) ) ; cbx_1__2__mux_2level_size10_4 mux_top_ipin_9 ( .in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[4] , chanx_left_out[4] , chanx_right_out[10] , chanx_left_out[10] , @@ -10508,7 +11626,7 @@ cbx_1__2__mux_2level_size10_4 mux_top_ipin_9 ( .sram ( mux_2level_size10_4_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_53 , SYNOPSYS_UNCONNECTED_54 , SYNOPSYS_UNCONNECTED_55 , SYNOPSYS_UNCONNECTED_56 } ) , - .out ( bottom_grid_pin_9_ ) , .p0 ( optlc_net_125 ) ) ; + .out ( bottom_grid_pin_9_ ) , .p0 ( optlc_net_120 ) ) ; cbx_1__2__mux_2level_size10_5 mux_top_ipin_11 ( .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[3] , chanx_left_out[3] , chanx_right_out[12] , chanx_left_out[12] , @@ -10517,8 +11635,7 @@ cbx_1__2__mux_2level_size10_5 mux_top_ipin_11 ( .sram ( mux_2level_size10_5_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_57 , SYNOPSYS_UNCONNECTED_58 , SYNOPSYS_UNCONNECTED_59 , SYNOPSYS_UNCONNECTED_60 } ) , - .out ( { ropt_net_148 } ) , - .p0 ( optlc_net_126 ) ) ; + .out ( bottom_grid_pin_11_ ) , .p0 ( optlc_net_117 ) ) ; cbx_1__2__mux_2level_size10_6 mux_top_ipin_13 ( .in ( { chanx_right_out[2] , chanx_left_out[2] , chanx_right_out[5] , chanx_left_out[5] , chanx_right_out[14] , chanx_left_out[14] , @@ -10527,7 +11644,7 @@ cbx_1__2__mux_2level_size10_6 mux_top_ipin_13 ( .sram ( mux_2level_size10_6_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_61 , SYNOPSYS_UNCONNECTED_62 , SYNOPSYS_UNCONNECTED_63 , SYNOPSYS_UNCONNECTED_64 } ) , - .out ( bottom_grid_pin_13_ ) , .p0 ( optlc_net_127 ) ) ; + .out ( bottom_grid_pin_13_ ) , .p0 ( optlc_net_119 ) ) ; cbx_1__2__mux_2level_size10 mux_top_ipin_15 ( .in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[4] , chanx_left_out[4] , chanx_right_out[7] , chanx_left_out[7] , @@ -10536,7 +11653,7 @@ cbx_1__2__mux_2level_size10 mux_top_ipin_15 ( .sram ( mux_2level_size10_7_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_65 , SYNOPSYS_UNCONNECTED_66 , SYNOPSYS_UNCONNECTED_67 , SYNOPSYS_UNCONNECTED_68 } ) , - .out ( bottom_grid_pin_15_ ) , .p0 ( optlc_net_125 ) ) ; + .out ( bottom_grid_pin_15_ ) , .p0 ( optlc_net_117 ) ) ; cbx_1__2__mux_2level_size10_mem_0 mem_top_ipin_1 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( mux_2level_size12_mem_1_ccff_tail ) , @@ -10587,16 +11704,16 @@ cbx_1__2__logical_tile_io_mode_io_ logical_tile_io_mode_io__0 ( .io_inpad ( bottom_width_0_height_0__pin_1_lower ) , .ccff_tail ( ccff_tail ) ) ; sky130_fd_sc_hd__buf_8 pReset_FTB00 ( .A ( pReset_W_in ) , .X ( pReset[0] ) ) ; -sky130_fd_sc_hd__buf_4 pReset_W_FTB01 ( .A ( pReset_W_in ) , +sky130_fd_sc_hd__bufbuf_16 pReset_W_FTB01 ( .A ( pReset_W_in ) , .X ( pReset_W_out ) ) ; -sky130_fd_sc_hd__bufbuf_16 pReset_S_FTB01 ( .A ( pReset_W_in ) , +sky130_fd_sc_hd__buf_4 pReset_S_FTB01 ( .A ( pReset_W_in ) , .X ( pReset_S_out ) ) ; -sky130_fd_sc_hd__buf_1 pReset_E_FTB01 ( .A ( pReset_W_in ) , - .X ( aps_rename_517_ ) ) ; -sky130_fd_sc_hd__buf_1 prog_clk_0_FTB00 ( .A ( prog_clk_0_S_in ) , +sky130_fd_sc_hd__buf_4 pReset_E_FTB01 ( .A ( pReset_W_in ) , + .X ( pReset_E_out ) ) ; +sky130_fd_sc_hd__buf_2 prog_clk_0_FTB00 ( .A ( prog_clk_0_S_in ) , .X ( prog_clk[0] ) ) ; sky130_fd_sc_hd__clkbuf_1 prog_clk_0_W_FTB01 ( .A ( prog_clk_0_S_in ) , - .X ( ctsbuf_net_1129 ) ) ; + .X ( ctsbuf_net_1121 ) ) ; sky130_fd_sc_hd__buf_8 FTB_19__18 ( .A ( chanx_left_in[0] ) , .X ( chanx_right_out[0] ) ) ; sky130_fd_sc_hd__buf_8 FTB_20__19 ( .A ( chanx_left_in[1] ) , @@ -10722,24 +11839,20 @@ sky130_fd_sc_hd__buf_6 FTB_79__78 ( .X ( bottom_width_0_height_0__pin_1_upper[0] ) ) ; sky130_fd_sc_hd__buf_6 FTB_80__79 ( .A ( SC_IN_TOP ) , .X ( SC_OUT_BOT ) ) ; sky130_fd_sc_hd__buf_6 FTB_81__80 ( .A ( SC_IN_BOT ) , .X ( SC_OUT_TOP ) ) ; -sky130_fd_sc_hd__conb_1 optlc_127 ( .LO ( SYNOPSYS_UNCONNECTED_69 ) , - .HI ( optlc_net_125 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_129 ( .LO ( SYNOPSYS_UNCONNECTED_70 ) , - .HI ( optlc_net_126 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_131 ( .LO ( SYNOPSYS_UNCONNECTED_71 ) , - .HI ( optlc_net_127 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_133 ( .LO ( SYNOPSYS_UNCONNECTED_72 ) , - .HI ( optlc_net_128 ) ) ; -sky130_fd_sc_hd__buf_6 ZBUF_6_f_inst_134 ( .A ( aps_rename_517_ ) , - .X ( pReset_E_out ) ) ; -sky130_fd_sc_hd__buf_6 ropt_mt_inst_1386 ( .A ( ropt_net_148 ) , - .X ( bottom_grid_pin_11_[0] ) ) ; -sky130_fd_sc_hd__buf_6 cts_buf_3651274 ( .A ( ctsbuf_net_1129 ) , +sky130_fd_sc_hd__conb_1 optlc_117 ( .LO ( SYNOPSYS_UNCONNECTED_69 ) , + .HI ( optlc_net_116 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_119 ( .LO ( SYNOPSYS_UNCONNECTED_70 ) , + .HI ( optlc_net_117 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_122 ( .LO ( SYNOPSYS_UNCONNECTED_71 ) , + .HI ( optlc_net_118 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_124 ( .LO ( SYNOPSYS_UNCONNECTED_72 ) , + .HI ( optlc_net_119 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_126 ( .LO ( SYNOPSYS_UNCONNECTED_73 ) , + .HI ( optlc_net_120 ) ) ; +sky130_fd_sc_hd__buf_6 ropt_mt_inst_1360 ( .A ( ropt_net_123 ) , + .X ( bottom_grid_pin_14_[0] ) ) ; +sky130_fd_sc_hd__buf_6 cts_buf_3651266 ( .A ( ctsbuf_net_1121 ) , .X ( prog_clk_0_W_out ) ) ; -sky130_fd_sc_hd__buf_6 ropt_mt_inst_1387 ( .A ( ropt_net_149 ) , - .X ( bottom_grid_pin_1_[0] ) ) ; -sky130_fd_sc_hd__buf_6 ropt_mt_inst_1388 ( .A ( ropt_net_150 ) , - .X ( bottom_grid_pin_8_[0] ) ) ; endmodule @@ -10751,7 +11864,7 @@ input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -wire copt_net_156 ; +wire copt_net_128 ; sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; @@ -10760,14 +11873,16 @@ sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( copt_net_156 ) ) ; + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( copt_net_128 ) ) ; sky130_fd_sc_hd__buf_6 FTB_16__15 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1394 ( .A ( copt_net_154 ) , - .X ( copt_net_152 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1395 ( .A ( copt_net_152 ) , +sky130_fd_sc_hd__buf_1 copt_h_inst_1361 ( .A ( copt_net_127 ) , .X ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1396 ( .A ( copt_net_156 ) , - .X ( copt_net_154 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1362 ( .A ( copt_net_128 ) , + .X ( copt_net_126 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1363 ( .A ( copt_net_130 ) , + .X ( copt_net_127 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1366 ( .A ( copt_net_126 ) , + .X ( copt_net_130 ) ) ; endmodule @@ -10917,9 +12032,13 @@ input [0:1] mem ; input [0:1] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -10931,12 +12050,18 @@ input [0:3] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -10946,12 +12071,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -10961,12 +12092,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -11062,9 +12199,13 @@ input [0:1] mem ; input [0:1] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -11076,12 +12217,18 @@ input [0:3] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -11091,12 +12238,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -11106,12 +12259,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -11172,7 +12331,7 @@ wire [0:0] mux_2level_basis_input4_mem4_1_out ; wire [0:0] mux_2level_basis_input4_mem4_2_out ; sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_1_0_ ( - .A ( mux_2level_basis_input4_mem4_2_out[0] ) , .X ( aps_rename_514_ ) ) ; + .A ( mux_2level_basis_input4_mem4_2_out[0] ) , .X ( net_net_90 ) ) ; cbx_1__1__local_encoder2to4_28 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , .data ( local_encoder2to4_0_data ) , .data_inv ( local_encoder2to4_0_data_inv ) ) ; @@ -11198,9 +12357,7 @@ cbx_1__1__mux_2level_basis_input2_mem2_6 mux_l1_in_2_ ( .in ( in[8:9] ) , .mem ( local_encoder2to4_0_data[0:1] ) , .mem_inv ( local_encoder2to4_0_data_inv[0:1] ) , .out ( mux_2level_basis_input2_mem2_0_out ) ) ; -sky130_fd_sc_hd__inv_6 BINV_R_139 ( .A ( BUF_net_140 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_140 ( .A ( aps_rename_514_ ) , - .Y ( BUF_net_140 ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_90 ( .A ( net_net_90 ) , .X ( out[0] ) ) ; endmodule @@ -11210,9 +12367,13 @@ input [0:1] mem ; input [0:1] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -11224,12 +12385,18 @@ input [0:3] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -11239,12 +12406,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -11254,12 +12427,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -11320,7 +12499,7 @@ wire [0:0] mux_2level_basis_input4_mem4_1_out ; wire [0:0] mux_2level_basis_input4_mem4_2_out ; sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_1_0_ ( - .A ( mux_2level_basis_input4_mem4_2_out[0] ) , .X ( aps_rename_513_ ) ) ; + .A ( mux_2level_basis_input4_mem4_2_out[0] ) , .X ( aps_rename_509_ ) ) ; cbx_1__1__local_encoder2to4_26 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , .data ( local_encoder2to4_0_data ) , .data_inv ( local_encoder2to4_0_data_inv ) ) ; @@ -11346,9 +12525,9 @@ cbx_1__1__mux_2level_basis_input2_mem2_5 mux_l1_in_2_ ( .in ( in[8:9] ) , .mem ( local_encoder2to4_0_data[0:1] ) , .mem_inv ( local_encoder2to4_0_data_inv[0:1] ) , .out ( mux_2level_basis_input2_mem2_0_out ) ) ; -sky130_fd_sc_hd__inv_6 BINV_R_137 ( .A ( BUF_net_138 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_138 ( .A ( aps_rename_513_ ) , - .Y ( BUF_net_138 ) ) ; +sky130_fd_sc_hd__inv_4 BINV_R_111 ( .A ( BUF_net_112 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_4 BINV_R_112 ( .A ( aps_rename_509_ ) , + .Y ( BUF_net_112 ) ) ; endmodule @@ -11358,9 +12537,13 @@ input [0:1] mem ; input [0:1] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -11372,12 +12555,18 @@ input [0:3] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -11387,12 +12576,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -11402,12 +12597,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -11503,9 +12704,13 @@ input [0:1] mem ; input [0:1] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -11517,12 +12722,18 @@ input [0:3] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -11532,12 +12743,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -11547,12 +12764,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -11612,7 +12835,7 @@ wire [0:0] mux_2level_basis_input4_mem4_0_out ; wire [0:0] mux_2level_basis_input4_mem4_1_out ; wire [0:0] mux_2level_basis_input4_mem4_2_out ; -sky130_fd_sc_hd__bufbuf_16 sky130_fd_sc_hd__buf_1_0_ ( +sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_1_0_ ( .A ( mux_2level_basis_input4_mem4_2_out[0] ) , .X ( out[0] ) ) ; cbx_1__1__local_encoder2to4_22 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , .data ( local_encoder2to4_0_data ) , @@ -11648,9 +12871,13 @@ input [0:1] mem ; input [0:1] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -11662,12 +12889,18 @@ input [0:3] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -11677,12 +12910,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -11692,12 +12931,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -11757,8 +13002,8 @@ wire [0:0] mux_2level_basis_input4_mem4_0_out ; wire [0:0] mux_2level_basis_input4_mem4_1_out ; wire [0:0] mux_2level_basis_input4_mem4_2_out ; -sky130_fd_sc_hd__bufbuf_16 sky130_fd_sc_hd__buf_1_0_ ( - .A ( mux_2level_basis_input4_mem4_2_out[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_1_0_ ( + .A ( mux_2level_basis_input4_mem4_2_out[0] ) , .X ( aps_rename_508_ ) ) ; cbx_1__1__local_encoder2to4_20 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , .data ( local_encoder2to4_0_data ) , .data_inv ( local_encoder2to4_0_data_inv ) ) ; @@ -11784,6 +13029,9 @@ cbx_1__1__mux_2level_basis_input2_mem2_2 mux_l1_in_2_ ( .in ( in[8:9] ) , .mem ( local_encoder2to4_0_data[0:1] ) , .mem_inv ( local_encoder2to4_0_data_inv[0:1] ) , .out ( mux_2level_basis_input2_mem2_0_out ) ) ; +sky130_fd_sc_hd__inv_4 BINV_R_109 ( .A ( BUF_net_110 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_4 BINV_R_110 ( .A ( aps_rename_508_ ) , + .Y ( BUF_net_110 ) ) ; endmodule @@ -11793,9 +13041,13 @@ input [0:1] mem ; input [0:1] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -11807,12 +13059,18 @@ input [0:3] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -11822,12 +13080,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -11837,12 +13101,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -11903,7 +13173,7 @@ wire [0:0] mux_2level_basis_input4_mem4_1_out ; wire [0:0] mux_2level_basis_input4_mem4_2_out ; sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_1_0_ ( - .A ( mux_2level_basis_input4_mem4_2_out[0] ) , .X ( net_net_97 ) ) ; + .A ( mux_2level_basis_input4_mem4_2_out[0] ) , .X ( out[0] ) ) ; cbx_1__1__local_encoder2to4_18 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , .data ( local_encoder2to4_0_data ) , .data_inv ( local_encoder2to4_0_data_inv ) ) ; @@ -11929,7 +13199,6 @@ cbx_1__1__mux_2level_basis_input2_mem2_1 mux_l1_in_2_ ( .in ( in[8:9] ) , .mem ( local_encoder2to4_0_data[0:1] ) , .mem_inv ( local_encoder2to4_0_data_inv[0:1] ) , .out ( mux_2level_basis_input2_mem2_0_out ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_97 ( .A ( net_net_97 ) , .X ( out[0] ) ) ; endmodule @@ -11939,9 +13208,13 @@ input [0:1] mem ; input [0:1] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -11953,12 +13226,18 @@ input [0:3] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -11968,12 +13247,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -11983,12 +13268,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -12049,7 +13340,7 @@ wire [0:0] mux_2level_basis_input4_mem4_1_out ; wire [0:0] mux_2level_basis_input4_mem4_2_out ; sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_1_0_ ( - .A ( mux_2level_basis_input4_mem4_2_out[0] ) , .X ( aps_rename_512_ ) ) ; + .A ( mux_2level_basis_input4_mem4_2_out[0] ) , .X ( out[0] ) ) ; cbx_1__1__local_encoder2to4_16 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , .data ( local_encoder2to4_0_data ) , .data_inv ( local_encoder2to4_0_data_inv ) ) ; @@ -12075,9 +13366,6 @@ cbx_1__1__mux_2level_basis_input2_mem2_0 mux_l1_in_2_ ( .in ( in[8:9] ) , .mem ( local_encoder2to4_0_data[0:1] ) , .mem_inv ( local_encoder2to4_0_data_inv[0:1] ) , .out ( mux_2level_basis_input2_mem2_0_out ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_95 ( .A ( BUF_net_96 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_96 ( .A ( aps_rename_512_ ) , - .Y ( BUF_net_96 ) ) ; endmodule @@ -12229,7 +13517,7 @@ input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ropt_net_179 ) , +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( copt_net_121 ) , .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; @@ -12238,26 +13526,20 @@ sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__buf_1 FTB_1__0 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1388 ( .A ( copt_net_147 ) , - .X ( copt_net_146 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1389 ( .A ( copt_net_149 ) , - .X ( copt_net_147 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1390 ( .A ( ropt_net_182 ) , - .X ( copt_net_148 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1391 ( .A ( ropt_net_181 ) , - .X ( copt_net_149 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1392 ( .A ( ccff_head[0] ) , - .X ( copt_net_150 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 copt_h_inst_1397 ( .A ( copt_net_146 ) , - .X ( copt_net_155 ) ) ; -sky130_fd_sc_hd__buf_1 ropt_h_inst_1420 ( .A ( copt_net_155 ) , - .X ( ropt_net_179 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1421 ( .A ( copt_net_150 ) , - .X ( ropt_net_180 ) ) ; -sky130_fd_sc_hd__buf_1 ropt_h_inst_1422 ( .A ( copt_net_148 ) , - .X ( ropt_net_181 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1423 ( .A ( ropt_net_180 ) , - .X ( ropt_net_182 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1354 ( .A ( copt_net_119 ) , + .X ( copt_net_118 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1355 ( .A ( copt_net_123 ) , + .X ( copt_net_119 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1356 ( .A ( ropt_net_139 ) , + .X ( copt_net_120 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1357 ( .A ( copt_net_122 ) , + .X ( copt_net_121 ) ) ; +sky130_fd_sc_hd__buf_2 copt_h_inst_1358 ( .A ( copt_net_120 ) , + .X ( copt_net_122 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1359 ( .A ( ccff_head[0] ) , + .X ( copt_net_123 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1376 ( .A ( copt_net_118 ) , + .X ( ropt_net_139 ) ) ; endmodule @@ -12269,12 +13551,18 @@ input [0:3] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -12284,12 +13572,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -12299,12 +13593,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -12314,12 +13614,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -12380,7 +13686,7 @@ wire [0:0] mux_2level_basis_input4_mem4_2_out ; wire [0:0] mux_2level_basis_input4_mem4_3_out ; sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_1_0_ ( - .A ( mux_2level_basis_input4_mem4_3_out[0] ) , .X ( aps_rename_511_ ) ) ; + .A ( mux_2level_basis_input4_mem4_3_out[0] ) , .X ( aps_rename_507_ ) ) ; cbx_1__1__local_encoder2to4_14 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , .data ( local_encoder2to4_0_data ) , .data_inv ( local_encoder2to4_0_data_inv ) ) ; @@ -12406,9 +13712,9 @@ cbx_1__1__mux_2level_basis_input4_mem4_31 mux_l2_in_0_ ( .mem ( local_encoder2to4_1_data ) , .mem_inv ( local_encoder2to4_1_data_inv ) , .out ( mux_2level_basis_input4_mem4_3_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_6 BINV_R_135 ( .A ( BUF_net_136 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_136 ( .A ( aps_rename_511_ ) , - .Y ( BUF_net_136 ) ) ; +sky130_fd_sc_hd__inv_4 BINV_R_84 ( .A ( BUF_net_85 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_4 BINV_R_85 ( .A ( aps_rename_507_ ) , + .Y ( BUF_net_85 ) ) ; endmodule @@ -12420,12 +13726,18 @@ input [0:3] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -12435,12 +13747,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -12450,12 +13768,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -12465,12 +13789,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -12531,7 +13861,7 @@ wire [0:0] mux_2level_basis_input4_mem4_2_out ; wire [0:0] mux_2level_basis_input4_mem4_3_out ; sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_1_0_ ( - .A ( mux_2level_basis_input4_mem4_3_out[0] ) , .X ( aps_rename_510_ ) ) ; + .A ( mux_2level_basis_input4_mem4_3_out[0] ) , .X ( aps_rename_506_ ) ) ; cbx_1__1__local_encoder2to4_12 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , .data ( local_encoder2to4_0_data ) , .data_inv ( local_encoder2to4_0_data_inv ) ) ; @@ -12557,9 +13887,9 @@ cbx_1__1__mux_2level_basis_input4_mem4_27 mux_l2_in_0_ ( .mem ( local_encoder2to4_1_data ) , .mem_inv ( local_encoder2to4_1_data_inv ) , .out ( mux_2level_basis_input4_mem4_3_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_6 BINV_R_133 ( .A ( BUF_net_134 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_134 ( .A ( aps_rename_510_ ) , - .Y ( BUF_net_134 ) ) ; +sky130_fd_sc_hd__inv_4 BINV_R_107 ( .A ( BUF_net_108 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_4 BINV_R_108 ( .A ( aps_rename_506_ ) , + .Y ( BUF_net_108 ) ) ; endmodule @@ -12571,12 +13901,18 @@ input [0:3] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -12586,12 +13922,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -12601,12 +13943,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -12616,12 +13964,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -12682,7 +14036,7 @@ wire [0:0] mux_2level_basis_input4_mem4_2_out ; wire [0:0] mux_2level_basis_input4_mem4_3_out ; sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_1_0_ ( - .A ( mux_2level_basis_input4_mem4_3_out[0] ) , .X ( aps_rename_509_ ) ) ; + .A ( mux_2level_basis_input4_mem4_3_out[0] ) , .X ( out[0] ) ) ; cbx_1__1__local_encoder2to4_10 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , .data ( local_encoder2to4_0_data ) , .data_inv ( local_encoder2to4_0_data_inv ) ) ; @@ -12708,9 +14062,6 @@ cbx_1__1__mux_2level_basis_input4_mem4_23 mux_l2_in_0_ ( .mem ( local_encoder2to4_1_data ) , .mem_inv ( local_encoder2to4_1_data_inv ) , .out ( mux_2level_basis_input4_mem4_3_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_6 BINV_R_131 ( .A ( BUF_net_132 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_132 ( .A ( aps_rename_509_ ) , - .Y ( BUF_net_132 ) ) ; endmodule @@ -12722,12 +14073,18 @@ input [0:3] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -12737,12 +14094,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -12752,12 +14115,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -12767,12 +14136,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -12833,7 +14208,7 @@ wire [0:0] mux_2level_basis_input4_mem4_2_out ; wire [0:0] mux_2level_basis_input4_mem4_3_out ; sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_1_0_ ( - .A ( mux_2level_basis_input4_mem4_3_out[0] ) , .X ( aps_rename_508_ ) ) ; + .A ( mux_2level_basis_input4_mem4_3_out[0] ) , .X ( aps_rename_505_ ) ) ; cbx_1__1__local_encoder2to4_8 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , .data ( local_encoder2to4_0_data ) , .data_inv ( local_encoder2to4_0_data_inv ) ) ; @@ -12859,9 +14234,9 @@ cbx_1__1__mux_2level_basis_input4_mem4_19 mux_l2_in_0_ ( .mem ( local_encoder2to4_1_data ) , .mem_inv ( local_encoder2to4_1_data_inv ) , .out ( mux_2level_basis_input4_mem4_3_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_6 BINV_R_129 ( .A ( BUF_net_130 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_130 ( .A ( aps_rename_508_ ) , - .Y ( BUF_net_130 ) ) ; +sky130_fd_sc_hd__inv_4 BINV_R_80 ( .A ( BUF_net_81 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_4 BINV_R_81 ( .A ( aps_rename_505_ ) , + .Y ( BUF_net_81 ) ) ; endmodule @@ -12873,12 +14248,18 @@ input [0:3] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -12888,12 +14269,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -12903,12 +14290,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -12918,12 +14311,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -12984,7 +14383,7 @@ wire [0:0] mux_2level_basis_input4_mem4_2_out ; wire [0:0] mux_2level_basis_input4_mem4_3_out ; sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_1_0_ ( - .A ( mux_2level_basis_input4_mem4_3_out[0] ) , .X ( aps_rename_507_ ) ) ; + .A ( mux_2level_basis_input4_mem4_3_out[0] ) , .X ( out[0] ) ) ; cbx_1__1__local_encoder2to4_6 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , .data ( local_encoder2to4_0_data ) , .data_inv ( local_encoder2to4_0_data_inv ) ) ; @@ -13010,9 +14409,6 @@ cbx_1__1__mux_2level_basis_input4_mem4_15 mux_l2_in_0_ ( .mem ( local_encoder2to4_1_data ) , .mem_inv ( local_encoder2to4_1_data_inv ) , .out ( mux_2level_basis_input4_mem4_3_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_85 ( .A ( BUF_net_86 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_86 ( .A ( aps_rename_507_ ) , - .Y ( BUF_net_86 ) ) ; endmodule @@ -13024,12 +14420,18 @@ input [0:3] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -13039,12 +14441,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -13054,12 +14462,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -13069,12 +14483,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -13134,8 +14554,8 @@ wire [0:0] mux_2level_basis_input4_mem4_1_out ; wire [0:0] mux_2level_basis_input4_mem4_2_out ; wire [0:0] mux_2level_basis_input4_mem4_3_out ; -sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_1_0_ ( - .A ( mux_2level_basis_input4_mem4_3_out[0] ) , .X ( net_net_84 ) ) ; +sky130_fd_sc_hd__bufbuf_16 sky130_fd_sc_hd__buf_1_0_ ( + .A ( mux_2level_basis_input4_mem4_3_out[0] ) , .X ( out[0] ) ) ; cbx_1__1__local_encoder2to4_4 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , .data ( local_encoder2to4_0_data ) , .data_inv ( local_encoder2to4_0_data_inv ) ) ; @@ -13161,7 +14581,6 @@ cbx_1__1__mux_2level_basis_input4_mem4_11 mux_l2_in_0_ ( .mem ( local_encoder2to4_1_data ) , .mem_inv ( local_encoder2to4_1_data_inv ) , .out ( mux_2level_basis_input4_mem4_3_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_84 ( .A ( net_net_84 ) , .X ( out[0] ) ) ; endmodule @@ -13173,12 +14592,18 @@ input [0:3] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -13188,12 +14613,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -13203,12 +14634,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -13218,12 +14655,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -13284,7 +14727,7 @@ wire [0:0] mux_2level_basis_input4_mem4_2_out ; wire [0:0] mux_2level_basis_input4_mem4_3_out ; sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_1_0_ ( - .A ( mux_2level_basis_input4_mem4_3_out[0] ) , .X ( aps_rename_506_ ) ) ; + .A ( mux_2level_basis_input4_mem4_3_out[0] ) , .X ( out[0] ) ) ; cbx_1__1__local_encoder2to4_2 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , .data ( local_encoder2to4_0_data ) , .data_inv ( local_encoder2to4_0_data_inv ) ) ; @@ -13310,9 +14753,6 @@ cbx_1__1__mux_2level_basis_input4_mem4_7 mux_l2_in_0_ ( .mem ( local_encoder2to4_1_data ) , .mem_inv ( local_encoder2to4_1_data_inv ) , .out ( mux_2level_basis_input4_mem4_3_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_82 ( .A ( BUF_net_83 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_83 ( .A ( aps_rename_506_ ) , - .Y ( BUF_net_83 ) ) ; endmodule @@ -13324,12 +14764,18 @@ input [0:3] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -13339,12 +14785,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -13354,12 +14806,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -13369,12 +14827,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -13435,7 +14899,7 @@ wire [0:0] mux_2level_basis_input4_mem4_2_out ; wire [0:0] mux_2level_basis_input4_mem4_3_out ; sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_1_0_ ( - .A ( mux_2level_basis_input4_mem4_3_out[0] ) , .X ( aps_rename_505_ ) ) ; + .A ( mux_2level_basis_input4_mem4_3_out[0] ) , .X ( out[0] ) ) ; cbx_1__1__local_encoder2to4_0 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , .data ( local_encoder2to4_0_data ) , .data_inv ( local_encoder2to4_0_data_inv ) ) ; @@ -13461,9 +14925,6 @@ cbx_1__1__mux_2level_basis_input4_mem4_3 mux_l2_in_0_ ( .mem ( local_encoder2to4_1_data ) , .mem_inv ( local_encoder2to4_1_data_inv ) , .out ( mux_2level_basis_input4_mem4_3_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_6 BINV_R_127 ( .A ( BUF_net_128 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_128 ( .A ( aps_rename_505_ ) , - .Y ( BUF_net_128 ) ) ; endmodule @@ -13547,9 +15008,11 @@ input clk_3_E_in ; output clk_3_E_out ; output clk_3_W_out ; -wire ropt_net_175 ; -wire ropt_net_166 ; -wire ropt_net_168 ; +wire ropt_net_132 ; +wire ropt_net_134 ; +wire ropt_net_133 ; +wire ropt_net_135 ; +wire ropt_net_136 ; wire [0:0] prog_clk ; wire prog_clk_0 ; wire [0:3] mux_2level_size10_0_sram ; @@ -13601,7 +15064,8 @@ cbx_1__1__mux_2level_size12_0 mux_top_ipin_0 ( .sram ( mux_2level_size12_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 , SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) , - .out ( bottom_grid_pin_0_ ) , .p0 ( optlc_net_143 ) ) ; + .out ( { ropt_net_140 } ) , + .p0 ( optlc_net_113 ) ) ; cbx_1__1__mux_2level_size12_1 mux_top_ipin_2 ( .in ( { chanx_right_out[2] , chanx_left_out[2] , chanx_right_out[5] , chanx_left_out[5] , chanx_right_out[8] , chanx_left_out[8] , @@ -13610,7 +15074,7 @@ cbx_1__1__mux_2level_size12_1 mux_top_ipin_2 ( .sram ( mux_2level_size12_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 , SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 } ) , - .out ( bottom_grid_pin_2_ ) , .p0 ( optlc_net_144 ) ) ; + .out ( bottom_grid_pin_2_ ) , .p0 ( optlc_net_115 ) ) ; cbx_1__1__mux_2level_size12_2 mux_top_ipin_4 ( .in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[4] , chanx_left_out[4] , chanx_right_out[10] , chanx_left_out[10] , @@ -13619,7 +15083,7 @@ cbx_1__1__mux_2level_size12_2 mux_top_ipin_4 ( .sram ( mux_2level_size12_2_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_9 , SYNOPSYS_UNCONNECTED_10 , SYNOPSYS_UNCONNECTED_11 , SYNOPSYS_UNCONNECTED_12 } ) , - .out ( bottom_grid_pin_4_ ) , .p0 ( optlc_net_141 ) ) ; + .out ( bottom_grid_pin_4_ ) , .p0 ( optlc_net_113 ) ) ; cbx_1__1__mux_2level_size12_3 mux_top_ipin_6 ( .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[3] , chanx_left_out[3] , chanx_right_out[6] , chanx_left_out[6] , @@ -13628,7 +15092,7 @@ cbx_1__1__mux_2level_size12_3 mux_top_ipin_6 ( .sram ( mux_2level_size12_3_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 , SYNOPSYS_UNCONNECTED_15 , SYNOPSYS_UNCONNECTED_16 } ) , - .out ( bottom_grid_pin_6_ ) , .p0 ( optlc_net_143 ) ) ; + .out ( bottom_grid_pin_6_ ) , .p0 ( optlc_net_115 ) ) ; cbx_1__1__mux_2level_size12_4 mux_top_ipin_8 ( .in ( { chanx_right_out[2] , chanx_left_out[2] , chanx_right_out[5] , chanx_left_out[5] , chanx_right_out[8] , chanx_left_out[8] , @@ -13637,7 +15101,7 @@ cbx_1__1__mux_2level_size12_4 mux_top_ipin_8 ( .sram ( mux_2level_size12_4_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_17 , SYNOPSYS_UNCONNECTED_18 , SYNOPSYS_UNCONNECTED_19 , SYNOPSYS_UNCONNECTED_20 } ) , - .out ( bottom_grid_pin_8_ ) , .p0 ( optlc_net_142 ) ) ; + .out ( bottom_grid_pin_8_ ) , .p0 ( optlc_net_116 ) ) ; cbx_1__1__mux_2level_size12_5 mux_top_ipin_10 ( .in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[4] , chanx_left_out[4] , chanx_right_out[10] , chanx_left_out[10] , @@ -13646,7 +15110,7 @@ cbx_1__1__mux_2level_size12_5 mux_top_ipin_10 ( .sram ( mux_2level_size12_5_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_21 , SYNOPSYS_UNCONNECTED_22 , SYNOPSYS_UNCONNECTED_23 , SYNOPSYS_UNCONNECTED_24 } ) , - .out ( bottom_grid_pin_10_ ) , .p0 ( optlc_net_141 ) ) ; + .out ( bottom_grid_pin_10_ ) , .p0 ( optlc_net_116 ) ) ; cbx_1__1__mux_2level_size12_6 mux_top_ipin_12 ( .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[3] , chanx_left_out[3] , chanx_right_out[6] , chanx_left_out[6] , @@ -13655,7 +15119,7 @@ cbx_1__1__mux_2level_size12_6 mux_top_ipin_12 ( .sram ( mux_2level_size12_6_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_25 , SYNOPSYS_UNCONNECTED_26 , SYNOPSYS_UNCONNECTED_27 , SYNOPSYS_UNCONNECTED_28 } ) , - .out ( bottom_grid_pin_12_ ) , .p0 ( optlc_net_141 ) ) ; + .out ( bottom_grid_pin_12_ ) , .p0 ( optlc_net_114 ) ) ; cbx_1__1__mux_2level_size12 mux_top_ipin_14 ( .in ( { chanx_right_out[2] , chanx_left_out[2] , chanx_right_out[5] , chanx_left_out[5] , chanx_right_out[8] , chanx_left_out[8] , @@ -13664,7 +15128,7 @@ cbx_1__1__mux_2level_size12 mux_top_ipin_14 ( .sram ( mux_2level_size12_7_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_29 , SYNOPSYS_UNCONNECTED_30 , SYNOPSYS_UNCONNECTED_31 , SYNOPSYS_UNCONNECTED_32 } ) , - .out ( bottom_grid_pin_14_ ) , .p0 ( optlc_net_144 ) ) ; + .out ( bottom_grid_pin_14_ ) , .p0 ( optlc_net_115 ) ) ; cbx_1__1__mux_2level_size12_mem_0 mem_top_ipin_0 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( mux_2level_size12_mem_0_ccff_tail ) , @@ -13712,7 +15176,7 @@ cbx_1__1__mux_2level_size10_0 mux_top_ipin_1 ( .sram ( mux_2level_size10_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_33 , SYNOPSYS_UNCONNECTED_34 , SYNOPSYS_UNCONNECTED_35 , SYNOPSYS_UNCONNECTED_36 } ) , - .out ( bottom_grid_pin_1_ ) , .p0 ( optlc_net_143 ) ) ; + .out ( bottom_grid_pin_1_ ) , .p0 ( optlc_net_113 ) ) ; cbx_1__1__mux_2level_size10_1 mux_top_ipin_3 ( .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[3] , chanx_left_out[3] , chanx_right_out[9] , chanx_left_out[9] , @@ -13721,7 +15185,8 @@ cbx_1__1__mux_2level_size10_1 mux_top_ipin_3 ( .sram ( mux_2level_size10_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_37 , SYNOPSYS_UNCONNECTED_38 , SYNOPSYS_UNCONNECTED_39 , SYNOPSYS_UNCONNECTED_40 } ) , - .out ( bottom_grid_pin_3_ ) , .p0 ( optlc_net_143 ) ) ; + .out ( { ropt_net_131 } ) , + .p0 ( optlc_net_113 ) ) ; cbx_1__1__mux_2level_size10_2 mux_top_ipin_5 ( .in ( { chanx_right_out[2] , chanx_left_out[2] , chanx_right_out[5] , chanx_left_out[5] , chanx_right_out[11] , chanx_left_out[11] , @@ -13730,7 +15195,7 @@ cbx_1__1__mux_2level_size10_2 mux_top_ipin_5 ( .sram ( mux_2level_size10_2_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_41 , SYNOPSYS_UNCONNECTED_42 , SYNOPSYS_UNCONNECTED_43 , SYNOPSYS_UNCONNECTED_44 } ) , - .out ( bottom_grid_pin_5_ ) , .p0 ( optlc_net_141 ) ) ; + .out ( bottom_grid_pin_5_ ) , .p0 ( optlc_net_115 ) ) ; cbx_1__1__mux_2level_size10_3 mux_top_ipin_7 ( .in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[4] , chanx_left_out[4] , chanx_right_out[7] , chanx_left_out[7] , @@ -13739,7 +15204,7 @@ cbx_1__1__mux_2level_size10_3 mux_top_ipin_7 ( .sram ( mux_2level_size10_3_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_45 , SYNOPSYS_UNCONNECTED_46 , SYNOPSYS_UNCONNECTED_47 , SYNOPSYS_UNCONNECTED_48 } ) , - .out ( bottom_grid_pin_7_ ) , .p0 ( optlc_net_142 ) ) ; + .out ( bottom_grid_pin_7_ ) , .p0 ( optlc_net_116 ) ) ; cbx_1__1__mux_2level_size10_4 mux_top_ipin_9 ( .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[3] , chanx_left_out[3] , chanx_right_out[9] , chanx_left_out[9] , @@ -13748,8 +15213,7 @@ cbx_1__1__mux_2level_size10_4 mux_top_ipin_9 ( .sram ( mux_2level_size10_4_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_49 , SYNOPSYS_UNCONNECTED_50 , SYNOPSYS_UNCONNECTED_51 , SYNOPSYS_UNCONNECTED_52 } ) , - .out ( { ZBUF_4_f_0 } ) , - .p0 ( optlc_net_144 ) ) ; + .out ( bottom_grid_pin_9_ ) , .p0 ( optlc_net_113 ) ) ; cbx_1__1__mux_2level_size10_5 mux_top_ipin_11 ( .in ( { chanx_right_out[2] , chanx_left_out[2] , chanx_right_out[5] , chanx_left_out[5] , chanx_right_out[11] , chanx_left_out[11] , @@ -13758,7 +15222,7 @@ cbx_1__1__mux_2level_size10_5 mux_top_ipin_11 ( .sram ( mux_2level_size10_5_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_53 , SYNOPSYS_UNCONNECTED_54 , SYNOPSYS_UNCONNECTED_55 , SYNOPSYS_UNCONNECTED_56 } ) , - .out ( bottom_grid_pin_11_ ) , .p0 ( optlc_net_142 ) ) ; + .out ( bottom_grid_pin_11_ ) , .p0 ( optlc_net_114 ) ) ; cbx_1__1__mux_2level_size10_6 mux_top_ipin_13 ( .in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[4] , chanx_left_out[4] , chanx_right_out[13] , chanx_left_out[13] , @@ -13767,7 +15231,7 @@ cbx_1__1__mux_2level_size10_6 mux_top_ipin_13 ( .sram ( mux_2level_size10_6_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_57 , SYNOPSYS_UNCONNECTED_58 , SYNOPSYS_UNCONNECTED_59 , SYNOPSYS_UNCONNECTED_60 } ) , - .out ( bottom_grid_pin_13_ ) , .p0 ( optlc_net_142 ) ) ; + .out ( bottom_grid_pin_13_ ) , .p0 ( optlc_net_116 ) ) ; cbx_1__1__mux_2level_size10 mux_top_ipin_15 ( .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[3] , chanx_left_out[3] , chanx_right_out[6] , chanx_left_out[6] , @@ -13776,8 +15240,7 @@ cbx_1__1__mux_2level_size10 mux_top_ipin_15 ( .sram ( mux_2level_size10_7_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_61 , SYNOPSYS_UNCONNECTED_62 , SYNOPSYS_UNCONNECTED_63 , SYNOPSYS_UNCONNECTED_64 } ) , - .out ( { ZBUF_4_f_1 } ) , - .p0 ( optlc_net_143 ) ) ; + .out ( bottom_grid_pin_15_ ) , .p0 ( optlc_net_113 ) ) ; cbx_1__1__mux_2level_size10_mem_0 mem_top_ipin_1 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( mux_2level_size12_mem_0_ccff_tail ) , @@ -13819,37 +15282,36 @@ cbx_1__1__mux_2level_size10_mem mem_top_ipin_15 ( .pReset ( pReset ) , .ccff_tail ( ccff_tail ) , .mem_out ( mux_2level_size10_7_sram ) ) ; sky130_fd_sc_hd__buf_8 pReset_FTB00 ( .A ( pReset_W_in ) , .X ( pReset[0] ) ) ; sky130_fd_sc_hd__buf_4 pReset_W_FTB01 ( .A ( pReset_W_in ) , - .X ( ZBUF_39_1 ) ) ; -sky130_fd_sc_hd__buf_4 pReset_S_FTB01 ( .A ( pReset_W_in ) , - .X ( aps_rename_515_ ) ) ; -sky130_fd_sc_hd__buf_1 pReset_E_FTB01 ( .A ( pReset_W_in ) , - .X ( aps_rename_516_ ) ) ; + .X ( pReset_W_out ) ) ; +sky130_fd_sc_hd__buf_1 pReset_S_FTB01 ( .A ( pReset_W_in ) , + .X ( aps_rename_510_ ) ) ; +sky130_fd_sc_hd__buf_4 pReset_E_FTB01 ( .A ( pReset_W_in ) , + .X ( pReset_E_out ) ) ; sky130_fd_sc_hd__buf_1 prog_clk_0_FTB00 ( .A ( prog_clk_0_N_in ) , .X ( prog_clk[0] ) ) ; sky130_fd_sc_hd__clkbuf_1 prog_clk_0_W_FTB01 ( .A ( prog_clk_0_N_in ) , - .X ( ctsbuf_net_1145 ) ) ; -sky130_fd_sc_hd__bufbuf_16 prog_clk_1_N_FTB01 ( .A ( prog_clk_1_E_in ) , - .X ( prog_clk_1_N_out ) ) ; + .X ( ctsbuf_net_1117 ) ) ; +sky130_fd_sc_hd__buf_1 prog_clk_1_N_FTB01 ( .A ( prog_clk_1_E_in ) , + .X ( aps_rename_511_ ) ) ; sky130_fd_sc_hd__buf_1 prog_clk_1_S_FTB01 ( .A ( prog_clk_1_E_in ) , - .X ( aps_rename_517_ ) ) ; + .X ( net_net_95 ) ) ; sky130_fd_sc_hd__bufbuf_16 prog_clk_2_W_FTB01 ( .A ( prog_clk_2_W_in ) , .X ( prog_clk_2_W_out ) ) ; -sky130_fd_sc_hd__buf_1 prog_clk_2_E_FTB01 ( .A ( prog_clk_2_W_in ) , - .X ( aps_rename_518_ ) ) ; -sky130_fd_sc_hd__buf_1 prog_clk_3_E_FTB01 ( .A ( prog_clk_3_E_in ) , - .X ( aps_rename_519_ ) ) ; +sky130_fd_sc_hd__buf_4 prog_clk_2_E_FTB01 ( .A ( prog_clk_2_W_in ) , + .X ( prog_clk_2_E_out ) ) ; +sky130_fd_sc_hd__buf_4 prog_clk_3_E_FTB01 ( .A ( prog_clk_3_E_in ) , + .X ( prog_clk_3_E_out ) ) ; sky130_fd_sc_hd__bufbuf_16 prog_clk_3_W_FTB01 ( .A ( prog_clk_3_E_in ) , .X ( prog_clk_3_W_out ) ) ; -sky130_fd_sc_hd__buf_1 clk_1_N_FTB01 ( .A ( clk_1_E_in ) , - .X ( aps_rename_520_ ) ) ; +sky130_fd_sc_hd__bufbuf_16 clk_1_N_FTB01 ( .A ( clk_1_E_in ) , + .X ( clk_1_N_out ) ) ; sky130_fd_sc_hd__buf_1 clk_1_S_FTB01 ( .A ( clk_1_E_in ) , - .X ( aps_rename_521_ ) ) ; + .X ( aps_rename_512_ ) ) ; sky130_fd_sc_hd__bufbuf_16 clk_2_W_FTB01 ( .A ( clk_2_W_in ) , .X ( clk_2_W_out ) ) ; -sky130_fd_sc_hd__buf_1 clk_2_E_FTB01 ( .A ( clk_2_W_in ) , - .X ( net_net_112 ) ) ; -sky130_fd_sc_hd__buf_1 clk_3_E_FTB01 ( .A ( clk_3_E_in ) , - .X ( aps_rename_522_ ) ) ; +sky130_fd_sc_hd__buf_4 clk_2_E_FTB01 ( .A ( clk_2_W_in ) , + .X ( clk_2_E_out ) ) ; +sky130_fd_sc_hd__buf_1 clk_3_E_FTB01 ( .A ( clk_3_E_in ) , .X ( net_net_98 ) ) ; sky130_fd_sc_hd__bufbuf_16 clk_3_W_FTB01 ( .A ( clk_3_E_in ) , .X ( clk_3_W_out ) ) ; sky130_fd_sc_hd__buf_8 FTB_17__16 ( .A ( chanx_left_in[0] ) , @@ -13899,7 +15361,7 @@ sky130_fd_sc_hd__buf_8 FTB_38__37 ( .A ( chanx_left_in[21] ) , sky130_fd_sc_hd__buf_8 FTB_39__38 ( .A ( chanx_left_in[22] ) , .X ( chanx_right_out[22] ) ) ; sky130_fd_sc_hd__buf_1 FTB_40__39 ( .A ( chanx_left_in[23] ) , - .X ( ropt_net_175 ) ) ; + .X ( ropt_net_132 ) ) ; sky130_fd_sc_hd__buf_8 FTB_41__40 ( .A ( chanx_left_in[24] ) , .X ( chanx_right_out[24] ) ) ; sky130_fd_sc_hd__buf_8 FTB_42__41 ( .A ( chanx_left_in[25] ) , @@ -13958,8 +15420,8 @@ sky130_fd_sc_hd__buf_8 FTB_68__67 ( .A ( chanx_right_in[21] ) , .X ( chanx_left_out[21] ) ) ; sky130_fd_sc_hd__buf_8 FTB_69__68 ( .A ( chanx_right_in[22] ) , .X ( chanx_left_out[22] ) ) ; -sky130_fd_sc_hd__buf_1 FTB_70__69 ( .A ( chanx_right_in[23] ) , - .X ( ropt_net_166 ) ) ; +sky130_fd_sc_hd__buf_6 FTB_70__69 ( .A ( chanx_right_in[23] ) , + .X ( ropt_net_134 ) ) ; sky130_fd_sc_hd__buf_8 FTB_71__70 ( .A ( chanx_right_in[24] ) , .X ( chanx_left_out[24] ) ) ; sky130_fd_sc_hd__buf_8 FTB_72__71 ( .A ( chanx_right_in[25] ) , @@ -13972,58 +15434,49 @@ sky130_fd_sc_hd__buf_8 FTB_75__74 ( .A ( chanx_right_in[28] ) , .X ( chanx_left_out[28] ) ) ; sky130_fd_sc_hd__buf_8 FTB_76__75 ( .A ( chanx_right_in[29] ) , .X ( chanx_left_out[29] ) ) ; -sky130_fd_sc_hd__buf_8 FTB_77__76 ( .A ( SC_IN_TOP ) , .X ( SC_OUT_BOT ) ) ; -sky130_fd_sc_hd__buf_6 FTB_78__77 ( .A ( SC_IN_BOT ) , .X ( ropt_net_168 ) ) ; -sky130_fd_sc_hd__buf_8 FTB_79__78 ( .A ( REGIN_FEEDTHROUGH ) , - .X ( REGOUT_FEEDTHROUGH ) ) ; -sky130_fd_sc_hd__buf_8 FTB_80__79 ( .A ( CIN_FEEDTHROUGH ) , - .X ( COUT_FEEDTHROUGH ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_102 ( .A ( BUF_net_103 ) , .Y ( pReset_E_out ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_103 ( .A ( aps_rename_516_ ) , - .Y ( BUF_net_103 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_104 ( .A ( BUF_net_105 ) , - .Y ( prog_clk_1_S_out ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_105 ( .A ( aps_rename_517_ ) , - .Y ( BUF_net_105 ) ) ; -sky130_fd_sc_hd__inv_6 BINV_R_106 ( .A ( BUF_net_107 ) , - .Y ( prog_clk_3_E_out ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_107 ( .A ( aps_rename_519_ ) , - .Y ( BUF_net_107 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_108 ( .A ( BUF_net_109 ) , .Y ( clk_1_N_out ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_109 ( .A ( aps_rename_520_ ) , - .Y ( BUF_net_109 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_110 ( .A ( BUF_net_111 ) , .Y ( clk_1_S_out ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_111 ( .A ( aps_rename_521_ ) , - .Y ( BUF_net_111 ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_112 ( .A ( net_net_112 ) , .X ( clk_2_E_out ) ) ; -sky130_fd_sc_hd__conb_1 optlc_143 ( .LO ( SYNOPSYS_UNCONNECTED_65 ) , - .HI ( optlc_net_141 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_145 ( .LO ( SYNOPSYS_UNCONNECTED_66 ) , - .HI ( optlc_net_142 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_147 ( .LO ( SYNOPSYS_UNCONNECTED_67 ) , - .HI ( optlc_net_143 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_149 ( .LO ( SYNOPSYS_UNCONNECTED_68 ) , - .HI ( optlc_net_144 ) ) ; -sky130_fd_sc_hd__buf_6 ZBUF_6_f_inst_150 ( .A ( aps_rename_518_ ) , - .X ( prog_clk_2_E_out ) ) ; -sky130_fd_sc_hd__buf_6 ZBUF_6_f_inst_151 ( .A ( aps_rename_522_ ) , - .X ( clk_3_E_out ) ) ; -sky130_fd_sc_hd__buf_6 ZBUF_6_f_inst_656 ( .A ( aps_rename_515_ ) , - .X ( pReset_S_out ) ) ; -sky130_fd_sc_hd__buf_6 ZBUF_4_f_inst_1385 ( .A ( ZBUF_4_f_0 ) , - .X ( bottom_grid_pin_9_[0] ) ) ; -sky130_fd_sc_hd__clkbuf_8 cts_buf_3651292 ( .A ( ctsbuf_net_1145 ) , +sky130_fd_sc_hd__buf_6 FTB_77__76 ( .A ( SC_IN_TOP ) , .X ( SC_OUT_BOT ) ) ; +sky130_fd_sc_hd__buf_1 FTB_78__77 ( .A ( SC_IN_BOT ) , .X ( ropt_net_133 ) ) ; +sky130_fd_sc_hd__buf_6 FTB_79__78 ( .A ( REGIN_FEEDTHROUGH ) , + .X ( ropt_net_135 ) ) ; +sky130_fd_sc_hd__buf_6 FTB_80__79 ( .A ( CIN_FEEDTHROUGH ) , + .X ( ropt_net_136 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_115 ( .LO ( SYNOPSYS_UNCONNECTED_65 ) , + .HI ( optlc_net_113 ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_92 ( .A ( aps_rename_510_ ) , + .Y ( BUF_net_92 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_93 ( .A ( BUF_net_94 ) , + .Y ( prog_clk_1_N_out ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_94 ( .A ( aps_rename_511_ ) , + .Y ( BUF_net_94 ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_95 ( .A ( net_net_95 ) , + .X ( prog_clk_1_S_out ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_96 ( .A ( BUF_net_97 ) , .Y ( clk_1_S_out ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_97 ( .A ( aps_rename_512_ ) , + .Y ( BUF_net_97 ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_98 ( .A ( net_net_98 ) , .X ( clk_3_E_out ) ) ; +sky130_fd_sc_hd__inv_4 BINV_R_105 ( .A ( BUF_net_92 ) , .Y ( pReset_S_out ) ) ; +sky130_fd_sc_hd__conb_1 optlc_117 ( .LO ( SYNOPSYS_UNCONNECTED_66 ) , + .HI ( optlc_net_114 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_119 ( .LO ( SYNOPSYS_UNCONNECTED_67 ) , + .HI ( optlc_net_115 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_121 ( .LO ( SYNOPSYS_UNCONNECTED_68 ) , + .HI ( optlc_net_116 ) ) ; +sky130_fd_sc_hd__buf_6 ropt_mt_inst_1367 ( .A ( ropt_net_131 ) , + .X ( bottom_grid_pin_3_[0] ) ) ; +sky130_fd_sc_hd__buf_6 cts_buf_3651261 ( .A ( ctsbuf_net_1117 ) , .X ( prog_clk_0_W_out ) ) ; -sky130_fd_sc_hd__buf_6 ZBUF_4_f_inst_1386 ( .A ( ZBUF_4_f_1 ) , - .X ( bottom_grid_pin_15_[0] ) ) ; -sky130_fd_sc_hd__buf_6 ZBUF_39_inst_1387 ( .A ( ZBUF_39_1 ) , - .X ( pReset_W_out ) ) ; -sky130_fd_sc_hd__buf_6 ropt_mt_inst_1417 ( .A ( ropt_net_175 ) , +sky130_fd_sc_hd__buf_6 ropt_mt_inst_1371 ( .A ( ropt_net_132 ) , .X ( chanx_right_out[23] ) ) ; -sky130_fd_sc_hd__buf_6 ropt_mt_inst_1408 ( .A ( ropt_net_166 ) , - .X ( chanx_left_out[23] ) ) ; -sky130_fd_sc_hd__buf_6 ropt_mt_inst_1410 ( .A ( ropt_net_168 ) , +sky130_fd_sc_hd__buf_6 ropt_mt_inst_1372 ( .A ( ropt_net_133 ) , .X ( SC_OUT_TOP ) ) ; +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1373 ( .A ( ropt_net_134 ) , + .X ( chanx_left_out[23] ) ) ; +sky130_fd_sc_hd__buf_6 ropt_mt_inst_1374 ( .A ( ropt_net_135 ) , + .X ( REGOUT_FEEDTHROUGH ) ) ; +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1375 ( .A ( ropt_net_136 ) , + .X ( COUT_FEEDTHROUGH ) ) ; +sky130_fd_sc_hd__buf_6 ropt_mt_inst_1377 ( .A ( ropt_net_140 ) , + .X ( bottom_grid_pin_0_[0] ) ) ; endmodule @@ -14035,21 +15488,21 @@ input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:0] mem_out ; -wire copt_net_156 ; +wire copt_net_148 ; sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( copt_net_156 ) ) ; + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( copt_net_148 ) ) ; sky130_fd_sc_hd__buf_6 FTB_18__17 ( .A ( mem_out[0] ) , .X ( ccff_tail[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1389 ( .A ( copt_net_156 ) , - .X ( copt_net_152 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1390 ( .A ( copt_net_152 ) , - .X ( copt_net_153 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1391 ( .A ( copt_net_153 ) , - .X ( copt_net_154 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1392 ( .A ( copt_net_154 ) , - .X ( copt_net_155 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1393 ( .A ( copt_net_155 ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1383 ( .A ( copt_net_149 ) , .X ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1384 ( .A ( copt_net_150 ) , + .X ( copt_net_149 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1385 ( .A ( copt_net_151 ) , + .X ( copt_net_150 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1386 ( .A ( copt_net_152 ) , + .X ( copt_net_151 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1387 ( .A ( copt_net_148 ) , + .X ( copt_net_152 ) ) ; endmodule @@ -14063,17 +15516,17 @@ input FPGA_OUT ; input FPGA_DIR ; input IO_ISOL_N ; -sky130_fd_sc_hd__nand2b_1 ISOL_EN_GATE ( .A_N ( FPGA_DIR ) , - .B ( IO_ISOL_N ) , .Y ( aps_rename_518_ ) ) ; +sky130_fd_sc_hd__or2b_4 ISOL_EN_GATE ( .A ( FPGA_DIR ) , .B_N ( IO_ISOL_N ) , + .X ( aps_rename_517_ ) ) ; sky130_fd_sc_hd__inv_1 INV_SOC_DIR ( .A ( BUF_net_117 ) , .Y ( SOC_DIR_N ) ) ; sky130_fd_sc_hd__ebufn_4 IN_PROTECT_GATE ( .A ( SOC_IN ) , .TE_B ( SOC_DIR_N ) , .Z ( FPGA_IN ) ) ; sky130_fd_sc_hd__ebufn_4 OUT_PROTECT_GATE ( .A ( FPGA_OUT ) , - .TE_B ( BUF_net_117 ) , .Z ( SOC_OUT ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_116 ( .A ( BUF_net_118 ) , .Y ( SOC_DIR ) ) ; -sky130_fd_sc_hd__inv_4 BINV_R_117 ( .A ( BUF_net_118 ) , .Y ( BUF_net_117 ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_118 ( .A ( aps_rename_518_ ) , + .TE_B ( aps_rename_517_ ) , .Z ( SOC_OUT ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_115 ( .A ( BUF_net_118 ) , .Y ( SOC_DIR ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_118 ( .A ( aps_rename_517_ ) , .Y ( BUF_net_118 ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_117 ( .A ( BUF_net_118 ) , .Y ( BUF_net_117 ) ) ; endmodule @@ -14156,17 +15609,15 @@ input FPGA_DIR ; input IO_ISOL_N ; sky130_fd_sc_hd__nand2b_1 ISOL_EN_GATE ( .A_N ( FPGA_DIR ) , - .B ( IO_ISOL_N ) , .Y ( aps_rename_517_ ) ) ; -sky130_fd_sc_hd__inv_1 INV_SOC_DIR ( .A ( aps_rename_517_ ) , - .Y ( SOC_DIR_N ) ) ; + .B ( IO_ISOL_N ) , .Y ( aps_rename_516_ ) ) ; sky130_fd_sc_hd__ebufn_4 IN_PROTECT_GATE ( .A ( SOC_IN ) , - .TE_B ( SOC_DIR_N ) , .Z ( FPGA_IN ) ) ; + .TE_B ( BUF_net_114 ) , .Z ( FPGA_IN ) ) ; sky130_fd_sc_hd__ebufn_4 OUT_PROTECT_GATE ( .A ( FPGA_OUT ) , - .TE_B ( BUF_net_113 ) , .Z ( SOC_OUT ) ) ; -sky130_fd_sc_hd__inv_4 BINV_R_113 ( .A ( BUF_net_115 ) , .Y ( BUF_net_113 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_114 ( .A ( BUF_net_115 ) , .Y ( SOC_DIR ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_115 ( .A ( aps_rename_517_ ) , - .Y ( BUF_net_115 ) ) ; + .TE_B ( BUF_net_111 ) , .Z ( SOC_OUT ) ) ; +sky130_fd_sc_hd__inv_4 BINV_R_111 ( .A ( BUF_net_114 ) , .Y ( BUF_net_111 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_113 ( .A ( BUF_net_114 ) , .Y ( SOC_DIR ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_114 ( .A ( aps_rename_516_ ) , + .Y ( BUF_net_114 ) ) ; endmodule @@ -14249,19 +15700,16 @@ input FPGA_DIR ; input IO_ISOL_N ; sky130_fd_sc_hd__nand2b_1 ISOL_EN_GATE ( .A_N ( FPGA_DIR ) , - .B ( IO_ISOL_N ) , .Y ( aps_rename_516_ ) ) ; -sky130_fd_sc_hd__inv_1 INV_SOC_DIR ( .A ( aps_rename_516_ ) , - .Y ( SOC_DIR_N ) ) ; + .B ( IO_ISOL_N ) , .Y ( aps_rename_515_ ) ) ; +sky130_fd_sc_hd__inv_1 INV_SOC_DIR ( .A ( BUF_net_108 ) , .Y ( SOC_DIR_N ) ) ; sky130_fd_sc_hd__ebufn_4 IN_PROTECT_GATE ( .A ( SOC_IN ) , .TE_B ( SOC_DIR_N ) , .Z ( FPGA_IN ) ) ; sky130_fd_sc_hd__ebufn_4 OUT_PROTECT_GATE ( .A ( FPGA_OUT ) , - .TE_B ( BUF_net_110 ) , .Z ( SOC_OUT ) ) ; -sky130_fd_sc_hd__inv_4 BINV_R_110 ( .A ( BUF_net_112 ) , .Y ( BUF_net_110 ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_112 ( .A ( aps_rename_516_ ) , - .Y ( BUF_net_112 ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_131 ( .A ( BUF_net_112 ) , .Y ( BUF_net_131 ) ) ; -sky130_fd_sc_hd__inv_6 BINV_R_137 ( .A ( BUF_net_138 ) , .Y ( SOC_DIR ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_138 ( .A ( BUF_net_131 ) , .Y ( BUF_net_138 ) ) ; + .TE_B ( BUF_net_108 ) , .Z ( SOC_OUT ) ) ; +sky130_fd_sc_hd__inv_4 BINV_R_108 ( .A ( BUF_net_110 ) , .Y ( BUF_net_108 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_109 ( .A ( BUF_net_110 ) , .Y ( SOC_DIR ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_110 ( .A ( aps_rename_515_ ) , + .Y ( BUF_net_110 ) ) ; endmodule @@ -14344,14 +15792,16 @@ input FPGA_DIR ; input IO_ISOL_N ; sky130_fd_sc_hd__or2b_4 ISOL_EN_GATE ( .A ( FPGA_DIR ) , .B_N ( IO_ISOL_N ) , - .X ( aps_rename_515_ ) ) ; + .X ( aps_rename_514_ ) ) ; +sky130_fd_sc_hd__inv_1 INV_SOC_DIR ( .A ( aps_rename_514_ ) , + .Y ( SOC_DIR_N ) ) ; sky130_fd_sc_hd__ebufn_4 IN_PROTECT_GATE ( .A ( SOC_IN ) , - .TE_B ( BUF_net_109 ) , .Z ( FPGA_IN ) ) ; + .TE_B ( SOC_DIR_N ) , .Z ( FPGA_IN ) ) ; sky130_fd_sc_hd__ebufn_4 OUT_PROTECT_GATE ( .A ( FPGA_OUT ) , - .TE_B ( aps_rename_515_ ) , .Z ( SOC_OUT ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_107 ( .A ( BUF_net_109 ) , .Y ( SOC_DIR ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_109 ( .A ( aps_rename_515_ ) , - .Y ( BUF_net_109 ) ) ; + .TE_B ( aps_rename_514_ ) , .Z ( SOC_OUT ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_106 ( .A ( BUF_net_107 ) , .Y ( SOC_DIR ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_107 ( .A ( aps_rename_514_ ) , + .Y ( BUF_net_107 ) ) ; endmodule @@ -14433,17 +15883,16 @@ input FPGA_OUT ; input FPGA_DIR ; input IO_ISOL_N ; -sky130_fd_sc_hd__or2b_4 ISOL_EN_GATE ( .A ( FPGA_DIR ) , .B_N ( IO_ISOL_N ) , - .X ( aps_rename_514_ ) ) ; -sky130_fd_sc_hd__inv_1 INV_SOC_DIR ( .A ( aps_rename_514_ ) , - .Y ( SOC_DIR_N ) ) ; +sky130_fd_sc_hd__nand2b_1 ISOL_EN_GATE ( .A_N ( FPGA_DIR ) , + .B ( IO_ISOL_N ) , .Y ( aps_rename_513_ ) ) ; sky130_fd_sc_hd__ebufn_4 IN_PROTECT_GATE ( .A ( SOC_IN ) , - .TE_B ( SOC_DIR_N ) , .Z ( FPGA_IN ) ) ; + .TE_B ( BUF_net_105 ) , .Z ( FPGA_IN ) ) ; sky130_fd_sc_hd__ebufn_4 OUT_PROTECT_GATE ( .A ( FPGA_OUT ) , - .TE_B ( aps_rename_514_ ) , .Z ( SOC_OUT ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_103 ( .A ( BUF_net_106 ) , .Y ( SOC_DIR ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_106 ( .A ( aps_rename_514_ ) , - .Y ( BUF_net_106 ) ) ; + .TE_B ( BUF_net_103 ) , .Z ( SOC_OUT ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_102 ( .A ( BUF_net_105 ) , .Y ( SOC_DIR ) ) ; +sky130_fd_sc_hd__inv_4 BINV_R_103 ( .A ( BUF_net_105 ) , .Y ( BUF_net_103 ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_105 ( .A ( aps_rename_513_ ) , + .Y ( BUF_net_105 ) ) ; endmodule @@ -14526,15 +15975,17 @@ input FPGA_DIR ; input IO_ISOL_N ; sky130_fd_sc_hd__nand2b_1 ISOL_EN_GATE ( .A_N ( FPGA_DIR ) , - .B ( IO_ISOL_N ) , .Y ( aps_rename_513_ ) ) ; + .B ( IO_ISOL_N ) , .Y ( aps_rename_512_ ) ) ; +sky130_fd_sc_hd__inv_1 INV_SOC_DIR ( .A ( aps_rename_512_ ) , + .Y ( SOC_DIR_N ) ) ; sky130_fd_sc_hd__ebufn_4 IN_PROTECT_GATE ( .A ( SOC_IN ) , - .TE_B ( BUF_net_102 ) , .Z ( FPGA_IN ) ) ; + .TE_B ( SOC_DIR_N ) , .Z ( FPGA_IN ) ) ; sky130_fd_sc_hd__ebufn_4 OUT_PROTECT_GATE ( .A ( FPGA_OUT ) , - .TE_B ( BUF_net_99 ) , .Z ( SOC_OUT ) ) ; -sky130_fd_sc_hd__inv_4 BINV_R_99 ( .A ( BUF_net_102 ) , .Y ( BUF_net_99 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_101 ( .A ( BUF_net_102 ) , .Y ( SOC_DIR ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_102 ( .A ( aps_rename_513_ ) , - .Y ( BUF_net_102 ) ) ; + .TE_B ( BUF_net_100 ) , .Z ( SOC_OUT ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_98 ( .A ( BUF_net_101 ) , .Y ( SOC_DIR ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_101 ( .A ( aps_rename_512_ ) , + .Y ( BUF_net_101 ) ) ; +sky130_fd_sc_hd__inv_4 BINV_R_100 ( .A ( BUF_net_101 ) , .Y ( BUF_net_100 ) ) ; endmodule @@ -14616,18 +16067,17 @@ input FPGA_OUT ; input FPGA_DIR ; input IO_ISOL_N ; -sky130_fd_sc_hd__nand2b_1 ISOL_EN_GATE ( .A_N ( FPGA_DIR ) , - .B ( IO_ISOL_N ) , .Y ( aps_rename_512_ ) ) ; -sky130_fd_sc_hd__inv_1 INV_SOC_DIR ( .A ( aps_rename_512_ ) , - .Y ( SOC_DIR_N ) ) ; +sky130_fd_sc_hd__or2b_4 ISOL_EN_GATE ( .A ( FPGA_DIR ) , .B_N ( IO_ISOL_N ) , + .X ( aps_rename_511_ ) ) ; +sky130_fd_sc_hd__inv_1 INV_SOC_DIR ( .A ( BUF_net_95 ) , .Y ( SOC_DIR_N ) ) ; sky130_fd_sc_hd__ebufn_4 IN_PROTECT_GATE ( .A ( SOC_IN ) , .TE_B ( SOC_DIR_N ) , .Z ( FPGA_IN ) ) ; sky130_fd_sc_hd__ebufn_4 OUT_PROTECT_GATE ( .A ( FPGA_OUT ) , - .TE_B ( BUF_net_96 ) , .Z ( SOC_OUT ) ) ; -sky130_fd_sc_hd__inv_4 BINV_R_96 ( .A ( BUF_net_98 ) , .Y ( BUF_net_96 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_97 ( .A ( BUF_net_98 ) , .Y ( SOC_DIR ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_98 ( .A ( aps_rename_512_ ) , - .Y ( BUF_net_98 ) ) ; + .TE_B ( aps_rename_511_ ) , .Z ( SOC_OUT ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_95 ( .A ( BUF_net_97 ) , .Y ( BUF_net_95 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_96 ( .A ( BUF_net_97 ) , .Y ( SOC_DIR ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_97 ( .A ( aps_rename_511_ ) , + .Y ( BUF_net_97 ) ) ; endmodule @@ -14710,16 +16160,16 @@ input FPGA_DIR ; input IO_ISOL_N ; sky130_fd_sc_hd__nand2b_1 ISOL_EN_GATE ( .A_N ( FPGA_DIR ) , - .B ( IO_ISOL_N ) , .Y ( aps_rename_511_ ) ) ; + .B ( IO_ISOL_N ) , .Y ( aps_rename_510_ ) ) ; sky130_fd_sc_hd__inv_1 INV_SOC_DIR ( .A ( BUF_net_93 ) , .Y ( SOC_DIR_N ) ) ; sky130_fd_sc_hd__ebufn_4 IN_PROTECT_GATE ( .A ( SOC_IN ) , .TE_B ( SOC_DIR_N ) , .Z ( FPGA_IN ) ) ; sky130_fd_sc_hd__ebufn_4 OUT_PROTECT_GATE ( .A ( FPGA_OUT ) , .TE_B ( BUF_net_93 ) , .Z ( SOC_OUT ) ) ; -sky130_fd_sc_hd__inv_4 BINV_R_93 ( .A ( BUF_net_95 ) , .Y ( BUF_net_93 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_94 ( .A ( BUF_net_95 ) , .Y ( SOC_DIR ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_95 ( .A ( aps_rename_511_ ) , - .Y ( BUF_net_95 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_92 ( .A ( BUF_net_94 ) , .Y ( SOC_DIR ) ) ; +sky130_fd_sc_hd__inv_4 BINV_R_93 ( .A ( BUF_net_94 ) , .Y ( BUF_net_93 ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_94 ( .A ( aps_rename_510_ ) , + .Y ( BUF_net_94 ) ) ; endmodule @@ -14802,14 +16252,14 @@ input FPGA_DIR ; input IO_ISOL_N ; sky130_fd_sc_hd__or2b_4 ISOL_EN_GATE ( .A ( FPGA_DIR ) , .B_N ( IO_ISOL_N ) , - .X ( aps_rename_510_ ) ) ; + .X ( aps_rename_509_ ) ) ; sky130_fd_sc_hd__ebufn_4 IN_PROTECT_GATE ( .A ( SOC_IN ) , - .TE_B ( BUF_net_92 ) , .Z ( FPGA_IN ) ) ; + .TE_B ( BUF_net_91 ) , .Z ( FPGA_IN ) ) ; sky130_fd_sc_hd__ebufn_4 OUT_PROTECT_GATE ( .A ( FPGA_OUT ) , - .TE_B ( aps_rename_510_ ) , .Z ( SOC_OUT ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_89 ( .A ( BUF_net_92 ) , .Y ( SOC_DIR ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_92 ( .A ( aps_rename_510_ ) , - .Y ( BUF_net_92 ) ) ; + .TE_B ( aps_rename_509_ ) , .Z ( SOC_OUT ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_90 ( .A ( BUF_net_91 ) , .Y ( SOC_DIR ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_91 ( .A ( aps_rename_509_ ) , + .Y ( BUF_net_91 ) ) ; endmodule @@ -15035,7 +16485,7 @@ input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ropt_net_160 ) , +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ropt_net_155 ) , .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; @@ -15044,20 +16494,20 @@ sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__buf_1 FTB_1__0 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1382 ( .A ( ccff_head[0] ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1376 ( .A ( copt_net_142 ) , + .X ( copt_net_141 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1377 ( .A ( copt_net_143 ) , + .X ( copt_net_142 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1378 ( .A ( ccff_head[0] ) , + .X ( copt_net_143 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1379 ( .A ( copt_net_141 ) , + .X ( copt_net_144 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1380 ( .A ( copt_net_146 ) , .X ( copt_net_145 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1383 ( .A ( copt_net_145 ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1381 ( .A ( copt_net_144 ) , .X ( copt_net_146 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1384 ( .A ( copt_net_146 ) , - .X ( copt_net_147 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1385 ( .A ( copt_net_147 ) , - .X ( copt_net_148 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1386 ( .A ( copt_net_148 ) , - .X ( copt_net_149 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1387 ( .A ( copt_net_149 ) , - .X ( copt_net_150 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1395 ( .A ( copt_net_150 ) , - .X ( ropt_net_160 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1389 ( .A ( copt_net_145 ) , + .X ( ropt_net_155 ) ) ; endmodule @@ -15069,12 +16519,18 @@ input [0:3] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -15084,12 +16540,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -15099,12 +16561,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -15114,12 +16582,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -15217,12 +16691,18 @@ input [0:3] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -15232,12 +16712,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -15247,12 +16733,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -15262,12 +16754,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -15328,7 +16826,7 @@ wire [0:0] mux_2level_basis_input4_mem4_2_out ; wire [0:0] mux_2level_basis_input4_mem4_3_out ; sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_1_0_ ( - .A ( mux_2level_basis_input4_mem4_3_out[0] ) , .X ( aps_rename_509_ ) ) ; + .A ( mux_2level_basis_input4_mem4_3_out[0] ) , .X ( out[0] ) ) ; cbx_1__0__local_encoder2to4_14 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , .data ( local_encoder2to4_0_data ) , .data_inv ( local_encoder2to4_0_data_inv ) ) ; @@ -15354,9 +16852,6 @@ cbx_1__0__mux_2level_basis_input4_mem4_31 mux_l2_in_0_ ( .mem ( local_encoder2to4_1_data ) , .mem_inv ( local_encoder2to4_1_data_inv ) , .out ( mux_2level_basis_input4_mem4_3_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_127 ( .A ( BUF_net_128 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_128 ( .A ( aps_rename_509_ ) , - .Y ( BUF_net_128 ) ) ; endmodule @@ -15368,12 +16863,18 @@ input [0:3] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -15383,12 +16884,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -15398,12 +16905,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -15413,12 +16926,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -15479,7 +16998,7 @@ wire [0:0] mux_2level_basis_input4_mem4_2_out ; wire [0:0] mux_2level_basis_input4_mem4_3_out ; sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_1_0_ ( - .A ( mux_2level_basis_input4_mem4_3_out[0] ) , .X ( out[0] ) ) ; + .A ( mux_2level_basis_input4_mem4_3_out[0] ) , .X ( aps_rename_508_ ) ) ; cbx_1__0__local_encoder2to4_12 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , .data ( local_encoder2to4_0_data ) , .data_inv ( local_encoder2to4_0_data_inv ) ) ; @@ -15505,6 +17024,9 @@ cbx_1__0__mux_2level_basis_input4_mem4_27 mux_l2_in_0_ ( .mem ( local_encoder2to4_1_data ) , .mem_inv ( local_encoder2to4_1_data_inv ) , .out ( mux_2level_basis_input4_mem4_3_out ) , .p0 ( p0 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_125 ( .A ( BUF_net_126 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_126 ( .A ( aps_rename_508_ ) , + .Y ( BUF_net_126 ) ) ; endmodule @@ -15516,12 +17038,18 @@ input [0:3] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -15531,12 +17059,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -15546,12 +17080,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -15561,12 +17101,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -15627,7 +17173,7 @@ wire [0:0] mux_2level_basis_input4_mem4_2_out ; wire [0:0] mux_2level_basis_input4_mem4_3_out ; sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_1_0_ ( - .A ( mux_2level_basis_input4_mem4_3_out[0] ) , .X ( out[0] ) ) ; + .A ( mux_2level_basis_input4_mem4_3_out[0] ) , .X ( aps_rename_507_ ) ) ; cbx_1__0__local_encoder2to4_10 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , .data ( local_encoder2to4_0_data ) , .data_inv ( local_encoder2to4_0_data_inv ) ) ; @@ -15653,6 +17199,9 @@ cbx_1__0__mux_2level_basis_input4_mem4_23 mux_l2_in_0_ ( .mem ( local_encoder2to4_1_data ) , .mem_inv ( local_encoder2to4_1_data_inv ) , .out ( mux_2level_basis_input4_mem4_3_out ) , .p0 ( p0 ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_123 ( .A ( BUF_net_124 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_124 ( .A ( aps_rename_507_ ) , + .Y ( BUF_net_124 ) ) ; endmodule @@ -15664,12 +17213,18 @@ input [0:3] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -15679,12 +17234,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -15694,12 +17255,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -15709,12 +17276,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -15774,8 +17347,8 @@ wire [0:0] mux_2level_basis_input4_mem4_1_out ; wire [0:0] mux_2level_basis_input4_mem4_2_out ; wire [0:0] mux_2level_basis_input4_mem4_3_out ; -sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_1_0_ ( - .A ( mux_2level_basis_input4_mem4_3_out[0] ) , .X ( aps_rename_508_ ) ) ; +sky130_fd_sc_hd__bufbuf_16 sky130_fd_sc_hd__buf_1_0_ ( + .A ( mux_2level_basis_input4_mem4_3_out[0] ) , .X ( out[0] ) ) ; cbx_1__0__local_encoder2to4_8 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , .data ( local_encoder2to4_0_data ) , .data_inv ( local_encoder2to4_0_data_inv ) ) ; @@ -15801,9 +17374,6 @@ cbx_1__0__mux_2level_basis_input4_mem4_19 mux_l2_in_0_ ( .mem ( local_encoder2to4_1_data ) , .mem_inv ( local_encoder2to4_1_data_inv ) , .out ( mux_2level_basis_input4_mem4_3_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_125 ( .A ( BUF_net_126 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_126 ( .A ( aps_rename_508_ ) , - .Y ( BUF_net_126 ) ) ; endmodule @@ -15815,12 +17385,18 @@ input [0:3] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -15830,12 +17406,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -15845,12 +17427,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -15860,12 +17448,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -15926,7 +17520,7 @@ wire [0:0] mux_2level_basis_input4_mem4_2_out ; wire [0:0] mux_2level_basis_input4_mem4_3_out ; sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_1_0_ ( - .A ( mux_2level_basis_input4_mem4_3_out[0] ) , .X ( out[0] ) ) ; + .A ( mux_2level_basis_input4_mem4_3_out[0] ) , .X ( aps_rename_506_ ) ) ; cbx_1__0__local_encoder2to4_6 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , .data ( local_encoder2to4_0_data ) , .data_inv ( local_encoder2to4_0_data_inv ) ) ; @@ -15952,6 +17546,9 @@ cbx_1__0__mux_2level_basis_input4_mem4_15 mux_l2_in_0_ ( .mem ( local_encoder2to4_1_data ) , .mem_inv ( local_encoder2to4_1_data_inv ) , .out ( mux_2level_basis_input4_mem4_3_out ) , .p0 ( p0 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_121 ( .A ( BUF_net_122 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_122 ( .A ( aps_rename_506_ ) , + .Y ( BUF_net_122 ) ) ; endmodule @@ -15963,12 +17560,18 @@ input [0:3] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -15978,12 +17581,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -15993,12 +17602,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -16008,12 +17623,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -16073,8 +17694,8 @@ wire [0:0] mux_2level_basis_input4_mem4_1_out ; wire [0:0] mux_2level_basis_input4_mem4_2_out ; wire [0:0] mux_2level_basis_input4_mem4_3_out ; -sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_1_0_ ( - .A ( mux_2level_basis_input4_mem4_3_out[0] ) , .X ( aps_rename_507_ ) ) ; +sky130_fd_sc_hd__bufbuf_16 sky130_fd_sc_hd__buf_1_0_ ( + .A ( mux_2level_basis_input4_mem4_3_out[0] ) , .X ( out[0] ) ) ; cbx_1__0__local_encoder2to4_4 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , .data ( local_encoder2to4_0_data ) , .data_inv ( local_encoder2to4_0_data_inv ) ) ; @@ -16100,9 +17721,6 @@ cbx_1__0__mux_2level_basis_input4_mem4_11 mux_l2_in_0_ ( .mem ( local_encoder2to4_1_data ) , .mem_inv ( local_encoder2to4_1_data_inv ) , .out ( mux_2level_basis_input4_mem4_3_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_124 ( .A ( aps_rename_507_ ) , - .Y ( BUF_net_124 ) ) ; -sky130_fd_sc_hd__inv_6 BINV_R_133 ( .A ( BUF_net_124 ) , .Y ( out[0] ) ) ; endmodule @@ -16114,12 +17732,18 @@ input [0:3] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -16129,12 +17753,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -16144,12 +17774,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -16159,12 +17795,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -16225,7 +17867,7 @@ wire [0:0] mux_2level_basis_input4_mem4_2_out ; wire [0:0] mux_2level_basis_input4_mem4_3_out ; sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_1_0_ ( - .A ( mux_2level_basis_input4_mem4_3_out[0] ) , .X ( aps_rename_506_ ) ) ; + .A ( mux_2level_basis_input4_mem4_3_out[0] ) , .X ( aps_rename_505_ ) ) ; cbx_1__0__local_encoder2to4_2 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , .data ( local_encoder2to4_0_data ) , .data_inv ( local_encoder2to4_0_data_inv ) ) ; @@ -16251,9 +17893,9 @@ cbx_1__0__mux_2level_basis_input4_mem4_7 mux_l2_in_0_ ( .mem ( local_encoder2to4_1_data ) , .mem_inv ( local_encoder2to4_1_data_inv ) , .out ( mux_2level_basis_input4_mem4_3_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_6 BINV_R_121 ( .A ( BUF_net_122 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_122 ( .A ( aps_rename_506_ ) , - .Y ( BUF_net_122 ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_120 ( .A ( aps_rename_505_ ) , + .Y ( BUF_net_120 ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_130 ( .A ( BUF_net_120 ) , .Y ( out[0] ) ) ; endmodule @@ -16265,12 +17907,18 @@ input [0:3] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -16280,12 +17928,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -16295,12 +17949,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -16310,12 +17970,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -16375,8 +18041,8 @@ wire [0:0] mux_2level_basis_input4_mem4_1_out ; wire [0:0] mux_2level_basis_input4_mem4_2_out ; wire [0:0] mux_2level_basis_input4_mem4_3_out ; -sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_1_0_ ( - .A ( mux_2level_basis_input4_mem4_3_out[0] ) , .X ( aps_rename_505_ ) ) ; +sky130_fd_sc_hd__bufbuf_16 sky130_fd_sc_hd__buf_1_0_ ( + .A ( mux_2level_basis_input4_mem4_3_out[0] ) , .X ( out[0] ) ) ; cbx_1__0__local_encoder2to4_0 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , .data ( local_encoder2to4_0_data ) , .data_inv ( local_encoder2to4_0_data_inv ) ) ; @@ -16402,9 +18068,6 @@ cbx_1__0__mux_2level_basis_input4_mem4_3 mux_l2_in_0_ ( .mem ( local_encoder2to4_1_data ) , .mem_inv ( local_encoder2to4_1_data_inv ) , .out ( mux_2level_basis_input4_mem4_3_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_119 ( .A ( BUF_net_120 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_120 ( .A ( aps_rename_505_ ) , - .Y ( BUF_net_120 ) ) ; endmodule @@ -16528,7 +18191,7 @@ cbx_1__0__mux_2level_size12_0 mux_top_ipin_0 ( .sram ( mux_2level_size12_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 , SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) , - .out ( bottom_grid_pin_0_ ) , .p0 ( optlc_net_142 ) ) ; + .out ( bottom_grid_pin_0_ ) , .p0 ( optlc_net_136 ) ) ; cbx_1__0__mux_2level_size12_1 mux_top_ipin_1 ( .in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[4] , chanx_left_out[4] , chanx_right_out[7] , chanx_left_out[7] , @@ -16537,7 +18200,7 @@ cbx_1__0__mux_2level_size12_1 mux_top_ipin_1 ( .sram ( mux_2level_size12_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 , SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 } ) , - .out ( bottom_grid_pin_2_ ) , .p0 ( optlc_net_143 ) ) ; + .out ( bottom_grid_pin_2_ ) , .p0 ( optlc_net_136 ) ) ; cbx_1__0__mux_2level_size12_2 mux_top_ipin_2 ( .in ( { chanx_right_out[2] , chanx_left_out[2] , chanx_right_out[5] , chanx_left_out[5] , chanx_right_out[8] , chanx_left_out[8] , @@ -16546,7 +18209,7 @@ cbx_1__0__mux_2level_size12_2 mux_top_ipin_2 ( .sram ( mux_2level_size12_2_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_9 , SYNOPSYS_UNCONNECTED_10 , SYNOPSYS_UNCONNECTED_11 , SYNOPSYS_UNCONNECTED_12 } ) , - .out ( bottom_grid_pin_4_ ) , .p0 ( optlc_net_143 ) ) ; + .out ( bottom_grid_pin_4_ ) , .p0 ( optlc_net_138 ) ) ; cbx_1__0__mux_2level_size12_3 mux_top_ipin_3 ( .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[3] , chanx_left_out[3] , chanx_right_out[9] , chanx_left_out[9] , @@ -16555,8 +18218,7 @@ cbx_1__0__mux_2level_size12_3 mux_top_ipin_3 ( .sram ( mux_2level_size12_3_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 , SYNOPSYS_UNCONNECTED_15 , SYNOPSYS_UNCONNECTED_16 } ) , - .out ( { aps_rename_519_ } ) , - .p0 ( optlc_net_141 ) ) ; + .out ( bottom_grid_pin_6_ ) , .p0 ( optlc_net_139 ) ) ; cbx_1__0__mux_2level_size12_4 mux_top_ipin_4 ( .in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[4] , chanx_left_out[4] , chanx_right_out[10] , chanx_left_out[10] , @@ -16565,7 +18227,7 @@ cbx_1__0__mux_2level_size12_4 mux_top_ipin_4 ( .sram ( mux_2level_size12_4_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_17 , SYNOPSYS_UNCONNECTED_18 , SYNOPSYS_UNCONNECTED_19 , SYNOPSYS_UNCONNECTED_20 } ) , - .out ( bottom_grid_pin_8_ ) , .p0 ( optlc_net_141 ) ) ; + .out ( bottom_grid_pin_8_ ) , .p0 ( optlc_net_138 ) ) ; cbx_1__0__mux_2level_size12_5 mux_top_ipin_5 ( .in ( { chanx_right_out[2] , chanx_left_out[2] , chanx_right_out[5] , chanx_left_out[5] , chanx_right_out[11] , chanx_left_out[11] , @@ -16574,8 +18236,7 @@ cbx_1__0__mux_2level_size12_5 mux_top_ipin_5 ( .sram ( mux_2level_size12_5_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_21 , SYNOPSYS_UNCONNECTED_22 , SYNOPSYS_UNCONNECTED_23 , SYNOPSYS_UNCONNECTED_24 } ) , - .out ( { aps_rename_520_ } ) , - .p0 ( optlc_net_142 ) ) ; + .out ( bottom_grid_pin_10_ ) , .p0 ( optlc_net_138 ) ) ; cbx_1__0__mux_2level_size12_6 mux_top_ipin_6 ( .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[3] , chanx_left_out[3] , chanx_right_out[6] , chanx_left_out[6] , @@ -16584,8 +18245,7 @@ cbx_1__0__mux_2level_size12_6 mux_top_ipin_6 ( .sram ( mux_2level_size12_6_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_25 , SYNOPSYS_UNCONNECTED_26 , SYNOPSYS_UNCONNECTED_27 , SYNOPSYS_UNCONNECTED_28 } ) , - .out ( { aps_rename_521_ } ) , - .p0 ( optlc_net_143 ) ) ; + .out ( bottom_grid_pin_12_ ) , .p0 ( optlc_net_138 ) ) ; cbx_1__0__mux_2level_size12_7 mux_top_ipin_7 ( .in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[4] , chanx_left_out[4] , chanx_right_out[7] , chanx_left_out[7] , @@ -16594,7 +18254,8 @@ cbx_1__0__mux_2level_size12_7 mux_top_ipin_7 ( .sram ( mux_2level_size12_7_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_29 , SYNOPSYS_UNCONNECTED_30 , SYNOPSYS_UNCONNECTED_31 , SYNOPSYS_UNCONNECTED_32 } ) , - .out ( bottom_grid_pin_14_ ) , .p0 ( optlc_net_141 ) ) ; + .out ( { aps_rename_518_ } ) , + .p0 ( optlc_net_136 ) ) ; cbx_1__0__mux_2level_size12 mux_top_ipin_8 ( .in ( { chanx_right_out[2] , chanx_left_out[2] , chanx_right_out[5] , chanx_left_out[5] , chanx_right_out[8] , chanx_left_out[8] , @@ -16603,7 +18264,7 @@ cbx_1__0__mux_2level_size12 mux_top_ipin_8 ( .sram ( mux_2level_size12_8_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_33 , SYNOPSYS_UNCONNECTED_34 , SYNOPSYS_UNCONNECTED_35 , SYNOPSYS_UNCONNECTED_36 } ) , - .out ( bottom_grid_pin_16_ ) , .p0 ( optlc_net_142 ) ) ; + .out ( bottom_grid_pin_16_ ) , .p0 ( optlc_net_137 ) ) ; cbx_1__0__mux_2level_size12_mem_0 mem_top_ipin_0 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( mux_2level_size12_mem_0_ccff_tail ) , @@ -16731,13 +18392,13 @@ cbx_1__0__logical_tile_io_mode_io_ logical_tile_io_mode_io__8 ( .ccff_tail ( ccff_tail ) ) ; sky130_fd_sc_hd__buf_8 pReset_FTB00 ( .A ( pReset_W_in ) , .X ( pReset[0] ) ) ; sky130_fd_sc_hd__buf_1 pReset_W_FTB01 ( .A ( pReset_W_in ) , - .X ( aps_rename_522_ ) ) ; -sky130_fd_sc_hd__bufbuf_16 pReset_E_FTB01 ( .A ( pReset_W_in ) , - .X ( pReset_E_out ) ) ; + .X ( aps_rename_519_ ) ) ; +sky130_fd_sc_hd__buf_1 pReset_E_FTB01 ( .A ( pReset_W_in ) , + .X ( net_net_129 ) ) ; sky130_fd_sc_hd__buf_1 prog_clk_0_FTB00 ( .A ( prog_clk_0_N_in ) , .X ( prog_clk[0] ) ) ; sky130_fd_sc_hd__clkbuf_1 prog_clk_0_W_FTB01 ( .A ( prog_clk_0_N_in ) , - .X ( ctsbuf_net_1144 ) ) ; + .X ( ctsbuf_net_1140 ) ) ; sky130_fd_sc_hd__buf_8 FTB_19__18 ( .A ( chanx_left_in[0] ) , .X ( chanx_right_out[0] ) ) ; sky130_fd_sc_hd__buf_8 FTB_20__19 ( .A ( chanx_left_in[1] ) , @@ -16887,22 +18548,22 @@ sky130_fd_sc_hd__buf_6 FTB_87__86 ( .X ( top_width_0_height_0__pin_17_upper[0] ) ) ; sky130_fd_sc_hd__buf_6 FTB_88__87 ( .A ( SC_IN_TOP ) , .X ( SC_OUT_BOT ) ) ; sky130_fd_sc_hd__buf_6 FTB_89__88 ( .A ( SC_IN_BOT ) , .X ( SC_OUT_TOP ) ) ; -sky130_fd_sc_hd__conb_1 optlc_142 ( .LO ( SYNOPSYS_UNCONNECTED_37 ) , - .HI ( optlc_net_141 ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_130 ( .A ( aps_rename_522_ ) , - .Y ( BUF_net_130 ) ) ; -sky130_fd_sc_hd__inv_6 BINV_R_135 ( .A ( BUF_net_130 ) , .Y ( pReset_W_out ) ) ; -sky130_fd_sc_hd__conb_1 optlc_144 ( .LO ( SYNOPSYS_UNCONNECTED_38 ) , - .HI ( optlc_net_142 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_146 ( .LO ( SYNOPSYS_UNCONNECTED_39 ) , - .HI ( optlc_net_143 ) ) ; -sky130_fd_sc_hd__buf_6 ZBUF_6_f_inst_147 ( .A ( aps_rename_521_ ) , - .X ( bottom_grid_pin_12_[0] ) ) ; -sky130_fd_sc_hd__buf_6 ZBUF_6_f_inst_148 ( .A ( aps_rename_519_ ) , - .X ( bottom_grid_pin_6_[0] ) ) ; -sky130_fd_sc_hd__buf_6 ZBUF_6_f_inst_149 ( .A ( aps_rename_520_ ) , - .X ( bottom_grid_pin_10_[0] ) ) ; -sky130_fd_sc_hd__buf_6 cts_buf_3651289 ( .A ( ctsbuf_net_1144 ) , +sky130_fd_sc_hd__conb_1 optlc_138 ( .LO ( SYNOPSYS_UNCONNECTED_37 ) , + .HI ( optlc_net_136 ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_128 ( .A ( aps_rename_519_ ) , + .Y ( BUF_net_128 ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_129 ( .A ( net_net_129 ) , + .X ( pReset_E_out ) ) ; +sky130_fd_sc_hd__conb_1 optlc_139 ( .LO ( SYNOPSYS_UNCONNECTED_38 ) , + .HI ( optlc_net_137 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_141 ( .LO ( SYNOPSYS_UNCONNECTED_39 ) , + .HI ( optlc_net_138 ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_134 ( .A ( BUF_net_128 ) , .Y ( pReset_W_out ) ) ; +sky130_fd_sc_hd__conb_1 optlc_142 ( .LO ( SYNOPSYS_UNCONNECTED_40 ) , + .HI ( optlc_net_139 ) ) ; +sky130_fd_sc_hd__buf_6 ZBUF_6_f_inst_143 ( .A ( aps_rename_518_ ) , + .X ( bottom_grid_pin_14_[0] ) ) ; +sky130_fd_sc_hd__clkbuf_8 cts_buf_3651283 ( .A ( ctsbuf_net_1140 ) , .X ( prog_clk_0_W_out ) ) ; endmodule @@ -16978,7 +18639,7 @@ input [0:0] mem ; input [0:0] mem_inv ; output [0:0] out ; -sky130_fd_sc_hd__mux2_2 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) , +sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ; endmodule @@ -17019,8 +18680,6 @@ wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ; wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ; wire [0:0] mux_2level_tapbuf_basis_input2_mem1_2_out ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( mux_2level_tapbuf_basis_input2_mem1_2_out[0] ) , .X ( out[0] ) ) ; sb_2__2__mux_2level_tapbuf_basis_input2_mem1_83 mux_l1_in_0_ ( .in ( in[0:1] ) , .mem ( sram[0] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) , @@ -17036,6 +18695,9 @@ sb_2__2__mux_2level_tapbuf_basis_input2_mem1 mux_l2_in_0_ ( .mem ( sram[1] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_4 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_2_out ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_158 ( .A ( BUF_net_159 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_159 ( + .A ( mux_2level_tapbuf_basis_input2_mem1_2_out[0] ) , .Y ( BUF_net_159 ) ) ; endmodule @@ -17046,7 +18708,7 @@ input [0:0] mem ; input [0:0] mem_inv ; output [0:0] out ; -sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) , +sky130_fd_sc_hd__mux2_2 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ; endmodule @@ -17087,6 +18749,8 @@ wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ; wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ; wire [0:0] mux_2level_tapbuf_basis_input2_mem1_2_out ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( mux_2level_tapbuf_basis_input2_mem1_2_out[0] ) , .X ( out[0] ) ) ; sb_2__2__mux_2level_tapbuf_basis_input2_mem1_80 mux_l1_in_0_ ( .in ( in[0:1] ) , .mem ( sram[0] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) , @@ -17102,9 +18766,6 @@ sb_2__2__mux_2level_tapbuf_basis_input2_mem1_82 mux_l2_in_0_ ( .mem ( sram[1] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_4 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_2_out ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_172 ( .A ( BUF_net_173 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_173 ( - .A ( mux_2level_tapbuf_basis_input2_mem1_2_out[0] ) , .Y ( BUF_net_173 ) ) ; endmodule @@ -17239,9 +18900,9 @@ sb_2__2__mux_2level_tapbuf_basis_input2_mem1_76 mux_l2_in_0_ ( .mem ( sram[1] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_4 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_2_out ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_170 ( .A ( BUF_net_171 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_171 ( - .A ( mux_2level_tapbuf_basis_input2_mem1_2_out[0] ) , .Y ( BUF_net_171 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_156 ( .A ( BUF_net_157 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_157 ( + .A ( mux_2level_tapbuf_basis_input2_mem1_2_out[0] ) , .Y ( BUF_net_157 ) ) ; endmodule @@ -17253,25 +18914,11 @@ input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -wire copt_net_180 ; - sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( copt_net_180 ) ) ; + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__buf_6 FTB_73__72 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1376 ( .A ( copt_net_182 ) , - .X ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1377 ( .A ( copt_net_180 ) , - .X ( copt_net_181 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1378 ( .A ( copt_net_185 ) , - .X ( copt_net_182 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1379 ( .A ( copt_net_184 ) , - .X ( copt_net_183 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1380 ( .A ( copt_net_181 ) , - .X ( copt_net_184 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1381 ( .A ( copt_net_183 ) , - .X ( copt_net_185 ) ) ; endmodule @@ -17946,9 +19593,9 @@ sb_2__2__mux_2level_tapbuf_basis_input2_mem1_71 mux_l2_in_0_ ( .mem ( sram[1] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_168 ( .A ( BUF_net_169 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_169 ( - .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_169 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_154 ( .A ( BUF_net_155 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_155 ( + .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_155 ) ) ; endmodule @@ -17997,9 +19644,9 @@ sb_2__2__mux_2level_tapbuf_basis_input2_mem1_69 mux_l2_in_0_ ( .mem ( sram[1] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_166 ( .A ( BUF_net_167 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_167 ( - .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_167 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_152 ( .A ( BUF_net_153 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_153 ( + .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_153 ) ) ; endmodule @@ -18048,9 +19695,9 @@ sb_2__2__mux_2level_tapbuf_basis_input2_mem1_67 mux_l2_in_0_ ( .mem ( sram[1] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_164 ( .A ( BUF_net_165 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_165 ( - .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_165 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_150 ( .A ( BUF_net_151 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_151 ( + .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_151 ) ) ; endmodule @@ -18062,7 +19709,7 @@ input [0:0] mem_inv ; output [0:0] out ; input p0 ; -sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , +sky130_fd_sc_hd__mux2_2 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ; endmodule @@ -18089,6 +19736,8 @@ input p0 ; wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ; wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) ) ; sb_2__2__mux_2level_tapbuf_basis_input2_mem1_64 mux_l1_in_0_ ( .in ( in ) , .mem ( sram[0] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) , @@ -18099,9 +19748,6 @@ sb_2__2__mux_2level_tapbuf_basis_input2_mem1_65 mux_l2_in_0_ ( .mem ( sram[1] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_162 ( .A ( BUF_net_163 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_163 ( - .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_163 ) ) ; endmodule @@ -18150,9 +19796,9 @@ sb_2__2__mux_2level_tapbuf_basis_input2_mem1_63 mux_l2_in_0_ ( .mem ( sram[1] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_160 ( .A ( BUF_net_161 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_161 ( - .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_161 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_148 ( .A ( BUF_net_149 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_149 ( + .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_149 ) ) ; endmodule @@ -18201,9 +19847,9 @@ sb_2__2__mux_2level_tapbuf_basis_input2_mem1_61 mux_l2_in_0_ ( .mem ( sram[1] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_158 ( .A ( BUF_net_159 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_159 ( - .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_159 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_146 ( .A ( BUF_net_147 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_147 ( + .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_147 ) ) ; endmodule @@ -18252,9 +19898,9 @@ sb_2__2__mux_2level_tapbuf_basis_input2_mem1_59 mux_l2_in_0_ ( .mem ( sram[1] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_156 ( .A ( BUF_net_157 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_157 ( - .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_157 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_144 ( .A ( BUF_net_145 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_145 ( + .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_145 ) ) ; endmodule @@ -18303,9 +19949,9 @@ sb_2__2__mux_2level_tapbuf_basis_input2_mem1_57 mux_l2_in_0_ ( .mem ( sram[1] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_154 ( .A ( BUF_net_155 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_155 ( - .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_155 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_142 ( .A ( BUF_net_143 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_143 ( + .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_143 ) ) ; endmodule @@ -18354,9 +20000,9 @@ sb_2__2__mux_2level_tapbuf_basis_input2_mem1_55 mux_l2_in_0_ ( .mem ( sram[1] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_152 ( .A ( BUF_net_153 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_153 ( - .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_153 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_140 ( .A ( BUF_net_141 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_141 ( + .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_141 ) ) ; endmodule @@ -18405,9 +20051,9 @@ sb_2__2__mux_2level_tapbuf_basis_input2_mem1_53 mux_l2_in_0_ ( .mem ( sram[1] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_150 ( .A ( BUF_net_151 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_151 ( - .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_151 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_138 ( .A ( BUF_net_139 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_139 ( + .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_139 ) ) ; endmodule @@ -18456,9 +20102,9 @@ sb_2__2__mux_2level_tapbuf_basis_input2_mem1_51 mux_l2_in_0_ ( .mem ( sram[1] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_148 ( .A ( BUF_net_149 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_149 ( - .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_149 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_136 ( .A ( BUF_net_137 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_137 ( + .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_137 ) ) ; endmodule @@ -18470,7 +20116,7 @@ input [0:0] mem_inv ; output [0:0] out ; input p0 ; -sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , +sky130_fd_sc_hd__mux2_2 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ; endmodule @@ -18507,9 +20153,8 @@ sb_2__2__mux_2level_tapbuf_basis_input2_mem1_49 mux_l2_in_0_ ( .mem ( sram[1] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_146 ( .A ( BUF_net_147 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_147 ( - .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_147 ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_135 ( + .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) ) ; endmodule @@ -18521,7 +20166,7 @@ input [0:0] mem_inv ; output [0:0] out ; input p0 ; -sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , +sky130_fd_sc_hd__mux2_2 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ; endmodule @@ -18558,9 +20203,8 @@ sb_2__2__mux_2level_tapbuf_basis_input2_mem1_47 mux_l2_in_0_ ( .mem ( sram[1] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_144 ( .A ( BUF_net_145 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_145 ( - .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_145 ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_134 ( + .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) ) ; endmodule @@ -18599,8 +20243,6 @@ input p0 ; wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ; wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) ) ; sb_2__2__mux_2level_tapbuf_basis_input2_mem1_44 mux_l1_in_0_ ( .in ( in ) , .mem ( sram[0] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) , @@ -18611,6 +20253,8 @@ sb_2__2__mux_2level_tapbuf_basis_input2_mem1_45 mux_l2_in_0_ ( .mem ( sram[1] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_133 ( + .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) ) ; endmodule @@ -18659,9 +20303,9 @@ sb_2__2__mux_2level_tapbuf_basis_input2_mem1_43 mux_l2_in_0_ ( .mem ( sram[1] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_142 ( .A ( BUF_net_143 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_143 ( - .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_143 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_131 ( .A ( BUF_net_132 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_132 ( + .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_132 ) ) ; endmodule @@ -18700,8 +20344,6 @@ input p0 ; wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ; wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) ) ; sb_2__2__mux_2level_tapbuf_basis_input2_mem1_40 mux_l1_in_0_ ( .in ( in ) , .mem ( sram[0] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) , @@ -18712,6 +20354,8 @@ sb_2__2__mux_2level_tapbuf_basis_input2_mem1_41 mux_l2_in_0_ ( .mem ( sram[1] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_130 ( + .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) ) ; endmodule @@ -18760,9 +20404,9 @@ sb_2__2__mux_2level_tapbuf_basis_input2_mem1_39 mux_l2_in_0_ ( .mem ( sram[1] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_140 ( .A ( BUF_net_141 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_141 ( - .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_141 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_128 ( .A ( BUF_net_129 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_129 ( + .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_129 ) ) ; endmodule @@ -18811,9 +20455,9 @@ sb_2__2__mux_2level_tapbuf_basis_input2_mem1_37 mux_l2_in_0_ ( .mem ( sram[1] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_138 ( .A ( BUF_net_139 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_139 ( - .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_139 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_126 ( .A ( BUF_net_127 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_127 ( + .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_127 ) ) ; endmodule @@ -18862,9 +20506,9 @@ sb_2__2__mux_2level_tapbuf_basis_input2_mem1_35 mux_l2_in_0_ ( .mem ( sram[1] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_136 ( .A ( BUF_net_137 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_137 ( - .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_137 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_124 ( .A ( BUF_net_125 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_125 ( + .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_125 ) ) ; endmodule @@ -18913,9 +20557,9 @@ sb_2__2__mux_2level_tapbuf_basis_input2_mem1_33 mux_l2_in_0_ ( .mem ( sram[1] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_134 ( .A ( BUF_net_135 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_135 ( - .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_135 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_122 ( .A ( BUF_net_123 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_123 ( + .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_123 ) ) ; endmodule @@ -18964,9 +20608,9 @@ sb_2__2__mux_2level_tapbuf_basis_input2_mem1_31 mux_l2_in_0_ ( .mem ( sram[1] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_132 ( .A ( BUF_net_133 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_133 ( - .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_133 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_120 ( .A ( BUF_net_121 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_121 ( + .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_121 ) ) ; endmodule @@ -19015,9 +20659,9 @@ sb_2__2__mux_2level_tapbuf_basis_input2_mem1_29 mux_l2_in_0_ ( .mem ( sram[1] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_130 ( .A ( BUF_net_131 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_131 ( - .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_131 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_118 ( .A ( BUF_net_119 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_119 ( + .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_119 ) ) ; endmodule @@ -19029,7 +20673,7 @@ input [0:0] mem_inv ; output [0:0] out ; input p0 ; -sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , +sky130_fd_sc_hd__mux2_2 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ; endmodule @@ -19056,6 +20700,8 @@ input p0 ; wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ; wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) ) ; sb_2__2__mux_2level_tapbuf_basis_input2_mem1_26 mux_l1_in_0_ ( .in ( in ) , .mem ( sram[0] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) , @@ -19066,9 +20712,6 @@ sb_2__2__mux_2level_tapbuf_basis_input2_mem1_27 mux_l2_in_0_ ( .mem ( sram[1] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_128 ( .A ( BUF_net_129 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_129 ( - .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_129 ) ) ; endmodule @@ -19117,9 +20760,9 @@ sb_2__2__mux_2level_tapbuf_basis_input2_mem1_25 mux_l2_in_0_ ( .mem ( sram[1] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_126 ( .A ( BUF_net_127 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_127 ( - .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_127 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_116 ( .A ( BUF_net_117 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_117 ( + .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_117 ) ) ; endmodule @@ -19131,7 +20774,7 @@ input [0:0] mem_inv ; output [0:0] out ; input p0 ; -sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , +sky130_fd_sc_hd__mux2_2 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ; endmodule @@ -19168,9 +20811,8 @@ sb_2__2__mux_2level_tapbuf_basis_input2_mem1_23 mux_l2_in_0_ ( .mem ( sram[1] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_124 ( .A ( BUF_net_125 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_125 ( - .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_125 ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_115 ( + .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) ) ; endmodule @@ -19209,6 +20851,8 @@ input p0 ; wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ; wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) ) ; sb_2__2__mux_2level_tapbuf_basis_input2_mem1_20 mux_l1_in_0_ ( .in ( in ) , .mem ( sram[0] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) , @@ -19219,9 +20863,6 @@ sb_2__2__mux_2level_tapbuf_basis_input2_mem1_21 mux_l2_in_0_ ( .mem ( sram[1] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_122 ( .A ( BUF_net_123 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_123 ( - .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_123 ) ) ; endmodule @@ -19233,7 +20874,7 @@ input [0:0] mem_inv ; output [0:0] out ; input p0 ; -sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , +sky130_fd_sc_hd__mux2_2 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ; endmodule @@ -19260,8 +20901,6 @@ input p0 ; wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ; wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) ) ; sb_2__2__mux_2level_tapbuf_basis_input2_mem1_18 mux_l1_in_0_ ( .in ( in ) , .mem ( sram[0] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) , @@ -19272,6 +20911,8 @@ sb_2__2__mux_2level_tapbuf_basis_input2_mem1_19 mux_l2_in_0_ ( .mem ( sram[1] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_114 ( + .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) ) ; endmodule @@ -19320,9 +20961,9 @@ sb_2__2__mux_2level_tapbuf_basis_input2_mem1_17 mux_l2_in_0_ ( .mem ( sram[1] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_120 ( .A ( BUF_net_121 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_121 ( - .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_121 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_112 ( .A ( BUF_net_113 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_113 ( + .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_113 ) ) ; endmodule @@ -19371,9 +21012,9 @@ sb_2__2__mux_2level_tapbuf_basis_input2_mem1_15 mux_l2_in_0_ ( .mem ( sram[1] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_118 ( .A ( BUF_net_119 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_119 ( - .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_119 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_110 ( .A ( BUF_net_111 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_111 ( + .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_111 ) ) ; endmodule @@ -19412,6 +21053,8 @@ input p0 ; wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ; wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) ) ; sb_2__2__mux_2level_tapbuf_basis_input2_mem1_12 mux_l1_in_0_ ( .in ( in ) , .mem ( sram[0] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) , @@ -19422,9 +21065,6 @@ sb_2__2__mux_2level_tapbuf_basis_input2_mem1_13 mux_l2_in_0_ ( .mem ( sram[1] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_116 ( .A ( BUF_net_117 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_117 ( - .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_117 ) ) ; endmodule @@ -19473,9 +21113,9 @@ sb_2__2__mux_2level_tapbuf_basis_input2_mem1_11 mux_l2_in_0_ ( .mem ( sram[1] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_114 ( .A ( BUF_net_115 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_115 ( - .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_115 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_108 ( .A ( BUF_net_109 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_109 ( + .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_109 ) ) ; endmodule @@ -19514,6 +21154,8 @@ input p0 ; wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ; wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) ) ; sb_2__2__mux_2level_tapbuf_basis_input2_mem1_8 mux_l1_in_0_ ( .in ( in ) , .mem ( sram[0] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) , @@ -19524,9 +21166,6 @@ sb_2__2__mux_2level_tapbuf_basis_input2_mem1_9 mux_l2_in_0_ ( .mem ( sram[1] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_112 ( .A ( BUF_net_113 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_113 ( - .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_113 ) ) ; endmodule @@ -19565,8 +21204,6 @@ input p0 ; wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ; wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) ) ; sb_2__2__mux_2level_tapbuf_basis_input2_mem1_6 mux_l1_in_0_ ( .in ( in ) , .mem ( sram[0] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) , @@ -19577,6 +21214,8 @@ sb_2__2__mux_2level_tapbuf_basis_input2_mem1_7 mux_l2_in_0_ ( .mem ( sram[1] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_107 ( + .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) ) ; endmodule @@ -19625,9 +21264,9 @@ sb_2__2__mux_2level_tapbuf_basis_input2_mem1_5 mux_l2_in_0_ ( .mem ( sram[1] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_110 ( .A ( BUF_net_111 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_111 ( - .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_111 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_105 ( .A ( BUF_net_106 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_106 ( + .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_106 ) ) ; endmodule @@ -19666,6 +21305,8 @@ input p0 ; wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ; wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) ) ; sb_2__2__mux_2level_tapbuf_basis_input2_mem1_2 mux_l1_in_0_ ( .in ( in ) , .mem ( sram[0] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) , @@ -19676,8 +21317,6 @@ sb_2__2__mux_2level_tapbuf_basis_input2_mem1_3 mux_l2_in_0_ ( .mem ( sram[1] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_109 ( - .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) ) ; endmodule @@ -19726,7 +21365,7 @@ sb_2__2__mux_2level_tapbuf_basis_input2_mem1_1 mux_l2_in_0_ ( .mem ( sram[1] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_108 ( +sky130_fd_sc_hd__buf_6 BUFT_RR_104 ( .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) ) ; endmodule @@ -19959,7 +21598,7 @@ input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ropt_net_200 ) , +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ropt_net_191 ) , .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; @@ -19968,18 +21607,30 @@ sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__buf_1 FTB_25__24 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1429 ( .A ( ccff_head[0] ) , - .X ( ropt_net_197 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1430 ( .A ( ropt_net_201 ) , - .X ( ropt_net_198 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1431 ( .A ( ropt_net_198 ) , - .X ( ropt_net_199 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1432 ( .A ( ropt_net_199 ) , - .X ( ropt_net_200 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1433 ( .A ( ropt_net_202 ) , - .X ( ropt_net_201 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1434 ( .A ( ropt_net_197 ) , - .X ( ropt_net_202 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1344 ( .A ( ccff_head[0] ) , + .X ( copt_net_164 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1345 ( .A ( copt_net_164 ) , + .X ( copt_net_165 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1346 ( .A ( copt_net_165 ) , + .X ( copt_net_166 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1347 ( .A ( copt_net_166 ) , + .X ( copt_net_167 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1348 ( .A ( copt_net_167 ) , + .X ( copt_net_168 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1349 ( .A ( ropt_net_195 ) , + .X ( copt_net_169 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1367 ( .A ( copt_net_169 ) , + .X ( ropt_net_190 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1368 ( .A ( ropt_net_192 ) , + .X ( ropt_net_191 ) ) ; +sky130_fd_sc_hd__buf_2 ropt_h_inst_1369 ( .A ( ropt_net_190 ) , + .X ( ropt_net_192 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1370 ( .A ( copt_net_168 ) , + .X ( ropt_net_193 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1371 ( .A ( ropt_net_193 ) , + .X ( ropt_net_194 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1372 ( .A ( ropt_net_194 ) , + .X ( ropt_net_195 ) ) ; endmodule @@ -19991,10 +21642,14 @@ input [0:2] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -20005,10 +21660,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -20074,9 +21733,9 @@ sb_2__2__mux_2level_tapbuf_basis_input3_mem3 mux_l2_in_0_ ( .mem ( local_encoder2to3_1_data ) , .mem_inv ( local_encoder2to3_1_data_inv ) , .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_106 ( .A ( BUF_net_107 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_107 ( - .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_107 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_102 ( .A ( BUF_net_103 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_103 ( + .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_103 ) ) ; endmodule @@ -20088,10 +21747,14 @@ input [0:2] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -20102,10 +21765,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -20171,9 +21838,9 @@ sb_2__2__mux_2level_tapbuf_basis_input3_mem3_21 mux_l2_in_0_ ( .mem ( local_encoder2to3_1_data ) , .mem_inv ( local_encoder2to3_1_data_inv ) , .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_104 ( .A ( BUF_net_105 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_105 ( - .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_105 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_100 ( .A ( BUF_net_101 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_101 ( + .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_101 ) ) ; endmodule @@ -20185,10 +21852,14 @@ input [0:2] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -20199,10 +21870,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -20268,9 +21943,9 @@ sb_2__2__mux_2level_tapbuf_basis_input3_mem3_19 mux_l2_in_0_ ( .mem ( local_encoder2to3_1_data ) , .mem_inv ( local_encoder2to3_1_data_inv ) , .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_102 ( .A ( BUF_net_103 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_103 ( - .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_103 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_98 ( .A ( BUF_net_99 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_99 ( + .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_99 ) ) ; endmodule @@ -20282,10 +21957,14 @@ input [0:2] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -20296,10 +21975,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -20365,9 +22048,9 @@ sb_2__2__mux_2level_tapbuf_basis_input3_mem3_17 mux_l2_in_0_ ( .mem ( local_encoder2to3_1_data ) , .mem_inv ( local_encoder2to3_1_data_inv ) , .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_100 ( .A ( BUF_net_101 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_101 ( - .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_101 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_96 ( .A ( BUF_net_97 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_97 ( + .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_97 ) ) ; endmodule @@ -20379,10 +22062,14 @@ input [0:2] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -20393,10 +22080,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -20462,9 +22153,9 @@ sb_2__2__mux_2level_tapbuf_basis_input3_mem3_15 mux_l2_in_0_ ( .mem ( local_encoder2to3_1_data ) , .mem_inv ( local_encoder2to3_1_data_inv ) , .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_98 ( .A ( BUF_net_99 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_99 ( - .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_99 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_94 ( .A ( BUF_net_95 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_95 ( + .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_95 ) ) ; endmodule @@ -20476,10 +22167,14 @@ input [0:2] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -20490,10 +22185,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -20559,9 +22258,9 @@ sb_2__2__mux_2level_tapbuf_basis_input3_mem3_13 mux_l2_in_0_ ( .mem ( local_encoder2to3_1_data ) , .mem_inv ( local_encoder2to3_1_data_inv ) , .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_96 ( .A ( BUF_net_97 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_97 ( - .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_97 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_92 ( .A ( BUF_net_93 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_93 ( + .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_93 ) ) ; endmodule @@ -20573,10 +22272,14 @@ input [0:2] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -20587,10 +22290,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -20656,9 +22363,9 @@ sb_2__2__mux_2level_tapbuf_basis_input3_mem3_11 mux_l2_in_0_ ( .mem ( local_encoder2to3_1_data ) , .mem_inv ( local_encoder2to3_1_data_inv ) , .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_94 ( .A ( BUF_net_95 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_95 ( - .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_95 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_90 ( .A ( BUF_net_91 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_91 ( + .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_91 ) ) ; endmodule @@ -20670,10 +22377,14 @@ input [0:2] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -20684,10 +22395,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -20753,9 +22468,9 @@ sb_2__2__mux_2level_tapbuf_basis_input3_mem3_9 mux_l2_in_0_ ( .mem ( local_encoder2to3_1_data ) , .mem_inv ( local_encoder2to3_1_data_inv ) , .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_92 ( .A ( BUF_net_93 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_93 ( - .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_93 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_88 ( .A ( BUF_net_89 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_89 ( + .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_89 ) ) ; endmodule @@ -20767,10 +22482,14 @@ input [0:2] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -20781,10 +22500,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -20850,9 +22573,9 @@ sb_2__2__mux_2level_tapbuf_basis_input3_mem3_7 mux_l2_in_0_ ( .mem ( local_encoder2to3_1_data ) , .mem_inv ( local_encoder2to3_1_data_inv ) , .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_90 ( .A ( BUF_net_91 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_91 ( - .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_91 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_86 ( .A ( BUF_net_87 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_87 ( + .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_87 ) ) ; endmodule @@ -20864,10 +22587,14 @@ input [0:2] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -20878,10 +22605,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -20947,7 +22678,7 @@ sb_2__2__mux_2level_tapbuf_basis_input3_mem3_5 mux_l2_in_0_ ( .mem ( local_encoder2to3_1_data ) , .mem_inv ( local_encoder2to3_1_data_inv ) , .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_89 ( +sky130_fd_sc_hd__buf_6 BUFT_RR_85 ( .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .X ( out[0] ) ) ; endmodule @@ -20960,10 +22691,14 @@ input [0:2] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -20974,10 +22709,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -21027,6 +22766,8 @@ wire [0:2] local_encoder2to3_1_data_inv ; wire [0:0] mux_2level_tapbuf_basis_input3_mem3_0_out ; wire [0:0] mux_2level_tapbuf_basis_input3_mem3_1_out ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .X ( out[0] ) ) ; sb_2__2__local_encoder2to3_2 local_encoder2to3_0_ ( .addr ( sram[0:1] ) , .data ( local_encoder2to3_0_data ) , .data_inv ( local_encoder2to3_0_data_inv ) ) ; @@ -21043,9 +22784,6 @@ sb_2__2__mux_2level_tapbuf_basis_input3_mem3_3 mux_l2_in_0_ ( .mem ( local_encoder2to3_1_data ) , .mem_inv ( local_encoder2to3_1_data_inv ) , .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_87 ( .A ( BUF_net_88 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_88 ( - .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_88 ) ) ; endmodule @@ -21057,10 +22795,14 @@ input [0:2] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -21071,10 +22813,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -21124,6 +22870,8 @@ wire [0:2] local_encoder2to3_1_data_inv ; wire [0:0] mux_2level_tapbuf_basis_input3_mem3_0_out ; wire [0:0] mux_2level_tapbuf_basis_input3_mem3_1_out ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .X ( out[0] ) ) ; sb_2__2__local_encoder2to3_0 local_encoder2to3_0_ ( .addr ( sram[0:1] ) , .data ( local_encoder2to3_0_data ) , .data_inv ( local_encoder2to3_0_data_inv ) ) ; @@ -21140,9 +22888,6 @@ sb_2__2__mux_2level_tapbuf_basis_input3_mem3_1 mux_l2_in_0_ ( .mem ( local_encoder2to3_1_data ) , .mem_inv ( local_encoder2to3_1_data_inv ) , .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_85 ( .A ( BUF_net_86 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_86 ( - .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_86 ) ) ; endmodule @@ -21303,84 +23048,84 @@ sb_2__2__mux_2level_tapbuf_size4_0 mux_bottom_track_1 ( .sram ( mux_2level_tapbuf_size4_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 , SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) , - .out ( chany_bottom_out[0] ) , .p0 ( optlc_net_178 ) ) ; + .out ( chany_bottom_out[0] ) , .p0 ( optlc_net_162 ) ) ; sb_2__2__mux_2level_tapbuf_size4_1 mux_bottom_track_3 ( .in ( { bottom_left_grid_pin_44_[0] , bottom_left_grid_pin_47_[0] , bottom_left_grid_pin_50_[0] , chanx_left_in[2] } ) , .sram ( mux_2level_tapbuf_size4_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 , SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 } ) , - .out ( chany_bottom_out[1] ) , .p0 ( optlc_net_178 ) ) ; + .out ( chany_bottom_out[1] ) , .p0 ( optlc_net_162 ) ) ; sb_2__2__mux_2level_tapbuf_size4_2 mux_bottom_track_5 ( .in ( { bottom_left_grid_pin_45_[0] , bottom_left_grid_pin_48_[0] , bottom_left_grid_pin_51_[0] , chanx_left_in[3] } ) , .sram ( mux_2level_tapbuf_size4_2_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_9 , SYNOPSYS_UNCONNECTED_10 , SYNOPSYS_UNCONNECTED_11 , SYNOPSYS_UNCONNECTED_12 } ) , - .out ( chany_bottom_out[2] ) , .p0 ( optlc_net_174 ) ) ; + .out ( chany_bottom_out[2] ) , .p0 ( optlc_net_162 ) ) ; sb_2__2__mux_2level_tapbuf_size4_3 mux_bottom_track_7 ( .in ( { bottom_right_grid_pin_1_[0] , bottom_left_grid_pin_46_[0] , bottom_left_grid_pin_49_[0] , chanx_left_in[4] } ) , .sram ( mux_2level_tapbuf_size4_3_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 , SYNOPSYS_UNCONNECTED_15 , SYNOPSYS_UNCONNECTED_16 } ) , - .out ( chany_bottom_out[3] ) , .p0 ( optlc_net_178 ) ) ; + .out ( chany_bottom_out[3] ) , .p0 ( optlc_net_162 ) ) ; sb_2__2__mux_2level_tapbuf_size4_4 mux_bottom_track_9 ( .in ( { bottom_left_grid_pin_44_[0] , bottom_left_grid_pin_47_[0] , bottom_left_grid_pin_50_[0] , chanx_left_in[5] } ) , .sram ( mux_2level_tapbuf_size4_4_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_17 , SYNOPSYS_UNCONNECTED_18 , SYNOPSYS_UNCONNECTED_19 , SYNOPSYS_UNCONNECTED_20 } ) , - .out ( chany_bottom_out[4] ) , .p0 ( optlc_net_177 ) ) ; + .out ( chany_bottom_out[4] ) , .p0 ( optlc_net_160 ) ) ; sb_2__2__mux_2level_tapbuf_size4_5 mux_bottom_track_11 ( .in ( { bottom_left_grid_pin_45_[0] , bottom_left_grid_pin_48_[0] , bottom_left_grid_pin_51_[0] , chanx_left_in[6] } ) , .sram ( mux_2level_tapbuf_size4_5_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_21 , SYNOPSYS_UNCONNECTED_22 , SYNOPSYS_UNCONNECTED_23 , SYNOPSYS_UNCONNECTED_24 } ) , - .out ( chany_bottom_out[5] ) , .p0 ( optlc_net_174 ) ) ; + .out ( chany_bottom_out[5] ) , .p0 ( optlc_net_162 ) ) ; sb_2__2__mux_2level_tapbuf_size4_6 mux_left_track_1 ( .in ( { chany_bottom_in[29] , left_top_grid_pin_1_[0] , left_bottom_grid_pin_38_[0] , left_bottom_grid_pin_41_[0] } ) , .sram ( mux_2level_tapbuf_size4_6_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_25 , SYNOPSYS_UNCONNECTED_26 , SYNOPSYS_UNCONNECTED_27 , SYNOPSYS_UNCONNECTED_28 } ) , - .out ( chanx_left_out[0] ) , .p0 ( optlc_net_174 ) ) ; + .out ( chanx_left_out[0] ) , .p0 ( optlc_net_160 ) ) ; sb_2__2__mux_2level_tapbuf_size4_7 mux_left_track_3 ( .in ( { chany_bottom_in[0] , left_bottom_grid_pin_36_[0] , left_bottom_grid_pin_39_[0] , left_bottom_grid_pin_42_[0] } ) , .sram ( mux_2level_tapbuf_size4_7_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_29 , SYNOPSYS_UNCONNECTED_30 , SYNOPSYS_UNCONNECTED_31 , SYNOPSYS_UNCONNECTED_32 } ) , - .out ( chanx_left_out[1] ) , .p0 ( optlc_net_174 ) ) ; + .out ( chanx_left_out[1] ) , .p0 ( optlc_net_160 ) ) ; sb_2__2__mux_2level_tapbuf_size4_8 mux_left_track_5 ( .in ( { chany_bottom_in[1] , left_bottom_grid_pin_37_[0] , left_bottom_grid_pin_40_[0] , left_bottom_grid_pin_43_[0] } ) , .sram ( mux_2level_tapbuf_size4_8_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_33 , SYNOPSYS_UNCONNECTED_34 , SYNOPSYS_UNCONNECTED_35 , SYNOPSYS_UNCONNECTED_36 } ) , - .out ( chanx_left_out[2] ) , .p0 ( optlc_net_174 ) ) ; + .out ( chanx_left_out[2] ) , .p0 ( optlc_net_160 ) ) ; sb_2__2__mux_2level_tapbuf_size4_9 mux_left_track_7 ( .in ( { chany_bottom_in[2] , left_top_grid_pin_1_[0] , left_bottom_grid_pin_38_[0] , left_bottom_grid_pin_41_[0] } ) , .sram ( mux_2level_tapbuf_size4_9_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_37 , SYNOPSYS_UNCONNECTED_38 , SYNOPSYS_UNCONNECTED_39 , SYNOPSYS_UNCONNECTED_40 } ) , - .out ( chanx_left_out[3] ) , .p0 ( optlc_net_174 ) ) ; + .out ( chanx_left_out[3] ) , .p0 ( optlc_net_160 ) ) ; sb_2__2__mux_2level_tapbuf_size4_10 mux_left_track_9 ( .in ( { chany_bottom_in[3] , left_bottom_grid_pin_36_[0] , left_bottom_grid_pin_39_[0] , left_bottom_grid_pin_42_[0] } ) , .sram ( mux_2level_tapbuf_size4_10_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_41 , SYNOPSYS_UNCONNECTED_42 , SYNOPSYS_UNCONNECTED_43 , SYNOPSYS_UNCONNECTED_44 } ) , - .out ( chanx_left_out[4] ) , .p0 ( optlc_net_174 ) ) ; + .out ( chanx_left_out[4] ) , .p0 ( optlc_net_160 ) ) ; sb_2__2__mux_2level_tapbuf_size4 mux_left_track_11 ( .in ( { chany_bottom_in[4] , left_bottom_grid_pin_37_[0] , left_bottom_grid_pin_40_[0] , left_bottom_grid_pin_43_[0] } ) , .sram ( mux_2level_tapbuf_size4_11_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_45 , SYNOPSYS_UNCONNECTED_46 , SYNOPSYS_UNCONNECTED_47 , SYNOPSYS_UNCONNECTED_48 } ) , - .out ( chanx_left_out[5] ) , .p0 ( optlc_net_174 ) ) ; + .out ( chanx_left_out[5] ) , .p0 ( optlc_net_160 ) ) ; sb_2__2__mux_2level_tapbuf_size4_mem_0 mem_bottom_track_1 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( mux_2level_tapbuf_size4_mem_0_ccff_tail ) , @@ -21444,187 +23189,187 @@ sb_2__2__mux_2level_tapbuf_size2_0 mux_bottom_track_13 ( .in ( { bottom_right_grid_pin_1_[0] , chanx_left_in[7] } ) , .sram ( mux_2level_tapbuf_size2_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_49 , SYNOPSYS_UNCONNECTED_50 } ) , - .out ( chany_bottom_out[6] ) , .p0 ( optlc_net_177 ) ) ; + .out ( chany_bottom_out[6] ) , .p0 ( optlc_net_162 ) ) ; sb_2__2__mux_2level_tapbuf_size2_1 mux_bottom_track_15 ( .in ( { bottom_left_grid_pin_44_[0] , chanx_left_in[8] } ) , .sram ( mux_2level_tapbuf_size2_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_51 , SYNOPSYS_UNCONNECTED_52 } ) , - .out ( chany_bottom_out[7] ) , .p0 ( optlc_net_175 ) ) ; + .out ( chany_bottom_out[7] ) , .p0 ( optlc_net_163 ) ) ; sb_2__2__mux_2level_tapbuf_size2_2 mux_bottom_track_17 ( .in ( { bottom_left_grid_pin_45_[0] , chanx_left_in[9] } ) , .sram ( mux_2level_tapbuf_size2_2_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_53 , SYNOPSYS_UNCONNECTED_54 } ) , - .out ( chany_bottom_out[8] ) , .p0 ( optlc_net_175 ) ) ; + .out ( chany_bottom_out[8] ) , .p0 ( optlc_net_163 ) ) ; sb_2__2__mux_2level_tapbuf_size2_3 mux_bottom_track_19 ( .in ( { bottom_left_grid_pin_46_[0] , chanx_left_in[10] } ) , .sram ( mux_2level_tapbuf_size2_3_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_55 , SYNOPSYS_UNCONNECTED_56 } ) , - .out ( chany_bottom_out[9] ) , .p0 ( optlc_net_175 ) ) ; + .out ( chany_bottom_out[9] ) , .p0 ( optlc_net_163 ) ) ; sb_2__2__mux_2level_tapbuf_size2_4 mux_bottom_track_21 ( .in ( { bottom_left_grid_pin_47_[0] , chanx_left_in[11] } ) , .sram ( mux_2level_tapbuf_size2_4_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_57 , SYNOPSYS_UNCONNECTED_58 } ) , - .out ( chany_bottom_out[10] ) , .p0 ( optlc_net_179 ) ) ; + .out ( chany_bottom_out[10] ) , .p0 ( optlc_net_163 ) ) ; sb_2__2__mux_2level_tapbuf_size2_5 mux_bottom_track_23 ( .in ( { bottom_left_grid_pin_48_[0] , chanx_left_in[12] } ) , .sram ( mux_2level_tapbuf_size2_5_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_59 , SYNOPSYS_UNCONNECTED_60 } ) , - .out ( chany_bottom_out[11] ) , .p0 ( optlc_net_179 ) ) ; + .out ( chany_bottom_out[11] ) , .p0 ( optlc_net_162 ) ) ; sb_2__2__mux_2level_tapbuf_size2_6 mux_bottom_track_25 ( .in ( { bottom_left_grid_pin_49_[0] , chanx_left_in[13] } ) , .sram ( mux_2level_tapbuf_size2_6_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_61 , SYNOPSYS_UNCONNECTED_62 } ) , - .out ( chany_bottom_out[12] ) , .p0 ( optlc_net_178 ) ) ; + .out ( chany_bottom_out[12] ) , .p0 ( optlc_net_163 ) ) ; sb_2__2__mux_2level_tapbuf_size2_7 mux_bottom_track_27 ( .in ( { bottom_left_grid_pin_50_[0] , chanx_left_in[14] } ) , .sram ( mux_2level_tapbuf_size2_7_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_63 , SYNOPSYS_UNCONNECTED_64 } ) , - .out ( chany_bottom_out[13] ) , .p0 ( optlc_net_177 ) ) ; + .out ( chany_bottom_out[13] ) , .p0 ( optlc_net_162 ) ) ; sb_2__2__mux_2level_tapbuf_size2_8 mux_bottom_track_39 ( .in ( { bottom_left_grid_pin_44_[0] , chanx_left_in[20] } ) , .sram ( mux_2level_tapbuf_size2_8_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_65 , SYNOPSYS_UNCONNECTED_66 } ) , - .out ( chany_bottom_out[19] ) , .p0 ( optlc_net_179 ) ) ; + .out ( chany_bottom_out[19] ) , .p0 ( optlc_net_162 ) ) ; sb_2__2__mux_2level_tapbuf_size2_9 mux_bottom_track_41 ( .in ( { bottom_left_grid_pin_45_[0] , chanx_left_in[21] } ) , .sram ( mux_2level_tapbuf_size2_9_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_67 , SYNOPSYS_UNCONNECTED_68 } ) , - .out ( chany_bottom_out[20] ) , .p0 ( optlc_net_175 ) ) ; + .out ( chany_bottom_out[20] ) , .p0 ( optlc_net_162 ) ) ; sb_2__2__mux_2level_tapbuf_size2_10 mux_bottom_track_43 ( .in ( { bottom_left_grid_pin_46_[0] , chanx_left_in[22] } ) , .sram ( mux_2level_tapbuf_size2_10_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_69 , SYNOPSYS_UNCONNECTED_70 } ) , - .out ( chany_bottom_out[21] ) , .p0 ( optlc_net_175 ) ) ; + .out ( chany_bottom_out[21] ) , .p0 ( optlc_net_163 ) ) ; sb_2__2__mux_2level_tapbuf_size2_11 mux_bottom_track_47 ( .in ( { bottom_left_grid_pin_48_[0] , chanx_left_in[24] } ) , .sram ( mux_2level_tapbuf_size2_11_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_71 , SYNOPSYS_UNCONNECTED_72 } ) , - .out ( chany_bottom_out[23] ) , .p0 ( optlc_net_175 ) ) ; + .out ( chany_bottom_out[23] ) , .p0 ( optlc_net_163 ) ) ; sb_2__2__mux_2level_tapbuf_size2_12 mux_bottom_track_49 ( .in ( { bottom_left_grid_pin_49_[0] , chanx_left_in[25] } ) , .sram ( mux_2level_tapbuf_size2_12_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_73 , SYNOPSYS_UNCONNECTED_74 } ) , - .out ( chany_bottom_out[24] ) , .p0 ( optlc_net_177 ) ) ; + .out ( chany_bottom_out[24] ) , .p0 ( optlc_net_163 ) ) ; sb_2__2__mux_2level_tapbuf_size2_13 mux_bottom_track_51 ( .in ( { bottom_left_grid_pin_50_[0] , chanx_left_in[26] } ) , .sram ( mux_2level_tapbuf_size2_13_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_75 , SYNOPSYS_UNCONNECTED_76 } ) , - .out ( chany_bottom_out[25] ) , .p0 ( optlc_net_177 ) ) ; + .out ( chany_bottom_out[25] ) , .p0 ( optlc_net_163 ) ) ; sb_2__2__mux_2level_tapbuf_size2_14 mux_bottom_track_53 ( .in ( { bottom_left_grid_pin_51_[0] , chanx_left_in[27] } ) , .sram ( mux_2level_tapbuf_size2_14_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_77 , SYNOPSYS_UNCONNECTED_78 } ) , - .out ( chany_bottom_out[26] ) , .p0 ( optlc_net_174 ) ) ; + .out ( chany_bottom_out[26] ) , .p0 ( optlc_net_162 ) ) ; sb_2__2__mux_2level_tapbuf_size2_15 mux_left_track_13 ( .in ( { chany_bottom_in[5] , left_top_grid_pin_1_[0] } ) , .sram ( mux_2level_tapbuf_size2_15_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_79 , SYNOPSYS_UNCONNECTED_80 } ) , - .out ( chanx_left_out[6] ) , .p0 ( optlc_net_176 ) ) ; + .out ( chanx_left_out[6] ) , .p0 ( optlc_net_161 ) ) ; sb_2__2__mux_2level_tapbuf_size2_16 mux_left_track_15 ( .in ( { chany_bottom_in[6] , left_bottom_grid_pin_36_[0] } ) , .sram ( mux_2level_tapbuf_size2_16_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_81 , SYNOPSYS_UNCONNECTED_82 } ) , - .out ( chanx_left_out[7] ) , .p0 ( optlc_net_176 ) ) ; + .out ( chanx_left_out[7] ) , .p0 ( optlc_net_163 ) ) ; sb_2__2__mux_2level_tapbuf_size2_17 mux_left_track_17 ( .in ( { chany_bottom_in[7] , left_bottom_grid_pin_37_[0] } ) , .sram ( mux_2level_tapbuf_size2_17_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_83 , SYNOPSYS_UNCONNECTED_84 } ) , - .out ( chanx_left_out[8] ) , .p0 ( optlc_net_176 ) ) ; + .out ( chanx_left_out[8] ) , .p0 ( optlc_net_161 ) ) ; sb_2__2__mux_2level_tapbuf_size2_18 mux_left_track_19 ( .in ( { chany_bottom_in[8] , left_bottom_grid_pin_38_[0] } ) , .sram ( mux_2level_tapbuf_size2_18_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_85 , SYNOPSYS_UNCONNECTED_86 } ) , - .out ( chanx_left_out[9] ) , .p0 ( optlc_net_176 ) ) ; + .out ( chanx_left_out[9] ) , .p0 ( optlc_net_161 ) ) ; sb_2__2__mux_2level_tapbuf_size2_19 mux_left_track_21 ( .in ( { chany_bottom_in[9] , left_bottom_grid_pin_39_[0] } ) , .sram ( mux_2level_tapbuf_size2_19_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_87 , SYNOPSYS_UNCONNECTED_88 } ) , - .out ( chanx_left_out[10] ) , .p0 ( optlc_net_175 ) ) ; + .out ( chanx_left_out[10] ) , .p0 ( optlc_net_161 ) ) ; sb_2__2__mux_2level_tapbuf_size2_20 mux_left_track_23 ( .in ( { chany_bottom_in[10] , left_bottom_grid_pin_40_[0] } ) , .sram ( mux_2level_tapbuf_size2_20_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_89 , SYNOPSYS_UNCONNECTED_90 } ) , - .out ( chanx_left_out[11] ) , .p0 ( optlc_net_175 ) ) ; + .out ( chanx_left_out[11] ) , .p0 ( optlc_net_163 ) ) ; sb_2__2__mux_2level_tapbuf_size2_21 mux_left_track_25 ( .in ( { chany_bottom_in[11] , left_bottom_grid_pin_41_[0] } ) , .sram ( mux_2level_tapbuf_size2_21_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_91 , SYNOPSYS_UNCONNECTED_92 } ) , - .out ( chanx_left_out[12] ) , .p0 ( optlc_net_175 ) ) ; + .out ( chanx_left_out[12] ) , .p0 ( optlc_net_163 ) ) ; sb_2__2__mux_2level_tapbuf_size2_22 mux_left_track_27 ( .in ( { chany_bottom_in[12] , left_bottom_grid_pin_42_[0] } ) , .sram ( mux_2level_tapbuf_size2_22_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_93 , SYNOPSYS_UNCONNECTED_94 } ) , - .out ( chanx_left_out[13] ) , .p0 ( optlc_net_175 ) ) ; + .out ( chanx_left_out[13] ) , .p0 ( optlc_net_163 ) ) ; sb_2__2__mux_2level_tapbuf_size2_23 mux_left_track_31 ( .in ( { chany_bottom_in[14] , left_bottom_grid_pin_36_[0] } ) , .sram ( mux_2level_tapbuf_size2_23_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_95 , SYNOPSYS_UNCONNECTED_96 } ) , - .out ( chanx_left_out[15] ) , .p0 ( optlc_net_176 ) ) ; + .out ( chanx_left_out[15] ) , .p0 ( optlc_net_163 ) ) ; sb_2__2__mux_2level_tapbuf_size2_24 mux_left_track_33 ( .in ( { chany_bottom_in[15] , left_bottom_grid_pin_37_[0] } ) , .sram ( mux_2level_tapbuf_size2_24_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_97 , SYNOPSYS_UNCONNECTED_98 } ) , - .out ( chanx_left_out[16] ) , .p0 ( optlc_net_176 ) ) ; + .out ( chanx_left_out[16] ) , .p0 ( optlc_net_163 ) ) ; sb_2__2__mux_2level_tapbuf_size2_25 mux_left_track_35 ( .in ( { chany_bottom_in[16] , left_bottom_grid_pin_38_[0] } ) , .sram ( mux_2level_tapbuf_size2_25_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_99 , SYNOPSYS_UNCONNECTED_100 } ) , - .out ( chanx_left_out[17] ) , .p0 ( optlc_net_176 ) ) ; + .out ( chanx_left_out[17] ) , .p0 ( optlc_net_161 ) ) ; sb_2__2__mux_2level_tapbuf_size2_26 mux_left_track_37 ( .in ( { chany_bottom_in[17] , left_bottom_grid_pin_39_[0] } ) , .sram ( mux_2level_tapbuf_size2_26_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_101 , SYNOPSYS_UNCONNECTED_102 } ) , - .out ( chanx_left_out[18] ) , .p0 ( optlc_net_176 ) ) ; + .out ( chanx_left_out[18] ) , .p0 ( optlc_net_161 ) ) ; sb_2__2__mux_2level_tapbuf_size2_27 mux_left_track_39 ( .in ( { chany_bottom_in[18] , left_bottom_grid_pin_40_[0] } ) , .sram ( mux_2level_tapbuf_size2_27_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_103 , SYNOPSYS_UNCONNECTED_104 } ) , - .out ( chanx_left_out[19] ) , .p0 ( optlc_net_176 ) ) ; + .out ( chanx_left_out[19] ) , .p0 ( optlc_net_161 ) ) ; sb_2__2__mux_2level_tapbuf_size2_28 mux_left_track_41 ( .in ( { chany_bottom_in[19] , left_bottom_grid_pin_41_[0] } ) , .sram ( mux_2level_tapbuf_size2_28_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_105 , SYNOPSYS_UNCONNECTED_106 } ) , - .out ( chanx_left_out[20] ) , .p0 ( optlc_net_176 ) ) ; + .out ( chanx_left_out[20] ) , .p0 ( optlc_net_161 ) ) ; sb_2__2__mux_2level_tapbuf_size2_29 mux_left_track_43 ( .in ( { chany_bottom_in[20] , left_bottom_grid_pin_42_[0] } ) , .sram ( mux_2level_tapbuf_size2_29_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_107 , SYNOPSYS_UNCONNECTED_108 } ) , - .out ( chanx_left_out[21] ) , .p0 ( optlc_net_176 ) ) ; + .out ( chanx_left_out[21] ) , .p0 ( optlc_net_161 ) ) ; sb_2__2__mux_2level_tapbuf_size2_30 mux_left_track_45 ( .in ( { chany_bottom_in[21] , left_top_grid_pin_1_[0] } ) , .sram ( mux_2level_tapbuf_size2_30_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_109 , SYNOPSYS_UNCONNECTED_110 } ) , - .out ( chanx_left_out[22] ) , .p0 ( optlc_net_176 ) ) ; + .out ( chanx_left_out[22] ) , .p0 ( optlc_net_161 ) ) ; sb_2__2__mux_2level_tapbuf_size2_31 mux_left_track_47 ( .in ( { chany_bottom_in[22] , left_bottom_grid_pin_36_[0] } ) , .sram ( mux_2level_tapbuf_size2_31_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_111 , SYNOPSYS_UNCONNECTED_112 } ) , - .out ( chanx_left_out[23] ) , .p0 ( optlc_net_176 ) ) ; + .out ( chanx_left_out[23] ) , .p0 ( optlc_net_161 ) ) ; sb_2__2__mux_2level_tapbuf_size2_32 mux_left_track_49 ( .in ( { chany_bottom_in[23] , left_bottom_grid_pin_37_[0] } ) , .sram ( mux_2level_tapbuf_size2_32_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_113 , SYNOPSYS_UNCONNECTED_114 } ) , - .out ( chanx_left_out[24] ) , .p0 ( optlc_net_176 ) ) ; + .out ( chanx_left_out[24] ) , .p0 ( optlc_net_163 ) ) ; sb_2__2__mux_2level_tapbuf_size2_33 mux_left_track_51 ( .in ( { chany_bottom_in[24] , left_bottom_grid_pin_38_[0] } ) , .sram ( mux_2level_tapbuf_size2_33_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_115 , SYNOPSYS_UNCONNECTED_116 } ) , - .out ( chanx_left_out[25] ) , .p0 ( optlc_net_176 ) ) ; + .out ( chanx_left_out[25] ) , .p0 ( optlc_net_161 ) ) ; sb_2__2__mux_2level_tapbuf_size2_34 mux_left_track_55 ( .in ( { chany_bottom_in[26] , left_bottom_grid_pin_40_[0] } ) , .sram ( mux_2level_tapbuf_size2_34_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_117 , SYNOPSYS_UNCONNECTED_118 } ) , - .out ( chanx_left_out[27] ) , .p0 ( optlc_net_175 ) ) ; + .out ( chanx_left_out[27] ) , .p0 ( optlc_net_161 ) ) ; sb_2__2__mux_2level_tapbuf_size2_35 mux_left_track_57 ( .in ( { chany_bottom_in[27] , left_bottom_grid_pin_41_[0] } ) , .sram ( mux_2level_tapbuf_size2_35_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_119 , SYNOPSYS_UNCONNECTED_120 } ) , - .out ( chanx_left_out[28] ) , .p0 ( optlc_net_175 ) ) ; + .out ( chanx_left_out[28] ) , .p0 ( optlc_net_161 ) ) ; sb_2__2__mux_2level_tapbuf_size2 mux_left_track_59 ( .in ( { chany_bottom_in[28] , left_bottom_grid_pin_42_[0] } ) , .sram ( mux_2level_tapbuf_size2_36_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_121 , SYNOPSYS_UNCONNECTED_122 } ) , - .out ( chanx_left_out[29] ) , .p0 ( optlc_net_175 ) ) ; + .out ( chanx_left_out[29] ) , .p0 ( optlc_net_163 ) ) ; sb_2__2__mux_2level_tapbuf_size2_mem_0 mem_bottom_track_13 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( mux_2level_tapbuf_size4_mem_5_ccff_tail ) , @@ -21814,25 +23559,25 @@ sb_2__2__mux_2level_tapbuf_size3_0 mux_bottom_track_29 ( chanx_left_in[15] } ) , .sram ( mux_2level_tapbuf_size3_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_123 , SYNOPSYS_UNCONNECTED_124 } ) , - .out ( chany_bottom_out[14] ) , .p0 ( optlc_net_177 ) ) ; + .out ( chany_bottom_out[14] ) , .p0 ( optlc_net_162 ) ) ; sb_2__2__mux_2level_tapbuf_size3_1 mux_bottom_track_45 ( .in ( { bottom_right_grid_pin_1_[0] , bottom_left_grid_pin_47_[0] , chanx_left_in[23] } ) , .sram ( mux_2level_tapbuf_size3_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_125 , SYNOPSYS_UNCONNECTED_126 } ) , - .out ( chany_bottom_out[22] ) , .p0 ( optlc_net_175 ) ) ; + .out ( chany_bottom_out[22] ) , .p0 ( optlc_net_163 ) ) ; sb_2__2__mux_2level_tapbuf_size3_2 mux_left_track_29 ( .in ( { chany_bottom_in[13] , left_top_grid_pin_1_[0] , left_bottom_grid_pin_43_[0] } ) , .sram ( mux_2level_tapbuf_size3_2_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_127 , SYNOPSYS_UNCONNECTED_128 } ) , - .out ( chanx_left_out[14] ) , .p0 ( optlc_net_176 ) ) ; + .out ( chanx_left_out[14] ) , .p0 ( optlc_net_163 ) ) ; sb_2__2__mux_2level_tapbuf_size3 mux_left_track_53 ( .in ( { chany_bottom_in[25] , left_bottom_grid_pin_39_[0] , left_bottom_grid_pin_43_[0] } ) , .sram ( mux_2level_tapbuf_size3_3_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_129 , SYNOPSYS_UNCONNECTED_130 } ) , - .out ( chanx_left_out[26] ) , .p0 ( optlc_net_176 ) ) ; + .out ( chanx_left_out[26] ) , .p0 ( optlc_net_161 ) ) ; sb_2__2__mux_2level_tapbuf_size3_mem_0 mem_bottom_track_29 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( mux_2level_tapbuf_size2_mem_7_ccff_tail ) , @@ -21854,7 +23599,7 @@ sb_2__2__mux_2level_tapbuf_size3_mem mem_left_track_53 ( .pReset ( pReset ) , .ccff_tail ( mux_2level_tapbuf_size3_mem_3_ccff_tail ) , .mem_out ( mux_2level_tapbuf_size3_3_sram ) ) ; sky130_fd_sc_hd__buf_8 pReset_FTB00 ( .A ( pReset_W_in ) , .X ( pReset[0] ) ) ; -sky130_fd_sc_hd__buf_8 prog_clk_0_FTB00 ( .A ( prog_clk_0_S_in ) , +sky130_fd_sc_hd__buf_1 prog_clk_0_FTB00 ( .A ( prog_clk_0_S_in ) , .X ( prog_clk[0] ) ) ; sky130_fd_sc_hd__buf_8 FTB_78__77 ( .A ( chanx_left_in[0] ) , .X ( chany_bottom_out[29] ) ) ; @@ -21871,18 +23616,14 @@ sky130_fd_sc_hd__buf_8 FTB_83__82 ( .A ( chanx_left_in[28] ) , sky130_fd_sc_hd__buf_8 FTB_84__83 ( .A ( chanx_left_in[29] ) , .X ( chany_bottom_out[28] ) ) ; sky130_fd_sc_hd__buf_6 FTB_85__84 ( .A ( SC_IN_BOT ) , .X ( SC_OUT_BOT ) ) ; -sky130_fd_sc_hd__conb_1 optlc_176 ( .LO ( SYNOPSYS_UNCONNECTED_131 ) , - .HI ( optlc_net_174 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_178 ( .LO ( SYNOPSYS_UNCONNECTED_132 ) , - .HI ( optlc_net_175 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_181 ( .LO ( SYNOPSYS_UNCONNECTED_133 ) , - .HI ( optlc_net_176 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_184 ( .LO ( SYNOPSYS_UNCONNECTED_134 ) , - .HI ( optlc_net_177 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_186 ( .LO ( SYNOPSYS_UNCONNECTED_135 ) , - .HI ( optlc_net_178 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_188 ( .LO ( SYNOPSYS_UNCONNECTED_136 ) , - .HI ( optlc_net_179 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_162 ( .LO ( SYNOPSYS_UNCONNECTED_131 ) , + .HI ( optlc_net_160 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_164 ( .LO ( SYNOPSYS_UNCONNECTED_132 ) , + .HI ( optlc_net_161 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_166 ( .LO ( SYNOPSYS_UNCONNECTED_133 ) , + .HI ( optlc_net_162 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_168 ( .LO ( SYNOPSYS_UNCONNECTED_134 ) , + .HI ( optlc_net_163 ) ) ; endmodule @@ -22113,7 +23854,7 @@ input [0:0] mem_inv ; output [0:0] out ; input p0 ; -sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , +sky130_fd_sc_hd__mux2_2 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ; endmodule @@ -22150,9 +23891,8 @@ sb_2__1__mux_2level_tapbuf_basis_input2_mem1_33 mux_l2_in_0_ ( .mem ( sram[1] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_194 ( .A ( BUF_net_195 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_195 ( - .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_195 ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_182 ( + .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) ) ; endmodule @@ -22251,7 +23991,7 @@ sb_2__1__mux_2level_tapbuf_basis_input2_mem1_29 mux_l2_in_0_ ( .mem ( sram[1] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_193 ( +sky130_fd_sc_hd__buf_6 BUFT_RR_181 ( .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) ) ; endmodule @@ -22264,7 +24004,7 @@ input [0:0] mem_inv ; output [0:0] out ; input p0 ; -sky130_fd_sc_hd__mux2_2 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , +sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ; endmodule @@ -22291,6 +24031,8 @@ input p0 ; wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ; wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) ) ; sb_2__1__mux_2level_tapbuf_basis_input2_mem1_26 mux_l1_in_0_ ( .in ( in ) , .mem ( sram[0] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) , @@ -22301,8 +24043,6 @@ sb_2__1__mux_2level_tapbuf_basis_input2_mem1_27 mux_l2_in_0_ ( .mem ( sram[1] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_192 ( - .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) ) ; endmodule @@ -22314,7 +24054,7 @@ input [0:0] mem_inv ; output [0:0] out ; input p0 ; -sky130_fd_sc_hd__mux2_2 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , +sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ; endmodule @@ -22341,6 +24081,8 @@ input p0 ; wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ; wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) ) ; sb_2__1__mux_2level_tapbuf_basis_input2_mem1_24 mux_l1_in_0_ ( .in ( in ) , .mem ( sram[0] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) , @@ -22351,8 +24093,6 @@ sb_2__1__mux_2level_tapbuf_basis_input2_mem1_25 mux_l2_in_0_ ( .mem ( sram[1] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_191 ( - .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) ) ; endmodule @@ -22493,7 +24233,7 @@ input [0:0] mem ; input [0:0] mem_inv ; output [0:0] out ; -sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) , +sky130_fd_sc_hd__mux2_2 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ; endmodule @@ -22534,8 +24274,6 @@ wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ; wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ; wire [0:0] mux_2level_tapbuf_basis_input2_mem1_2_out ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( mux_2level_tapbuf_basis_input2_mem1_2_out[0] ) , .X ( out[0] ) ) ; sb_2__1__mux_2level_tapbuf_basis_input2_mem1_21 mux_l1_in_0_ ( .in ( in[0:1] ) , .mem ( sram[0] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) , @@ -22551,6 +24289,8 @@ sb_2__1__mux_2level_tapbuf_basis_input2_mem1_23 mux_l2_in_0_ ( .mem ( sram[1] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_4 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_2_out ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_180 ( + .A ( mux_2level_tapbuf_basis_input2_mem1_2_out[0] ) , .X ( out[0] ) ) ; endmodule @@ -22629,7 +24369,7 @@ input [0:0] mem ; input [0:0] mem_inv ; output [0:0] out ; -sky130_fd_sc_hd__mux2_2 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) , +sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ; endmodule @@ -22685,8 +24425,9 @@ sb_2__1__mux_2level_tapbuf_basis_input2_mem1_17 mux_l2_in_0_ ( .mem ( sram[1] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_4 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_2_out ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_190 ( - .A ( mux_2level_tapbuf_basis_input2_mem1_2_out[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_178 ( .A ( BUF_net_179 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_179 ( + .A ( mux_2level_tapbuf_basis_input2_mem1_2_out[0] ) , .Y ( BUF_net_179 ) ) ; endmodule @@ -22738,8 +24479,6 @@ wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ; wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ; wire [0:0] mux_2level_tapbuf_basis_input2_mem1_2_out ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( mux_2level_tapbuf_basis_input2_mem1_2_out[0] ) , .X ( out[0] ) ) ; sb_2__1__mux_2level_tapbuf_basis_input2_mem1_12 mux_l1_in_0_ ( .in ( in[0:1] ) , .mem ( sram[0] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) , @@ -22755,6 +24494,8 @@ sb_2__1__mux_2level_tapbuf_basis_input2_mem1_14 mux_l2_in_0_ ( .mem ( sram[1] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_4 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_2_out ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_177 ( + .A ( mux_2level_tapbuf_basis_input2_mem1_2_out[0] ) , .X ( out[0] ) ) ; endmodule @@ -22765,7 +24506,7 @@ input [0:0] mem ; input [0:0] mem_inv ; output [0:0] out ; -sky130_fd_sc_hd__mux2_2 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) , +sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ; endmodule @@ -22806,7 +24547,7 @@ wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ; wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ; wire [0:0] mux_2level_tapbuf_basis_input2_mem1_2_out ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( mux_2level_tapbuf_basis_input2_mem1_2_out[0] ) , .X ( out[0] ) ) ; sb_2__1__mux_2level_tapbuf_basis_input2_mem1_9 mux_l1_in_0_ ( .in ( in[0:1] ) , .mem ( sram[0] ) , @@ -22833,7 +24574,7 @@ input [0:0] mem ; input [0:0] mem_inv ; output [0:0] out ; -sky130_fd_sc_hd__mux2_2 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) , +sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ; endmodule @@ -22874,8 +24615,6 @@ wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ; wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ; wire [0:0] mux_2level_tapbuf_basis_input2_mem1_2_out ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( mux_2level_tapbuf_basis_input2_mem1_2_out[0] ) , .X ( out[0] ) ) ; sb_2__1__mux_2level_tapbuf_basis_input2_mem1_6 mux_l1_in_0_ ( .in ( in[0:1] ) , .mem ( sram[0] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) , @@ -22891,6 +24630,9 @@ sb_2__1__mux_2level_tapbuf_basis_input2_mem1_8 mux_l2_in_0_ ( .mem ( sram[1] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_4 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_2_out ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_175 ( .A ( BUF_net_176 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_176 ( + .A ( mux_2level_tapbuf_basis_input2_mem1_2_out[0] ) , .Y ( BUF_net_176 ) ) ; endmodule @@ -22901,7 +24643,7 @@ input [0:0] mem ; input [0:0] mem_inv ; output [0:0] out ; -sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) , +sky130_fd_sc_hd__mux2_2 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ; endmodule @@ -23198,10 +24940,14 @@ input [0:2] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -23212,10 +24958,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -23281,9 +25031,9 @@ sb_2__1__mux_2level_tapbuf_basis_input3_mem3 mux_l2_in_0_ ( .mem ( local_encoder2to3_1_data ) , .mem_inv ( local_encoder2to3_1_data_inv ) , .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_188 ( .A ( BUF_net_189 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_189 ( - .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_189 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_173 ( .A ( BUF_net_174 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_174 ( + .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_174 ) ) ; endmodule @@ -23295,10 +25045,14 @@ input [0:2] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -23309,10 +25063,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -23362,6 +25120,8 @@ wire [0:2] local_encoder2to3_1_data_inv ; wire [0:0] mux_2level_tapbuf_basis_input3_mem3_0_out ; wire [0:0] mux_2level_tapbuf_basis_input3_mem3_1_out ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .X ( out[0] ) ) ; sb_2__1__local_encoder2to3_56 local_encoder2to3_0_ ( .addr ( sram[0:1] ) , .data ( local_encoder2to3_0_data ) , .data_inv ( local_encoder2to3_0_data_inv ) ) ; @@ -23378,9 +25138,6 @@ sb_2__1__mux_2level_tapbuf_basis_input3_mem3_77 mux_l2_in_0_ ( .mem ( local_encoder2to3_1_data ) , .mem_inv ( local_encoder2to3_1_data_inv ) , .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_186 ( .A ( BUF_net_187 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_187 ( - .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_187 ) ) ; endmodule @@ -23392,10 +25149,14 @@ input [0:2] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -23406,10 +25167,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -23459,8 +25224,6 @@ wire [0:2] local_encoder2to3_1_data_inv ; wire [0:0] mux_2level_tapbuf_basis_input3_mem3_0_out ; wire [0:0] mux_2level_tapbuf_basis_input3_mem3_1_out ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .X ( out[0] ) ) ; sb_2__1__local_encoder2to3_54 local_encoder2to3_0_ ( .addr ( sram[0:1] ) , .data ( local_encoder2to3_0_data ) , .data_inv ( local_encoder2to3_0_data_inv ) ) ; @@ -23477,6 +25240,9 @@ sb_2__1__mux_2level_tapbuf_basis_input3_mem3_75 mux_l2_in_0_ ( .mem ( local_encoder2to3_1_data ) , .mem_inv ( local_encoder2to3_1_data_inv ) , .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .p0 ( p0 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_171 ( .A ( BUF_net_172 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_172 ( + .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_172 ) ) ; endmodule @@ -23488,10 +25254,14 @@ input [0:2] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -23502,10 +25272,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -23571,9 +25345,8 @@ sb_2__1__mux_2level_tapbuf_basis_input3_mem3_73 mux_l2_in_0_ ( .mem ( local_encoder2to3_1_data ) , .mem_inv ( local_encoder2to3_1_data_inv ) , .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_184 ( .A ( BUF_net_185 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_185 ( - .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_185 ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_170 ( + .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .X ( out[0] ) ) ; endmodule @@ -23585,10 +25358,14 @@ input [0:2] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -23599,10 +25376,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -23668,9 +25449,9 @@ sb_2__1__mux_2level_tapbuf_basis_input3_mem3_71 mux_l2_in_0_ ( .mem ( local_encoder2to3_1_data ) , .mem_inv ( local_encoder2to3_1_data_inv ) , .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_182 ( .A ( BUF_net_183 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_183 ( - .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_183 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_168 ( .A ( BUF_net_169 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_169 ( + .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_169 ) ) ; endmodule @@ -23682,10 +25463,14 @@ input [0:2] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -23696,10 +25481,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -23749,6 +25538,8 @@ wire [0:2] local_encoder2to3_1_data_inv ; wire [0:0] mux_2level_tapbuf_basis_input3_mem3_0_out ; wire [0:0] mux_2level_tapbuf_basis_input3_mem3_1_out ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .X ( out[0] ) ) ; sb_2__1__local_encoder2to3_48 local_encoder2to3_0_ ( .addr ( sram[0:1] ) , .data ( local_encoder2to3_0_data ) , .data_inv ( local_encoder2to3_0_data_inv ) ) ; @@ -23765,9 +25556,6 @@ sb_2__1__mux_2level_tapbuf_basis_input3_mem3_69 mux_l2_in_0_ ( .mem ( local_encoder2to3_1_data ) , .mem_inv ( local_encoder2to3_1_data_inv ) , .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_180 ( .A ( BUF_net_181 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_181 ( - .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_181 ) ) ; endmodule @@ -23779,10 +25567,14 @@ input [0:2] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -23793,10 +25585,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -23862,9 +25658,8 @@ sb_2__1__mux_2level_tapbuf_basis_input3_mem3_67 mux_l2_in_0_ ( .mem ( local_encoder2to3_1_data ) , .mem_inv ( local_encoder2to3_1_data_inv ) , .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_178 ( .A ( BUF_net_179 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_179 ( - .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_179 ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_167 ( + .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .X ( out[0] ) ) ; endmodule @@ -23876,10 +25671,14 @@ input [0:2] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -23890,10 +25689,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -23943,6 +25746,8 @@ wire [0:2] local_encoder2to3_1_data_inv ; wire [0:0] mux_2level_tapbuf_basis_input3_mem3_0_out ; wire [0:0] mux_2level_tapbuf_basis_input3_mem3_1_out ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .X ( out[0] ) ) ; sb_2__1__local_encoder2to3_44 local_encoder2to3_0_ ( .addr ( sram[0:1] ) , .data ( local_encoder2to3_0_data ) , .data_inv ( local_encoder2to3_0_data_inv ) ) ; @@ -23959,9 +25764,6 @@ sb_2__1__mux_2level_tapbuf_basis_input3_mem3_65 mux_l2_in_0_ ( .mem ( local_encoder2to3_1_data ) , .mem_inv ( local_encoder2to3_1_data_inv ) , .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_176 ( .A ( BUF_net_177 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_177 ( - .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_177 ) ) ; endmodule @@ -24073,10 +25875,14 @@ input [0:2] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -24087,10 +25893,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -24101,10 +25911,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -24155,8 +25969,6 @@ wire [0:0] mux_2level_tapbuf_basis_input3_mem3_0_out ; wire [0:0] mux_2level_tapbuf_basis_input3_mem3_1_out ; wire [0:0] mux_2level_tapbuf_basis_input3_mem3_2_out ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( mux_2level_tapbuf_basis_input3_mem3_2_out[0] ) , .X ( out[0] ) ) ; sb_2__1__local_encoder2to3_42 local_encoder2to3_0_ ( .addr ( sram[0:1] ) , .data ( local_encoder2to3_0_data ) , .data_inv ( local_encoder2to3_0_data_inv ) ) ; @@ -24178,6 +25990,9 @@ sb_2__1__mux_2level_tapbuf_basis_input3_mem3_63 mux_l2_in_0_ ( .mem ( local_encoder2to3_1_data ) , .mem_inv ( local_encoder2to3_1_data_inv ) , .out ( mux_2level_tapbuf_basis_input3_mem3_2_out ) , .p0 ( p0 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_165 ( .A ( BUF_net_166 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_166 ( + .A ( mux_2level_tapbuf_basis_input3_mem3_2_out[0] ) , .Y ( BUF_net_166 ) ) ; endmodule @@ -24189,10 +26004,14 @@ input [0:2] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -24203,10 +26022,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -24217,10 +26040,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -24292,9 +26119,9 @@ sb_2__1__mux_2level_tapbuf_basis_input3_mem3_60 mux_l2_in_0_ ( .mem ( local_encoder2to3_1_data ) , .mem_inv ( local_encoder2to3_1_data_inv ) , .out ( mux_2level_tapbuf_basis_input3_mem3_2_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_174 ( .A ( BUF_net_175 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_175 ( - .A ( mux_2level_tapbuf_basis_input3_mem3_2_out[0] ) , .Y ( BUF_net_175 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_163 ( .A ( BUF_net_164 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_164 ( + .A ( mux_2level_tapbuf_basis_input3_mem3_2_out[0] ) , .Y ( BUF_net_164 ) ) ; endmodule @@ -24306,10 +26133,14 @@ input [0:2] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -24320,10 +26151,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -24334,10 +26169,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -24422,10 +26261,14 @@ input [0:2] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -24436,10 +26279,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -24450,10 +26297,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -24538,10 +26389,14 @@ input [0:2] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -24552,10 +26407,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -24566,10 +26425,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -24641,9 +26504,9 @@ sb_2__1__mux_2level_tapbuf_basis_input3_mem3_51 mux_l2_in_0_ ( .mem ( local_encoder2to3_1_data ) , .mem_inv ( local_encoder2to3_1_data_inv ) , .out ( mux_2level_tapbuf_basis_input3_mem3_2_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_172 ( .A ( BUF_net_173 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_173 ( - .A ( mux_2level_tapbuf_basis_input3_mem3_2_out[0] ) , .Y ( BUF_net_173 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_185 ( .A ( BUF_net_186 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_186 ( + .A ( mux_2level_tapbuf_basis_input3_mem3_2_out[0] ) , .Y ( BUF_net_186 ) ) ; endmodule @@ -24674,9 +26537,13 @@ input [0:1] mem ; input [0:1] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -24688,12 +26555,18 @@ input [0:3] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -24704,12 +26577,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -24720,12 +26599,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -24786,8 +26671,7 @@ wire [0:0] mux_2level_tapbuf_basis_input4_mem4_1_out ; wire [0:0] mux_2level_tapbuf_basis_input4_mem4_2_out ; sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_4_0_ ( - .A ( mux_2level_tapbuf_basis_input4_mem4_2_out[0] ) , - .X ( aps_rename_507_ ) ) ; + .A ( mux_2level_tapbuf_basis_input4_mem4_2_out[0] ) , .X ( net_net_162 ) ) ; sb_2__1__local_encoder2to4_6 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , .data ( local_encoder2to4_0_data ) , .data_inv ( local_encoder2to4_0_data_inv ) ) ; @@ -24814,9 +26698,7 @@ sb_2__1__mux_2level_tapbuf_basis_input2_mem2 mux_l1_in_2_ ( .in ( in[8:9] ) , .mem ( local_encoder2to4_0_data[0:1] ) , .mem_inv ( local_encoder2to4_0_data_inv[0:1] ) , .out ( mux_2level_tapbuf_basis_input2_mem2_0_out ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_170 ( .A ( BUF_net_171 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_171 ( .A ( aps_rename_507_ ) , - .Y ( BUF_net_171 ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_162 ( .A ( net_net_162 ) , .X ( out[0] ) ) ; endmodule @@ -24947,9 +26829,13 @@ input [0:1] mem ; input [0:1] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -24961,10 +26847,14 @@ input [0:2] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -24975,10 +26865,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -25029,6 +26923,8 @@ wire [0:0] mux_2level_tapbuf_basis_input2_mem2_0_out ; wire [0:0] mux_2level_tapbuf_basis_input3_mem3_0_out ; wire [0:0] mux_2level_tapbuf_basis_input3_mem3_1_out ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .X ( out[0] ) ) ; sb_2__1__local_encoder2to3_32 local_encoder2to3_0_ ( .addr ( sram[0:1] ) , .data ( local_encoder2to3_0_data ) , .data_inv ( local_encoder2to3_0_data_inv ) ) ; @@ -25050,8 +26946,6 @@ sb_2__1__mux_2level_tapbuf_basis_input2_mem2_12 mux_l1_in_1_ ( .in ( in[3:4] ) , .mem ( local_encoder2to3_0_data[0:1] ) , .mem_inv ( local_encoder2to3_0_data_inv[0:1] ) , .out ( mux_2level_tapbuf_basis_input2_mem2_0_out ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_169 ( - .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .X ( out[0] ) ) ; endmodule @@ -25062,9 +26956,13 @@ input [0:1] mem ; input [0:1] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -25076,10 +26974,14 @@ input [0:2] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -25090,10 +26992,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -25165,9 +27071,9 @@ sb_2__1__mux_2level_tapbuf_basis_input2_mem2_11 mux_l1_in_1_ ( .in ( in[3:4] ) , .mem ( local_encoder2to3_0_data[0:1] ) , .mem_inv ( local_encoder2to3_0_data_inv[0:1] ) , .out ( mux_2level_tapbuf_basis_input2_mem2_0_out ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_167 ( .A ( BUF_net_168 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_168 ( - .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_168 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_160 ( .A ( BUF_net_161 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_161 ( + .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_161 ) ) ; endmodule @@ -25178,9 +27084,13 @@ input [0:1] mem ; input [0:1] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -25192,10 +27102,14 @@ input [0:2] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -25206,10 +27120,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -25281,9 +27199,9 @@ sb_2__1__mux_2level_tapbuf_basis_input2_mem2_10 mux_l1_in_1_ ( .in ( in[3:4] ) , .mem ( local_encoder2to3_0_data[0:1] ) , .mem_inv ( local_encoder2to3_0_data_inv[0:1] ) , .out ( mux_2level_tapbuf_basis_input2_mem2_0_out ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_165 ( .A ( BUF_net_166 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_166 ( - .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_166 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_158 ( .A ( BUF_net_159 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_159 ( + .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_159 ) ) ; endmodule @@ -25294,9 +27212,13 @@ input [0:1] mem ; input [0:1] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -25308,10 +27230,14 @@ input [0:2] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -25322,10 +27248,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -25376,6 +27306,8 @@ wire [0:0] mux_2level_tapbuf_basis_input2_mem2_0_out ; wire [0:0] mux_2level_tapbuf_basis_input3_mem3_0_out ; wire [0:0] mux_2level_tapbuf_basis_input3_mem3_1_out ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .X ( out[0] ) ) ; sb_2__1__local_encoder2to3_26 local_encoder2to3_0_ ( .addr ( sram[0:1] ) , .data ( local_encoder2to3_0_data ) , .data_inv ( local_encoder2to3_0_data_inv ) ) ; @@ -25397,8 +27329,6 @@ sb_2__1__mux_2level_tapbuf_basis_input2_mem2_9 mux_l1_in_1_ ( .in ( in[3:4] ) , .mem ( local_encoder2to3_0_data[0:1] ) , .mem_inv ( local_encoder2to3_0_data_inv[0:1] ) , .out ( mux_2level_tapbuf_basis_input2_mem2_0_out ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_164 ( - .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .X ( out[0] ) ) ; endmodule @@ -25409,9 +27339,13 @@ input [0:1] mem ; input [0:1] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -25423,10 +27357,14 @@ input [0:2] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -25437,10 +27375,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -25512,9 +27454,9 @@ sb_2__1__mux_2level_tapbuf_basis_input2_mem2_8 mux_l1_in_1_ ( .in ( in[3:4] ) , .mem ( local_encoder2to3_0_data[0:1] ) , .mem_inv ( local_encoder2to3_0_data_inv[0:1] ) , .out ( mux_2level_tapbuf_basis_input2_mem2_0_out ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_162 ( .A ( BUF_net_163 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_163 ( - .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_163 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_156 ( .A ( BUF_net_157 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_157 ( + .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_157 ) ) ; endmodule @@ -25525,9 +27467,13 @@ input [0:1] mem ; input [0:1] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -25539,10 +27485,14 @@ input [0:2] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -25553,10 +27503,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -25607,8 +27561,6 @@ wire [0:0] mux_2level_tapbuf_basis_input2_mem2_0_out ; wire [0:0] mux_2level_tapbuf_basis_input3_mem3_0_out ; wire [0:0] mux_2level_tapbuf_basis_input3_mem3_1_out ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .X ( out[0] ) ) ; sb_2__1__local_encoder2to3_22 local_encoder2to3_0_ ( .addr ( sram[0:1] ) , .data ( local_encoder2to3_0_data ) , .data_inv ( local_encoder2to3_0_data_inv ) ) ; @@ -25630,6 +27582,9 @@ sb_2__1__mux_2level_tapbuf_basis_input2_mem2_7 mux_l1_in_1_ ( .in ( in[3:4] ) , .mem ( local_encoder2to3_0_data[0:1] ) , .mem_inv ( local_encoder2to3_0_data_inv[0:1] ) , .out ( mux_2level_tapbuf_basis_input2_mem2_0_out ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_154 ( .A ( BUF_net_155 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_155 ( + .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_155 ) ) ; endmodule @@ -25701,12 +27656,18 @@ input [0:3] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -25717,12 +27678,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -25733,12 +27700,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -25797,9 +27770,8 @@ wire [0:0] mux_2level_tapbuf_basis_input4_mem4_0_out ; wire [0:0] mux_2level_tapbuf_basis_input4_mem4_1_out ; wire [0:0] mux_2level_tapbuf_basis_input4_mem4_2_out ; -sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_4_0_ ( - .A ( mux_2level_tapbuf_basis_input4_mem4_2_out[0] ) , - .X ( aps_rename_506_ ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( mux_2level_tapbuf_basis_input4_mem4_2_out[0] ) , .X ( out[0] ) ) ; sb_2__1__local_encoder2to4_4 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , .data ( local_encoder2to4_0_data ) , .data_inv ( local_encoder2to4_0_data_inv ) ) ; @@ -25821,9 +27793,6 @@ sb_2__1__mux_2level_tapbuf_basis_input4_mem4_8 mux_l2_in_0_ ( .mem ( local_encoder2to4_1_data ) , .mem_inv ( local_encoder2to4_1_data_inv ) , .out ( mux_2level_tapbuf_basis_input4_mem4_2_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_160 ( .A ( BUF_net_161 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_161 ( .A ( aps_rename_506_ ) , - .Y ( BUF_net_161 ) ) ; endmodule @@ -25835,12 +27804,18 @@ input [0:3] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -25851,12 +27826,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -25867,12 +27848,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -25931,7 +27918,7 @@ wire [0:0] mux_2level_tapbuf_basis_input4_mem4_0_out ; wire [0:0] mux_2level_tapbuf_basis_input4_mem4_1_out ; wire [0:0] mux_2level_tapbuf_basis_input4_mem4_2_out ; -sky130_fd_sc_hd__bufbuf_16 sky130_fd_sc_hd__buf_4_0_ ( +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( mux_2level_tapbuf_basis_input4_mem4_2_out[0] ) , .X ( out[0] ) ) ; sb_2__1__local_encoder2to4_2 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , .data ( local_encoder2to4_0_data ) , @@ -25965,12 +27952,18 @@ input [0:3] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -25981,12 +27974,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -25997,12 +27996,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -26061,9 +28066,8 @@ wire [0:0] mux_2level_tapbuf_basis_input4_mem4_0_out ; wire [0:0] mux_2level_tapbuf_basis_input4_mem4_1_out ; wire [0:0] mux_2level_tapbuf_basis_input4_mem4_2_out ; -sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_4_0_ ( - .A ( mux_2level_tapbuf_basis_input4_mem4_2_out[0] ) , - .X ( aps_rename_505_ ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( mux_2level_tapbuf_basis_input4_mem4_2_out[0] ) , .X ( out[0] ) ) ; sb_2__1__local_encoder2to4_0 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , .data ( local_encoder2to4_0_data ) , .data_inv ( local_encoder2to4_0_data_inv ) ) ; @@ -26085,9 +28089,6 @@ sb_2__1__mux_2level_tapbuf_basis_input4_mem4_2 mux_l2_in_0_ ( .mem ( local_encoder2to4_1_data ) , .mem_inv ( local_encoder2to4_1_data_inv ) , .out ( mux_2level_tapbuf_basis_input4_mem4_2_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_158 ( .A ( BUF_net_159 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_159 ( .A ( aps_rename_505_ ) , - .Y ( BUF_net_159 ) ) ; endmodule @@ -26239,9 +28240,13 @@ input [0:1] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( p0 ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -26252,10 +28257,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -26266,10 +28275,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -26280,10 +28293,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -26333,7 +28350,10 @@ wire [0:2] local_encoder2to3_1_data_inv ; wire [0:0] mux_2level_tapbuf_basis_input2_mem2_0_out ; wire [0:0] mux_2level_tapbuf_basis_input3_mem3_0_out ; wire [0:0] mux_2level_tapbuf_basis_input3_mem3_1_out ; +wire [0:0] mux_2level_tapbuf_basis_input3_mem3_2_out ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( mux_2level_tapbuf_basis_input3_mem3_2_out[0] ) , .X ( out[0] ) ) ; sb_2__1__local_encoder2to3_20 local_encoder2to3_0_ ( .addr ( sram[0:1] ) , .data ( local_encoder2to3_0_data ) , .data_inv ( local_encoder2to3_0_data_inv ) ) ; @@ -26353,7 +28373,8 @@ sb_2__1__mux_2level_tapbuf_basis_input3_mem3_36 mux_l2_in_0_ ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] , mux_2level_tapbuf_basis_input2_mem2_0_out[0] } ) , .mem ( local_encoder2to3_1_data ) , - .mem_inv ( local_encoder2to3_1_data_inv ) , .out ( out ) ) ; + .mem_inv ( local_encoder2to3_1_data_inv ) , + .out ( mux_2level_tapbuf_basis_input3_mem3_2_out ) ) ; sb_2__1__mux_2level_tapbuf_basis_input2_mem2_6 mux_l1_in_2_ ( .in ( { in[6] , SYNOPSYS_UNCONNECTED_1 } ) , .mem ( local_encoder2to3_0_data[0:1] ) , @@ -26370,9 +28391,13 @@ input [0:1] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( p0 ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -26383,10 +28408,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -26397,10 +28426,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -26411,10 +28444,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -26466,6 +28503,8 @@ wire [0:0] mux_2level_tapbuf_basis_input3_mem3_0_out ; wire [0:0] mux_2level_tapbuf_basis_input3_mem3_1_out ; wire [0:0] mux_2level_tapbuf_basis_input3_mem3_2_out ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( mux_2level_tapbuf_basis_input3_mem3_2_out[0] ) , .X ( out[0] ) ) ; sb_2__1__local_encoder2to3_18 local_encoder2to3_0_ ( .addr ( sram[0:1] ) , .data ( local_encoder2to3_0_data ) , .data_inv ( local_encoder2to3_0_data_inv ) ) ; @@ -26492,9 +28531,6 @@ sb_2__1__mux_2level_tapbuf_basis_input2_mem2_5 mux_l1_in_2_ ( .mem ( local_encoder2to3_0_data[0:1] ) , .mem_inv ( local_encoder2to3_0_data_inv[0:1] ) , .out ( mux_2level_tapbuf_basis_input2_mem2_0_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_156 ( .A ( BUF_net_157 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_157 ( - .A ( mux_2level_tapbuf_basis_input3_mem3_2_out[0] ) , .Y ( BUF_net_157 ) ) ; endmodule @@ -26506,9 +28542,13 @@ input [0:1] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( p0 ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -26519,10 +28559,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -26533,10 +28577,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -26547,10 +28595,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -26641,9 +28693,13 @@ input [0:1] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( p0 ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -26654,10 +28710,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -26668,10 +28728,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -26682,10 +28746,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -26776,9 +28844,13 @@ input [0:1] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( p0 ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -26789,10 +28861,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -26803,10 +28879,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -26817,10 +28897,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -26872,8 +28956,6 @@ wire [0:0] mux_2level_tapbuf_basis_input3_mem3_0_out ; wire [0:0] mux_2level_tapbuf_basis_input3_mem3_1_out ; wire [0:0] mux_2level_tapbuf_basis_input3_mem3_2_out ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( mux_2level_tapbuf_basis_input3_mem3_2_out[0] ) , .X ( out[0] ) ) ; sb_2__1__local_encoder2to3_12 local_encoder2to3_0_ ( .addr ( sram[0:1] ) , .data ( local_encoder2to3_0_data ) , .data_inv ( local_encoder2to3_0_data_inv ) ) ; @@ -26900,6 +28982,9 @@ sb_2__1__mux_2level_tapbuf_basis_input2_mem2_2 mux_l1_in_2_ ( .mem ( local_encoder2to3_0_data[0:1] ) , .mem_inv ( local_encoder2to3_0_data_inv[0:1] ) , .out ( mux_2level_tapbuf_basis_input2_mem2_0_out ) , .p0 ( p0 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_152 ( .A ( BUF_net_153 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_153 ( + .A ( mux_2level_tapbuf_basis_input3_mem3_2_out[0] ) , .Y ( BUF_net_153 ) ) ; endmodule @@ -26911,9 +28996,13 @@ input [0:1] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( p0 ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -26924,10 +29013,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -26938,10 +29031,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -26952,10 +29049,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -27046,9 +29147,13 @@ input [0:1] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( p0 ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -27059,10 +29164,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -27073,10 +29182,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -27087,10 +29200,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -27241,7 +29358,7 @@ input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ropt_net_226 ) , +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ropt_net_208 ) , .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; @@ -27250,30 +29367,28 @@ sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__buf_1 FTB_9__8 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1392 ( .A ( ccff_head[0] ) , - .X ( copt_net_204 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1393 ( .A ( copt_net_204 ) , - .X ( copt_net_205 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1394 ( .A ( ropt_net_227 ) , - .X ( copt_net_206 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1395 ( .A ( copt_net_205 ) , - .X ( copt_net_207 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1396 ( .A ( copt_net_207 ) , - .X ( copt_net_208 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1397 ( .A ( copt_net_208 ) , - .X ( copt_net_209 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1409 ( .A ( ropt_net_225 ) , - .X ( ropt_net_222 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1410 ( .A ( ropt_net_222 ) , - .X ( ropt_net_223 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1411 ( .A ( ropt_net_223 ) , - .X ( ropt_net_224 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 ropt_h_inst_1412 ( .A ( copt_net_206 ) , - .X ( ropt_net_225 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 ropt_h_inst_1413 ( .A ( ropt_net_224 ) , - .X ( ropt_net_226 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1414 ( .A ( copt_net_209 ) , - .X ( ropt_net_227 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1381 ( .A ( copt_net_195 ) , + .X ( copt_net_193 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1382 ( .A ( copt_net_193 ) , + .X ( copt_net_194 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1383 ( .A ( ccff_head[0] ) , + .X ( copt_net_195 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1384 ( .A ( copt_net_198 ) , + .X ( copt_net_196 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1385 ( .A ( copt_net_194 ) , + .X ( copt_net_197 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 copt_h_inst_1386 ( .A ( ropt_net_210 ) , + .X ( copt_net_198 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1397 ( .A ( copt_net_196 ) , + .X ( ropt_net_206 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1398 ( .A ( ropt_net_206 ) , + .X ( ropt_net_207 ) ) ; +sky130_fd_sc_hd__buf_2 ropt_h_inst_1399 ( .A ( ropt_net_207 ) , + .X ( ropt_net_208 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1400 ( .A ( copt_net_197 ) , + .X ( ropt_net_209 ) ) ; +sky130_fd_sc_hd__buf_1 ropt_h_inst_1401 ( .A ( ropt_net_209 ) , + .X ( ropt_net_210 ) ) ; endmodule @@ -27284,10 +29399,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -27299,10 +29418,14 @@ input [0:2] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -27313,10 +29436,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -27327,10 +29454,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -27382,6 +29513,8 @@ wire [0:0] mux_2level_tapbuf_basis_input3_mem3_1_out ; wire [0:0] mux_2level_tapbuf_basis_input3_mem3_2_out ; wire [0:0] mux_2level_tapbuf_basis_input3_mem3_3_out ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( mux_2level_tapbuf_basis_input3_mem3_3_out[0] ) , .X ( out[0] ) ) ; sb_2__1__local_encoder2to3_6 local_encoder2to3_0_ ( .addr ( sram[0:1] ) , .data ( local_encoder2to3_0_data ) , .data_inv ( local_encoder2to3_0_data_inv ) ) ; @@ -27408,9 +29541,6 @@ sb_2__1__mux_2level_tapbuf_basis_input3_mem3_15 mux_l2_in_0_ ( .mem ( local_encoder2to3_1_data ) , .mem_inv ( local_encoder2to3_1_data_inv ) , .out ( mux_2level_tapbuf_basis_input3_mem3_3_out ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_154 ( .A ( BUF_net_155 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_155 ( - .A ( mux_2level_tapbuf_basis_input3_mem3_3_out[0] ) , .Y ( BUF_net_155 ) ) ; endmodule @@ -27421,10 +29551,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -27436,10 +29570,14 @@ input [0:2] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -27450,10 +29588,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -27464,10 +29606,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -27519,6 +29665,8 @@ wire [0:0] mux_2level_tapbuf_basis_input3_mem3_1_out ; wire [0:0] mux_2level_tapbuf_basis_input3_mem3_2_out ; wire [0:0] mux_2level_tapbuf_basis_input3_mem3_3_out ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( mux_2level_tapbuf_basis_input3_mem3_3_out[0] ) , .X ( out[0] ) ) ; sb_2__1__local_encoder2to3_4 local_encoder2to3_0_ ( .addr ( sram[0:1] ) , .data ( local_encoder2to3_0_data ) , .data_inv ( local_encoder2to3_0_data_inv ) ) ; @@ -27545,9 +29693,6 @@ sb_2__1__mux_2level_tapbuf_basis_input3_mem3_11 mux_l2_in_0_ ( .mem ( local_encoder2to3_1_data ) , .mem_inv ( local_encoder2to3_1_data_inv ) , .out ( mux_2level_tapbuf_basis_input3_mem3_3_out ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_152 ( .A ( BUF_net_153 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_153 ( - .A ( mux_2level_tapbuf_basis_input3_mem3_3_out[0] ) , .Y ( BUF_net_153 ) ) ; endmodule @@ -27558,10 +29703,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -27573,10 +29722,14 @@ input [0:2] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -27587,10 +29740,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -27601,10 +29758,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -27656,6 +29817,8 @@ wire [0:0] mux_2level_tapbuf_basis_input3_mem3_1_out ; wire [0:0] mux_2level_tapbuf_basis_input3_mem3_2_out ; wire [0:0] mux_2level_tapbuf_basis_input3_mem3_3_out ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( mux_2level_tapbuf_basis_input3_mem3_3_out[0] ) , .X ( out[0] ) ) ; sb_2__1__local_encoder2to3_2 local_encoder2to3_0_ ( .addr ( sram[0:1] ) , .data ( local_encoder2to3_0_data ) , .data_inv ( local_encoder2to3_0_data_inv ) ) ; @@ -27682,9 +29845,6 @@ sb_2__1__mux_2level_tapbuf_basis_input3_mem3_7 mux_l2_in_0_ ( .mem ( local_encoder2to3_1_data ) , .mem_inv ( local_encoder2to3_1_data_inv ) , .out ( mux_2level_tapbuf_basis_input3_mem3_3_out ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_150 ( .A ( BUF_net_151 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_151 ( - .A ( mux_2level_tapbuf_basis_input3_mem3_3_out[0] ) , .Y ( BUF_net_151 ) ) ; endmodule @@ -27695,10 +29855,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -27710,10 +29874,14 @@ input [0:2] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -27724,10 +29892,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -27738,10 +29910,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -27793,8 +29969,6 @@ wire [0:0] mux_2level_tapbuf_basis_input3_mem3_1_out ; wire [0:0] mux_2level_tapbuf_basis_input3_mem3_2_out ; wire [0:0] mux_2level_tapbuf_basis_input3_mem3_3_out ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( mux_2level_tapbuf_basis_input3_mem3_3_out[0] ) , .X ( out[0] ) ) ; sb_2__1__local_encoder2to3_0 local_encoder2to3_0_ ( .addr ( sram[0:1] ) , .data ( local_encoder2to3_0_data ) , .data_inv ( local_encoder2to3_0_data_inv ) ) ; @@ -27821,6 +29995,9 @@ sb_2__1__mux_2level_tapbuf_basis_input3_mem3_3 mux_l2_in_0_ ( .mem ( local_encoder2to3_1_data ) , .mem_inv ( local_encoder2to3_1_data_inv ) , .out ( mux_2level_tapbuf_basis_input3_mem3_3_out ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_150 ( .A ( BUF_net_151 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_151 ( + .A ( mux_2level_tapbuf_basis_input3_mem3_3_out[0] ) , .Y ( BUF_net_151 ) ) ; endmodule @@ -27878,8 +30055,8 @@ input pReset_W_in ; output pReset_N_out ; input prog_clk_0_N_in ; -wire ropt_net_217 ; -wire ZBUF_74_0 ; +wire ZBUF_250_f_0 ; +wire ZBUF_263_f_0 ; wire [0:0] prog_clk ; wire prog_clk_0 ; wire [0:3] mux_2level_tapbuf_size10_0_sram ; @@ -27989,7 +30166,7 @@ sb_2__1__mux_2level_tapbuf_size8_0 mux_top_track_0 ( .sram ( mux_2level_tapbuf_size8_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 , SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) , - .out ( chany_top_out[0] ) , .p0 ( optlc_net_202 ) ) ; + .out ( chany_top_out[0] ) , .p0 ( optlc_net_192 ) ) ; sb_2__1__mux_2level_tapbuf_size8_1 mux_bottom_track_1 ( .in ( { chany_bottom_out[4] , chany_bottom_out[20] , bottom_right_grid_pin_1_[0] , bottom_left_grid_pin_46_[0] , @@ -27998,7 +30175,7 @@ sb_2__1__mux_2level_tapbuf_size8_1 mux_bottom_track_1 ( .sram ( mux_2level_tapbuf_size8_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 , SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 } ) , - .out ( chany_bottom_out[0] ) , .p0 ( optlc_net_202 ) ) ; + .out ( chany_bottom_out[0] ) , .p0 ( optlc_net_189 ) ) ; sb_2__1__mux_2level_tapbuf_size8_2 mux_bottom_track_3 ( .in ( { chany_bottom_out[7] , chany_bottom_out[21] , bottom_left_grid_pin_44_[0] , bottom_left_grid_pin_47_[0] , @@ -28007,7 +30184,7 @@ sb_2__1__mux_2level_tapbuf_size8_2 mux_bottom_track_3 ( .sram ( mux_2level_tapbuf_size8_2_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_9 , SYNOPSYS_UNCONNECTED_10 , SYNOPSYS_UNCONNECTED_11 , SYNOPSYS_UNCONNECTED_12 } ) , - .out ( chany_bottom_out[1] ) , .p0 ( optlc_net_199 ) ) ; + .out ( chany_bottom_out[1] ) , .p0 ( optlc_net_189 ) ) ; sb_2__1__mux_2level_tapbuf_size8 mux_bottom_track_5 ( .in ( { chany_bottom_out[8] , chany_bottom_out[23] , bottom_left_grid_pin_45_[0] , bottom_left_grid_pin_48_[0] , @@ -28016,7 +30193,7 @@ sb_2__1__mux_2level_tapbuf_size8 mux_bottom_track_5 ( .sram ( mux_2level_tapbuf_size8_3_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 , SYNOPSYS_UNCONNECTED_15 , SYNOPSYS_UNCONNECTED_16 } ) , - .out ( chany_bottom_out[2] ) , .p0 ( optlc_net_202 ) ) ; + .out ( chany_bottom_out[2] ) , .p0 ( optlc_net_189 ) ) ; sb_2__1__mux_2level_tapbuf_size8_mem_0 mem_top_track_0 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( mux_2level_tapbuf_size8_mem_0_ccff_tail ) , @@ -28043,7 +30220,7 @@ sb_2__1__mux_2level_tapbuf_size7_0 mux_top_track_2 ( .sram ( mux_2level_tapbuf_size7_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_17 , SYNOPSYS_UNCONNECTED_18 , SYNOPSYS_UNCONNECTED_19 , SYNOPSYS_UNCONNECTED_20 } ) , - .out ( chany_top_out[1] ) , .p0 ( optlc_net_202 ) ) ; + .out ( chany_top_out[1] ) , .p0 ( optlc_net_192 ) ) ; sb_2__1__mux_2level_tapbuf_size7_1 mux_top_track_4 ( .in ( { top_left_grid_pin_46_[0] , top_left_grid_pin_49_[0] , top_right_grid_pin_1_[0] , chany_top_out[8] , chany_top_out[23] , @@ -28051,7 +30228,7 @@ sb_2__1__mux_2level_tapbuf_size7_1 mux_top_track_4 ( .sram ( mux_2level_tapbuf_size7_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_21 , SYNOPSYS_UNCONNECTED_22 , SYNOPSYS_UNCONNECTED_23 , SYNOPSYS_UNCONNECTED_24 } ) , - .out ( chany_top_out[2] ) , .p0 ( optlc_net_201 ) ) ; + .out ( chany_top_out[2] ) , .p0 ( optlc_net_190 ) ) ; sb_2__1__mux_2level_tapbuf_size7_2 mux_top_track_12 ( .in ( { top_left_grid_pin_44_[0] , top_left_grid_pin_50_[0] , chany_top_out[12] , chany_top_out[27] , chanx_left_in[6] , @@ -28059,7 +30236,7 @@ sb_2__1__mux_2level_tapbuf_size7_2 mux_top_track_12 ( .sram ( mux_2level_tapbuf_size7_2_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_25 , SYNOPSYS_UNCONNECTED_26 , SYNOPSYS_UNCONNECTED_27 , SYNOPSYS_UNCONNECTED_28 } ) , - .out ( chany_top_out[6] ) , .p0 ( optlc_net_201 ) ) ; + .out ( chany_top_out[6] ) , .p0 ( optlc_net_190 ) ) ; sb_2__1__mux_2level_tapbuf_size7_3 mux_top_track_20 ( .in ( { top_left_grid_pin_45_[0] , top_left_grid_pin_51_[0] , chany_top_out[13] , chany_top_out[28] , chanx_left_in[5] , @@ -28067,7 +30244,7 @@ sb_2__1__mux_2level_tapbuf_size7_3 mux_top_track_20 ( .sram ( mux_2level_tapbuf_size7_3_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_29 , SYNOPSYS_UNCONNECTED_30 , SYNOPSYS_UNCONNECTED_31 , SYNOPSYS_UNCONNECTED_32 } ) , - .out ( chany_top_out[10] ) , .p0 ( optlc_net_201 ) ) ; + .out ( chany_top_out[10] ) , .p0 ( optlc_net_190 ) ) ; sb_2__1__mux_2level_tapbuf_size7_4 mux_top_track_28 ( .in ( { top_left_grid_pin_46_[0] , top_right_grid_pin_1_[0] , chany_top_out[15] , chany_top_out[29] , chanx_left_in[4] , @@ -28075,7 +30252,7 @@ sb_2__1__mux_2level_tapbuf_size7_4 mux_top_track_28 ( .sram ( mux_2level_tapbuf_size7_4_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_33 , SYNOPSYS_UNCONNECTED_34 , SYNOPSYS_UNCONNECTED_35 , SYNOPSYS_UNCONNECTED_36 } ) , - .out ( chany_top_out[14] ) , .p0 ( optlc_net_202 ) ) ; + .out ( chany_top_out[14] ) , .p0 ( optlc_net_192 ) ) ; sb_2__1__mux_2level_tapbuf_size7_5 mux_bottom_track_13 ( .in ( { chany_bottom_out[12] , chany_bottom_out[27] , bottom_right_grid_pin_1_[0] , bottom_left_grid_pin_49_[0] , @@ -28083,7 +30260,7 @@ sb_2__1__mux_2level_tapbuf_size7_5 mux_bottom_track_13 ( .sram ( mux_2level_tapbuf_size7_5_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_37 , SYNOPSYS_UNCONNECTED_38 , SYNOPSYS_UNCONNECTED_39 , SYNOPSYS_UNCONNECTED_40 } ) , - .out ( chany_bottom_out[6] ) , .p0 ( optlc_net_198 ) ) ; + .out ( chany_bottom_out[6] ) , .p0 ( optlc_net_187 ) ) ; sb_2__1__mux_2level_tapbuf_size7 mux_bottom_track_21 ( .in ( { chany_bottom_out[13] , chany_bottom_out[28] , bottom_left_grid_pin_44_[0] , bottom_left_grid_pin_50_[0] , @@ -28091,8 +30268,7 @@ sb_2__1__mux_2level_tapbuf_size7 mux_bottom_track_21 ( .sram ( mux_2level_tapbuf_size7_6_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_41 , SYNOPSYS_UNCONNECTED_42 , SYNOPSYS_UNCONNECTED_43 , SYNOPSYS_UNCONNECTED_44 } ) , - .out ( { aps_rename_508_ } ) , - .p0 ( optlc_net_198 ) ) ; + .out ( chany_bottom_out[10] ) , .p0 ( optlc_net_187 ) ) ; sb_2__1__mux_2level_tapbuf_size7_mem_0 mem_top_track_2 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( mux_2level_tapbuf_size8_mem_0_ccff_tail ) , @@ -28136,7 +30312,7 @@ sb_2__1__mux_2level_tapbuf_size9_0 mux_top_track_6 ( .sram ( mux_2level_tapbuf_size9_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_45 , SYNOPSYS_UNCONNECTED_46 , SYNOPSYS_UNCONNECTED_47 , SYNOPSYS_UNCONNECTED_48 } ) , - .out ( chany_top_out[3] ) , .p0 ( optlc_net_201 ) ) ; + .out ( chany_top_out[3] ) , .p0 ( optlc_net_190 ) ) ; sb_2__1__mux_2level_tapbuf_size9_1 mux_top_track_10 ( .in ( { top_left_grid_pin_45_[0] , top_left_grid_pin_47_[0] , top_left_grid_pin_49_[0] , top_left_grid_pin_51_[0] , @@ -28145,7 +30321,7 @@ sb_2__1__mux_2level_tapbuf_size9_1 mux_top_track_10 ( .sram ( mux_2level_tapbuf_size9_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_49 , SYNOPSYS_UNCONNECTED_50 , SYNOPSYS_UNCONNECTED_51 , SYNOPSYS_UNCONNECTED_52 } ) , - .out ( chany_top_out[5] ) , .p0 ( optlc_net_201 ) ) ; + .out ( chany_top_out[5] ) , .p0 ( optlc_net_190 ) ) ; sb_2__1__mux_2level_tapbuf_size9 mux_bottom_track_11 ( .in ( { chany_bottom_out[11] , chany_bottom_out[25] , bottom_left_grid_pin_44_[0] , bottom_left_grid_pin_46_[0] , @@ -28154,7 +30330,7 @@ sb_2__1__mux_2level_tapbuf_size9 mux_bottom_track_11 ( .sram ( mux_2level_tapbuf_size9_2_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_53 , SYNOPSYS_UNCONNECTED_54 , SYNOPSYS_UNCONNECTED_55 , SYNOPSYS_UNCONNECTED_56 } ) , - .out ( chany_bottom_out[5] ) , .p0 ( optlc_net_201 ) ) ; + .out ( chany_bottom_out[5] ) , .p0 ( optlc_net_190 ) ) ; sb_2__1__mux_2level_tapbuf_size9_mem_0 mem_top_track_6 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( mux_2level_tapbuf_size7_mem_1_ccff_tail ) , @@ -28176,42 +30352,42 @@ sb_2__1__mux_2level_tapbuf_size5_0 mux_top_track_36 ( .sram ( mux_2level_tapbuf_size5_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_57 , SYNOPSYS_UNCONNECTED_58 , SYNOPSYS_UNCONNECTED_59 , SYNOPSYS_UNCONNECTED_60 } ) , - .out ( chany_top_out[18] ) , .p0 ( optlc_net_202 ) ) ; + .out ( chany_top_out[18] ) , .p0 ( optlc_net_192 ) ) ; sb_2__1__mux_2level_tapbuf_size5_1 mux_top_track_44 ( .in ( { top_left_grid_pin_48_[0] , chany_top_out[17] , chanx_left_in[2] , chanx_left_in[13] , chanx_left_in[24] } ) , .sram ( mux_2level_tapbuf_size5_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_61 , SYNOPSYS_UNCONNECTED_62 , SYNOPSYS_UNCONNECTED_63 , SYNOPSYS_UNCONNECTED_64 } ) , - .out ( chany_top_out[22] ) , .p0 ( optlc_net_202 ) ) ; + .out ( chany_top_out[22] ) , .p0 ( optlc_net_192 ) ) ; sb_2__1__mux_2level_tapbuf_size5_2 mux_top_track_52 ( .in ( { top_left_grid_pin_49_[0] , chany_top_out[19] , chanx_left_in[1] , chanx_left_in[12] , chanx_left_in[23] } ) , .sram ( mux_2level_tapbuf_size5_2_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_65 , SYNOPSYS_UNCONNECTED_66 , SYNOPSYS_UNCONNECTED_67 , SYNOPSYS_UNCONNECTED_68 } ) , - .out ( chany_top_out[26] ) , .p0 ( optlc_net_202 ) ) ; + .out ( chany_top_out[26] ) , .p0 ( optlc_net_192 ) ) ; sb_2__1__mux_2level_tapbuf_size5_3 mux_bottom_track_53 ( .in ( { chany_bottom_out[19] , bottom_left_grid_pin_48_[0] , chanx_left_in[0] , chanx_left_in[11] , chanx_left_in[22] } ) , .sram ( mux_2level_tapbuf_size5_3_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_69 , SYNOPSYS_UNCONNECTED_70 , SYNOPSYS_UNCONNECTED_71 , SYNOPSYS_UNCONNECTED_72 } ) , - .out ( chany_bottom_out[26] ) , .p0 ( optlc_net_201 ) ) ; + .out ( chany_bottom_out[26] ) , .p0 ( optlc_net_192 ) ) ; sb_2__1__mux_2level_tapbuf_size5_4 mux_left_track_5 ( .in ( { chany_bottom_out[8] , chany_bottom_in[1] , chany_top_out[8] , left_bottom_grid_pin_38_[0] , chanx_left_out[19] } ) , .sram ( mux_2level_tapbuf_size5_4_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_73 , SYNOPSYS_UNCONNECTED_74 , SYNOPSYS_UNCONNECTED_75 , SYNOPSYS_UNCONNECTED_76 } ) , - .out ( chanx_left_out[2] ) , .p0 ( optlc_net_199 ) ) ; + .out ( chanx_left_out[2] ) , .p0 ( optlc_net_188 ) ) ; sb_2__1__mux_2level_tapbuf_size5 mux_left_track_11 ( .in ( { chany_bottom_out[12] , chany_bottom_in[5] , chany_top_out[12] , left_bottom_grid_pin_38_[0] , chanx_left_out[19] } ) , .sram ( mux_2level_tapbuf_size5_5_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_77 , SYNOPSYS_UNCONNECTED_78 , SYNOPSYS_UNCONNECTED_79 , SYNOPSYS_UNCONNECTED_80 } ) , - .out ( chanx_left_out[5] ) , .p0 ( optlc_net_198 ) ) ; + .out ( chanx_left_out[5] ) , .p0 ( optlc_net_191 ) ) ; sb_2__1__mux_2level_tapbuf_size5_mem_0 mem_top_track_36 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( mux_2level_tapbuf_size7_mem_4_ccff_tail ) , @@ -28251,7 +30427,7 @@ sb_2__1__mux_2level_tapbuf_size10 mux_bottom_track_7 ( .sram ( mux_2level_tapbuf_size10_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_81 , SYNOPSYS_UNCONNECTED_82 , SYNOPSYS_UNCONNECTED_83 , SYNOPSYS_UNCONNECTED_84 } ) , - .out ( chany_bottom_out[3] ) , .p0 ( optlc_net_201 ) ) ; + .out ( chany_bottom_out[3] ) , .p0 ( optlc_net_187 ) ) ; sb_2__1__mux_2level_tapbuf_size10_mem mem_bottom_track_7 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( mux_2level_tapbuf_size8_mem_3_ccff_tail ) , @@ -28264,7 +30440,7 @@ sb_2__1__mux_2level_tapbuf_size6_0 mux_bottom_track_29 ( .sram ( mux_2level_tapbuf_size6_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_85 , SYNOPSYS_UNCONNECTED_86 , SYNOPSYS_UNCONNECTED_87 , SYNOPSYS_UNCONNECTED_88 } ) , - .out ( chany_bottom_out[14] ) , .p0 ( optlc_net_198 ) ) ; + .out ( chany_bottom_out[14] ) , .p0 ( optlc_net_187 ) ) ; sb_2__1__mux_2level_tapbuf_size6_1 mux_left_track_1 ( .in ( { chany_top_in[0] , chany_bottom_out[4] , chany_top_out[4] , left_bottom_grid_pin_36_[0] , left_bottom_grid_pin_39_[0] , @@ -28272,7 +30448,7 @@ sb_2__1__mux_2level_tapbuf_size6_1 mux_left_track_1 ( .sram ( mux_2level_tapbuf_size6_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_89 , SYNOPSYS_UNCONNECTED_90 , SYNOPSYS_UNCONNECTED_91 , SYNOPSYS_UNCONNECTED_92 } ) , - .out ( chanx_left_out[0] ) , .p0 ( optlc_net_200 ) ) ; + .out ( chanx_left_out[0] ) , .p0 ( optlc_net_188 ) ) ; sb_2__1__mux_2level_tapbuf_size6_2 mux_left_track_3 ( .in ( { chany_bottom_out[7] , chany_bottom_in[0] , chany_top_out[7] , left_bottom_grid_pin_37_[0] , left_bottom_grid_pin_40_[0] , @@ -28280,7 +30456,7 @@ sb_2__1__mux_2level_tapbuf_size6_2 mux_left_track_3 ( .sram ( mux_2level_tapbuf_size6_2_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_93 , SYNOPSYS_UNCONNECTED_94 , SYNOPSYS_UNCONNECTED_95 , SYNOPSYS_UNCONNECTED_96 } ) , - .out ( chanx_left_out[1] ) , .p0 ( optlc_net_199 ) ) ; + .out ( chanx_left_out[1] ) , .p0 ( optlc_net_188 ) ) ; sb_2__1__mux_2level_tapbuf_size6_3 mux_left_track_7 ( .in ( { chany_bottom_out[9] , chany_bottom_in[2] , chany_top_out[9] , left_bottom_grid_pin_36_[0] , left_bottom_grid_pin_39_[0] , @@ -28288,7 +30464,7 @@ sb_2__1__mux_2level_tapbuf_size6_3 mux_left_track_7 ( .sram ( mux_2level_tapbuf_size6_3_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_97 , SYNOPSYS_UNCONNECTED_98 , SYNOPSYS_UNCONNECTED_99 , SYNOPSYS_UNCONNECTED_100 } ) , - .out ( chanx_left_out[3] ) , .p0 ( optlc_net_200 ) ) ; + .out ( chanx_left_out[3] ) , .p0 ( optlc_net_191 ) ) ; sb_2__1__mux_2level_tapbuf_size6 mux_left_track_9 ( .in ( { chany_bottom_out[11] , chany_bottom_in[4] , chany_top_out[11] , left_bottom_grid_pin_37_[0] , left_bottom_grid_pin_40_[0] , @@ -28296,7 +30472,7 @@ sb_2__1__mux_2level_tapbuf_size6 mux_left_track_9 ( .sram ( mux_2level_tapbuf_size6_4_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_101 , SYNOPSYS_UNCONNECTED_102 , SYNOPSYS_UNCONNECTED_103 , SYNOPSYS_UNCONNECTED_104 } ) , - .out ( chanx_left_out[4] ) , .p0 ( optlc_net_200 ) ) ; + .out ( chanx_left_out[4] ) , .p0 ( optlc_net_191 ) ) ; sb_2__1__mux_2level_tapbuf_size6_mem_0 mem_bottom_track_29 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( mux_2level_tapbuf_size7_mem_6_ccff_tail ) , @@ -28328,56 +30504,56 @@ sb_2__1__mux_2level_tapbuf_size4_0 mux_bottom_track_37 ( .sram ( mux_2level_tapbuf_size4_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_105 , SYNOPSYS_UNCONNECTED_106 , SYNOPSYS_UNCONNECTED_107 , SYNOPSYS_UNCONNECTED_108 } ) , - .out ( chany_bottom_out[18] ) , .p0 ( optlc_net_198 ) ) ; + .out ( chany_bottom_out[18] ) , .p0 ( optlc_net_187 ) ) ; sb_2__1__mux_2level_tapbuf_size4_1 mux_bottom_track_45 ( .in ( { chany_bottom_out[17] , bottom_left_grid_pin_47_[0] , chanx_left_in[10] , chanx_left_in[21] } ) , .sram ( mux_2level_tapbuf_size4_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_109 , SYNOPSYS_UNCONNECTED_110 , SYNOPSYS_UNCONNECTED_111 , SYNOPSYS_UNCONNECTED_112 } ) , - .out ( chany_bottom_out[22] ) , .p0 ( optlc_net_200 ) ) ; + .out ( chany_bottom_out[22] ) , .p0 ( optlc_net_187 ) ) ; sb_2__1__mux_2level_tapbuf_size4_2 mux_left_track_13 ( .in ( { chany_bottom_out[13] , chany_bottom_in[9] , chany_top_out[13] , left_bottom_grid_pin_36_[0] } ) , .sram ( mux_2level_tapbuf_size4_2_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_113 , SYNOPSYS_UNCONNECTED_114 , SYNOPSYS_UNCONNECTED_115 , SYNOPSYS_UNCONNECTED_116 } ) , - .out ( chanx_left_out[6] ) , .p0 ( optlc_net_198 ) ) ; + .out ( chanx_left_out[6] ) , .p0 ( optlc_net_187 ) ) ; sb_2__1__mux_2level_tapbuf_size4_3 mux_left_track_15 ( .in ( { chany_bottom_out[15] , chany_bottom_in[13] , chany_top_out[15] , left_bottom_grid_pin_37_[0] } ) , .sram ( mux_2level_tapbuf_size4_3_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_117 , SYNOPSYS_UNCONNECTED_118 , SYNOPSYS_UNCONNECTED_119 , SYNOPSYS_UNCONNECTED_120 } ) , - .out ( chanx_left_out[7] ) , .p0 ( optlc_net_198 ) ) ; + .out ( chanx_left_out[7] ) , .p0 ( optlc_net_191 ) ) ; sb_2__1__mux_2level_tapbuf_size4_4 mux_left_track_17 ( .in ( { chany_bottom_out[16] , chany_top_out[16] , chany_bottom_in[17] , left_bottom_grid_pin_38_[0] } ) , .sram ( mux_2level_tapbuf_size4_4_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_121 , SYNOPSYS_UNCONNECTED_122 , SYNOPSYS_UNCONNECTED_123 , SYNOPSYS_UNCONNECTED_124 } ) , - .out ( chanx_left_out[8] ) , .p0 ( optlc_net_198 ) ) ; + .out ( chanx_left_out[8] ) , .p0 ( optlc_net_191 ) ) ; sb_2__1__mux_2level_tapbuf_size4_5 mux_left_track_19 ( .in ( { chany_bottom_out[17] , chany_top_out[17] , chany_bottom_in[21] , left_bottom_grid_pin_39_[0] } ) , .sram ( mux_2level_tapbuf_size4_5_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_125 , SYNOPSYS_UNCONNECTED_126 , SYNOPSYS_UNCONNECTED_127 , SYNOPSYS_UNCONNECTED_128 } ) , - .out ( chanx_left_out[9] ) , .p0 ( optlc_net_200 ) ) ; + .out ( chanx_left_out[9] ) , .p0 ( optlc_net_191 ) ) ; sb_2__1__mux_2level_tapbuf_size4_6 mux_left_track_21 ( .in ( { chany_bottom_out[19] , chany_top_out[19] , chany_bottom_in[25] , left_bottom_grid_pin_40_[0] } ) , .sram ( mux_2level_tapbuf_size4_6_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_129 , SYNOPSYS_UNCONNECTED_130 , SYNOPSYS_UNCONNECTED_131 , SYNOPSYS_UNCONNECTED_132 } ) , - .out ( chanx_left_out[10] ) , .p0 ( optlc_net_200 ) ) ; + .out ( chanx_left_out[10] ) , .p0 ( optlc_net_191 ) ) ; sb_2__1__mux_2level_tapbuf_size4 mux_left_track_23 ( .in ( { chany_bottom_out[20] , chany_top_out[20] , chany_bottom_in[29] , chanx_left_out[19] } ) , .sram ( mux_2level_tapbuf_size4_7_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_133 , SYNOPSYS_UNCONNECTED_134 , SYNOPSYS_UNCONNECTED_135 , SYNOPSYS_UNCONNECTED_136 } ) , - .out ( chanx_left_out[11] ) , .p0 ( optlc_net_198 ) ) ; + .out ( chanx_left_out[11] ) , .p0 ( optlc_net_188 ) ) ; sb_2__1__mux_2level_tapbuf_size4_mem_0 mem_bottom_track_37 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( mux_2level_tapbuf_size6_mem_0_ccff_tail ) , @@ -28423,49 +30599,49 @@ sb_2__1__mux_2level_tapbuf_size3_0 mux_left_track_25 ( left_bottom_grid_pin_42_[0] } ) , .sram ( mux_2level_tapbuf_size3_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_137 , SYNOPSYS_UNCONNECTED_138 } ) , - .out ( chanx_left_out[12] ) , .p0 ( optlc_net_200 ) ) ; + .out ( chanx_left_out[12] ) , .p0 ( optlc_net_188 ) ) ; sb_2__1__mux_2level_tapbuf_size3_1 mux_left_track_27 ( .in ( { chany_bottom_out[23] , chany_top_out[23] , left_bottom_grid_pin_43_[0] } ) , .sram ( mux_2level_tapbuf_size3_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_139 , SYNOPSYS_UNCONNECTED_140 } ) , - .out ( chanx_left_out[13] ) , .p0 ( optlc_net_200 ) ) ; + .out ( chanx_left_out[13] ) , .p0 ( optlc_net_188 ) ) ; sb_2__1__mux_2level_tapbuf_size3_2 mux_left_track_29 ( .in ( { chany_bottom_out[24] , chany_top_out[24] , left_bottom_grid_pin_36_[0] } ) , .sram ( mux_2level_tapbuf_size3_2_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_141 , SYNOPSYS_UNCONNECTED_142 } ) , - .out ( chanx_left_out[14] ) , .p0 ( optlc_net_200 ) ) ; + .out ( chanx_left_out[14] ) , .p0 ( optlc_net_188 ) ) ; sb_2__1__mux_2level_tapbuf_size3_3 mux_left_track_31 ( .in ( { chany_bottom_out[25] , chany_top_out[25] , left_bottom_grid_pin_37_[0] } ) , .sram ( mux_2level_tapbuf_size3_3_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_143 , SYNOPSYS_UNCONNECTED_144 } ) , - .out ( chanx_left_out[15] ) , .p0 ( optlc_net_200 ) ) ; + .out ( chanx_left_out[15] ) , .p0 ( optlc_net_191 ) ) ; sb_2__1__mux_2level_tapbuf_size3_4 mux_left_track_33 ( .in ( { chany_bottom_out[27] , chany_top_out[27] , left_bottom_grid_pin_38_[0] } ) , .sram ( mux_2level_tapbuf_size3_4_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_145 , SYNOPSYS_UNCONNECTED_146 } ) , - .out ( chanx_left_out[16] ) , .p0 ( optlc_net_198 ) ) ; + .out ( chanx_left_out[16] ) , .p0 ( optlc_net_191 ) ) ; sb_2__1__mux_2level_tapbuf_size3_5 mux_left_track_35 ( .in ( { chany_bottom_out[28] , chany_top_out[28] , left_bottom_grid_pin_39_[0] } ) , .sram ( mux_2level_tapbuf_size3_5_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_147 , SYNOPSYS_UNCONNECTED_148 } ) , - .out ( chanx_left_out[17] ) , .p0 ( optlc_net_200 ) ) ; + .out ( chanx_left_out[17] ) , .p0 ( optlc_net_191 ) ) ; sb_2__1__mux_2level_tapbuf_size3_6 mux_left_track_37 ( .in ( { chany_bottom_out[29] , chany_top_out[29] , left_bottom_grid_pin_40_[0] } ) , .sram ( mux_2level_tapbuf_size3_6_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_149 , SYNOPSYS_UNCONNECTED_150 } ) , - .out ( chanx_left_out[18] ) , .p0 ( optlc_net_200 ) ) ; + .out ( chanx_left_out[18] ) , .p0 ( optlc_net_188 ) ) ; sb_2__1__mux_2level_tapbuf_size3 mux_left_track_51 ( .in ( { chany_top_in[9] , left_bottom_grid_pin_39_[0] , left_bottom_grid_pin_43_[0] } ) , .sram ( mux_2level_tapbuf_size3_7_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_151 , SYNOPSYS_UNCONNECTED_152 } ) , - .out ( chanx_left_out[25] ) , .p0 ( optlc_net_199 ) ) ; + .out ( chanx_left_out[25] ) , .p0 ( optlc_net_188 ) ) ; sb_2__1__mux_2level_tapbuf_size3_mem_0 mem_left_track_25 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( mux_2level_tapbuf_size4_mem_7_ccff_tail ) , @@ -28510,37 +30686,37 @@ sb_2__1__mux_2level_tapbuf_size2_0 mux_left_track_41 ( .in ( { chany_top_in[29] , left_bottom_grid_pin_42_[0] } ) , .sram ( mux_2level_tapbuf_size2_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_153 , SYNOPSYS_UNCONNECTED_154 } ) , - .out ( chanx_left_out[20] ) , .p0 ( optlc_net_199 ) ) ; + .out ( chanx_left_out[20] ) , .p0 ( optlc_net_189 ) ) ; sb_2__1__mux_2level_tapbuf_size2_1 mux_left_track_45 ( .in ( { chany_top_in[21] , left_bottom_grid_pin_36_[0] } ) , .sram ( mux_2level_tapbuf_size2_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_155 , SYNOPSYS_UNCONNECTED_156 } ) , - .out ( chanx_left_out[22] ) , .p0 ( optlc_net_199 ) ) ; + .out ( chanx_left_out[22] ) , .p0 ( optlc_net_189 ) ) ; sb_2__1__mux_2level_tapbuf_size2_2 mux_left_track_47 ( .in ( { chany_top_in[17] , left_bottom_grid_pin_37_[0] } ) , .sram ( mux_2level_tapbuf_size2_2_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_157 , SYNOPSYS_UNCONNECTED_158 } ) , - .out ( chanx_left_out[23] ) , .p0 ( optlc_net_199 ) ) ; + .out ( chanx_left_out[23] ) , .p0 ( optlc_net_188 ) ) ; sb_2__1__mux_2level_tapbuf_size2_3 mux_left_track_49 ( .in ( { chany_top_in[13] , left_bottom_grid_pin_38_[0] } ) , .sram ( mux_2level_tapbuf_size2_3_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_159 , SYNOPSYS_UNCONNECTED_160 } ) , - .out ( chanx_left_out[24] ) , .p0 ( optlc_net_199 ) ) ; + .out ( chanx_left_out[24] ) , .p0 ( optlc_net_189 ) ) ; sb_2__1__mux_2level_tapbuf_size2_4 mux_left_track_53 ( .in ( { chany_top_in[5] , left_bottom_grid_pin_40_[0] } ) , .sram ( mux_2level_tapbuf_size2_4_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_161 , SYNOPSYS_UNCONNECTED_162 } ) , - .out ( chanx_left_out[26] ) , .p0 ( optlc_net_199 ) ) ; + .out ( chanx_left_out[26] ) , .p0 ( optlc_net_189 ) ) ; sb_2__1__mux_2level_tapbuf_size2_5 mux_left_track_55 ( .in ( { chany_top_in[4] , chanx_left_out[19] } ) , .sram ( mux_2level_tapbuf_size2_5_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_163 , SYNOPSYS_UNCONNECTED_164 } ) , - .out ( chanx_left_out[27] ) , .p0 ( optlc_net_199 ) ) ; + .out ( chanx_left_out[27] ) , .p0 ( optlc_net_188 ) ) ; sb_2__1__mux_2level_tapbuf_size2 mux_left_track_57 ( .in ( { chany_top_in[2] , left_bottom_grid_pin_42_[0] } ) , .sram ( mux_2level_tapbuf_size2_6_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_165 , SYNOPSYS_UNCONNECTED_166 } ) , - .out ( chanx_left_out[28] ) , .p0 ( optlc_net_199 ) ) ; + .out ( chanx_left_out[28] ) , .p0 ( optlc_net_188 ) ) ; sb_2__1__mux_2level_tapbuf_size2_mem_0 mem_left_track_41 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( mux_2level_tapbuf_size3_mem_6_ccff_tail ) , @@ -28576,12 +30752,12 @@ sb_2__1__mux_2level_tapbuf_size2_mem mem_left_track_57 ( .pReset ( pReset ) , .ccff_head ( mux_2level_tapbuf_size2_mem_5_ccff_tail ) , .ccff_tail ( ccff_tail ) , .mem_out ( mux_2level_tapbuf_size2_6_sram ) ) ; sky130_fd_sc_hd__buf_8 pReset_FTB00 ( .A ( pReset_W_in ) , .X ( pReset[0] ) ) ; -sky130_fd_sc_hd__conb_1 optlc_200 ( .LO ( SYNOPSYS_UNCONNECTED_167 ) , - .HI ( optlc_net_198 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_189 ( .LO ( SYNOPSYS_UNCONNECTED_167 ) , + .HI ( optlc_net_187 ) ) ; sky130_fd_sc_hd__buf_1 prog_clk_0_FTB00 ( .A ( prog_clk_0_N_in ) , .X ( prog_clk[0] ) ) ; sky130_fd_sc_hd__buf_1 FTB_110__109 ( .A ( chany_top_in[1] ) , - .X ( ropt_net_217 ) ) ; + .X ( ZBUF_250_f_0 ) ) ; sky130_fd_sc_hd__buf_8 FTB_111__110 ( .A ( chany_top_in[3] ) , .X ( chany_bottom_out[4] ) ) ; sky130_fd_sc_hd__buf_8 FTB_112__111 ( .A ( chany_top_in[6] ) , @@ -28615,7 +30791,7 @@ sky130_fd_sc_hd__buf_8 FTB_125__124 ( .A ( chany_top_in[23] ) , sky130_fd_sc_hd__buf_8 FTB_126__125 ( .A ( chany_top_in[24] ) , .X ( chany_bottom_out[25] ) ) ; sky130_fd_sc_hd__buf_1 FTB_127__126 ( .A ( chany_top_in[25] ) , - .X ( ZBUF_74_0 ) ) ; + .X ( ZBUF_263_f_0 ) ) ; sky130_fd_sc_hd__buf_8 FTB_128__127 ( .A ( chany_top_in[26] ) , .X ( chany_bottom_out[27] ) ) ; sky130_fd_sc_hd__buf_8 FTB_129__128 ( .A ( chany_top_in[27] ) , @@ -28662,21 +30838,21 @@ sky130_fd_sc_hd__buf_8 FTB_149__148 ( .A ( chany_bottom_in[28] ) , .X ( chany_top_out[29] ) ) ; sky130_fd_sc_hd__buf_8 FTB_150__149 ( .A ( left_bottom_grid_pin_41_[0] ) , .X ( chanx_left_out[19] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_196 ( .A ( BUF_net_197 ) , .Y ( pReset_N_out ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_197 ( .A ( pReset_W_in ) , .Y ( BUF_net_197 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_202 ( .LO ( SYNOPSYS_UNCONNECTED_168 ) , - .HI ( optlc_net_199 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_204 ( .LO ( SYNOPSYS_UNCONNECTED_169 ) , - .HI ( optlc_net_200 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_207 ( .LO ( SYNOPSYS_UNCONNECTED_170 ) , - .HI ( optlc_net_201 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_209 ( .LO ( SYNOPSYS_UNCONNECTED_171 ) , - .HI ( optlc_net_202 ) ) ; -sky130_fd_sc_hd__buf_6 ZBUF_214_f_inst_210 ( .A ( aps_rename_508_ ) , - .X ( chany_bottom_out[10] ) ) ; -sky130_fd_sc_hd__buf_6 ropt_mt_inst_1406 ( .A ( ropt_net_217 ) , +sky130_fd_sc_hd__inv_8 BINV_R_183 ( .A ( BUF_net_184 ) , .Y ( pReset_N_out ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_184 ( .A ( pReset_W_in ) , .Y ( BUF_net_184 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_191 ( .LO ( SYNOPSYS_UNCONNECTED_168 ) , + .HI ( optlc_net_188 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_193 ( .LO ( SYNOPSYS_UNCONNECTED_169 ) , + .HI ( optlc_net_189 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_195 ( .LO ( SYNOPSYS_UNCONNECTED_170 ) , + .HI ( optlc_net_190 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_197 ( .LO ( SYNOPSYS_UNCONNECTED_171 ) , + .HI ( optlc_net_191 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_199 ( .LO ( SYNOPSYS_UNCONNECTED_172 ) , + .HI ( optlc_net_192 ) ) ; +sky130_fd_sc_hd__buf_6 ZBUF_250_f_inst_1393 ( .A ( ZBUF_250_f_0 ) , .X ( chanx_left_out[29] ) ) ; -sky130_fd_sc_hd__buf_6 ropt_mt_inst_1408 ( .A ( ZBUF_74_0 ) , +sky130_fd_sc_hd__buf_6 ropt_mt_inst_1396 ( .A ( ZBUF_263_f_0 ) , .X ( chanx_left_out[21] ) ) ; endmodule @@ -28689,17 +30865,17 @@ input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -wire copt_net_169 ; +wire copt_net_159 ; sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( copt_net_169 ) ) ; + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( copt_net_159 ) ) ; sky130_fd_sc_hd__buf_6 FTB_77__76 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; -sky130_fd_sc_hd__buf_1 ropt_h_inst_1366 ( .A ( ropt_net_188 ) , +sky130_fd_sc_hd__buf_1 copt_h_inst_1344 ( .A ( copt_net_163 ) , .X ( mem_out[1] ) ) ; -sky130_fd_sc_hd__buf_1 copt_h_inst_1348 ( .A ( copt_net_169 ) , - .X ( ropt_net_188 ) ) ; +sky130_fd_sc_hd__buf_1 copt_h_inst_1346 ( .A ( copt_net_159 ) , + .X ( copt_net_163 ) ) ; endmodule @@ -29298,8 +31474,6 @@ input p0 ; wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ; wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) ) ; sb_2__0__mux_2level_tapbuf_basis_input2_mem1_85 mux_l1_in_0_ ( .in ( in ) , .mem ( sram[0] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) , @@ -29310,6 +31484,8 @@ sb_2__0__mux_2level_tapbuf_basis_input2_mem1 mux_l2_in_0_ ( .mem ( sram[1] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_142 ( + .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) ) ; endmodule @@ -29348,8 +31524,6 @@ input p0 ; wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ; wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) ) ; sb_2__0__mux_2level_tapbuf_basis_input2_mem1_83 mux_l1_in_0_ ( .in ( in ) , .mem ( sram[0] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) , @@ -29360,6 +31534,8 @@ sb_2__0__mux_2level_tapbuf_basis_input2_mem1_84 mux_l2_in_0_ ( .mem ( sram[1] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_141 ( + .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) ) ; endmodule @@ -29421,7 +31597,7 @@ input [0:0] mem_inv ; output [0:0] out ; input p0 ; -sky130_fd_sc_hd__mux2_2 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , +sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ; endmodule @@ -29471,7 +31647,7 @@ input [0:0] mem_inv ; output [0:0] out ; input p0 ; -sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , +sky130_fd_sc_hd__mux2_2 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ; endmodule @@ -29558,9 +31734,9 @@ sb_2__0__mux_2level_tapbuf_basis_input2_mem1_76 mux_l2_in_0_ ( .mem ( sram[1] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_150 ( .A ( BUF_net_151 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_151 ( - .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_151 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_139 ( .A ( BUF_net_140 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_140 ( + .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_140 ) ) ; endmodule @@ -29609,9 +31785,9 @@ sb_2__0__mux_2level_tapbuf_basis_input2_mem1_74 mux_l2_in_0_ ( .mem ( sram[1] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_148 ( .A ( BUF_net_149 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_149 ( - .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_149 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_137 ( .A ( BUF_net_138 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_138 ( + .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_138 ) ) ; endmodule @@ -29660,9 +31836,9 @@ sb_2__0__mux_2level_tapbuf_basis_input2_mem1_72 mux_l2_in_0_ ( .mem ( sram[1] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_146 ( .A ( BUF_net_147 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_147 ( - .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_147 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_145 ( .A ( BUF_net_146 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_146 ( + .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_146 ) ) ; endmodule @@ -29674,7 +31850,7 @@ input [0:0] mem_inv ; output [0:0] out ; input p0 ; -sky130_fd_sc_hd__mux2_2 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , +sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ; endmodule @@ -29701,8 +31877,6 @@ input p0 ; wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ; wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) ) ; sb_2__0__mux_2level_tapbuf_basis_input2_mem1_69 mux_l1_in_0_ ( .in ( in ) , .mem ( sram[0] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) , @@ -29713,6 +31887,9 @@ sb_2__0__mux_2level_tapbuf_basis_input2_mem1_70 mux_l2_in_0_ ( .mem ( sram[1] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_135 ( .A ( BUF_net_136 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_136 ( + .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_136 ) ) ; endmodule @@ -29724,7 +31901,7 @@ input [0:0] mem_inv ; output [0:0] out ; input p0 ; -sky130_fd_sc_hd__mux2_2 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , +sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ; endmodule @@ -29751,8 +31928,6 @@ input p0 ; wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ; wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) ) ; sb_2__0__mux_2level_tapbuf_basis_input2_mem1_67 mux_l1_in_0_ ( .in ( in ) , .mem ( sram[0] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) , @@ -29763,6 +31938,9 @@ sb_2__0__mux_2level_tapbuf_basis_input2_mem1_68 mux_l2_in_0_ ( .mem ( sram[1] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_133 ( .A ( BUF_net_134 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_134 ( + .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_134 ) ) ; endmodule @@ -29774,7 +31952,7 @@ input [0:0] mem_inv ; output [0:0] out ; input p0 ; -sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , +sky130_fd_sc_hd__mux2_2 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ; endmodule @@ -29801,6 +31979,8 @@ input p0 ; wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ; wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) ) ; sb_2__0__mux_2level_tapbuf_basis_input2_mem1_65 mux_l1_in_0_ ( .in ( in ) , .mem ( sram[0] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) , @@ -29811,9 +31991,6 @@ sb_2__0__mux_2level_tapbuf_basis_input2_mem1_66 mux_l2_in_0_ ( .mem ( sram[1] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_144 ( .A ( BUF_net_145 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_145 ( - .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_145 ) ) ; endmodule @@ -29825,7 +32002,7 @@ input [0:0] mem_inv ; output [0:0] out ; input p0 ; -sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , +sky130_fd_sc_hd__mux2_2 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ; endmodule @@ -29852,6 +32029,8 @@ input p0 ; wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ; wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) ) ; sb_2__0__mux_2level_tapbuf_basis_input2_mem1_63 mux_l1_in_0_ ( .in ( in ) , .mem ( sram[0] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) , @@ -29862,9 +32041,6 @@ sb_2__0__mux_2level_tapbuf_basis_input2_mem1_64 mux_l2_in_0_ ( .mem ( sram[1] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_142 ( .A ( BUF_net_143 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_143 ( - .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_143 ) ) ; endmodule @@ -29876,7 +32052,7 @@ input [0:0] mem_inv ; output [0:0] out ; input p0 ; -sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , +sky130_fd_sc_hd__mux2_2 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ; endmodule @@ -29903,6 +32079,8 @@ input p0 ; wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ; wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) ) ; sb_2__0__mux_2level_tapbuf_basis_input2_mem1_61 mux_l1_in_0_ ( .in ( in ) , .mem ( sram[0] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) , @@ -29913,9 +32091,6 @@ sb_2__0__mux_2level_tapbuf_basis_input2_mem1_62 mux_l2_in_0_ ( .mem ( sram[1] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_140 ( .A ( BUF_net_141 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_141 ( - .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_141 ) ) ; endmodule @@ -29927,7 +32102,7 @@ input [0:0] mem_inv ; output [0:0] out ; input p0 ; -sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , +sky130_fd_sc_hd__mux2_2 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ; endmodule @@ -29954,6 +32129,8 @@ input p0 ; wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ; wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) ) ; sb_2__0__mux_2level_tapbuf_basis_input2_mem1_59 mux_l1_in_0_ ( .in ( in ) , .mem ( sram[0] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) , @@ -29964,9 +32141,6 @@ sb_2__0__mux_2level_tapbuf_basis_input2_mem1_60 mux_l2_in_0_ ( .mem ( sram[1] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_138 ( .A ( BUF_net_139 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_139 ( - .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_139 ) ) ; endmodule @@ -29978,7 +32152,7 @@ input [0:0] mem_inv ; output [0:0] out ; input p0 ; -sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , +sky130_fd_sc_hd__mux2_2 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ; endmodule @@ -30005,6 +32179,8 @@ input p0 ; wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ; wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) ) ; sb_2__0__mux_2level_tapbuf_basis_input2_mem1_57 mux_l1_in_0_ ( .in ( in ) , .mem ( sram[0] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) , @@ -30015,9 +32191,6 @@ sb_2__0__mux_2level_tapbuf_basis_input2_mem1_58 mux_l2_in_0_ ( .mem ( sram[1] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_136 ( .A ( BUF_net_137 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_137 ( - .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_137 ) ) ; endmodule @@ -30029,7 +32202,7 @@ input [0:0] mem_inv ; output [0:0] out ; input p0 ; -sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , +sky130_fd_sc_hd__mux2_2 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ; endmodule @@ -30066,9 +32239,8 @@ sb_2__0__mux_2level_tapbuf_basis_input2_mem1_56 mux_l2_in_0_ ( .mem ( sram[1] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_134 ( .A ( BUF_net_135 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_135 ( - .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_135 ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_132 ( + .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) ) ; endmodule @@ -30080,7 +32252,7 @@ input [0:0] mem_inv ; output [0:0] out ; input p0 ; -sky130_fd_sc_hd__mux2_2 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , +sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ; endmodule @@ -30117,8 +32289,9 @@ sb_2__0__mux_2level_tapbuf_basis_input2_mem1_54 mux_l2_in_0_ ( .mem ( sram[1] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_133 ( - .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_130 ( .A ( BUF_net_131 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_131 ( + .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_131 ) ) ; endmodule @@ -30207,6 +32380,8 @@ input p0 ; wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ; wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) ) ; sb_2__0__mux_2level_tapbuf_basis_input2_mem1_49 mux_l1_in_0_ ( .in ( in ) , .mem ( sram[0] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) , @@ -30217,8 +32392,6 @@ sb_2__0__mux_2level_tapbuf_basis_input2_mem1_50 mux_l2_in_0_ ( .mem ( sram[1] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_132 ( - .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) ) ; endmodule @@ -30230,7 +32403,7 @@ input [0:0] mem_inv ; output [0:0] out ; input p0 ; -sky130_fd_sc_hd__mux2_2 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , +sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ; endmodule @@ -30280,7 +32453,7 @@ input [0:0] mem_inv ; output [0:0] out ; input p0 ; -sky130_fd_sc_hd__mux2_2 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , +sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ; endmodule @@ -30357,8 +32530,6 @@ input p0 ; wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ; wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) ) ; sb_2__0__mux_2level_tapbuf_basis_input2_mem1_43 mux_l1_in_0_ ( .in ( in ) , .mem ( sram[0] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) , @@ -30369,6 +32540,9 @@ sb_2__0__mux_2level_tapbuf_basis_input2_mem1_44 mux_l2_in_0_ ( .mem ( sram[1] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_128 ( .A ( BUF_net_129 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_129 ( + .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_129 ) ) ; endmodule @@ -30380,7 +32554,7 @@ input [0:0] mem_inv ; output [0:0] out ; input p0 ; -sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , +sky130_fd_sc_hd__mux2_2 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ; endmodule @@ -30417,9 +32591,8 @@ sb_2__0__mux_2level_tapbuf_basis_input2_mem1_42 mux_l2_in_0_ ( .mem ( sram[1] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_130 ( .A ( BUF_net_131 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_131 ( - .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_131 ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_127 ( + .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) ) ; endmodule @@ -30431,7 +32604,7 @@ input [0:0] mem_inv ; output [0:0] out ; input p0 ; -sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , +sky130_fd_sc_hd__mux2_2 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ; endmodule @@ -30468,9 +32641,8 @@ sb_2__0__mux_2level_tapbuf_basis_input2_mem1_40 mux_l2_in_0_ ( .mem ( sram[1] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_128 ( .A ( BUF_net_129 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_129 ( - .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_129 ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_126 ( + .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) ) ; endmodule @@ -30519,9 +32691,9 @@ sb_2__0__mux_2level_tapbuf_basis_input2_mem1_38 mux_l2_in_0_ ( .mem ( sram[1] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_126 ( .A ( BUF_net_127 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_127 ( - .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_127 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_124 ( .A ( BUF_net_125 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_125 ( + .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_125 ) ) ; endmodule @@ -30533,7 +32705,7 @@ input [0:0] mem_inv ; output [0:0] out ; input p0 ; -sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , +sky130_fd_sc_hd__mux2_2 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ; endmodule @@ -30570,9 +32742,8 @@ sb_2__0__mux_2level_tapbuf_basis_input2_mem1_36 mux_l2_in_0_ ( .mem ( sram[1] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_124 ( .A ( BUF_net_125 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_125 ( - .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_125 ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_123 ( + .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) ) ; endmodule @@ -30584,7 +32755,7 @@ input [0:0] mem_inv ; output [0:0] out ; input p0 ; -sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , +sky130_fd_sc_hd__mux2_2 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ; endmodule @@ -30621,9 +32792,8 @@ sb_2__0__mux_2level_tapbuf_basis_input2_mem1_34 mux_l2_in_0_ ( .mem ( sram[1] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_122 ( .A ( BUF_net_123 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_123 ( - .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_123 ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_122 ( + .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) ) ; endmodule @@ -30685,7 +32855,7 @@ input [0:0] mem_inv ; output [0:0] out ; input p0 ; -sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , +sky130_fd_sc_hd__mux2_2 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ; endmodule @@ -30722,9 +32892,8 @@ sb_2__0__mux_2level_tapbuf_basis_input2_mem1_30 mux_l2_in_0_ ( .mem ( sram[1] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_120 ( .A ( BUF_net_121 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_121 ( - .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_121 ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_121 ( + .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) ) ; endmodule @@ -30773,9 +32942,9 @@ sb_2__0__mux_2level_tapbuf_basis_input2_mem1_28 mux_l2_in_0_ ( .mem ( sram[1] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_118 ( .A ( BUF_net_119 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_119 ( - .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_119 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_119 ( .A ( BUF_net_120 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_120 ( + .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_120 ) ) ; endmodule @@ -30824,9 +32993,9 @@ sb_2__0__mux_2level_tapbuf_basis_input2_mem1_26 mux_l2_in_0_ ( .mem ( sram[1] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_116 ( .A ( BUF_net_117 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_117 ( - .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_117 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_117 ( .A ( BUF_net_118 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_118 ( + .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_118 ) ) ; endmodule @@ -30865,6 +33034,8 @@ input p0 ; wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ; wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) ) ; sb_2__0__mux_2level_tapbuf_basis_input2_mem1_23 mux_l1_in_0_ ( .in ( in ) , .mem ( sram[0] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) , @@ -30875,9 +33046,6 @@ sb_2__0__mux_2level_tapbuf_basis_input2_mem1_24 mux_l2_in_0_ ( .mem ( sram[1] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_114 ( .A ( BUF_net_115 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_115 ( - .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_115 ) ) ; endmodule @@ -30926,8 +33094,9 @@ sb_2__0__mux_2level_tapbuf_basis_input2_mem1_22 mux_l2_in_0_ ( .mem ( sram[1] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_113 ( - .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_115 ( .A ( BUF_net_116 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_116 ( + .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_116 ) ) ; endmodule @@ -30976,9 +33145,9 @@ sb_2__0__mux_2level_tapbuf_basis_input2_mem1_20 mux_l2_in_0_ ( .mem ( sram[1] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_111 ( .A ( BUF_net_112 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_112 ( - .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_112 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_113 ( .A ( BUF_net_114 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_114 ( + .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_114 ) ) ; endmodule @@ -31017,6 +33186,8 @@ input p0 ; wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ; wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) ) ; sb_2__0__mux_2level_tapbuf_basis_input2_mem1_17 mux_l1_in_0_ ( .in ( in ) , .mem ( sram[0] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) , @@ -31027,9 +33198,6 @@ sb_2__0__mux_2level_tapbuf_basis_input2_mem1_18 mux_l2_in_0_ ( .mem ( sram[1] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_109 ( .A ( BUF_net_110 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_110 ( - .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_110 ) ) ; endmodule @@ -31170,7 +33338,7 @@ input [0:0] mem ; input [0:0] mem_inv ; output [0:0] out ; -sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) , +sky130_fd_sc_hd__mux2_2 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ; endmodule @@ -31226,9 +33394,8 @@ sb_2__0__mux_2level_tapbuf_basis_input2_mem1_14 mux_l2_in_0_ ( .mem ( sram[1] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_4 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_2_out ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_107 ( .A ( BUF_net_108 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_108 ( - .A ( mux_2level_tapbuf_basis_input2_mem1_2_out[0] ) , .Y ( BUF_net_108 ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_112 ( + .A ( mux_2level_tapbuf_basis_input2_mem1_2_out[0] ) , .X ( out[0] ) ) ; endmodule @@ -31239,7 +33406,7 @@ input [0:0] mem ; input [0:0] mem_inv ; output [0:0] out ; -sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) , +sky130_fd_sc_hd__mux2_2 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ; endmodule @@ -31295,9 +33462,8 @@ sb_2__0__mux_2level_tapbuf_basis_input2_mem1_11 mux_l2_in_0_ ( .mem ( sram[1] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_4 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_2_out ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_105 ( .A ( BUF_net_106 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_106 ( - .A ( mux_2level_tapbuf_basis_input2_mem1_2_out[0] ) , .Y ( BUF_net_106 ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_111 ( + .A ( mux_2level_tapbuf_basis_input2_mem1_2_out[0] ) , .X ( out[0] ) ) ; endmodule @@ -31308,7 +33474,7 @@ input [0:0] mem ; input [0:0] mem_inv ; output [0:0] out ; -sky130_fd_sc_hd__mux2_2 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) , +sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ; endmodule @@ -31349,8 +33515,6 @@ wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ; wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ; wire [0:0] mux_2level_tapbuf_basis_input2_mem1_2_out ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( mux_2level_tapbuf_basis_input2_mem1_2_out[0] ) , .X ( out[0] ) ) ; sb_2__0__mux_2level_tapbuf_basis_input2_mem1_6 mux_l1_in_0_ ( .in ( in[0:1] ) , .mem ( sram[0] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) , @@ -31366,6 +33530,9 @@ sb_2__0__mux_2level_tapbuf_basis_input2_mem1_8 mux_l2_in_0_ ( .mem ( sram[1] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_4 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_2_out ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_109 ( .A ( BUF_net_110 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_110 ( + .A ( mux_2level_tapbuf_basis_input2_mem1_2_out[0] ) , .Y ( BUF_net_110 ) ) ; endmodule @@ -31376,7 +33543,7 @@ input [0:0] mem ; input [0:0] mem_inv ; output [0:0] out ; -sky130_fd_sc_hd__mux2_2 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) , +sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ; endmodule @@ -31417,8 +33584,6 @@ wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ; wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ; wire [0:0] mux_2level_tapbuf_basis_input2_mem1_2_out ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( mux_2level_tapbuf_basis_input2_mem1_2_out[0] ) , .X ( out[0] ) ) ; sb_2__0__mux_2level_tapbuf_basis_input2_mem1_3 mux_l1_in_0_ ( .in ( in[0:1] ) , .mem ( sram[0] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) , @@ -31434,6 +33599,9 @@ sb_2__0__mux_2level_tapbuf_basis_input2_mem1_5 mux_l2_in_0_ ( .mem ( sram[1] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_4 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_2_out ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_107 ( .A ( BUF_net_108 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_108 ( + .A ( mux_2level_tapbuf_basis_input2_mem1_2_out[0] ) , .Y ( BUF_net_108 ) ) ; endmodule @@ -31485,8 +33653,6 @@ wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ; wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ; wire [0:0] mux_2level_tapbuf_basis_input2_mem1_2_out ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( mux_2level_tapbuf_basis_input2_mem1_2_out[0] ) , .X ( out[0] ) ) ; sb_2__0__mux_2level_tapbuf_basis_input2_mem1_0 mux_l1_in_0_ ( .in ( in[0:1] ) , .mem ( sram[0] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) , @@ -31502,6 +33668,9 @@ sb_2__0__mux_2level_tapbuf_basis_input2_mem1_2 mux_l2_in_0_ ( .mem ( sram[1] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_4 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_2_out ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_105 ( .A ( BUF_net_106 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_106 ( + .A ( mux_2level_tapbuf_basis_input2_mem1_2_out[0] ) , .Y ( BUF_net_106 ) ) ; endmodule @@ -31733,7 +33902,7 @@ input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ropt_net_186 ) , +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ropt_net_182 ) , .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; @@ -31742,28 +33911,28 @@ sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__buf_1 FTB_25__24 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1338 ( .A ( copt_net_161 ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1336 ( .A ( ccff_head[0] ) , + .X ( copt_net_153 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1337 ( .A ( copt_net_158 ) , + .X ( copt_net_154 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1338 ( .A ( copt_net_156 ) , + .X ( copt_net_155 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1339 ( .A ( copt_net_154 ) , + .X ( copt_net_156 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1340 ( .A ( copt_net_155 ) , + .X ( copt_net_157 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1341 ( .A ( copt_net_153 ) , .X ( copt_net_158 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1339 ( .A ( copt_net_158 ) , - .X ( copt_net_159 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1340 ( .A ( copt_net_163 ) , - .X ( copt_net_160 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1341 ( .A ( ccff_head[0] ) , - .X ( copt_net_161 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1342 ( .A ( copt_net_159 ) , - .X ( copt_net_162 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1343 ( .A ( copt_net_162 ) , - .X ( copt_net_163 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1361 ( .A ( ropt_net_184 ) , - .X ( ropt_net_183 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1362 ( .A ( copt_net_160 ) , - .X ( ropt_net_184 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1363 ( .A ( ropt_net_183 ) , - .X ( ropt_net_185 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1364 ( .A ( ropt_net_187 ) , - .X ( ropt_net_186 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1365 ( .A ( ropt_net_185 ) , - .X ( ropt_net_187 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1359 ( .A ( copt_net_157 ) , + .X ( ropt_net_178 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1360 ( .A ( ropt_net_178 ) , + .X ( ropt_net_179 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1361 ( .A ( ropt_net_179 ) , + .X ( ropt_net_180 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1362 ( .A ( ropt_net_180 ) , + .X ( ropt_net_181 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1363 ( .A ( ropt_net_181 ) , + .X ( ropt_net_182 ) ) ; endmodule @@ -31775,10 +33944,14 @@ input [0:2] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -31789,10 +33962,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -31872,10 +34049,14 @@ input [0:2] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -31886,10 +34067,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -31969,10 +34154,14 @@ input [0:2] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -31983,10 +34172,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -32066,10 +34259,14 @@ input [0:2] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -32080,10 +34277,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -32163,10 +34364,14 @@ input [0:2] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -32177,10 +34382,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -32260,10 +34469,14 @@ input [0:2] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -32274,10 +34487,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -32357,10 +34574,14 @@ input [0:2] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -32371,10 +34592,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -32440,8 +34665,9 @@ sb_2__0__mux_2level_tapbuf_basis_input3_mem3_11 mux_l2_in_0_ ( .mem ( local_encoder2to3_1_data ) , .mem_inv ( local_encoder2to3_1_data_inv ) , .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_92 ( - .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_91 ( .A ( BUF_net_92 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_92 ( + .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_92 ) ) ; endmodule @@ -32453,10 +34679,14 @@ input [0:2] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -32467,10 +34697,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -32536,9 +34770,9 @@ sb_2__0__mux_2level_tapbuf_basis_input3_mem3_9 mux_l2_in_0_ ( .mem ( local_encoder2to3_1_data ) , .mem_inv ( local_encoder2to3_1_data_inv ) , .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_90 ( .A ( BUF_net_91 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_91 ( - .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_91 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_89 ( .A ( BUF_net_90 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_90 ( + .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_90 ) ) ; endmodule @@ -32550,10 +34784,14 @@ input [0:2] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -32564,10 +34802,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -32633,9 +34875,8 @@ sb_2__0__mux_2level_tapbuf_basis_input3_mem3_7 mux_l2_in_0_ ( .mem ( local_encoder2to3_1_data ) , .mem_inv ( local_encoder2to3_1_data_inv ) , .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_88 ( .A ( BUF_net_89 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_89 ( - .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_89 ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_88 ( + .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .X ( out[0] ) ) ; endmodule @@ -32647,10 +34888,14 @@ input [0:2] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -32661,10 +34906,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -32743,10 +34992,14 @@ input [0:2] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -32757,10 +35010,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -32840,10 +35097,14 @@ input [0:2] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -32854,10 +35115,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -33084,84 +35349,84 @@ sb_2__0__mux_2level_tapbuf_size4_0 mux_top_track_0 ( .sram ( mux_2level_tapbuf_size4_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 , SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) , - .out ( chany_top_out[0] ) , .p0 ( optlc_net_156 ) ) ; + .out ( chany_top_out[0] ) , .p0 ( optlc_net_149 ) ) ; sb_2__0__mux_2level_tapbuf_size4_1 mux_top_track_2 ( .in ( { top_left_grid_pin_45_[0] , top_left_grid_pin_48_[0] , top_left_grid_pin_51_[0] , chanx_left_in[29] } ) , .sram ( mux_2level_tapbuf_size4_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 , SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 } ) , - .out ( chany_top_out[1] ) , .p0 ( optlc_net_156 ) ) ; + .out ( chany_top_out[1] ) , .p0 ( optlc_net_149 ) ) ; sb_2__0__mux_2level_tapbuf_size4_2 mux_top_track_4 ( .in ( { top_left_grid_pin_46_[0] , top_left_grid_pin_49_[0] , top_right_grid_pin_1_[0] , chanx_left_in[28] } ) , .sram ( mux_2level_tapbuf_size4_2_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_9 , SYNOPSYS_UNCONNECTED_10 , SYNOPSYS_UNCONNECTED_11 , SYNOPSYS_UNCONNECTED_12 } ) , - .out ( chany_top_out[2] ) , .p0 ( optlc_net_156 ) ) ; + .out ( chany_top_out[2] ) , .p0 ( optlc_net_149 ) ) ; sb_2__0__mux_2level_tapbuf_size4_3 mux_top_track_6 ( .in ( { top_left_grid_pin_44_[0] , top_left_grid_pin_47_[0] , top_left_grid_pin_50_[0] , chanx_left_in[27] } ) , .sram ( mux_2level_tapbuf_size4_3_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 , SYNOPSYS_UNCONNECTED_15 , SYNOPSYS_UNCONNECTED_16 } ) , - .out ( chany_top_out[3] ) , .p0 ( optlc_net_156 ) ) ; + .out ( chany_top_out[3] ) , .p0 ( optlc_net_149 ) ) ; sb_2__0__mux_2level_tapbuf_size4_4 mux_top_track_8 ( .in ( { top_left_grid_pin_45_[0] , top_left_grid_pin_48_[0] , top_left_grid_pin_51_[0] , chanx_left_in[26] } ) , .sram ( mux_2level_tapbuf_size4_4_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_17 , SYNOPSYS_UNCONNECTED_18 , SYNOPSYS_UNCONNECTED_19 , SYNOPSYS_UNCONNECTED_20 } ) , - .out ( chany_top_out[4] ) , .p0 ( optlc_net_156 ) ) ; + .out ( chany_top_out[4] ) , .p0 ( optlc_net_151 ) ) ; sb_2__0__mux_2level_tapbuf_size4_5 mux_top_track_10 ( .in ( { top_left_grid_pin_46_[0] , top_left_grid_pin_49_[0] , top_right_grid_pin_1_[0] , chanx_left_in[25] } ) , .sram ( mux_2level_tapbuf_size4_5_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_21 , SYNOPSYS_UNCONNECTED_22 , SYNOPSYS_UNCONNECTED_23 , SYNOPSYS_UNCONNECTED_24 } ) , - .out ( chany_top_out[5] ) , .p0 ( optlc_net_156 ) ) ; + .out ( chany_top_out[5] ) , .p0 ( optlc_net_152 ) ) ; sb_2__0__mux_2level_tapbuf_size4_6 mux_left_track_1 ( .in ( { chany_top_in[0] , left_bottom_grid_pin_1_[0] , left_bottom_grid_pin_7_[0] , left_bottom_grid_pin_13_[0] } ) , .sram ( mux_2level_tapbuf_size4_6_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_25 , SYNOPSYS_UNCONNECTED_26 , SYNOPSYS_UNCONNECTED_27 , SYNOPSYS_UNCONNECTED_28 } ) , - .out ( chanx_left_out[0] ) , .p0 ( optlc_net_154 ) ) ; + .out ( chanx_left_out[0] ) , .p0 ( optlc_net_147 ) ) ; sb_2__0__mux_2level_tapbuf_size4_7 mux_left_track_3 ( .in ( { chany_top_in[29] , left_bottom_grid_pin_3_[0] , left_bottom_grid_pin_9_[0] , left_bottom_grid_pin_15_[0] } ) , .sram ( mux_2level_tapbuf_size4_7_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_29 , SYNOPSYS_UNCONNECTED_30 , SYNOPSYS_UNCONNECTED_31 , SYNOPSYS_UNCONNECTED_32 } ) , - .out ( chanx_left_out[1] ) , .p0 ( optlc_net_154 ) ) ; + .out ( chanx_left_out[1] ) , .p0 ( optlc_net_147 ) ) ; sb_2__0__mux_2level_tapbuf_size4_8 mux_left_track_5 ( .in ( { chany_top_in[28] , left_bottom_grid_pin_5_[0] , left_bottom_grid_pin_11_[0] , left_bottom_grid_pin_17_[0] } ) , .sram ( mux_2level_tapbuf_size4_8_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_33 , SYNOPSYS_UNCONNECTED_34 , SYNOPSYS_UNCONNECTED_35 , SYNOPSYS_UNCONNECTED_36 } ) , - .out ( chanx_left_out[2] ) , .p0 ( optlc_net_154 ) ) ; + .out ( chanx_left_out[2] ) , .p0 ( optlc_net_147 ) ) ; sb_2__0__mux_2level_tapbuf_size4_9 mux_left_track_7 ( .in ( { chany_top_in[27] , left_bottom_grid_pin_1_[0] , left_bottom_grid_pin_7_[0] , left_bottom_grid_pin_13_[0] } ) , .sram ( mux_2level_tapbuf_size4_9_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_37 , SYNOPSYS_UNCONNECTED_38 , SYNOPSYS_UNCONNECTED_39 , SYNOPSYS_UNCONNECTED_40 } ) , - .out ( chanx_left_out[3] ) , .p0 ( optlc_net_154 ) ) ; + .out ( chanx_left_out[3] ) , .p0 ( optlc_net_147 ) ) ; sb_2__0__mux_2level_tapbuf_size4_10 mux_left_track_9 ( .in ( { chany_top_in[26] , left_bottom_grid_pin_3_[0] , left_bottom_grid_pin_9_[0] , left_bottom_grid_pin_15_[0] } ) , .sram ( mux_2level_tapbuf_size4_10_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_41 , SYNOPSYS_UNCONNECTED_42 , SYNOPSYS_UNCONNECTED_43 , SYNOPSYS_UNCONNECTED_44 } ) , - .out ( chanx_left_out[4] ) , .p0 ( optlc_net_154 ) ) ; + .out ( chanx_left_out[4] ) , .p0 ( optlc_net_149 ) ) ; sb_2__0__mux_2level_tapbuf_size4 mux_left_track_11 ( .in ( { chany_top_in[25] , left_bottom_grid_pin_5_[0] , left_bottom_grid_pin_11_[0] , left_bottom_grid_pin_17_[0] } ) , .sram ( mux_2level_tapbuf_size4_11_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_45 , SYNOPSYS_UNCONNECTED_46 , SYNOPSYS_UNCONNECTED_47 , SYNOPSYS_UNCONNECTED_48 } ) , - .out ( chanx_left_out[5] ) , .p0 ( optlc_net_156 ) ) ; + .out ( chanx_left_out[5] ) , .p0 ( optlc_net_151 ) ) ; sb_2__0__mux_2level_tapbuf_size4_mem_0 mem_top_track_0 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( mux_2level_tapbuf_size4_mem_0_ccff_tail ) , @@ -33226,31 +35491,31 @@ sb_2__0__mux_2level_tapbuf_size3_0 mux_top_track_12 ( chanx_left_in[24] } ) , .sram ( mux_2level_tapbuf_size3_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_49 , SYNOPSYS_UNCONNECTED_50 } ) , - .out ( chany_top_out[6] ) , .p0 ( optlc_net_157 ) ) ; + .out ( chany_top_out[6] ) , .p0 ( optlc_net_148 ) ) ; sb_2__0__mux_2level_tapbuf_size3_1 mux_top_track_44 ( .in ( { top_left_grid_pin_48_[0] , top_right_grid_pin_1_[0] , chanx_left_in[8] } ) , .sram ( mux_2level_tapbuf_size3_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_51 , SYNOPSYS_UNCONNECTED_52 } ) , - .out ( chany_top_out[22] ) , .p0 ( optlc_net_156 ) ) ; + .out ( chany_top_out[22] ) , .p0 ( optlc_net_151 ) ) ; sb_2__0__mux_2level_tapbuf_size3_2 mux_left_track_13 ( .in ( { chany_top_in[24] , left_bottom_grid_pin_1_[0] , left_bottom_grid_pin_17_[0] } ) , .sram ( mux_2level_tapbuf_size3_2_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_53 , SYNOPSYS_UNCONNECTED_54 } ) , - .out ( chanx_left_out[6] ) , .p0 ( optlc_net_157 ) ) ; + .out ( chanx_left_out[6] ) , .p0 ( optlc_net_151 ) ) ; sb_2__0__mux_2level_tapbuf_size3_3 mux_left_track_29 ( .in ( { chany_top_in[16] , left_bottom_grid_pin_1_[0] , left_bottom_grid_pin_17_[0] } ) , .sram ( mux_2level_tapbuf_size3_3_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_55 , SYNOPSYS_UNCONNECTED_56 } ) , - .out ( chanx_left_out[14] ) , .p0 ( optlc_net_155 ) ) ; + .out ( chanx_left_out[14] ) , .p0 ( optlc_net_147 ) ) ; sb_2__0__mux_2level_tapbuf_size3 mux_left_track_45 ( .in ( { chany_top_in[8] , left_bottom_grid_pin_1_[0] , left_bottom_grid_pin_17_[0] } ) , .sram ( mux_2level_tapbuf_size3_4_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_57 , SYNOPSYS_UNCONNECTED_58 } ) , - .out ( chanx_left_out[22] ) , .p0 ( optlc_net_155 ) ) ; + .out ( chanx_left_out[22] ) , .p0 ( optlc_net_147 ) ) ; sb_2__0__mux_2level_tapbuf_size3_mem_0 mem_top_track_12 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( mux_2level_tapbuf_size4_mem_5_ccff_tail ) , @@ -33280,182 +35545,182 @@ sb_2__0__mux_2level_tapbuf_size2_0 mux_top_track_14 ( .in ( { top_left_grid_pin_45_[0] , chanx_left_in[23] } ) , .sram ( mux_2level_tapbuf_size2_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_59 , SYNOPSYS_UNCONNECTED_60 } ) , - .out ( chany_top_out[7] ) , .p0 ( optlc_net_157 ) ) ; + .out ( chany_top_out[7] ) , .p0 ( optlc_net_148 ) ) ; sb_2__0__mux_2level_tapbuf_size2_1 mux_top_track_16 ( .in ( { top_left_grid_pin_46_[0] , chanx_left_in[22] } ) , .sram ( mux_2level_tapbuf_size2_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_61 , SYNOPSYS_UNCONNECTED_62 } ) , - .out ( chany_top_out[8] ) , .p0 ( optlc_net_157 ) ) ; + .out ( chany_top_out[8] ) , .p0 ( optlc_net_152 ) ) ; sb_2__0__mux_2level_tapbuf_size2_2 mux_top_track_18 ( .in ( { top_left_grid_pin_47_[0] , chanx_left_in[21] } ) , .sram ( mux_2level_tapbuf_size2_2_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_63 , SYNOPSYS_UNCONNECTED_64 } ) , - .out ( chany_top_out[9] ) , .p0 ( optlc_net_157 ) ) ; + .out ( chany_top_out[9] ) , .p0 ( optlc_net_148 ) ) ; sb_2__0__mux_2level_tapbuf_size2_3 mux_top_track_20 ( .in ( { top_left_grid_pin_48_[0] , chanx_left_in[20] } ) , .sram ( mux_2level_tapbuf_size2_3_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_65 , SYNOPSYS_UNCONNECTED_66 } ) , - .out ( chany_top_out[10] ) , .p0 ( optlc_net_157 ) ) ; + .out ( chany_top_out[10] ) , .p0 ( optlc_net_150 ) ) ; sb_2__0__mux_2level_tapbuf_size2_4 mux_top_track_22 ( .in ( { top_left_grid_pin_49_[0] , chanx_left_in[19] } ) , .sram ( mux_2level_tapbuf_size2_4_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_67 , SYNOPSYS_UNCONNECTED_68 } ) , - .out ( chany_top_out[11] ) , .p0 ( optlc_net_157 ) ) ; + .out ( chany_top_out[11] ) , .p0 ( optlc_net_150 ) ) ; sb_2__0__mux_2level_tapbuf_size2_5 mux_top_track_24 ( .in ( { top_left_grid_pin_50_[0] , chanx_left_in[18] } ) , .sram ( mux_2level_tapbuf_size2_5_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_69 , SYNOPSYS_UNCONNECTED_70 } ) , - .out ( chany_top_out[12] ) , .p0 ( optlc_net_155 ) ) ; + .out ( chany_top_out[12] ) , .p0 ( optlc_net_148 ) ) ; sb_2__0__mux_2level_tapbuf_size2_6 mux_top_track_26 ( .in ( { top_left_grid_pin_51_[0] , chanx_left_in[17] } ) , .sram ( mux_2level_tapbuf_size2_6_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_71 , SYNOPSYS_UNCONNECTED_72 } ) , - .out ( chany_top_out[13] ) , .p0 ( optlc_net_155 ) ) ; + .out ( chany_top_out[13] ) , .p0 ( optlc_net_150 ) ) ; sb_2__0__mux_2level_tapbuf_size2_7 mux_top_track_28 ( .in ( { top_right_grid_pin_1_[0] , chanx_left_in[16] } ) , .sram ( mux_2level_tapbuf_size2_7_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_73 , SYNOPSYS_UNCONNECTED_74 } ) , - .out ( chany_top_out[14] ) , .p0 ( optlc_net_157 ) ) ; + .out ( chany_top_out[14] ) , .p0 ( optlc_net_148 ) ) ; sb_2__0__mux_2level_tapbuf_size2_8 mux_top_track_36 ( .in ( { top_left_grid_pin_44_[0] , chanx_left_in[12] } ) , .sram ( mux_2level_tapbuf_size2_8_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_75 , SYNOPSYS_UNCONNECTED_76 } ) , - .out ( chany_top_out[18] ) , .p0 ( optlc_net_157 ) ) ; + .out ( chany_top_out[18] ) , .p0 ( optlc_net_148 ) ) ; sb_2__0__mux_2level_tapbuf_size2_9 mux_top_track_38 ( .in ( { top_left_grid_pin_45_[0] , chanx_left_in[11] } ) , .sram ( mux_2level_tapbuf_size2_9_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_77 , SYNOPSYS_UNCONNECTED_78 } ) , - .out ( chany_top_out[19] ) , .p0 ( optlc_net_157 ) ) ; + .out ( chany_top_out[19] ) , .p0 ( optlc_net_148 ) ) ; sb_2__0__mux_2level_tapbuf_size2_10 mux_top_track_40 ( .in ( { top_left_grid_pin_46_[0] , chanx_left_in[10] } ) , .sram ( mux_2level_tapbuf_size2_10_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_79 , SYNOPSYS_UNCONNECTED_80 } ) , - .out ( chany_top_out[20] ) , .p0 ( optlc_net_157 ) ) ; + .out ( chany_top_out[20] ) , .p0 ( optlc_net_148 ) ) ; sb_2__0__mux_2level_tapbuf_size2_11 mux_top_track_42 ( .in ( { top_left_grid_pin_47_[0] , chanx_left_in[9] } ) , .sram ( mux_2level_tapbuf_size2_11_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_81 , SYNOPSYS_UNCONNECTED_82 } ) , - .out ( chany_top_out[21] ) , .p0 ( optlc_net_157 ) ) ; + .out ( chany_top_out[21] ) , .p0 ( optlc_net_148 ) ) ; sb_2__0__mux_2level_tapbuf_size2_12 mux_top_track_46 ( .in ( { top_left_grid_pin_49_[0] , chanx_left_in[7] } ) , .sram ( mux_2level_tapbuf_size2_12_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_83 , SYNOPSYS_UNCONNECTED_84 } ) , - .out ( chany_top_out[23] ) , .p0 ( optlc_net_156 ) ) ; + .out ( chany_top_out[23] ) , .p0 ( optlc_net_149 ) ) ; sb_2__0__mux_2level_tapbuf_size2_13 mux_top_track_48 ( .in ( { top_left_grid_pin_50_[0] , chanx_left_in[6] } ) , .sram ( mux_2level_tapbuf_size2_13_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_85 , SYNOPSYS_UNCONNECTED_86 } ) , - .out ( chany_top_out[24] ) , .p0 ( optlc_net_156 ) ) ; + .out ( chany_top_out[24] ) , .p0 ( optlc_net_152 ) ) ; sb_2__0__mux_2level_tapbuf_size2_14 mux_top_track_50 ( .in ( { top_left_grid_pin_51_[0] , chanx_left_in[5] } ) , .sram ( mux_2level_tapbuf_size2_14_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_87 , SYNOPSYS_UNCONNECTED_88 } ) , - .out ( chany_top_out[25] ) , .p0 ( optlc_net_156 ) ) ; + .out ( chany_top_out[25] ) , .p0 ( optlc_net_149 ) ) ; sb_2__0__mux_2level_tapbuf_size2_15 mux_left_track_15 ( .in ( { chany_top_in[23] , left_bottom_grid_pin_3_[0] } ) , .sram ( mux_2level_tapbuf_size2_15_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_89 , SYNOPSYS_UNCONNECTED_90 } ) , - .out ( chanx_left_out[7] ) , .p0 ( optlc_net_157 ) ) ; + .out ( chanx_left_out[7] ) , .p0 ( optlc_net_152 ) ) ; sb_2__0__mux_2level_tapbuf_size2_16 mux_left_track_17 ( .in ( { chany_top_in[22] , left_bottom_grid_pin_5_[0] } ) , .sram ( mux_2level_tapbuf_size2_16_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_91 , SYNOPSYS_UNCONNECTED_92 } ) , - .out ( chanx_left_out[8] ) , .p0 ( optlc_net_157 ) ) ; + .out ( chanx_left_out[8] ) , .p0 ( optlc_net_152 ) ) ; sb_2__0__mux_2level_tapbuf_size2_17 mux_left_track_19 ( .in ( { chany_top_in[21] , left_bottom_grid_pin_7_[0] } ) , .sram ( mux_2level_tapbuf_size2_17_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_93 , SYNOPSYS_UNCONNECTED_94 } ) , - .out ( chanx_left_out[9] ) , .p0 ( optlc_net_157 ) ) ; + .out ( chanx_left_out[9] ) , .p0 ( optlc_net_148 ) ) ; sb_2__0__mux_2level_tapbuf_size2_18 mux_left_track_21 ( .in ( { chany_top_in[20] , left_bottom_grid_pin_9_[0] } ) , .sram ( mux_2level_tapbuf_size2_18_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_95 , SYNOPSYS_UNCONNECTED_96 } ) , - .out ( chanx_left_out[10] ) , .p0 ( optlc_net_155 ) ) ; + .out ( chanx_left_out[10] ) , .p0 ( optlc_net_148 ) ) ; sb_2__0__mux_2level_tapbuf_size2_19 mux_left_track_23 ( .in ( { chany_top_in[19] , left_bottom_grid_pin_11_[0] } ) , .sram ( mux_2level_tapbuf_size2_19_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_97 , SYNOPSYS_UNCONNECTED_98 } ) , - .out ( chanx_left_out[11] ) , .p0 ( optlc_net_155 ) ) ; + .out ( chanx_left_out[11] ) , .p0 ( optlc_net_150 ) ) ; sb_2__0__mux_2level_tapbuf_size2_20 mux_left_track_25 ( .in ( { chany_top_in[18] , left_bottom_grid_pin_13_[0] } ) , .sram ( mux_2level_tapbuf_size2_20_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_99 , SYNOPSYS_UNCONNECTED_100 } ) , - .out ( chanx_left_out[12] ) , .p0 ( optlc_net_155 ) ) ; + .out ( chanx_left_out[12] ) , .p0 ( optlc_net_148 ) ) ; sb_2__0__mux_2level_tapbuf_size2_21 mux_left_track_27 ( .in ( { chany_top_in[17] , left_bottom_grid_pin_15_[0] } ) , .sram ( mux_2level_tapbuf_size2_21_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_101 , SYNOPSYS_UNCONNECTED_102 } ) , - .out ( chanx_left_out[13] ) , .p0 ( optlc_net_155 ) ) ; + .out ( chanx_left_out[13] ) , .p0 ( optlc_net_150 ) ) ; sb_2__0__mux_2level_tapbuf_size2_22 mux_left_track_31 ( .in ( { chany_top_in[15] , left_bottom_grid_pin_3_[0] } ) , .sram ( mux_2level_tapbuf_size2_22_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_103 , SYNOPSYS_UNCONNECTED_104 } ) , - .out ( chanx_left_out[15] ) , .p0 ( optlc_net_155 ) ) ; + .out ( chanx_left_out[15] ) , .p0 ( optlc_net_150 ) ) ; sb_2__0__mux_2level_tapbuf_size2_23 mux_left_track_33 ( .in ( { chany_top_in[14] , left_bottom_grid_pin_5_[0] } ) , .sram ( mux_2level_tapbuf_size2_23_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_105 , SYNOPSYS_UNCONNECTED_106 } ) , - .out ( chanx_left_out[16] ) , .p0 ( optlc_net_155 ) ) ; + .out ( chanx_left_out[16] ) , .p0 ( optlc_net_150 ) ) ; sb_2__0__mux_2level_tapbuf_size2_24 mux_left_track_35 ( .in ( { chany_top_in[13] , left_bottom_grid_pin_7_[0] } ) , .sram ( mux_2level_tapbuf_size2_24_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_107 , SYNOPSYS_UNCONNECTED_108 } ) , - .out ( chanx_left_out[17] ) , .p0 ( optlc_net_154 ) ) ; + .out ( chanx_left_out[17] ) , .p0 ( optlc_net_150 ) ) ; sb_2__0__mux_2level_tapbuf_size2_25 mux_left_track_37 ( .in ( { chany_top_in[12] , left_bottom_grid_pin_9_[0] } ) , .sram ( mux_2level_tapbuf_size2_25_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_109 , SYNOPSYS_UNCONNECTED_110 } ) , - .out ( chanx_left_out[18] ) , .p0 ( optlc_net_154 ) ) ; + .out ( chanx_left_out[18] ) , .p0 ( optlc_net_150 ) ) ; sb_2__0__mux_2level_tapbuf_size2_26 mux_left_track_39 ( .in ( { chany_top_in[11] , left_bottom_grid_pin_11_[0] } ) , .sram ( mux_2level_tapbuf_size2_26_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_111 , SYNOPSYS_UNCONNECTED_112 } ) , - .out ( chanx_left_out[19] ) , .p0 ( optlc_net_155 ) ) ; + .out ( chanx_left_out[19] ) , .p0 ( optlc_net_150 ) ) ; sb_2__0__mux_2level_tapbuf_size2_27 mux_left_track_41 ( .in ( { chany_top_in[10] , left_bottom_grid_pin_13_[0] } ) , .sram ( mux_2level_tapbuf_size2_27_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_113 , SYNOPSYS_UNCONNECTED_114 } ) , - .out ( chanx_left_out[20] ) , .p0 ( optlc_net_155 ) ) ; + .out ( chanx_left_out[20] ) , .p0 ( optlc_net_150 ) ) ; sb_2__0__mux_2level_tapbuf_size2_28 mux_left_track_43 ( .in ( { chany_top_in[9] , left_bottom_grid_pin_15_[0] } ) , .sram ( mux_2level_tapbuf_size2_28_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_115 , SYNOPSYS_UNCONNECTED_116 } ) , - .out ( chanx_left_out[21] ) , .p0 ( optlc_net_155 ) ) ; + .out ( chanx_left_out[21] ) , .p0 ( optlc_net_150 ) ) ; sb_2__0__mux_2level_tapbuf_size2_29 mux_left_track_47 ( .in ( { chany_top_in[7] , left_bottom_grid_pin_3_[0] } ) , .sram ( mux_2level_tapbuf_size2_29_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_117 , SYNOPSYS_UNCONNECTED_118 } ) , - .out ( chanx_left_out[23] ) , .p0 ( optlc_net_154 ) ) ; + .out ( chanx_left_out[23] ) , .p0 ( optlc_net_150 ) ) ; sb_2__0__mux_2level_tapbuf_size2_30 mux_left_track_49 ( .in ( { chany_top_in[6] , left_bottom_grid_pin_5_[0] } ) , .sram ( mux_2level_tapbuf_size2_30_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_119 , SYNOPSYS_UNCONNECTED_120 } ) , - .out ( chanx_left_out[24] ) , .p0 ( optlc_net_154 ) ) ; + .out ( chanx_left_out[24] ) , .p0 ( optlc_net_147 ) ) ; sb_2__0__mux_2level_tapbuf_size2_31 mux_left_track_51 ( .in ( { chany_top_in[5] , left_bottom_grid_pin_7_[0] } ) , .sram ( mux_2level_tapbuf_size2_31_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_121 , SYNOPSYS_UNCONNECTED_122 } ) , - .out ( chanx_left_out[25] ) , .p0 ( optlc_net_154 ) ) ; + .out ( chanx_left_out[25] ) , .p0 ( optlc_net_148 ) ) ; sb_2__0__mux_2level_tapbuf_size2_32 mux_left_track_53 ( .in ( { chany_top_in[4] , left_bottom_grid_pin_9_[0] } ) , .sram ( mux_2level_tapbuf_size2_32_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_123 , SYNOPSYS_UNCONNECTED_124 } ) , - .out ( chanx_left_out[26] ) , .p0 ( optlc_net_155 ) ) ; + .out ( chanx_left_out[26] ) , .p0 ( optlc_net_152 ) ) ; sb_2__0__mux_2level_tapbuf_size2_33 mux_left_track_55 ( .in ( { chany_top_in[3] , left_bottom_grid_pin_11_[0] } ) , .sram ( mux_2level_tapbuf_size2_33_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_125 , SYNOPSYS_UNCONNECTED_126 } ) , - .out ( chanx_left_out[27] ) , .p0 ( optlc_net_155 ) ) ; + .out ( chanx_left_out[27] ) , .p0 ( optlc_net_148 ) ) ; sb_2__0__mux_2level_tapbuf_size2_34 mux_left_track_57 ( .in ( { chany_top_in[2] , left_bottom_grid_pin_13_[0] } ) , .sram ( mux_2level_tapbuf_size2_34_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_127 , SYNOPSYS_UNCONNECTED_128 } ) , - .out ( chanx_left_out[28] ) , .p0 ( optlc_net_157 ) ) ; + .out ( chanx_left_out[28] ) , .p0 ( optlc_net_148 ) ) ; sb_2__0__mux_2level_tapbuf_size2 mux_left_track_59 ( .in ( { chany_top_in[1] , left_bottom_grid_pin_15_[0] } ) , .sram ( mux_2level_tapbuf_size2_35_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_129 , SYNOPSYS_UNCONNECTED_130 } ) , - .out ( chanx_left_out[29] ) , .p0 ( optlc_net_157 ) ) ; + .out ( chanx_left_out[29] ) , .p0 ( optlc_net_152 ) ) ; sb_2__0__mux_2level_tapbuf_size2_mem_0 mem_top_track_14 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( mux_2level_tapbuf_size3_mem_0_ccff_tail ) , @@ -33636,32 +35901,36 @@ sb_2__0__mux_2level_tapbuf_size2_mem mem_left_track_59 ( .pReset ( pReset ) , .ccff_head ( mux_2level_tapbuf_size2_mem_34_ccff_tail ) , .ccff_tail ( ccff_tail ) , .mem_out ( mux_2level_tapbuf_size2_35_sram ) ) ; sky130_fd_sc_hd__buf_8 pReset_FTB00 ( .A ( pReset_W_in ) , .X ( pReset[0] ) ) ; -sky130_fd_sc_hd__conb_1 optlc_156 ( .LO ( SYNOPSYS_UNCONNECTED_131 ) , - .HI ( optlc_net_154 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_149 ( .LO ( SYNOPSYS_UNCONNECTED_131 ) , + .HI ( optlc_net_147 ) ) ; sky130_fd_sc_hd__buf_1 prog_clk_0_FTB00 ( .A ( prog_clk_0_N_in ) , .X ( prog_clk[0] ) ) ; -sky130_fd_sc_hd__buf_8 FTB_78__77 ( .A ( chanx_left_in[1] ) , +sky130_fd_sc_hd__buf_6 FTB_78__77 ( .A ( chanx_left_in[1] ) , .X ( chany_top_out[29] ) ) ; -sky130_fd_sc_hd__buf_6 FTB_79__78 ( .A ( chanx_left_in[2] ) , +sky130_fd_sc_hd__buf_8 FTB_79__78 ( .A ( chanx_left_in[2] ) , .X ( chany_top_out[28] ) ) ; sky130_fd_sc_hd__buf_8 FTB_80__79 ( .A ( chanx_left_in[3] ) , .X ( chany_top_out[27] ) ) ; sky130_fd_sc_hd__buf_8 FTB_81__80 ( .A ( chanx_left_in[4] ) , .X ( chany_top_out[26] ) ) ; -sky130_fd_sc_hd__buf_8 FTB_82__81 ( .A ( chanx_left_in[13] ) , +sky130_fd_sc_hd__buf_6 FTB_82__81 ( .A ( chanx_left_in[13] ) , .X ( chany_top_out[17] ) ) ; sky130_fd_sc_hd__buf_8 FTB_83__82 ( .A ( chanx_left_in[14] ) , .X ( chany_top_out[16] ) ) ; sky130_fd_sc_hd__buf_8 FTB_84__83 ( .A ( chanx_left_in[15] ) , .X ( chany_top_out[15] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_152 ( .A ( BUF_net_153 ) , .Y ( pReset_N_out ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_153 ( .A ( pReset_W_in ) , .Y ( BUF_net_153 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_158 ( .LO ( SYNOPSYS_UNCONNECTED_132 ) , - .HI ( optlc_net_155 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_160 ( .LO ( SYNOPSYS_UNCONNECTED_133 ) , - .HI ( optlc_net_156 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_162 ( .LO ( SYNOPSYS_UNCONNECTED_134 ) , - .HI ( optlc_net_157 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_143 ( .A ( BUF_net_144 ) , .Y ( pReset_N_out ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_144 ( .A ( pReset_W_in ) , .Y ( BUF_net_144 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_151 ( .LO ( SYNOPSYS_UNCONNECTED_132 ) , + .HI ( optlc_net_148 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_153 ( .LO ( SYNOPSYS_UNCONNECTED_133 ) , + .HI ( optlc_net_149 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_156 ( .LO ( SYNOPSYS_UNCONNECTED_134 ) , + .HI ( optlc_net_150 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_158 ( .LO ( SYNOPSYS_UNCONNECTED_135 ) , + .HI ( optlc_net_151 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_160 ( .LO ( SYNOPSYS_UNCONNECTED_136 ) , + .HI ( optlc_net_152 ) ) ; endmodule @@ -33855,7 +36124,7 @@ input [0:0] mem_inv ; output [0:0] out ; input p0 ; -sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , +sky130_fd_sc_hd__mux2_2 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ; endmodule @@ -33932,8 +36201,6 @@ input p0 ; wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ; wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) ) ; sb_1__2__mux_2level_tapbuf_basis_input2_mem1_30 mux_l1_in_0_ ( .in ( in ) , .mem ( sram[0] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) , @@ -33944,6 +36211,9 @@ sb_1__2__mux_2level_tapbuf_basis_input2_mem1_31 mux_l2_in_0_ ( .mem ( sram[1] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_195 ( .A ( BUF_net_196 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_196 ( + .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_196 ) ) ; endmodule @@ -33955,7 +36225,7 @@ input [0:0] mem_inv ; output [0:0] out ; input p0 ; -sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , +sky130_fd_sc_hd__mux2_2 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ; endmodule @@ -34005,7 +36275,7 @@ input [0:0] mem_inv ; output [0:0] out ; input p0 ; -sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , +sky130_fd_sc_hd__mux2_2 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ; endmodule @@ -34082,6 +36352,8 @@ input p0 ; wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ; wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) ) ; sb_1__2__mux_2level_tapbuf_basis_input2_mem1_24 mux_l1_in_0_ ( .in ( in ) , .mem ( sram[0] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) , @@ -34092,8 +36364,6 @@ sb_1__2__mux_2level_tapbuf_basis_input2_mem1_25 mux_l2_in_0_ ( .mem ( sram[1] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_197 ( - .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) ) ; endmodule @@ -34132,6 +36402,8 @@ input p0 ; wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ; wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) ) ; sb_1__2__mux_2level_tapbuf_basis_input2_mem1_22 mux_l1_in_0_ ( .in ( in ) , .mem ( sram[0] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) , @@ -34142,9 +36414,6 @@ sb_1__2__mux_2level_tapbuf_basis_input2_mem1_23 mux_l2_in_0_ ( .mem ( sram[1] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_195 ( .A ( BUF_net_196 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_196 ( - .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_196 ) ) ; endmodule @@ -34156,7 +36425,7 @@ input [0:0] mem_inv ; output [0:0] out ; input p0 ; -sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , +sky130_fd_sc_hd__mux2_2 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ; endmodule @@ -34183,8 +36452,6 @@ input p0 ; wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ; wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) ) ; sb_1__2__mux_2level_tapbuf_basis_input2_mem1_20 mux_l1_in_0_ ( .in ( in ) , .mem ( sram[0] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) , @@ -34195,6 +36462,8 @@ sb_1__2__mux_2level_tapbuf_basis_input2_mem1_21 mux_l2_in_0_ ( .mem ( sram[1] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_194 ( + .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) ) ; endmodule @@ -34206,7 +36475,7 @@ input [0:0] mem_inv ; output [0:0] out ; input p0 ; -sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , +sky130_fd_sc_hd__mux2_2 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ; endmodule @@ -34233,6 +36502,8 @@ input p0 ; wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ; wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) ) ; sb_1__2__mux_2level_tapbuf_basis_input2_mem1_18 mux_l1_in_0_ ( .in ( in ) , .mem ( sram[0] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) , @@ -34243,9 +36514,6 @@ sb_1__2__mux_2level_tapbuf_basis_input2_mem1_19 mux_l2_in_0_ ( .mem ( sram[1] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_193 ( .A ( BUF_net_194 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_194 ( - .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_194 ) ) ; endmodule @@ -34257,7 +36525,7 @@ input [0:0] mem_inv ; output [0:0] out ; input p0 ; -sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , +sky130_fd_sc_hd__mux2_2 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ; endmodule @@ -34384,6 +36652,8 @@ input p0 ; wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ; wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) ) ; sb_1__2__mux_2level_tapbuf_basis_input2_mem1_12 mux_l1_in_0_ ( .in ( in ) , .mem ( sram[0] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) , @@ -34394,8 +36664,6 @@ sb_1__2__mux_2level_tapbuf_basis_input2_mem1_13 mux_l2_in_0_ ( .mem ( sram[1] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_192 ( - .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) ) ; endmodule @@ -34470,7 +36738,7 @@ input [0:0] mem ; input [0:0] mem_inv ; output [0:0] out ; -sky130_fd_sc_hd__mux2_2 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) , +sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ; endmodule @@ -34511,8 +36779,6 @@ wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ; wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ; wire [0:0] mux_2level_tapbuf_basis_input2_mem1_2_out ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( mux_2level_tapbuf_basis_input2_mem1_2_out[0] ) , .X ( out[0] ) ) ; sb_1__2__mux_2level_tapbuf_basis_input2_mem1_9 mux_l1_in_0_ ( .in ( in[0:1] ) , .mem ( sram[0] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) , @@ -34528,6 +36794,9 @@ sb_1__2__mux_2level_tapbuf_basis_input2_mem1_11 mux_l2_in_0_ ( .mem ( sram[1] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_4 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_2_out ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_192 ( .A ( BUF_net_193 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_193 ( + .A ( mux_2level_tapbuf_basis_input2_mem1_2_out[0] ) , .Y ( BUF_net_193 ) ) ; endmodule @@ -34647,6 +36916,8 @@ wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ; wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ; wire [0:0] mux_2level_tapbuf_basis_input2_mem1_2_out ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( mux_2level_tapbuf_basis_input2_mem1_2_out[0] ) , .X ( out[0] ) ) ; sb_1__2__mux_2level_tapbuf_basis_input2_mem1_3 mux_l1_in_0_ ( .in ( in[0:1] ) , .mem ( sram[0] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) , @@ -34662,8 +36933,6 @@ sb_1__2__mux_2level_tapbuf_basis_input2_mem1_5 mux_l2_in_0_ ( .mem ( sram[1] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_4 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_2_out ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_191 ( - .A ( mux_2level_tapbuf_basis_input2_mem1_2_out[0] ) , .X ( out[0] ) ) ; endmodule @@ -34730,9 +36999,9 @@ sb_1__2__mux_2level_tapbuf_basis_input2_mem1_2 mux_l2_in_0_ ( .mem ( sram[1] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_4 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_2_out ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_189 ( .A ( BUF_net_190 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_190 ( - .A ( mux_2level_tapbuf_basis_input2_mem1_2_out[0] ) , .Y ( BUF_net_190 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_190 ( .A ( BUF_net_191 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_191 ( + .A ( mux_2level_tapbuf_basis_input2_mem1_2_out[0] ) , .Y ( BUF_net_191 ) ) ; endmodule @@ -34824,10 +37093,14 @@ input [0:2] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -34838,10 +37111,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -34852,10 +37129,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -34927,9 +37208,9 @@ sb_1__2__mux_2level_tapbuf_basis_input3_mem3 mux_l2_in_0_ ( .mem ( local_encoder2to3_1_data ) , .mem_inv ( local_encoder2to3_1_data_inv ) , .out ( mux_2level_tapbuf_basis_input3_mem3_2_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_187 ( .A ( BUF_net_188 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_188 ( - .A ( mux_2level_tapbuf_basis_input3_mem3_2_out[0] ) , .Y ( BUF_net_188 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_188 ( .A ( BUF_net_189 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_189 ( + .A ( mux_2level_tapbuf_basis_input3_mem3_2_out[0] ) , .Y ( BUF_net_189 ) ) ; endmodule @@ -34941,10 +37222,14 @@ input [0:2] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -34955,10 +37240,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -34969,10 +37258,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -35044,9 +37337,8 @@ sb_1__2__mux_2level_tapbuf_basis_input3_mem3_73 mux_l2_in_0_ ( .mem ( local_encoder2to3_1_data ) , .mem_inv ( local_encoder2to3_1_data_inv ) , .out ( mux_2level_tapbuf_basis_input3_mem3_2_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_185 ( .A ( BUF_net_186 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_186 ( - .A ( mux_2level_tapbuf_basis_input3_mem3_2_out[0] ) , .Y ( BUF_net_186 ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_187 ( + .A ( mux_2level_tapbuf_basis_input3_mem3_2_out[0] ) , .X ( out[0] ) ) ; endmodule @@ -35058,10 +37350,14 @@ input [0:2] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -35072,10 +37368,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -35086,10 +37386,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -35161,7 +37465,7 @@ sb_1__2__mux_2level_tapbuf_basis_input3_mem3_70 mux_l2_in_0_ ( .mem ( local_encoder2to3_1_data ) , .mem_inv ( local_encoder2to3_1_data_inv ) , .out ( mux_2level_tapbuf_basis_input3_mem3_2_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_184 ( +sky130_fd_sc_hd__buf_6 BUFT_RR_186 ( .A ( mux_2level_tapbuf_basis_input3_mem3_2_out[0] ) , .X ( out[0] ) ) ; endmodule @@ -35174,10 +37478,14 @@ input [0:2] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -35188,10 +37496,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -35202,10 +37514,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -35277,9 +37593,9 @@ sb_1__2__mux_2level_tapbuf_basis_input3_mem3_67 mux_l2_in_0_ ( .mem ( local_encoder2to3_1_data ) , .mem_inv ( local_encoder2to3_1_data_inv ) , .out ( mux_2level_tapbuf_basis_input3_mem3_2_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_182 ( .A ( BUF_net_183 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_183 ( - .A ( mux_2level_tapbuf_basis_input3_mem3_2_out[0] ) , .Y ( BUF_net_183 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_184 ( .A ( BUF_net_185 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_185 ( + .A ( mux_2level_tapbuf_basis_input3_mem3_2_out[0] ) , .Y ( BUF_net_185 ) ) ; endmodule @@ -35451,10 +37767,14 @@ input [0:2] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -35465,10 +37785,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -35547,10 +37871,14 @@ input [0:2] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -35561,10 +37889,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -35614,8 +37946,6 @@ wire [0:2] local_encoder2to3_1_data_inv ; wire [0:0] mux_2level_tapbuf_basis_input3_mem3_0_out ; wire [0:0] mux_2level_tapbuf_basis_input3_mem3_1_out ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .X ( out[0] ) ) ; sb_1__2__local_encoder2to3_46 local_encoder2to3_0_ ( .addr ( sram[0:1] ) , .data ( local_encoder2to3_0_data ) , .data_inv ( local_encoder2to3_0_data_inv ) ) ; @@ -35632,6 +37962,8 @@ sb_1__2__mux_2level_tapbuf_basis_input3_mem3_62 mux_l2_in_0_ ( .mem ( local_encoder2to3_1_data ) , .mem_inv ( local_encoder2to3_1_data_inv ) , .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .p0 ( p0 ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_183 ( + .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .X ( out[0] ) ) ; endmodule @@ -35643,10 +37975,14 @@ input [0:2] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -35657,10 +37993,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -35710,6 +38050,8 @@ wire [0:2] local_encoder2to3_1_data_inv ; wire [0:0] mux_2level_tapbuf_basis_input3_mem3_0_out ; wire [0:0] mux_2level_tapbuf_basis_input3_mem3_1_out ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .X ( out[0] ) ) ; sb_1__2__local_encoder2to3_44 local_encoder2to3_0_ ( .addr ( sram[0:1] ) , .data ( local_encoder2to3_0_data ) , .data_inv ( local_encoder2to3_0_data_inv ) ) ; @@ -35726,9 +38068,6 @@ sb_1__2__mux_2level_tapbuf_basis_input3_mem3_60 mux_l2_in_0_ ( .mem ( local_encoder2to3_1_data ) , .mem_inv ( local_encoder2to3_1_data_inv ) , .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_180 ( .A ( BUF_net_181 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_181 ( - .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_181 ) ) ; endmodule @@ -35740,10 +38079,14 @@ input [0:2] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -35754,10 +38097,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -35823,9 +38170,9 @@ sb_1__2__mux_2level_tapbuf_basis_input3_mem3_58 mux_l2_in_0_ ( .mem ( local_encoder2to3_1_data ) , .mem_inv ( local_encoder2to3_1_data_inv ) , .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_178 ( .A ( BUF_net_179 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_179 ( - .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_179 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_181 ( .A ( BUF_net_182 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_182 ( + .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_182 ) ) ; endmodule @@ -35837,10 +38184,14 @@ input [0:2] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -35851,10 +38202,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -35920,9 +38275,9 @@ sb_1__2__mux_2level_tapbuf_basis_input3_mem3_56 mux_l2_in_0_ ( .mem ( local_encoder2to3_1_data ) , .mem_inv ( local_encoder2to3_1_data_inv ) , .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_176 ( .A ( BUF_net_177 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_177 ( - .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_177 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_179 ( .A ( BUF_net_180 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_180 ( + .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_180 ) ) ; endmodule @@ -35934,10 +38289,14 @@ input [0:2] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -35948,10 +38307,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -36017,9 +38380,9 @@ sb_1__2__mux_2level_tapbuf_basis_input3_mem3_54 mux_l2_in_0_ ( .mem ( local_encoder2to3_1_data ) , .mem_inv ( local_encoder2to3_1_data_inv ) , .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_174 ( .A ( BUF_net_175 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_175 ( - .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_175 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_177 ( .A ( BUF_net_178 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_178 ( + .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_178 ) ) ; endmodule @@ -36031,10 +38394,14 @@ input [0:2] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -36045,10 +38412,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -36114,9 +38485,9 @@ sb_1__2__mux_2level_tapbuf_basis_input3_mem3_52 mux_l2_in_0_ ( .mem ( local_encoder2to3_1_data ) , .mem_inv ( local_encoder2to3_1_data_inv ) , .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_172 ( .A ( BUF_net_173 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_173 ( - .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_173 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_175 ( .A ( BUF_net_176 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_176 ( + .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_176 ) ) ; endmodule @@ -36128,10 +38499,14 @@ input [0:2] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -36142,10 +38517,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -36211,9 +38590,8 @@ sb_1__2__mux_2level_tapbuf_basis_input3_mem3_50 mux_l2_in_0_ ( .mem ( local_encoder2to3_1_data ) , .mem_inv ( local_encoder2to3_1_data_inv ) , .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_170 ( .A ( BUF_net_171 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_171 ( - .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_171 ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_174 ( + .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .X ( out[0] ) ) ; endmodule @@ -36324,9 +38702,13 @@ input [0:1] mem ; input [0:1] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -36338,10 +38720,14 @@ input [0:2] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -36352,10 +38738,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -36439,9 +38829,13 @@ input [0:1] mem ; input [0:1] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -36453,10 +38847,14 @@ input [0:2] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -36467,10 +38865,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -36542,8 +38944,9 @@ sb_1__2__mux_2level_tapbuf_basis_input2_mem2_14 mux_l1_in_1_ ( .in ( in[3:4] ) , .mem ( local_encoder2to3_0_data[0:1] ) , .mem_inv ( local_encoder2to3_0_data_inv[0:1] ) , .out ( mux_2level_tapbuf_basis_input2_mem2_0_out ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_169 ( - .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_172 ( .A ( BUF_net_173 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_173 ( + .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_173 ) ) ; endmodule @@ -36554,9 +38957,13 @@ input [0:1] mem ; input [0:1] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -36568,10 +38975,14 @@ input [0:2] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -36582,10 +38993,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -36669,9 +39084,13 @@ input [0:1] mem ; input [0:1] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -36683,10 +39102,14 @@ input [0:2] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -36697,10 +39120,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -36772,9 +39199,9 @@ sb_1__2__mux_2level_tapbuf_basis_input2_mem2_12 mux_l1_in_1_ ( .in ( in[3:4] ) , .mem ( local_encoder2to3_0_data[0:1] ) , .mem_inv ( local_encoder2to3_0_data_inv[0:1] ) , .out ( mux_2level_tapbuf_basis_input2_mem2_0_out ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_167 ( .A ( BUF_net_168 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_168 ( - .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_168 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_170 ( .A ( BUF_net_171 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_171 ( + .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_171 ) ) ; endmodule @@ -36785,9 +39212,13 @@ input [0:1] mem ; input [0:1] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -36799,10 +39230,14 @@ input [0:2] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -36813,10 +39248,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -36888,9 +39327,9 @@ sb_1__2__mux_2level_tapbuf_basis_input2_mem2_11 mux_l1_in_1_ ( .in ( in[3:4] ) , .mem ( local_encoder2to3_0_data[0:1] ) , .mem_inv ( local_encoder2to3_0_data_inv[0:1] ) , .out ( mux_2level_tapbuf_basis_input2_mem2_0_out ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_165 ( .A ( BUF_net_166 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_166 ( - .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_166 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_168 ( .A ( BUF_net_169 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_169 ( + .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_169 ) ) ; endmodule @@ -36942,12 +39381,18 @@ input [0:3] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -36958,12 +39403,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -36974,12 +39425,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -37040,7 +39497,7 @@ wire [0:0] mux_2level_tapbuf_basis_input4_mem4_2_out ; sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_4_0_ ( .A ( mux_2level_tapbuf_basis_input4_mem4_2_out[0] ) , - .X ( aps_rename_506_ ) ) ; + .X ( aps_rename_507_ ) ) ; sb_1__2__local_encoder2to4_6 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , .data ( local_encoder2to4_0_data ) , .data_inv ( local_encoder2to4_0_data_inv ) ) ; @@ -37062,9 +39519,9 @@ sb_1__2__mux_2level_tapbuf_basis_input4_mem4 mux_l2_in_0_ ( .mem ( local_encoder2to4_1_data ) , .mem_inv ( local_encoder2to4_1_data_inv ) , .out ( mux_2level_tapbuf_basis_input4_mem4_2_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_163 ( .A ( BUF_net_164 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_164 ( .A ( aps_rename_506_ ) , - .Y ( BUF_net_164 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_166 ( .A ( BUF_net_167 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_167 ( .A ( aps_rename_507_ ) , + .Y ( BUF_net_167 ) ) ; endmodule @@ -37076,12 +39533,18 @@ input [0:3] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -37092,12 +39555,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -37108,12 +39577,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -37245,9 +39720,13 @@ input [0:1] mem ; input [0:1] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -37259,12 +39738,18 @@ input [0:3] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -37275,12 +39760,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -37291,12 +39782,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -37357,7 +39854,8 @@ wire [0:0] mux_2level_tapbuf_basis_input4_mem4_1_out ; wire [0:0] mux_2level_tapbuf_basis_input4_mem4_2_out ; sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_4_0_ ( - .A ( mux_2level_tapbuf_basis_input4_mem4_2_out[0] ) , .X ( net_net_162 ) ) ; + .A ( mux_2level_tapbuf_basis_input4_mem4_2_out[0] ) , + .X ( aps_rename_506_ ) ) ; sb_1__2__local_encoder2to4_2 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , .data ( local_encoder2to4_0_data ) , .data_inv ( local_encoder2to4_0_data_inv ) ) ; @@ -37384,7 +39882,9 @@ sb_1__2__mux_2level_tapbuf_basis_input2_mem2_10 mux_l1_in_2_ ( .in ( in[8:9] ) , .mem ( local_encoder2to4_0_data[0:1] ) , .mem_inv ( local_encoder2to4_0_data_inv[0:1] ) , .out ( mux_2level_tapbuf_basis_input2_mem2_0_out ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_162 ( .A ( net_net_162 ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_164 ( .A ( BUF_net_165 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_165 ( .A ( aps_rename_506_ ) , + .Y ( BUF_net_165 ) ) ; endmodule @@ -37395,9 +39895,13 @@ input [0:1] mem ; input [0:1] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -37409,12 +39913,18 @@ input [0:3] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -37425,12 +39935,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -37441,12 +39957,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -37535,9 +40057,9 @@ sb_1__2__mux_2level_tapbuf_basis_input2_mem2_9 mux_l1_in_2_ ( .in ( in[8:9] ) , .mem ( local_encoder2to4_0_data[0:1] ) , .mem_inv ( local_encoder2to4_0_data_inv[0:1] ) , .out ( mux_2level_tapbuf_basis_input2_mem2_0_out ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_199 ( .A ( BUF_net_200 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_200 ( .A ( aps_rename_505_ ) , - .Y ( BUF_net_200 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_162 ( .A ( BUF_net_163 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_163 ( .A ( aps_rename_505_ ) , + .Y ( BUF_net_163 ) ) ; endmodule @@ -37608,10 +40130,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -37623,10 +40149,14 @@ input [0:2] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -37637,10 +40167,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -37651,10 +40185,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -37745,10 +40283,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -37760,10 +40302,14 @@ input [0:2] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -37774,10 +40320,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -37788,10 +40338,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -37869,8 +40423,9 @@ sb_1__2__mux_2level_tapbuf_basis_input3_mem3_34 mux_l2_in_0_ ( .mem ( local_encoder2to3_1_data ) , .mem_inv ( local_encoder2to3_1_data_inv ) , .out ( mux_2level_tapbuf_basis_input3_mem3_3_out ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_159 ( - .A ( mux_2level_tapbuf_basis_input3_mem3_3_out[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_158 ( .A ( BUF_net_159 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_159 ( + .A ( mux_2level_tapbuf_basis_input3_mem3_3_out[0] ) , .Y ( BUF_net_159 ) ) ; endmodule @@ -37881,10 +40436,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -37896,10 +40455,14 @@ input [0:2] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -37910,10 +40473,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -37924,10 +40491,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -37979,6 +40550,8 @@ wire [0:0] mux_2level_tapbuf_basis_input3_mem3_1_out ; wire [0:0] mux_2level_tapbuf_basis_input3_mem3_2_out ; wire [0:0] mux_2level_tapbuf_basis_input3_mem3_3_out ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( mux_2level_tapbuf_basis_input3_mem3_3_out[0] ) , .X ( out[0] ) ) ; sb_1__2__local_encoder2to3_18 local_encoder2to3_0_ ( .addr ( sram[0:1] ) , .data ( local_encoder2to3_0_data ) , .data_inv ( local_encoder2to3_0_data_inv ) ) ; @@ -38005,8 +40578,6 @@ sb_1__2__mux_2level_tapbuf_basis_input3_mem3_30 mux_l2_in_0_ ( .mem ( local_encoder2to3_1_data ) , .mem_inv ( local_encoder2to3_1_data_inv ) , .out ( mux_2level_tapbuf_basis_input3_mem3_3_out ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_158 ( - .A ( mux_2level_tapbuf_basis_input3_mem3_3_out[0] ) , .X ( out[0] ) ) ; endmodule @@ -38178,7 +40749,7 @@ input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( copt_net_216 ) , +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ropt_net_240 ) , .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; @@ -38187,34 +40758,36 @@ sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__buf_1 FTB_19__18 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1420 ( .A ( ccff_head[0] ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1419 ( .A ( ropt_net_244 ) , .X ( copt_net_211 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1421 ( .A ( copt_net_211 ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1420 ( .A ( ropt_net_241 ) , .X ( copt_net_212 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1422 ( .A ( copt_net_212 ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1421 ( .A ( copt_net_215 ) , .X ( copt_net_213 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1423 ( .A ( ropt_net_246 ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1422 ( .A ( copt_net_213 ) , .X ( copt_net_214 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1424 ( .A ( copt_net_213 ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1423 ( .A ( copt_net_211 ) , .X ( copt_net_215 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1425 ( .A ( ropt_net_241 ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1424 ( .A ( copt_net_212 ) , .X ( copt_net_216 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1446 ( .A ( copt_net_214 ) , +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1443 ( .A ( copt_net_216 ) , + .X ( ropt_net_236 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1444 ( .A ( ropt_net_236 ) , + .X ( ropt_net_237 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1445 ( .A ( ropt_net_237 ) , + .X ( ropt_net_238 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1446 ( .A ( ropt_net_238 ) , + .X ( ropt_net_239 ) ) ; +sky130_fd_sc_hd__buf_2 ropt_h_inst_1447 ( .A ( ropt_net_239 ) , .X ( ropt_net_240 ) ) ; -sky130_fd_sc_hd__buf_2 ropt_h_inst_1447 ( .A ( ropt_net_240 ) , +sky130_fd_sc_hd__buf_1 ropt_h_inst_1448 ( .A ( copt_net_214 ) , .X ( ropt_net_241 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1448 ( .A ( copt_net_215 ) , +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1449 ( .A ( ropt_net_243 ) , .X ( ropt_net_242 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1449 ( .A ( ropt_net_247 ) , +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1450 ( .A ( ccff_head[0] ) , .X ( ropt_net_243 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1450 ( .A ( ropt_net_242 ) , +sky130_fd_sc_hd__buf_1 ropt_h_inst_1451 ( .A ( ropt_net_242 ) , .X ( ropt_net_244 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1451 ( .A ( ropt_net_243 ) , - .X ( ropt_net_245 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1452 ( .A ( ropt_net_245 ) , - .X ( ropt_net_246 ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 ropt_h_inst_1453 ( .A ( ropt_net_244 ) , - .X ( ropt_net_247 ) ) ; endmodule @@ -38226,9 +40799,13 @@ input [0:1] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( p0 ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -38239,10 +40816,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -38253,10 +40834,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -38267,10 +40852,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -38361,9 +40950,13 @@ input [0:1] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( p0 ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -38374,10 +40967,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -38388,10 +40985,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -38402,10 +41003,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -38483,8 +41088,9 @@ sb_1__2__mux_2level_tapbuf_basis_input2_mem2_7 mux_l1_in_2_ ( .mem ( local_encoder2to3_0_data[0:1] ) , .mem_inv ( local_encoder2to3_0_data_inv[0:1] ) , .out ( mux_2level_tapbuf_basis_input2_mem2_0_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_157 ( - .A ( mux_2level_tapbuf_basis_input3_mem3_2_out[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_156 ( .A ( BUF_net_157 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_157 ( + .A ( mux_2level_tapbuf_basis_input3_mem3_2_out[0] ) , .Y ( BUF_net_157 ) ) ; endmodule @@ -38496,9 +41102,13 @@ input [0:1] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( p0 ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -38509,10 +41119,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -38523,10 +41137,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -38537,10 +41155,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -38618,9 +41240,9 @@ sb_1__2__mux_2level_tapbuf_basis_input2_mem2_6 mux_l1_in_2_ ( .mem ( local_encoder2to3_0_data[0:1] ) , .mem_inv ( local_encoder2to3_0_data_inv[0:1] ) , .out ( mux_2level_tapbuf_basis_input2_mem2_0_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_155 ( .A ( BUF_net_156 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_156 ( - .A ( mux_2level_tapbuf_basis_input3_mem3_2_out[0] ) , .Y ( BUF_net_156 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_154 ( .A ( BUF_net_155 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_155 ( + .A ( mux_2level_tapbuf_basis_input3_mem3_2_out[0] ) , .Y ( BUF_net_155 ) ) ; endmodule @@ -38632,9 +41254,13 @@ input [0:1] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( p0 ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -38645,10 +41271,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -38659,10 +41289,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -38673,10 +41307,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -38754,9 +41392,9 @@ sb_1__2__mux_2level_tapbuf_basis_input2_mem2_5 mux_l1_in_2_ ( .mem ( local_encoder2to3_0_data[0:1] ) , .mem_inv ( local_encoder2to3_0_data_inv[0:1] ) , .out ( mux_2level_tapbuf_basis_input2_mem2_0_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_153 ( .A ( BUF_net_154 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_154 ( - .A ( mux_2level_tapbuf_basis_input3_mem3_2_out[0] ) , .Y ( BUF_net_154 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_152 ( .A ( BUF_net_153 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_153 ( + .A ( mux_2level_tapbuf_basis_input3_mem3_2_out[0] ) , .Y ( BUF_net_153 ) ) ; endmodule @@ -38768,9 +41406,13 @@ input [0:1] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( p0 ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -38781,10 +41423,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -38795,10 +41441,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -38809,10 +41459,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -38890,9 +41544,8 @@ sb_1__2__mux_2level_tapbuf_basis_input2_mem2_4 mux_l1_in_2_ ( .mem ( local_encoder2to3_0_data[0:1] ) , .mem_inv ( local_encoder2to3_0_data_inv[0:1] ) , .out ( mux_2level_tapbuf_basis_input2_mem2_0_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_151 ( .A ( BUF_net_152 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_152 ( - .A ( mux_2level_tapbuf_basis_input3_mem3_2_out[0] ) , .Y ( BUF_net_152 ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_151 ( + .A ( mux_2level_tapbuf_basis_input3_mem3_2_out[0] ) , .X ( out[0] ) ) ; endmodule @@ -38904,9 +41557,13 @@ input [0:1] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( p0 ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -38917,10 +41574,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -38931,10 +41592,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -38945,10 +41610,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -39026,9 +41695,9 @@ sb_1__2__mux_2level_tapbuf_basis_input2_mem2_3 mux_l1_in_2_ ( .mem ( local_encoder2to3_0_data[0:1] ) , .mem_inv ( local_encoder2to3_0_data_inv[0:1] ) , .out ( mux_2level_tapbuf_basis_input2_mem2_0_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_149 ( .A ( BUF_net_150 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_150 ( - .A ( mux_2level_tapbuf_basis_input3_mem3_2_out[0] ) , .Y ( BUF_net_150 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_199 ( .A ( BUF_net_200 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_200 ( + .A ( mux_2level_tapbuf_basis_input3_mem3_2_out[0] ) , .Y ( BUF_net_200 ) ) ; endmodule @@ -39040,9 +41709,13 @@ input [0:1] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( p0 ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -39053,10 +41726,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -39067,10 +41744,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -39081,10 +41762,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -39175,9 +41860,13 @@ input [0:1] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( p0 ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -39188,10 +41877,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -39202,10 +41895,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -39216,10 +41913,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -39310,9 +42011,13 @@ input [0:1] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( p0 ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -39323,10 +42028,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -39337,10 +42046,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -39351,10 +42064,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -39406,8 +42123,6 @@ wire [0:0] mux_2level_tapbuf_basis_input3_mem3_0_out ; wire [0:0] mux_2level_tapbuf_basis_input3_mem3_1_out ; wire [0:0] mux_2level_tapbuf_basis_input3_mem3_2_out ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( mux_2level_tapbuf_basis_input3_mem3_2_out[0] ) , .X ( out[0] ) ) ; sb_1__2__local_encoder2to3_0 local_encoder2to3_0_ ( .addr ( sram[0:1] ) , .data ( local_encoder2to3_0_data ) , .data_inv ( local_encoder2to3_0_data_inv ) ) ; @@ -39434,6 +42149,9 @@ sb_1__2__mux_2level_tapbuf_basis_input2_mem2_0 mux_l1_in_2_ ( .mem ( local_encoder2to3_0_data[0:1] ) , .mem_inv ( local_encoder2to3_0_data_inv[0:1] ) , .out ( mux_2level_tapbuf_basis_input2_mem2_0_out ) , .p0 ( p0 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_149 ( .A ( BUF_net_150 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_150 ( + .A ( mux_2level_tapbuf_basis_input3_mem3_2_out[0] ) , .Y ( BUF_net_150 ) ) ; endmodule @@ -39499,6 +42217,7 @@ output pReset_E_out ; input prog_clk_0_S_in ; wire ropt_net_228 ; +wire ropt_net_227 ; wire [0:0] prog_clk ; wire prog_clk_0 ; wire [0:3] mux_2level_tapbuf_size10_0_sram ; @@ -39608,7 +42327,7 @@ sb_1__2__mux_2level_tapbuf_size7_0 mux_right_track_0 ( .sram ( mux_2level_tapbuf_size7_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 , SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) , - .out ( chanx_right_out[0] ) , .p0 ( optlc_net_204 ) ) ; + .out ( chanx_right_out[0] ) , .p0 ( optlc_net_203 ) ) ; sb_1__2__mux_2level_tapbuf_size7_1 mux_right_track_2 ( .in ( { right_bottom_grid_pin_36_[0] , right_bottom_grid_pin_39_[0] , right_bottom_grid_pin_42_[0] , chany_bottom_in[8] , @@ -39616,7 +42335,7 @@ sb_1__2__mux_2level_tapbuf_size7_1 mux_right_track_2 ( .sram ( mux_2level_tapbuf_size7_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 , SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 } ) , - .out ( chanx_right_out[1] ) , .p0 ( optlc_net_204 ) ) ; + .out ( chanx_right_out[1] ) , .p0 ( optlc_net_203 ) ) ; sb_1__2__mux_2level_tapbuf_size7_2 mux_right_track_12 ( .in ( { right_top_grid_pin_1_[0] , right_bottom_grid_pin_41_[0] , chany_bottom_in[4] , chany_bottom_in[15] , chany_bottom_in[26] , @@ -39624,7 +42343,7 @@ sb_1__2__mux_2level_tapbuf_size7_2 mux_right_track_12 ( .sram ( mux_2level_tapbuf_size7_2_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_9 , SYNOPSYS_UNCONNECTED_10 , SYNOPSYS_UNCONNECTED_11 , SYNOPSYS_UNCONNECTED_12 } ) , - .out ( chanx_right_out[6] ) , .p0 ( optlc_net_204 ) ) ; + .out ( chanx_right_out[6] ) , .p0 ( optlc_net_209 ) ) ; sb_1__2__mux_2level_tapbuf_size7_3 mux_right_track_20 ( .in ( { right_bottom_grid_pin_36_[0] , right_bottom_grid_pin_42_[0] , chany_bottom_in[3] , chany_bottom_in[14] , chany_bottom_in[25] , @@ -39648,7 +42367,7 @@ sb_1__2__mux_2level_tapbuf_size7_5 mux_left_track_1 ( .sram ( mux_2level_tapbuf_size7_5_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_21 , SYNOPSYS_UNCONNECTED_22 , SYNOPSYS_UNCONNECTED_23 , SYNOPSYS_UNCONNECTED_24 } ) , - .out ( chanx_left_out[0] ) , .p0 ( optlc_net_208 ) ) ; + .out ( chanx_left_out[0] ) , .p0 ( optlc_net_202 ) ) ; sb_1__2__mux_2level_tapbuf_size7_6 mux_left_track_13 ( .in ( { chanx_left_out[12] , chanx_left_out[27] , chany_bottom_in[4] , chany_bottom_in[15] , chany_bottom_in[26] , left_top_grid_pin_1_[0] , @@ -39656,7 +42375,7 @@ sb_1__2__mux_2level_tapbuf_size7_6 mux_left_track_13 ( .sram ( mux_2level_tapbuf_size7_6_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_25 , SYNOPSYS_UNCONNECTED_26 , SYNOPSYS_UNCONNECTED_27 , SYNOPSYS_UNCONNECTED_28 } ) , - .out ( chanx_left_out[6] ) , .p0 ( optlc_net_207 ) ) ; + .out ( chanx_left_out[6] ) , .p0 ( optlc_net_208 ) ) ; sb_1__2__mux_2level_tapbuf_size7_7 mux_left_track_21 ( .in ( { chanx_left_out[13] , chanx_left_out[28] , chany_bottom_in[5] , chany_bottom_in[16] , chany_bottom_in[27] , @@ -39664,7 +42383,7 @@ sb_1__2__mux_2level_tapbuf_size7_7 mux_left_track_21 ( .sram ( mux_2level_tapbuf_size7_7_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_29 , SYNOPSYS_UNCONNECTED_30 , SYNOPSYS_UNCONNECTED_31 , SYNOPSYS_UNCONNECTED_32 } ) , - .out ( chanx_left_out[10] ) , .p0 ( optlc_net_206 ) ) ; + .out ( chanx_left_out[10] ) , .p0 ( optlc_net_205 ) ) ; sb_1__2__mux_2level_tapbuf_size7 mux_left_track_29 ( .in ( { chanx_left_out[15] , chanx_left_out[29] , chany_bottom_in[6] , chany_bottom_in[17] , chany_bottom_in[28] , @@ -39672,7 +42391,7 @@ sb_1__2__mux_2level_tapbuf_size7 mux_left_track_29 ( .sram ( mux_2level_tapbuf_size7_8_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_33 , SYNOPSYS_UNCONNECTED_34 , SYNOPSYS_UNCONNECTED_35 , SYNOPSYS_UNCONNECTED_36 } ) , - .out ( chanx_left_out[14] ) , .p0 ( optlc_net_206 ) ) ; + .out ( chanx_left_out[14] ) , .p0 ( optlc_net_201 ) ) ; sb_1__2__mux_2level_tapbuf_size7_mem_0 mem_right_track_0 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( mux_2level_tapbuf_size7_mem_0_ccff_tail ) , @@ -39725,7 +42444,7 @@ sb_1__2__mux_2level_tapbuf_size8_0 mux_right_track_4 ( .sram ( mux_2level_tapbuf_size8_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_37 , SYNOPSYS_UNCONNECTED_38 , SYNOPSYS_UNCONNECTED_39 , SYNOPSYS_UNCONNECTED_40 } ) , - .out ( chanx_right_out[2] ) , .p0 ( optlc_net_205 ) ) ; + .out ( chanx_right_out[2] ) , .p0 ( optlc_net_209 ) ) ; sb_1__2__mux_2level_tapbuf_size8_1 mux_left_track_3 ( .in ( { chanx_left_out[7] , chanx_left_out[21] , chany_bottom_in[0] , chany_bottom_in[11] , chany_bottom_in[22] , @@ -39734,7 +42453,7 @@ sb_1__2__mux_2level_tapbuf_size8_1 mux_left_track_3 ( .sram ( mux_2level_tapbuf_size8_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_41 , SYNOPSYS_UNCONNECTED_42 , SYNOPSYS_UNCONNECTED_43 , SYNOPSYS_UNCONNECTED_44 } ) , - .out ( chanx_left_out[1] ) , .p0 ( optlc_net_209 ) ) ; + .out ( chanx_left_out[1] ) , .p0 ( optlc_net_206 ) ) ; sb_1__2__mux_2level_tapbuf_size8 mux_left_track_5 ( .in ( { chanx_left_out[8] , chanx_left_out[23] , chany_bottom_in[1] , chany_bottom_in[12] , chany_bottom_in[23] , @@ -39743,7 +42462,7 @@ sb_1__2__mux_2level_tapbuf_size8 mux_left_track_5 ( .sram ( mux_2level_tapbuf_size8_2_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_45 , SYNOPSYS_UNCONNECTED_46 , SYNOPSYS_UNCONNECTED_47 , SYNOPSYS_UNCONNECTED_48 } ) , - .out ( chanx_left_out[2] ) , .p0 ( optlc_net_209 ) ) ; + .out ( chanx_left_out[2] ) , .p0 ( optlc_net_206 ) ) ; sb_1__2__mux_2level_tapbuf_size8_mem_0 mem_right_track_4 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( mux_2level_tapbuf_size7_mem_1_ccff_tail ) , @@ -39768,7 +42487,7 @@ sb_1__2__mux_2level_tapbuf_size10_0 mux_right_track_6 ( .sram ( mux_2level_tapbuf_size10_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_49 , SYNOPSYS_UNCONNECTED_50 , SYNOPSYS_UNCONNECTED_51 , SYNOPSYS_UNCONNECTED_52 } ) , - .out ( chanx_right_out[3] ) , .p0 ( optlc_net_204 ) ) ; + .out ( chanx_right_out[3] ) , .p0 ( optlc_net_205 ) ) ; sb_1__2__mux_2level_tapbuf_size10 mux_left_track_7 ( .in ( { chanx_left_out[9] , chanx_left_out[24] , chany_bottom_in[2] , chany_bottom_in[13] , chany_bottom_in[24] , left_top_grid_pin_1_[0] , @@ -39777,7 +42496,7 @@ sb_1__2__mux_2level_tapbuf_size10 mux_left_track_7 ( .sram ( mux_2level_tapbuf_size10_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_53 , SYNOPSYS_UNCONNECTED_54 , SYNOPSYS_UNCONNECTED_55 , SYNOPSYS_UNCONNECTED_56 } ) , - .out ( chanx_left_out[3] ) , .p0 ( optlc_net_203 ) ) ; + .out ( chanx_left_out[3] ) , .p0 ( optlc_net_207 ) ) ; sb_1__2__mux_2level_tapbuf_size10_mem_0 mem_right_track_6 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( mux_2level_tapbuf_size8_mem_0_ccff_tail ) , @@ -39796,8 +42515,8 @@ sb_1__2__mux_2level_tapbuf_size9_0 mux_right_track_10 ( .sram ( mux_2level_tapbuf_size9_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_57 , SYNOPSYS_UNCONNECTED_58 , SYNOPSYS_UNCONNECTED_59 , SYNOPSYS_UNCONNECTED_60 } ) , - .out ( { aps_rename_507_ } ) , - .p0 ( optlc_net_204 ) ) ; + .out ( { aps_rename_508_ } ) , + .p0 ( optlc_net_209 ) ) ; sb_1__2__mux_2level_tapbuf_size9 mux_left_track_11 ( .in ( { chanx_left_out[11] , chanx_left_out[25] , chany_bottom_in[3] , chany_bottom_in[14] , chany_bottom_in[25] , @@ -39806,7 +42525,7 @@ sb_1__2__mux_2level_tapbuf_size9 mux_left_track_11 ( .sram ( mux_2level_tapbuf_size9_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_61 , SYNOPSYS_UNCONNECTED_62 , SYNOPSYS_UNCONNECTED_63 , SYNOPSYS_UNCONNECTED_64 } ) , - .out ( chanx_left_out[5] ) , .p0 ( optlc_net_208 ) ) ; + .out ( chanx_left_out[5] ) , .p0 ( optlc_net_206 ) ) ; sb_1__2__mux_2level_tapbuf_size9_mem_0 mem_right_track_10 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( mux_2level_tapbuf_size10_mem_0_ccff_tail ) , @@ -39823,21 +42542,21 @@ sb_1__2__mux_2level_tapbuf_size5_0 mux_right_track_36 ( .sram ( mux_2level_tapbuf_size5_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_65 , SYNOPSYS_UNCONNECTED_66 , SYNOPSYS_UNCONNECTED_67 , SYNOPSYS_UNCONNECTED_68 } ) , - .out ( chanx_right_out[18] ) , .p0 ( optlc_net_203 ) ) ; + .out ( chanx_right_out[18] ) , .p0 ( optlc_net_204 ) ) ; sb_1__2__mux_2level_tapbuf_size5_1 mux_right_track_44 ( .in ( { right_bottom_grid_pin_39_[0] , chany_bottom_in[0] , chany_bottom_in[11] , chany_bottom_in[22] , chanx_right_out[17] } ) , .sram ( mux_2level_tapbuf_size5_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_69 , SYNOPSYS_UNCONNECTED_70 , SYNOPSYS_UNCONNECTED_71 , SYNOPSYS_UNCONNECTED_72 } ) , - .out ( chanx_right_out[22] ) , .p0 ( optlc_net_203 ) ) ; + .out ( chanx_right_out[22] ) , .p0 ( optlc_net_204 ) ) ; sb_1__2__mux_2level_tapbuf_size5_2 mux_bottom_track_5 ( .in ( { chanx_left_out[8] , bottom_left_grid_pin_46_[0] , bottom_left_grid_pin_49_[0] , chanx_left_in[4] , chanx_right_out[8] } ) , .sram ( mux_2level_tapbuf_size5_2_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_73 , SYNOPSYS_UNCONNECTED_74 , SYNOPSYS_UNCONNECTED_75 , SYNOPSYS_UNCONNECTED_76 } ) , - .out ( chany_bottom_out[2] ) , .p0 ( optlc_net_202 ) ) ; + .out ( chany_bottom_out[2] ) , .p0 ( optlc_net_201 ) ) ; sb_1__2__mux_2level_tapbuf_size5_3 mux_bottom_track_11 ( .in ( { chanx_left_out[12] , bottom_left_grid_pin_46_[0] , bottom_left_grid_pin_49_[0] , chanx_right_out[12] , @@ -39845,7 +42564,7 @@ sb_1__2__mux_2level_tapbuf_size5_3 mux_bottom_track_11 ( .sram ( mux_2level_tapbuf_size5_3_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_77 , SYNOPSYS_UNCONNECTED_78 , SYNOPSYS_UNCONNECTED_79 , SYNOPSYS_UNCONNECTED_80 } ) , - .out ( chany_bottom_out[5] ) , .p0 ( optlc_net_202 ) ) ; + .out ( chany_bottom_out[5] ) , .p0 ( optlc_net_201 ) ) ; sb_1__2__mux_2level_tapbuf_size5 mux_left_track_37 ( .in ( { chanx_left_out[16] , chany_bottom_in[7] , chany_bottom_in[18] , chany_bottom_in[29] , left_bottom_grid_pin_38_[0] } ) , @@ -39884,35 +42603,35 @@ sb_1__2__mux_2level_tapbuf_size4_0 mux_right_track_52 ( .sram ( mux_2level_tapbuf_size4_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_85 , SYNOPSYS_UNCONNECTED_86 , SYNOPSYS_UNCONNECTED_87 , SYNOPSYS_UNCONNECTED_88 } ) , - .out ( chanx_right_out[26] ) , .p0 ( optlc_net_203 ) ) ; + .out ( chanx_right_out[26] ) , .p0 ( optlc_net_204 ) ) ; sb_1__2__mux_2level_tapbuf_size4_1 mux_bottom_track_13 ( .in ( { chanx_left_out[13] , bottom_left_grid_pin_44_[0] , chanx_right_out[13] , chanx_left_in[17] } ) , .sram ( mux_2level_tapbuf_size4_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_89 , SYNOPSYS_UNCONNECTED_90 , SYNOPSYS_UNCONNECTED_91 , SYNOPSYS_UNCONNECTED_92 } ) , - .out ( chany_bottom_out[6] ) , .p0 ( optlc_net_208 ) ) ; + .out ( chany_bottom_out[6] ) , .p0 ( optlc_net_207 ) ) ; sb_1__2__mux_2level_tapbuf_size4_2 mux_bottom_track_15 ( .in ( { chanx_left_out[15] , bottom_left_grid_pin_45_[0] , chanx_right_out[15] , chanx_left_in[21] } ) , .sram ( mux_2level_tapbuf_size4_2_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_93 , SYNOPSYS_UNCONNECTED_94 , SYNOPSYS_UNCONNECTED_95 , SYNOPSYS_UNCONNECTED_96 } ) , - .out ( chany_bottom_out[7] ) , .p0 ( optlc_net_210 ) ) ; + .out ( chany_bottom_out[7] ) , .p0 ( optlc_net_207 ) ) ; sb_1__2__mux_2level_tapbuf_size4_3 mux_bottom_track_17 ( .in ( { chanx_left_out[16] , bottom_left_grid_pin_46_[0] , chanx_right_out[16] , chanx_left_in[25] } ) , .sram ( mux_2level_tapbuf_size4_3_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_97 , SYNOPSYS_UNCONNECTED_98 , SYNOPSYS_UNCONNECTED_99 , SYNOPSYS_UNCONNECTED_100 } ) , - .out ( chany_bottom_out[8] ) , .p0 ( optlc_net_210 ) ) ; + .out ( chany_bottom_out[8] ) , .p0 ( optlc_net_207 ) ) ; sb_1__2__mux_2level_tapbuf_size4_4 mux_bottom_track_19 ( .in ( { chanx_left_out[17] , bottom_left_grid_pin_47_[0] , chanx_right_out[17] , chanx_left_in[29] } ) , .sram ( mux_2level_tapbuf_size4_4_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_101 , SYNOPSYS_UNCONNECTED_102 , SYNOPSYS_UNCONNECTED_103 , SYNOPSYS_UNCONNECTED_104 } ) , - .out ( chany_bottom_out[9] ) , .p0 ( optlc_net_208 ) ) ; + .out ( chany_bottom_out[9] ) , .p0 ( optlc_net_207 ) ) ; sb_1__2__mux_2level_tapbuf_size4_5 mux_bottom_track_37 ( .in ( { chanx_left_out[29] , chanx_right_in[29] , bottom_left_grid_pin_44_[0] , chanx_right_out[29] } ) , @@ -39926,14 +42645,14 @@ sb_1__2__mux_2level_tapbuf_size4_6 mux_left_track_45 ( .sram ( mux_2level_tapbuf_size4_6_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_109 , SYNOPSYS_UNCONNECTED_110 , SYNOPSYS_UNCONNECTED_111 , SYNOPSYS_UNCONNECTED_112 } ) , - .out ( chanx_left_out[22] ) , .p0 ( optlc_net_208 ) ) ; + .out ( chanx_left_out[22] ) , .p0 ( optlc_net_207 ) ) ; sb_1__2__mux_2level_tapbuf_size4 mux_left_track_53 ( .in ( { chanx_left_out[19] , chany_bottom_in[9] , chany_bottom_in[20] , left_bottom_grid_pin_40_[0] } ) , .sram ( mux_2level_tapbuf_size4_7_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_113 , SYNOPSYS_UNCONNECTED_114 , SYNOPSYS_UNCONNECTED_115 , SYNOPSYS_UNCONNECTED_116 } ) , - .out ( chanx_left_out[26] ) , .p0 ( optlc_net_202 ) ) ; + .out ( chanx_left_out[26] ) , .p0 ( optlc_net_201 ) ) ; sb_1__2__mux_2level_tapbuf_size4_mem_0 mem_right_track_52 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( mux_2level_tapbuf_size5_mem_1_ccff_tail ) , @@ -39980,7 +42699,7 @@ sb_1__2__mux_2level_tapbuf_size6_0 mux_bottom_track_1 ( .sram ( mux_2level_tapbuf_size6_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_117 , SYNOPSYS_UNCONNECTED_118 , SYNOPSYS_UNCONNECTED_119 , SYNOPSYS_UNCONNECTED_120 } ) , - .out ( chany_bottom_out[0] ) , .p0 ( optlc_net_202 ) ) ; + .out ( chany_bottom_out[0] ) , .p0 ( optlc_net_207 ) ) ; sb_1__2__mux_2level_tapbuf_size6_1 mux_bottom_track_3 ( .in ( { chanx_left_out[7] , bottom_left_grid_pin_45_[0] , bottom_left_grid_pin_48_[0] , bottom_left_grid_pin_51_[0] , @@ -39988,7 +42707,7 @@ sb_1__2__mux_2level_tapbuf_size6_1 mux_bottom_track_3 ( .sram ( mux_2level_tapbuf_size6_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_121 , SYNOPSYS_UNCONNECTED_122 , SYNOPSYS_UNCONNECTED_123 , SYNOPSYS_UNCONNECTED_124 } ) , - .out ( chany_bottom_out[1] ) , .p0 ( optlc_net_202 ) ) ; + .out ( chany_bottom_out[1] ) , .p0 ( optlc_net_201 ) ) ; sb_1__2__mux_2level_tapbuf_size6_2 mux_bottom_track_7 ( .in ( { chanx_left_out[9] , bottom_left_grid_pin_44_[0] , bottom_left_grid_pin_47_[0] , bottom_left_grid_pin_50_[0] , @@ -40030,7 +42749,7 @@ sb_1__2__mux_2level_tapbuf_size3_0 mux_bottom_track_21 ( chanx_right_out[19] } ) , .sram ( mux_2level_tapbuf_size3_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_133 , SYNOPSYS_UNCONNECTED_134 } ) , - .out ( chany_bottom_out[10] ) , .p0 ( optlc_net_202 ) ) ; + .out ( chany_bottom_out[10] ) , .p0 ( optlc_net_207 ) ) ; sb_1__2__mux_2level_tapbuf_size3_1 mux_bottom_track_23 ( .in ( { chanx_left_out[20] , bottom_left_grid_pin_49_[0] , chanx_right_out[20] } ) , @@ -40042,13 +42761,13 @@ sb_1__2__mux_2level_tapbuf_size3_2 mux_bottom_track_25 ( chanx_right_out[21] } ) , .sram ( mux_2level_tapbuf_size3_2_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_137 , SYNOPSYS_UNCONNECTED_138 } ) , - .out ( chany_bottom_out[12] ) , .p0 ( optlc_net_207 ) ) ; + .out ( chany_bottom_out[12] ) , .p0 ( optlc_net_210 ) ) ; sb_1__2__mux_2level_tapbuf_size3 mux_bottom_track_27 ( .in ( { chanx_left_out[23] , bottom_left_grid_pin_51_[0] , chanx_right_out[23] } ) , .sram ( mux_2level_tapbuf_size3_3_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_139 , SYNOPSYS_UNCONNECTED_140 } ) , - .out ( chany_bottom_out[13] ) , .p0 ( optlc_net_206 ) ) ; + .out ( chany_bottom_out[13] ) , .p0 ( optlc_net_201 ) ) ; sb_1__2__mux_2level_tapbuf_size3_mem_0 mem_bottom_track_21 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( mux_2level_tapbuf_size4_mem_4_ccff_tail ) , @@ -40073,57 +42792,57 @@ sb_1__2__mux_2level_tapbuf_size2_0 mux_bottom_track_29 ( .in ( { chanx_left_out[24] , chanx_right_out[24] } ) , .sram ( mux_2level_tapbuf_size2_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_141 , SYNOPSYS_UNCONNECTED_142 } ) , - .out ( chany_bottom_out[14] ) , .p0 ( optlc_net_207 ) ) ; + .out ( chany_bottom_out[14] ) , .p0 ( optlc_net_208 ) ) ; sb_1__2__mux_2level_tapbuf_size2_1 mux_bottom_track_31 ( .in ( { chanx_left_out[25] , chanx_right_out[25] } ) , .sram ( mux_2level_tapbuf_size2_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_143 , SYNOPSYS_UNCONNECTED_144 } ) , - .out ( chany_bottom_out[15] ) , .p0 ( optlc_net_207 ) ) ; + .out ( chany_bottom_out[15] ) , .p0 ( optlc_net_210 ) ) ; sb_1__2__mux_2level_tapbuf_size2_2 mux_bottom_track_33 ( .in ( { chanx_left_out[27] , chanx_right_out[27] } ) , .sram ( mux_2level_tapbuf_size2_2_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_145 , SYNOPSYS_UNCONNECTED_146 } ) , - .out ( chany_bottom_out[16] ) , .p0 ( optlc_net_204 ) ) ; + .out ( chany_bottom_out[16] ) , .p0 ( optlc_net_210 ) ) ; sb_1__2__mux_2level_tapbuf_size2_3 mux_bottom_track_35 ( .in ( { chanx_left_out[28] , chanx_right_out[28] } ) , .sram ( mux_2level_tapbuf_size2_3_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_147 , SYNOPSYS_UNCONNECTED_148 } ) , - .out ( chany_bottom_out[17] ) , .p0 ( optlc_net_207 ) ) ; + .out ( chany_bottom_out[17] ) , .p0 ( optlc_net_202 ) ) ; sb_1__2__mux_2level_tapbuf_size2_4 mux_bottom_track_39 ( .in ( { chanx_right_in[25] , bottom_left_grid_pin_45_[0] } ) , .sram ( mux_2level_tapbuf_size2_4_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_149 , SYNOPSYS_UNCONNECTED_150 } ) , - .out ( chany_bottom_out[19] ) , .p0 ( optlc_net_205 ) ) ; + .out ( chany_bottom_out[19] ) , .p0 ( optlc_net_203 ) ) ; sb_1__2__mux_2level_tapbuf_size2_5 mux_bottom_track_41 ( .in ( { chanx_right_in[21] , bottom_left_grid_pin_46_[0] } ) , .sram ( mux_2level_tapbuf_size2_5_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_151 , SYNOPSYS_UNCONNECTED_152 } ) , - .out ( chany_bottom_out[20] ) , .p0 ( optlc_net_206 ) ) ; + .out ( chany_bottom_out[20] ) , .p0 ( optlc_net_203 ) ) ; sb_1__2__mux_2level_tapbuf_size2_6 mux_bottom_track_43 ( .in ( { chanx_right_in[17] , bottom_left_grid_pin_47_[0] } ) , .sram ( mux_2level_tapbuf_size2_6_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_153 , SYNOPSYS_UNCONNECTED_154 } ) , - .out ( chany_bottom_out[21] ) , .p0 ( optlc_net_206 ) ) ; + .out ( chany_bottom_out[21] ) , .p0 ( optlc_net_202 ) ) ; sb_1__2__mux_2level_tapbuf_size2_7 mux_bottom_track_45 ( .in ( { chanx_right_in[13] , bottom_left_grid_pin_48_[0] } ) , .sram ( mux_2level_tapbuf_size2_7_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_155 , SYNOPSYS_UNCONNECTED_156 } ) , - .out ( chany_bottom_out[22] ) , .p0 ( optlc_net_201 ) ) ; + .out ( chany_bottom_out[22] ) , .p0 ( optlc_net_202 ) ) ; sb_1__2__mux_2level_tapbuf_size2_8 mux_bottom_track_47 ( .in ( { chanx_right_in[9] , bottom_left_grid_pin_49_[0] } ) , .sram ( mux_2level_tapbuf_size2_8_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_157 , SYNOPSYS_UNCONNECTED_158 } ) , - .out ( chany_bottom_out[23] ) , .p0 ( optlc_net_201 ) ) ; + .out ( chany_bottom_out[23] ) , .p0 ( optlc_net_202 ) ) ; sb_1__2__mux_2level_tapbuf_size2_9 mux_bottom_track_49 ( .in ( { chanx_right_in[5] , bottom_left_grid_pin_50_[0] } ) , .sram ( mux_2level_tapbuf_size2_9_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_159 , SYNOPSYS_UNCONNECTED_160 } ) , - .out ( chany_bottom_out[24] ) , .p0 ( optlc_net_206 ) ) ; + .out ( chany_bottom_out[24] ) , .p0 ( optlc_net_202 ) ) ; sb_1__2__mux_2level_tapbuf_size2 mux_bottom_track_51 ( .in ( { chanx_right_in[4] , bottom_left_grid_pin_51_[0] } ) , .sram ( mux_2level_tapbuf_size2_10_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_161 , SYNOPSYS_UNCONNECTED_162 } ) , - .out ( chany_bottom_out[25] ) , .p0 ( optlc_net_201 ) ) ; + .out ( chany_bottom_out[25] ) , .p0 ( optlc_net_210 ) ) ; sb_1__2__mux_2level_tapbuf_size2_mem_0 mem_bottom_track_29 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( mux_2level_tapbuf_size3_mem_3_ccff_tail ) , @@ -40180,18 +42899,18 @@ sb_1__2__mux_2level_tapbuf_size2_mem mem_bottom_track_51 ( .ccff_tail ( mux_2level_tapbuf_size2_mem_10_ccff_tail ) , .mem_out ( mux_2level_tapbuf_size2_10_sram ) ) ; sky130_fd_sc_hd__buf_8 pReset_FTB00 ( .A ( pReset_E_in ) , .X ( pReset[0] ) ) ; -sky130_fd_sc_hd__bufbuf_16 pReset_W_FTB01 ( .A ( pReset_E_in ) , - .X ( pReset_W_out ) ) ; +sky130_fd_sc_hd__buf_1 pReset_W_FTB01 ( .A ( pReset_E_in ) , + .X ( aps_rename_509_ ) ) ; sky130_fd_sc_hd__buf_1 pReset_E_FTB01 ( .A ( pReset_E_in ) , - .X ( net_net_198 ) ) ; + .X ( aps_rename_510_ ) ) ; sky130_fd_sc_hd__buf_1 prog_clk_0_FTB00 ( .A ( prog_clk_0_S_in ) , .X ( prog_clk[0] ) ) ; -sky130_fd_sc_hd__buf_8 FTB_107__106 ( .A ( chanx_right_in[0] ) , - .X ( chany_bottom_out[28] ) ) ; +sky130_fd_sc_hd__buf_6 FTB_107__106 ( .A ( chanx_right_in[0] ) , + .X ( ropt_net_228 ) ) ; sky130_fd_sc_hd__buf_8 FTB_108__107 ( .A ( chanx_right_in[1] ) , .X ( chany_bottom_out[27] ) ) ; sky130_fd_sc_hd__buf_6 FTB_109__108 ( .A ( chanx_right_in[2] ) , - .X ( ropt_net_228 ) ) ; + .X ( ropt_net_227 ) ) ; sky130_fd_sc_hd__buf_8 FTB_110__109 ( .A ( chanx_right_in[3] ) , .X ( chanx_left_out[4] ) ) ; sky130_fd_sc_hd__buf_8 FTB_111__110 ( .A ( chanx_right_in[6] ) , @@ -40271,8 +42990,9 @@ sky130_fd_sc_hd__buf_8 FTB_147__146 ( .A ( chanx_left_in[27] ) , sky130_fd_sc_hd__buf_8 FTB_148__147 ( .A ( chanx_left_in[28] ) , .X ( chanx_right_out[29] ) ) ; sky130_fd_sc_hd__buf_8 FTB_149__148 ( .A ( SC_IN_BOT ) , .X ( SC_OUT_BOT ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_198 ( .A ( net_net_198 ) , - .X ( pReset_E_out ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_197 ( .A ( BUF_net_198 ) , .Y ( pReset_W_out ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_198 ( .A ( aps_rename_509_ ) , + .Y ( BUF_net_198 ) ) ; sky130_fd_sc_hd__conb_1 optlc_203 ( .LO ( SYNOPSYS_UNCONNECTED_163 ) , .HI ( optlc_net_201 ) ) ; sky130_fd_sc_hd__conb_1 optlc_205 ( .LO ( SYNOPSYS_UNCONNECTED_164 ) , @@ -40283,20 +43003,24 @@ sky130_fd_sc_hd__conb_1 optlc_211 ( .LO ( SYNOPSYS_UNCONNECTED_166 ) , .HI ( optlc_net_204 ) ) ; sky130_fd_sc_hd__conb_1 optlc_213 ( .LO ( SYNOPSYS_UNCONNECTED_167 ) , .HI ( optlc_net_205 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_217 ( .LO ( SYNOPSYS_UNCONNECTED_168 ) , +sky130_fd_sc_hd__conb_1 optlc_215 ( .LO ( SYNOPSYS_UNCONNECTED_168 ) , .HI ( optlc_net_206 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_219 ( .LO ( SYNOPSYS_UNCONNECTED_169 ) , +sky130_fd_sc_hd__conb_1 optlc_218 ( .LO ( SYNOPSYS_UNCONNECTED_169 ) , .HI ( optlc_net_207 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_223 ( .LO ( SYNOPSYS_UNCONNECTED_170 ) , +sky130_fd_sc_hd__conb_1 optlc_220 ( .LO ( SYNOPSYS_UNCONNECTED_170 ) , .HI ( optlc_net_208 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_225 ( .LO ( SYNOPSYS_UNCONNECTED_171 ) , +sky130_fd_sc_hd__conb_1 optlc_223 ( .LO ( SYNOPSYS_UNCONNECTED_171 ) , .HI ( optlc_net_209 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_227 ( .LO ( SYNOPSYS_UNCONNECTED_172 ) , +sky130_fd_sc_hd__conb_1 optlc_225 ( .LO ( SYNOPSYS_UNCONNECTED_172 ) , .HI ( optlc_net_210 ) ) ; -sky130_fd_sc_hd__buf_6 ZBUF_6_f_inst_228 ( .A ( aps_rename_507_ ) , +sky130_fd_sc_hd__buf_6 ZBUF_6_f_inst_226 ( .A ( aps_rename_508_ ) , .X ( chanx_right_out[5] ) ) ; -sky130_fd_sc_hd__buf_8 ropt_mt_inst_1437 ( .A ( ropt_net_228 ) , +sky130_fd_sc_hd__buf_6 ZBUF_6_f_inst_227 ( .A ( aps_rename_510_ ) , + .X ( pReset_E_out ) ) ; +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1435 ( .A ( ropt_net_227 ) , .X ( chany_bottom_out[26] ) ) ; +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1436 ( .A ( ropt_net_228 ) , + .X ( chany_bottom_out[28] ) ) ; endmodule @@ -40308,8 +43032,6 @@ input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -wire copt_net_208 ; - sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , @@ -40317,13 +43039,8 @@ sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( copt_net_208 ) ) ; -sky130_fd_sc_hd__bufbuf_8 FTB_68__67 ( .A ( copt_net_209 ) , - .X ( ccff_tail[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1418 ( .A ( copt_net_208 ) , - .X ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1419 ( .A ( mem_out[3] ) , - .X ( copt_net_209 ) ) ; + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_6 FTB_68__67 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -40555,10 +43272,14 @@ input [0:2] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -40569,10 +43290,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -40583,10 +43308,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -40637,6 +43366,8 @@ wire [0:0] mux_2level_tapbuf_basis_input3_mem3_0_out ; wire [0:0] mux_2level_tapbuf_basis_input3_mem3_1_out ; wire [0:0] mux_2level_tapbuf_basis_input3_mem3_2_out ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( mux_2level_tapbuf_basis_input3_mem3_2_out[0] ) , .X ( out[0] ) ) ; sb_1__1__local_encoder2to3_22 local_encoder2to3_0_ ( .addr ( sram[0:1] ) , .data ( local_encoder2to3_0_data ) , .data_inv ( local_encoder2to3_0_data_inv ) ) ; @@ -40658,8 +43389,6 @@ sb_1__1__mux_2level_tapbuf_basis_input3_mem3 mux_l2_in_0_ ( .mem ( local_encoder2to3_1_data ) , .mem_inv ( local_encoder2to3_1_data_inv ) , .out ( mux_2level_tapbuf_basis_input3_mem3_2_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_190 ( - .A ( mux_2level_tapbuf_basis_input3_mem3_2_out[0] ) , .X ( out[0] ) ) ; endmodule @@ -40671,10 +43400,14 @@ input [0:2] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -40685,10 +43418,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -40699,10 +43436,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -40774,9 +43515,9 @@ sb_1__1__mux_2level_tapbuf_basis_input3_mem3_40 mux_l2_in_0_ ( .mem ( local_encoder2to3_1_data ) , .mem_inv ( local_encoder2to3_1_data_inv ) , .out ( mux_2level_tapbuf_basis_input3_mem3_2_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_188 ( .A ( BUF_net_189 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_189 ( - .A ( mux_2level_tapbuf_basis_input3_mem3_2_out[0] ) , .Y ( BUF_net_189 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_170 ( .A ( BUF_net_171 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_171 ( + .A ( mux_2level_tapbuf_basis_input3_mem3_2_out[0] ) , .Y ( BUF_net_171 ) ) ; endmodule @@ -40788,10 +43529,14 @@ input [0:2] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -40802,10 +43547,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -40816,10 +43565,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -40848,7 +43601,7 @@ sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ; sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ; sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) , .Y ( data_inv[1] ) ) ; -sky130_fd_sc_hd__inv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ; +sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ; sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) , .Y ( data[0] ) ) ; sky130_fd_sc_hd__buf_1 FTB_51__50 ( .A ( addr[1] ) , .X ( data[2] ) ) ; @@ -40891,9 +43644,9 @@ sb_1__1__mux_2level_tapbuf_basis_input3_mem3_37 mux_l2_in_0_ ( .mem ( local_encoder2to3_1_data ) , .mem_inv ( local_encoder2to3_1_data_inv ) , .out ( mux_2level_tapbuf_basis_input3_mem3_2_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_186 ( .A ( BUF_net_187 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_187 ( - .A ( mux_2level_tapbuf_basis_input3_mem3_2_out[0] ) , .Y ( BUF_net_187 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_164 ( .A ( BUF_net_165 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_165 ( + .A ( mux_2level_tapbuf_basis_input3_mem3_2_out[0] ) , .Y ( BUF_net_165 ) ) ; endmodule @@ -40905,10 +43658,14 @@ input [0:2] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -40919,10 +43676,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -40933,10 +43694,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -40987,6 +43752,8 @@ wire [0:0] mux_2level_tapbuf_basis_input3_mem3_0_out ; wire [0:0] mux_2level_tapbuf_basis_input3_mem3_1_out ; wire [0:0] mux_2level_tapbuf_basis_input3_mem3_2_out ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( mux_2level_tapbuf_basis_input3_mem3_2_out[0] ) , .X ( out[0] ) ) ; sb_1__1__local_encoder2to3_16 local_encoder2to3_0_ ( .addr ( sram[0:1] ) , .data ( local_encoder2to3_0_data ) , .data_inv ( local_encoder2to3_0_data_inv ) ) ; @@ -41008,9 +43775,6 @@ sb_1__1__mux_2level_tapbuf_basis_input3_mem3_34 mux_l2_in_0_ ( .mem ( local_encoder2to3_1_data ) , .mem_inv ( local_encoder2to3_1_data_inv ) , .out ( mux_2level_tapbuf_basis_input3_mem3_2_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_184 ( .A ( BUF_net_185 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_185 ( - .A ( mux_2level_tapbuf_basis_input3_mem3_2_out[0] ) , .Y ( BUF_net_185 ) ) ; endmodule @@ -41022,10 +43786,14 @@ input [0:2] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -41036,10 +43804,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -41050,10 +43822,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -41138,10 +43914,14 @@ input [0:2] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -41152,10 +43932,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -41166,10 +43950,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -41220,6 +44008,8 @@ wire [0:0] mux_2level_tapbuf_basis_input3_mem3_0_out ; wire [0:0] mux_2level_tapbuf_basis_input3_mem3_1_out ; wire [0:0] mux_2level_tapbuf_basis_input3_mem3_2_out ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( mux_2level_tapbuf_basis_input3_mem3_2_out[0] ) , .X ( out[0] ) ) ; sb_1__1__local_encoder2to3_12 local_encoder2to3_0_ ( .addr ( sram[0:1] ) , .data ( local_encoder2to3_0_data ) , .data_inv ( local_encoder2to3_0_data_inv ) ) ; @@ -41241,9 +44031,6 @@ sb_1__1__mux_2level_tapbuf_basis_input3_mem3_28 mux_l2_in_0_ ( .mem ( local_encoder2to3_1_data ) , .mem_inv ( local_encoder2to3_1_data_inv ) , .out ( mux_2level_tapbuf_basis_input3_mem3_2_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_182 ( .A ( BUF_net_183 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_183 ( - .A ( mux_2level_tapbuf_basis_input3_mem3_2_out[0] ) , .Y ( BUF_net_183 ) ) ; endmodule @@ -41255,10 +44042,14 @@ input [0:2] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -41269,10 +44060,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -41283,10 +44078,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -41358,9 +44157,8 @@ sb_1__1__mux_2level_tapbuf_basis_input3_mem3_25 mux_l2_in_0_ ( .mem ( local_encoder2to3_1_data ) , .mem_inv ( local_encoder2to3_1_data_inv ) , .out ( mux_2level_tapbuf_basis_input3_mem3_2_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_180 ( .A ( BUF_net_181 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_181 ( - .A ( mux_2level_tapbuf_basis_input3_mem3_2_out[0] ) , .Y ( BUF_net_181 ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_163 ( + .A ( mux_2level_tapbuf_basis_input3_mem3_2_out[0] ) , .X ( out[0] ) ) ; endmodule @@ -41372,10 +44170,14 @@ input [0:2] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -41386,10 +44188,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -41400,10 +44206,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -41475,9 +44285,8 @@ sb_1__1__mux_2level_tapbuf_basis_input3_mem3_22 mux_l2_in_0_ ( .mem ( local_encoder2to3_1_data ) , .mem_inv ( local_encoder2to3_1_data_inv ) , .out ( mux_2level_tapbuf_basis_input3_mem3_2_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_178 ( .A ( BUF_net_179 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_179 ( - .A ( mux_2level_tapbuf_basis_input3_mem3_2_out[0] ) , .Y ( BUF_net_179 ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_162 ( + .A ( mux_2level_tapbuf_basis_input3_mem3_2_out[0] ) , .X ( out[0] ) ) ; endmodule @@ -41489,10 +44298,14 @@ input [0:2] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -41503,10 +44316,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -41517,10 +44334,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -41571,6 +44392,8 @@ wire [0:0] mux_2level_tapbuf_basis_input3_mem3_0_out ; wire [0:0] mux_2level_tapbuf_basis_input3_mem3_1_out ; wire [0:0] mux_2level_tapbuf_basis_input3_mem3_2_out ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( mux_2level_tapbuf_basis_input3_mem3_2_out[0] ) , .X ( out[0] ) ) ; sb_1__1__local_encoder2to3_6 local_encoder2to3_0_ ( .addr ( sram[0:1] ) , .data ( local_encoder2to3_0_data ) , .data_inv ( local_encoder2to3_0_data_inv ) ) ; @@ -41592,9 +44415,6 @@ sb_1__1__mux_2level_tapbuf_basis_input3_mem3_19 mux_l2_in_0_ ( .mem ( local_encoder2to3_1_data ) , .mem_inv ( local_encoder2to3_1_data_inv ) , .out ( mux_2level_tapbuf_basis_input3_mem3_2_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_176 ( .A ( BUF_net_177 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_177 ( - .A ( mux_2level_tapbuf_basis_input3_mem3_2_out[0] ) , .Y ( BUF_net_177 ) ) ; endmodule @@ -41606,10 +44426,14 @@ input [0:2] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -41620,10 +44444,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -41634,10 +44462,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -41688,6 +44520,8 @@ wire [0:0] mux_2level_tapbuf_basis_input3_mem3_0_out ; wire [0:0] mux_2level_tapbuf_basis_input3_mem3_1_out ; wire [0:0] mux_2level_tapbuf_basis_input3_mem3_2_out ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( mux_2level_tapbuf_basis_input3_mem3_2_out[0] ) , .X ( out[0] ) ) ; sb_1__1__local_encoder2to3_4 local_encoder2to3_0_ ( .addr ( sram[0:1] ) , .data ( local_encoder2to3_0_data ) , .data_inv ( local_encoder2to3_0_data_inv ) ) ; @@ -41709,9 +44543,6 @@ sb_1__1__mux_2level_tapbuf_basis_input3_mem3_16 mux_l2_in_0_ ( .mem ( local_encoder2to3_1_data ) , .mem_inv ( local_encoder2to3_1_data_inv ) , .out ( mux_2level_tapbuf_basis_input3_mem3_2_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_174 ( .A ( BUF_net_175 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_175 ( - .A ( mux_2level_tapbuf_basis_input3_mem3_2_out[0] ) , .Y ( BUF_net_175 ) ) ; endmodule @@ -41723,10 +44554,14 @@ input [0:2] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -41737,10 +44572,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -41751,10 +44590,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -41805,6 +44648,8 @@ wire [0:0] mux_2level_tapbuf_basis_input3_mem3_0_out ; wire [0:0] mux_2level_tapbuf_basis_input3_mem3_1_out ; wire [0:0] mux_2level_tapbuf_basis_input3_mem3_2_out ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( mux_2level_tapbuf_basis_input3_mem3_2_out[0] ) , .X ( out[0] ) ) ; sb_1__1__local_encoder2to3_2 local_encoder2to3_0_ ( .addr ( sram[0:1] ) , .data ( local_encoder2to3_0_data ) , .data_inv ( local_encoder2to3_0_data_inv ) ) ; @@ -41826,9 +44671,6 @@ sb_1__1__mux_2level_tapbuf_basis_input3_mem3_13 mux_l2_in_0_ ( .mem ( local_encoder2to3_1_data ) , .mem_inv ( local_encoder2to3_1_data_inv ) , .out ( mux_2level_tapbuf_basis_input3_mem3_2_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_195 ( .A ( BUF_net_196 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_196 ( - .A ( mux_2level_tapbuf_basis_input3_mem3_2_out[0] ) , .Y ( BUF_net_196 ) ) ; endmodule @@ -41840,10 +44682,14 @@ input [0:2] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -41854,10 +44700,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -41868,10 +44718,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -42036,12 +44890,18 @@ input [0:3] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -42052,12 +44912,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -42068,12 +44934,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -42132,8 +45004,9 @@ wire [0:0] mux_2level_tapbuf_basis_input4_mem4_0_out ; wire [0:0] mux_2level_tapbuf_basis_input4_mem4_1_out ; wire [0:0] mux_2level_tapbuf_basis_input4_mem4_2_out ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( mux_2level_tapbuf_basis_input4_mem4_2_out[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_4_0_ ( + .A ( mux_2level_tapbuf_basis_input4_mem4_2_out[0] ) , + .X ( aps_rename_513_ ) ) ; sb_1__1__local_encoder2to4_62 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , .data ( local_encoder2to4_0_data ) , .data_inv ( local_encoder2to4_0_data_inv ) ) ; @@ -42155,6 +45028,9 @@ sb_1__1__mux_2level_tapbuf_basis_input4_mem4 mux_l2_in_0_ ( .mem ( local_encoder2to4_1_data ) , .mem_inv ( local_encoder2to4_1_data_inv ) , .out ( mux_2level_tapbuf_basis_input4_mem4_2_out ) , .p0 ( p0 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_160 ( .A ( BUF_net_161 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_161 ( .A ( aps_rename_513_ ) , + .Y ( BUF_net_161 ) ) ; endmodule @@ -42166,12 +45042,18 @@ input [0:3] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -42182,12 +45064,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -42198,12 +45086,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -42264,7 +45158,7 @@ wire [0:0] mux_2level_tapbuf_basis_input4_mem4_2_out ; sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_4_0_ ( .A ( mux_2level_tapbuf_basis_input4_mem4_2_out[0] ) , - .X ( aps_rename_520_ ) ) ; + .X ( aps_rename_512_ ) ) ; sb_1__1__local_encoder2to4_60 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , .data ( local_encoder2to4_0_data ) , .data_inv ( local_encoder2to4_0_data_inv ) ) ; @@ -42286,9 +45180,9 @@ sb_1__1__mux_2level_tapbuf_basis_input4_mem4_100 mux_l2_in_0_ ( .mem ( local_encoder2to4_1_data ) , .mem_inv ( local_encoder2to4_1_data_inv ) , .out ( mux_2level_tapbuf_basis_input4_mem4_2_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_172 ( .A ( BUF_net_173 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_173 ( .A ( aps_rename_520_ ) , - .Y ( BUF_net_173 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_158 ( .A ( BUF_net_159 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_159 ( .A ( aps_rename_512_ ) , + .Y ( BUF_net_159 ) ) ; endmodule @@ -42300,12 +45194,18 @@ input [0:3] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -42316,12 +45216,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -42332,12 +45238,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -42396,9 +45308,8 @@ wire [0:0] mux_2level_tapbuf_basis_input4_mem4_0_out ; wire [0:0] mux_2level_tapbuf_basis_input4_mem4_1_out ; wire [0:0] mux_2level_tapbuf_basis_input4_mem4_2_out ; -sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_4_0_ ( - .A ( mux_2level_tapbuf_basis_input4_mem4_2_out[0] ) , - .X ( aps_rename_519_ ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( mux_2level_tapbuf_basis_input4_mem4_2_out[0] ) , .X ( out[0] ) ) ; sb_1__1__local_encoder2to4_58 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , .data ( local_encoder2to4_0_data ) , .data_inv ( local_encoder2to4_0_data_inv ) ) ; @@ -42420,9 +45331,6 @@ sb_1__1__mux_2level_tapbuf_basis_input4_mem4_97 mux_l2_in_0_ ( .mem ( local_encoder2to4_1_data ) , .mem_inv ( local_encoder2to4_1_data_inv ) , .out ( mux_2level_tapbuf_basis_input4_mem4_2_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_170 ( .A ( BUF_net_171 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_171 ( .A ( aps_rename_519_ ) , - .Y ( BUF_net_171 ) ) ; endmodule @@ -42434,12 +45342,18 @@ input [0:3] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -42450,12 +45364,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -42466,12 +45386,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -42532,7 +45458,7 @@ wire [0:0] mux_2level_tapbuf_basis_input4_mem4_2_out ; sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_4_0_ ( .A ( mux_2level_tapbuf_basis_input4_mem4_2_out[0] ) , - .X ( aps_rename_518_ ) ) ; + .X ( aps_rename_511_ ) ) ; sb_1__1__local_encoder2to4_56 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , .data ( local_encoder2to4_0_data ) , .data_inv ( local_encoder2to4_0_data_inv ) ) ; @@ -42554,9 +45480,9 @@ sb_1__1__mux_2level_tapbuf_basis_input4_mem4_94 mux_l2_in_0_ ( .mem ( local_encoder2to4_1_data ) , .mem_inv ( local_encoder2to4_1_data_inv ) , .out ( mux_2level_tapbuf_basis_input4_mem4_2_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_168 ( .A ( BUF_net_169 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_169 ( .A ( aps_rename_518_ ) , - .Y ( BUF_net_169 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_156 ( .A ( BUF_net_157 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_157 ( .A ( aps_rename_511_ ) , + .Y ( BUF_net_157 ) ) ; endmodule @@ -42728,12 +45654,18 @@ input [0:3] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -42744,12 +45676,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -42760,12 +45698,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -42776,12 +45720,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -42841,9 +45791,8 @@ wire [0:0] mux_2level_tapbuf_basis_input4_mem4_1_out ; wire [0:0] mux_2level_tapbuf_basis_input4_mem4_2_out ; wire [0:0] mux_2level_tapbuf_basis_input4_mem4_3_out ; -sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_4_0_ ( - .A ( mux_2level_tapbuf_basis_input4_mem4_3_out[0] ) , - .X ( aps_rename_517_ ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( mux_2level_tapbuf_basis_input4_mem4_3_out[0] ) , .X ( out[0] ) ) ; sb_1__1__local_encoder2to4_54 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , .data ( local_encoder2to4_0_data ) , .data_inv ( local_encoder2to4_0_data_inv ) ) ; @@ -42870,9 +45819,6 @@ sb_1__1__mux_2level_tapbuf_basis_input4_mem4_91 mux_l2_in_0_ ( .mem ( local_encoder2to4_1_data ) , .mem_inv ( local_encoder2to4_1_data_inv ) , .out ( mux_2level_tapbuf_basis_input4_mem4_3_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_166 ( .A ( BUF_net_167 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_167 ( .A ( aps_rename_517_ ) , - .Y ( BUF_net_167 ) ) ; endmodule @@ -42884,12 +45830,18 @@ input [0:3] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -42900,12 +45852,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -42916,12 +45874,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -42932,12 +45896,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -43036,12 +46006,18 @@ input [0:3] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -43052,12 +46028,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -43068,12 +46050,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -43084,12 +46072,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -43149,7 +46143,7 @@ wire [0:0] mux_2level_tapbuf_basis_input4_mem4_1_out ; wire [0:0] mux_2level_tapbuf_basis_input4_mem4_2_out ; wire [0:0] mux_2level_tapbuf_basis_input4_mem4_3_out ; -sky130_fd_sc_hd__bufbuf_16 sky130_fd_sc_hd__buf_4_0_ ( +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( mux_2level_tapbuf_basis_input4_mem4_3_out[0] ) , .X ( out[0] ) ) ; sb_1__1__local_encoder2to4_50 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , .data ( local_encoder2to4_0_data ) , @@ -43188,12 +46182,18 @@ input [0:3] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -43204,12 +46204,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -43220,12 +46226,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -43236,12 +46248,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -43340,12 +46358,18 @@ input [0:3] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -43356,12 +46380,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -43372,12 +46402,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -43388,12 +46424,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -43455,7 +46497,7 @@ wire [0:0] mux_2level_tapbuf_basis_input4_mem4_3_out ; sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_4_0_ ( .A ( mux_2level_tapbuf_basis_input4_mem4_3_out[0] ) , - .X ( aps_rename_516_ ) ) ; + .X ( aps_rename_510_ ) ) ; sb_1__1__local_encoder2to4_46 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , .data ( local_encoder2to4_0_data ) , .data_inv ( local_encoder2to4_0_data_inv ) ) ; @@ -43482,9 +46524,9 @@ sb_1__1__mux_2level_tapbuf_basis_input4_mem4_75 mux_l2_in_0_ ( .mem ( local_encoder2to4_1_data ) , .mem_inv ( local_encoder2to4_1_data_inv ) , .out ( mux_2level_tapbuf_basis_input4_mem4_3_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_164 ( .A ( BUF_net_165 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_165 ( .A ( aps_rename_516_ ) , - .Y ( BUF_net_165 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_154 ( .A ( BUF_net_155 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_155 ( .A ( aps_rename_510_ ) , + .Y ( BUF_net_155 ) ) ; endmodule @@ -43496,12 +46538,18 @@ input [0:3] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -43512,12 +46560,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -43528,12 +46582,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -43544,12 +46604,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -43609,7 +46675,7 @@ wire [0:0] mux_2level_tapbuf_basis_input4_mem4_1_out ; wire [0:0] mux_2level_tapbuf_basis_input4_mem4_2_out ; wire [0:0] mux_2level_tapbuf_basis_input4_mem4_3_out ; -sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_4_0_ ( +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( mux_2level_tapbuf_basis_input4_mem4_3_out[0] ) , .X ( out[0] ) ) ; sb_1__1__local_encoder2to4_44 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , .data ( local_encoder2to4_0_data ) , @@ -43648,12 +46714,18 @@ input [0:3] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -43664,12 +46736,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -43680,12 +46758,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -43696,12 +46780,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -43761,9 +46851,8 @@ wire [0:0] mux_2level_tapbuf_basis_input4_mem4_1_out ; wire [0:0] mux_2level_tapbuf_basis_input4_mem4_2_out ; wire [0:0] mux_2level_tapbuf_basis_input4_mem4_3_out ; -sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_4_0_ ( - .A ( mux_2level_tapbuf_basis_input4_mem4_3_out[0] ) , - .X ( aps_rename_515_ ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( mux_2level_tapbuf_basis_input4_mem4_3_out[0] ) , .X ( out[0] ) ) ; sb_1__1__local_encoder2to4_42 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , .data ( local_encoder2to4_0_data ) , .data_inv ( local_encoder2to4_0_data_inv ) ) ; @@ -43790,9 +46879,6 @@ sb_1__1__mux_2level_tapbuf_basis_input4_mem4_67 mux_l2_in_0_ ( .mem ( local_encoder2to4_1_data ) , .mem_inv ( local_encoder2to4_1_data_inv ) , .out ( mux_2level_tapbuf_basis_input4_mem4_3_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_162 ( .A ( BUF_net_163 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_163 ( .A ( aps_rename_515_ ) , - .Y ( BUF_net_163 ) ) ; endmodule @@ -43804,12 +46890,18 @@ input [0:3] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -43820,12 +46912,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -43836,12 +46934,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -43852,12 +46956,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -43917,9 +47027,8 @@ wire [0:0] mux_2level_tapbuf_basis_input4_mem4_1_out ; wire [0:0] mux_2level_tapbuf_basis_input4_mem4_2_out ; wire [0:0] mux_2level_tapbuf_basis_input4_mem4_3_out ; -sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_4_0_ ( - .A ( mux_2level_tapbuf_basis_input4_mem4_3_out[0] ) , - .X ( aps_rename_514_ ) ) ; +sky130_fd_sc_hd__bufbuf_16 sky130_fd_sc_hd__buf_4_0_ ( + .A ( mux_2level_tapbuf_basis_input4_mem4_3_out[0] ) , .X ( out[0] ) ) ; sb_1__1__local_encoder2to4_40 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , .data ( local_encoder2to4_0_data ) , .data_inv ( local_encoder2to4_0_data_inv ) ) ; @@ -43946,9 +47055,6 @@ sb_1__1__mux_2level_tapbuf_basis_input4_mem4_63 mux_l2_in_0_ ( .mem ( local_encoder2to4_1_data ) , .mem_inv ( local_encoder2to4_1_data_inv ) , .out ( mux_2level_tapbuf_basis_input4_mem4_3_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_160 ( .A ( BUF_net_161 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_161 ( .A ( aps_rename_514_ ) , - .Y ( BUF_net_161 ) ) ; endmodule @@ -44199,9 +47305,13 @@ input [0:1] mem ; input [0:1] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -44213,12 +47323,18 @@ input [0:3] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -44229,12 +47345,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -44245,12 +47367,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -44348,9 +47476,13 @@ input [0:1] mem ; input [0:1] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -44362,12 +47494,18 @@ input [0:3] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -44378,12 +47516,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -44394,12 +47538,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -44461,8 +47611,7 @@ wire [0:0] mux_2level_tapbuf_basis_input4_mem4_1_out ; wire [0:0] mux_2level_tapbuf_basis_input4_mem4_2_out ; sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_4_0_ ( - .A ( mux_2level_tapbuf_basis_input4_mem4_2_out[0] ) , - .X ( aps_rename_513_ ) ) ; + .A ( mux_2level_tapbuf_basis_input4_mem4_2_out[0] ) , .X ( net_net_153 ) ) ; sb_1__1__local_encoder2to4_36 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , .data ( local_encoder2to4_0_data ) , .data_inv ( local_encoder2to4_0_data_inv ) ) ; @@ -44489,9 +47638,7 @@ sb_1__1__mux_2level_tapbuf_basis_input2_mem2_10 mux_l1_in_2_ ( .in ( in[8:9] ) , .mem ( local_encoder2to4_0_data[0:1] ) , .mem_inv ( local_encoder2to4_0_data_inv[0:1] ) , .out ( mux_2level_tapbuf_basis_input2_mem2_0_out ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_158 ( .A ( BUF_net_159 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_159 ( .A ( aps_rename_513_ ) , - .Y ( BUF_net_159 ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_153 ( .A ( net_net_153 ) , .X ( out[0] ) ) ; endmodule @@ -44502,9 +47649,13 @@ input [0:1] mem ; input [0:1] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -44516,12 +47667,18 @@ input [0:3] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -44532,12 +47689,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -44548,12 +47711,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -44615,7 +47784,7 @@ wire [0:0] mux_2level_tapbuf_basis_input4_mem4_2_out ; sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_4_0_ ( .A ( mux_2level_tapbuf_basis_input4_mem4_2_out[0] ) , - .X ( aps_rename_512_ ) ) ; + .X ( aps_rename_509_ ) ) ; sb_1__1__local_encoder2to4_34 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , .data ( local_encoder2to4_0_data ) , .data_inv ( local_encoder2to4_0_data_inv ) ) ; @@ -44642,9 +47811,9 @@ sb_1__1__mux_2level_tapbuf_basis_input2_mem2_9 mux_l1_in_2_ ( .in ( in[8:9] ) , .mem ( local_encoder2to4_0_data[0:1] ) , .mem_inv ( local_encoder2to4_0_data_inv[0:1] ) , .out ( mux_2level_tapbuf_basis_input2_mem2_0_out ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_156 ( .A ( BUF_net_157 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_157 ( .A ( aps_rename_512_ ) , - .Y ( BUF_net_157 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_151 ( .A ( BUF_net_152 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_152 ( .A ( aps_rename_509_ ) , + .Y ( BUF_net_152 ) ) ; endmodule @@ -44655,9 +47824,13 @@ input [0:1] mem ; input [0:1] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -44669,12 +47842,18 @@ input [0:3] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -44685,12 +47864,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -44701,12 +47886,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -44804,9 +47995,13 @@ input [0:1] mem ; input [0:1] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -44818,12 +48013,18 @@ input [0:3] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -44834,12 +48035,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -44850,12 +48057,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -44953,9 +48166,13 @@ input [0:1] mem ; input [0:1] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -44967,12 +48184,18 @@ input [0:3] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -44983,12 +48206,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -44999,12 +48228,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -45102,9 +48337,13 @@ input [0:1] mem ; input [0:1] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -45116,12 +48355,18 @@ input [0:3] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -45132,12 +48377,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -45148,12 +48399,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -45213,9 +48470,8 @@ wire [0:0] mux_2level_tapbuf_basis_input4_mem4_0_out ; wire [0:0] mux_2level_tapbuf_basis_input4_mem4_1_out ; wire [0:0] mux_2level_tapbuf_basis_input4_mem4_2_out ; -sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_4_0_ ( - .A ( mux_2level_tapbuf_basis_input4_mem4_2_out[0] ) , - .X ( aps_rename_511_ ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( mux_2level_tapbuf_basis_input4_mem4_2_out[0] ) , .X ( out[0] ) ) ; sb_1__1__local_encoder2to4_26 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , .data ( local_encoder2to4_0_data ) , .data_inv ( local_encoder2to4_0_data_inv ) ) ; @@ -45242,9 +48498,6 @@ sb_1__1__mux_2level_tapbuf_basis_input2_mem2_5 mux_l1_in_2_ ( .in ( in[8:9] ) , .mem ( local_encoder2to4_0_data[0:1] ) , .mem_inv ( local_encoder2to4_0_data_inv[0:1] ) , .out ( mux_2level_tapbuf_basis_input2_mem2_0_out ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_154 ( .A ( BUF_net_155 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_155 ( .A ( aps_rename_511_ ) , - .Y ( BUF_net_155 ) ) ; endmodule @@ -45255,9 +48508,13 @@ input [0:1] mem ; input [0:1] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -45269,12 +48526,18 @@ input [0:3] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -45285,12 +48548,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -45301,12 +48570,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -45368,7 +48643,7 @@ wire [0:0] mux_2level_tapbuf_basis_input4_mem4_2_out ; sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_4_0_ ( .A ( mux_2level_tapbuf_basis_input4_mem4_2_out[0] ) , - .X ( aps_rename_510_ ) ) ; + .X ( aps_rename_508_ ) ) ; sb_1__1__local_encoder2to4_24 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , .data ( local_encoder2to4_0_data ) , .data_inv ( local_encoder2to4_0_data_inv ) ) ; @@ -45395,9 +48670,9 @@ sb_1__1__mux_2level_tapbuf_basis_input2_mem2_4 mux_l1_in_2_ ( .in ( in[8:9] ) , .mem ( local_encoder2to4_0_data[0:1] ) , .mem_inv ( local_encoder2to4_0_data_inv[0:1] ) , .out ( mux_2level_tapbuf_basis_input2_mem2_0_out ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_152 ( .A ( BUF_net_153 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_153 ( .A ( aps_rename_510_ ) , - .Y ( BUF_net_153 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_149 ( .A ( BUF_net_150 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_150 ( .A ( aps_rename_508_ ) , + .Y ( BUF_net_150 ) ) ; endmodule @@ -45408,9 +48683,13 @@ input [0:1] mem ; input [0:1] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -45422,12 +48701,18 @@ input [0:3] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -45438,12 +48723,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -45454,12 +48745,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -45519,9 +48816,8 @@ wire [0:0] mux_2level_tapbuf_basis_input4_mem4_0_out ; wire [0:0] mux_2level_tapbuf_basis_input4_mem4_1_out ; wire [0:0] mux_2level_tapbuf_basis_input4_mem4_2_out ; -sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_4_0_ ( - .A ( mux_2level_tapbuf_basis_input4_mem4_2_out[0] ) , - .X ( aps_rename_509_ ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( mux_2level_tapbuf_basis_input4_mem4_2_out[0] ) , .X ( out[0] ) ) ; sb_1__1__local_encoder2to4_22 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , .data ( local_encoder2to4_0_data ) , .data_inv ( local_encoder2to4_0_data_inv ) ) ; @@ -45548,9 +48844,6 @@ sb_1__1__mux_2level_tapbuf_basis_input2_mem2_3 mux_l1_in_2_ ( .in ( in[8:9] ) , .mem ( local_encoder2to4_0_data[0:1] ) , .mem_inv ( local_encoder2to4_0_data_inv[0:1] ) , .out ( mux_2level_tapbuf_basis_input2_mem2_0_out ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_150 ( .A ( BUF_net_151 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_151 ( .A ( aps_rename_509_ ) , - .Y ( BUF_net_151 ) ) ; endmodule @@ -45561,9 +48854,13 @@ input [0:1] mem ; input [0:1] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -45575,12 +48872,18 @@ input [0:3] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -45591,12 +48894,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -45607,12 +48916,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -45672,7 +48987,7 @@ wire [0:0] mux_2level_tapbuf_basis_input4_mem4_0_out ; wire [0:0] mux_2level_tapbuf_basis_input4_mem4_1_out ; wire [0:0] mux_2level_tapbuf_basis_input4_mem4_2_out ; -sky130_fd_sc_hd__bufbuf_16 sky130_fd_sc_hd__buf_4_0_ ( +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( mux_2level_tapbuf_basis_input4_mem4_2_out[0] ) , .X ( out[0] ) ) ; sb_1__1__local_encoder2to4_20 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , .data ( local_encoder2to4_0_data ) , @@ -45710,9 +49025,13 @@ input [0:1] mem ; input [0:1] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -45724,12 +49043,18 @@ input [0:3] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -45740,12 +49065,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -45756,12 +49087,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -45821,9 +49158,8 @@ wire [0:0] mux_2level_tapbuf_basis_input4_mem4_0_out ; wire [0:0] mux_2level_tapbuf_basis_input4_mem4_1_out ; wire [0:0] mux_2level_tapbuf_basis_input4_mem4_2_out ; -sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_4_0_ ( - .A ( mux_2level_tapbuf_basis_input4_mem4_2_out[0] ) , - .X ( aps_rename_508_ ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( mux_2level_tapbuf_basis_input4_mem4_2_out[0] ) , .X ( out[0] ) ) ; sb_1__1__local_encoder2to4_18 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , .data ( local_encoder2to4_0_data ) , .data_inv ( local_encoder2to4_0_data_inv ) ) ; @@ -45850,9 +49186,6 @@ sb_1__1__mux_2level_tapbuf_basis_input2_mem2_1 mux_l1_in_2_ ( .in ( in[8:9] ) , .mem ( local_encoder2to4_0_data[0:1] ) , .mem_inv ( local_encoder2to4_0_data_inv[0:1] ) , .out ( mux_2level_tapbuf_basis_input2_mem2_0_out ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_193 ( .A ( BUF_net_194 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_194 ( .A ( aps_rename_508_ ) , - .Y ( BUF_net_194 ) ) ; endmodule @@ -45863,9 +49196,13 @@ input [0:1] mem ; input [0:1] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -45877,12 +49214,18 @@ input [0:3] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -45893,12 +49236,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -45909,12 +49258,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -45974,9 +49329,8 @@ wire [0:0] mux_2level_tapbuf_basis_input4_mem4_0_out ; wire [0:0] mux_2level_tapbuf_basis_input4_mem4_1_out ; wire [0:0] mux_2level_tapbuf_basis_input4_mem4_2_out ; -sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_4_0_ ( - .A ( mux_2level_tapbuf_basis_input4_mem4_2_out[0] ) , - .X ( aps_rename_507_ ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( mux_2level_tapbuf_basis_input4_mem4_2_out[0] ) , .X ( out[0] ) ) ; sb_1__1__local_encoder2to4_16 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , .data ( local_encoder2to4_0_data ) , .data_inv ( local_encoder2to4_0_data_inv ) ) ; @@ -46003,9 +49357,6 @@ sb_1__1__mux_2level_tapbuf_basis_input2_mem2_0 mux_l1_in_2_ ( .in ( in[8:9] ) , .mem ( local_encoder2to4_0_data[0:1] ) , .mem_inv ( local_encoder2to4_0_data_inv[0:1] ) , .out ( mux_2level_tapbuf_basis_input2_mem2_0_out ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_148 ( .A ( BUF_net_149 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_149 ( .A ( aps_rename_507_ ) , - .Y ( BUF_net_149 ) ) ; endmodule @@ -46157,7 +49508,7 @@ input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( copt_net_207 ) , +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; @@ -46166,10 +49517,6 @@ sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__buf_1 FTB_1__0 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 copt_h_inst_1416 ( .A ( ccff_head[0] ) , - .X ( copt_net_206 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1417 ( .A ( copt_net_206 ) , - .X ( copt_net_207 ) ) ; endmodule @@ -46180,10 +49527,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -46195,12 +49546,18 @@ input [0:3] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -46211,12 +49568,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -46227,12 +49590,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -46292,7 +49661,7 @@ wire [0:0] mux_2level_tapbuf_basis_input4_mem4_0_out ; wire [0:0] mux_2level_tapbuf_basis_input4_mem4_1_out ; wire [0:0] mux_2level_tapbuf_basis_input4_mem4_2_out ; -sky130_fd_sc_hd__bufbuf_16 sky130_fd_sc_hd__buf_4_0_ ( +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( mux_2level_tapbuf_basis_input4_mem4_2_out[0] ) , .X ( out[0] ) ) ; sb_1__1__local_encoder2to4_14 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , .data ( local_encoder2to4_0_data ) , @@ -46330,10 +49699,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -46345,12 +49718,18 @@ input [0:3] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -46361,12 +49740,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -46377,12 +49762,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -46442,8 +49833,9 @@ wire [0:0] mux_2level_tapbuf_basis_input4_mem4_0_out ; wire [0:0] mux_2level_tapbuf_basis_input4_mem4_1_out ; wire [0:0] mux_2level_tapbuf_basis_input4_mem4_2_out ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( mux_2level_tapbuf_basis_input4_mem4_2_out[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_4_0_ ( + .A ( mux_2level_tapbuf_basis_input4_mem4_2_out[0] ) , + .X ( aps_rename_507_ ) ) ; sb_1__1__local_encoder2to4_12 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , .data ( local_encoder2to4_0_data ) , .data_inv ( local_encoder2to4_0_data_inv ) ) ; @@ -46470,6 +49862,9 @@ sb_1__1__mux_2level_tapbuf_basis_input3_mem3_6 mux_l1_in_2_ ( .in ( in[8:10] ) , .mem ( local_encoder2to4_0_data[0:2] ) , .mem_inv ( local_encoder2to4_0_data_inv[0:2] ) , .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_147 ( .A ( BUF_net_148 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_148 ( .A ( aps_rename_507_ ) , + .Y ( BUF_net_148 ) ) ; endmodule @@ -46480,10 +49875,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -46495,12 +49894,18 @@ input [0:3] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -46511,12 +49916,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -46527,12 +49938,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -46592,8 +50009,8 @@ wire [0:0] mux_2level_tapbuf_basis_input4_mem4_0_out ; wire [0:0] mux_2level_tapbuf_basis_input4_mem4_1_out ; wire [0:0] mux_2level_tapbuf_basis_input4_mem4_2_out ; -sky130_fd_sc_hd__bufbuf_16 sky130_fd_sc_hd__buf_4_0_ ( - .A ( mux_2level_tapbuf_basis_input4_mem4_2_out[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_4_0_ ( + .A ( mux_2level_tapbuf_basis_input4_mem4_2_out[0] ) , .X ( net_net_146 ) ) ; sb_1__1__local_encoder2to4_10 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , .data ( local_encoder2to4_0_data ) , .data_inv ( local_encoder2to4_0_data_inv ) ) ; @@ -46620,6 +50037,7 @@ sb_1__1__mux_2level_tapbuf_basis_input3_mem3_5 mux_l1_in_2_ ( .in ( in[8:10] ) , .mem ( local_encoder2to4_0_data[0:2] ) , .mem_inv ( local_encoder2to4_0_data_inv[0:2] ) , .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_146 ( .A ( net_net_146 ) , .X ( out[0] ) ) ; endmodule @@ -46630,10 +50048,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -46645,12 +50067,18 @@ input [0:3] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -46661,12 +50089,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -46677,12 +50111,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -46771,9 +50211,9 @@ sb_1__1__mux_2level_tapbuf_basis_input3_mem3_4 mux_l1_in_2_ ( .in ( in[8:10] ) , .mem ( local_encoder2to4_0_data[0:2] ) , .mem_inv ( local_encoder2to4_0_data_inv[0:2] ) , .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_146 ( .A ( BUF_net_147 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_147 ( .A ( aps_rename_506_ ) , - .Y ( BUF_net_147 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_144 ( .A ( BUF_net_145 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_145 ( .A ( aps_rename_506_ ) , + .Y ( BUF_net_145 ) ) ; endmodule @@ -46784,10 +50224,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -46799,12 +50243,18 @@ input [0:3] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -46815,12 +50265,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -46831,12 +50287,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -46934,10 +50396,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -46949,12 +50415,18 @@ input [0:3] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -46965,12 +50437,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -46981,12 +50459,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -47046,7 +50530,7 @@ wire [0:0] mux_2level_tapbuf_basis_input4_mem4_0_out ; wire [0:0] mux_2level_tapbuf_basis_input4_mem4_1_out ; wire [0:0] mux_2level_tapbuf_basis_input4_mem4_2_out ; -sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_4_0_ ( +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( mux_2level_tapbuf_basis_input4_mem4_2_out[0] ) , .X ( out[0] ) ) ; sb_1__1__local_encoder2to4_4 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , .data ( local_encoder2to4_0_data ) , @@ -47084,10 +50568,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -47099,12 +50587,18 @@ input [0:3] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -47115,12 +50609,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -47131,12 +50631,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -47225,9 +50731,9 @@ sb_1__1__mux_2level_tapbuf_basis_input3_mem3_1 mux_l1_in_2_ ( .in ( in[8:10] ) , .mem ( local_encoder2to4_0_data[0:2] ) , .mem_inv ( local_encoder2to4_0_data_inv[0:2] ) , .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_144 ( .A ( BUF_net_145 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_145 ( .A ( aps_rename_505_ ) , - .Y ( BUF_net_145 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_172 ( .A ( BUF_net_173 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_173 ( .A ( aps_rename_505_ ) , + .Y ( BUF_net_173 ) ) ; endmodule @@ -47238,10 +50744,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -47253,12 +50763,18 @@ input [0:3] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -47269,12 +50785,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -47285,12 +50807,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -47641,7 +51169,7 @@ sb_1__1__mux_2level_tapbuf_size11_0 mux_top_track_0 ( .sram ( mux_2level_tapbuf_size11_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 , SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) , - .out ( chany_top_out[0] ) , .p0 ( optlc_net_200 ) ) ; + .out ( chany_top_out[0] ) , .p0 ( optlc_net_179 ) ) ; sb_1__1__mux_2level_tapbuf_size11_1 mux_top_track_2 ( .in ( { top_left_grid_pin_45_[0] , top_left_grid_pin_48_[0] , top_left_grid_pin_51_[0] , chanx_right_in[2] , chanx_left_out[7] , @@ -47650,7 +51178,7 @@ sb_1__1__mux_2level_tapbuf_size11_1 mux_top_track_2 ( .sram ( mux_2level_tapbuf_size11_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 , SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 } ) , - .out ( chany_top_out[1] ) , .p0 ( optlc_net_201 ) ) ; + .out ( chany_top_out[1] ) , .p0 ( optlc_net_179 ) ) ; sb_1__1__mux_2level_tapbuf_size11_2 mux_right_track_0 ( .in ( { chany_bottom_out[4] , chany_bottom_out[20] , chany_top_in[29] , right_bottom_grid_pin_36_[0] , right_bottom_grid_pin_39_[0] , @@ -47659,8 +51187,7 @@ sb_1__1__mux_2level_tapbuf_size11_2 mux_right_track_0 ( .sram ( mux_2level_tapbuf_size11_2_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_9 , SYNOPSYS_UNCONNECTED_10 , SYNOPSYS_UNCONNECTED_11 , SYNOPSYS_UNCONNECTED_12 } ) , - .out ( { aps_rename_521_ } ) , - .p0 ( optlc_net_198 ) ) ; + .out ( chanx_right_out[0] ) , .p0 ( optlc_net_180 ) ) ; sb_1__1__mux_2level_tapbuf_size11_3 mux_right_track_2 ( .in ( { chany_top_in[0] , chany_bottom_out[7] , chany_bottom_out[21] , right_bottom_grid_pin_37_[0] , right_bottom_grid_pin_40_[0] , @@ -47669,7 +51196,7 @@ sb_1__1__mux_2level_tapbuf_size11_3 mux_right_track_2 ( .sram ( mux_2level_tapbuf_size11_3_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 , SYNOPSYS_UNCONNECTED_15 , SYNOPSYS_UNCONNECTED_16 } ) , - .out ( chanx_right_out[1] ) , .p0 ( optlc_net_202 ) ) ; + .out ( chanx_right_out[1] ) , .p0 ( optlc_net_180 ) ) ; sb_1__1__mux_2level_tapbuf_size11_4 mux_bottom_track_1 ( .in ( { chany_bottom_out[4] , chany_bottom_out[20] , chanx_left_out[4] , chanx_left_out[20] , chanx_right_in[25] , @@ -47679,7 +51206,7 @@ sb_1__1__mux_2level_tapbuf_size11_4 mux_bottom_track_1 ( .sram ( mux_2level_tapbuf_size11_4_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_17 , SYNOPSYS_UNCONNECTED_18 , SYNOPSYS_UNCONNECTED_19 , SYNOPSYS_UNCONNECTED_20 } ) , - .out ( chany_bottom_out[0] ) , .p0 ( optlc_net_204 ) ) ; + .out ( chany_bottom_out[0] ) , .p0 ( optlc_net_176 ) ) ; sb_1__1__mux_2level_tapbuf_size11_5 mux_bottom_track_3 ( .in ( { chany_bottom_out[7] , chany_bottom_out[21] , chanx_left_out[7] , chanx_left_out[21] , chanx_right_in[21] , @@ -47689,7 +51216,7 @@ sb_1__1__mux_2level_tapbuf_size11_5 mux_bottom_track_3 ( .sram ( mux_2level_tapbuf_size11_5_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_21 , SYNOPSYS_UNCONNECTED_22 , SYNOPSYS_UNCONNECTED_23 , SYNOPSYS_UNCONNECTED_24 } ) , - .out ( chany_bottom_out[1] ) , .p0 ( optlc_net_199 ) ) ; + .out ( chany_bottom_out[1] ) , .p0 ( optlc_net_177 ) ) ; sb_1__1__mux_2level_tapbuf_size11_6 mux_left_track_1 ( .in ( { chany_top_in[0] , chany_bottom_out[4] , chany_bottom_out[20] , chanx_left_out[4] , chanx_left_out[20] , chany_top_out[4] , @@ -47699,7 +51226,7 @@ sb_1__1__mux_2level_tapbuf_size11_6 mux_left_track_1 ( .sram ( mux_2level_tapbuf_size11_6_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_25 , SYNOPSYS_UNCONNECTED_26 , SYNOPSYS_UNCONNECTED_27 , SYNOPSYS_UNCONNECTED_28 } ) , - .out ( chanx_left_out[0] ) , .p0 ( optlc_net_204 ) ) ; + .out ( chanx_left_out[0] ) , .p0 ( optlc_net_179 ) ) ; sb_1__1__mux_2level_tapbuf_size11 mux_left_track_3 ( .in ( { chany_bottom_out[7] , chany_bottom_out[21] , chany_top_in[29] , chanx_left_out[7] , chanx_left_out[21] , chany_bottom_in[0] , @@ -47708,7 +51235,7 @@ sb_1__1__mux_2level_tapbuf_size11 mux_left_track_3 ( .sram ( mux_2level_tapbuf_size11_7_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_29 , SYNOPSYS_UNCONNECTED_30 , SYNOPSYS_UNCONNECTED_31 , SYNOPSYS_UNCONNECTED_32 } ) , - .out ( chanx_left_out[1] ) , .p0 ( optlc_net_199 ) ) ; + .out ( chanx_left_out[1] ) , .p0 ( optlc_net_177 ) ) ; sb_1__1__mux_2level_tapbuf_size11_mem_0 mem_top_track_0 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( mux_2level_tapbuf_size11_mem_0_ccff_tail ) , @@ -47756,7 +51283,7 @@ sb_1__1__mux_2level_tapbuf_size10_0 mux_top_track_4 ( .sram ( mux_2level_tapbuf_size10_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_33 , SYNOPSYS_UNCONNECTED_34 , SYNOPSYS_UNCONNECTED_35 , SYNOPSYS_UNCONNECTED_36 } ) , - .out ( chany_top_out[2] ) , .p0 ( optlc_net_197 ) ) ; + .out ( chany_top_out[2] ) , .p0 ( optlc_net_174 ) ) ; sb_1__1__mux_2level_tapbuf_size10_1 mux_top_track_12 ( .in ( { top_left_grid_pin_44_[0] , top_left_grid_pin_50_[0] , chanx_left_out[12] , chanx_right_in[13] , chanx_left_out[27] , @@ -47765,7 +51292,7 @@ sb_1__1__mux_2level_tapbuf_size10_1 mux_top_track_12 ( .sram ( mux_2level_tapbuf_size10_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_37 , SYNOPSYS_UNCONNECTED_38 , SYNOPSYS_UNCONNECTED_39 , SYNOPSYS_UNCONNECTED_40 } ) , - .out ( chany_top_out[6] ) , .p0 ( optlc_net_200 ) ) ; + .out ( chany_top_out[6] ) , .p0 ( optlc_net_175 ) ) ; sb_1__1__mux_2level_tapbuf_size10_2 mux_top_track_20 ( .in ( { top_left_grid_pin_45_[0] , top_left_grid_pin_51_[0] , chanx_left_out[13] , chanx_right_in[17] , chanx_left_out[28] , @@ -47774,7 +51301,7 @@ sb_1__1__mux_2level_tapbuf_size10_2 mux_top_track_20 ( .sram ( mux_2level_tapbuf_size10_2_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_41 , SYNOPSYS_UNCONNECTED_42 , SYNOPSYS_UNCONNECTED_43 , SYNOPSYS_UNCONNECTED_44 } ) , - .out ( chany_top_out[10] ) , .p0 ( optlc_net_203 ) ) ; + .out ( chany_top_out[10] ) , .p0 ( optlc_net_179 ) ) ; sb_1__1__mux_2level_tapbuf_size10_3 mux_right_track_4 ( .in ( { chany_top_in[1] , chany_bottom_out[8] , chany_bottom_out[23] , right_bottom_grid_pin_38_[0] , right_bottom_grid_pin_41_[0] , @@ -47783,7 +51310,7 @@ sb_1__1__mux_2level_tapbuf_size10_3 mux_right_track_4 ( .sram ( mux_2level_tapbuf_size10_3_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_45 , SYNOPSYS_UNCONNECTED_46 , SYNOPSYS_UNCONNECTED_47 , SYNOPSYS_UNCONNECTED_48 } ) , - .out ( chanx_right_out[2] ) , .p0 ( optlc_net_198 ) ) ; + .out ( chanx_right_out[2] ) , .p0 ( optlc_net_175 ) ) ; sb_1__1__mux_2level_tapbuf_size10_4 mux_right_track_12 ( .in ( { chany_top_in[5] , chany_bottom_out[12] , chany_bottom_out[27] , right_bottom_grid_pin_36_[0] , right_bottom_grid_pin_42_[0] , @@ -47792,7 +51319,7 @@ sb_1__1__mux_2level_tapbuf_size10_4 mux_right_track_12 ( .sram ( mux_2level_tapbuf_size10_4_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_49 , SYNOPSYS_UNCONNECTED_50 , SYNOPSYS_UNCONNECTED_51 , SYNOPSYS_UNCONNECTED_52 } ) , - .out ( chanx_right_out[6] ) , .p0 ( optlc_net_202 ) ) ; + .out ( chanx_right_out[6] ) , .p0 ( optlc_net_180 ) ) ; sb_1__1__mux_2level_tapbuf_size10_5 mux_right_track_20 ( .in ( { chany_top_in[9] , chany_bottom_out[13] , chany_bottom_out[28] , right_bottom_grid_pin_37_[0] , right_bottom_grid_pin_43_[0] , @@ -47801,7 +51328,7 @@ sb_1__1__mux_2level_tapbuf_size10_5 mux_right_track_20 ( .sram ( mux_2level_tapbuf_size10_5_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_53 , SYNOPSYS_UNCONNECTED_54 , SYNOPSYS_UNCONNECTED_55 , SYNOPSYS_UNCONNECTED_56 } ) , - .out ( chanx_right_out[10] ) , .p0 ( optlc_net_202 ) ) ; + .out ( chanx_right_out[10] ) , .p0 ( optlc_net_180 ) ) ; sb_1__1__mux_2level_tapbuf_size10_6 mux_bottom_track_5 ( .in ( { chany_bottom_out[8] , chany_bottom_out[23] , chanx_left_out[8] , chanx_right_in[17] , chanx_left_out[23] , @@ -47810,7 +51337,7 @@ sb_1__1__mux_2level_tapbuf_size10_6 mux_bottom_track_5 ( .sram ( mux_2level_tapbuf_size10_6_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_57 , SYNOPSYS_UNCONNECTED_58 , SYNOPSYS_UNCONNECTED_59 , SYNOPSYS_UNCONNECTED_60 } ) , - .out ( chany_bottom_out[2] ) , .p0 ( optlc_net_201 ) ) ; + .out ( chany_bottom_out[2] ) , .p0 ( optlc_net_177 ) ) ; sb_1__1__mux_2level_tapbuf_size10_7 mux_bottom_track_13 ( .in ( { chany_bottom_out[12] , chany_bottom_out[27] , chanx_right_in[5] , chanx_left_out[12] , chanx_left_out[27] , @@ -47819,7 +51346,7 @@ sb_1__1__mux_2level_tapbuf_size10_7 mux_bottom_track_13 ( .sram ( mux_2level_tapbuf_size10_7_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_61 , SYNOPSYS_UNCONNECTED_62 , SYNOPSYS_UNCONNECTED_63 , SYNOPSYS_UNCONNECTED_64 } ) , - .out ( chany_bottom_out[6] ) , .p0 ( optlc_net_204 ) ) ; + .out ( chany_bottom_out[6] ) , .p0 ( optlc_net_176 ) ) ; sb_1__1__mux_2level_tapbuf_size10_8 mux_bottom_track_21 ( .in ( { chany_bottom_out[13] , chany_bottom_out[28] , chanx_right_in[4] , chanx_left_out[13] , chanx_left_out[28] , @@ -47828,7 +51355,7 @@ sb_1__1__mux_2level_tapbuf_size10_8 mux_bottom_track_21 ( .sram ( mux_2level_tapbuf_size10_8_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_65 , SYNOPSYS_UNCONNECTED_66 , SYNOPSYS_UNCONNECTED_67 , SYNOPSYS_UNCONNECTED_68 } ) , - .out ( chany_bottom_out[10] ) , .p0 ( optlc_net_204 ) ) ; + .out ( chany_bottom_out[10] ) , .p0 ( optlc_net_176 ) ) ; sb_1__1__mux_2level_tapbuf_size10_9 mux_left_track_5 ( .in ( { chany_bottom_out[8] , chany_bottom_out[23] , chany_top_in[25] , chanx_left_out[8] , chanx_left_out[23] , chany_bottom_in[1] , @@ -47837,7 +51364,7 @@ sb_1__1__mux_2level_tapbuf_size10_9 mux_left_track_5 ( .sram ( mux_2level_tapbuf_size10_9_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_69 , SYNOPSYS_UNCONNECTED_70 , SYNOPSYS_UNCONNECTED_71 , SYNOPSYS_UNCONNECTED_72 } ) , - .out ( chanx_left_out[2] ) , .p0 ( optlc_net_201 ) ) ; + .out ( chanx_left_out[2] ) , .p0 ( optlc_net_182 ) ) ; sb_1__1__mux_2level_tapbuf_size10_10 mux_left_track_13 ( .in ( { chany_bottom_out[12] , chany_top_in[13] , chany_bottom_out[27] , chanx_left_out[12] , chanx_left_out[27] , chany_bottom_in[5] , @@ -47846,7 +51373,7 @@ sb_1__1__mux_2level_tapbuf_size10_10 mux_left_track_13 ( .sram ( mux_2level_tapbuf_size10_10_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_73 , SYNOPSYS_UNCONNECTED_74 , SYNOPSYS_UNCONNECTED_75 , SYNOPSYS_UNCONNECTED_76 } ) , - .out ( chanx_left_out[6] ) , .p0 ( optlc_net_204 ) ) ; + .out ( chanx_left_out[6] ) , .p0 ( optlc_net_176 ) ) ; sb_1__1__mux_2level_tapbuf_size10 mux_left_track_21 ( .in ( { chany_top_in[9] , chany_bottom_out[13] , chany_bottom_out[28] , chanx_left_out[13] , chanx_left_out[28] , chany_bottom_in[9] , @@ -47855,7 +51382,7 @@ sb_1__1__mux_2level_tapbuf_size10 mux_left_track_21 ( .sram ( mux_2level_tapbuf_size10_11_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_77 , SYNOPSYS_UNCONNECTED_78 , SYNOPSYS_UNCONNECTED_79 , SYNOPSYS_UNCONNECTED_80 } ) , - .out ( chanx_left_out[10] ) , .p0 ( optlc_net_204 ) ) ; + .out ( chanx_left_out[10] ) , .p0 ( optlc_net_176 ) ) ; sb_1__1__mux_2level_tapbuf_size10_mem_0 mem_top_track_4 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( mux_2level_tapbuf_size11_mem_1_ccff_tail ) , @@ -47925,7 +51452,7 @@ sb_1__1__mux_2level_tapbuf_size12_0 mux_top_track_6 ( .sram ( mux_2level_tapbuf_size12_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_81 , SYNOPSYS_UNCONNECTED_82 , SYNOPSYS_UNCONNECTED_83 , SYNOPSYS_UNCONNECTED_84 } ) , - .out ( chany_top_out[3] ) , .p0 ( optlc_net_203 ) ) ; + .out ( chany_top_out[3] ) , .p0 ( optlc_net_182 ) ) ; sb_1__1__mux_2level_tapbuf_size12_1 mux_top_track_10 ( .in ( { top_left_grid_pin_45_[0] , top_left_grid_pin_47_[0] , top_left_grid_pin_49_[0] , top_left_grid_pin_51_[0] , @@ -47935,7 +51462,7 @@ sb_1__1__mux_2level_tapbuf_size12_1 mux_top_track_10 ( .sram ( mux_2level_tapbuf_size12_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_85 , SYNOPSYS_UNCONNECTED_86 , SYNOPSYS_UNCONNECTED_87 , SYNOPSYS_UNCONNECTED_88 } ) , - .out ( chany_top_out[5] ) , .p0 ( optlc_net_201 ) ) ; + .out ( chany_top_out[5] ) , .p0 ( optlc_net_179 ) ) ; sb_1__1__mux_2level_tapbuf_size12_2 mux_right_track_6 ( .in ( { chany_top_in[2] , chany_bottom_out[9] , chany_bottom_out[24] , right_bottom_grid_pin_36_[0] , right_bottom_grid_pin_38_[0] , @@ -47945,8 +51472,7 @@ sb_1__1__mux_2level_tapbuf_size12_2 mux_right_track_6 ( .sram ( mux_2level_tapbuf_size12_2_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_89 , SYNOPSYS_UNCONNECTED_90 , SYNOPSYS_UNCONNECTED_91 , SYNOPSYS_UNCONNECTED_92 } ) , - .out ( { aps_rename_522_ } ) , - .p0 ( optlc_net_202 ) ) ; + .out ( chanx_right_out[3] ) , .p0 ( optlc_net_180 ) ) ; sb_1__1__mux_2level_tapbuf_size12_3 mux_right_track_10 ( .in ( { chany_top_in[4] , chany_bottom_out[11] , chany_bottom_out[25] , right_bottom_grid_pin_37_[0] , right_bottom_grid_pin_39_[0] , @@ -47956,7 +51482,7 @@ sb_1__1__mux_2level_tapbuf_size12_3 mux_right_track_10 ( .sram ( mux_2level_tapbuf_size12_3_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_93 , SYNOPSYS_UNCONNECTED_94 , SYNOPSYS_UNCONNECTED_95 , SYNOPSYS_UNCONNECTED_96 } ) , - .out ( chanx_right_out[5] ) , .p0 ( optlc_net_202 ) ) ; + .out ( chanx_right_out[5] ) , .p0 ( optlc_net_180 ) ) ; sb_1__1__mux_2level_tapbuf_size12_4 mux_bottom_track_7 ( .in ( { chany_bottom_out[9] , chany_bottom_out[24] , chanx_left_out[9] , chanx_right_in[13] , chanx_left_out[24] , @@ -47966,7 +51492,7 @@ sb_1__1__mux_2level_tapbuf_size12_4 mux_bottom_track_7 ( .sram ( mux_2level_tapbuf_size12_4_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_97 , SYNOPSYS_UNCONNECTED_98 , SYNOPSYS_UNCONNECTED_99 , SYNOPSYS_UNCONNECTED_100 } ) , - .out ( chany_bottom_out[3] ) , .p0 ( optlc_net_199 ) ) ; + .out ( chany_bottom_out[3] ) , .p0 ( optlc_net_177 ) ) ; sb_1__1__mux_2level_tapbuf_size12_5 mux_bottom_track_11 ( .in ( { chany_bottom_out[11] , chany_bottom_out[25] , chanx_right_in[9] , chanx_left_out[11] , chanx_left_out[25] , @@ -47976,7 +51502,7 @@ sb_1__1__mux_2level_tapbuf_size12_5 mux_bottom_track_11 ( .sram ( mux_2level_tapbuf_size12_5_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_101 , SYNOPSYS_UNCONNECTED_102 , SYNOPSYS_UNCONNECTED_103 , SYNOPSYS_UNCONNECTED_104 } ) , - .out ( chany_bottom_out[5] ) , .p0 ( optlc_net_199 ) ) ; + .out ( chany_bottom_out[5] ) , .p0 ( optlc_net_176 ) ) ; sb_1__1__mux_2level_tapbuf_size12_6 mux_left_track_7 ( .in ( { chany_bottom_out[9] , chany_top_in[21] , chany_bottom_out[24] , chanx_left_out[9] , chanx_left_out[24] , chany_bottom_in[2] , @@ -47986,7 +51512,7 @@ sb_1__1__mux_2level_tapbuf_size12_6 mux_left_track_7 ( .sram ( mux_2level_tapbuf_size12_6_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_105 , SYNOPSYS_UNCONNECTED_106 , SYNOPSYS_UNCONNECTED_107 , SYNOPSYS_UNCONNECTED_108 } ) , - .out ( chanx_left_out[3] ) , .p0 ( optlc_net_199 ) ) ; + .out ( chanx_left_out[3] ) , .p0 ( optlc_net_182 ) ) ; sb_1__1__mux_2level_tapbuf_size12 mux_left_track_11 ( .in ( { chany_bottom_out[11] , chany_top_in[17] , chany_bottom_out[25] , chanx_left_out[11] , chanx_left_out[25] , chany_bottom_in[4] , @@ -47996,7 +51522,7 @@ sb_1__1__mux_2level_tapbuf_size12 mux_left_track_11 ( .sram ( mux_2level_tapbuf_size12_7_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_109 , SYNOPSYS_UNCONNECTED_110 , SYNOPSYS_UNCONNECTED_111 , SYNOPSYS_UNCONNECTED_112 } ) , - .out ( chanx_left_out[5] ) , .p0 ( optlc_net_204 ) ) ; + .out ( chanx_left_out[5] ) , .p0 ( optlc_net_177 ) ) ; sb_1__1__mux_2level_tapbuf_size12_mem_0 mem_top_track_6 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( mux_2level_tapbuf_size10_mem_0_ccff_tail ) , @@ -48045,7 +51571,7 @@ sb_1__1__mux_2level_tapbuf_size9_0 mux_top_track_28 ( .sram ( mux_2level_tapbuf_size9_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_113 , SYNOPSYS_UNCONNECTED_114 , SYNOPSYS_UNCONNECTED_115 , SYNOPSYS_UNCONNECTED_116 } ) , - .out ( chany_top_out[14] ) , .p0 ( optlc_net_198 ) ) ; + .out ( chany_top_out[14] ) , .p0 ( optlc_net_178 ) ) ; sb_1__1__mux_2level_tapbuf_size9_1 mux_right_track_28 ( .in ( { chany_top_in[13] , chany_bottom_out[15] , chany_bottom_out[29] , right_bottom_grid_pin_38_[0] , chany_bottom_in[2] , @@ -48054,7 +51580,7 @@ sb_1__1__mux_2level_tapbuf_size9_1 mux_right_track_28 ( .sram ( mux_2level_tapbuf_size9_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_117 , SYNOPSYS_UNCONNECTED_118 , SYNOPSYS_UNCONNECTED_119 , SYNOPSYS_UNCONNECTED_120 } ) , - .out ( chanx_right_out[14] ) , .p0 ( optlc_net_202 ) ) ; + .out ( chanx_right_out[14] ) , .p0 ( optlc_net_178 ) ) ; sb_1__1__mux_2level_tapbuf_size9_2 mux_bottom_track_29 ( .in ( { chany_bottom_out[15] , chany_bottom_out[29] , chanx_right_in[2] , chanx_left_out[15] , chanx_left_out[29] , @@ -48063,7 +51589,7 @@ sb_1__1__mux_2level_tapbuf_size9_2 mux_bottom_track_29 ( .sram ( mux_2level_tapbuf_size9_2_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_121 , SYNOPSYS_UNCONNECTED_122 , SYNOPSYS_UNCONNECTED_123 , SYNOPSYS_UNCONNECTED_124 } ) , - .out ( chany_bottom_out[14] ) , .p0 ( optlc_net_202 ) ) ; + .out ( chany_bottom_out[14] ) , .p0 ( optlc_net_180 ) ) ; sb_1__1__mux_2level_tapbuf_size9 mux_left_track_29 ( .in ( { chany_top_in[5] , chany_bottom_out[15] , chany_bottom_out[29] , chanx_left_out[15] , chanx_left_out[29] , chany_bottom_in[13] , @@ -48071,7 +51597,7 @@ sb_1__1__mux_2level_tapbuf_size9 mux_left_track_29 ( .sram ( mux_2level_tapbuf_size9_3_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_125 , SYNOPSYS_UNCONNECTED_126 , SYNOPSYS_UNCONNECTED_127 , SYNOPSYS_UNCONNECTED_128 } ) , - .out ( chanx_left_out[14] ) , .p0 ( optlc_net_204 ) ) ; + .out ( chanx_left_out[14] ) , .p0 ( optlc_net_179 ) ) ; sb_1__1__mux_2level_tapbuf_size9_mem_0 mem_top_track_28 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( mux_2level_tapbuf_size10_mem_2_ccff_tail ) , @@ -48099,7 +51625,7 @@ sb_1__1__mux_2level_tapbuf_size6_0 mux_top_track_36 ( .sram ( mux_2level_tapbuf_size6_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_129 , SYNOPSYS_UNCONNECTED_130 , SYNOPSYS_UNCONNECTED_131 , SYNOPSYS_UNCONNECTED_132 } ) , - .out ( chany_top_out[18] ) , .p0 ( optlc_net_200 ) ) ; + .out ( chany_top_out[18] ) , .p0 ( optlc_net_175 ) ) ; sb_1__1__mux_2level_tapbuf_size6_1 mux_top_track_44 ( .in ( { top_left_grid_pin_48_[0] , chanx_left_out[17] , chanx_right_in[29] , chany_top_out[17] , chanx_left_in[2] , @@ -48107,7 +51633,7 @@ sb_1__1__mux_2level_tapbuf_size6_1 mux_top_track_44 ( .sram ( mux_2level_tapbuf_size6_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_133 , SYNOPSYS_UNCONNECTED_134 , SYNOPSYS_UNCONNECTED_135 , SYNOPSYS_UNCONNECTED_136 } ) , - .out ( chany_top_out[22] ) , .p0 ( optlc_net_203 ) ) ; + .out ( chany_top_out[22] ) , .p0 ( optlc_net_181 ) ) ; sb_1__1__mux_2level_tapbuf_size6_2 mux_top_track_52 ( .in ( { top_left_grid_pin_49_[0] , chanx_right_in[0] , chanx_left_out[19] , chany_top_out[19] , chanx_left_in[1] , @@ -48115,7 +51641,7 @@ sb_1__1__mux_2level_tapbuf_size6_2 mux_top_track_52 ( .sram ( mux_2level_tapbuf_size6_2_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_137 , SYNOPSYS_UNCONNECTED_138 , SYNOPSYS_UNCONNECTED_139 , SYNOPSYS_UNCONNECTED_140 } ) , - .out ( chany_top_out[26] ) , .p0 ( optlc_net_203 ) ) ; + .out ( chany_top_out[26] ) , .p0 ( optlc_net_181 ) ) ; sb_1__1__mux_2level_tapbuf_size6_3 mux_right_track_36 ( .in ( { chany_bottom_out[16] , chany_top_in[17] , right_bottom_grid_pin_39_[0] , chany_bottom_in[1] , @@ -48123,7 +51649,7 @@ sb_1__1__mux_2level_tapbuf_size6_3 mux_right_track_36 ( .sram ( mux_2level_tapbuf_size6_3_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_141 , SYNOPSYS_UNCONNECTED_142 , SYNOPSYS_UNCONNECTED_143 , SYNOPSYS_UNCONNECTED_144 } ) , - .out ( chanx_right_out[18] ) , .p0 ( optlc_net_198 ) ) ; + .out ( chanx_right_out[18] ) , .p0 ( optlc_net_178 ) ) ; sb_1__1__mux_2level_tapbuf_size6_4 mux_right_track_44 ( .in ( { chany_bottom_out[17] , chany_top_in[21] , right_bottom_grid_pin_40_[0] , chany_bottom_in[0] , @@ -48131,7 +51657,7 @@ sb_1__1__mux_2level_tapbuf_size6_4 mux_right_track_44 ( .sram ( mux_2level_tapbuf_size6_4_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_145 , SYNOPSYS_UNCONNECTED_146 , SYNOPSYS_UNCONNECTED_147 , SYNOPSYS_UNCONNECTED_148 } ) , - .out ( chanx_right_out[22] ) , .p0 ( optlc_net_203 ) ) ; + .out ( chanx_right_out[22] ) , .p0 ( optlc_net_175 ) ) ; sb_1__1__mux_2level_tapbuf_size6_5 mux_right_track_52 ( .in ( { chany_bottom_out[19] , chany_top_in[25] , right_bottom_grid_pin_41_[0] , chany_top_out[19] , @@ -48139,7 +51665,7 @@ sb_1__1__mux_2level_tapbuf_size6_5 mux_right_track_52 ( .sram ( mux_2level_tapbuf_size6_5_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_149 , SYNOPSYS_UNCONNECTED_150 , SYNOPSYS_UNCONNECTED_151 , SYNOPSYS_UNCONNECTED_152 } ) , - .out ( chanx_right_out[26] ) , .p0 ( optlc_net_200 ) ) ; + .out ( chanx_right_out[26] ) , .p0 ( optlc_net_178 ) ) ; sb_1__1__mux_2level_tapbuf_size6_6 mux_bottom_track_37 ( .in ( { chany_bottom_out[16] , chanx_right_in[1] , chanx_left_out[16] , bottom_left_grid_pin_47_[0] , chanx_right_out[16] , @@ -48147,7 +51673,7 @@ sb_1__1__mux_2level_tapbuf_size6_6 mux_bottom_track_37 ( .sram ( mux_2level_tapbuf_size6_6_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_153 , SYNOPSYS_UNCONNECTED_154 , SYNOPSYS_UNCONNECTED_155 , SYNOPSYS_UNCONNECTED_156 } ) , - .out ( chany_bottom_out[18] ) , .p0 ( optlc_net_198 ) ) ; + .out ( chany_bottom_out[18] ) , .p0 ( optlc_net_180 ) ) ; sb_1__1__mux_2level_tapbuf_size6_7 mux_bottom_track_45 ( .in ( { chany_bottom_out[17] , chanx_right_in[0] , chanx_left_out[17] , bottom_left_grid_pin_48_[0] , chanx_right_out[17] , @@ -48155,14 +51681,14 @@ sb_1__1__mux_2level_tapbuf_size6_7 mux_bottom_track_45 ( .sram ( mux_2level_tapbuf_size6_7_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_157 , SYNOPSYS_UNCONNECTED_158 , SYNOPSYS_UNCONNECTED_159 , SYNOPSYS_UNCONNECTED_160 } ) , - .out ( chany_bottom_out[22] ) , .p0 ( optlc_net_205 ) ) ; + .out ( chany_bottom_out[22] ) , .p0 ( optlc_net_176 ) ) ; sb_1__1__mux_2level_tapbuf_size6_8 mux_bottom_track_53 ( .in ( { chany_bottom_out[19] , chanx_left_out[19] , chanx_right_in[29] , bottom_left_grid_pin_49_[0] , chanx_left_in[0] , chanx_right_out[19] } ) , .sram ( mux_2level_tapbuf_size6_8_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_161 , SYNOPSYS_UNCONNECTED_162 , SYNOPSYS_UNCONNECTED_163 , SYNOPSYS_UNCONNECTED_164 } ) , - .out ( chany_bottom_out[26] ) , .p0 ( optlc_net_205 ) ) ; + .out ( chany_bottom_out[26] ) , .p0 ( optlc_net_176 ) ) ; sb_1__1__mux_2level_tapbuf_size6_9 mux_left_track_37 ( .in ( { chany_top_in[4] , chany_bottom_out[16] , chanx_left_out[16] , chany_top_out[16] , chany_bottom_in[17] , @@ -48170,7 +51696,7 @@ sb_1__1__mux_2level_tapbuf_size6_9 mux_left_track_37 ( .sram ( mux_2level_tapbuf_size6_9_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_165 , SYNOPSYS_UNCONNECTED_166 , SYNOPSYS_UNCONNECTED_167 , SYNOPSYS_UNCONNECTED_168 } ) , - .out ( chanx_left_out[18] ) , .p0 ( optlc_net_200 ) ) ; + .out ( chanx_left_out[18] ) , .p0 ( optlc_net_181 ) ) ; sb_1__1__mux_2level_tapbuf_size6_10 mux_left_track_45 ( .in ( { chany_top_in[2] , chany_bottom_out[17] , chanx_left_out[17] , chany_top_out[17] , chany_bottom_in[21] , @@ -48178,7 +51704,7 @@ sb_1__1__mux_2level_tapbuf_size6_10 mux_left_track_45 ( .sram ( mux_2level_tapbuf_size6_10_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_169 , SYNOPSYS_UNCONNECTED_170 , SYNOPSYS_UNCONNECTED_171 , SYNOPSYS_UNCONNECTED_172 } ) , - .out ( chanx_left_out[22] ) , .p0 ( optlc_net_197 ) ) ; + .out ( chanx_left_out[22] ) , .p0 ( optlc_net_174 ) ) ; sb_1__1__mux_2level_tapbuf_size6 mux_left_track_53 ( .in ( { chany_top_in[1] , chany_bottom_out[19] , chanx_left_out[19] , chany_top_out[19] , chany_bottom_in[25] , @@ -48186,7 +51712,7 @@ sb_1__1__mux_2level_tapbuf_size6 mux_left_track_53 ( .sram ( mux_2level_tapbuf_size6_11_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_173 , SYNOPSYS_UNCONNECTED_174 , SYNOPSYS_UNCONNECTED_175 , SYNOPSYS_UNCONNECTED_176 } ) , - .out ( chanx_left_out[26] ) , .p0 ( optlc_net_197 ) ) ; + .out ( chanx_left_out[26] ) , .p0 ( optlc_net_174 ) ) ; sb_1__1__mux_2level_tapbuf_size6_mem_0 mem_top_track_36 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( mux_2level_tapbuf_size9_mem_0_ccff_tail ) , @@ -48250,14 +51776,14 @@ sky130_fd_sc_hd__buf_4 Test_en_N_FTB01 ( .A ( Test_en_S_in ) , .X ( Test_en_N_out ) ) ; sky130_fd_sc_hd__buf_8 pReset_FTB00 ( .A ( pReset_E_in ) , .X ( pReset[0] ) ) ; sky130_fd_sc_hd__buf_1 pReset_N_FTB01 ( .A ( pReset_E_in ) , - .X ( aps_rename_523_ ) ) ; -sky130_fd_sc_hd__bufbuf_16 pReset_W_FTB01 ( .A ( pReset_E_in ) , - .X ( pReset_W_out ) ) ; + .X ( aps_rename_514_ ) ) ; +sky130_fd_sc_hd__buf_1 pReset_W_FTB01 ( .A ( pReset_E_in ) , + .X ( aps_rename_515_ ) ) ; sky130_fd_sc_hd__buf_4 pReset_E_FTB01 ( .A ( pReset_E_in ) , .X ( pReset_E_out ) ) ; sky130_fd_sc_hd__buf_4 Reset_N_FTB01 ( .A ( Reset_S_in ) , .X ( Reset_N_out ) ) ; -sky130_fd_sc_hd__buf_16 prog_clk_0_FTB00 ( .A ( prog_clk_0_N_in ) , +sky130_fd_sc_hd__buf_6 prog_clk_0_FTB00 ( .A ( prog_clk_0_N_in ) , .X ( prog_clk[0] ) ) ; sky130_fd_sc_hd__buf_8 FTB_69__68 ( .A ( chany_top_in[3] ) , .X ( chany_bottom_out[4] ) ) ; @@ -48411,31 +51937,30 @@ sky130_fd_sc_hd__buf_8 FTB_143__142 ( .A ( chanx_left_in[27] ) , .X ( chanx_right_out[28] ) ) ; sky130_fd_sc_hd__buf_8 FTB_144__143 ( .A ( chanx_left_in[28] ) , .X ( chanx_right_out[29] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_191 ( .A ( BUF_net_192 ) , .Y ( pReset_N_out ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_192 ( .A ( aps_rename_523_ ) , - .Y ( BUF_net_192 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_199 ( .LO ( SYNOPSYS_UNCONNECTED_177 ) , - .HI ( optlc_net_197 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_201 ( .LO ( SYNOPSYS_UNCONNECTED_178 ) , - .HI ( optlc_net_198 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_204 ( .LO ( SYNOPSYS_UNCONNECTED_179 ) , - .HI ( optlc_net_199 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_206 ( .LO ( SYNOPSYS_UNCONNECTED_180 ) , - .HI ( optlc_net_200 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_208 ( .LO ( SYNOPSYS_UNCONNECTED_181 ) , - .HI ( optlc_net_201 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_210 ( .LO ( SYNOPSYS_UNCONNECTED_182 ) , - .HI ( optlc_net_202 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_212 ( .LO ( SYNOPSYS_UNCONNECTED_183 ) , - .HI ( optlc_net_203 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_214 ( .LO ( SYNOPSYS_UNCONNECTED_184 ) , - .HI ( optlc_net_204 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_216 ( .LO ( SYNOPSYS_UNCONNECTED_185 ) , - .HI ( optlc_net_205 ) ) ; -sky130_fd_sc_hd__buf_6 ZBUF_6_f_inst_217 ( .A ( aps_rename_522_ ) , - .X ( chanx_right_out[3] ) ) ; -sky130_fd_sc_hd__buf_6 ZBUF_6_f_inst_218 ( .A ( aps_rename_521_ ) , - .X ( chanx_right_out[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_166 ( .A ( BUF_net_167 ) , .Y ( pReset_N_out ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_167 ( .A ( aps_rename_514_ ) , + .Y ( BUF_net_167 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_168 ( .A ( BUF_net_169 ) , .Y ( pReset_W_out ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_169 ( .A ( aps_rename_515_ ) , + .Y ( BUF_net_169 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_176 ( .LO ( SYNOPSYS_UNCONNECTED_177 ) , + .HI ( optlc_net_174 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_178 ( .LO ( SYNOPSYS_UNCONNECTED_178 ) , + .HI ( optlc_net_175 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_180 ( .LO ( SYNOPSYS_UNCONNECTED_179 ) , + .HI ( optlc_net_176 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_182 ( .LO ( SYNOPSYS_UNCONNECTED_180 ) , + .HI ( optlc_net_177 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_184 ( .LO ( SYNOPSYS_UNCONNECTED_181 ) , + .HI ( optlc_net_178 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_186 ( .LO ( SYNOPSYS_UNCONNECTED_182 ) , + .HI ( optlc_net_179 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_188 ( .LO ( SYNOPSYS_UNCONNECTED_183 ) , + .HI ( optlc_net_180 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_190 ( .LO ( SYNOPSYS_UNCONNECTED_184 ) , + .HI ( optlc_net_181 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_192 ( .LO ( SYNOPSYS_UNCONNECTED_185 ) , + .HI ( optlc_net_182 ) ) ; endmodule @@ -48510,12 +52035,18 @@ input [0:3] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -48526,12 +52057,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -48542,12 +52079,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -48606,7 +52149,7 @@ wire [0:0] mux_2level_tapbuf_basis_input4_mem4_0_out ; wire [0:0] mux_2level_tapbuf_basis_input4_mem4_1_out ; wire [0:0] mux_2level_tapbuf_basis_input4_mem4_2_out ; -sky130_fd_sc_hd__bufbuf_16 sky130_fd_sc_hd__buf_4_0_ ( +sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_4_0_ ( .A ( mux_2level_tapbuf_basis_input4_mem4_2_out[0] ) , .X ( out[0] ) ) ; sb_1__0__local_encoder2to4_6 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , .data ( local_encoder2to4_0_data ) , @@ -48640,12 +52183,18 @@ input [0:3] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -48656,12 +52205,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -48672,12 +52227,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -48737,7 +52298,8 @@ wire [0:0] mux_2level_tapbuf_basis_input4_mem4_1_out ; wire [0:0] mux_2level_tapbuf_basis_input4_mem4_2_out ; sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_4_0_ ( - .A ( mux_2level_tapbuf_basis_input4_mem4_2_out[0] ) , .X ( out[0] ) ) ; + .A ( mux_2level_tapbuf_basis_input4_mem4_2_out[0] ) , + .X ( aps_rename_505_ ) ) ; sb_1__0__local_encoder2to4_4 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , .data ( local_encoder2to4_0_data ) , .data_inv ( local_encoder2to4_0_data_inv ) ) ; @@ -48759,6 +52321,9 @@ sb_1__0__mux_2level_tapbuf_basis_input4_mem4_8 mux_l2_in_0_ ( .mem ( local_encoder2to4_1_data ) , .mem_inv ( local_encoder2to4_1_data_inv ) , .out ( mux_2level_tapbuf_basis_input4_mem4_2_out ) , .p0 ( p0 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_213 ( .A ( BUF_net_214 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_214 ( .A ( aps_rename_505_ ) , + .Y ( BUF_net_214 ) ) ; endmodule @@ -48770,12 +52335,18 @@ input [0:3] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -48786,12 +52357,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -48802,12 +52379,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -48866,7 +52449,7 @@ wire [0:0] mux_2level_tapbuf_basis_input4_mem4_0_out ; wire [0:0] mux_2level_tapbuf_basis_input4_mem4_1_out ; wire [0:0] mux_2level_tapbuf_basis_input4_mem4_2_out ; -sky130_fd_sc_hd__bufbuf_16 sky130_fd_sc_hd__buf_4_0_ ( +sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_4_0_ ( .A ( mux_2level_tapbuf_basis_input4_mem4_2_out[0] ) , .X ( out[0] ) ) ; sb_1__0__local_encoder2to4_2 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , .data ( local_encoder2to4_0_data ) , @@ -48920,9 +52503,13 @@ input [0:1] mem ; input [0:1] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -48934,12 +52521,18 @@ input [0:3] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -48950,12 +52543,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -48966,12 +52565,18 @@ input [0:3] mem ; input [0:3] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; scs8hd_muxinv2_1 scs8hd_muxinv2_1_1 ( .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0B ( mem_inv[2] ) , .S1B ( mem_inv[3] ) , .S0 ( mem[2] ) , - .S1 ( mem[3] ) , .Z ( out[0] ) ) ; + .S1 ( mem[3] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -49129,10 +52734,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -49144,10 +52753,14 @@ input [0:2] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -49158,10 +52771,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -49172,10 +52789,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -49265,10 +52886,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -49280,10 +52905,14 @@ input [0:2] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -49294,10 +52923,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -49308,10 +52941,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -49402,10 +53039,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -49417,10 +53058,14 @@ input [0:2] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -49431,10 +53076,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -49445,10 +53094,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -49500,8 +53153,6 @@ wire [0:0] mux_2level_tapbuf_basis_input3_mem3_1_out ; wire [0:0] mux_2level_tapbuf_basis_input3_mem3_2_out ; wire [0:0] mux_2level_tapbuf_basis_input3_mem3_3_out ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( mux_2level_tapbuf_basis_input3_mem3_3_out[0] ) , .X ( out[0] ) ) ; sb_1__0__local_encoder2to3_50 local_encoder2to3_0_ ( .addr ( sram[0:1] ) , .data ( local_encoder2to3_0_data ) , .data_inv ( local_encoder2to3_0_data_inv ) ) ; @@ -49528,6 +53179,9 @@ sb_1__0__mux_2level_tapbuf_basis_input3_mem3_66 mux_l2_in_0_ ( .mem ( local_encoder2to3_1_data ) , .mem_inv ( local_encoder2to3_1_data_inv ) , .out ( mux_2level_tapbuf_basis_input3_mem3_3_out ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_211 ( .A ( BUF_net_212 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_212 ( + .A ( mux_2level_tapbuf_basis_input3_mem3_3_out[0] ) , .Y ( BUF_net_212 ) ) ; endmodule @@ -49742,8 +53396,6 @@ input p0 ; wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ; wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) ) ; sb_1__0__mux_2level_tapbuf_basis_input2_mem1_35 mux_l1_in_0_ ( .in ( in ) , .mem ( sram[0] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) , @@ -49754,6 +53406,8 @@ sb_1__0__mux_2level_tapbuf_basis_input2_mem1 mux_l2_in_0_ ( .mem ( sram[1] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_192 ( + .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) ) ; endmodule @@ -49765,7 +53419,7 @@ input [0:0] mem_inv ; output [0:0] out ; input p0 ; -sky130_fd_sc_hd__mux2_2 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , +sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ; endmodule @@ -49802,8 +53456,9 @@ sb_1__0__mux_2level_tapbuf_basis_input2_mem1_34 mux_l2_in_0_ ( .mem ( sram[1] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_192 ( - .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_190 ( .A ( BUF_net_191 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_191 ( + .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_191 ) ) ; endmodule @@ -49852,9 +53507,9 @@ sb_1__0__mux_2level_tapbuf_basis_input2_mem1_32 mux_l2_in_0_ ( .mem ( sram[1] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_190 ( .A ( BUF_net_191 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_191 ( - .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_191 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_188 ( .A ( BUF_net_189 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_189 ( + .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_189 ) ) ; endmodule @@ -49903,9 +53558,9 @@ sb_1__0__mux_2level_tapbuf_basis_input2_mem1_30 mux_l2_in_0_ ( .mem ( sram[1] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_188 ( .A ( BUF_net_189 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_189 ( - .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_189 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_186 ( .A ( BUF_net_187 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_187 ( + .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_187 ) ) ; endmodule @@ -49954,9 +53609,9 @@ sb_1__0__mux_2level_tapbuf_basis_input2_mem1_28 mux_l2_in_0_ ( .mem ( sram[1] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_186 ( .A ( BUF_net_187 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_187 ( - .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_187 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_184 ( .A ( BUF_net_185 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_185 ( + .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_185 ) ) ; endmodule @@ -49995,8 +53650,6 @@ input p0 ; wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ; wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) ) ; sb_1__0__mux_2level_tapbuf_basis_input2_mem1_25 mux_l1_in_0_ ( .in ( in ) , .mem ( sram[0] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) , @@ -50007,6 +53660,9 @@ sb_1__0__mux_2level_tapbuf_basis_input2_mem1_26 mux_l2_in_0_ ( .mem ( sram[1] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_182 ( .A ( BUF_net_183 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_183 ( + .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_183 ) ) ; endmodule @@ -50055,9 +53711,9 @@ sb_1__0__mux_2level_tapbuf_basis_input2_mem1_24 mux_l2_in_0_ ( .mem ( sram[1] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_184 ( .A ( BUF_net_185 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_185 ( - .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_185 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_180 ( .A ( BUF_net_181 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_181 ( + .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_181 ) ) ; endmodule @@ -50119,7 +53775,7 @@ input [0:0] mem_inv ; output [0:0] out ; input p0 ; -sky130_fd_sc_hd__mux2_2 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , +sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ; endmodule @@ -50146,6 +53802,8 @@ input p0 ; wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ; wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) ) ; sb_1__0__mux_2level_tapbuf_basis_input2_mem1_19 mux_l1_in_0_ ( .in ( in ) , .mem ( sram[0] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) , @@ -50156,8 +53814,6 @@ sb_1__0__mux_2level_tapbuf_basis_input2_mem1_20 mux_l2_in_0_ ( .mem ( sram[1] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_183 ( - .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) ) ; endmodule @@ -50256,9 +53912,9 @@ sb_1__0__mux_2level_tapbuf_basis_input2_mem1_16 mux_l2_in_0_ ( .mem ( sram[1] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_181 ( .A ( BUF_net_182 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_182 ( - .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_182 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_178 ( .A ( BUF_net_179 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_179 ( + .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_179 ) ) ; endmodule @@ -50405,9 +54061,9 @@ sb_1__0__mux_2level_tapbuf_basis_input2_mem1_14 mux_l2_in_0_ ( .mem ( sram[1] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_4 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_2_out ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_179 ( .A ( BUF_net_180 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_180 ( - .A ( mux_2level_tapbuf_basis_input2_mem1_2_out[0] ) , .Y ( BUF_net_180 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_176 ( .A ( BUF_net_177 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_177 ( + .A ( mux_2level_tapbuf_basis_input2_mem1_2_out[0] ) , .Y ( BUF_net_177 ) ) ; endmodule @@ -50418,7 +54074,7 @@ input [0:0] mem ; input [0:0] mem_inv ; output [0:0] out ; -sky130_fd_sc_hd__mux2_2 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) , +sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ; endmodule @@ -50459,8 +54115,6 @@ wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ; wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ; wire [0:0] mux_2level_tapbuf_basis_input2_mem1_2_out ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( mux_2level_tapbuf_basis_input2_mem1_2_out[0] ) , .X ( out[0] ) ) ; sb_1__0__mux_2level_tapbuf_basis_input2_mem1_9 mux_l1_in_0_ ( .in ( in[0:1] ) , .mem ( sram[0] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) , @@ -50476,6 +54130,9 @@ sb_1__0__mux_2level_tapbuf_basis_input2_mem1_11 mux_l2_in_0_ ( .mem ( sram[1] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_4 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_2_out ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_174 ( .A ( BUF_net_175 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_175 ( + .A ( mux_2level_tapbuf_basis_input2_mem1_2_out[0] ) , .Y ( BUF_net_175 ) ) ; endmodule @@ -50542,9 +54199,9 @@ sb_1__0__mux_2level_tapbuf_basis_input2_mem1_8 mux_l2_in_0_ ( .mem ( sram[1] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_4 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_2_out ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_177 ( .A ( BUF_net_178 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_178 ( - .A ( mux_2level_tapbuf_basis_input2_mem1_2_out[0] ) , .Y ( BUF_net_178 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_172 ( .A ( BUF_net_173 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_173 ( + .A ( mux_2level_tapbuf_basis_input2_mem1_2_out[0] ) , .Y ( BUF_net_173 ) ) ; endmodule @@ -50611,9 +54268,9 @@ sb_1__0__mux_2level_tapbuf_basis_input2_mem1_5 mux_l2_in_0_ ( .mem ( sram[1] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_4 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_2_out ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_175 ( .A ( BUF_net_176 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_176 ( - .A ( mux_2level_tapbuf_basis_input2_mem1_2_out[0] ) , .Y ( BUF_net_176 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_170 ( .A ( BUF_net_171 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_171 ( + .A ( mux_2level_tapbuf_basis_input2_mem1_2_out[0] ) , .Y ( BUF_net_171 ) ) ; endmodule @@ -50665,6 +54322,8 @@ wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ; wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ; wire [0:0] mux_2level_tapbuf_basis_input2_mem1_2_out ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( mux_2level_tapbuf_basis_input2_mem1_2_out[0] ) , .X ( out[0] ) ) ; sb_1__0__mux_2level_tapbuf_basis_input2_mem1_0 mux_l1_in_0_ ( .in ( in[0:1] ) , .mem ( sram[0] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) , @@ -50680,9 +54339,6 @@ sb_1__0__mux_2level_tapbuf_basis_input2_mem1_2 mux_l2_in_0_ ( .mem ( sram[1] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_4 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_2_out ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_173 ( .A ( BUF_net_174 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_174 ( - .A ( mux_2level_tapbuf_basis_input2_mem1_2_out[0] ) , .Y ( BUF_net_174 ) ) ; endmodule @@ -50814,10 +54470,14 @@ input [0:2] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -50828,10 +54488,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -50897,8 +54561,9 @@ sb_1__0__mux_2level_tapbuf_basis_input3_mem3_62 mux_l2_in_0_ ( .mem ( local_encoder2to3_1_data ) , .mem_inv ( local_encoder2to3_1_data_inv ) , .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_172 ( - .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_209 ( .A ( BUF_net_210 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_210 ( + .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_210 ) ) ; endmodule @@ -50910,10 +54575,14 @@ input [0:2] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -50924,10 +54593,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -50993,8 +54666,9 @@ sb_1__0__mux_2level_tapbuf_basis_input3_mem3_60 mux_l2_in_0_ ( .mem ( local_encoder2to3_1_data ) , .mem_inv ( local_encoder2to3_1_data_inv ) , .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_171 ( - .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_168 ( .A ( BUF_net_169 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_169 ( + .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_169 ) ) ; endmodule @@ -51006,10 +54680,14 @@ input [0:2] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -51020,10 +54698,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -51089,9 +54771,8 @@ sb_1__0__mux_2level_tapbuf_basis_input3_mem3_58 mux_l2_in_0_ ( .mem ( local_encoder2to3_1_data ) , .mem_inv ( local_encoder2to3_1_data_inv ) , .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_169 ( .A ( BUF_net_170 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_170 ( - .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_170 ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_167 ( + .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .X ( out[0] ) ) ; endmodule @@ -51103,10 +54784,14 @@ input [0:2] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -51117,10 +54802,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -51186,9 +54875,9 @@ sb_1__0__mux_2level_tapbuf_basis_input3_mem3_56 mux_l2_in_0_ ( .mem ( local_encoder2to3_1_data ) , .mem_inv ( local_encoder2to3_1_data_inv ) , .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_167 ( .A ( BUF_net_168 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_168 ( - .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_168 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_165 ( .A ( BUF_net_166 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_166 ( + .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_166 ) ) ; endmodule @@ -51200,10 +54889,14 @@ input [0:2] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -51214,10 +54907,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -51283,9 +54980,8 @@ sb_1__0__mux_2level_tapbuf_basis_input3_mem3_54 mux_l2_in_0_ ( .mem ( local_encoder2to3_1_data ) , .mem_inv ( local_encoder2to3_1_data_inv ) , .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_165 ( .A ( BUF_net_166 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_166 ( - .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_166 ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_164 ( + .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .X ( out[0] ) ) ; endmodule @@ -51297,10 +54993,14 @@ input [0:2] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -51311,10 +55011,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -51364,6 +55068,8 @@ wire [0:2] local_encoder2to3_1_data_inv ; wire [0:0] mux_2level_tapbuf_basis_input3_mem3_0_out ; wire [0:0] mux_2level_tapbuf_basis_input3_mem3_1_out ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .X ( out[0] ) ) ; sb_1__0__local_encoder2to3_38 local_encoder2to3_0_ ( .addr ( sram[0:1] ) , .data ( local_encoder2to3_0_data ) , .data_inv ( local_encoder2to3_0_data_inv ) ) ; @@ -51380,9 +55086,6 @@ sb_1__0__mux_2level_tapbuf_basis_input3_mem3_52 mux_l2_in_0_ ( .mem ( local_encoder2to3_1_data ) , .mem_inv ( local_encoder2to3_1_data_inv ) , .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_163 ( .A ( BUF_net_164 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_164 ( - .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_164 ) ) ; endmodule @@ -51513,9 +55216,13 @@ input [0:1] mem ; input [0:1] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -51527,10 +55234,14 @@ input [0:2] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -51541,10 +55252,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -51616,9 +55331,9 @@ sb_1__0__mux_2level_tapbuf_basis_input2_mem2_15 mux_l1_in_1_ ( .in ( in[3:4] ) , .mem ( local_encoder2to3_0_data[0:1] ) , .mem_inv ( local_encoder2to3_0_data_inv[0:1] ) , .out ( mux_2level_tapbuf_basis_input2_mem2_0_out ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_161 ( .A ( BUF_net_162 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_162 ( - .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_162 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_162 ( .A ( BUF_net_163 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_163 ( + .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_163 ) ) ; endmodule @@ -51629,9 +55344,13 @@ input [0:1] mem ; input [0:1] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -51643,10 +55362,14 @@ input [0:2] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -51657,10 +55380,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -51732,9 +55459,9 @@ sb_1__0__mux_2level_tapbuf_basis_input2_mem2_14 mux_l1_in_1_ ( .in ( in[3:4] ) , .mem ( local_encoder2to3_0_data[0:1] ) , .mem_inv ( local_encoder2to3_0_data_inv[0:1] ) , .out ( mux_2level_tapbuf_basis_input2_mem2_0_out ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_159 ( .A ( BUF_net_160 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_160 ( - .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_160 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_160 ( .A ( BUF_net_161 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_161 ( + .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_161 ) ) ; endmodule @@ -51745,9 +55472,13 @@ input [0:1] mem ; input [0:1] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -51759,10 +55490,14 @@ input [0:2] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -51773,10 +55508,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -51848,9 +55587,9 @@ sb_1__0__mux_2level_tapbuf_basis_input2_mem2_13 mux_l1_in_1_ ( .in ( in[3:4] ) , .mem ( local_encoder2to3_0_data[0:1] ) , .mem_inv ( local_encoder2to3_0_data_inv[0:1] ) , .out ( mux_2level_tapbuf_basis_input2_mem2_0_out ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_157 ( .A ( BUF_net_158 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_158 ( - .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_158 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_158 ( .A ( BUF_net_159 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_159 ( + .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_159 ) ) ; endmodule @@ -51861,9 +55600,13 @@ input [0:1] mem ; input [0:1] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -51875,10 +55618,14 @@ input [0:2] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -51889,10 +55636,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -51964,9 +55715,9 @@ sb_1__0__mux_2level_tapbuf_basis_input2_mem2_12 mux_l1_in_1_ ( .in ( in[3:4] ) , .mem ( local_encoder2to3_0_data[0:1] ) , .mem_inv ( local_encoder2to3_0_data_inv[0:1] ) , .out ( mux_2level_tapbuf_basis_input2_mem2_0_out ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_205 ( .A ( BUF_net_206 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_206 ( - .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_206 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_156 ( .A ( BUF_net_157 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_157 ( + .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_157 ) ) ; endmodule @@ -51977,9 +55728,13 @@ input [0:1] mem ; input [0:1] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -51991,10 +55746,14 @@ input [0:2] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -52005,10 +55764,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -52059,6 +55822,8 @@ wire [0:0] mux_2level_tapbuf_basis_input2_mem2_0_out ; wire [0:0] mux_2level_tapbuf_basis_input3_mem3_0_out ; wire [0:0] mux_2level_tapbuf_basis_input3_mem3_1_out ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .X ( out[0] ) ) ; sb_1__0__local_encoder2to3_28 local_encoder2to3_0_ ( .addr ( sram[0:1] ) , .data ( local_encoder2to3_0_data ) , .data_inv ( local_encoder2to3_0_data_inv ) ) ; @@ -52080,9 +55845,6 @@ sb_1__0__mux_2level_tapbuf_basis_input2_mem2_11 mux_l1_in_1_ ( .in ( in[3:4] ) , .mem ( local_encoder2to3_0_data[0:1] ) , .mem_inv ( local_encoder2to3_0_data_inv[0:1] ) , .out ( mux_2level_tapbuf_basis_input2_mem2_0_out ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_155 ( .A ( BUF_net_156 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_156 ( - .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_156 ) ) ; endmodule @@ -52093,9 +55855,13 @@ input [0:1] mem ; input [0:1] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -52107,10 +55873,14 @@ input [0:2] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -52121,10 +55891,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -52196,9 +55970,8 @@ sb_1__0__mux_2level_tapbuf_basis_input2_mem2_10 mux_l1_in_1_ ( .in ( in[3:4] ) , .mem ( local_encoder2to3_0_data[0:1] ) , .mem_inv ( local_encoder2to3_0_data_inv[0:1] ) , .out ( mux_2level_tapbuf_basis_input2_mem2_0_out ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_153 ( .A ( BUF_net_154 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_154 ( - .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_154 ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_155 ( + .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .X ( out[0] ) ) ; endmodule @@ -52270,10 +56043,14 @@ input [0:2] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -52284,10 +56061,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -52298,10 +56079,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -52386,10 +56171,14 @@ input [0:2] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -52400,10 +56189,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -52414,10 +56207,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -52468,6 +56265,8 @@ wire [0:0] mux_2level_tapbuf_basis_input3_mem3_0_out ; wire [0:0] mux_2level_tapbuf_basis_input3_mem3_1_out ; wire [0:0] mux_2level_tapbuf_basis_input3_mem3_2_out ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( mux_2level_tapbuf_basis_input3_mem3_2_out[0] ) , .X ( out[0] ) ) ; sb_1__0__local_encoder2to3_22 local_encoder2to3_0_ ( .addr ( sram[0:1] ) , .data ( local_encoder2to3_0_data ) , .data_inv ( local_encoder2to3_0_data_inv ) ) ; @@ -52489,9 +56288,6 @@ sb_1__0__mux_2level_tapbuf_basis_input3_mem3_35 mux_l2_in_0_ ( .mem ( local_encoder2to3_1_data ) , .mem_inv ( local_encoder2to3_1_data_inv ) , .out ( mux_2level_tapbuf_basis_input3_mem3_2_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_151 ( .A ( BUF_net_152 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_152 ( - .A ( mux_2level_tapbuf_basis_input3_mem3_2_out[0] ) , .Y ( BUF_net_152 ) ) ; endmodule @@ -52503,10 +56299,14 @@ input [0:2] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -52517,10 +56317,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -52531,10 +56335,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -52606,9 +56414,9 @@ sb_1__0__mux_2level_tapbuf_basis_input3_mem3_32 mux_l2_in_0_ ( .mem ( local_encoder2to3_1_data ) , .mem_inv ( local_encoder2to3_1_data_inv ) , .out ( mux_2level_tapbuf_basis_input3_mem3_2_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_149 ( .A ( BUF_net_150 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_150 ( - .A ( mux_2level_tapbuf_basis_input3_mem3_2_out[0] ) , .Y ( BUF_net_150 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_153 ( .A ( BUF_net_154 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_154 ( + .A ( mux_2level_tapbuf_basis_input3_mem3_2_out[0] ) , .Y ( BUF_net_154 ) ) ; endmodule @@ -52800,7 +56608,7 @@ input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ropt_net_249 ) , +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ropt_net_255 ) , .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; @@ -52809,34 +56617,32 @@ sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__buf_1 FTB_21__20 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1414 ( .A ( ropt_net_250 ) , - .X ( copt_net_213 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1415 ( .A ( copt_net_213 ) , - .X ( copt_net_214 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1416 ( .A ( copt_net_214 ) , - .X ( copt_net_215 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1417 ( .A ( copt_net_218 ) , - .X ( copt_net_216 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1418 ( .A ( ccff_head[0] ) , - .X ( copt_net_217 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1419 ( .A ( copt_net_215 ) , - .X ( copt_net_218 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1444 ( .A ( copt_net_216 ) , - .X ( ropt_net_243 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1445 ( .A ( ropt_net_243 ) , - .X ( ropt_net_244 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1446 ( .A ( ropt_net_244 ) , - .X ( ropt_net_245 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1447 ( .A ( ropt_net_245 ) , - .X ( ropt_net_246 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1448 ( .A ( ropt_net_246 ) , - .X ( ropt_net_247 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1449 ( .A ( ropt_net_247 ) , - .X ( ropt_net_248 ) ) ; -sky130_fd_sc_hd__buf_4 ropt_h_inst_1450 ( .A ( ropt_net_248 ) , - .X ( ropt_net_249 ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 ropt_h_inst_1451 ( .A ( copt_net_217 ) , - .X ( ropt_net_250 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1435 ( .A ( ropt_net_258 ) , + .X ( copt_net_226 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1436 ( .A ( ccff_head[0] ) , + .X ( copt_net_227 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1437 ( .A ( copt_net_226 ) , + .X ( copt_net_228 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1438 ( .A ( copt_net_227 ) , + .X ( copt_net_229 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1439 ( .A ( copt_net_228 ) , + .X ( copt_net_230 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1440 ( .A ( copt_net_229 ) , + .X ( copt_net_231 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1461 ( .A ( ropt_net_254 ) , + .X ( ropt_net_252 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1462 ( .A ( ropt_net_252 ) , + .X ( ropt_net_253 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1463 ( .A ( copt_net_230 ) , + .X ( ropt_net_254 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1464 ( .A ( ropt_net_257 ) , + .X ( ropt_net_255 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1465 ( .A ( ropt_net_253 ) , + .X ( ropt_net_256 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1466 ( .A ( ropt_net_256 ) , + .X ( ropt_net_257 ) ) ; +sky130_fd_sc_hd__buf_1 ropt_h_inst_1467 ( .A ( copt_net_231 ) , + .X ( ropt_net_258 ) ) ; endmodule @@ -52848,9 +56654,13 @@ input [0:1] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( p0 ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -52861,10 +56671,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -52875,10 +56689,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -52889,10 +56707,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -52944,8 +56766,6 @@ wire [0:0] mux_2level_tapbuf_basis_input3_mem3_0_out ; wire [0:0] mux_2level_tapbuf_basis_input3_mem3_1_out ; wire [0:0] mux_2level_tapbuf_basis_input3_mem3_2_out ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( mux_2level_tapbuf_basis_input3_mem3_2_out[0] ) , .X ( out[0] ) ) ; sb_1__0__local_encoder2to3_18 local_encoder2to3_0_ ( .addr ( sram[0:1] ) , .data ( local_encoder2to3_0_data ) , .data_inv ( local_encoder2to3_0_data_inv ) ) ; @@ -52972,6 +56792,9 @@ sb_1__0__mux_2level_tapbuf_basis_input2_mem2_9 mux_l1_in_2_ ( .mem ( local_encoder2to3_0_data[0:1] ) , .mem_inv ( local_encoder2to3_0_data_inv[0:1] ) , .out ( mux_2level_tapbuf_basis_input2_mem2_0_out ) , .p0 ( p0 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_151 ( .A ( BUF_net_152 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_152 ( + .A ( mux_2level_tapbuf_basis_input3_mem3_2_out[0] ) , .Y ( BUF_net_152 ) ) ; endmodule @@ -52983,9 +56806,13 @@ input [0:1] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( p0 ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -52996,10 +56823,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -53010,10 +56841,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -53024,10 +56859,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -53118,9 +56957,13 @@ input [0:1] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( p0 ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -53131,10 +56974,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -53145,10 +56992,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -53159,10 +57010,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -53214,8 +57069,6 @@ wire [0:0] mux_2level_tapbuf_basis_input3_mem3_0_out ; wire [0:0] mux_2level_tapbuf_basis_input3_mem3_1_out ; wire [0:0] mux_2level_tapbuf_basis_input3_mem3_2_out ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( mux_2level_tapbuf_basis_input3_mem3_2_out[0] ) , .X ( out[0] ) ) ; sb_1__0__local_encoder2to3_14 local_encoder2to3_0_ ( .addr ( sram[0:1] ) , .data ( local_encoder2to3_0_data ) , .data_inv ( local_encoder2to3_0_data_inv ) ) ; @@ -53242,6 +57095,9 @@ sb_1__0__mux_2level_tapbuf_basis_input2_mem2_7 mux_l1_in_2_ ( .mem ( local_encoder2to3_0_data[0:1] ) , .mem_inv ( local_encoder2to3_0_data_inv[0:1] ) , .out ( mux_2level_tapbuf_basis_input2_mem2_0_out ) , .p0 ( p0 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_149 ( .A ( BUF_net_150 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_150 ( + .A ( mux_2level_tapbuf_basis_input3_mem3_2_out[0] ) , .Y ( BUF_net_150 ) ) ; endmodule @@ -53253,9 +57109,13 @@ input [0:1] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( p0 ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -53266,10 +57126,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -53280,10 +57144,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -53294,10 +57162,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -53349,8 +57221,6 @@ wire [0:0] mux_2level_tapbuf_basis_input3_mem3_0_out ; wire [0:0] mux_2level_tapbuf_basis_input3_mem3_1_out ; wire [0:0] mux_2level_tapbuf_basis_input3_mem3_2_out ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( mux_2level_tapbuf_basis_input3_mem3_2_out[0] ) , .X ( out[0] ) ) ; sb_1__0__local_encoder2to3_12 local_encoder2to3_0_ ( .addr ( sram[0:1] ) , .data ( local_encoder2to3_0_data ) , .data_inv ( local_encoder2to3_0_data_inv ) ) ; @@ -53377,6 +57247,9 @@ sb_1__0__mux_2level_tapbuf_basis_input2_mem2_6 mux_l1_in_2_ ( .mem ( local_encoder2to3_0_data[0:1] ) , .mem_inv ( local_encoder2to3_0_data_inv[0:1] ) , .out ( mux_2level_tapbuf_basis_input2_mem2_0_out ) , .p0 ( p0 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_147 ( .A ( BUF_net_148 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_148 ( + .A ( mux_2level_tapbuf_basis_input3_mem3_2_out[0] ) , .Y ( BUF_net_148 ) ) ; endmodule @@ -53388,9 +57261,13 @@ input [0:1] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( p0 ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -53401,10 +57278,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -53415,10 +57296,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -53429,10 +57314,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -53484,8 +57373,6 @@ wire [0:0] mux_2level_tapbuf_basis_input3_mem3_0_out ; wire [0:0] mux_2level_tapbuf_basis_input3_mem3_1_out ; wire [0:0] mux_2level_tapbuf_basis_input3_mem3_2_out ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( mux_2level_tapbuf_basis_input3_mem3_2_out[0] ) , .X ( out[0] ) ) ; sb_1__0__local_encoder2to3_10 local_encoder2to3_0_ ( .addr ( sram[0:1] ) , .data ( local_encoder2to3_0_data ) , .data_inv ( local_encoder2to3_0_data_inv ) ) ; @@ -53512,6 +57399,9 @@ sb_1__0__mux_2level_tapbuf_basis_input2_mem2_5 mux_l1_in_2_ ( .mem ( local_encoder2to3_0_data[0:1] ) , .mem_inv ( local_encoder2to3_0_data_inv[0:1] ) , .out ( mux_2level_tapbuf_basis_input2_mem2_0_out ) , .p0 ( p0 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_207 ( .A ( BUF_net_208 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_208 ( + .A ( mux_2level_tapbuf_basis_input3_mem3_2_out[0] ) , .Y ( BUF_net_208 ) ) ; endmodule @@ -53523,9 +57413,13 @@ input [0:1] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( p0 ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -53536,10 +57430,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -53550,10 +57448,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -53564,10 +57466,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -53619,6 +57525,8 @@ wire [0:0] mux_2level_tapbuf_basis_input3_mem3_0_out ; wire [0:0] mux_2level_tapbuf_basis_input3_mem3_1_out ; wire [0:0] mux_2level_tapbuf_basis_input3_mem3_2_out ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( mux_2level_tapbuf_basis_input3_mem3_2_out[0] ) , .X ( out[0] ) ) ; sb_1__0__local_encoder2to3_8 local_encoder2to3_0_ ( .addr ( sram[0:1] ) , .data ( local_encoder2to3_0_data ) , .data_inv ( local_encoder2to3_0_data_inv ) ) ; @@ -53645,9 +57553,6 @@ sb_1__0__mux_2level_tapbuf_basis_input2_mem2_4 mux_l1_in_2_ ( .mem ( local_encoder2to3_0_data[0:1] ) , .mem_inv ( local_encoder2to3_0_data_inv[0:1] ) , .out ( mux_2level_tapbuf_basis_input2_mem2_0_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_147 ( .A ( BUF_net_148 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_148 ( - .A ( mux_2level_tapbuf_basis_input3_mem3_2_out[0] ) , .Y ( BUF_net_148 ) ) ; endmodule @@ -53659,9 +57564,13 @@ input [0:1] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( p0 ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -53672,10 +57581,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -53686,10 +57599,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -53700,10 +57617,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -53755,8 +57676,6 @@ wire [0:0] mux_2level_tapbuf_basis_input3_mem3_0_out ; wire [0:0] mux_2level_tapbuf_basis_input3_mem3_1_out ; wire [0:0] mux_2level_tapbuf_basis_input3_mem3_2_out ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( mux_2level_tapbuf_basis_input3_mem3_2_out[0] ) , .X ( out[0] ) ) ; sb_1__0__local_encoder2to3_6 local_encoder2to3_0_ ( .addr ( sram[0:1] ) , .data ( local_encoder2to3_0_data ) , .data_inv ( local_encoder2to3_0_data_inv ) ) ; @@ -53783,6 +57702,9 @@ sb_1__0__mux_2level_tapbuf_basis_input2_mem2_3 mux_l1_in_2_ ( .mem ( local_encoder2to3_0_data[0:1] ) , .mem_inv ( local_encoder2to3_0_data_inv[0:1] ) , .out ( mux_2level_tapbuf_basis_input2_mem2_0_out ) , .p0 ( p0 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_215 ( .A ( BUF_net_216 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_216 ( + .A ( mux_2level_tapbuf_basis_input3_mem3_2_out[0] ) , .Y ( BUF_net_216 ) ) ; endmodule @@ -53794,9 +57716,13 @@ input [0:1] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( p0 ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -53807,10 +57733,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -53821,10 +57751,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -53835,10 +57769,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -53929,9 +57867,13 @@ input [0:1] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( p0 ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -53942,10 +57884,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -53956,10 +57902,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -53970,10 +57920,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -54025,8 +57979,6 @@ wire [0:0] mux_2level_tapbuf_basis_input3_mem3_0_out ; wire [0:0] mux_2level_tapbuf_basis_input3_mem3_1_out ; wire [0:0] mux_2level_tapbuf_basis_input3_mem3_2_out ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( mux_2level_tapbuf_basis_input3_mem3_2_out[0] ) , .X ( out[0] ) ) ; sb_1__0__local_encoder2to3_2 local_encoder2to3_0_ ( .addr ( sram[0:1] ) , .data ( local_encoder2to3_0_data ) , .data_inv ( local_encoder2to3_0_data_inv ) ) ; @@ -54053,6 +58005,9 @@ sb_1__0__mux_2level_tapbuf_basis_input2_mem2_1 mux_l1_in_2_ ( .mem ( local_encoder2to3_0_data[0:1] ) , .mem_inv ( local_encoder2to3_0_data_inv[0:1] ) , .out ( mux_2level_tapbuf_basis_input2_mem2_0_out ) , .p0 ( p0 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_205 ( .A ( BUF_net_206 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_206 ( + .A ( mux_2level_tapbuf_basis_input3_mem3_2_out[0] ) , .Y ( BUF_net_206 ) ) ; endmodule @@ -54064,9 +58019,13 @@ input [0:1] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( p0 ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -54077,10 +58036,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -54091,10 +58054,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -54105,10 +58072,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -54261,7 +58232,7 @@ output prog_clk_3_N_out ; input clk_3_S_in ; output clk_3_N_out ; -wire ropt_net_229 ; +wire ropt_net_242 ; wire [0:0] prog_clk ; wire prog_clk_0 ; wire [0:3] mux_2level_tapbuf_size10_0_sram ; @@ -54371,7 +58342,7 @@ sb_1__0__mux_2level_tapbuf_size7_0 mux_top_track_0 ( .sram ( mux_2level_tapbuf_size7_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 , SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) , - .out ( chany_top_out[0] ) , .p0 ( optlc_net_212 ) ) ; + .out ( chany_top_out[0] ) , .p0 ( optlc_net_220 ) ) ; sb_1__0__mux_2level_tapbuf_size7_1 mux_right_track_0 ( .in ( { chany_top_in[10] , chany_top_in[21] , right_bottom_grid_pin_1_[0] , right_bottom_grid_pin_7_[0] , @@ -54380,7 +58351,7 @@ sb_1__0__mux_2level_tapbuf_size7_1 mux_right_track_0 ( .sram ( mux_2level_tapbuf_size7_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 , SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 } ) , - .out ( chanx_right_out[0] ) , .p0 ( optlc_net_212 ) ) ; + .out ( chanx_right_out[0] ) , .p0 ( optlc_net_220 ) ) ; sb_1__0__mux_2level_tapbuf_size7_2 mux_right_track_12 ( .in ( { chany_top_in[4] , chany_top_in[15] , chany_top_in[26] , right_bottom_grid_pin_1_[0] , right_bottom_grid_pin_13_[0] , @@ -54388,7 +58359,7 @@ sb_1__0__mux_2level_tapbuf_size7_2 mux_right_track_12 ( .sram ( mux_2level_tapbuf_size7_2_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_9 , SYNOPSYS_UNCONNECTED_10 , SYNOPSYS_UNCONNECTED_11 , SYNOPSYS_UNCONNECTED_12 } ) , - .out ( chanx_right_out[6] ) , .p0 ( optlc_net_212 ) ) ; + .out ( chanx_right_out[6] ) , .p0 ( optlc_net_224 ) ) ; sb_1__0__mux_2level_tapbuf_size7_3 mux_right_track_20 ( .in ( { chany_top_in[5] , chany_top_in[16] , chany_top_in[27] , right_bottom_grid_pin_3_[0] , right_bottom_grid_pin_15_[0] , @@ -54396,7 +58367,7 @@ sb_1__0__mux_2level_tapbuf_size7_3 mux_right_track_20 ( .sram ( mux_2level_tapbuf_size7_3_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 , SYNOPSYS_UNCONNECTED_15 , SYNOPSYS_UNCONNECTED_16 } ) , - .out ( chanx_right_out[10] ) , .p0 ( optlc_net_209 ) ) ; + .out ( chanx_right_out[10] ) , .p0 ( optlc_net_224 ) ) ; sb_1__0__mux_2level_tapbuf_size7_4 mux_right_track_28 ( .in ( { chany_top_in[6] , chany_top_in[17] , chany_top_in[28] , right_bottom_grid_pin_5_[0] , right_bottom_grid_pin_17_[0] , @@ -54404,7 +58375,7 @@ sb_1__0__mux_2level_tapbuf_size7_4 mux_right_track_28 ( .sram ( mux_2level_tapbuf_size7_4_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_17 , SYNOPSYS_UNCONNECTED_18 , SYNOPSYS_UNCONNECTED_19 , SYNOPSYS_UNCONNECTED_20 } ) , - .out ( chanx_right_out[14] ) , .p0 ( optlc_net_209 ) ) ; + .out ( chanx_right_out[14] ) , .p0 ( optlc_net_224 ) ) ; sb_1__0__mux_2level_tapbuf_size7_5 mux_left_track_3 ( .in ( { chany_top_in[10] , chany_top_in[21] , chanx_left_out[7] , chanx_left_out[21] , left_bottom_grid_pin_3_[0] , @@ -54412,7 +58383,7 @@ sb_1__0__mux_2level_tapbuf_size7_5 mux_left_track_3 ( .sram ( mux_2level_tapbuf_size7_5_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_21 , SYNOPSYS_UNCONNECTED_22 , SYNOPSYS_UNCONNECTED_23 , SYNOPSYS_UNCONNECTED_24 } ) , - .out ( chanx_left_out[1] ) , .p0 ( optlc_net_207 ) ) ; + .out ( chanx_left_out[1] ) , .p0 ( optlc_net_223 ) ) ; sb_1__0__mux_2level_tapbuf_size7_6 mux_left_track_5 ( .in ( { chany_top_in[9] , chany_top_in[20] , chanx_left_out[8] , chanx_left_out[23] , left_bottom_grid_pin_5_[0] , @@ -54420,7 +58391,7 @@ sb_1__0__mux_2level_tapbuf_size7_6 mux_left_track_5 ( .sram ( mux_2level_tapbuf_size7_6_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_25 , SYNOPSYS_UNCONNECTED_26 , SYNOPSYS_UNCONNECTED_27 , SYNOPSYS_UNCONNECTED_28 } ) , - .out ( chanx_left_out[2] ) , .p0 ( optlc_net_210 ) ) ; + .out ( chanx_left_out[2] ) , .p0 ( optlc_net_221 ) ) ; sb_1__0__mux_2level_tapbuf_size7_7 mux_left_track_13 ( .in ( { chany_top_in[6] , chany_top_in[17] , chany_top_in[28] , chanx_left_out[12] , chanx_left_out[27] , left_bottom_grid_pin_1_[0] , @@ -54428,7 +58399,7 @@ sb_1__0__mux_2level_tapbuf_size7_7 mux_left_track_13 ( .sram ( mux_2level_tapbuf_size7_7_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_29 , SYNOPSYS_UNCONNECTED_30 , SYNOPSYS_UNCONNECTED_31 , SYNOPSYS_UNCONNECTED_32 } ) , - .out ( chanx_left_out[6] ) , .p0 ( optlc_net_211 ) ) ; + .out ( chanx_left_out[6] ) , .p0 ( optlc_net_223 ) ) ; sb_1__0__mux_2level_tapbuf_size7_8 mux_left_track_21 ( .in ( { chany_top_in[5] , chany_top_in[16] , chany_top_in[27] , chanx_left_out[13] , chanx_left_out[28] , left_bottom_grid_pin_3_[0] , @@ -54436,7 +58407,7 @@ sb_1__0__mux_2level_tapbuf_size7_8 mux_left_track_21 ( .sram ( mux_2level_tapbuf_size7_8_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_33 , SYNOPSYS_UNCONNECTED_34 , SYNOPSYS_UNCONNECTED_35 , SYNOPSYS_UNCONNECTED_36 } ) , - .out ( chanx_left_out[10] ) , .p0 ( optlc_net_207 ) ) ; + .out ( chanx_left_out[10] ) , .p0 ( optlc_net_223 ) ) ; sb_1__0__mux_2level_tapbuf_size7 mux_left_track_29 ( .in ( { chany_top_in[4] , chany_top_in[15] , chany_top_in[26] , chanx_left_out[15] , chanx_left_out[29] , left_bottom_grid_pin_5_[0] , @@ -54444,7 +58415,7 @@ sb_1__0__mux_2level_tapbuf_size7 mux_left_track_29 ( .sram ( mux_2level_tapbuf_size7_9_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_37 , SYNOPSYS_UNCONNECTED_38 , SYNOPSYS_UNCONNECTED_39 , SYNOPSYS_UNCONNECTED_40 } ) , - .out ( chanx_left_out[14] ) , .p0 ( optlc_net_210 ) ) ; + .out ( chanx_left_out[14] ) , .p0 ( optlc_net_223 ) ) ; sb_1__0__mux_2level_tapbuf_size7_mem_0 mem_top_track_0 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( mux_2level_tapbuf_size7_mem_0_ccff_tail ) , @@ -54501,7 +58472,7 @@ sb_1__0__mux_2level_tapbuf_size6_0 mux_top_track_2 ( .sram ( mux_2level_tapbuf_size6_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_41 , SYNOPSYS_UNCONNECTED_42 , SYNOPSYS_UNCONNECTED_43 , SYNOPSYS_UNCONNECTED_44 } ) , - .out ( chany_top_out[1] ) , .p0 ( optlc_net_210 ) ) ; + .out ( chany_top_out[1] ) , .p0 ( optlc_net_218 ) ) ; sb_1__0__mux_2level_tapbuf_size6_1 mux_top_track_6 ( .in ( { top_left_grid_pin_44_[0] , top_left_grid_pin_47_[0] , top_left_grid_pin_50_[0] , chanx_right_in[5] , chanx_left_out[9] , @@ -54509,7 +58480,7 @@ sb_1__0__mux_2level_tapbuf_size6_1 mux_top_track_6 ( .sram ( mux_2level_tapbuf_size6_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_45 , SYNOPSYS_UNCONNECTED_46 , SYNOPSYS_UNCONNECTED_47 , SYNOPSYS_UNCONNECTED_48 } ) , - .out ( chany_top_out[3] ) , .p0 ( optlc_net_212 ) ) ; + .out ( chany_top_out[3] ) , .p0 ( optlc_net_218 ) ) ; sb_1__0__mux_2level_tapbuf_size6 mux_top_track_8 ( .in ( { chany_top_out[19] , top_left_grid_pin_48_[0] , top_left_grid_pin_51_[0] , chanx_right_in[9] , chanx_left_out[11] , @@ -54517,7 +58488,7 @@ sb_1__0__mux_2level_tapbuf_size6 mux_top_track_8 ( .sram ( mux_2level_tapbuf_size6_2_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_49 , SYNOPSYS_UNCONNECTED_50 , SYNOPSYS_UNCONNECTED_51 , SYNOPSYS_UNCONNECTED_52 } ) , - .out ( chany_top_out[4] ) , .p0 ( optlc_net_208 ) ) ; + .out ( chany_top_out[4] ) , .p0 ( optlc_net_225 ) ) ; sb_1__0__mux_2level_tapbuf_size6_mem_0 mem_top_track_2 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( mux_2level_tapbuf_size7_mem_0_ccff_tail ) , @@ -54539,42 +58510,42 @@ sb_1__0__mux_2level_tapbuf_size5_0 mux_top_track_4 ( .sram ( mux_2level_tapbuf_size5_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_53 , SYNOPSYS_UNCONNECTED_54 , SYNOPSYS_UNCONNECTED_55 , SYNOPSYS_UNCONNECTED_56 } ) , - .out ( chany_top_out[2] ) , .p0 ( optlc_net_210 ) ) ; + .out ( chany_top_out[2] ) , .p0 ( optlc_net_223 ) ) ; sb_1__0__mux_2level_tapbuf_size5_1 mux_top_track_10 ( .in ( { top_left_grid_pin_46_[0] , top_left_grid_pin_49_[0] , chanx_left_out[12] , chanx_right_in[13] , chanx_right_out[12] } ) , .sram ( mux_2level_tapbuf_size5_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_57 , SYNOPSYS_UNCONNECTED_58 , SYNOPSYS_UNCONNECTED_59 , SYNOPSYS_UNCONNECTED_60 } ) , - .out ( chany_top_out[5] ) , .p0 ( optlc_net_210 ) ) ; + .out ( chany_top_out[5] ) , .p0 ( optlc_net_222 ) ) ; sb_1__0__mux_2level_tapbuf_size5_2 mux_right_track_36 ( .in ( { chany_top_in[7] , chany_top_in[18] , chany_top_in[29] , right_bottom_grid_pin_7_[0] , chanx_right_out[16] } ) , .sram ( mux_2level_tapbuf_size5_2_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_61 , SYNOPSYS_UNCONNECTED_62 , SYNOPSYS_UNCONNECTED_63 , SYNOPSYS_UNCONNECTED_64 } ) , - .out ( chanx_right_out[18] ) , .p0 ( optlc_net_209 ) ) ; + .out ( chanx_right_out[18] ) , .p0 ( optlc_net_220 ) ) ; sb_1__0__mux_2level_tapbuf_size5_3 mux_left_track_37 ( .in ( { chany_top_in[3] , chany_top_in[14] , chany_top_in[25] , chanx_left_out[16] , left_bottom_grid_pin_7_[0] } ) , .sram ( mux_2level_tapbuf_size5_3_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_65 , SYNOPSYS_UNCONNECTED_66 , SYNOPSYS_UNCONNECTED_67 , SYNOPSYS_UNCONNECTED_68 } ) , - .out ( chanx_left_out[18] ) , .p0 ( optlc_net_210 ) ) ; + .out ( chanx_left_out[18] ) , .p0 ( optlc_net_223 ) ) ; sb_1__0__mux_2level_tapbuf_size5_4 mux_left_track_45 ( .in ( { chany_top_in[2] , chany_top_in[13] , chany_top_in[24] , chanx_left_out[17] , left_bottom_grid_pin_9_[0] } ) , .sram ( mux_2level_tapbuf_size5_4_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_69 , SYNOPSYS_UNCONNECTED_70 , SYNOPSYS_UNCONNECTED_71 , SYNOPSYS_UNCONNECTED_72 } ) , - .out ( chanx_left_out[22] ) , .p0 ( optlc_net_210 ) ) ; + .out ( chanx_left_out[22] ) , .p0 ( optlc_net_221 ) ) ; sb_1__0__mux_2level_tapbuf_size5 mux_left_track_53 ( .in ( { chany_top_in[1] , chany_top_in[12] , chany_top_in[23] , chanx_left_out[19] , left_bottom_grid_pin_11_[0] } ) , .sram ( mux_2level_tapbuf_size5_5_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_73 , SYNOPSYS_UNCONNECTED_74 , SYNOPSYS_UNCONNECTED_75 , SYNOPSYS_UNCONNECTED_76 } ) , - .out ( chanx_left_out[26] ) , .p0 ( optlc_net_210 ) ) ; + .out ( chanx_left_out[26] ) , .p0 ( optlc_net_221 ) ) ; sb_1__0__mux_2level_tapbuf_size5_mem_0 mem_top_track_4 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( mux_2level_tapbuf_size6_mem_0_ccff_tail ) , @@ -54610,42 +58581,42 @@ sb_1__0__mux_2level_tapbuf_size4_0 mux_top_track_12 ( .sram ( mux_2level_tapbuf_size4_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_77 , SYNOPSYS_UNCONNECTED_78 , SYNOPSYS_UNCONNECTED_79 , SYNOPSYS_UNCONNECTED_80 } ) , - .out ( chany_top_out[6] ) , .p0 ( optlc_net_208 ) ) ; + .out ( chany_top_out[6] ) , .p0 ( optlc_net_224 ) ) ; sb_1__0__mux_2level_tapbuf_size4_1 mux_top_track_14 ( .in ( { chany_top_out[19] , chanx_left_out[15] , chanx_right_in[21] , chanx_right_out[15] } ) , .sram ( mux_2level_tapbuf_size4_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_81 , SYNOPSYS_UNCONNECTED_82 , SYNOPSYS_UNCONNECTED_83 , SYNOPSYS_UNCONNECTED_84 } ) , - .out ( chany_top_out[7] ) , .p0 ( optlc_net_208 ) ) ; + .out ( chany_top_out[7] ) , .p0 ( optlc_net_222 ) ) ; sb_1__0__mux_2level_tapbuf_size4_2 mux_top_track_16 ( .in ( { top_left_grid_pin_46_[0] , chanx_left_out[16] , chanx_right_in[25] , chanx_right_out[16] } ) , .sram ( mux_2level_tapbuf_size4_2_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_85 , SYNOPSYS_UNCONNECTED_86 , SYNOPSYS_UNCONNECTED_87 , SYNOPSYS_UNCONNECTED_88 } ) , - .out ( chany_top_out[8] ) , .p0 ( optlc_net_208 ) ) ; + .out ( chany_top_out[8] ) , .p0 ( optlc_net_220 ) ) ; sb_1__0__mux_2level_tapbuf_size4_3 mux_top_track_18 ( .in ( { top_left_grid_pin_47_[0] , chanx_left_out[17] , chanx_right_in[29] , chanx_right_out[17] } ) , .sram ( mux_2level_tapbuf_size4_3_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_89 , SYNOPSYS_UNCONNECTED_90 , SYNOPSYS_UNCONNECTED_91 , SYNOPSYS_UNCONNECTED_92 } ) , - .out ( chany_top_out[9] ) , .p0 ( optlc_net_208 ) ) ; + .out ( chany_top_out[9] ) , .p0 ( optlc_net_220 ) ) ; sb_1__0__mux_2level_tapbuf_size4_4 mux_right_track_44 ( .in ( { chany_top_in[8] , chany_top_in[19] , right_bottom_grid_pin_9_[0] , chanx_right_out[17] } ) , .sram ( mux_2level_tapbuf_size4_4_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_93 , SYNOPSYS_UNCONNECTED_94 , SYNOPSYS_UNCONNECTED_95 , SYNOPSYS_UNCONNECTED_96 } ) , - .out ( chanx_right_out[22] ) , .p0 ( optlc_net_209 ) ) ; + .out ( chanx_right_out[22] ) , .p0 ( optlc_net_218 ) ) ; sb_1__0__mux_2level_tapbuf_size4 mux_right_track_52 ( .in ( { chany_top_in[9] , chany_top_in[20] , right_bottom_grid_pin_11_[0] , chanx_right_out[19] } ) , .sram ( mux_2level_tapbuf_size4_5_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_97 , SYNOPSYS_UNCONNECTED_98 , SYNOPSYS_UNCONNECTED_99 , SYNOPSYS_UNCONNECTED_100 } ) , - .out ( chanx_right_out[26] ) , .p0 ( optlc_net_208 ) ) ; + .out ( chanx_right_out[26] ) , .p0 ( optlc_net_218 ) ) ; sb_1__0__mux_2level_tapbuf_size4_mem_0 mem_top_track_12 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( mux_2level_tapbuf_size5_mem_1_ccff_tail ) , @@ -54681,31 +58652,31 @@ sb_1__0__mux_2level_tapbuf_size3_0 mux_top_track_20 ( chanx_right_out[19] } ) , .sram ( mux_2level_tapbuf_size3_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_101 , SYNOPSYS_UNCONNECTED_102 } ) , - .out ( chany_top_out[10] ) , .p0 ( optlc_net_212 ) ) ; + .out ( chany_top_out[10] ) , .p0 ( optlc_net_225 ) ) ; sb_1__0__mux_2level_tapbuf_size3_1 mux_top_track_22 ( .in ( { top_left_grid_pin_49_[0] , chanx_left_out[20] , chanx_right_out[20] } ) , .sram ( mux_2level_tapbuf_size3_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_103 , SYNOPSYS_UNCONNECTED_104 } ) , - .out ( chany_top_out[11] ) , .p0 ( optlc_net_212 ) ) ; + .out ( chany_top_out[11] ) , .p0 ( optlc_net_217 ) ) ; sb_1__0__mux_2level_tapbuf_size3_2 mux_top_track_24 ( .in ( { top_left_grid_pin_50_[0] , chanx_left_out[21] , chanx_right_out[21] } ) , .sram ( mux_2level_tapbuf_size3_2_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_105 , SYNOPSYS_UNCONNECTED_106 } ) , - .out ( chany_top_out[12] ) , .p0 ( optlc_net_212 ) ) ; + .out ( chany_top_out[12] ) , .p0 ( optlc_net_217 ) ) ; sb_1__0__mux_2level_tapbuf_size3_3 mux_top_track_26 ( .in ( { top_left_grid_pin_51_[0] , chanx_left_out[23] , chanx_right_out[23] } ) , .sram ( mux_2level_tapbuf_size3_3_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_107 , SYNOPSYS_UNCONNECTED_108 } ) , - .out ( chany_top_out[13] ) , .p0 ( optlc_net_212 ) ) ; + .out ( chany_top_out[13] ) , .p0 ( optlc_net_222 ) ) ; sb_1__0__mux_2level_tapbuf_size3 mux_top_track_36 ( .in ( { top_left_grid_pin_44_[0] , chanx_left_out[29] , chanx_right_out[29] } ) , .sram ( mux_2level_tapbuf_size3_4_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_109 , SYNOPSYS_UNCONNECTED_110 } ) , - .out ( chany_top_out[18] ) , .p0 ( optlc_net_211 ) ) ; + .out ( chany_top_out[18] ) , .p0 ( optlc_net_217 ) ) ; sb_1__0__mux_2level_tapbuf_size3_mem_0 mem_top_track_20 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( mux_2level_tapbuf_size4_mem_3_ccff_tail ) , @@ -54735,57 +58706,57 @@ sb_1__0__mux_2level_tapbuf_size2_0 mux_top_track_28 ( .in ( { chanx_left_out[24] , chanx_right_out[24] } ) , .sram ( mux_2level_tapbuf_size2_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_111 , SYNOPSYS_UNCONNECTED_112 } ) , - .out ( chany_top_out[14] ) , .p0 ( optlc_net_211 ) ) ; + .out ( chany_top_out[14] ) , .p0 ( optlc_net_222 ) ) ; sb_1__0__mux_2level_tapbuf_size2_1 mux_top_track_30 ( .in ( { chanx_left_out[25] , chanx_right_out[25] } ) , .sram ( mux_2level_tapbuf_size2_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_113 , SYNOPSYS_UNCONNECTED_114 } ) , - .out ( chany_top_out[15] ) , .p0 ( optlc_net_209 ) ) ; + .out ( chany_top_out[15] ) , .p0 ( optlc_net_222 ) ) ; sb_1__0__mux_2level_tapbuf_size2_2 mux_top_track_32 ( .in ( { chanx_left_out[27] , chanx_right_out[27] } ) , .sram ( mux_2level_tapbuf_size2_2_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_115 , SYNOPSYS_UNCONNECTED_116 } ) , - .out ( chany_top_out[16] ) , .p0 ( optlc_net_211 ) ) ; + .out ( chany_top_out[16] ) , .p0 ( optlc_net_222 ) ) ; sb_1__0__mux_2level_tapbuf_size2_3 mux_top_track_34 ( .in ( { chanx_left_out[28] , chanx_right_out[28] } ) , .sram ( mux_2level_tapbuf_size2_3_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_117 , SYNOPSYS_UNCONNECTED_118 } ) , - .out ( chany_top_out[17] ) , .p0 ( optlc_net_211 ) ) ; + .out ( chany_top_out[17] ) , .p0 ( optlc_net_222 ) ) ; sb_1__0__mux_2level_tapbuf_size2_4 mux_top_track_40 ( .in ( { top_left_grid_pin_46_[0] , chanx_left_in[29] } ) , .sram ( mux_2level_tapbuf_size2_4_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_119 , SYNOPSYS_UNCONNECTED_120 } ) , - .out ( chany_top_out[20] ) , .p0 ( optlc_net_207 ) ) ; + .out ( chany_top_out[20] ) , .p0 ( optlc_net_217 ) ) ; sb_1__0__mux_2level_tapbuf_size2_5 mux_top_track_42 ( .in ( { top_left_grid_pin_47_[0] , chanx_left_in[25] } ) , .sram ( mux_2level_tapbuf_size2_5_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_121 , SYNOPSYS_UNCONNECTED_122 } ) , - .out ( chany_top_out[21] ) , .p0 ( optlc_net_207 ) ) ; + .out ( chany_top_out[21] ) , .p0 ( optlc_net_217 ) ) ; sb_1__0__mux_2level_tapbuf_size2_6 mux_top_track_44 ( .in ( { top_left_grid_pin_48_[0] , chanx_left_in[21] } ) , .sram ( mux_2level_tapbuf_size2_6_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_123 , SYNOPSYS_UNCONNECTED_124 } ) , - .out ( chany_top_out[22] ) , .p0 ( optlc_net_207 ) ) ; + .out ( chany_top_out[22] ) , .p0 ( optlc_net_217 ) ) ; sb_1__0__mux_2level_tapbuf_size2_7 mux_top_track_46 ( .in ( { top_left_grid_pin_49_[0] , chanx_left_in[17] } ) , .sram ( mux_2level_tapbuf_size2_7_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_125 , SYNOPSYS_UNCONNECTED_126 } ) , - .out ( chany_top_out[23] ) , .p0 ( optlc_net_207 ) ) ; + .out ( chany_top_out[23] ) , .p0 ( optlc_net_217 ) ) ; sb_1__0__mux_2level_tapbuf_size2_8 mux_top_track_48 ( .in ( { top_left_grid_pin_50_[0] , chanx_left_in[13] } ) , .sram ( mux_2level_tapbuf_size2_8_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_127 , SYNOPSYS_UNCONNECTED_128 } ) , - .out ( chany_top_out[24] ) , .p0 ( optlc_net_211 ) ) ; + .out ( chany_top_out[24] ) , .p0 ( optlc_net_217 ) ) ; sb_1__0__mux_2level_tapbuf_size2_9 mux_top_track_50 ( .in ( { top_left_grid_pin_51_[0] , chanx_left_in[9] } ) , .sram ( mux_2level_tapbuf_size2_9_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_129 , SYNOPSYS_UNCONNECTED_130 } ) , - .out ( chany_top_out[25] ) , .p0 ( optlc_net_211 ) ) ; + .out ( chany_top_out[25] ) , .p0 ( optlc_net_217 ) ) ; sb_1__0__mux_2level_tapbuf_size2 mux_top_track_58 ( .in ( { chanx_right_in[0] , chanx_left_in[1] } ) , .sram ( mux_2level_tapbuf_size2_10_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_131 , SYNOPSYS_UNCONNECTED_132 } ) , - .out ( chany_top_out[29] ) , .p0 ( optlc_net_211 ) ) ; + .out ( chany_top_out[29] ) , .p0 ( optlc_net_224 ) ) ; sb_1__0__mux_2level_tapbuf_size2_mem_0 mem_top_track_28 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( mux_2level_tapbuf_size3_mem_3_ccff_tail ) , @@ -54849,7 +58820,7 @@ sb_1__0__mux_2level_tapbuf_size8_0 mux_right_track_2 ( .sram ( mux_2level_tapbuf_size8_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_133 , SYNOPSYS_UNCONNECTED_134 , SYNOPSYS_UNCONNECTED_135 , SYNOPSYS_UNCONNECTED_136 } ) , - .out ( chanx_right_out[1] ) , .p0 ( optlc_net_209 ) ) ; + .out ( chanx_right_out[1] ) , .p0 ( optlc_net_220 ) ) ; sb_1__0__mux_2level_tapbuf_size8_1 mux_right_track_4 ( .in ( { chany_top_in[1] , chany_top_in[12] , chany_top_in[23] , right_bottom_grid_pin_5_[0] , right_bottom_grid_pin_11_[0] , @@ -54858,7 +58829,7 @@ sb_1__0__mux_2level_tapbuf_size8_1 mux_right_track_4 ( .sram ( mux_2level_tapbuf_size8_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_137 , SYNOPSYS_UNCONNECTED_138 , SYNOPSYS_UNCONNECTED_139 , SYNOPSYS_UNCONNECTED_140 } ) , - .out ( chanx_right_out[2] ) , .p0 ( optlc_net_208 ) ) ; + .out ( chanx_right_out[2] ) , .p0 ( optlc_net_219 ) ) ; sb_1__0__mux_2level_tapbuf_size8 mux_left_track_1 ( .in ( { chany_top_in[0] , chany_top_in[11] , chany_top_in[22] , chanx_left_out[4] , chanx_left_out[20] , left_bottom_grid_pin_1_[0] , @@ -54866,7 +58837,7 @@ sb_1__0__mux_2level_tapbuf_size8 mux_left_track_1 ( .sram ( mux_2level_tapbuf_size8_2_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_141 , SYNOPSYS_UNCONNECTED_142 , SYNOPSYS_UNCONNECTED_143 , SYNOPSYS_UNCONNECTED_144 } ) , - .out ( chanx_left_out[0] ) , .p0 ( optlc_net_212 ) ) ; + .out ( chanx_left_out[0] ) , .p0 ( optlc_net_221 ) ) ; sb_1__0__mux_2level_tapbuf_size8_mem_0 mem_right_track_2 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( mux_2level_tapbuf_size7_mem_1_ccff_tail ) , @@ -54891,8 +58862,8 @@ sb_1__0__mux_2level_tapbuf_size10 mux_right_track_6 ( .sram ( mux_2level_tapbuf_size10_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_145 , SYNOPSYS_UNCONNECTED_146 , SYNOPSYS_UNCONNECTED_147 , SYNOPSYS_UNCONNECTED_148 } ) , - .out ( { aps_rename_505_ } ) , - .p0 ( optlc_net_208 ) ) ; + .out ( { aps_rename_506_ } ) , + .p0 ( optlc_net_219 ) ) ; sb_1__0__mux_2level_tapbuf_size10_mem mem_right_track_6 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( mux_2level_tapbuf_size8_mem_1_ccff_tail ) , @@ -54906,7 +58877,8 @@ sb_1__0__mux_2level_tapbuf_size9_0 mux_right_track_10 ( .sram ( mux_2level_tapbuf_size9_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_149 , SYNOPSYS_UNCONNECTED_150 , SYNOPSYS_UNCONNECTED_151 , SYNOPSYS_UNCONNECTED_152 } ) , - .out ( chanx_right_out[5] ) , .p0 ( optlc_net_208 ) ) ; + .out ( { aps_rename_507_ } ) , + .p0 ( optlc_net_220 ) ) ; sb_1__0__mux_2level_tapbuf_size9_1 mux_left_track_7 ( .in ( { chany_top_in[8] , chany_top_in[19] , chanx_left_out[9] , chanx_left_out[24] , left_bottom_grid_pin_1_[0] , @@ -54915,8 +58887,7 @@ sb_1__0__mux_2level_tapbuf_size9_1 mux_left_track_7 ( .sram ( mux_2level_tapbuf_size9_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_153 , SYNOPSYS_UNCONNECTED_154 , SYNOPSYS_UNCONNECTED_155 , SYNOPSYS_UNCONNECTED_156 } ) , - .out ( { aps_rename_506_ } ) , - .p0 ( optlc_net_210 ) ) ; + .out ( chanx_left_out[3] ) , .p0 ( optlc_net_221 ) ) ; sb_1__0__mux_2level_tapbuf_size9 mux_left_track_11 ( .in ( { chany_top_in[7] , chany_top_in[18] , chany_top_in[29] , chanx_left_out[11] , chanx_left_out[25] , left_bottom_grid_pin_3_[0] , @@ -54925,7 +58896,8 @@ sb_1__0__mux_2level_tapbuf_size9 mux_left_track_11 ( .sram ( mux_2level_tapbuf_size9_2_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_157 , SYNOPSYS_UNCONNECTED_158 , SYNOPSYS_UNCONNECTED_159 , SYNOPSYS_UNCONNECTED_160 } ) , - .out ( chanx_left_out[5] ) , .p0 ( optlc_net_207 ) ) ; + .out ( { aps_rename_508_ } ) , + .p0 ( optlc_net_223 ) ) ; sb_1__0__mux_2level_tapbuf_size9_mem_0 mem_right_track_10 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( mux_2level_tapbuf_size10_mem_0_ccff_tail ) , @@ -54941,23 +58913,23 @@ sb_1__0__mux_2level_tapbuf_size9_mem mem_left_track_11 ( .pReset ( pReset ) , .ccff_head ( mux_2level_tapbuf_size9_mem_1_ccff_tail ) , .ccff_tail ( mux_2level_tapbuf_size9_mem_2_ccff_tail ) , .mem_out ( mux_2level_tapbuf_size9_2_sram ) ) ; -sky130_fd_sc_hd__conb_1 optlc_209 ( .LO ( SYNOPSYS_UNCONNECTED_161 ) , - .HI ( optlc_net_207 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_219 ( .LO ( SYNOPSYS_UNCONNECTED_161 ) , + .HI ( optlc_net_217 ) ) ; sky130_fd_sc_hd__buf_8 pReset_FTB00 ( .A ( pReset_E_in ) , .X ( pReset[0] ) ) ; sky130_fd_sc_hd__buf_1 pReset_N_FTB01 ( .A ( pReset_E_in ) , - .X ( aps_rename_507_ ) ) ; + .X ( aps_rename_509_ ) ) ; sky130_fd_sc_hd__bufbuf_16 pReset_W_FTB01 ( .A ( pReset_E_in ) , .X ( pReset_W_out ) ) ; sky130_fd_sc_hd__buf_1 pReset_E_FTB01 ( .A ( pReset_E_in ) , - .X ( aps_rename_508_ ) ) ; -sky130_fd_sc_hd__conb_1 optlc_211 ( .LO ( SYNOPSYS_UNCONNECTED_162 ) , - .HI ( optlc_net_208 ) ) ; + .X ( aps_rename_510_ ) ) ; +sky130_fd_sc_hd__conb_1 optlc_223 ( .LO ( SYNOPSYS_UNCONNECTED_162 ) , + .HI ( optlc_net_218 ) ) ; sky130_fd_sc_hd__buf_1 prog_clk_0_FTB00 ( .A ( prog_clk_0_N_in ) , .X ( prog_clk[0] ) ) ; sky130_fd_sc_hd__buf_1 prog_clk_3_N_FTB01 ( .A ( prog_clk_3_S_in ) , - .X ( aps_rename_509_ ) ) ; + .X ( aps_rename_511_ ) ) ; sky130_fd_sc_hd__buf_1 clk_3_N_FTB01 ( .A ( clk_3_S_in ) , - .X ( aps_rename_510_ ) ) ; + .X ( aps_rename_512_ ) ) ; sky130_fd_sc_hd__buf_8 FTB_105__104 ( .A ( top_left_grid_pin_45_[0] ) , .X ( chany_top_out[19] ) ) ; sky130_fd_sc_hd__buf_8 FTB_106__105 ( .A ( chanx_right_in[3] ) , @@ -55003,7 +58975,7 @@ sky130_fd_sc_hd__buf_8 FTB_125__124 ( .A ( chanx_left_in[2] ) , sky130_fd_sc_hd__buf_8 FTB_126__125 ( .A ( chanx_left_in[3] ) , .X ( chanx_right_out[4] ) ) ; sky130_fd_sc_hd__buf_6 FTB_127__126 ( .A ( chanx_left_in[4] ) , - .X ( ropt_net_229 ) ) ; + .X ( ropt_net_242 ) ) ; sky130_fd_sc_hd__buf_8 FTB_128__127 ( .A ( chanx_left_in[5] ) , .X ( chany_top_out[26] ) ) ; sky130_fd_sc_hd__buf_8 FTB_129__128 ( .A ( chanx_left_in[6] ) , @@ -55047,32 +59019,40 @@ sky130_fd_sc_hd__inv_8 BINV_R_195 ( .A ( BUF_net_196 ) , .Y ( Test_en_N_out ) ) ; sky130_fd_sc_hd__inv_1 BINV_R_196 ( .A ( Test_en_S_in ) , .Y ( BUF_net_196 ) ) ; sky130_fd_sc_hd__inv_8 BINV_R_197 ( .A ( BUF_net_198 ) , .Y ( pReset_N_out ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_198 ( .A ( aps_rename_507_ ) , +sky130_fd_sc_hd__inv_1 BINV_R_198 ( .A ( aps_rename_509_ ) , .Y ( BUF_net_198 ) ) ; sky130_fd_sc_hd__inv_8 BINV_R_199 ( .A ( BUF_net_200 ) , .Y ( Reset_N_out ) ) ; sky130_fd_sc_hd__inv_1 BINV_R_200 ( .A ( Reset_S_in ) , .Y ( BUF_net_200 ) ) ; sky130_fd_sc_hd__inv_8 BINV_R_201 ( .A ( BUF_net_202 ) , .Y ( prog_clk_3_N_out ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_202 ( .A ( aps_rename_509_ ) , +sky130_fd_sc_hd__inv_1 BINV_R_202 ( .A ( aps_rename_511_ ) , .Y ( BUF_net_202 ) ) ; sky130_fd_sc_hd__inv_8 BINV_R_203 ( .A ( BUF_net_204 ) , .Y ( clk_3_N_out ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_204 ( .A ( aps_rename_510_ ) , +sky130_fd_sc_hd__inv_1 BINV_R_204 ( .A ( aps_rename_512_ ) , .Y ( BUF_net_204 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_213 ( .LO ( SYNOPSYS_UNCONNECTED_163 ) , - .HI ( optlc_net_209 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_215 ( .LO ( SYNOPSYS_UNCONNECTED_164 ) , - .HI ( optlc_net_210 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_217 ( .LO ( SYNOPSYS_UNCONNECTED_165 ) , - .HI ( optlc_net_211 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_219 ( .LO ( SYNOPSYS_UNCONNECTED_166 ) , - .HI ( optlc_net_212 ) ) ; -sky130_fd_sc_hd__buf_6 ZBUF_6_f_inst_220 ( .A ( aps_rename_505_ ) , +sky130_fd_sc_hd__conb_1 optlc_225 ( .LO ( SYNOPSYS_UNCONNECTED_163 ) , + .HI ( optlc_net_219 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_227 ( .LO ( SYNOPSYS_UNCONNECTED_164 ) , + .HI ( optlc_net_220 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_230 ( .LO ( SYNOPSYS_UNCONNECTED_165 ) , + .HI ( optlc_net_221 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_232 ( .LO ( SYNOPSYS_UNCONNECTED_166 ) , + .HI ( optlc_net_222 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_235 ( .LO ( SYNOPSYS_UNCONNECTED_167 ) , + .HI ( optlc_net_223 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_237 ( .LO ( SYNOPSYS_UNCONNECTED_168 ) , + .HI ( optlc_net_224 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_239 ( .LO ( SYNOPSYS_UNCONNECTED_169 ) , + .HI ( optlc_net_225 ) ) ; +sky130_fd_sc_hd__buf_6 ZBUF_6_f_inst_240 ( .A ( aps_rename_506_ ) , .X ( chanx_right_out[3] ) ) ; -sky130_fd_sc_hd__buf_6 ZBUF_6_f_inst_221 ( .A ( aps_rename_508_ ) , +sky130_fd_sc_hd__buf_6 ZBUF_6_f_inst_241 ( .A ( aps_rename_508_ ) , + .X ( chanx_left_out[5] ) ) ; +sky130_fd_sc_hd__buf_6 ZBUF_6_f_inst_242 ( .A ( aps_rename_507_ ) , + .X ( chanx_right_out[5] ) ) ; +sky130_fd_sc_hd__buf_6 ZBUF_6_f_inst_243 ( .A ( aps_rename_510_ ) , .X ( pReset_E_out ) ) ; -sky130_fd_sc_hd__buf_6 ZBUF_6_f_inst_222 ( .A ( aps_rename_506_ ) , - .X ( chanx_left_out[3] ) ) ; -sky130_fd_sc_hd__buf_8 ropt_mt_inst_1431 ( .A ( ropt_net_229 ) , +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1451 ( .A ( ropt_net_242 ) , .X ( chany_top_out[27] ) ) ; endmodule @@ -55116,7 +59096,7 @@ input [0:0] mem ; input [0:0] mem_inv ; output [0:0] out ; -sky130_fd_sc_hd__mux2_2 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) , +sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ; endmodule @@ -55157,8 +59137,6 @@ wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ; wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ; wire [0:0] mux_2level_tapbuf_basis_input2_mem1_2_out ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( mux_2level_tapbuf_basis_input2_mem1_2_out[0] ) , .X ( out[0] ) ) ; sb_0__2__mux_2level_tapbuf_basis_input2_mem1_57 mux_l1_in_0_ ( .in ( in[0:1] ) , .mem ( sram[0] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) , @@ -55174,6 +59152,9 @@ sb_0__2__mux_2level_tapbuf_basis_input2_mem1 mux_l2_in_0_ ( .mem ( sram[1] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_4 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_2_out ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_100 ( .A ( BUF_net_101 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_101 ( + .A ( mux_2level_tapbuf_basis_input2_mem1_2_out[0] ) , .Y ( BUF_net_101 ) ) ; endmodule @@ -55240,9 +59221,9 @@ sb_0__2__mux_2level_tapbuf_basis_input2_mem1_56 mux_l2_in_0_ ( .mem ( sram[1] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_4 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_2_out ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_92 ( .A ( BUF_net_93 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_93 ( - .A ( mux_2level_tapbuf_basis_input2_mem1_2_out[0] ) , .Y ( BUF_net_93 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_98 ( .A ( BUF_net_99 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_99 ( + .A ( mux_2level_tapbuf_basis_input2_mem1_2_out[0] ) , .Y ( BUF_net_99 ) ) ; endmodule @@ -55254,18 +59235,18 @@ input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -wire copt_net_111 ; +wire copt_net_129 ; sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( copt_net_111 ) ) ; + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( copt_net_129 ) ) ; sky130_fd_sc_hd__buf_6 FTB_45__44 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1289 ( .A ( copt_net_111 ) , - .X ( copt_net_109 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1290 ( .A ( copt_net_109 ) , - .X ( copt_net_110 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1291 ( .A ( copt_net_110 ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1311 ( .A ( copt_net_129 ) , + .X ( copt_net_127 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1312 ( .A ( copt_net_127 ) , + .X ( copt_net_128 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1313 ( .A ( copt_net_128 ) , .X ( mem_out[1] ) ) ; endmodule @@ -55721,8 +59702,6 @@ input p0 ; wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ; wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) ) ; sb_0__2__mux_2level_tapbuf_basis_input2_mem1_52 mux_l1_in_0_ ( .in ( in ) , .mem ( sram[0] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) , @@ -55733,6 +59712,8 @@ sb_0__2__mux_2level_tapbuf_basis_input2_mem1_53 mux_l2_in_0_ ( .mem ( sram[1] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_97 ( + .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) ) ; endmodule @@ -55794,7 +59775,7 @@ input [0:0] mem_inv ; output [0:0] out ; input p0 ; -sky130_fd_sc_hd__mux2_2 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , +sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ; endmodule @@ -55821,8 +59802,6 @@ input p0 ; wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ; wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) ) ; sb_0__2__mux_2level_tapbuf_basis_input2_mem1_48 mux_l1_in_0_ ( .in ( in ) , .mem ( sram[0] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) , @@ -55833,6 +59812,9 @@ sb_0__2__mux_2level_tapbuf_basis_input2_mem1_49 mux_l2_in_0_ ( .mem ( sram[1] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_95 ( .A ( BUF_net_96 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_96 ( + .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_96 ) ) ; endmodule @@ -55921,8 +59903,6 @@ input p0 ; wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ; wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) ) ; sb_0__2__mux_2level_tapbuf_basis_input2_mem1_44 mux_l1_in_0_ ( .in ( in ) , .mem ( sram[0] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) , @@ -55933,6 +59913,8 @@ sb_0__2__mux_2level_tapbuf_basis_input2_mem1_45 mux_l2_in_0_ ( .mem ( sram[1] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_94 ( + .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) ) ; endmodule @@ -55944,7 +59926,7 @@ input [0:0] mem_inv ; output [0:0] out ; input p0 ; -sky130_fd_sc_hd__mux2_2 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , +sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ; endmodule @@ -56021,6 +60003,8 @@ input p0 ; wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ; wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) ) ; sb_0__2__mux_2level_tapbuf_basis_input2_mem1_40 mux_l1_in_0_ ( .in ( in ) , .mem ( sram[0] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) , @@ -56031,9 +60015,6 @@ sb_0__2__mux_2level_tapbuf_basis_input2_mem1_41 mux_l2_in_0_ ( .mem ( sram[1] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_6 BINV_R_94 ( .A ( BUF_net_95 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_2 BINV_R_95 ( - .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_95 ) ) ; endmodule @@ -56082,9 +60063,9 @@ sb_0__2__mux_2level_tapbuf_basis_input2_mem1_39 mux_l2_in_0_ ( .mem ( sram[1] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_90 ( .A ( BUF_net_91 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_91 ( - .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_91 ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_92 ( .A ( BUF_net_93 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_93 ( + .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_93 ) ) ; endmodule @@ -56146,7 +60127,7 @@ input [0:0] mem_inv ; output [0:0] out ; input p0 ; -sky130_fd_sc_hd__mux2_2 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , +sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ; endmodule @@ -56173,8 +60154,6 @@ input p0 ; wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ; wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) ) ; sb_0__2__mux_2level_tapbuf_basis_input2_mem1_34 mux_l1_in_0_ ( .in ( in ) , .mem ( sram[0] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) , @@ -56185,6 +60164,9 @@ sb_0__2__mux_2level_tapbuf_basis_input2_mem1_35 mux_l2_in_0_ ( .mem ( sram[1] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_90 ( .A ( BUF_net_91 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_91 ( + .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_91 ) ) ; endmodule @@ -56246,7 +60228,7 @@ input [0:0] mem_inv ; output [0:0] out ; input p0 ; -sky130_fd_sc_hd__mux2_2 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , +sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ; endmodule @@ -56273,8 +60255,6 @@ input p0 ; wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ; wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) ) ; sb_0__2__mux_2level_tapbuf_basis_input2_mem1_30 mux_l1_in_0_ ( .in ( in ) , .mem ( sram[0] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) , @@ -56285,6 +60265,9 @@ sb_0__2__mux_2level_tapbuf_basis_input2_mem1_31 mux_l2_in_0_ ( .mem ( sram[1] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_88 ( .A ( BUF_net_89 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_89 ( + .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_89 ) ) ; endmodule @@ -56296,7 +60279,7 @@ input [0:0] mem_inv ; output [0:0] out ; input p0 ; -sky130_fd_sc_hd__mux2_2 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , +sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ; endmodule @@ -56323,8 +60306,6 @@ input p0 ; wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ; wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) ) ; sb_0__2__mux_2level_tapbuf_basis_input2_mem1_28 mux_l1_in_0_ ( .in ( in ) , .mem ( sram[0] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) , @@ -56335,6 +60316,9 @@ sb_0__2__mux_2level_tapbuf_basis_input2_mem1_29 mux_l2_in_0_ ( .mem ( sram[1] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_87 ( + .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_87 ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_110 ( .A ( BUF_net_87 ) , .Y ( out[0] ) ) ; endmodule @@ -56346,7 +60330,7 @@ input [0:0] mem_inv ; output [0:0] out ; input p0 ; -sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , +sky130_fd_sc_hd__mux2_2 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ; endmodule @@ -56373,6 +60357,8 @@ input p0 ; wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ; wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) ) ; sb_0__2__mux_2level_tapbuf_basis_input2_mem1_26 mux_l1_in_0_ ( .in ( in ) , .mem ( sram[0] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) , @@ -56383,9 +60369,6 @@ sb_0__2__mux_2level_tapbuf_basis_input2_mem1_27 mux_l2_in_0_ ( .mem ( sram[1] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_88 ( .A ( BUF_net_89 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_89 ( - .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_89 ) ) ; endmodule @@ -56484,9 +60467,9 @@ sb_0__2__mux_2level_tapbuf_basis_input2_mem1_23 mux_l2_in_0_ ( .mem ( sram[1] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_86 ( .A ( BUF_net_87 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_87 ( - .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_87 ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_85 ( + .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_85 ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_108 ( .A ( BUF_net_85 ) , .Y ( out[0] ) ) ; endmodule @@ -56535,9 +60518,9 @@ sb_0__2__mux_2level_tapbuf_basis_input2_mem1_21 mux_l2_in_0_ ( .mem ( sram[1] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_6 BINV_R_84 ( .A ( BUF_net_85 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_2 BINV_R_85 ( - .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_85 ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_104 ( .A ( BUF_net_105 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_105 ( + .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_105 ) ) ; endmodule @@ -56576,8 +60559,6 @@ input p0 ; wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ; wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) ) ; sb_0__2__mux_2level_tapbuf_basis_input2_mem1_18 mux_l1_in_0_ ( .in ( in ) , .mem ( sram[0] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) , @@ -56588,6 +60569,9 @@ sb_0__2__mux_2level_tapbuf_basis_input2_mem1_19 mux_l2_in_0_ ( .mem ( sram[1] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_83 ( + .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_83 ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_106 ( .A ( BUF_net_83 ) , .Y ( out[0] ) ) ; endmodule @@ -56636,9 +60620,9 @@ sb_0__2__mux_2level_tapbuf_basis_input2_mem1_17 mux_l2_in_0_ ( .mem ( sram[1] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_82 ( .A ( BUF_net_83 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_83 ( - .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_83 ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_80 ( .A ( BUF_net_81 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_81 ( + .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_81 ) ) ; endmodule @@ -56777,6 +60761,8 @@ input p0 ; wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ; wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) ) ; sb_0__2__mux_2level_tapbuf_basis_input2_mem1_10 mux_l1_in_0_ ( .in ( in ) , .mem ( sram[0] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) , @@ -56787,9 +60773,6 @@ sb_0__2__mux_2level_tapbuf_basis_input2_mem1_11 mux_l2_in_0_ ( .mem ( sram[1] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_80 ( .A ( BUF_net_81 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_81 ( - .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_81 ) ) ; endmodule @@ -56828,8 +60811,6 @@ input p0 ; wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ; wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) ) ; sb_0__2__mux_2level_tapbuf_basis_input2_mem1_8 mux_l1_in_0_ ( .in ( in ) , .mem ( sram[0] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) , @@ -56840,6 +60821,8 @@ sb_0__2__mux_2level_tapbuf_basis_input2_mem1_9 mux_l2_in_0_ ( .mem ( sram[1] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_79 ( + .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) ) ; endmodule @@ -56878,6 +60861,8 @@ input p0 ; wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ; wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) ) ; sb_0__2__mux_2level_tapbuf_basis_input2_mem1_6 mux_l1_in_0_ ( .in ( in ) , .mem ( sram[0] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) , @@ -56888,9 +60873,6 @@ sb_0__2__mux_2level_tapbuf_basis_input2_mem1_7 mux_l2_in_0_ ( .mem ( sram[1] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_6 BINV_R_78 ( .A ( BUF_net_79 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_2 BINV_R_79 ( - .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_79 ) ) ; endmodule @@ -56939,9 +60921,9 @@ sb_0__2__mux_2level_tapbuf_basis_input2_mem1_5 mux_l2_in_0_ ( .mem ( sram[1] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_6 BINV_R_76 ( .A ( BUF_net_77 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_2 BINV_R_77 ( - .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_77 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_77 ( .A ( BUF_net_78 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_78 ( + .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_78 ) ) ; endmodule @@ -57153,7 +61135,7 @@ input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ropt_net_180 ) , +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ropt_net_158 ) , .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; @@ -57162,24 +61144,24 @@ sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__buf_1 FTB_13__12 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1280 ( .A ( ccff_head[0] ) , - .X ( copt_net_100 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1281 ( .A ( copt_net_100 ) , - .X ( copt_net_101 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1282 ( .A ( copt_net_101 ) , - .X ( copt_net_102 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1283 ( .A ( copt_net_102 ) , - .X ( copt_net_103 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1284 ( .A ( copt_net_103 ) , - .X ( copt_net_104 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1285 ( .A ( copt_net_104 ) , - .X ( copt_net_105 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1357 ( .A ( ropt_net_179 ) , - .X ( ropt_net_178 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1358 ( .A ( copt_net_105 ) , - .X ( ropt_net_179 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1359 ( .A ( ropt_net_178 ) , - .X ( ropt_net_180 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1302 ( .A ( ccff_head[0] ) , + .X ( copt_net_118 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1303 ( .A ( copt_net_118 ) , + .X ( copt_net_119 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1304 ( .A ( copt_net_119 ) , + .X ( copt_net_120 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1305 ( .A ( copt_net_120 ) , + .X ( copt_net_121 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1306 ( .A ( copt_net_121 ) , + .X ( copt_net_122 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1307 ( .A ( copt_net_122 ) , + .X ( copt_net_123 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1341 ( .A ( ropt_net_160 ) , + .X ( ropt_net_158 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1342 ( .A ( copt_net_123 ) , + .X ( ropt_net_159 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1343 ( .A ( ropt_net_159 ) , + .X ( ropt_net_160 ) ) ; endmodule @@ -57191,10 +61173,14 @@ input [0:2] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -57205,10 +61191,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -57287,10 +61277,14 @@ input [0:2] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -57301,10 +61295,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -57383,10 +61381,14 @@ input [0:2] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -57397,10 +61399,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -57450,8 +61456,6 @@ wire [0:2] local_encoder2to3_1_data_inv ; wire [0:0] mux_2level_tapbuf_basis_input3_mem3_0_out ; wire [0:0] mux_2level_tapbuf_basis_input3_mem3_1_out ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .X ( out[0] ) ) ; sb_0__2__local_encoder2to3_6 local_encoder2to3_0_ ( .addr ( sram[0:1] ) , .data ( local_encoder2to3_0_data ) , .data_inv ( local_encoder2to3_0_data_inv ) ) ; @@ -57468,6 +61472,9 @@ sb_0__2__mux_2level_tapbuf_basis_input3_mem3_7 mux_l2_in_0_ ( .mem ( local_encoder2to3_1_data ) , .mem_inv ( local_encoder2to3_1_data_inv ) , .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .p0 ( p0 ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_75 ( .A ( BUF_net_76 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_76 ( + .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_76 ) ) ; endmodule @@ -57479,10 +61486,14 @@ input [0:2] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -57493,10 +61504,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -57546,6 +61561,8 @@ wire [0:2] local_encoder2to3_1_data_inv ; wire [0:0] mux_2level_tapbuf_basis_input3_mem3_0_out ; wire [0:0] mux_2level_tapbuf_basis_input3_mem3_1_out ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .X ( out[0] ) ) ; sb_0__2__local_encoder2to3_4 local_encoder2to3_0_ ( .addr ( sram[0:1] ) , .data ( local_encoder2to3_0_data ) , .data_inv ( local_encoder2to3_0_data_inv ) ) ; @@ -57562,9 +61579,6 @@ sb_0__2__mux_2level_tapbuf_basis_input3_mem3_5 mux_l2_in_0_ ( .mem ( local_encoder2to3_1_data ) , .mem_inv ( local_encoder2to3_1_data_inv ) , .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_6 BINV_R_74 ( .A ( BUF_net_75 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_75 ( - .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_75 ) ) ; endmodule @@ -57576,10 +61590,14 @@ input [0:2] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -57590,10 +61608,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -57672,10 +61694,14 @@ input [0:2] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -57686,10 +61712,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -57755,8 +61785,9 @@ sb_0__2__mux_2level_tapbuf_basis_input3_mem3_1 mux_l2_in_0_ ( .mem ( local_encoder2to3_1_data ) , .mem_inv ( local_encoder2to3_1_data_inv ) , .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_73 ( - .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_73 ( .A ( BUF_net_74 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_74 ( + .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_74 ) ) ; endmodule @@ -57791,8 +61822,6 @@ input pReset_E_in ; output pReset_S_out ; input prog_clk_0_E_in ; -wire ropt_net_134 ; -wire ropt_net_132 ; wire [0:0] prog_clk ; wire prog_clk_0 ; wire [0:1] mux_2level_tapbuf_size2_0_sram ; @@ -57873,42 +61902,42 @@ sb_0__2__mux_2level_tapbuf_size4_0 mux_right_track_0 ( .sram ( mux_2level_tapbuf_size4_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 , SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) , - .out ( chanx_right_out[0] ) , .p0 ( optlc_net_98 ) ) ; + .out ( chanx_right_out[0] ) , .p0 ( optlc_net_114 ) ) ; sb_0__2__mux_2level_tapbuf_size4_1 mux_right_track_2 ( .in ( { right_bottom_grid_pin_36_[0] , right_bottom_grid_pin_39_[0] , right_bottom_grid_pin_42_[0] , chany_bottom_in[27] } ) , .sram ( mux_2level_tapbuf_size4_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 , SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 } ) , - .out ( chanx_right_out[1] ) , .p0 ( optlc_net_96 ) ) ; + .out ( chanx_right_out[1] ) , .p0 ( optlc_net_113 ) ) ; sb_0__2__mux_2level_tapbuf_size4_2 mux_right_track_4 ( .in ( { right_bottom_grid_pin_37_[0] , right_bottom_grid_pin_40_[0] , right_bottom_grid_pin_43_[0] , chany_bottom_in[26] } ) , .sram ( mux_2level_tapbuf_size4_2_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_9 , SYNOPSYS_UNCONNECTED_10 , SYNOPSYS_UNCONNECTED_11 , SYNOPSYS_UNCONNECTED_12 } ) , - .out ( chanx_right_out[2] ) , .p0 ( optlc_net_96 ) ) ; + .out ( chanx_right_out[2] ) , .p0 ( optlc_net_113 ) ) ; sb_0__2__mux_2level_tapbuf_size4_3 mux_right_track_6 ( .in ( { right_top_grid_pin_1_[0] , right_bottom_grid_pin_38_[0] , right_bottom_grid_pin_41_[0] , chany_bottom_in[25] } ) , .sram ( mux_2level_tapbuf_size4_3_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 , SYNOPSYS_UNCONNECTED_15 , SYNOPSYS_UNCONNECTED_16 } ) , - .out ( chanx_right_out[3] ) , .p0 ( optlc_net_98 ) ) ; + .out ( chanx_right_out[3] ) , .p0 ( optlc_net_114 ) ) ; sb_0__2__mux_2level_tapbuf_size4_4 mux_right_track_8 ( .in ( { right_bottom_grid_pin_36_[0] , right_bottom_grid_pin_39_[0] , right_bottom_grid_pin_42_[0] , chany_bottom_in[24] } ) , .sram ( mux_2level_tapbuf_size4_4_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_17 , SYNOPSYS_UNCONNECTED_18 , SYNOPSYS_UNCONNECTED_19 , SYNOPSYS_UNCONNECTED_20 } ) , - .out ( chanx_right_out[4] ) , .p0 ( optlc_net_96 ) ) ; + .out ( chanx_right_out[4] ) , .p0 ( optlc_net_114 ) ) ; sb_0__2__mux_2level_tapbuf_size4 mux_right_track_10 ( .in ( { right_bottom_grid_pin_37_[0] , right_bottom_grid_pin_40_[0] , right_bottom_grid_pin_43_[0] , chany_bottom_in[23] } ) , .sram ( mux_2level_tapbuf_size4_5_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_21 , SYNOPSYS_UNCONNECTED_22 , SYNOPSYS_UNCONNECTED_23 , SYNOPSYS_UNCONNECTED_24 } ) , - .out ( chanx_right_out[5] ) , .p0 ( optlc_net_96 ) ) ; + .out ( chanx_right_out[5] ) , .p0 ( optlc_net_113 ) ) ; sb_0__2__mux_2level_tapbuf_size4_mem_0 mem_right_track_0 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( mux_2level_tapbuf_size4_mem_0_ccff_tail ) , @@ -57942,137 +61971,137 @@ sb_0__2__mux_2level_tapbuf_size2_0 mux_right_track_12 ( .in ( { right_top_grid_pin_1_[0] , chany_bottom_in[22] } ) , .sram ( mux_2level_tapbuf_size2_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_25 , SYNOPSYS_UNCONNECTED_26 } ) , - .out ( chanx_right_out[6] ) , .p0 ( optlc_net_96 ) ) ; + .out ( chanx_right_out[6] ) , .p0 ( optlc_net_116 ) ) ; sb_0__2__mux_2level_tapbuf_size2_1 mux_right_track_14 ( .in ( { right_bottom_grid_pin_36_[0] , chany_bottom_in[21] } ) , .sram ( mux_2level_tapbuf_size2_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_27 , SYNOPSYS_UNCONNECTED_28 } ) , - .out ( chanx_right_out[7] ) , .p0 ( optlc_net_96 ) ) ; + .out ( chanx_right_out[7] ) , .p0 ( optlc_net_113 ) ) ; sb_0__2__mux_2level_tapbuf_size2_2 mux_right_track_16 ( .in ( { right_bottom_grid_pin_37_[0] , chany_bottom_in[20] } ) , .sram ( mux_2level_tapbuf_size2_2_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_29 , SYNOPSYS_UNCONNECTED_30 } ) , - .out ( chanx_right_out[8] ) , .p0 ( optlc_net_96 ) ) ; + .out ( chanx_right_out[8] ) , .p0 ( optlc_net_115 ) ) ; sb_0__2__mux_2level_tapbuf_size2_3 mux_right_track_18 ( .in ( { right_bottom_grid_pin_38_[0] , chany_bottom_in[19] } ) , .sram ( mux_2level_tapbuf_size2_3_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_31 , SYNOPSYS_UNCONNECTED_32 } ) , - .out ( chanx_right_out[9] ) , .p0 ( optlc_net_96 ) ) ; + .out ( chanx_right_out[9] ) , .p0 ( optlc_net_116 ) ) ; sb_0__2__mux_2level_tapbuf_size2_4 mux_right_track_20 ( .in ( { right_bottom_grid_pin_39_[0] , chany_bottom_in[18] } ) , .sram ( mux_2level_tapbuf_size2_4_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_33 , SYNOPSYS_UNCONNECTED_34 } ) , - .out ( chanx_right_out[10] ) , .p0 ( optlc_net_99 ) ) ; + .out ( chanx_right_out[10] ) , .p0 ( optlc_net_115 ) ) ; sb_0__2__mux_2level_tapbuf_size2_5 mux_right_track_22 ( .in ( { right_bottom_grid_pin_40_[0] , chany_bottom_in[17] } ) , .sram ( mux_2level_tapbuf_size2_5_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_35 , SYNOPSYS_UNCONNECTED_36 } ) , - .out ( chanx_right_out[11] ) , .p0 ( optlc_net_97 ) ) ; + .out ( chanx_right_out[11] ) , .p0 ( optlc_net_114 ) ) ; sb_0__2__mux_2level_tapbuf_size2_6 mux_right_track_24 ( .in ( { right_bottom_grid_pin_41_[0] , chany_bottom_in[16] } ) , .sram ( mux_2level_tapbuf_size2_6_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_37 , SYNOPSYS_UNCONNECTED_38 } ) , - .out ( chanx_right_out[12] ) , .p0 ( optlc_net_99 ) ) ; + .out ( chanx_right_out[12] ) , .p0 ( optlc_net_114 ) ) ; sb_0__2__mux_2level_tapbuf_size2_7 mux_right_track_26 ( .in ( { right_bottom_grid_pin_42_[0] , chany_bottom_in[15] } ) , .sram ( mux_2level_tapbuf_size2_7_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_39 , SYNOPSYS_UNCONNECTED_40 } ) , - .out ( chanx_right_out[13] ) , .p0 ( optlc_net_99 ) ) ; + .out ( chanx_right_out[13] ) , .p0 ( optlc_net_114 ) ) ; sb_0__2__mux_2level_tapbuf_size2_8 mux_right_track_30 ( .in ( { right_bottom_grid_pin_36_[0] , chany_bottom_in[13] } ) , .sram ( mux_2level_tapbuf_size2_8_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_41 , SYNOPSYS_UNCONNECTED_42 } ) , - .out ( chanx_right_out[15] ) , .p0 ( optlc_net_96 ) ) ; + .out ( chanx_right_out[15] ) , .p0 ( optlc_net_117 ) ) ; sb_0__2__mux_2level_tapbuf_size2_9 mux_right_track_32 ( .in ( { right_bottom_grid_pin_37_[0] , chany_bottom_in[12] } ) , .sram ( mux_2level_tapbuf_size2_9_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_43 , SYNOPSYS_UNCONNECTED_44 } ) , - .out ( chanx_right_out[16] ) , .p0 ( optlc_net_97 ) ) ; + .out ( chanx_right_out[16] ) , .p0 ( optlc_net_116 ) ) ; sb_0__2__mux_2level_tapbuf_size2_10 mux_right_track_34 ( .in ( { right_bottom_grid_pin_38_[0] , chany_bottom_in[11] } ) , .sram ( mux_2level_tapbuf_size2_10_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_45 , SYNOPSYS_UNCONNECTED_46 } ) , - .out ( chanx_right_out[17] ) , .p0 ( optlc_net_97 ) ) ; + .out ( chanx_right_out[17] ) , .p0 ( optlc_net_116 ) ) ; sb_0__2__mux_2level_tapbuf_size2_11 mux_right_track_36 ( .in ( { right_bottom_grid_pin_39_[0] , chany_bottom_in[10] } ) , .sram ( mux_2level_tapbuf_size2_11_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_47 , SYNOPSYS_UNCONNECTED_48 } ) , - .out ( chanx_right_out[18] ) , .p0 ( optlc_net_99 ) ) ; + .out ( chanx_right_out[18] ) , .p0 ( optlc_net_117 ) ) ; sb_0__2__mux_2level_tapbuf_size2_12 mux_right_track_38 ( .in ( { right_bottom_grid_pin_40_[0] , chany_bottom_in[9] } ) , .sram ( mux_2level_tapbuf_size2_12_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_49 , SYNOPSYS_UNCONNECTED_50 } ) , - .out ( chanx_right_out[19] ) , .p0 ( optlc_net_99 ) ) ; + .out ( chanx_right_out[19] ) , .p0 ( optlc_net_117 ) ) ; sb_0__2__mux_2level_tapbuf_size2_13 mux_right_track_40 ( .in ( { right_bottom_grid_pin_41_[0] , chany_bottom_in[8] } ) , .sram ( mux_2level_tapbuf_size2_13_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_51 , SYNOPSYS_UNCONNECTED_52 } ) , - .out ( chanx_right_out[20] ) , .p0 ( optlc_net_99 ) ) ; + .out ( chanx_right_out[20] ) , .p0 ( optlc_net_117 ) ) ; sb_0__2__mux_2level_tapbuf_size2_14 mux_right_track_42 ( .in ( { right_bottom_grid_pin_42_[0] , chany_bottom_in[7] } ) , .sram ( mux_2level_tapbuf_size2_14_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_53 , SYNOPSYS_UNCONNECTED_54 } ) , - .out ( chanx_right_out[21] ) , .p0 ( optlc_net_99 ) ) ; + .out ( chanx_right_out[21] ) , .p0 ( optlc_net_116 ) ) ; sb_0__2__mux_2level_tapbuf_size2_15 mux_right_track_44 ( .in ( { right_top_grid_pin_1_[0] , chany_bottom_in[6] } ) , .sram ( mux_2level_tapbuf_size2_15_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_55 , SYNOPSYS_UNCONNECTED_56 } ) , - .out ( chanx_right_out[22] ) , .p0 ( optlc_net_99 ) ) ; + .out ( chanx_right_out[22] ) , .p0 ( optlc_net_116 ) ) ; sb_0__2__mux_2level_tapbuf_size2_16 mux_right_track_46 ( .in ( { right_bottom_grid_pin_36_[0] , chany_bottom_in[5] } ) , .sram ( mux_2level_tapbuf_size2_16_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_57 , SYNOPSYS_UNCONNECTED_58 } ) , - .out ( chanx_right_out[23] ) , .p0 ( optlc_net_99 ) ) ; + .out ( chanx_right_out[23] ) , .p0 ( optlc_net_117 ) ) ; sb_0__2__mux_2level_tapbuf_size2_17 mux_right_track_48 ( .in ( { right_bottom_grid_pin_37_[0] , chany_bottom_in[4] } ) , .sram ( mux_2level_tapbuf_size2_17_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_59 , SYNOPSYS_UNCONNECTED_60 } ) , - .out ( chanx_right_out[24] ) , .p0 ( optlc_net_99 ) ) ; + .out ( chanx_right_out[24] ) , .p0 ( optlc_net_116 ) ) ; sb_0__2__mux_2level_tapbuf_size2_18 mux_right_track_50 ( .in ( { right_bottom_grid_pin_38_[0] , chany_bottom_in[3] } ) , .sram ( mux_2level_tapbuf_size2_18_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_61 , SYNOPSYS_UNCONNECTED_62 } ) , - .out ( chanx_right_out[25] ) , .p0 ( optlc_net_99 ) ) ; + .out ( chanx_right_out[25] ) , .p0 ( optlc_net_115 ) ) ; sb_0__2__mux_2level_tapbuf_size2_19 mux_right_track_54 ( .in ( { right_bottom_grid_pin_40_[0] , chany_bottom_in[1] } ) , .sram ( mux_2level_tapbuf_size2_19_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_63 , SYNOPSYS_UNCONNECTED_64 } ) , - .out ( chanx_right_out[27] ) , .p0 ( optlc_net_98 ) ) ; + .out ( chanx_right_out[27] ) , .p0 ( optlc_net_114 ) ) ; sb_0__2__mux_2level_tapbuf_size2_20 mux_right_track_56 ( .in ( { right_bottom_grid_pin_41_[0] , chany_bottom_in[0] } ) , .sram ( mux_2level_tapbuf_size2_20_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_65 , SYNOPSYS_UNCONNECTED_66 } ) , - .out ( chanx_right_out[28] ) , .p0 ( optlc_net_96 ) ) ; + .out ( chanx_right_out[28] ) , .p0 ( optlc_net_114 ) ) ; sb_0__2__mux_2level_tapbuf_size2_21 mux_right_track_58 ( .in ( { right_bottom_grid_pin_42_[0] , chany_bottom_in[29] } ) , .sram ( mux_2level_tapbuf_size2_21_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_67 , SYNOPSYS_UNCONNECTED_68 } ) , - .out ( chanx_right_out[29] ) , .p0 ( optlc_net_99 ) ) ; + .out ( chanx_right_out[29] ) , .p0 ( optlc_net_113 ) ) ; sb_0__2__mux_2level_tapbuf_size2_22 mux_bottom_track_1 ( .in ( { chanx_right_in[28] , bottom_left_grid_pin_1_[0] } ) , .sram ( mux_2level_tapbuf_size2_22_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_69 , SYNOPSYS_UNCONNECTED_70 } ) , - .out ( chany_bottom_out[0] ) , .p0 ( optlc_net_97 ) ) ; + .out ( chany_bottom_out[0] ) , .p0 ( optlc_net_112 ) ) ; sb_0__2__mux_2level_tapbuf_size2_23 mux_bottom_track_7 ( .in ( { chanx_right_in[25] , bottom_left_grid_pin_1_[0] } ) , .sram ( mux_2level_tapbuf_size2_23_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_71 , SYNOPSYS_UNCONNECTED_72 } ) , - .out ( chany_bottom_out[3] ) , .p0 ( optlc_net_97 ) ) ; + .out ( chany_bottom_out[3] ) , .p0 ( optlc_net_112 ) ) ; sb_0__2__mux_2level_tapbuf_size2_24 mux_bottom_track_13 ( .in ( { chanx_right_in[22] , bottom_left_grid_pin_1_[0] } ) , .sram ( mux_2level_tapbuf_size2_24_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_73 , SYNOPSYS_UNCONNECTED_74 } ) , - .out ( chany_bottom_out[6] ) , .p0 ( optlc_net_97 ) ) ; + .out ( chany_bottom_out[6] ) , .p0 ( optlc_net_112 ) ) ; sb_0__2__mux_2level_tapbuf_size2_25 mux_bottom_track_29 ( .in ( { chanx_right_in[14] , bottom_left_grid_pin_1_[0] } ) , .sram ( mux_2level_tapbuf_size2_25_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_75 , SYNOPSYS_UNCONNECTED_76 } ) , - .out ( chany_bottom_out[14] ) , .p0 ( optlc_net_97 ) ) ; + .out ( chany_bottom_out[14] ) , .p0 ( optlc_net_112 ) ) ; sb_0__2__mux_2level_tapbuf_size2 mux_bottom_track_45 ( .in ( { chanx_right_in[6] , bottom_left_grid_pin_1_[0] } ) , .sram ( mux_2level_tapbuf_size2_26_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_77 , SYNOPSYS_UNCONNECTED_78 } ) , - .out ( chany_bottom_out[22] ) , .p0 ( optlc_net_97 ) ) ; + .out ( chany_bottom_out[22] ) , .p0 ( optlc_net_112 ) ) ; sb_0__2__mux_2level_tapbuf_size2_mem_0 mem_right_track_12 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( mux_2level_tapbuf_size4_mem_5_ccff_tail ) , @@ -58212,13 +62241,13 @@ sb_0__2__mux_2level_tapbuf_size3_0 mux_right_track_28 ( chany_bottom_in[14] } ) , .sram ( mux_2level_tapbuf_size3_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_79 , SYNOPSYS_UNCONNECTED_80 } ) , - .out ( chanx_right_out[14] ) , .p0 ( optlc_net_99 ) ) ; + .out ( chanx_right_out[14] ) , .p0 ( optlc_net_115 ) ) ; sb_0__2__mux_2level_tapbuf_size3 mux_right_track_52 ( .in ( { right_bottom_grid_pin_39_[0] , right_bottom_grid_pin_43_[0] , chany_bottom_in[2] } ) , .sram ( mux_2level_tapbuf_size3_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_81 , SYNOPSYS_UNCONNECTED_82 } ) , - .out ( chanx_right_out[26] ) , .p0 ( optlc_net_96 ) ) ; + .out ( chanx_right_out[26] ) , .p0 ( optlc_net_114 ) ) ; sb_0__2__mux_2level_tapbuf_size3_mem_0 mem_right_track_28 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( mux_2level_tapbuf_size2_mem_7_ccff_tail ) , @@ -58230,8 +62259,8 @@ sb_0__2__mux_2level_tapbuf_size3_mem mem_right_track_52 ( .pReset ( pReset ) , .ccff_tail ( mux_2level_tapbuf_size3_mem_1_ccff_tail ) , .mem_out ( mux_2level_tapbuf_size3_1_sram ) ) ; sky130_fd_sc_hd__buf_8 pReset_FTB00 ( .A ( pReset_E_in ) , .X ( pReset[0] ) ) ; -sky130_fd_sc_hd__buf_6 pReset_S_FTB01 ( .A ( pReset_E_in ) , - .X ( pReset_S_out ) ) ; +sky130_fd_sc_hd__conb_1 optlc_115 ( .LO ( SYNOPSYS_UNCONNECTED_83 ) , + .HI ( optlc_net_112 ) ) ; sky130_fd_sc_hd__buf_1 prog_clk_0_FTB00 ( .A ( prog_clk_0_E_in ) , .X ( prog_clk[0] ) ) ; sky130_fd_sc_hd__buf_8 FTB_48__47 ( .A ( chanx_right_in[0] ) , @@ -58254,16 +62283,16 @@ sky130_fd_sc_hd__buf_8 FTB_56__55 ( .A ( chanx_right_in[9] ) , .X ( chany_bottom_out[19] ) ) ; sky130_fd_sc_hd__buf_8 FTB_57__56 ( .A ( chanx_right_in[10] ) , .X ( chany_bottom_out[18] ) ) ; -sky130_fd_sc_hd__buf_6 FTB_58__57 ( .A ( chanx_right_in[11] ) , - .X ( ropt_net_134 ) ) ; +sky130_fd_sc_hd__buf_8 FTB_58__57 ( .A ( chanx_right_in[11] ) , + .X ( chany_bottom_out[17] ) ) ; sky130_fd_sc_hd__buf_8 FTB_59__58 ( .A ( chanx_right_in[12] ) , .X ( chany_bottom_out[16] ) ) ; sky130_fd_sc_hd__buf_8 FTB_60__59 ( .A ( chanx_right_in[13] ) , .X ( chany_bottom_out[15] ) ) ; sky130_fd_sc_hd__buf_8 FTB_61__60 ( .A ( chanx_right_in[15] ) , .X ( chany_bottom_out[13] ) ) ; -sky130_fd_sc_hd__buf_6 FTB_62__61 ( .A ( chanx_right_in[16] ) , - .X ( ropt_net_132 ) ) ; +sky130_fd_sc_hd__buf_8 FTB_62__61 ( .A ( chanx_right_in[16] ) , + .X ( chany_bottom_out[12] ) ) ; sky130_fd_sc_hd__buf_8 FTB_63__62 ( .A ( chanx_right_in[17] ) , .X ( chany_bottom_out[11] ) ) ; sky130_fd_sc_hd__buf_8 FTB_64__63 ( .A ( chanx_right_in[18] ) , @@ -58278,25 +62307,25 @@ sky130_fd_sc_hd__buf_8 FTB_68__67 ( .A ( chanx_right_in[23] ) , .X ( chany_bottom_out[5] ) ) ; sky130_fd_sc_hd__buf_8 FTB_69__68 ( .A ( chanx_right_in[24] ) , .X ( chany_bottom_out[4] ) ) ; -sky130_fd_sc_hd__buf_8 FTB_70__69 ( .A ( chanx_right_in[26] ) , +sky130_fd_sc_hd__buf_6 FTB_70__69 ( .A ( chanx_right_in[26] ) , .X ( chany_bottom_out[2] ) ) ; sky130_fd_sc_hd__buf_8 FTB_71__70 ( .A ( chanx_right_in[27] ) , .X ( chany_bottom_out[1] ) ) ; sky130_fd_sc_hd__buf_8 FTB_72__71 ( .A ( chanx_right_in[29] ) , .X ( chany_bottom_out[29] ) ) ; sky130_fd_sc_hd__buf_6 FTB_73__72 ( .A ( SC_IN_TOP ) , .X ( SC_OUT_BOT ) ) ; -sky130_fd_sc_hd__conb_1 optlc_98 ( .LO ( SYNOPSYS_UNCONNECTED_83 ) , - .HI ( optlc_net_96 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_100 ( .LO ( SYNOPSYS_UNCONNECTED_84 ) , - .HI ( optlc_net_97 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_102 ( .LO ( SYNOPSYS_UNCONNECTED_85 ) , - .HI ( optlc_net_98 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_104 ( .LO ( SYNOPSYS_UNCONNECTED_86 ) , - .HI ( optlc_net_99 ) ) ; -sky130_fd_sc_hd__buf_8 ropt_mt_inst_1311 ( .A ( ropt_net_132 ) , - .X ( chany_bottom_out[12] ) ) ; -sky130_fd_sc_hd__buf_8 ropt_mt_inst_1313 ( .A ( ropt_net_134 ) , - .X ( chany_bottom_out[17] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_102 ( .A ( BUF_net_103 ) , .Y ( pReset_S_out ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_103 ( .A ( pReset_E_in ) , .Y ( BUF_net_103 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_117 ( .LO ( SYNOPSYS_UNCONNECTED_84 ) , + .HI ( optlc_net_113 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_119 ( .LO ( SYNOPSYS_UNCONNECTED_85 ) , + .HI ( optlc_net_114 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_122 ( .LO ( SYNOPSYS_UNCONNECTED_86 ) , + .HI ( optlc_net_115 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_124 ( .LO ( SYNOPSYS_UNCONNECTED_87 ) , + .HI ( optlc_net_116 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_126 ( .LO ( SYNOPSYS_UNCONNECTED_88 ) , + .HI ( optlc_net_117 ) ) ; endmodule @@ -58481,9 +62510,9 @@ sb_0__1__mux_2level_tapbuf_basis_input2_mem1 mux_l2_in_0_ ( .mem ( sram[1] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_216 ( .A ( BUF_net_217 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_217 ( - .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_217 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_209 ( .A ( BUF_net_210 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_210 ( + .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_210 ) ) ; endmodule @@ -58582,9 +62611,9 @@ sb_0__1__mux_2level_tapbuf_basis_input2_mem1_41 mux_l2_in_0_ ( .mem ( sram[1] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_214 ( .A ( BUF_net_215 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_215 ( - .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_215 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_201 ( .A ( BUF_net_202 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_202 ( + .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_202 ) ) ; endmodule @@ -58733,9 +62762,9 @@ sb_0__1__mux_2level_tapbuf_basis_input2_mem1_35 mux_l2_in_0_ ( .mem ( sram[1] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_212 ( .A ( BUF_net_213 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_213 ( - .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_213 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_199 ( .A ( BUF_net_200 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_200 ( + .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_200 ) ) ; endmodule @@ -58784,9 +62813,9 @@ sb_0__1__mux_2level_tapbuf_basis_input2_mem1_33 mux_l2_in_0_ ( .mem ( sram[1] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_210 ( .A ( BUF_net_211 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_211 ( - .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_211 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_197 ( .A ( BUF_net_198 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_198 ( + .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_198 ) ) ; endmodule @@ -58825,8 +62854,6 @@ input p0 ; wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ; wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) ) ; sb_0__1__mux_2level_tapbuf_basis_input2_mem1_30 mux_l1_in_0_ ( .in ( in ) , .mem ( sram[0] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) , @@ -58837,6 +62864,9 @@ sb_0__1__mux_2level_tapbuf_basis_input2_mem1_31 mux_l2_in_0_ ( .mem ( sram[1] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_195 ( .A ( BUF_net_196 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_196 ( + .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_196 ) ) ; endmodule @@ -59149,7 +63179,7 @@ input [0:0] mem ; input [0:0] mem_inv ; output [0:0] out ; -sky130_fd_sc_hd__mux2_2 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) , +sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ; endmodule @@ -59205,8 +63235,9 @@ sb_0__1__mux_2level_tapbuf_basis_input2_mem1_23 mux_l2_in_0_ ( .mem ( sram[1] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_4 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_2_out ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_209 ( - .A ( mux_2level_tapbuf_basis_input2_mem1_2_out[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_193 ( .A ( BUF_net_194 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_194 ( + .A ( mux_2level_tapbuf_basis_input2_mem1_2_out[0] ) , .Y ( BUF_net_194 ) ) ; endmodule @@ -59258,6 +63289,8 @@ wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ; wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ; wire [0:0] mux_2level_tapbuf_basis_input2_mem1_2_out ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( mux_2level_tapbuf_basis_input2_mem1_2_out[0] ) , .X ( out[0] ) ) ; sb_0__1__mux_2level_tapbuf_basis_input2_mem1_18 mux_l1_in_0_ ( .in ( in[0:1] ) , .mem ( sram[0] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) , @@ -59273,8 +63306,6 @@ sb_0__1__mux_2level_tapbuf_basis_input2_mem1_20 mux_l2_in_0_ ( .mem ( sram[1] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_4 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_2_out ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_208 ( - .A ( mux_2level_tapbuf_basis_input2_mem1_2_out[0] ) , .X ( out[0] ) ) ; endmodule @@ -59285,7 +63316,7 @@ input [0:0] mem ; input [0:0] mem_inv ; output [0:0] out ; -sky130_fd_sc_hd__mux2_2 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) , +sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ; endmodule @@ -59326,8 +63357,6 @@ wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ; wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ; wire [0:0] mux_2level_tapbuf_basis_input2_mem1_2_out ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( mux_2level_tapbuf_basis_input2_mem1_2_out[0] ) , .X ( out[0] ) ) ; sb_0__1__mux_2level_tapbuf_basis_input2_mem1_15 mux_l1_in_0_ ( .in ( in[0:1] ) , .mem ( sram[0] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) , @@ -59343,6 +63372,9 @@ sb_0__1__mux_2level_tapbuf_basis_input2_mem1_17 mux_l2_in_0_ ( .mem ( sram[1] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_4 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_2_out ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_213 ( .A ( BUF_net_214 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_214 ( + .A ( mux_2level_tapbuf_basis_input2_mem1_2_out[0] ) , .Y ( BUF_net_214 ) ) ; endmodule @@ -59353,7 +63385,7 @@ input [0:0] mem ; input [0:0] mem_inv ; output [0:0] out ; -sky130_fd_sc_hd__mux2_2 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) , +sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ; endmodule @@ -59394,8 +63426,6 @@ wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ; wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ; wire [0:0] mux_2level_tapbuf_basis_input2_mem1_2_out ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( mux_2level_tapbuf_basis_input2_mem1_2_out[0] ) , .X ( out[0] ) ) ; sb_0__1__mux_2level_tapbuf_basis_input2_mem1_12 mux_l1_in_0_ ( .in ( in[0:1] ) , .mem ( sram[0] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) , @@ -59411,6 +63441,9 @@ sb_0__1__mux_2level_tapbuf_basis_input2_mem1_14 mux_l2_in_0_ ( .mem ( sram[1] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_4 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_2_out ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_191 ( .A ( BUF_net_192 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_192 ( + .A ( mux_2level_tapbuf_basis_input2_mem1_2_out[0] ) , .Y ( BUF_net_192 ) ) ; endmodule @@ -59421,7 +63454,7 @@ input [0:0] mem ; input [0:0] mem_inv ; output [0:0] out ; -sky130_fd_sc_hd__mux2_2 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) , +sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ; endmodule @@ -59477,8 +63510,9 @@ sb_0__1__mux_2level_tapbuf_basis_input2_mem1_11 mux_l2_in_0_ ( .mem ( sram[1] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_4 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_2_out ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_207 ( - .A ( mux_2level_tapbuf_basis_input2_mem1_2_out[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_207 ( .A ( BUF_net_208 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_208 ( + .A ( mux_2level_tapbuf_basis_input2_mem1_2_out[0] ) , .Y ( BUF_net_208 ) ) ; endmodule @@ -59489,7 +63523,7 @@ input [0:0] mem ; input [0:0] mem_inv ; output [0:0] out ; -sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) , +sky130_fd_sc_hd__mux2_2 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ; endmodule @@ -59530,6 +63564,8 @@ wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ; wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ; wire [0:0] mux_2level_tapbuf_basis_input2_mem1_2_out ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( mux_2level_tapbuf_basis_input2_mem1_2_out[0] ) , .X ( out[0] ) ) ; sb_0__1__mux_2level_tapbuf_basis_input2_mem1_6 mux_l1_in_0_ ( .in ( in[0:1] ) , .mem ( sram[0] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) , @@ -59545,9 +63581,6 @@ sb_0__1__mux_2level_tapbuf_basis_input2_mem1_8 mux_l2_in_0_ ( .mem ( sram[1] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_4 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_2_out ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_205 ( .A ( BUF_net_206 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_206 ( - .A ( mux_2level_tapbuf_basis_input2_mem1_2_out[0] ) , .Y ( BUF_net_206 ) ) ; endmodule @@ -59599,6 +63632,8 @@ wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ; wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ; wire [0:0] mux_2level_tapbuf_basis_input2_mem1_2_out ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( mux_2level_tapbuf_basis_input2_mem1_2_out[0] ) , .X ( out[0] ) ) ; sb_0__1__mux_2level_tapbuf_basis_input2_mem1_3 mux_l1_in_0_ ( .in ( in[0:1] ) , .mem ( sram[0] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) , @@ -59614,9 +63649,6 @@ sb_0__1__mux_2level_tapbuf_basis_input2_mem1_5 mux_l2_in_0_ ( .mem ( sram[1] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_4 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_2_out ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_203 ( .A ( BUF_net_204 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_204 ( - .A ( mux_2level_tapbuf_basis_input2_mem1_2_out[0] ) , .Y ( BUF_net_204 ) ) ; endmodule @@ -59668,6 +63700,8 @@ wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ; wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ; wire [0:0] mux_2level_tapbuf_basis_input2_mem1_2_out ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( mux_2level_tapbuf_basis_input2_mem1_2_out[0] ) , .X ( out[0] ) ) ; sb_0__1__mux_2level_tapbuf_basis_input2_mem1_0 mux_l1_in_0_ ( .in ( in[0:1] ) , .mem ( sram[0] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) , @@ -59683,9 +63717,6 @@ sb_0__1__mux_2level_tapbuf_basis_input2_mem1_2 mux_l2_in_0_ ( .mem ( sram[1] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_4 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_2_out ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_201 ( .A ( BUF_net_202 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_202 ( - .A ( mux_2level_tapbuf_basis_input2_mem1_2_out[0] ) , .Y ( BUF_net_202 ) ) ; endmodule @@ -59937,10 +63968,14 @@ input [0:2] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -59951,10 +63986,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -60004,6 +64043,8 @@ wire [0:2] local_encoder2to3_1_data_inv ; wire [0:0] mux_2level_tapbuf_basis_input3_mem3_0_out ; wire [0:0] mux_2level_tapbuf_basis_input3_mem3_1_out ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .X ( out[0] ) ) ; sb_0__1__local_encoder2to3_62 local_encoder2to3_0_ ( .addr ( sram[0:1] ) , .data ( local_encoder2to3_0_data ) , .data_inv ( local_encoder2to3_0_data_inv ) ) ; @@ -60020,9 +64061,6 @@ sb_0__1__mux_2level_tapbuf_basis_input3_mem3 mux_l2_in_0_ ( .mem ( local_encoder2to3_1_data ) , .mem_inv ( local_encoder2to3_1_data_inv ) , .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_199 ( .A ( BUF_net_200 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_200 ( - .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_200 ) ) ; endmodule @@ -60034,10 +64072,14 @@ input [0:2] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -60048,10 +64090,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -60130,10 +64176,14 @@ input [0:2] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -60144,10 +64194,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -60197,8 +64251,6 @@ wire [0:2] local_encoder2to3_1_data_inv ; wire [0:0] mux_2level_tapbuf_basis_input3_mem3_0_out ; wire [0:0] mux_2level_tapbuf_basis_input3_mem3_1_out ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .X ( out[0] ) ) ; sb_0__1__local_encoder2to3_58 local_encoder2to3_0_ ( .addr ( sram[0:1] ) , .data ( local_encoder2to3_0_data ) , .data_inv ( local_encoder2to3_0_data_inv ) ) ; @@ -60215,6 +64267,9 @@ sb_0__1__mux_2level_tapbuf_basis_input3_mem3_67 mux_l2_in_0_ ( .mem ( local_encoder2to3_1_data ) , .mem_inv ( local_encoder2to3_1_data_inv ) , .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .p0 ( p0 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_189 ( .A ( BUF_net_190 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_190 ( + .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_190 ) ) ; endmodule @@ -60226,10 +64281,14 @@ input [0:2] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -60240,10 +64299,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -60293,6 +64356,8 @@ wire [0:2] local_encoder2to3_1_data_inv ; wire [0:0] mux_2level_tapbuf_basis_input3_mem3_0_out ; wire [0:0] mux_2level_tapbuf_basis_input3_mem3_1_out ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .X ( out[0] ) ) ; sb_0__1__local_encoder2to3_56 local_encoder2to3_0_ ( .addr ( sram[0:1] ) , .data ( local_encoder2to3_0_data ) , .data_inv ( local_encoder2to3_0_data_inv ) ) ; @@ -60309,9 +64374,6 @@ sb_0__1__mux_2level_tapbuf_basis_input3_mem3_65 mux_l2_in_0_ ( .mem ( local_encoder2to3_1_data ) , .mem_inv ( local_encoder2to3_1_data_inv ) , .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_197 ( .A ( BUF_net_198 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_198 ( - .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_198 ) ) ; endmodule @@ -60323,10 +64385,14 @@ input [0:2] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -60337,10 +64403,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -60406,9 +64476,8 @@ sb_0__1__mux_2level_tapbuf_basis_input3_mem3_63 mux_l2_in_0_ ( .mem ( local_encoder2to3_1_data ) , .mem_inv ( local_encoder2to3_1_data_inv ) , .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_195 ( .A ( BUF_net_196 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_196 ( - .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_196 ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_188 ( + .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .X ( out[0] ) ) ; endmodule @@ -60420,10 +64489,14 @@ input [0:2] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -60434,10 +64507,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -60503,9 +64580,9 @@ sb_0__1__mux_2level_tapbuf_basis_input3_mem3_61 mux_l2_in_0_ ( .mem ( local_encoder2to3_1_data ) , .mem_inv ( local_encoder2to3_1_data_inv ) , .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_193 ( .A ( BUF_net_194 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_194 ( - .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_194 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_186 ( .A ( BUF_net_187 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_187 ( + .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_187 ) ) ; endmodule @@ -60517,10 +64594,14 @@ input [0:2] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -60531,10 +64612,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -60600,9 +64685,9 @@ sb_0__1__mux_2level_tapbuf_basis_input3_mem3_59 mux_l2_in_0_ ( .mem ( local_encoder2to3_1_data ) , .mem_inv ( local_encoder2to3_1_data_inv ) , .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_191 ( .A ( BUF_net_192 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_192 ( - .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_192 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_184 ( .A ( BUF_net_185 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_185 ( + .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_185 ) ) ; endmodule @@ -60614,10 +64699,14 @@ input [0:2] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -60628,10 +64717,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -60697,9 +64790,9 @@ sb_0__1__mux_2level_tapbuf_basis_input3_mem3_57 mux_l2_in_0_ ( .mem ( local_encoder2to3_1_data ) , .mem_inv ( local_encoder2to3_1_data_inv ) , .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_189 ( .A ( BUF_net_190 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_190 ( - .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_190 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_182 ( .A ( BUF_net_183 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_183 ( + .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_183 ) ) ; endmodule @@ -60711,10 +64804,14 @@ input [0:2] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -60725,10 +64822,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -60794,9 +64895,9 @@ sb_0__1__mux_2level_tapbuf_basis_input3_mem3_55 mux_l2_in_0_ ( .mem ( local_encoder2to3_1_data ) , .mem_inv ( local_encoder2to3_1_data_inv ) , .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_187 ( .A ( BUF_net_188 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_188 ( - .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_188 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_180 ( .A ( BUF_net_181 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_181 ( + .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_181 ) ) ; endmodule @@ -60808,10 +64909,14 @@ input [0:2] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -60822,10 +64927,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -60891,9 +65000,9 @@ sb_0__1__mux_2level_tapbuf_basis_input3_mem3_53 mux_l2_in_0_ ( .mem ( local_encoder2to3_1_data ) , .mem_inv ( local_encoder2to3_1_data_inv ) , .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_185 ( .A ( BUF_net_186 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_186 ( - .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_186 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_178 ( .A ( BUF_net_179 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_179 ( + .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_179 ) ) ; endmodule @@ -60905,10 +65014,14 @@ input [0:2] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -60919,10 +65032,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -60972,6 +65089,8 @@ wire [0:2] local_encoder2to3_1_data_inv ; wire [0:0] mux_2level_tapbuf_basis_input3_mem3_0_out ; wire [0:0] mux_2level_tapbuf_basis_input3_mem3_1_out ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .X ( out[0] ) ) ; sb_0__1__local_encoder2to3_42 local_encoder2to3_0_ ( .addr ( sram[0:1] ) , .data ( local_encoder2to3_0_data ) , .data_inv ( local_encoder2to3_0_data_inv ) ) ; @@ -60988,8 +65107,6 @@ sb_0__1__mux_2level_tapbuf_basis_input3_mem3_51 mux_l2_in_0_ ( .mem ( local_encoder2to3_1_data ) , .mem_inv ( local_encoder2to3_1_data_inv ) , .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_184 ( - .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .X ( out[0] ) ) ; endmodule @@ -61001,10 +65118,14 @@ input [0:2] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -61015,10 +65136,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -61084,9 +65209,8 @@ sb_0__1__mux_2level_tapbuf_basis_input3_mem3_49 mux_l2_in_0_ ( .mem ( local_encoder2to3_1_data ) , .mem_inv ( local_encoder2to3_1_data_inv ) , .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_182 ( .A ( BUF_net_183 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_183 ( - .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_183 ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_177 ( + .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .X ( out[0] ) ) ; endmodule @@ -61337,9 +65461,13 @@ input [0:1] mem ; input [0:1] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -61351,10 +65479,14 @@ input [0:2] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -61365,10 +65497,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -61419,8 +65555,6 @@ wire [0:0] mux_2level_tapbuf_basis_input2_mem2_0_out ; wire [0:0] mux_2level_tapbuf_basis_input3_mem3_0_out ; wire [0:0] mux_2level_tapbuf_basis_input3_mem3_1_out ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .X ( out[0] ) ) ; sb_0__1__local_encoder2to3_38 local_encoder2to3_0_ ( .addr ( sram[0:1] ) , .data ( local_encoder2to3_0_data ) , .data_inv ( local_encoder2to3_0_data_inv ) ) ; @@ -61442,6 +65576,9 @@ sb_0__1__mux_2level_tapbuf_basis_input2_mem2 mux_l1_in_1_ ( .in ( in[3:4] ) , .mem ( local_encoder2to3_0_data[0:1] ) , .mem_inv ( local_encoder2to3_0_data_inv[0:1] ) , .out ( mux_2level_tapbuf_basis_input2_mem2_0_out ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_205 ( .A ( BUF_net_206 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_206 ( + .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_206 ) ) ; endmodule @@ -61452,9 +65589,13 @@ input [0:1] mem ; input [0:1] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -61466,10 +65607,14 @@ input [0:2] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -61480,10 +65625,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -61567,9 +65716,13 @@ input [0:1] mem ; input [0:1] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -61581,10 +65734,14 @@ input [0:2] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -61595,10 +65752,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -61670,9 +65831,9 @@ sb_0__1__mux_2level_tapbuf_basis_input2_mem2_9 mux_l1_in_1_ ( .in ( in[3:4] ) , .mem ( local_encoder2to3_0_data[0:1] ) , .mem_inv ( local_encoder2to3_0_data_inv[0:1] ) , .out ( mux_2level_tapbuf_basis_input2_mem2_0_out ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_180 ( .A ( BUF_net_181 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_181 ( - .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_181 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_175 ( .A ( BUF_net_176 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_176 ( + .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_176 ) ) ; endmodule @@ -61683,9 +65844,13 @@ input [0:1] mem ; input [0:1] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -61697,10 +65862,14 @@ input [0:2] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -61711,10 +65880,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -61786,9 +65959,9 @@ sb_0__1__mux_2level_tapbuf_basis_input2_mem2_8 mux_l1_in_1_ ( .in ( in[3:4] ) , .mem ( local_encoder2to3_0_data[0:1] ) , .mem_inv ( local_encoder2to3_0_data_inv[0:1] ) , .out ( mux_2level_tapbuf_basis_input2_mem2_0_out ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_178 ( .A ( BUF_net_179 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_179 ( - .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_179 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_173 ( .A ( BUF_net_174 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_174 ( + .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_174 ) ) ; endmodule @@ -61799,9 +65972,13 @@ input [0:1] mem ; input [0:1] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -61813,10 +65990,14 @@ input [0:2] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -61827,10 +66008,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -61914,9 +66099,13 @@ input [0:1] mem ; input [0:1] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -61928,10 +66117,14 @@ input [0:2] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -61942,10 +66135,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -62017,9 +66214,9 @@ sb_0__1__mux_2level_tapbuf_basis_input2_mem2_6 mux_l1_in_1_ ( .in ( in[3:4] ) , .mem ( local_encoder2to3_0_data[0:1] ) , .mem_inv ( local_encoder2to3_0_data_inv[0:1] ) , .out ( mux_2level_tapbuf_basis_input2_mem2_0_out ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_176 ( .A ( BUF_net_177 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_177 ( - .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_177 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_171 ( .A ( BUF_net_172 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_172 ( + .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_172 ) ) ; endmodule @@ -62030,9 +66227,13 @@ input [0:1] mem ; input [0:1] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -62044,10 +66245,14 @@ input [0:2] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -62058,10 +66263,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -62133,9 +66342,9 @@ sb_0__1__mux_2level_tapbuf_basis_input2_mem2_5 mux_l1_in_1_ ( .in ( in[3:4] ) , .mem ( local_encoder2to3_0_data[0:1] ) , .mem_inv ( local_encoder2to3_0_data_inv[0:1] ) , .out ( mux_2level_tapbuf_basis_input2_mem2_0_out ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_174 ( .A ( BUF_net_175 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_175 ( - .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_175 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_169 ( .A ( BUF_net_170 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_170 ( + .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_170 ) ) ; endmodule @@ -62146,9 +66355,13 @@ input [0:1] mem ; input [0:1] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -62160,10 +66373,14 @@ input [0:2] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -62174,10 +66391,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -62249,9 +66470,8 @@ sb_0__1__mux_2level_tapbuf_basis_input2_mem2_4 mux_l1_in_1_ ( .in ( in[3:4] ) , .mem ( local_encoder2to3_0_data[0:1] ) , .mem_inv ( local_encoder2to3_0_data_inv[0:1] ) , .out ( mux_2level_tapbuf_basis_input2_mem2_0_out ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_172 ( .A ( BUF_net_173 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_173 ( - .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_173 ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_168 ( + .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .X ( out[0] ) ) ; endmodule @@ -62262,9 +66482,13 @@ input [0:1] mem ; input [0:1] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -62276,10 +66500,14 @@ input [0:2] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -62290,10 +66518,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -62344,8 +66576,6 @@ wire [0:0] mux_2level_tapbuf_basis_input2_mem2_0_out ; wire [0:0] mux_2level_tapbuf_basis_input3_mem3_0_out ; wire [0:0] mux_2level_tapbuf_basis_input3_mem3_1_out ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .X ( out[0] ) ) ; sb_0__1__local_encoder2to3_22 local_encoder2to3_0_ ( .addr ( sram[0:1] ) , .data ( local_encoder2to3_0_data ) , .data_inv ( local_encoder2to3_0_data_inv ) ) ; @@ -62367,6 +66597,9 @@ sb_0__1__mux_2level_tapbuf_basis_input2_mem2_3 mux_l1_in_1_ ( .in ( in[3:4] ) , .mem ( local_encoder2to3_0_data[0:1] ) , .mem_inv ( local_encoder2to3_0_data_inv[0:1] ) , .out ( mux_2level_tapbuf_basis_input2_mem2_0_out ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_166 ( .A ( BUF_net_167 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_167 ( + .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_167 ) ) ; endmodule @@ -62377,9 +66610,13 @@ input [0:1] mem ; input [0:1] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -62391,10 +66628,14 @@ input [0:2] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -62405,10 +66646,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -62480,9 +66725,9 @@ sb_0__1__mux_2level_tapbuf_basis_input2_mem2_2 mux_l1_in_1_ ( .in ( in[3:4] ) , .mem ( local_encoder2to3_0_data[0:1] ) , .mem_inv ( local_encoder2to3_0_data_inv[0:1] ) , .out ( mux_2level_tapbuf_basis_input2_mem2_0_out ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_170 ( .A ( BUF_net_171 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_171 ( - .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_171 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_164 ( .A ( BUF_net_165 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_165 ( + .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_165 ) ) ; endmodule @@ -62493,9 +66738,13 @@ input [0:1] mem ; input [0:1] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -62507,10 +66756,14 @@ input [0:2] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -62521,10 +66774,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -62596,9 +66853,8 @@ sb_0__1__mux_2level_tapbuf_basis_input2_mem2_1 mux_l1_in_1_ ( .in ( in[3:4] ) , .mem ( local_encoder2to3_0_data[0:1] ) , .mem_inv ( local_encoder2to3_0_data_inv[0:1] ) , .out ( mux_2level_tapbuf_basis_input2_mem2_0_out ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_168 ( .A ( BUF_net_169 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_169 ( - .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_169 ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_163 ( + .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .X ( out[0] ) ) ; endmodule @@ -62609,9 +66865,13 @@ input [0:1] mem ; input [0:1] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv2_1 scs8hd_muxinv2_1_0 ( .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0B ( mem_inv[0] ) , .S1B ( mem_inv[1] ) , .S0 ( mem[0] ) , - .S1 ( mem[1] ) , .Z ( out[0] ) ) ; + .S1 ( mem[1] ) , .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -62623,10 +66883,14 @@ input [0:2] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -62637,10 +66901,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -62712,9 +66980,9 @@ sb_0__1__mux_2level_tapbuf_basis_input2_mem2_0 mux_l1_in_1_ ( .in ( in[3:4] ) , .mem ( local_encoder2to3_0_data[0:1] ) , .mem_inv ( local_encoder2to3_0_data_inv[0:1] ) , .out ( mux_2level_tapbuf_basis_input2_mem2_0_out ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_218 ( .A ( BUF_net_219 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_219 ( - .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_219 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_203 ( .A ( BUF_net_204 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_204 ( + .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_204 ) ) ; endmodule @@ -62866,7 +67134,7 @@ input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ropt_net_245 ) , +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ropt_net_236 ) , .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; @@ -62875,34 +67143,26 @@ sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__buf_1 FTB_17__16 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1417 ( .A ( ccff_head[0] ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1412 ( .A ( ccff_head[0] ) , + .X ( copt_net_222 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1413 ( .A ( copt_net_224 ) , + .X ( copt_net_223 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1414 ( .A ( copt_net_222 ) , + .X ( copt_net_224 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1415 ( .A ( copt_net_226 ) , + .X ( copt_net_225 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1416 ( .A ( ropt_net_238 ) , + .X ( copt_net_226 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1417 ( .A ( copt_net_223 ) , .X ( copt_net_227 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1418 ( .A ( ropt_net_249 ) , - .X ( copt_net_228 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1419 ( .A ( copt_net_228 ) , - .X ( copt_net_229 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1420 ( .A ( copt_net_229 ) , - .X ( copt_net_230 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1421 ( .A ( ropt_net_248 ) , - .X ( copt_net_231 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1422 ( .A ( copt_net_230 ) , - .X ( copt_net_232 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1432 ( .A ( copt_net_231 ) , - .X ( ropt_net_243 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1433 ( .A ( ropt_net_243 ) , - .X ( ropt_net_244 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1434 ( .A ( ropt_net_246 ) , - .X ( ropt_net_245 ) ) ; -sky130_fd_sc_hd__buf_2 ropt_h_inst_1435 ( .A ( ropt_net_244 ) , - .X ( ropt_net_246 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1436 ( .A ( copt_net_232 ) , - .X ( ropt_net_247 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1437 ( .A ( ropt_net_247 ) , - .X ( ropt_net_248 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1438 ( .A ( ropt_net_250 ) , - .X ( ropt_net_249 ) ) ; -sky130_fd_sc_hd__buf_2 ropt_h_inst_1439 ( .A ( copt_net_227 ) , - .X ( ropt_net_250 ) ) ; +sky130_fd_sc_hd__buf_1 ropt_h_inst_1426 ( .A ( ropt_net_239 ) , + .X ( ropt_net_236 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1427 ( .A ( copt_net_227 ) , + .X ( ropt_net_237 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1428 ( .A ( ropt_net_237 ) , + .X ( ropt_net_238 ) ) ; +sky130_fd_sc_hd__buf_1 ropt_h_inst_1429 ( .A ( copt_net_225 ) , + .X ( ropt_net_239 ) ) ; endmodule @@ -62914,10 +67174,14 @@ input [0:2] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -62928,10 +67192,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -62942,10 +67210,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -62996,6 +67268,8 @@ wire [0:0] mux_2level_tapbuf_basis_input3_mem3_0_out ; wire [0:0] mux_2level_tapbuf_basis_input3_mem3_1_out ; wire [0:0] mux_2level_tapbuf_basis_input3_mem3_2_out ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( mux_2level_tapbuf_basis_input3_mem3_2_out[0] ) , .X ( out[0] ) ) ; sb_0__1__local_encoder2to3_14 local_encoder2to3_0_ ( .addr ( sram[0:1] ) , .data ( local_encoder2to3_0_data ) , .data_inv ( local_encoder2to3_0_data_inv ) ) ; @@ -63017,9 +67291,6 @@ sb_0__1__mux_2level_tapbuf_basis_input3_mem3_23 mux_l2_in_0_ ( .mem ( local_encoder2to3_1_data ) , .mem_inv ( local_encoder2to3_1_data_inv ) , .out ( mux_2level_tapbuf_basis_input3_mem3_2_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_166 ( .A ( BUF_net_167 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_167 ( - .A ( mux_2level_tapbuf_basis_input3_mem3_2_out[0] ) , .Y ( BUF_net_167 ) ) ; endmodule @@ -63031,10 +67302,14 @@ input [0:2] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -63045,10 +67320,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -63059,10 +67338,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -63134,9 +67417,9 @@ sb_0__1__mux_2level_tapbuf_basis_input3_mem3_20 mux_l2_in_0_ ( .mem ( local_encoder2to3_1_data ) , .mem_inv ( local_encoder2to3_1_data_inv ) , .out ( mux_2level_tapbuf_basis_input3_mem3_2_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_164 ( .A ( BUF_net_165 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_165 ( - .A ( mux_2level_tapbuf_basis_input3_mem3_2_out[0] ) , .Y ( BUF_net_165 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_161 ( .A ( BUF_net_162 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_162 ( + .A ( mux_2level_tapbuf_basis_input3_mem3_2_out[0] ) , .Y ( BUF_net_162 ) ) ; endmodule @@ -63148,10 +67431,14 @@ input [0:2] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -63162,10 +67449,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -63176,10 +67467,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -63251,9 +67546,9 @@ sb_0__1__mux_2level_tapbuf_basis_input3_mem3_17 mux_l2_in_0_ ( .mem ( local_encoder2to3_1_data ) , .mem_inv ( local_encoder2to3_1_data_inv ) , .out ( mux_2level_tapbuf_basis_input3_mem3_2_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_162 ( .A ( BUF_net_163 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_163 ( - .A ( mux_2level_tapbuf_basis_input3_mem3_2_out[0] ) , .Y ( BUF_net_163 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_159 ( .A ( BUF_net_160 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_160 ( + .A ( mux_2level_tapbuf_basis_input3_mem3_2_out[0] ) , .Y ( BUF_net_160 ) ) ; endmodule @@ -63265,10 +67560,14 @@ input [0:2] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -63279,10 +67578,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -63293,10 +67596,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -63368,9 +67675,9 @@ sb_0__1__mux_2level_tapbuf_basis_input3_mem3_14 mux_l2_in_0_ ( .mem ( local_encoder2to3_1_data ) , .mem_inv ( local_encoder2to3_1_data_inv ) , .out ( mux_2level_tapbuf_basis_input3_mem3_2_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_160 ( .A ( BUF_net_161 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_161 ( - .A ( mux_2level_tapbuf_basis_input3_mem3_2_out[0] ) , .Y ( BUF_net_161 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_157 ( .A ( BUF_net_158 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_158 ( + .A ( mux_2level_tapbuf_basis_input3_mem3_2_out[0] ) , .Y ( BUF_net_158 ) ) ; endmodule @@ -63382,10 +67689,14 @@ input [0:2] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -63396,10 +67707,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -63410,10 +67725,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -63485,9 +67804,9 @@ sb_0__1__mux_2level_tapbuf_basis_input3_mem3_11 mux_l2_in_0_ ( .mem ( local_encoder2to3_1_data ) , .mem_inv ( local_encoder2to3_1_data_inv ) , .out ( mux_2level_tapbuf_basis_input3_mem3_2_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_158 ( .A ( BUF_net_159 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_159 ( - .A ( mux_2level_tapbuf_basis_input3_mem3_2_out[0] ) , .Y ( BUF_net_159 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_155 ( .A ( BUF_net_156 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_156 ( + .A ( mux_2level_tapbuf_basis_input3_mem3_2_out[0] ) , .Y ( BUF_net_156 ) ) ; endmodule @@ -63499,10 +67818,14 @@ input [0:2] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -63513,10 +67836,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -63527,10 +67854,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -63581,6 +67912,8 @@ wire [0:0] mux_2level_tapbuf_basis_input3_mem3_0_out ; wire [0:0] mux_2level_tapbuf_basis_input3_mem3_1_out ; wire [0:0] mux_2level_tapbuf_basis_input3_mem3_2_out ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( mux_2level_tapbuf_basis_input3_mem3_2_out[0] ) , .X ( out[0] ) ) ; sb_0__1__local_encoder2to3_4 local_encoder2to3_0_ ( .addr ( sram[0:1] ) , .data ( local_encoder2to3_0_data ) , .data_inv ( local_encoder2to3_0_data_inv ) ) ; @@ -63602,9 +67935,6 @@ sb_0__1__mux_2level_tapbuf_basis_input3_mem3_8 mux_l2_in_0_ ( .mem ( local_encoder2to3_1_data ) , .mem_inv ( local_encoder2to3_1_data_inv ) , .out ( mux_2level_tapbuf_basis_input3_mem3_2_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_156 ( .A ( BUF_net_157 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_157 ( - .A ( mux_2level_tapbuf_basis_input3_mem3_2_out[0] ) , .Y ( BUF_net_157 ) ) ; endmodule @@ -63616,10 +67946,14 @@ input [0:2] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -63630,10 +67964,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -63644,10 +67982,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -63719,8 +68061,9 @@ sb_0__1__mux_2level_tapbuf_basis_input3_mem3_5 mux_l2_in_0_ ( .mem ( local_encoder2to3_1_data ) , .mem_inv ( local_encoder2to3_1_data_inv ) , .out ( mux_2level_tapbuf_basis_input3_mem3_2_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_155 ( - .A ( mux_2level_tapbuf_basis_input3_mem3_2_out[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_153 ( .A ( BUF_net_154 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_154 ( + .A ( mux_2level_tapbuf_basis_input3_mem3_2_out[0] ) , .Y ( BUF_net_154 ) ) ; endmodule @@ -63732,10 +68075,14 @@ input [0:2] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -63746,10 +68093,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -63760,10 +68111,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -63814,6 +68169,8 @@ wire [0:0] mux_2level_tapbuf_basis_input3_mem3_0_out ; wire [0:0] mux_2level_tapbuf_basis_input3_mem3_1_out ; wire [0:0] mux_2level_tapbuf_basis_input3_mem3_2_out ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( mux_2level_tapbuf_basis_input3_mem3_2_out[0] ) , .X ( out[0] ) ) ; sb_0__1__local_encoder2to3_0 local_encoder2to3_0_ ( .addr ( sram[0:1] ) , .data ( local_encoder2to3_0_data ) , .data_inv ( local_encoder2to3_0_data_inv ) ) ; @@ -63835,9 +68192,6 @@ sb_0__1__mux_2level_tapbuf_basis_input3_mem3_2 mux_l2_in_0_ ( .mem ( local_encoder2to3_1_data ) , .mem_inv ( local_encoder2to3_1_data_inv ) , .out ( mux_2level_tapbuf_basis_input3_mem3_2_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_153 ( .A ( BUF_net_154 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_154 ( - .A ( mux_2level_tapbuf_basis_input3_mem3_2_out[0] ) , .Y ( BUF_net_154 ) ) ; endmodule @@ -63982,21 +68336,21 @@ sb_0__1__mux_2level_tapbuf_size6_0 mux_top_track_0 ( .sram ( mux_2level_tapbuf_size6_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 , SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) , - .out ( chany_top_out[0] ) , .p0 ( optlc_net_220 ) ) ; + .out ( chany_top_out[0] ) , .p0 ( optlc_net_219 ) ) ; sb_0__1__mux_2level_tapbuf_size6_1 mux_top_track_6 ( .in ( { top_left_grid_pin_1_[0] , chanx_right_in[4] , chanx_right_in[15] , chanx_right_in[26] , chany_top_out[9] , chany_top_out[24] } ) , .sram ( mux_2level_tapbuf_size6_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 , SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 } ) , - .out ( chany_top_out[3] ) , .p0 ( optlc_net_220 ) ) ; + .out ( chany_top_out[3] ) , .p0 ( optlc_net_215 ) ) ; sb_0__1__mux_2level_tapbuf_size6_2 mux_top_track_12 ( .in ( { top_left_grid_pin_1_[0] , chanx_right_in[6] , chanx_right_in[17] , chanx_right_in[28] , chany_top_out[12] , chany_top_out[27] } ) , .sram ( mux_2level_tapbuf_size6_2_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_9 , SYNOPSYS_UNCONNECTED_10 , SYNOPSYS_UNCONNECTED_11 , SYNOPSYS_UNCONNECTED_12 } ) , - .out ( chany_top_out[6] ) , .p0 ( optlc_net_225 ) ) ; + .out ( chany_top_out[6] ) , .p0 ( optlc_net_219 ) ) ; sb_0__1__mux_2level_tapbuf_size6_3 mux_right_track_2 ( .in ( { chany_top_in[0] , chany_bottom_out[7] , right_bottom_grid_pin_37_[0] , right_bottom_grid_pin_40_[0] , @@ -64004,7 +68358,7 @@ sb_0__1__mux_2level_tapbuf_size6_3 mux_right_track_2 ( .sram ( mux_2level_tapbuf_size6_3_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 , SYNOPSYS_UNCONNECTED_15 , SYNOPSYS_UNCONNECTED_16 } ) , - .out ( chanx_right_out[1] ) , .p0 ( optlc_net_223 ) ) ; + .out ( chanx_right_out[1] ) , .p0 ( optlc_net_215 ) ) ; sb_0__1__mux_2level_tapbuf_size6_4 mux_right_track_6 ( .in ( { chany_top_in[2] , chany_bottom_out[9] , right_bottom_grid_pin_36_[0] , right_bottom_grid_pin_39_[0] , @@ -64012,7 +68366,7 @@ sb_0__1__mux_2level_tapbuf_size6_4 mux_right_track_6 ( .sram ( mux_2level_tapbuf_size6_4_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_17 , SYNOPSYS_UNCONNECTED_18 , SYNOPSYS_UNCONNECTED_19 , SYNOPSYS_UNCONNECTED_20 } ) , - .out ( chanx_right_out[3] ) , .p0 ( optlc_net_222 ) ) ; + .out ( chanx_right_out[3] ) , .p0 ( optlc_net_217 ) ) ; sb_0__1__mux_2level_tapbuf_size6_5 mux_right_track_8 ( .in ( { chany_top_in[4] , chany_bottom_out[11] , right_bottom_grid_pin_37_[0] , right_bottom_grid_pin_40_[0] , @@ -64020,21 +68374,21 @@ sb_0__1__mux_2level_tapbuf_size6_5 mux_right_track_8 ( .sram ( mux_2level_tapbuf_size6_5_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_21 , SYNOPSYS_UNCONNECTED_22 , SYNOPSYS_UNCONNECTED_23 , SYNOPSYS_UNCONNECTED_24 } ) , - .out ( chanx_right_out[4] ) , .p0 ( optlc_net_222 ) ) ; + .out ( chanx_right_out[4] ) , .p0 ( optlc_net_217 ) ) ; sb_0__1__mux_2level_tapbuf_size6_6 mux_bottom_track_7 ( .in ( { chany_bottom_out[9] , chany_bottom_out[24] , chanx_right_in[6] , chanx_right_in[17] , chanx_right_in[28] , bottom_left_grid_pin_1_[0] } ) , .sram ( mux_2level_tapbuf_size6_6_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_25 , SYNOPSYS_UNCONNECTED_26 , SYNOPSYS_UNCONNECTED_27 , SYNOPSYS_UNCONNECTED_28 } ) , - .out ( chany_bottom_out[3] ) , .p0 ( optlc_net_221 ) ) ; + .out ( chany_bottom_out[3] ) , .p0 ( optlc_net_220 ) ) ; sb_0__1__mux_2level_tapbuf_size6 mux_bottom_track_13 ( .in ( { chany_bottom_out[12] , chany_bottom_out[27] , chanx_right_in[4] , chanx_right_in[15] , chanx_right_in[26] , bottom_left_grid_pin_1_[0] } ) , .sram ( mux_2level_tapbuf_size6_7_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_29 , SYNOPSYS_UNCONNECTED_30 , SYNOPSYS_UNCONNECTED_31 , SYNOPSYS_UNCONNECTED_32 } ) , - .out ( chany_bottom_out[6] ) , .p0 ( optlc_net_221 ) ) ; + .out ( chany_bottom_out[6] ) , .p0 ( optlc_net_216 ) ) ; sb_0__1__mux_2level_tapbuf_size6_mem_0 mem_top_track_0 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( mux_2level_tapbuf_size6_mem_0_ccff_tail ) , @@ -64080,28 +68434,28 @@ sb_0__1__mux_2level_tapbuf_size5_0 mux_top_track_2 ( .sram ( mux_2level_tapbuf_size5_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_33 , SYNOPSYS_UNCONNECTED_34 , SYNOPSYS_UNCONNECTED_35 , SYNOPSYS_UNCONNECTED_36 } ) , - .out ( chany_top_out[1] ) , .p0 ( optlc_net_220 ) ) ; + .out ( chany_top_out[1] ) , .p0 ( optlc_net_215 ) ) ; sb_0__1__mux_2level_tapbuf_size5_1 mux_top_track_4 ( .in ( { chanx_right_in[3] , chanx_right_in[14] , chanx_right_in[25] , chany_top_out[8] , chany_top_out[23] } ) , .sram ( mux_2level_tapbuf_size5_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_37 , SYNOPSYS_UNCONNECTED_38 , SYNOPSYS_UNCONNECTED_39 , SYNOPSYS_UNCONNECTED_40 } ) , - .out ( chany_top_out[2] ) , .p0 ( optlc_net_220 ) ) ; + .out ( chany_top_out[2] ) , .p0 ( optlc_net_215 ) ) ; sb_0__1__mux_2level_tapbuf_size5_2 mux_top_track_10 ( .in ( { chanx_right_in[5] , chanx_right_in[16] , chanx_right_in[27] , chany_top_out[11] , chany_top_out[25] } ) , .sram ( mux_2level_tapbuf_size5_2_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_41 , SYNOPSYS_UNCONNECTED_42 , SYNOPSYS_UNCONNECTED_43 , SYNOPSYS_UNCONNECTED_44 } ) , - .out ( chany_top_out[5] ) , .p0 ( optlc_net_222 ) ) ; + .out ( chany_top_out[5] ) , .p0 ( optlc_net_217 ) ) ; sb_0__1__mux_2level_tapbuf_size5_3 mux_top_track_20 ( .in ( { chanx_right_in[7] , chanx_right_in[18] , chanx_right_in[29] , chany_top_out[13] , chany_top_out[28] } ) , .sram ( mux_2level_tapbuf_size5_3_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_45 , SYNOPSYS_UNCONNECTED_46 , SYNOPSYS_UNCONNECTED_47 , SYNOPSYS_UNCONNECTED_48 } ) , - .out ( chany_top_out[10] ) , .p0 ( optlc_net_225 ) ) ; + .out ( chany_top_out[10] ) , .p0 ( optlc_net_219 ) ) ; sb_0__1__mux_2level_tapbuf_size5_4 mux_right_track_0 ( .in ( { chany_bottom_out[4] , right_bottom_grid_pin_36_[0] , right_bottom_grid_pin_39_[0] , right_bottom_grid_pin_42_[0] , @@ -64109,7 +68463,7 @@ sb_0__1__mux_2level_tapbuf_size5_4 mux_right_track_0 ( .sram ( mux_2level_tapbuf_size5_4_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_49 , SYNOPSYS_UNCONNECTED_50 , SYNOPSYS_UNCONNECTED_51 , SYNOPSYS_UNCONNECTED_52 } ) , - .out ( chanx_right_out[0] ) , .p0 ( optlc_net_223 ) ) ; + .out ( chanx_right_out[0] ) , .p0 ( optlc_net_215 ) ) ; sb_0__1__mux_2level_tapbuf_size5_5 mux_right_track_4 ( .in ( { chany_top_in[1] , chany_bottom_out[8] , right_bottom_grid_pin_38_[0] , right_bottom_grid_pin_41_[0] , @@ -64117,7 +68471,7 @@ sb_0__1__mux_2level_tapbuf_size5_5 mux_right_track_4 ( .sram ( mux_2level_tapbuf_size5_5_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_53 , SYNOPSYS_UNCONNECTED_54 , SYNOPSYS_UNCONNECTED_55 , SYNOPSYS_UNCONNECTED_56 } ) , - .out ( chanx_right_out[2] ) , .p0 ( optlc_net_222 ) ) ; + .out ( chanx_right_out[2] ) , .p0 ( optlc_net_217 ) ) ; sb_0__1__mux_2level_tapbuf_size5_6 mux_right_track_10 ( .in ( { chany_top_in[5] , chany_bottom_out[12] , right_bottom_grid_pin_38_[0] , right_bottom_grid_pin_41_[0] , @@ -64125,7 +68479,7 @@ sb_0__1__mux_2level_tapbuf_size5_6 mux_right_track_10 ( .sram ( mux_2level_tapbuf_size5_6_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_57 , SYNOPSYS_UNCONNECTED_58 , SYNOPSYS_UNCONNECTED_59 , SYNOPSYS_UNCONNECTED_60 } ) , - .out ( chanx_right_out[5] ) , .p0 ( optlc_net_222 ) ) ; + .out ( chanx_right_out[5] ) , .p0 ( optlc_net_217 ) ) ; sb_0__1__mux_2level_tapbuf_size5_7 mux_bottom_track_1 ( .in ( { chany_bottom_out[4] , chany_bottom_out[20] , chanx_right_in[9] , chanx_right_in[20] , bottom_left_grid_pin_1_[0] } ) , @@ -64139,28 +68493,28 @@ sb_0__1__mux_2level_tapbuf_size5_8 mux_bottom_track_5 ( .sram ( mux_2level_tapbuf_size5_8_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_65 , SYNOPSYS_UNCONNECTED_66 , SYNOPSYS_UNCONNECTED_67 , SYNOPSYS_UNCONNECTED_68 } ) , - .out ( chany_bottom_out[2] ) , .p0 ( optlc_net_225 ) ) ; + .out ( chany_bottom_out[2] ) , .p0 ( optlc_net_221 ) ) ; sb_0__1__mux_2level_tapbuf_size5_9 mux_bottom_track_11 ( .in ( { chany_bottom_out[11] , chany_bottom_out[25] , chanx_right_in[5] , chanx_right_in[16] , chanx_right_in[27] } ) , .sram ( mux_2level_tapbuf_size5_9_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_69 , SYNOPSYS_UNCONNECTED_70 , SYNOPSYS_UNCONNECTED_71 , SYNOPSYS_UNCONNECTED_72 } ) , - .out ( chany_bottom_out[5] ) , .p0 ( optlc_net_221 ) ) ; + .out ( chany_bottom_out[5] ) , .p0 ( optlc_net_216 ) ) ; sb_0__1__mux_2level_tapbuf_size5_10 mux_bottom_track_21 ( .in ( { chany_bottom_out[13] , chany_bottom_out[28] , chanx_right_in[3] , chanx_right_in[14] , chanx_right_in[25] } ) , .sram ( mux_2level_tapbuf_size5_10_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_73 , SYNOPSYS_UNCONNECTED_74 , SYNOPSYS_UNCONNECTED_75 , SYNOPSYS_UNCONNECTED_76 } ) , - .out ( chany_bottom_out[10] ) , .p0 ( optlc_net_224 ) ) ; + .out ( chany_bottom_out[10] ) , .p0 ( optlc_net_218 ) ) ; sb_0__1__mux_2level_tapbuf_size5 mux_bottom_track_29 ( .in ( { chany_bottom_out[15] , chany_bottom_out[29] , chanx_right_in[2] , chanx_right_in[13] , chanx_right_in[24] } ) , .sram ( mux_2level_tapbuf_size5_11_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_77 , SYNOPSYS_UNCONNECTED_78 , SYNOPSYS_UNCONNECTED_79 , SYNOPSYS_UNCONNECTED_80 } ) , - .out ( chany_bottom_out[14] ) , .p0 ( optlc_net_224 ) ) ; + .out ( chany_bottom_out[14] ) , .p0 ( optlc_net_221 ) ) ; sb_0__1__mux_2level_tapbuf_size5_mem_0 mem_top_track_2 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( mux_2level_tapbuf_size6_mem_0_ccff_tail ) , @@ -64227,84 +68581,84 @@ sb_0__1__mux_2level_tapbuf_size4_0 mux_top_track_28 ( .sram ( mux_2level_tapbuf_size4_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_81 , SYNOPSYS_UNCONNECTED_82 , SYNOPSYS_UNCONNECTED_83 , SYNOPSYS_UNCONNECTED_84 } ) , - .out ( chany_top_out[14] ) , .p0 ( optlc_net_223 ) ) ; + .out ( chany_top_out[14] ) , .p0 ( optlc_net_221 ) ) ; sb_0__1__mux_2level_tapbuf_size4_1 mux_top_track_52 ( .in ( { chanx_right_in[0] , chanx_right_in[11] , chanx_right_in[22] , chany_top_out[19] } ) , .sram ( mux_2level_tapbuf_size4_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_85 , SYNOPSYS_UNCONNECTED_86 , SYNOPSYS_UNCONNECTED_87 , SYNOPSYS_UNCONNECTED_88 } ) , - .out ( chany_top_out[26] ) , .p0 ( optlc_net_226 ) ) ; + .out ( chany_top_out[26] ) , .p0 ( optlc_net_217 ) ) ; sb_0__1__mux_2level_tapbuf_size4_2 mux_right_track_12 ( .in ( { chany_top_in[9] , chany_bottom_out[13] , right_bottom_grid_pin_36_[0] , chany_top_out[13] } ) , .sram ( mux_2level_tapbuf_size4_2_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_89 , SYNOPSYS_UNCONNECTED_90 , SYNOPSYS_UNCONNECTED_91 , SYNOPSYS_UNCONNECTED_92 } ) , - .out ( chanx_right_out[6] ) , .p0 ( optlc_net_226 ) ) ; + .out ( chanx_right_out[6] ) , .p0 ( optlc_net_219 ) ) ; sb_0__1__mux_2level_tapbuf_size4_3 mux_right_track_14 ( .in ( { chany_top_in[13] , chany_bottom_out[15] , right_bottom_grid_pin_37_[0] , chany_top_out[15] } ) , .sram ( mux_2level_tapbuf_size4_3_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_93 , SYNOPSYS_UNCONNECTED_94 , SYNOPSYS_UNCONNECTED_95 , SYNOPSYS_UNCONNECTED_96 } ) , - .out ( chanx_right_out[7] ) , .p0 ( optlc_net_223 ) ) ; + .out ( chanx_right_out[7] ) , .p0 ( optlc_net_219 ) ) ; sb_0__1__mux_2level_tapbuf_size4_4 mux_right_track_16 ( .in ( { chany_bottom_out[16] , chany_top_in[17] , right_bottom_grid_pin_38_[0] , chany_top_out[16] } ) , .sram ( mux_2level_tapbuf_size4_4_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_97 , SYNOPSYS_UNCONNECTED_98 , SYNOPSYS_UNCONNECTED_99 , SYNOPSYS_UNCONNECTED_100 } ) , - .out ( chanx_right_out[8] ) , .p0 ( optlc_net_223 ) ) ; + .out ( chanx_right_out[8] ) , .p0 ( optlc_net_219 ) ) ; sb_0__1__mux_2level_tapbuf_size4_5 mux_right_track_18 ( .in ( { chany_bottom_out[17] , chany_top_in[21] , right_bottom_grid_pin_39_[0] , chany_top_out[17] } ) , .sram ( mux_2level_tapbuf_size4_5_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_101 , SYNOPSYS_UNCONNECTED_102 , SYNOPSYS_UNCONNECTED_103 , SYNOPSYS_UNCONNECTED_104 } ) , - .out ( chanx_right_out[9] ) , .p0 ( optlc_net_223 ) ) ; + .out ( chanx_right_out[9] ) , .p0 ( optlc_net_219 ) ) ; sb_0__1__mux_2level_tapbuf_size4_6 mux_right_track_20 ( .in ( { chany_bottom_out[19] , chany_top_in[25] , right_bottom_grid_pin_40_[0] , chany_top_out[19] } ) , .sram ( mux_2level_tapbuf_size4_6_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_105 , SYNOPSYS_UNCONNECTED_106 , SYNOPSYS_UNCONNECTED_107 , SYNOPSYS_UNCONNECTED_108 } ) , - .out ( chanx_right_out[10] ) , .p0 ( optlc_net_223 ) ) ; + .out ( chanx_right_out[10] ) , .p0 ( optlc_net_215 ) ) ; sb_0__1__mux_2level_tapbuf_size4_7 mux_right_track_22 ( .in ( { chany_bottom_out[20] , chany_top_in[29] , right_bottom_grid_pin_41_[0] , chany_top_out[20] } ) , .sram ( mux_2level_tapbuf_size4_7_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_109 , SYNOPSYS_UNCONNECTED_110 , SYNOPSYS_UNCONNECTED_111 , SYNOPSYS_UNCONNECTED_112 } ) , - .out ( chanx_right_out[11] ) , .p0 ( optlc_net_223 ) ) ; + .out ( chanx_right_out[11] ) , .p0 ( optlc_net_215 ) ) ; sb_0__1__mux_2level_tapbuf_size4_8 mux_right_track_36 ( .in ( { chany_bottom_out[29] , right_bottom_grid_pin_40_[0] , chany_top_out[29] , chany_bottom_in[29] } ) , .sram ( mux_2level_tapbuf_size4_8_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_113 , SYNOPSYS_UNCONNECTED_114 , SYNOPSYS_UNCONNECTED_115 , SYNOPSYS_UNCONNECTED_116 } ) , - .out ( chanx_right_out[18] ) , .p0 ( optlc_net_221 ) ) ; + .out ( chanx_right_out[18] ) , .p0 ( optlc_net_218 ) ) ; sb_0__1__mux_2level_tapbuf_size4_9 mux_bottom_track_3 ( .in ( { chany_bottom_out[7] , chany_bottom_out[21] , chanx_right_in[8] , chanx_right_in[19] } ) , .sram ( mux_2level_tapbuf_size4_9_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_117 , SYNOPSYS_UNCONNECTED_118 , SYNOPSYS_UNCONNECTED_119 , SYNOPSYS_UNCONNECTED_120 } ) , - .out ( chany_bottom_out[1] ) , .p0 ( optlc_net_225 ) ) ; + .out ( chany_bottom_out[1] ) , .p0 ( optlc_net_220 ) ) ; sb_0__1__mux_2level_tapbuf_size4_10 mux_bottom_track_37 ( .in ( { chany_bottom_out[16] , chanx_right_in[1] , chanx_right_in[12] , chanx_right_in[23] } ) , .sram ( mux_2level_tapbuf_size4_10_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_121 , SYNOPSYS_UNCONNECTED_122 , SYNOPSYS_UNCONNECTED_123 , SYNOPSYS_UNCONNECTED_124 } ) , - .out ( chany_bottom_out[18] ) , .p0 ( optlc_net_224 ) ) ; + .out ( chany_bottom_out[18] ) , .p0 ( optlc_net_221 ) ) ; sb_0__1__mux_2level_tapbuf_size4 mux_bottom_track_45 ( .in ( { chany_bottom_out[17] , chanx_right_in[0] , chanx_right_in[11] , chanx_right_in[22] } ) , .sram ( mux_2level_tapbuf_size4_11_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_125 , SYNOPSYS_UNCONNECTED_126 , SYNOPSYS_UNCONNECTED_127 , SYNOPSYS_UNCONNECTED_128 } ) , - .out ( chany_bottom_out[22] ) , .p0 ( optlc_net_224 ) ) ; + .out ( chany_bottom_out[22] ) , .p0 ( optlc_net_216 ) ) ; sb_0__1__mux_2level_tapbuf_size4_mem_0 mem_top_track_28 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( mux_2level_tapbuf_size5_mem_3_ccff_tail ) , @@ -64369,59 +68723,59 @@ sb_0__1__mux_2level_tapbuf_size3_0 mux_top_track_36 ( .in ( { chanx_right_in[9] , chanx_right_in[20] , chany_top_out[16] } ) , .sram ( mux_2level_tapbuf_size3_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_129 , SYNOPSYS_UNCONNECTED_130 } ) , - .out ( chany_top_out[18] ) , .p0 ( optlc_net_226 ) ) ; + .out ( chany_top_out[18] ) , .p0 ( optlc_net_221 ) ) ; sb_0__1__mux_2level_tapbuf_size3_1 mux_top_track_44 ( .in ( { chanx_right_in[10] , chanx_right_in[21] , chany_top_out[17] } ) , .sram ( mux_2level_tapbuf_size3_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_131 , SYNOPSYS_UNCONNECTED_132 } ) , - .out ( chany_top_out[22] ) , .p0 ( optlc_net_226 ) ) ; + .out ( chany_top_out[22] ) , .p0 ( optlc_net_221 ) ) ; sb_0__1__mux_2level_tapbuf_size3_2 mux_right_track_24 ( .in ( { chany_bottom_out[21] , right_bottom_grid_pin_42_[0] , chany_top_out[21] } ) , .sram ( mux_2level_tapbuf_size3_2_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_133 , SYNOPSYS_UNCONNECTED_134 } ) , - .out ( chanx_right_out[12] ) , .p0 ( optlc_net_225 ) ) ; + .out ( chanx_right_out[12] ) , .p0 ( optlc_net_218 ) ) ; sb_0__1__mux_2level_tapbuf_size3_3 mux_right_track_26 ( .in ( { chany_bottom_out[23] , right_bottom_grid_pin_43_[0] , chany_top_out[23] } ) , .sram ( mux_2level_tapbuf_size3_3_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_135 , SYNOPSYS_UNCONNECTED_136 } ) , - .out ( chanx_right_out[13] ) , .p0 ( optlc_net_221 ) ) ; + .out ( chanx_right_out[13] ) , .p0 ( optlc_net_218 ) ) ; sb_0__1__mux_2level_tapbuf_size3_4 mux_right_track_28 ( .in ( { chany_bottom_out[24] , right_bottom_grid_pin_36_[0] , chany_top_out[24] } ) , .sram ( mux_2level_tapbuf_size3_4_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_137 , SYNOPSYS_UNCONNECTED_138 } ) , - .out ( chanx_right_out[14] ) , .p0 ( optlc_net_221 ) ) ; + .out ( chanx_right_out[14] ) , .p0 ( optlc_net_216 ) ) ; sb_0__1__mux_2level_tapbuf_size3_5 mux_right_track_30 ( .in ( { chany_bottom_out[25] , right_bottom_grid_pin_37_[0] , chany_top_out[25] } ) , .sram ( mux_2level_tapbuf_size3_5_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_139 , SYNOPSYS_UNCONNECTED_140 } ) , - .out ( chanx_right_out[15] ) , .p0 ( optlc_net_221 ) ) ; + .out ( chanx_right_out[15] ) , .p0 ( optlc_net_216 ) ) ; sb_0__1__mux_2level_tapbuf_size3_6 mux_right_track_32 ( .in ( { chany_bottom_out[27] , right_bottom_grid_pin_38_[0] , chany_top_out[27] } ) , .sram ( mux_2level_tapbuf_size3_6_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_141 , SYNOPSYS_UNCONNECTED_142 } ) , - .out ( chanx_right_out[16] ) , .p0 ( optlc_net_221 ) ) ; + .out ( chanx_right_out[16] ) , .p0 ( optlc_net_218 ) ) ; sb_0__1__mux_2level_tapbuf_size3_7 mux_right_track_34 ( .in ( { chany_bottom_out[28] , right_bottom_grid_pin_39_[0] , chany_top_out[28] } ) , .sram ( mux_2level_tapbuf_size3_7_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_143 , SYNOPSYS_UNCONNECTED_144 } ) , - .out ( chanx_right_out[17] ) , .p0 ( optlc_net_221 ) ) ; + .out ( chanx_right_out[17] ) , .p0 ( optlc_net_218 ) ) ; sb_0__1__mux_2level_tapbuf_size3_8 mux_right_track_50 ( .in ( { right_bottom_grid_pin_39_[0] , right_bottom_grid_pin_43_[0] , chany_bottom_in[4] } ) , .sram ( mux_2level_tapbuf_size3_8_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_145 , SYNOPSYS_UNCONNECTED_146 } ) , - .out ( chanx_right_out[25] ) , .p0 ( optlc_net_221 ) ) ; + .out ( chanx_right_out[25] ) , .p0 ( optlc_net_218 ) ) ; sb_0__1__mux_2level_tapbuf_size3 mux_bottom_track_53 ( .in ( { chany_bottom_out[19] , chanx_right_in[10] , chanx_right_in[21] } ) , .sram ( mux_2level_tapbuf_size3_9_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_147 , SYNOPSYS_UNCONNECTED_148 } ) , - .out ( chany_bottom_out[26] ) , .p0 ( optlc_net_224 ) ) ; + .out ( chany_bottom_out[26] ) , .p0 ( optlc_net_218 ) ) ; sb_0__1__mux_2level_tapbuf_size3_mem_0 mem_top_track_36 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( mux_2level_tapbuf_size4_mem_0_ccff_tail ) , @@ -64475,42 +68829,42 @@ sb_0__1__mux_2level_tapbuf_size2_0 mux_right_track_38 ( .in ( { right_bottom_grid_pin_41_[0] , chany_bottom_in[25] } ) , .sram ( mux_2level_tapbuf_size2_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_149 , SYNOPSYS_UNCONNECTED_150 } ) , - .out ( chanx_right_out[19] ) , .p0 ( optlc_net_221 ) ) ; + .out ( chanx_right_out[19] ) , .p0 ( optlc_net_218 ) ) ; sb_0__1__mux_2level_tapbuf_size2_1 mux_right_track_40 ( .in ( { right_bottom_grid_pin_42_[0] , chany_bottom_in[21] } ) , .sram ( mux_2level_tapbuf_size2_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_151 , SYNOPSYS_UNCONNECTED_152 } ) , - .out ( chanx_right_out[20] ) , .p0 ( optlc_net_221 ) ) ; + .out ( chanx_right_out[20] ) , .p0 ( optlc_net_218 ) ) ; sb_0__1__mux_2level_tapbuf_size2_2 mux_right_track_44 ( .in ( { right_bottom_grid_pin_36_[0] , chany_bottom_in[13] } ) , .sram ( mux_2level_tapbuf_size2_2_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_153 , SYNOPSYS_UNCONNECTED_154 } ) , - .out ( chanx_right_out[22] ) , .p0 ( optlc_net_221 ) ) ; + .out ( chanx_right_out[22] ) , .p0 ( optlc_net_216 ) ) ; sb_0__1__mux_2level_tapbuf_size2_3 mux_right_track_46 ( .in ( { right_bottom_grid_pin_37_[0] , chany_bottom_in[9] } ) , .sram ( mux_2level_tapbuf_size2_3_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_155 , SYNOPSYS_UNCONNECTED_156 } ) , - .out ( chanx_right_out[23] ) , .p0 ( optlc_net_221 ) ) ; + .out ( chanx_right_out[23] ) , .p0 ( optlc_net_216 ) ) ; sb_0__1__mux_2level_tapbuf_size2_4 mux_right_track_48 ( .in ( { right_bottom_grid_pin_38_[0] , chany_bottom_in[5] } ) , .sram ( mux_2level_tapbuf_size2_4_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_157 , SYNOPSYS_UNCONNECTED_158 } ) , - .out ( chanx_right_out[24] ) , .p0 ( optlc_net_221 ) ) ; + .out ( chanx_right_out[24] ) , .p0 ( optlc_net_216 ) ) ; sb_0__1__mux_2level_tapbuf_size2_5 mux_right_track_52 ( .in ( { right_bottom_grid_pin_40_[0] , chany_bottom_in[2] } ) , .sram ( mux_2level_tapbuf_size2_5_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_159 , SYNOPSYS_UNCONNECTED_160 } ) , - .out ( chanx_right_out[26] ) , .p0 ( optlc_net_221 ) ) ; + .out ( chanx_right_out[26] ) , .p0 ( optlc_net_218 ) ) ; sb_0__1__mux_2level_tapbuf_size2_6 mux_right_track_54 ( .in ( { right_bottom_grid_pin_41_[0] , chany_bottom_in[1] } ) , .sram ( mux_2level_tapbuf_size2_6_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_161 , SYNOPSYS_UNCONNECTED_162 } ) , - .out ( chanx_right_out[27] ) , .p0 ( optlc_net_221 ) ) ; + .out ( chanx_right_out[27] ) , .p0 ( optlc_net_218 ) ) ; sb_0__1__mux_2level_tapbuf_size2 mux_right_track_56 ( .in ( { right_bottom_grid_pin_42_[0] , chany_bottom_in[0] } ) , .sram ( mux_2level_tapbuf_size2_7_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_163 , SYNOPSYS_UNCONNECTED_164 } ) , - .out ( chanx_right_out[28] ) , .p0 ( optlc_net_221 ) ) ; + .out ( chanx_right_out[28] ) , .p0 ( optlc_net_218 ) ) ; sb_0__1__mux_2level_tapbuf_size2_mem_0 mem_right_track_38 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( mux_2level_tapbuf_size4_mem_8_ccff_tail ) , @@ -64552,8 +68906,8 @@ sb_0__1__mux_2level_tapbuf_size2_mem mem_right_track_56 ( .pReset ( pReset ) , .ccff_tail ( mux_2level_tapbuf_size2_mem_7_ccff_tail ) , .mem_out ( mux_2level_tapbuf_size2_7_sram ) ) ; sky130_fd_sc_hd__buf_8 pReset_FTB00 ( .A ( pReset_E_in ) , .X ( pReset[0] ) ) ; -sky130_fd_sc_hd__buf_6 pReset_S_FTB01 ( .A ( pReset_E_in ) , - .X ( pReset_S_out ) ) ; +sky130_fd_sc_hd__conb_1 optlc_217 ( .LO ( SYNOPSYS_UNCONNECTED_165 ) , + .HI ( optlc_net_215 ) ) ; sky130_fd_sc_hd__buf_1 prog_clk_0_FTB00 ( .A ( prog_clk_0_E_in ) , .X ( prog_clk[0] ) ) ; sky130_fd_sc_hd__buf_8 FTB_115__114 ( .A ( chany_top_in[3] ) , @@ -64634,20 +68988,20 @@ sky130_fd_sc_hd__buf_8 FTB_152__151 ( .A ( chany_bottom_in[27] ) , .X ( chany_top_out[28] ) ) ; sky130_fd_sc_hd__buf_8 FTB_153__152 ( .A ( chany_bottom_in[28] ) , .X ( chany_top_out[29] ) ) ; -sky130_fd_sc_hd__conb_1 optlc_222 ( .LO ( SYNOPSYS_UNCONNECTED_165 ) , +sky130_fd_sc_hd__inv_8 BINV_R_211 ( .A ( BUF_net_212 ) , .Y ( pReset_S_out ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_212 ( .A ( pReset_E_in ) , .Y ( BUF_net_212 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_219 ( .LO ( SYNOPSYS_UNCONNECTED_166 ) , + .HI ( optlc_net_216 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_221 ( .LO ( SYNOPSYS_UNCONNECTED_167 ) , + .HI ( optlc_net_217 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_224 ( .LO ( SYNOPSYS_UNCONNECTED_168 ) , + .HI ( optlc_net_218 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_226 ( .LO ( SYNOPSYS_UNCONNECTED_169 ) , + .HI ( optlc_net_219 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_228 ( .LO ( SYNOPSYS_UNCONNECTED_170 ) , .HI ( optlc_net_220 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_224 ( .LO ( SYNOPSYS_UNCONNECTED_166 ) , +sky130_fd_sc_hd__conb_1 optlc_230 ( .LO ( SYNOPSYS_UNCONNECTED_171 ) , .HI ( optlc_net_221 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_226 ( .LO ( SYNOPSYS_UNCONNECTED_167 ) , - .HI ( optlc_net_222 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_228 ( .LO ( SYNOPSYS_UNCONNECTED_168 ) , - .HI ( optlc_net_223 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_230 ( .LO ( SYNOPSYS_UNCONNECTED_169 ) , - .HI ( optlc_net_224 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_233 ( .LO ( SYNOPSYS_UNCONNECTED_170 ) , - .HI ( optlc_net_225 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_235 ( .LO ( SYNOPSYS_UNCONNECTED_171 ) , - .HI ( optlc_net_226 ) ) ; endmodule @@ -64747,6 +69101,8 @@ wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ; wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ; wire [0:0] mux_2level_tapbuf_basis_input2_mem1_2_out ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( mux_2level_tapbuf_basis_input2_mem1_2_out[0] ) , .X ( out[0] ) ) ; sb_0__0__mux_2level_tapbuf_basis_input2_mem1_58 mux_l1_in_0_ ( .in ( in[0:1] ) , .mem ( sram[0] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) , @@ -64762,8 +69118,6 @@ sb_0__0__mux_2level_tapbuf_basis_input2_mem1 mux_l2_in_0_ ( .mem ( sram[1] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_4 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_2_out ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_99 ( - .A ( mux_2level_tapbuf_basis_input2_mem1_2_out[0] ) , .X ( out[0] ) ) ; endmodule @@ -64815,8 +69169,6 @@ wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ; wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ; wire [0:0] mux_2level_tapbuf_basis_input2_mem1_2_out ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( mux_2level_tapbuf_basis_input2_mem1_2_out[0] ) , .X ( out[0] ) ) ; sb_0__0__mux_2level_tapbuf_basis_input2_mem1_55 mux_l1_in_0_ ( .in ( in[0:1] ) , .mem ( sram[0] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) , @@ -64832,6 +69184,8 @@ sb_0__0__mux_2level_tapbuf_basis_input2_mem1_57 mux_l2_in_0_ ( .mem ( sram[1] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_4 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_2_out ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_100 ( + .A ( mux_2level_tapbuf_basis_input2_mem1_2_out[0] ) , .X ( out[0] ) ) ; endmodule @@ -64883,8 +69237,6 @@ wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ; wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ; wire [0:0] mux_2level_tapbuf_basis_input2_mem1_2_out ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( mux_2level_tapbuf_basis_input2_mem1_2_out[0] ) , .X ( out[0] ) ) ; sb_0__0__mux_2level_tapbuf_basis_input2_mem1_52 mux_l1_in_0_ ( .in ( in[0:1] ) , .mem ( sram[0] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) , @@ -64900,6 +69252,8 @@ sb_0__0__mux_2level_tapbuf_basis_input2_mem1_54 mux_l2_in_0_ ( .mem ( sram[1] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_4 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_2_out ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_99 ( + .A ( mux_2level_tapbuf_basis_input2_mem1_2_out[0] ) , .X ( out[0] ) ) ; endmodule @@ -65031,10 +69385,14 @@ input [0:2] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -65045,10 +69403,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -65127,10 +69489,14 @@ input [0:2] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -65141,10 +69507,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -65210,8 +69580,9 @@ sb_0__0__mux_2level_tapbuf_basis_input3_mem3_9 mux_l2_in_0_ ( .mem ( local_encoder2to3_1_data ) , .mem_inv ( local_encoder2to3_1_data_inv ) , .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_98 ( - .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_97 ( .A ( BUF_net_98 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_98 ( + .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_98 ) ) ; endmodule @@ -65223,10 +69594,14 @@ input [0:2] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -65237,10 +69612,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -65306,9 +69685,8 @@ sb_0__0__mux_2level_tapbuf_basis_input3_mem3_7 mux_l2_in_0_ ( .mem ( local_encoder2to3_1_data ) , .mem_inv ( local_encoder2to3_1_data_inv ) , .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_96 ( .A ( BUF_net_97 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_97 ( - .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_97 ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_96 ( + .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .X ( out[0] ) ) ; endmodule @@ -65320,10 +69698,14 @@ input [0:2] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -65334,10 +69716,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -65387,8 +69773,6 @@ wire [0:2] local_encoder2to3_1_data_inv ; wire [0:0] mux_2level_tapbuf_basis_input3_mem3_0_out ; wire [0:0] mux_2level_tapbuf_basis_input3_mem3_1_out ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .X ( out[0] ) ) ; sb_0__0__local_encoder2to3_4 local_encoder2to3_0_ ( .addr ( sram[0:1] ) , .data ( local_encoder2to3_0_data ) , .data_inv ( local_encoder2to3_0_data_inv ) ) ; @@ -65405,6 +69789,9 @@ sb_0__0__mux_2level_tapbuf_basis_input3_mem3_5 mux_l2_in_0_ ( .mem ( local_encoder2to3_1_data ) , .mem_inv ( local_encoder2to3_1_data_inv ) , .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .p0 ( p0 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_94 ( .A ( BUF_net_95 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_95 ( + .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_95 ) ) ; endmodule @@ -65416,10 +69803,14 @@ input [0:2] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -65430,10 +69821,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -65483,6 +69878,8 @@ wire [0:2] local_encoder2to3_1_data_inv ; wire [0:0] mux_2level_tapbuf_basis_input3_mem3_0_out ; wire [0:0] mux_2level_tapbuf_basis_input3_mem3_1_out ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .X ( out[0] ) ) ; sb_0__0__local_encoder2to3_2 local_encoder2to3_0_ ( .addr ( sram[0:1] ) , .data ( local_encoder2to3_0_data ) , .data_inv ( local_encoder2to3_0_data_inv ) ) ; @@ -65499,9 +69896,6 @@ sb_0__0__mux_2level_tapbuf_basis_input3_mem3_3 mux_l2_in_0_ ( .mem ( local_encoder2to3_1_data ) , .mem_inv ( local_encoder2to3_1_data_inv ) , .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_100 ( .A ( BUF_net_101 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_101 ( - .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_101 ) ) ; endmodule @@ -65513,10 +69907,14 @@ input [0:2] mem_inv ; output [0:0] out ; input p0 ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -65527,10 +69925,14 @@ input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; +wire [0:0] out_inv ; + scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( in[2] ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , - .Z ( out[0] ) ) ; + .Z ( out_inv[0] ) ) ; +sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0 ( .A ( out_inv[0] ) , + .Y ( out[0] ) ) ; endmodule @@ -65596,9 +69998,8 @@ sb_0__0__mux_2level_tapbuf_basis_input3_mem3_1 mux_l2_in_0_ ( .mem ( local_encoder2to3_1_data ) , .mem_inv ( local_encoder2to3_1_data_inv ) , .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_94 ( .A ( BUF_net_95 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_95 ( - .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_95 ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_93 ( + .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .X ( out[0] ) ) ; endmodule @@ -65610,19 +70011,18 @@ input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -wire copt_net_120 ; - sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( copt_net_120 ) ) ; -sky130_fd_sc_hd__buf_6 FTB_26__25 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1300 ( .A ( copt_net_120 ) , - .X ( copt_net_118 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1301 ( .A ( copt_net_118 ) , - .X ( copt_net_119 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1302 ( .A ( copt_net_119 ) , - .X ( mem_out[1] ) ) ; + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_6 FTB_26__25 ( .A ( ropt_net_183 ) , + .X ( ccff_tail[0] ) ) ; +sky130_fd_sc_hd__buf_1 ropt_h_inst_1364 ( .A ( copt_net_117 ) , + .X ( ropt_net_183 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1297 ( .A ( mem_out[1] ) , + .X ( copt_net_116 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1298 ( .A ( copt_net_116 ) , + .X ( copt_net_117 ) ) ; endmodule @@ -66018,29 +70418,31 @@ input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ropt_net_157 ) , +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ropt_net_182 ) , .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__buf_1 FTB_1__0 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1291 ( .A ( copt_net_112 ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1289 ( .A ( ccff_head[0] ) , + .X ( copt_net_108 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1290 ( .A ( copt_net_108 ) , .X ( copt_net_109 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1292 ( .A ( copt_net_109 ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1291 ( .A ( copt_net_109 ) , .X ( copt_net_110 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1293 ( .A ( ccff_head[0] ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1292 ( .A ( copt_net_112 ) , .X ( copt_net_111 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1294 ( .A ( copt_net_111 ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1293 ( .A ( copt_net_110 ) , .X ( copt_net_112 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1295 ( .A ( copt_net_110 ) , +sky130_fd_sc_hd__buf_1 copt_h_inst_1294 ( .A ( copt_net_111 ) , .X ( copt_net_113 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1296 ( .A ( copt_net_113 ) , - .X ( copt_net_114 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1336 ( .A ( copt_net_114 ) , - .X ( ropt_net_155 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1337 ( .A ( ropt_net_155 ) , - .X ( ropt_net_156 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1338 ( .A ( ropt_net_156 ) , - .X ( ropt_net_157 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1360 ( .A ( ropt_net_180 ) , + .X ( ropt_net_179 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1361 ( .A ( copt_net_113 ) , + .X ( ropt_net_180 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1362 ( .A ( ropt_net_179 ) , + .X ( ropt_net_181 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1363 ( .A ( ropt_net_181 ) , + .X ( ropt_net_182 ) ) ; endmodule @@ -66052,7 +70454,7 @@ input [0:0] mem_inv ; output [0:0] out ; input p0 ; -sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , +sky130_fd_sc_hd__mux2_2 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ; endmodule @@ -66102,7 +70504,7 @@ input [0:0] mem_inv ; output [0:0] out ; input p0 ; -sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , +sky130_fd_sc_hd__mux2_2 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ; endmodule @@ -66189,9 +70591,9 @@ sb_0__0__mux_2level_tapbuf_basis_input2_mem1_47 mux_l2_in_0_ ( .mem ( sram[1] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_102 ( .A ( BUF_net_103 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_103 ( - .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_103 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_91 ( .A ( BUF_net_92 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_92 ( + .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_92 ) ) ; endmodule @@ -66230,8 +70632,6 @@ input p0 ; wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ; wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) ) ; sb_0__0__mux_2level_tapbuf_basis_input2_mem1_44 mux_l1_in_0_ ( .in ( in ) , .mem ( sram[0] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) , @@ -66242,6 +70642,9 @@ sb_0__0__mux_2level_tapbuf_basis_input2_mem1_45 mux_l2_in_0_ ( .mem ( sram[1] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_89 ( .A ( BUF_net_90 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_90 ( + .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_90 ) ) ; endmodule @@ -66280,6 +70683,8 @@ input p0 ; wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ; wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) ) ; sb_0__0__mux_2level_tapbuf_basis_input2_mem1_42 mux_l1_in_0_ ( .in ( in ) , .mem ( sram[0] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) , @@ -66290,9 +70695,6 @@ sb_0__0__mux_2level_tapbuf_basis_input2_mem1_43 mux_l2_in_0_ ( .mem ( sram[1] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_92 ( .A ( BUF_net_93 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_93 ( - .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_93 ) ) ; endmodule @@ -66354,7 +70756,7 @@ input [0:0] mem_inv ; output [0:0] out ; input p0 ; -sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , +sky130_fd_sc_hd__mux2_2 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ; endmodule @@ -66404,7 +70806,7 @@ input [0:0] mem_inv ; output [0:0] out ; input p0 ; -sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , +sky130_fd_sc_hd__mux2_2 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ; endmodule @@ -66491,9 +70893,9 @@ sb_0__0__mux_2level_tapbuf_basis_input2_mem1_35 mux_l2_in_0_ ( .mem ( sram[1] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_90 ( .A ( BUF_net_91 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_91 ( - .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_91 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_87 ( .A ( BUF_net_88 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_88 ( + .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_88 ) ) ; endmodule @@ -66505,7 +70907,7 @@ input [0:0] mem_inv ; output [0:0] out ; input p0 ; -sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , +sky130_fd_sc_hd__mux2_2 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ; endmodule @@ -66592,9 +70994,9 @@ sb_0__0__mux_2level_tapbuf_basis_input2_mem1_31 mux_l2_in_0_ ( .mem ( sram[1] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_88 ( .A ( BUF_net_89 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_89 ( - .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_89 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_101 ( .A ( BUF_net_102 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_102 ( + .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_102 ) ) ; endmodule @@ -66606,7 +71008,7 @@ input [0:0] mem_inv ; output [0:0] out ; input p0 ; -sky130_fd_sc_hd__mux2_2 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , +sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ; endmodule @@ -66633,8 +71035,6 @@ input p0 ; wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ; wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) ) ; sb_0__0__mux_2level_tapbuf_basis_input2_mem1_28 mux_l1_in_0_ ( .in ( in ) , .mem ( sram[0] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) , @@ -66645,6 +71045,9 @@ sb_0__0__mux_2level_tapbuf_basis_input2_mem1_29 mux_l2_in_0_ ( .mem ( sram[1] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_85 ( .A ( BUF_net_86 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_86 ( + .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_86 ) ) ; endmodule @@ -66693,9 +71096,9 @@ sb_0__0__mux_2level_tapbuf_basis_input2_mem1_27 mux_l2_in_0_ ( .mem ( sram[1] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_86 ( .A ( BUF_net_87 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_87 ( - .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_87 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_83 ( .A ( BUF_net_84 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_84 ( + .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_84 ) ) ; endmodule @@ -66744,9 +71147,9 @@ sb_0__0__mux_2level_tapbuf_basis_input2_mem1_25 mux_l2_in_0_ ( .mem ( sram[1] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_84 ( .A ( BUF_net_85 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_85 ( - .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_85 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_81 ( .A ( BUF_net_82 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_82 ( + .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_82 ) ) ; endmodule @@ -66858,7 +71261,7 @@ input [0:0] mem_inv ; output [0:0] out ; input p0 ; -sky130_fd_sc_hd__mux2_2 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , +sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ; endmodule @@ -66895,8 +71298,9 @@ sb_0__0__mux_2level_tapbuf_basis_input2_mem1_19 mux_l2_in_0_ ( .mem ( sram[1] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_83 ( - .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_79 ( .A ( BUF_net_80 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_80 ( + .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_80 ) ) ; endmodule @@ -66908,7 +71312,7 @@ input [0:0] mem_inv ; output [0:0] out ; input p0 ; -sky130_fd_sc_hd__mux2_2 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , +sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ; endmodule @@ -66935,6 +71339,8 @@ input p0 ; wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ; wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) ) ; sb_0__0__mux_2level_tapbuf_basis_input2_mem1_16 mux_l1_in_0_ ( .in ( in ) , .mem ( sram[0] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) , @@ -66945,8 +71351,6 @@ sb_0__0__mux_2level_tapbuf_basis_input2_mem1_17 mux_l2_in_0_ ( .mem ( sram[1] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_82 ( - .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) ) ; endmodule @@ -66985,6 +71389,8 @@ input p0 ; wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ; wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) ) ; sb_0__0__mux_2level_tapbuf_basis_input2_mem1_14 mux_l1_in_0_ ( .in ( in ) , .mem ( sram[0] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) , @@ -66995,9 +71401,6 @@ sb_0__0__mux_2level_tapbuf_basis_input2_mem1_15 mux_l2_in_0_ ( .mem ( sram[1] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_80 ( .A ( BUF_net_81 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_81 ( - .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_81 ) ) ; endmodule @@ -67036,8 +71439,6 @@ input p0 ; wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ; wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) ) ; sb_0__0__mux_2level_tapbuf_basis_input2_mem1_12 mux_l1_in_0_ ( .in ( in ) , .mem ( sram[0] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) , @@ -67048,6 +71449,9 @@ sb_0__0__mux_2level_tapbuf_basis_input2_mem1_13 mux_l2_in_0_ ( .mem ( sram[1] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_77 ( .A ( BUF_net_78 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_78 ( + .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_78 ) ) ; endmodule @@ -67059,7 +71463,7 @@ input [0:0] mem_inv ; output [0:0] out ; input p0 ; -sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , +sky130_fd_sc_hd__mux2_2 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ; endmodule @@ -67086,8 +71490,6 @@ input p0 ; wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ; wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) ) ; sb_0__0__mux_2level_tapbuf_basis_input2_mem1_10 mux_l1_in_0_ ( .in ( in ) , .mem ( sram[0] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) , @@ -67098,6 +71500,8 @@ sb_0__0__mux_2level_tapbuf_basis_input2_mem1_11 mux_l2_in_0_ ( .mem ( sram[1] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_76 ( + .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) ) ; endmodule @@ -67136,6 +71540,8 @@ input p0 ; wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ; wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) ) ; sb_0__0__mux_2level_tapbuf_basis_input2_mem1_8 mux_l1_in_0_ ( .in ( in ) , .mem ( sram[0] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) , @@ -67146,9 +71552,6 @@ sb_0__0__mux_2level_tapbuf_basis_input2_mem1_9 mux_l2_in_0_ ( .mem ( sram[1] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_78 ( .A ( BUF_net_79 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_79 ( - .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_79 ) ) ; endmodule @@ -67247,9 +71650,8 @@ sb_0__0__mux_2level_tapbuf_basis_input2_mem1_5 mux_l2_in_0_ ( .mem ( sram[1] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_76 ( .A ( BUF_net_77 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_77 ( - .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_77 ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_75 ( + .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) ) ; endmodule @@ -67298,9 +71700,8 @@ sb_0__0__mux_2level_tapbuf_basis_input2_mem1_3 mux_l2_in_0_ ( .mem ( sram[1] ) , .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) , .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_74 ( .A ( BUF_net_75 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_75 ( - .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_75 ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_74 ( + .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) ) ; endmodule @@ -67382,6 +71783,7 @@ output [0:0] ccff_tail ; input pReset_E_in ; input prog_clk_0_E_in ; +wire ropt_net_136 ; wire [0:0] prog_clk ; wire prog_clk_0 ; wire [0:1] mux_2level_tapbuf_size2_0_sram ; @@ -67460,22 +71862,22 @@ sb_0__0__mux_2level_tapbuf_size2_0 mux_top_track_0 ( .in ( { top_left_grid_pin_1_[0] , chanx_right_in[1] } ) , .sram ( mux_2level_tapbuf_size2_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 } ) , - .out ( chany_top_out[0] ) , .p0 ( optlc_net_106 ) ) ; + .out ( chany_top_out[0] ) , .p0 ( optlc_net_103 ) ) ; sb_0__0__mux_2level_tapbuf_size2_1 mux_top_track_6 ( .in ( { top_left_grid_pin_1_[0] , chanx_right_in[4] } ) , .sram ( mux_2level_tapbuf_size2_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) , - .out ( chany_top_out[3] ) , .p0 ( optlc_net_106 ) ) ; + .out ( chany_top_out[3] ) , .p0 ( optlc_net_103 ) ) ; sb_0__0__mux_2level_tapbuf_size2_2 mux_top_track_12 ( .in ( { top_left_grid_pin_1_[0] , chanx_right_in[7] } ) , .sram ( mux_2level_tapbuf_size2_2_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 } ) , - .out ( chany_top_out[6] ) , .p0 ( optlc_net_106 ) ) ; + .out ( chany_top_out[6] ) , .p0 ( optlc_net_103 ) ) ; sb_0__0__mux_2level_tapbuf_size2_3 mux_top_track_28 ( .in ( { top_left_grid_pin_1_[0] , chanx_right_in[15] } ) , .sram ( mux_2level_tapbuf_size2_3_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 } ) , - .out ( chany_top_out[14] ) , .p0 ( optlc_net_105 ) ) ; + .out ( chany_top_out[14] ) , .p0 ( optlc_net_103 ) ) ; sb_0__0__mux_2level_tapbuf_size2_4 mux_top_track_44 ( .in ( { top_left_grid_pin_1_[0] , chanx_right_in[23] } ) , .sram ( mux_2level_tapbuf_size2_4_sram ) , @@ -67485,17 +71887,17 @@ sb_0__0__mux_2level_tapbuf_size2_5 mux_right_track_14 ( .in ( { chany_top_in[6] , right_bottom_grid_pin_3_[0] } ) , .sram ( mux_2level_tapbuf_size2_5_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_11 , SYNOPSYS_UNCONNECTED_12 } ) , - .out ( chanx_right_out[7] ) , .p0 ( optlc_net_108 ) ) ; + .out ( chanx_right_out[7] ) , .p0 ( optlc_net_103 ) ) ; sb_0__0__mux_2level_tapbuf_size2_6 mux_right_track_16 ( .in ( { chany_top_in[7] , right_bottom_grid_pin_5_[0] } ) , .sram ( mux_2level_tapbuf_size2_6_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 } ) , - .out ( chanx_right_out[8] ) , .p0 ( optlc_net_104 ) ) ; + .out ( chanx_right_out[8] ) , .p0 ( optlc_net_103 ) ) ; sb_0__0__mux_2level_tapbuf_size2_7 mux_right_track_18 ( .in ( { chany_top_in[8] , right_bottom_grid_pin_7_[0] } ) , .sram ( mux_2level_tapbuf_size2_7_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_15 , SYNOPSYS_UNCONNECTED_16 } ) , - .out ( chanx_right_out[9] ) , .p0 ( optlc_net_104 ) ) ; + .out ( chanx_right_out[9] ) , .p0 ( optlc_net_103 ) ) ; sb_0__0__mux_2level_tapbuf_size2_8 mux_right_track_20 ( .in ( { chany_top_in[9] , right_bottom_grid_pin_9_[0] } ) , .sram ( mux_2level_tapbuf_size2_8_sram ) , @@ -67520,22 +71922,22 @@ sb_0__0__mux_2level_tapbuf_size2_12 mux_right_track_30 ( .in ( { chany_top_in[14] , right_bottom_grid_pin_3_[0] } ) , .sram ( mux_2level_tapbuf_size2_12_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_25 , SYNOPSYS_UNCONNECTED_26 } ) , - .out ( chanx_right_out[15] ) , .p0 ( optlc_net_104 ) ) ; + .out ( chanx_right_out[15] ) , .p0 ( optlc_net_103 ) ) ; sb_0__0__mux_2level_tapbuf_size2_13 mux_right_track_32 ( .in ( { chany_top_in[15] , right_bottom_grid_pin_5_[0] } ) , .sram ( mux_2level_tapbuf_size2_13_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_27 , SYNOPSYS_UNCONNECTED_28 } ) , - .out ( chanx_right_out[16] ) , .p0 ( optlc_net_104 ) ) ; + .out ( chanx_right_out[16] ) , .p0 ( optlc_net_103 ) ) ; sb_0__0__mux_2level_tapbuf_size2_14 mux_right_track_34 ( .in ( { chany_top_in[16] , right_bottom_grid_pin_7_[0] } ) , .sram ( mux_2level_tapbuf_size2_14_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_29 , SYNOPSYS_UNCONNECTED_30 } ) , - .out ( chanx_right_out[17] ) , .p0 ( optlc_net_104 ) ) ; + .out ( chanx_right_out[17] ) , .p0 ( optlc_net_103 ) ) ; sb_0__0__mux_2level_tapbuf_size2_15 mux_right_track_36 ( .in ( { chany_top_in[17] , right_bottom_grid_pin_9_[0] } ) , .sram ( mux_2level_tapbuf_size2_15_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_31 , SYNOPSYS_UNCONNECTED_32 } ) , - .out ( chanx_right_out[18] ) , .p0 ( optlc_net_106 ) ) ; + .out ( chanx_right_out[18] ) , .p0 ( optlc_net_103 ) ) ; sb_0__0__mux_2level_tapbuf_size2_16 mux_right_track_38 ( .in ( { chany_top_in[18] , right_bottom_grid_pin_11_[0] } ) , .sram ( mux_2level_tapbuf_size2_16_sram ) , @@ -67545,7 +71947,7 @@ sb_0__0__mux_2level_tapbuf_size2_17 mux_right_track_40 ( .in ( { chany_top_in[19] , right_bottom_grid_pin_13_[0] } ) , .sram ( mux_2level_tapbuf_size2_17_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_35 , SYNOPSYS_UNCONNECTED_36 } ) , - .out ( chanx_right_out[20] ) , .p0 ( optlc_net_105 ) ) ; + .out ( chanx_right_out[20] ) , .p0 ( optlc_net_106 ) ) ; sb_0__0__mux_2level_tapbuf_size2_18 mux_right_track_42 ( .in ( { chany_top_in[20] , right_bottom_grid_pin_15_[0] } ) , .sram ( mux_2level_tapbuf_size2_18_sram ) , @@ -67560,12 +71962,12 @@ sb_0__0__mux_2level_tapbuf_size2_20 mux_right_track_48 ( .in ( { chany_top_in[23] , right_bottom_grid_pin_5_[0] } ) , .sram ( mux_2level_tapbuf_size2_20_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_41 , SYNOPSYS_UNCONNECTED_42 } ) , - .out ( chanx_right_out[24] ) , .p0 ( optlc_net_104 ) ) ; + .out ( chanx_right_out[24] ) , .p0 ( optlc_net_105 ) ) ; sb_0__0__mux_2level_tapbuf_size2_21 mux_right_track_50 ( .in ( { chany_top_in[24] , right_bottom_grid_pin_7_[0] } ) , .sram ( mux_2level_tapbuf_size2_21_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_43 , SYNOPSYS_UNCONNECTED_44 } ) , - .out ( chanx_right_out[25] ) , .p0 ( optlc_net_104 ) ) ; + .out ( chanx_right_out[25] ) , .p0 ( optlc_net_103 ) ) ; sb_0__0__mux_2level_tapbuf_size2_22 mux_right_track_52 ( .in ( { chany_top_in[25] , right_bottom_grid_pin_9_[0] } ) , .sram ( mux_2level_tapbuf_size2_22_sram ) , @@ -67575,7 +71977,7 @@ sb_0__0__mux_2level_tapbuf_size2_23 mux_right_track_54 ( .in ( { chany_top_in[26] , right_bottom_grid_pin_11_[0] } ) , .sram ( mux_2level_tapbuf_size2_23_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_47 , SYNOPSYS_UNCONNECTED_48 } ) , - .out ( chanx_right_out[27] ) , .p0 ( optlc_net_105 ) ) ; + .out ( chanx_right_out[27] ) , .p0 ( optlc_net_106 ) ) ; sb_0__0__mux_2level_tapbuf_size2_24 mux_right_track_56 ( .in ( { chany_top_in[27] , right_bottom_grid_pin_13_[0] } ) , .sram ( mux_2level_tapbuf_size2_24_sram ) , @@ -67727,7 +72129,7 @@ sb_0__0__mux_2level_tapbuf_size4_1 mux_right_track_2 ( .sram ( mux_2level_tapbuf_size4_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_57 , SYNOPSYS_UNCONNECTED_58 , SYNOPSYS_UNCONNECTED_59 , SYNOPSYS_UNCONNECTED_60 } ) , - .out ( chanx_right_out[1] ) , .p0 ( optlc_net_108 ) ) ; + .out ( chanx_right_out[1] ) , .p0 ( optlc_net_104 ) ) ; sb_0__0__mux_2level_tapbuf_size4_2 mux_right_track_4 ( .in ( { chany_top_in[1] , right_bottom_grid_pin_5_[0] , right_bottom_grid_pin_11_[0] , right_bottom_grid_pin_17_[0] } ) , @@ -67748,14 +72150,14 @@ sb_0__0__mux_2level_tapbuf_size4_4 mux_right_track_8 ( .sram ( mux_2level_tapbuf_size4_4_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_69 , SYNOPSYS_UNCONNECTED_70 , SYNOPSYS_UNCONNECTED_71 , SYNOPSYS_UNCONNECTED_72 } ) , - .out ( chanx_right_out[4] ) , .p0 ( optlc_net_108 ) ) ; + .out ( chanx_right_out[4] ) , .p0 ( optlc_net_104 ) ) ; sb_0__0__mux_2level_tapbuf_size4 mux_right_track_10 ( .in ( { chany_top_in[4] , right_bottom_grid_pin_5_[0] , right_bottom_grid_pin_11_[0] , right_bottom_grid_pin_17_[0] } ) , .sram ( mux_2level_tapbuf_size4_5_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_73 , SYNOPSYS_UNCONNECTED_74 , SYNOPSYS_UNCONNECTED_75 , SYNOPSYS_UNCONNECTED_76 } ) , - .out ( chanx_right_out[5] ) , .p0 ( optlc_net_108 ) ) ; + .out ( chanx_right_out[5] ) , .p0 ( optlc_net_104 ) ) ; sb_0__0__mux_2level_tapbuf_size4_mem_0 mem_right_track_0 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( mux_2level_tapbuf_size2_mem_4_ccff_tail ) , @@ -67791,7 +72193,7 @@ sb_0__0__mux_2level_tapbuf_size3_0 mux_right_track_12 ( right_bottom_grid_pin_17_[0] } ) , .sram ( mux_2level_tapbuf_size3_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_77 , SYNOPSYS_UNCONNECTED_78 } ) , - .out ( chanx_right_out[6] ) , .p0 ( optlc_net_108 ) ) ; + .out ( chanx_right_out[6] ) , .p0 ( optlc_net_105 ) ) ; sb_0__0__mux_2level_tapbuf_size3_1 mux_right_track_28 ( .in ( { chany_top_in[13] , right_bottom_grid_pin_1_[0] , right_bottom_grid_pin_17_[0] } ) , @@ -67842,7 +72244,7 @@ sky130_fd_sc_hd__buf_8 FTB_56__55 ( .A ( chanx_right_in[11] ) , .X ( chany_top_out[10] ) ) ; sky130_fd_sc_hd__buf_8 FTB_57__56 ( .A ( chanx_right_in[12] ) , .X ( chany_top_out[11] ) ) ; -sky130_fd_sc_hd__buf_8 FTB_58__57 ( .A ( chanx_right_in[13] ) , +sky130_fd_sc_hd__buf_6 FTB_58__57 ( .A ( chanx_right_in[13] ) , .X ( chany_top_out[12] ) ) ; sky130_fd_sc_hd__buf_8 FTB_59__58 ( .A ( chanx_right_in[14] ) , .X ( chany_top_out[13] ) ) ; @@ -67866,22 +72268,24 @@ sky130_fd_sc_hd__buf_8 FTB_68__67 ( .A ( chanx_right_in[25] ) , .X ( chany_top_out[24] ) ) ; sky130_fd_sc_hd__buf_6 FTB_69__68 ( .A ( chanx_right_in[26] ) , .X ( chany_top_out[25] ) ) ; -sky130_fd_sc_hd__buf_8 FTB_70__69 ( .A ( chanx_right_in[27] ) , - .X ( chany_top_out[26] ) ) ; +sky130_fd_sc_hd__buf_6 FTB_70__69 ( .A ( chanx_right_in[27] ) , + .X ( ropt_net_136 ) ) ; sky130_fd_sc_hd__buf_8 FTB_71__70 ( .A ( chanx_right_in[28] ) , .X ( chany_top_out[27] ) ) ; sky130_fd_sc_hd__buf_8 FTB_72__71 ( .A ( chanx_right_in[29] ) , .X ( chany_top_out[28] ) ) ; -sky130_fd_sc_hd__conb_1 optlc_106 ( .LO ( SYNOPSYS_UNCONNECTED_83 ) , +sky130_fd_sc_hd__conb_1 optlc_105 ( .LO ( SYNOPSYS_UNCONNECTED_83 ) , + .HI ( optlc_net_103 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_107 ( .LO ( SYNOPSYS_UNCONNECTED_84 ) , .HI ( optlc_net_104 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_109 ( .LO ( SYNOPSYS_UNCONNECTED_84 ) , +sky130_fd_sc_hd__conb_1 optlc_109 ( .LO ( SYNOPSYS_UNCONNECTED_85 ) , .HI ( optlc_net_105 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_111 ( .LO ( SYNOPSYS_UNCONNECTED_85 ) , +sky130_fd_sc_hd__conb_1 optlc_111 ( .LO ( SYNOPSYS_UNCONNECTED_86 ) , .HI ( optlc_net_106 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_113 ( .LO ( SYNOPSYS_UNCONNECTED_86 ) , +sky130_fd_sc_hd__conb_1 optlc_113 ( .LO ( SYNOPSYS_UNCONNECTED_87 ) , .HI ( optlc_net_107 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_115 ( .LO ( SYNOPSYS_UNCONNECTED_87 ) , - .HI ( optlc_net_108 ) ) ; +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1317 ( .A ( ropt_net_136 ) , + .X ( chany_top_out[26] ) ) ; endmodule @@ -67897,18 +72301,18 @@ sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__buf_6 FTB_111__110 ( .A ( copt_net_248 ) , +sky130_fd_sc_hd__buf_6 FTB_111__110 ( .A ( copt_net_243 ) , .X ( ccff_tail[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1706 ( .A ( copt_net_250 ) , - .X ( copt_net_246 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1707 ( .A ( copt_net_246 ) , - .X ( copt_net_247 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1708 ( .A ( copt_net_247 ) , - .X ( copt_net_248 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1709 ( .A ( mem_out[1] ) , - .X ( copt_net_249 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1710 ( .A ( copt_net_249 ) , - .X ( copt_net_250 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1596 ( .A ( mem_out[1] ) , + .X ( copt_net_239 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1597 ( .A ( copt_net_242 ) , + .X ( copt_net_240 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1598 ( .A ( copt_net_240 ) , + .X ( copt_net_241 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1599 ( .A ( copt_net_239 ) , + .X ( copt_net_242 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1600 ( .A ( copt_net_241 ) , + .X ( copt_net_243 ) ) ; endmodule @@ -67929,14 +72333,14 @@ sky130_fd_sc_hd__buf_1 FTB_110__109 ( .A ( mem_out[1] ) , endmodule -module grid_clb_mux_1level_basis_input3_mem3 ( in , mem , mem_inv , out , p0 ) ; +module grid_clb_mux_1level_basis_input3_mem3 ( in , mem , mem_inv , out , p3 ) ; input [0:2] in ; input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; -input p0 ; +input p3 ; -scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , +scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p3 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out[0] ) ) ; @@ -67959,12 +72363,12 @@ sky130_fd_sc_hd__buf_1 FTB_109__108 ( .A ( addr[1] ) , .X ( data[2] ) ) ; endmodule -module grid_clb_mux_1level_size2 ( in , sram , sram_inv , out , p0 ) ; +module grid_clb_mux_1level_size2 ( in , sram , sram_inv , out , p3 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; output [0:0] out ; -input p0 ; +input p3 ; wire [0:2] local_encoder2to3_0_data ; wire [0:2] local_encoder2to3_0_data_inv ; @@ -67979,7 +72383,7 @@ grid_clb_mux_1level_basis_input3_mem3 mux_l1_in_0_ ( .in ( { in[0] , in[1] , SYNOPSYS_UNCONNECTED_1 } ) , .mem ( local_encoder2to3_0_data ) , .mem_inv ( local_encoder2to3_0_data_inv ) , - .out ( mux_1level_basis_input3_mem3_0_out ) , .p0 ( p0 ) ) ; + .out ( mux_1level_basis_input3_mem3_0_out ) , .p3 ( p3 ) ) ; endmodule @@ -68124,9 +72528,9 @@ grid_clb_mux_1level_tapbuf_basis_input3_mem3 mux_l1_in_0_ ( .mem ( local_encoder2to3_0_data ) , .mem_inv ( local_encoder2to3_0_data_inv ) , .out ( mux_1level_tapbuf_basis_input3_mem3_0_out ) , .p3 ( p3 ) ) ; -sky130_fd_sc_hd__inv_2 BINV_R_178 ( +sky130_fd_sc_hd__inv_8 BINV_R_177 ( .A ( mux_1level_tapbuf_basis_input3_mem3_0_out[0] ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_179 ( +sky130_fd_sc_hd__inv_2 BINV_R_178 ( .A ( mux_1level_tapbuf_basis_input3_mem3_0_out[0] ) , .Y ( p_abuf0 ) ) ; endmodule @@ -68183,16 +72587,15 @@ grid_clb_mux_1level_tapbuf_basis_input3_mem3_14 mux_l1_in_0_ ( .mem ( local_encoder2to3_0_data ) , .mem_inv ( local_encoder2to3_0_data_inv ) , .out ( mux_1level_tapbuf_basis_input3_mem3_0_out ) , .p3 ( p3 ) ) ; -sky130_fd_sc_hd__inv_2 BINV_R_175 ( +sky130_fd_sc_hd__inv_2 BINV_R_174 ( .A ( mux_1level_tapbuf_basis_input3_mem3_0_out[0] ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_176 ( +sky130_fd_sc_hd__inv_8 BINV_R_175 ( .A ( mux_1level_tapbuf_basis_input3_mem3_0_out[0] ) , .Y ( p_abuf0 ) ) ; endmodule module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff ( - Test_en , ff_D , ff_DI , ff_reset , ff_Q , ff_clk , p_abuf0 , p_abuf1 , - p_abuf2 ) ; + Test_en , ff_D , ff_DI , ff_reset , ff_Q , ff_clk , p_abuf0 , p_abuf1 ) ; input [0:0] Test_en ; input [0:0] ff_D ; input [0:0] ff_DI ; @@ -68201,15 +72604,13 @@ output [0:0] ff_Q ; input [0:0] ff_clk ; output p_abuf0 ; output p_abuf1 ; -output p_abuf2 ; sky130_fd_sc_hd__sdfrtp_1 sky130_fd_sc_hd__sdfrtp_1_0_ ( .D ( ff_D[0] ) , .SCD ( ff_DI[0] ) , .SCE ( Test_en[0] ) , .CLK ( ff_clk[0] ) , - .RESET_B ( ff_reset[0] ) , .Q ( p_abuf2 ) ) ; -sky130_fd_sc_hd__inv_2 BINV_R_129 ( .A ( BUF_net_132 ) , .Y ( ff_Q[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_130 ( .A ( BUF_net_132 ) , .Y ( p_abuf0 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_131 ( .A ( BUF_net_132 ) , .Y ( p_abuf1 ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_132 ( .A ( p_abuf2 ) , .Y ( BUF_net_132 ) ) ; + .RESET_B ( ff_reset[0] ) , .Q ( p_abuf1 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_129 ( .A ( BUF_net_131 ) , .Y ( ff_Q[0] ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_130 ( .A ( BUF_net_131 ) , .Y ( p_abuf0 ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_131 ( .A ( p_abuf1 ) , .Y ( BUF_net_131 ) ) ; endmodule @@ -68651,7 +73052,7 @@ module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric ( pReset , prog_clk , Test_en , fabric_in , fabric_reg_in , fabric_sc_in , fabric_cin , fabric_reset , fabric_clk , ccff_head , fabric_out , fabric_reg_out , fabric_sc_out , fabric_cout , ccff_tail , p_abuf0 , - p_abuf3 , p_abuf4 , p0 , p3 ) ; + p_abuf2 , p_abuf3 , p0 , p3 ) ; input [0:0] pReset ; input [0:0] prog_clk ; input [0:0] Test_en ; @@ -68668,8 +73069,8 @@ output [0:0] fabric_sc_out ; output [0:0] fabric_cout ; output [0:0] ccff_tail ; output p_abuf0 ; +output p_abuf2 ; output p_abuf3 ; -output p_abuf4 ; input p0 ; input p3 ; @@ -68706,8 +73107,7 @@ grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ .Test_en ( Test_en ) , .ff_D ( mux_1level_size2_1_out ) , .ff_DI ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ) , .ff_reset ( fabric_reset ) , .ff_Q ( fabric_sc_out ) , - .ff_clk ( fabric_clk ) , .p_abuf0 ( aps_rename_506_ ) , - .p_abuf1 ( p_abuf0 ) , .p_abuf2 ( p_abuf2 ) ) ; + .ff_clk ( fabric_clk ) , .p_abuf0 ( p_abuf0 ) , .p_abuf1 ( p_abuf1 ) ) ; grid_clb_mux_1level_tapbuf_size2_14 mux_fabric_out_0 ( .in ( { logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q[0] , @@ -68715,14 +73115,14 @@ grid_clb_mux_1level_tapbuf_size2_14 mux_fabric_out_0 ( } ) , .sram ( mux_1level_tapbuf_size2_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_2 , SYNOPSYS_UNCONNECTED_3 } ) , - .out ( fabric_out[0] ) , .p_abuf0 ( p_abuf3 ) , .p3 ( p3 ) ) ; + .out ( fabric_out[0] ) , .p_abuf0 ( p_abuf2 ) , .p3 ( p3 ) ) ; grid_clb_mux_1level_tapbuf_size2 mux_fabric_out_1 ( - .in ( { aps_rename_506_ , + .in ( { p_abuf0 , logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] } ) , .sram ( mux_1level_tapbuf_size2_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_4 , SYNOPSYS_UNCONNECTED_5 } ) , - .out ( fabric_out[1] ) , .p_abuf0 ( p_abuf4 ) , .p3 ( p3 ) ) ; + .out ( fabric_out[1] ) , .p_abuf0 ( p_abuf3 ) , .p3 ( p3 ) ) ; grid_clb_mux_1level_tapbuf_size2_mem_14 mem_fabric_out_0 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) , @@ -68733,7 +73133,7 @@ grid_clb_mux_1level_tapbuf_size2_mem mem_fabric_out_1 ( .pReset ( pReset ) , .ccff_head ( mux_1level_tapbuf_size2_mem_0_ccff_tail ) , .ccff_tail ( mux_1level_tapbuf_size2_mem_1_ccff_tail ) , .mem_out ( mux_1level_tapbuf_size2_1_sram ) ) ; -sky130_fd_sc_hd__buf_6 FTB_112__111 ( .A ( p_abuf2 ) , +sky130_fd_sc_hd__buf_6 FTB_112__111 ( .A ( p_abuf1 ) , .X ( fabric_reg_out[0] ) ) ; grid_clb_mux_1level_size2_30 mux_ff_0_D_0 ( .in ( { @@ -68749,7 +73149,7 @@ grid_clb_mux_1level_size2 mux_ff_1_D_0 ( } ) , .sram ( mux_1level_size2_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_8 , SYNOPSYS_UNCONNECTED_9 } ) , - .out ( mux_1level_size2_1_out ) , .p0 ( p0 ) ) ; + .out ( mux_1level_size2_1_out ) , .p3 ( p3 ) ) ; grid_clb_mux_1level_size2_mem_30 mem_ff_0_D_0 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( mux_1level_tapbuf_size2_mem_1_ccff_tail ) , @@ -68795,7 +73195,7 @@ grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric logical_tile_c .ccff_head ( ccff_head ) , .fabric_out ( fle_out ) , .fabric_reg_out ( fle_reg_out ) , .fabric_sc_out ( fle_sc_out ) , .fabric_cout ( fle_cout ) , .ccff_tail ( ccff_tail ) , - .p_abuf0 ( p_abuf0 ) , .p_abuf3 ( p_abuf1 ) , .p_abuf4 ( p_abuf2 ) , + .p_abuf0 ( p_abuf0 ) , .p_abuf2 ( p_abuf1 ) , .p_abuf3 ( p_abuf2 ) , .p0 ( p0 ) , .p3 ( p3 ) ) ; endmodule @@ -68833,14 +73233,14 @@ endmodule module grid_clb_mux_1level_basis_input3_mem3_27 ( in , mem , mem_inv , out , - p6 ) ; + p3 ) ; input [0:2] in ; input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; -input p6 ; +input p3 ; -scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p6 ) , +scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p3 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out[0] ) ) ; @@ -68863,12 +73263,12 @@ sky130_fd_sc_hd__buf_1 FTB_95__94 ( .A ( addr[1] ) , .X ( data[2] ) ) ; endmodule -module grid_clb_mux_1level_size2_27 ( in , sram , sram_inv , out , p6 ) ; +module grid_clb_mux_1level_size2_27 ( in , sram , sram_inv , out , p3 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; output [0:0] out ; -input p6 ; +input p3 ; wire [0:2] local_encoder2to3_0_data ; wire [0:2] local_encoder2to3_0_data_inv ; @@ -68883,19 +73283,19 @@ grid_clb_mux_1level_basis_input3_mem3_27 mux_l1_in_0_ ( .in ( { in[0] , in[1] , SYNOPSYS_UNCONNECTED_1 } ) , .mem ( local_encoder2to3_0_data ) , .mem_inv ( local_encoder2to3_0_data_inv ) , - .out ( mux_1level_basis_input3_mem3_0_out ) , .p6 ( p6 ) ) ; + .out ( mux_1level_basis_input3_mem3_0_out ) , .p3 ( p3 ) ) ; endmodule module grid_clb_mux_1level_basis_input3_mem3_26 ( in , mem , mem_inv , out , - p6 ) ; + p0 ) ; input [0:2] in ; input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; -input p6 ; +input p0 ; -scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p6 ) , +scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out[0] ) ) ; @@ -68918,12 +73318,12 @@ sky130_fd_sc_hd__buf_1 FTB_94__93 ( .A ( addr[1] ) , .X ( data[2] ) ) ; endmodule -module grid_clb_mux_1level_size2_26 ( in , sram , sram_inv , out , p6 ) ; +module grid_clb_mux_1level_size2_26 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; output [0:0] out ; -input p6 ; +input p0 ; wire [0:2] local_encoder2to3_0_data ; wire [0:2] local_encoder2to3_0_data_inv ; @@ -68938,7 +73338,7 @@ grid_clb_mux_1level_basis_input3_mem3_26 mux_l1_in_0_ ( .in ( { in[0] , in[1] , SYNOPSYS_UNCONNECTED_1 } ) , .mem ( local_encoder2to3_0_data ) , .mem_inv ( local_encoder2to3_0_data_inv ) , - .out ( mux_1level_basis_input3_mem3_0_out ) , .p6 ( p6 ) ) ; + .out ( mux_1level_basis_input3_mem3_0_out ) , .p0 ( p0 ) ) ; endmodule @@ -69026,9 +73426,9 @@ grid_clb_mux_1level_tapbuf_basis_input3_mem3_13 mux_l1_in_0_ ( .mem ( local_encoder2to3_0_data ) , .mem_inv ( local_encoder2to3_0_data_inv ) , .out ( mux_1level_tapbuf_basis_input3_mem3_0_out ) , .p3 ( p3 ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_172 ( +sky130_fd_sc_hd__inv_8 BINV_R_171 ( .A ( mux_1level_tapbuf_basis_input3_mem3_0_out[0] ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_173 ( +sky130_fd_sc_hd__inv_1 BINV_R_172 ( .A ( mux_1level_tapbuf_basis_input3_mem3_0_out[0] ) , .Y ( p_abuf0 ) ) ; endmodule @@ -69085,9 +73485,9 @@ grid_clb_mux_1level_tapbuf_basis_input3_mem3_12 mux_l1_in_0_ ( .mem ( local_encoder2to3_0_data ) , .mem_inv ( local_encoder2to3_0_data_inv ) , .out ( mux_1level_tapbuf_basis_input3_mem3_0_out ) , .p3 ( p3 ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_169 ( +sky130_fd_sc_hd__inv_1 BINV_R_168 ( .A ( mux_1level_tapbuf_basis_input3_mem3_0_out[0] ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_170 ( +sky130_fd_sc_hd__inv_8 BINV_R_169 ( .A ( mux_1level_tapbuf_basis_input3_mem3_0_out[0] ) , .Y ( p_abuf0 ) ) ; endmodule @@ -69210,14 +73610,14 @@ endmodule module grid_clb_mux_1level_basis_input3_mem3_24 ( in , mem , mem_inv , out , - p6 ) ; + p3 ) ; input [0:2] in ; input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; -input p6 ; +input p3 ; -scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p6 ) , +scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p3 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out[0] ) ) ; @@ -69240,12 +73640,12 @@ sky130_fd_sc_hd__buf_1 FTB_86__85 ( .A ( addr[1] ) , .X ( data[2] ) ) ; endmodule -module grid_clb_mux_1level_size2_24 ( in , sram , sram_inv , out , p6 ) ; +module grid_clb_mux_1level_size2_24 ( in , sram , sram_inv , out , p3 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; output [0:0] out ; -input p6 ; +input p3 ; wire [0:2] local_encoder2to3_0_data ; wire [0:2] local_encoder2to3_0_data_inv ; @@ -69260,7 +73660,7 @@ grid_clb_mux_1level_basis_input3_mem3_24 mux_l1_in_0_ ( .in ( { in[0] , in[1] , SYNOPSYS_UNCONNECTED_1 } ) , .mem ( local_encoder2to3_0_data ) , .mem_inv ( local_encoder2to3_0_data_inv ) , - .out ( mux_1level_basis_input3_mem3_0_out ) , .p6 ( p6 ) ) ; + .out ( mux_1level_basis_input3_mem3_0_out ) , .p3 ( p3 ) ) ; endmodule @@ -69477,7 +73877,7 @@ endmodule module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_6 ( pReset , prog_clk , frac_logic_in , frac_logic_cin , ccff_head , - frac_logic_out , frac_logic_cout , ccff_tail , p3 , p6 ) ; + frac_logic_out , frac_logic_cout , ccff_tail , p3 ) ; input [0:0] pReset ; input [0:0] prog_clk ; input [0:3] frac_logic_in ; @@ -69487,7 +73887,6 @@ output [0:1] frac_logic_out ; output [0:0] frac_logic_cout ; output [0:0] ccff_tail ; input p3 ; -input p6 ; wire [0:0] direct_interc_5_out ; wire [0:0] direct_interc_7_out ; @@ -69523,7 +73922,7 @@ grid_clb_mux_1level_size2_24 mux_frac_logic_out_0 ( } ) , .sram ( mux_1level_size2_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_2 , SYNOPSYS_UNCONNECTED_3 } ) , - .out ( frac_logic_out[0] ) , .p6 ( p6 ) ) ; + .out ( frac_logic_out[0] ) , .p3 ( p3 ) ) ; grid_clb_mux_1level_size2_25 mux_frac_lut4_0_in_2 ( .in ( { frac_logic_cin[0] , frac_logic_in[2] } ) , .sram ( mux_1level_size2_1_sram ) , @@ -69544,7 +73943,7 @@ module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_6 ( pReset , prog_clk , Test_en , fabric_in , fabric_reg_in , fabric_sc_in , fabric_cin , fabric_reset , fabric_clk , ccff_head , fabric_out , fabric_reg_out , fabric_sc_out , fabric_cout , ccff_tail , p_abuf0 , - p_abuf1 , p3 , p6 ) ; + p_abuf1 , p0 , p3 ) ; input [0:0] pReset ; input [0:0] prog_clk ; input [0:0] Test_en ; @@ -69562,8 +73961,8 @@ output [0:0] fabric_cout ; output [0:0] ccff_tail ; output p_abuf0 ; output p_abuf1 ; +input p0 ; input p3 ; -input p6 ; wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ; wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ; @@ -69588,7 +73987,7 @@ grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ .frac_logic_cout ( { SYNOPSYS_UNCONNECTED_1 } ) , .ccff_tail ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) , - .p3 ( p3 ) , .p6 ( p6 ) ) ; + .p3 ( p3 ) ) ; grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_12 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0 ( .Test_en ( Test_en ) , .ff_D ( mux_1level_size2_0_out ) , .ff_DI ( fabric_sc_in ) , .ff_reset ( fabric_reset ) , @@ -69632,7 +74031,7 @@ grid_clb_mux_1level_size2_26 mux_ff_0_D_0 ( fabric_reg_in[0] } ) , .sram ( mux_1level_size2_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_6 , SYNOPSYS_UNCONNECTED_7 } ) , - .out ( mux_1level_size2_0_out ) , .p6 ( p6 ) ) ; + .out ( mux_1level_size2_0_out ) , .p0 ( p0 ) ) ; grid_clb_mux_1level_size2_27 mux_ff_1_D_0 ( .in ( { logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] , @@ -69640,7 +74039,7 @@ grid_clb_mux_1level_size2_27 mux_ff_1_D_0 ( } ) , .sram ( mux_1level_size2_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_8 , SYNOPSYS_UNCONNECTED_9 } ) , - .out ( mux_1level_size2_1_out ) , .p6 ( p6 ) ) ; + .out ( mux_1level_size2_1_out ) , .p3 ( p3 ) ) ; grid_clb_mux_1level_size2_mem_26 mem_ff_0_D_0 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( mux_1level_tapbuf_size2_mem_1_ccff_tail ) , @@ -69655,7 +74054,7 @@ endmodule module grid_clb_logical_tile_clb_mode_default__fle_6 ( pReset , prog_clk , Test_en , fle_in , fle_reg_in , fle_sc_in , fle_cin , fle_reset , fle_clk , ccff_head , fle_out , fle_reg_out , fle_sc_out , fle_cout , - ccff_tail , p_abuf0 , p_abuf1 , p3 , p6 ) ; + ccff_tail , p_abuf0 , p_abuf1 , p0 , p3 ) ; input [0:0] pReset ; input [0:0] prog_clk ; input [0:0] Test_en ; @@ -69673,8 +74072,8 @@ output [0:0] fle_cout ; output [0:0] ccff_tail ; output p_abuf0 ; output p_abuf1 ; +input p0 ; input p3 ; -input p6 ; grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_6 logical_tile_clb_mode_default__fle_mode_physical__fabric_0 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , @@ -69686,7 +74085,7 @@ grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_6 logical_tile .fabric_reg_out ( fle_reg_out ) , .fabric_sc_out ( fle_sc_out ) , .fabric_cout ( { SYNOPSYS_UNCONNECTED_2 } ) , .ccff_tail ( ccff_tail ) , .p_abuf0 ( p_abuf0 ) , .p_abuf1 ( p_abuf1 ) , - .p3 ( p3 ) , .p6 ( p6 ) ) ; + .p0 ( p0 ) , .p3 ( p3 ) ) ; endmodule @@ -69778,14 +74177,14 @@ endmodule module grid_clb_mux_1level_basis_input3_mem3_22 ( in , mem , mem_inv , out , - p6 ) ; + p0 ) ; input [0:2] in ; input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; -input p6 ; +input p0 ; -scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p6 ) , +scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out[0] ) ) ; @@ -69808,12 +74207,12 @@ sky130_fd_sc_hd__buf_1 FTB_80__79 ( .A ( addr[1] ) , .X ( data[2] ) ) ; endmodule -module grid_clb_mux_1level_size2_22 ( in , sram , sram_inv , out , p6 ) ; +module grid_clb_mux_1level_size2_22 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; output [0:0] out ; -input p6 ; +input p0 ; wire [0:2] local_encoder2to3_0_data ; wire [0:2] local_encoder2to3_0_data_inv ; @@ -69828,7 +74227,7 @@ grid_clb_mux_1level_basis_input3_mem3_22 mux_l1_in_0_ ( .in ( { in[0] , in[1] , SYNOPSYS_UNCONNECTED_1 } ) , .mem ( local_encoder2to3_0_data ) , .mem_inv ( local_encoder2to3_0_data_inv ) , - .out ( mux_1level_basis_input3_mem3_0_out ) , .p6 ( p6 ) ) ; + .out ( mux_1level_basis_input3_mem3_0_out ) , .p0 ( p0 ) ) ; endmodule @@ -69865,14 +74264,14 @@ endmodule module grid_clb_mux_1level_tapbuf_basis_input3_mem3_11 ( in , mem , mem_inv , - out , p6 ) ; + out , p3 ) ; input [0:2] in ; input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; -input p6 ; +input p3 ; -scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p6 ) , +scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p3 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out[0] ) ) ; @@ -69896,13 +74295,13 @@ endmodule module grid_clb_mux_1level_tapbuf_size2_11 ( in , sram , sram_inv , out , - p_abuf0 , p6 ) ; + p_abuf0 , p3 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; output [0:0] out ; output p_abuf0 ; -input p6 ; +input p3 ; wire [0:2] local_encoder2to3_0_data ; wire [0:2] local_encoder2to3_0_data_inv ; @@ -69915,23 +74314,23 @@ grid_clb_mux_1level_tapbuf_basis_input3_mem3_11 mux_l1_in_0_ ( .in ( { in[0] , in[1] , SYNOPSYS_UNCONNECTED_1 } ) , .mem ( local_encoder2to3_0_data ) , .mem_inv ( local_encoder2to3_0_data_inv ) , - .out ( mux_1level_tapbuf_basis_input3_mem3_0_out ) , .p6 ( p6 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_166 ( + .out ( mux_1level_tapbuf_basis_input3_mem3_0_out ) , .p3 ( p3 ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_165 ( .A ( mux_1level_tapbuf_basis_input3_mem3_0_out[0] ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_167 ( +sky130_fd_sc_hd__inv_8 BINV_R_166 ( .A ( mux_1level_tapbuf_basis_input3_mem3_0_out[0] ) , .Y ( p_abuf0 ) ) ; endmodule module grid_clb_mux_1level_tapbuf_basis_input3_mem3_10 ( in , mem , mem_inv , - out , p6 ) ; + out , p3 ) ; input [0:2] in ; input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; -input p6 ; +input p3 ; -scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p6 ) , +scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p3 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out[0] ) ) ; @@ -69955,13 +74354,13 @@ endmodule module grid_clb_mux_1level_tapbuf_size2_10 ( in , sram , sram_inv , out , - p_abuf0 , p6 ) ; + p_abuf0 , p3 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; output [0:0] out ; output p_abuf0 ; -input p6 ; +input p3 ; wire [0:2] local_encoder2to3_0_data ; wire [0:2] local_encoder2to3_0_data_inv ; @@ -69974,10 +74373,10 @@ grid_clb_mux_1level_tapbuf_basis_input3_mem3_10 mux_l1_in_0_ ( .in ( { in[0] , in[1] , SYNOPSYS_UNCONNECTED_1 } ) , .mem ( local_encoder2to3_0_data ) , .mem_inv ( local_encoder2to3_0_data_inv ) , - .out ( mux_1level_tapbuf_basis_input3_mem3_0_out ) , .p6 ( p6 ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_163 ( + .out ( mux_1level_tapbuf_basis_input3_mem3_0_out ) , .p3 ( p3 ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_162 ( .A ( mux_1level_tapbuf_basis_input3_mem3_0_out[0] ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_164 ( +sky130_fd_sc_hd__inv_8 BINV_R_163 ( .A ( mux_1level_tapbuf_basis_input3_mem3_0_out[0] ) , .Y ( p_abuf0 ) ) ; endmodule @@ -70433,7 +74832,7 @@ module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_5 ( pReset , prog_clk , Test_en , fabric_in , fabric_reg_in , fabric_sc_in , fabric_cin , fabric_reset , fabric_clk , ccff_head , fabric_out , fabric_reg_out , fabric_sc_out , fabric_cout , ccff_tail , p_abuf0 , - p_abuf1 , p6 ) ; + p_abuf1 , p0 , p3 , p6 ) ; input [0:0] pReset ; input [0:0] prog_clk ; input [0:0] Test_en ; @@ -70451,6 +74850,8 @@ output [0:0] fabric_cout ; output [0:0] ccff_tail ; output p_abuf0 ; output p_abuf1 ; +input p0 ; +input p3 ; input p6 ; wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ; @@ -70494,14 +74895,14 @@ grid_clb_mux_1level_tapbuf_size2_10 mux_fabric_out_0 ( } ) , .sram ( mux_1level_tapbuf_size2_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_2 , SYNOPSYS_UNCONNECTED_3 } ) , - .out ( fabric_out[0] ) , .p_abuf0 ( p_abuf0 ) , .p6 ( p6 ) ) ; + .out ( fabric_out[0] ) , .p_abuf0 ( p_abuf0 ) , .p3 ( p3 ) ) ; grid_clb_mux_1level_tapbuf_size2_11 mux_fabric_out_1 ( .in ( { fabric_sc_out[0] , logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] } ) , .sram ( mux_1level_tapbuf_size2_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_4 , SYNOPSYS_UNCONNECTED_5 } ) , - .out ( fabric_out[1] ) , .p_abuf0 ( p_abuf1 ) , .p6 ( p6 ) ) ; + .out ( fabric_out[1] ) , .p_abuf0 ( p_abuf1 ) , .p3 ( p3 ) ) ; grid_clb_mux_1level_tapbuf_size2_mem_10 mem_fabric_out_0 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) , @@ -70520,7 +74921,7 @@ grid_clb_mux_1level_size2_22 mux_ff_0_D_0 ( fabric_reg_in[0] } ) , .sram ( mux_1level_size2_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_6 , SYNOPSYS_UNCONNECTED_7 } ) , - .out ( mux_1level_size2_0_out ) , .p6 ( p6 ) ) ; + .out ( mux_1level_size2_0_out ) , .p0 ( p0 ) ) ; grid_clb_mux_1level_size2_23 mux_ff_1_D_0 ( .in ( { logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] , @@ -70543,7 +74944,7 @@ endmodule module grid_clb_logical_tile_clb_mode_default__fle_5 ( pReset , prog_clk , Test_en , fle_in , fle_reg_in , fle_sc_in , fle_cin , fle_reset , fle_clk , ccff_head , fle_out , fle_reg_out , fle_sc_out , fle_cout , - ccff_tail , p_abuf0 , p_abuf1 , p6 ) ; + ccff_tail , p_abuf0 , p_abuf1 , p0 , p3 , p6 ) ; input [0:0] pReset ; input [0:0] prog_clk ; input [0:0] Test_en ; @@ -70561,6 +74962,8 @@ output [0:0] fle_cout ; output [0:0] ccff_tail ; output p_abuf0 ; output p_abuf1 ; +input p0 ; +input p3 ; input p6 ; grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_5 logical_tile_clb_mode_default__fle_mode_physical__fabric_0 ( @@ -70573,7 +74976,7 @@ grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_5 logical_tile .fabric_reg_out ( fle_reg_out ) , .fabric_sc_out ( fle_sc_out ) , .fabric_cout ( { SYNOPSYS_UNCONNECTED_2 } ) , .ccff_tail ( ccff_tail ) , .p_abuf0 ( p_abuf0 ) , .p_abuf1 ( p_abuf1 ) , - .p6 ( p6 ) ) ; + .p0 ( p0 ) , .p3 ( p3 ) , .p6 ( p6 ) ) ; endmodule @@ -70610,14 +75013,14 @@ endmodule module grid_clb_mux_1level_basis_input3_mem3_19 ( in , mem , mem_inv , out , - p0 ) ; + p6 ) ; input [0:2] in ; input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; -input p0 ; +input p6 ; -scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , +scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p6 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out[0] ) ) ; @@ -70640,12 +75043,12 @@ sky130_fd_sc_hd__buf_1 FTB_67__66 ( .A ( addr[1] ) , .X ( data[2] ) ) ; endmodule -module grid_clb_mux_1level_size2_19 ( in , sram , sram_inv , out , p0 ) ; +module grid_clb_mux_1level_size2_19 ( in , sram , sram_inv , out , p6 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; output [0:0] out ; -input p0 ; +input p6 ; wire [0:2] local_encoder2to3_0_data ; wire [0:2] local_encoder2to3_0_data_inv ; @@ -70660,19 +75063,19 @@ grid_clb_mux_1level_basis_input3_mem3_19 mux_l1_in_0_ ( .in ( { in[0] , in[1] , SYNOPSYS_UNCONNECTED_1 } ) , .mem ( local_encoder2to3_0_data ) , .mem_inv ( local_encoder2to3_0_data_inv ) , - .out ( mux_1level_basis_input3_mem3_0_out ) , .p0 ( p0 ) ) ; + .out ( mux_1level_basis_input3_mem3_0_out ) , .p6 ( p6 ) ) ; endmodule module grid_clb_mux_1level_basis_input3_mem3_18 ( in , mem , mem_inv , out , - p0 ) ; + p6 ) ; input [0:2] in ; input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; -input p0 ; +input p6 ; -scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , +scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p6 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out[0] ) ) ; @@ -70695,12 +75098,12 @@ sky130_fd_sc_hd__buf_1 FTB_66__65 ( .A ( addr[1] ) , .X ( data[2] ) ) ; endmodule -module grid_clb_mux_1level_size2_18 ( in , sram , sram_inv , out , p0 ) ; +module grid_clb_mux_1level_size2_18 ( in , sram , sram_inv , out , p6 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; output [0:0] out ; -input p0 ; +input p6 ; wire [0:2] local_encoder2to3_0_data ; wire [0:2] local_encoder2to3_0_data_inv ; @@ -70715,7 +75118,7 @@ grid_clb_mux_1level_basis_input3_mem3_18 mux_l1_in_0_ ( .in ( { in[0] , in[1] , SYNOPSYS_UNCONNECTED_1 } ) , .mem ( local_encoder2to3_0_data ) , .mem_inv ( local_encoder2to3_0_data_inv ) , - .out ( mux_1level_basis_input3_mem3_0_out ) , .p0 ( p0 ) ) ; + .out ( mux_1level_basis_input3_mem3_0_out ) , .p6 ( p6 ) ) ; endmodule @@ -70752,14 +75155,14 @@ endmodule module grid_clb_mux_1level_tapbuf_basis_input3_mem3_9 ( in , mem , mem_inv , - out , p0 ) ; + out , p6 ) ; input [0:2] in ; input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; -input p0 ; +input p6 ; -scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , +scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p6 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out[0] ) ) ; @@ -70783,13 +75186,13 @@ endmodule module grid_clb_mux_1level_tapbuf_size2_9 ( in , sram , sram_inv , out , - p_abuf0 , p0 ) ; + p_abuf0 , p6 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; output [0:0] out ; output p_abuf0 ; -input p0 ; +input p6 ; wire [0:2] local_encoder2to3_0_data ; wire [0:2] local_encoder2to3_0_data_inv ; @@ -70802,23 +75205,23 @@ grid_clb_mux_1level_tapbuf_basis_input3_mem3_9 mux_l1_in_0_ ( .in ( { in[0] , in[1] , SYNOPSYS_UNCONNECTED_1 } ) , .mem ( local_encoder2to3_0_data ) , .mem_inv ( local_encoder2to3_0_data_inv ) , - .out ( mux_1level_tapbuf_basis_input3_mem3_0_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_160 ( + .out ( mux_1level_tapbuf_basis_input3_mem3_0_out ) , .p6 ( p6 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_159 ( .A ( mux_1level_tapbuf_basis_input3_mem3_0_out[0] ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_161 ( +sky130_fd_sc_hd__inv_1 BINV_R_160 ( .A ( mux_1level_tapbuf_basis_input3_mem3_0_out[0] ) , .Y ( p_abuf0 ) ) ; endmodule module grid_clb_mux_1level_tapbuf_basis_input3_mem3_8 ( in , mem , mem_inv , - out , p0 ) ; + out , p6 ) ; input [0:2] in ; input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; -input p0 ; +input p6 ; -scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , +scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p6 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out[0] ) ) ; @@ -70842,13 +75245,13 @@ endmodule module grid_clb_mux_1level_tapbuf_size2_8 ( in , sram , sram_inv , out , - p_abuf0 , p0 ) ; + p_abuf0 , p6 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; output [0:0] out ; output p_abuf0 ; -input p0 ; +input p6 ; wire [0:2] local_encoder2to3_0_data ; wire [0:2] local_encoder2to3_0_data_inv ; @@ -70861,10 +75264,10 @@ grid_clb_mux_1level_tapbuf_basis_input3_mem3_8 mux_l1_in_0_ ( .in ( { in[0] , in[1] , SYNOPSYS_UNCONNECTED_1 } ) , .mem ( local_encoder2to3_0_data ) , .mem_inv ( local_encoder2to3_0_data_inv ) , - .out ( mux_1level_tapbuf_basis_input3_mem3_0_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_157 ( + .out ( mux_1level_tapbuf_basis_input3_mem3_0_out ) , .p6 ( p6 ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_156 ( .A ( mux_1level_tapbuf_basis_input3_mem3_0_out[0] ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_158 ( +sky130_fd_sc_hd__inv_8 BINV_R_157 ( .A ( mux_1level_tapbuf_basis_input3_mem3_0_out[0] ) , .Y ( p_abuf0 ) ) ; endmodule @@ -70932,14 +75335,14 @@ endmodule module grid_clb_mux_1level_basis_input3_mem3_17 ( in , mem , mem_inv , out , - p0 ) ; + p6 ) ; input [0:2] in ; input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; -input p0 ; +input p6 ; -scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , +scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p6 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out[0] ) ) ; @@ -70962,12 +75365,12 @@ sky130_fd_sc_hd__buf_1 FTB_59__58 ( .A ( addr[1] ) , .X ( data[2] ) ) ; endmodule -module grid_clb_mux_1level_size2_17 ( in , sram , sram_inv , out , p0 ) ; +module grid_clb_mux_1level_size2_17 ( in , sram , sram_inv , out , p6 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; output [0:0] out ; -input p0 ; +input p6 ; wire [0:2] local_encoder2to3_0_data ; wire [0:2] local_encoder2to3_0_data_inv ; @@ -70982,19 +75385,19 @@ grid_clb_mux_1level_basis_input3_mem3_17 mux_l1_in_0_ ( .in ( { in[0] , in[1] , SYNOPSYS_UNCONNECTED_1 } ) , .mem ( local_encoder2to3_0_data ) , .mem_inv ( local_encoder2to3_0_data_inv ) , - .out ( mux_1level_basis_input3_mem3_0_out ) , .p0 ( p0 ) ) ; + .out ( mux_1level_basis_input3_mem3_0_out ) , .p6 ( p6 ) ) ; endmodule module grid_clb_mux_1level_basis_input3_mem3_16 ( in , mem , mem_inv , out , - p0 ) ; + p6 ) ; input [0:2] in ; input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; -input p0 ; +input p6 ; -scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , +scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p6 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out[0] ) ) ; @@ -71017,12 +75420,12 @@ sky130_fd_sc_hd__buf_1 FTB_58__57 ( .A ( addr[1] ) , .X ( data[2] ) ) ; endmodule -module grid_clb_mux_1level_size2_16 ( in , sram , sram_inv , out , p0 ) ; +module grid_clb_mux_1level_size2_16 ( in , sram , sram_inv , out , p6 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; output [0:0] out ; -input p0 ; +input p6 ; wire [0:2] local_encoder2to3_0_data ; wire [0:2] local_encoder2to3_0_data_inv ; @@ -71037,7 +75440,7 @@ grid_clb_mux_1level_basis_input3_mem3_16 mux_l1_in_0_ ( .in ( { in[0] , in[1] , SYNOPSYS_UNCONNECTED_1 } ) , .mem ( local_encoder2to3_0_data ) , .mem_inv ( local_encoder2to3_0_data_inv ) , - .out ( mux_1level_basis_input3_mem3_0_out ) , .p0 ( p0 ) ) ; + .out ( mux_1level_basis_input3_mem3_0_out ) , .p6 ( p6 ) ) ; endmodule @@ -71254,7 +75657,7 @@ endmodule module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_4 ( pReset , prog_clk , frac_logic_in , frac_logic_cin , ccff_head , - frac_logic_out , frac_logic_cout , ccff_tail , p0 ) ; + frac_logic_out , frac_logic_cout , ccff_tail , p6 ) ; input [0:0] pReset ; input [0:0] prog_clk ; input [0:3] frac_logic_in ; @@ -71263,7 +75666,7 @@ input [0:0] ccff_head ; output [0:1] frac_logic_out ; output [0:0] frac_logic_cout ; output [0:0] ccff_tail ; -input p0 ; +input p6 ; wire [0:0] direct_interc_5_out ; wire [0:0] direct_interc_7_out ; @@ -71299,12 +75702,12 @@ grid_clb_mux_1level_size2_16 mux_frac_logic_out_0 ( } ) , .sram ( mux_1level_size2_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_2 , SYNOPSYS_UNCONNECTED_3 } ) , - .out ( frac_logic_out[0] ) , .p0 ( p0 ) ) ; + .out ( frac_logic_out[0] ) , .p6 ( p6 ) ) ; grid_clb_mux_1level_size2_17 mux_frac_lut4_0_in_2 ( .in ( { frac_logic_cin[0] , frac_logic_in[2] } ) , .sram ( mux_1level_size2_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_4 , SYNOPSYS_UNCONNECTED_5 } ) , - .out ( mux_1level_size2_1_out ) , .p0 ( p0 ) ) ; + .out ( mux_1level_size2_1_out ) , .p6 ( p6 ) ) ; grid_clb_mux_1level_size2_mem_16 mem_frac_logic_out_0 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ) , @@ -71320,7 +75723,7 @@ module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_4 ( pReset , prog_clk , Test_en , fabric_in , fabric_reg_in , fabric_sc_in , fabric_cin , fabric_reset , fabric_clk , ccff_head , fabric_out , fabric_reg_out , fabric_sc_out , fabric_cout , ccff_tail , p_abuf0 , - p_abuf1 , p0 ) ; + p_abuf1 , p6 ) ; input [0:0] pReset ; input [0:0] prog_clk ; input [0:0] Test_en ; @@ -71338,7 +75741,7 @@ output [0:0] fabric_cout ; output [0:0] ccff_tail ; output p_abuf0 ; output p_abuf1 ; -input p0 ; +input p6 ; wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ; wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ; @@ -71363,7 +75766,7 @@ grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ .frac_logic_cout ( { SYNOPSYS_UNCONNECTED_1 } ) , .ccff_tail ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) , - .p0 ( p0 ) ) ; + .p6 ( p6 ) ) ; grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_8 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0 ( .Test_en ( Test_en ) , .ff_D ( mux_1level_size2_0_out ) , .ff_DI ( fabric_sc_in ) , .ff_reset ( fabric_reset ) , @@ -71381,14 +75784,14 @@ grid_clb_mux_1level_tapbuf_size2_8 mux_fabric_out_0 ( } ) , .sram ( mux_1level_tapbuf_size2_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_2 , SYNOPSYS_UNCONNECTED_3 } ) , - .out ( fabric_out[0] ) , .p_abuf0 ( p_abuf0 ) , .p0 ( p0 ) ) ; + .out ( fabric_out[0] ) , .p_abuf0 ( p_abuf0 ) , .p6 ( p6 ) ) ; grid_clb_mux_1level_tapbuf_size2_9 mux_fabric_out_1 ( .in ( { fabric_sc_out[0] , logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] } ) , .sram ( mux_1level_tapbuf_size2_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_4 , SYNOPSYS_UNCONNECTED_5 } ) , - .out ( fabric_out[1] ) , .p_abuf0 ( p_abuf1 ) , .p0 ( p0 ) ) ; + .out ( fabric_out[1] ) , .p_abuf0 ( p_abuf1 ) , .p6 ( p6 ) ) ; grid_clb_mux_1level_tapbuf_size2_mem_8 mem_fabric_out_0 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) , @@ -71407,7 +75810,7 @@ grid_clb_mux_1level_size2_18 mux_ff_0_D_0 ( fabric_reg_in[0] } ) , .sram ( mux_1level_size2_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_6 , SYNOPSYS_UNCONNECTED_7 } ) , - .out ( mux_1level_size2_0_out ) , .p0 ( p0 ) ) ; + .out ( mux_1level_size2_0_out ) , .p6 ( p6 ) ) ; grid_clb_mux_1level_size2_19 mux_ff_1_D_0 ( .in ( { logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] , @@ -71415,7 +75818,7 @@ grid_clb_mux_1level_size2_19 mux_ff_1_D_0 ( } ) , .sram ( mux_1level_size2_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_8 , SYNOPSYS_UNCONNECTED_9 } ) , - .out ( mux_1level_size2_1_out ) , .p0 ( p0 ) ) ; + .out ( mux_1level_size2_1_out ) , .p6 ( p6 ) ) ; grid_clb_mux_1level_size2_mem_18 mem_ff_0_D_0 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( mux_1level_tapbuf_size2_mem_1_ccff_tail ) , @@ -71430,7 +75833,7 @@ endmodule module grid_clb_logical_tile_clb_mode_default__fle_4 ( pReset , prog_clk , Test_en , fle_in , fle_reg_in , fle_sc_in , fle_cin , fle_reset , fle_clk , ccff_head , fle_out , fle_reg_out , fle_sc_out , fle_cout , - ccff_tail , p_abuf0 , p_abuf1 , p0 ) ; + ccff_tail , p_abuf0 , p_abuf1 , p6 ) ; input [0:0] pReset ; input [0:0] prog_clk ; input [0:0] Test_en ; @@ -71448,7 +75851,7 @@ output [0:0] fle_cout ; output [0:0] ccff_tail ; output p_abuf0 ; output p_abuf1 ; -input p0 ; +input p6 ; grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_4 logical_tile_clb_mode_default__fle_mode_physical__fabric_0 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , @@ -71460,7 +75863,7 @@ grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_4 logical_tile .fabric_reg_out ( fle_reg_out ) , .fabric_sc_out ( fle_sc_out ) , .fabric_cout ( { SYNOPSYS_UNCONNECTED_2 } ) , .ccff_tail ( ccff_tail ) , .p_abuf0 ( p_abuf0 ) , .p_abuf1 ( p_abuf1 ) , - .p0 ( p0 ) ) ; + .p6 ( p6 ) ) ; endmodule @@ -71497,14 +75900,14 @@ endmodule module grid_clb_mux_1level_basis_input3_mem3_15 ( in , mem , mem_inv , out , - p0 ) ; + p6 ) ; input [0:2] in ; input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; -input p0 ; +input p6 ; -scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , +scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p6 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out[0] ) ) ; @@ -71527,12 +75930,12 @@ sky130_fd_sc_hd__buf_1 FTB_53__52 ( .A ( addr[1] ) , .X ( data[2] ) ) ; endmodule -module grid_clb_mux_1level_size2_15 ( in , sram , sram_inv , out , p0 ) ; +module grid_clb_mux_1level_size2_15 ( in , sram , sram_inv , out , p6 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; output [0:0] out ; -input p0 ; +input p6 ; wire [0:2] local_encoder2to3_0_data ; wire [0:2] local_encoder2to3_0_data_inv ; @@ -71547,19 +75950,19 @@ grid_clb_mux_1level_basis_input3_mem3_15 mux_l1_in_0_ ( .in ( { in[0] , in[1] , SYNOPSYS_UNCONNECTED_1 } ) , .mem ( local_encoder2to3_0_data ) , .mem_inv ( local_encoder2to3_0_data_inv ) , - .out ( mux_1level_basis_input3_mem3_0_out ) , .p0 ( p0 ) ) ; + .out ( mux_1level_basis_input3_mem3_0_out ) , .p6 ( p6 ) ) ; endmodule module grid_clb_mux_1level_basis_input3_mem3_14 ( in , mem , mem_inv , out , - p2 ) ; + p0 ) ; input [0:2] in ; input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; -input p2 ; +input p0 ; -scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p2 ) , +scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out[0] ) ) ; @@ -71582,12 +75985,12 @@ sky130_fd_sc_hd__buf_1 FTB_52__51 ( .A ( addr[1] ) , .X ( data[2] ) ) ; endmodule -module grid_clb_mux_1level_size2_14 ( in , sram , sram_inv , out , p2 ) ; +module grid_clb_mux_1level_size2_14 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; output [0:0] out ; -input p2 ; +input p0 ; wire [0:2] local_encoder2to3_0_data ; wire [0:2] local_encoder2to3_0_data_inv ; @@ -71602,7 +76005,7 @@ grid_clb_mux_1level_basis_input3_mem3_14 mux_l1_in_0_ ( .in ( { in[0] , in[1] , SYNOPSYS_UNCONNECTED_1 } ) , .mem ( local_encoder2to3_0_data ) , .mem_inv ( local_encoder2to3_0_data_inv ) , - .out ( mux_1level_basis_input3_mem3_0_out ) , .p2 ( p2 ) ) ; + .out ( mux_1level_basis_input3_mem3_0_out ) , .p0 ( p0 ) ) ; endmodule @@ -71639,14 +76042,14 @@ endmodule module grid_clb_mux_1level_tapbuf_basis_input3_mem3_7 ( in , mem , mem_inv , - out , p0 ) ; + out , p6 ) ; input [0:2] in ; input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; -input p0 ; +input p6 ; -scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , +scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p6 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out[0] ) ) ; @@ -71670,13 +76073,13 @@ endmodule module grid_clb_mux_1level_tapbuf_size2_7 ( in , sram , sram_inv , out , - p_abuf0 , p0 ) ; + p_abuf0 , p6 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; output [0:0] out ; output p_abuf0 ; -input p0 ; +input p6 ; wire [0:2] local_encoder2to3_0_data ; wire [0:2] local_encoder2to3_0_data_inv ; @@ -71689,23 +76092,23 @@ grid_clb_mux_1level_tapbuf_basis_input3_mem3_7 mux_l1_in_0_ ( .in ( { in[0] , in[1] , SYNOPSYS_UNCONNECTED_1 } ) , .mem ( local_encoder2to3_0_data ) , .mem_inv ( local_encoder2to3_0_data_inv ) , - .out ( mux_1level_tapbuf_basis_input3_mem3_0_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_154 ( + .out ( mux_1level_tapbuf_basis_input3_mem3_0_out ) , .p6 ( p6 ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_153 ( .A ( mux_1level_tapbuf_basis_input3_mem3_0_out[0] ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_155 ( +sky130_fd_sc_hd__inv_8 BINV_R_154 ( .A ( mux_1level_tapbuf_basis_input3_mem3_0_out[0] ) , .Y ( p_abuf0 ) ) ; endmodule module grid_clb_mux_1level_tapbuf_basis_input3_mem3_6 ( in , mem , mem_inv , - out , p2 ) ; + out , p0 ) ; input [0:2] in ; input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; -input p2 ; +input p0 ; -scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p2 ) , +scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out[0] ) ) ; @@ -71729,13 +76132,13 @@ endmodule module grid_clb_mux_1level_tapbuf_size2_6 ( in , sram , sram_inv , out , - p_abuf0 , p2 ) ; + p_abuf0 , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; output [0:0] out ; output p_abuf0 ; -input p2 ; +input p0 ; wire [0:2] local_encoder2to3_0_data ; wire [0:2] local_encoder2to3_0_data_inv ; @@ -71748,10 +76151,10 @@ grid_clb_mux_1level_tapbuf_basis_input3_mem3_6 mux_l1_in_0_ ( .in ( { in[0] , in[1] , SYNOPSYS_UNCONNECTED_1 } ) , .mem ( local_encoder2to3_0_data ) , .mem_inv ( local_encoder2to3_0_data_inv ) , - .out ( mux_1level_tapbuf_basis_input3_mem3_0_out ) , .p2 ( p2 ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_151 ( + .out ( mux_1level_tapbuf_basis_input3_mem3_0_out ) , .p0 ( p0 ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_150 ( .A ( mux_1level_tapbuf_basis_input3_mem3_0_out[0] ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_152 ( +sky130_fd_sc_hd__inv_8 BINV_R_151 ( .A ( mux_1level_tapbuf_basis_input3_mem3_0_out[0] ) , .Y ( p_abuf0 ) ) ; endmodule @@ -71819,14 +76222,14 @@ endmodule module grid_clb_mux_1level_basis_input3_mem3_13 ( in , mem , mem_inv , out , - p2 ) ; + p0 ) ; input [0:2] in ; input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; -input p2 ; +input p0 ; -scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p2 ) , +scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out[0] ) ) ; @@ -71849,12 +76252,12 @@ sky130_fd_sc_hd__buf_1 FTB_45__44 ( .A ( addr[1] ) , .X ( data[2] ) ) ; endmodule -module grid_clb_mux_1level_size2_13 ( in , sram , sram_inv , out , p2 ) ; +module grid_clb_mux_1level_size2_13 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; output [0:0] out ; -input p2 ; +input p0 ; wire [0:2] local_encoder2to3_0_data ; wire [0:2] local_encoder2to3_0_data_inv ; @@ -71869,19 +76272,19 @@ grid_clb_mux_1level_basis_input3_mem3_13 mux_l1_in_0_ ( .in ( { in[0] , in[1] , SYNOPSYS_UNCONNECTED_1 } ) , .mem ( local_encoder2to3_0_data ) , .mem_inv ( local_encoder2to3_0_data_inv ) , - .out ( mux_1level_basis_input3_mem3_0_out ) , .p2 ( p2 ) ) ; + .out ( mux_1level_basis_input3_mem3_0_out ) , .p0 ( p0 ) ) ; endmodule module grid_clb_mux_1level_basis_input3_mem3_12 ( in , mem , mem_inv , out , - p2 ) ; + p0 ) ; input [0:2] in ; input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; -input p2 ; +input p0 ; -scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p2 ) , +scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out[0] ) ) ; @@ -71904,12 +76307,12 @@ sky130_fd_sc_hd__buf_1 FTB_44__43 ( .A ( addr[1] ) , .X ( data[2] ) ) ; endmodule -module grid_clb_mux_1level_size2_12 ( in , sram , sram_inv , out , p2 ) ; +module grid_clb_mux_1level_size2_12 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; output [0:0] out ; -input p2 ; +input p0 ; wire [0:2] local_encoder2to3_0_data ; wire [0:2] local_encoder2to3_0_data_inv ; @@ -71924,7 +76327,7 @@ grid_clb_mux_1level_basis_input3_mem3_12 mux_l1_in_0_ ( .in ( { in[0] , in[1] , SYNOPSYS_UNCONNECTED_1 } ) , .mem ( local_encoder2to3_0_data ) , .mem_inv ( local_encoder2to3_0_data_inv ) , - .out ( mux_1level_basis_input3_mem3_0_out ) , .p2 ( p2 ) ) ; + .out ( mux_1level_basis_input3_mem3_0_out ) , .p0 ( p0 ) ) ; endmodule @@ -72141,7 +76544,7 @@ endmodule module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_3 ( pReset , prog_clk , frac_logic_in , frac_logic_cin , ccff_head , - frac_logic_out , frac_logic_cout , ccff_tail , p2 ) ; + frac_logic_out , frac_logic_cout , ccff_tail , p0 ) ; input [0:0] pReset ; input [0:0] prog_clk ; input [0:3] frac_logic_in ; @@ -72150,7 +76553,7 @@ input [0:0] ccff_head ; output [0:1] frac_logic_out ; output [0:0] frac_logic_cout ; output [0:0] ccff_tail ; -input p2 ; +input p0 ; wire [0:0] direct_interc_5_out ; wire [0:0] direct_interc_7_out ; @@ -72186,12 +76589,12 @@ grid_clb_mux_1level_size2_12 mux_frac_logic_out_0 ( } ) , .sram ( mux_1level_size2_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_2 , SYNOPSYS_UNCONNECTED_3 } ) , - .out ( frac_logic_out[0] ) , .p2 ( p2 ) ) ; + .out ( frac_logic_out[0] ) , .p0 ( p0 ) ) ; grid_clb_mux_1level_size2_13 mux_frac_lut4_0_in_2 ( .in ( { frac_logic_cin[0] , frac_logic_in[2] } ) , .sram ( mux_1level_size2_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_4 , SYNOPSYS_UNCONNECTED_5 } ) , - .out ( mux_1level_size2_1_out ) , .p2 ( p2 ) ) ; + .out ( mux_1level_size2_1_out ) , .p0 ( p0 ) ) ; grid_clb_mux_1level_size2_mem_12 mem_frac_logic_out_0 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ) , @@ -72207,7 +76610,7 @@ module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_3 ( pReset , prog_clk , Test_en , fabric_in , fabric_reg_in , fabric_sc_in , fabric_cin , fabric_reset , fabric_clk , ccff_head , fabric_out , fabric_reg_out , fabric_sc_out , fabric_cout , ccff_tail , p_abuf0 , - p_abuf1 , p0 , p2 ) ; + p_abuf1 , p0 , p6 ) ; input [0:0] pReset ; input [0:0] prog_clk ; input [0:0] Test_en ; @@ -72226,7 +76629,7 @@ output [0:0] ccff_tail ; output p_abuf0 ; output p_abuf1 ; input p0 ; -input p2 ; +input p6 ; wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ; wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ; @@ -72251,7 +76654,7 @@ grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ .frac_logic_cout ( { SYNOPSYS_UNCONNECTED_1 } ) , .ccff_tail ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) , - .p2 ( p2 ) ) ; + .p0 ( p0 ) ) ; grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_6 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0 ( .Test_en ( Test_en ) , .ff_D ( mux_1level_size2_0_out ) , .ff_DI ( fabric_sc_in ) , .ff_reset ( fabric_reset ) , @@ -72269,14 +76672,14 @@ grid_clb_mux_1level_tapbuf_size2_6 mux_fabric_out_0 ( } ) , .sram ( mux_1level_tapbuf_size2_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_2 , SYNOPSYS_UNCONNECTED_3 } ) , - .out ( fabric_out[0] ) , .p_abuf0 ( p_abuf0 ) , .p2 ( p2 ) ) ; + .out ( fabric_out[0] ) , .p_abuf0 ( p_abuf0 ) , .p0 ( p0 ) ) ; grid_clb_mux_1level_tapbuf_size2_7 mux_fabric_out_1 ( .in ( { fabric_sc_out[0] , logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] } ) , .sram ( mux_1level_tapbuf_size2_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_4 , SYNOPSYS_UNCONNECTED_5 } ) , - .out ( fabric_out[1] ) , .p_abuf0 ( p_abuf1 ) , .p0 ( p0 ) ) ; + .out ( fabric_out[1] ) , .p_abuf0 ( p_abuf1 ) , .p6 ( p6 ) ) ; grid_clb_mux_1level_tapbuf_size2_mem_6 mem_fabric_out_0 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) , @@ -72295,7 +76698,7 @@ grid_clb_mux_1level_size2_14 mux_ff_0_D_0 ( fabric_reg_in[0] } ) , .sram ( mux_1level_size2_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_6 , SYNOPSYS_UNCONNECTED_7 } ) , - .out ( mux_1level_size2_0_out ) , .p2 ( p2 ) ) ; + .out ( mux_1level_size2_0_out ) , .p0 ( p0 ) ) ; grid_clb_mux_1level_size2_15 mux_ff_1_D_0 ( .in ( { logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] , @@ -72303,7 +76706,7 @@ grid_clb_mux_1level_size2_15 mux_ff_1_D_0 ( } ) , .sram ( mux_1level_size2_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_8 , SYNOPSYS_UNCONNECTED_9 } ) , - .out ( mux_1level_size2_1_out ) , .p0 ( p0 ) ) ; + .out ( mux_1level_size2_1_out ) , .p6 ( p6 ) ) ; grid_clb_mux_1level_size2_mem_14 mem_ff_0_D_0 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( mux_1level_tapbuf_size2_mem_1_ccff_tail ) , @@ -72318,7 +76721,7 @@ endmodule module grid_clb_logical_tile_clb_mode_default__fle_3 ( pReset , prog_clk , Test_en , fle_in , fle_reg_in , fle_sc_in , fle_cin , fle_reset , fle_clk , ccff_head , fle_out , fle_reg_out , fle_sc_out , fle_cout , - ccff_tail , p_abuf0 , p_abuf1 , p0 , p2 ) ; + ccff_tail , p_abuf0 , p_abuf1 , p0 , p6 ) ; input [0:0] pReset ; input [0:0] prog_clk ; input [0:0] Test_en ; @@ -72337,7 +76740,7 @@ output [0:0] ccff_tail ; output p_abuf0 ; output p_abuf1 ; input p0 ; -input p2 ; +input p6 ; grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_3 logical_tile_clb_mode_default__fle_mode_physical__fabric_0 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , @@ -72349,7 +76752,7 @@ grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_3 logical_tile .fabric_reg_out ( fle_reg_out ) , .fabric_sc_out ( fle_sc_out ) , .fabric_cout ( { SYNOPSYS_UNCONNECTED_2 } ) , .ccff_tail ( ccff_tail ) , .p_abuf0 ( p_abuf0 ) , .p_abuf1 ( p_abuf1 ) , - .p0 ( p0 ) , .p2 ( p2 ) ) ; + .p0 ( p0 ) , .p6 ( p6 ) ) ; endmodule @@ -72386,14 +76789,14 @@ endmodule module grid_clb_mux_1level_basis_input3_mem3_11 ( in , mem , mem_inv , out , - p2 ) ; + p4 ) ; input [0:2] in ; input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; -input p2 ; +input p4 ; -scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p2 ) , +scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p4 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out[0] ) ) ; @@ -72416,12 +76819,12 @@ sky130_fd_sc_hd__buf_1 FTB_39__38 ( .A ( addr[1] ) , .X ( data[2] ) ) ; endmodule -module grid_clb_mux_1level_size2_11 ( in , sram , sram_inv , out , p2 ) ; +module grid_clb_mux_1level_size2_11 ( in , sram , sram_inv , out , p4 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; output [0:0] out ; -input p2 ; +input p4 ; wire [0:2] local_encoder2to3_0_data ; wire [0:2] local_encoder2to3_0_data_inv ; @@ -72436,19 +76839,19 @@ grid_clb_mux_1level_basis_input3_mem3_11 mux_l1_in_0_ ( .in ( { in[0] , in[1] , SYNOPSYS_UNCONNECTED_1 } ) , .mem ( local_encoder2to3_0_data ) , .mem_inv ( local_encoder2to3_0_data_inv ) , - .out ( mux_1level_basis_input3_mem3_0_out ) , .p2 ( p2 ) ) ; + .out ( mux_1level_basis_input3_mem3_0_out ) , .p4 ( p4 ) ) ; endmodule module grid_clb_mux_1level_basis_input3_mem3_10 ( in , mem , mem_inv , out , - p1 ) ; + p4 ) ; input [0:2] in ; input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; -input p1 ; +input p4 ; -scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p1 ) , +scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p4 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out[0] ) ) ; @@ -72471,12 +76874,12 @@ sky130_fd_sc_hd__buf_1 FTB_38__37 ( .A ( addr[1] ) , .X ( data[2] ) ) ; endmodule -module grid_clb_mux_1level_size2_10 ( in , sram , sram_inv , out , p1 ) ; +module grid_clb_mux_1level_size2_10 ( in , sram , sram_inv , out , p4 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; output [0:0] out ; -input p1 ; +input p4 ; wire [0:2] local_encoder2to3_0_data ; wire [0:2] local_encoder2to3_0_data_inv ; @@ -72491,7 +76894,7 @@ grid_clb_mux_1level_basis_input3_mem3_10 mux_l1_in_0_ ( .in ( { in[0] , in[1] , SYNOPSYS_UNCONNECTED_1 } ) , .mem ( local_encoder2to3_0_data ) , .mem_inv ( local_encoder2to3_0_data_inv ) , - .out ( mux_1level_basis_input3_mem3_0_out ) , .p1 ( p1 ) ) ; + .out ( mux_1level_basis_input3_mem3_0_out ) , .p4 ( p4 ) ) ; endmodule @@ -72528,14 +76931,14 @@ endmodule module grid_clb_mux_1level_tapbuf_basis_input3_mem3_5 ( in , mem , mem_inv , - out , p2 ) ; + out , p4 ) ; input [0:2] in ; input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; -input p2 ; +input p4 ; -scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p2 ) , +scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p4 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out[0] ) ) ; @@ -72559,13 +76962,13 @@ endmodule module grid_clb_mux_1level_tapbuf_size2_5 ( in , sram , sram_inv , out , - p_abuf0 , p2 ) ; + p_abuf0 , p4 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; output [0:0] out ; output p_abuf0 ; -input p2 ; +input p4 ; wire [0:2] local_encoder2to3_0_data ; wire [0:2] local_encoder2to3_0_data_inv ; @@ -72578,23 +76981,23 @@ grid_clb_mux_1level_tapbuf_basis_input3_mem3_5 mux_l1_in_0_ ( .in ( { in[0] , in[1] , SYNOPSYS_UNCONNECTED_1 } ) , .mem ( local_encoder2to3_0_data ) , .mem_inv ( local_encoder2to3_0_data_inv ) , - .out ( mux_1level_tapbuf_basis_input3_mem3_0_out ) , .p2 ( p2 ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_148 ( + .out ( mux_1level_tapbuf_basis_input3_mem3_0_out ) , .p4 ( p4 ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_147 ( .A ( mux_1level_tapbuf_basis_input3_mem3_0_out[0] ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_149 ( +sky130_fd_sc_hd__inv_8 BINV_R_148 ( .A ( mux_1level_tapbuf_basis_input3_mem3_0_out[0] ) , .Y ( p_abuf0 ) ) ; endmodule module grid_clb_mux_1level_tapbuf_basis_input3_mem3_4 ( in , mem , mem_inv , - out , p1 ) ; + out , p4 ) ; input [0:2] in ; input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; -input p1 ; +input p4 ; -scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p1 ) , +scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p4 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out[0] ) ) ; @@ -72618,13 +77021,13 @@ endmodule module grid_clb_mux_1level_tapbuf_size2_4 ( in , sram , sram_inv , out , - p_abuf0 , p1 ) ; + p_abuf0 , p4 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; output [0:0] out ; output p_abuf0 ; -input p1 ; +input p4 ; wire [0:2] local_encoder2to3_0_data ; wire [0:2] local_encoder2to3_0_data_inv ; @@ -72637,10 +77040,10 @@ grid_clb_mux_1level_tapbuf_basis_input3_mem3_4 mux_l1_in_0_ ( .in ( { in[0] , in[1] , SYNOPSYS_UNCONNECTED_1 } ) , .mem ( local_encoder2to3_0_data ) , .mem_inv ( local_encoder2to3_0_data_inv ) , - .out ( mux_1level_tapbuf_basis_input3_mem3_0_out ) , .p1 ( p1 ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_145 ( + .out ( mux_1level_tapbuf_basis_input3_mem3_0_out ) , .p4 ( p4 ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_144 ( .A ( mux_1level_tapbuf_basis_input3_mem3_0_out[0] ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_146 ( +sky130_fd_sc_hd__inv_8 BINV_R_145 ( .A ( mux_1level_tapbuf_basis_input3_mem3_0_out[0] ) , .Y ( p_abuf0 ) ) ; endmodule @@ -72708,14 +77111,14 @@ endmodule module grid_clb_mux_1level_basis_input3_mem3_9 ( in , mem , mem_inv , out , - p1 ) ; + p2 ) ; input [0:2] in ; input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; -input p1 ; +input p2 ; -scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p1 ) , +scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p2 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out[0] ) ) ; @@ -72738,12 +77141,12 @@ sky130_fd_sc_hd__buf_1 FTB_31__30 ( .A ( addr[1] ) , .X ( data[2] ) ) ; endmodule -module grid_clb_mux_1level_size2_9 ( in , sram , sram_inv , out , p1 ) ; +module grid_clb_mux_1level_size2_9 ( in , sram , sram_inv , out , p2 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; output [0:0] out ; -input p1 ; +input p2 ; wire [0:2] local_encoder2to3_0_data ; wire [0:2] local_encoder2to3_0_data_inv ; @@ -72758,7 +77161,7 @@ grid_clb_mux_1level_basis_input3_mem3_9 mux_l1_in_0_ ( .in ( { in[0] , in[1] , SYNOPSYS_UNCONNECTED_1 } ) , .mem ( local_encoder2to3_0_data ) , .mem_inv ( local_encoder2to3_0_data_inv ) , - .out ( mux_1level_basis_input3_mem3_0_out ) , .p1 ( p1 ) ) ; + .out ( mux_1level_basis_input3_mem3_0_out ) , .p2 ( p2 ) ) ; endmodule @@ -73030,7 +77433,7 @@ endmodule module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_2 ( pReset , prog_clk , frac_logic_in , frac_logic_cin , ccff_head , - frac_logic_out , frac_logic_cout , ccff_tail , p1 , p2 ) ; + frac_logic_out , frac_logic_cout , ccff_tail , p2 ) ; input [0:0] pReset ; input [0:0] prog_clk ; input [0:3] frac_logic_in ; @@ -73039,7 +77442,6 @@ input [0:0] ccff_head ; output [0:1] frac_logic_out ; output [0:0] frac_logic_cout ; output [0:0] ccff_tail ; -input p1 ; input p2 ; wire [0:0] direct_interc_5_out ; @@ -73081,7 +77483,7 @@ grid_clb_mux_1level_size2_9 mux_frac_lut4_0_in_2 ( .in ( { frac_logic_cin[0] , frac_logic_in[2] } ) , .sram ( mux_1level_size2_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_4 , SYNOPSYS_UNCONNECTED_5 } ) , - .out ( mux_1level_size2_1_out ) , .p1 ( p1 ) ) ; + .out ( mux_1level_size2_1_out ) , .p2 ( p2 ) ) ; grid_clb_mux_1level_size2_mem_8 mem_frac_logic_out_0 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ) , @@ -73097,7 +77499,7 @@ module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_2 ( pReset , prog_clk , Test_en , fabric_in , fabric_reg_in , fabric_sc_in , fabric_cin , fabric_reset , fabric_clk , ccff_head , fabric_out , fabric_reg_out , fabric_sc_out , fabric_cout , ccff_tail , p_abuf0 , - p_abuf1 , p1 , p2 ) ; + p_abuf1 , p2 , p4 ) ; input [0:0] pReset ; input [0:0] prog_clk ; input [0:0] Test_en ; @@ -73115,8 +77517,8 @@ output [0:0] fabric_cout ; output [0:0] ccff_tail ; output p_abuf0 ; output p_abuf1 ; -input p1 ; input p2 ; +input p4 ; wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ; wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ; @@ -73141,7 +77543,7 @@ grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ .frac_logic_cout ( { SYNOPSYS_UNCONNECTED_1 } ) , .ccff_tail ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) , - .p1 ( p1 ) , .p2 ( p2 ) ) ; + .p2 ( p2 ) ) ; grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_4 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0 ( .Test_en ( Test_en ) , .ff_D ( mux_1level_size2_0_out ) , .ff_DI ( fabric_sc_in ) , .ff_reset ( fabric_reset ) , @@ -73159,14 +77561,14 @@ grid_clb_mux_1level_tapbuf_size2_4 mux_fabric_out_0 ( } ) , .sram ( mux_1level_tapbuf_size2_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_2 , SYNOPSYS_UNCONNECTED_3 } ) , - .out ( fabric_out[0] ) , .p_abuf0 ( p_abuf0 ) , .p1 ( p1 ) ) ; + .out ( fabric_out[0] ) , .p_abuf0 ( p_abuf0 ) , .p4 ( p4 ) ) ; grid_clb_mux_1level_tapbuf_size2_5 mux_fabric_out_1 ( .in ( { fabric_sc_out[0] , logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] } ) , .sram ( mux_1level_tapbuf_size2_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_4 , SYNOPSYS_UNCONNECTED_5 } ) , - .out ( fabric_out[1] ) , .p_abuf0 ( p_abuf1 ) , .p2 ( p2 ) ) ; + .out ( fabric_out[1] ) , .p_abuf0 ( p_abuf1 ) , .p4 ( p4 ) ) ; grid_clb_mux_1level_tapbuf_size2_mem_4 mem_fabric_out_0 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) , @@ -73185,7 +77587,7 @@ grid_clb_mux_1level_size2_10 mux_ff_0_D_0 ( fabric_reg_in[0] } ) , .sram ( mux_1level_size2_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_6 , SYNOPSYS_UNCONNECTED_7 } ) , - .out ( mux_1level_size2_0_out ) , .p1 ( p1 ) ) ; + .out ( mux_1level_size2_0_out ) , .p4 ( p4 ) ) ; grid_clb_mux_1level_size2_11 mux_ff_1_D_0 ( .in ( { logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] , @@ -73193,7 +77595,7 @@ grid_clb_mux_1level_size2_11 mux_ff_1_D_0 ( } ) , .sram ( mux_1level_size2_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_8 , SYNOPSYS_UNCONNECTED_9 } ) , - .out ( mux_1level_size2_1_out ) , .p2 ( p2 ) ) ; + .out ( mux_1level_size2_1_out ) , .p4 ( p4 ) ) ; grid_clb_mux_1level_size2_mem_10 mem_ff_0_D_0 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( mux_1level_tapbuf_size2_mem_1_ccff_tail ) , @@ -73208,7 +77610,7 @@ endmodule module grid_clb_logical_tile_clb_mode_default__fle_2 ( pReset , prog_clk , Test_en , fle_in , fle_reg_in , fle_sc_in , fle_cin , fle_reset , fle_clk , ccff_head , fle_out , fle_reg_out , fle_sc_out , fle_cout , - ccff_tail , p_abuf0 , p_abuf1 , p1 , p2 ) ; + ccff_tail , p_abuf0 , p_abuf1 , p2 , p4 ) ; input [0:0] pReset ; input [0:0] prog_clk ; input [0:0] Test_en ; @@ -73226,8 +77628,8 @@ output [0:0] fle_cout ; output [0:0] ccff_tail ; output p_abuf0 ; output p_abuf1 ; -input p1 ; input p2 ; +input p4 ; grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_2 logical_tile_clb_mode_default__fle_mode_physical__fabric_0 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , @@ -73239,7 +77641,7 @@ grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_2 logical_tile .fabric_reg_out ( fle_reg_out ) , .fabric_sc_out ( fle_sc_out ) , .fabric_cout ( { SYNOPSYS_UNCONNECTED_2 } ) , .ccff_tail ( ccff_tail ) , .p_abuf0 ( p_abuf0 ) , .p_abuf1 ( p_abuf1 ) , - .p1 ( p1 ) , .p2 ( p2 ) ) ; + .p2 ( p2 ) , .p4 ( p4 ) ) ; endmodule @@ -73276,14 +77678,14 @@ endmodule module grid_clb_mux_1level_basis_input3_mem3_7 ( in , mem , mem_inv , out , - p0 ) ; + p5 ) ; input [0:2] in ; input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; -input p0 ; +input p5 ; -scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , +scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p5 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out[0] ) ) ; @@ -73306,12 +77708,12 @@ sky130_fd_sc_hd__buf_1 FTB_25__24 ( .A ( addr[1] ) , .X ( data[2] ) ) ; endmodule -module grid_clb_mux_1level_size2_7 ( in , sram , sram_inv , out , p0 ) ; +module grid_clb_mux_1level_size2_7 ( in , sram , sram_inv , out , p5 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; output [0:0] out ; -input p0 ; +input p5 ; wire [0:2] local_encoder2to3_0_data ; wire [0:2] local_encoder2to3_0_data_inv ; @@ -73326,19 +77728,19 @@ grid_clb_mux_1level_basis_input3_mem3_7 mux_l1_in_0_ ( .in ( { in[0] , in[1] , SYNOPSYS_UNCONNECTED_1 } ) , .mem ( local_encoder2to3_0_data ) , .mem_inv ( local_encoder2to3_0_data_inv ) , - .out ( mux_1level_basis_input3_mem3_0_out ) , .p0 ( p0 ) ) ; + .out ( mux_1level_basis_input3_mem3_0_out ) , .p5 ( p5 ) ) ; endmodule module grid_clb_mux_1level_basis_input3_mem3_6 ( in , mem , mem_inv , out , - p0 ) ; + p5 ) ; input [0:2] in ; input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; -input p0 ; +input p5 ; -scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , +scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p5 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out[0] ) ) ; @@ -73361,12 +77763,12 @@ sky130_fd_sc_hd__buf_1 FTB_24__23 ( .A ( addr[1] ) , .X ( data[2] ) ) ; endmodule -module grid_clb_mux_1level_size2_6 ( in , sram , sram_inv , out , p0 ) ; +module grid_clb_mux_1level_size2_6 ( in , sram , sram_inv , out , p5 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; output [0:0] out ; -input p0 ; +input p5 ; wire [0:2] local_encoder2to3_0_data ; wire [0:2] local_encoder2to3_0_data_inv ; @@ -73381,7 +77783,7 @@ grid_clb_mux_1level_basis_input3_mem3_6 mux_l1_in_0_ ( .in ( { in[0] , in[1] , SYNOPSYS_UNCONNECTED_1 } ) , .mem ( local_encoder2to3_0_data ) , .mem_inv ( local_encoder2to3_0_data_inv ) , - .out ( mux_1level_basis_input3_mem3_0_out ) , .p0 ( p0 ) ) ; + .out ( mux_1level_basis_input3_mem3_0_out ) , .p5 ( p5 ) ) ; endmodule @@ -73418,14 +77820,14 @@ endmodule module grid_clb_mux_1level_tapbuf_basis_input3_mem3_3 ( in , mem , mem_inv , - out , p0 ) ; + out , p5 ) ; input [0:2] in ; input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; -input p0 ; +input p5 ; -scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , +scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p5 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out[0] ) ) ; @@ -73449,13 +77851,13 @@ endmodule module grid_clb_mux_1level_tapbuf_size2_3 ( in , sram , sram_inv , out , - p_abuf0 , p0 ) ; + p_abuf0 , p5 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; output [0:0] out ; output p_abuf0 ; -input p0 ; +input p5 ; wire [0:2] local_encoder2to3_0_data ; wire [0:2] local_encoder2to3_0_data_inv ; @@ -73468,10 +77870,10 @@ grid_clb_mux_1level_tapbuf_basis_input3_mem3_3 mux_l1_in_0_ ( .in ( { in[0] , in[1] , SYNOPSYS_UNCONNECTED_1 } ) , .mem ( local_encoder2to3_0_data ) , .mem_inv ( local_encoder2to3_0_data_inv ) , - .out ( mux_1level_tapbuf_basis_input3_mem3_0_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_142 ( + .out ( mux_1level_tapbuf_basis_input3_mem3_0_out ) , .p5 ( p5 ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_141 ( .A ( mux_1level_tapbuf_basis_input3_mem3_0_out[0] ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_143 ( +sky130_fd_sc_hd__inv_8 BINV_R_142 ( .A ( mux_1level_tapbuf_basis_input3_mem3_0_out[0] ) , .Y ( p_abuf0 ) ) ; endmodule @@ -73528,9 +77930,9 @@ grid_clb_mux_1level_tapbuf_basis_input3_mem3_2 mux_l1_in_0_ ( .mem ( local_encoder2to3_0_data ) , .mem_inv ( local_encoder2to3_0_data_inv ) , .out ( mux_1level_tapbuf_basis_input3_mem3_0_out ) , .p0 ( p0 ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_139 ( +sky130_fd_sc_hd__inv_1 BINV_R_138 ( .A ( mux_1level_tapbuf_basis_input3_mem3_0_out[0] ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_140 ( +sky130_fd_sc_hd__inv_8 BINV_R_139 ( .A ( mux_1level_tapbuf_basis_input3_mem3_0_out[0] ) , .Y ( p_abuf0 ) ) ; endmodule @@ -73598,14 +78000,14 @@ endmodule module grid_clb_mux_1level_basis_input3_mem3_5 ( in , mem , mem_inv , out , - p5 ) ; + p1 ) ; input [0:2] in ; input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; -input p5 ; +input p1 ; -scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p5 ) , +scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p1 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out[0] ) ) ; @@ -73628,12 +78030,12 @@ sky130_fd_sc_hd__buf_1 FTB_17__16 ( .A ( addr[1] ) , .X ( data[2] ) ) ; endmodule -module grid_clb_mux_1level_size2_5 ( in , sram , sram_inv , out , p5 ) ; +module grid_clb_mux_1level_size2_5 ( in , sram , sram_inv , out , p1 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; output [0:0] out ; -input p5 ; +input p1 ; wire [0:2] local_encoder2to3_0_data ; wire [0:2] local_encoder2to3_0_data_inv ; @@ -73648,19 +78050,19 @@ grid_clb_mux_1level_basis_input3_mem3_5 mux_l1_in_0_ ( .in ( { in[0] , in[1] , SYNOPSYS_UNCONNECTED_1 } ) , .mem ( local_encoder2to3_0_data ) , .mem_inv ( local_encoder2to3_0_data_inv ) , - .out ( mux_1level_basis_input3_mem3_0_out ) , .p5 ( p5 ) ) ; + .out ( mux_1level_basis_input3_mem3_0_out ) , .p1 ( p1 ) ) ; endmodule module grid_clb_mux_1level_basis_input3_mem3_4 ( in , mem , mem_inv , out , - p5 ) ; + p0 ) ; input [0:2] in ; input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; -input p5 ; +input p0 ; -scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p5 ) , +scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p0 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out[0] ) ) ; @@ -73683,12 +78085,12 @@ sky130_fd_sc_hd__buf_1 FTB_16__15 ( .A ( addr[1] ) , .X ( data[2] ) ) ; endmodule -module grid_clb_mux_1level_size2_4 ( in , sram , sram_inv , out , p5 ) ; +module grid_clb_mux_1level_size2_4 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; output [0:0] out ; -input p5 ; +input p0 ; wire [0:2] local_encoder2to3_0_data ; wire [0:2] local_encoder2to3_0_data_inv ; @@ -73703,7 +78105,7 @@ grid_clb_mux_1level_basis_input3_mem3_4 mux_l1_in_0_ ( .in ( { in[0] , in[1] , SYNOPSYS_UNCONNECTED_1 } ) , .mem ( local_encoder2to3_0_data ) , .mem_inv ( local_encoder2to3_0_data_inv ) , - .out ( mux_1level_basis_input3_mem3_0_out ) , .p5 ( p5 ) ) ; + .out ( mux_1level_basis_input3_mem3_0_out ) , .p0 ( p0 ) ) ; endmodule @@ -73920,7 +78322,7 @@ endmodule module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_1 ( pReset , prog_clk , frac_logic_in , frac_logic_cin , ccff_head , - frac_logic_out , frac_logic_cout , ccff_tail , p5 ) ; + frac_logic_out , frac_logic_cout , ccff_tail , p0 , p1 ) ; input [0:0] pReset ; input [0:0] prog_clk ; input [0:3] frac_logic_in ; @@ -73929,7 +78331,8 @@ input [0:0] ccff_head ; output [0:1] frac_logic_out ; output [0:0] frac_logic_cout ; output [0:0] ccff_tail ; -input p5 ; +input p0 ; +input p1 ; wire [0:0] direct_interc_5_out ; wire [0:0] direct_interc_7_out ; @@ -73965,12 +78368,12 @@ grid_clb_mux_1level_size2_4 mux_frac_logic_out_0 ( } ) , .sram ( mux_1level_size2_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_2 , SYNOPSYS_UNCONNECTED_3 } ) , - .out ( frac_logic_out[0] ) , .p5 ( p5 ) ) ; + .out ( frac_logic_out[0] ) , .p0 ( p0 ) ) ; grid_clb_mux_1level_size2_5 mux_frac_lut4_0_in_2 ( .in ( { frac_logic_cin[0] , frac_logic_in[2] } ) , .sram ( mux_1level_size2_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_4 , SYNOPSYS_UNCONNECTED_5 } ) , - .out ( mux_1level_size2_1_out ) , .p5 ( p5 ) ) ; + .out ( mux_1level_size2_1_out ) , .p1 ( p1 ) ) ; grid_clb_mux_1level_size2_mem_4 mem_frac_logic_out_0 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ) , @@ -73986,7 +78389,7 @@ module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_1 ( pReset , prog_clk , Test_en , fabric_in , fabric_reg_in , fabric_sc_in , fabric_cin , fabric_reset , fabric_clk , ccff_head , fabric_out , fabric_reg_out , fabric_sc_out , fabric_cout , ccff_tail , p_abuf0 , - p_abuf1 , p0 , p5 ) ; + p_abuf1 , p0 , p1 , p5 ) ; input [0:0] pReset ; input [0:0] prog_clk ; input [0:0] Test_en ; @@ -74005,6 +78408,7 @@ output [0:0] ccff_tail ; output p_abuf0 ; output p_abuf1 ; input p0 ; +input p1 ; input p5 ; wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ; @@ -74030,7 +78434,7 @@ grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ .frac_logic_cout ( { SYNOPSYS_UNCONNECTED_1 } ) , .ccff_tail ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) , - .p5 ( p5 ) ) ; + .p0 ( p0 ) , .p1 ( p1 ) ) ; grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_2 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0 ( .Test_en ( Test_en ) , .ff_D ( mux_1level_size2_0_out ) , .ff_DI ( fabric_sc_in ) , .ff_reset ( fabric_reset ) , @@ -74055,7 +78459,7 @@ grid_clb_mux_1level_tapbuf_size2_3 mux_fabric_out_1 ( } ) , .sram ( mux_1level_tapbuf_size2_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_4 , SYNOPSYS_UNCONNECTED_5 } ) , - .out ( fabric_out[1] ) , .p_abuf0 ( p_abuf1 ) , .p0 ( p0 ) ) ; + .out ( fabric_out[1] ) , .p_abuf0 ( p_abuf1 ) , .p5 ( p5 ) ) ; grid_clb_mux_1level_tapbuf_size2_mem_2 mem_fabric_out_0 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) , @@ -74074,7 +78478,7 @@ grid_clb_mux_1level_size2_6 mux_ff_0_D_0 ( fabric_reg_in[0] } ) , .sram ( mux_1level_size2_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_6 , SYNOPSYS_UNCONNECTED_7 } ) , - .out ( mux_1level_size2_0_out ) , .p0 ( p0 ) ) ; + .out ( mux_1level_size2_0_out ) , .p5 ( p5 ) ) ; grid_clb_mux_1level_size2_7 mux_ff_1_D_0 ( .in ( { logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] , @@ -74082,7 +78486,7 @@ grid_clb_mux_1level_size2_7 mux_ff_1_D_0 ( } ) , .sram ( mux_1level_size2_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_8 , SYNOPSYS_UNCONNECTED_9 } ) , - .out ( mux_1level_size2_1_out ) , .p0 ( p0 ) ) ; + .out ( mux_1level_size2_1_out ) , .p5 ( p5 ) ) ; grid_clb_mux_1level_size2_mem_6 mem_ff_0_D_0 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( mux_1level_tapbuf_size2_mem_1_ccff_tail ) , @@ -74097,7 +78501,7 @@ endmodule module grid_clb_logical_tile_clb_mode_default__fle_1 ( pReset , prog_clk , Test_en , fle_in , fle_reg_in , fle_sc_in , fle_cin , fle_reset , fle_clk , ccff_head , fle_out , fle_reg_out , fle_sc_out , fle_cout , - ccff_tail , p_abuf0 , p_abuf1 , p0 , p5 ) ; + ccff_tail , p_abuf0 , p_abuf1 , p0 , p1 , p5 ) ; input [0:0] pReset ; input [0:0] prog_clk ; input [0:0] Test_en ; @@ -74116,6 +78520,7 @@ output [0:0] ccff_tail ; output p_abuf0 ; output p_abuf1 ; input p0 ; +input p1 ; input p5 ; grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_1 logical_tile_clb_mode_default__fle_mode_physical__fabric_0 ( @@ -74128,7 +78533,7 @@ grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_1 logical_tile .fabric_reg_out ( fle_reg_out ) , .fabric_sc_out ( fle_sc_out ) , .fabric_cout ( { SYNOPSYS_UNCONNECTED_2 } ) , .ccff_tail ( ccff_tail ) , .p_abuf0 ( p_abuf0 ) , .p_abuf1 ( p_abuf1 ) , - .p0 ( p0 ) , .p5 ( p5 ) ) ; + .p0 ( p0 ) , .p1 ( p1 ) , .p5 ( p5 ) ) ; endmodule @@ -74165,14 +78570,14 @@ endmodule module grid_clb_mux_1level_basis_input3_mem3_3 ( in , mem , mem_inv , out , - p1 ) ; + p5 ) ; input [0:2] in ; input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; -input p1 ; +input p5 ; -scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p1 ) , +scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p5 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out[0] ) ) ; @@ -74195,12 +78600,12 @@ sky130_fd_sc_hd__buf_1 FTB_11__10 ( .A ( addr[1] ) , .X ( data[2] ) ) ; endmodule -module grid_clb_mux_1level_size2_3 ( in , sram , sram_inv , out , p1 ) ; +module grid_clb_mux_1level_size2_3 ( in , sram , sram_inv , out , p5 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; output [0:0] out ; -input p1 ; +input p5 ; wire [0:2] local_encoder2to3_0_data ; wire [0:2] local_encoder2to3_0_data_inv ; @@ -74215,19 +78620,19 @@ grid_clb_mux_1level_basis_input3_mem3_3 mux_l1_in_0_ ( .in ( { in[0] , in[1] , SYNOPSYS_UNCONNECTED_1 } ) , .mem ( local_encoder2to3_0_data ) , .mem_inv ( local_encoder2to3_0_data_inv ) , - .out ( mux_1level_basis_input3_mem3_0_out ) , .p1 ( p1 ) ) ; + .out ( mux_1level_basis_input3_mem3_0_out ) , .p5 ( p5 ) ) ; endmodule module grid_clb_mux_1level_basis_input3_mem3_2 ( in , mem , mem_inv , out , - p5 ) ; + p1 ) ; input [0:2] in ; input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; -input p5 ; +input p1 ; -scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p5 ) , +scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p1 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out[0] ) ) ; @@ -74250,12 +78655,12 @@ sky130_fd_sc_hd__buf_1 FTB_10__9 ( .A ( addr[1] ) , .X ( data[2] ) ) ; endmodule -module grid_clb_mux_1level_size2_2 ( in , sram , sram_inv , out , p5 ) ; +module grid_clb_mux_1level_size2_2 ( in , sram , sram_inv , out , p1 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; output [0:0] out ; -input p5 ; +input p1 ; wire [0:2] local_encoder2to3_0_data ; wire [0:2] local_encoder2to3_0_data_inv ; @@ -74270,7 +78675,7 @@ grid_clb_mux_1level_basis_input3_mem3_2 mux_l1_in_0_ ( .in ( { in[0] , in[1] , SYNOPSYS_UNCONNECTED_1 } ) , .mem ( local_encoder2to3_0_data ) , .mem_inv ( local_encoder2to3_0_data_inv ) , - .out ( mux_1level_basis_input3_mem3_0_out ) , .p5 ( p5 ) ) ; + .out ( mux_1level_basis_input3_mem3_0_out ) , .p1 ( p1 ) ) ; endmodule @@ -74358,22 +78763,22 @@ grid_clb_mux_1level_tapbuf_basis_input3_mem3_1 mux_l1_in_0_ ( .mem ( local_encoder2to3_0_data ) , .mem_inv ( local_encoder2to3_0_data_inv ) , .out ( mux_1level_tapbuf_basis_input3_mem3_0_out ) , .p1 ( p1 ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_136 ( +sky130_fd_sc_hd__inv_1 BINV_R_135 ( .A ( mux_1level_tapbuf_basis_input3_mem3_0_out[0] ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_137 ( +sky130_fd_sc_hd__inv_8 BINV_R_136 ( .A ( mux_1level_tapbuf_basis_input3_mem3_0_out[0] ) , .Y ( p_abuf0 ) ) ; endmodule module grid_clb_mux_1level_tapbuf_basis_input3_mem3_0 ( in , mem , mem_inv , - out , p4 ) ; + out , p1 ) ; input [0:2] in ; input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; -input p4 ; +input p1 ; -scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p4 ) , +scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p1 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out[0] ) ) ; @@ -74397,13 +78802,13 @@ endmodule module grid_clb_mux_1level_tapbuf_size2_0 ( in , sram , sram_inv , out , - p_abuf0 , p4 ) ; + p_abuf0 , p1 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; output [0:0] out ; output p_abuf0 ; -input p4 ; +input p1 ; wire [0:2] local_encoder2to3_0_data ; wire [0:2] local_encoder2to3_0_data_inv ; @@ -74416,10 +78821,10 @@ grid_clb_mux_1level_tapbuf_basis_input3_mem3_0 mux_l1_in_0_ ( .in ( { in[0] , in[1] , SYNOPSYS_UNCONNECTED_1 } ) , .mem ( local_encoder2to3_0_data ) , .mem_inv ( local_encoder2to3_0_data_inv ) , - .out ( mux_1level_tapbuf_basis_input3_mem3_0_out ) , .p4 ( p4 ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_133 ( + .out ( mux_1level_tapbuf_basis_input3_mem3_0_out ) , .p1 ( p1 ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_132 ( .A ( mux_1level_tapbuf_basis_input3_mem3_0_out[0] ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_134 ( +sky130_fd_sc_hd__inv_8 BINV_R_133 ( .A ( mux_1level_tapbuf_basis_input3_mem3_0_out[0] ) , .Y ( p_abuf0 ) ) ; endmodule @@ -74487,14 +78892,14 @@ endmodule module grid_clb_mux_1level_basis_input3_mem3_1 ( in , mem , mem_inv , out , - p4 ) ; + p2 ) ; input [0:2] in ; input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; -input p4 ; +input p2 ; -scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p4 ) , +scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p2 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out[0] ) ) ; @@ -74517,12 +78922,12 @@ sky130_fd_sc_hd__buf_1 FTB_3__2 ( .A ( addr[1] ) , .X ( data[2] ) ) ; endmodule -module grid_clb_mux_1level_size2_1 ( in , sram , sram_inv , out , p4 ) ; +module grid_clb_mux_1level_size2_1 ( in , sram , sram_inv , out , p2 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; output [0:0] out ; -input p4 ; +input p2 ; wire [0:2] local_encoder2to3_0_data ; wire [0:2] local_encoder2to3_0_data_inv ; @@ -74537,19 +78942,19 @@ grid_clb_mux_1level_basis_input3_mem3_1 mux_l1_in_0_ ( .in ( { in[0] , in[1] , SYNOPSYS_UNCONNECTED_1 } ) , .mem ( local_encoder2to3_0_data ) , .mem_inv ( local_encoder2to3_0_data_inv ) , - .out ( mux_1level_basis_input3_mem3_0_out ) , .p4 ( p4 ) ) ; + .out ( mux_1level_basis_input3_mem3_0_out ) , .p2 ( p2 ) ) ; endmodule module grid_clb_mux_1level_basis_input3_mem3_0 ( in , mem , mem_inv , out , - p4 ) ; + p2 ) ; input [0:2] in ; input [0:2] mem ; input [0:2] mem_inv ; output [0:0] out ; -input p4 ; +input p2 ; -scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p4 ) , +scs8hd_muxinv3_1 scs8hd_muxinv3_1_0 ( .Q1 ( in[0] ) , .Q3 ( p2 ) , .S0B ( mem_inv[0] ) , .S2B ( mem_inv[2] ) , .S0 ( mem[0] ) , .S2 ( mem[2] ) , .Q2 ( in[1] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out[0] ) ) ; @@ -74572,12 +78977,12 @@ sky130_fd_sc_hd__buf_1 FTB_2__1 ( .A ( addr[1] ) , .X ( data[2] ) ) ; endmodule -module grid_clb_mux_1level_size2_0 ( in , sram , sram_inv , out , p4 ) ; +module grid_clb_mux_1level_size2_0 ( in , sram , sram_inv , out , p2 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; output [0:0] out ; -input p4 ; +input p2 ; wire [0:2] local_encoder2to3_0_data ; wire [0:2] local_encoder2to3_0_data_inv ; @@ -74592,7 +78997,7 @@ grid_clb_mux_1level_basis_input3_mem3_0 mux_l1_in_0_ ( .in ( { in[0] , in[1] , SYNOPSYS_UNCONNECTED_1 } ) , .mem ( local_encoder2to3_0_data ) , .mem_inv ( local_encoder2to3_0_data_inv ) , - .out ( mux_1level_basis_input3_mem3_0_out ) , .p4 ( p4 ) ) ; + .out ( mux_1level_basis_input3_mem3_0_out ) , .p2 ( p2 ) ) ; endmodule @@ -74629,7 +79034,7 @@ input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:16] mem_out ; -sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ropt_net_252 ) , +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ropt_net_244 ) , .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; @@ -74664,20 +79069,20 @@ sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_15_ ( .D ( mem_out[14] ) , sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_16_ ( .D ( mem_out[15] ) , .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[16] ) ) ; sky130_fd_sc_hd__buf_1 FTB_1__0 ( .A ( mem_out[16] ) , .X ( ccff_tail[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1699 ( .A ( copt_net_242 ) , - .X ( copt_net_239 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1700 ( .A ( copt_net_239 ) , - .X ( copt_net_240 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1701 ( .A ( copt_net_244 ) , - .X ( copt_net_241 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1702 ( .A ( copt_net_243 ) , - .X ( copt_net_242 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1703 ( .A ( copt_net_241 ) , - .X ( copt_net_243 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1704 ( .A ( ccff_head[0] ) , - .X ( copt_net_244 ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 ropt_h_inst_1712 ( .A ( copt_net_240 ) , - .X ( ropt_net_252 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1589 ( .A ( ccff_head[0] ) , + .X ( copt_net_232 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1590 ( .A ( copt_net_232 ) , + .X ( copt_net_233 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1591 ( .A ( copt_net_233 ) , + .X ( copt_net_234 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1592 ( .A ( copt_net_234 ) , + .X ( copt_net_235 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1593 ( .A ( copt_net_237 ) , + .X ( copt_net_236 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1594 ( .A ( copt_net_235 ) , + .X ( copt_net_237 ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 ropt_h_inst_1601 ( .A ( copt_net_236 ) , + .X ( ropt_net_244 ) ) ; endmodule @@ -74823,7 +79228,7 @@ endmodule module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0 ( pReset , prog_clk , frac_logic_in , frac_logic_cin , ccff_head , - frac_logic_out , frac_logic_cout , ccff_tail , p4 ) ; + frac_logic_out , frac_logic_cout , ccff_tail , p2 ) ; input [0:0] pReset ; input [0:0] prog_clk ; input [0:3] frac_logic_in ; @@ -74832,7 +79237,7 @@ input [0:0] ccff_head ; output [0:1] frac_logic_out ; output [0:0] frac_logic_cout ; output [0:0] ccff_tail ; -input p4 ; +input p2 ; wire [0:0] direct_interc_5_out ; wire [0:0] direct_interc_7_out ; @@ -74868,12 +79273,12 @@ grid_clb_mux_1level_size2_0 mux_frac_logic_out_0 ( } ) , .sram ( mux_1level_size2_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_2 , SYNOPSYS_UNCONNECTED_3 } ) , - .out ( frac_logic_out[0] ) , .p4 ( p4 ) ) ; + .out ( frac_logic_out[0] ) , .p2 ( p2 ) ) ; grid_clb_mux_1level_size2_1 mux_frac_lut4_0_in_2 ( .in ( { frac_logic_cin[0] , frac_logic_in[2] } ) , .sram ( mux_1level_size2_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_4 , SYNOPSYS_UNCONNECTED_5 } ) , - .out ( mux_1level_size2_1_out ) , .p4 ( p4 ) ) ; + .out ( mux_1level_size2_1_out ) , .p2 ( p2 ) ) ; grid_clb_mux_1level_size2_mem_0 mem_frac_logic_out_0 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ) , @@ -74889,7 +79294,7 @@ module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_0 ( pReset , prog_clk , Test_en , fabric_in , fabric_reg_in , fabric_sc_in , fabric_cin , fabric_reset , fabric_clk , ccff_head , fabric_out , fabric_reg_out , fabric_sc_out , fabric_cout , ccff_tail , p_abuf0 , - p_abuf1 , p1 , p4 , p5 ) ; + p_abuf1 , p1 , p2 , p5 ) ; input [0:0] pReset ; input [0:0] prog_clk ; input [0:0] Test_en ; @@ -74908,7 +79313,7 @@ output [0:0] ccff_tail ; output p_abuf0 ; output p_abuf1 ; input p1 ; -input p4 ; +input p2 ; input p5 ; wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ; @@ -74934,7 +79339,7 @@ grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ .frac_logic_cout ( { SYNOPSYS_UNCONNECTED_1 } ) , .ccff_tail ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) , - .p4 ( p4 ) ) ; + .p2 ( p2 ) ) ; grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0 ( .Test_en ( Test_en ) , .ff_D ( mux_1level_size2_0_out ) , .ff_DI ( fabric_sc_in ) , .ff_reset ( fabric_reset ) , @@ -74952,7 +79357,7 @@ grid_clb_mux_1level_tapbuf_size2_0 mux_fabric_out_0 ( } ) , .sram ( mux_1level_tapbuf_size2_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_2 , SYNOPSYS_UNCONNECTED_3 } ) , - .out ( fabric_out[0] ) , .p_abuf0 ( p_abuf0 ) , .p4 ( p4 ) ) ; + .out ( fabric_out[0] ) , .p_abuf0 ( p_abuf0 ) , .p1 ( p1 ) ) ; grid_clb_mux_1level_tapbuf_size2_1 mux_fabric_out_1 ( .in ( { fabric_sc_out[0] , logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] @@ -74978,7 +79383,7 @@ grid_clb_mux_1level_size2_2 mux_ff_0_D_0 ( fabric_reg_in[0] } ) , .sram ( mux_1level_size2_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_6 , SYNOPSYS_UNCONNECTED_7 } ) , - .out ( mux_1level_size2_0_out ) , .p5 ( p5 ) ) ; + .out ( mux_1level_size2_0_out ) , .p1 ( p1 ) ) ; grid_clb_mux_1level_size2_3 mux_ff_1_D_0 ( .in ( { logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] , @@ -74986,7 +79391,7 @@ grid_clb_mux_1level_size2_3 mux_ff_1_D_0 ( } ) , .sram ( mux_1level_size2_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_8 , SYNOPSYS_UNCONNECTED_9 } ) , - .out ( mux_1level_size2_1_out ) , .p1 ( p1 ) ) ; + .out ( mux_1level_size2_1_out ) , .p5 ( p5 ) ) ; grid_clb_mux_1level_size2_mem_2 mem_ff_0_D_0 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( mux_1level_tapbuf_size2_mem_1_ccff_tail ) , @@ -75001,7 +79406,7 @@ endmodule module grid_clb_logical_tile_clb_mode_default__fle_0 ( pReset , prog_clk , Test_en , fle_in , fle_reg_in , fle_sc_in , fle_cin , fle_reset , fle_clk , ccff_head , fle_out , fle_reg_out , fle_sc_out , fle_cout , - ccff_tail , p_abuf0 , p_abuf1 , p1 , p4 , p5 ) ; + ccff_tail , p_abuf0 , p_abuf1 , p1 , p2 , p5 ) ; input [0:0] pReset ; input [0:0] prog_clk ; input [0:0] Test_en ; @@ -75020,7 +79425,7 @@ output [0:0] ccff_tail ; output p_abuf0 ; output p_abuf1 ; input p1 ; -input p4 ; +input p2 ; input p5 ; grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_0 logical_tile_clb_mode_default__fle_mode_physical__fabric_0 ( @@ -75033,7 +79438,7 @@ grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_0 logical_tile .fabric_reg_out ( fle_reg_out ) , .fabric_sc_out ( fle_sc_out ) , .fabric_cout ( { SYNOPSYS_UNCONNECTED_2 } ) , .ccff_tail ( ccff_tail ) , .p_abuf0 ( p_abuf0 ) , .p_abuf1 ( p_abuf1 ) , - .p1 ( p1 ) , .p4 ( p4 ) , .p5 ( p5 ) ) ; + .p1 ( p1 ) , .p2 ( p2 ) , .p5 ( p5 ) ) ; endmodule @@ -75136,7 +79541,7 @@ grid_clb_logical_tile_clb_mode_default__fle_0 logical_tile_clb_mode_default__fle .fle_sc_out ( logical_tile_clb_mode_default__fle_0_fle_sc_out ) , .fle_cout ( { SYNOPSYS_UNCONNECTED_2 } ) , .ccff_tail ( logical_tile_clb_mode_default__fle_0_ccff_tail ) , - .p_abuf0 ( p_abuf1 ) , .p_abuf1 ( p_abuf2 ) , .p1 ( p2 ) , .p4 ( p5 ) , + .p_abuf0 ( p_abuf1 ) , .p_abuf1 ( p_abuf2 ) , .p1 ( p2 ) , .p2 ( p3 ) , .p5 ( p6 ) ) ; grid_clb_logical_tile_clb_mode_default__fle_1 logical_tile_clb_mode_default__fle_1 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , @@ -75151,7 +79556,8 @@ grid_clb_logical_tile_clb_mode_default__fle_1 logical_tile_clb_mode_default__fle .fle_sc_out ( logical_tile_clb_mode_default__fle_1_fle_sc_out ) , .fle_cout ( { SYNOPSYS_UNCONNECTED_4 } ) , .ccff_tail ( logical_tile_clb_mode_default__fle_1_ccff_tail ) , - .p_abuf0 ( p_abuf3 ) , .p_abuf1 ( p_abuf4 ) , .p0 ( p0 ) , .p5 ( p6 ) ) ; + .p_abuf0 ( p_abuf3 ) , .p_abuf1 ( p_abuf4 ) , .p0 ( p0 ) , .p1 ( p2 ) , + .p5 ( p6 ) ) ; grid_clb_logical_tile_clb_mode_default__fle_2 logical_tile_clb_mode_default__fle_2 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , .fle_in ( { clb_I2[0] , clb_I2[1] , clb_I2i[0] , clb_I2i[1] } ) , @@ -75165,7 +79571,7 @@ grid_clb_logical_tile_clb_mode_default__fle_2 logical_tile_clb_mode_default__fle .fle_sc_out ( logical_tile_clb_mode_default__fle_2_fle_sc_out ) , .fle_cout ( { SYNOPSYS_UNCONNECTED_6 } ) , .ccff_tail ( logical_tile_clb_mode_default__fle_2_ccff_tail ) , - .p_abuf0 ( p_abuf5 ) , .p_abuf1 ( p_abuf6 ) , .p1 ( p2 ) , .p2 ( p3 ) ) ; + .p_abuf0 ( p_abuf5 ) , .p_abuf1 ( p_abuf6 ) , .p2 ( p3 ) , .p4 ( p5 ) ) ; grid_clb_logical_tile_clb_mode_default__fle_3 logical_tile_clb_mode_default__fle_3 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , .fle_in ( { clb_I3[0] , clb_I3[1] , clb_I3i[0] , clb_I3i[1] } ) , @@ -75179,7 +79585,7 @@ grid_clb_logical_tile_clb_mode_default__fle_3 logical_tile_clb_mode_default__fle .fle_sc_out ( logical_tile_clb_mode_default__fle_3_fle_sc_out ) , .fle_cout ( { SYNOPSYS_UNCONNECTED_8 } ) , .ccff_tail ( logical_tile_clb_mode_default__fle_3_ccff_tail ) , - .p_abuf0 ( p_abuf7 ) , .p_abuf1 ( p_abuf8 ) , .p0 ( p1 ) , .p2 ( p3 ) ) ; + .p_abuf0 ( p_abuf7 ) , .p_abuf1 ( p_abuf8 ) , .p0 ( p1 ) , .p6 ( p7 ) ) ; grid_clb_logical_tile_clb_mode_default__fle_4 logical_tile_clb_mode_default__fle_4 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , .fle_in ( { clb_I4[0] , clb_I4[1] , clb_I4i[0] , clb_I4i[1] } ) , @@ -75193,7 +79599,7 @@ grid_clb_logical_tile_clb_mode_default__fle_4 logical_tile_clb_mode_default__fle .fle_sc_out ( logical_tile_clb_mode_default__fle_4_fle_sc_out ) , .fle_cout ( { SYNOPSYS_UNCONNECTED_10 } ) , .ccff_tail ( logical_tile_clb_mode_default__fle_4_ccff_tail ) , - .p_abuf0 ( p_abuf9 ) , .p_abuf1 ( p_abuf10 ) , .p0 ( p1 ) ) ; + .p_abuf0 ( p_abuf9 ) , .p_abuf1 ( p_abuf10 ) , .p6 ( p7 ) ) ; grid_clb_logical_tile_clb_mode_default__fle_5 logical_tile_clb_mode_default__fle_5 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , .fle_in ( { clb_I5[0] , clb_I5[1] , clb_I5i[0] , clb_I5i[1] } ) , @@ -75207,7 +79613,8 @@ grid_clb_logical_tile_clb_mode_default__fle_5 logical_tile_clb_mode_default__fle .fle_sc_out ( logical_tile_clb_mode_default__fle_5_fle_sc_out ) , .fle_cout ( { SYNOPSYS_UNCONNECTED_12 } ) , .ccff_tail ( logical_tile_clb_mode_default__fle_5_ccff_tail ) , - .p_abuf0 ( p_abuf11 ) , .p_abuf1 ( p_abuf12 ) , .p6 ( p7 ) ) ; + .p_abuf0 ( p_abuf11 ) , .p_abuf1 ( p_abuf12 ) , .p0 ( p1 ) , .p3 ( p4 ) , + .p6 ( p7 ) ) ; grid_clb_logical_tile_clb_mode_default__fle_6 logical_tile_clb_mode_default__fle_6 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , .fle_in ( { clb_I6[0] , clb_I6[1] , clb_I6i[0] , clb_I6i[1] } ) , @@ -75221,7 +79628,7 @@ grid_clb_logical_tile_clb_mode_default__fle_6 logical_tile_clb_mode_default__fle .fle_sc_out ( logical_tile_clb_mode_default__fle_6_fle_sc_out ) , .fle_cout ( { SYNOPSYS_UNCONNECTED_14 } ) , .ccff_tail ( logical_tile_clb_mode_default__fle_6_ccff_tail ) , - .p_abuf0 ( p_abuf13 ) , .p_abuf1 ( p_abuf14 ) , .p3 ( p4 ) , .p6 ( p7 ) ) ; + .p_abuf0 ( p_abuf13 ) , .p_abuf1 ( p_abuf14 ) , .p0 ( p1 ) , .p3 ( p4 ) ) ; grid_clb_logical_tile_clb_mode_default__fle logical_tile_clb_mode_default__fle_7 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , .fle_in ( { clb_I7[0] , clb_I7[1] , clb_I7i[0] , clb_I7i[1] } ) , @@ -75233,7 +79640,7 @@ grid_clb_logical_tile_clb_mode_default__fle logical_tile_clb_mode_default__fle_7 .fle_out ( { clb_O[15] , clb_O[14] } ) , .fle_reg_out ( clb_reg_out ) , .fle_sc_out ( clb_sc_out ) , .fle_cout ( clb_cout ) , .ccff_tail ( ccff_tail ) , .p_abuf0 ( p_abuf0 ) , - .p_abuf1 ( p_abuf15 ) , .p_abuf2 ( p_abuf16 ) , .p0 ( p0 ) , .p3 ( p4 ) ) ; + .p_abuf1 ( p_abuf15 ) , .p_abuf2 ( p_abuf16 ) , .p0 ( p1 ) , .p3 ( p4 ) ) ; endmodule @@ -75382,7 +79789,10 @@ output prog_clk_0_N_out ; input clk_0_N_in ; input clk_0_S_in ; -wire p_abuf12 ; +wire p_abuf10 ; +wire p_abuf14 ; +wire p_abuf16 ; +wire p_abuf0 ; wire prog_clk_0 ; wire [0:0] prog_clk ; wire [0:0] clk ; @@ -75437,16 +79847,17 @@ grid_clb_logical_tile_clb_mode_clb_ logical_tile_clb_mode_clb__0 ( .clb_sc_in ( { SC_IN_BOT } ) , .clb_cin ( { SYNOPSYS_UNCONNECTED_1 } ) , .clb_reset ( Reset ) , .clb_clk ( clk ) , .ccff_head ( ccff_head ) , - .clb_O ( { aps_rename_507_ , aps_rename_508_ , aps_rename_509_ , - aps_rename_510_ , aps_rename_511_ , aps_rename_512_ , - aps_rename_513_ , aps_rename_514_ , aps_rename_515_ , - aps_rename_516_ , right_width_0_height_0__pin_46_lower[0] , - aps_rename_518_ , aps_rename_519_ , aps_rename_520_ , - aps_rename_521_ , aps_rename_522_ } ) , + .clb_O ( { aps_rename_506_ , aps_rename_507_ , aps_rename_508_ , + aps_rename_509_ , aps_rename_510_ , aps_rename_511_ , + aps_rename_512_ , aps_rename_513_ , + right_width_0_height_0__pin_44_lower[0] , aps_rename_515_ , + aps_rename_516_ , aps_rename_517_ , + right_width_0_height_0__pin_48_lower[0] , aps_rename_519_ , + right_width_0_height_0__pin_50_lower[0] , aps_rename_521_ } ) , .clb_reg_out ( bottom_width_0_height_0__pin_52_ ) , - .clb_sc_out ( { aps_rename_523_ } ) , + .clb_sc_out ( { SC_OUT_BOT } ) , .clb_cout ( bottom_width_0_height_0__pin_54_ ) , - .ccff_tail ( ccff_tail ) , .p_abuf0 ( SC_OUT_BOT ) , + .ccff_tail ( ccff_tail ) , .p_abuf0 ( p_abuf0 ) , .p_abuf1 ( top_width_0_height_0__pin_37_lower[0] ) , .p_abuf2 ( top_width_0_height_0__pin_36_lower[0] ) , .p_abuf3 ( top_width_0_height_0__pin_39_lower[0] ) , @@ -75456,106 +79867,94 @@ grid_clb_logical_tile_clb_mode_clb_ logical_tile_clb_mode_clb__0 ( .p_abuf7 ( top_width_0_height_0__pin_43_lower[0] ) , .p_abuf8 ( top_width_0_height_0__pin_42_lower[0] ) , .p_abuf9 ( right_width_0_height_0__pin_45_lower[0] ) , - .p_abuf10 ( right_width_0_height_0__pin_44_lower[0] ) , + .p_abuf10 ( p_abuf10 ) , .p_abuf11 ( right_width_0_height_0__pin_47_lower[0] ) , - .p_abuf12 ( p_abuf12 ) , + .p_abuf12 ( right_width_0_height_0__pin_46_lower[0] ) , .p_abuf13 ( right_width_0_height_0__pin_49_lower[0] ) , - .p_abuf14 ( right_width_0_height_0__pin_48_lower[0] ) , + .p_abuf14 ( p_abuf14 ) , .p_abuf15 ( right_width_0_height_0__pin_51_lower[0] ) , - .p_abuf16 ( right_width_0_height_0__pin_50_lower[0] ) , - .p0 ( optlc_net_227 ) , .p1 ( optlc_net_228 ) , .p2 ( optlc_net_229 ) , - .p3 ( optlc_net_230 ) , .p4 ( optlc_net_231 ) , .p5 ( optlc_net_232 ) , - .p6 ( optlc_net_233 ) , .p7 ( optlc_net_234 ) ) ; + .p_abuf16 ( p_abuf16 ) , .p0 ( optlc_net_220 ) , .p1 ( optlc_net_221 ) , + .p2 ( optlc_net_222 ) , .p3 ( optlc_net_223 ) , .p4 ( optlc_net_224 ) , + .p5 ( optlc_net_225 ) , .p6 ( optlc_net_226 ) , .p7 ( optlc_net_227 ) ) ; sky130_fd_sc_hd__buf_2 Test_en_FTB00 ( .A ( Test_en_W_in ) , .X ( Test_en[0] ) ) ; -sky130_fd_sc_hd__buf_1 Test_en_W_FTB01 ( .A ( Test_en_W_in ) , - .X ( net_net_181 ) ) ; -sky130_fd_sc_hd__buf_1 Test_en_E_FTB01 ( .A ( Test_en_W_in ) , - .X ( net_net_182 ) ) ; +sky130_fd_sc_hd__bufbuf_16 Test_en_W_FTB01 ( .A ( Test_en_W_in ) , + .X ( Test_en_W_out ) ) ; +sky130_fd_sc_hd__bufbuf_16 Test_en_E_FTB01 ( .A ( Test_en_W_in ) , + .X ( Test_en_E_out ) ) ; sky130_fd_sc_hd__buf_8 pReset_FTB00 ( .A ( pReset_N_in ) , .X ( pReset[0] ) ) ; sky130_fd_sc_hd__buf_4 Reset_FTB00 ( .A ( Reset_W_in ) , .X ( Reset[0] ) ) ; -sky130_fd_sc_hd__buf_1 Reset_W_FTB01 ( .A ( Reset_W_in ) , - .X ( aps_rename_524_ ) ) ; -sky130_fd_sc_hd__buf_1 Reset_E_FTB01 ( .A ( Reset_W_in ) , - .X ( aps_rename_525_ ) ) ; +sky130_fd_sc_hd__bufbuf_16 Reset_W_FTB01 ( .A ( Reset_W_in ) , + .X ( Reset_W_out ) ) ; +sky130_fd_sc_hd__bufbuf_16 Reset_E_FTB01 ( .A ( Reset_W_in ) , + .X ( Reset_E_out ) ) ; sky130_fd_sc_hd__buf_6 prog_clk_0_FTB00 ( .A ( prog_clk_0_S_in ) , .X ( prog_clk_0 ) ) ; -sky130_fd_sc_hd__clkbuf_1 prog_clk_0_S_FTB01 ( .A ( prog_clk_0_S_in ) , - .X ( ctsbuf_net_1235 ) ) ; +sky130_fd_sc_hd__buf_4 prog_clk_0_S_FTB01 ( .A ( prog_clk_0_S_in ) , + .X ( ctsbuf_net_1228 ) ) ; sky130_fd_sc_hd__clkbuf_1 prog_clk_0_E_FTB01 ( .A ( prog_clk_0_S_in ) , - .X ( ctsbuf_net_2236 ) ) ; + .X ( ctsbuf_net_2229 ) ) ; sky130_fd_sc_hd__clkbuf_1 prog_clk_0_W_FTB01 ( .A ( prog_clk_0_S_in ) , - .X ( ctsbuf_net_3237 ) ) ; -sky130_fd_sc_hd__buf_4 prog_clk_0_N_FTB01 ( .A ( prog_clk_0_S_in ) , - .X ( ctsbuf_net_4238 ) ) ; + .X ( ctsbuf_net_3230 ) ) ; +sky130_fd_sc_hd__clkbuf_1 prog_clk_0_N_FTB01 ( .A ( prog_clk_0_S_in ) , + .X ( ctsbuf_net_4231 ) ) ; sky130_fd_sc_hd__buf_1 clk_0_FTB00 ( .A ( clk_0_S_in ) , .X ( clk[0] ) ) ; -sky130_fd_sc_hd__buf_6 FTB_113__112 ( .A ( aps_rename_507_ ) , +sky130_fd_sc_hd__buf_6 FTB_113__112 ( .A ( aps_rename_506_ ) , .X ( top_width_0_height_0__pin_36_upper[0] ) ) ; -sky130_fd_sc_hd__buf_6 FTB_114__113 ( .A ( aps_rename_508_ ) , +sky130_fd_sc_hd__buf_6 FTB_114__113 ( .A ( aps_rename_507_ ) , .X ( top_width_0_height_0__pin_37_upper[0] ) ) ; -sky130_fd_sc_hd__buf_6 FTB_115__114 ( .A ( aps_rename_509_ ) , +sky130_fd_sc_hd__buf_6 FTB_115__114 ( .A ( aps_rename_508_ ) , .X ( top_width_0_height_0__pin_38_upper[0] ) ) ; -sky130_fd_sc_hd__buf_6 FTB_116__115 ( .A ( aps_rename_510_ ) , +sky130_fd_sc_hd__buf_6 FTB_116__115 ( .A ( aps_rename_509_ ) , .X ( top_width_0_height_0__pin_39_upper[0] ) ) ; -sky130_fd_sc_hd__buf_6 FTB_117__116 ( .A ( aps_rename_511_ ) , +sky130_fd_sc_hd__buf_6 FTB_117__116 ( .A ( aps_rename_510_ ) , .X ( top_width_0_height_0__pin_40_upper[0] ) ) ; -sky130_fd_sc_hd__buf_6 FTB_118__117 ( .A ( aps_rename_512_ ) , +sky130_fd_sc_hd__buf_6 FTB_118__117 ( .A ( aps_rename_511_ ) , .X ( top_width_0_height_0__pin_41_upper[0] ) ) ; -sky130_fd_sc_hd__buf_6 FTB_119__118 ( .A ( aps_rename_513_ ) , +sky130_fd_sc_hd__buf_6 FTB_119__118 ( .A ( aps_rename_512_ ) , .X ( top_width_0_height_0__pin_42_upper[0] ) ) ; -sky130_fd_sc_hd__buf_6 FTB_120__119 ( .A ( aps_rename_514_ ) , +sky130_fd_sc_hd__buf_6 FTB_120__119 ( .A ( aps_rename_513_ ) , .X ( top_width_0_height_0__pin_43_upper[0] ) ) ; -sky130_fd_sc_hd__buf_6 FTB_121__120 ( .A ( aps_rename_515_ ) , +sky130_fd_sc_hd__buf_6 FTB_121__120 ( .A ( p_abuf10 ) , .X ( right_width_0_height_0__pin_44_upper[0] ) ) ; -sky130_fd_sc_hd__buf_6 FTB_122__121 ( .A ( aps_rename_516_ ) , +sky130_fd_sc_hd__buf_6 FTB_122__121 ( .A ( aps_rename_515_ ) , .X ( right_width_0_height_0__pin_45_upper[0] ) ) ; -sky130_fd_sc_hd__buf_6 FTB_123__122 ( .A ( p_abuf12 ) , +sky130_fd_sc_hd__buf_6 FTB_123__122 ( .A ( aps_rename_516_ ) , .X ( right_width_0_height_0__pin_46_upper[0] ) ) ; -sky130_fd_sc_hd__buf_6 FTB_124__123 ( .A ( aps_rename_518_ ) , +sky130_fd_sc_hd__buf_6 FTB_124__123 ( .A ( aps_rename_517_ ) , .X ( right_width_0_height_0__pin_47_upper[0] ) ) ; -sky130_fd_sc_hd__buf_6 FTB_125__124 ( .A ( aps_rename_519_ ) , +sky130_fd_sc_hd__buf_6 FTB_125__124 ( .A ( p_abuf14 ) , .X ( right_width_0_height_0__pin_48_upper[0] ) ) ; -sky130_fd_sc_hd__buf_6 FTB_126__125 ( .A ( aps_rename_520_ ) , +sky130_fd_sc_hd__buf_6 FTB_126__125 ( .A ( aps_rename_519_ ) , .X ( right_width_0_height_0__pin_49_upper[0] ) ) ; -sky130_fd_sc_hd__buf_6 FTB_127__126 ( .A ( aps_rename_521_ ) , +sky130_fd_sc_hd__buf_6 FTB_127__126 ( .A ( p_abuf16 ) , .X ( right_width_0_height_0__pin_50_upper[0] ) ) ; -sky130_fd_sc_hd__buf_6 FTB_128__127 ( .A ( aps_rename_522_ ) , +sky130_fd_sc_hd__buf_6 FTB_128__127 ( .A ( aps_rename_521_ ) , .X ( right_width_0_height_0__pin_51_upper[0] ) ) ; -sky130_fd_sc_hd__buf_6 FTB_129__128 ( .A ( aps_rename_523_ ) , - .X ( SC_OUT_TOP ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_181 ( .A ( net_net_181 ) , - .X ( Test_en_W_out ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_182 ( .A ( net_net_182 ) , - .X ( Test_en_E_out ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_183 ( .A ( BUF_net_184 ) , .Y ( Reset_W_out ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_184 ( .A ( aps_rename_524_ ) , - .Y ( BUF_net_184 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_185 ( .A ( BUF_net_186 ) , .Y ( Reset_E_out ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_186 ( .A ( aps_rename_525_ ) , - .Y ( BUF_net_186 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_189 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , +sky130_fd_sc_hd__buf_6 FTB_129__128 ( .A ( p_abuf0 ) , .X ( SC_OUT_TOP ) ) ; +sky130_fd_sc_hd__conb_1 optlc_182 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , + .HI ( optlc_net_220 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_184 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , + .HI ( optlc_net_221 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_186 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , + .HI ( optlc_net_222 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_188 ( .LO ( SYNOPSYS_UNCONNECTED_5 ) , + .HI ( optlc_net_223 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_190 ( .LO ( SYNOPSYS_UNCONNECTED_6 ) , + .HI ( optlc_net_224 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_192 ( .LO ( SYNOPSYS_UNCONNECTED_7 ) , + .HI ( optlc_net_225 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_194 ( .LO ( SYNOPSYS_UNCONNECTED_8 ) , + .HI ( optlc_net_226 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_196 ( .LO ( SYNOPSYS_UNCONNECTED_9 ) , .HI ( optlc_net_227 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_191 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , - .HI ( optlc_net_228 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_193 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , - .HI ( optlc_net_229 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_195 ( .LO ( SYNOPSYS_UNCONNECTED_5 ) , - .HI ( optlc_net_230 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_197 ( .LO ( SYNOPSYS_UNCONNECTED_6 ) , - .HI ( optlc_net_231 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_199 ( .LO ( SYNOPSYS_UNCONNECTED_7 ) , - .HI ( optlc_net_232 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_201 ( .LO ( SYNOPSYS_UNCONNECTED_8 ) , - .HI ( optlc_net_233 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_203 ( .LO ( SYNOPSYS_UNCONNECTED_9 ) , - .HI ( optlc_net_234 ) ) ; -sky130_fd_sc_hd__buf_6 cts_buf_4181396 ( .A ( ctsbuf_net_1235 ) , +sky130_fd_sc_hd__buf_6 cts_buf_4181389 ( .A ( ctsbuf_net_1228 ) , .X ( prog_clk_0_S_out ) ) ; -sky130_fd_sc_hd__buf_6 cts_buf_4231401 ( .A ( ctsbuf_net_2236 ) , +sky130_fd_sc_hd__clkbuf_8 cts_buf_4231394 ( .A ( ctsbuf_net_2229 ) , .X ( prog_clk_0_E_out ) ) ; -sky130_fd_sc_hd__buf_6 cts_buf_4281406 ( .A ( ctsbuf_net_3237 ) , +sky130_fd_sc_hd__buf_6 cts_buf_4281399 ( .A ( ctsbuf_net_3230 ) , .X ( prog_clk_0_W_out ) ) ; -sky130_fd_sc_hd__buf_6 cts_buf_4331411 ( .A ( ctsbuf_net_4238 ) , +sky130_fd_sc_hd__buf_6 cts_buf_4331404 ( .A ( ctsbuf_net_4231 ) , .X ( prog_clk_0_N_out ) ) ; endmodule @@ -75940,7 +80339,19 @@ module fpga_core ( pReset , prog_clk , Test_en , IO_ISOL_N , clk , Reset , p3480 , p3481 , p3482 , p3483 , p3484 , p3485 , p3486 , p3487 , p3488 , p3489 , p3490 , p3491 , p3492 , p3493 , p3494 , p3495 , p3496 , p3497 , p3498 , p3499 , p3500 , p3501 , p3502 , p3503 , p3504 , p3505 , p3506 , - p3507 , p3508 , p3509 ) ; + p3507 , p3508 , p3509 , p3510 , p3511 , p3512 , p3513 , p3514 , p3515 , + p3516 , p3517 , p3518 , p3519 , p3520 , p3521 , p3522 , p3523 , p3524 , + p3525 , p3526 , p3527 , p3528 , p3529 , p3530 , p3531 , p3532 , p3533 , + p3534 , p3535 , p3536 , p3537 , p3538 , p3539 , p3540 , p3541 , p3542 , + p3543 , p3544 , p3545 , p3546 , p3547 , p3548 , p3549 , p3550 , p3551 , + p3552 , p3553 , p3554 , p3555 , p3556 , p3557 , p3558 , p3559 , p3560 , + p3561 , p3562 , p3563 , p3564 , p3565 , p3566 , p3567 , p3568 , p3569 , + p3570 , p3571 , p3572 , p3573 , p3574 , p3575 , p3576 , p3577 , p3578 , + p3579 , p3580 , p3581 , p3582 , p3583 , p3584 , p3585 , p3586 , p3587 , + p3588 , p3589 , p3590 , p3591 , p3592 , p3593 , p3594 , p3595 , p3596 , + p3597 , p3598 , p3599 , p3600 , p3601 , p3602 , p3603 , p3604 , p3605 , + p3606 , p3607 , p3608 , p3609 , p3610 , p3611 , p3612 , p3613 , p3614 , + p3615 , p3616 , p3617 , p3618 , p3619 , p3620 ) ; input [0:0] pReset ; input [0:0] prog_clk ; input [0:0] Test_en ; @@ -79465,6 +83876,117 @@ input p3506 ; input p3507 ; input p3508 ; input p3509 ; +input p3510 ; +input p3511 ; +input p3512 ; +input p3513 ; +input p3514 ; +input p3515 ; +input p3516 ; +input p3517 ; +input p3518 ; +input p3519 ; +input p3520 ; +input p3521 ; +input p3522 ; +input p3523 ; +input p3524 ; +input p3525 ; +input p3526 ; +input p3527 ; +input p3528 ; +input p3529 ; +input p3530 ; +input p3531 ; +input p3532 ; +input p3533 ; +input p3534 ; +input p3535 ; +input p3536 ; +input p3537 ; +input p3538 ; +input p3539 ; +input p3540 ; +input p3541 ; +input p3542 ; +input p3543 ; +input p3544 ; +input p3545 ; +input p3546 ; +input p3547 ; +input p3548 ; +input p3549 ; +input p3550 ; +input p3551 ; +input p3552 ; +input p3553 ; +input p3554 ; +input p3555 ; +input p3556 ; +input p3557 ; +input p3558 ; +input p3559 ; +input p3560 ; +input p3561 ; +input p3562 ; +input p3563 ; +input p3564 ; +input p3565 ; +input p3566 ; +input p3567 ; +input p3568 ; +input p3569 ; +input p3570 ; +input p3571 ; +input p3572 ; +input p3573 ; +input p3574 ; +input p3575 ; +input p3576 ; +input p3577 ; +input p3578 ; +input p3579 ; +input p3580 ; +input p3581 ; +input p3582 ; +input p3583 ; +input p3584 ; +input p3585 ; +input p3586 ; +input p3587 ; +input p3588 ; +input p3589 ; +input p3590 ; +input p3591 ; +input p3592 ; +input p3593 ; +input p3594 ; +input p3595 ; +input p3596 ; +input p3597 ; +input p3598 ; +input p3599 ; +input p3600 ; +input p3601 ; +input p3602 ; +input p3603 ; +input p3604 ; +input p3605 ; +input p3606 ; +input p3607 ; +input p3608 ; +input p3609 ; +input p3610 ; +input p3611 ; +input p3612 ; +input p3613 ; +input p3614 ; +input p3615 ; +input p3616 ; +input p3617 ; +input p3618 ; +input p3619 ; +input p3620 ; wire [0:0] cbx_1__0__0_bottom_grid_pin_0_ ; wire [0:0] cbx_1__0__0_bottom_grid_pin_10_ ; @@ -105360,16 +109882,16 @@ sb_1__0_ sb_1__0_ ( .chanx_right_out ( sb_1__0__0_chanx_right_out ) , .chanx_left_out ( sb_1__0__0_chanx_left_out ) , .ccff_tail ( sb_1__0__0_ccff_tail ) , .SC_IN_TOP ( scff_Wires[26] ) , - .SC_OUT_TOP ( scff_Wires[27] ) , .Test_en_S_in ( p829 ) , + .SC_OUT_TOP ( scff_Wires[27] ) , .Test_en_S_in ( p1352 ) , .Test_en_N_out ( SYNOPSYS_UNCONNECTED_2055 ) , .pReset_S_in ( SYNOPSYS_UNCONNECTED_2056 ) , .pReset_E_in ( pResetWires[28] ) , .pReset_W_in ( SYNOPSYS_UNCONNECTED_2057 ) , .pReset_N_out ( pResetWires[27] ) , .pReset_W_out ( pResetWires[26] ) , - .pReset_E_out ( SYNOPSYS_UNCONNECTED_2058 ) , .Reset_S_in ( p829 ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_2058 ) , .Reset_S_in ( p1352 ) , .Reset_N_out ( SYNOPSYS_UNCONNECTED_2059 ) , - .prog_clk_0_N_in ( prog_clk_0_wires[2] ) , .prog_clk_3_S_in ( p829 ) , - .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_2060 ) , .clk_3_S_in ( p829 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[2] ) , .prog_clk_3_S_in ( p1352 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_2060 ) , .clk_3_S_in ( p1352 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_2061 ) ) ; sb_1__0_ sb_2__0_ ( .pReset ( { SYNOPSYS_UNCONNECTED_2062 } ) , @@ -105406,17 +109928,17 @@ sb_1__0_ sb_2__0_ ( .chany_top_out ( sb_1__0__1_chany_top_out ) , .chanx_right_out ( sb_1__0__1_chanx_right_out ) , .chanx_left_out ( sb_1__0__1_chanx_left_out ) , - .ccff_tail ( sb_1__0__1_ccff_tail ) , .SC_IN_TOP ( p1229 ) , - .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_2063 ) , .Test_en_S_in ( p753 ) , + .ccff_tail ( sb_1__0__1_ccff_tail ) , .SC_IN_TOP ( p1155 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_2063 ) , .Test_en_S_in ( p1142 ) , .Test_en_N_out ( SYNOPSYS_UNCONNECTED_2064 ) , .pReset_S_in ( SYNOPSYS_UNCONNECTED_2065 ) , .pReset_E_in ( pResetWires[31] ) , .pReset_W_in ( SYNOPSYS_UNCONNECTED_2066 ) , .pReset_N_out ( pResetWires[30] ) , .pReset_W_out ( pResetWires[29] ) , - .pReset_E_out ( SYNOPSYS_UNCONNECTED_2067 ) , .Reset_S_in ( p753 ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_2067 ) , .Reset_S_in ( p1142 ) , .Reset_N_out ( SYNOPSYS_UNCONNECTED_2068 ) , - .prog_clk_0_N_in ( prog_clk_0_wires[65] ) , .prog_clk_3_S_in ( p753 ) , - .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_2069 ) , .clk_3_S_in ( p753 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[65] ) , .prog_clk_3_S_in ( p1142 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_2069 ) , .clk_3_S_in ( p1142 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_2070 ) ) ; sb_1__0_ sb_3__0_ ( .pReset ( { SYNOPSYS_UNCONNECTED_2071 } ) , @@ -105454,16 +109976,16 @@ sb_1__0_ sb_3__0_ ( .chanx_right_out ( sb_1__0__2_chanx_right_out ) , .chanx_left_out ( sb_1__0__2_chanx_left_out ) , .ccff_tail ( sb_1__0__2_ccff_tail ) , .SC_IN_TOP ( scff_Wires[79] ) , - .SC_OUT_TOP ( scff_Wires[80] ) , .Test_en_S_in ( p1276 ) , + .SC_OUT_TOP ( scff_Wires[80] ) , .Test_en_S_in ( p1149 ) , .Test_en_N_out ( SYNOPSYS_UNCONNECTED_2072 ) , .pReset_S_in ( SYNOPSYS_UNCONNECTED_2073 ) , .pReset_E_in ( pResetWires[34] ) , .pReset_W_in ( SYNOPSYS_UNCONNECTED_2074 ) , .pReset_N_out ( pResetWires[33] ) , .pReset_W_out ( pResetWires[32] ) , - .pReset_E_out ( SYNOPSYS_UNCONNECTED_2075 ) , .Reset_S_in ( p1276 ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_2075 ) , .Reset_S_in ( p1149 ) , .Reset_N_out ( SYNOPSYS_UNCONNECTED_2076 ) , - .prog_clk_0_N_in ( prog_clk_0_wires[103] ) , .prog_clk_3_S_in ( p1276 ) , - .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_2077 ) , .clk_3_S_in ( p1276 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[103] ) , .prog_clk_3_S_in ( p1149 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_2077 ) , .clk_3_S_in ( p1149 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_2078 ) ) ; sb_1__0_ sb_4__0_ ( .pReset ( { SYNOPSYS_UNCONNECTED_2079 } ) , @@ -105500,17 +110022,17 @@ sb_1__0_ sb_4__0_ ( .chany_top_out ( sb_1__0__3_chany_top_out ) , .chanx_right_out ( sb_1__0__3_chanx_right_out ) , .chanx_left_out ( sb_1__0__3_chanx_left_out ) , - .ccff_tail ( sb_1__0__3_ccff_tail ) , .SC_IN_TOP ( p1395 ) , - .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_2080 ) , .Test_en_S_in ( p1329 ) , + .ccff_tail ( sb_1__0__3_ccff_tail ) , .SC_IN_TOP ( p1309 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_2080 ) , .Test_en_S_in ( p1251 ) , .Test_en_N_out ( SYNOPSYS_UNCONNECTED_2081 ) , .pReset_S_in ( SYNOPSYS_UNCONNECTED_2082 ) , .pReset_E_in ( pResetWires[37] ) , .pReset_W_in ( SYNOPSYS_UNCONNECTED_2083 ) , .pReset_N_out ( pResetWires[36] ) , .pReset_W_out ( pResetWires[35] ) , - .pReset_E_out ( SYNOPSYS_UNCONNECTED_2084 ) , .Reset_S_in ( p1329 ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_2084 ) , .Reset_S_in ( p1251 ) , .Reset_N_out ( SYNOPSYS_UNCONNECTED_2085 ) , - .prog_clk_0_N_in ( prog_clk_0_wires[141] ) , .prog_clk_3_S_in ( p1329 ) , - .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_2086 ) , .clk_3_S_in ( p1329 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[141] ) , .prog_clk_3_S_in ( p1251 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_2086 ) , .clk_3_S_in ( p1251 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_2087 ) ) ; sb_1__0_ sb_5__0_ ( .pReset ( { SYNOPSYS_UNCONNECTED_2088 } ) , @@ -105548,16 +110070,16 @@ sb_1__0_ sb_5__0_ ( .chanx_right_out ( sb_1__0__4_chanx_right_out ) , .chanx_left_out ( sb_1__0__4_chanx_left_out ) , .ccff_tail ( sb_1__0__4_ccff_tail ) , .SC_IN_TOP ( scff_Wires[132] ) , - .SC_OUT_TOP ( scff_Wires[133] ) , .Test_en_S_in ( p1210 ) , + .SC_OUT_TOP ( scff_Wires[133] ) , .Test_en_S_in ( p1141 ) , .Test_en_N_out ( SYNOPSYS_UNCONNECTED_2089 ) , .pReset_S_in ( SYNOPSYS_UNCONNECTED_2090 ) , .pReset_E_in ( pResetWires[40] ) , .pReset_W_in ( SYNOPSYS_UNCONNECTED_2091 ) , .pReset_N_out ( pResetWires[39] ) , .pReset_W_out ( pResetWires[38] ) , - .pReset_E_out ( SYNOPSYS_UNCONNECTED_2092 ) , .Reset_S_in ( p1210 ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_2092 ) , .Reset_S_in ( p1141 ) , .Reset_N_out ( SYNOPSYS_UNCONNECTED_2093 ) , - .prog_clk_0_N_in ( prog_clk_0_wires[179] ) , .prog_clk_3_S_in ( p1210 ) , - .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_2094 ) , .clk_3_S_in ( p1210 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[179] ) , .prog_clk_3_S_in ( p1481 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_2094 ) , .clk_3_S_in ( p1141 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_2095 ) ) ; sb_1__0_ sb_6__0_ ( .pReset ( { SYNOPSYS_UNCONNECTED_2096 } ) , @@ -105594,7 +110116,7 @@ sb_1__0_ sb_6__0_ ( .chany_top_out ( sb_1__0__5_chany_top_out ) , .chanx_right_out ( sb_1__0__5_chanx_right_out ) , .chanx_left_out ( sb_1__0__5_chanx_left_out ) , - .ccff_tail ( sb_1__0__5_ccff_tail ) , .SC_IN_TOP ( p1330 ) , + .ccff_tail ( sb_1__0__5_ccff_tail ) , .SC_IN_TOP ( p1313 ) , .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_2097 ) , .Test_en_S_in ( Test_en[0] ) , .Test_en_N_out ( Test_enWires[1] ) , .pReset_S_in ( pReset[0] ) , .pReset_E_in ( SYNOPSYS_UNCONNECTED_2098 ) , @@ -105642,16 +110164,16 @@ sb_1__0_ sb_7__0_ ( .chanx_right_out ( sb_1__0__6_chanx_right_out ) , .chanx_left_out ( sb_1__0__6_chanx_left_out ) , .ccff_tail ( sb_1__0__6_ccff_tail ) , .SC_IN_TOP ( scff_Wires[185] ) , - .SC_OUT_TOP ( scff_Wires[186] ) , .Test_en_S_in ( p1165 ) , + .SC_OUT_TOP ( scff_Wires[186] ) , .Test_en_S_in ( p893 ) , .Test_en_N_out ( SYNOPSYS_UNCONNECTED_2101 ) , .pReset_S_in ( SYNOPSYS_UNCONNECTED_2102 ) , .pReset_E_in ( SYNOPSYS_UNCONNECTED_2103 ) , .pReset_W_in ( pResetWires[44] ) , .pReset_N_out ( pResetWires[45] ) , .pReset_W_out ( SYNOPSYS_UNCONNECTED_2104 ) , - .pReset_E_out ( pResetWires[46] ) , .Reset_S_in ( p1523 ) , + .pReset_E_out ( pResetWires[46] ) , .Reset_S_in ( p893 ) , .Reset_N_out ( SYNOPSYS_UNCONNECTED_2105 ) , - .prog_clk_0_N_in ( prog_clk_0_wires[255] ) , .prog_clk_3_S_in ( p1523 ) , - .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_2106 ) , .clk_3_S_in ( p1523 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[255] ) , .prog_clk_3_S_in ( p893 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_2106 ) , .clk_3_S_in ( p893 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_2107 ) ) ; sb_1__0_ sb_8__0_ ( .pReset ( { SYNOPSYS_UNCONNECTED_2108 } ) , @@ -105688,17 +110210,17 @@ sb_1__0_ sb_8__0_ ( .chany_top_out ( sb_1__0__7_chany_top_out ) , .chanx_right_out ( sb_1__0__7_chanx_right_out ) , .chanx_left_out ( sb_1__0__7_chanx_left_out ) , - .ccff_tail ( sb_1__0__7_ccff_tail ) , .SC_IN_TOP ( p1461 ) , - .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_2109 ) , .Test_en_S_in ( p981 ) , + .ccff_tail ( sb_1__0__7_ccff_tail ) , .SC_IN_TOP ( p1448 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_2109 ) , .Test_en_S_in ( p1046 ) , .Test_en_N_out ( SYNOPSYS_UNCONNECTED_2110 ) , .pReset_S_in ( SYNOPSYS_UNCONNECTED_2111 ) , .pReset_E_in ( SYNOPSYS_UNCONNECTED_2112 ) , .pReset_W_in ( pResetWires[47] ) , .pReset_N_out ( pResetWires[48] ) , .pReset_W_out ( SYNOPSYS_UNCONNECTED_2113 ) , - .pReset_E_out ( pResetWires[49] ) , .Reset_S_in ( p981 ) , + .pReset_E_out ( pResetWires[49] ) , .Reset_S_in ( p1046 ) , .Reset_N_out ( SYNOPSYS_UNCONNECTED_2114 ) , - .prog_clk_0_N_in ( prog_clk_0_wires[293] ) , .prog_clk_3_S_in ( p981 ) , - .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_2115 ) , .clk_3_S_in ( p981 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[293] ) , .prog_clk_3_S_in ( p1046 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_2115 ) , .clk_3_S_in ( p1046 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_2116 ) ) ; sb_1__0_ sb_9__0_ ( .pReset ( { SYNOPSYS_UNCONNECTED_2117 } ) , @@ -105736,16 +110258,16 @@ sb_1__0_ sb_9__0_ ( .chanx_right_out ( sb_1__0__8_chanx_right_out ) , .chanx_left_out ( sb_1__0__8_chanx_left_out ) , .ccff_tail ( sb_1__0__8_ccff_tail ) , .SC_IN_TOP ( scff_Wires[238] ) , - .SC_OUT_TOP ( scff_Wires[239] ) , .Test_en_S_in ( p1066 ) , + .SC_OUT_TOP ( scff_Wires[239] ) , .Test_en_S_in ( p813 ) , .Test_en_N_out ( SYNOPSYS_UNCONNECTED_2118 ) , .pReset_S_in ( SYNOPSYS_UNCONNECTED_2119 ) , .pReset_E_in ( SYNOPSYS_UNCONNECTED_2120 ) , .pReset_W_in ( pResetWires[50] ) , .pReset_N_out ( pResetWires[51] ) , .pReset_W_out ( SYNOPSYS_UNCONNECTED_2121 ) , - .pReset_E_out ( pResetWires[52] ) , .Reset_S_in ( p1066 ) , + .pReset_E_out ( pResetWires[52] ) , .Reset_S_in ( p813 ) , .Reset_N_out ( SYNOPSYS_UNCONNECTED_2122 ) , - .prog_clk_0_N_in ( prog_clk_0_wires[331] ) , .prog_clk_3_S_in ( p1066 ) , - .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_2123 ) , .clk_3_S_in ( p1066 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[331] ) , .prog_clk_3_S_in ( p1447 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_2123 ) , .clk_3_S_in ( p813 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_2124 ) ) ; sb_1__0_ sb_10__0_ ( .pReset ( { SYNOPSYS_UNCONNECTED_2125 } ) , @@ -105782,17 +110304,17 @@ sb_1__0_ sb_10__0_ ( .chany_top_out ( sb_1__0__9_chany_top_out ) , .chanx_right_out ( sb_1__0__9_chanx_right_out ) , .chanx_left_out ( sb_1__0__9_chanx_left_out ) , - .ccff_tail ( sb_1__0__9_ccff_tail ) , .SC_IN_TOP ( p1181 ) , - .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_2126 ) , .Test_en_S_in ( p1086 ) , + .ccff_tail ( sb_1__0__9_ccff_tail ) , .SC_IN_TOP ( p1221 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_2126 ) , .Test_en_S_in ( p1477 ) , .Test_en_N_out ( SYNOPSYS_UNCONNECTED_2127 ) , .pReset_S_in ( SYNOPSYS_UNCONNECTED_2128 ) , .pReset_E_in ( SYNOPSYS_UNCONNECTED_2129 ) , .pReset_W_in ( pResetWires[53] ) , .pReset_N_out ( pResetWires[54] ) , .pReset_W_out ( SYNOPSYS_UNCONNECTED_2130 ) , - .pReset_E_out ( pResetWires[55] ) , .Reset_S_in ( p1086 ) , + .pReset_E_out ( pResetWires[55] ) , .Reset_S_in ( p1477 ) , .Reset_N_out ( SYNOPSYS_UNCONNECTED_2131 ) , - .prog_clk_0_N_in ( prog_clk_0_wires[369] ) , .prog_clk_3_S_in ( p1086 ) , - .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_2132 ) , .clk_3_S_in ( p1086 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[369] ) , .prog_clk_3_S_in ( p1084 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_2132 ) , .clk_3_S_in ( p1477 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_2133 ) ) ; sb_1__0_ sb_11__0_ ( .pReset ( { SYNOPSYS_UNCONNECTED_2134 } ) , @@ -105830,16 +110352,16 @@ sb_1__0_ sb_11__0_ ( .chanx_right_out ( sb_1__0__10_chanx_right_out ) , .chanx_left_out ( sb_1__0__10_chanx_left_out ) , .ccff_tail ( sb_1__0__10_ccff_tail ) , .SC_IN_TOP ( scff_Wires[291] ) , - .SC_OUT_TOP ( scff_Wires[292] ) , .Test_en_S_in ( p1368 ) , + .SC_OUT_TOP ( scff_Wires[292] ) , .Test_en_S_in ( p1374 ) , .Test_en_N_out ( SYNOPSYS_UNCONNECTED_2135 ) , .pReset_S_in ( SYNOPSYS_UNCONNECTED_2136 ) , .pReset_E_in ( SYNOPSYS_UNCONNECTED_2137 ) , .pReset_W_in ( pResetWires[56] ) , .pReset_N_out ( pResetWires[57] ) , .pReset_W_out ( SYNOPSYS_UNCONNECTED_2138 ) , - .pReset_E_out ( pResetWires[58] ) , .Reset_S_in ( p1368 ) , + .pReset_E_out ( pResetWires[58] ) , .Reset_S_in ( p1374 ) , .Reset_N_out ( SYNOPSYS_UNCONNECTED_2139 ) , - .prog_clk_0_N_in ( prog_clk_0_wires[407] ) , .prog_clk_3_S_in ( p1368 ) , - .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_2140 ) , .clk_3_S_in ( p1368 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[407] ) , .prog_clk_3_S_in ( p1374 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_2140 ) , .clk_3_S_in ( p1374 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_2141 ) ) ; sb_1__1_ sb_1__1_ ( .pReset ( { SYNOPSYS_UNCONNECTED_2142 } ) , @@ -105884,27 +110406,27 @@ sb_1__1_ sb_1__1_ ( .chanx_right_out ( sb_1__1__0_chanx_right_out ) , .chany_bottom_out ( sb_1__1__0_chany_bottom_out ) , .chanx_left_out ( sb_1__1__0_chanx_left_out ) , - .ccff_tail ( sb_1__1__0_ccff_tail ) , .Test_en_S_in ( p2487 ) , + .ccff_tail ( sb_1__1__0_ccff_tail ) , .Test_en_S_in ( p2787 ) , .Test_en_N_out ( SYNOPSYS_UNCONNECTED_2143 ) , .pReset_S_in ( SYNOPSYS_UNCONNECTED_2144 ) , .pReset_E_in ( pResetWires[66] ) , .pReset_W_in ( SYNOPSYS_UNCONNECTED_2145 ) , .pReset_N_out ( pResetWires[65] ) , .pReset_W_out ( pResetWires[62] ) , - .pReset_E_out ( SYNOPSYS_UNCONNECTED_2146 ) , .Reset_S_in ( p3360 ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_2146 ) , .Reset_S_in ( p2787 ) , .Reset_N_out ( SYNOPSYS_UNCONNECTED_2147 ) , .prog_clk_0_N_in ( prog_clk_0_wires[8] ) , .prog_clk_1_N_in ( prog_clk_2_wires[4] ) , .prog_clk_1_S_in ( SYNOPSYS_UNCONNECTED_2148 ) , .prog_clk_1_E_out ( prog_clk_1_wires[1] ) , - .prog_clk_1_W_out ( prog_clk_1_wires[2] ) , .prog_clk_2_N_in ( p3487 ) , - .prog_clk_2_E_in ( p1183 ) , .prog_clk_2_S_in ( p378 ) , - .prog_clk_2_W_in ( p1176 ) , + .prog_clk_1_W_out ( prog_clk_1_wires[2] ) , .prog_clk_2_N_in ( p3228 ) , + .prog_clk_2_E_in ( p437 ) , .prog_clk_2_S_in ( p76 ) , + .prog_clk_2_W_in ( p439 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_2149 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_2150 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_2151 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_2152 ) , - .prog_clk_3_W_in ( p2693 ) , .prog_clk_3_E_in ( p168 ) , - .prog_clk_3_S_in ( p1116 ) , .prog_clk_3_N_in ( p3483 ) , + .prog_clk_3_W_in ( p2990 ) , .prog_clk_3_E_in ( p674 ) , + .prog_clk_3_S_in ( p887 ) , .prog_clk_3_N_in ( p3191 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_2153 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_2154 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_2155 ) , @@ -105912,12 +110434,12 @@ sb_1__1_ sb_1__1_ ( .clk_1_N_in ( clk_2_wires[4] ) , .clk_1_S_in ( SYNOPSYS_UNCONNECTED_2157 ) , .clk_1_E_out ( clk_1_wires[1] ) , .clk_1_W_out ( clk_1_wires[2] ) , - .clk_2_N_in ( p3177 ) , .clk_2_E_in ( p986 ) , .clk_2_S_in ( p3340 ) , - .clk_2_W_in ( p2571 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_2158 ) , + .clk_2_N_in ( p3000 ) , .clk_2_E_in ( p117 ) , .clk_2_S_in ( p541 ) , + .clk_2_W_in ( p2868 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_2158 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_2159 ) , .clk_2_N_out ( SYNOPSYS_UNCONNECTED_2160 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_2161 ) , .clk_3_W_in ( p2693 ) , - .clk_3_E_in ( p858 ) , .clk_3_S_in ( p83 ) , .clk_3_N_in ( p3130 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_2161 ) , .clk_3_W_in ( p2975 ) , + .clk_3_E_in ( p962 ) , .clk_3_S_in ( p2672 ) , .clk_3_N_in ( p2922 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_2162 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_2163 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_2164 ) , @@ -105965,16 +110487,16 @@ sb_1__1_ sb_1__2_ ( .chanx_right_out ( sb_1__1__1_chanx_right_out ) , .chany_bottom_out ( sb_1__1__1_chany_bottom_out ) , .chanx_left_out ( sb_1__1__1_chanx_left_out ) , - .ccff_tail ( sb_1__1__1_ccff_tail ) , .Test_en_S_in ( p2944 ) , + .ccff_tail ( sb_1__1__1_ccff_tail ) , .Test_en_S_in ( p2997 ) , .Test_en_N_out ( SYNOPSYS_UNCONNECTED_2167 ) , .pReset_S_in ( SYNOPSYS_UNCONNECTED_2168 ) , .pReset_E_in ( pResetWires[115] ) , .pReset_W_in ( SYNOPSYS_UNCONNECTED_2169 ) , .pReset_N_out ( pResetWires[114] ) , .pReset_W_out ( pResetWires[111] ) , - .pReset_E_out ( SYNOPSYS_UNCONNECTED_2170 ) , .Reset_S_in ( p2944 ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_2170 ) , .Reset_S_in ( p2997 ) , .Reset_N_out ( SYNOPSYS_UNCONNECTED_2171 ) , - .prog_clk_0_N_in ( prog_clk_0_wires[13] ) , .prog_clk_1_N_in ( p1220 ) , - .prog_clk_1_S_in ( p383 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[13] ) , .prog_clk_1_N_in ( p1504 ) , + .prog_clk_1_S_in ( p519 ) , .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_2172 ) , .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_2173 ) , .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_2174 ) , @@ -105985,13 +110507,13 @@ sb_1__1_ sb_1__2_ ( .prog_clk_2_S_out ( prog_clk_2_wires[3] ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_2178 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_2179 ) , - .prog_clk_3_W_in ( p2150 ) , .prog_clk_3_E_in ( p238 ) , - .prog_clk_3_S_in ( p6 ) , .prog_clk_3_N_in ( p236 ) , + .prog_clk_3_W_in ( p1393 ) , .prog_clk_3_E_in ( p348 ) , + .prog_clk_3_S_in ( p545 ) , .prog_clk_3_N_in ( p114 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_2180 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_2181 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_2182 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_2183 ) , .clk_1_N_in ( p1220 ) , - .clk_1_S_in ( p106 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_2184 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_2183 ) , .clk_1_N_in ( p1504 ) , + .clk_1_S_in ( p1097 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_2184 ) , .clk_1_W_out ( SYNOPSYS_UNCONNECTED_2185 ) , .clk_2_N_in ( SYNOPSYS_UNCONNECTED_2186 ) , .clk_2_E_in ( clk_2_wires[1] ) , @@ -106000,8 +110522,8 @@ sb_1__1_ sb_1__2_ ( .clk_2_W_out ( SYNOPSYS_UNCONNECTED_2189 ) , .clk_2_S_out ( clk_2_wires[3] ) , .clk_2_N_out ( SYNOPSYS_UNCONNECTED_2190 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_2191 ) , .clk_3_W_in ( p2150 ) , - .clk_3_E_in ( p810 ) , .clk_3_S_in ( p2867 ) , .clk_3_N_in ( p625 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_2191 ) , .clk_3_W_in ( p1393 ) , + .clk_3_E_in ( p1748 ) , .clk_3_S_in ( p2876 ) , .clk_3_N_in ( p507 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_2192 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_2193 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_2194 ) , @@ -106049,27 +110571,27 @@ sb_1__1_ sb_1__3_ ( .chanx_right_out ( sb_1__1__2_chanx_right_out ) , .chany_bottom_out ( sb_1__1__2_chany_bottom_out ) , .chanx_left_out ( sb_1__1__2_chanx_left_out ) , - .ccff_tail ( sb_1__1__2_ccff_tail ) , .Test_en_S_in ( p3357 ) , + .ccff_tail ( sb_1__1__2_ccff_tail ) , .Test_en_S_in ( p1444 ) , .Test_en_N_out ( SYNOPSYS_UNCONNECTED_2197 ) , .pReset_S_in ( SYNOPSYS_UNCONNECTED_2198 ) , .pReset_E_in ( pResetWires[164] ) , .pReset_W_in ( SYNOPSYS_UNCONNECTED_2199 ) , .pReset_N_out ( pResetWires[163] ) , .pReset_W_out ( pResetWires[160] ) , - .pReset_E_out ( SYNOPSYS_UNCONNECTED_2200 ) , .Reset_S_in ( p3408 ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_2200 ) , .Reset_S_in ( p1444 ) , .Reset_N_out ( SYNOPSYS_UNCONNECTED_2201 ) , .prog_clk_0_N_in ( prog_clk_0_wires[18] ) , .prog_clk_1_N_in ( prog_clk_2_wires[11] ) , .prog_clk_1_S_in ( SYNOPSYS_UNCONNECTED_2202 ) , .prog_clk_1_E_out ( prog_clk_1_wires[8] ) , - .prog_clk_1_W_out ( prog_clk_1_wires[9] ) , .prog_clk_2_N_in ( p3466 ) , - .prog_clk_2_E_in ( p720 ) , .prog_clk_2_S_in ( p140 ) , - .prog_clk_2_W_in ( p264 ) , + .prog_clk_1_W_out ( prog_clk_1_wires[9] ) , .prog_clk_2_N_in ( p3553 ) , + .prog_clk_2_E_in ( p665 ) , .prog_clk_2_S_in ( p657 ) , + .prog_clk_2_W_in ( p884 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_2203 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_2204 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_2205 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_2206 ) , - .prog_clk_3_W_in ( p2239 ) , .prog_clk_3_E_in ( p279 ) , - .prog_clk_3_S_in ( p808 ) , .prog_clk_3_N_in ( p3461 ) , + .prog_clk_3_W_in ( p3016 ) , .prog_clk_3_E_in ( p627 ) , + .prog_clk_3_S_in ( p1233 ) , .prog_clk_3_N_in ( p3547 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_2207 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_2208 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_2209 ) , @@ -106077,12 +110599,12 @@ sb_1__1_ sb_1__3_ ( .clk_1_N_in ( clk_2_wires[11] ) , .clk_1_S_in ( SYNOPSYS_UNCONNECTED_2211 ) , .clk_1_E_out ( clk_1_wires[8] ) , .clk_1_W_out ( clk_1_wires[9] ) , - .clk_2_N_in ( p3358 ) , .clk_2_E_in ( p984 ) , .clk_2_S_in ( p3391 ) , - .clk_2_W_in ( p2043 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_2212 ) , + .clk_2_N_in ( p3270 ) , .clk_2_E_in ( p86 ) , .clk_2_S_in ( p1148 ) , + .clk_2_W_in ( p2902 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_2212 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_2213 ) , .clk_2_N_out ( SYNOPSYS_UNCONNECTED_2214 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_2215 ) , .clk_3_W_in ( p2239 ) , - .clk_3_E_in ( p796 ) , .clk_3_S_in ( p384 ) , .clk_3_N_in ( p3354 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_2215 ) , .clk_3_W_in ( p2543 ) , + .clk_3_E_in ( p1069 ) , .clk_3_S_in ( p286 ) , .clk_3_N_in ( p3176 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_2216 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_2217 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_2218 ) , @@ -106130,16 +110652,16 @@ sb_1__1_ sb_1__4_ ( .chanx_right_out ( sb_1__1__3_chanx_right_out ) , .chany_bottom_out ( sb_1__1__3_chany_bottom_out ) , .chanx_left_out ( sb_1__1__3_chanx_left_out ) , - .ccff_tail ( sb_1__1__3_ccff_tail ) , .Test_en_S_in ( p2972 ) , + .ccff_tail ( sb_1__1__3_ccff_tail ) , .Test_en_S_in ( p1966 ) , .Test_en_N_out ( SYNOPSYS_UNCONNECTED_2221 ) , .pReset_S_in ( SYNOPSYS_UNCONNECTED_2222 ) , .pReset_E_in ( pResetWires[213] ) , .pReset_W_in ( SYNOPSYS_UNCONNECTED_2223 ) , .pReset_N_out ( pResetWires[212] ) , .pReset_W_out ( pResetWires[209] ) , - .pReset_E_out ( SYNOPSYS_UNCONNECTED_2224 ) , .Reset_S_in ( p2972 ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_2224 ) , .Reset_S_in ( p1966 ) , .Reset_N_out ( SYNOPSYS_UNCONNECTED_2225 ) , - .prog_clk_0_N_in ( prog_clk_0_wires[23] ) , .prog_clk_1_N_in ( p1431 ) , - .prog_clk_1_S_in ( p222 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[23] ) , .prog_clk_1_N_in ( p1908 ) , + .prog_clk_1_S_in ( p177 ) , .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_2226 ) , .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_2227 ) , .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_2228 ) , @@ -106150,13 +110672,13 @@ sb_1__1_ sb_1__4_ ( .prog_clk_2_S_out ( prog_clk_2_wires[10] ) , .prog_clk_2_N_out ( prog_clk_2_wires[8] ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_2232 ) , - .prog_clk_3_W_in ( p2227 ) , .prog_clk_3_E_in ( p1192 ) , - .prog_clk_3_S_in ( p590 ) , .prog_clk_3_N_in ( p1671 ) , + .prog_clk_3_W_in ( p1971 ) , .prog_clk_3_E_in ( p855 ) , + .prog_clk_3_S_in ( p868 ) , .prog_clk_3_N_in ( p2089 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_2233 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_2234 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_2235 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_2236 ) , .clk_1_N_in ( p1431 ) , - .clk_1_S_in ( p498 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_2237 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_2236 ) , .clk_1_N_in ( p1908 ) , + .clk_1_S_in ( p1063 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_2237 ) , .clk_1_W_out ( SYNOPSYS_UNCONNECTED_2238 ) , .clk_2_N_in ( SYNOPSYS_UNCONNECTED_2239 ) , .clk_2_E_in ( clk_2_wires[6] ) , @@ -106164,8 +110686,8 @@ sb_1__1_ sb_1__4_ ( .clk_2_W_in ( SYNOPSYS_UNCONNECTED_2241 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_2242 ) , .clk_2_S_out ( clk_2_wires[10] ) , .clk_2_N_out ( clk_2_wires[8] ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_2243 ) , .clk_3_W_in ( p2227 ) , - .clk_3_E_in ( p1676 ) , .clk_3_S_in ( p2883 ) , .clk_3_N_in ( p353 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_2243 ) , .clk_3_W_in ( p1971 ) , + .clk_3_E_in ( p136 ) , .clk_3_S_in ( p1738 ) , .clk_3_N_in ( p1783 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_2244 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_2245 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_2246 ) , @@ -106213,40 +110735,40 @@ sb_1__1_ sb_1__5_ ( .chanx_right_out ( sb_1__1__4_chanx_right_out ) , .chany_bottom_out ( sb_1__1__4_chany_bottom_out ) , .chanx_left_out ( sb_1__1__4_chanx_left_out ) , - .ccff_tail ( sb_1__1__4_ccff_tail ) , .Test_en_S_in ( p2645 ) , + .ccff_tail ( sb_1__1__4_ccff_tail ) , .Test_en_S_in ( p1909 ) , .Test_en_N_out ( SYNOPSYS_UNCONNECTED_2249 ) , .pReset_S_in ( SYNOPSYS_UNCONNECTED_2250 ) , .pReset_E_in ( pResetWires[262] ) , .pReset_W_in ( SYNOPSYS_UNCONNECTED_2251 ) , .pReset_N_out ( pResetWires[261] ) , .pReset_W_out ( pResetWires[258] ) , - .pReset_E_out ( SYNOPSYS_UNCONNECTED_2252 ) , .Reset_S_in ( p3168 ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_2252 ) , .Reset_S_in ( p1909 ) , .Reset_N_out ( SYNOPSYS_UNCONNECTED_2253 ) , .prog_clk_0_N_in ( prog_clk_0_wires[28] ) , .prog_clk_1_N_in ( SYNOPSYS_UNCONNECTED_2254 ) , .prog_clk_1_S_in ( prog_clk_2_wires[9] ) , .prog_clk_1_E_out ( prog_clk_1_wires[15] ) , - .prog_clk_1_W_out ( prog_clk_1_wires[16] ) , .prog_clk_2_N_in ( p3432 ) , - .prog_clk_2_E_in ( p131 ) , .prog_clk_2_S_in ( p619 ) , - .prog_clk_2_W_in ( p990 ) , + .prog_clk_1_W_out ( prog_clk_1_wires[16] ) , .prog_clk_2_N_in ( p3577 ) , + .prog_clk_2_E_in ( p534 ) , .prog_clk_2_S_in ( p748 ) , + .prog_clk_2_W_in ( p516 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_2255 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_2256 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_2257 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_2258 ) , - .prog_clk_3_W_in ( p2226 ) , .prog_clk_3_E_in ( p1251 ) , - .prog_clk_3_S_in ( p1138 ) , .prog_clk_3_N_in ( p3418 ) , + .prog_clk_3_W_in ( p2793 ) , .prog_clk_3_E_in ( p210 ) , + .prog_clk_3_S_in ( p1120 ) , .prog_clk_3_N_in ( p3564 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_2259 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_2260 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_2261 ) , .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_2262 ) , .clk_1_N_in ( SYNOPSYS_UNCONNECTED_2263 ) , .clk_1_S_in ( clk_2_wires[9] ) , .clk_1_E_out ( clk_1_wires[15] ) , - .clk_1_W_out ( clk_1_wires[16] ) , .clk_2_N_in ( p3359 ) , - .clk_2_E_in ( p786 ) , .clk_2_S_in ( p3131 ) , .clk_2_W_in ( p1971 ) , + .clk_1_W_out ( clk_1_wires[16] ) , .clk_2_N_in ( p3134 ) , + .clk_2_E_in ( p585 ) , .clk_2_S_in ( p669 ) , .clk_2_W_in ( p3174 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_2264 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_2265 ) , .clk_2_N_out ( SYNOPSYS_UNCONNECTED_2266 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_2267 ) , .clk_3_W_in ( p2226 ) , - .clk_3_E_in ( p819 ) , .clk_3_S_in ( p552 ) , .clk_3_N_in ( p3351 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_2267 ) , .clk_3_W_in ( p3260 ) , + .clk_3_E_in ( p1062 ) , .clk_3_S_in ( p1697 ) , .clk_3_N_in ( p3091 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_2268 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_2269 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_2270 ) , @@ -106294,38 +110816,38 @@ sb_1__1_ sb_1__6_ ( .chanx_right_out ( sb_1__1__5_chanx_right_out ) , .chany_bottom_out ( sb_1__1__5_chany_bottom_out ) , .chanx_left_out ( sb_1__1__5_chanx_left_out ) , - .ccff_tail ( sb_1__1__5_ccff_tail ) , .Test_en_S_in ( p2476 ) , + .ccff_tail ( sb_1__1__5_ccff_tail ) , .Test_en_S_in ( p1849 ) , .Test_en_N_out ( SYNOPSYS_UNCONNECTED_2273 ) , .pReset_S_in ( SYNOPSYS_UNCONNECTED_2274 ) , .pReset_E_in ( pResetWires[311] ) , .pReset_W_in ( SYNOPSYS_UNCONNECTED_2275 ) , .pReset_N_out ( pResetWires[310] ) , .pReset_W_out ( pResetWires[307] ) , - .pReset_E_out ( SYNOPSYS_UNCONNECTED_2276 ) , .Reset_S_in ( p3453 ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_2276 ) , .Reset_S_in ( p1849 ) , .Reset_N_out ( SYNOPSYS_UNCONNECTED_2277 ) , - .prog_clk_0_N_in ( prog_clk_0_wires[33] ) , .prog_clk_1_N_in ( p1382 ) , - .prog_clk_1_S_in ( p924 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[33] ) , .prog_clk_1_N_in ( p2245 ) , + .prog_clk_1_S_in ( p300 ) , .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_2278 ) , .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_2279 ) , - .prog_clk_2_N_in ( p3467 ) , .prog_clk_2_E_in ( p1064 ) , - .prog_clk_2_S_in ( p1163 ) , .prog_clk_2_W_in ( p78 ) , + .prog_clk_2_N_in ( p1629 ) , .prog_clk_2_E_in ( p787 ) , + .prog_clk_2_S_in ( p23 ) , .prog_clk_2_W_in ( p142 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_2280 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_2281 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_2282 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_2283 ) , - .prog_clk_3_W_in ( p1836 ) , .prog_clk_3_E_in ( p181 ) , - .prog_clk_3_S_in ( p486 ) , .prog_clk_3_N_in ( p3458 ) , + .prog_clk_3_W_in ( p3355 ) , .prog_clk_3_E_in ( p968 ) , + .prog_clk_3_S_in ( p857 ) , .prog_clk_3_N_in ( p781 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_2284 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_2285 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_2286 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_2287 ) , .clk_1_N_in ( p1382 ) , - .clk_1_S_in ( p656 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_2288 ) , - .clk_1_W_out ( SYNOPSYS_UNCONNECTED_2289 ) , .clk_2_N_in ( p3110 ) , - .clk_2_E_in ( p840 ) , .clk_2_S_in ( p3445 ) , .clk_2_W_in ( p1703 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_2287 ) , .clk_1_N_in ( p2245 ) , + .clk_1_S_in ( p998 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_2288 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_2289 ) , .clk_2_N_in ( p3514 ) , + .clk_2_E_in ( p1152 ) , .clk_2_S_in ( p242 ) , .clk_2_W_in ( p3488 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_2290 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_2291 ) , .clk_2_N_out ( SYNOPSYS_UNCONNECTED_2292 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_2293 ) , .clk_3_W_in ( p1836 ) , - .clk_3_E_in ( p861 ) , .clk_3_S_in ( p1465 ) , .clk_3_N_in ( p3017 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_2293 ) , .clk_3_W_in ( p3501 ) , + .clk_3_E_in ( p81 ) , .clk_3_S_in ( p1765 ) , .clk_3_N_in ( p3492 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_2294 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_2295 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_2296 ) , @@ -106373,27 +110895,27 @@ sb_1__1_ sb_1__7_ ( .chanx_right_out ( sb_1__1__6_chanx_right_out ) , .chany_bottom_out ( sb_1__1__6_chany_bottom_out ) , .chanx_left_out ( sb_1__1__6_chanx_left_out ) , - .ccff_tail ( sb_1__1__6_ccff_tail ) , .Test_en_S_in ( p2928 ) , + .ccff_tail ( sb_1__1__6_ccff_tail ) , .Test_en_S_in ( p2195 ) , .Test_en_N_out ( SYNOPSYS_UNCONNECTED_2299 ) , .pReset_S_in ( SYNOPSYS_UNCONNECTED_2300 ) , .pReset_E_in ( pResetWires[360] ) , .pReset_W_in ( SYNOPSYS_UNCONNECTED_2301 ) , .pReset_N_out ( pResetWires[359] ) , .pReset_W_out ( pResetWires[356] ) , - .pReset_E_out ( SYNOPSYS_UNCONNECTED_2302 ) , .Reset_S_in ( p3318 ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_2302 ) , .Reset_S_in ( p2195 ) , .Reset_N_out ( SYNOPSYS_UNCONNECTED_2303 ) , .prog_clk_0_N_in ( prog_clk_0_wires[38] ) , .prog_clk_1_N_in ( prog_clk_2_wires[18] ) , .prog_clk_1_S_in ( SYNOPSYS_UNCONNECTED_2304 ) , .prog_clk_1_E_out ( prog_clk_1_wires[22] ) , - .prog_clk_1_W_out ( prog_clk_1_wires[23] ) , .prog_clk_2_N_in ( p3272 ) , - .prog_clk_2_E_in ( p944 ) , .prog_clk_2_S_in ( p23 ) , - .prog_clk_2_W_in ( p1226 ) , + .prog_clk_1_W_out ( prog_clk_1_wires[23] ) , .prog_clk_2_N_in ( p3408 ) , + .prog_clk_2_E_in ( p694 ) , .prog_clk_2_S_in ( p281 ) , + .prog_clk_2_W_in ( p850 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_2305 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_2306 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_2307 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_2308 ) , - .prog_clk_3_W_in ( p2515 ) , .prog_clk_3_E_in ( p313 ) , - .prog_clk_3_S_in ( p1221 ) , .prog_clk_3_N_in ( p3214 ) , + .prog_clk_3_W_in ( p2587 ) , .prog_clk_3_E_in ( p59 ) , + .prog_clk_3_S_in ( p902 ) , .prog_clk_3_N_in ( p3372 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_2309 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_2310 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_2311 ) , @@ -106401,12 +110923,12 @@ sb_1__1_ sb_1__7_ ( .clk_1_N_in ( clk_2_wires[18] ) , .clk_1_S_in ( SYNOPSYS_UNCONNECTED_2313 ) , .clk_1_E_out ( clk_1_wires[22] ) , .clk_1_W_out ( clk_1_wires[23] ) , - .clk_2_N_in ( p3264 ) , .clk_2_E_in ( p291 ) , .clk_2_S_in ( p3285 ) , - .clk_2_W_in ( p2330 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_2314 ) , + .clk_2_N_in ( p2812 ) , .clk_2_E_in ( p992 ) , .clk_2_S_in ( p479 ) , + .clk_2_W_in ( p3520 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_2314 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_2315 ) , .clk_2_N_out ( SYNOPSYS_UNCONNECTED_2316 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_2317 ) , .clk_3_W_in ( p2515 ) , - .clk_3_E_in ( p925 ) , .clk_3_S_in ( p454 ) , .clk_3_N_in ( p3235 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_2317 ) , .clk_3_W_in ( p3529 ) , + .clk_3_E_in ( p786 ) , .clk_3_S_in ( p2106 ) , .clk_3_N_in ( p2702 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_2318 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_2319 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_2320 ) , @@ -106454,16 +110976,16 @@ sb_1__1_ sb_1__8_ ( .chanx_right_out ( sb_1__1__7_chanx_right_out ) , .chany_bottom_out ( sb_1__1__7_chany_bottom_out ) , .chanx_left_out ( sb_1__1__7_chanx_left_out ) , - .ccff_tail ( sb_1__1__7_ccff_tail ) , .Test_en_S_in ( p3241 ) , + .ccff_tail ( sb_1__1__7_ccff_tail ) , .Test_en_S_in ( p2285 ) , .Test_en_N_out ( SYNOPSYS_UNCONNECTED_2323 ) , .pReset_S_in ( SYNOPSYS_UNCONNECTED_2324 ) , .pReset_E_in ( pResetWires[409] ) , .pReset_W_in ( SYNOPSYS_UNCONNECTED_2325 ) , .pReset_N_out ( pResetWires[408] ) , .pReset_W_out ( pResetWires[405] ) , - .pReset_E_out ( SYNOPSYS_UNCONNECTED_2326 ) , .Reset_S_in ( p3241 ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_2326 ) , .Reset_S_in ( p2285 ) , .Reset_N_out ( SYNOPSYS_UNCONNECTED_2327 ) , - .prog_clk_0_N_in ( prog_clk_0_wires[43] ) , .prog_clk_1_N_in ( p2138 ) , - .prog_clk_1_S_in ( p61 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[43] ) , .prog_clk_1_N_in ( p1503 ) , + .prog_clk_1_S_in ( p62 ) , .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_2328 ) , .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_2329 ) , .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_2330 ) , @@ -106474,13 +110996,13 @@ sb_1__1_ sb_1__8_ ( .prog_clk_2_S_out ( prog_clk_2_wires[17] ) , .prog_clk_2_N_out ( prog_clk_2_wires[15] ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_2334 ) , - .prog_clk_3_W_in ( p1190 ) , .prog_clk_3_E_in ( p234 ) , - .prog_clk_3_S_in ( p290 ) , .prog_clk_3_N_in ( p1647 ) , + .prog_clk_3_W_in ( p1628 ) , .prog_clk_3_E_in ( p187 ) , + .prog_clk_3_S_in ( p49 ) , .prog_clk_3_N_in ( p403 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_2335 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_2336 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_2337 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_2338 ) , .clk_1_N_in ( p2138 ) , - .clk_1_S_in ( p794 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_2339 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_2338 ) , .clk_1_N_in ( p1503 ) , + .clk_1_S_in ( p976 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_2339 ) , .clk_1_W_out ( SYNOPSYS_UNCONNECTED_2340 ) , .clk_2_N_in ( SYNOPSYS_UNCONNECTED_2341 ) , .clk_2_E_in ( clk_2_wires[13] ) , @@ -106488,8 +111010,8 @@ sb_1__1_ sb_1__8_ ( .clk_2_W_in ( SYNOPSYS_UNCONNECTED_2343 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_2344 ) , .clk_2_S_out ( clk_2_wires[17] ) , .clk_2_N_out ( clk_2_wires[15] ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_2345 ) , .clk_3_W_in ( p1190 ) , - .clk_3_E_in ( p1629 ) , .clk_3_S_in ( p3229 ) , .clk_3_N_in ( p1977 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_2345 ) , .clk_3_W_in ( p1628 ) , + .clk_3_E_in ( p825 ) , .clk_3_S_in ( p2093 ) , .clk_3_N_in ( p118 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_2346 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_2347 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_2348 ) , @@ -106537,40 +111059,40 @@ sb_1__1_ sb_1__9_ ( .chanx_right_out ( sb_1__1__8_chanx_right_out ) , .chany_bottom_out ( sb_1__1__8_chany_bottom_out ) , .chanx_left_out ( sb_1__1__8_chanx_left_out ) , - .ccff_tail ( sb_1__1__8_ccff_tail ) , .Test_en_S_in ( p3251 ) , + .ccff_tail ( sb_1__1__8_ccff_tail ) , .Test_en_S_in ( p2297 ) , .Test_en_N_out ( SYNOPSYS_UNCONNECTED_2351 ) , .pReset_S_in ( SYNOPSYS_UNCONNECTED_2352 ) , .pReset_E_in ( pResetWires[458] ) , .pReset_W_in ( SYNOPSYS_UNCONNECTED_2353 ) , .pReset_N_out ( pResetWires[457] ) , .pReset_W_out ( pResetWires[454] ) , - .pReset_E_out ( SYNOPSYS_UNCONNECTED_2354 ) , .Reset_S_in ( p3316 ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_2354 ) , .Reset_S_in ( p2297 ) , .Reset_N_out ( SYNOPSYS_UNCONNECTED_2355 ) , .prog_clk_0_N_in ( prog_clk_0_wires[48] ) , .prog_clk_1_N_in ( SYNOPSYS_UNCONNECTED_2356 ) , .prog_clk_1_S_in ( prog_clk_2_wires[16] ) , .prog_clk_1_E_out ( prog_clk_1_wires[29] ) , - .prog_clk_1_W_out ( prog_clk_1_wires[30] ) , .prog_clk_2_N_in ( p3074 ) , - .prog_clk_2_E_in ( p866 ) , .prog_clk_2_S_in ( p412 ) , - .prog_clk_2_W_in ( p1073 ) , + .prog_clk_1_W_out ( prog_clk_1_wires[30] ) , .prog_clk_2_N_in ( p3425 ) , + .prog_clk_2_E_in ( p422 ) , .prog_clk_2_S_in ( p594 ) , + .prog_clk_2_W_in ( p795 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_2357 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_2358 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_2359 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_2360 ) , - .prog_clk_3_W_in ( p2242 ) , .prog_clk_3_E_in ( p1030 ) , - .prog_clk_3_S_in ( p803 ) , .prog_clk_3_N_in ( p3023 ) , + .prog_clk_3_W_in ( p3004 ) , .prog_clk_3_E_in ( p1022 ) , + .prog_clk_3_S_in ( p573 ) , .prog_clk_3_N_in ( p3370 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_2361 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_2362 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_2363 ) , .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_2364 ) , .clk_1_N_in ( SYNOPSYS_UNCONNECTED_2365 ) , .clk_1_S_in ( clk_2_wires[16] ) , .clk_1_E_out ( clk_1_wires[29] ) , - .clk_1_W_out ( clk_1_wires[30] ) , .clk_2_N_in ( p2652 ) , - .clk_2_E_in ( p51 ) , .clk_2_S_in ( p3277 ) , .clk_2_W_in ( p1984 ) , + .clk_1_W_out ( clk_1_wires[30] ) , .clk_2_N_in ( p3598 ) , + .clk_2_E_in ( p1053 ) , .clk_2_S_in ( p279 ) , .clk_2_W_in ( p3611 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_2366 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_2367 ) , .clk_2_N_out ( SYNOPSYS_UNCONNECTED_2368 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_2369 ) , .clk_3_W_in ( p2242 ) , - .clk_3_E_in ( p671 ) , .clk_3_S_in ( p189 ) , .clk_3_N_in ( p2587 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_2369 ) , .clk_3_W_in ( p3613 ) , + .clk_3_E_in ( p273 ) , .clk_3_S_in ( p2091 ) , .clk_3_N_in ( p3593 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_2370 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_2371 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_2372 ) , @@ -106618,16 +111140,16 @@ sb_1__1_ sb_1__10_ ( .chanx_right_out ( sb_1__1__9_chanx_right_out ) , .chany_bottom_out ( sb_1__1__9_chany_bottom_out ) , .chanx_left_out ( sb_1__1__9_chanx_left_out ) , - .ccff_tail ( sb_1__1__9_ccff_tail ) , .Test_en_S_in ( p2650 ) , + .ccff_tail ( sb_1__1__9_ccff_tail ) , .Test_en_S_in ( p2504 ) , .Test_en_N_out ( SYNOPSYS_UNCONNECTED_2375 ) , .pReset_S_in ( SYNOPSYS_UNCONNECTED_2376 ) , .pReset_E_in ( pResetWires[507] ) , .pReset_W_in ( SYNOPSYS_UNCONNECTED_2377 ) , .pReset_N_out ( pResetWires[506] ) , .pReset_W_out ( pResetWires[503] ) , - .pReset_E_out ( SYNOPSYS_UNCONNECTED_2378 ) , .Reset_S_in ( p2650 ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_2378 ) , .Reset_S_in ( p2504 ) , .Reset_N_out ( SYNOPSYS_UNCONNECTED_2379 ) , - .prog_clk_0_N_in ( prog_clk_0_wires[53] ) , .prog_clk_1_N_in ( p1361 ) , - .prog_clk_1_S_in ( p869 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[53] ) , .prog_clk_1_N_in ( p1542 ) , + .prog_clk_1_S_in ( p880 ) , .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_2380 ) , .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_2381 ) , .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_2382 ) , @@ -106638,13 +111160,13 @@ sb_1__1_ sb_1__10_ ( .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_2386 ) , .prog_clk_2_N_out ( prog_clk_2_wires[22] ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_2387 ) , - .prog_clk_3_W_in ( p1476 ) , .prog_clk_3_E_in ( p348 ) , - .prog_clk_3_S_in ( p136 ) , .prog_clk_3_N_in ( p1637 ) , + .prog_clk_3_W_in ( p2351 ) , .prog_clk_3_E_in ( p799 ) , + .prog_clk_3_S_in ( p78 ) , .prog_clk_3_N_in ( p85 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_2388 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_2389 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_2390 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_2391 ) , .clk_1_N_in ( p1361 ) , - .clk_1_S_in ( p485 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_2392 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_2391 ) , .clk_1_N_in ( p1542 ) , + .clk_1_S_in ( p243 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_2392 ) , .clk_1_W_out ( SYNOPSYS_UNCONNECTED_2393 ) , .clk_2_N_in ( SYNOPSYS_UNCONNECTED_2394 ) , .clk_2_E_in ( clk_2_wires[20] ) , @@ -106653,8 +111175,8 @@ sb_1__1_ sb_1__10_ ( .clk_2_W_out ( SYNOPSYS_UNCONNECTED_2397 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_2398 ) , .clk_2_N_out ( clk_2_wires[22] ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_2399 ) , .clk_3_W_in ( p1476 ) , - .clk_3_E_in ( p795 ) , .clk_3_S_in ( p2577 ) , .clk_3_N_in ( p114 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_2399 ) , .clk_3_W_in ( p2351 ) , + .clk_3_E_in ( p127 ) , .clk_3_S_in ( p2443 ) , .clk_3_N_in ( p483 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_2400 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_2401 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_2402 ) , @@ -106702,40 +111224,40 @@ sb_1__1_ sb_1__11_ ( .chanx_right_out ( sb_1__1__10_chanx_right_out ) , .chany_bottom_out ( sb_1__1__10_chany_bottom_out ) , .chanx_left_out ( sb_1__1__10_chanx_left_out ) , - .ccff_tail ( sb_1__1__10_ccff_tail ) , .Test_en_S_in ( p3162 ) , + .ccff_tail ( sb_1__1__10_ccff_tail ) , .Test_en_S_in ( p2043 ) , .Test_en_N_out ( SYNOPSYS_UNCONNECTED_2405 ) , .pReset_S_in ( SYNOPSYS_UNCONNECTED_2406 ) , .pReset_E_in ( pResetWires[556] ) , .pReset_W_in ( SYNOPSYS_UNCONNECTED_2407 ) , .pReset_N_out ( pResetWires[555] ) , .pReset_W_out ( pResetWires[552] ) , - .pReset_E_out ( SYNOPSYS_UNCONNECTED_2408 ) , .Reset_S_in ( p3162 ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_2408 ) , .Reset_S_in ( p2043 ) , .Reset_N_out ( SYNOPSYS_UNCONNECTED_2409 ) , .prog_clk_0_N_in ( prog_clk_0_wires[58] ) , .prog_clk_1_N_in ( SYNOPSYS_UNCONNECTED_2410 ) , .prog_clk_1_S_in ( prog_clk_2_wires[23] ) , .prog_clk_1_E_out ( prog_clk_1_wires[36] ) , - .prog_clk_1_W_out ( prog_clk_1_wires[37] ) , .prog_clk_2_N_in ( p3456 ) , - .prog_clk_2_E_in ( p774 ) , .prog_clk_2_S_in ( p479 ) , - .prog_clk_2_W_in ( p8 ) , + .prog_clk_1_W_out ( prog_clk_1_wires[37] ) , .prog_clk_2_N_in ( p3585 ) , + .prog_clk_2_E_in ( p800 ) , .prog_clk_2_S_in ( p765 ) , + .prog_clk_2_W_in ( p150 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_2411 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_2412 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_2413 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_2414 ) , - .prog_clk_3_W_in ( p2494 ) , .prog_clk_3_E_in ( p1101 ) , - .prog_clk_3_S_in ( p1308 ) , .prog_clk_3_N_in ( p3444 ) , + .prog_clk_3_W_in ( p2638 ) , .prog_clk_3_E_in ( p8 ) , + .prog_clk_3_S_in ( p1200 ) , .prog_clk_3_N_in ( p3580 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_2415 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_2416 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_2417 ) , .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_2418 ) , .clk_1_N_in ( SYNOPSYS_UNCONNECTED_2419 ) , .clk_1_S_in ( clk_2_wires[23] ) , .clk_1_E_out ( clk_1_wires[36] ) , - .clk_1_W_out ( clk_1_wires[37] ) , .clk_2_N_in ( p2982 ) , - .clk_2_E_in ( p1194 ) , .clk_2_S_in ( p3132 ) , .clk_2_W_in ( p2288 ) , + .clk_1_W_out ( clk_1_wires[37] ) , .clk_2_N_in ( p3415 ) , + .clk_2_E_in ( p542 ) , .clk_2_S_in ( p1176 ) , .clk_2_W_in ( p2707 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_2420 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_2421 ) , .clk_2_N_out ( SYNOPSYS_UNCONNECTED_2422 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_2423 ) , .clk_3_W_in ( p2494 ) , - .clk_3_E_in ( p112 ) , .clk_3_S_in ( p1312 ) , .clk_3_N_in ( p2919 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_2423 ) , .clk_3_W_in ( p2856 ) , + .clk_3_E_in ( p828 ) , .clk_3_S_in ( p1699 ) , .clk_3_N_in ( p3374 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_2424 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_2425 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_2426 ) , @@ -106783,38 +111305,38 @@ sb_1__1_ sb_2__1_ ( .chanx_right_out ( sb_1__1__11_chanx_right_out ) , .chany_bottom_out ( sb_1__1__11_chany_bottom_out ) , .chanx_left_out ( sb_1__1__11_chanx_left_out ) , - .ccff_tail ( sb_1__1__11_ccff_tail ) , .Test_en_S_in ( p2659 ) , + .ccff_tail ( sb_1__1__11_ccff_tail ) , .Test_en_S_in ( p1654 ) , .Test_en_N_out ( SYNOPSYS_UNCONNECTED_2429 ) , .pReset_S_in ( SYNOPSYS_UNCONNECTED_2430 ) , .pReset_E_in ( pResetWires[70] ) , .pReset_W_in ( SYNOPSYS_UNCONNECTED_2431 ) , .pReset_N_out ( pResetWires[69] ) , .pReset_W_out ( pResetWires[67] ) , - .pReset_E_out ( SYNOPSYS_UNCONNECTED_2432 ) , .Reset_S_in ( p3267 ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_2432 ) , .Reset_S_in ( p1654 ) , .Reset_N_out ( SYNOPSYS_UNCONNECTED_2433 ) , - .prog_clk_0_N_in ( prog_clk_0_wires[68] ) , .prog_clk_1_N_in ( p1791 ) , - .prog_clk_1_S_in ( p836 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[68] ) , .prog_clk_1_N_in ( p1582 ) , + .prog_clk_1_S_in ( p60 ) , .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_2434 ) , .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_2435 ) , - .prog_clk_2_N_in ( p2258 ) , .prog_clk_2_E_in ( p877 ) , - .prog_clk_2_S_in ( p442 ) , .prog_clk_2_W_in ( p1214 ) , + .prog_clk_2_N_in ( p3410 ) , .prog_clk_2_E_in ( p290 ) , + .prog_clk_2_S_in ( p227 ) , .prog_clk_2_W_in ( p626 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_2436 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_2437 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_2438 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_2439 ) , - .prog_clk_3_W_in ( p2093 ) , .prog_clk_3_E_in ( p1218 ) , - .prog_clk_3_S_in ( p1124 ) , .prog_clk_3_N_in ( p1998 ) , + .prog_clk_3_W_in ( p2209 ) , .prog_clk_3_E_in ( p1123 ) , + .prog_clk_3_S_in ( p1146 ) , .prog_clk_3_N_in ( p3375 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_2440 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_2441 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_2442 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_2443 ) , .clk_1_N_in ( p1791 ) , - .clk_1_S_in ( p223 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_2444 ) , - .clk_1_W_out ( SYNOPSYS_UNCONNECTED_2445 ) , .clk_2_N_in ( p2702 ) , - .clk_2_E_in ( p129 ) , .clk_2_S_in ( p3209 ) , .clk_2_W_in ( p2036 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_2443 ) , .clk_1_N_in ( p1582 ) , + .clk_1_S_in ( p1101 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_2444 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_2445 ) , .clk_2_N_in ( p3513 ) , + .clk_2_E_in ( p33 ) , .clk_2_S_in ( p1095 ) , .clk_2_W_in ( p3612 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_2446 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_2447 ) , .clk_2_N_out ( SYNOPSYS_UNCONNECTED_2448 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_2449 ) , .clk_3_W_in ( p2093 ) , - .clk_3_E_in ( p634 ) , .clk_3_S_in ( p1082 ) , .clk_3_N_in ( p2555 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_2449 ) , .clk_3_W_in ( p3614 ) , + .clk_3_E_in ( p1079 ) , .clk_3_S_in ( p319 ) , .clk_3_N_in ( p3487 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_2450 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_2451 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_2452 ) , @@ -106862,16 +111384,16 @@ sb_1__1_ sb_2__2_ ( .chanx_right_out ( sb_1__1__12_chanx_right_out ) , .chany_bottom_out ( sb_1__1__12_chany_bottom_out ) , .chanx_left_out ( sb_1__1__12_chanx_left_out ) , - .ccff_tail ( sb_1__1__12_ccff_tail ) , .Test_en_S_in ( p2619 ) , + .ccff_tail ( sb_1__1__12_ccff_tail ) , .Test_en_S_in ( p1316 ) , .Test_en_N_out ( SYNOPSYS_UNCONNECTED_2455 ) , .pReset_S_in ( SYNOPSYS_UNCONNECTED_2456 ) , .pReset_E_in ( pResetWires[119] ) , .pReset_W_in ( SYNOPSYS_UNCONNECTED_2457 ) , .pReset_N_out ( pResetWires[118] ) , .pReset_W_out ( pResetWires[116] ) , - .pReset_E_out ( SYNOPSYS_UNCONNECTED_2458 ) , .Reset_S_in ( p2619 ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_2458 ) , .Reset_S_in ( p1316 ) , .Reset_N_out ( SYNOPSYS_UNCONNECTED_2459 ) , - .prog_clk_0_N_in ( prog_clk_0_wires[71] ) , .prog_clk_1_N_in ( p1941 ) , - .prog_clk_1_S_in ( p314 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[71] ) , .prog_clk_1_N_in ( p2284 ) , + .prog_clk_1_S_in ( p498 ) , .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_2460 ) , .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_2461 ) , .prog_clk_2_N_in ( prog_clk_3_wires[69] ) , @@ -106882,13 +111404,13 @@ sb_1__1_ sb_2__2_ ( .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_2465 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_2466 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_2467 ) , - .prog_clk_3_W_in ( p1796 ) , .prog_clk_3_E_in ( p62 ) , - .prog_clk_3_S_in ( p844 ) , .prog_clk_3_N_in ( p394 ) , + .prog_clk_3_W_in ( p1920 ) , .prog_clk_3_E_in ( p1119 ) , + .prog_clk_3_S_in ( p776 ) , .prog_clk_3_N_in ( p397 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_2468 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_2469 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_2470 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_2471 ) , .clk_1_N_in ( p1941 ) , - .clk_1_S_in ( p870 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_2472 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_2471 ) , .clk_1_N_in ( p2284 ) , + .clk_1_S_in ( p1156 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_2472 ) , .clk_1_W_out ( SYNOPSYS_UNCONNECTED_2473 ) , .clk_2_N_in ( clk_3_wires[69] ) , .clk_2_E_in ( SYNOPSYS_UNCONNECTED_2474 ) , @@ -106897,8 +111419,8 @@ sb_1__1_ sb_2__2_ ( .clk_2_W_out ( clk_2_wires[2] ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_2477 ) , .clk_2_N_out ( SYNOPSYS_UNCONNECTED_2478 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_2479 ) , .clk_3_W_in ( p1796 ) , - .clk_3_E_in ( p838 ) , .clk_3_S_in ( p2581 ) , .clk_3_N_in ( p1630 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_2479 ) , .clk_3_W_in ( p1920 ) , + .clk_3_E_in ( p379 ) , .clk_3_S_in ( p323 ) , .clk_3_N_in ( p2128 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_2480 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_2481 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_2482 ) , @@ -106946,20 +111468,20 @@ sb_1__1_ sb_2__3_ ( .chanx_right_out ( sb_1__1__13_chanx_right_out ) , .chany_bottom_out ( sb_1__1__13_chany_bottom_out ) , .chanx_left_out ( sb_1__1__13_chanx_left_out ) , - .ccff_tail ( sb_1__1__13_ccff_tail ) , .Test_en_S_in ( p2824 ) , + .ccff_tail ( sb_1__1__13_ccff_tail ) , .Test_en_S_in ( p2338 ) , .Test_en_N_out ( SYNOPSYS_UNCONNECTED_2485 ) , .pReset_S_in ( SYNOPSYS_UNCONNECTED_2486 ) , .pReset_E_in ( pResetWires[168] ) , .pReset_W_in ( SYNOPSYS_UNCONNECTED_2487 ) , .pReset_N_out ( pResetWires[167] ) , .pReset_W_out ( pResetWires[165] ) , - .pReset_E_out ( SYNOPSYS_UNCONNECTED_2488 ) , .Reset_S_in ( p3479 ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_2488 ) , .Reset_S_in ( p2338 ) , .Reset_N_out ( SYNOPSYS_UNCONNECTED_2489 ) , - .prog_clk_0_N_in ( prog_clk_0_wires[74] ) , .prog_clk_1_N_in ( p1616 ) , - .prog_clk_1_S_in ( p268 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[74] ) , .prog_clk_1_N_in ( p1227 ) , + .prog_clk_1_S_in ( p1281 ) , .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_2490 ) , .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_2491 ) , - .prog_clk_2_N_in ( p2669 ) , .prog_clk_2_E_in ( p1080 ) , - .prog_clk_2_S_in ( p653 ) , .prog_clk_2_W_in ( p792 ) , + .prog_clk_2_N_in ( p2584 ) , .prog_clk_2_E_in ( p593 ) , + .prog_clk_2_S_in ( p1762 ) , .prog_clk_2_W_in ( p342 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_2492 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_2493 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_2494 ) , @@ -106971,10 +111493,10 @@ sb_1__1_ sb_2__3_ ( .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_2499 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_2500 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_2501 ) , - .prog_clk_3_S_out ( prog_clk_3_wires[68] ) , .clk_1_N_in ( p1616 ) , - .clk_1_S_in ( p871 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_2502 ) , - .clk_1_W_out ( SYNOPSYS_UNCONNECTED_2503 ) , .clk_2_N_in ( p2669 ) , - .clk_2_E_in ( p211 ) , .clk_2_S_in ( p3473 ) , .clk_2_W_in ( p123 ) , + .prog_clk_3_S_out ( prog_clk_3_wires[68] ) , .clk_1_N_in ( p1227 ) , + .clk_1_S_in ( p139 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_2502 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_2503 ) , .clk_2_N_in ( p1392 ) , + .clk_2_E_in ( p818 ) , .clk_2_S_in ( p2064 ) , .clk_2_W_in ( p756 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_2504 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_2505 ) , .clk_2_N_out ( SYNOPSYS_UNCONNECTED_2506 ) , @@ -107030,16 +111552,16 @@ sb_1__1_ sb_2__4_ ( .chanx_right_out ( sb_1__1__14_chanx_right_out ) , .chany_bottom_out ( sb_1__1__14_chany_bottom_out ) , .chanx_left_out ( sb_1__1__14_chanx_left_out ) , - .ccff_tail ( sb_1__1__14_ccff_tail ) , .Test_en_S_in ( p1958 ) , + .ccff_tail ( sb_1__1__14_ccff_tail ) , .Test_en_S_in ( p1850 ) , .Test_en_N_out ( SYNOPSYS_UNCONNECTED_2515 ) , .pReset_S_in ( SYNOPSYS_UNCONNECTED_2516 ) , .pReset_E_in ( pResetWires[217] ) , .pReset_W_in ( SYNOPSYS_UNCONNECTED_2517 ) , .pReset_N_out ( pResetWires[216] ) , .pReset_W_out ( pResetWires[214] ) , - .pReset_E_out ( SYNOPSYS_UNCONNECTED_2518 ) , .Reset_S_in ( p1958 ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_2518 ) , .Reset_S_in ( p1850 ) , .Reset_N_out ( SYNOPSYS_UNCONNECTED_2519 ) , - .prog_clk_0_N_in ( prog_clk_0_wires[77] ) , .prog_clk_1_N_in ( p1358 ) , - .prog_clk_1_S_in ( p629 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[77] ) , .prog_clk_1_N_in ( p1886 ) , + .prog_clk_1_S_in ( p1704 ) , .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_2520 ) , .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_2521 ) , .prog_clk_2_N_in ( prog_clk_3_wires[59] ) , @@ -107057,8 +111579,8 @@ sb_1__1_ sb_2__4_ ( .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_2531 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_2532 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_2533 ) , - .prog_clk_3_S_out ( prog_clk_3_wires[64] ) , .clk_1_N_in ( p1358 ) , - .clk_1_S_in ( p1650 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_2534 ) , + .prog_clk_3_S_out ( prog_clk_3_wires[64] ) , .clk_1_N_in ( p1886 ) , + .clk_1_S_in ( p1171 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_2534 ) , .clk_1_W_out ( SYNOPSYS_UNCONNECTED_2535 ) , .clk_2_N_in ( clk_3_wires[59] ) , .clk_2_E_in ( SYNOPSYS_UNCONNECTED_2536 ) , @@ -107119,20 +111641,20 @@ sb_1__1_ sb_2__5_ ( .chanx_right_out ( sb_1__1__15_chanx_right_out ) , .chany_bottom_out ( sb_1__1__15_chany_bottom_out ) , .chanx_left_out ( sb_1__1__15_chanx_left_out ) , - .ccff_tail ( sb_1__1__15_ccff_tail ) , .Test_en_S_in ( p2666 ) , + .ccff_tail ( sb_1__1__15_ccff_tail ) , .Test_en_S_in ( p2583 ) , .Test_en_N_out ( SYNOPSYS_UNCONNECTED_2549 ) , .pReset_S_in ( SYNOPSYS_UNCONNECTED_2550 ) , .pReset_E_in ( pResetWires[266] ) , .pReset_W_in ( SYNOPSYS_UNCONNECTED_2551 ) , .pReset_N_out ( pResetWires[265] ) , .pReset_W_out ( pResetWires[263] ) , - .pReset_E_out ( SYNOPSYS_UNCONNECTED_2552 ) , .Reset_S_in ( p3176 ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_2552 ) , .Reset_S_in ( p2583 ) , .Reset_N_out ( SYNOPSYS_UNCONNECTED_2553 ) , - .prog_clk_0_N_in ( prog_clk_0_wires[80] ) , .prog_clk_1_N_in ( p1267 ) , - .prog_clk_1_S_in ( p676 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[80] ) , .prog_clk_1_N_in ( p1863 ) , + .prog_clk_1_S_in ( p75 ) , .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_2554 ) , .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_2555 ) , - .prog_clk_2_N_in ( p2849 ) , .prog_clk_2_E_in ( p342 ) , - .prog_clk_2_S_in ( p63 ) , .prog_clk_2_W_in ( p904 ) , + .prog_clk_2_N_in ( p1980 ) , .prog_clk_2_E_in ( p641 ) , + .prog_clk_2_S_in ( p1682 ) , .prog_clk_2_W_in ( p61 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_2556 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_2557 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_2558 ) , @@ -107144,10 +111666,10 @@ sb_1__1_ sb_2__5_ ( .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_2563 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_2564 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_2565 ) , - .prog_clk_3_S_out ( prog_clk_3_wires[58] ) , .clk_1_N_in ( p1267 ) , - .clk_1_S_in ( p315 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_2566 ) , - .clk_1_W_out ( SYNOPSYS_UNCONNECTED_2567 ) , .clk_2_N_in ( p2631 ) , - .clk_2_E_in ( p597 ) , .clk_2_S_in ( p3136 ) , .clk_2_W_in ( p609 ) , + .prog_clk_3_S_out ( prog_clk_3_wires[58] ) , .clk_1_N_in ( p1863 ) , + .clk_1_S_in ( p917 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_2566 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_2567 ) , .clk_2_N_in ( p1980 ) , + .clk_2_E_in ( p480 ) , .clk_2_S_in ( p2400 ) , .clk_2_W_in ( p863 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_2568 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_2569 ) , .clk_2_N_out ( SYNOPSYS_UNCONNECTED_2570 ) , @@ -107203,20 +111725,20 @@ sb_1__1_ sb_2__6_ ( .chanx_right_out ( sb_1__1__16_chanx_right_out ) , .chany_bottom_out ( sb_1__1__16_chany_bottom_out ) , .chanx_left_out ( sb_1__1__16_chanx_left_out ) , - .ccff_tail ( sb_1__1__16_ccff_tail ) , .Test_en_S_in ( p2123 ) , + .ccff_tail ( sb_1__1__16_ccff_tail ) , .Test_en_S_in ( p1969 ) , .Test_en_N_out ( SYNOPSYS_UNCONNECTED_2579 ) , .pReset_S_in ( SYNOPSYS_UNCONNECTED_2580 ) , .pReset_E_in ( pResetWires[315] ) , .pReset_W_in ( SYNOPSYS_UNCONNECTED_2581 ) , .pReset_N_out ( pResetWires[314] ) , .pReset_W_out ( pResetWires[312] ) , - .pReset_E_out ( SYNOPSYS_UNCONNECTED_2582 ) , .Reset_S_in ( p3274 ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_2582 ) , .Reset_S_in ( p1969 ) , .Reset_N_out ( SYNOPSYS_UNCONNECTED_2583 ) , - .prog_clk_0_N_in ( prog_clk_0_wires[83] ) , .prog_clk_1_N_in ( p1725 ) , - .prog_clk_1_S_in ( p139 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[83] ) , .prog_clk_1_N_in ( p1510 ) , + .prog_clk_1_S_in ( p680 ) , .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_2584 ) , .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_2585 ) , - .prog_clk_2_N_in ( p2225 ) , .prog_clk_2_E_in ( p1092 ) , - .prog_clk_2_S_in ( p782 ) , .prog_clk_2_W_in ( p1169 ) , + .prog_clk_2_N_in ( p2240 ) , .prog_clk_2_E_in ( p129 ) , + .prog_clk_2_S_in ( p1778 ) , .prog_clk_2_W_in ( p1037 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_2586 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_2587 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_2588 ) , @@ -107228,10 +111750,10 @@ sb_1__1_ sb_2__6_ ( .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_2593 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_2594 ) , .prog_clk_3_N_out ( prog_clk_3_wires[52] ) , - .prog_clk_3_S_out ( prog_clk_3_wires[54] ) , .clk_1_N_in ( p1725 ) , - .clk_1_S_in ( p594 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_2595 ) , - .clk_1_W_out ( SYNOPSYS_UNCONNECTED_2596 ) , .clk_2_N_in ( p1921 ) , - .clk_2_E_in ( p343 ) , .clk_2_S_in ( p3228 ) , .clk_2_W_in ( p133 ) , + .prog_clk_3_S_out ( prog_clk_3_wires[54] ) , .clk_1_N_in ( p1510 ) , + .clk_1_S_in ( p969 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_2595 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_2596 ) , .clk_2_N_in ( p2283 ) , + .clk_2_E_in ( p981 ) , .clk_2_S_in ( p1672 ) , .clk_2_W_in ( p343 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_2597 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_2598 ) , .clk_2_N_out ( SYNOPSYS_UNCONNECTED_2599 ) , @@ -107286,20 +111808,20 @@ sb_1__1_ sb_2__7_ ( .chanx_right_out ( sb_1__1__17_chanx_right_out ) , .chany_bottom_out ( sb_1__1__17_chany_bottom_out ) , .chanx_left_out ( sb_1__1__17_chanx_left_out ) , - .ccff_tail ( sb_1__1__17_ccff_tail ) , .Test_en_S_in ( p3100 ) , + .ccff_tail ( sb_1__1__17_ccff_tail ) , .Test_en_S_in ( p2001 ) , .Test_en_N_out ( SYNOPSYS_UNCONNECTED_2607 ) , .pReset_S_in ( SYNOPSYS_UNCONNECTED_2608 ) , .pReset_E_in ( pResetWires[364] ) , .pReset_W_in ( SYNOPSYS_UNCONNECTED_2609 ) , .pReset_N_out ( pResetWires[363] ) , .pReset_W_out ( pResetWires[361] ) , - .pReset_E_out ( SYNOPSYS_UNCONNECTED_2610 ) , .Reset_S_in ( p3377 ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_2610 ) , .Reset_S_in ( p2001 ) , .Reset_N_out ( SYNOPSYS_UNCONNECTED_2611 ) , - .prog_clk_0_N_in ( prog_clk_0_wires[86] ) , .prog_clk_1_N_in ( p1932 ) , - .prog_clk_1_S_in ( p241 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[86] ) , .prog_clk_1_N_in ( p1295 ) , + .prog_clk_1_S_in ( p1044 ) , .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_2612 ) , .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_2613 ) , - .prog_clk_2_N_in ( p2145 ) , .prog_clk_2_E_in ( p587 ) , - .prog_clk_2_S_in ( p618 ) , .prog_clk_2_W_in ( p1054 ) , + .prog_clk_2_N_in ( p2230 ) , .prog_clk_2_E_in ( p395 ) , + .prog_clk_2_S_in ( p52 ) , .prog_clk_2_W_in ( p774 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_2614 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_2615 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_2616 ) , @@ -107311,10 +111833,10 @@ sb_1__1_ sb_2__7_ ( .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_2621 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_2622 ) , .prog_clk_3_N_out ( prog_clk_3_wires[56] ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_2623 ) , .clk_1_N_in ( p1932 ) , - .clk_1_S_in ( p403 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_2624 ) , - .clk_1_W_out ( SYNOPSYS_UNCONNECTED_2625 ) , .clk_2_N_in ( p2191 ) , - .clk_2_E_in ( p911 ) , .clk_2_S_in ( p3348 ) , .clk_2_W_in ( p303 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_2623 ) , .clk_1_N_in ( p1295 ) , + .clk_1_S_in ( p260 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_2624 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_2625 ) , .clk_2_N_in ( p1478 ) , + .clk_2_E_in ( p819 ) , .clk_2_S_in ( p1659 ) , .clk_2_W_in ( p332 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_2626 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_2627 ) , .clk_2_N_out ( SYNOPSYS_UNCONNECTED_2628 ) , @@ -107370,16 +111892,16 @@ sb_1__1_ sb_2__8_ ( .chanx_right_out ( sb_1__1__18_chanx_right_out ) , .chany_bottom_out ( sb_1__1__18_chany_bottom_out ) , .chanx_left_out ( sb_1__1__18_chanx_left_out ) , - .ccff_tail ( sb_1__1__18_ccff_tail ) , .Test_en_S_in ( p1571 ) , + .ccff_tail ( sb_1__1__18_ccff_tail ) , .Test_en_S_in ( p1467 ) , .Test_en_N_out ( SYNOPSYS_UNCONNECTED_2637 ) , .pReset_S_in ( SYNOPSYS_UNCONNECTED_2638 ) , .pReset_E_in ( pResetWires[413] ) , .pReset_W_in ( SYNOPSYS_UNCONNECTED_2639 ) , .pReset_N_out ( pResetWires[412] ) , .pReset_W_out ( pResetWires[410] ) , - .pReset_E_out ( SYNOPSYS_UNCONNECTED_2640 ) , .Reset_S_in ( p1571 ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_2640 ) , .Reset_S_in ( p1467 ) , .Reset_N_out ( SYNOPSYS_UNCONNECTED_2641 ) , - .prog_clk_0_N_in ( prog_clk_0_wires[89] ) , .prog_clk_1_N_in ( p1394 ) , - .prog_clk_1_S_in ( p880 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[89] ) , .prog_clk_1_N_in ( p1919 ) , + .prog_clk_1_S_in ( p145 ) , .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_2642 ) , .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_2643 ) , .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_2644 ) , @@ -107397,8 +111919,8 @@ sb_1__1_ sb_2__8_ ( .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_2653 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_2654 ) , .prog_clk_3_N_out ( prog_clk_3_wires[62] ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_2655 ) , .clk_1_N_in ( p1394 ) , - .clk_1_S_in ( p252 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_2656 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_2655 ) , .clk_1_N_in ( p1919 ) , + .clk_1_S_in ( p1039 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_2656 ) , .clk_1_W_out ( SYNOPSYS_UNCONNECTED_2657 ) , .clk_2_N_in ( SYNOPSYS_UNCONNECTED_2658 ) , .clk_2_E_in ( SYNOPSYS_UNCONNECTED_2659 ) , @@ -107459,20 +111981,20 @@ sb_1__1_ sb_2__9_ ( .chanx_right_out ( sb_1__1__19_chanx_right_out ) , .chany_bottom_out ( sb_1__1__19_chany_bottom_out ) , .chanx_left_out ( sb_1__1__19_chanx_left_out ) , - .ccff_tail ( sb_1__1__19_ccff_tail ) , .Test_en_S_in ( p1864 ) , + .ccff_tail ( sb_1__1__19_ccff_tail ) , .Test_en_S_in ( p2525 ) , .Test_en_N_out ( SYNOPSYS_UNCONNECTED_2671 ) , .pReset_S_in ( SYNOPSYS_UNCONNECTED_2672 ) , .pReset_E_in ( pResetWires[462] ) , .pReset_W_in ( SYNOPSYS_UNCONNECTED_2673 ) , .pReset_N_out ( pResetWires[461] ) , .pReset_W_out ( pResetWires[459] ) , - .pReset_E_out ( SYNOPSYS_UNCONNECTED_2674 ) , .Reset_S_in ( p3452 ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_2674 ) , .Reset_S_in ( p2525 ) , .Reset_N_out ( SYNOPSYS_UNCONNECTED_2675 ) , - .prog_clk_0_N_in ( prog_clk_0_wires[92] ) , .prog_clk_1_N_in ( p1873 ) , - .prog_clk_1_S_in ( p912 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[92] ) , .prog_clk_1_N_in ( p1299 ) , + .prog_clk_1_S_in ( p1211 ) , .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_2676 ) , .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_2677 ) , - .prog_clk_2_N_in ( p2193 ) , .prog_clk_2_E_in ( p54 ) , - .prog_clk_2_S_in ( p533 ) , .prog_clk_2_W_in ( p204 ) , + .prog_clk_2_N_in ( p2809 ) , .prog_clk_2_E_in ( p538 ) , + .prog_clk_2_S_in ( p390 ) , .prog_clk_2_W_in ( p453 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_2678 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_2679 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_2680 ) , @@ -107484,10 +112006,10 @@ sb_1__1_ sb_2__9_ ( .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_2685 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_2686 ) , .prog_clk_3_N_out ( prog_clk_3_wires[66] ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_2687 ) , .clk_1_N_in ( p1873 ) , - .clk_1_S_in ( p173 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_2688 ) , - .clk_1_W_out ( SYNOPSYS_UNCONNECTED_2689 ) , .clk_2_N_in ( p2193 ) , - .clk_2_E_in ( p326 ) , .clk_2_S_in ( p3447 ) , .clk_2_W_in ( p1137 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_2687 ) , .clk_1_N_in ( p1299 ) , + .clk_1_S_in ( p214 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_2688 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_2689 ) , .clk_2_N_in ( p1650 ) , + .clk_2_E_in ( p659 ) , .clk_2_S_in ( p2395 ) , .clk_2_W_in ( p134 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_2690 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_2691 ) , .clk_2_N_out ( SYNOPSYS_UNCONNECTED_2692 ) , @@ -107543,16 +112065,16 @@ sb_1__1_ sb_2__10_ ( .chanx_right_out ( sb_1__1__20_chanx_right_out ) , .chany_bottom_out ( sb_1__1__20_chany_bottom_out ) , .chanx_left_out ( sb_1__1__20_chanx_left_out ) , - .ccff_tail ( sb_1__1__20_ccff_tail ) , .Test_en_S_in ( p2943 ) , + .ccff_tail ( sb_1__1__20_ccff_tail ) , .Test_en_S_in ( p2300 ) , .Test_en_N_out ( SYNOPSYS_UNCONNECTED_2701 ) , .pReset_S_in ( SYNOPSYS_UNCONNECTED_2702 ) , .pReset_E_in ( pResetWires[511] ) , .pReset_W_in ( SYNOPSYS_UNCONNECTED_2703 ) , .pReset_N_out ( pResetWires[510] ) , .pReset_W_out ( pResetWires[508] ) , - .pReset_E_out ( SYNOPSYS_UNCONNECTED_2704 ) , .Reset_S_in ( p2959 ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_2704 ) , .Reset_S_in ( p2300 ) , .Reset_N_out ( SYNOPSYS_UNCONNECTED_2705 ) , - .prog_clk_0_N_in ( prog_clk_0_wires[95] ) , .prog_clk_1_N_in ( p1385 ) , - .prog_clk_1_S_in ( p341 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[95] ) , .prog_clk_1_N_in ( p1429 ) , + .prog_clk_1_S_in ( p181 ) , .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_2706 ) , .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_2707 ) , .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_2708 ) , @@ -107563,13 +112085,13 @@ sb_1__1_ sb_2__10_ ( .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_2711 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_2712 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_2713 ) , - .prog_clk_3_W_in ( p1565 ) , .prog_clk_3_E_in ( p190 ) , - .prog_clk_3_S_in ( p1651 ) , .prog_clk_3_N_in ( p15 ) , + .prog_clk_3_W_in ( p1613 ) , .prog_clk_3_E_in ( p543 ) , + .prog_clk_3_S_in ( p246 ) , .prog_clk_3_N_in ( p152 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_2714 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_2715 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_2716 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_2717 ) , .clk_1_N_in ( p1385 ) , - .clk_1_S_in ( p908 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_2718 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_2717 ) , .clk_1_N_in ( p1429 ) , + .clk_1_S_in ( p1080 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_2718 ) , .clk_1_W_out ( SYNOPSYS_UNCONNECTED_2719 ) , .clk_2_N_in ( SYNOPSYS_UNCONNECTED_2720 ) , .clk_2_E_in ( SYNOPSYS_UNCONNECTED_2721 ) , @@ -107578,8 +112100,8 @@ sb_1__1_ sb_2__10_ ( .clk_2_W_out ( clk_2_wires[21] ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_2723 ) , .clk_2_N_out ( SYNOPSYS_UNCONNECTED_2724 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_2725 ) , .clk_3_W_in ( p1565 ) , - .clk_3_E_in ( p273 ) , .clk_3_S_in ( p2897 ) , .clk_3_N_in ( p540 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_2725 ) , .clk_3_W_in ( p1613 ) , + .clk_3_E_in ( p320 ) , .clk_3_S_in ( p2111 ) , .clk_3_N_in ( p677 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_2726 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_2727 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_2728 ) , @@ -107627,38 +112149,38 @@ sb_1__1_ sb_2__11_ ( .chanx_right_out ( sb_1__1__21_chanx_right_out ) , .chany_bottom_out ( sb_1__1__21_chany_bottom_out ) , .chanx_left_out ( sb_1__1__21_chanx_left_out ) , - .ccff_tail ( sb_1__1__21_ccff_tail ) , .Test_en_S_in ( p2625 ) , + .ccff_tail ( sb_1__1__21_ccff_tail ) , .Test_en_S_in ( p1648 ) , .Test_en_N_out ( SYNOPSYS_UNCONNECTED_2731 ) , .pReset_S_in ( SYNOPSYS_UNCONNECTED_2732 ) , .pReset_E_in ( pResetWires[560] ) , .pReset_W_in ( SYNOPSYS_UNCONNECTED_2733 ) , .pReset_N_out ( pResetWires[559] ) , .pReset_W_out ( pResetWires[557] ) , - .pReset_E_out ( SYNOPSYS_UNCONNECTED_2734 ) , .Reset_S_in ( p2625 ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_2734 ) , .Reset_S_in ( p1648 ) , .Reset_N_out ( SYNOPSYS_UNCONNECTED_2735 ) , - .prog_clk_0_N_in ( prog_clk_0_wires[98] ) , .prog_clk_1_N_in ( p2182 ) , - .prog_clk_1_S_in ( p239 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[98] ) , .prog_clk_1_N_in ( p2031 ) , + .prog_clk_1_S_in ( p830 ) , .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_2736 ) , .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_2737 ) , - .prog_clk_2_N_in ( p3356 ) , .prog_clk_2_E_in ( p1333 ) , - .prog_clk_2_S_in ( p1231 ) , .prog_clk_2_W_in ( p1291 ) , + .prog_clk_2_N_in ( p3504 ) , .prog_clk_2_E_in ( p508 ) , + .prog_clk_2_S_in ( p1332 ) , .prog_clk_2_W_in ( p865 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_2738 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_2739 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_2740 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_2741 ) , - .prog_clk_3_W_in ( p2848 ) , .prog_clk_3_E_in ( p145 ) , - .prog_clk_3_S_in ( p102 ) , .prog_clk_3_N_in ( p3345 ) , + .prog_clk_3_W_in ( p2369 ) , .prog_clk_3_E_in ( p158 ) , + .prog_clk_3_S_in ( p196 ) , .prog_clk_3_N_in ( p3477 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_2742 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_2743 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_2744 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_2745 ) , .clk_1_N_in ( p2182 ) , - .clk_1_S_in ( p1130 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_2746 ) , - .clk_1_W_out ( SYNOPSYS_UNCONNECTED_2747 ) , .clk_2_N_in ( p3488 ) , - .clk_2_E_in ( p888 ) , .clk_2_S_in ( p2530 ) , .clk_2_W_in ( p2728 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_2745 ) , .clk_1_N_in ( p2031 ) , + .clk_1_S_in ( p106 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_2746 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_2747 ) , .clk_2_N_in ( p2744 ) , + .clk_2_E_in ( p632 ) , .clk_2_S_in ( p351 ) , .clk_2_W_in ( p3516 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_2748 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_2749 ) , .clk_2_N_out ( SYNOPSYS_UNCONNECTED_2750 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_2751 ) , .clk_3_W_in ( p2848 ) , - .clk_3_E_in ( p971 ) , .clk_3_S_in ( p1246 ) , .clk_3_N_in ( p3484 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_2751 ) , .clk_3_W_in ( p3531 ) , + .clk_3_E_in ( p912 ) , .clk_3_S_in ( p1203 ) , .clk_3_N_in ( p2714 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_2752 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_2753 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_2754 ) , @@ -107706,27 +112228,27 @@ sb_1__1_ sb_3__1_ ( .chanx_right_out ( sb_1__1__22_chanx_right_out ) , .chany_bottom_out ( sb_1__1__22_chany_bottom_out ) , .chanx_left_out ( sb_1__1__22_chanx_left_out ) , - .ccff_tail ( sb_1__1__22_ccff_tail ) , .Test_en_S_in ( p2839 ) , + .ccff_tail ( sb_1__1__22_ccff_tail ) , .Test_en_S_in ( p2249 ) , .Test_en_N_out ( SYNOPSYS_UNCONNECTED_2757 ) , .pReset_S_in ( SYNOPSYS_UNCONNECTED_2758 ) , .pReset_E_in ( pResetWires[74] ) , .pReset_W_in ( SYNOPSYS_UNCONNECTED_2759 ) , .pReset_N_out ( pResetWires[73] ) , .pReset_W_out ( pResetWires[71] ) , - .pReset_E_out ( SYNOPSYS_UNCONNECTED_2760 ) , .Reset_S_in ( p3376 ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_2760 ) , .Reset_S_in ( p2316 ) , .Reset_N_out ( SYNOPSYS_UNCONNECTED_2761 ) , .prog_clk_0_N_in ( prog_clk_0_wires[106] ) , .prog_clk_1_N_in ( prog_clk_2_wires[30] ) , .prog_clk_1_S_in ( SYNOPSYS_UNCONNECTED_2762 ) , .prog_clk_1_E_out ( prog_clk_1_wires[43] ) , - .prog_clk_1_W_out ( prog_clk_1_wires[44] ) , .prog_clk_2_N_in ( p3071 ) , - .prog_clk_2_E_in ( p824 ) , .prog_clk_2_S_in ( p19 ) , - .prog_clk_2_W_in ( p1123 ) , + .prog_clk_1_W_out ( prog_clk_1_wires[44] ) , .prog_clk_2_N_in ( p3403 ) , + .prog_clk_2_E_in ( p155 ) , .prog_clk_2_S_in ( p816 ) , + .prog_clk_2_W_in ( p942 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_2763 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_2764 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_2765 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_2766 ) , - .prog_clk_3_W_in ( p2662 ) , .prog_clk_3_E_in ( p159 ) , - .prog_clk_3_S_in ( p1459 ) , .prog_clk_3_N_in ( p3044 ) , + .prog_clk_3_W_in ( p2756 ) , .prog_clk_3_E_in ( p872 ) , + .prog_clk_3_S_in ( p84 ) , .prog_clk_3_N_in ( p3380 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_2767 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_2768 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_2769 ) , @@ -107734,12 +112256,12 @@ sb_1__1_ sb_3__1_ ( .clk_1_N_in ( clk_2_wires[30] ) , .clk_1_S_in ( SYNOPSYS_UNCONNECTED_2771 ) , .clk_1_E_out ( clk_1_wires[43] ) , .clk_1_W_out ( clk_1_wires[44] ) , - .clk_2_N_in ( p3103 ) , .clk_2_E_in ( p1002 ) , .clk_2_S_in ( p3347 ) , - .clk_2_W_in ( p2590 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_2772 ) , + .clk_2_N_in ( p2027 ) , .clk_2_E_in ( p1190 ) , .clk_2_S_in ( p1150 ) , + .clk_2_W_in ( p3566 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_2772 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_2773 ) , .clk_2_N_out ( SYNOPSYS_UNCONNECTED_2774 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_2775 ) , .clk_3_W_in ( p2662 ) , - .clk_3_E_in ( p598 ) , .clk_3_S_in ( p681 ) , .clk_3_N_in ( p3029 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_2775 ) , .clk_3_W_in ( p3574 ) , + .clk_3_E_in ( p858 ) , .clk_3_S_in ( p2114 ) , .clk_3_N_in ( p1668 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_2776 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_2777 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_2778 ) , @@ -107787,16 +112309,16 @@ sb_1__1_ sb_3__2_ ( .chanx_right_out ( sb_1__1__23_chanx_right_out ) , .chany_bottom_out ( sb_1__1__23_chany_bottom_out ) , .chanx_left_out ( sb_1__1__23_chanx_left_out ) , - .ccff_tail ( sb_1__1__23_ccff_tail ) , .Test_en_S_in ( p2845 ) , + .ccff_tail ( sb_1__1__23_ccff_tail ) , .Test_en_S_in ( p2260 ) , .Test_en_N_out ( SYNOPSYS_UNCONNECTED_2781 ) , .pReset_S_in ( SYNOPSYS_UNCONNECTED_2782 ) , .pReset_E_in ( pResetWires[123] ) , .pReset_W_in ( SYNOPSYS_UNCONNECTED_2783 ) , .pReset_N_out ( pResetWires[122] ) , .pReset_W_out ( pResetWires[120] ) , - .pReset_E_out ( SYNOPSYS_UNCONNECTED_2784 ) , .Reset_S_in ( p2845 ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_2784 ) , .Reset_S_in ( p2260 ) , .Reset_N_out ( SYNOPSYS_UNCONNECTED_2785 ) , - .prog_clk_0_N_in ( prog_clk_0_wires[109] ) , .prog_clk_1_N_in ( p1558 ) , - .prog_clk_1_S_in ( p848 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[109] ) , .prog_clk_1_N_in ( p1872 ) , + .prog_clk_1_S_in ( p919 ) , .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_2786 ) , .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_2787 ) , .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_2788 ) , @@ -107807,13 +112329,13 @@ sb_1__1_ sb_3__2_ ( .prog_clk_2_S_out ( prog_clk_2_wires[29] ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_2792 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_2793 ) , - .prog_clk_3_W_in ( p1518 ) , .prog_clk_3_E_in ( p1026 ) , - .prog_clk_3_S_in ( p855 ) , .prog_clk_3_N_in ( p579 ) , + .prog_clk_3_W_in ( p1387 ) , .prog_clk_3_E_in ( p240 ) , + .prog_clk_3_S_in ( p35 ) , .prog_clk_3_N_in ( p220 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_2794 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_2795 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_2796 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_2797 ) , .clk_1_N_in ( p1558 ) , - .clk_1_S_in ( p81 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_2798 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_2797 ) , .clk_1_N_in ( p1872 ) , + .clk_1_S_in ( p606 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_2798 ) , .clk_1_W_out ( SYNOPSYS_UNCONNECTED_2799 ) , .clk_2_N_in ( SYNOPSYS_UNCONNECTED_2800 ) , .clk_2_E_in ( clk_2_wires[28] ) , @@ -107822,8 +112344,8 @@ sb_1__1_ sb_3__2_ ( .clk_2_W_out ( SYNOPSYS_UNCONNECTED_2803 ) , .clk_2_S_out ( clk_2_wires[29] ) , .clk_2_N_out ( SYNOPSYS_UNCONNECTED_2804 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_2805 ) , .clk_3_W_in ( p1518 ) , - .clk_3_E_in ( p325 ) , .clk_3_S_in ( p2739 ) , .clk_3_N_in ( p410 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_2805 ) , .clk_3_W_in ( p1387 ) , + .clk_3_E_in ( p961 ) , .clk_3_S_in ( p2107 ) , .clk_3_N_in ( p1718 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_2806 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_2807 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_2808 ) , @@ -107871,27 +112393,27 @@ sb_1__1_ sb_3__3_ ( .chanx_right_out ( sb_1__1__24_chanx_right_out ) , .chany_bottom_out ( sb_1__1__24_chany_bottom_out ) , .chanx_left_out ( sb_1__1__24_chanx_left_out ) , - .ccff_tail ( sb_1__1__24_ccff_tail ) , .Test_en_S_in ( p2442 ) , + .ccff_tail ( sb_1__1__24_ccff_tail ) , .Test_en_S_in ( p2346 ) , .Test_en_N_out ( SYNOPSYS_UNCONNECTED_2811 ) , .pReset_S_in ( SYNOPSYS_UNCONNECTED_2812 ) , .pReset_E_in ( pResetWires[172] ) , .pReset_W_in ( SYNOPSYS_UNCONNECTED_2813 ) , .pReset_N_out ( pResetWires[171] ) , .pReset_W_out ( pResetWires[169] ) , - .pReset_E_out ( SYNOPSYS_UNCONNECTED_2814 ) , .Reset_S_in ( p2442 ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_2814 ) , .Reset_S_in ( p2346 ) , .Reset_N_out ( SYNOPSYS_UNCONNECTED_2815 ) , .prog_clk_0_N_in ( prog_clk_0_wires[112] ) , .prog_clk_1_N_in ( prog_clk_2_wires[41] ) , .prog_clk_1_S_in ( SYNOPSYS_UNCONNECTED_2816 ) , .prog_clk_1_E_out ( prog_clk_1_wires[50] ) , - .prog_clk_1_W_out ( prog_clk_1_wires[51] ) , .prog_clk_2_N_in ( p3502 ) , - .prog_clk_2_E_in ( p35 ) , .prog_clk_2_S_in ( p1122 ) , - .prog_clk_2_W_in ( p1132 ) , + .prog_clk_1_W_out ( prog_clk_1_wires[51] ) , .prog_clk_2_N_in ( p3455 ) , + .prog_clk_2_E_in ( p935 ) , .prog_clk_2_S_in ( p361 ) , + .prog_clk_2_W_in ( p179 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_2817 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_2818 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_2819 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_2820 ) , - .prog_clk_3_W_in ( p2779 ) , .prog_clk_3_E_in ( p937 ) , - .prog_clk_3_S_in ( p200 ) , .prog_clk_3_N_in ( p3500 ) , + .prog_clk_3_W_in ( p2621 ) , .prog_clk_3_E_in ( p207 ) , + .prog_clk_3_S_in ( p1278 ) , .prog_clk_3_N_in ( p3444 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_2821 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_2822 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_2823 ) , @@ -107899,12 +112421,12 @@ sb_1__1_ sb_3__3_ ( .clk_1_N_in ( clk_2_wires[41] ) , .clk_1_S_in ( SYNOPSYS_UNCONNECTED_2825 ) , .clk_1_E_out ( clk_1_wires[50] ) , .clk_1_W_out ( clk_1_wires[51] ) , - .clk_2_N_in ( p3061 ) , .clk_2_E_in ( p502 ) , .clk_2_S_in ( p2310 ) , - .clk_2_W_in ( p2745 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_2826 ) , + .clk_2_N_in ( p3407 ) , .clk_2_E_in ( p647 ) , .clk_2_S_in ( p1177 ) , + .clk_2_W_in ( p3067 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_2826 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_2827 ) , .clk_2_N_out ( SYNOPSYS_UNCONNECTED_2828 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_2829 ) , .clk_3_W_in ( p2779 ) , - .clk_3_E_in ( p680 ) , .clk_3_S_in ( p1193 ) , .clk_3_N_in ( p3011 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_2829 ) , .clk_3_W_in ( p3106 ) , + .clk_3_E_in ( p598 ) , .clk_3_S_in ( p2135 ) , .clk_3_N_in ( p3391 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_2830 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_2831 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_2832 ) , @@ -107952,16 +112474,16 @@ sb_1__1_ sb_3__4_ ( .chanx_right_out ( sb_1__1__25_chanx_right_out ) , .chany_bottom_out ( sb_1__1__25_chany_bottom_out ) , .chanx_left_out ( sb_1__1__25_chanx_left_out ) , - .ccff_tail ( sb_1__1__25_ccff_tail ) , .Test_en_S_in ( p2408 ) , + .ccff_tail ( sb_1__1__25_ccff_tail ) , .Test_en_S_in ( p2184 ) , .Test_en_N_out ( SYNOPSYS_UNCONNECTED_2835 ) , .pReset_S_in ( SYNOPSYS_UNCONNECTED_2836 ) , .pReset_E_in ( pResetWires[221] ) , .pReset_W_in ( SYNOPSYS_UNCONNECTED_2837 ) , .pReset_N_out ( pResetWires[220] ) , .pReset_W_out ( pResetWires[218] ) , - .pReset_E_out ( SYNOPSYS_UNCONNECTED_2838 ) , .Reset_S_in ( p2408 ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_2838 ) , .Reset_S_in ( p2184 ) , .Reset_N_out ( SYNOPSYS_UNCONNECTED_2839 ) , - .prog_clk_0_N_in ( prog_clk_0_wires[115] ) , .prog_clk_1_N_in ( p2254 ) , - .prog_clk_1_S_in ( p1010 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[115] ) , .prog_clk_1_N_in ( p1994 ) , + .prog_clk_1_S_in ( p82 ) , .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_2840 ) , .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_2841 ) , .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_2842 ) , @@ -107972,13 +112494,13 @@ sb_1__1_ sb_3__4_ ( .prog_clk_2_S_out ( prog_clk_2_wires[40] ) , .prog_clk_2_N_out ( prog_clk_2_wires[38] ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_2846 ) , - .prog_clk_3_W_in ( p1613 ) , .prog_clk_3_E_in ( p778 ) , - .prog_clk_3_S_in ( p475 ) , .prog_clk_3_N_in ( p2026 ) , + .prog_clk_3_W_in ( p2202 ) , .prog_clk_3_E_in ( p189 ) , + .prog_clk_3_S_in ( p625 ) , .prog_clk_3_N_in ( p1032 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_2847 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_2848 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_2849 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_2850 ) , .clk_1_N_in ( p2254 ) , - .clk_1_S_in ( p116 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_2851 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_2850 ) , .clk_1_N_in ( p1994 ) , + .clk_1_S_in ( p1259 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_2851 ) , .clk_1_W_out ( SYNOPSYS_UNCONNECTED_2852 ) , .clk_2_N_in ( SYNOPSYS_UNCONNECTED_2853 ) , .clk_2_E_in ( clk_2_wires[37] ) , @@ -107986,8 +112508,8 @@ sb_1__1_ sb_3__4_ ( .clk_2_W_in ( SYNOPSYS_UNCONNECTED_2855 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_2856 ) , .clk_2_S_out ( clk_2_wires[40] ) , .clk_2_N_out ( clk_2_wires[38] ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_2857 ) , .clk_3_W_in ( p1613 ) , - .clk_3_E_in ( p1624 ) , .clk_3_S_in ( p2337 ) , .clk_3_N_in ( p1991 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_2857 ) , .clk_3_W_in ( p2202 ) , + .clk_3_E_in ( p1753 ) , .clk_3_S_in ( p2072 ) , .clk_3_N_in ( p1689 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_2858 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_2859 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_2860 ) , @@ -108035,40 +112557,40 @@ sb_1__1_ sb_3__5_ ( .chanx_right_out ( sb_1__1__26_chanx_right_out ) , .chany_bottom_out ( sb_1__1__26_chany_bottom_out ) , .chanx_left_out ( sb_1__1__26_chanx_left_out ) , - .ccff_tail ( sb_1__1__26_ccff_tail ) , .Test_en_S_in ( p2420 ) , + .ccff_tail ( sb_1__1__26_ccff_tail ) , .Test_en_S_in ( p2234 ) , .Test_en_N_out ( SYNOPSYS_UNCONNECTED_2863 ) , .pReset_S_in ( SYNOPSYS_UNCONNECTED_2864 ) , .pReset_E_in ( pResetWires[270] ) , .pReset_W_in ( SYNOPSYS_UNCONNECTED_2865 ) , .pReset_N_out ( pResetWires[269] ) , .pReset_W_out ( pResetWires[267] ) , - .pReset_E_out ( SYNOPSYS_UNCONNECTED_2866 ) , .Reset_S_in ( p3332 ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_2866 ) , .Reset_S_in ( p2234 ) , .Reset_N_out ( SYNOPSYS_UNCONNECTED_2867 ) , .prog_clk_0_N_in ( prog_clk_0_wires[118] ) , .prog_clk_1_N_in ( SYNOPSYS_UNCONNECTED_2868 ) , .prog_clk_1_S_in ( prog_clk_2_wires[39] ) , .prog_clk_1_E_out ( prog_clk_1_wires[57] ) , - .prog_clk_1_W_out ( prog_clk_1_wires[58] ) , .prog_clk_2_N_in ( p3406 ) , - .prog_clk_2_E_in ( p651 ) , .prog_clk_2_S_in ( p711 ) , - .prog_clk_2_W_in ( p495 ) , + .prog_clk_1_W_out ( prog_clk_1_wires[58] ) , .prog_clk_2_N_in ( p3161 ) , + .prog_clk_2_E_in ( p228 ) , .prog_clk_2_S_in ( p558 ) , + .prog_clk_2_W_in ( p949 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_2869 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_2870 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_2871 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_2872 ) , - .prog_clk_3_W_in ( p2783 ) , .prog_clk_3_E_in ( p1161 ) , - .prog_clk_3_S_in ( p1336 ) , .prog_clk_3_N_in ( p3379 ) , + .prog_clk_3_W_in ( p3027 ) , .prog_clk_3_E_in ( p685 ) , + .prog_clk_3_S_in ( p1264 ) , .prog_clk_3_N_in ( p3061 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_2873 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_2874 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_2875 ) , .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_2876 ) , .clk_1_N_in ( SYNOPSYS_UNCONNECTED_2877 ) , .clk_1_S_in ( clk_2_wires[39] ) , .clk_1_E_out ( clk_1_wires[57] ) , - .clk_1_W_out ( clk_1_wires[58] ) , .clk_2_N_in ( p1574 ) , - .clk_2_E_in ( p110 ) , .clk_2_S_in ( p3296 ) , .clk_2_W_in ( p2733 ) , + .clk_1_W_out ( clk_1_wires[58] ) , .clk_2_N_in ( p3102 ) , + .clk_2_E_in ( p562 ) , .clk_2_S_in ( p955 ) , .clk_2_W_in ( p3308 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_2878 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_2879 ) , .clk_2_N_out ( SYNOPSYS_UNCONNECTED_2880 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_2881 ) , .clk_3_W_in ( p2783 ) , - .clk_3_E_in ( p503 ) , .clk_3_S_in ( p1238 ) , .clk_3_N_in ( p367 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_2881 ) , .clk_3_W_in ( p3328 ) , + .clk_3_E_in ( p1198 ) , .clk_3_S_in ( p2077 ) , .clk_3_N_in ( p3069 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_2882 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_2883 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_2884 ) , @@ -108116,20 +112638,20 @@ sb_1__1_ sb_3__6_ ( .chanx_right_out ( sb_1__1__27_chanx_right_out ) , .chany_bottom_out ( sb_1__1__27_chany_bottom_out ) , .chanx_left_out ( sb_1__1__27_chanx_left_out ) , - .ccff_tail ( sb_1__1__27_ccff_tail ) , .Test_en_S_in ( p3097 ) , + .ccff_tail ( sb_1__1__27_ccff_tail ) , .Test_en_S_in ( p2622 ) , .Test_en_N_out ( SYNOPSYS_UNCONNECTED_2887 ) , .pReset_S_in ( SYNOPSYS_UNCONNECTED_2888 ) , .pReset_E_in ( pResetWires[319] ) , .pReset_W_in ( SYNOPSYS_UNCONNECTED_2889 ) , .pReset_N_out ( pResetWires[318] ) , .pReset_W_out ( pResetWires[316] ) , - .pReset_E_out ( SYNOPSYS_UNCONNECTED_2890 ) , .Reset_S_in ( p3429 ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_2890 ) , .Reset_S_in ( p2622 ) , .Reset_N_out ( SYNOPSYS_UNCONNECTED_2891 ) , - .prog_clk_0_N_in ( prog_clk_0_wires[121] ) , .prog_clk_1_N_in ( p1498 ) , - .prog_clk_1_S_in ( p1022 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[121] ) , .prog_clk_1_N_in ( p1652 ) , + .prog_clk_1_S_in ( p958 ) , .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_2892 ) , .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_2893 ) , - .prog_clk_2_N_in ( p1942 ) , .prog_clk_2_E_in ( p30 ) , - .prog_clk_2_S_in ( p364 ) , .prog_clk_2_W_in ( p1222 ) , + .prog_clk_2_N_in ( p2628 ) , .prog_clk_2_E_in ( p297 ) , + .prog_clk_2_S_in ( p404 ) , .prog_clk_2_W_in ( p954 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_2894 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_2895 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_2896 ) , @@ -108141,10 +112663,10 @@ sb_1__1_ sb_3__6_ ( .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_2901 ) , .prog_clk_3_W_out ( prog_clk_3_wires[50] ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_2902 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_2903 ) , .clk_1_N_in ( p1498 ) , - .clk_1_S_in ( p34 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_2904 ) , - .clk_1_W_out ( SYNOPSYS_UNCONNECTED_2905 ) , .clk_2_N_in ( p1942 ) , - .clk_2_E_in ( p1144 ) , .clk_2_S_in ( p3416 ) , .clk_2_W_in ( p338 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_2903 ) , .clk_1_N_in ( p1652 ) , + .clk_1_S_in ( p119 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_2904 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_2905 ) , .clk_2_N_in ( p2317 ) , + .clk_2_E_in ( p205 ) , .clk_2_S_in ( p2449 ) , .clk_2_W_in ( p413 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_2906 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_2907 ) , .clk_2_N_out ( SYNOPSYS_UNCONNECTED_2908 ) , @@ -108200,27 +112722,27 @@ sb_1__1_ sb_3__7_ ( .chanx_right_out ( sb_1__1__28_chanx_right_out ) , .chany_bottom_out ( sb_1__1__28_chany_bottom_out ) , .chanx_left_out ( sb_1__1__28_chanx_left_out ) , - .ccff_tail ( sb_1__1__28_ccff_tail ) , .Test_en_S_in ( p2409 ) , + .ccff_tail ( sb_1__1__28_ccff_tail ) , .Test_en_S_in ( p1973 ) , .Test_en_N_out ( SYNOPSYS_UNCONNECTED_2917 ) , .pReset_S_in ( SYNOPSYS_UNCONNECTED_2918 ) , .pReset_E_in ( pResetWires[368] ) , .pReset_W_in ( SYNOPSYS_UNCONNECTED_2919 ) , .pReset_N_out ( pResetWires[367] ) , .pReset_W_out ( pResetWires[365] ) , - .pReset_E_out ( SYNOPSYS_UNCONNECTED_2920 ) , .Reset_S_in ( p2409 ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_2920 ) , .Reset_S_in ( p1973 ) , .Reset_N_out ( SYNOPSYS_UNCONNECTED_2921 ) , .prog_clk_0_N_in ( prog_clk_0_wires[124] ) , .prog_clk_1_N_in ( prog_clk_2_wires[54] ) , .prog_clk_1_S_in ( SYNOPSYS_UNCONNECTED_2922 ) , .prog_clk_1_E_out ( prog_clk_1_wires[64] ) , - .prog_clk_1_W_out ( prog_clk_1_wires[65] ) , .prog_clk_2_N_in ( p2942 ) , - .prog_clk_2_E_in ( p126 ) , .prog_clk_2_S_in ( p700 ) , - .prog_clk_2_W_in ( p1275 ) , + .prog_clk_1_W_out ( prog_clk_1_wires[65] ) , .prog_clk_2_N_in ( p2555 ) , + .prog_clk_2_E_in ( p128 ) , .prog_clk_2_S_in ( p971 ) , + .prog_clk_2_W_in ( p299 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_2923 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_2924 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_2925 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_2926 ) , - .prog_clk_3_W_in ( p3245 ) , .prog_clk_3_E_in ( p1254 ) , - .prog_clk_3_S_in ( p481 ) , .prog_clk_3_N_in ( p2895 ) , + .prog_clk_3_W_in ( p2579 ) , .prog_clk_3_E_in ( p719 ) , + .prog_clk_3_S_in ( p131 ) , .prog_clk_3_N_in ( p2437 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_2927 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_2928 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_2929 ) , @@ -108228,12 +112750,12 @@ sb_1__1_ sb_3__7_ ( .clk_1_N_in ( clk_2_wires[54] ) , .clk_1_S_in ( SYNOPSYS_UNCONNECTED_2931 ) , .clk_1_E_out ( clk_1_wires[64] ) , .clk_1_W_out ( clk_1_wires[65] ) , - .clk_2_N_in ( p2818 ) , .clk_2_E_in ( p1045 ) , .clk_2_S_in ( p2311 ) , - .clk_2_W_in ( p3224 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_2932 ) , + .clk_2_N_in ( p2973 ) , .clk_2_E_in ( p34 ) , .clk_2_S_in ( p1262 ) , + .clk_2_W_in ( p3368 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_2932 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_2933 ) , .clk_2_N_out ( SYNOPSYS_UNCONNECTED_2934 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_2935 ) , .clk_3_W_in ( p3261 ) , - .clk_3_E_in ( p1036 ) , .clk_3_S_in ( p433 ) , .clk_3_N_in ( p2764 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_2935 ) , .clk_3_W_in ( p3419 ) , + .clk_3_E_in ( p1081 ) , .clk_3_S_in ( p1784 ) , .clk_3_N_in ( p2871 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_2936 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_2937 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_2938 ) , @@ -108281,16 +112803,16 @@ sb_1__1_ sb_3__8_ ( .chanx_right_out ( sb_1__1__29_chanx_right_out ) , .chany_bottom_out ( sb_1__1__29_chany_bottom_out ) , .chanx_left_out ( sb_1__1__29_chanx_left_out ) , - .ccff_tail ( sb_1__1__29_ccff_tail ) , .Test_en_S_in ( p2833 ) , + .ccff_tail ( sb_1__1__29_ccff_tail ) , .Test_en_S_in ( p2041 ) , .Test_en_N_out ( SYNOPSYS_UNCONNECTED_2941 ) , .pReset_S_in ( SYNOPSYS_UNCONNECTED_2942 ) , .pReset_E_in ( pResetWires[417] ) , .pReset_W_in ( SYNOPSYS_UNCONNECTED_2943 ) , .pReset_N_out ( pResetWires[416] ) , .pReset_W_out ( pResetWires[414] ) , - .pReset_E_out ( SYNOPSYS_UNCONNECTED_2944 ) , .Reset_S_in ( p2833 ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_2944 ) , .Reset_S_in ( p2041 ) , .Reset_N_out ( SYNOPSYS_UNCONNECTED_2945 ) , - .prog_clk_0_N_in ( prog_clk_0_wires[127] ) , .prog_clk_1_N_in ( p1908 ) , - .prog_clk_1_S_in ( p287 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[127] ) , .prog_clk_1_N_in ( p1554 ) , + .prog_clk_1_S_in ( p442 ) , .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_2946 ) , .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_2947 ) , .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_2948 ) , @@ -108301,13 +112823,13 @@ sb_1__1_ sb_3__8_ ( .prog_clk_2_S_out ( prog_clk_2_wires[53] ) , .prog_clk_2_N_out ( prog_clk_2_wires[51] ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_2952 ) , - .prog_clk_3_W_in ( p1477 ) , .prog_clk_3_E_in ( p154 ) , - .prog_clk_3_S_in ( p56 ) , .prog_clk_3_N_in ( p1727 ) , + .prog_clk_3_W_in ( p1489 ) , .prog_clk_3_E_in ( p502 ) , + .prog_clk_3_S_in ( p112 ) , .prog_clk_3_N_in ( p1678 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_2953 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_2954 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_2955 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_2956 ) , .clk_1_N_in ( p1908 ) , - .clk_1_S_in ( p1084 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_2957 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_2956 ) , .clk_1_N_in ( p1554 ) , + .clk_1_S_in ( p581 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_2957 ) , .clk_1_W_out ( SYNOPSYS_UNCONNECTED_2958 ) , .clk_2_N_in ( SYNOPSYS_UNCONNECTED_2959 ) , .clk_2_E_in ( clk_2_wires[50] ) , @@ -108315,8 +112837,8 @@ sb_1__1_ sb_3__8_ ( .clk_2_W_in ( SYNOPSYS_UNCONNECTED_2961 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_2962 ) , .clk_2_S_out ( clk_2_wires[53] ) , .clk_2_N_out ( clk_2_wires[51] ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_2963 ) , .clk_3_W_in ( p1477 ) , - .clk_3_E_in ( p1674 ) , .clk_3_S_in ( p2730 ) , .clk_3_N_in ( p1632 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_2963 ) , .clk_3_W_in ( p1489 ) , + .clk_3_E_in ( p1758 ) , .clk_3_S_in ( p1669 ) , .clk_3_N_in ( p869 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_2964 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_2965 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_2966 ) , @@ -108364,40 +112886,40 @@ sb_1__1_ sb_3__9_ ( .chanx_right_out ( sb_1__1__30_chanx_right_out ) , .chany_bottom_out ( sb_1__1__30_chany_bottom_out ) , .chanx_left_out ( sb_1__1__30_chanx_left_out ) , - .ccff_tail ( sb_1__1__30_ccff_tail ) , .Test_en_S_in ( p3188 ) , + .ccff_tail ( sb_1__1__30_ccff_tail ) , .Test_en_S_in ( p2312 ) , .Test_en_N_out ( SYNOPSYS_UNCONNECTED_2969 ) , .pReset_S_in ( SYNOPSYS_UNCONNECTED_2970 ) , .pReset_E_in ( pResetWires[466] ) , .pReset_W_in ( SYNOPSYS_UNCONNECTED_2971 ) , .pReset_N_out ( pResetWires[465] ) , .pReset_W_out ( pResetWires[463] ) , - .pReset_E_out ( SYNOPSYS_UNCONNECTED_2972 ) , .Reset_S_in ( p3409 ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_2972 ) , .Reset_S_in ( p2312 ) , .Reset_N_out ( SYNOPSYS_UNCONNECTED_2973 ) , .prog_clk_0_N_in ( prog_clk_0_wires[130] ) , .prog_clk_1_N_in ( SYNOPSYS_UNCONNECTED_2974 ) , .prog_clk_1_S_in ( prog_clk_2_wires[52] ) , .prog_clk_1_E_out ( prog_clk_1_wires[71] ) , - .prog_clk_1_W_out ( prog_clk_1_wires[72] ) , .prog_clk_2_N_in ( p3503 ) , - .prog_clk_2_E_in ( p788 ) , .prog_clk_2_S_in ( p726 ) , - .prog_clk_2_W_in ( p289 ) , + .prog_clk_1_W_out ( prog_clk_1_wires[72] ) , .prog_clk_2_N_in ( p3498 ) , + .prog_clk_2_E_in ( p494 ) , .prog_clk_2_S_in ( p1085 ) , + .prog_clk_2_W_in ( p876 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_2975 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_2976 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_2977 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_2978 ) , - .prog_clk_3_W_in ( p2504 ) , .prog_clk_3_E_in ( p1223 ) , - .prog_clk_3_S_in ( p1191 ) , .prog_clk_3_N_in ( p3501 ) , + .prog_clk_3_W_in ( p3003 ) , .prog_clk_3_E_in ( p237 ) , + .prog_clk_3_S_in ( p852 ) , .prog_clk_3_N_in ( p3490 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_2979 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_2980 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_2981 ) , .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_2982 ) , .clk_1_N_in ( SYNOPSYS_UNCONNECTED_2983 ) , .clk_1_S_in ( clk_2_wires[52] ) , .clk_1_E_out ( clk_1_wires[71] ) , - .clk_1_W_out ( clk_1_wires[72] ) , .clk_2_N_in ( p3425 ) , - .clk_2_E_in ( p958 ) , .clk_2_S_in ( p3381 ) , .clk_2_W_in ( p2332 ) , + .clk_1_W_out ( clk_1_wires[72] ) , .clk_2_N_in ( p3402 ) , + .clk_2_E_in ( p1125 ) , .clk_2_S_in ( p26 ) , .clk_2_W_in ( p3369 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_2984 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_2985 ) , .clk_2_N_out ( SYNOPSYS_UNCONNECTED_2986 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_2987 ) , .clk_3_W_in ( p2504 ) , - .clk_3_E_in ( p24 ) , .clk_3_S_in ( p1342 ) , .clk_3_N_in ( p3422 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_2987 ) , .clk_3_W_in ( p3411 ) , + .clk_3_E_in ( p607 ) , .clk_3_S_in ( p2124 ) , .clk_3_N_in ( p3386 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_2988 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_2989 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_2990 ) , @@ -108445,16 +112967,16 @@ sb_1__1_ sb_3__10_ ( .chanx_right_out ( sb_1__1__31_chanx_right_out ) , .chany_bottom_out ( sb_1__1__31_chany_bottom_out ) , .chanx_left_out ( sb_1__1__31_chanx_left_out ) , - .ccff_tail ( sb_1__1__31_ccff_tail ) , .Test_en_S_in ( p886 ) , + .ccff_tail ( sb_1__1__31_ccff_tail ) , .Test_en_S_in ( p1398 ) , .Test_en_N_out ( SYNOPSYS_UNCONNECTED_2993 ) , .pReset_S_in ( SYNOPSYS_UNCONNECTED_2994 ) , .pReset_E_in ( pResetWires[515] ) , .pReset_W_in ( SYNOPSYS_UNCONNECTED_2995 ) , .pReset_N_out ( pResetWires[514] ) , .pReset_W_out ( pResetWires[512] ) , - .pReset_E_out ( SYNOPSYS_UNCONNECTED_2996 ) , .Reset_S_in ( p886 ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_2996 ) , .Reset_S_in ( p1398 ) , .Reset_N_out ( SYNOPSYS_UNCONNECTED_2997 ) , - .prog_clk_0_N_in ( prog_clk_0_wires[133] ) , .prog_clk_1_N_in ( p2202 ) , - .prog_clk_1_S_in ( p141 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[133] ) , .prog_clk_1_N_in ( p1491 ) , + .prog_clk_1_S_in ( p1121 ) , .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_2998 ) , .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_2999 ) , .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_3000 ) , @@ -108465,13 +112987,13 @@ sb_1__1_ sb_3__10_ ( .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_3004 ) , .prog_clk_2_N_out ( prog_clk_2_wires[64] ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_3005 ) , - .prog_clk_3_W_in ( p1499 ) , .prog_clk_3_E_in ( p217 ) , - .prog_clk_3_S_in ( p825 ) , .prog_clk_3_N_in ( p2008 ) , + .prog_clk_3_W_in ( p1611 ) , .prog_clk_3_E_in ( p833 ) , + .prog_clk_3_S_in ( p815 ) , .prog_clk_3_N_in ( p445 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_3006 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_3007 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_3008 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_3009 ) , .clk_1_N_in ( p2202 ) , - .clk_1_S_in ( p1145 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_3010 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_3009 ) , .clk_1_N_in ( p1491 ) , + .clk_1_S_in ( p310 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_3010 ) , .clk_1_W_out ( SYNOPSYS_UNCONNECTED_3011 ) , .clk_2_N_in ( SYNOPSYS_UNCONNECTED_3012 ) , .clk_2_E_in ( clk_2_wires[63] ) , @@ -108480,8 +113002,8 @@ sb_1__1_ sb_3__10_ ( .clk_2_W_out ( SYNOPSYS_UNCONNECTED_3015 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_3016 ) , .clk_2_N_out ( clk_2_wires[64] ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_3017 ) , .clk_3_W_in ( p1499 ) , - .clk_3_E_in ( p1675 ) , .clk_3_S_in ( p826 ) , .clk_3_N_in ( p2049 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_3017 ) , .clk_3_W_in ( p1611 ) , + .clk_3_E_in ( p285 ) , .clk_3_S_in ( p629 ) , .clk_3_N_in ( p153 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_3018 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_3019 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_3020 ) , @@ -108529,40 +113051,40 @@ sb_1__1_ sb_3__11_ ( .chanx_right_out ( sb_1__1__32_chanx_right_out ) , .chany_bottom_out ( sb_1__1__32_chany_bottom_out ) , .chanx_left_out ( sb_1__1__32_chanx_left_out ) , - .ccff_tail ( sb_1__1__32_ccff_tail ) , .Test_en_S_in ( p2259 ) , + .ccff_tail ( sb_1__1__32_ccff_tail ) , .Test_en_S_in ( p2331 ) , .Test_en_N_out ( SYNOPSYS_UNCONNECTED_3023 ) , .pReset_S_in ( SYNOPSYS_UNCONNECTED_3024 ) , .pReset_E_in ( pResetWires[564] ) , .pReset_W_in ( SYNOPSYS_UNCONNECTED_3025 ) , .pReset_N_out ( pResetWires[563] ) , .pReset_W_out ( pResetWires[561] ) , - .pReset_E_out ( SYNOPSYS_UNCONNECTED_3026 ) , .Reset_S_in ( p3489 ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_3026 ) , .Reset_S_in ( p2331 ) , .Reset_N_out ( SYNOPSYS_UNCONNECTED_3027 ) , .prog_clk_0_N_in ( prog_clk_0_wires[136] ) , .prog_clk_1_N_in ( SYNOPSYS_UNCONNECTED_3028 ) , .prog_clk_1_S_in ( prog_clk_2_wires[65] ) , .prog_clk_1_E_out ( prog_clk_1_wires[78] ) , - .prog_clk_1_W_out ( prog_clk_1_wires[79] ) , .prog_clk_2_N_in ( p2948 ) , - .prog_clk_2_E_in ( p1189 ) , .prog_clk_2_S_in ( p60 ) , - .prog_clk_2_W_in ( p230 ) , + .prog_clk_1_W_out ( prog_clk_1_wires[79] ) , .prog_clk_2_N_in ( p3506 ) , + .prog_clk_2_E_in ( p637 ) , .prog_clk_2_S_in ( p1255 ) , + .prog_clk_2_W_in ( p910 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_3029 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_3030 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_3031 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_3032 ) , - .prog_clk_3_W_in ( p2460 ) , .prog_clk_3_E_in ( p142 ) , - .prog_clk_3_S_in ( p1384 ) , .prog_clk_3_N_in ( p2893 ) , + .prog_clk_3_W_in ( p2251 ) , .prog_clk_3_E_in ( p837 ) , + .prog_clk_3_S_in ( p236 ) , .prog_clk_3_N_in ( p3480 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_3033 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_3034 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_3035 ) , .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_3036 ) , .clk_1_N_in ( SYNOPSYS_UNCONNECTED_3037 ) , .clk_1_S_in ( clk_2_wires[65] ) , .clk_1_E_out ( clk_1_wires[78] ) , - .clk_1_W_out ( clk_1_wires[79] ) , .clk_2_N_in ( p1826 ) , - .clk_2_E_in ( p926 ) , .clk_2_S_in ( p3482 ) , .clk_2_W_in ( p2308 ) , + .clk_1_W_out ( clk_1_wires[79] ) , .clk_2_N_in ( p3469 ) , + .clk_2_E_in ( p1199 ) , .clk_2_S_in ( p1164 ) , .clk_2_W_in ( p3523 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_3038 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_3039 ) , .clk_2_N_out ( SYNOPSYS_UNCONNECTED_3040 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_3041 ) , .clk_3_W_in ( p2460 ) , - .clk_3_E_in ( p468 ) , .clk_3_S_in ( p561 ) , .clk_3_N_in ( p1735 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_3041 ) , .clk_3_W_in ( p3530 ) , + .clk_3_E_in ( p58 ) , .clk_3_S_in ( p2126 ) , .clk_3_N_in ( p3449 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_3042 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_3043 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_3044 ) , @@ -108610,38 +113132,38 @@ sb_1__1_ sb_4__1_ ( .chanx_right_out ( sb_1__1__33_chanx_right_out ) , .chany_bottom_out ( sb_1__1__33_chany_bottom_out ) , .chanx_left_out ( sb_1__1__33_chanx_left_out ) , - .ccff_tail ( sb_1__1__33_ccff_tail ) , .Test_en_S_in ( p2501 ) , + .ccff_tail ( sb_1__1__33_ccff_tail ) , .Test_en_S_in ( p2597 ) , .Test_en_N_out ( SYNOPSYS_UNCONNECTED_3047 ) , .pReset_S_in ( SYNOPSYS_UNCONNECTED_3048 ) , .pReset_E_in ( pResetWires[78] ) , .pReset_W_in ( SYNOPSYS_UNCONNECTED_3049 ) , .pReset_N_out ( pResetWires[77] ) , .pReset_W_out ( pResetWires[75] ) , - .pReset_E_out ( SYNOPSYS_UNCONNECTED_3050 ) , .Reset_S_in ( p3431 ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_3050 ) , .Reset_S_in ( p2529 ) , .Reset_N_out ( SYNOPSYS_UNCONNECTED_3051 ) , - .prog_clk_0_N_in ( prog_clk_0_wires[144] ) , .prog_clk_1_N_in ( p1514 ) , - .prog_clk_1_S_in ( p557 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[144] ) , .prog_clk_1_N_in ( p1184 ) , + .prog_clk_1_S_in ( p1138 ) , .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_3052 ) , .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_3053 ) , - .prog_clk_2_N_in ( p3499 ) , .prog_clk_2_E_in ( p425 ) , - .prog_clk_2_S_in ( p5 ) , .prog_clk_2_W_in ( p1012 ) , + .prog_clk_2_N_in ( p3539 ) , .prog_clk_2_E_in ( p731 ) , + .prog_clk_2_S_in ( p1178 ) , .prog_clk_2_W_in ( p217 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_3054 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_3055 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_3056 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_3057 ) , - .prog_clk_3_W_in ( p2609 ) , .prog_clk_3_E_in ( p1266 ) , - .prog_clk_3_S_in ( p1535 ) , .prog_clk_3_N_in ( p3497 ) , + .prog_clk_3_W_in ( p3268 ) , .prog_clk_3_E_in ( p6 ) , + .prog_clk_3_S_in ( p99 ) , .prog_clk_3_N_in ( p3528 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_3058 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_3059 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_3060 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_3061 ) , .clk_1_N_in ( p1514 ) , - .clk_1_S_in ( p103 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_3062 ) , - .clk_1_W_out ( SYNOPSYS_UNCONNECTED_3063 ) , .clk_2_N_in ( p3327 ) , - .clk_2_E_in ( p647 ) , .clk_2_S_in ( p3421 ) , .clk_2_W_in ( p2542 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_3061 ) , .clk_1_N_in ( p1184 ) , + .clk_1_S_in ( p475 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_3062 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_3063 ) , .clk_2_N_in ( p3535 ) , + .clk_2_E_in ( p862 ) , .clk_2_S_in ( p1302 ) , .clk_2_W_in ( p3197 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_3064 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_3065 ) , .clk_2_N_out ( SYNOPSYS_UNCONNECTED_3066 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_3067 ) , .clk_3_W_in ( p2609 ) , - .clk_3_E_in ( p406 ) , .clk_3_S_in ( p511 ) , .clk_3_N_in ( p3300 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_3067 ) , .clk_3_W_in ( p1936 ) , + .clk_3_E_in ( p1189 ) , .clk_3_S_in ( p2389 ) , .clk_3_N_in ( p3522 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_3068 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_3069 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_3070 ) , @@ -108689,16 +113211,16 @@ sb_1__1_ sb_4__2_ ( .chanx_right_out ( sb_1__1__34_chanx_right_out ) , .chany_bottom_out ( sb_1__1__34_chany_bottom_out ) , .chanx_left_out ( sb_1__1__34_chanx_left_out ) , - .ccff_tail ( sb_1__1__34_ccff_tail ) , .Test_en_S_in ( p2840 ) , + .ccff_tail ( sb_1__1__34_ccff_tail ) , .Test_en_S_in ( p2348 ) , .Test_en_N_out ( SYNOPSYS_UNCONNECTED_3073 ) , .pReset_S_in ( SYNOPSYS_UNCONNECTED_3074 ) , .pReset_E_in ( pResetWires[127] ) , .pReset_W_in ( SYNOPSYS_UNCONNECTED_3075 ) , .pReset_N_out ( pResetWires[126] ) , .pReset_W_out ( pResetWires[124] ) , - .pReset_E_out ( SYNOPSYS_UNCONNECTED_3076 ) , .Reset_S_in ( p2840 ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_3076 ) , .Reset_S_in ( p2348 ) , .Reset_N_out ( SYNOPSYS_UNCONNECTED_3077 ) , - .prog_clk_0_N_in ( prog_clk_0_wires[147] ) , .prog_clk_1_N_in ( p1824 ) , - .prog_clk_1_S_in ( p374 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[147] ) , .prog_clk_1_N_in ( p1541 ) , + .prog_clk_1_S_in ( p1114 ) , .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_3078 ) , .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_3079 ) , .prog_clk_2_N_in ( prog_clk_3_wires[25] ) , @@ -108708,14 +113230,14 @@ sb_1__1_ sb_4__2_ ( .prog_clk_2_W_out ( prog_clk_2_wires[27] ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_3083 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_3084 ) , - .prog_clk_2_E_out ( prog_clk_2_wires[25] ) , .prog_clk_3_W_in ( p2500 ) , - .prog_clk_3_E_in ( p596 ) , .prog_clk_3_S_in ( p117 ) , - .prog_clk_3_N_in ( p118 ) , + .prog_clk_2_E_out ( prog_clk_2_wires[25] ) , .prog_clk_3_W_in ( p1258 ) , + .prog_clk_3_E_in ( p532 ) , .prog_clk_3_S_in ( p107 ) , + .prog_clk_3_N_in ( p340 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_3085 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_3086 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_3087 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_3088 ) , .clk_1_N_in ( p1824 ) , - .clk_1_S_in ( p662 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_3089 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_3088 ) , .clk_1_N_in ( p1541 ) , + .clk_1_S_in ( p548 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_3089 ) , .clk_1_W_out ( SYNOPSYS_UNCONNECTED_3090 ) , .clk_2_N_in ( clk_3_wires[25] ) , .clk_2_E_in ( SYNOPSYS_UNCONNECTED_3091 ) , @@ -108724,8 +113246,8 @@ sb_1__1_ sb_4__2_ ( .clk_2_W_out ( clk_2_wires[27] ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_3094 ) , .clk_2_N_out ( SYNOPSYS_UNCONNECTED_3095 ) , - .clk_2_E_out ( clk_2_wires[25] ) , .clk_3_W_in ( p2500 ) , - .clk_3_E_in ( p1631 ) , .clk_3_S_in ( p2718 ) , .clk_3_N_in ( p1665 ) , + .clk_2_E_out ( clk_2_wires[25] ) , .clk_3_W_in ( p1258 ) , + .clk_3_E_in ( p1717 ) , .clk_3_S_in ( p2139 ) , .clk_3_N_in ( p845 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_3096 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_3097 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_3098 ) , @@ -108773,20 +113295,20 @@ sb_1__1_ sb_4__3_ ( .chanx_right_out ( sb_1__1__35_chanx_right_out ) , .chany_bottom_out ( sb_1__1__35_chany_bottom_out ) , .chanx_left_out ( sb_1__1__35_chanx_left_out ) , - .ccff_tail ( sb_1__1__35_ccff_tail ) , .Test_en_S_in ( p2843 ) , + .ccff_tail ( sb_1__1__35_ccff_tail ) , .Test_en_S_in ( p2024 ) , .Test_en_N_out ( SYNOPSYS_UNCONNECTED_3101 ) , .pReset_S_in ( SYNOPSYS_UNCONNECTED_3102 ) , .pReset_E_in ( pResetWires[176] ) , .pReset_W_in ( SYNOPSYS_UNCONNECTED_3103 ) , .pReset_N_out ( pResetWires[175] ) , .pReset_W_out ( pResetWires[173] ) , - .pReset_E_out ( SYNOPSYS_UNCONNECTED_3104 ) , .Reset_S_in ( p2985 ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_3104 ) , .Reset_S_in ( p2024 ) , .Reset_N_out ( SYNOPSYS_UNCONNECTED_3105 ) , - .prog_clk_0_N_in ( prog_clk_0_wires[150] ) , .prog_clk_1_N_in ( p1374 ) , - .prog_clk_1_S_in ( p543 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[150] ) , .prog_clk_1_N_in ( p1442 ) , + .prog_clk_1_S_in ( p1052 ) , .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_3106 ) , .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_3107 ) , - .prog_clk_2_N_in ( p2446 ) , .prog_clk_2_E_in ( p402 ) , - .prog_clk_2_S_in ( p1995 ) , .prog_clk_2_W_in ( p964 ) , + .prog_clk_2_N_in ( p1563 ) , .prog_clk_2_E_in ( p811 ) , + .prog_clk_2_S_in ( p201 ) , .prog_clk_2_W_in ( p1049 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_3108 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_3109 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_3110 ) , @@ -108798,10 +113320,10 @@ sb_1__1_ sb_4__3_ ( .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_3115 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_3116 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_3117 ) , - .prog_clk_3_S_out ( prog_clk_3_wires[24] ) , .clk_1_N_in ( p1374 ) , - .clk_1_S_in ( p149 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_3118 ) , - .clk_1_W_out ( SYNOPSYS_UNCONNECTED_3119 ) , .clk_2_N_in ( p1807 ) , - .clk_2_E_in ( p73 ) , .clk_2_S_in ( p2898 ) , .clk_2_W_in ( p92 ) , + .prog_clk_3_S_out ( prog_clk_3_wires[24] ) , .clk_1_N_in ( p1442 ) , + .clk_1_S_in ( p121 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_3118 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_3119 ) , .clk_2_N_in ( p1563 ) , + .clk_2_E_in ( p123 ) , .clk_2_S_in ( p1712 ) , .clk_2_W_in ( p492 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_3120 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_3121 ) , .clk_2_N_out ( SYNOPSYS_UNCONNECTED_3122 ) , @@ -108857,16 +113379,16 @@ sb_1__1_ sb_4__4_ ( .chanx_right_out ( sb_1__1__36_chanx_right_out ) , .chany_bottom_out ( sb_1__1__36_chany_bottom_out ) , .chanx_left_out ( sb_1__1__36_chanx_left_out ) , - .ccff_tail ( sb_1__1__36_ccff_tail ) , .Test_en_S_in ( p2102 ) , + .ccff_tail ( sb_1__1__36_ccff_tail ) , .Test_en_S_in ( p1954 ) , .Test_en_N_out ( SYNOPSYS_UNCONNECTED_3131 ) , .pReset_S_in ( SYNOPSYS_UNCONNECTED_3132 ) , .pReset_E_in ( pResetWires[225] ) , .pReset_W_in ( SYNOPSYS_UNCONNECTED_3133 ) , .pReset_N_out ( pResetWires[224] ) , .pReset_W_out ( pResetWires[222] ) , - .pReset_E_out ( SYNOPSYS_UNCONNECTED_3134 ) , .Reset_S_in ( p2102 ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_3134 ) , .Reset_S_in ( p1954 ) , .Reset_N_out ( SYNOPSYS_UNCONNECTED_3135 ) , - .prog_clk_0_N_in ( prog_clk_0_wires[153] ) , .prog_clk_1_N_in ( p1584 ) , - .prog_clk_1_S_in ( p1024 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[153] ) , .prog_clk_1_N_in ( p1029 ) , + .prog_clk_1_S_in ( p1754 ) , .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_3136 ) , .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_3137 ) , .prog_clk_2_N_in ( prog_clk_3_wires[15] ) , @@ -108884,8 +113406,8 @@ sb_1__1_ sb_4__4_ ( .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_3146 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_3147 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_3148 ) , - .prog_clk_3_S_out ( prog_clk_3_wires[20] ) , .clk_1_N_in ( p1584 ) , - .clk_1_S_in ( p1980 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_3149 ) , + .prog_clk_3_S_out ( prog_clk_3_wires[20] ) , .clk_1_N_in ( p1029 ) , + .clk_1_S_in ( p1054 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_3149 ) , .clk_1_W_out ( SYNOPSYS_UNCONNECTED_3150 ) , .clk_2_N_in ( clk_3_wires[15] ) , .clk_2_E_in ( SYNOPSYS_UNCONNECTED_3151 ) , @@ -108946,20 +113468,20 @@ sb_1__1_ sb_4__5_ ( .chanx_right_out ( sb_1__1__37_chanx_right_out ) , .chany_bottom_out ( sb_1__1__37_chany_bottom_out ) , .chanx_left_out ( sb_1__1__37_chanx_left_out ) , - .ccff_tail ( sb_1__1__37_ccff_tail ) , .Test_en_S_in ( p2859 ) , + .ccff_tail ( sb_1__1__37_ccff_tail ) , .Test_en_S_in ( p1968 ) , .Test_en_N_out ( SYNOPSYS_UNCONNECTED_3163 ) , .pReset_S_in ( SYNOPSYS_UNCONNECTED_3164 ) , .pReset_E_in ( pResetWires[274] ) , .pReset_W_in ( SYNOPSYS_UNCONNECTED_3165 ) , .pReset_N_out ( pResetWires[273] ) , .pReset_W_out ( pResetWires[271] ) , - .pReset_E_out ( SYNOPSYS_UNCONNECTED_3166 ) , .Reset_S_in ( p3101 ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_3166 ) , .Reset_S_in ( p1968 ) , .Reset_N_out ( SYNOPSYS_UNCONNECTED_3167 ) , - .prog_clk_0_N_in ( prog_clk_0_wires[156] ) , .prog_clk_1_N_in ( p1448 ) , - .prog_clk_1_S_in ( p192 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[156] ) , .prog_clk_1_N_in ( p1854 ) , + .prog_clk_1_S_in ( p163 ) , .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_3168 ) , .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_3169 ) , - .prog_clk_2_N_in ( p1600 ) , .prog_clk_2_E_in ( p900 ) , - .prog_clk_2_S_in ( p563 ) , .prog_clk_2_W_in ( p520 ) , + .prog_clk_2_N_in ( p2355 ) , .prog_clk_2_E_in ( p458 ) , + .prog_clk_2_S_in ( p768 ) , .prog_clk_2_W_in ( p311 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_3170 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_3171 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_3172 ) , @@ -108971,10 +113493,10 @@ sb_1__1_ sb_4__5_ ( .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_3177 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_3178 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_3179 ) , - .prog_clk_3_S_out ( prog_clk_3_wires[14] ) , .clk_1_N_in ( p1448 ) , - .clk_1_S_in ( p130 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_3180 ) , - .clk_1_W_out ( SYNOPSYS_UNCONNECTED_3181 ) , .clk_2_N_in ( p1501 ) , - .clk_2_E_in ( p508 ) , .clk_2_S_in ( p3021 ) , .clk_2_W_in ( p593 ) , + .prog_clk_3_S_out ( prog_clk_3_wires[14] ) , .clk_1_N_in ( p1854 ) , + .clk_1_S_in ( p959 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_3180 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_3181 ) , .clk_2_N_in ( p1915 ) , + .clk_2_E_in ( p820 ) , .clk_2_S_in ( p1725 ) , .clk_2_W_in ( p736 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_3182 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_3183 ) , .clk_2_N_out ( SYNOPSYS_UNCONNECTED_3184 ) , @@ -109030,20 +113552,20 @@ sb_1__1_ sb_4__6_ ( .chanx_right_out ( sb_1__1__38_chanx_right_out ) , .chany_bottom_out ( sb_1__1__38_chany_bottom_out ) , .chanx_left_out ( sb_1__1__38_chanx_left_out ) , - .ccff_tail ( sb_1__1__38_ccff_tail ) , .Test_en_S_in ( p2969 ) , + .ccff_tail ( sb_1__1__38_ccff_tail ) , .Test_en_S_in ( p1926 ) , .Test_en_N_out ( SYNOPSYS_UNCONNECTED_3193 ) , .pReset_S_in ( SYNOPSYS_UNCONNECTED_3194 ) , .pReset_E_in ( pResetWires[323] ) , .pReset_W_in ( SYNOPSYS_UNCONNECTED_3195 ) , .pReset_N_out ( pResetWires[322] ) , .pReset_W_out ( pResetWires[320] ) , - .pReset_E_out ( SYNOPSYS_UNCONNECTED_3196 ) , .Reset_S_in ( p3311 ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_3196 ) , .Reset_S_in ( p1926 ) , .Reset_N_out ( SYNOPSYS_UNCONNECTED_3197 ) , - .prog_clk_0_N_in ( prog_clk_0_wires[159] ) , .prog_clk_1_N_in ( p1553 ) , - .prog_clk_1_S_in ( p461 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[159] ) , .prog_clk_1_N_in ( p1831 ) , + .prog_clk_1_S_in ( p1136 ) , .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_3198 ) , .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_3199 ) , - .prog_clk_2_N_in ( p2646 ) , .prog_clk_2_E_in ( p1001 ) , - .prog_clk_2_S_in ( p125 ) , .prog_clk_2_W_in ( p304 ) , + .prog_clk_2_N_in ( p2567 ) , .prog_clk_2_E_in ( p247 ) , + .prog_clk_2_S_in ( p1807 ) , .prog_clk_2_W_in ( p1690 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_3200 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_3201 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_3202 ) , @@ -109055,10 +113577,10 @@ sb_1__1_ sb_4__6_ ( .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_3207 ) , .prog_clk_3_W_out ( prog_clk_3_wires[46] ) , .prog_clk_3_N_out ( prog_clk_3_wires[8] ) , - .prog_clk_3_S_out ( prog_clk_3_wires[10] ) , .clk_1_N_in ( p1553 ) , - .clk_1_S_in ( p355 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_3208 ) , - .clk_1_W_out ( SYNOPSYS_UNCONNECTED_3209 ) , .clk_2_N_in ( p2472 ) , - .clk_2_E_in ( p215 ) , .clk_2_S_in ( p3286 ) , .clk_2_W_in ( p1198 ) , + .prog_clk_3_S_out ( prog_clk_3_wires[10] ) , .clk_1_N_in ( p1831 ) , + .clk_1_S_in ( p93 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_3208 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_3209 ) , .clk_2_N_in ( p2578 ) , + .clk_2_E_in ( p140 ) , .clk_2_S_in ( p1687 ) , .clk_2_W_in ( p231 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_3210 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_3211 ) , .clk_2_N_out ( SYNOPSYS_UNCONNECTED_3212 ) , @@ -109113,20 +113635,20 @@ sb_1__1_ sb_4__7_ ( .chanx_right_out ( sb_1__1__39_chanx_right_out ) , .chany_bottom_out ( sb_1__1__39_chany_bottom_out ) , .chanx_left_out ( sb_1__1__39_chanx_left_out ) , - .ccff_tail ( sb_1__1__39_ccff_tail ) , .Test_en_S_in ( p2237 ) , + .ccff_tail ( sb_1__1__39_ccff_tail ) , .Test_en_S_in ( p2210 ) , .Test_en_N_out ( SYNOPSYS_UNCONNECTED_3219 ) , .pReset_S_in ( SYNOPSYS_UNCONNECTED_3220 ) , .pReset_E_in ( pResetWires[372] ) , .pReset_W_in ( SYNOPSYS_UNCONNECTED_3221 ) , .pReset_N_out ( pResetWires[371] ) , .pReset_W_out ( pResetWires[369] ) , - .pReset_E_out ( SYNOPSYS_UNCONNECTED_3222 ) , .Reset_S_in ( p3243 ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_3222 ) , .Reset_S_in ( p2210 ) , .Reset_N_out ( SYNOPSYS_UNCONNECTED_3223 ) , - .prog_clk_0_N_in ( prog_clk_0_wires[162] ) , .prog_clk_1_N_in ( p1487 ) , - .prog_clk_1_S_in ( p512 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[162] ) , .prog_clk_1_N_in ( p1301 ) , + .prog_clk_1_S_in ( p1168 ) , .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_3224 ) , .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_3225 ) , - .prog_clk_2_N_in ( p2847 ) , .prog_clk_2_E_in ( p1195 ) , - .prog_clk_2_S_in ( p2010 ) , .prog_clk_2_W_in ( p1083 ) , + .prog_clk_2_N_in ( p1866 ) , .prog_clk_2_E_in ( p670 ) , + .prog_clk_2_S_in ( p2059 ) , .prog_clk_2_W_in ( p180 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_3226 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_3227 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_3228 ) , @@ -109138,10 +113660,10 @@ sb_1__1_ sb_4__7_ ( .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_3233 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_3234 ) , .prog_clk_3_N_out ( prog_clk_3_wires[12] ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_3235 ) , .clk_1_N_in ( p1487 ) , - .clk_1_S_in ( p973 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_3236 ) , - .clk_1_W_out ( SYNOPSYS_UNCONNECTED_3237 ) , .clk_2_N_in ( p2174 ) , - .clk_2_E_in ( p235 ) , .clk_2_S_in ( p3221 ) , .clk_2_W_in ( p153 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_3235 ) , .clk_1_N_in ( p1301 ) , + .clk_1_S_in ( p375 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_3236 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_3237 ) , .clk_2_N_in ( p1866 ) , + .clk_2_E_in ( p307 ) , .clk_2_S_in ( p2169 ) , .clk_2_W_in ( p829 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_3238 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_3239 ) , .clk_2_N_out ( SYNOPSYS_UNCONNECTED_3240 ) , @@ -109197,16 +113719,16 @@ sb_1__1_ sb_4__8_ ( .chanx_right_out ( sb_1__1__40_chanx_right_out ) , .chany_bottom_out ( sb_1__1__40_chany_bottom_out ) , .chanx_left_out ( sb_1__1__40_chanx_left_out ) , - .ccff_tail ( sb_1__1__40_ccff_tail ) , .Test_en_S_in ( p1882 ) , + .ccff_tail ( sb_1__1__40_ccff_tail ) , .Test_en_S_in ( p1420 ) , .Test_en_N_out ( SYNOPSYS_UNCONNECTED_3249 ) , .pReset_S_in ( SYNOPSYS_UNCONNECTED_3250 ) , .pReset_E_in ( pResetWires[421] ) , .pReset_W_in ( SYNOPSYS_UNCONNECTED_3251 ) , .pReset_N_out ( pResetWires[420] ) , .pReset_W_out ( pResetWires[418] ) , - .pReset_E_out ( SYNOPSYS_UNCONNECTED_3252 ) , .Reset_S_in ( p1882 ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_3252 ) , .Reset_S_in ( p1420 ) , .Reset_N_out ( SYNOPSYS_UNCONNECTED_3253 ) , - .prog_clk_0_N_in ( prog_clk_0_wires[165] ) , .prog_clk_1_N_in ( p1849 ) , - .prog_clk_1_S_in ( p892 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[165] ) , .prog_clk_1_N_in ( p1495 ) , + .prog_clk_1_S_in ( p1197 ) , .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_3254 ) , .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_3255 ) , .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_3256 ) , @@ -109224,8 +113746,8 @@ sb_1__1_ sb_4__8_ ( .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_3264 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_3265 ) , .prog_clk_3_N_out ( prog_clk_3_wires[18] ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_3266 ) , .clk_1_N_in ( p1764 ) , - .clk_1_S_in ( p1654 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_3267 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_3266 ) , .clk_1_N_in ( p1495 ) , + .clk_1_S_in ( p166 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_3267 ) , .clk_1_W_out ( SYNOPSYS_UNCONNECTED_3268 ) , .clk_2_N_in ( SYNOPSYS_UNCONNECTED_3269 ) , .clk_2_E_in ( SYNOPSYS_UNCONNECTED_3270 ) , @@ -109286,20 +113808,20 @@ sb_1__1_ sb_4__9_ ( .chanx_right_out ( sb_1__1__41_chanx_right_out ) , .chany_bottom_out ( sb_1__1__41_chany_bottom_out ) , .chanx_left_out ( sb_1__1__41_chanx_left_out ) , - .ccff_tail ( sb_1__1__41_ccff_tail ) , .Test_en_S_in ( p2989 ) , + .ccff_tail ( sb_1__1__41_ccff_tail ) , .Test_en_S_in ( p2295 ) , .Test_en_N_out ( SYNOPSYS_UNCONNECTED_3281 ) , .pReset_S_in ( SYNOPSYS_UNCONNECTED_3282 ) , .pReset_E_in ( pResetWires[470] ) , .pReset_W_in ( SYNOPSYS_UNCONNECTED_3283 ) , .pReset_N_out ( pResetWires[469] ) , .pReset_W_out ( pResetWires[467] ) , - .pReset_E_out ( SYNOPSYS_UNCONNECTED_3284 ) , .Reset_S_in ( p2989 ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_3284 ) , .Reset_S_in ( p2295 ) , .Reset_N_out ( SYNOPSYS_UNCONNECTED_3285 ) , - .prog_clk_0_N_in ( prog_clk_0_wires[168] ) , .prog_clk_1_N_in ( p1335 ) , - .prog_clk_1_S_in ( p714 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[168] ) , .prog_clk_1_N_in ( p1631 ) , + .prog_clk_1_S_in ( p198 ) , .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_3286 ) , .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_3287 ) , - .prog_clk_2_N_in ( p2674 ) , .prog_clk_2_E_in ( p766 ) , - .prog_clk_2_S_in ( p1740 ) , .prog_clk_2_W_in ( p1089 ) , + .prog_clk_2_N_in ( p2550 ) , .prog_clk_2_E_in ( p706 ) , + .prog_clk_2_S_in ( p515 ) , .prog_clk_2_W_in ( p218 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_3288 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_3289 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_3290 ) , @@ -109311,10 +113833,10 @@ sb_1__1_ sb_4__9_ ( .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_3295 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_3296 ) , .prog_clk_3_N_out ( prog_clk_3_wires[22] ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_3297 ) , .clk_1_N_in ( p1335 ) , - .clk_1_S_in ( p298 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_3298 ) , - .clk_1_W_out ( SYNOPSYS_UNCONNECTED_3299 ) , .clk_2_N_in ( p2484 ) , - .clk_2_E_in ( p224 ) , .clk_2_S_in ( p2891 ) , .clk_2_W_in ( p295 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_3297 ) , .clk_1_N_in ( p1631 ) , + .clk_1_S_in ( p1096 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_3298 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_3299 ) , .clk_2_N_in ( p2550 ) , + .clk_2_E_in ( p48 ) , .clk_2_S_in ( p2082 ) , .clk_2_W_in ( p566 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_3300 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_3301 ) , .clk_2_N_out ( SYNOPSYS_UNCONNECTED_3302 ) , @@ -109370,16 +113892,16 @@ sb_1__1_ sb_4__10_ ( .chanx_right_out ( sb_1__1__42_chanx_right_out ) , .chany_bottom_out ( sb_1__1__42_chany_bottom_out ) , .chanx_left_out ( sb_1__1__42_chanx_left_out ) , - .ccff_tail ( sb_1__1__42_ccff_tail ) , .Test_en_S_in ( p2170 ) , + .ccff_tail ( sb_1__1__42_ccff_tail ) , .Test_en_S_in ( p2361 ) , .Test_en_N_out ( SYNOPSYS_UNCONNECTED_3311 ) , .pReset_S_in ( SYNOPSYS_UNCONNECTED_3312 ) , .pReset_E_in ( pResetWires[519] ) , .pReset_W_in ( SYNOPSYS_UNCONNECTED_3313 ) , .pReset_N_out ( pResetWires[518] ) , .pReset_W_out ( pResetWires[516] ) , - .pReset_E_out ( SYNOPSYS_UNCONNECTED_3314 ) , .Reset_S_in ( p2170 ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_3314 ) , .Reset_S_in ( p2361 ) , .Reset_N_out ( SYNOPSYS_UNCONNECTED_3315 ) , - .prog_clk_0_N_in ( prog_clk_0_wires[171] ) , .prog_clk_1_N_in ( p1403 ) , - .prog_clk_1_S_in ( p176 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[171] ) , .prog_clk_1_N_in ( p1984 ) , + .prog_clk_1_S_in ( p256 ) , .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_3316 ) , .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_3317 ) , .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_3318 ) , @@ -109389,14 +113911,14 @@ sb_1__1_ sb_4__10_ ( .prog_clk_2_W_out ( prog_clk_2_wires[62] ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_3321 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_3322 ) , - .prog_clk_2_E_out ( prog_clk_2_wires[60] ) , .prog_clk_3_W_in ( p1934 ) , - .prog_clk_3_E_in ( p249 ) , .prog_clk_3_S_in ( p328 ) , - .prog_clk_3_N_in ( p945 ) , + .prog_clk_2_E_out ( prog_clk_2_wires[60] ) , .prog_clk_3_W_in ( p1602 ) , + .prog_clk_3_E_in ( p726 ) , .prog_clk_3_S_in ( p363 ) , + .prog_clk_3_N_in ( p493 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_3323 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_3324 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_3325 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_3326 ) , .clk_1_N_in ( p1403 ) , - .clk_1_S_in ( p1099 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_3327 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_3326 ) , .clk_1_N_in ( p1984 ) , + .clk_1_S_in ( p990 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_3327 ) , .clk_1_W_out ( SYNOPSYS_UNCONNECTED_3328 ) , .clk_2_N_in ( SYNOPSYS_UNCONNECTED_3329 ) , .clk_2_E_in ( SYNOPSYS_UNCONNECTED_3330 ) , @@ -109405,8 +113927,8 @@ sb_1__1_ sb_4__10_ ( .clk_2_W_out ( clk_2_wires[62] ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_3332 ) , .clk_2_N_out ( SYNOPSYS_UNCONNECTED_3333 ) , - .clk_2_E_out ( clk_2_wires[60] ) , .clk_3_W_in ( p1934 ) , - .clk_3_E_in ( p1992 ) , .clk_3_S_in ( p1973 ) , .clk_3_N_in ( p97 ) , + .clk_2_E_out ( clk_2_wires[60] ) , .clk_3_W_in ( p1602 ) , + .clk_3_E_in ( p202 ) , .clk_3_S_in ( p2081 ) , .clk_3_N_in ( p1658 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_3334 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_3335 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_3336 ) , @@ -109454,38 +113976,38 @@ sb_1__1_ sb_4__11_ ( .chanx_right_out ( sb_1__1__43_chanx_right_out ) , .chany_bottom_out ( sb_1__1__43_chany_bottom_out ) , .chanx_left_out ( sb_1__1__43_chanx_left_out ) , - .ccff_tail ( sb_1__1__43_ccff_tail ) , .Test_en_S_in ( p3240 ) , + .ccff_tail ( sb_1__1__43_ccff_tail ) , .Test_en_S_in ( p2009 ) , .Test_en_N_out ( SYNOPSYS_UNCONNECTED_3339 ) , .pReset_S_in ( SYNOPSYS_UNCONNECTED_3340 ) , .pReset_E_in ( pResetWires[568] ) , .pReset_W_in ( SYNOPSYS_UNCONNECTED_3341 ) , .pReset_N_out ( pResetWires[567] ) , .pReset_W_out ( pResetWires[565] ) , - .pReset_E_out ( SYNOPSYS_UNCONNECTED_3342 ) , .Reset_S_in ( p3240 ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_3342 ) , .Reset_S_in ( p2009 ) , .Reset_N_out ( SYNOPSYS_UNCONNECTED_3343 ) , - .prog_clk_0_N_in ( prog_clk_0_wires[174] ) , .prog_clk_1_N_in ( p1848 ) , - .prog_clk_1_S_in ( p746 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[174] ) , .prog_clk_1_N_in ( p2228 ) , + .prog_clk_1_S_in ( p470 ) , .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_3344 ) , .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_3345 ) , - .prog_clk_2_N_in ( p3090 ) , .prog_clk_2_E_in ( p889 ) , - .prog_clk_2_S_in ( p494 ) , .prog_clk_2_W_in ( p1271 ) , + .prog_clk_2_N_in ( p3608 ) , .prog_clk_2_E_in ( p298 ) , + .prog_clk_2_S_in ( p600 ) , .prog_clk_2_W_in ( p115 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_3346 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_3347 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_3348 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_3349 ) , - .prog_clk_3_W_in ( p2668 ) , .prog_clk_3_E_in ( p426 ) , - .prog_clk_3_S_in ( p1340 ) , .prog_clk_3_N_in ( p3009 ) , + .prog_clk_3_W_in ( p2334 ) , .prog_clk_3_E_in ( p782 ) , + .prog_clk_3_S_in ( p1043 ) , .prog_clk_3_N_in ( p3606 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_3350 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_3351 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_3352 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_3353 ) , .clk_1_N_in ( p1848 ) , - .clk_1_S_in ( p459 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_3354 ) , - .clk_1_W_out ( SYNOPSYS_UNCONNECTED_3355 ) , .clk_2_N_in ( p3411 ) , - .clk_2_E_in ( p777 ) , .clk_2_S_in ( p3217 ) , .clk_2_W_in ( p2573 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_3353 ) , .clk_1_N_in ( p2228 ) , + .clk_1_S_in ( p1127 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_3354 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_3355 ) , .clk_2_N_in ( p3130 ) , + .clk_2_E_in ( p505 ) , .clk_2_S_in ( p182 ) , .clk_2_W_in ( p3549 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_3356 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_3357 ) , .clk_2_N_out ( SYNOPSYS_UNCONNECTED_3358 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_3359 ) , .clk_3_W_in ( p2668 ) , - .clk_3_E_in ( p523 ) , .clk_3_S_in ( p1262 ) , .clk_3_N_in ( p3390 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_3359 ) , .clk_3_W_in ( p3557 ) , + .clk_3_E_in ( p1195 ) , .clk_3_S_in ( p1688 ) , .clk_3_N_in ( p3093 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_3360 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_3361 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_3362 ) , @@ -109533,27 +114055,27 @@ sb_1__1_ sb_5__1_ ( .chanx_right_out ( sb_1__1__44_chanx_right_out ) , .chany_bottom_out ( sb_1__1__44_chany_bottom_out ) , .chanx_left_out ( sb_1__1__44_chanx_left_out ) , - .ccff_tail ( sb_1__1__44_ccff_tail ) , .Test_en_S_in ( p2496 ) , + .ccff_tail ( sb_1__1__44_ccff_tail ) , .Test_en_S_in ( p2633 ) , .Test_en_N_out ( SYNOPSYS_UNCONNECTED_3365 ) , .pReset_S_in ( SYNOPSYS_UNCONNECTED_3366 ) , .pReset_E_in ( pResetWires[82] ) , .pReset_W_in ( SYNOPSYS_UNCONNECTED_3367 ) , .pReset_N_out ( pResetWires[81] ) , .pReset_W_out ( pResetWires[79] ) , - .pReset_E_out ( SYNOPSYS_UNCONNECTED_3368 ) , .Reset_S_in ( p2496 ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_3368 ) , .Reset_S_in ( p2633 ) , .Reset_N_out ( SYNOPSYS_UNCONNECTED_3369 ) , .prog_clk_0_N_in ( prog_clk_0_wires[182] ) , .prog_clk_1_N_in ( prog_clk_2_wires[32] ) , .prog_clk_1_S_in ( SYNOPSYS_UNCONNECTED_3370 ) , .prog_clk_1_E_out ( prog_clk_1_wires[85] ) , - .prog_clk_1_W_out ( prog_clk_1_wires[86] ) , .prog_clk_2_N_in ( p3331 ) , - .prog_clk_2_E_in ( p1207 ) , .prog_clk_2_S_in ( p1242 ) , - .prog_clk_2_W_in ( p529 ) , + .prog_clk_1_W_out ( prog_clk_1_wires[86] ) , .prog_clk_2_N_in ( p2804 ) , + .prog_clk_2_E_in ( p135 ) , .prog_clk_2_S_in ( p715 ) , + .prog_clk_2_W_in ( p417 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_3371 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_3372 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_3373 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_3374 ) , - .prog_clk_3_W_in ( p3164 ) , .prog_clk_3_E_in ( p186 ) , - .prog_clk_3_S_in ( p654 ) , .prog_clk_3_N_in ( p3288 ) , + .prog_clk_3_W_in ( p2757 ) , .prog_clk_3_E_in ( p963 ) , + .prog_clk_3_S_in ( p1023 ) , .prog_clk_3_N_in ( p2656 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_3375 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_3376 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_3377 ) , @@ -109561,12 +114083,12 @@ sb_1__1_ sb_5__1_ ( .clk_1_N_in ( clk_2_wires[32] ) , .clk_1_S_in ( SYNOPSYS_UNCONNECTED_3379 ) , .clk_1_E_out ( clk_1_wires[85] ) , .clk_1_W_out ( clk_1_wires[86] ) , - .clk_2_N_in ( p3403 ) , .clk_2_E_in ( p865 ) , .clk_2_S_in ( p2346 ) , - .clk_2_W_in ( p3129 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_3380 ) , + .clk_2_N_in ( p3540 ) , .clk_2_E_in ( p308 ) , .clk_2_S_in ( p1381 ) , + .clk_2_W_in ( p3615 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_3380 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_3381 ) , .clk_2_N_out ( SYNOPSYS_UNCONNECTED_3382 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_3383 ) , .clk_3_W_in ( p3164 ) , - .clk_3_E_in ( p818 ) , .clk_3_S_in ( p276 ) , .clk_3_N_in ( p3393 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_3383 ) , .clk_3_W_in ( p3616 ) , + .clk_3_E_in ( p1202 ) , .clk_3_S_in ( p2397 ) , .clk_3_N_in ( p3525 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_3384 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_3385 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_3386 ) , @@ -109614,16 +114136,16 @@ sb_1__1_ sb_5__2_ ( .chanx_right_out ( sb_1__1__45_chanx_right_out ) , .chany_bottom_out ( sb_1__1__45_chany_bottom_out ) , .chanx_left_out ( sb_1__1__45_chanx_left_out ) , - .ccff_tail ( sb_1__1__45_ccff_tail ) , .Test_en_S_in ( p2938 ) , + .ccff_tail ( sb_1__1__45_ccff_tail ) , .Test_en_S_in ( p2222 ) , .Test_en_N_out ( SYNOPSYS_UNCONNECTED_3389 ) , .pReset_S_in ( SYNOPSYS_UNCONNECTED_3390 ) , .pReset_E_in ( pResetWires[131] ) , .pReset_W_in ( SYNOPSYS_UNCONNECTED_3391 ) , .pReset_N_out ( pResetWires[130] ) , .pReset_W_out ( pResetWires[128] ) , - .pReset_E_out ( SYNOPSYS_UNCONNECTED_3392 ) , .Reset_S_in ( p2938 ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_3392 ) , .Reset_S_in ( p2222 ) , .Reset_N_out ( SYNOPSYS_UNCONNECTED_3393 ) , - .prog_clk_0_N_in ( prog_clk_0_wires[185] ) , .prog_clk_1_N_in ( p1525 ) , - .prog_clk_1_S_in ( p501 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[185] ) , .prog_clk_1_N_in ( p1370 ) , + .prog_clk_1_S_in ( p605 ) , .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_3394 ) , .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_3395 ) , .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_3396 ) , @@ -109634,13 +114156,13 @@ sb_1__1_ sb_5__2_ ( .prog_clk_2_S_out ( prog_clk_2_wires[31] ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_3400 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_3401 ) , - .prog_clk_3_W_in ( p1867 ) , .prog_clk_3_E_in ( p841 ) , - .prog_clk_3_S_in ( p429 ) , .prog_clk_3_N_in ( p551 ) , + .prog_clk_3_W_in ( p1538 ) , .prog_clk_3_E_in ( p94 ) , + .prog_clk_3_S_in ( p808 ) , .prog_clk_3_N_in ( p456 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_3402 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_3403 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_3404 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_3405 ) , .clk_1_N_in ( p1525 ) , - .clk_1_S_in ( p39 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_3406 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_3405 ) , .clk_1_N_in ( p1370 ) , + .clk_1_S_in ( p9 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_3406 ) , .clk_1_W_out ( SYNOPSYS_UNCONNECTED_3407 ) , .clk_2_N_in ( SYNOPSYS_UNCONNECTED_3408 ) , .clk_2_E_in ( SYNOPSYS_UNCONNECTED_3409 ) , @@ -109649,8 +114171,8 @@ sb_1__1_ sb_5__2_ ( .clk_2_W_out ( SYNOPSYS_UNCONNECTED_3411 ) , .clk_2_S_out ( clk_2_wires[31] ) , .clk_2_N_out ( SYNOPSYS_UNCONNECTED_3412 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_3413 ) , .clk_3_W_in ( p1867 ) , - .clk_3_E_in ( p108 ) , .clk_3_S_in ( p2896 ) , .clk_3_N_in ( p300 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_3413 ) , .clk_3_W_in ( p1538 ) , + .clk_3_E_in ( p564 ) , .clk_3_S_in ( p2068 ) , .clk_3_N_in ( p728 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_3414 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_3415 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_3416 ) , @@ -109698,27 +114220,27 @@ sb_1__1_ sb_5__3_ ( .chanx_right_out ( sb_1__1__46_chanx_right_out ) , .chany_bottom_out ( sb_1__1__46_chany_bottom_out ) , .chanx_left_out ( sb_1__1__46_chanx_left_out ) , - .ccff_tail ( sb_1__1__46_ccff_tail ) , .Test_en_S_in ( p2495 ) , + .ccff_tail ( sb_1__1__46_ccff_tail ) , .Test_en_S_in ( p2252 ) , .Test_en_N_out ( SYNOPSYS_UNCONNECTED_3419 ) , .pReset_S_in ( SYNOPSYS_UNCONNECTED_3420 ) , .pReset_E_in ( pResetWires[180] ) , .pReset_W_in ( SYNOPSYS_UNCONNECTED_3421 ) , .pReset_N_out ( pResetWires[179] ) , .pReset_W_out ( pResetWires[177] ) , - .pReset_E_out ( SYNOPSYS_UNCONNECTED_3422 ) , .Reset_S_in ( p2495 ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_3422 ) , .Reset_S_in ( p2252 ) , .Reset_N_out ( SYNOPSYS_UNCONNECTED_3423 ) , .prog_clk_0_N_in ( prog_clk_0_wires[188] ) , .prog_clk_1_N_in ( prog_clk_2_wires[45] ) , .prog_clk_1_S_in ( SYNOPSYS_UNCONNECTED_3424 ) , .prog_clk_1_E_out ( prog_clk_1_wires[92] ) , - .prog_clk_1_W_out ( prog_clk_1_wires[93] ) , .prog_clk_2_N_in ( p3326 ) , - .prog_clk_2_E_in ( p203 ) , .prog_clk_2_S_in ( p843 ) , - .prog_clk_2_W_in ( p331 ) , + .prog_clk_1_W_out ( prog_clk_1_wires[93] ) , .prog_clk_2_N_in ( p3602 ) , + .prog_clk_2_E_in ( p443 ) , .prog_clk_2_S_in ( p193 ) , + .prog_clk_2_W_in ( p784 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_3425 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_3426 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_3427 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_3428 ) , - .prog_clk_3_W_in ( p3069 ) , .prog_clk_3_E_in ( p987 ) , - .prog_clk_3_S_in ( p452 ) , .prog_clk_3_N_in ( p3287 ) , + .prog_clk_3_W_in ( p2624 ) , .prog_clk_3_E_in ( p763 ) , + .prog_clk_3_S_in ( p1181 ) , .prog_clk_3_N_in ( p3600 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_3429 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_3430 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_3431 ) , @@ -109726,12 +114248,12 @@ sb_1__1_ sb_5__3_ ( .clk_1_N_in ( clk_2_wires[45] ) , .clk_1_S_in ( SYNOPSYS_UNCONNECTED_3433 ) , .clk_1_E_out ( clk_1_wires[92] ) , .clk_1_W_out ( clk_1_wires[93] ) , - .clk_2_N_in ( p3430 ) , .clk_2_E_in ( p522 ) , .clk_2_S_in ( p2342 ) , - .clk_2_W_in ( p3028 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_3434 ) , + .clk_2_N_in ( p3141 ) , .clk_2_E_in ( p1059 ) , .clk_2_S_in ( p934 ) , + .clk_2_W_in ( p2906 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_3434 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_3435 ) , .clk_2_N_out ( SYNOPSYS_UNCONNECTED_3436 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_3437 ) , .clk_3_W_in ( p3069 ) , - .clk_3_E_in ( p769 ) , .clk_3_S_in ( p221 ) , .clk_3_N_in ( p3420 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_3437 ) , .clk_3_W_in ( p3029 ) , + .clk_3_E_in ( p225 ) , .clk_3_S_in ( p2109 ) , .clk_3_N_in ( p3038 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_3438 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_3439 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_3440 ) , @@ -109779,16 +114301,16 @@ sb_1__1_ sb_5__4_ ( .chanx_right_out ( sb_1__1__47_chanx_right_out ) , .chany_bottom_out ( sb_1__1__47_chany_bottom_out ) , .chanx_left_out ( sb_1__1__47_chanx_left_out ) , - .ccff_tail ( sb_1__1__47_ccff_tail ) , .Test_en_S_in ( p2407 ) , + .ccff_tail ( sb_1__1__47_ccff_tail ) , .Test_en_S_in ( p2605 ) , .Test_en_N_out ( SYNOPSYS_UNCONNECTED_3443 ) , .pReset_S_in ( SYNOPSYS_UNCONNECTED_3444 ) , .pReset_E_in ( pResetWires[229] ) , .pReset_W_in ( SYNOPSYS_UNCONNECTED_3445 ) , .pReset_N_out ( pResetWires[228] ) , .pReset_W_out ( pResetWires[226] ) , - .pReset_E_out ( SYNOPSYS_UNCONNECTED_3446 ) , .Reset_S_in ( p2407 ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_3446 ) , .Reset_S_in ( p2605 ) , .Reset_N_out ( SYNOPSYS_UNCONNECTED_3447 ) , - .prog_clk_0_N_in ( prog_clk_0_wires[191] ) , .prog_clk_1_N_in ( p684 ) , - .prog_clk_1_S_in ( p872 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[191] ) , .prog_clk_1_N_in ( p1937 ) , + .prog_clk_1_S_in ( p318 ) , .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_3448 ) , .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_3449 ) , .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_3450 ) , @@ -109799,13 +114321,13 @@ sb_1__1_ sb_5__4_ ( .prog_clk_2_S_out ( prog_clk_2_wires[44] ) , .prog_clk_2_N_out ( prog_clk_2_wires[42] ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_3454 ) , - .prog_clk_3_W_in ( p1590 ) , .prog_clk_3_E_in ( p560 ) , - .prog_clk_3_S_in ( p733 ) , .prog_clk_3_N_in ( p2534 ) , + .prog_clk_3_W_in ( p1498 ) , .prog_clk_3_E_in ( p336 ) , + .prog_clk_3_S_in ( p37 ) , .prog_clk_3_N_in ( p1675 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_3455 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_3456 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_3457 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_3458 ) , .clk_1_N_in ( p684 ) , - .clk_1_S_in ( p262 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_3459 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_3458 ) , .clk_1_N_in ( p1937 ) , + .clk_1_S_in ( p750 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_3459 ) , .clk_1_W_out ( SYNOPSYS_UNCONNECTED_3460 ) , .clk_2_N_in ( SYNOPSYS_UNCONNECTED_3461 ) , .clk_2_E_in ( SYNOPSYS_UNCONNECTED_3462 ) , @@ -109813,8 +114335,8 @@ sb_1__1_ sb_5__4_ ( .clk_2_W_in ( clk_2_wires[35] ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_3464 ) , .clk_2_S_out ( clk_2_wires[44] ) , .clk_2_N_out ( clk_2_wires[42] ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_3465 ) , .clk_3_W_in ( p1590 ) , - .clk_3_E_in ( p996 ) , .clk_3_S_in ( p2286 ) , .clk_3_N_in ( p802 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_3465 ) , .clk_3_W_in ( p1498 ) , + .clk_3_E_in ( p294 ) , .clk_3_S_in ( p2405 ) , .clk_3_N_in ( p1757 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_3466 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_3467 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_3468 ) , @@ -109862,40 +114384,40 @@ sb_1__1_ sb_5__5_ ( .chanx_right_out ( sb_1__1__48_chanx_right_out ) , .chany_bottom_out ( sb_1__1__48_chany_bottom_out ) , .chanx_left_out ( sb_1__1__48_chanx_left_out ) , - .ccff_tail ( sb_1__1__48_ccff_tail ) , .Test_en_S_in ( p2816 ) , + .ccff_tail ( sb_1__1__48_ccff_tail ) , .Test_en_S_in ( p2528 ) , .Test_en_N_out ( SYNOPSYS_UNCONNECTED_3471 ) , .pReset_S_in ( SYNOPSYS_UNCONNECTED_3472 ) , .pReset_E_in ( pResetWires[278] ) , .pReset_W_in ( SYNOPSYS_UNCONNECTED_3473 ) , .pReset_N_out ( pResetWires[277] ) , .pReset_W_out ( pResetWires[275] ) , - .pReset_E_out ( SYNOPSYS_UNCONNECTED_3474 ) , .Reset_S_in ( p3307 ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_3474 ) , .Reset_S_in ( p2528 ) , .Reset_N_out ( SYNOPSYS_UNCONNECTED_3475 ) , .prog_clk_0_N_in ( prog_clk_0_wires[194] ) , .prog_clk_1_N_in ( SYNOPSYS_UNCONNECTED_3476 ) , .prog_clk_1_S_in ( prog_clk_2_wires[43] ) , .prog_clk_1_E_out ( prog_clk_1_wires[99] ) , - .prog_clk_1_W_out ( prog_clk_1_wires[100] ) , .prog_clk_2_N_in ( p3486 ) , - .prog_clk_2_E_in ( p613 ) , .prog_clk_2_S_in ( p1150 ) , - .prog_clk_2_W_in ( p3 ) , + .prog_clk_1_W_out ( prog_clk_1_wires[100] ) , .prog_clk_2_N_in ( p3417 ) , + .prog_clk_2_E_in ( p529 ) , .prog_clk_2_S_in ( p1261 ) , + .prog_clk_2_W_in ( p172 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_3477 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_3478 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_3479 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_3480 ) , - .prog_clk_3_W_in ( p2168 ) , .prog_clk_3_E_in ( p1378 ) , - .prog_clk_3_S_in ( p284 ) , .prog_clk_3_N_in ( p3485 ) , + .prog_clk_3_W_in ( p3342 ) , .prog_clk_3_E_in ( p996 ) , + .prog_clk_3_S_in ( p656 ) , .prog_clk_3_N_in ( p3363 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_3481 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_3482 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_3483 ) , .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_3484 ) , .clk_1_N_in ( SYNOPSYS_UNCONNECTED_3485 ) , .clk_1_S_in ( clk_2_wires[43] ) , .clk_1_E_out ( clk_1_wires[99] ) , - .clk_1_W_out ( clk_1_wires[100] ) , .clk_2_N_in ( p2037 ) , - .clk_2_E_in ( p992 ) , .clk_2_S_in ( p3290 ) , .clk_2_W_in ( p2018 ) , + .clk_1_W_out ( clk_1_wires[100] ) , .clk_2_N_in ( p3571 ) , + .clk_2_E_in ( p1007 ) , .clk_2_S_in ( p18 ) , .clk_2_W_in ( p3310 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_3486 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_3487 ) , .clk_2_N_out ( SYNOPSYS_UNCONNECTED_3488 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_3489 ) , .clk_3_W_in ( p2168 ) , - .clk_3_E_in ( p263 ) , .clk_3_S_in ( p66 ) , .clk_3_N_in ( p2073 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_3489 ) , .clk_3_W_in ( p2961 ) , + .clk_3_E_in ( p277 ) , .clk_3_S_in ( p2417 ) , .clk_3_N_in ( p3570 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_3490 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_3491 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_3492 ) , @@ -109943,20 +114465,20 @@ sb_1__1_ sb_5__6_ ( .chanx_right_out ( sb_1__1__49_chanx_right_out ) , .chany_bottom_out ( sb_1__1__49_chany_bottom_out ) , .chanx_left_out ( sb_1__1__49_chanx_left_out ) , - .ccff_tail ( sb_1__1__49_ccff_tail ) , .Test_en_S_in ( p2514 ) , + .ccff_tail ( sb_1__1__49_ccff_tail ) , .Test_en_S_in ( p1928 ) , .Test_en_N_out ( SYNOPSYS_UNCONNECTED_3495 ) , .pReset_S_in ( SYNOPSYS_UNCONNECTED_3496 ) , .pReset_E_in ( pResetWires[327] ) , .pReset_W_in ( SYNOPSYS_UNCONNECTED_3497 ) , .pReset_N_out ( pResetWires[326] ) , .pReset_W_out ( pResetWires[324] ) , - .pReset_E_out ( SYNOPSYS_UNCONNECTED_3498 ) , .Reset_S_in ( p2514 ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_3498 ) , .Reset_S_in ( p1928 ) , .Reset_N_out ( SYNOPSYS_UNCONNECTED_3499 ) , - .prog_clk_0_N_in ( prog_clk_0_wires[197] ) , .prog_clk_1_N_in ( p1346 ) , - .prog_clk_1_S_in ( p1078 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[197] ) , .prog_clk_1_N_in ( p2045 ) , + .prog_clk_1_S_in ( p4 ) , .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_3500 ) , .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_3501 ) , - .prog_clk_2_N_in ( p2846 ) , .prog_clk_2_E_in ( p537 ) , - .prog_clk_2_S_in ( p311 ) , .prog_clk_2_W_in ( p1357 ) , + .prog_clk_2_N_in ( p2535 ) , .prog_clk_2_E_in ( p501 ) , + .prog_clk_2_S_in ( p360 ) , .prog_clk_2_W_in ( p1714 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_3502 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_3503 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_3504 ) , @@ -109968,10 +114490,10 @@ sb_1__1_ sb_5__6_ ( .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_3509 ) , .prog_clk_3_W_out ( prog_clk_3_wires[6] ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_3510 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_3511 ) , .clk_1_N_in ( p1346 ) , - .clk_1_S_in ( p17 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_3512 ) , - .clk_1_W_out ( SYNOPSYS_UNCONNECTED_3513 ) , .clk_2_N_in ( p1510 ) , - .clk_2_E_in ( p202 ) , .clk_2_S_in ( p2273 ) , .clk_2_W_in ( p251 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_3511 ) , .clk_1_N_in ( p2045 ) , + .clk_1_S_in ( p1126 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_3512 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_3513 ) , .clk_2_N_in ( p2613 ) , + .clk_2_E_in ( p761 ) , .clk_2_S_in ( p1768 ) , .clk_2_W_in ( p660 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_3514 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_3515 ) , .clk_2_N_out ( SYNOPSYS_UNCONNECTED_3516 ) , @@ -110027,27 +114549,27 @@ sb_1__1_ sb_5__7_ ( .chanx_right_out ( sb_1__1__50_chanx_right_out ) , .chany_bottom_out ( sb_1__1__50_chany_bottom_out ) , .chanx_left_out ( sb_1__1__50_chanx_left_out ) , - .ccff_tail ( sb_1__1__50_ccff_tail ) , .Test_en_S_in ( p2699 ) , + .ccff_tail ( sb_1__1__50_ccff_tail ) , .Test_en_S_in ( p2207 ) , .Test_en_N_out ( SYNOPSYS_UNCONNECTED_3525 ) , .pReset_S_in ( SYNOPSYS_UNCONNECTED_3526 ) , .pReset_E_in ( pResetWires[376] ) , .pReset_W_in ( SYNOPSYS_UNCONNECTED_3527 ) , .pReset_N_out ( pResetWires[375] ) , .pReset_W_out ( pResetWires[373] ) , - .pReset_E_out ( SYNOPSYS_UNCONNECTED_3528 ) , .Reset_S_in ( p2620 ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_3528 ) , .Reset_S_in ( p2207 ) , .Reset_N_out ( SYNOPSYS_UNCONNECTED_3529 ) , .prog_clk_0_N_in ( prog_clk_0_wires[200] ) , .prog_clk_1_N_in ( prog_clk_2_wires[58] ) , .prog_clk_1_S_in ( SYNOPSYS_UNCONNECTED_3530 ) , .prog_clk_1_E_out ( prog_clk_1_wires[106] ) , - .prog_clk_1_W_out ( prog_clk_1_wires[107] ) , .prog_clk_2_N_in ( p3367 ) , - .prog_clk_2_E_in ( p1213 ) , .prog_clk_2_S_in ( p1279 ) , - .prog_clk_2_W_in ( p1011 ) , + .prog_clk_1_W_out ( prog_clk_1_wires[107] ) , .prog_clk_2_N_in ( p2825 ) , + .prog_clk_2_E_in ( p684 ) , .prog_clk_2_S_in ( p1185 ) , + .prog_clk_2_W_in ( p313 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_3531 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_3532 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_3533 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_3534 ) , - .prog_clk_3_W_in ( p2680 ) , .prog_clk_3_E_in ( p804 ) , - .prog_clk_3_S_in ( p578 ) , .prog_clk_3_N_in ( p3352 ) , + .prog_clk_3_W_in ( p3166 ) , .prog_clk_3_E_in ( p444 ) , + .prog_clk_3_S_in ( p278 ) , .prog_clk_3_N_in ( p2705 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_3535 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_3536 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_3537 ) , @@ -110055,12 +114577,12 @@ sb_1__1_ sb_5__7_ ( .clk_1_N_in ( clk_2_wires[58] ) , .clk_1_S_in ( SYNOPSYS_UNCONNECTED_3539 ) , .clk_1_E_out ( clk_1_wires[106] ) , .clk_1_W_out ( clk_1_wires[107] ) , - .clk_2_N_in ( p3465 ) , .clk_2_E_in ( p801 ) , .clk_2_S_in ( p2549 ) , - .clk_2_W_in ( p2570 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_3540 ) , + .clk_2_N_in ( p3272 ) , .clk_2_E_in ( p66 ) , .clk_2_S_in ( p1028 ) , + .clk_2_W_in ( p3054 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_3540 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_3541 ) , .clk_2_N_out ( SYNOPSYS_UNCONNECTED_3542 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_3543 ) , .clk_3_W_in ( p2680 ) , - .clk_3_E_in ( p530 ) , .clk_3_S_in ( p179 ) , .clk_3_N_in ( p3464 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_3543 ) , .clk_3_W_in ( p2949 ) , + .clk_3_E_in ( p1167 ) , .clk_3_S_in ( p2061 ) , .clk_3_N_in ( p3175 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_3544 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_3545 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_3546 ) , @@ -110108,16 +114630,16 @@ sb_1__1_ sb_5__8_ ( .chanx_right_out ( sb_1__1__51_chanx_right_out ) , .chany_bottom_out ( sb_1__1__51_chany_bottom_out ) , .chanx_left_out ( sb_1__1__51_chanx_left_out ) , - .ccff_tail ( sb_1__1__51_ccff_tail ) , .Test_en_S_in ( p2117 ) , + .ccff_tail ( sb_1__1__51_ccff_tail ) , .Test_en_S_in ( p2548 ) , .Test_en_N_out ( SYNOPSYS_UNCONNECTED_3549 ) , .pReset_S_in ( SYNOPSYS_UNCONNECTED_3550 ) , .pReset_E_in ( pResetWires[425] ) , .pReset_W_in ( SYNOPSYS_UNCONNECTED_3551 ) , .pReset_N_out ( pResetWires[424] ) , .pReset_W_out ( pResetWires[422] ) , - .pReset_E_out ( SYNOPSYS_UNCONNECTED_3552 ) , .Reset_S_in ( p2117 ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_3552 ) , .Reset_S_in ( p2548 ) , .Reset_N_out ( SYNOPSYS_UNCONNECTED_3553 ) , - .prog_clk_0_N_in ( prog_clk_0_wires[203] ) , .prog_clk_1_N_in ( p1338 ) , - .prog_clk_1_S_in ( p308 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[203] ) , .prog_clk_1_N_in ( p1852 ) , + .prog_clk_1_S_in ( p451 ) , .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_3554 ) , .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_3555 ) , .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_3556 ) , @@ -110128,13 +114650,13 @@ sb_1__1_ sb_5__8_ ( .prog_clk_2_S_out ( prog_clk_2_wires[57] ) , .prog_clk_2_N_out ( prog_clk_2_wires[55] ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_3560 ) , - .prog_clk_3_W_in ( p2417 ) , .prog_clk_3_E_in ( p87 ) , - .prog_clk_3_S_in ( p100 ) , .prog_clk_3_N_in ( p1677 ) , + .prog_clk_3_W_in ( p1526 ) , .prog_clk_3_E_in ( p365 ) , + .prog_clk_3_S_in ( p274 ) , .prog_clk_3_N_in ( p1791 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_3561 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_3562 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_3563 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_3564 ) , .clk_1_N_in ( p1338 ) , - .clk_1_S_in ( p789 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_3565 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_3564 ) , .clk_1_N_in ( p1852 ) , + .clk_1_S_in ( p1089 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_3565 ) , .clk_1_W_out ( SYNOPSYS_UNCONNECTED_3566 ) , .clk_2_N_in ( SYNOPSYS_UNCONNECTED_3567 ) , .clk_2_E_in ( SYNOPSYS_UNCONNECTED_3568 ) , @@ -110142,8 +114664,8 @@ sb_1__1_ sb_5__8_ ( .clk_2_W_in ( clk_2_wires[48] ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_3570 ) , .clk_2_S_out ( clk_2_wires[57] ) , .clk_2_N_out ( clk_2_wires[55] ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_3571 ) , .clk_3_W_in ( p2417 ) , - .clk_3_E_in ( p1015 ) , .clk_3_S_in ( p1978 ) , .clk_3_N_in ( p534 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_3571 ) , .clk_3_W_in ( p1526 ) , + .clk_3_E_in ( p103 ) , .clk_3_S_in ( p2385 ) , .clk_3_N_in ( p1710 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_3572 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_3573 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_3574 ) , @@ -110191,40 +114713,40 @@ sb_1__1_ sb_5__9_ ( .chanx_right_out ( sb_1__1__52_chanx_right_out ) , .chany_bottom_out ( sb_1__1__52_chany_bottom_out ) , .chanx_left_out ( sb_1__1__52_chanx_left_out ) , - .ccff_tail ( sb_1__1__52_ccff_tail ) , .Test_en_S_in ( p3083 ) , + .ccff_tail ( sb_1__1__52_ccff_tail ) , .Test_en_S_in ( p1829 ) , .Test_en_N_out ( SYNOPSYS_UNCONNECTED_3577 ) , .pReset_S_in ( SYNOPSYS_UNCONNECTED_3578 ) , .pReset_E_in ( pResetWires[474] ) , .pReset_W_in ( SYNOPSYS_UNCONNECTED_3579 ) , .pReset_N_out ( pResetWires[473] ) , .pReset_W_out ( pResetWires[471] ) , - .pReset_E_out ( SYNOPSYS_UNCONNECTED_3580 ) , .Reset_S_in ( p3192 ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_3580 ) , .Reset_S_in ( p1829 ) , .Reset_N_out ( SYNOPSYS_UNCONNECTED_3581 ) , .prog_clk_0_N_in ( prog_clk_0_wires[206] ) , .prog_clk_1_N_in ( SYNOPSYS_UNCONNECTED_3582 ) , .prog_clk_1_S_in ( prog_clk_2_wires[56] ) , .prog_clk_1_E_out ( prog_clk_1_wires[113] ) , - .prog_clk_1_W_out ( prog_clk_1_wires[114] ) , .prog_clk_2_N_in ( p3471 ) , - .prog_clk_2_E_in ( p1263 ) , .prog_clk_2_S_in ( p602 ) , - .prog_clk_2_W_in ( p1088 ) , + .prog_clk_1_W_out ( prog_clk_1_wires[114] ) , .prog_clk_2_N_in ( p3618 ) , + .prog_clk_2_E_in ( p269 ) , .prog_clk_2_S_in ( p987 ) , + .prog_clk_2_W_in ( p733 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_3583 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_3584 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_3585 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_3586 ) , - .prog_clk_3_W_in ( p2445 ) , .prog_clk_3_E_in ( p91 ) , - .prog_clk_3_S_in ( p1034 ) , .prog_clk_3_N_in ( p3463 ) , + .prog_clk_3_W_in ( p3274 ) , .prog_clk_3_E_in ( p686 ) , + .prog_clk_3_S_in ( p794 ) , .prog_clk_3_N_in ( p3617 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_3587 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_3588 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_3589 ) , .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_3590 ) , .clk_1_N_in ( SYNOPSYS_UNCONNECTED_3591 ) , .clk_1_S_in ( clk_2_wires[56] ) , .clk_1_E_out ( clk_1_wires[113] ) , - .clk_1_W_out ( clk_1_wires[114] ) , .clk_2_N_in ( p2584 ) , - .clk_2_E_in ( p742 ) , .clk_2_S_in ( p3138 ) , .clk_2_W_in ( p2331 ) , + .clk_1_W_out ( clk_1_wires[114] ) , .clk_2_N_in ( p3267 ) , + .clk_2_E_in ( p345 ) , .clk_2_S_in ( p923 ) , .clk_2_W_in ( p3190 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_3592 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_3593 ) , .clk_2_N_out ( SYNOPSYS_UNCONNECTED_3594 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_3595 ) , .clk_3_W_in ( p2445 ) , - .clk_3_E_in ( p1162 ) , .clk_3_S_in ( p1298 ) , .clk_3_N_in ( p2556 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_3595 ) , .clk_3_W_in ( p3024 ) , + .clk_3_E_in ( p938 ) , .clk_3_S_in ( p1667 ) , .clk_3_N_in ( p3217 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_3596 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_3597 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_3598 ) , @@ -110272,16 +114794,16 @@ sb_1__1_ sb_5__10_ ( .chanx_right_out ( sb_1__1__53_chanx_right_out ) , .chany_bottom_out ( sb_1__1__53_chany_bottom_out ) , .chanx_left_out ( sb_1__1__53_chanx_left_out ) , - .ccff_tail ( sb_1__1__53_ccff_tail ) , .Test_en_S_in ( p2467 ) , + .ccff_tail ( sb_1__1__53_ccff_tail ) , .Test_en_S_in ( p2221 ) , .Test_en_N_out ( SYNOPSYS_UNCONNECTED_3601 ) , .pReset_S_in ( SYNOPSYS_UNCONNECTED_3602 ) , .pReset_E_in ( pResetWires[523] ) , .pReset_W_in ( SYNOPSYS_UNCONNECTED_3603 ) , .pReset_N_out ( pResetWires[522] ) , .pReset_W_out ( pResetWires[520] ) , - .pReset_E_out ( SYNOPSYS_UNCONNECTED_3604 ) , .Reset_S_in ( p2467 ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_3604 ) , .Reset_S_in ( p2221 ) , .Reset_N_out ( SYNOPSYS_UNCONNECTED_3605 ) , - .prog_clk_0_N_in ( prog_clk_0_wires[209] ) , .prog_clk_1_N_in ( p1813 ) , - .prog_clk_1_S_in ( p457 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[209] ) , .prog_clk_1_N_in ( p1399 ) , + .prog_clk_1_S_in ( p1269 ) , .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_3606 ) , .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_3607 ) , .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_3608 ) , @@ -110292,13 +114814,13 @@ sb_1__1_ sb_5__10_ ( .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_3612 ) , .prog_clk_2_N_out ( prog_clk_2_wires[66] ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_3613 ) , - .prog_clk_3_W_in ( p1493 ) , .prog_clk_3_E_in ( p93 ) , - .prog_clk_3_S_in ( p7 ) , .prog_clk_3_N_in ( p728 ) , + .prog_clk_3_W_in ( p1903 ) , .prog_clk_3_E_in ( p305 ) , + .prog_clk_3_S_in ( p559 ) , .prog_clk_3_N_in ( p1683 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_3614 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_3615 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_3616 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_3617 ) , .clk_1_N_in ( p1813 ) , - .clk_1_S_in ( p417 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_3618 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_3617 ) , .clk_1_N_in ( p1399 ) , + .clk_1_S_in ( p654 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_3618 ) , .clk_1_W_out ( SYNOPSYS_UNCONNECTED_3619 ) , .clk_2_N_in ( SYNOPSYS_UNCONNECTED_3620 ) , .clk_2_E_in ( SYNOPSYS_UNCONNECTED_3621 ) , @@ -110307,8 +114829,8 @@ sb_1__1_ sb_5__10_ ( .clk_2_W_out ( SYNOPSYS_UNCONNECTED_3623 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_3624 ) , .clk_2_N_out ( clk_2_wires[66] ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_3625 ) , .clk_3_W_in ( p1493 ) , - .clk_3_E_in ( p790 ) , .clk_3_S_in ( p2278 ) , .clk_3_N_in ( p1642 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_3625 ) , .clk_3_W_in ( p1903 ) , + .clk_3_E_in ( p1025 ) , .clk_3_S_in ( p2117 ) , .clk_3_N_in ( p266 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_3626 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_3627 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_3628 ) , @@ -110356,40 +114878,40 @@ sb_1__1_ sb_5__11_ ( .chanx_right_out ( sb_1__1__54_chanx_right_out ) , .chany_bottom_out ( sb_1__1__54_chany_bottom_out ) , .chanx_left_out ( sb_1__1__54_chanx_left_out ) , - .ccff_tail ( sb_1__1__54_ccff_tail ) , .Test_en_S_in ( p2194 ) , + .ccff_tail ( sb_1__1__54_ccff_tail ) , .Test_en_S_in ( p2767 ) , .Test_en_N_out ( SYNOPSYS_UNCONNECTED_3631 ) , .pReset_S_in ( SYNOPSYS_UNCONNECTED_3632 ) , .pReset_E_in ( pResetWires[572] ) , .pReset_W_in ( SYNOPSYS_UNCONNECTED_3633 ) , .pReset_N_out ( pResetWires[571] ) , .pReset_W_out ( pResetWires[569] ) , - .pReset_E_out ( SYNOPSYS_UNCONNECTED_3634 ) , .Reset_S_in ( p2194 ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_3634 ) , .Reset_S_in ( p2767 ) , .Reset_N_out ( SYNOPSYS_UNCONNECTED_3635 ) , .prog_clk_0_N_in ( prog_clk_0_wires[212] ) , .prog_clk_1_N_in ( SYNOPSYS_UNCONNECTED_3636 ) , .prog_clk_1_S_in ( prog_clk_2_wires[67] ) , .prog_clk_1_E_out ( prog_clk_1_wires[120] ) , - .prog_clk_1_W_out ( prog_clk_1_wires[121] ) , .prog_clk_2_N_in ( p3451 ) , - .prog_clk_2_E_in ( p772 ) , .prog_clk_2_S_in ( p280 ) , - .prog_clk_2_W_in ( p351 ) , + .prog_clk_1_W_out ( prog_clk_1_wires[121] ) , .prog_clk_2_N_in ( p3414 ) , + .prog_clk_2_E_in ( p331 ) , .prog_clk_2_S_in ( p1312 ) , + .prog_clk_2_W_in ( p461 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_3637 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_3638 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_3639 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_3640 ) , - .prog_clk_3_W_in ( p2630 ) , .prog_clk_3_E_in ( p1273 ) , - .prog_clk_3_S_in ( p1349 ) , .prog_clk_3_N_in ( p3446 ) , + .prog_clk_3_W_in ( p2816 ) , .prog_clk_3_E_in ( p540 ) , + .prog_clk_3_S_in ( p653 ) , .prog_clk_3_N_in ( p3373 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_3641 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_3642 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_3643 ) , .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_3644 ) , .clk_1_N_in ( SYNOPSYS_UNCONNECTED_3645 ) , .clk_1_S_in ( clk_2_wires[67] ) , .clk_1_E_out ( clk_1_wires[120] ) , - .clk_1_W_out ( clk_1_wires[121] ) , .clk_2_N_in ( p3172 ) , - .clk_2_E_in ( p43 ) , .clk_2_S_in ( p1990 ) , .clk_2_W_in ( p2540 ) , + .clk_1_W_out ( clk_1_wires[121] ) , .clk_2_N_in ( p3232 ) , + .clk_2_E_in ( p394 ) , .clk_2_S_in ( p288 ) , .clk_2_W_in ( p3582 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_3646 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_3647 ) , .clk_2_N_out ( SYNOPSYS_UNCONNECTED_3648 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_3649 ) , .clk_3_W_in ( p2630 ) , - .clk_3_E_in ( p875 ) , .clk_3_S_in ( p225 ) , .clk_3_N_in ( p3144 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_3649 ) , .clk_3_W_in ( p3590 ) , + .clk_3_E_in ( p758 ) , .clk_3_S_in ( p2685 ) , .clk_3_N_in ( p3203 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_3650 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_3651 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_3652 ) , @@ -110444,12 +114966,12 @@ sb_1__1_ sb_6__1_ ( .pReset_N_out ( pResetWires[85] ) , .pReset_W_out ( pResetWires[83] ) , .pReset_E_out ( pResetWires[86] ) , .Reset_S_in ( ResetWires[2] ) , .Reset_N_out ( ResetWires[3] ) , - .prog_clk_0_N_in ( prog_clk_0_wires[220] ) , .prog_clk_1_N_in ( p1347 ) , - .prog_clk_1_S_in ( p178 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[220] ) , .prog_clk_1_N_in ( p1553 ) , + .prog_clk_1_S_in ( p1102 ) , .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_3657 ) , .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_3658 ) , - .prog_clk_2_N_in ( p1503 ) , .prog_clk_2_E_in ( p1100 ) , - .prog_clk_2_S_in ( p1999 ) , .prog_clk_2_W_in ( p205 ) , + .prog_clk_2_N_in ( p1270 ) , .prog_clk_2_E_in ( p306 ) , + .prog_clk_2_S_in ( p620 ) , .prog_clk_2_W_in ( p859 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_3659 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_3660 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_3661 ) , @@ -110461,10 +114983,10 @@ sb_1__1_ sb_6__1_ ( .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_3666 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_3667 ) , .prog_clk_3_N_out ( prog_clk_3_wires[92] ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_3668 ) , .clk_1_N_in ( p1347 ) , - .clk_1_S_in ( p630 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_3669 ) , - .clk_1_W_out ( SYNOPSYS_UNCONNECTED_3670 ) , .clk_2_N_in ( p1503 ) , - .clk_2_E_in ( p558 ) , .clk_2_S_in ( p695 ) , .clk_2_W_in ( p1153 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_3668 ) , .clk_1_N_in ( p1553 ) , + .clk_1_S_in ( p672 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_3669 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_3670 ) , .clk_2_N_in ( p1270 ) , + .clk_2_E_in ( p184 ) , .clk_2_S_in ( p95 ) , .clk_2_W_in ( p410 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_3671 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_3672 ) , .clk_2_N_out ( SYNOPSYS_UNCONNECTED_3673 ) , @@ -110527,12 +115049,12 @@ sb_1__1_ sb_6__2_ ( .pReset_N_out ( pResetWires[134] ) , .pReset_W_out ( pResetWires[132] ) , .pReset_E_out ( pResetWires[135] ) , .Reset_S_in ( ResetWires[4] ) , .Reset_N_out ( ResetWires[5] ) , - .prog_clk_0_N_in ( prog_clk_0_wires[223] ) , .prog_clk_1_N_in ( p1615 ) , - .prog_clk_1_S_in ( p86 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[223] ) , .prog_clk_1_N_in ( p1508 ) , + .prog_clk_1_S_in ( p317 ) , .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_3684 ) , .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_3685 ) , - .prog_clk_2_N_in ( p2696 ) , .prog_clk_2_E_in ( p377 ) , - .prog_clk_2_S_in ( p1668 ) , .prog_clk_2_W_in ( p1114 ) , + .prog_clk_2_N_in ( p2580 ) , .prog_clk_2_E_in ( p549 ) , + .prog_clk_2_S_in ( p89 ) , .prog_clk_2_W_in ( p409 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_3686 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_3687 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_3688 ) , @@ -110544,10 +115066,10 @@ sb_1__1_ sb_6__2_ ( .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_3693 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_3694 ) , .prog_clk_3_N_out ( prog_clk_3_wires[94] ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_3695 ) , .clk_1_N_in ( p1615 ) , - .clk_1_S_in ( p862 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_3696 ) , - .clk_1_W_out ( SYNOPSYS_UNCONNECTED_3697 ) , .clk_2_N_in ( p1940 ) , - .clk_2_E_in ( p704 ) , .clk_2_S_in ( p446 ) , .clk_2_W_in ( p296 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_3695 ) , .clk_1_N_in ( p1508 ) , + .clk_1_S_in ( p1188 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_3696 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_3697 ) , .clk_2_N_in ( p2580 ) , + .clk_2_E_in ( p556 ) , .clk_2_S_in ( p466 ) , .clk_2_W_in ( p209 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_3698 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_3699 ) , .clk_2_N_out ( SYNOPSYS_UNCONNECTED_3700 ) , @@ -110610,12 +115132,12 @@ sb_1__1_ sb_6__3_ ( .pReset_N_out ( pResetWires[183] ) , .pReset_W_out ( pResetWires[181] ) , .pReset_E_out ( pResetWires[184] ) , .Reset_S_in ( ResetWires[6] ) , .Reset_N_out ( ResetWires[7] ) , - .prog_clk_0_N_in ( prog_clk_0_wires[226] ) , .prog_clk_1_N_in ( p1550 ) , - .prog_clk_1_S_in ( p710 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[226] ) , .prog_clk_1_N_in ( p1567 ) , + .prog_clk_1_S_in ( p897 ) , .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_3711 ) , .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_3712 ) , - .prog_clk_2_N_in ( p1931 ) , .prog_clk_2_E_in ( p729 ) , - .prog_clk_2_S_in ( p1680 ) , .prog_clk_2_W_in ( p916 ) , + .prog_clk_2_N_in ( p3139 ) , .prog_clk_2_E_in ( p610 ) , + .prog_clk_2_S_in ( p783 ) , .prog_clk_2_W_in ( p264 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_3713 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_3714 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_3715 ) , @@ -110627,10 +115149,10 @@ sb_1__1_ sb_6__3_ ( .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_3720 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_3721 ) , .prog_clk_3_N_out ( prog_clk_3_wires[96] ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_3722 ) , .clk_1_N_in ( p1550 ) , - .clk_1_S_in ( p135 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_3723 ) , - .clk_1_W_out ( SYNOPSYS_UNCONNECTED_3724 ) , .clk_2_N_in ( p1931 ) , - .clk_2_E_in ( p74 ) , .clk_2_S_in ( p565 ) , .clk_2_W_in ( p247 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_3722 ) , .clk_1_N_in ( p1567 ) , + .clk_1_S_in ( p253 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_3723 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_3724 ) , .clk_2_N_in ( p1874 ) , + .clk_2_E_in ( p149 ) , .clk_2_S_in ( p283 ) , .clk_2_W_in ( p693 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_3725 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_3726 ) , .clk_2_N_out ( SYNOPSYS_UNCONNECTED_3727 ) , @@ -110693,12 +115215,12 @@ sb_1__1_ sb_6__4_ ( .pReset_N_out ( pResetWires[232] ) , .pReset_W_out ( pResetWires[230] ) , .pReset_E_out ( pResetWires[233] ) , .Reset_S_in ( ResetWires[8] ) , .Reset_N_out ( ResetWires[9] ) , - .prog_clk_0_N_in ( prog_clk_0_wires[229] ) , .prog_clk_1_N_in ( p1317 ) , - .prog_clk_1_S_in ( p96 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[229] ) , .prog_clk_1_N_in ( p1438 ) , + .prog_clk_1_S_in ( p206 ) , .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_3738 ) , .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_3739 ) , - .prog_clk_2_N_in ( p2949 ) , .prog_clk_2_E_in ( p706 ) , - .prog_clk_2_S_in ( p1670 ) , .prog_clk_2_W_in ( p201 ) , + .prog_clk_2_N_in ( p2213 ) , .prog_clk_2_E_in ( p377 ) , + .prog_clk_2_S_in ( p1772 ) , .prog_clk_2_W_in ( p235 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_3740 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_3741 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_3742 ) , @@ -110710,10 +115232,10 @@ sb_1__1_ sb_6__4_ ( .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_3747 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_3748 ) , .prog_clk_3_N_out ( prog_clk_3_wires[98] ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_3749 ) , .clk_1_N_in ( p1317 ) , - .clk_1_S_in ( p1075 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_3750 ) , - .clk_1_W_out ( SYNOPSYS_UNCONNECTED_3751 ) , .clk_2_N_in ( p2452 ) , - .clk_2_E_in ( p254 ) , .clk_2_S_in ( p431 ) , .clk_2_W_in ( p393 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_3749 ) , .clk_1_N_in ( p1438 ) , + .clk_1_S_in ( p578 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_3750 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_3751 ) , .clk_2_N_in ( p1277 ) , + .clk_2_E_in ( p233 ) , .clk_2_S_in ( p1686 ) , .clk_2_W_in ( p937 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_3752 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_3753 ) , .clk_2_N_out ( SYNOPSYS_UNCONNECTED_3754 ) , @@ -110777,12 +115299,12 @@ sb_1__1_ sb_6__5_ ( .pReset_N_out ( pResetWires[281] ) , .pReset_W_out ( pResetWires[279] ) , .pReset_E_out ( pResetWires[282] ) , .Reset_S_in ( ResetWires[10] ) , .Reset_N_out ( ResetWires[11] ) , - .prog_clk_0_N_in ( prog_clk_0_wires[232] ) , .prog_clk_1_N_in ( p1821 ) , - .prog_clk_1_S_in ( p1006 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[232] ) , .prog_clk_1_N_in ( p1458 ) , + .prog_clk_1_S_in ( p1159 ) , .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_3765 ) , .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_3766 ) , - .prog_clk_2_N_in ( p2804 ) , .prog_clk_2_E_in ( p399 ) , - .prog_clk_2_S_in ( p1673 ) , .prog_clk_2_W_in ( p310 ) , + .prog_clk_2_N_in ( p1878 ) , .prog_clk_2_E_in ( p592 ) , + .prog_clk_2_S_in ( p446 ) , .prog_clk_2_W_in ( p710 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_3767 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_3768 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_3769 ) , @@ -110794,10 +115316,10 @@ sb_1__1_ sb_6__5_ ( .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_3774 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_3775 ) , .prog_clk_3_N_out ( prog_clk_3_wires[100] ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_3776 ) , .clk_1_N_in ( p1821 ) , - .clk_1_S_in ( p432 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_3777 ) , - .clk_1_W_out ( SYNOPSYS_UNCONNECTED_3778 ) , .clk_2_N_in ( p2712 ) , - .clk_2_E_in ( p799 ) , .clk_2_S_in ( p483 ) , .clk_2_W_in ( p1168 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_3776 ) , .clk_1_N_in ( p1458 ) , + .clk_1_S_in ( p28 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_3777 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_3778 ) , .clk_2_N_in ( p1878 ) , + .clk_2_E_in ( p729 ) , .clk_2_S_in ( p704 ) , .clk_2_W_in ( p53 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_3779 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_3780 ) , .clk_2_N_out ( SYNOPSYS_UNCONNECTED_3781 ) , @@ -110861,12 +115383,12 @@ sb_1__1_ sb_6__6_ ( .pReset_N_out ( pResetWires[330] ) , .pReset_W_out ( pResetWires[328] ) , .pReset_E_out ( pResetWires[331] ) , .Reset_S_in ( ResetWires[12] ) , .Reset_N_out ( ResetWires[13] ) , - .prog_clk_0_N_in ( prog_clk_0_wires[235] ) , .prog_clk_1_N_in ( p1521 ) , - .prog_clk_1_S_in ( p773 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[235] ) , .prog_clk_1_N_in ( p1476 ) , + .prog_clk_1_S_in ( p1035 ) , .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_3792 ) , .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_3793 ) , - .prog_clk_2_N_in ( p1435 ) , .prog_clk_2_E_in ( p963 ) , - .prog_clk_2_S_in ( p2001 ) , .prog_clk_2_W_in ( p1666 ) , + .prog_clk_2_N_in ( p3011 ) , .prog_clk_2_E_in ( p709 ) , + .prog_clk_2_S_in ( p359 ) , .prog_clk_2_W_in ( p2053 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_3794 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_3795 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_3796 ) , @@ -110878,10 +115400,10 @@ sb_1__1_ sb_6__6_ ( .prog_clk_3_E_out ( prog_clk_3_wires[0] ) , .prog_clk_3_W_out ( prog_clk_3_wires[2] ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_3801 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_3802 ) , .clk_1_N_in ( p1521 ) , - .clk_1_S_in ( p365 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_3803 ) , - .clk_1_W_out ( SYNOPSYS_UNCONNECTED_3804 ) , .clk_2_N_in ( p1840 ) , - .clk_2_E_in ( p26 ) , .clk_2_S_in ( p390 ) , .clk_2_W_in ( p174 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_3802 ) , .clk_1_N_in ( p1476 ) , + .clk_1_S_in ( p98 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_3803 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_3804 ) , .clk_2_N_in ( p2015 ) , + .clk_2_E_in ( p272 ) , .clk_2_S_in ( p671 ) , .clk_2_W_in ( p617 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_3805 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_3806 ) , .clk_2_N_out ( SYNOPSYS_UNCONNECTED_3807 ) , @@ -110944,30 +115466,30 @@ sb_1__1_ sb_6__7_ ( .pReset_N_out ( pResetWires[379] ) , .pReset_W_out ( pResetWires[377] ) , .pReset_E_out ( pResetWires[380] ) , .Reset_S_in ( ResetWires[14] ) , .Reset_N_out ( ResetWires[15] ) , - .prog_clk_0_N_in ( prog_clk_0_wires[238] ) , .prog_clk_1_N_in ( p2161 ) , - .prog_clk_1_S_in ( p1170 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[238] ) , .prog_clk_1_N_in ( p1206 ) , + .prog_clk_1_S_in ( p560 ) , .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_3817 ) , .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_3818 ) , - .prog_clk_2_N_in ( p3435 ) , .prog_clk_2_E_in ( p887 ) , - .prog_clk_2_S_in ( p663 ) , .prog_clk_2_W_in ( p57 ) , + .prog_clk_2_N_in ( p3609 ) , .prog_clk_2_E_in ( p10 ) , + .prog_clk_2_S_in ( p293 ) , .prog_clk_2_W_in ( p270 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_3819 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_3820 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_3821 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_3822 ) , - .prog_clk_3_W_in ( p2465 ) , .prog_clk_3_E_in ( p1234 ) , - .prog_clk_3_S_in ( p1175 ) , .prog_clk_3_N_in ( p3423 ) , + .prog_clk_3_W_in ( p3341 ) , .prog_clk_3_E_in ( p635 ) , + .prog_clk_3_S_in ( p1107 ) , .prog_clk_3_N_in ( p3607 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_3823 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_3824 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_3825 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_3826 ) , .clk_1_N_in ( p2161 ) , - .clk_1_S_in ( p99 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_3827 ) , - .clk_1_W_out ( SYNOPSYS_UNCONNECTED_3828 ) , .clk_2_N_in ( p3494 ) , - .clk_2_E_in ( p113 ) , .clk_2_S_in ( p1072 ) , .clk_2_W_in ( p2282 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_3826 ) , .clk_1_N_in ( p1206 ) , + .clk_1_S_in ( p1027 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_3827 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_3828 ) , .clk_2_N_in ( p2833 ) , + .clk_2_E_in ( p1220 ) , .clk_2_S_in ( p922 ) , .clk_2_W_in ( p3379 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_3829 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_3830 ) , .clk_2_N_out ( SYNOPSYS_UNCONNECTED_3831 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_3832 ) , .clk_3_W_in ( p2465 ) , - .clk_3_E_in ( p883 ) , .clk_3_S_in ( p260 ) , .clk_3_N_in ( p3491 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_3832 ) , .clk_3_W_in ( p3398 ) , + .clk_3_E_in ( p392 ) , .clk_3_S_in ( p223 ) , .clk_3_N_in ( p2712 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_3833 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_3834 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_3835 ) , @@ -111023,30 +115545,30 @@ sb_1__1_ sb_6__8_ ( .pReset_N_out ( pResetWires[428] ) , .pReset_W_out ( pResetWires[426] ) , .pReset_E_out ( pResetWires[429] ) , .Reset_S_in ( ResetWires[16] ) , .Reset_N_out ( ResetWires[17] ) , - .prog_clk_0_N_in ( prog_clk_0_wires[241] ) , .prog_clk_1_N_in ( p1203 ) , - .prog_clk_1_S_in ( p228 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[241] ) , .prog_clk_1_N_in ( p2028 ) , + .prog_clk_1_S_in ( p1296 ) , .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_3840 ) , .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_3841 ) , - .prog_clk_2_N_in ( p3355 ) , .prog_clk_2_E_in ( p949 ) , - .prog_clk_2_S_in ( p283 ) , .prog_clk_2_W_in ( p1390 ) , + .prog_clk_2_N_in ( p3401 ) , .prog_clk_2_E_in ( p426 ) , + .prog_clk_2_S_in ( p1131 ) , .prog_clk_2_W_in ( p57 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_3842 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_3843 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_3844 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_3845 ) , - .prog_clk_3_W_in ( p2622 ) , .prog_clk_3_E_in ( p435 ) , - .prog_clk_3_S_in ( p956 ) , .prog_clk_3_N_in ( p3349 ) , + .prog_clk_3_W_in ( p2635 ) , .prog_clk_3_E_in ( p478 ) , + .prog_clk_3_S_in ( p408 ) , .prog_clk_3_N_in ( p3389 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_3846 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_3847 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_3848 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_3849 ) , .clk_1_N_in ( p1203 ) , - .clk_1_S_in ( p709 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_3850 ) , - .clk_1_W_out ( SYNOPSYS_UNCONNECTED_3851 ) , .clk_2_N_in ( p3075 ) , - .clk_2_E_in ( p712 ) , .clk_2_S_in ( p1282 ) , .clk_2_W_in ( p2531 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_3849 ) , .clk_1_N_in ( p2028 ) , + .clk_1_S_in ( p400 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_3850 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_3851 ) , .clk_2_N_in ( p3512 ) , + .clk_2_E_in ( p186 ) , .clk_2_S_in ( p1212 ) , .clk_2_W_in ( p3188 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_3852 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_3853 ) , .clk_2_N_out ( SYNOPSYS_UNCONNECTED_3854 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_3855 ) , .clk_3_W_in ( p2622 ) , - .clk_3_E_in ( p180 ) , .clk_3_S_in ( p717 ) , .clk_3_N_in ( p3026 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_3855 ) , .clk_3_W_in ( p3271 ) , + .clk_3_E_in ( p1099 ) , .clk_3_S_in ( p101 ) , .clk_3_N_in ( p3478 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_3856 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_3857 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_3858 ) , @@ -111102,30 +115624,30 @@ sb_1__1_ sb_6__9_ ( .pReset_N_out ( pResetWires[477] ) , .pReset_W_out ( pResetWires[475] ) , .pReset_E_out ( pResetWires[478] ) , .Reset_S_in ( ResetWires[18] ) , .Reset_N_out ( ResetWires[19] ) , - .prog_clk_0_N_in ( prog_clk_0_wires[244] ) , .prog_clk_1_N_in ( p1573 ) , - .prog_clk_1_S_in ( p258 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[244] ) , .prog_clk_1_N_in ( p1556 ) , + .prog_clk_1_S_in ( p947 ) , .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_3863 ) , .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_3864 ) , - .prog_clk_2_N_in ( p3455 ) , .prog_clk_2_E_in ( p968 ) , - .prog_clk_2_S_in ( p1303 ) , .prog_clk_2_W_in ( p269 ) , + .prog_clk_2_N_in ( p3559 ) , .prog_clk_2_E_in ( p321 ) , + .prog_clk_2_S_in ( p966 ) , .prog_clk_2_W_in ( p116 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_3865 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_3866 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_3867 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_3868 ) , - .prog_clk_3_W_in ( p2149 ) , .prog_clk_3_E_in ( p219 ) , - .prog_clk_3_S_in ( p686 ) , .prog_clk_3_N_in ( p3439 ) , + .prog_clk_3_W_in ( p3226 ) , .prog_clk_3_E_in ( p832 ) , + .prog_clk_3_S_in ( p553 ) , .prog_clk_3_N_in ( p3550 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_3869 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_3870 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_3871 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_3872 ) , .clk_1_N_in ( p1573 ) , - .clk_1_S_in ( p660 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_3873 ) , - .clk_1_W_out ( SYNOPSYS_UNCONNECTED_3874 ) , .clk_2_N_in ( p2703 ) , - .clk_2_E_in ( p416 ) , .clk_2_S_in ( p1444 ) , .clk_2_W_in ( p1972 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_3872 ) , .clk_1_N_in ( p1556 ) , + .clk_1_S_in ( p407 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_3873 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_3874 ) , .clk_2_N_in ( p3399 ) , + .clk_2_E_in ( p364 ) , .clk_2_S_in ( p289 ) , .clk_2_W_in ( p3186 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_3875 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_3876 ) , .clk_2_N_out ( SYNOPSYS_UNCONNECTED_3877 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_3878 ) , .clk_3_W_in ( p2149 ) , - .clk_3_E_in ( p162 ) , .clk_3_S_in ( p482 ) , .clk_3_N_in ( p2583 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_3878 ) , .clk_3_W_in ( p3256 ) , + .clk_3_E_in ( p1076 ) , .clk_3_S_in ( p1117 ) , .clk_3_N_in ( p3392 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_3879 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_3880 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_3881 ) , @@ -111181,30 +115703,30 @@ sb_1__1_ sb_6__10_ ( .pReset_N_out ( pResetWires[526] ) , .pReset_W_out ( pResetWires[524] ) , .pReset_E_out ( pResetWires[527] ) , .Reset_S_in ( ResetWires[20] ) , .Reset_N_out ( ResetWires[21] ) , - .prog_clk_0_N_in ( prog_clk_0_wires[247] ) , .prog_clk_1_N_in ( p1876 ) , - .prog_clk_1_S_in ( p554 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[247] ) , .prog_clk_1_N_in ( p1294 ) , + .prog_clk_1_S_in ( p1219 ) , .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_3886 ) , .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_3887 ) , - .prog_clk_2_N_in ( p2974 ) , .prog_clk_2_E_in ( p1352 ) , - .prog_clk_2_S_in ( p1241 ) , .prog_clk_2_W_in ( p212 ) , + .prog_clk_2_N_in ( p3351 ) , .prog_clk_2_E_in ( p40 ) , + .prog_clk_2_S_in ( p1019 ) , .prog_clk_2_W_in ( p932 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_3888 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_3889 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_3890 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_3891 ) , - .prog_clk_3_W_in ( p3073 ) , .prog_clk_3_E_in ( p1076 ) , - .prog_clk_3_S_in ( p77 ) , .prog_clk_3_N_in ( p2918 ) , + .prog_clk_3_W_in ( p2199 ) , .prog_clk_3_E_in ( p682 ) , + .prog_clk_3_S_in ( p197 ) , .prog_clk_3_N_in ( p3295 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_3892 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_3893 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_3894 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_3895 ) , .clk_1_N_in ( p1876 ) , - .clk_1_S_in ( p306 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_3896 ) , - .clk_1_W_out ( SYNOPSYS_UNCONNECTED_3897 ) , .clk_2_N_in ( p3268 ) , - .clk_2_E_in ( p589 ) , .clk_2_S_in ( p440 ) , .clk_2_W_in ( p3012 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_3895 ) , .clk_1_N_in ( p1294 ) , + .clk_1_S_in ( p90 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_3896 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_3897 ) , .clk_2_N_in ( p2018 ) , + .clk_2_E_in ( p580 ) , .clk_2_S_in ( p537 ) , .clk_2_W_in ( p3431 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_3898 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_3899 ) , .clk_2_N_out ( SYNOPSYS_UNCONNECTED_3900 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_3901 ) , .clk_3_W_in ( p3073 ) , - .clk_3_E_in ( p156 ) , .clk_3_S_in ( p1196 ) , .clk_3_N_in ( p3218 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_3901 ) , .clk_3_W_in ( p3473 ) , + .clk_3_E_in ( p1100 ) , .clk_3_S_in ( p1274 ) , .clk_3_N_in ( p1701 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_3902 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_3903 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_3904 ) , @@ -111260,30 +115782,30 @@ sb_1__1_ sb_6__11_ ( .pReset_N_out ( pResetWires[575] ) , .pReset_W_out ( pResetWires[573] ) , .pReset_E_out ( pResetWires[576] ) , .Reset_S_in ( ResetWires[22] ) , .Reset_N_out ( ResetWires[23] ) , - .prog_clk_0_N_in ( prog_clk_0_wires[250] ) , .prog_clk_1_N_in ( p1937 ) , - .prog_clk_1_S_in ( p998 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[250] ) , .prog_clk_1_N_in ( p1802 ) , + .prog_clk_1_S_in ( p974 ) , .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_3909 ) , .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_3910 ) , - .prog_clk_2_N_in ( p3505 ) , .prog_clk_2_E_in ( p1265 ) , - .prog_clk_2_S_in ( p1098 ) , .prog_clk_2_W_in ( p94 ) , + .prog_clk_2_N_in ( p3507 ) , .prog_clk_2_E_in ( p215 ) , + .prog_clk_2_S_in ( p1238 ) , .prog_clk_2_W_in ( p796 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_3911 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_3912 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_3913 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_3914 ) , - .prog_clk_3_W_in ( p2147 ) , .prog_clk_3_E_in ( p257 ) , - .prog_clk_3_S_in ( p182 ) , .prog_clk_3_N_in ( p3504 ) , + .prog_clk_3_W_in ( p3359 ) , .prog_clk_3_E_in ( p793 ) , + .prog_clk_3_S_in ( p531 ) , .prog_clk_3_N_in ( p3491 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_3915 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_3916 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_3917 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_3918 ) , .clk_1_N_in ( p1937 ) , - .clk_1_S_in ( p469 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_3919 ) , - .clk_1_W_out ( SYNOPSYS_UNCONNECTED_3920 ) , .clk_2_N_in ( p3092 ) , - .clk_2_E_in ( p807 ) , .clk_2_S_in ( p611 ) , .clk_2_W_in ( p2028 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_3918 ) , .clk_1_N_in ( p1802 ) , + .clk_1_S_in ( p92 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_3919 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_3920 ) , .clk_2_N_in ( p3129 ) , + .clk_2_E_in ( p738 ) , .clk_2_S_in ( p1133 ) , .clk_2_W_in ( p3305 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_3921 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_3922 ) , .clk_2_N_out ( SYNOPSYS_UNCONNECTED_3923 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_3924 ) , .clk_3_W_in ( p2147 ) , - .clk_3_E_in ( p577 ) , .clk_3_S_in ( p1118 ) , .clk_3_N_in ( p3038 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_3924 ) , .clk_3_W_in ( p3244 ) , + .clk_3_E_in ( p867 ) , .clk_3_S_in ( p412 ) , .clk_3_N_in ( p3059 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_3925 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_3926 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_3927 ) , @@ -111331,27 +115853,27 @@ sb_1__1_ sb_7__1_ ( .chanx_right_out ( sb_1__1__66_chanx_right_out ) , .chany_bottom_out ( sb_1__1__66_chany_bottom_out ) , .chanx_left_out ( sb_1__1__66_chanx_left_out ) , - .ccff_tail ( sb_1__1__66_ccff_tail ) , .Test_en_S_in ( p1292 ) , + .ccff_tail ( sb_1__1__66_ccff_tail ) , .Test_en_S_in ( p1625 ) , .Test_en_N_out ( SYNOPSYS_UNCONNECTED_3930 ) , .pReset_S_in ( SYNOPSYS_UNCONNECTED_3931 ) , .pReset_E_in ( SYNOPSYS_UNCONNECTED_3932 ) , .pReset_W_in ( pResetWires[87] ) , .pReset_N_out ( pResetWires[89] ) , .pReset_W_out ( SYNOPSYS_UNCONNECTED_3933 ) , - .pReset_E_out ( pResetWires[90] ) , .Reset_S_in ( p1292 ) , + .pReset_E_out ( pResetWires[90] ) , .Reset_S_in ( p1625 ) , .Reset_N_out ( SYNOPSYS_UNCONNECTED_3934 ) , .prog_clk_0_N_in ( prog_clk_0_wires[258] ) , .prog_clk_1_N_in ( prog_clk_2_wires[74] ) , .prog_clk_1_S_in ( SYNOPSYS_UNCONNECTED_3935 ) , .prog_clk_1_E_out ( prog_clk_1_wires[127] ) , - .prog_clk_1_W_out ( prog_clk_1_wires[128] ) , .prog_clk_2_N_in ( p3498 ) , - .prog_clk_2_E_in ( p70 ) , .prog_clk_2_S_in ( p1058 ) , - .prog_clk_2_W_in ( p1344 ) , + .prog_clk_1_W_out ( prog_clk_1_wires[128] ) , .prog_clk_2_N_in ( p3533 ) , + .prog_clk_2_E_in ( p36 ) , .prog_clk_2_S_in ( p972 ) , + .prog_clk_2_W_in ( p668 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_3936 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_3937 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_3938 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_3939 ) , - .prog_clk_3_W_in ( p2691 ) , .prog_clk_3_E_in ( p1033 ) , - .prog_clk_3_S_in ( p376 ) , .prog_clk_3_N_in ( p3496 ) , + .prog_clk_3_W_in ( p3149 ) , .prog_clk_3_E_in ( p324 ) , + .prog_clk_3_S_in ( p513 ) , .prog_clk_3_N_in ( p3517 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_3940 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_3941 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_3942 ) , @@ -111359,12 +115881,12 @@ sb_1__1_ sb_7__1_ ( .clk_1_N_in ( clk_2_wires[74] ) , .clk_1_S_in ( SYNOPSYS_UNCONNECTED_3944 ) , .clk_1_E_out ( clk_1_wires[127] ) , .clk_1_W_out ( clk_1_wires[128] ) , - .clk_2_N_in ( p2256 ) , .clk_2_E_in ( p1020 ) , .clk_2_S_in ( p1201 ) , - .clk_2_W_in ( p2533 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_3945 ) , + .clk_2_N_in ( p3620 ) , .clk_2_E_in ( p843 ) , .clk_2_S_in ( p649 ) , + .clk_2_W_in ( p3208 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_3945 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_3946 ) , .clk_2_N_out ( SYNOPSYS_UNCONNECTED_3947 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_3948 ) , .clk_3_W_in ( p2691 ) , - .clk_3_E_in ( p758 ) , .clk_3_S_in ( p261 ) , .clk_3_N_in ( p1989 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_3948 ) , .clk_3_W_in ( p3277 ) , + .clk_3_E_in ( p1118 ) , .clk_3_S_in ( p1016 ) , .clk_3_N_in ( p3619 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_3949 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_3950 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_3951 ) , @@ -111412,16 +115934,16 @@ sb_1__1_ sb_7__2_ ( .chanx_right_out ( sb_1__1__67_chanx_right_out ) , .chany_bottom_out ( sb_1__1__67_chany_bottom_out ) , .chanx_left_out ( sb_1__1__67_chanx_left_out ) , - .ccff_tail ( sb_1__1__67_ccff_tail ) , .Test_en_S_in ( p3099 ) , + .ccff_tail ( sb_1__1__67_ccff_tail ) , .Test_en_S_in ( p2520 ) , .Test_en_N_out ( SYNOPSYS_UNCONNECTED_3954 ) , .pReset_S_in ( SYNOPSYS_UNCONNECTED_3955 ) , .pReset_E_in ( SYNOPSYS_UNCONNECTED_3956 ) , .pReset_W_in ( pResetWires[136] ) , .pReset_N_out ( pResetWires[138] ) , .pReset_W_out ( SYNOPSYS_UNCONNECTED_3957 ) , - .pReset_E_out ( pResetWires[139] ) , .Reset_S_in ( p3099 ) , + .pReset_E_out ( pResetWires[139] ) , .Reset_S_in ( p2520 ) , .Reset_N_out ( SYNOPSYS_UNCONNECTED_3958 ) , - .prog_clk_0_N_in ( prog_clk_0_wires[261] ) , .prog_clk_1_N_in ( p1502 ) , - .prog_clk_1_S_in ( p381 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[261] ) , .prog_clk_1_N_in ( p1871 ) , + .prog_clk_1_S_in ( p334 ) , .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_3959 ) , .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_3960 ) , .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_3961 ) , @@ -111432,13 +115954,13 @@ sb_1__1_ sb_7__2_ ( .prog_clk_2_S_out ( prog_clk_2_wires[73] ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_3965 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_3966 ) , - .prog_clk_3_W_in ( p1872 ) , .prog_clk_3_E_in ( p806 ) , - .prog_clk_3_S_in ( p705 ) , .prog_clk_3_N_in ( p600 ) , + .prog_clk_3_W_in ( p1599 ) , .prog_clk_3_E_in ( p72 ) , + .prog_clk_3_S_in ( p878 ) , .prog_clk_3_N_in ( p716 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_3967 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_3968 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_3969 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_3970 ) , .clk_1_N_in ( p1502 ) , - .clk_1_S_in ( p434 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_3971 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_3970 ) , .clk_1_N_in ( p1871 ) , + .clk_1_S_in ( p1116 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_3971 ) , .clk_1_W_out ( SYNOPSYS_UNCONNECTED_3972 ) , .clk_2_N_in ( SYNOPSYS_UNCONNECTED_3973 ) , .clk_2_E_in ( clk_2_wires[72] ) , @@ -111447,8 +115969,8 @@ sb_1__1_ sb_7__2_ ( .clk_2_W_out ( SYNOPSYS_UNCONNECTED_3976 ) , .clk_2_S_out ( clk_2_wires[73] ) , .clk_2_N_out ( SYNOPSYS_UNCONNECTED_3977 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_3978 ) , .clk_3_W_in ( p1872 ) , - .clk_3_E_in ( p1987 ) , .clk_3_S_in ( p3025 ) , .clk_3_N_in ( p127 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_3978 ) , .clk_3_W_in ( p1599 ) , + .clk_3_E_in ( p691 ) , .clk_3_S_in ( p2429 ) , .clk_3_N_in ( p1663 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_3979 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_3980 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_3981 ) , @@ -111496,27 +116018,27 @@ sb_1__1_ sb_7__3_ ( .chanx_right_out ( sb_1__1__68_chanx_right_out ) , .chany_bottom_out ( sb_1__1__68_chany_bottom_out ) , .chanx_left_out ( sb_1__1__68_chanx_left_out ) , - .ccff_tail ( sb_1__1__68_ccff_tail ) , .Test_en_S_in ( p2642 ) , + .ccff_tail ( sb_1__1__68_ccff_tail ) , .Test_en_S_in ( p2021 ) , .Test_en_N_out ( SYNOPSYS_UNCONNECTED_3984 ) , .pReset_S_in ( SYNOPSYS_UNCONNECTED_3985 ) , .pReset_E_in ( SYNOPSYS_UNCONNECTED_3986 ) , .pReset_W_in ( pResetWires[185] ) , .pReset_N_out ( pResetWires[187] ) , .pReset_W_out ( SYNOPSYS_UNCONNECTED_3987 ) , - .pReset_E_out ( pResetWires[188] ) , .Reset_S_in ( p3173 ) , + .pReset_E_out ( pResetWires[188] ) , .Reset_S_in ( p2021 ) , .Reset_N_out ( SYNOPSYS_UNCONNECTED_3988 ) , .prog_clk_0_N_in ( prog_clk_0_wires[264] ) , .prog_clk_1_N_in ( prog_clk_2_wires[85] ) , .prog_clk_1_S_in ( SYNOPSYS_UNCONNECTED_3989 ) , .prog_clk_1_E_out ( prog_clk_1_wires[134] ) , - .prog_clk_1_W_out ( prog_clk_1_wires[135] ) , .prog_clk_2_N_in ( p3468 ) , - .prog_clk_2_E_in ( p948 ) , .prog_clk_2_S_in ( p1142 ) , - .prog_clk_2_W_in ( p170 ) , + .prog_clk_1_W_out ( prog_clk_1_wires[135] ) , .prog_clk_2_N_in ( p3603 ) , + .prog_clk_2_E_in ( p382 ) , .prog_clk_2_S_in ( p1038 ) , + .prog_clk_2_W_in ( p762 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_3990 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_3991 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_3992 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_3993 ) , - .prog_clk_3_W_in ( p2654 ) , .prog_clk_3_E_in ( p84 ) , - .prog_clk_3_S_in ( p621 ) , .prog_clk_3_N_in ( p3460 ) , + .prog_clk_3_W_in ( p3105 ) , .prog_clk_3_E_in ( p705 ) , + .prog_clk_3_S_in ( p226 ) , .prog_clk_3_N_in ( p3601 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_3994 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_3995 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_3996 ) , @@ -111524,12 +116046,12 @@ sb_1__1_ sb_7__3_ ( .clk_1_N_in ( clk_2_wires[85] ) , .clk_1_S_in ( SYNOPSYS_UNCONNECTED_3998 ) , .clk_1_E_out ( clk_1_wires[134] ) , .clk_1_W_out ( clk_1_wires[135] ) , - .clk_2_N_in ( p3495 ) , .clk_2_E_in ( p906 ) , .clk_2_S_in ( p3126 ) , - .clk_2_W_in ( p2546 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_3999 ) , + .clk_2_N_in ( p3154 ) , .clk_2_E_in ( p87 ) , .clk_2_S_in ( p275 ) , + .clk_2_W_in ( p3073 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_3999 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_4000 ) , .clk_2_N_out ( SYNOPSYS_UNCONNECTED_4001 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_4002 ) , .clk_3_W_in ( p2654 ) , - .clk_3_E_in ( p863 ) , .clk_3_S_in ( p388 ) , .clk_3_N_in ( p3492 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_4002 ) , .clk_3_W_in ( p3113 ) , + .clk_3_E_in ( p894 ) , .clk_3_S_in ( p1770 ) , .clk_3_N_in ( p3048 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_4003 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4004 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_4005 ) , @@ -111577,16 +116099,16 @@ sb_1__1_ sb_7__4_ ( .chanx_right_out ( sb_1__1__69_chanx_right_out ) , .chany_bottom_out ( sb_1__1__69_chany_bottom_out ) , .chanx_left_out ( sb_1__1__69_chanx_left_out ) , - .ccff_tail ( sb_1__1__69_ccff_tail ) , .Test_en_S_in ( p3322 ) , + .ccff_tail ( sb_1__1__69_ccff_tail ) , .Test_en_S_in ( p1651 ) , .Test_en_N_out ( SYNOPSYS_UNCONNECTED_4008 ) , .pReset_S_in ( SYNOPSYS_UNCONNECTED_4009 ) , .pReset_E_in ( SYNOPSYS_UNCONNECTED_4010 ) , .pReset_W_in ( pResetWires[234] ) , .pReset_N_out ( pResetWires[236] ) , .pReset_W_out ( SYNOPSYS_UNCONNECTED_4011 ) , - .pReset_E_out ( pResetWires[237] ) , .Reset_S_in ( p3325 ) , + .pReset_E_out ( pResetWires[237] ) , .Reset_S_in ( p1651 ) , .Reset_N_out ( SYNOPSYS_UNCONNECTED_4012 ) , - .prog_clk_0_N_in ( prog_clk_0_wires[267] ) , .prog_clk_1_N_in ( p2162 ) , - .prog_clk_1_S_in ( p650 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[267] ) , .prog_clk_1_N_in ( p1932 ) , + .prog_clk_1_S_in ( p956 ) , .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_4013 ) , .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_4014 ) , .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_4015 ) , @@ -111597,13 +116119,13 @@ sb_1__1_ sb_7__4_ ( .prog_clk_2_S_out ( prog_clk_2_wires[84] ) , .prog_clk_2_N_out ( prog_clk_2_wires[82] ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_4019 ) , - .prog_clk_3_W_in ( p1809 ) , .prog_clk_3_E_in ( p881 ) , - .prog_clk_3_S_in ( p46 ) , .prog_clk_3_N_in ( p1976 ) , + .prog_clk_3_W_in ( p2314 ) , .prog_clk_3_E_in ( p132 ) , + .prog_clk_3_S_in ( p3 ) , .prog_clk_3_N_in ( p2102 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_4020 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4021 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_4022 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_4023 ) , .clk_1_N_in ( p2162 ) , - .clk_1_S_in ( p163 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_4024 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_4023 ) , .clk_1_N_in ( p1932 ) , + .clk_1_S_in ( p252 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_4024 ) , .clk_1_W_out ( SYNOPSYS_UNCONNECTED_4025 ) , .clk_2_N_in ( SYNOPSYS_UNCONNECTED_4026 ) , .clk_2_E_in ( clk_2_wires[81] ) , @@ -111611,8 +116133,8 @@ sb_1__1_ sb_7__4_ ( .clk_2_W_in ( SYNOPSYS_UNCONNECTED_4028 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_4029 ) , .clk_2_S_out ( clk_2_wires[84] ) , .clk_2_N_out ( clk_2_wires[82] ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_4030 ) , .clk_3_W_in ( p1809 ) , - .clk_3_E_in ( p1702 ) , .clk_3_S_in ( p3292 ) , .clk_3_N_in ( p2021 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_4030 ) , .clk_3_W_in ( p2314 ) , + .clk_3_E_in ( p778 ) , .clk_3_S_in ( p797 ) , .clk_3_N_in ( p1773 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_4031 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4032 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_4033 ) , @@ -111660,40 +116182,40 @@ sb_1__1_ sb_7__5_ ( .chanx_right_out ( sb_1__1__70_chanx_right_out ) , .chany_bottom_out ( sb_1__1__70_chany_bottom_out ) , .chanx_left_out ( sb_1__1__70_chanx_left_out ) , - .ccff_tail ( sb_1__1__70_ccff_tail ) , .Test_en_S_in ( p2791 ) , + .ccff_tail ( sb_1__1__70_ccff_tail ) , .Test_en_S_in ( p2836 ) , .Test_en_N_out ( SYNOPSYS_UNCONNECTED_4036 ) , .pReset_S_in ( SYNOPSYS_UNCONNECTED_4037 ) , .pReset_E_in ( SYNOPSYS_UNCONNECTED_4038 ) , .pReset_W_in ( pResetWires[283] ) , .pReset_N_out ( pResetWires[285] ) , .pReset_W_out ( SYNOPSYS_UNCONNECTED_4039 ) , - .pReset_E_out ( pResetWires[286] ) , .Reset_S_in ( p2791 ) , + .pReset_E_out ( pResetWires[286] ) , .Reset_S_in ( p2836 ) , .Reset_N_out ( SYNOPSYS_UNCONNECTED_4040 ) , .prog_clk_0_N_in ( prog_clk_0_wires[270] ) , .prog_clk_1_N_in ( SYNOPSYS_UNCONNECTED_4041 ) , .prog_clk_1_S_in ( prog_clk_2_wires[83] ) , .prog_clk_1_E_out ( prog_clk_1_wires[141] ) , - .prog_clk_1_W_out ( prog_clk_1_wires[142] ) , .prog_clk_2_N_in ( p3434 ) , - .prog_clk_2_E_in ( p1260 ) , .prog_clk_2_S_in ( p583 ) , - .prog_clk_2_W_in ( p1070 ) , + .prog_clk_1_W_out ( prog_clk_1_wires[142] ) , .prog_clk_2_N_in ( p3604 ) , + .prog_clk_2_E_in ( p333 ) , .prog_clk_2_S_in ( p88 ) , + .prog_clk_2_W_in ( p19 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_4042 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_4043 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_4044 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_4045 ) , - .prog_clk_3_W_in ( p2617 ) , .prog_clk_3_E_in ( p797 ) , - .prog_clk_3_S_in ( p1186 ) , .prog_clk_3_N_in ( p3424 ) , + .prog_clk_3_W_in ( p2796 ) , .prog_clk_3_E_in ( p518 ) , + .prog_clk_3_S_in ( p944 ) , .prog_clk_3_N_in ( p3599 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_4046 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4047 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_4048 ) , .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_4049 ) , .clk_1_N_in ( SYNOPSYS_UNCONNECTED_4050 ) , .clk_1_S_in ( clk_2_wires[83] ) , .clk_1_E_out ( clk_1_wires[141] ) , - .clk_1_W_out ( clk_1_wires[142] ) , .clk_2_N_in ( p3204 ) , - .clk_2_E_in ( p18 ) , .clk_2_S_in ( p2736 ) , .clk_2_W_in ( p2544 ) , + .clk_1_W_out ( clk_1_wires[142] ) , .clk_2_N_in ( p3497 ) , + .clk_2_E_in ( p957 ) , .clk_2_S_in ( p1224 ) , .clk_2_W_in ( p3039 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_4051 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_4052 ) , .clk_2_N_out ( SYNOPSYS_UNCONNECTED_4053 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_4054 ) , .clk_3_W_in ( p2617 ) , - .clk_3_E_in ( p812 ) , .clk_3_S_in ( p11 ) , .clk_3_N_in ( p3153 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_4054 ) , .clk_3_W_in ( p3118 ) , + .clk_3_E_in ( p421 ) , .clk_3_S_in ( p2647 ) , .clk_3_N_in ( p3495 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_4055 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4056 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_4057 ) , @@ -111741,20 +116263,20 @@ sb_1__1_ sb_7__6_ ( .chanx_right_out ( sb_1__1__71_chanx_right_out ) , .chany_bottom_out ( sb_1__1__71_chany_bottom_out ) , .chanx_left_out ( sb_1__1__71_chanx_left_out ) , - .ccff_tail ( sb_1__1__71_ccff_tail ) , .Test_en_S_in ( p2947 ) , + .ccff_tail ( sb_1__1__71_ccff_tail ) , .Test_en_S_in ( p2212 ) , .Test_en_N_out ( SYNOPSYS_UNCONNECTED_4060 ) , .pReset_S_in ( SYNOPSYS_UNCONNECTED_4061 ) , .pReset_E_in ( SYNOPSYS_UNCONNECTED_4062 ) , .pReset_W_in ( pResetWires[332] ) , .pReset_N_out ( pResetWires[334] ) , .pReset_W_out ( SYNOPSYS_UNCONNECTED_4063 ) , - .pReset_E_out ( pResetWires[335] ) , .Reset_S_in ( p3323 ) , + .pReset_E_out ( pResetWires[335] ) , .Reset_S_in ( p2212 ) , .Reset_N_out ( SYNOPSYS_UNCONNECTED_4064 ) , - .prog_clk_0_N_in ( prog_clk_0_wires[273] ) , .prog_clk_1_N_in ( p1420 ) , - .prog_clk_1_S_in ( p516 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[273] ) , .prog_clk_1_N_in ( p1408 ) , + .prog_clk_1_S_in ( p42 ) , .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_4065 ) , .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_4066 ) , - .prog_clk_2_N_in ( p2497 ) , .prog_clk_2_E_in ( p845 ) , - .prog_clk_2_S_in ( p902 ) , .prog_clk_2_W_in ( p450 ) , + .prog_clk_2_N_in ( p1935 ) , .prog_clk_2_E_in ( p13 ) , + .prog_clk_2_S_in ( p744 ) , .prog_clk_2_W_in ( p860 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_4067 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_4068 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_4069 ) , @@ -111766,10 +116288,10 @@ sb_1__1_ sb_7__6_ ( .prog_clk_3_E_out ( prog_clk_3_wires[4] ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4074 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_4075 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_4076 ) , .clk_1_N_in ( p1420 ) , - .clk_1_S_in ( p915 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_4077 ) , - .clk_1_W_out ( SYNOPSYS_UNCONNECTED_4078 ) , .clk_2_N_in ( p2497 ) , - .clk_2_E_in ( p175 ) , .clk_2_S_in ( p3283 ) , .clk_2_W_in ( p137 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_4076 ) , .clk_1_N_in ( p1408 ) , + .clk_1_S_in ( p1266 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_4077 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_4078 ) , .clk_2_N_in ( p1449 ) , + .clk_2_E_in ( p630 ) , .clk_2_S_in ( p2097 ) , .clk_2_W_in ( p521 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_4079 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_4080 ) , .clk_2_N_out ( SYNOPSYS_UNCONNECTED_4081 ) , @@ -111825,27 +116347,27 @@ sb_1__1_ sb_7__7_ ( .chanx_right_out ( sb_1__1__72_chanx_right_out ) , .chany_bottom_out ( sb_1__1__72_chany_bottom_out ) , .chanx_left_out ( sb_1__1__72_chanx_left_out ) , - .ccff_tail ( sb_1__1__72_ccff_tail ) , .Test_en_S_in ( p3072 ) , + .ccff_tail ( sb_1__1__72_ccff_tail ) , .Test_en_S_in ( p1560 ) , .Test_en_N_out ( SYNOPSYS_UNCONNECTED_4090 ) , .pReset_S_in ( SYNOPSYS_UNCONNECTED_4091 ) , .pReset_E_in ( SYNOPSYS_UNCONNECTED_4092 ) , .pReset_W_in ( pResetWires[381] ) , .pReset_N_out ( pResetWires[383] ) , .pReset_W_out ( SYNOPSYS_UNCONNECTED_4093 ) , - .pReset_E_out ( pResetWires[384] ) , .Reset_S_in ( p3072 ) , + .pReset_E_out ( pResetWires[384] ) , .Reset_S_in ( p1560 ) , .Reset_N_out ( SYNOPSYS_UNCONNECTED_4094 ) , .prog_clk_0_N_in ( prog_clk_0_wires[276] ) , .prog_clk_1_N_in ( prog_clk_2_wires[98] ) , .prog_clk_1_S_in ( SYNOPSYS_UNCONNECTED_4095 ) , .prog_clk_1_E_out ( prog_clk_1_wires[148] ) , - .prog_clk_1_W_out ( prog_clk_1_wires[149] ) , .prog_clk_2_N_in ( p3433 ) , - .prog_clk_2_E_in ( p616 ) , .prog_clk_2_S_in ( p206 ) , - .prog_clk_2_W_in ( p1081 ) , + .prog_clk_1_W_out ( prog_clk_1_wires[149] ) , .prog_clk_2_N_in ( p3505 ) , + .prog_clk_2_E_in ( p584 ) , .prog_clk_2_S_in ( p1182 ) , + .prog_clk_2_W_in ( p804 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_4096 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_4097 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_4098 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_4099 ) , - .prog_clk_3_W_in ( p2387 ) , .prog_clk_3_E_in ( p1018 ) , - .prog_clk_3_S_in ( p985 ) , .prog_clk_3_N_in ( p3413 ) , + .prog_clk_3_W_in ( p2546 ) , .prog_clk_3_E_in ( p933 ) , + .prog_clk_3_S_in ( p386 ) , .prog_clk_3_N_in ( p3486 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_4100 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4101 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_4102 ) , @@ -111853,12 +116375,12 @@ sb_1__1_ sb_7__7_ ( .clk_1_N_in ( clk_2_wires[98] ) , .clk_1_S_in ( SYNOPSYS_UNCONNECTED_4104 ) , .clk_1_E_out ( clk_1_wires[148] ) , .clk_1_W_out ( clk_1_wires[149] ) , - .clk_2_N_in ( p3396 ) , .clk_2_E_in ( p580 ) , .clk_2_S_in ( p2999 ) , - .clk_2_W_in ( p2284 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_4105 ) , + .clk_2_N_in ( p3331 ) , .clk_2_E_in ( p126 ) , .clk_2_S_in ( p1248 ) , + .clk_2_W_in ( p3427 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_4105 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_4106 ) , .clk_2_N_out ( SYNOPSYS_UNCONNECTED_4107 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_4108 ) , .clk_3_W_in ( p2387 ) , - .clk_3_E_in ( p884 ) , .clk_3_S_in ( p1359 ) , .clk_3_N_in ( p3389 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_4108 ) , .clk_3_W_in ( p3463 ) , + .clk_3_E_in ( p1010 ) , .clk_3_S_in ( p790 ) , .clk_3_N_in ( p3294 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_4109 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4110 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_4111 ) , @@ -111906,16 +116428,16 @@ sb_1__1_ sb_7__8_ ( .chanx_right_out ( sb_1__1__73_chanx_right_out ) , .chany_bottom_out ( sb_1__1__73_chany_bottom_out ) , .chanx_left_out ( sb_1__1__73_chanx_left_out ) , - .ccff_tail ( sb_1__1__73_ccff_tail ) , .Test_en_S_in ( p2437 ) , + .ccff_tail ( sb_1__1__73_ccff_tail ) , .Test_en_S_in ( p1415 ) , .Test_en_N_out ( SYNOPSYS_UNCONNECTED_4114 ) , .pReset_S_in ( SYNOPSYS_UNCONNECTED_4115 ) , .pReset_E_in ( SYNOPSYS_UNCONNECTED_4116 ) , .pReset_W_in ( pResetWires[430] ) , .pReset_N_out ( pResetWires[432] ) , .pReset_W_out ( SYNOPSYS_UNCONNECTED_4117 ) , - .pReset_E_out ( pResetWires[433] ) , .Reset_S_in ( p2437 ) , + .pReset_E_out ( pResetWires[433] ) , .Reset_S_in ( p1415 ) , .Reset_N_out ( SYNOPSYS_UNCONNECTED_4118 ) , - .prog_clk_0_N_in ( prog_clk_0_wires[279] ) , .prog_clk_1_N_in ( p1853 ) , - .prog_clk_1_S_in ( p703 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[279] ) , .prog_clk_1_N_in ( p1307 ) , + .prog_clk_1_S_in ( p427 ) , .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_4119 ) , .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_4120 ) , .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_4121 ) , @@ -111926,13 +116448,13 @@ sb_1__1_ sb_7__8_ ( .prog_clk_2_S_out ( prog_clk_2_wires[97] ) , .prog_clk_2_N_out ( prog_clk_2_wires[95] ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_4125 ) , - .prog_clk_3_W_in ( p2263 ) , .prog_clk_3_E_in ( p959 ) , - .prog_clk_3_S_in ( p581 ) , .prog_clk_3_N_in ( p85 ) , + .prog_clk_3_W_in ( p1272 ) , .prog_clk_3_E_in ( p296 ) , + .prog_clk_3_S_in ( p151 ) , .prog_clk_3_N_in ( p449 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_4126 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4127 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_4128 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_4129 ) , .clk_1_N_in ( p1853 ) , - .clk_1_S_in ( p286 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_4130 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_4129 ) , .clk_1_N_in ( p1307 ) , + .clk_1_S_in ( p1093 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_4130 ) , .clk_1_W_out ( SYNOPSYS_UNCONNECTED_4131 ) , .clk_2_N_in ( SYNOPSYS_UNCONNECTED_4132 ) , .clk_2_E_in ( clk_2_wires[94] ) , @@ -111940,8 +116462,8 @@ sb_1__1_ sb_7__8_ ( .clk_2_W_in ( SYNOPSYS_UNCONNECTED_4134 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_4135 ) , .clk_2_S_out ( clk_2_wires[97] ) , .clk_2_N_out ( clk_2_wires[95] ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_4136 ) , .clk_3_W_in ( p2263 ) , - .clk_3_E_in ( p161 ) , .clk_3_S_in ( p2269 ) , .clk_3_N_in ( p1640 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_4136 ) , .clk_3_W_in ( p1272 ) , + .clk_3_E_in ( p703 ) , .clk_3_S_in ( p582 ) , .clk_3_N_in ( p47 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_4137 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4138 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_4139 ) , @@ -111989,40 +116511,40 @@ sb_1__1_ sb_7__9_ ( .chanx_right_out ( sb_1__1__74_chanx_right_out ) , .chany_bottom_out ( sb_1__1__74_chany_bottom_out ) , .chanx_left_out ( sb_1__1__74_chanx_left_out ) , - .ccff_tail ( sb_1__1__74_ccff_tail ) , .Test_en_S_in ( p3186 ) , + .ccff_tail ( sb_1__1__74_ccff_tail ) , .Test_en_S_in ( p1925 ) , .Test_en_N_out ( SYNOPSYS_UNCONNECTED_4142 ) , .pReset_S_in ( SYNOPSYS_UNCONNECTED_4143 ) , .pReset_E_in ( SYNOPSYS_UNCONNECTED_4144 ) , .pReset_W_in ( pResetWires[479] ) , .pReset_N_out ( pResetWires[481] ) , .pReset_W_out ( SYNOPSYS_UNCONNECTED_4145 ) , - .pReset_E_out ( pResetWires[482] ) , .Reset_S_in ( p3186 ) , + .pReset_E_out ( pResetWires[482] ) , .Reset_S_in ( p1925 ) , .Reset_N_out ( SYNOPSYS_UNCONNECTED_4146 ) , .prog_clk_0_N_in ( prog_clk_0_wires[282] ) , .prog_clk_1_N_in ( SYNOPSYS_UNCONNECTED_4147 ) , .prog_clk_1_S_in ( prog_clk_2_wires[96] ) , .prog_clk_1_E_out ( prog_clk_1_wires[155] ) , - .prog_clk_1_W_out ( prog_clk_1_wires[156] ) , .prog_clk_2_N_in ( p3095 ) , - .prog_clk_2_E_in ( p1188 ) , .prog_clk_2_S_in ( p1008 ) , - .prog_clk_2_W_in ( p1119 ) , + .prog_clk_1_W_out ( prog_clk_1_wires[156] ) , .prog_clk_2_N_in ( p1540 ) , + .prog_clk_2_E_in ( p609 ) , .prog_clk_2_S_in ( p826 ) , + .prog_clk_2_W_in ( p952 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_4148 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_4149 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_4150 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_4151 ) , - .prog_clk_3_W_in ( p2854 ) , .prog_clk_3_E_in ( p407 ) , - .prog_clk_3_S_in ( p471 ) , .prog_clk_3_N_in ( p3041 ) , + .prog_clk_3_W_in ( p2631 ) , .prog_clk_3_E_in ( p683 ) , + .prog_clk_3_S_in ( p983 ) , .prog_clk_3_N_in ( p583 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_4152 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4153 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_4154 ) , .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_4155 ) , .clk_1_N_in ( SYNOPSYS_UNCONNECTED_4156 ) , .clk_1_S_in ( clk_2_wires[96] ) , .clk_1_E_out ( clk_1_wires[155] ) , - .clk_1_W_out ( clk_1_wires[156] ) , .clk_2_N_in ( p3057 ) , - .clk_2_E_in ( p917 ) , .clk_2_S_in ( p3114 ) , .clk_2_W_in ( p2723 ) , + .clk_1_W_out ( clk_1_wires[156] ) , .clk_2_N_in ( p3572 ) , + .clk_2_E_in ( p1366 ) , .clk_2_S_in ( p1172 ) , .clk_2_W_in ( p3086 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_4157 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_4158 ) , .clk_2_N_out ( SYNOPSYS_UNCONNECTED_4159 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_4160 ) , .clk_3_W_in ( p2854 ) , - .clk_3_E_in ( p48 ) , .clk_3_S_in ( p240 ) , .clk_3_N_in ( p3015 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_4160 ) , .clk_3_W_in ( p3159 ) , + .clk_3_E_in ( p303 ) , .clk_3_S_in ( p1670 ) , .clk_3_N_in ( p3563 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_4161 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4162 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_4163 ) , @@ -112070,16 +116592,16 @@ sb_1__1_ sb_7__10_ ( .chanx_right_out ( sb_1__1__75_chanx_right_out ) , .chany_bottom_out ( sb_1__1__75_chany_bottom_out ) , .chanx_left_out ( sb_1__1__75_chanx_left_out ) , - .ccff_tail ( sb_1__1__75_ccff_tail ) , .Test_en_S_in ( p3050 ) , + .ccff_tail ( sb_1__1__75_ccff_tail ) , .Test_en_S_in ( p1552 ) , .Test_en_N_out ( SYNOPSYS_UNCONNECTED_4166 ) , .pReset_S_in ( SYNOPSYS_UNCONNECTED_4167 ) , .pReset_E_in ( SYNOPSYS_UNCONNECTED_4168 ) , .pReset_W_in ( pResetWires[528] ) , .pReset_N_out ( pResetWires[530] ) , .pReset_W_out ( SYNOPSYS_UNCONNECTED_4169 ) , - .pReset_E_out ( pResetWires[531] ) , .Reset_S_in ( p3068 ) , + .pReset_E_out ( pResetWires[531] ) , .Reset_S_in ( p1552 ) , .Reset_N_out ( SYNOPSYS_UNCONNECTED_4170 ) , - .prog_clk_0_N_in ( prog_clk_0_wires[285] ) , .prog_clk_1_N_in ( p1350 ) , - .prog_clk_1_S_in ( p923 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[285] ) , .prog_clk_1_N_in ( p1515 ) , + .prog_clk_1_S_in ( p388 ) , .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_4171 ) , .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_4172 ) , .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_4173 ) , @@ -112090,13 +116612,13 @@ sb_1__1_ sb_7__10_ ( .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_4177 ) , .prog_clk_2_N_out ( prog_clk_2_wires[108] ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_4178 ) , - .prog_clk_3_W_in ( p1253 ) , .prog_clk_3_E_in ( p784 ) , - .prog_clk_3_S_in ( p510 ) , .prog_clk_3_N_in ( p1622 ) , + .prog_clk_3_W_in ( p1645 ) , .prog_clk_3_E_in ( p170 ) , + .prog_clk_3_S_in ( p881 ) , .prog_clk_3_N_in ( p764 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_4179 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4180 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_4181 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_4182 ) , .clk_1_N_in ( p1350 ) , - .clk_1_S_in ( p37 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_4183 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_4182 ) , .clk_1_N_in ( p1515 ) , + .clk_1_S_in ( p1078 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_4183 ) , .clk_1_W_out ( SYNOPSYS_UNCONNECTED_4184 ) , .clk_2_N_in ( SYNOPSYS_UNCONNECTED_4185 ) , .clk_2_E_in ( clk_2_wires[107] ) , @@ -112105,8 +116627,8 @@ sb_1__1_ sb_7__10_ ( .clk_2_W_out ( SYNOPSYS_UNCONNECTED_4188 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_4189 ) , .clk_2_N_out ( clk_2_wires[108] ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_4190 ) , .clk_3_W_in ( p1253 ) , - .clk_3_E_in ( p1698 ) , .clk_3_S_in ( p3024 ) , .clk_3_N_in ( p197 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_4190 ) , .clk_3_W_in ( p1423 ) , + .clk_3_E_in ( p792 ) , .clk_3_S_in ( p717 ) , .clk_3_N_in ( p203 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_4191 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4192 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_4193 ) , @@ -112154,40 +116676,40 @@ sb_1__1_ sb_7__11_ ( .chanx_right_out ( sb_1__1__76_chanx_right_out ) , .chany_bottom_out ( sb_1__1__76_chany_bottom_out ) , .chanx_left_out ( sb_1__1__76_chanx_left_out ) , - .ccff_tail ( sb_1__1__76_ccff_tail ) , .Test_en_S_in ( p2633 ) , + .ccff_tail ( sb_1__1__76_ccff_tail ) , .Test_en_S_in ( p1549 ) , .Test_en_N_out ( SYNOPSYS_UNCONNECTED_4196 ) , .pReset_S_in ( SYNOPSYS_UNCONNECTED_4197 ) , .pReset_E_in ( SYNOPSYS_UNCONNECTED_4198 ) , .pReset_W_in ( pResetWires[577] ) , .pReset_N_out ( pResetWires[579] ) , .pReset_W_out ( SYNOPSYS_UNCONNECTED_4199 ) , - .pReset_E_out ( pResetWires[580] ) , .Reset_S_in ( p2633 ) , + .pReset_E_out ( pResetWires[580] ) , .Reset_S_in ( p1549 ) , .Reset_N_out ( SYNOPSYS_UNCONNECTED_4200 ) , .prog_clk_0_N_in ( prog_clk_0_wires[288] ) , .prog_clk_1_N_in ( SYNOPSYS_UNCONNECTED_4201 ) , .prog_clk_1_S_in ( prog_clk_2_wires[109] ) , .prog_clk_1_E_out ( prog_clk_1_wires[162] ) , - .prog_clk_1_W_out ( prog_clk_1_wires[163] ) , .prog_clk_2_N_in ( p3507 ) , - .prog_clk_2_E_in ( p38 ) , .prog_clk_2_S_in ( p1060 ) , - .prog_clk_2_W_in ( p555 ) , + .prog_clk_1_W_out ( prog_clk_1_wires[163] ) , .prog_clk_2_N_in ( p3534 ) , + .prog_clk_2_E_in ( p276 ) , .prog_clk_2_S_in ( p430 ) , + .prog_clk_2_W_in ( p687 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_4202 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_4203 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_4204 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_4205 ) , - .prog_clk_3_W_in ( p2522 ) , .prog_clk_3_E_in ( p715 ) , - .prog_clk_3_S_in ( p631 ) , .prog_clk_3_N_in ( p3506 ) , + .prog_clk_3_W_in ( p3240 ) , .prog_clk_3_E_in ( p810 ) , + .prog_clk_3_S_in ( p1009 ) , .prog_clk_3_N_in ( p3524 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_4206 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4207 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_4208 ) , .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_4209 ) , .clk_1_N_in ( SYNOPSYS_UNCONNECTED_4210 ) , .clk_1_S_in ( clk_2_wires[109] ) , .clk_1_E_out ( clk_1_wires[162] ) , - .clk_1_W_out ( clk_1_wires[163] ) , .clk_2_N_in ( p2937 ) , - .clk_2_E_in ( p1042 ) , .clk_2_S_in ( p2561 ) , .clk_2_W_in ( p2309 ) , + .clk_1_W_out ( clk_1_wires[163] ) , .clk_2_N_in ( p3461 ) , + .clk_2_E_in ( p1175 ) , .clk_2_S_in ( p441 ) , .clk_2_W_in ( p3282 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_4211 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_4212 ) , .clk_2_N_out ( SYNOPSYS_UNCONNECTED_4213 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_4214 ) , .clk_3_W_in ( p2522 ) , - .clk_3_E_in ( p966 ) , .clk_3_S_in ( p277 ) , .clk_3_N_in ( p2916 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_4214 ) , .clk_3_W_in ( p3360 ) , + .clk_3_E_in ( p476 ) , .clk_3_S_in ( p1194 ) , .clk_3_N_in ( p3440 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_4215 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4216 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_4217 ) , @@ -112235,38 +116757,38 @@ sb_1__1_ sb_8__1_ ( .chanx_right_out ( sb_1__1__77_chanx_right_out ) , .chany_bottom_out ( sb_1__1__77_chany_bottom_out ) , .chanx_left_out ( sb_1__1__77_chanx_left_out ) , - .ccff_tail ( sb_1__1__77_ccff_tail ) , .Test_en_S_in ( p3200 ) , + .ccff_tail ( sb_1__1__77_ccff_tail ) , .Test_en_S_in ( p1426 ) , .Test_en_N_out ( SYNOPSYS_UNCONNECTED_4220 ) , .pReset_S_in ( SYNOPSYS_UNCONNECTED_4221 ) , .pReset_E_in ( SYNOPSYS_UNCONNECTED_4222 ) , .pReset_W_in ( pResetWires[91] ) , .pReset_N_out ( pResetWires[93] ) , .pReset_W_out ( SYNOPSYS_UNCONNECTED_4223 ) , - .pReset_E_out ( pResetWires[94] ) , .Reset_S_in ( p3457 ) , + .pReset_E_out ( pResetWires[94] ) , .Reset_S_in ( p1426 ) , .Reset_N_out ( SYNOPSYS_UNCONNECTED_4224 ) , - .prog_clk_0_N_in ( prog_clk_0_wires[296] ) , .prog_clk_1_N_in ( p1389 ) , - .prog_clk_1_S_in ( p856 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[296] ) , .prog_clk_1_N_in ( p1581 ) , + .prog_clk_1_S_in ( p973 ) , .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_4225 ) , .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_4226 ) , - .prog_clk_2_N_in ( p3375 ) , .prog_clk_2_E_in ( p957 ) , - .prog_clk_2_S_in ( p121 ) , .prog_clk_2_W_in ( p373 ) , + .prog_clk_2_N_in ( p3542 ) , .prog_clk_2_E_in ( p374 ) , + .prog_clk_2_S_in ( p510 ) , .prog_clk_2_W_in ( p838 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_4227 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_4228 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_4229 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_4230 ) , - .prog_clk_3_W_in ( p1760 ) , .prog_clk_3_E_in ( p1016 ) , - .prog_clk_3_S_in ( p989 ) , .prog_clk_3_N_in ( p3336 ) , + .prog_clk_3_W_in ( p3128 ) , .prog_clk_3_E_in ( p823 ) , + .prog_clk_3_S_in ( p1098 ) , .prog_clk_3_N_in ( p3515 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_4231 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4232 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_4233 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_4234 ) , .clk_1_N_in ( p1389 ) , - .clk_1_S_in ( p332 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_4235 ) , - .clk_1_W_out ( SYNOPSYS_UNCONNECTED_4236 ) , .clk_2_N_in ( p3397 ) , - .clk_2_E_in ( p0 ) , .clk_2_S_in ( p3441 ) , .clk_2_W_in ( p1731 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_4234 ) , .clk_1_N_in ( p1581 ) , + .clk_1_S_in ( p330 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_4235 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_4236 ) , .clk_2_N_in ( p3261 ) , + .clk_2_E_in ( p0 ) , .clk_2_S_in ( p74 ) , .clk_2_W_in ( p3299 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_4237 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_4238 ) , .clk_2_N_out ( SYNOPSYS_UNCONNECTED_4239 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_4240 ) , .clk_3_W_in ( p1760 ) , - .clk_3_E_in ( p566 ) , .clk_3_S_in ( p847 ) , .clk_3_N_in ( p3388 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_4240 ) , .clk_3_W_in ( p3333 ) , + .clk_3_E_in ( p1057 ) , .clk_3_S_in ( p1341 ) , .clk_3_N_in ( p3181 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_4241 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4242 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_4243 ) , @@ -112314,16 +116836,16 @@ sb_1__1_ sb_8__2_ ( .chanx_right_out ( sb_1__1__78_chanx_right_out ) , .chany_bottom_out ( sb_1__1__78_chany_bottom_out ) , .chanx_left_out ( sb_1__1__78_chanx_left_out ) , - .ccff_tail ( sb_1__1__78_ccff_tail ) , .Test_en_S_in ( p1947 ) , + .ccff_tail ( sb_1__1__78_ccff_tail ) , .Test_en_S_in ( p2549 ) , .Test_en_N_out ( SYNOPSYS_UNCONNECTED_4246 ) , .pReset_S_in ( SYNOPSYS_UNCONNECTED_4247 ) , .pReset_E_in ( SYNOPSYS_UNCONNECTED_4248 ) , .pReset_W_in ( pResetWires[140] ) , .pReset_N_out ( pResetWires[142] ) , .pReset_W_out ( SYNOPSYS_UNCONNECTED_4249 ) , - .pReset_E_out ( pResetWires[143] ) , .Reset_S_in ( p1947 ) , + .pReset_E_out ( pResetWires[143] ) , .Reset_S_in ( p2549 ) , .Reset_N_out ( SYNOPSYS_UNCONNECTED_4250 ) , - .prog_clk_0_N_in ( prog_clk_0_wires[299] ) , .prog_clk_1_N_in ( p1620 ) , - .prog_clk_1_S_in ( p891 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[299] ) , .prog_clk_1_N_in ( p2321 ) , + .prog_clk_1_S_in ( p436 ) , .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_4251 ) , .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_4252 ) , .prog_clk_2_N_in ( prog_clk_3_wires[43] ) , @@ -112333,14 +116855,14 @@ sb_1__1_ sb_8__2_ ( .prog_clk_2_W_out ( prog_clk_2_wires[71] ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_4256 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_4257 ) , - .prog_clk_2_E_out ( prog_clk_2_wires[69] ) , .prog_clk_3_W_in ( p2152 ) , - .prog_clk_3_E_in ( p798 ) , .prog_clk_3_S_in ( p740 ) , - .prog_clk_3_N_in ( p699 ) , + .prog_clk_2_E_out ( prog_clk_2_wires[69] ) , .prog_clk_3_W_in ( p2047 ) , + .prog_clk_3_E_in ( p871 ) , .prog_clk_3_S_in ( p125 ) , + .prog_clk_3_N_in ( p788 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_4258 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4259 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_4260 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_4261 ) , .clk_1_N_in ( p1620 ) , - .clk_1_S_in ( p301 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_4262 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_4261 ) , .clk_1_N_in ( p2321 ) , + .clk_1_S_in ( p1106 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_4262 ) , .clk_1_W_out ( SYNOPSYS_UNCONNECTED_4263 ) , .clk_2_N_in ( clk_3_wires[43] ) , .clk_2_E_in ( SYNOPSYS_UNCONNECTED_4264 ) , @@ -112349,8 +116871,8 @@ sb_1__1_ sb_8__2_ ( .clk_2_W_out ( clk_2_wires[71] ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_4267 ) , .clk_2_N_out ( SYNOPSYS_UNCONNECTED_4268 ) , - .clk_2_E_out ( clk_2_wires[69] ) , .clk_3_W_in ( p2152 ) , - .clk_3_E_in ( p1634 ) , .clk_3_S_in ( p1720 ) , .clk_3_N_in ( p460 ) , + .clk_2_E_out ( clk_2_wires[69] ) , .clk_3_W_in ( p2047 ) , + .clk_3_E_in ( p341 ) , .clk_3_S_in ( p2377 ) , .clk_3_N_in ( p2122 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_4269 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4270 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_4271 ) , @@ -112398,20 +116920,20 @@ sb_1__1_ sb_8__3_ ( .chanx_right_out ( sb_1__1__79_chanx_right_out ) , .chany_bottom_out ( sb_1__1__79_chany_bottom_out ) , .chanx_left_out ( sb_1__1__79_chanx_left_out ) , - .ccff_tail ( sb_1__1__79_ccff_tail ) , .Test_en_S_in ( p2643 ) , + .ccff_tail ( sb_1__1__79_ccff_tail ) , .Test_en_S_in ( p2262 ) , .Test_en_N_out ( SYNOPSYS_UNCONNECTED_4274 ) , .pReset_S_in ( SYNOPSYS_UNCONNECTED_4275 ) , .pReset_E_in ( SYNOPSYS_UNCONNECTED_4276 ) , .pReset_W_in ( pResetWires[189] ) , .pReset_N_out ( pResetWires[191] ) , .pReset_W_out ( SYNOPSYS_UNCONNECTED_4277 ) , - .pReset_E_out ( pResetWires[192] ) , .Reset_S_in ( p2643 ) , + .pReset_E_out ( pResetWires[192] ) , .Reset_S_in ( p2262 ) , .Reset_N_out ( SYNOPSYS_UNCONNECTED_4278 ) , - .prog_clk_0_N_in ( prog_clk_0_wires[302] ) , .prog_clk_1_N_in ( p1509 ) , - .prog_clk_1_S_in ( p664 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[302] ) , .prog_clk_1_N_in ( p1601 ) , + .prog_clk_1_S_in ( p568 ) , .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_4279 ) , .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_4280 ) , - .prog_clk_2_N_in ( p2267 ) , .prog_clk_2_E_in ( p639 ) , - .prog_clk_2_S_in ( p1967 ) , .prog_clk_2_W_in ( p323 ) , + .prog_clk_2_N_in ( p2325 ) , .prog_clk_2_E_in ( p459 ) , + .prog_clk_2_S_in ( p1782 ) , .prog_clk_2_W_in ( p506 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_4281 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_4282 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_4283 ) , @@ -112423,10 +116945,10 @@ sb_1__1_ sb_8__3_ ( .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_4288 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4289 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_4290 ) , - .prog_clk_3_S_out ( prog_clk_3_wires[42] ) , .clk_1_N_in ( p1509 ) , - .clk_1_S_in ( p128 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_4291 ) , - .clk_1_W_out ( SYNOPSYS_UNCONNECTED_4292 ) , .clk_2_N_in ( p2267 ) , - .clk_2_E_in ( p265 ) , .clk_2_S_in ( p2564 ) , .clk_2_W_in ( p1185 ) , + .prog_clk_3_S_out ( prog_clk_3_wires[42] ) , .clk_1_N_in ( p1601 ) , + .clk_1_S_in ( p831 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_4291 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_4292 ) , .clk_2_N_in ( p1497 ) , + .clk_2_E_in ( p699 ) , .clk_2_S_in ( p2067 ) , .clk_2_W_in ( p885 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_4293 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_4294 ) , .clk_2_N_out ( SYNOPSYS_UNCONNECTED_4295 ) , @@ -112482,16 +117004,16 @@ sb_1__1_ sb_8__4_ ( .chanx_right_out ( sb_1__1__80_chanx_right_out ) , .chany_bottom_out ( sb_1__1__80_chany_bottom_out ) , .chanx_left_out ( sb_1__1__80_chanx_left_out ) , - .ccff_tail ( sb_1__1__80_ccff_tail ) , .Test_en_S_in ( p1822 ) , + .ccff_tail ( sb_1__1__80_ccff_tail ) , .Test_en_S_in ( p1902 ) , .Test_en_N_out ( SYNOPSYS_UNCONNECTED_4304 ) , .pReset_S_in ( SYNOPSYS_UNCONNECTED_4305 ) , .pReset_E_in ( SYNOPSYS_UNCONNECTED_4306 ) , .pReset_W_in ( pResetWires[238] ) , .pReset_N_out ( pResetWires[240] ) , .pReset_W_out ( SYNOPSYS_UNCONNECTED_4307 ) , - .pReset_E_out ( pResetWires[241] ) , .Reset_S_in ( p1822 ) , + .pReset_E_out ( pResetWires[241] ) , .Reset_S_in ( p1902 ) , .Reset_N_out ( SYNOPSYS_UNCONNECTED_4308 ) , - .prog_clk_0_N_in ( prog_clk_0_wires[305] ) , .prog_clk_1_N_in ( p1174 ) , - .prog_clk_1_S_in ( p509 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[305] ) , .prog_clk_1_N_in ( p1856 ) , + .prog_clk_1_S_in ( p1715 ) , .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_4309 ) , .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_4310 ) , .prog_clk_2_N_in ( prog_clk_3_wires[33] ) , @@ -112509,8 +117031,8 @@ sb_1__1_ sb_8__4_ ( .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_4319 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4320 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_4321 ) , - .prog_clk_3_S_out ( prog_clk_3_wires[38] ) , .clk_1_N_in ( p1174 ) , - .clk_1_S_in ( p1649 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_4322 ) , + .prog_clk_3_S_out ( prog_clk_3_wires[38] ) , .clk_1_N_in ( p1856 ) , + .clk_1_S_in ( p208 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_4322 ) , .clk_1_W_out ( SYNOPSYS_UNCONNECTED_4323 ) , .clk_2_N_in ( clk_3_wires[33] ) , .clk_2_E_in ( SYNOPSYS_UNCONNECTED_4324 ) , @@ -112571,20 +117093,20 @@ sb_1__1_ sb_8__5_ ( .chanx_right_out ( sb_1__1__81_chanx_right_out ) , .chany_bottom_out ( sb_1__1__81_chany_bottom_out ) , .chanx_left_out ( sb_1__1__81_chanx_left_out ) , - .ccff_tail ( sb_1__1__81_ccff_tail ) , .Test_en_S_in ( p2962 ) , + .ccff_tail ( sb_1__1__81_ccff_tail ) , .Test_en_S_in ( p2512 ) , .Test_en_N_out ( SYNOPSYS_UNCONNECTED_4336 ) , .pReset_S_in ( SYNOPSYS_UNCONNECTED_4337 ) , .pReset_E_in ( SYNOPSYS_UNCONNECTED_4338 ) , .pReset_W_in ( pResetWires[287] ) , .pReset_N_out ( pResetWires[289] ) , .pReset_W_out ( SYNOPSYS_UNCONNECTED_4339 ) , - .pReset_E_out ( pResetWires[290] ) , .Reset_S_in ( p3252 ) , + .pReset_E_out ( pResetWires[290] ) , .Reset_S_in ( p2512 ) , .Reset_N_out ( SYNOPSYS_UNCONNECTED_4340 ) , - .prog_clk_0_N_in ( prog_clk_0_wires[308] ) , .prog_clk_1_N_in ( p1748 ) , - .prog_clk_1_S_in ( p233 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[308] ) , .prog_clk_1_N_in ( p1617 ) , + .prog_clk_1_S_in ( p137 ) , .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_4341 ) , .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_4342 ) , - .prog_clk_2_N_in ( p1833 ) , .prog_clk_2_E_in ( p811 ) , - .prog_clk_2_S_in ( p1625 ) , .prog_clk_2_W_in ( p1164 ) , + .prog_clk_2_N_in ( p2484 ) , .prog_clk_2_E_in ( p486 ) , + .prog_clk_2_S_in ( p2055 ) , .prog_clk_2_W_in ( p827 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_4343 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_4344 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_4345 ) , @@ -112596,10 +117118,10 @@ sb_1__1_ sb_8__5_ ( .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_4350 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4351 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_4352 ) , - .prog_clk_3_S_out ( prog_clk_3_wires[32] ) , .clk_1_N_in ( p1748 ) , - .clk_1_S_in ( p910 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_4353 ) , - .clk_1_W_out ( SYNOPSYS_UNCONNECTED_4354 ) , .clk_2_N_in ( p1924 ) , - .clk_2_E_in ( p47 ) , .clk_2_S_in ( p3211 ) , .clk_2_W_in ( p389 ) , + .prog_clk_3_S_out ( prog_clk_3_wires[32] ) , .clk_1_N_in ( p1617 ) , + .clk_1_S_in ( p905 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_4353 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_4354 ) , .clk_2_N_in ( p1976 ) , + .clk_2_E_in ( p491 ) , .clk_2_S_in ( p2384 ) , .clk_2_W_in ( p304 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_4355 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_4356 ) , .clk_2_N_out ( SYNOPSYS_UNCONNECTED_4357 ) , @@ -112655,20 +117177,20 @@ sb_1__1_ sb_8__6_ ( .chanx_right_out ( sb_1__1__82_chanx_right_out ) , .chany_bottom_out ( sb_1__1__82_chany_bottom_out ) , .chanx_left_out ( sb_1__1__82_chanx_left_out ) , - .ccff_tail ( sb_1__1__82_ccff_tail ) , .Test_en_S_in ( p2206 ) , + .ccff_tail ( sb_1__1__82_ccff_tail ) , .Test_en_S_in ( p2516 ) , .Test_en_N_out ( SYNOPSYS_UNCONNECTED_4366 ) , .pReset_S_in ( SYNOPSYS_UNCONNECTED_4367 ) , .pReset_E_in ( SYNOPSYS_UNCONNECTED_4368 ) , .pReset_W_in ( pResetWires[336] ) , .pReset_N_out ( pResetWires[338] ) , .pReset_W_out ( SYNOPSYS_UNCONNECTED_4369 ) , - .pReset_E_out ( pResetWires[339] ) , .Reset_S_in ( p3107 ) , + .pReset_E_out ( pResetWires[339] ) , .Reset_S_in ( p2516 ) , .Reset_N_out ( SYNOPSYS_UNCONNECTED_4370 ) , - .prog_clk_0_N_in ( prog_clk_0_wires[311] ) , .prog_clk_1_N_in ( p1861 ) , - .prog_clk_1_S_in ( p144 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[311] ) , .prog_clk_1_N_in ( p1328 ) , + .prog_clk_1_S_in ( p43 ) , .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_4371 ) , .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_4372 ) , - .prog_clk_2_N_in ( p2957 ) , .prog_clk_2_E_in ( p294 ) , - .prog_clk_2_S_in ( p1661 ) , .prog_clk_2_W_in ( p386 ) , + .prog_clk_2_N_in ( p2046 ) , .prog_clk_2_E_in ( p512 ) , + .prog_clk_2_S_in ( p385 ) , .prog_clk_2_W_in ( p511 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_4373 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_4374 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_4375 ) , @@ -112680,10 +117202,10 @@ sb_1__1_ sb_8__6_ ( .prog_clk_3_E_out ( prog_clk_3_wires[44] ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4380 ) , .prog_clk_3_N_out ( prog_clk_3_wires[26] ) , - .prog_clk_3_S_out ( prog_clk_3_wires[28] ) , .clk_1_N_in ( p1861 ) , - .clk_1_S_in ( p839 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_4381 ) , - .clk_1_W_out ( SYNOPSYS_UNCONNECTED_4382 ) , .clk_2_N_in ( p2926 ) , - .clk_2_E_in ( p822 ) , .clk_2_S_in ( p3001 ) , .clk_2_W_in ( p1247 ) , + .prog_clk_3_S_out ( prog_clk_3_wires[28] ) , .clk_1_N_in ( p1328 ) , + .clk_1_S_in ( p1002 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_4381 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_4382 ) , .clk_2_N_in ( p2046 ) , + .clk_2_E_in ( p801 ) , .clk_2_S_in ( p2390 ) , .clk_2_W_in ( p370 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_4383 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_4384 ) , .clk_2_N_out ( SYNOPSYS_UNCONNECTED_4385 ) , @@ -112738,20 +117260,20 @@ sb_1__1_ sb_8__7_ ( .chanx_right_out ( sb_1__1__83_chanx_right_out ) , .chany_bottom_out ( sb_1__1__83_chany_bottom_out ) , .chanx_left_out ( sb_1__1__83_chanx_left_out ) , - .ccff_tail ( sb_1__1__83_ccff_tail ) , .Test_en_S_in ( p2136 ) , + .ccff_tail ( sb_1__1__83_ccff_tail ) , .Test_en_S_in ( p2523 ) , .Test_en_N_out ( SYNOPSYS_UNCONNECTED_4392 ) , .pReset_S_in ( SYNOPSYS_UNCONNECTED_4393 ) , .pReset_E_in ( SYNOPSYS_UNCONNECTED_4394 ) , .pReset_W_in ( pResetWires[385] ) , .pReset_N_out ( pResetWires[387] ) , .pReset_W_out ( SYNOPSYS_UNCONNECTED_4395 ) , - .pReset_E_out ( pResetWires[388] ) , .Reset_S_in ( p3271 ) , + .pReset_E_out ( pResetWires[388] ) , .Reset_S_in ( p2523 ) , .Reset_N_out ( SYNOPSYS_UNCONNECTED_4396 ) , - .prog_clk_0_N_in ( prog_clk_0_wires[314] ) , .prog_clk_1_N_in ( p1827 ) , - .prog_clk_1_S_in ( p868 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[314] ) , .prog_clk_1_N_in ( p1445 ) , + .prog_clk_1_S_in ( p1225 ) , .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_4397 ) , .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_4398 ) , - .prog_clk_2_N_in ( p2463 ) , .prog_clk_2_E_in ( p152 ) , - .prog_clk_2_S_in ( p1645 ) , .prog_clk_2_W_in ( p177 ) , + .prog_clk_2_N_in ( p2501 ) , .prog_clk_2_E_in ( p433 ) , + .prog_clk_2_S_in ( p387 ) , .prog_clk_2_W_in ( p171 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_4399 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_4400 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_4401 ) , @@ -112763,10 +117285,10 @@ sb_1__1_ sb_8__7_ ( .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_4406 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4407 ) , .prog_clk_3_N_out ( prog_clk_3_wires[30] ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_4408 ) , .clk_1_N_in ( p1827 ) , - .clk_1_S_in ( p507 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_4409 ) , - .clk_1_W_out ( SYNOPSYS_UNCONNECTED_4410 ) , .clk_2_N_in ( p2463 ) , - .clk_2_E_in ( p942 ) , .clk_2_S_in ( p3226 ) , .clk_2_W_in ( p528 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_4408 ) , .clk_1_N_in ( p1445 ) , + .clk_1_S_in ( p157 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_4409 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_4410 ) , .clk_2_N_in ( p2594 ) , + .clk_2_E_in ( p597 ) , .clk_2_S_in ( p2386 ) , .clk_2_W_in ( p590 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_4411 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_4412 ) , .clk_2_N_out ( SYNOPSYS_UNCONNECTED_4413 ) , @@ -112822,16 +117344,16 @@ sb_1__1_ sb_8__8_ ( .chanx_right_out ( sb_1__1__84_chanx_right_out ) , .chany_bottom_out ( sb_1__1__84_chany_bottom_out ) , .chanx_left_out ( sb_1__1__84_chanx_left_out ) , - .ccff_tail ( sb_1__1__84_ccff_tail ) , .Test_en_S_in ( p1491 ) , + .ccff_tail ( sb_1__1__84_ccff_tail ) , .Test_en_S_in ( p2323 ) , .Test_en_N_out ( SYNOPSYS_UNCONNECTED_4422 ) , .pReset_S_in ( SYNOPSYS_UNCONNECTED_4423 ) , .pReset_E_in ( SYNOPSYS_UNCONNECTED_4424 ) , .pReset_W_in ( pResetWires[434] ) , .pReset_N_out ( pResetWires[436] ) , .pReset_W_out ( SYNOPSYS_UNCONNECTED_4425 ) , - .pReset_E_out ( pResetWires[437] ) , .Reset_S_in ( p1491 ) , + .pReset_E_out ( pResetWires[437] ) , .Reset_S_in ( p2323 ) , .Reset_N_out ( SYNOPSYS_UNCONNECTED_4426 ) , - .prog_clk_0_N_in ( prog_clk_0_wires[317] ) , .prog_clk_1_N_in ( p1793 ) , - .prog_clk_1_S_in ( p165 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[317] ) , .prog_clk_1_N_in ( p1425 ) , + .prog_clk_1_S_in ( p2105 ) , .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_4427 ) , .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_4428 ) , .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_4429 ) , @@ -112849,8 +117371,8 @@ sb_1__1_ sb_8__8_ ( .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_4437 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4438 ) , .prog_clk_3_N_out ( prog_clk_3_wires[36] ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_4439 ) , .clk_1_N_in ( p1793 ) , - .clk_1_S_in ( p805 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_4440 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_4439 ) , .clk_1_N_in ( p1425 ) , + .clk_1_S_in ( p1187 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_4440 ) , .clk_1_W_out ( SYNOPSYS_UNCONNECTED_4441 ) , .clk_2_N_in ( SYNOPSYS_UNCONNECTED_4442 ) , .clk_2_E_in ( SYNOPSYS_UNCONNECTED_4443 ) , @@ -112911,20 +117433,20 @@ sb_1__1_ sb_8__9_ ( .chanx_right_out ( sb_1__1__85_chanx_right_out ) , .chany_bottom_out ( sb_1__1__85_chany_bottom_out ) , .chanx_left_out ( sb_1__1__85_chanx_left_out ) , - .ccff_tail ( sb_1__1__85_ccff_tail ) , .Test_en_S_in ( p2466 ) , + .ccff_tail ( sb_1__1__85_ccff_tail ) , .Test_en_S_in ( p2302 ) , .Test_en_N_out ( SYNOPSYS_UNCONNECTED_4454 ) , .pReset_S_in ( SYNOPSYS_UNCONNECTED_4455 ) , .pReset_E_in ( SYNOPSYS_UNCONNECTED_4456 ) , .pReset_W_in ( pResetWires[483] ) , .pReset_N_out ( pResetWires[485] ) , .pReset_W_out ( SYNOPSYS_UNCONNECTED_4457 ) , - .pReset_E_out ( pResetWires[486] ) , .Reset_S_in ( p2466 ) , + .pReset_E_out ( pResetWires[486] ) , .Reset_S_in ( p2302 ) , .Reset_N_out ( SYNOPSYS_UNCONNECTED_4458 ) , - .prog_clk_0_N_in ( prog_clk_0_wires[320] ) , .prog_clk_1_N_in ( p1563 ) , - .prog_clk_1_S_in ( p588 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[320] ) , .prog_clk_1_N_in ( p1486 ) , + .prog_clk_1_S_in ( p376 ) , .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_4459 ) , .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_4460 ) , - .prog_clk_2_N_in ( p2433 ) , .prog_clk_2_E_in ( p909 ) , - .prog_clk_2_S_in ( p2011 ) , .prog_clk_2_W_in ( p345 ) , + .prog_clk_2_N_in ( p1867 ) , .prog_clk_2_E_in ( p757 ) , + .prog_clk_2_S_in ( p791 ) , .prog_clk_2_W_in ( p165 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_4461 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_4462 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_4463 ) , @@ -112936,10 +117458,10 @@ sb_1__1_ sb_8__9_ ( .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_4468 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4469 ) , .prog_clk_3_N_out ( prog_clk_3_wires[40] ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_4470 ) , .clk_1_N_in ( p1563 ) , - .clk_1_S_in ( p1028 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_4471 ) , - .clk_1_W_out ( SYNOPSYS_UNCONNECTED_4472 ) , .clk_2_N_in ( p2121 ) , - .clk_2_E_in ( p115 ) , .clk_2_S_in ( p2307 ) , .clk_2_W_in ( p894 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_4470 ) , .clk_1_N_in ( p1486 ) , + .clk_1_S_in ( p848 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_4471 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_4472 ) , .clk_2_N_in ( p1867 ) , + .clk_2_E_in ( p814 ) , .clk_2_S_in ( p2116 ) , .clk_2_W_in ( p873 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_4473 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_4474 ) , .clk_2_N_out ( SYNOPSYS_UNCONNECTED_4475 ) , @@ -112995,16 +117517,16 @@ sb_1__1_ sb_8__10_ ( .chanx_right_out ( sb_1__1__86_chanx_right_out ) , .chany_bottom_out ( sb_1__1__86_chany_bottom_out ) , .chanx_left_out ( sb_1__1__86_chanx_left_out ) , - .ccff_tail ( sb_1__1__86_ccff_tail ) , .Test_en_S_in ( p1907 ) , + .ccff_tail ( sb_1__1__86_ccff_tail ) , .Test_en_S_in ( p2241 ) , .Test_en_N_out ( SYNOPSYS_UNCONNECTED_4484 ) , .pReset_S_in ( SYNOPSYS_UNCONNECTED_4485 ) , .pReset_E_in ( SYNOPSYS_UNCONNECTED_4486 ) , .pReset_W_in ( pResetWires[532] ) , .pReset_N_out ( pResetWires[534] ) , .pReset_W_out ( SYNOPSYS_UNCONNECTED_4487 ) , - .pReset_E_out ( pResetWires[535] ) , .Reset_S_in ( p1907 ) , + .pReset_E_out ( pResetWires[535] ) , .Reset_S_in ( p2241 ) , .Reset_N_out ( SYNOPSYS_UNCONNECTED_4488 ) , - .prog_clk_0_N_in ( prog_clk_0_wires[323] ) , .prog_clk_1_N_in ( p1562 ) , - .prog_clk_1_S_in ( p55 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[323] ) , .prog_clk_1_N_in ( p2264 ) , + .prog_clk_1_S_in ( p623 ) , .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_4489 ) , .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_4490 ) , .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_4491 ) , @@ -113014,14 +117536,14 @@ sb_1__1_ sb_8__10_ ( .prog_clk_2_W_out ( prog_clk_2_wires[106] ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_4494 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_4495 ) , - .prog_clk_2_E_out ( prog_clk_2_wires[104] ) , .prog_clk_3_W_in ( p2183 ) , - .prog_clk_3_E_in ( p1074 ) , .prog_clk_3_S_in ( p1969 ) , - .prog_clk_3_N_in ( p750 ) , + .prog_clk_2_E_out ( prog_clk_2_wires[104] ) , .prog_clk_3_W_in ( p1434 ) , + .prog_clk_3_E_in ( p20 ) , .prog_clk_3_S_in ( p2087 ) , + .prog_clk_3_N_in ( p468 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_4496 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4497 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_4498 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_4499 ) , .clk_1_N_in ( p1562 ) , - .clk_1_S_in ( p515 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_4500 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_4499 ) , .clk_1_N_in ( p2264 ) , + .clk_1_S_in ( p886 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_4500 ) , .clk_1_W_out ( SYNOPSYS_UNCONNECTED_4501 ) , .clk_2_N_in ( SYNOPSYS_UNCONNECTED_4502 ) , .clk_2_E_in ( SYNOPSYS_UNCONNECTED_4503 ) , @@ -113030,8 +117552,8 @@ sb_1__1_ sb_8__10_ ( .clk_2_W_out ( clk_2_wires[106] ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_4505 ) , .clk_2_N_out ( SYNOPSYS_UNCONNECTED_4506 ) , - .clk_2_E_out ( clk_2_wires[104] ) , .clk_3_W_in ( p2183 ) , - .clk_3_E_in ( p2009 ) , .clk_3_S_in ( p1730 ) , .clk_3_N_in ( p293 ) , + .clk_2_E_out ( clk_2_wires[104] ) , .clk_3_W_in ( p1434 ) , + .clk_3_E_in ( p916 ) , .clk_3_S_in ( p2150 ) , .clk_3_N_in ( p2118 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_4507 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4508 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_4509 ) , @@ -113079,38 +117601,38 @@ sb_1__1_ sb_8__11_ ( .chanx_right_out ( sb_1__1__87_chanx_right_out ) , .chany_bottom_out ( sb_1__1__87_chany_bottom_out ) , .chanx_left_out ( sb_1__1__87_chanx_left_out ) , - .ccff_tail ( sb_1__1__87_ccff_tail ) , .Test_en_S_in ( p2997 ) , + .ccff_tail ( sb_1__1__87_ccff_tail ) , .Test_en_S_in ( p1860 ) , .Test_en_N_out ( SYNOPSYS_UNCONNECTED_4512 ) , .pReset_S_in ( SYNOPSYS_UNCONNECTED_4513 ) , .pReset_E_in ( SYNOPSYS_UNCONNECTED_4514 ) , .pReset_W_in ( pResetWires[581] ) , .pReset_N_out ( pResetWires[583] ) , .pReset_W_out ( SYNOPSYS_UNCONNECTED_4515 ) , - .pReset_E_out ( pResetWires[584] ) , .Reset_S_in ( p3373 ) , + .pReset_E_out ( pResetWires[584] ) , .Reset_S_in ( p1860 ) , .Reset_N_out ( SYNOPSYS_UNCONNECTED_4516 ) , - .prog_clk_0_N_in ( prog_clk_0_wires[326] ) , .prog_clk_1_N_in ( p1539 ) , - .prog_clk_1_S_in ( p438 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[326] ) , .prog_clk_1_N_in ( p1473 ) , + .prog_clk_1_S_in ( p621 ) , .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_4517 ) , .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_4518 ) , - .prog_clk_2_N_in ( p3410 ) , .prog_clk_2_E_in ( p731 ) , - .prog_clk_2_S_in ( p1627 ) , .prog_clk_2_W_in ( p196 ) , + .prog_clk_2_N_in ( p3575 ) , .prog_clk_2_E_in ( p520 ) , + .prog_clk_2_S_in ( p1250 ) , .prog_clk_2_W_in ( p185 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_4519 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_4520 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_4521 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_4522 ) , - .prog_clk_3_W_in ( p3078 ) , .prog_clk_3_E_in ( p982 ) , - .prog_clk_3_S_in ( p339 ) , .prog_clk_3_N_in ( p3382 ) , + .prog_clk_3_W_in ( p2762 ) , .prog_clk_3_E_in ( p16 ) , + .prog_clk_3_S_in ( p7 ) , .prog_clk_3_N_in ( p3565 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_4523 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4524 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_4525 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_4526 ) , .clk_1_N_in ( p1539 ) , - .clk_1_S_in ( p993 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_4527 ) , - .clk_1_W_out ( SYNOPSYS_UNCONNECTED_4528 ) , .clk_2_N_in ( p3402 ) , - .clk_2_E_in ( p833 ) , .clk_2_S_in ( p3334 ) , .clk_2_W_in ( p3006 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_4526 ) , .clk_1_N_in ( p1473 ) , + .clk_1_S_in ( p730 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_4527 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_4528 ) , .clk_2_N_in ( p3589 ) , + .clk_2_E_in ( p1279 ) , .clk_2_S_in ( p1105 ) , .clk_2_W_in ( p3605 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_4529 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_4530 ) , .clk_2_N_out ( SYNOPSYS_UNCONNECTED_4531 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_4532 ) , .clk_3_W_in ( p3078 ) , - .clk_3_E_in ( p274 ) , .clk_3_S_in ( p14 ) , .clk_3_N_in ( p3394 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_4532 ) , .clk_3_W_in ( p3610 ) , + .clk_3_E_in ( p337 ) , .clk_3_S_in ( p1781 ) , .clk_3_N_in ( p3584 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_4533 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4534 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_4535 ) , @@ -113158,27 +117680,27 @@ sb_1__1_ sb_9__1_ ( .chanx_right_out ( sb_1__1__88_chanx_right_out ) , .chany_bottom_out ( sb_1__1__88_chany_bottom_out ) , .chanx_left_out ( sb_1__1__88_chanx_left_out ) , - .ccff_tail ( sb_1__1__88_ccff_tail ) , .Test_en_S_in ( p2936 ) , + .ccff_tail ( sb_1__1__88_ccff_tail ) , .Test_en_S_in ( p1545 ) , .Test_en_N_out ( SYNOPSYS_UNCONNECTED_4538 ) , .pReset_S_in ( SYNOPSYS_UNCONNECTED_4539 ) , .pReset_E_in ( SYNOPSYS_UNCONNECTED_4540 ) , .pReset_W_in ( pResetWires[95] ) , .pReset_N_out ( pResetWires[97] ) , .pReset_W_out ( SYNOPSYS_UNCONNECTED_4541 ) , - .pReset_E_out ( pResetWires[98] ) , .Reset_S_in ( p2936 ) , + .pReset_E_out ( pResetWires[98] ) , .Reset_S_in ( p1545 ) , .Reset_N_out ( SYNOPSYS_UNCONNECTED_4542 ) , .prog_clk_0_N_in ( prog_clk_0_wires[334] ) , .prog_clk_1_N_in ( prog_clk_2_wires[76] ) , .prog_clk_1_S_in ( SYNOPSYS_UNCONNECTED_4543 ) , .prog_clk_1_E_out ( prog_clk_1_wires[169] ) , - .prog_clk_1_W_out ( prog_clk_1_wires[170] ) , .prog_clk_2_N_in ( p3282 ) , - .prog_clk_2_E_in ( p370 ) , .prog_clk_2_S_in ( p1409 ) , - .prog_clk_2_W_in ( p58 ) , + .prog_clk_1_W_out ( prog_clk_1_wires[170] ) , .prog_clk_2_N_in ( p3509 ) , + .prog_clk_2_E_in ( p213 ) , .prog_clk_2_S_in ( p711 ) , + .prog_clk_2_W_in ( p292 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_4544 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_4545 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_4546 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_4547 ) , - .prog_clk_3_W_in ( p3062 ) , .prog_clk_3_E_in ( p1061 ) , - .prog_clk_3_S_in ( p188 ) , .prog_clk_3_N_in ( p3304 ) , + .prog_clk_3_W_in ( p2983 ) , .prog_clk_3_E_in ( p1066 ) , + .prog_clk_3_S_in ( p1306 ) , .prog_clk_3_N_in ( p3493 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_4548 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4549 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_4550 ) , @@ -113186,12 +117708,12 @@ sb_1__1_ sb_9__1_ ( .clk_1_N_in ( clk_2_wires[76] ) , .clk_1_S_in ( SYNOPSYS_UNCONNECTED_4552 ) , .clk_1_E_out ( clk_1_wires[169] ) , .clk_1_W_out ( clk_1_wires[170] ) , - .clk_2_N_in ( p3493 ) , .clk_2_E_in ( p157 ) , .clk_2_S_in ( p2878 ) , - .clk_2_W_in ( p3014 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_4553 ) , + .clk_2_N_in ( p2821 ) , .clk_2_E_in ( p1192 ) , .clk_2_S_in ( p55 ) , + .clk_2_W_in ( p3189 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_4553 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_4554 ) , .clk_2_N_out ( SYNOPSYS_UNCONNECTED_4555 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_4556 ) , .clk_3_W_in ( p3062 ) , - .clk_3_E_in ( p955 ) , .clk_3_S_in ( p1304 ) , .clk_3_N_in ( p3490 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_4556 ) , .clk_3_W_in ( p3249 ) , + .clk_3_E_in ( p326 ) , .clk_3_S_in ( p1143 ) , .clk_3_N_in ( p2655 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_4557 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4558 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_4559 ) , @@ -113239,16 +117761,16 @@ sb_1__1_ sb_9__2_ ( .chanx_right_out ( sb_1__1__89_chanx_right_out ) , .chany_bottom_out ( sb_1__1__89_chany_bottom_out ) , .chanx_left_out ( sb_1__1__89_chanx_left_out ) , - .ccff_tail ( sb_1__1__89_ccff_tail ) , .Test_en_S_in ( p2440 ) , + .ccff_tail ( sb_1__1__89_ccff_tail ) , .Test_en_S_in ( p1918 ) , .Test_en_N_out ( SYNOPSYS_UNCONNECTED_4562 ) , .pReset_S_in ( SYNOPSYS_UNCONNECTED_4563 ) , .pReset_E_in ( SYNOPSYS_UNCONNECTED_4564 ) , .pReset_W_in ( pResetWires[144] ) , .pReset_N_out ( pResetWires[146] ) , .pReset_W_out ( SYNOPSYS_UNCONNECTED_4565 ) , - .pReset_E_out ( pResetWires[147] ) , .Reset_S_in ( p2440 ) , + .pReset_E_out ( pResetWires[147] ) , .Reset_S_in ( p1918 ) , .Reset_N_out ( SYNOPSYS_UNCONNECTED_4566 ) , - .prog_clk_0_N_in ( prog_clk_0_wires[337] ) , .prog_clk_1_N_in ( p1903 ) , - .prog_clk_1_S_in ( p413 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[337] ) , .prog_clk_1_N_in ( p1462 ) , + .prog_clk_1_S_in ( p745 ) , .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_4567 ) , .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_4568 ) , .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_4569 ) , @@ -113259,13 +117781,13 @@ sb_1__1_ sb_9__2_ ( .prog_clk_2_S_out ( prog_clk_2_wires[75] ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_4573 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_4574 ) , - .prog_clk_3_W_in ( p1400 ) , .prog_clk_3_E_in ( p45 ) , - .prog_clk_3_S_in ( p646 ) , .prog_clk_3_N_in ( p763 ) , + .prog_clk_3_W_in ( p1636 ) , .prog_clk_3_E_in ( p851 ) , + .prog_clk_3_S_in ( p639 ) , .prog_clk_3_N_in ( p191 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_4575 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4576 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_4577 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_4578 ) , .clk_1_N_in ( p1903 ) , - .clk_1_S_in ( p1103 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_4579 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_4578 ) , .clk_1_N_in ( p1462 ) , + .clk_1_S_in ( p41 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_4579 ) , .clk_1_W_out ( SYNOPSYS_UNCONNECTED_4580 ) , .clk_2_N_in ( SYNOPSYS_UNCONNECTED_4581 ) , .clk_2_E_in ( SYNOPSYS_UNCONNECTED_4582 ) , @@ -113274,8 +117796,8 @@ sb_1__1_ sb_9__2_ ( .clk_2_W_out ( SYNOPSYS_UNCONNECTED_4584 ) , .clk_2_S_out ( clk_2_wires[75] ) , .clk_2_N_out ( SYNOPSYS_UNCONNECTED_4585 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_4586 ) , .clk_3_W_in ( p1400 ) , - .clk_3_E_in ( p821 ) , .clk_3_S_in ( p2336 ) , .clk_3_N_in ( p1633 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_4586 ) , .clk_3_W_in ( p1636 ) , + .clk_3_E_in ( p120 ) , .clk_3_S_in ( p1674 ) , .clk_3_N_in ( p753 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_4587 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4588 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_4589 ) , @@ -113323,27 +117845,27 @@ sb_1__1_ sb_9__3_ ( .chanx_right_out ( sb_1__1__90_chanx_right_out ) , .chany_bottom_out ( sb_1__1__90_chany_bottom_out ) , .chanx_left_out ( sb_1__1__90_chanx_left_out ) , - .ccff_tail ( sb_1__1__90_ccff_tail ) , .Test_en_S_in ( p3273 ) , + .ccff_tail ( sb_1__1__90_ccff_tail ) , .Test_en_S_in ( p1985 ) , .Test_en_N_out ( SYNOPSYS_UNCONNECTED_4592 ) , .pReset_S_in ( SYNOPSYS_UNCONNECTED_4593 ) , .pReset_E_in ( SYNOPSYS_UNCONNECTED_4594 ) , .pReset_W_in ( pResetWires[193] ) , .pReset_N_out ( pResetWires[195] ) , .pReset_W_out ( SYNOPSYS_UNCONNECTED_4595 ) , - .pReset_E_out ( pResetWires[196] ) , .Reset_S_in ( p3395 ) , + .pReset_E_out ( pResetWires[196] ) , .Reset_S_in ( p1985 ) , .Reset_N_out ( SYNOPSYS_UNCONNECTED_4596 ) , .prog_clk_0_N_in ( prog_clk_0_wires[340] ) , .prog_clk_1_N_in ( prog_clk_2_wires[89] ) , .prog_clk_1_S_in ( SYNOPSYS_UNCONNECTED_4597 ) , .prog_clk_1_E_out ( prog_clk_1_wires[176] ) , - .prog_clk_1_W_out ( prog_clk_1_wires[177] ) , .prog_clk_2_N_in ( p2379 ) , - .prog_clk_2_E_in ( p492 ) , .prog_clk_2_S_in ( p1270 ) , - .prog_clk_2_W_in ( p437 ) , + .prog_clk_1_W_out ( prog_clk_1_wires[177] ) , .prog_clk_2_N_in ( p3511 ) , + .prog_clk_2_E_in ( p347 ) , .prog_clk_2_S_in ( p195 ) , + .prog_clk_2_W_in ( p1012 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_4598 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_4599 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_4600 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_4601 ) , - .prog_clk_3_W_in ( p2204 ) , .prog_clk_3_E_in ( p1371 ) , - .prog_clk_3_S_in ( p640 ) , .prog_clk_3_N_in ( p2319 ) , + .prog_clk_3_W_in ( p3426 ) , .prog_clk_3_E_in ( p999 ) , + .prog_clk_3_S_in ( p1214 ) , .prog_clk_3_N_in ( p3479 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_4602 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4603 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_4604 ) , @@ -113351,12 +117873,12 @@ sb_1__1_ sb_9__3_ ( .clk_1_N_in ( clk_2_wires[89] ) , .clk_1_S_in ( SYNOPSYS_UNCONNECTED_4606 ) , .clk_1_E_out ( clk_1_wires[176] ) , .clk_1_W_out ( clk_1_wires[177] ) , - .clk_2_N_in ( p2265 ) , .clk_2_E_in ( p1053 ) , .clk_2_S_in ( p3380 ) , - .clk_2_W_in ( p2035 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_4607 ) , + .clk_2_N_in ( p3502 ) , .clk_2_E_in ( p551 ) , .clk_2_S_in ( p489 ) , + .clk_2_W_in ( p3521 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_4607 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_4608 ) , .clk_2_N_out ( SYNOPSYS_UNCONNECTED_4609 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_4610 ) , .clk_3_W_in ( p2204 ) , - .clk_3_E_in ( p147 ) , .clk_3_S_in ( p1326 ) , .clk_3_N_in ( p2048 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_4610 ) , .clk_3_W_in ( p3538 ) , + .clk_3_E_in ( p167 ) , .clk_3_S_in ( p1716 ) , .clk_3_N_in ( p3494 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_4611 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4612 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_4613 ) , @@ -113404,16 +117926,16 @@ sb_1__1_ sb_9__4_ ( .chanx_right_out ( sb_1__1__91_chanx_right_out ) , .chany_bottom_out ( sb_1__1__91_chany_bottom_out ) , .chanx_left_out ( sb_1__1__91_chanx_left_out ) , - .ccff_tail ( sb_1__1__91_ccff_tail ) , .Test_en_S_in ( p2836 ) , + .ccff_tail ( sb_1__1__91_ccff_tail ) , .Test_en_S_in ( p2801 ) , .Test_en_N_out ( SYNOPSYS_UNCONNECTED_4616 ) , .pReset_S_in ( SYNOPSYS_UNCONNECTED_4617 ) , .pReset_E_in ( SYNOPSYS_UNCONNECTED_4618 ) , .pReset_W_in ( pResetWires[242] ) , .pReset_N_out ( pResetWires[244] ) , .pReset_W_out ( SYNOPSYS_UNCONNECTED_4619 ) , - .pReset_E_out ( pResetWires[245] ) , .Reset_S_in ( p2836 ) , + .pReset_E_out ( pResetWires[245] ) , .Reset_S_in ( p2801 ) , .Reset_N_out ( SYNOPSYS_UNCONNECTED_4620 ) , - .prog_clk_0_N_in ( prog_clk_0_wires[343] ) , .prog_clk_1_N_in ( p1557 ) , - .prog_clk_1_S_in ( p832 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[343] ) , .prog_clk_1_N_in ( p2310 ) , + .prog_clk_1_S_in ( p1086 ) , .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_4621 ) , .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_4622 ) , .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_4623 ) , @@ -113424,13 +117946,13 @@ sb_1__1_ sb_9__4_ ( .prog_clk_2_S_out ( prog_clk_2_wires[88] ) , .prog_clk_2_N_out ( prog_clk_2_wires[86] ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_4627 ) , - .prog_clk_3_W_in ( p1614 ) , .prog_clk_3_E_in ( p744 ) , - .prog_clk_3_S_in ( p347 ) , .prog_clk_3_N_in ( p2017 ) , + .prog_clk_3_W_in ( p2218 ) , .prog_clk_3_E_in ( p812 ) , + .prog_clk_3_S_in ( p698 ) , .prog_clk_3_N_in ( p1803 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_4628 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4629 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_4630 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_4631 ) , .clk_1_N_in ( p1557 ) , - .clk_1_S_in ( p52 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_4632 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_4631 ) , .clk_1_N_in ( p2310 ) , + .clk_1_S_in ( p644 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_4632 ) , .clk_1_W_out ( SYNOPSYS_UNCONNECTED_4633 ) , .clk_2_N_in ( SYNOPSYS_UNCONNECTED_4634 ) , .clk_2_E_in ( SYNOPSYS_UNCONNECTED_4635 ) , @@ -113438,8 +117960,8 @@ sb_1__1_ sb_9__4_ ( .clk_2_W_in ( clk_2_wires[79] ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_4637 ) , .clk_2_S_out ( clk_2_wires[88] ) , .clk_2_N_out ( clk_2_wires[86] ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_4638 ) , .clk_3_W_in ( p1614 ) , - .clk_3_E_in ( p42 ) , .clk_3_S_in ( p2740 ) , .clk_3_N_in ( p361 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_4638 ) , .clk_3_W_in ( p2305 ) , + .clk_3_E_in ( p56 ) , .clk_3_S_in ( p2665 ) , .clk_3_N_in ( p2063 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_4639 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4640 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_4641 ) , @@ -113487,40 +118009,40 @@ sb_1__1_ sb_9__5_ ( .chanx_right_out ( sb_1__1__92_chanx_right_out ) , .chany_bottom_out ( sb_1__1__92_chany_bottom_out ) , .chanx_left_out ( sb_1__1__92_chanx_left_out ) , - .ccff_tail ( sb_1__1__92_ccff_tail ) , .Test_en_S_in ( p2826 ) , + .ccff_tail ( sb_1__1__92_ccff_tail ) , .Test_en_S_in ( p1956 ) , .Test_en_N_out ( SYNOPSYS_UNCONNECTED_4644 ) , .pReset_S_in ( SYNOPSYS_UNCONNECTED_4645 ) , .pReset_E_in ( SYNOPSYS_UNCONNECTED_4646 ) , .pReset_W_in ( pResetWires[291] ) , .pReset_N_out ( pResetWires[293] ) , .pReset_W_out ( SYNOPSYS_UNCONNECTED_4647 ) , - .pReset_E_out ( pResetWires[294] ) , .Reset_S_in ( p3407 ) , + .pReset_E_out ( pResetWires[294] ) , .Reset_S_in ( p1956 ) , .Reset_N_out ( SYNOPSYS_UNCONNECTED_4648 ) , .prog_clk_0_N_in ( prog_clk_0_wires[346] ) , .prog_clk_1_N_in ( SYNOPSYS_UNCONNECTED_4649 ) , .prog_clk_1_S_in ( prog_clk_2_wires[87] ) , .prog_clk_1_E_out ( prog_clk_1_wires[183] ) , - .prog_clk_1_W_out ( prog_clk_1_wires[184] ) , .prog_clk_2_N_in ( p3509 ) , - .prog_clk_2_E_in ( p830 ) , .prog_clk_2_S_in ( p713 ) , - .prog_clk_2_W_in ( p195 ) , + .prog_clk_1_W_out ( prog_clk_1_wires[184] ) , .prog_clk_2_N_in ( p3157 ) , + .prog_clk_2_E_in ( p577 ) , .prog_clk_2_S_in ( p432 ) , + .prog_clk_2_W_in ( p50 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_4650 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_4651 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_4652 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_4653 ) , - .prog_clk_3_W_in ( p2708 ) , .prog_clk_3_E_in ( p281 ) , - .prog_clk_3_S_in ( p1331 ) , .prog_clk_3_N_in ( p3508 ) , + .prog_clk_3_W_in ( p3474 ) , .prog_clk_3_E_in ( p821 ) , + .prog_clk_3_S_in ( p1253 ) , .prog_clk_3_N_in ( p3047 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_4654 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4655 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_4656 ) , .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_4657 ) , .clk_1_N_in ( SYNOPSYS_UNCONNECTED_4658 ) , .clk_1_S_in ( clk_2_wires[87] ) , .clk_1_E_out ( clk_1_wires[183] ) , - .clk_1_W_out ( clk_1_wires[184] ) , .clk_2_N_in ( p1960 ) , - .clk_2_E_in ( p1031 ) , .clk_2_S_in ( p3387 ) , .clk_2_W_in ( p2566 ) , + .clk_1_W_out ( clk_1_wires[184] ) , .clk_2_N_in ( p3412 ) , + .clk_2_E_in ( p712 ) , .clk_2_S_in ( p473 ) , .clk_2_W_in ( p3442 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_4659 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_4660 ) , .clk_2_N_out ( SYNOPSYS_UNCONNECTED_4661 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_4662 ) , .clk_3_W_in ( p2708 ) , - .clk_3_E_in ( p1129 ) , .clk_3_S_in ( p318 ) , .clk_3_N_in ( p1713 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_4662 ) , .clk_3_W_in ( p3347 ) , + .clk_3_E_in ( p160 ) , .clk_3_S_in ( p1691 ) , .clk_3_N_in ( p3371 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_4663 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4664 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_4665 ) , @@ -113568,20 +118090,20 @@ sb_1__1_ sb_9__6_ ( .chanx_right_out ( sb_1__1__93_chanx_right_out ) , .chany_bottom_out ( sb_1__1__93_chany_bottom_out ) , .chanx_left_out ( sb_1__1__93_chanx_left_out ) , - .ccff_tail ( sb_1__1__93_ccff_tail ) , .Test_en_S_in ( p2965 ) , + .ccff_tail ( sb_1__1__93_ccff_tail ) , .Test_en_S_in ( p1547 ) , .Test_en_N_out ( SYNOPSYS_UNCONNECTED_4668 ) , .pReset_S_in ( SYNOPSYS_UNCONNECTED_4669 ) , .pReset_E_in ( SYNOPSYS_UNCONNECTED_4670 ) , .pReset_W_in ( pResetWires[340] ) , .pReset_N_out ( pResetWires[342] ) , .pReset_W_out ( SYNOPSYS_UNCONNECTED_4671 ) , - .pReset_E_out ( pResetWires[343] ) , .Reset_S_in ( p2965 ) , + .pReset_E_out ( pResetWires[343] ) , .Reset_S_in ( p1547 ) , .Reset_N_out ( SYNOPSYS_UNCONNECTED_4672 ) , - .prog_clk_0_N_in ( prog_clk_0_wires[349] ) , .prog_clk_1_N_in ( p1956 ) , - .prog_clk_1_S_in ( p297 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[349] ) , .prog_clk_1_N_in ( p1877 ) , + .prog_clk_1_S_in ( p1160 ) , .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_4673 ) , .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_4674 ) , - .prog_clk_2_N_in ( p2122 ) , .prog_clk_2_E_in ( p1151 ) , - .prog_clk_2_S_in ( p455 ) , .prog_clk_2_W_in ( p907 ) , + .prog_clk_2_N_in ( p1952 ) , .prog_clk_2_E_in ( p667 ) , + .prog_clk_2_S_in ( p39 ) , .prog_clk_2_W_in ( p743 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_4675 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_4676 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_4677 ) , @@ -113593,10 +118115,10 @@ sb_1__1_ sb_9__6_ ( .prog_clk_3_E_out ( prog_clk_3_wires[48] ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4682 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_4683 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_4684 ) , .clk_1_N_in ( p1956 ) , - .clk_1_S_in ( p75 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_4685 ) , - .clk_1_W_out ( SYNOPSYS_UNCONNECTED_4686 ) , .clk_2_N_in ( p1766 ) , - .clk_2_E_in ( p337 ) , .clk_2_S_in ( p2871 ) , .clk_2_W_in ( p216 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_4684 ) , .clk_1_N_in ( p1877 ) , + .clk_1_S_in ( p454 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_4685 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_4686 ) , .clk_2_N_in ( p1952 ) , + .clk_2_E_in ( p267 ) , .clk_2_S_in ( p724 ) , .clk_2_W_in ( p258 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_4687 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_4688 ) , .clk_2_N_out ( SYNOPSYS_UNCONNECTED_4689 ) , @@ -113652,27 +118174,27 @@ sb_1__1_ sb_9__7_ ( .chanx_right_out ( sb_1__1__94_chanx_right_out ) , .chany_bottom_out ( sb_1__1__94_chany_bottom_out ) , .chanx_left_out ( sb_1__1__94_chanx_left_out ) , - .ccff_tail ( sb_1__1__94_ccff_tail ) , .Test_en_S_in ( p3160 ) , + .ccff_tail ( sb_1__1__94_ccff_tail ) , .Test_en_S_in ( p2344 ) , .Test_en_N_out ( SYNOPSYS_UNCONNECTED_4698 ) , .pReset_S_in ( SYNOPSYS_UNCONNECTED_4699 ) , .pReset_E_in ( SYNOPSYS_UNCONNECTED_4700 ) , .pReset_W_in ( pResetWires[389] ) , .pReset_N_out ( pResetWires[391] ) , .pReset_W_out ( SYNOPSYS_UNCONNECTED_4701 ) , - .pReset_E_out ( pResetWires[392] ) , .Reset_S_in ( p3160 ) , + .pReset_E_out ( pResetWires[392] ) , .Reset_S_in ( p2344 ) , .Reset_N_out ( SYNOPSYS_UNCONNECTED_4702 ) , .prog_clk_0_N_in ( prog_clk_0_wires[352] ) , .prog_clk_1_N_in ( prog_clk_2_wires[102] ) , .prog_clk_1_S_in ( SYNOPSYS_UNCONNECTED_4703 ) , .prog_clk_1_E_out ( prog_clk_1_wires[190] ) , - .prog_clk_1_W_out ( prog_clk_1_wires[191] ) , .prog_clk_2_N_in ( p3454 ) , - .prog_clk_2_E_in ( p724 ) , .prog_clk_2_S_in ( p752 ) , - .prog_clk_2_W_in ( p256 ) , + .prog_clk_1_W_out ( prog_clk_1_wires[191] ) , .prog_clk_2_N_in ( p3573 ) , + .prog_clk_2_E_in ( p565 ) , .prog_clk_2_S_in ( p1336 ) , + .prog_clk_2_W_in ( p339 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_4704 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_4705 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_4706 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_4707 ) , - .prog_clk_3_W_in ( p2475 ) , .prog_clk_3_E_in ( p95 ) , - .prog_clk_3_S_in ( p1046 ) , .prog_clk_3_N_in ( p3440 ) , + .prog_clk_3_W_in ( p2630 ) , .prog_clk_3_E_in ( p1113 ) , + .prog_clk_3_S_in ( p595 ) , .prog_clk_3_N_in ( p3569 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_4708 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4709 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_4710 ) , @@ -113680,12 +118202,12 @@ sb_1__1_ sb_9__7_ ( .clk_1_N_in ( clk_2_wires[102] ) , .clk_1_S_in ( SYNOPSYS_UNCONNECTED_4712 ) , .clk_1_E_out ( clk_1_wires[190] ) , .clk_1_W_out ( clk_1_wires[191] ) , - .clk_2_N_in ( p3308 ) , .clk_2_E_in ( p1063 ) , .clk_2_S_in ( p3125 ) , - .clk_2_W_in ( p2297 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_4713 ) , + .clk_2_N_in ( p2819 ) , .clk_2_E_in ( p219 ) , .clk_2_S_in ( p1031 ) , + .clk_2_W_in ( p2431 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_4713 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_4714 ) , .clk_2_N_out ( SYNOPSYS_UNCONNECTED_4715 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_4716 ) , .clk_3_W_in ( p2475 ) , - .clk_3_E_in ( p1087 ) , .clk_3_S_in ( p1269 ) , .clk_3_N_in ( p3301 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_4716 ) , .clk_3_W_in ( p1326 ) , + .clk_3_E_in ( p1056 ) , .clk_3_S_in ( p2136 ) , .clk_3_N_in ( p2660 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_4717 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4718 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_4719 ) , @@ -113733,16 +118255,16 @@ sb_1__1_ sb_9__8_ ( .chanx_right_out ( sb_1__1__95_chanx_right_out ) , .chany_bottom_out ( sb_1__1__95_chany_bottom_out ) , .chanx_left_out ( sb_1__1__95_chanx_left_out ) , - .ccff_tail ( sb_1__1__95_ccff_tail ) , .Test_en_S_in ( p3082 ) , + .ccff_tail ( sb_1__1__95_ccff_tail ) , .Test_en_S_in ( p2313 ) , .Test_en_N_out ( SYNOPSYS_UNCONNECTED_4722 ) , .pReset_S_in ( SYNOPSYS_UNCONNECTED_4723 ) , .pReset_E_in ( SYNOPSYS_UNCONNECTED_4724 ) , .pReset_W_in ( pResetWires[438] ) , .pReset_N_out ( pResetWires[440] ) , .pReset_W_out ( SYNOPSYS_UNCONNECTED_4725 ) , - .pReset_E_out ( pResetWires[441] ) , .Reset_S_in ( p3082 ) , + .pReset_E_out ( pResetWires[441] ) , .Reset_S_in ( p2313 ) , .Reset_N_out ( SYNOPSYS_UNCONNECTED_4726 ) , - .prog_clk_0_N_in ( prog_clk_0_wires[355] ) , .prog_clk_1_N_in ( p1416 ) , - .prog_clk_1_S_in ( p591 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[355] ) , .prog_clk_1_N_in ( p2011 ) , + .prog_clk_1_S_in ( p96 ) , .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_4727 ) , .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_4728 ) , .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_4729 ) , @@ -113753,13 +118275,13 @@ sb_1__1_ sb_9__8_ ( .prog_clk_2_S_out ( prog_clk_2_wires[101] ) , .prog_clk_2_N_out ( prog_clk_2_wires[99] ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_4733 ) , - .prog_clk_3_W_in ( p1868 ) , .prog_clk_3_E_in ( p897 ) , - .prog_clk_3_S_in ( p575 ) , .prog_clk_3_N_in ( p169 ) , + .prog_clk_3_W_in ( p1433 ) , .prog_clk_3_E_in ( p130 ) , + .prog_clk_3_S_in ( p576 ) , .prog_clk_3_N_in ( p405 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_4734 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4735 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_4736 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_4737 ) , .clk_1_N_in ( p1416 ) , - .clk_1_S_in ( p893 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_4738 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_4737 ) , .clk_1_N_in ( p2011 ) , + .clk_1_S_in ( p875 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_4738 ) , .clk_1_W_out ( SYNOPSYS_UNCONNECTED_4739 ) , .clk_2_N_in ( SYNOPSYS_UNCONNECTED_4740 ) , .clk_2_E_in ( SYNOPSYS_UNCONNECTED_4741 ) , @@ -113767,8 +118289,8 @@ sb_1__1_ sb_9__8_ ( .clk_2_W_in ( clk_2_wires[92] ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_4743 ) , .clk_2_S_out ( clk_2_wires[101] ) , .clk_2_N_out ( clk_2_wires[99] ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_4744 ) , .clk_3_W_in ( p1868 ) , - .clk_3_E_in ( p321 ) , .clk_3_S_in ( p3018 ) , .clk_3_N_in ( p674 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_4744 ) , .clk_3_W_in ( p1433 ) , + .clk_3_E_in ( p967 ) , .clk_3_S_in ( p2104 ) , .clk_3_N_in ( p1680 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_4745 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4746 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_4747 ) , @@ -113816,40 +118338,40 @@ sb_1__1_ sb_9__9_ ( .chanx_right_out ( sb_1__1__96_chanx_right_out ) , .chany_bottom_out ( sb_1__1__96_chany_bottom_out ) , .chanx_left_out ( sb_1__1__96_chanx_left_out ) , - .ccff_tail ( sb_1__1__96_ccff_tail ) , .Test_en_S_in ( p2511 ) , + .ccff_tail ( sb_1__1__96_ccff_tail ) , .Test_en_S_in ( p1318 ) , .Test_en_N_out ( SYNOPSYS_UNCONNECTED_4750 ) , .pReset_S_in ( SYNOPSYS_UNCONNECTED_4751 ) , .pReset_E_in ( SYNOPSYS_UNCONNECTED_4752 ) , .pReset_W_in ( pResetWires[487] ) , .pReset_N_out ( pResetWires[489] ) , .pReset_W_out ( SYNOPSYS_UNCONNECTED_4753 ) , - .pReset_E_out ( pResetWires[490] ) , .Reset_S_in ( p2511 ) , + .pReset_E_out ( pResetWires[490] ) , .Reset_S_in ( p1318 ) , .Reset_N_out ( SYNOPSYS_UNCONNECTED_4754 ) , .prog_clk_0_N_in ( prog_clk_0_wires[358] ) , .prog_clk_1_N_in ( SYNOPSYS_UNCONNECTED_4755 ) , .prog_clk_1_S_in ( prog_clk_2_wires[100] ) , .prog_clk_1_E_out ( prog_clk_1_wires[197] ) , - .prog_clk_1_W_out ( prog_clk_1_wires[198] ) , .prog_clk_2_N_in ( p3470 ) , - .prog_clk_2_E_in ( p545 ) , .prog_clk_2_S_in ( p439 ) , - .prog_clk_2_W_in ( p536 ) , + .prog_clk_1_W_out ( prog_clk_1_wires[198] ) , .prog_clk_2_N_in ( p3248 ) , + .prog_clk_2_E_in ( p536 ) , .prog_clk_2_S_in ( p678 ) , + .prog_clk_2_W_in ( p903 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_4756 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_4757 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_4758 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_4759 ) , - .prog_clk_3_W_in ( p2683 ) , .prog_clk_3_E_in ( p1215 ) , - .prog_clk_3_S_in ( p1450 ) , .prog_clk_3_N_in ( p3462 ) , + .prog_clk_3_W_in ( p2311 ) , .prog_clk_3_E_in ( p544 ) , + .prog_clk_3_S_in ( p1077 ) , .prog_clk_3_N_in ( p3195 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_4760 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4761 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_4762 ) , .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_4763 ) , .clk_1_N_in ( SYNOPSYS_UNCONNECTED_4764 ) , .clk_1_S_in ( clk_2_wires[100] ) , .clk_1_E_out ( clk_1_wires[197] ) , - .clk_1_W_out ( clk_1_wires[198] ) , .clk_2_N_in ( p3370 ) , - .clk_2_E_in ( p927 ) , .clk_2_S_in ( p2318 ) , .clk_2_W_in ( p2537 ) , + .clk_1_W_out ( clk_1_wires[198] ) , .clk_2_N_in ( p2074 ) , + .clk_2_E_in ( p69 ) , .clk_2_S_in ( p159 ) , .clk_2_W_in ( p3438 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_4765 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_4766 ) , .clk_2_N_out ( SYNOPSYS_UNCONNECTED_4767 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_4768 ) , .clk_3_W_in ( p2683 ) , - .clk_3_E_in ( p335 ) , .clk_3_S_in ( p1332 ) , .clk_3_N_in ( p3343 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_4768 ) , .clk_3_W_in ( p3458 ) , + .clk_3_E_in ( p1231 ) , .clk_3_S_in ( p1144 ) , .clk_3_N_in ( p2198 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_4769 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4770 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_4771 ) , @@ -113897,16 +118419,16 @@ sb_1__1_ sb_9__10_ ( .chanx_right_out ( sb_1__1__97_chanx_right_out ) , .chany_bottom_out ( sb_1__1__97_chany_bottom_out ) , .chanx_left_out ( sb_1__1__97_chanx_left_out ) , - .ccff_tail ( sb_1__1__97_ccff_tail ) , .Test_en_S_in ( p2967 ) , + .ccff_tail ( sb_1__1__97_ccff_tail ) , .Test_en_S_in ( p1942 ) , .Test_en_N_out ( SYNOPSYS_UNCONNECTED_4774 ) , .pReset_S_in ( SYNOPSYS_UNCONNECTED_4775 ) , .pReset_E_in ( SYNOPSYS_UNCONNECTED_4776 ) , .pReset_W_in ( pResetWires[536] ) , .pReset_N_out ( pResetWires[538] ) , .pReset_W_out ( SYNOPSYS_UNCONNECTED_4777 ) , - .pReset_E_out ( pResetWires[539] ) , .Reset_S_in ( p2967 ) , + .pReset_E_out ( pResetWires[539] ) , .Reset_S_in ( p1942 ) , .Reset_N_out ( SYNOPSYS_UNCONNECTED_4778 ) , - .prog_clk_0_N_in ( prog_clk_0_wires[361] ) , .prog_clk_1_N_in ( p1328 ) , - .prog_clk_1_S_in ( p1019 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[361] ) , .prog_clk_1_N_in ( p1961 ) , + .prog_clk_1_S_in ( p751 ) , .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_4779 ) , .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_4780 ) , .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_4781 ) , @@ -113917,13 +118439,13 @@ sb_1__1_ sb_9__10_ ( .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_4785 ) , .prog_clk_2_N_out ( prog_clk_2_wires[110] ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_4786 ) , - .prog_clk_3_W_in ( p1556 ) , .prog_clk_3_E_in ( p760 ) , - .prog_clk_3_S_in ( p368 ) , .prog_clk_3_N_in ( p765 ) , + .prog_clk_3_W_in ( p1898 ) , .prog_clk_3_E_in ( p624 ) , + .prog_clk_3_S_in ( p147 ) , .prog_clk_3_N_in ( p367 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_4787 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4788 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_4789 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_4790 ) , .clk_1_N_in ( p1328 ) , - .clk_1_S_in ( p104 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_4791 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_4790 ) , .clk_1_N_in ( p1961 ) , + .clk_1_S_in ( p415 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_4791 ) , .clk_1_W_out ( SYNOPSYS_UNCONNECTED_4792 ) , .clk_2_N_in ( SYNOPSYS_UNCONNECTED_4793 ) , .clk_2_E_in ( SYNOPSYS_UNCONNECTED_4794 ) , @@ -113932,8 +118454,8 @@ sb_1__1_ sb_9__10_ ( .clk_2_W_out ( SYNOPSYS_UNCONNECTED_4796 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_4797 ) , .clk_2_N_out ( clk_2_wires[110] ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_4798 ) , .clk_3_W_in ( p1556 ) , - .clk_3_E_in ( p210 ) , .clk_3_S_in ( p2869 ) , .clk_3_N_in ( p395 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_4798 ) , .clk_3_W_in ( p1898 ) , + .clk_3_E_in ( p393 ) , .clk_3_S_in ( p1709 ) , .clk_3_N_in ( p1721 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_4799 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4800 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_4801 ) , @@ -113981,40 +118503,40 @@ sb_1__1_ sb_9__11_ ( .chanx_right_out ( sb_1__1__98_chanx_right_out ) , .chany_bottom_out ( sb_1__1__98_chany_bottom_out ) , .chanx_left_out ( sb_1__1__98_chanx_left_out ) , - .ccff_tail ( sb_1__1__98_ccff_tail ) , .Test_en_S_in ( p2151 ) , + .ccff_tail ( sb_1__1__98_ccff_tail ) , .Test_en_S_in ( p2558 ) , .Test_en_N_out ( SYNOPSYS_UNCONNECTED_4804 ) , .pReset_S_in ( SYNOPSYS_UNCONNECTED_4805 ) , .pReset_E_in ( SYNOPSYS_UNCONNECTED_4806 ) , .pReset_W_in ( pResetWires[585] ) , .pReset_N_out ( pResetWires[587] ) , .pReset_W_out ( SYNOPSYS_UNCONNECTED_4807 ) , - .pReset_E_out ( pResetWires[588] ) , .Reset_S_in ( p3478 ) , + .pReset_E_out ( pResetWires[588] ) , .Reset_S_in ( p2558 ) , .Reset_N_out ( SYNOPSYS_UNCONNECTED_4808 ) , .prog_clk_0_N_in ( prog_clk_0_wires[364] ) , .prog_clk_1_N_in ( SYNOPSYS_UNCONNECTED_4809 ) , .prog_clk_1_S_in ( prog_clk_2_wires[111] ) , .prog_clk_1_E_out ( prog_clk_1_wires[204] ) , - .prog_clk_1_W_out ( prog_clk_1_wires[205] ) , .prog_clk_2_N_in ( p3469 ) , - .prog_clk_2_E_in ( p929 ) , .prog_clk_2_S_in ( p478 ) , - .prog_clk_2_W_in ( p524 ) , + .prog_clk_1_W_out ( prog_clk_1_wires[205] ) , .prog_clk_2_N_in ( p2515 ) , + .prog_clk_2_E_in ( p474 ) , .prog_clk_2_S_in ( p174 ) , + .prog_clk_2_W_in ( p221 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_4810 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_4811 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_4812 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_4813 ) , - .prog_clk_3_W_in ( p1851 ) , .prog_clk_3_E_in ( p214 ) , - .prog_clk_3_S_in ( p754 ) , .prog_clk_3_N_in ( p3459 ) , + .prog_clk_3_W_in ( p2040 ) , .prog_clk_3_E_in ( p888 ) , + .prog_clk_3_S_in ( p1128 ) , .prog_clk_3_N_in ( p2467 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_4814 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4815 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_4816 ) , .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_4817 ) , .clk_1_N_in ( SYNOPSYS_UNCONNECTED_4818 ) , .clk_1_S_in ( clk_2_wires[111] ) , .clk_1_E_out ( clk_1_wires[204] ) , - .clk_1_W_out ( clk_1_wires[205] ) , .clk_2_N_in ( p3098 ) , - .clk_2_E_in ( p913 ) , .clk_2_S_in ( p3474 ) , .clk_2_W_in ( p1704 ) , + .clk_1_W_out ( clk_1_wires[205] ) , .clk_2_N_in ( p3556 ) , + .clk_2_E_in ( p108 ) , .clk_2_S_in ( p931 ) , .clk_2_W_in ( p2913 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_4819 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_4820 ) , .clk_2_N_out ( SYNOPSYS_UNCONNECTED_4821 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_4822 ) , .clk_3_W_in ( p1851 ) , - .clk_3_E_in ( p873 ) , .clk_3_S_in ( p1386 ) , .clk_3_N_in ( p3004 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_4822 ) , .clk_3_W_in ( p2993 ) , + .clk_3_E_in ( p1247 ) , .clk_3_S_in ( p2383 ) , .clk_3_N_in ( p3551 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_4823 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4824 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_4825 ) , @@ -114062,38 +118584,38 @@ sb_1__1_ sb_10__1_ ( .chanx_right_out ( sb_1__1__99_chanx_right_out ) , .chany_bottom_out ( sb_1__1__99_chany_bottom_out ) , .chanx_left_out ( sb_1__1__99_chanx_left_out ) , - .ccff_tail ( sb_1__1__99_ccff_tail ) , .Test_en_S_in ( p2490 ) , + .ccff_tail ( sb_1__1__99_ccff_tail ) , .Test_en_S_in ( p1357 ) , .Test_en_N_out ( SYNOPSYS_UNCONNECTED_4828 ) , .pReset_S_in ( SYNOPSYS_UNCONNECTED_4829 ) , .pReset_E_in ( SYNOPSYS_UNCONNECTED_4830 ) , .pReset_W_in ( pResetWires[99] ) , .pReset_N_out ( pResetWires[101] ) , .pReset_W_out ( SYNOPSYS_UNCONNECTED_4831 ) , - .pReset_E_out ( pResetWires[102] ) , .Reset_S_in ( p2388 ) , + .pReset_E_out ( pResetWires[102] ) , .Reset_S_in ( p1357 ) , .Reset_N_out ( SYNOPSYS_UNCONNECTED_4832 ) , - .prog_clk_0_N_in ( prog_clk_0_wires[372] ) , .prog_clk_1_N_in ( p1841 ) , - .prog_clk_1_S_in ( p1079 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[372] ) , .prog_clk_1_N_in ( p1838 ) , + .prog_clk_1_S_in ( p1072 ) , .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_4833 ) , .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_4834 ) , - .prog_clk_2_N_in ( p3371 ) , .prog_clk_2_E_in ( p827 ) , - .prog_clk_2_S_in ( p658 ) , .prog_clk_2_W_in ( p1268 ) , + .prog_clk_2_N_in ( p3503 ) , .prog_clk_2_E_in ( p953 ) , + .prog_clk_2_S_in ( p844 ) , .prog_clk_2_W_in ( p232 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_4835 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_4836 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_4837 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_4838 ) , - .prog_clk_3_W_in ( p2934 ) , .prog_clk_3_E_in ( p1152 ) , - .prog_clk_3_S_in ( p1187 ) , .prog_clk_3_N_in ( p3342 ) , + .prog_clk_3_W_in ( p1993 ) , .prog_clk_3_E_in ( p561 ) , + .prog_clk_3_S_in ( p46 ) , .prog_clk_3_N_in ( p3483 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_4839 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4840 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_4841 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_4842 ) , .clk_1_N_in ( p1841 ) , - .clk_1_S_in ( p208 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_4843 ) , - .clk_1_W_out ( SYNOPSYS_UNCONNECTED_4844 ) , .clk_2_N_in ( p2695 ) , - .clk_2_E_in ( p708 ) , .clk_2_S_in ( p2334 ) , .clk_2_W_in ( p2875 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_4842 ) , .clk_1_N_in ( p1838 ) , + .clk_1_S_in ( p419 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_4843 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_4844 ) , .clk_2_N_in ( p3532 ) , + .clk_2_E_in ( p807 ) , .clk_2_S_in ( p773 ) , .clk_2_W_in ( p3293 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_4845 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_4846 ) , .clk_2_N_out ( SYNOPSYS_UNCONNECTED_4847 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_4848 ) , .clk_3_W_in ( p2934 ) , - .clk_3_E_in ( p28 ) , .clk_3_S_in ( p1408 ) , .clk_3_N_in ( p2557 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_4848 ) , .clk_3_W_in ( p3338 ) , + .clk_3_E_in ( p29 ) , .clk_3_S_in ( p1124 ) , .clk_3_N_in ( p3519 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_4849 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4850 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_4851 ) , @@ -114141,16 +118663,16 @@ sb_1__1_ sb_10__2_ ( .chanx_right_out ( sb_1__1__100_chanx_right_out ) , .chany_bottom_out ( sb_1__1__100_chany_bottom_out ) , .chanx_left_out ( sb_1__1__100_chanx_left_out ) , - .ccff_tail ( sb_1__1__100_ccff_tail ) , .Test_en_S_in ( p2505 ) , + .ccff_tail ( sb_1__1__100_ccff_tail ) , .Test_en_S_in ( p2007 ) , .Test_en_N_out ( SYNOPSYS_UNCONNECTED_4854 ) , .pReset_S_in ( SYNOPSYS_UNCONNECTED_4855 ) , .pReset_E_in ( SYNOPSYS_UNCONNECTED_4856 ) , .pReset_W_in ( pResetWires[148] ) , .pReset_N_out ( pResetWires[150] ) , .pReset_W_out ( SYNOPSYS_UNCONNECTED_4857 ) , - .pReset_E_out ( pResetWires[151] ) , .Reset_S_in ( p2505 ) , + .pReset_E_out ( pResetWires[151] ) , .Reset_S_in ( p2007 ) , .Reset_N_out ( SYNOPSYS_UNCONNECTED_4858 ) , - .prog_clk_0_N_in ( prog_clk_0_wires[375] ) , .prog_clk_1_N_in ( p1913 ) , - .prog_clk_1_S_in ( p231 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[375] ) , .prog_clk_1_N_in ( p2290 ) , + .prog_clk_1_S_in ( p557 ) , .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_4859 ) , .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_4860 ) , .prog_clk_2_N_in ( prog_clk_3_wires[87] ) , @@ -114160,14 +118682,14 @@ sb_1__1_ sb_10__2_ ( .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_4864 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_4865 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_4866 ) , - .prog_clk_2_E_out ( prog_clk_2_wires[114] ) , .prog_clk_3_W_in ( p1451 ) , - .prog_clk_3_E_in ( p397 ) , .prog_clk_3_S_in ( p666 ) , - .prog_clk_3_N_in ( p109 ) , + .prog_clk_2_E_out ( prog_clk_2_wires[114] ) , .prog_clk_3_W_in ( p1432 ) , + .prog_clk_3_E_in ( p110 ) , .prog_clk_3_S_in ( p572 ) , + .prog_clk_3_N_in ( p780 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_4867 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4868 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_4869 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_4870 ) , .clk_1_N_in ( p1829 ) , - .clk_1_S_in ( p967 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_4871 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_4870 ) , .clk_1_N_in ( p2290 ) , + .clk_1_S_in ( p946 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_4871 ) , .clk_1_W_out ( SYNOPSYS_UNCONNECTED_4872 ) , .clk_2_N_in ( clk_3_wires[87] ) , .clk_2_E_in ( SYNOPSYS_UNCONNECTED_4873 ) , @@ -114176,8 +118698,8 @@ sb_1__1_ sb_10__2_ ( .clk_2_W_out ( SYNOPSYS_UNCONNECTED_4876 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_4877 ) , .clk_2_N_out ( SYNOPSYS_UNCONNECTED_4878 ) , - .clk_2_E_out ( clk_2_wires[114] ) , .clk_3_W_in ( p1451 ) , - .clk_3_E_in ( p1069 ) , .clk_3_S_in ( p2317 ) , .clk_3_N_in ( p1681 ) , + .clk_2_E_out ( clk_2_wires[114] ) , .clk_3_W_in ( p1432 ) , + .clk_3_E_in ( p1673 ) , .clk_3_S_in ( p1760 ) , .clk_3_N_in ( p2100 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_4879 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4880 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_4881 ) , @@ -114225,20 +118747,20 @@ sb_1__1_ sb_10__3_ ( .chanx_right_out ( sb_1__1__101_chanx_right_out ) , .chany_bottom_out ( sb_1__1__101_chany_bottom_out ) , .chanx_left_out ( sb_1__1__101_chanx_left_out ) , - .ccff_tail ( sb_1__1__101_ccff_tail ) , .Test_en_S_in ( p2931 ) , + .ccff_tail ( sb_1__1__101_ccff_tail ) , .Test_en_S_in ( p1137 ) , .Test_en_N_out ( SYNOPSYS_UNCONNECTED_4884 ) , .pReset_S_in ( SYNOPSYS_UNCONNECTED_4885 ) , .pReset_E_in ( SYNOPSYS_UNCONNECTED_4886 ) , .pReset_W_in ( pResetWires[197] ) , .pReset_N_out ( pResetWires[199] ) , .pReset_W_out ( SYNOPSYS_UNCONNECTED_4887 ) , - .pReset_E_out ( pResetWires[200] ) , .Reset_S_in ( p3249 ) , + .pReset_E_out ( pResetWires[200] ) , .Reset_S_in ( p1137 ) , .Reset_N_out ( SYNOPSYS_UNCONNECTED_4888 ) , - .prog_clk_0_N_in ( prog_clk_0_wires[378] ) , .prog_clk_1_N_in ( p1846 ) , - .prog_clk_1_S_in ( p527 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[378] ) , .prog_clk_1_N_in ( p1580 ) , + .prog_clk_1_S_in ( p1217 ) , .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_4889 ) , .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_4890 ) , - .prog_clk_2_N_in ( p2991 ) , .prog_clk_2_E_in ( p928 ) , - .prog_clk_2_S_in ( p1653 ) , .prog_clk_2_W_in ( p1180 ) , + .prog_clk_2_N_in ( p1949 ) , .prog_clk_2_E_in ( p1034 ) , + .prog_clk_2_S_in ( p1792 ) , .prog_clk_2_W_in ( p368 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_4891 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_4892 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_4893 ) , @@ -114250,10 +118772,10 @@ sb_1__1_ sb_10__3_ ( .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_4898 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4899 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_4900 ) , - .prog_clk_3_S_out ( prog_clk_3_wires[86] ) , .clk_1_N_in ( p1846 ) , - .clk_1_S_in ( p401 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_4901 ) , - .clk_1_W_out ( SYNOPSYS_UNCONNECTED_4902 ) , .clk_2_N_in ( p2694 ) , - .clk_2_E_in ( p513 ) , .clk_2_S_in ( p3215 ) , .clk_2_W_in ( p29 ) , + .prog_clk_3_S_out ( prog_clk_3_wires[86] ) , .clk_1_N_in ( p1580 ) , + .clk_1_S_in ( p463 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_4901 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_4902 ) , .clk_2_N_in ( p1949 ) , + .clk_2_E_in ( p424 ) , .clk_2_S_in ( p1702 ) , .clk_2_W_in ( p839 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_4903 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_4904 ) , .clk_2_N_out ( SYNOPSYS_UNCONNECTED_4905 ) , @@ -114309,16 +118831,16 @@ sb_1__1_ sb_10__4_ ( .chanx_right_out ( sb_1__1__102_chanx_right_out ) , .chany_bottom_out ( sb_1__1__102_chany_bottom_out ) , .chanx_left_out ( sb_1__1__102_chanx_left_out ) , - .ccff_tail ( sb_1__1__102_ccff_tail ) , .Test_en_S_in ( p1810 ) , + .ccff_tail ( sb_1__1__102_ccff_tail ) , .Test_en_S_in ( p1931 ) , .Test_en_N_out ( SYNOPSYS_UNCONNECTED_4914 ) , .pReset_S_in ( SYNOPSYS_UNCONNECTED_4915 ) , .pReset_E_in ( SYNOPSYS_UNCONNECTED_4916 ) , .pReset_W_in ( pResetWires[246] ) , .pReset_N_out ( pResetWires[248] ) , .pReset_W_out ( SYNOPSYS_UNCONNECTED_4917 ) , - .pReset_E_out ( pResetWires[249] ) , .Reset_S_in ( p1810 ) , + .pReset_E_out ( pResetWires[249] ) , .Reset_S_in ( p1931 ) , .Reset_N_out ( SYNOPSYS_UNCONNECTED_4918 ) , - .prog_clk_0_N_in ( prog_clk_0_wires[381] ) , .prog_clk_1_N_in ( p1520 ) , - .prog_clk_1_S_in ( p158 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[381] ) , .prog_clk_1_N_in ( p1362 ) , + .prog_clk_1_S_in ( p1677 ) , .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_4919 ) , .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_4920 ) , .prog_clk_2_N_in ( prog_clk_3_wires[77] ) , @@ -114336,8 +118858,8 @@ sb_1__1_ sb_10__4_ ( .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_4930 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4931 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_4932 ) , - .prog_clk_3_S_out ( prog_clk_3_wires[82] ) , .clk_1_N_in ( p1520 ) , - .clk_1_S_in ( p1655 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_4933 ) , + .prog_clk_3_S_out ( prog_clk_3_wires[82] ) , .clk_1_N_in ( p1362 ) , + .clk_1_S_in ( p759 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_4933 ) , .clk_1_W_out ( SYNOPSYS_UNCONNECTED_4934 ) , .clk_2_N_in ( clk_3_wires[77] ) , .clk_2_E_in ( SYNOPSYS_UNCONNECTED_4935 ) , @@ -114398,20 +118920,20 @@ sb_1__1_ sb_10__5_ ( .chanx_right_out ( sb_1__1__103_chanx_right_out ) , .chany_bottom_out ( sb_1__1__103_chany_bottom_out ) , .chanx_left_out ( sb_1__1__103_chanx_left_out ) , - .ccff_tail ( sb_1__1__103_ccff_tail ) , .Test_en_S_in ( p2634 ) , + .ccff_tail ( sb_1__1__103_ccff_tail ) , .Test_en_S_in ( p1953 ) , .Test_en_N_out ( SYNOPSYS_UNCONNECTED_4948 ) , .pReset_S_in ( SYNOPSYS_UNCONNECTED_4949 ) , .pReset_E_in ( SYNOPSYS_UNCONNECTED_4950 ) , .pReset_W_in ( pResetWires[295] ) , .pReset_N_out ( pResetWires[297] ) , .pReset_W_out ( SYNOPSYS_UNCONNECTED_4951 ) , - .pReset_E_out ( pResetWires[298] ) , .Reset_S_in ( p2634 ) , + .pReset_E_out ( pResetWires[298] ) , .Reset_S_in ( p1953 ) , .Reset_N_out ( SYNOPSYS_UNCONNECTED_4952 ) , - .prog_clk_0_N_in ( prog_clk_0_wires[384] ) , .prog_clk_1_N_in ( p2154 ) , - .prog_clk_1_S_in ( p725 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[384] ) , .prog_clk_1_N_in ( p1590 ) , + .prog_clk_1_S_in ( p1061 ) , .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_4953 ) , .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_4954 ) , - .prog_clk_2_N_in ( p2607 ) , .prog_clk_2_E_in ( p379 ) , - .prog_clk_2_S_in ( p1965 ) , .prog_clk_2_W_in ( p227 ) , + .prog_clk_2_N_in ( p3006 ) , .prog_clk_2_E_in ( p263 ) , + .prog_clk_2_S_in ( p396 ) , .prog_clk_2_W_in ( p615 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_4955 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_4956 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_4957 ) , @@ -114423,10 +118945,10 @@ sb_1__1_ sb_10__5_ ( .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_4962 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4963 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_4964 ) , - .prog_clk_3_S_out ( prog_clk_3_wires[76] ) , .clk_1_N_in ( p2154 ) , - .clk_1_S_in ( p359 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_4965 ) , - .clk_1_W_out ( SYNOPSYS_UNCONNECTED_4966 ) , .clk_2_N_in ( p2607 ) , - .clk_2_E_in ( p635 ) , .clk_2_S_in ( p2554 ) , .clk_2_W_in ( p816 ) , + .prog_clk_3_S_out ( prog_clk_3_wires[76] ) , .clk_1_N_in ( p1590 ) , + .clk_1_S_in ( p111 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_4965 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_4966 ) , .clk_2_N_in ( p2775 ) , + .clk_2_E_in ( p602 ) , .clk_2_S_in ( p1692 ) , .clk_2_W_in ( p315 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_4967 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_4968 ) , .clk_2_N_out ( SYNOPSYS_UNCONNECTED_4969 ) , @@ -114482,20 +119004,20 @@ sb_1__1_ sb_10__6_ ( .chanx_right_out ( sb_1__1__104_chanx_right_out ) , .chany_bottom_out ( sb_1__1__104_chany_bottom_out ) , .chanx_left_out ( sb_1__1__104_chanx_left_out ) , - .ccff_tail ( sb_1__1__104_ccff_tail ) , .Test_en_S_in ( p2775 ) , + .ccff_tail ( sb_1__1__104_ccff_tail ) , .Test_en_S_in ( p2265 ) , .Test_en_N_out ( SYNOPSYS_UNCONNECTED_4978 ) , .pReset_S_in ( SYNOPSYS_UNCONNECTED_4979 ) , .pReset_E_in ( SYNOPSYS_UNCONNECTED_4980 ) , .pReset_W_in ( pResetWires[344] ) , .pReset_N_out ( pResetWires[346] ) , .pReset_W_out ( SYNOPSYS_UNCONNECTED_4981 ) , - .pReset_E_out ( pResetWires[347] ) , .Reset_S_in ( p2775 ) , + .pReset_E_out ( pResetWires[347] ) , .Reset_S_in ( p2265 ) , .Reset_N_out ( SYNOPSYS_UNCONNECTED_4982 ) , - .prog_clk_0_N_in ( prog_clk_0_wires[387] ) , .prog_clk_1_N_in ( p1337 ) , - .prog_clk_1_S_in ( p307 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[387] ) , .prog_clk_1_N_in ( p1400 ) , + .prog_clk_1_S_in ( p870 ) , .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_4983 ) , .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_4984 ) , - .prog_clk_2_N_in ( p2209 ) , .prog_clk_2_E_in ( p1052 ) , - .prog_clk_2_S_in ( p1694 ) , .prog_clk_2_W_in ( p346 ) , + .prog_clk_2_N_in ( p2577 ) , .prog_clk_2_E_in ( p24 ) , + .prog_clk_2_S_in ( p358 ) , .prog_clk_2_W_in ( p495 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_4985 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_4986 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_4987 ) , @@ -114507,10 +119029,10 @@ sb_1__1_ sb_10__6_ ( .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_4992 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4993 ) , .prog_clk_3_N_out ( prog_clk_3_wires[70] ) , - .prog_clk_3_S_out ( prog_clk_3_wires[72] ) , .clk_1_N_in ( p1337 ) , - .clk_1_S_in ( p1025 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_4994 ) , - .clk_1_W_out ( SYNOPSYS_UNCONNECTED_4995 ) , .clk_2_N_in ( p2209 ) , - .clk_2_E_in ( p448 ) , .clk_2_S_in ( p2743 ) , .clk_2_W_in ( p1228 ) , + .prog_clk_3_S_out ( prog_clk_3_wires[72] ) , .clk_1_N_in ( p1400 ) , + .clk_1_S_in ( p141 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_4994 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_4995 ) , .clk_2_N_in ( p1191 ) , + .clk_2_E_in ( p898 ) , .clk_2_S_in ( p2101 ) , .clk_2_W_in ( p68 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_4996 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_4997 ) , .clk_2_N_out ( SYNOPSYS_UNCONNECTED_4998 ) , @@ -114565,20 +119087,20 @@ sb_1__1_ sb_10__7_ ( .chanx_right_out ( sb_1__1__105_chanx_right_out ) , .chany_bottom_out ( sb_1__1__105_chany_bottom_out ) , .chanx_left_out ( sb_1__1__105_chanx_left_out ) , - .ccff_tail ( sb_1__1__105_ccff_tail ) , .Test_en_S_in ( p2637 ) , + .ccff_tail ( sb_1__1__105_ccff_tail ) , .Test_en_S_in ( p1603 ) , .Test_en_N_out ( SYNOPSYS_UNCONNECTED_5006 ) , .pReset_S_in ( SYNOPSYS_UNCONNECTED_5007 ) , .pReset_E_in ( SYNOPSYS_UNCONNECTED_5008 ) , .pReset_W_in ( pResetWires[393] ) , .pReset_N_out ( pResetWires[395] ) , .pReset_W_out ( SYNOPSYS_UNCONNECTED_5009 ) , - .pReset_E_out ( pResetWires[396] ) , .Reset_S_in ( p3275 ) , + .pReset_E_out ( pResetWires[396] ) , .Reset_S_in ( p1603 ) , .Reset_N_out ( SYNOPSYS_UNCONNECTED_5010 ) , - .prog_clk_0_N_in ( prog_clk_0_wires[390] ) , .prog_clk_1_N_in ( p1926 ) , - .prog_clk_1_S_in ( p253 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[390] ) , .prog_clk_1_N_in ( p1566 ) , + .prog_clk_1_S_in ( p372 ) , .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_5011 ) , .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_5012 ) , - .prog_clk_2_N_in ( p2796 ) , .prog_clk_2_E_in ( p837 ) , - .prog_clk_2_S_in ( p360 ) , .prog_clk_2_W_in ( p409 ) , + .prog_clk_2_N_in ( p1573 ) , .prog_clk_2_E_in ( p503 ) , + .prog_clk_2_S_in ( p440 ) , .prog_clk_2_W_in ( p985 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5013 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_5014 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_5015 ) , @@ -114590,10 +119112,10 @@ sb_1__1_ sb_10__7_ ( .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5020 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5021 ) , .prog_clk_3_N_out ( prog_clk_3_wires[74] ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_5022 ) , .clk_1_N_in ( p1926 ) , - .clk_1_S_in ( p1280 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_5023 ) , - .clk_1_W_out ( SYNOPSYS_UNCONNECTED_5024 ) , .clk_2_N_in ( p2776 ) , - .clk_2_E_in ( p350 ) , .clk_2_S_in ( p3212 ) , .clk_2_W_in ( p53 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_5022 ) , .clk_1_N_in ( p1566 ) , + .clk_1_S_in ( p900 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_5023 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_5024 ) , .clk_2_N_in ( p1573 ) , + .clk_2_E_in ( p316 ) , .clk_2_S_in ( p346 ) , .clk_2_W_in ( p362 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5025 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_5026 ) , .clk_2_N_out ( SYNOPSYS_UNCONNECTED_5027 ) , @@ -114649,16 +119171,16 @@ sb_1__1_ sb_10__8_ ( .chanx_right_out ( sb_1__1__106_chanx_right_out ) , .chany_bottom_out ( sb_1__1__106_chany_bottom_out ) , .chanx_left_out ( sb_1__1__106_chanx_left_out ) , - .ccff_tail ( sb_1__1__106_ccff_tail ) , .Test_en_S_in ( p1891 ) , + .ccff_tail ( sb_1__1__106_ccff_tail ) , .Test_en_S_in ( p1910 ) , .Test_en_N_out ( SYNOPSYS_UNCONNECTED_5036 ) , .pReset_S_in ( SYNOPSYS_UNCONNECTED_5037 ) , .pReset_E_in ( SYNOPSYS_UNCONNECTED_5038 ) , .pReset_W_in ( pResetWires[442] ) , .pReset_N_out ( pResetWires[444] ) , .pReset_W_out ( SYNOPSYS_UNCONNECTED_5039 ) , - .pReset_E_out ( pResetWires[445] ) , .Reset_S_in ( p1891 ) , + .pReset_E_out ( pResetWires[445] ) , .Reset_S_in ( p1910 ) , .Reset_N_out ( SYNOPSYS_UNCONNECTED_5040 ) , - .prog_clk_0_N_in ( prog_clk_0_wires[393] ) , .prog_clk_1_N_in ( p2113 ) , - .prog_clk_1_S_in ( p309 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[393] ) , .prog_clk_1_N_in ( p1638 ) , + .prog_clk_1_S_in ( p1661 ) , .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_5041 ) , .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_5042 ) , .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_5043 ) , @@ -114676,8 +119198,8 @@ sb_1__1_ sb_10__8_ ( .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5052 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5053 ) , .prog_clk_3_N_out ( prog_clk_3_wires[80] ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_5054 ) , .clk_1_N_in ( p2113 ) , - .clk_1_S_in ( p1687 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_5055 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_5054 ) , .clk_1_N_in ( p1638 ) , + .clk_1_S_in ( p755 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_5055 ) , .clk_1_W_out ( SYNOPSYS_UNCONNECTED_5056 ) , .clk_2_N_in ( SYNOPSYS_UNCONNECTED_5057 ) , .clk_2_E_in ( SYNOPSYS_UNCONNECTED_5058 ) , @@ -114738,20 +119260,20 @@ sb_1__1_ sb_10__9_ ( .chanx_right_out ( sb_1__1__107_chanx_right_out ) , .chany_bottom_out ( sb_1__1__107_chany_bottom_out ) , .chanx_left_out ( sb_1__1__107_chanx_left_out ) , - .ccff_tail ( sb_1__1__107_ccff_tail ) , .Test_en_S_in ( p2710 ) , + .ccff_tail ( sb_1__1__107_ccff_tail ) , .Test_en_S_in ( p1842 ) , .Test_en_N_out ( SYNOPSYS_UNCONNECTED_5070 ) , .pReset_S_in ( SYNOPSYS_UNCONNECTED_5071 ) , .pReset_E_in ( SYNOPSYS_UNCONNECTED_5072 ) , .pReset_W_in ( pResetWires[491] ) , .pReset_N_out ( pResetWires[493] ) , .pReset_W_out ( SYNOPSYS_UNCONNECTED_5073 ) , - .pReset_E_out ( pResetWires[494] ) , .Reset_S_in ( p2676 ) , + .pReset_E_out ( pResetWires[494] ) , .Reset_S_in ( p1842 ) , .Reset_N_out ( SYNOPSYS_UNCONNECTED_5074 ) , - .prog_clk_0_N_in ( prog_clk_0_wires[396] ) , .prog_clk_1_N_in ( p1470 ) , - .prog_clk_1_S_in ( p167 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[396] ) , .prog_clk_1_N_in ( p1471 ) , + .prog_clk_1_S_in ( p725 ) , .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_5075 ) , .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_5076 ) , - .prog_clk_2_N_in ( p1843 ) , .prog_clk_2_E_in ( p553 ) , - .prog_clk_2_S_in ( p1657 ) , .prog_clk_2_W_in ( p36 ) , + .prog_clk_2_N_in ( p2941 ) , .prog_clk_2_E_in ( p490 ) , + .prog_clk_2_S_in ( p1774 ) , .prog_clk_2_W_in ( p638 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5077 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_5078 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_5079 ) , @@ -114763,10 +119285,10 @@ sb_1__1_ sb_10__9_ ( .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5084 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5085 ) , .prog_clk_3_N_out ( prog_clk_3_wires[84] ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_5086 ) , .clk_1_N_in ( p1470 ) , - .clk_1_S_in ( p756 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_5087 ) , - .clk_1_W_out ( SYNOPSYS_UNCONNECTED_5088 ) , .clk_2_N_in ( p1925 ) , - .clk_2_E_in ( p333 ) , .clk_2_S_in ( p2543 ) , .clk_2_W_in ( p1134 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_5086 ) , .clk_1_N_in ( p1471 ) , + .clk_1_S_in ( p259 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_5087 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_5088 ) , .clk_2_N_in ( p2211 ) , + .clk_2_E_in ( p380 ) , .clk_2_S_in ( p1681 ) , .clk_2_W_in ( p176 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5089 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_5090 ) , .clk_2_N_out ( SYNOPSYS_UNCONNECTED_5091 ) , @@ -114822,16 +119344,16 @@ sb_1__1_ sb_10__10_ ( .chanx_right_out ( sb_1__1__108_chanx_right_out ) , .chany_bottom_out ( sb_1__1__108_chany_bottom_out ) , .chanx_left_out ( sb_1__1__108_chanx_left_out ) , - .ccff_tail ( sb_1__1__108_ccff_tail ) , .Test_en_S_in ( p2821 ) , + .ccff_tail ( sb_1__1__108_ccff_tail ) , .Test_en_S_in ( p1428 ) , .Test_en_N_out ( SYNOPSYS_UNCONNECTED_5100 ) , .pReset_S_in ( SYNOPSYS_UNCONNECTED_5101 ) , .pReset_E_in ( SYNOPSYS_UNCONNECTED_5102 ) , .pReset_W_in ( pResetWires[540] ) , .pReset_N_out ( pResetWires[542] ) , .pReset_W_out ( SYNOPSYS_UNCONNECTED_5103 ) , - .pReset_E_out ( pResetWires[543] ) , .Reset_S_in ( p2821 ) , + .pReset_E_out ( pResetWires[543] ) , .Reset_S_in ( p1428 ) , .Reset_N_out ( SYNOPSYS_UNCONNECTED_5104 ) , - .prog_clk_0_N_in ( prog_clk_0_wires[399] ) , .prog_clk_1_N_in ( p1471 ) , - .prog_clk_1_S_in ( p67 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[399] ) , .prog_clk_1_N_in ( p1885 ) , + .prog_clk_1_S_in ( p71 ) , .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_5105 ) , .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_5106 ) , .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_5107 ) , @@ -114841,14 +119363,14 @@ sb_1__1_ sb_10__10_ ( .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5110 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_5111 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_5112 ) , - .prog_clk_2_E_out ( prog_clk_2_wires[133] ) , .prog_clk_3_W_in ( p1579 ) , - .prog_clk_3_E_in ( p1155 ) , .prog_clk_3_S_in ( p1994 ) , - .prog_clk_3_N_in ( p40 ) , + .prog_clk_2_E_out ( prog_clk_2_wires[133] ) , .prog_clk_3_W_in ( p1287 ) , + .prog_clk_3_E_in ( p1026 ) , .prog_clk_3_S_in ( p418 ) , + .prog_clk_3_N_in ( p38 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5113 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5114 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_5115 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_5116 ) , .clk_1_N_in ( p1471 ) , - .clk_1_S_in ( p1004 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_5117 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_5116 ) , .clk_1_N_in ( p1885 ) , + .clk_1_S_in ( p1216 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_5117 ) , .clk_1_W_out ( SYNOPSYS_UNCONNECTED_5118 ) , .clk_2_N_in ( SYNOPSYS_UNCONNECTED_5119 ) , .clk_2_E_in ( SYNOPSYS_UNCONNECTED_5120 ) , @@ -114857,8 +119379,8 @@ sb_1__1_ sb_10__10_ ( .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5122 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_5123 ) , .clk_2_N_out ( SYNOPSYS_UNCONNECTED_5124 ) , - .clk_2_E_out ( clk_2_wires[133] ) , .clk_3_W_in ( p1579 ) , - .clk_3_E_in ( p1659 ) , .clk_3_S_in ( p2748 ) , .clk_3_N_in ( p730 ) , + .clk_2_E_out ( clk_2_wires[133] ) , .clk_3_W_in ( p1287 ) , + .clk_3_E_in ( p329 ) , .clk_3_S_in ( p701 ) , .clk_3_N_in ( p1749 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5125 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5126 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_5127 ) , @@ -114906,38 +119428,38 @@ sb_1__1_ sb_10__11_ ( .chanx_right_out ( sb_1__1__109_chanx_right_out ) , .chany_bottom_out ( sb_1__1__109_chany_bottom_out ) , .chanx_left_out ( sb_1__1__109_chanx_left_out ) , - .ccff_tail ( sb_1__1__109_ccff_tail ) , .Test_en_S_in ( p1845 ) , + .ccff_tail ( sb_1__1__109_ccff_tail ) , .Test_en_S_in ( p1995 ) , .Test_en_N_out ( SYNOPSYS_UNCONNECTED_5130 ) , .pReset_S_in ( SYNOPSYS_UNCONNECTED_5131 ) , .pReset_E_in ( SYNOPSYS_UNCONNECTED_5132 ) , .pReset_W_in ( pResetWires[589] ) , .pReset_N_out ( pResetWires[591] ) , .pReset_W_out ( SYNOPSYS_UNCONNECTED_5133 ) , - .pReset_E_out ( pResetWires[592] ) , .Reset_S_in ( p3093 ) , + .pReset_E_out ( pResetWires[592] ) , .Reset_S_in ( p1995 ) , .Reset_N_out ( SYNOPSYS_UNCONNECTED_5134 ) , - .prog_clk_0_N_in ( prog_clk_0_wires[402] ) , .prog_clk_1_N_in ( p1915 ) , - .prog_clk_1_S_in ( p641 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[402] ) , .prog_clk_1_N_in ( p2036 ) , + .prog_clk_1_S_in ( p64 ) , .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_5135 ) , .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_5136 ) , - .prog_clk_2_N_in ( p3320 ) , .prog_clk_2_E_in ( p80 ) , - .prog_clk_2_S_in ( p1356 ) , .prog_clk_2_W_in ( p151 ) , + .prog_clk_2_N_in ( p3471 ) , .prog_clk_2_E_in ( p434 ) , + .prog_clk_2_S_in ( p989 ) , .prog_clk_2_W_in ( p928 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5137 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_5138 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_5139 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5140 ) , - .prog_clk_3_W_in ( p2614 ) , .prog_clk_3_E_in ( p1345 ) , - .prog_clk_3_S_in ( p691 ) , .prog_clk_3_N_in ( p3284 ) , + .prog_clk_3_W_in ( p1615 ) , .prog_clk_3_E_in ( p700 ) , + .prog_clk_3_S_in ( p628 ) , .prog_clk_3_N_in ( p3441 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5141 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5142 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_5143 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_5144 ) , .clk_1_N_in ( p1915 ) , - .clk_1_S_in ( p1057 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_5145 ) , - .clk_1_W_out ( SYNOPSYS_UNCONNECTED_5146 ) , .clk_2_N_in ( p3159 ) , - .clk_2_E_in ( p767 ) , .clk_2_S_in ( p3035 ) , .clk_2_W_in ( p2551 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_5144 ) , .clk_1_N_in ( p2036 ) , + .clk_1_S_in ( p1112 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_5145 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_5146 ) , .clk_2_N_in ( p3334 ) , + .clk_2_E_in ( p67 ) , .clk_2_S_in ( p1218 ) , .clk_2_W_in ( p2682 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5147 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_5148 ) , .clk_2_N_out ( SYNOPSYS_UNCONNECTED_5149 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5150 ) , .clk_3_W_in ( p2614 ) , - .clk_3_E_in ( p623 ) , .clk_3_S_in ( p1321 ) , .clk_3_N_in ( p3123 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5150 ) , .clk_3_W_in ( p2779 ) , + .clk_3_E_in ( p1139 ) , .clk_3_S_in ( p1726 ) , .clk_3_N_in ( p3315 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5151 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5152 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_5153 ) , @@ -114985,27 +119507,27 @@ sb_1__1_ sb_11__1_ ( .chanx_right_out ( sb_1__1__110_chanx_right_out ) , .chany_bottom_out ( sb_1__1__110_chany_bottom_out ) , .chanx_left_out ( sb_1__1__110_chanx_left_out ) , - .ccff_tail ( sb_1__1__110_ccff_tail ) , .Test_en_S_in ( p2635 ) , + .ccff_tail ( sb_1__1__110_ccff_tail ) , .Test_en_S_in ( p2570 ) , .Test_en_N_out ( SYNOPSYS_UNCONNECTED_5156 ) , .pReset_S_in ( SYNOPSYS_UNCONNECTED_5157 ) , .pReset_E_in ( SYNOPSYS_UNCONNECTED_5158 ) , .pReset_W_in ( pResetWires[103] ) , .pReset_N_out ( pResetWires[105] ) , .pReset_W_out ( SYNOPSYS_UNCONNECTED_5159 ) , - .pReset_E_out ( pResetWires[106] ) , .Reset_S_in ( p3427 ) , + .pReset_E_out ( pResetWires[106] ) , .Reset_S_in ( p2570 ) , .Reset_N_out ( SYNOPSYS_UNCONNECTED_5160 ) , .prog_clk_0_N_in ( prog_clk_0_wires[410] ) , .prog_clk_1_N_in ( prog_clk_2_wires[116] ) , .prog_clk_1_S_in ( SYNOPSYS_UNCONNECTED_5161 ) , .prog_clk_1_E_out ( prog_clk_1_wires[211] ) , - .prog_clk_1_W_out ( prog_clk_1_wires[212] ) , .prog_clk_2_N_in ( p3401 ) , - .prog_clk_2_E_in ( p64 ) , .prog_clk_2_S_in ( p292 ) , - .prog_clk_2_W_in ( p1149 ) , + .prog_clk_1_W_out ( prog_clk_1_wires[212] ) , .prog_clk_2_N_in ( p3586 ) , + .prog_clk_2_E_in ( p401 ) , .prog_clk_2_S_in ( p1173 ) , + .prog_clk_2_W_in ( p836 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5162 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_5163 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_5164 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5165 ) , - .prog_clk_3_W_in ( p2992 ) , .prog_clk_3_E_in ( p1248 ) , - .prog_clk_3_S_in ( p544 ) , .prog_clk_3_N_in ( p3378 ) , + .prog_clk_3_W_in ( p2598 ) , .prog_clk_3_E_in ( p747 ) , + .prog_clk_3_S_in ( p63 ) , .prog_clk_3_N_in ( p3581 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5166 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5167 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_5168 ) , @@ -115013,12 +119535,12 @@ sb_1__1_ sb_11__1_ ( .clk_1_N_in ( clk_2_wires[116] ) , .clk_1_S_in ( SYNOPSYS_UNCONNECTED_5170 ) , .clk_1_E_out ( clk_1_wires[211] ) , .clk_1_W_out ( clk_1_wires[212] ) , - .clk_2_N_in ( p1544 ) , .clk_2_E_in ( p978 ) , .clk_2_S_in ( p3412 ) , - .clk_2_W_in ( p2889 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5171 ) , + .clk_2_N_in ( p3465 ) , .clk_2_E_in ( p5 ) , .clk_2_S_in ( p1067 ) , + .clk_2_W_in ( p3583 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5171 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_5172 ) , .clk_2_N_out ( SYNOPSYS_UNCONNECTED_5173 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5174 ) , .clk_3_W_in ( p2992 ) , - .clk_3_E_in ( p1071 ) , .clk_3_S_in ( p209 ) , .clk_3_N_in ( p312 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5174 ) , .clk_3_W_in ( p3587 ) , + .clk_3_E_in ( p849 ) , .clk_3_S_in ( p2388 ) , .clk_3_N_in ( p3437 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5175 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5176 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_5177 ) , @@ -115066,16 +119588,16 @@ sb_1__1_ sb_11__2_ ( .chanx_right_out ( sb_1__1__111_chanx_right_out ) , .chany_bottom_out ( sb_1__1__111_chany_bottom_out ) , .chanx_left_out ( sb_1__1__111_chanx_left_out ) , - .ccff_tail ( sb_1__1__111_ccff_tail ) , .Test_en_S_in ( p2112 ) , + .ccff_tail ( sb_1__1__111_ccff_tail ) , .Test_en_S_in ( p2354 ) , .Test_en_N_out ( SYNOPSYS_UNCONNECTED_5180 ) , .pReset_S_in ( SYNOPSYS_UNCONNECTED_5181 ) , .pReset_E_in ( SYNOPSYS_UNCONNECTED_5182 ) , .pReset_W_in ( pResetWires[152] ) , .pReset_N_out ( pResetWires[154] ) , .pReset_W_out ( SYNOPSYS_UNCONNECTED_5183 ) , - .pReset_E_out ( pResetWires[155] ) , .Reset_S_in ( p2112 ) , + .pReset_E_out ( pResetWires[155] ) , .Reset_S_in ( p2354 ) , .Reset_N_out ( SYNOPSYS_UNCONNECTED_5184 ) , - .prog_clk_0_N_in ( prog_clk_0_wires[413] ) , .prog_clk_1_N_in ( p1506 ) , - .prog_clk_1_S_in ( p352 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[413] ) , .prog_clk_1_N_in ( p1978 ) , + .prog_clk_1_S_in ( p940 ) , .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_5185 ) , .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_5186 ) , .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_5187 ) , @@ -115086,13 +119608,13 @@ sb_1__1_ sb_11__2_ ( .prog_clk_2_S_out ( prog_clk_2_wires[115] ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_5191 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5192 ) , - .prog_clk_3_W_in ( p1859 ) , .prog_clk_3_E_in ( p857 ) , - .prog_clk_3_S_in ( p302 ) , .prog_clk_3_N_in ( p408 ) , + .prog_clk_3_W_in ( p1999 ) , .prog_clk_3_E_in ( p70 ) , + .prog_clk_3_S_in ( p673 ) , .prog_clk_3_N_in ( p156 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5193 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5194 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_5195 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_5196 ) , .clk_1_N_in ( p1506 ) , - .clk_1_S_in ( p1017 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_5197 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_5196 ) , .clk_1_N_in ( p1978 ) , + .clk_1_S_in ( p229 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_5197 ) , .clk_1_W_out ( SYNOPSYS_UNCONNECTED_5198 ) , .clk_2_N_in ( SYNOPSYS_UNCONNECTED_5199 ) , .clk_2_E_in ( SYNOPSYS_UNCONNECTED_5200 ) , @@ -115101,8 +119623,8 @@ sb_1__1_ sb_11__2_ ( .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5202 ) , .clk_2_S_out ( clk_2_wires[115] ) , .clk_2_N_out ( SYNOPSYS_UNCONNECTED_5203 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5204 ) , .clk_3_W_in ( p1859 ) , - .clk_3_E_in ( p356 ) , .clk_3_S_in ( p1983 ) , .clk_3_N_in ( p143 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5204 ) , .clk_3_W_in ( p1999 ) , + .clk_3_E_in ( p882 ) , .clk_3_S_in ( p2088 ) , .clk_3_N_in ( p1763 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5205 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5206 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_5207 ) , @@ -115150,27 +119672,27 @@ sb_1__1_ sb_11__3_ ( .chanx_right_out ( sb_1__1__112_chanx_right_out ) , .chany_bottom_out ( sb_1__1__112_chany_bottom_out ) , .chanx_left_out ( sb_1__1__112_chanx_left_out ) , - .ccff_tail ( sb_1__1__112_ccff_tail ) , .Test_en_S_in ( p2410 ) , + .ccff_tail ( sb_1__1__112_ccff_tail ) , .Test_en_S_in ( p1858 ) , .Test_en_N_out ( SYNOPSYS_UNCONNECTED_5210 ) , .pReset_S_in ( SYNOPSYS_UNCONNECTED_5211 ) , .pReset_E_in ( SYNOPSYS_UNCONNECTED_5212 ) , .pReset_W_in ( pResetWires[201] ) , .pReset_N_out ( pResetWires[203] ) , .pReset_W_out ( SYNOPSYS_UNCONNECTED_5213 ) , - .pReset_E_out ( pResetWires[204] ) , .Reset_S_in ( p3199 ) , + .pReset_E_out ( pResetWires[204] ) , .Reset_S_in ( p1858 ) , .Reset_N_out ( SYNOPSYS_UNCONNECTED_5214 ) , .prog_clk_0_N_in ( prog_clk_0_wires[416] ) , .prog_clk_1_N_in ( prog_clk_2_wires[123] ) , .prog_clk_1_S_in ( SYNOPSYS_UNCONNECTED_5215 ) , .prog_clk_1_E_out ( prog_clk_1_wires[218] ) , - .prog_clk_1_W_out ( prog_clk_1_wires[219] ) , .prog_clk_2_N_in ( p3270 ) , - .prog_clk_2_E_in ( p895 ) , .prog_clk_2_S_in ( p1211 ) , - .prog_clk_2_W_in ( p4 ) , + .prog_clk_1_W_out ( prog_clk_1_wires[219] ) , .prog_clk_2_N_in ( p3588 ) , + .prog_clk_2_E_in ( p907 ) , .prog_clk_2_S_in ( p866 ) , + .prog_clk_2_W_in ( p254 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5216 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_5217 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_5218 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5219 ) , - .prog_clk_3_W_in ( p2853 ) , .prog_clk_3_E_in ( p71 ) , - .prog_clk_3_S_in ( p246 ) , .prog_clk_3_N_in ( p3219 ) , + .prog_clk_3_W_in ( p3151 ) , .prog_clk_3_E_in ( p664 ) , + .prog_clk_3_S_in ( p1385 ) , .prog_clk_3_N_in ( p3579 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5220 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5221 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_5222 ) , @@ -115178,12 +119700,12 @@ sb_1__1_ sb_11__3_ ( .clk_1_N_in ( clk_2_wires[123] ) , .clk_1_S_in ( SYNOPSYS_UNCONNECTED_5224 ) , .clk_1_E_out ( clk_1_wires[218] ) , .clk_1_W_out ( clk_1_wires[219] ) , - .clk_2_N_in ( p3202 ) , .clk_2_E_in ( p947 ) , .clk_2_S_in ( p3121 ) , - .clk_2_W_in ( p2719 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5225 ) , + .clk_2_N_in ( p3595 ) , .clk_2_E_in ( p1241 ) , .clk_2_S_in ( p535 ) , + .clk_2_W_in ( p3064 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5225 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_5226 ) , .clk_2_N_out ( SYNOPSYS_UNCONNECTED_5227 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5228 ) , .clk_3_W_in ( p2853 ) , - .clk_3_E_in ( p723 ) , .clk_3_S_in ( p943 ) , .clk_3_N_in ( p3128 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5228 ) , .clk_3_W_in ( p3135 ) , + .clk_3_E_in ( p138 ) , .clk_3_S_in ( p1706 ) , .clk_3_N_in ( p3592 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5229 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5230 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_5231 ) , @@ -115231,16 +119753,16 @@ sb_1__1_ sb_11__4_ ( .chanx_right_out ( sb_1__1__113_chanx_right_out ) , .chany_bottom_out ( sb_1__1__113_chany_bottom_out ) , .chanx_left_out ( sb_1__1__113_chanx_left_out ) , - .ccff_tail ( sb_1__1__113_ccff_tail ) , .Test_en_S_in ( p2424 ) , + .ccff_tail ( sb_1__1__113_ccff_tail ) , .Test_en_S_in ( p2834 ) , .Test_en_N_out ( SYNOPSYS_UNCONNECTED_5234 ) , .pReset_S_in ( SYNOPSYS_UNCONNECTED_5235 ) , .pReset_E_in ( SYNOPSYS_UNCONNECTED_5236 ) , .pReset_W_in ( pResetWires[250] ) , .pReset_N_out ( pResetWires[252] ) , .pReset_W_out ( SYNOPSYS_UNCONNECTED_5237 ) , - .pReset_E_out ( pResetWires[253] ) , .Reset_S_in ( p2424 ) , + .pReset_E_out ( pResetWires[253] ) , .Reset_S_in ( p2834 ) , .Reset_N_out ( SYNOPSYS_UNCONNECTED_5238 ) , - .prog_clk_0_N_in ( prog_clk_0_wires[419] ) , .prog_clk_1_N_in ( p1567 ) , - .prog_clk_1_S_in ( p441 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[419] ) , .prog_clk_1_N_in ( p1459 ) , + .prog_clk_1_S_in ( p1122 ) , .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_5239 ) , .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_5240 ) , .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_5241 ) , @@ -115251,13 +119773,13 @@ sb_1__1_ sb_11__4_ ( .prog_clk_2_S_out ( prog_clk_2_wires[122] ) , .prog_clk_2_N_out ( prog_clk_2_wires[120] ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5245 ) , - .prog_clk_3_W_in ( p2426 ) , .prog_clk_3_E_in ( p764 ) , - .prog_clk_3_S_in ( p514 ) , .prog_clk_3_N_in ( p546 ) , + .prog_clk_3_W_in ( p2559 ) , .prog_clk_3_E_in ( p216 ) , + .prog_clk_3_S_in ( p918 ) , .prog_clk_3_N_in ( p777 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5246 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5247 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_5248 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_5249 ) , .clk_1_N_in ( p1567 ) , - .clk_1_S_in ( p617 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_5250 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_5249 ) , .clk_1_N_in ( p1459 ) , + .clk_1_S_in ( p73 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_5250 ) , .clk_1_W_out ( SYNOPSYS_UNCONNECTED_5251 ) , .clk_2_N_in ( SYNOPSYS_UNCONNECTED_5252 ) , .clk_2_E_in ( SYNOPSYS_UNCONNECTED_5253 ) , @@ -115265,8 +119787,8 @@ sb_1__1_ sb_11__4_ ( .clk_2_W_in ( clk_2_wires[118] ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5255 ) , .clk_2_S_out ( clk_2_wires[122] ) , .clk_2_N_out ( clk_2_wires[120] ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5256 ) , .clk_3_W_in ( p2426 ) , - .clk_3_E_in ( p248 ) , .clk_3_S_in ( p2289 ) , .clk_3_N_in ( p255 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5256 ) , .clk_3_W_in ( p2559 ) , + .clk_3_E_in ( p1048 ) , .clk_3_S_in ( p2669 ) , .clk_3_N_in ( p350 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5257 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5258 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_5259 ) , @@ -115314,40 +119836,40 @@ sb_1__1_ sb_11__5_ ( .chanx_right_out ( sb_1__1__114_chanx_right_out ) , .chany_bottom_out ( sb_1__1__114_chany_bottom_out ) , .chanx_left_out ( sb_1__1__114_chanx_left_out ) , - .ccff_tail ( sb_1__1__114_ccff_tail ) , .Test_en_S_in ( p3321 ) , + .ccff_tail ( sb_1__1__114_ccff_tail ) , .Test_en_S_in ( p2267 ) , .Test_en_N_out ( SYNOPSYS_UNCONNECTED_5262 ) , .pReset_S_in ( SYNOPSYS_UNCONNECTED_5263 ) , .pReset_E_in ( SYNOPSYS_UNCONNECTED_5264 ) , .pReset_W_in ( pResetWires[299] ) , .pReset_N_out ( pResetWires[301] ) , .pReset_W_out ( SYNOPSYS_UNCONNECTED_5265 ) , - .pReset_E_out ( pResetWires[302] ) , .Reset_S_in ( p3428 ) , + .pReset_E_out ( pResetWires[302] ) , .Reset_S_in ( p2267 ) , .Reset_N_out ( SYNOPSYS_UNCONNECTED_5266 ) , .prog_clk_0_N_in ( prog_clk_0_wires[422] ) , .prog_clk_1_N_in ( SYNOPSYS_UNCONNECTED_5267 ) , .prog_clk_1_S_in ( prog_clk_2_wires[121] ) , .prog_clk_1_E_out ( prog_clk_1_wires[225] ) , - .prog_clk_1_W_out ( prog_clk_1_wires[226] ) , .prog_clk_2_N_in ( p2658 ) , - .prog_clk_2_E_in ( p1160 ) , .prog_clk_2_S_in ( p101 ) , - .prog_clk_2_W_in ( p1208 ) , + .prog_clk_1_W_out ( prog_clk_1_wires[226] ) , .prog_clk_2_N_in ( p2781 ) , + .prog_clk_2_E_in ( p690 ) , .prog_clk_2_S_in ( p1276 ) , + .prog_clk_2_W_in ( p754 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5268 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_5269 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_5270 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5271 ) , - .prog_clk_3_W_in ( p2922 ) , .prog_clk_3_E_in ( p780 ) , - .prog_clk_3_S_in ( p1412 ) , .prog_clk_3_N_in ( p2575 ) , + .prog_clk_3_W_in ( p2996 ) , .prog_clk_3_E_in ( p1003 ) , + .prog_clk_3_S_in ( p175 ) , .prog_clk_3_N_in ( p2718 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5272 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5273 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_5274 ) , .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_5275 ) , .clk_1_N_in ( SYNOPSYS_UNCONNECTED_5276 ) , .clk_1_S_in ( clk_2_wires[121] ) , .clk_1_E_out ( clk_1_wires[225] ) , - .clk_1_W_out ( clk_1_wires[226] ) , .clk_2_N_in ( p3313 ) , - .clk_2_E_in ( p166 ) , .clk_2_S_in ( p3417 ) , .clk_2_W_in ( p2866 ) , + .clk_1_W_out ( clk_1_wires[226] ) , .clk_2_N_in ( p3554 ) , + .clk_2_E_in ( p840 ) , .clk_2_S_in ( p1260 ) , .clk_2_W_in ( p3568 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5277 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_5278 ) , .clk_2_N_out ( SYNOPSYS_UNCONNECTED_5279 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5280 ) , .clk_3_W_in ( p2922 ) , - .clk_3_E_in ( p584 ) , .clk_3_S_in ( p941 ) , .clk_3_N_in ( p3294 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5280 ) , .clk_3_W_in ( p3578 ) , + .clk_3_E_in ( p105 ) , .clk_3_S_in ( p2069 ) , .clk_3_N_in ( p3543 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5281 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5282 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_5283 ) , @@ -115395,38 +119917,38 @@ sb_1__1_ sb_11__6_ ( .chanx_right_out ( sb_1__1__115_chanx_right_out ) , .chany_bottom_out ( sb_1__1__115_chany_bottom_out ) , .chanx_left_out ( sb_1__1__115_chanx_left_out ) , - .ccff_tail ( sb_1__1__115_ccff_tail ) , .Test_en_S_in ( p2924 ) , + .ccff_tail ( sb_1__1__115_ccff_tail ) , .Test_en_S_in ( p2051 ) , .Test_en_N_out ( SYNOPSYS_UNCONNECTED_5286 ) , .pReset_S_in ( SYNOPSYS_UNCONNECTED_5287 ) , .pReset_E_in ( SYNOPSYS_UNCONNECTED_5288 ) , .pReset_W_in ( pResetWires[348] ) , .pReset_N_out ( pResetWires[350] ) , .pReset_W_out ( SYNOPSYS_UNCONNECTED_5289 ) , - .pReset_E_out ( pResetWires[351] ) , .Reset_S_in ( p2924 ) , + .pReset_E_out ( pResetWires[351] ) , .Reset_S_in ( p2051 ) , .Reset_N_out ( SYNOPSYS_UNCONNECTED_5290 ) , - .prog_clk_0_N_in ( prog_clk_0_wires[425] ) , .prog_clk_1_N_in ( p1136 ) , - .prog_clk_1_S_in ( p1043 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[425] ) , .prog_clk_1_N_in ( p1621 ) , + .prog_clk_1_S_in ( p411 ) , .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_5291 ) , .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_5292 ) , - .prog_clk_2_N_in ( p3374 ) , .prog_clk_2_E_in ( p1013 ) , - .prog_clk_2_S_in ( p213 ) , .prog_clk_2_W_in ( p938 ) , + .prog_clk_2_N_in ( p3464 ) , .prog_clk_2_E_in ( p249 ) , + .prog_clk_2_S_in ( p1158 ) , .prog_clk_2_W_in ( p1064 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5293 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_5294 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_5295 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5296 ) , - .prog_clk_3_W_in ( p2416 ) , .prog_clk_3_E_in ( p305 ) , - .prog_clk_3_S_in ( p1398 ) , .prog_clk_3_N_in ( p3333 ) , + .prog_clk_3_W_in ( p2521 ) , .prog_clk_3_E_in ( p554 ) , + .prog_clk_3_S_in ( p527 ) , .prog_clk_3_N_in ( p3429 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5297 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5298 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_5299 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_5300 ) , .clk_1_N_in ( p1136 ) , - .clk_1_S_in ( p505 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_5301 ) , - .clk_1_W_out ( SYNOPSYS_UNCONNECTED_5302 ) , .clk_2_N_in ( p3058 ) , - .clk_2_E_in ( p991 ) , .clk_2_S_in ( p2902 ) , .clk_2_W_in ( p2281 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_5300 ) , .clk_1_N_in ( p1621 ) , + .clk_1_S_in ( p1147 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_5301 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_5302 ) , .clk_2_N_in ( p3596 ) , + .clk_2_E_in ( p122 ) , .clk_2_S_in ( p1288 ) , .clk_2_W_in ( p3032 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5303 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_5304 ) , .clk_2_N_out ( SYNOPSYS_UNCONNECTED_5305 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5306 ) , .clk_3_W_in ( p2416 ) , - .clk_3_E_in ( p854 ) , .clk_3_S_in ( p1290 ) , .clk_3_N_in ( p3036 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5306 ) , .clk_3_W_in ( p3140 ) , + .clk_3_E_in ( p1108 ) , .clk_3_S_in ( p1771 ) , .clk_3_N_in ( p3594 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5307 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5308 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_5309 ) , @@ -115474,27 +119996,27 @@ sb_1__1_ sb_11__7_ ( .chanx_right_out ( sb_1__1__116_chanx_right_out ) , .chany_bottom_out ( sb_1__1__116_chany_bottom_out ) , .chanx_left_out ( sb_1__1__116_chanx_left_out ) , - .ccff_tail ( sb_1__1__116_ccff_tail ) , .Test_en_S_in ( p2988 ) , + .ccff_tail ( sb_1__1__116_ccff_tail ) , .Test_en_S_in ( p2617 ) , .Test_en_N_out ( SYNOPSYS_UNCONNECTED_5312 ) , .pReset_S_in ( SYNOPSYS_UNCONNECTED_5313 ) , .pReset_E_in ( SYNOPSYS_UNCONNECTED_5314 ) , .pReset_W_in ( pResetWires[397] ) , .pReset_N_out ( pResetWires[399] ) , .pReset_W_out ( SYNOPSYS_UNCONNECTED_5315 ) , - .pReset_E_out ( pResetWires[400] ) , .Reset_S_in ( p2988 ) , + .pReset_E_out ( pResetWires[400] ) , .Reset_S_in ( p2617 ) , .Reset_N_out ( SYNOPSYS_UNCONNECTED_5316 ) , .prog_clk_0_N_in ( prog_clk_0_wires[428] ) , .prog_clk_1_N_in ( prog_clk_2_wires[130] ) , .prog_clk_1_S_in ( SYNOPSYS_UNCONNECTED_5317 ) , .prog_clk_1_E_out ( prog_clk_1_wires[232] ) , - .prog_clk_1_W_out ( prog_clk_1_wires[233] ) , .prog_clk_2_N_in ( p3436 ) , - .prog_clk_2_E_in ( p1141 ) , .prog_clk_2_S_in ( p535 ) , - .prog_clk_2_W_in ( p1140 ) , + .prog_clk_1_W_out ( prog_clk_1_wires[233] ) , .prog_clk_2_N_in ( p3597 ) , + .prog_clk_2_E_in ( p248 ) , .prog_clk_2_S_in ( p708 ) , + .prog_clk_2_W_in ( p640 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5318 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_5319 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_5320 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5321 ) , - .prog_clk_3_W_in ( p2187 ) , .prog_clk_3_E_in ( p105 ) , - .prog_clk_3_S_in ( p1107 ) , .prog_clk_3_N_in ( p3415 ) , + .prog_clk_3_W_in ( p3321 ) , .prog_clk_3_E_in ( p477 ) , + .prog_clk_3_S_in ( p1071 ) , .prog_clk_3_N_in ( p3591 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5322 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5323 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_5324 ) , @@ -115502,12 +120024,12 @@ sb_1__1_ sb_11__7_ ( .clk_1_N_in ( clk_2_wires[130] ) , .clk_1_S_in ( SYNOPSYS_UNCONNECTED_5326 ) , .clk_1_E_out ( clk_1_wires[232] ) , .clk_1_W_out ( clk_1_wires[233] ) , - .clk_2_N_in ( p2164 ) , .clk_2_E_in ( p683 ) , .clk_2_S_in ( p2888 ) , - .clk_2_W_in ( p2016 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5327 ) , + .clk_2_N_in ( p1502 ) , .clk_2_E_in ( p312 ) , .clk_2_S_in ( p977 ) , + .clk_2_W_in ( p3304 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5327 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_5328 ) , .clk_2_N_out ( SYNOPSYS_UNCONNECTED_5329 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5330 ) , .clk_3_W_in ( p2187 ) , - .clk_3_E_in ( p659 ) , .clk_3_S_in ( p1377 ) , .clk_3_N_in ( p1970 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5330 ) , .clk_3_W_in ( p2759 ) , + .clk_3_E_in ( p975 ) , .clk_3_S_in ( p2411 ) , .clk_3_N_in ( p517 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5331 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5332 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_5333 ) , @@ -115555,16 +120077,16 @@ sb_1__1_ sb_11__8_ ( .chanx_right_out ( sb_1__1__117_chanx_right_out ) , .chany_bottom_out ( sb_1__1__117_chany_bottom_out ) , .chanx_left_out ( sb_1__1__117_chanx_left_out ) , - .ccff_tail ( sb_1__1__117_ccff_tail ) , .Test_en_S_in ( p2394 ) , + .ccff_tail ( sb_1__1__117_ccff_tail ) , .Test_en_S_in ( p1304 ) , .Test_en_N_out ( SYNOPSYS_UNCONNECTED_5336 ) , .pReset_S_in ( SYNOPSYS_UNCONNECTED_5337 ) , .pReset_E_in ( SYNOPSYS_UNCONNECTED_5338 ) , .pReset_W_in ( pResetWires[446] ) , .pReset_N_out ( pResetWires[448] ) , .pReset_W_out ( SYNOPSYS_UNCONNECTED_5339 ) , - .pReset_E_out ( pResetWires[449] ) , .Reset_S_in ( p2394 ) , + .pReset_E_out ( pResetWires[449] ) , .Reset_S_in ( p1304 ) , .Reset_N_out ( SYNOPSYS_UNCONNECTED_5340 ) , - .prog_clk_0_N_in ( prog_clk_0_wires[431] ) , .prog_clk_1_N_in ( p1795 ) , - .prog_clk_1_S_in ( p547 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[431] ) , .prog_clk_1_N_in ( p1945 ) , + .prog_clk_1_S_in ( p982 ) , .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_5341 ) , .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_5342 ) , .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_5343 ) , @@ -115575,13 +120097,13 @@ sb_1__1_ sb_11__8_ ( .prog_clk_2_S_out ( prog_clk_2_wires[129] ) , .prog_clk_2_N_out ( prog_clk_2_wires[127] ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5347 ) , - .prog_clk_3_W_in ( p2438 ) , .prog_clk_3_E_in ( p191 ) , - .prog_clk_3_S_in ( p823 ) , .prog_clk_3_N_in ( p1658 ) , + .prog_clk_3_W_in ( p2023 ) , .prog_clk_3_E_in ( p846 ) , + .prog_clk_3_S_in ( p723 ) , .prog_clk_3_N_in ( p1724 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5348 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5349 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_5350 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_5351 ) , .clk_1_N_in ( p1795 ) , - .clk_1_S_in ( p447 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_5352 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_5351 ) , .clk_1_N_in ( p1945 ) , + .clk_1_S_in ( p448 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_5352 ) , .clk_1_W_out ( SYNOPSYS_UNCONNECTED_5353 ) , .clk_2_N_in ( SYNOPSYS_UNCONNECTED_5354 ) , .clk_2_E_in ( SYNOPSYS_UNCONNECTED_5355 ) , @@ -115589,8 +120111,8 @@ sb_1__1_ sb_11__8_ ( .clk_2_W_in ( clk_2_wires[125] ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5357 ) , .clk_2_S_out ( clk_2_wires[129] ) , .clk_2_N_out ( clk_2_wires[127] ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5358 ) , .clk_3_W_in ( p2438 ) , - .clk_3_E_in ( p953 ) , .clk_3_S_in ( p2287 ) , .clk_3_N_in ( p1718 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5358 ) , .clk_3_W_in ( p2023 ) , + .clk_3_E_in ( p280 ) , .clk_3_S_in ( p555 ) , .clk_3_N_in ( p1665 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5359 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5360 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_5361 ) , @@ -115638,40 +120160,40 @@ sb_1__1_ sb_11__9_ ( .chanx_right_out ( sb_1__1__118_chanx_right_out ) , .chany_bottom_out ( sb_1__1__118_chany_bottom_out ) , .chanx_left_out ( sb_1__1__118_chanx_left_out ) , - .ccff_tail ( sb_1__1__118_ccff_tail ) , .Test_en_S_in ( p2397 ) , + .ccff_tail ( sb_1__1__118_ccff_tail ) , .Test_en_S_in ( p2037 ) , .Test_en_N_out ( SYNOPSYS_UNCONNECTED_5364 ) , .pReset_S_in ( SYNOPSYS_UNCONNECTED_5365 ) , .pReset_E_in ( SYNOPSYS_UNCONNECTED_5366 ) , .pReset_W_in ( pResetWires[495] ) , .pReset_N_out ( pResetWires[497] ) , .pReset_W_out ( SYNOPSYS_UNCONNECTED_5367 ) , - .pReset_E_out ( pResetWires[498] ) , .Reset_S_in ( p3089 ) , + .pReset_E_out ( pResetWires[498] ) , .Reset_S_in ( p2037 ) , .Reset_N_out ( SYNOPSYS_UNCONNECTED_5368 ) , .prog_clk_0_N_in ( prog_clk_0_wires[434] ) , .prog_clk_1_N_in ( SYNOPSYS_UNCONNECTED_5369 ) , .prog_clk_1_S_in ( prog_clk_2_wires[128] ) , .prog_clk_1_E_out ( prog_clk_1_wires[239] ) , - .prog_clk_1_W_out ( prog_clk_1_wires[240] ) , .prog_clk_2_N_in ( p3481 ) , - .prog_clk_2_E_in ( p1277 ) , .prog_clk_2_S_in ( p667 ) , - .prog_clk_2_W_in ( p82 ) , + .prog_clk_1_W_out ( prog_clk_1_wires[240] ) , .prog_clk_2_N_in ( p3273 ) , + .prog_clk_2_E_in ( p11 ) , .prog_clk_2_S_in ( p1210 ) , + .prog_clk_2_W_in ( p612 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5370 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_5371 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_5372 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5373 ) , - .prog_clk_3_W_in ( p2981 ) , .prog_clk_3_E_in ( p997 ) , - .prog_clk_3_S_in ( p1110 ) , .prog_clk_3_N_in ( p3475 ) , + .prog_clk_3_W_in ( p3349 ) , .prog_clk_3_E_in ( p550 ) , + .prog_clk_3_S_in ( p452 ) , .prog_clk_3_N_in ( p3173 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5374 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5375 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_5376 ) , .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_5377 ) , .clk_1_N_in ( SYNOPSYS_UNCONNECTED_5378 ) , .clk_1_S_in ( clk_2_wires[128] ) , .clk_1_E_out ( clk_1_wires[239] ) , - .clk_1_W_out ( clk_1_wires[240] ) , .clk_2_N_in ( p2835 ) , - .clk_2_E_in ( p484 ) , .clk_2_S_in ( p3020 ) , .clk_2_W_in ( p2899 ) , + .clk_1_W_out ( clk_1_wires[240] ) , .clk_2_N_in ( p3561 ) , + .clk_2_E_in ( p245 ) , .clk_2_S_in ( p1325 ) , .clk_2_W_in ( p3548 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5379 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_5380 ) , .clk_2_N_out ( SYNOPSYS_UNCONNECTED_5381 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5382 ) , .clk_3_W_in ( p2981 ) , - .clk_3_E_in ( p122 ) , .clk_3_S_in ( p419 ) , .clk_3_N_in ( p2735 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5382 ) , .clk_3_W_in ( p3562 ) , + .clk_3_E_in ( p1222 ) , .clk_3_S_in ( p1743 ) , .clk_3_N_in ( p3552 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5383 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5384 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_5385 ) , @@ -115719,16 +120241,16 @@ sb_1__1_ sb_11__10_ ( .chanx_right_out ( sb_1__1__119_chanx_right_out ) , .chany_bottom_out ( sb_1__1__119_chany_bottom_out ) , .chanx_left_out ( sb_1__1__119_chanx_left_out ) , - .ccff_tail ( sb_1__1__119_ccff_tail ) , .Test_en_S_in ( p3094 ) , + .ccff_tail ( sb_1__1__119_ccff_tail ) , .Test_en_S_in ( p2266 ) , .Test_en_N_out ( SYNOPSYS_UNCONNECTED_5388 ) , .pReset_S_in ( SYNOPSYS_UNCONNECTED_5389 ) , .pReset_E_in ( SYNOPSYS_UNCONNECTED_5390 ) , .pReset_W_in ( pResetWires[544] ) , .pReset_N_out ( pResetWires[546] ) , .pReset_W_out ( SYNOPSYS_UNCONNECTED_5391 ) , - .pReset_E_out ( pResetWires[547] ) , .Reset_S_in ( p3094 ) , + .pReset_E_out ( pResetWires[547] ) , .Reset_S_in ( p2266 ) , .Reset_N_out ( SYNOPSYS_UNCONNECTED_5392 ) , - .prog_clk_0_N_in ( prog_clk_0_wires[437] ) , .prog_clk_1_N_in ( p1586 ) , - .prog_clk_1_S_in ( p453 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[437] ) , .prog_clk_1_N_in ( p2258 ) , + .prog_clk_1_S_in ( p1204 ) , .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_5393 ) , .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_5394 ) , .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_5395 ) , @@ -115739,13 +120261,13 @@ sb_1__1_ sb_11__10_ ( .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_5399 ) , .prog_clk_2_N_out ( prog_clk_2_wires[134] ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5400 ) , - .prog_clk_3_W_in ( p1555 ) , .prog_clk_3_E_in ( p385 ) , - .prog_clk_3_S_in ( p172 ) , .prog_clk_3_N_in ( p878 ) , + .prog_clk_3_W_in ( p1957 ) , .prog_clk_3_E_in ( p51 ) , + .prog_clk_3_S_in ( p338 ) , .prog_clk_3_N_in ( p587 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5401 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5402 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_5403 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_5404 ) , .clk_1_N_in ( p1586 ) , - .clk_1_S_in ( p20 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_5405 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_5404 ) , .clk_1_N_in ( p2258 ) , + .clk_1_S_in ( p178 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_5405 ) , .clk_1_W_out ( SYNOPSYS_UNCONNECTED_5406 ) , .clk_2_N_in ( SYNOPSYS_UNCONNECTED_5407 ) , .clk_2_E_in ( SYNOPSYS_UNCONNECTED_5408 ) , @@ -115754,8 +120276,8 @@ sb_1__1_ sb_11__10_ ( .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5410 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_5411 ) , .clk_2_N_out ( clk_2_wires[134] ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5412 ) , .clk_3_W_in ( p1555 ) , - .clk_3_E_in ( p550 ) , .clk_3_S_in ( p3030 ) , .clk_3_N_in ( p336 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5412 ) , .clk_3_W_in ( p1957 ) , + .clk_3_E_in ( p514 ) , .clk_3_S_in ( p2120 ) , .clk_3_N_in ( p2070 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5413 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5414 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_5415 ) , @@ -115803,40 +120325,40 @@ sb_1__1_ sb_11__11_ ( .chanx_right_out ( sb_1__1__120_chanx_right_out ) , .chany_bottom_out ( sb_1__1__120_chany_bottom_out ) , .chanx_left_out ( sb_1__1__120_chanx_left_out ) , - .ccff_tail ( sb_1__1__120_ccff_tail ) , .Test_en_S_in ( p2803 ) , + .ccff_tail ( sb_1__1__120_ccff_tail ) , .Test_en_S_in ( p2224 ) , .Test_en_N_out ( SYNOPSYS_UNCONNECTED_5418 ) , .pReset_S_in ( SYNOPSYS_UNCONNECTED_5419 ) , .pReset_E_in ( SYNOPSYS_UNCONNECTED_5420 ) , .pReset_W_in ( pResetWires[593] ) , .pReset_N_out ( pResetWires[595] ) , .pReset_W_out ( SYNOPSYS_UNCONNECTED_5421 ) , - .pReset_E_out ( pResetWires[596] ) , .Reset_S_in ( p3054 ) , + .pReset_E_out ( pResetWires[596] ) , .Reset_S_in ( p2224 ) , .Reset_N_out ( SYNOPSYS_UNCONNECTED_5422 ) , .prog_clk_0_N_in ( prog_clk_0_wires[440] ) , .prog_clk_1_N_in ( SYNOPSYS_UNCONNECTED_5423 ) , .prog_clk_1_S_in ( prog_clk_2_wires[135] ) , .prog_clk_1_E_out ( prog_clk_1_wires[246] ) , - .prog_clk_1_W_out ( prog_clk_1_wires[247] ) , .prog_clk_2_N_in ( p3480 ) , - .prog_clk_2_E_in ( p68 ) , .prog_clk_2_S_in ( p363 ) , - .prog_clk_2_W_in ( p1050 ) , + .prog_clk_1_W_out ( prog_clk_1_wires[247] ) , .prog_clk_2_N_in ( p3164 ) , + .prog_clk_2_E_in ( p357 ) , .prog_clk_2_S_in ( p1036 ) , + .prog_clk_2_W_in ( p302 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5424 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_5425 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_5426 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5427 ) , - .prog_clk_3_W_in ( p2698 ) , .prog_clk_3_E_in ( p783 ) , - .prog_clk_3_S_in ( p1301 ) , .prog_clk_3_N_in ( p3472 ) , + .prog_clk_3_W_in ( p2981 ) , .prog_clk_3_E_in ( p265 ) , + .prog_clk_3_S_in ( p645 ) , .prog_clk_3_N_in ( p3062 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5428 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5429 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_5430 ) , .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_5431 ) , .clk_1_N_in ( SYNOPSYS_UNCONNECTED_5432 ) , .clk_1_S_in ( clk_2_wires[135] ) , .clk_1_E_out ( clk_1_wires[246] ) , - .clk_1_W_out ( clk_1_wires[247] ) , .clk_2_N_in ( p2964 ) , - .clk_2_E_in ( p1159 ) , .clk_2_S_in ( p3019 ) , .clk_2_W_in ( p2558 ) , + .clk_1_W_out ( clk_1_wires[247] ) , .clk_2_N_in ( p3002 ) , + .clk_2_E_in ( p1268 ) , .clk_2_S_in ( p1284 ) , .clk_2_W_in ( p3031 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5433 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_5434 ) , .clk_2_N_out ( SYNOPSYS_UNCONNECTED_5435 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5436 ) , .clk_3_W_in ( p2698 ) , - .clk_3_E_in ( p864 ) , .clk_3_S_in ( p690 ) , .clk_3_N_in ( p2911 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5436 ) , .clk_3_W_in ( p3120 ) , + .clk_3_E_in ( p522 ) , .clk_3_S_in ( p2058 ) , .clk_3_N_in ( p2865 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5437 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5438 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_5439 ) , @@ -115876,7 +120398,7 @@ sb_1__2_ sb_1__12_ ( .chanx_right_out ( sb_1__12__0_chanx_right_out ) , .chany_bottom_out ( sb_1__12__0_chany_bottom_out ) , .chanx_left_out ( sb_1__12__0_chanx_left_out ) , - .ccff_tail ( sb_1__12__0_ccff_tail ) , .SC_IN_BOT ( p1216 ) , + .ccff_tail ( sb_1__12__0_ccff_tail ) , .SC_IN_BOT ( p1338 ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_5442 ) , .pReset_S_in ( SYNOPSYS_UNCONNECTED_5443 ) , .pReset_E_in ( pResetWires[604] ) , @@ -115962,7 +120484,7 @@ sb_1__2_ sb_3__12_ ( .chanx_right_out ( sb_1__12__2_chanx_right_out ) , .chany_bottom_out ( sb_1__12__2_chany_bottom_out ) , .chanx_left_out ( sb_1__12__2_chanx_left_out ) , - .ccff_tail ( sb_1__12__2_ccff_tail ) , .SC_IN_BOT ( p1272 ) , + .ccff_tail ( sb_1__12__2_ccff_tail ) , .SC_IN_BOT ( p1257 ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_5451 ) , .pReset_S_in ( SYNOPSYS_UNCONNECTED_5452 ) , .pReset_E_in ( pResetWires[610] ) , @@ -116048,7 +120570,7 @@ sb_1__2_ sb_5__12_ ( .chanx_right_out ( sb_1__12__4_chanx_right_out ) , .chany_bottom_out ( sb_1__12__4_chany_bottom_out ) , .chanx_left_out ( sb_1__12__4_chanx_left_out ) , - .ccff_tail ( sb_1__12__4_ccff_tail ) , .SC_IN_BOT ( p1462 ) , + .ccff_tail ( sb_1__12__4_ccff_tail ) , .SC_IN_BOT ( p1412 ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_5460 ) , .pReset_S_in ( SYNOPSYS_UNCONNECTED_5461 ) , .pReset_E_in ( pResetWires[616] ) , @@ -116132,7 +120654,7 @@ sb_1__2_ sb_7__12_ ( .chanx_right_out ( sb_1__12__6_chanx_right_out ) , .chany_bottom_out ( sb_1__12__6_chany_bottom_out ) , .chanx_left_out ( sb_1__12__6_chanx_left_out ) , - .ccff_tail ( sb_1__12__6_ccff_tail ) , .SC_IN_BOT ( p1524 ) , + .ccff_tail ( sb_1__12__6_ccff_tail ) , .SC_IN_BOT ( p1384 ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_5468 ) , .pReset_S_in ( SYNOPSYS_UNCONNECTED_5469 ) , .pReset_E_in ( SYNOPSYS_UNCONNECTED_5470 ) , @@ -116218,7 +120740,7 @@ sb_1__2_ sb_9__12_ ( .chanx_right_out ( sb_1__12__8_chanx_right_out ) , .chany_bottom_out ( sb_1__12__8_chany_bottom_out ) , .chanx_left_out ( sb_1__12__8_chanx_left_out ) , - .ccff_tail ( sb_1__12__8_ccff_tail ) , .SC_IN_BOT ( p1396 ) , + .ccff_tail ( sb_1__12__8_ccff_tail ) , .SC_IN_BOT ( p1360 ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_5477 ) , .pReset_S_in ( SYNOPSYS_UNCONNECTED_5478 ) , .pReset_E_in ( SYNOPSYS_UNCONNECTED_5479 ) , @@ -116304,7 +120826,7 @@ sb_1__2_ sb_11__12_ ( .chanx_right_out ( sb_1__12__10_chanx_right_out ) , .chany_bottom_out ( sb_1__12__10_chany_bottom_out ) , .chanx_left_out ( sb_1__12__10_chanx_left_out ) , - .ccff_tail ( sb_1__12__10_ccff_tail ) , .SC_IN_BOT ( p1310 ) , + .ccff_tail ( sb_1__12__10_ccff_tail ) , .SC_IN_BOT ( p1480 ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_5486 ) , .pReset_S_in ( SYNOPSYS_UNCONNECTED_5487 ) , .pReset_E_in ( SYNOPSYS_UNCONNECTED_5488 ) , @@ -116834,7 +121356,7 @@ cbx_1__0_ cbx_1__0_ ( .top_width_0_height_0__pin_17_upper ( grid_io_bottom_11_top_width_0_height_0__pin_17_upper ) , .top_width_0_height_0__pin_17_lower ( grid_io_bottom_11_top_width_0_height_0__pin_17_lower ) , .SC_IN_TOP ( scff_Wires[25] ) , .SC_OUT_BOT ( scff_Wires[26] ) , - .SC_IN_BOT ( p1495 ) , .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_5504 ) , + .SC_IN_BOT ( p1011 ) , .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_5504 ) , .pReset_E_in ( pResetWires[26] ) , .pReset_W_in ( SYNOPSYS_UNCONNECTED_5505 ) , .pReset_W_out ( pResetWires[25] ) , @@ -116888,7 +121410,7 @@ cbx_1__0_ cbx_2__0_ ( .top_width_0_height_0__pin_15_lower ( grid_io_bottom_10_top_width_0_height_0__pin_15_lower ) , .top_width_0_height_0__pin_17_upper ( grid_io_bottom_10_top_width_0_height_0__pin_17_upper ) , .top_width_0_height_0__pin_17_lower ( grid_io_bottom_10_top_width_0_height_0__pin_17_lower ) , - .SC_IN_TOP ( p1229 ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_5508 ) , + .SC_IN_TOP ( p1608 ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_5508 ) , .SC_IN_BOT ( scff_Wires[27] ) , .SC_OUT_TOP ( scff_Wires[28] ) , .pReset_E_in ( pResetWires[29] ) , .pReset_W_in ( SYNOPSYS_UNCONNECTED_5509 ) , @@ -116944,7 +121466,7 @@ cbx_1__0_ cbx_3__0_ ( .top_width_0_height_0__pin_17_upper ( grid_io_bottom_9_top_width_0_height_0__pin_17_upper ) , .top_width_0_height_0__pin_17_lower ( grid_io_bottom_9_top_width_0_height_0__pin_17_lower ) , .SC_IN_TOP ( scff_Wires[78] ) , .SC_OUT_BOT ( scff_Wires[79] ) , - .SC_IN_BOT ( p1391 ) , .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_5513 ) , + .SC_IN_BOT ( p1622 ) , .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_5513 ) , .pReset_E_in ( pResetWires[32] ) , .pReset_W_in ( SYNOPSYS_UNCONNECTED_5514 ) , .pReset_W_out ( pResetWires[31] ) , @@ -116998,7 +121520,7 @@ cbx_1__0_ cbx_4__0_ ( .top_width_0_height_0__pin_15_lower ( grid_io_bottom_8_top_width_0_height_0__pin_15_lower ) , .top_width_0_height_0__pin_17_upper ( grid_io_bottom_8_top_width_0_height_0__pin_17_upper ) , .top_width_0_height_0__pin_17_lower ( grid_io_bottom_8_top_width_0_height_0__pin_17_lower ) , - .SC_IN_TOP ( p1395 ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_5518 ) , + .SC_IN_TOP ( p1309 ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_5518 ) , .SC_IN_BOT ( scff_Wires[80] ) , .SC_OUT_TOP ( scff_Wires[81] ) , .pReset_E_in ( pResetWires[35] ) , .pReset_W_in ( SYNOPSYS_UNCONNECTED_5519 ) , @@ -117054,7 +121576,7 @@ cbx_1__0_ cbx_5__0_ ( .top_width_0_height_0__pin_17_upper ( grid_io_bottom_7_top_width_0_height_0__pin_17_upper ) , .top_width_0_height_0__pin_17_lower ( grid_io_bottom_7_top_width_0_height_0__pin_17_lower ) , .SC_IN_TOP ( scff_Wires[131] ) , .SC_OUT_BOT ( scff_Wires[132] ) , - .SC_IN_BOT ( p1429 ) , .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_5523 ) , + .SC_IN_BOT ( p1555 ) , .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_5523 ) , .pReset_E_in ( pResetWires[38] ) , .pReset_W_in ( SYNOPSYS_UNCONNECTED_5524 ) , .pReset_W_out ( pResetWires[37] ) , @@ -117108,7 +121630,7 @@ cbx_1__0_ cbx_6__0_ ( .top_width_0_height_0__pin_15_lower ( grid_io_bottom_6_top_width_0_height_0__pin_15_lower ) , .top_width_0_height_0__pin_17_upper ( grid_io_bottom_6_top_width_0_height_0__pin_17_upper ) , .top_width_0_height_0__pin_17_lower ( grid_io_bottom_6_top_width_0_height_0__pin_17_lower ) , - .SC_IN_TOP ( p1330 ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_5528 ) , + .SC_IN_TOP ( p1246 ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_5528 ) , .SC_IN_BOT ( scff_Wires[133] ) , .SC_OUT_TOP ( scff_Wires[134] ) , .pReset_E_in ( pResetWires[41] ) , .pReset_W_in ( SYNOPSYS_UNCONNECTED_5529 ) , @@ -117164,7 +121686,7 @@ cbx_1__0_ cbx_7__0_ ( .top_width_0_height_0__pin_17_upper ( grid_io_bottom_5_top_width_0_height_0__pin_17_upper ) , .top_width_0_height_0__pin_17_lower ( grid_io_bottom_5_top_width_0_height_0__pin_17_lower ) , .SC_IN_TOP ( scff_Wires[184] ) , .SC_OUT_BOT ( scff_Wires[185] ) , - .SC_IN_BOT ( p1819 ) , .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_5533 ) , + .SC_IN_BOT ( p1228 ) , .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_5533 ) , .pReset_E_in ( SYNOPSYS_UNCONNECTED_5534 ) , .pReset_W_in ( pResetWires[43] ) , .pReset_W_out ( SYNOPSYS_UNCONNECTED_5535 ) , @@ -117218,7 +121740,7 @@ cbx_1__0_ cbx_8__0_ ( .top_width_0_height_0__pin_15_lower ( grid_io_bottom_4_top_width_0_height_0__pin_15_lower ) , .top_width_0_height_0__pin_17_upper ( grid_io_bottom_4_top_width_0_height_0__pin_17_upper ) , .top_width_0_height_0__pin_17_lower ( grid_io_bottom_4_top_width_0_height_0__pin_17_lower ) , - .SC_IN_TOP ( p1461 ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_5538 ) , + .SC_IN_TOP ( p1448 ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_5538 ) , .SC_IN_BOT ( scff_Wires[186] ) , .SC_OUT_TOP ( scff_Wires[187] ) , .pReset_E_in ( SYNOPSYS_UNCONNECTED_5539 ) , .pReset_W_in ( pResetWires[46] ) , @@ -117274,7 +121796,7 @@ cbx_1__0_ cbx_9__0_ ( .top_width_0_height_0__pin_17_upper ( grid_io_bottom_3_top_width_0_height_0__pin_17_upper ) , .top_width_0_height_0__pin_17_lower ( grid_io_bottom_3_top_width_0_height_0__pin_17_lower ) , .SC_IN_TOP ( scff_Wires[237] ) , .SC_OUT_BOT ( scff_Wires[238] ) , - .SC_IN_BOT ( p1316 ) , .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_5543 ) , + .SC_IN_BOT ( p1837 ) , .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_5543 ) , .pReset_E_in ( SYNOPSYS_UNCONNECTED_5544 ) , .pReset_W_in ( pResetWires[49] ) , .pReset_W_out ( SYNOPSYS_UNCONNECTED_5545 ) , @@ -117328,7 +121850,7 @@ cbx_1__0_ cbx_10__0_ ( .top_width_0_height_0__pin_15_lower ( grid_io_bottom_2_top_width_0_height_0__pin_15_lower ) , .top_width_0_height_0__pin_17_upper ( grid_io_bottom_2_top_width_0_height_0__pin_17_upper ) , .top_width_0_height_0__pin_17_lower ( grid_io_bottom_2_top_width_0_height_0__pin_17_lower ) , - .SC_IN_TOP ( p1181 ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_5548 ) , + .SC_IN_TOP ( p1221 ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_5548 ) , .SC_IN_BOT ( scff_Wires[239] ) , .SC_OUT_TOP ( scff_Wires[240] ) , .pReset_E_in ( SYNOPSYS_UNCONNECTED_5549 ) , .pReset_W_in ( pResetWires[52] ) , @@ -117384,7 +121906,7 @@ cbx_1__0_ cbx_11__0_ ( .top_width_0_height_0__pin_17_upper ( grid_io_bottom_1_top_width_0_height_0__pin_17_upper ) , .top_width_0_height_0__pin_17_lower ( grid_io_bottom_1_top_width_0_height_0__pin_17_lower ) , .SC_IN_TOP ( scff_Wires[290] ) , .SC_OUT_BOT ( scff_Wires[291] ) , - .SC_IN_BOT ( p1800 ) , .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_5553 ) , + .SC_IN_BOT ( p1290 ) , .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_5553 ) , .pReset_E_in ( SYNOPSYS_UNCONNECTED_5554 ) , .pReset_W_in ( pResetWires[55] ) , .pReset_W_out ( SYNOPSYS_UNCONNECTED_5555 ) , @@ -117438,7 +121960,7 @@ cbx_1__0_ cbx_12__0_ ( .top_width_0_height_0__pin_15_lower ( grid_io_bottom_0_top_width_0_height_0__pin_15_lower ) , .top_width_0_height_0__pin_17_upper ( grid_io_bottom_0_top_width_0_height_0__pin_17_upper ) , .top_width_0_height_0__pin_17_lower ( grid_io_bottom_0_top_width_0_height_0__pin_17_lower ) , - .SC_IN_TOP ( p1418 ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_5558 ) , + .SC_IN_TOP ( p1529 ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_5558 ) , .SC_IN_BOT ( scff_Wires[292] ) , .SC_OUT_TOP ( scff_Wires[293] ) , .pReset_E_in ( SYNOPSYS_UNCONNECTED_5559 ) , .pReset_W_in ( pResetWires[58] ) , @@ -117470,7 +121992,7 @@ cbx_1__1_ cbx_1__1_ ( .bottom_grid_pin_14_ ( cbx_1__1__0_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__0_bottom_grid_pin_15_ ) , .ccff_tail ( cbx_1__1__0_ccff_tail ) , .SC_IN_TOP ( scff_Wires[22] ) , - .SC_OUT_BOT ( scff_Wires[23] ) , .SC_IN_BOT ( p1388 ) , + .SC_OUT_BOT ( scff_Wires[23] ) , .SC_IN_BOT ( p1963 ) , .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_5563 ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[0] ) , .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[0] ) , @@ -117485,19 +122007,19 @@ cbx_1__1_ cbx_1__1_ ( .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_5566 ) , .prog_clk_1_E_in ( prog_clk_1_wires[2] ) , .prog_clk_1_N_out ( prog_clk_1_wires[3] ) , - .prog_clk_1_S_out ( prog_clk_1_wires[4] ) , .prog_clk_2_E_in ( p1411 ) , - .prog_clk_2_W_in ( p366 ) , + .prog_clk_1_S_out ( prog_clk_1_wires[4] ) , .prog_clk_2_E_in ( p3241 ) , + .prog_clk_2_W_in ( p1657 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5567 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5568 ) , - .prog_clk_3_W_in ( p2715 ) , .prog_clk_3_E_in ( p1415 ) , + .prog_clk_3_W_in ( p1870 ) , .prog_clk_3_E_in ( p3179 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5569 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5570 ) , .clk_1_W_in ( SYNOPSYS_UNCONNECTED_5571 ) , .clk_1_E_in ( clk_1_wires[2] ) , .clk_1_N_out ( clk_1_wires[3] ) , - .clk_1_S_out ( clk_1_wires[4] ) , .clk_2_E_in ( p1411 ) , - .clk_2_W_in ( p2580 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5572 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5573 ) , .clk_3_W_in ( p2094 ) , - .clk_3_E_in ( p90 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5574 ) , + .clk_1_S_out ( clk_1_wires[4] ) , .clk_2_E_in ( p2243 ) , + .clk_2_W_in ( p2119 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5572 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5573 ) , .clk_3_W_in ( p2246 ) , + .clk_3_E_in ( p2171 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5574 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5575 ) ) ; cbx_1__1_ cbx_1__2_ ( .pReset ( { SYNOPSYS_UNCONNECTED_5576 } ) , @@ -117523,7 +122045,7 @@ cbx_1__1_ cbx_1__2_ ( .bottom_grid_pin_14_ ( cbx_1__1__1_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__1_bottom_grid_pin_15_ ) , .ccff_tail ( cbx_1__1__1_ccff_tail ) , .SC_IN_TOP ( scff_Wires[20] ) , - .SC_OUT_BOT ( scff_Wires[21] ) , .SC_IN_BOT ( p2247 ) , + .SC_OUT_BOT ( scff_Wires[21] ) , .SC_IN_BOT ( p2637 ) , .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_5577 ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[1] ) , .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[1] ) , @@ -117534,21 +122056,21 @@ cbx_1__1_ cbx_1__2_ ( .pReset_W_out ( pResetWires[110] ) , .pReset_S_out ( pResetWires[112] ) , .pReset_E_out ( SYNOPSYS_UNCONNECTED_5579 ) , .prog_clk_0_N_in ( prog_clk_0_wires[11] ) , - .prog_clk_0_W_out ( prog_clk_0_wires[10] ) , .prog_clk_1_W_in ( p2842 ) , - .prog_clk_1_E_in ( p2005 ) , + .prog_clk_0_W_out ( prog_clk_0_wires[10] ) , .prog_clk_1_W_in ( p1561 ) , + .prog_clk_1_E_in ( p2379 ) , .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_5580 ) , .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_5581 ) , - .prog_clk_2_E_in ( p2684 ) , .prog_clk_2_W_in ( p2760 ) , + .prog_clk_2_E_in ( p2625 ) , .prog_clk_2_W_in ( p3382 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5582 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5583 ) , - .prog_clk_3_W_in ( p2685 ) , .prog_clk_3_E_in ( p518 ) , + .prog_clk_3_W_in ( p3405 ) , .prog_clk_3_E_in ( p2471 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5584 ) , - .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5585 ) , .clk_1_W_in ( p1466 ) , - .clk_1_E_in ( p2076 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_5586 ) , - .clk_1_S_out ( SYNOPSYS_UNCONNECTED_5587 ) , .clk_2_E_in ( p2684 ) , - .clk_2_W_in ( p2560 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5588 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5589 ) , .clk_3_W_in ( p1783 ) , - .clk_3_E_in ( p2579 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5590 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5585 ) , .clk_1_W_in ( p2591 ) , + .clk_1_E_in ( p574 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_5586 ) , + .clk_1_S_out ( SYNOPSYS_UNCONNECTED_5587 ) , .clk_2_E_in ( p2965 ) , + .clk_2_W_in ( p3198 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5588 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5589 ) , .clk_3_W_in ( p3259 ) , + .clk_3_E_in ( p2859 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5590 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5591 ) ) ; cbx_1__1_ cbx_1__3_ ( .pReset ( { SYNOPSYS_UNCONNECTED_5592 } ) , @@ -117574,7 +122096,7 @@ cbx_1__1_ cbx_1__3_ ( .bottom_grid_pin_14_ ( cbx_1__1__2_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__2_bottom_grid_pin_15_ ) , .ccff_tail ( cbx_1__1__2_ccff_tail ) , .SC_IN_TOP ( scff_Wires[18] ) , - .SC_OUT_BOT ( scff_Wires[19] ) , .SC_IN_BOT ( p1530 ) , + .SC_OUT_BOT ( scff_Wires[19] ) , .SC_IN_BOT ( p1368 ) , .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_5593 ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[2] ) , .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[2] ) , @@ -117589,19 +122111,19 @@ cbx_1__1_ cbx_1__3_ ( .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_5596 ) , .prog_clk_1_E_in ( prog_clk_1_wires[9] ) , .prog_clk_1_N_out ( prog_clk_1_wires[10] ) , - .prog_clk_1_S_out ( prog_clk_1_wires[11] ) , .prog_clk_2_E_in ( p2808 ) , - .prog_clk_2_W_in ( p1236 ) , + .prog_clk_1_S_out ( prog_clk_1_wires[11] ) , .prog_clk_2_E_in ( p3541 ) , + .prog_clk_2_W_in ( p2141 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5597 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5598 ) , - .prog_clk_3_W_in ( p3165 ) , .prog_clk_3_E_in ( p1369 ) , + .prog_clk_3_W_in ( p2324 ) , .prog_clk_3_E_in ( p3518 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5599 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5600 ) , .clk_1_W_in ( SYNOPSYS_UNCONNECTED_5601 ) , .clk_1_E_in ( clk_1_wires[9] ) , .clk_1_N_out ( clk_1_wires[10] ) , - .clk_1_S_out ( clk_1_wires[11] ) , .clk_2_E_in ( p2808 ) , - .clk_2_W_in ( p3145 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5602 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5603 ) , .clk_3_W_in ( p1785 ) , - .clk_3_E_in ( p2753 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5604 ) , + .clk_1_S_out ( clk_1_wires[11] ) , .clk_2_E_in ( p2216 ) , + .clk_2_W_in ( p2921 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5602 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5603 ) , .clk_3_W_in ( p2982 ) , + .clk_3_E_in ( p2057 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5604 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5605 ) ) ; cbx_1__1_ cbx_1__4_ ( .pReset ( { SYNOPSYS_UNCONNECTED_5606 } ) , @@ -117627,7 +122149,7 @@ cbx_1__1_ cbx_1__4_ ( .bottom_grid_pin_14_ ( cbx_1__1__3_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__3_bottom_grid_pin_15_ ) , .ccff_tail ( cbx_1__1__3_ccff_tail ) , .SC_IN_TOP ( scff_Wires[16] ) , - .SC_OUT_BOT ( scff_Wires[17] ) , .SC_IN_BOT ( p1944 ) , + .SC_OUT_BOT ( scff_Wires[17] ) , .SC_IN_BOT ( p1439 ) , .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_5607 ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[3] ) , .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[3] ) , @@ -117638,21 +122160,21 @@ cbx_1__1_ cbx_1__4_ ( .pReset_W_out ( pResetWires[208] ) , .pReset_S_out ( pResetWires[210] ) , .pReset_E_out ( SYNOPSYS_UNCONNECTED_5609 ) , .prog_clk_0_N_in ( prog_clk_0_wires[21] ) , - .prog_clk_0_W_out ( prog_clk_0_wires[20] ) , .prog_clk_1_W_in ( p2825 ) , - .prog_clk_1_E_in ( p1997 ) , + .prog_clk_0_W_out ( prog_clk_0_wires[20] ) , .prog_clk_1_W_in ( p1597 ) , + .prog_clk_1_E_in ( p190 ) , .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_5610 ) , .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_5611 ) , - .prog_clk_2_E_in ( p2115 ) , .prog_clk_2_W_in ( p2773 ) , + .prog_clk_2_E_in ( p2585 ) , .prog_clk_2_W_in ( p3101 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5612 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5613 ) , - .prog_clk_3_W_in ( p3190 ) , .prog_clk_3_E_in ( p1040 ) , + .prog_clk_3_W_in ( p3051 ) , .prog_clk_3_E_in ( p2416 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5614 ) , - .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5615 ) , .clk_1_W_in ( p1322 ) , - .clk_1_E_in ( p1732 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_5616 ) , - .clk_1_S_out ( SYNOPSYS_UNCONNECTED_5617 ) , .clk_2_E_in ( p2115 ) , - .clk_2_W_in ( p3137 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5618 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5619 ) , .clk_3_W_in ( p2471 ) , - .clk_3_E_in ( p2077 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5620 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5615 ) , .clk_1_W_in ( p1941 ) , + .clk_1_E_in ( p1818 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_5616 ) , + .clk_1_S_out ( SYNOPSYS_UNCONNECTED_5617 ) , .clk_2_E_in ( p3234 ) , + .clk_2_W_in ( p3367 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5618 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5619 ) , .clk_3_W_in ( p3404 ) , + .clk_3_E_in ( p3219 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5620 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5621 ) ) ; cbx_1__1_ cbx_1__5_ ( .pReset ( { SYNOPSYS_UNCONNECTED_5622 } ) , @@ -117678,7 +122200,7 @@ cbx_1__1_ cbx_1__5_ ( .bottom_grid_pin_14_ ( cbx_1__1__4_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__4_bottom_grid_pin_15_ ) , .ccff_tail ( cbx_1__1__4_ccff_tail ) , .SC_IN_TOP ( scff_Wires[14] ) , - .SC_OUT_BOT ( scff_Wires[15] ) , .SC_IN_BOT ( p1912 ) , + .SC_OUT_BOT ( scff_Wires[15] ) , .SC_IN_BOT ( p1234 ) , .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_5623 ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[4] ) , .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[4] ) , @@ -117693,19 +122215,19 @@ cbx_1__1_ cbx_1__5_ ( .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_5626 ) , .prog_clk_1_E_in ( prog_clk_1_wires[16] ) , .prog_clk_1_N_out ( prog_clk_1_wires[17] ) , - .prog_clk_1_S_out ( prog_clk_1_wires[18] ) , .prog_clk_2_E_in ( p2488 ) , - .prog_clk_2_W_in ( p184 ) , + .prog_clk_1_S_out ( prog_clk_1_wires[18] ) , .prog_clk_2_E_in ( p2850 ) , + .prog_clk_2_W_in ( p1799 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5627 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5628 ) , - .prog_clk_3_W_in ( p1938 ) , .prog_clk_3_E_in ( p1311 ) , + .prog_clk_3_W_in ( p1981 ) , .prog_clk_3_E_in ( p2645 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5629 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5630 ) , .clk_1_W_in ( SYNOPSYS_UNCONNECTED_5631 ) , .clk_1_E_in ( clk_1_wires[16] ) , .clk_1_N_out ( clk_1_wires[17] ) , - .clk_1_S_out ( clk_1_wires[18] ) , .clk_2_E_in ( p2488 ) , - .clk_2_W_in ( p2356 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5632 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5633 ) , .clk_3_W_in ( p2461 ) , - .clk_3_E_in ( p2335 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5634 ) , + .clk_1_S_out ( clk_1_wires[18] ) , .clk_2_E_in ( p1815 ) , + .clk_2_W_in ( p3077 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5632 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5633 ) , .clk_3_W_in ( p3155 ) , + .clk_3_E_in ( p1825 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5634 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5635 ) ) ; cbx_1__1_ cbx_1__6_ ( .pReset ( { SYNOPSYS_UNCONNECTED_5636 } ) , @@ -117731,7 +122253,7 @@ cbx_1__1_ cbx_1__6_ ( .bottom_grid_pin_14_ ( cbx_1__1__5_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__5_bottom_grid_pin_15_ ) , .ccff_tail ( cbx_1__1__5_ccff_tail ) , .SC_IN_TOP ( scff_Wires[12] ) , - .SC_OUT_BOT ( scff_Wires[13] ) , .SC_IN_BOT ( p1802 ) , + .SC_OUT_BOT ( scff_Wires[13] ) , .SC_IN_BOT ( p1196 ) , .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_5637 ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[5] ) , .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[5] ) , @@ -117742,21 +122264,21 @@ cbx_1__1_ cbx_1__6_ ( .pReset_W_out ( pResetWires[306] ) , .pReset_S_out ( pResetWires[308] ) , .pReset_E_out ( SYNOPSYS_UNCONNECTED_5639 ) , .prog_clk_0_N_in ( prog_clk_0_wires[31] ) , - .prog_clk_0_W_out ( prog_clk_0_wires[30] ) , .prog_clk_1_W_in ( p2189 ) , - .prog_clk_1_E_in ( p879 ) , + .prog_clk_0_W_out ( prog_clk_0_wires[30] ) , .prog_clk_1_W_in ( p1864 ) , + .prog_clk_1_E_in ( p727 ) , .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_5640 ) , .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_5641 ) , - .prog_clk_2_E_in ( p1568 ) , .prog_clk_2_W_in ( p2090 ) , + .prog_clk_2_E_in ( p3114 ) , .prog_clk_2_W_in ( p2861 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5642 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5643 ) , - .prog_clk_3_W_in ( p2146 ) , .prog_clk_3_E_in ( p414 ) , + .prog_clk_3_W_in ( p2998 ) , .prog_clk_3_E_in ( p3097 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5644 ) , - .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5645 ) , .clk_1_W_in ( p1353 ) , - .clk_1_E_in ( p1690 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_5646 ) , - .clk_1_S_out ( SYNOPSYS_UNCONNECTED_5647 ) , .clk_2_E_in ( p1568 ) , - .clk_2_W_in ( p2277 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5648 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5649 ) , .clk_3_W_in ( p2386 ) , - .clk_3_E_in ( p1255 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5650 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5645 ) , .clk_1_W_in ( p2561 ) , + .clk_1_E_in ( p662 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_5646 ) , + .clk_1_S_out ( SYNOPSYS_UNCONNECTED_5647 ) , .clk_2_E_in ( p3162 ) , + .clk_2_W_in ( p3385 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5648 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5649 ) , .clk_3_W_in ( p3418 ) , + .clk_3_E_in ( p3081 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5650 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5651 ) ) ; cbx_1__1_ cbx_1__7_ ( .pReset ( { SYNOPSYS_UNCONNECTED_5652 } ) , @@ -117782,7 +122304,7 @@ cbx_1__1_ cbx_1__7_ ( .bottom_grid_pin_14_ ( cbx_1__1__6_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__6_bottom_grid_pin_15_ ) , .ccff_tail ( cbx_1__1__6_ccff_tail ) , .SC_IN_TOP ( scff_Wires[10] ) , - .SC_OUT_BOT ( scff_Wires[11] ) , .SC_IN_BOT ( p1313 ) , + .SC_OUT_BOT ( scff_Wires[11] ) , .SC_IN_BOT ( p1475 ) , .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_5653 ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[6] ) , .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[6] ) , @@ -117797,19 +122319,19 @@ cbx_1__1_ cbx_1__7_ ( .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_5656 ) , .prog_clk_1_E_in ( prog_clk_1_wires[23] ) , .prog_clk_1_N_out ( prog_clk_1_wires[24] ) , - .prog_clk_1_S_out ( prog_clk_1_wires[25] ) , .prog_clk_2_E_in ( p2932 ) , - .prog_clk_2_W_in ( p320 ) , + .prog_clk_1_S_out ( prog_clk_1_wires[25] ) , .prog_clk_2_E_in ( p2813 ) , + .prog_clk_2_W_in ( p3383 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5657 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5658 ) , - .prog_clk_3_W_in ( p2392 ) , .prog_clk_3_E_in ( p573 ) , + .prog_clk_3_W_in ( p3409 ) , .prog_clk_3_E_in ( p2724 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5659 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5660 ) , .clk_1_W_in ( SYNOPSYS_UNCONNECTED_5661 ) , .clk_1_E_in ( clk_1_wires[23] ) , .clk_1_N_out ( clk_1_wires[24] ) , - .clk_1_S_out ( clk_1_wires[25] ) , .clk_2_E_in ( p2932 ) , - .clk_2_W_in ( p2357 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5662 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5663 ) , .clk_3_W_in ( p2492 ) , - .clk_3_E_in ( p2915 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5664 ) , + .clk_1_S_out ( clk_1_wires[25] ) , .clk_2_E_in ( p2939 ) , + .clk_2_W_in ( p3316 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5662 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5663 ) , .clk_3_W_in ( p3353 ) , + .clk_3_E_in ( p2928 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5664 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5665 ) ) ; cbx_1__1_ cbx_1__8_ ( .pReset ( { SYNOPSYS_UNCONNECTED_5666 } ) , @@ -117835,7 +122357,7 @@ cbx_1__1_ cbx_1__8_ ( .bottom_grid_pin_14_ ( cbx_1__1__7_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__7_bottom_grid_pin_15_ ) , .ccff_tail ( cbx_1__1__7_ccff_tail ) , .SC_IN_TOP ( scff_Wires[8] ) , - .SC_OUT_BOT ( scff_Wires[9] ) , .SC_IN_BOT ( p1909 ) , + .SC_OUT_BOT ( scff_Wires[9] ) , .SC_IN_BOT ( p1627 ) , .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_5667 ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[7] ) , .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[7] ) , @@ -117846,21 +122368,21 @@ cbx_1__1_ cbx_1__8_ ( .pReset_W_out ( pResetWires[404] ) , .pReset_S_out ( pResetWires[406] ) , .pReset_E_out ( SYNOPSYS_UNCONNECTED_5669 ) , .prog_clk_0_N_in ( prog_clk_0_wires[41] ) , - .prog_clk_0_W_out ( prog_clk_0_wires[40] ) , .prog_clk_1_W_in ( p1419 ) , - .prog_clk_1_E_in ( p421 ) , + .prog_clk_0_W_out ( prog_clk_0_wires[40] ) , .prog_clk_1_W_in ( p1596 ) , + .prog_clk_1_E_in ( p575 ) , .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_5670 ) , .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_5671 ) , - .prog_clk_2_E_in ( p2439 ) , .prog_clk_2_W_in ( p920 ) , + .prog_clk_2_E_in ( p3252 ) , .prog_clk_2_W_in ( p3193 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5672 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5673 ) , - .prog_clk_3_W_in ( p3109 ) , .prog_clk_3_E_in ( p626 ) , + .prog_clk_3_W_in ( p3222 ) , .prog_clk_3_E_in ( p3178 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5674 ) , - .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5675 ) , .clk_1_W_in ( p1289 ) , - .clk_1_E_in ( p1685 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_5676 ) , - .clk_1_S_out ( SYNOPSYS_UNCONNECTED_5677 ) , .clk_2_E_in ( p2439 ) , - .clk_2_W_in ( p3033 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5678 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5679 ) , .clk_3_W_in ( p1469 ) , - .clk_3_E_in ( p2343 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5680 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5675 ) , .clk_1_W_in ( p2020 ) , + .clk_1_E_in ( p1058 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_5676 ) , + .clk_1_S_out ( SYNOPSYS_UNCONNECTED_5677 ) , .clk_2_E_in ( p1132 ) , + .clk_2_W_in ( p3450 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5678 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5679 ) , .clk_3_W_in ( p3470 ) , + .clk_3_E_in ( p1267 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5680 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5681 ) ) ; cbx_1__1_ cbx_1__9_ ( .pReset ( { SYNOPSYS_UNCONNECTED_5682 } ) , @@ -117886,7 +122408,7 @@ cbx_1__1_ cbx_1__9_ ( .bottom_grid_pin_14_ ( cbx_1__1__8_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__8_bottom_grid_pin_15_ ) , .ccff_tail ( cbx_1__1__8_ccff_tail ) , .SC_IN_TOP ( scff_Wires[6] ) , - .SC_OUT_BOT ( scff_Wires[7] ) , .SC_IN_BOT ( p1511 ) , + .SC_OUT_BOT ( scff_Wires[7] ) , .SC_IN_BOT ( p1417 ) , .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_5683 ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[8] ) , .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[8] ) , @@ -117901,19 +122423,19 @@ cbx_1__1_ cbx_1__9_ ( .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_5686 ) , .prog_clk_1_E_in ( prog_clk_1_wires[30] ) , .prog_clk_1_N_out ( prog_clk_1_wires[31] ) , - .prog_clk_1_S_out ( prog_clk_1_wires[32] ) , .prog_clk_2_E_in ( p2118 ) , - .prog_clk_2_W_in ( p567 ) , + .prog_clk_1_S_out ( prog_clk_1_wires[32] ) , .prog_clk_2_E_in ( p2966 ) , + .prog_clk_2_W_in ( p3284 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5687 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5688 ) , - .prog_clk_3_W_in ( p2441 ) , .prog_clk_3_E_in ( p1392 ) , + .prog_clk_3_W_in ( p3337 ) , .prog_clk_3_E_in ( p2930 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5689 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5690 ) , .clk_1_W_in ( SYNOPSYS_UNCONNECTED_5691 ) , .clk_1_E_in ( clk_1_wires[30] ) , .clk_1_N_out ( clk_1_wires[31] ) , - .clk_1_S_out ( clk_1_wires[32] ) , .clk_2_E_in ( p2118 ) , - .clk_2_W_in ( p3140 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5692 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5693 ) , .clk_3_W_in ( p3187 ) , - .clk_3_E_in ( p2069 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5694 ) , + .clk_1_S_out ( clk_1_wires[32] ) , .clk_2_E_in ( p1469 ) , + .clk_2_W_in ( p2914 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5692 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5693 ) , .clk_3_W_in ( p2948 ) , + .clk_3_E_in ( p161 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5694 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5695 ) ) ; cbx_1__1_ cbx_1__10_ ( .pReset ( { SYNOPSYS_UNCONNECTED_5696 } ) , @@ -117939,7 +122461,7 @@ cbx_1__1_ cbx_1__10_ ( .bottom_grid_pin_14_ ( cbx_1__1__9_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__9_bottom_grid_pin_15_ ) , .ccff_tail ( cbx_1__1__9_ccff_tail ) , .SC_IN_TOP ( scff_Wires[4] ) , - .SC_OUT_BOT ( scff_Wires[5] ) , .SC_IN_BOT ( p1803 ) , + .SC_OUT_BOT ( scff_Wires[5] ) , .SC_IN_BOT ( p1518 ) , .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_5697 ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[9] ) , .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[9] ) , @@ -117950,21 +122472,21 @@ cbx_1__1_ cbx_1__10_ ( .pReset_W_out ( pResetWires[502] ) , .pReset_S_out ( pResetWires[504] ) , .pReset_E_out ( SYNOPSYS_UNCONNECTED_5699 ) , .prog_clk_0_N_in ( prog_clk_0_wires[51] ) , - .prog_clk_0_W_out ( prog_clk_0_wires[50] ) , .prog_clk_1_W_in ( p2157 ) , - .prog_clk_1_E_in ( p1085 ) , + .prog_clk_0_W_out ( prog_clk_0_wires[50] ) , .prog_clk_1_W_in ( p1315 ) , + .prog_clk_1_E_in ( p789 ) , .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_5700 ) , .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_5701 ) , - .prog_clk_2_E_in ( p1575 ) , .prog_clk_2_W_in ( p2106 ) , + .prog_clk_2_E_in ( p2798 ) , .prog_clk_2_W_in ( p2729 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5702 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5703 ) , - .prog_clk_3_W_in ( p2933 ) , .prog_clk_3_E_in ( p612 ) , + .prog_clk_3_W_in ( p2797 ) , .prog_clk_3_E_in ( p2739 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5704 ) , - .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5705 ) , .clk_1_W_in ( p1496 ) , - .clk_1_E_in ( p1719 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_5706 ) , - .clk_1_S_out ( SYNOPSYS_UNCONNECTED_5707 ) , .clk_2_E_in ( p1575 ) , - .clk_2_W_in ( p2905 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5708 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5709 ) , .clk_3_W_in ( p2502 ) , - .clk_3_E_in ( p1397 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5710 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5705 ) , .clk_1_W_in ( p1821 ) , + .clk_1_E_in ( p2178 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_5706 ) , + .clk_1_S_out ( SYNOPSYS_UNCONNECTED_5707 ) , .clk_2_E_in ( p2742 ) , + .clk_2_W_in ( p3209 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5708 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5709 ) , .clk_3_W_in ( p3254 ) , + .clk_3_E_in ( p2663 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5710 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5711 ) ) ; cbx_1__1_ cbx_1__11_ ( .pReset ( { SYNOPSYS_UNCONNECTED_5712 } ) , @@ -117990,7 +122512,7 @@ cbx_1__1_ cbx_1__11_ ( .bottom_grid_pin_14_ ( cbx_1__1__10_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__10_bottom_grid_pin_15_ ) , .ccff_tail ( cbx_1__1__10_ccff_tail ) , .SC_IN_TOP ( scff_Wires[2] ) , - .SC_OUT_BOT ( scff_Wires[3] ) , .SC_IN_BOT ( p1552 ) , + .SC_OUT_BOT ( scff_Wires[3] ) , .SC_IN_BOT ( p1646 ) , .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_5713 ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[10] ) , .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[10] ) , @@ -118005,19 +122527,19 @@ cbx_1__1_ cbx_1__11_ ( .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_5716 ) , .prog_clk_1_E_in ( prog_clk_1_wires[37] ) , .prog_clk_1_N_out ( prog_clk_1_wires[38] ) , - .prog_clk_1_S_out ( prog_clk_1_wires[39] ) , .prog_clk_2_E_in ( p2266 ) , - .prog_clk_2_W_in ( p132 ) , + .prog_clk_1_S_out ( prog_clk_1_wires[39] ) , .prog_clk_2_E_in ( p2999 ) , + .prog_clk_2_W_in ( p2683 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5717 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5718 ) , - .prog_clk_3_W_in ( p2478 ) , .prog_clk_3_E_in ( p1209 ) , + .prog_clk_3_W_in ( p2828 ) , .prog_clk_3_E_in ( p2910 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5719 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5720 ) , .clk_1_W_in ( SYNOPSYS_UNCONNECTED_5721 ) , .clk_1_E_in ( clk_1_wires[37] ) , .clk_1_N_out ( clk_1_wires[38] ) , - .clk_1_S_out ( clk_1_wires[39] ) , .clk_2_E_in ( p2266 ) , - .clk_2_W_in ( p2749 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5722 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5723 ) , .clk_3_W_in ( p2838 ) , - .clk_3_E_in ( p2082 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5724 ) , + .clk_1_S_out ( clk_1_wires[39] ) , .clk_2_E_in ( p2200 ) , + .clk_2_W_in ( p2398 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5722 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5723 ) , .clk_3_W_in ( p2634 ) , + .clk_3_E_in ( p2164 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5724 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5725 ) ) ; cbx_1__1_ cbx_2__1_ ( .pReset ( { SYNOPSYS_UNCONNECTED_5726 } ) , @@ -118042,7 +122564,7 @@ cbx_1__1_ cbx_2__1_ ( .bottom_grid_pin_13_ ( cbx_1__1__11_bottom_grid_pin_13_ ) , .bottom_grid_pin_14_ ( cbx_1__1__11_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__11_bottom_grid_pin_15_ ) , - .ccff_tail ( cbx_1__1__11_ccff_tail ) , .SC_IN_TOP ( p1910 ) , + .ccff_tail ( cbx_1__1__11_ccff_tail ) , .SC_IN_TOP ( p2048 ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_5727 ) , .SC_IN_BOT ( scff_Wires[29] ) , .SC_OUT_TOP ( scff_Wires[30] ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[11] ) , @@ -118058,20 +122580,20 @@ cbx_1__1_ cbx_2__1_ ( .prog_clk_1_W_in ( prog_clk_1_wires[1] ) , .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_5731 ) , .prog_clk_1_N_out ( prog_clk_1_wires[5] ) , - .prog_clk_1_S_out ( prog_clk_1_wires[6] ) , .prog_clk_2_E_in ( p2473 ) , - .prog_clk_2_W_in ( p874 ) , + .prog_clk_1_S_out ( prog_clk_1_wires[6] ) , .prog_clk_2_E_in ( p2852 ) , + .prog_clk_2_W_in ( p3210 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5732 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5733 ) , - .prog_clk_3_W_in ( p3242 ) , .prog_clk_3_E_in ( p1767 ) , + .prog_clk_3_W_in ( p3275 ) , .prog_clk_3_E_in ( p2727 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5734 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5735 ) , .clk_1_W_in ( clk_1_wires[1] ) , .clk_1_E_in ( SYNOPSYS_UNCONNECTED_5736 ) , .clk_1_N_out ( clk_1_wires[5] ) , .clk_1_S_out ( clk_1_wires[6] ) , - .clk_2_E_in ( p2473 ) , .clk_2_W_in ( p3232 ) , + .clk_2_E_in ( p1577 ) , .clk_2_W_in ( p2932 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5737 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5738 ) , .clk_3_W_in ( p2403 ) , - .clk_3_E_in ( p2324 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5739 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5738 ) , .clk_3_W_in ( p3007 ) , + .clk_3_E_in ( p874 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5739 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5740 ) ) ; cbx_1__1_ cbx_2__2_ ( .pReset ( { SYNOPSYS_UNCONNECTED_5741 } ) , @@ -118096,7 +122618,7 @@ cbx_1__1_ cbx_2__2_ ( .bottom_grid_pin_13_ ( cbx_1__1__12_bottom_grid_pin_13_ ) , .bottom_grid_pin_14_ ( cbx_1__1__12_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__12_bottom_grid_pin_15_ ) , - .ccff_tail ( cbx_1__1__12_ccff_tail ) , .SC_IN_TOP ( p2224 ) , + .ccff_tail ( cbx_1__1__12_ccff_tail ) , .SC_IN_TOP ( p2339 ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_5742 ) , .SC_IN_BOT ( scff_Wires[31] ) , .SC_OUT_TOP ( scff_Wires[32] ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[12] ) , @@ -118109,23 +122631,23 @@ cbx_1__1_ cbx_2__2_ ( .pReset_E_out ( SYNOPSYS_UNCONNECTED_5744 ) , .prog_clk_0_N_in ( prog_clk_0_wires[69] ) , .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_5745 ) , - .prog_clk_1_W_in ( p1288 ) , .prog_clk_1_E_in ( p1623 ) , + .prog_clk_1_W_in ( p1331 ) , .prog_clk_1_E_in ( p633 ) , .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_5746 ) , .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_5747 ) , .prog_clk_2_E_in ( prog_clk_2_wires[2] ) , .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_5748 ) , .prog_clk_2_W_out ( prog_clk_2_wires[1] ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5749 ) , - .prog_clk_3_W_in ( p1288 ) , .prog_clk_3_E_in ( p2045 ) , + .prog_clk_3_W_in ( p1887 ) , .prog_clk_3_E_in ( p2142 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5750 ) , - .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5751 ) , .clk_1_W_in ( p1605 ) , - .clk_1_E_in ( p148 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_5752 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5751 ) , .clk_1_W_in ( p1887 ) , + .clk_1_E_in ( p1736 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_5752 ) , .clk_1_S_out ( SYNOPSYS_UNCONNECTED_5753 ) , .clk_2_E_in ( clk_2_wires[2] ) , .clk_2_W_in ( SYNOPSYS_UNCONNECTED_5754 ) , .clk_2_W_out ( clk_2_wires[1] ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5755 ) , .clk_3_W_in ( p1288 ) , - .clk_3_E_in ( p1751 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5756 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5755 ) , .clk_3_W_in ( p1887 ) , + .clk_3_E_in ( p1817 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5756 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5757 ) ) ; cbx_1__1_ cbx_2__3_ ( .pReset ( { SYNOPSYS_UNCONNECTED_5758 } ) , @@ -118150,7 +122672,7 @@ cbx_1__1_ cbx_2__3_ ( .bottom_grid_pin_13_ ( cbx_1__1__13_bottom_grid_pin_13_ ) , .bottom_grid_pin_14_ ( cbx_1__1__13_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__13_bottom_grid_pin_15_ ) , - .ccff_tail ( cbx_1__1__13_ccff_tail ) , .SC_IN_TOP ( p1475 ) , + .ccff_tail ( cbx_1__1__13_ccff_tail ) , .SC_IN_TOP ( p1881 ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_5759 ) , .SC_IN_BOT ( scff_Wires[33] ) , .SC_OUT_TOP ( scff_Wires[34] ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[13] ) , @@ -118166,20 +122688,20 @@ cbx_1__1_ cbx_2__3_ ( .prog_clk_1_W_in ( prog_clk_1_wires[8] ) , .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_5763 ) , .prog_clk_1_N_out ( prog_clk_1_wires[12] ) , - .prog_clk_1_S_out ( prog_clk_1_wires[13] ) , .prog_clk_2_E_in ( p2455 ) , - .prog_clk_2_W_in ( p814 ) , + .prog_clk_1_S_out ( prog_clk_1_wires[13] ) , .prog_clk_2_E_in ( p3250 ) , + .prog_clk_2_W_in ( p3365 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5764 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5765 ) , - .prog_clk_3_W_in ( p2841 ) , .prog_clk_3_E_in ( p542 ) , + .prog_clk_3_W_in ( p3400 ) , .prog_clk_3_E_in ( p3201 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5766 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5767 ) , .clk_1_W_in ( clk_1_wires[8] ) , .clk_1_E_in ( SYNOPSYS_UNCONNECTED_5768 ) , .clk_1_N_out ( clk_1_wires[12] ) , .clk_1_S_out ( clk_1_wires[13] ) , - .clk_2_E_in ( p2455 ) , .clk_2_W_in ( p2762 ) , + .clk_2_E_in ( p2352 ) , .clk_2_W_in ( p2936 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5769 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5770 ) , .clk_3_W_in ( p2176 ) , - .clk_3_E_in ( p2344 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5771 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5770 ) , .clk_3_W_in ( p2968 ) , + .clk_3_E_in ( p2185 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5771 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5772 ) ) ; cbx_1__1_ cbx_2__4_ ( .pReset ( { SYNOPSYS_UNCONNECTED_5773 } ) , @@ -118204,7 +122726,7 @@ cbx_1__1_ cbx_2__4_ ( .bottom_grid_pin_13_ ( cbx_1__1__14_bottom_grid_pin_13_ ) , .bottom_grid_pin_14_ ( cbx_1__1__14_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__14_bottom_grid_pin_15_ ) , - .ccff_tail ( cbx_1__1__14_ccff_tail ) , .SC_IN_TOP ( p1452 ) , + .ccff_tail ( cbx_1__1__14_ccff_tail ) , .SC_IN_TOP ( p1551 ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_5774 ) , .SC_IN_BOT ( scff_Wires[35] ) , .SC_OUT_TOP ( scff_Wires[36] ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[14] ) , @@ -118217,23 +122739,23 @@ cbx_1__1_ cbx_2__4_ ( .pReset_E_out ( SYNOPSYS_UNCONNECTED_5776 ) , .prog_clk_0_N_in ( prog_clk_0_wires[75] ) , .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_5777 ) , - .prog_clk_1_W_in ( p1927 ) , .prog_clk_1_E_in ( p649 ) , + .prog_clk_1_W_in ( p1557 ) , .prog_clk_1_E_in ( p854 ) , .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_5778 ) , .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_5779 ) , .prog_clk_2_E_in ( prog_clk_2_wires[7] ) , .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_5780 ) , .prog_clk_2_W_out ( prog_clk_2_wires[6] ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5781 ) , - .prog_clk_3_W_in ( p1927 ) , .prog_clk_3_E_in ( p1104 ) , + .prog_clk_3_W_in ( p1340 ) , .prog_clk_3_E_in ( p741 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5782 ) , - .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5783 ) , .clk_1_W_in ( p1776 ) , - .clk_1_E_in ( p569 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_5784 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5783 ) , .clk_1_W_in ( p1340 ) , + .clk_1_E_in ( p354 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_5784 ) , .clk_1_S_out ( SYNOPSYS_UNCONNECTED_5785 ) , .clk_2_E_in ( clk_2_wires[7] ) , .clk_2_W_in ( SYNOPSYS_UNCONNECTED_5786 ) , .clk_2_W_out ( clk_2_wires[6] ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5787 ) , .clk_3_W_in ( p1927 ) , - .clk_3_E_in ( p13 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5788 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5787 ) , .clk_3_W_in ( p1465 ) , + .clk_3_E_in ( p1047 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5788 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5789 ) ) ; cbx_1__1_ cbx_2__5_ ( .pReset ( { SYNOPSYS_UNCONNECTED_5790 } ) , @@ -118258,7 +122780,7 @@ cbx_1__1_ cbx_2__5_ ( .bottom_grid_pin_13_ ( cbx_1__1__15_bottom_grid_pin_13_ ) , .bottom_grid_pin_14_ ( cbx_1__1__15_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__15_bottom_grid_pin_15_ ) , - .ccff_tail ( cbx_1__1__15_ccff_tail ) , .SC_IN_TOP ( p2210 ) , + .ccff_tail ( cbx_1__1__15_ccff_tail ) , .SC_IN_TOP ( p1323 ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_5791 ) , .SC_IN_BOT ( scff_Wires[37] ) , .SC_OUT_TOP ( scff_Wires[38] ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[15] ) , @@ -118274,20 +122796,20 @@ cbx_1__1_ cbx_2__5_ ( .prog_clk_1_W_in ( prog_clk_1_wires[15] ) , .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_5795 ) , .prog_clk_1_N_out ( prog_clk_1_wires[19] ) , - .prog_clk_1_S_out ( prog_clk_1_wires[20] ) , .prog_clk_2_E_in ( p1443 ) , - .prog_clk_2_W_in ( p470 ) , + .prog_clk_1_S_out ( prog_clk_1_wires[20] ) , .prog_clk_2_E_in ( p3148 ) , + .prog_clk_2_W_in ( p2490 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5796 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5797 ) , - .prog_clk_3_W_in ( p1945 ) , .prog_clk_3_E_in ( p1985 ) , + .prog_clk_3_W_in ( p2554 ) , .prog_clk_3_E_in ( p3085 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5798 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5799 ) , .clk_1_W_in ( clk_1_wires[15] ) , .clk_1_E_in ( SYNOPSYS_UNCONNECTED_5800 ) , .clk_1_N_out ( clk_1_wires[19] ) , .clk_1_S_out ( clk_1_wires[20] ) , - .clk_2_E_in ( p1443 ) , .clk_2_W_in ( p1717 ) , + .clk_2_E_in ( p2227 ) , .clk_2_W_in ( p3527 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5801 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5802 ) , .clk_3_W_in ( p1576 ) , - .clk_3_E_in ( p975 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5803 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5802 ) , .clk_3_W_in ( p3537 ) , + .clk_3_E_in ( p2167 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5803 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5804 ) ) ; cbx_1__1_ cbx_2__6_ ( .pReset ( { SYNOPSYS_UNCONNECTED_5805 } ) , @@ -118312,7 +122834,7 @@ cbx_1__1_ cbx_2__6_ ( .bottom_grid_pin_13_ ( cbx_1__1__16_bottom_grid_pin_13_ ) , .bottom_grid_pin_14_ ( cbx_1__1__16_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__16_bottom_grid_pin_15_ ) , - .ccff_tail ( cbx_1__1__16_ccff_tail ) , .SC_IN_TOP ( p2186 ) , + .ccff_tail ( cbx_1__1__16_ccff_tail ) , .SC_IN_TOP ( p1208 ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_5806 ) , .SC_IN_BOT ( scff_Wires[39] ) , .SC_OUT_TOP ( scff_Wires[40] ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[16] ) , @@ -118325,20 +122847,20 @@ cbx_1__1_ cbx_2__6_ ( .pReset_E_out ( SYNOPSYS_UNCONNECTED_5808 ) , .prog_clk_0_N_in ( prog_clk_0_wires[81] ) , .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_5809 ) , - .prog_clk_1_W_in ( p2788 ) , .prog_clk_1_E_in ( p472 ) , + .prog_clk_1_W_in ( p1343 ) , .prog_clk_1_E_in ( p571 ) , .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_5810 ) , .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_5811 ) , - .prog_clk_2_E_in ( p1875 ) , .prog_clk_2_W_in ( p2755 ) , + .prog_clk_2_E_in ( p3476 ) , .prog_clk_2_W_in ( p2462 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5812 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5813 ) , - .prog_clk_3_W_in ( p3364 ) , .prog_clk_3_E_in ( p2015 ) , + .prog_clk_3_W_in ( p2619 ) , .prog_clk_3_E_in ( p3451 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5814 ) , - .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5815 ) , .clk_1_W_in ( p1768 ) , - .clk_1_E_in ( p846 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_5816 ) , - .clk_1_S_out ( SYNOPSYS_UNCONNECTED_5817 ) , .clk_2_E_in ( p1875 ) , - .clk_2_W_in ( p3353 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5818 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5819 ) , .clk_3_W_in ( p2632 ) , - .clk_3_E_in ( p1741 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5820 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5815 ) , .clk_1_W_in ( p2544 ) , + .clk_1_E_in ( p805 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_5816 ) , + .clk_1_S_out ( SYNOPSYS_UNCONNECTED_5817 ) , .clk_2_E_in ( p2498 ) , + .clk_2_W_in ( p3430 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5818 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5819 ) , .clk_3_W_in ( p3454 ) , + .clk_3_E_in ( p2447 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5820 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5821 ) ) ; cbx_1__1_ cbx_2__7_ ( .pReset ( { SYNOPSYS_UNCONNECTED_5822 } ) , @@ -118363,7 +122885,7 @@ cbx_1__1_ cbx_2__7_ ( .bottom_grid_pin_13_ ( cbx_1__1__17_bottom_grid_pin_13_ ) , .bottom_grid_pin_14_ ( cbx_1__1__17_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__17_bottom_grid_pin_15_ ) , - .ccff_tail ( cbx_1__1__17_ccff_tail ) , .SC_IN_TOP ( p2100 ) , + .ccff_tail ( cbx_1__1__17_ccff_tail ) , .SC_IN_TOP ( p2004 ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_5823 ) , .SC_IN_BOT ( scff_Wires[41] ) , .SC_OUT_TOP ( scff_Wires[42] ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[17] ) , @@ -118379,20 +122901,20 @@ cbx_1__1_ cbx_2__7_ ( .prog_clk_1_W_in ( prog_clk_1_wires[22] ) , .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_5827 ) , .prog_clk_1_N_out ( prog_clk_1_wires[26] ) , - .prog_clk_1_S_out ( prog_clk_1_wires[27] ) , .prog_clk_2_E_in ( p1855 ) , - .prog_clk_2_W_in ( p1090 ) , + .prog_clk_1_S_out ( prog_clk_1_wires[27] ) , .prog_clk_2_E_in ( p3325 ) , + .prog_clk_2_W_in ( p3204 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5828 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5829 ) , - .prog_clk_3_W_in ( p2780 ) , .prog_clk_3_E_in ( p1981 ) , + .prog_clk_3_W_in ( p3225 ) , .prog_clk_3_E_in ( p3306 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5830 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5831 ) , .clk_1_W_in ( clk_1_wires[22] ) , .clk_1_E_in ( SYNOPSYS_UNCONNECTED_5832 ) , .clk_1_N_out ( clk_1_wires[26] ) , .clk_1_S_out ( clk_1_wires[27] ) , - .clk_2_E_in ( p1855 ) , .clk_2_W_in ( p3043 ) , + .clk_2_E_in ( p2571 ) , .clk_2_W_in ( p2934 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5833 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5834 ) , .clk_3_W_in ( p3055 ) , - .clk_3_E_in ( p1773 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5835 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5834 ) , .clk_3_W_in ( p2952 ) , + .clk_3_E_in ( p2464 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5835 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5836 ) ) ; cbx_1__1_ cbx_2__8_ ( .pReset ( { SYNOPSYS_UNCONNECTED_5837 } ) , @@ -118417,7 +122939,7 @@ cbx_1__1_ cbx_2__8_ ( .bottom_grid_pin_13_ ( cbx_1__1__18_bottom_grid_pin_13_ ) , .bottom_grid_pin_14_ ( cbx_1__1__18_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__18_bottom_grid_pin_15_ ) , - .ccff_tail ( cbx_1__1__18_ccff_tail ) , .SC_IN_TOP ( p1759 ) , + .ccff_tail ( cbx_1__1__18_ccff_tail ) , .SC_IN_TOP ( p1612 ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_5838 ) , .SC_IN_BOT ( scff_Wires[43] ) , .SC_OUT_TOP ( scff_Wires[44] ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[18] ) , @@ -118430,23 +122952,23 @@ cbx_1__1_ cbx_2__8_ ( .pReset_E_out ( SYNOPSYS_UNCONNECTED_5840 ) , .prog_clk_0_N_in ( prog_clk_0_wires[87] ) , .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_5841 ) , - .prog_clk_1_W_in ( p1825 ) , .prog_clk_1_E_in ( p411 ) , + .prog_clk_1_W_in ( p1484 ) , .prog_clk_1_E_in ( p655 ) , .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_5842 ) , .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_5843 ) , .prog_clk_2_E_in ( prog_clk_2_wires[14] ) , .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_5844 ) , .prog_clk_2_W_out ( prog_clk_2_wires[13] ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5845 ) , - .prog_clk_3_W_in ( p1825 ) , .prog_clk_3_E_in ( p1712 ) , + .prog_clk_3_W_in ( p1655 ) , .prog_clk_3_E_in ( p1070 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5846 ) , - .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5847 ) , .clk_1_W_in ( p1534 ) , - .clk_1_E_in ( p465 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_5848 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5847 ) , .clk_1_W_in ( p1335 ) , + .clk_1_E_in ( p255 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_5848 ) , .clk_1_S_out ( SYNOPSYS_UNCONNECTED_5849 ) , .clk_2_E_in ( clk_2_wires[14] ) , .clk_2_W_in ( SYNOPSYS_UNCONNECTED_5850 ) , .clk_2_W_out ( clk_2_wires[13] ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5851 ) , .clk_3_W_in ( p1825 ) , - .clk_3_E_in ( p1287 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5852 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5851 ) , .clk_3_W_in ( p371 ) , + .clk_3_E_in ( p528 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5852 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5853 ) ) ; cbx_1__1_ cbx_2__9_ ( .pReset ( { SYNOPSYS_UNCONNECTED_5854 } ) , @@ -118471,7 +122993,7 @@ cbx_1__1_ cbx_2__9_ ( .bottom_grid_pin_13_ ( cbx_1__1__19_bottom_grid_pin_13_ ) , .bottom_grid_pin_14_ ( cbx_1__1__19_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__19_bottom_grid_pin_15_ ) , - .ccff_tail ( cbx_1__1__19_ccff_tail ) , .SC_IN_TOP ( p1526 ) , + .ccff_tail ( cbx_1__1__19_ccff_tail ) , .SC_IN_TOP ( p1305 ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_5855 ) , .SC_IN_BOT ( scff_Wires[45] ) , .SC_OUT_TOP ( scff_Wires[46] ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[19] ) , @@ -118487,20 +123009,20 @@ cbx_1__1_ cbx_2__9_ ( .prog_clk_1_W_in ( prog_clk_1_wires[29] ) , .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_5859 ) , .prog_clk_1_N_out ( prog_clk_1_wires[33] ) , - .prog_clk_1_S_out ( prog_clk_1_wires[34] ) , .prog_clk_2_E_in ( p2809 ) , - .prog_clk_2_W_in ( p1225 ) , + .prog_clk_1_S_out ( prog_clk_1_wires[34] ) , .prog_clk_2_E_in ( p3165 ) , + .prog_clk_2_W_in ( p2673 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5860 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5861 ) , - .prog_clk_3_W_in ( p3449 ) , .prog_clk_3_E_in ( p672 ) , + .prog_clk_3_W_in ( p2760 ) , .prog_clk_3_E_in ( p3083 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5862 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5863 ) , .clk_1_W_in ( clk_1_wires[29] ) , .clk_1_E_in ( SYNOPSYS_UNCONNECTED_5864 ) , .clk_1_N_out ( clk_1_wires[33] ) , .clk_1_S_out ( clk_1_wires[34] ) , - .clk_2_E_in ( p2809 ) , .clk_2_W_in ( p3443 ) , + .clk_2_E_in ( p1591 ) , .clk_2_W_in ( p2428 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5865 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5866 ) , .clk_3_W_in ( p1929 ) , - .clk_3_E_in ( p2758 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5867 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5866 ) , .clk_3_W_in ( p2524 ) , + .clk_3_E_in ( p1087 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5867 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5868 ) ) ; cbx_1__1_ cbx_2__10_ ( .pReset ( { SYNOPSYS_UNCONNECTED_5869 } ) , @@ -118525,7 +123047,7 @@ cbx_1__1_ cbx_2__10_ ( .bottom_grid_pin_13_ ( cbx_1__1__20_bottom_grid_pin_13_ ) , .bottom_grid_pin_14_ ( cbx_1__1__20_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__20_bottom_grid_pin_15_ ) , - .ccff_tail ( cbx_1__1__20_ccff_tail ) , .SC_IN_TOP ( p2158 ) , + .ccff_tail ( cbx_1__1__20_ccff_tail ) , .SC_IN_TOP ( p1991 ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_5870 ) , .SC_IN_BOT ( scff_Wires[47] ) , .SC_OUT_TOP ( scff_Wires[48] ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[20] ) , @@ -118538,23 +123060,23 @@ cbx_1__1_ cbx_2__10_ ( .pReset_E_out ( SYNOPSYS_UNCONNECTED_5872 ) , .prog_clk_0_N_in ( prog_clk_0_wires[93] ) , .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_5873 ) , - .prog_clk_1_W_in ( p1607 ) , .prog_clk_1_E_in ( p921 ) , + .prog_clk_1_W_in ( p1506 ) , .prog_clk_1_E_in ( p803 ) , .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_5874 ) , .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_5875 ) , .prog_clk_2_E_in ( prog_clk_2_wires[21] ) , .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_5876 ) , .prog_clk_2_W_out ( prog_clk_2_wires[20] ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5877 ) , - .prog_clk_3_W_in ( p1527 ) , .prog_clk_3_E_in ( p2047 ) , + .prog_clk_3_W_in ( p1604 ) , .prog_clk_3_E_in ( p1769 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5878 ) , - .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5879 ) , .clk_1_W_in ( p1422 ) , - .clk_1_E_in ( p380 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_5880 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5879 ) , .clk_1_W_in ( p1604 ) , + .clk_1_E_in ( p530 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_5880 ) , .clk_1_S_out ( SYNOPSYS_UNCONNECTED_5881 ) , .clk_2_E_in ( clk_2_wires[21] ) , .clk_2_W_in ( SYNOPSYS_UNCONNECTED_5882 ) , .clk_2_W_out ( clk_2_wires[20] ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5883 ) , .clk_3_W_in ( p1527 ) , - .clk_3_E_in ( p1320 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5884 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5883 ) , .clk_3_W_in ( p1604 ) , + .clk_3_E_in ( p15 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5884 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5885 ) ) ; cbx_1__1_ cbx_2__11_ ( .pReset ( { SYNOPSYS_UNCONNECTED_5886 } ) , @@ -118579,7 +123101,7 @@ cbx_1__1_ cbx_2__11_ ( .bottom_grid_pin_13_ ( cbx_1__1__21_bottom_grid_pin_13_ ) , .bottom_grid_pin_14_ ( cbx_1__1__21_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__21_bottom_grid_pin_15_ ) , - .ccff_tail ( cbx_1__1__21_ccff_tail ) , .SC_IN_TOP ( p1787 ) , + .ccff_tail ( cbx_1__1__21_ccff_tail ) , .SC_IN_TOP ( p1454 ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_5887 ) , .SC_IN_BOT ( scff_Wires[49] ) , .SC_OUT_TOP ( scff_Wires[50] ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[21] ) , @@ -118595,20 +123117,20 @@ cbx_1__1_ cbx_2__11_ ( .prog_clk_1_W_in ( prog_clk_1_wires[36] ) , .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_5891 ) , .prog_clk_1_N_out ( prog_clk_1_wires[40] ) , - .prog_clk_1_S_out ( prog_clk_1_wires[41] ) , .prog_clk_2_E_in ( p1939 ) , - .prog_clk_2_W_in ( p751 ) , + .prog_clk_1_S_out ( prog_clk_1_wires[41] ) , .prog_clk_2_E_in ( p3131 ) , + .prog_clk_2_W_in ( p2917 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5892 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5893 ) , - .prog_clk_3_W_in ( p2700 ) , .prog_clk_3_E_in ( p1765 ) , + .prog_clk_3_W_in ( p2974 ) , .prog_clk_3_E_in ( p3035 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5894 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5895 ) , .clk_1_W_in ( clk_1_wires[36] ) , .clk_1_E_in ( SYNOPSYS_UNCONNECTED_5896 ) , .clk_1_N_out ( clk_1_wires[40] ) , .clk_1_S_out ( clk_1_wires[41] ) , - .clk_2_E_in ( p1939 ) , .clk_2_W_in ( p2894 ) , + .clk_2_E_in ( p2248 ) , .clk_2_W_in ( p3177 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5897 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5898 ) , .clk_3_W_in ( p2940 ) , - .clk_3_E_in ( p1697 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5899 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5898 ) , .clk_3_W_in ( p3262 ) , + .clk_3_E_in ( p2205 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5899 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5900 ) ) ; cbx_1__1_ cbx_3__1_ ( .pReset ( { SYNOPSYS_UNCONNECTED_5901 } ) , @@ -118634,7 +123156,7 @@ cbx_1__1_ cbx_3__1_ ( .bottom_grid_pin_14_ ( cbx_1__1__22_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__22_bottom_grid_pin_15_ ) , .ccff_tail ( cbx_1__1__22_ccff_tail ) , .SC_IN_TOP ( scff_Wires[75] ) , - .SC_OUT_BOT ( scff_Wires[76] ) , .SC_IN_BOT ( p1327 ) , + .SC_OUT_BOT ( scff_Wires[76] ) , .SC_IN_BOT ( p1435 ) , .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_5902 ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[22] ) , .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[22] ) , @@ -118649,19 +123171,19 @@ cbx_1__1_ cbx_3__1_ ( .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_5906 ) , .prog_clk_1_E_in ( prog_clk_1_wires[44] ) , .prog_clk_1_N_out ( prog_clk_1_wires[45] ) , - .prog_clk_1_S_out ( prog_clk_1_wires[46] ) , .prog_clk_2_E_in ( p2647 ) , - .prog_clk_2_W_in ( p1182 ) , + .prog_clk_1_S_out ( prog_clk_1_wires[46] ) , .prog_clk_2_E_in ( p2795 ) , + .prog_clk_2_W_in ( p2496 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5907 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5908 ) , - .prog_clk_3_W_in ( p3317 ) , .prog_clk_3_E_in ( p972 ) , + .prog_clk_3_W_in ( p2538 ) , .prog_clk_3_E_in ( p2731 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5909 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5910 ) , .clk_1_W_in ( SYNOPSYS_UNCONNECTED_5911 ) , .clk_1_E_in ( clk_1_wires[44] ) , .clk_1_N_out ( clk_1_wires[45] ) , - .clk_1_S_out ( clk_1_wires[46] ) , .clk_2_E_in ( p2647 ) , - .clk_2_W_in ( p3295 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5912 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5913 ) , .clk_3_W_in ( p2628 ) , - .clk_3_E_in ( p2525 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5914 ) , + .clk_1_S_out ( clk_1_wires[46] ) , .clk_2_E_in ( p2247 ) , + .clk_2_W_in ( p3289 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5912 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5913 ) , .clk_3_W_in ( p3348 ) , + .clk_3_E_in ( p2170 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5914 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5915 ) ) ; cbx_1__1_ cbx_3__2_ ( .pReset ( { SYNOPSYS_UNCONNECTED_5916 } ) , @@ -118687,7 +123209,7 @@ cbx_1__1_ cbx_3__2_ ( .bottom_grid_pin_14_ ( cbx_1__1__23_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__23_bottom_grid_pin_15_ ) , .ccff_tail ( cbx_1__1__23_ccff_tail ) , .SC_IN_TOP ( scff_Wires[73] ) , - .SC_OUT_BOT ( scff_Wires[74] ) , .SC_IN_BOT ( p1570 ) , + .SC_OUT_BOT ( scff_Wires[74] ) , .SC_IN_BOT ( p1924 ) , .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_5917 ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[23] ) , .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[23] ) , @@ -118699,20 +123221,20 @@ cbx_1__1_ cbx_3__2_ ( .pReset_E_out ( SYNOPSYS_UNCONNECTED_5919 ) , .prog_clk_0_N_in ( prog_clk_0_wires[107] ) , .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_5920 ) , - .prog_clk_1_W_in ( p2689 ) , .prog_clk_1_E_in ( p716 ) , + .prog_clk_1_W_in ( p1310 ) , .prog_clk_1_E_in ( p1779 ) , .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_5921 ) , .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_5922 ) , - .prog_clk_2_E_in ( p1786 ) , .prog_clk_2_W_in ( p2593 ) , + .prog_clk_2_E_in ( p2945 ) , .prog_clk_2_W_in ( p2112 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5923 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5924 ) , - .prog_clk_3_W_in ( p3477 ) , .prog_clk_3_E_in ( p1126 ) , + .prog_clk_3_W_in ( p1533 ) , .prog_clk_3_E_in ( p2908 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5925 ) , - .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5926 ) , .clk_1_W_in ( p1486 ) , - .clk_1_E_in ( p2 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_5927 ) , - .clk_1_S_out ( SYNOPSYS_UNCONNECTED_5928 ) , .clk_2_E_in ( p1786 ) , - .clk_2_W_in ( p3476 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5929 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5930 ) , .clk_3_W_in ( p2811 ) , - .clk_3_E_in ( p1738 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5931 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5926 ) , .clk_1_W_in ( p2193 ) , + .clk_1_E_in ( p211 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_5927 ) , + .clk_1_S_out ( SYNOPSYS_UNCONNECTED_5928 ) , .clk_2_E_in ( p1828 ) , + .clk_2_W_in ( p3436 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5929 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5930 ) , .clk_3_W_in ( p3466 ) , + .clk_3_E_in ( p1705 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5931 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5932 ) ) ; cbx_1__1_ cbx_3__3_ ( .pReset ( { SYNOPSYS_UNCONNECTED_5933 } ) , @@ -118738,7 +123260,7 @@ cbx_1__1_ cbx_3__3_ ( .bottom_grid_pin_14_ ( cbx_1__1__24_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__24_bottom_grid_pin_15_ ) , .ccff_tail ( cbx_1__1__24_ccff_tail ) , .SC_IN_TOP ( scff_Wires[71] ) , - .SC_OUT_BOT ( scff_Wires[72] ) , .SC_IN_BOT ( p1370 ) , + .SC_OUT_BOT ( scff_Wires[72] ) , .SC_IN_BOT ( p1494 ) , .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_5934 ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[24] ) , .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[24] ) , @@ -118753,19 +123275,19 @@ cbx_1__1_ cbx_3__3_ ( .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_5938 ) , .prog_clk_1_E_in ( prog_clk_1_wires[51] ) , .prog_clk_1_N_out ( prog_clk_1_wires[52] ) , - .prog_clk_1_S_out ( prog_clk_1_wires[53] ) , .prog_clk_2_E_in ( p2110 ) , - .prog_clk_2_W_in ( p668 ) , + .prog_clk_1_S_out ( prog_clk_1_wires[53] ) , .prog_clk_2_E_in ( p2959 ) , + .prog_clk_2_W_in ( p3366 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5939 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5940 ) , - .prog_clk_3_W_in ( p2640 ) , .prog_clk_3_E_in ( p299 ) , + .prog_clk_3_W_in ( p3422 ) , .prog_clk_3_E_in ( p2929 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5941 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5942 ) , .clk_1_W_in ( SYNOPSYS_UNCONNECTED_5943 ) , .clk_1_E_in ( clk_1_wires[51] ) , .clk_1_N_out ( clk_1_wires[52] ) , - .clk_1_S_out ( clk_1_wires[53] ) , .clk_2_E_in ( p2110 ) , - .clk_2_W_in ( p2586 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5944 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5945 ) , .clk_3_W_in ( p2709 ) , - .clk_3_E_in ( p1966 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5946 ) , + .clk_1_S_out ( clk_1_wires[53] ) , .clk_2_E_in ( p1499 ) , + .clk_2_W_in ( p2488 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5944 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5945 ) , .clk_3_W_in ( p2493 ) , + .clk_3_E_in ( p1090 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5946 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5947 ) ) ; cbx_1__1_ cbx_3__4_ ( .pReset ( { SYNOPSYS_UNCONNECTED_5948 } ) , @@ -118791,7 +123313,7 @@ cbx_1__1_ cbx_3__4_ ( .bottom_grid_pin_14_ ( cbx_1__1__25_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__25_bottom_grid_pin_15_ ) , .ccff_tail ( cbx_1__1__25_ccff_tail ) , .SC_IN_TOP ( scff_Wires[69] ) , - .SC_OUT_BOT ( scff_Wires[70] ) , .SC_IN_BOT ( p1517 ) , + .SC_OUT_BOT ( scff_Wires[70] ) , .SC_IN_BOT ( p1249 ) , .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_5949 ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[25] ) , .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[25] ) , @@ -118803,20 +123325,20 @@ cbx_1__1_ cbx_3__4_ ( .pReset_E_out ( SYNOPSYS_UNCONNECTED_5951 ) , .prog_clk_0_N_in ( prog_clk_0_wires[113] ) , .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_5952 ) , - .prog_clk_1_W_in ( p1604 ) , .prog_clk_1_E_in ( p692 ) , + .prog_clk_1_W_in ( p1531 ) , .prog_clk_1_E_in ( p464 ) , .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_5953 ) , .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_5954 ) , - .prog_clk_2_E_in ( p1828 ) , .prog_clk_2_W_in ( p387 ) , + .prog_clk_2_E_in ( p2698 ) , .prog_clk_2_W_in ( p3448 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5955 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5956 ) , - .prog_clk_3_W_in ( p1962 ) , .prog_clk_3_E_in ( p120 ) , + .prog_clk_3_W_in ( p3472 ) , .prog_clk_3_E_in ( p2737 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5957 ) , - .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5958 ) , .clk_1_W_in ( p1372 ) , - .clk_1_E_in ( p669 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_5959 ) , - .clk_1_S_out ( SYNOPSYS_UNCONNECTED_5960 ) , .clk_2_E_in ( p1828 ) , - .clk_2_W_in ( p2721 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5961 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5962 ) , .clk_3_W_in ( p2795 ) , - .clk_3_E_in ( p1688 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5963 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5958 ) , .clk_1_W_in ( p2805 ) , + .clk_1_E_in ( p2174 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_5959 ) , + .clk_1_S_out ( SYNOPSYS_UNCONNECTED_5960 ) , .clk_2_E_in ( p2292 ) , + .clk_2_W_in ( p3489 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5961 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5962 ) , .clk_3_W_in ( p3510 ) , + .clk_3_E_in ( p2151 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5963 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5964 ) ) ; cbx_1__1_ cbx_3__5_ ( .pReset ( { SYNOPSYS_UNCONNECTED_5965 } ) , @@ -118842,7 +123364,7 @@ cbx_1__1_ cbx_3__5_ ( .bottom_grid_pin_14_ ( cbx_1__1__26_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__26_bottom_grid_pin_15_ ) , .ccff_tail ( cbx_1__1__26_ccff_tail ) , .SC_IN_TOP ( scff_Wires[67] ) , - .SC_OUT_BOT ( scff_Wires[68] ) , .SC_IN_BOT ( p1319 ) , + .SC_OUT_BOT ( scff_Wires[68] ) , .SC_IN_BOT ( p1490 ) , .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_5966 ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[26] ) , .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[26] ) , @@ -118857,19 +123379,19 @@ cbx_1__1_ cbx_3__5_ ( .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_5970 ) , .prog_clk_1_E_in ( prog_clk_1_wires[58] ) , .prog_clk_1_N_out ( prog_clk_1_wires[59] ) , - .prog_clk_1_S_out ( prog_clk_1_wires[60] ) , .prog_clk_2_E_in ( p2682 ) , - .prog_clk_2_W_in ( p1005 ) , + .prog_clk_1_S_out ( prog_clk_1_wires[60] ) , .prog_clk_2_E_in ( p3453 ) , + .prog_clk_2_W_in ( p2715 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5971 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5972 ) , - .prog_clk_3_W_in ( p3077 ) , .prog_clk_3_E_in ( p979 ) , + .prog_clk_3_W_in ( p2761 ) , .prog_clk_3_E_in ( p3433 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5973 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5974 ) , .clk_1_W_in ( SYNOPSYS_UNCONNECTED_5975 ) , .clk_1_E_in ( clk_1_wires[58] ) , .clk_1_N_out ( clk_1_wires[59] ) , - .clk_1_S_out ( clk_1_wires[60] ) , .clk_2_E_in ( p2682 ) , - .clk_2_W_in ( p3000 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5976 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5977 ) , .clk_3_W_in ( p3060 ) , - .clk_3_E_in ( p2595 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5978 ) , + .clk_1_S_out ( clk_1_wires[60] ) , .clk_2_E_in ( p1424 ) , + .clk_2_W_in ( p3435 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5976 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5977 ) , .clk_3_W_in ( p3475 ) , + .clk_3_E_in ( p1017 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5978 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5979 ) ) ; cbx_1__1_ cbx_3__6_ ( .pReset ( { SYNOPSYS_UNCONNECTED_5980 } ) , @@ -118895,7 +123417,7 @@ cbx_1__1_ cbx_3__6_ ( .bottom_grid_pin_14_ ( cbx_1__1__27_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__27_bottom_grid_pin_15_ ) , .ccff_tail ( cbx_1__1__27_ccff_tail ) , .SC_IN_TOP ( scff_Wires[65] ) , - .SC_OUT_BOT ( scff_Wires[66] ) , .SC_IN_BOT ( p2253 ) , + .SC_OUT_BOT ( scff_Wires[66] ) , .SC_IN_BOT ( p1240 ) , .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_5981 ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[27] ) , .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[27] ) , @@ -118907,19 +123429,19 @@ cbx_1__1_ cbx_3__6_ ( .pReset_E_out ( SYNOPSYS_UNCONNECTED_5983 ) , .prog_clk_0_N_in ( prog_clk_0_wires[119] ) , .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_5984 ) , - .prog_clk_1_W_in ( p1585 ) , .prog_clk_1_E_in ( p474 ) , + .prog_clk_1_W_in ( p1367 ) , .prog_clk_1_E_in ( p257 ) , .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_5985 ) , .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_5986 ) , - .prog_clk_2_E_in ( p1091 ) , .prog_clk_2_W_in ( p1314 ) , + .prog_clk_2_E_in ( p1388 ) , .prog_clk_2_W_in ( p2670 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5987 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5988 ) , .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_5989 ) , .prog_clk_3_E_in ( prog_clk_3_wires[50] ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5990 ) , - .prog_clk_3_W_out ( prog_clk_3_wires[51] ) , .clk_1_W_in ( p1428 ) , - .clk_1_E_in ( p1996 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_5991 ) , - .clk_1_S_out ( SYNOPSYS_UNCONNECTED_5992 ) , .clk_2_E_in ( p1091 ) , - .clk_2_W_in ( p652 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5993 ) , + .prog_clk_3_W_out ( prog_clk_3_wires[51] ) , .clk_1_W_in ( p2838 ) , + .clk_1_E_in ( p853 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_5991 ) , + .clk_1_S_out ( SYNOPSYS_UNCONNECTED_5992 ) , .clk_2_E_in ( p1451 ) , + .clk_2_W_in ( p930 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5993 ) , .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5994 ) , .clk_3_W_in ( SYNOPSYS_UNCONNECTED_5995 ) , .clk_3_E_in ( clk_3_wires[50] ) , @@ -118949,7 +123471,7 @@ cbx_1__1_ cbx_3__7_ ( .bottom_grid_pin_14_ ( cbx_1__1__28_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__28_bottom_grid_pin_15_ ) , .ccff_tail ( cbx_1__1__28_ccff_tail ) , .SC_IN_TOP ( scff_Wires[63] ) , - .SC_OUT_BOT ( scff_Wires[64] ) , .SC_IN_BOT ( p1285 ) , + .SC_OUT_BOT ( scff_Wires[64] ) , .SC_IN_BOT ( p1450 ) , .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_5998 ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[28] ) , .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[28] ) , @@ -118964,19 +123486,19 @@ cbx_1__1_ cbx_3__7_ ( .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_6002 ) , .prog_clk_1_E_in ( prog_clk_1_wires[65] ) , .prog_clk_1_N_out ( prog_clk_1_wires[66] ) , - .prog_clk_1_S_out ( prog_clk_1_wires[67] ) , .prog_clk_2_E_in ( p2422 ) , - .prog_clk_2_W_in ( p834 ) , + .prog_clk_1_S_out ( prog_clk_1_wires[67] ) , .prog_clk_2_E_in ( p2353 ) , + .prog_clk_2_W_in ( p3300 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6003 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6004 ) , - .prog_clk_3_W_in ( p2771 ) , .prog_clk_3_E_in ( p1274 ) , + .prog_clk_3_W_in ( p3320 ) , .prog_clk_3_E_in ( p2182 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6005 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6006 ) , .clk_1_W_in ( SYNOPSYS_UNCONNECTED_6007 ) , .clk_1_E_in ( clk_1_wires[65] ) , .clk_1_N_out ( clk_1_wires[66] ) , - .clk_1_S_out ( clk_1_wires[67] ) , .clk_2_E_in ( p2422 ) , - .clk_2_W_in ( p2892 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6008 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6009 ) , .clk_3_W_in ( p2994 ) , - .clk_3_E_in ( p2333 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6010 ) , + .clk_1_S_out ( clk_1_wires[67] ) , .clk_2_E_in ( p3019 ) , + .clk_2_W_in ( p3434 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6008 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6009 ) , .clk_3_W_in ( p3460 ) , + .clk_3_E_in ( p2920 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6010 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6011 ) ) ; cbx_1__1_ cbx_3__8_ ( .pReset ( { SYNOPSYS_UNCONNECTED_6012 } ) , @@ -119002,7 +123524,7 @@ cbx_1__1_ cbx_3__8_ ( .bottom_grid_pin_14_ ( cbx_1__1__29_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__29_bottom_grid_pin_15_ ) , .ccff_tail ( cbx_1__1__29_ccff_tail ) , .SC_IN_TOP ( scff_Wires[61] ) , - .SC_OUT_BOT ( scff_Wires[62] ) , .SC_IN_BOT ( p1490 ) , + .SC_OUT_BOT ( scff_Wires[62] ) , .SC_IN_BOT ( p2257 ) , .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_6013 ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[29] ) , .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[29] ) , @@ -119014,20 +123536,20 @@ cbx_1__1_ cbx_3__8_ ( .pReset_E_out ( SYNOPSYS_UNCONNECTED_6015 ) , .prog_clk_0_N_in ( prog_clk_0_wires[125] ) , .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6016 ) , - .prog_clk_1_W_in ( p2648 ) , .prog_clk_1_E_in ( p146 ) , + .prog_clk_1_W_in ( p1201 ) , .prog_clk_1_E_in ( p2147 ) , .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_6017 ) , .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_6018 ) , - .prog_clk_2_E_in ( p2248 ) , .prog_clk_2_W_in ( p2606 ) , + .prog_clk_2_E_in ( p3255 ) , .prog_clk_2_W_in ( p2186 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6019 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6020 ) , - .prog_clk_3_W_in ( p2211 ) , .prog_clk_3_E_in ( p687 ) , + .prog_clk_3_W_in ( p2026 ) , .prog_clk_3_E_in ( p3196 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6021 ) , - .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6022 ) , .clk_1_W_in ( p1770 ) , - .clk_1_E_in ( p637 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_6023 ) , - .clk_1_S_out ( SYNOPSYS_UNCONNECTED_6024 ) , .clk_2_E_in ( p2248 ) , - .clk_2_W_in ( p2909 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6025 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6026 ) , .clk_3_W_in ( p2986 ) , - .clk_3_E_in ( p2068 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6027 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6022 ) , .clk_1_W_in ( p2356 ) , + .clk_1_E_in ( p994 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_6023 ) , + .clk_1_S_out ( SYNOPSYS_UNCONNECTED_6024 ) , .clk_2_E_in ( p3025 ) , + .clk_2_W_in ( p3076 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6025 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6026 ) , .clk_3_W_in ( p3109 ) , + .clk_3_E_in ( p2935 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6027 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6028 ) ) ; cbx_1__1_ cbx_3__9_ ( .pReset ( { SYNOPSYS_UNCONNECTED_6029 } ) , @@ -119053,7 +123575,7 @@ cbx_1__1_ cbx_3__9_ ( .bottom_grid_pin_14_ ( cbx_1__1__30_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__30_bottom_grid_pin_15_ ) , .ccff_tail ( cbx_1__1__30_ccff_tail ) , .SC_IN_TOP ( scff_Wires[59] ) , - .SC_OUT_BOT ( scff_Wires[60] ) , .SC_IN_BOT ( p1566 ) , + .SC_OUT_BOT ( scff_Wires[60] ) , .SC_IN_BOT ( p1375 ) , .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_6030 ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[30] ) , .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[30] ) , @@ -119068,19 +123590,19 @@ cbx_1__1_ cbx_3__9_ ( .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_6034 ) , .prog_clk_1_E_in ( prog_clk_1_wires[72] ) , .prog_clk_1_N_out ( prog_clk_1_wires[73] ) , - .prog_clk_1_S_out ( prog_clk_1_wires[74] ) , .prog_clk_2_E_in ( p1850 ) , - .prog_clk_2_W_in ( p449 ) , + .prog_clk_1_S_out ( prog_clk_1_wires[74] ) , .prog_clk_2_E_in ( p2766 ) , + .prog_clk_2_W_in ( p2690 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6035 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6036 ) , - .prog_clk_3_W_in ( p3437 ) , .prog_clk_3_E_in ( p954 ) , + .prog_clk_3_W_in ( p2831 ) , .prog_clk_3_E_in ( p2649 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6037 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6038 ) , .clk_1_W_in ( SYNOPSYS_UNCONNECTED_6039 ) , .clk_1_E_in ( clk_1_wires[72] ) , .clk_1_N_out ( clk_1_wires[73] ) , - .clk_1_S_out ( clk_1_wires[74] ) , .clk_2_E_in ( p1850 ) , - .clk_2_W_in ( p3419 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6040 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6041 ) , .clk_3_W_in ( p2692 ) , - .clk_3_E_in ( p1742 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6042 ) , + .clk_1_S_out ( clk_1_wires[74] ) , .clk_2_E_in ( p1418 ) , + .clk_2_W_in ( p3312 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6040 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6041 ) , .clk_3_W_in ( p3322 ) , + .clk_3_E_in ( p1151 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6042 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6043 ) ) ; cbx_1__1_ cbx_3__10_ ( .pReset ( { SYNOPSYS_UNCONNECTED_6044 } ) , @@ -119106,7 +123628,7 @@ cbx_1__1_ cbx_3__10_ ( .bottom_grid_pin_14_ ( cbx_1__1__31_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__31_bottom_grid_pin_15_ ) , .ccff_tail ( cbx_1__1__31_ccff_tail ) , .SC_IN_TOP ( scff_Wires[57] ) , - .SC_OUT_BOT ( scff_Wires[58] ) , .SC_IN_BOT ( p1456 ) , + .SC_OUT_BOT ( scff_Wires[58] ) , .SC_IN_BOT ( p1129 ) , .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_6045 ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[31] ) , .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[31] ) , @@ -119118,20 +123640,20 @@ cbx_1__1_ cbx_3__10_ ( .pReset_E_out ( SYNOPSYS_UNCONNECTED_6047 ) , .prog_clk_0_N_in ( prog_clk_0_wires[131] ) , .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6048 ) , - .prog_clk_1_W_in ( p2817 ) , .prog_clk_1_E_in ( p980 ) , + .prog_clk_1_W_in ( p1365 ) , .prog_clk_1_E_in ( p469 ) , .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_6049 ) , .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_6050 ) , - .prog_clk_2_E_in ( p1499 ) , .prog_clk_2_W_in ( p2759 ) , + .prog_clk_2_E_in ( p2522 ) , .prog_clk_2_W_in ( p2881 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6051 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6052 ) , - .prog_clk_3_W_in ( p2234 ) , .prog_clk_3_E_in ( p571 ) , + .prog_clk_3_W_in ( p2987 ) , .prog_clk_3_E_in ( p2492 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6053 ) , - .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6054 ) , .clk_1_W_in ( p1445 ) , - .clk_1_E_in ( p398 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_6055 ) , - .clk_1_S_out ( SYNOPSYS_UNCONNECTED_6056 ) , .clk_2_E_in ( p1499 ) , - .clk_2_W_in ( p2095 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6057 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6058 ) , .clk_3_W_in ( p2192 ) , - .clk_3_E_in ( p1106 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6059 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6054 ) , .clk_1_W_in ( p2575 ) , + .clk_1_E_in ( p1088 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_6055 ) , + .clk_1_S_out ( SYNOPSYS_UNCONNECTED_6056 ) , .clk_2_E_in ( p2513 ) , + .clk_2_W_in ( p3212 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6057 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6058 ) , .clk_3_W_in ( p3265 ) , + .clk_3_E_in ( p2392 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6059 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6060 ) ) ; cbx_1__1_ cbx_3__11_ ( .pReset ( { SYNOPSYS_UNCONNECTED_6061 } ) , @@ -119157,7 +123679,7 @@ cbx_1__1_ cbx_3__11_ ( .bottom_grid_pin_14_ ( cbx_1__1__32_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__32_bottom_grid_pin_15_ ) , .ccff_tail ( cbx_1__1__32_ccff_tail ) , .SC_IN_TOP ( scff_Wires[55] ) , - .SC_OUT_BOT ( scff_Wires[56] ) , .SC_IN_BOT ( p1489 ) , + .SC_OUT_BOT ( scff_Wires[56] ) , .SC_IN_BOT ( p1880 ) , .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_6062 ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[32] ) , .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[32] ) , @@ -119172,19 +123694,19 @@ cbx_1__1_ cbx_3__11_ ( .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_6066 ) , .prog_clk_1_E_in ( prog_clk_1_wires[79] ) , .prog_clk_1_N_out ( prog_clk_1_wires[80] ) , - .prog_clk_1_S_out ( prog_clk_1_wires[81] ) , .prog_clk_2_E_in ( p1581 ) , - .prog_clk_2_W_in ( p1166 ) , + .prog_clk_1_S_out ( prog_clk_1_wires[81] ) , .prog_clk_2_E_in ( p2802 ) , + .prog_clk_2_W_in ( p3283 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6067 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6068 ) , - .prog_clk_3_W_in ( p3259 ) , .prog_clk_3_E_in ( p745 ) , + .prog_clk_3_W_in ( p3323 ) , .prog_clk_3_E_in ( p2704 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6069 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6070 ) , .clk_1_W_in ( SYNOPSYS_UNCONNECTED_6071 ) , .clk_1_E_in ( clk_1_wires[79] ) , .clk_1_N_out ( clk_1_wires[80] ) , - .clk_1_S_out ( clk_1_wires[81] ) , .clk_2_E_in ( p1581 ) , - .clk_2_W_in ( p3234 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6072 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6073 ) , .clk_3_W_in ( p2789 ) , - .clk_3_E_in ( p1205 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6074 ) , + .clk_1_S_out ( clk_1_wires[81] ) , .clk_2_E_in ( p2822 ) , + .clk_2_W_in ( p2483 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6072 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6073 ) , .clk_3_W_in ( p2556 ) , + .clk_3_E_in ( p2735 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6074 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6075 ) ) ; cbx_1__1_ cbx_4__1_ ( .pReset ( { SYNOPSYS_UNCONNECTED_6076 } ) , @@ -119209,7 +123731,7 @@ cbx_1__1_ cbx_4__1_ ( .bottom_grid_pin_13_ ( cbx_1__1__33_bottom_grid_pin_13_ ) , .bottom_grid_pin_14_ ( cbx_1__1__33_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__33_bottom_grid_pin_15_ ) , - .ccff_tail ( cbx_1__1__33_ccff_tail ) , .SC_IN_TOP ( p1007 ) , + .ccff_tail ( cbx_1__1__33_ccff_tail ) , .SC_IN_TOP ( p1379 ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_6077 ) , .SC_IN_BOT ( scff_Wires[82] ) , .SC_OUT_TOP ( scff_Wires[83] ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[33] ) , @@ -119225,20 +123747,20 @@ cbx_1__1_ cbx_4__1_ ( .prog_clk_1_W_in ( prog_clk_1_wires[43] ) , .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_6081 ) , .prog_clk_1_N_out ( prog_clk_1_wires[47] ) , - .prog_clk_1_S_out ( prog_clk_1_wires[48] ) , .prog_clk_2_E_in ( p2513 ) , - .prog_clk_2_W_in ( p815 ) , + .prog_clk_1_S_out ( prog_clk_1_wires[48] ) , .prog_clk_2_E_in ( p3263 ) , + .prog_clk_2_W_in ( p842 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6082 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6083 ) , - .prog_clk_3_W_in ( p3085 ) , .prog_clk_3_E_in ( p787 ) , + .prog_clk_3_W_in ( p1329 ) , .prog_clk_3_E_in ( p3215 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6084 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6085 ) , .clk_1_W_in ( clk_1_wires[43] ) , .clk_1_E_in ( SYNOPSYS_UNCONNECTED_6086 ) , .clk_1_N_out ( clk_1_wires[47] ) , .clk_1_S_out ( clk_1_wires[48] ) , - .clk_2_E_in ( p2513 ) , .clk_2_W_in ( p3003 ) , + .clk_2_E_in ( p2629 ) , .clk_2_W_in ( p3040 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6087 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6088 ) , .clk_3_W_in ( p2777 ) , - .clk_3_E_in ( p2275 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6089 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6088 ) , .clk_3_W_in ( p3163 ) , + .clk_3_E_in ( p2480 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6089 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6090 ) ) ; cbx_1__1_ cbx_4__2_ ( .pReset ( { SYNOPSYS_UNCONNECTED_6091 } ) , @@ -119263,7 +123785,7 @@ cbx_1__1_ cbx_4__2_ ( .bottom_grid_pin_13_ ( cbx_1__1__34_bottom_grid_pin_13_ ) , .bottom_grid_pin_14_ ( cbx_1__1__34_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__34_bottom_grid_pin_15_ ) , - .ccff_tail ( cbx_1__1__34_ccff_tail ) , .SC_IN_TOP ( p2133 ) , + .ccff_tail ( cbx_1__1__34_ccff_tail ) , .SC_IN_TOP ( p1441 ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_6092 ) , .SC_IN_BOT ( scff_Wires[84] ) , .SC_OUT_TOP ( scff_Wires[85] ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[34] ) , @@ -119276,23 +123798,23 @@ cbx_1__1_ cbx_4__2_ ( .pReset_E_out ( SYNOPSYS_UNCONNECTED_6094 ) , .prog_clk_0_N_in ( prog_clk_0_wires[145] ) , .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6095 ) , - .prog_clk_1_W_in ( p1421 ) , .prog_clk_1_E_in ( p2359 ) , + .prog_clk_1_W_in ( p1492 ) , .prog_clk_1_E_in ( p104 ) , .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_6096 ) , .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_6097 ) , .prog_clk_2_E_in ( prog_clk_2_wires[27] ) , .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_6098 ) , .prog_clk_2_W_out ( prog_clk_2_wires[28] ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6099 ) , - .prog_clk_3_W_in ( p1421 ) , .prog_clk_3_E_in ( p2088 ) , + .prog_clk_3_W_in ( p1391 ) , .prog_clk_3_E_in ( p352 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6100 ) , - .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6101 ) , .clk_1_W_in ( p1500 ) , - .clk_1_E_in ( p615 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_6102 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6101 ) , .clk_1_W_in ( p1391 ) , + .clk_1_E_in ( p806 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_6102 ) , .clk_1_S_out ( SYNOPSYS_UNCONNECTED_6103 ) , .clk_2_E_in ( clk_2_wires[27] ) , .clk_2_W_in ( SYNOPSYS_UNCONNECTED_6104 ) , .clk_2_W_out ( clk_2_wires[28] ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6105 ) , .clk_3_W_in ( p1421 ) , - .clk_3_E_in ( p2285 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6106 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6105 ) , .clk_3_W_in ( p1391 ) , + .clk_3_E_in ( p1230 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6106 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6107 ) ) ; cbx_1__1_ cbx_4__3_ ( .pReset ( { SYNOPSYS_UNCONNECTED_6108 } ) , @@ -119317,7 +123839,7 @@ cbx_1__1_ cbx_4__3_ ( .bottom_grid_pin_13_ ( cbx_1__1__35_bottom_grid_pin_13_ ) , .bottom_grid_pin_14_ ( cbx_1__1__35_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__35_bottom_grid_pin_15_ ) , - .ccff_tail ( cbx_1__1__35_ccff_tail ) , .SC_IN_TOP ( p1577 ) , + .ccff_tail ( cbx_1__1__35_ccff_tail ) , .SC_IN_TOP ( p1548 ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_6109 ) , .SC_IN_BOT ( scff_Wires[86] ) , .SC_OUT_TOP ( scff_Wires[87] ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[35] ) , @@ -119333,20 +123855,20 @@ cbx_1__1_ cbx_4__3_ ( .prog_clk_1_W_in ( prog_clk_1_wires[50] ) , .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_6113 ) , .prog_clk_1_N_out ( prog_clk_1_wires[54] ) , - .prog_clk_1_S_out ( prog_clk_1_wires[55] ) , .prog_clk_2_E_in ( p2443 ) , - .prog_clk_2_W_in ( p1318 ) , + .prog_clk_1_S_out ( prog_clk_1_wires[55] ) , .prog_clk_2_E_in ( p2219 ) , + .prog_clk_2_W_in ( p3066 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6114 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6115 ) , - .prog_clk_3_W_in ( p2802 ) , .prog_clk_3_E_in ( p72 ) , + .prog_clk_3_W_in ( p3146 ) , .prog_clk_3_E_in ( p2153 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6116 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6117 ) , .clk_1_W_in ( clk_1_wires[50] ) , .clk_1_E_in ( SYNOPSYS_UNCONNECTED_6118 ) , .clk_1_N_out ( clk_1_wires[54] ) , .clk_1_S_out ( clk_1_wires[55] ) , - .clk_2_E_in ( p2443 ) , .clk_2_W_in ( p2750 ) , + .clk_2_E_in ( p2250 ) , .clk_2_W_in ( p1806 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6119 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6120 ) , .clk_3_W_in ( p1847 ) , - .clk_3_E_in ( p2279 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6121 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6120 ) , .clk_3_W_in ( p2002 ) , + .clk_3_E_in ( p2083 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6121 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6122 ) ) ; cbx_1__1_ cbx_4__4_ ( .pReset ( { SYNOPSYS_UNCONNECTED_6123 } ) , @@ -119371,7 +123893,7 @@ cbx_1__1_ cbx_4__4_ ( .bottom_grid_pin_13_ ( cbx_1__1__36_bottom_grid_pin_13_ ) , .bottom_grid_pin_14_ ( cbx_1__1__36_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__36_bottom_grid_pin_15_ ) , - .ccff_tail ( cbx_1__1__36_ccff_tail ) , .SC_IN_TOP ( p1885 ) , + .ccff_tail ( cbx_1__1__36_ccff_tail ) , .SC_IN_TOP ( p2574 ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_6124 ) , .SC_IN_BOT ( scff_Wires[88] ) , .SC_OUT_TOP ( scff_Wires[89] ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[36] ) , @@ -119384,23 +123906,23 @@ cbx_1__1_ cbx_4__4_ ( .pReset_E_out ( SYNOPSYS_UNCONNECTED_6126 ) , .prog_clk_0_N_in ( prog_clk_0_wires[151] ) , .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6127 ) , - .prog_clk_1_W_in ( p1794 ) , .prog_clk_1_E_in ( p340 ) , + .prog_clk_1_W_in ( p1205 ) , .prog_clk_1_E_in ( p241 ) , .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_6128 ) , .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_6129 ) , .prog_clk_2_E_in ( prog_clk_2_wires[36] ) , .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_6130 ) , .prog_clk_2_W_out ( prog_clk_2_wires[37] ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6131 ) , - .prog_clk_3_W_in ( p1878 ) , .prog_clk_3_E_in ( p1715 ) , + .prog_clk_3_W_in ( p1840 ) , .prog_clk_3_E_in ( p2432 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6132 ) , - .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6133 ) , .clk_1_W_in ( p1133 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6133 ) , .clk_1_W_in ( p1840 ) , .clk_1_E_in ( p688 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_6134 ) , .clk_1_S_out ( SYNOPSYS_UNCONNECTED_6135 ) , .clk_2_E_in ( clk_2_wires[36] ) , .clk_2_W_in ( SYNOPSYS_UNCONNECTED_6136 ) , .clk_2_W_out ( clk_2_wires[37] ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6137 ) , .clk_3_W_in ( p1878 ) , - .clk_3_E_in ( p1184 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6138 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6137 ) , .clk_3_W_in ( p1840 ) , + .clk_3_E_in ( p194 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6138 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6139 ) ) ; cbx_1__1_ cbx_4__5_ ( .pReset ( { SYNOPSYS_UNCONNECTED_6140 } ) , @@ -119425,7 +123947,7 @@ cbx_1__1_ cbx_4__5_ ( .bottom_grid_pin_13_ ( cbx_1__1__37_bottom_grid_pin_13_ ) , .bottom_grid_pin_14_ ( cbx_1__1__37_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__37_bottom_grid_pin_15_ ) , - .ccff_tail ( cbx_1__1__37_ccff_tail ) , .SC_IN_TOP ( p2431 ) , + .ccff_tail ( cbx_1__1__37_ccff_tail ) , .SC_IN_TOP ( p1578 ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_6141 ) , .SC_IN_BOT ( scff_Wires[90] ) , .SC_OUT_TOP ( scff_Wires[91] ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[37] ) , @@ -119441,20 +123963,20 @@ cbx_1__1_ cbx_4__5_ ( .prog_clk_1_W_in ( prog_clk_1_wires[57] ) , .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_6145 ) , .prog_clk_1_N_out ( prog_clk_1_wires[61] ) , - .prog_clk_1_S_out ( prog_clk_1_wires[62] ) , .prog_clk_2_E_in ( p2181 ) , - .prog_clk_2_W_in ( p1219 ) , + .prog_clk_1_S_out ( prog_clk_1_wires[62] ) , .prog_clk_2_E_in ( p3023 ) , + .prog_clk_2_W_in ( p2451 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6146 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6147 ) , - .prog_clk_3_W_in ( p3400 ) , .prog_clk_3_E_in ( p2301 ) , + .prog_clk_3_W_in ( p2615 ) , .prog_clk_3_E_in ( p2863 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6148 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6149 ) , .clk_1_W_in ( clk_1_wires[57] ) , .clk_1_E_in ( SYNOPSYS_UNCONNECTED_6150 ) , .clk_1_N_out ( clk_1_wires[61] ) , .clk_1_S_out ( clk_1_wires[62] ) , - .clk_2_E_in ( p2201 ) , .clk_2_W_in ( p3392 ) , + .clk_2_E_in ( p3167 ) , .clk_2_W_in ( p2709 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6151 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6152 ) , .clk_3_W_in ( p2850 ) , - .clk_3_E_in ( p2060 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6153 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6152 ) , .clk_3_W_in ( p2788 ) , + .clk_3_E_in ( p3063 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6153 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6154 ) ) ; cbx_1__1_ cbx_4__6_ ( .pReset ( { SYNOPSYS_UNCONNECTED_6155 } ) , @@ -119479,7 +124001,7 @@ cbx_1__1_ cbx_4__6_ ( .bottom_grid_pin_13_ ( cbx_1__1__38_bottom_grid_pin_13_ ) , .bottom_grid_pin_14_ ( cbx_1__1__38_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__38_bottom_grid_pin_15_ ) , - .ccff_tail ( cbx_1__1__38_ccff_tail ) , .SC_IN_TOP ( p1299 ) , + .ccff_tail ( cbx_1__1__38_ccff_tail ) , .SC_IN_TOP ( p1543 ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_6156 ) , .SC_IN_BOT ( scff_Wires[92] ) , .SC_OUT_TOP ( scff_Wires[93] ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[38] ) , @@ -119492,19 +124014,19 @@ cbx_1__1_ cbx_4__6_ ( .pReset_E_out ( SYNOPSYS_UNCONNECTED_6158 ) , .prog_clk_0_N_in ( prog_clk_0_wires[157] ) , .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6159 ) , - .prog_clk_1_W_in ( p2468 ) , .prog_clk_1_E_in ( p831 ) , + .prog_clk_1_W_in ( p1193 ) , .prog_clk_1_E_in ( p435 ) , .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_6160 ) , .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_6161 ) , - .prog_clk_2_E_in ( p1299 ) , .prog_clk_2_W_in ( p2338 ) , + .prog_clk_2_E_in ( p1997 ) , .prog_clk_2_W_in ( p2406 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6162 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6163 ) , .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_6164 ) , .prog_clk_3_E_in ( prog_clk_3_wires[46] ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6165 ) , - .prog_clk_3_W_out ( prog_clk_3_wires[47] ) , .clk_1_W_in ( p1472 ) , - .clk_1_E_in ( p601 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_6166 ) , - .clk_1_S_out ( SYNOPSYS_UNCONNECTED_6167 ) , .clk_2_E_in ( p1299 ) , - .clk_2_W_in ( p1302 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6168 ) , + .prog_clk_3_W_out ( prog_clk_3_wires[47] ) , .clk_1_W_in ( p2596 ) , + .clk_1_E_in ( p658 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_6166 ) , + .clk_1_S_out ( SYNOPSYS_UNCONNECTED_6167 ) , .clk_2_E_in ( p1997 ) , + .clk_2_W_in ( p899 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6168 ) , .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6169 ) , .clk_3_W_in ( SYNOPSYS_UNCONNECTED_6170 ) , .clk_3_E_in ( clk_3_wires[46] ) , @@ -119533,7 +124055,7 @@ cbx_1__1_ cbx_4__7_ ( .bottom_grid_pin_13_ ( cbx_1__1__39_bottom_grid_pin_13_ ) , .bottom_grid_pin_14_ ( cbx_1__1__39_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__39_bottom_grid_pin_15_ ) , - .ccff_tail ( cbx_1__1__39_ccff_tail ) , .SC_IN_TOP ( p2389 ) , + .ccff_tail ( cbx_1__1__39_ccff_tail ) , .SC_IN_TOP ( p1501 ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_6173 ) , .SC_IN_BOT ( scff_Wires[94] ) , .SC_OUT_TOP ( scff_Wires[95] ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[39] ) , @@ -119549,20 +124071,20 @@ cbx_1__1_ cbx_4__7_ ( .prog_clk_1_W_in ( prog_clk_1_wires[64] ) , .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_6177 ) , .prog_clk_1_N_out ( prog_clk_1_wires[68] ) , - .prog_clk_1_S_out ( prog_clk_1_wires[69] ) , .prog_clk_2_E_in ( p2421 ) , - .prog_clk_2_W_in ( p266 ) , + .prog_clk_1_S_out ( prog_clk_1_wires[69] ) , .prog_clk_2_E_in ( p2306 ) , + .prog_clk_2_W_in ( p2722 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6178 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6179 ) , - .prog_clk_3_W_in ( p2963 ) , .prog_clk_3_E_in ( p2304 ) , + .prog_clk_3_W_in ( p2832 ) , .prog_clk_3_E_in ( p2145 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6180 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6181 ) , .clk_1_W_in ( clk_1_wires[64] ) , .clk_1_E_in ( SYNOPSYS_UNCONNECTED_6182 ) , .clk_1_N_out ( clk_1_wires[68] ) , .clk_1_S_out ( clk_1_wires[69] ) , - .clk_2_E_in ( p2421 ) , .clk_2_W_in ( p3002 ) , + .clk_2_E_in ( p1933 ) , .clk_2_W_in ( p3296 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6183 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6184 ) , .clk_3_W_in ( p3053 ) , - .clk_3_E_in ( p2385 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6185 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6184 ) , .clk_3_W_in ( p3358 ) , + .clk_3_E_in ( p1813 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6185 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6186 ) ) ; cbx_1__1_ cbx_4__8_ ( .pReset ( { SYNOPSYS_UNCONNECTED_6187 } ) , @@ -119587,7 +124109,7 @@ cbx_1__1_ cbx_4__8_ ( .bottom_grid_pin_13_ ( cbx_1__1__40_bottom_grid_pin_13_ ) , .bottom_grid_pin_14_ ( cbx_1__1__40_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__40_bottom_grid_pin_15_ ) , - .ccff_tail ( cbx_1__1__40_ccff_tail ) , .SC_IN_TOP ( p1792 ) , + .ccff_tail ( cbx_1__1__40_ccff_tail ) , .SC_IN_TOP ( p1174 ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_6188 ) , .SC_IN_BOT ( scff_Wires[96] ) , .SC_OUT_TOP ( scff_Wires[97] ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[40] ) , @@ -119600,23 +124122,23 @@ cbx_1__1_ cbx_4__8_ ( .pReset_E_out ( SYNOPSYS_UNCONNECTED_6190 ) , .prog_clk_0_N_in ( prog_clk_0_wires[163] ) , .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6191 ) , - .prog_clk_1_W_in ( p1871 ) , .prog_clk_1_E_in ( p10 ) , + .prog_clk_1_W_in ( p721 ) , .prog_clk_1_E_in ( p746 ) , .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_6192 ) , .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_6193 ) , .prog_clk_2_E_in ( prog_clk_2_wires[49] ) , .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_6194 ) , .prog_clk_2_W_out ( prog_clk_2_wires[50] ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6195 ) , - .prog_clk_3_W_in ( p1817 ) , .prog_clk_3_E_in ( p1708 ) , + .prog_clk_3_W_in ( p1964 ) , .prog_clk_3_E_in ( p964 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6196 ) , - .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6197 ) , .clk_1_W_in ( p1407 ) , - .clk_1_E_in ( p531 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_6198 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6197 ) , .clk_1_W_in ( p1875 ) , + .clk_1_E_in ( p414 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_6198 ) , .clk_1_S_out ( SYNOPSYS_UNCONNECTED_6199 ) , .clk_2_E_in ( clk_2_wires[49] ) , .clk_2_W_in ( SYNOPSYS_UNCONNECTED_6200 ) , .clk_2_W_out ( clk_2_wires[50] ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6201 ) , .clk_3_W_in ( p1817 ) , - .clk_3_E_in ( p762 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6202 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6201 ) , .clk_3_W_in ( p1964 ) , + .clk_3_E_in ( p603 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6202 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6203 ) ) ; cbx_1__1_ cbx_4__9_ ( .pReset ( { SYNOPSYS_UNCONNECTED_6204 } ) , @@ -119641,7 +124163,7 @@ cbx_1__1_ cbx_4__9_ ( .bottom_grid_pin_13_ ( cbx_1__1__41_bottom_grid_pin_13_ ) , .bottom_grid_pin_14_ ( cbx_1__1__41_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__41_bottom_grid_pin_15_ ) , - .ccff_tail ( cbx_1__1__41_ccff_tail ) , .SC_IN_TOP ( p2091 ) , + .ccff_tail ( cbx_1__1__41_ccff_tail ) , .SC_IN_TOP ( p1411 ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_6205 ) , .SC_IN_BOT ( scff_Wires[98] ) , .SC_OUT_TOP ( scff_Wires[99] ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[41] ) , @@ -119657,20 +124179,20 @@ cbx_1__1_ cbx_4__9_ ( .prog_clk_1_W_in ( prog_clk_1_wires[71] ) , .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_6209 ) , .prog_clk_1_N_out ( prog_clk_1_wires[75] ) , - .prog_clk_1_S_out ( prog_clk_1_wires[76] ) , .prog_clk_2_E_in ( p2444 ) , - .prog_clk_2_W_in ( p1148 ) , + .prog_clk_1_S_out ( prog_clk_1_wires[76] ) , .prog_clk_2_E_in ( p3361 ) , + .prog_clk_2_W_in ( p3485 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6210 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6211 ) , - .prog_clk_3_W_in ( p1516 ) , .prog_clk_3_E_in ( p1993 ) , + .prog_clk_3_W_in ( p3499 ) , .prog_clk_3_E_in ( p3286 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6212 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6213 ) , .clk_1_W_in ( clk_1_wires[71] ) , .clk_1_E_in ( SYNOPSYS_UNCONNECTED_6214 ) , .clk_1_N_out ( clk_1_wires[75] ) , .clk_1_S_out ( clk_1_wires[76] ) , - .clk_2_E_in ( p2444 ) , .clk_2_W_in ( p2906 ) , + .clk_2_E_in ( p2839 ) , .clk_2_W_in ( p2076 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6215 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6216 ) , .clk_3_W_in ( p2970 ) , - .clk_3_E_in ( p2321 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6217 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6216 ) , .clk_3_W_in ( p2329 ) , + .clk_3_E_in ( p2740 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6217 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6218 ) ) ; cbx_1__1_ cbx_4__10_ ( .pReset ( { SYNOPSYS_UNCONNECTED_6219 } ) , @@ -119695,7 +124217,7 @@ cbx_1__1_ cbx_4__10_ ( .bottom_grid_pin_13_ ( cbx_1__1__42_bottom_grid_pin_13_ ) , .bottom_grid_pin_14_ ( cbx_1__1__42_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__42_bottom_grid_pin_15_ ) , - .ccff_tail ( cbx_1__1__42_ccff_tail ) , .SC_IN_TOP ( p1425 ) , + .ccff_tail ( cbx_1__1__42_ccff_tail ) , .SC_IN_TOP ( p1130 ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_6220 ) , .SC_IN_BOT ( scff_Wires[100] ) , .SC_OUT_TOP ( scff_Wires[101] ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[42] ) , @@ -119708,23 +124230,23 @@ cbx_1__1_ cbx_4__10_ ( .pReset_E_out ( SYNOPSYS_UNCONNECTED_6222 ) , .prog_clk_0_N_in ( prog_clk_0_wires[169] ) , .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6223 ) , - .prog_clk_1_W_in ( p1799 ) , .prog_clk_1_E_in ( p1643 ) , + .prog_clk_1_W_in ( p1282 ) , .prog_clk_1_E_in ( p676 ) , .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_6224 ) , .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_6225 ) , .prog_clk_2_E_in ( prog_clk_2_wires[62] ) , .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_6226 ) , .prog_clk_2_W_out ( prog_clk_2_wires[63] ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6227 ) , - .prog_clk_3_W_in ( p1799 ) , .prog_clk_3_E_in ( p860 ) , + .prog_clk_3_W_in ( p1223 ) , .prog_clk_3_E_in ( p1005 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6228 ) , - .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6229 ) , .clk_1_W_in ( p1383 ) , - .clk_1_E_in ( p354 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_6230 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6229 ) , .clk_1_W_in ( p1223 ) , + .clk_1_E_in ( p1004 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_6230 ) , .clk_1_S_out ( SYNOPSYS_UNCONNECTED_6231 ) , .clk_2_E_in ( clk_2_wires[62] ) , .clk_2_W_in ( SYNOPSYS_UNCONNECTED_6232 ) , .clk_2_W_out ( clk_2_wires[63] ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6233 ) , .clk_3_W_in ( p1799 ) , - .clk_3_E_in ( p1747 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6234 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6233 ) , .clk_3_W_in ( p1223 ) , + .clk_3_E_in ( p12 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6234 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6235 ) ) ; cbx_1__1_ cbx_4__11_ ( .pReset ( { SYNOPSYS_UNCONNECTED_6236 } ) , @@ -119749,7 +124271,7 @@ cbx_1__1_ cbx_4__11_ ( .bottom_grid_pin_13_ ( cbx_1__1__43_bottom_grid_pin_13_ ) , .bottom_grid_pin_14_ ( cbx_1__1__43_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__43_bottom_grid_pin_15_ ) , - .ccff_tail ( cbx_1__1__43_ccff_tail ) , .SC_IN_TOP ( p1884 ) , + .ccff_tail ( cbx_1__1__43_ccff_tail ) , .SC_IN_TOP ( p1916 ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_6237 ) , .SC_IN_BOT ( scff_Wires[102] ) , .SC_OUT_TOP ( scff_Wires[103] ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[43] ) , @@ -119765,20 +124287,20 @@ cbx_1__1_ cbx_4__11_ ( .prog_clk_1_W_in ( prog_clk_1_wires[78] ) , .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_6241 ) , .prog_clk_1_N_out ( prog_clk_1_wires[82] ) , - .prog_clk_1_S_out ( prog_clk_1_wires[83] ) , .prog_clk_2_E_in ( p1442 ) , - .prog_clk_2_W_in ( p1257 ) , + .prog_clk_1_S_out ( prog_clk_1_wires[83] ) , .prog_clk_2_E_in ( p2814 ) , + .prog_clk_2_W_in ( p802 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6242 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6243 ) , - .prog_clk_3_W_in ( p3169 ) , .prog_clk_3_E_in ( p1636 ) , + .prog_clk_3_W_in ( p1239 ) , .prog_clk_3_E_in ( p2716 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6244 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6245 ) , .clk_1_W_in ( clk_1_wires[78] ) , .clk_1_E_in ( SYNOPSYS_UNCONNECTED_6246 ) , .clk_1_N_out ( clk_1_wires[82] ) , .clk_1_S_out ( clk_1_wires[83] ) , - .clk_2_E_in ( p1442 ) , .clk_2_W_in ( p3143 ) , + .clk_2_E_in ( p2824 ) , .clk_2_W_in ( p3447 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6247 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6248 ) , .clk_3_W_in ( p1806 ) , - .clk_3_E_in ( p250 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6249 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6248 ) , .clk_3_W_in ( p3456 ) , + .clk_3_E_in ( p2738 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6249 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6250 ) ) ; cbx_1__1_ cbx_5__1_ ( .pReset ( { SYNOPSYS_UNCONNECTED_6251 } ) , @@ -119804,7 +124326,7 @@ cbx_1__1_ cbx_5__1_ ( .bottom_grid_pin_14_ ( cbx_1__1__44_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__44_bottom_grid_pin_15_ ) , .ccff_tail ( cbx_1__1__44_ccff_tail ) , .SC_IN_TOP ( scff_Wires[128] ) , - .SC_OUT_BOT ( scff_Wires[129] ) , .SC_IN_BOT ( p1404 ) , + .SC_OUT_BOT ( scff_Wires[129] ) , .SC_IN_BOT ( p1346 ) , .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_6252 ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[44] ) , .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[44] ) , @@ -119819,19 +124341,19 @@ cbx_1__1_ cbx_5__1_ ( .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_6256 ) , .prog_clk_1_E_in ( prog_clk_1_wires[86] ) , .prog_clk_1_N_out ( prog_clk_1_wires[87] ) , - .prog_clk_1_S_out ( prog_clk_1_wires[88] ) , .prog_clk_2_E_in ( p2612 ) , - .prog_clk_2_W_in ( p1250 ) , + .prog_clk_1_S_out ( prog_clk_1_wires[88] ) , .prog_clk_2_E_in ( p3243 ) , + .prog_clk_2_W_in ( p3192 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6257 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6258 ) , - .prog_clk_3_W_in ( p3244 ) , .prog_clk_3_E_in ( p1038 ) , + .prog_clk_3_W_in ( p3279 ) , .prog_clk_3_E_in ( p3184 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6259 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6260 ) , .clk_1_W_in ( SYNOPSYS_UNCONNECTED_6261 ) , .clk_1_E_in ( clk_1_wires[86] ) , .clk_1_N_out ( clk_1_wires[87] ) , - .clk_1_S_out ( clk_1_wires[88] ) , .clk_2_E_in ( p2612 ) , - .clk_2_W_in ( p3231 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6262 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6263 ) , .clk_3_W_in ( p2653 ) , - .clk_3_E_in ( p2598 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6264 ) , + .clk_1_S_out ( clk_1_wires[88] ) , .clk_2_E_in ( p1624 ) , + .clk_2_W_in ( p3362 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6262 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6263 ) , .clk_3_W_in ( p3396 ) , + .clk_3_E_in ( p284 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6264 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6265 ) ) ; cbx_1__1_ cbx_5__2_ ( .pReset ( { SYNOPSYS_UNCONNECTED_6266 } ) , @@ -119857,7 +124379,7 @@ cbx_1__1_ cbx_5__2_ ( .bottom_grid_pin_14_ ( cbx_1__1__45_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__45_bottom_grid_pin_15_ ) , .ccff_tail ( cbx_1__1__45_ccff_tail ) , .SC_IN_TOP ( scff_Wires[126] ) , - .SC_OUT_BOT ( scff_Wires[127] ) , .SC_IN_BOT ( p1457 ) , + .SC_OUT_BOT ( scff_Wires[127] ) , .SC_IN_BOT ( p2280 ) , .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_6267 ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[45] ) , .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[45] ) , @@ -119869,23 +124391,23 @@ cbx_1__1_ cbx_5__2_ ( .pReset_E_out ( SYNOPSYS_UNCONNECTED_6269 ) , .prog_clk_0_N_in ( prog_clk_0_wires[183] ) , .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6270 ) , - .prog_clk_1_W_in ( p1870 ) , .prog_clk_1_E_in ( p1711 ) , + .prog_clk_1_W_in ( p1500 ) , .prog_clk_1_E_in ( p2092 ) , .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_6271 ) , .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_6272 ) , .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_6273 ) , .prog_clk_2_W_in ( prog_clk_2_wires[25] ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6274 ) , - .prog_clk_2_E_out ( prog_clk_2_wires[26] ) , .prog_clk_3_W_in ( p1919 ) , - .prog_clk_3_E_in ( p952 ) , + .prog_clk_2_E_out ( prog_clk_2_wires[26] ) , .prog_clk_3_W_in ( p1990 ) , + .prog_clk_3_E_in ( p906 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6275 ) , - .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6276 ) , .clk_1_W_in ( p1167 ) , - .clk_1_E_in ( p636 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_6277 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6276 ) , .clk_1_W_in ( p1934 ) , + .clk_1_E_in ( p927 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_6277 ) , .clk_1_S_out ( SYNOPSYS_UNCONNECTED_6278 ) , .clk_2_E_in ( SYNOPSYS_UNCONNECTED_6279 ) , .clk_2_W_in ( clk_2_wires[25] ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6280 ) , - .clk_2_E_out ( clk_2_wires[26] ) , .clk_3_W_in ( p1919 ) , - .clk_3_E_in ( p1749 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6281 ) , + .clk_2_E_out ( clk_2_wires[26] ) , .clk_3_W_in ( p1990 ) , + .clk_3_E_in ( p244 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6281 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6282 ) ) ; cbx_1__1_ cbx_5__3_ ( .pReset ( { SYNOPSYS_UNCONNECTED_6283 } ) , @@ -119911,7 +124433,7 @@ cbx_1__1_ cbx_5__3_ ( .bottom_grid_pin_14_ ( cbx_1__1__46_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__46_bottom_grid_pin_15_ ) , .ccff_tail ( cbx_1__1__46_ccff_tail ) , .SC_IN_TOP ( scff_Wires[124] ) , - .SC_OUT_BOT ( scff_Wires[125] ) , .SC_IN_BOT ( p1769 ) , + .SC_OUT_BOT ( scff_Wires[125] ) , .SC_IN_BOT ( p1616 ) , .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_6284 ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[46] ) , .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[46] ) , @@ -119926,19 +124448,19 @@ cbx_1__1_ cbx_5__3_ ( .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_6288 ) , .prog_clk_1_E_in ( prog_clk_1_wires[93] ) , .prog_clk_1_N_out ( prog_clk_1_wires[94] ) , - .prog_clk_1_S_out ( prog_clk_1_wires[95] ) , .prog_clk_2_E_in ( p1492 ) , - .prog_clk_2_W_in ( p734 ) , + .prog_clk_1_S_out ( prog_clk_1_wires[95] ) , .prog_clk_2_E_in ( p3015 ) , + .prog_clk_2_W_in ( p3378 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6289 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6290 ) , - .prog_clk_3_W_in ( p2774 ) , .prog_clk_3_E_in ( p592 ) , + .prog_clk_3_W_in ( p3421 ) , .prog_clk_3_E_in ( p2891 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6291 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6292 ) , .clk_1_W_in ( SYNOPSYS_UNCONNECTED_6293 ) , .clk_1_E_in ( clk_1_wires[93] ) , .clk_1_N_out ( clk_1_wires[94] ) , - .clk_1_S_out ( clk_1_wires[95] ) , .clk_2_E_in ( p1492 ) , - .clk_2_W_in ( p2870 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6294 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6295 ) , .clk_3_W_in ( p2995 ) , - .clk_3_E_in ( p1067 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6296 ) , + .clk_1_S_out ( clk_1_wires[95] ) , .clk_2_E_in ( p2526 ) , + .clk_2_W_in ( p3317 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6294 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6295 ) , .clk_3_W_in ( p3336 ) , + .clk_3_E_in ( p2476 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6296 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6297 ) ) ; cbx_1__1_ cbx_5__4_ ( .pReset ( { SYNOPSYS_UNCONNECTED_6298 } ) , @@ -119964,7 +124486,7 @@ cbx_1__1_ cbx_5__4_ ( .bottom_grid_pin_14_ ( cbx_1__1__47_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__47_bottom_grid_pin_15_ ) , .ccff_tail ( cbx_1__1__47_ccff_tail ) , .SC_IN_TOP ( scff_Wires[122] ) , - .SC_OUT_BOT ( scff_Wires[123] ) , .SC_IN_BOT ( p1790 ) , + .SC_OUT_BOT ( scff_Wires[123] ) , .SC_IN_BOT ( p1576 ) , .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_6299 ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[47] ) , .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[47] ) , @@ -119976,23 +124498,23 @@ cbx_1__1_ cbx_5__4_ ( .pReset_E_out ( SYNOPSYS_UNCONNECTED_6301 ) , .prog_clk_0_N_in ( prog_clk_0_wires[189] ) , .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6302 ) , - .prog_clk_1_W_in ( p1224 ) , .prog_clk_1_E_in ( p319 ) , + .prog_clk_1_W_in ( p1457 ) , .prog_clk_1_E_in ( p622 ) , .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_6303 ) , .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_6304 ) , .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_6305 ) , .prog_clk_2_W_in ( prog_clk_2_wires[34] ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6306 ) , - .prog_clk_2_E_out ( prog_clk_2_wires[35] ) , .prog_clk_3_W_in ( p1224 ) , - .prog_clk_3_E_in ( p244 ) , + .prog_clk_2_E_out ( prog_clk_2_wires[35] ) , .prog_clk_3_W_in ( p1041 ) , + .prog_clk_3_E_in ( p984 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6307 ) , - .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6308 ) , .clk_1_W_in ( p1528 ) , - .clk_1_E_in ( p1714 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_6309 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6308 ) , .clk_1_W_in ( p1041 ) , + .clk_1_E_in ( p604 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_6309 ) , .clk_1_S_out ( SYNOPSYS_UNCONNECTED_6310 ) , .clk_2_E_in ( SYNOPSYS_UNCONNECTED_6311 ) , .clk_2_W_in ( clk_2_wires[34] ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6312 ) , - .clk_2_E_out ( clk_2_wires[35] ) , .clk_3_W_in ( p1224 ) , - .clk_3_E_in ( p1156 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6313 ) , + .clk_2_E_out ( clk_2_wires[35] ) , .clk_3_W_in ( p1041 ) , + .clk_3_E_in ( p328 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6313 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6314 ) ) ; cbx_1__1_ cbx_5__5_ ( .pReset ( { SYNOPSYS_UNCONNECTED_6315 } ) , @@ -120018,7 +124540,7 @@ cbx_1__1_ cbx_5__5_ ( .bottom_grid_pin_14_ ( cbx_1__1__48_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__48_bottom_grid_pin_15_ ) , .ccff_tail ( cbx_1__1__48_ccff_tail ) , .SC_IN_TOP ( scff_Wires[120] ) , - .SC_OUT_BOT ( scff_Wires[121] ) , .SC_IN_BOT ( p1351 ) , + .SC_OUT_BOT ( scff_Wires[121] ) , .SC_IN_BOT ( p1350 ) , .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_6316 ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[48] ) , .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[48] ) , @@ -120033,19 +124555,19 @@ cbx_1__1_ cbx_5__5_ ( .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_6320 ) , .prog_clk_1_E_in ( prog_clk_1_wires[100] ) , .prog_clk_1_N_out ( prog_clk_1_wires[101] ) , - .prog_clk_1_S_out ( prog_clk_1_wires[102] ) , .prog_clk_2_E_in ( p1900 ) , - .prog_clk_2_W_in ( p270 ) , + .prog_clk_1_S_out ( prog_clk_1_wires[102] ) , .prog_clk_2_E_in ( p3397 ) , + .prog_clk_2_W_in ( p1800 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6321 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6322 ) , - .prog_clk_3_W_in ( p2167 ) , .prog_clk_3_E_in ( p1217 ) , + .prog_clk_3_W_in ( p2049 ) , .prog_clk_3_E_in ( p3377 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6323 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6324 ) , .clk_1_W_in ( SYNOPSYS_UNCONNECTED_6325 ) , .clk_1_E_in ( clk_1_wires[100] ) , .clk_1_N_out ( clk_1_wires[101] ) , - .clk_1_S_out ( clk_1_wires[102] ) , .clk_2_E_in ( p1900 ) , - .clk_2_W_in ( p2056 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6326 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6327 ) , .clk_3_W_in ( p1569 ) , - .clk_3_E_in ( p1695 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6328 ) , + .clk_1_S_out ( clk_1_wires[102] ) , .clk_2_E_in ( p2551 ) , + .clk_2_W_in ( p3482 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6326 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6327 ) , .clk_3_W_in ( p3508 ) , + .clk_3_E_in ( p2455 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6328 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6329 ) ) ; cbx_1__1_ cbx_5__6_ ( .pReset ( { SYNOPSYS_UNCONNECTED_6330 } ) , @@ -120071,7 +124593,7 @@ cbx_1__1_ cbx_5__6_ ( .bottom_grid_pin_14_ ( cbx_1__1__49_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__49_bottom_grid_pin_15_ ) , .ccff_tail ( cbx_1__1__49_ccff_tail ) , .SC_IN_TOP ( scff_Wires[118] ) , - .SC_OUT_BOT ( scff_Wires[119] ) , .SC_IN_BOT ( p1249 ) , + .SC_OUT_BOT ( scff_Wires[119] ) , .SC_IN_BOT ( p1483 ) , .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_6331 ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[49] ) , .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[49] ) , @@ -120083,19 +124605,19 @@ cbx_1__1_ cbx_5__6_ ( .pReset_E_out ( SYNOPSYS_UNCONNECTED_6333 ) , .prog_clk_0_N_in ( prog_clk_0_wires[195] ) , .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6334 ) , - .prog_clk_1_W_in ( p1354 ) , .prog_clk_1_E_in ( p620 ) , + .prog_clk_1_W_in ( p1342 ) , .prog_clk_1_E_in ( p327 ) , .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_6335 ) , .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_6336 ) , - .prog_clk_2_E_in ( p1393 ) , .prog_clk_2_W_in ( p50 ) , + .prog_clk_2_E_in ( p1843 ) , .prog_clk_2_W_in ( p1766 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6337 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6338 ) , .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_6339 ) , .prog_clk_3_E_in ( prog_clk_3_wires[6] ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6340 ) , - .prog_clk_3_W_out ( prog_clk_3_wires[7] ) , .clk_1_W_in ( p1154 ) , - .clk_1_E_in ( p633 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_6341 ) , - .clk_1_S_out ( SYNOPSYS_UNCONNECTED_6342 ) , .clk_2_E_in ( p1393 ) , - .clk_2_W_in ( p960 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6343 ) , + .prog_clk_3_W_out ( prog_clk_3_wires[7] ) , .clk_1_W_in ( p2000 ) , + .clk_1_E_in ( p734 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_6341 ) , + .clk_1_S_out ( SYNOPSYS_UNCONNECTED_6342 ) , .clk_2_E_in ( p1921 ) , + .clk_2_W_in ( p749 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6343 ) , .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6344 ) , .clk_3_W_in ( SYNOPSYS_UNCONNECTED_6345 ) , .clk_3_E_in ( clk_3_wires[6] ) , @@ -120125,7 +124647,7 @@ cbx_1__1_ cbx_5__7_ ( .bottom_grid_pin_14_ ( cbx_1__1__50_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__50_bottom_grid_pin_15_ ) , .ccff_tail ( cbx_1__1__50_ccff_tail ) , .SC_IN_TOP ( scff_Wires[116] ) , - .SC_OUT_BOT ( scff_Wires[117] ) , .SC_IN_BOT ( p1325 ) , + .SC_OUT_BOT ( scff_Wires[117] ) , .SC_IN_BOT ( p1153 ) , .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_6348 ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[50] ) , .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[50] ) , @@ -120140,19 +124662,19 @@ cbx_1__1_ cbx_5__7_ ( .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_6352 ) , .prog_clk_1_E_in ( prog_clk_1_wires[107] ) , .prog_clk_1_N_out ( prog_clk_1_wires[108] ) , - .prog_clk_1_S_out ( prog_clk_1_wires[109] ) , .prog_clk_2_E_in ( p1811 ) , - .prog_clk_2_W_in ( p1139 ) , + .prog_clk_1_S_out ( prog_clk_1_wires[109] ) , .prog_clk_2_E_in ( p2818 ) , + .prog_clk_2_W_in ( p2666 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6353 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6354 ) , - .prog_clk_3_W_in ( p3329 ) , .prog_clk_3_E_in ( p1055 ) , + .prog_clk_3_W_in ( p2791 ) , .prog_clk_3_E_in ( p2667 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6355 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6356 ) , .clk_1_W_in ( SYNOPSYS_UNCONNECTED_6357 ) , .clk_1_E_in ( clk_1_wires[107] ) , .clk_1_N_out ( clk_1_wires[108] ) , - .clk_1_S_out ( clk_1_wires[109] ) , .clk_2_E_in ( p1811 ) , - .clk_2_W_in ( p3297 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6358 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6359 ) , .clk_3_W_in ( p2120 ) , - .clk_3_E_in ( p1689 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6360 ) , + .clk_1_S_out ( clk_1_wires[109] ) , .clk_2_E_in ( p1609 ) , + .clk_2_W_in ( p2407 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6358 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6359 ) , .clk_3_W_in ( p2618 ) , + .clk_3_E_in ( p268 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6360 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6361 ) ) ; cbx_1__1_ cbx_5__8_ ( .pReset ( { SYNOPSYS_UNCONNECTED_6362 } ) , @@ -120178,7 +124700,7 @@ cbx_1__1_ cbx_5__8_ ( .bottom_grid_pin_14_ ( cbx_1__1__51_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__51_bottom_grid_pin_15_ ) , .ccff_tail ( cbx_1__1__51_ccff_tail ) , .SC_IN_TOP ( scff_Wires[114] ) , - .SC_OUT_BOT ( scff_Wires[115] ) , .SC_IN_BOT ( p1200 ) , + .SC_OUT_BOT ( scff_Wires[115] ) , .SC_IN_BOT ( p1586 ) , .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_6363 ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[51] ) , .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[51] ) , @@ -120190,23 +124712,23 @@ cbx_1__1_ cbx_5__8_ ( .pReset_E_out ( SYNOPSYS_UNCONNECTED_6365 ) , .prog_clk_0_N_in ( prog_clk_0_wires[201] ) , .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6366 ) , - .prog_clk_1_W_in ( p1447 ) , .prog_clk_1_E_in ( p2354 ) , + .prog_clk_1_W_in ( p924 ) , .prog_clk_1_E_in ( p533 ) , .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_6367 ) , .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_6368 ) , .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_6369 ) , .prog_clk_2_W_in ( prog_clk_2_wires[47] ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6370 ) , - .prog_clk_2_E_out ( prog_clk_2_wires[48] ) , .prog_clk_3_W_in ( p1447 ) , - .prog_clk_3_E_in ( p1281 ) , + .prog_clk_2_E_out ( prog_clk_2_wires[48] ) , .prog_clk_3_W_in ( p1353 ) , + .prog_clk_3_E_in ( p914 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6371 ) , - .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6372 ) , .clk_1_W_in ( p1365 ) , - .clk_1_E_in ( p237 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_6373 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6372 ) , .clk_1_W_in ( p1353 ) , + .clk_1_E_in ( p911 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_6373 ) , .clk_1_S_out ( SYNOPSYS_UNCONNECTED_6374 ) , .clk_2_E_in ( SYNOPSYS_UNCONNECTED_6375 ) , .clk_2_W_in ( clk_2_wires[47] ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6376 ) , - .clk_2_E_out ( clk_2_wires[48] ) , .clk_3_W_in ( p1447 ) , - .clk_3_E_in ( p2302 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6377 ) , + .clk_2_E_out ( clk_2_wires[48] ) , .clk_3_W_in ( p1353 ) , + .clk_3_E_in ( p369 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6377 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6378 ) ) ; cbx_1__1_ cbx_5__9_ ( .pReset ( { SYNOPSYS_UNCONNECTED_6379 } ) , @@ -120232,7 +124754,7 @@ cbx_1__1_ cbx_5__9_ ( .bottom_grid_pin_14_ ( cbx_1__1__52_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__52_bottom_grid_pin_15_ ) , .ccff_tail ( cbx_1__1__52_ccff_tail ) , .SC_IN_TOP ( scff_Wires[112] ) , - .SC_OUT_BOT ( scff_Wires[113] ) , .SC_IN_BOT ( p1519 ) , + .SC_OUT_BOT ( scff_Wires[113] ) , .SC_IN_BOT ( p1358 ) , .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_6380 ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[52] ) , .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[52] ) , @@ -120247,19 +124769,19 @@ cbx_1__1_ cbx_5__9_ ( .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_6384 ) , .prog_clk_1_E_in ( prog_clk_1_wires[114] ) , .prog_clk_1_N_out ( prog_clk_1_wires[115] ) , - .prog_clk_1_S_out ( prog_clk_1_wires[116] ) , .prog_clk_2_E_in ( p1564 ) , - .prog_clk_2_W_in ( p371 ) , + .prog_clk_1_S_out ( prog_clk_1_wires[116] ) , .prog_clk_2_E_in ( p3098 ) , + .prog_clk_2_W_in ( p1103 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6385 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6386 ) , - .prog_clk_3_W_in ( p2105 ) , .prog_clk_3_E_in ( p1202 ) , + .prog_clk_3_W_in ( p1291 ) , .prog_clk_3_E_in ( p3065 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6387 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6388 ) , .clk_1_W_in ( SYNOPSYS_UNCONNECTED_6389 ) , .clk_1_E_in ( clk_1_wires[114] ) , .clk_1_N_out ( clk_1_wires[115] ) , - .clk_1_S_out ( clk_1_wires[116] ) , .clk_2_E_in ( p1564 ) , - .clk_2_W_in ( p2526 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6390 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6391 ) , .clk_3_W_in ( p2711 ) , - .clk_3_E_in ( p396 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6392 ) , + .clk_1_S_out ( clk_1_wires[116] ) , .clk_2_E_in ( p2269 ) , + .clk_2_W_in ( p2401 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6390 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6391 ) , .clk_3_W_in ( p2612 ) , + .clk_3_E_in ( p2166 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6392 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6393 ) ) ; cbx_1__1_ cbx_5__10_ ( .pReset ( { SYNOPSYS_UNCONNECTED_6394 } ) , @@ -120285,7 +124807,7 @@ cbx_1__1_ cbx_5__10_ ( .bottom_grid_pin_14_ ( cbx_1__1__53_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__53_bottom_grid_pin_15_ ) , .ccff_tail ( cbx_1__1__53_ccff_tail ) , .SC_IN_TOP ( scff_Wires[110] ) , - .SC_OUT_BOT ( scff_Wires[111] ) , .SC_IN_BOT ( p1062 ) , + .SC_OUT_BOT ( scff_Wires[111] ) , .SC_IN_BOT ( p1967 ) , .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_6395 ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[53] ) , .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[53] ) , @@ -120297,23 +124819,23 @@ cbx_1__1_ cbx_5__10_ ( .pReset_E_out ( SYNOPSYS_UNCONNECTED_6397 ) , .prog_clk_0_N_in ( prog_clk_0_wires[207] ) , .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6398 ) , - .prog_clk_1_W_in ( p2111 ) , .prog_clk_1_E_in ( p632 ) , + .prog_clk_1_W_in ( p1364 ) , .prog_clk_1_E_in ( p1734 ) , .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_6399 ) , .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_6400 ) , .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_6401 ) , .prog_clk_2_W_in ( prog_clk_2_wires[60] ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6402 ) , - .prog_clk_2_E_out ( prog_clk_2_wires[61] ) , .prog_clk_3_W_in ( p2128 ) , - .prog_clk_3_E_in ( p187 ) , + .prog_clk_2_E_out ( prog_clk_2_wires[61] ) , .prog_clk_3_W_in ( p1319 ) , + .prog_clk_3_E_in ( p1094 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6403 ) , - .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6404 ) , .clk_1_W_in ( p1432 ) , - .clk_1_E_in ( p473 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_6405 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6404 ) , .clk_1_W_in ( p1319 ) , + .clk_1_E_in ( p1744 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_6405 ) , .clk_1_S_out ( SYNOPSYS_UNCONNECTED_6406 ) , .clk_2_E_in ( SYNOPSYS_UNCONNECTED_6407 ) , .clk_2_W_in ( clk_2_wires[60] ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6408 ) , - .clk_2_E_out ( clk_2_wires[61] ) , .clk_3_W_in ( p2128 ) , - .clk_3_E_in ( p1278 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6409 ) , + .clk_2_E_out ( clk_2_wires[61] ) , .clk_3_W_in ( p1319 ) , + .clk_3_E_in ( p1767 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6409 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6410 ) ) ; cbx_1__1_ cbx_5__11_ ( .pReset ( { SYNOPSYS_UNCONNECTED_6411 } ) , @@ -120339,7 +124861,7 @@ cbx_1__1_ cbx_5__11_ ( .bottom_grid_pin_14_ ( cbx_1__1__54_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__54_bottom_grid_pin_15_ ) , .ccff_tail ( cbx_1__1__54_ccff_tail ) , .SC_IN_TOP ( scff_Wires[108] ) , - .SC_OUT_BOT ( scff_Wires[109] ) , .SC_IN_BOT ( p1436 ) , + .SC_OUT_BOT ( scff_Wires[109] ) , .SC_IN_BOT ( p1289 ) , .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_6412 ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[54] ) , .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[54] ) , @@ -120354,19 +124876,19 @@ cbx_1__1_ cbx_5__11_ ( .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_6416 ) , .prog_clk_1_E_in ( prog_clk_1_wires[121] ) , .prog_clk_1_N_out ( prog_clk_1_wires[122] ) , - .prog_clk_1_S_out ( prog_clk_1_wires[123] ) , .prog_clk_2_E_in ( p2241 ) , - .prog_clk_2_W_in ( p757 ) , + .prog_clk_1_S_out ( prog_clk_1_wires[123] ) , .prog_clk_2_E_in ( p2810 ) , + .prog_clk_2_W_in ( p3446 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6417 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6418 ) , - .prog_clk_3_W_in ( p3201 ) , .prog_clk_3_E_in ( p207 ) , + .prog_clk_3_W_in ( p3457 ) , .prog_clk_3_E_in ( p2736 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6419 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6420 ) , .clk_1_W_in ( SYNOPSYS_UNCONNECTED_6421 ) , .clk_1_E_in ( clk_1_wires[121] ) , .clk_1_N_out ( clk_1_wires[122] ) , - .clk_1_S_out ( clk_1_wires[123] ) , .clk_2_E_in ( p2241 ) , - .clk_2_W_in ( p3116 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6422 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6423 ) , .clk_3_W_in ( p2830 ) , - .clk_3_E_in ( p2020 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6424 ) , + .clk_1_S_out ( clk_1_wires[123] ) , .clk_2_E_in ( p3013 ) , + .clk_2_W_in ( p951 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6422 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6423 ) , .clk_3_W_in ( p1349 ) , + .clk_3_E_in ( p2911 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6424 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6425 ) ) ; cbx_1__1_ cbx_6__1_ ( .pReset ( { SYNOPSYS_UNCONNECTED_6426 } ) , @@ -120391,7 +124913,7 @@ cbx_1__1_ cbx_6__1_ ( .bottom_grid_pin_13_ ( cbx_1__1__55_bottom_grid_pin_13_ ) , .bottom_grid_pin_14_ ( cbx_1__1__55_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__55_bottom_grid_pin_15_ ) , - .ccff_tail ( cbx_1__1__55_ccff_tail ) , .SC_IN_TOP ( p1930 ) , + .ccff_tail ( cbx_1__1__55_ccff_tail ) , .SC_IN_TOP ( p1996 ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_6427 ) , .SC_IN_BOT ( scff_Wires[135] ) , .SC_OUT_TOP ( scff_Wires[136] ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[55] ) , @@ -120407,20 +124929,20 @@ cbx_1__1_ cbx_6__1_ ( .prog_clk_1_W_in ( prog_clk_1_wires[85] ) , .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_6431 ) , .prog_clk_1_N_out ( prog_clk_1_wires[89] ) , - .prog_clk_1_S_out ( prog_clk_1_wires[90] ) , .prog_clk_2_E_in ( p1529 ) , - .prog_clk_2_W_in ( p562 ) , + .prog_clk_1_S_out ( prog_clk_1_wires[90] ) , .prog_clk_2_E_in ( p1846 ) , + .prog_clk_2_W_in ( p3211 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6432 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6433 ) , - .prog_clk_3_W_in ( p2215 ) , .prog_clk_3_E_in ( p1644 ) , + .prog_clk_3_W_in ( p3278 ) , .prog_clk_3_E_in ( p1785 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6434 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6435 ) , .clk_1_W_in ( clk_1_wires[85] ) , .clk_1_E_in ( SYNOPSYS_UNCONNECTED_6436 ) , .clk_1_N_out ( clk_1_wires[89] ) , .clk_1_S_out ( clk_1_wires[90] ) , - .clk_2_E_in ( p1529 ) , .clk_2_W_in ( p2910 ) , + .clk_2_E_in ( p2786 ) , .clk_2_W_in ( p2933 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6437 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6438 ) , .clk_3_W_in ( p2939 ) , - .clk_3_E_in ( p79 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6439 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6438 ) , .clk_3_W_in ( p2986 ) , + .clk_3_E_in ( p2664 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6439 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6440 ) ) ; cbx_1__1_ cbx_6__2_ ( .pReset ( { SYNOPSYS_UNCONNECTED_6441 } ) , @@ -120445,7 +124967,7 @@ cbx_1__1_ cbx_6__2_ ( .bottom_grid_pin_13_ ( cbx_1__1__56_bottom_grid_pin_13_ ) , .bottom_grid_pin_14_ ( cbx_1__1__56_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__56_bottom_grid_pin_15_ ) , - .ccff_tail ( cbx_1__1__56_ccff_tail ) , .SC_IN_TOP ( p1922 ) , + .ccff_tail ( cbx_1__1__56_ccff_tail ) , .SC_IN_TOP ( p1855 ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_6442 ) , .SC_IN_BOT ( scff_Wires[137] ) , .SC_OUT_TOP ( scff_Wires[138] ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[56] ) , @@ -120458,20 +124980,20 @@ cbx_1__1_ cbx_6__2_ ( .pReset_E_out ( SYNOPSYS_UNCONNECTED_6444 ) , .prog_clk_0_N_in ( prog_clk_0_wires[221] ) , .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6445 ) , - .prog_clk_1_W_in ( p2398 ) , .prog_clk_1_E_in ( p930 ) , + .prog_clk_1_W_in ( p1421 ) , .prog_clk_1_E_in ( p271 ) , .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_6446 ) , .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_6447 ) , - .prog_clk_2_E_in ( p2235 ) , .prog_clk_2_W_in ( p2292 ) , + .prog_clk_2_E_in ( p3030 ) , .prog_clk_2_W_in ( p2895 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6448 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6449 ) , - .prog_clk_3_W_in ( p3108 ) , .prog_clk_3_E_in ( p1726 ) , + .prog_clk_3_W_in ( p3017 ) , .prog_clk_3_E_in ( p2893 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6450 ) , - .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6451 ) , .clk_1_W_in ( p1111 ) , - .clk_1_E_in ( p476 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_6452 ) , - .clk_1_S_out ( SYNOPSYS_UNCONNECTED_6453 ) , .clk_2_E_in ( p2235 ) , - .clk_2_W_in ( p3016 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6454 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6455 ) , .clk_3_W_in ( p2180 ) , - .clk_3_E_in ( p2042 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6456 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6451 ) , .clk_1_W_in ( p1509 ) , + .clk_1_E_in ( p817 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_6452 ) , + .clk_1_S_out ( SYNOPSYS_UNCONNECTED_6453 ) , .clk_2_E_in ( p2333 ) , + .clk_2_W_in ( p2475 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6454 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6455 ) , .clk_3_W_in ( p2636 ) , + .clk_3_E_in ( p2079 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6456 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6457 ) ) ; cbx_1__1_ cbx_6__3_ ( .pReset ( { SYNOPSYS_UNCONNECTED_6458 } ) , @@ -120496,7 +125018,7 @@ cbx_1__1_ cbx_6__3_ ( .bottom_grid_pin_13_ ( cbx_1__1__57_bottom_grid_pin_13_ ) , .bottom_grid_pin_14_ ( cbx_1__1__57_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__57_bottom_grid_pin_15_ ) , - .ccff_tail ( cbx_1__1__57_ccff_tail ) , .SC_IN_TOP ( p2626 ) , + .ccff_tail ( cbx_1__1__57_ccff_tail ) , .SC_IN_TOP ( p1443 ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_6459 ) , .SC_IN_BOT ( scff_Wires[139] ) , .SC_OUT_TOP ( scff_Wires[140] ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[57] ) , @@ -120512,20 +125034,20 @@ cbx_1__1_ cbx_6__3_ ( .prog_clk_1_W_in ( prog_clk_1_wires[92] ) , .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_6463 ) , .prog_clk_1_N_out ( prog_clk_1_wires[96] ) , - .prog_clk_1_S_out ( prog_clk_1_wires[97] ) , .prog_clk_2_E_in ( p1865 ) , - .prog_clk_2_W_in ( p698 ) , + .prog_clk_1_S_out ( prog_clk_1_wires[97] ) , .prog_clk_2_E_in ( p2363 ) , + .prog_clk_2_W_in ( p1797 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6464 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6465 ) , - .prog_clk_3_W_in ( p3310 ) , .prog_clk_3_E_in ( p2550 ) , + .prog_clk_3_W_in ( p1923 ) , .prog_clk_3_E_in ( p2134 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6466 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6467 ) , .clk_1_W_in ( clk_1_wires[92] ) , .clk_1_E_in ( SYNOPSYS_UNCONNECTED_6468 ) , .clk_1_N_out ( clk_1_wires[96] ) , .clk_1_S_out ( clk_1_wires[97] ) , - .clk_2_E_in ( p1865 ) , .clk_2_W_in ( p3281 ) , + .clk_2_E_in ( p2299 ) , .clk_2_W_in ( p2394 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6469 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6470 ) , .clk_3_W_in ( p3194 ) , - .clk_3_E_in ( p1736 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6471 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6470 ) , .clk_3_W_in ( p2627 ) , + .clk_3_E_in ( p2175 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6471 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6472 ) ) ; cbx_1__1_ cbx_6__4_ ( .pReset ( { SYNOPSYS_UNCONNECTED_6473 } ) , @@ -120550,7 +125072,7 @@ cbx_1__1_ cbx_6__4_ ( .bottom_grid_pin_13_ ( cbx_1__1__58_bottom_grid_pin_13_ ) , .bottom_grid_pin_14_ ( cbx_1__1__58_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__58_bottom_grid_pin_15_ ) , - .ccff_tail ( cbx_1__1__58_ccff_tail ) , .SC_IN_TOP ( p2130 ) , + .ccff_tail ( cbx_1__1__58_ccff_tail ) , .SC_IN_TOP ( p1273 ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_6474 ) , .SC_IN_BOT ( scff_Wires[141] ) , .SC_OUT_TOP ( scff_Wires[142] ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[58] ) , @@ -120563,20 +125085,20 @@ cbx_1__1_ cbx_6__4_ ( .pReset_E_out ( SYNOPSYS_UNCONNECTED_6476 ) , .prog_clk_0_N_in ( prog_clk_0_wires[227] ) , .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6477 ) , - .prog_clk_1_W_in ( p2436 ) , .prog_clk_1_E_in ( p673 ) , + .prog_clk_1_W_in ( p1232 ) , .prog_clk_1_E_in ( p596 ) , .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_6478 ) , .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_6479 ) , - .prog_clk_2_E_in ( p842 ) , .prog_clk_2_W_in ( p2381 ) , + .prog_clk_2_E_in ( p2259 ) , .prog_clk_2_W_in ( p3183 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6480 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6481 ) , - .prog_clk_3_W_in ( p3051 ) , .prog_clk_3_E_in ( p2044 ) , + .prog_clk_3_W_in ( p3231 ) , .prog_clk_3_E_in ( p2084 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6482 ) , - .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6483 ) , .clk_1_W_in ( p1293 ) , - .clk_1_E_in ( p890 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_6484 ) , - .clk_1_S_out ( SYNOPSYS_UNCONNECTED_6485 ) , .clk_2_E_in ( p842 ) , - .clk_2_W_in ( p3008 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6486 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6487 ) , .clk_3_W_in ( p2236 ) , - .clk_3_E_in ( p727 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6488 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6483 ) , .clk_1_W_in ( p1308 ) , + .clk_1_E_in ( p97 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_6484 ) , + .clk_1_S_out ( SYNOPSYS_UNCONNECTED_6485 ) , .clk_2_E_in ( p3171 ) , + .clk_2_W_in ( p3301 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6486 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6487 ) , .clk_3_W_in ( p3343 ) , + .clk_3_E_in ( p3041 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6488 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6489 ) ) ; cbx_1__1_ cbx_6__5_ ( .pReset ( { SYNOPSYS_UNCONNECTED_6490 } ) , @@ -120601,7 +125123,7 @@ cbx_1__1_ cbx_6__5_ ( .bottom_grid_pin_13_ ( cbx_1__1__59_bottom_grid_pin_13_ ) , .bottom_grid_pin_14_ ( cbx_1__1__59_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__59_bottom_grid_pin_15_ ) , - .ccff_tail ( cbx_1__1__59_ccff_tail ) , .SC_IN_TOP ( p2413 ) , + .ccff_tail ( cbx_1__1__59_ccff_tail ) , .SC_IN_TOP ( p1559 ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_6491 ) , .SC_IN_BOT ( scff_Wires[143] ) , .SC_OUT_TOP ( scff_Wires[144] ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[59] ) , @@ -120617,20 +125139,20 @@ cbx_1__1_ cbx_6__5_ ( .prog_clk_1_W_in ( prog_clk_1_wires[99] ) , .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_6495 ) , .prog_clk_1_N_out ( prog_clk_1_wires[103] ) , - .prog_clk_1_S_out ( prog_clk_1_wires[104] ) , .prog_clk_2_E_in ( p2675 ) , - .prog_clk_2_W_in ( p939 ) , + .prog_clk_1_S_out ( prog_clk_1_wires[104] ) , .prog_clk_2_E_in ( p1505 ) , + .prog_clk_2_W_in ( p2658 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6496 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6497 ) , - .prog_clk_3_W_in ( p3063 ) , .prog_clk_3_E_in ( p2384 ) , + .prog_clk_3_W_in ( p2750 ) , .prog_clk_3_E_in ( p618 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6498 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6499 ) , .clk_1_W_in ( clk_1_wires[99] ) , .clk_1_E_in ( SYNOPSYS_UNCONNECTED_6500 ) , .clk_1_N_out ( clk_1_wires[103] ) , .clk_1_S_out ( clk_1_wires[104] ) , - .clk_2_E_in ( p2675 ) , .clk_2_W_in ( p3022 ) , + .clk_2_E_in ( p1958 ) , .clk_2_W_in ( p3087 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6501 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6502 ) , .clk_3_W_in ( p2983 ) , - .clk_3_E_in ( p2569 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6503 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6502 ) , .clk_3_W_in ( p3122 ) , + .clk_3_E_in ( p1742 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6503 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6504 ) ) ; cbx_1__1_ cbx_6__6_ ( .pReset ( { SYNOPSYS_UNCONNECTED_6505 } ) , @@ -120655,7 +125177,7 @@ cbx_1__1_ cbx_6__6_ ( .bottom_grid_pin_13_ ( cbx_1__1__60_bottom_grid_pin_13_ ) , .bottom_grid_pin_14_ ( cbx_1__1__60_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__60_bottom_grid_pin_15_ ) , - .ccff_tail ( cbx_1__1__60_ccff_tail ) , .SC_IN_TOP ( p1835 ) , + .ccff_tail ( cbx_1__1__60_ccff_tail ) , .SC_IN_TOP ( p2017 ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_6506 ) , .SC_IN_BOT ( scff_Wires[145] ) , .SC_OUT_TOP ( scff_Wires[146] ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[60] ) , @@ -120668,19 +125190,19 @@ cbx_1__1_ cbx_6__6_ ( .pReset_E_out ( SYNOPSYS_UNCONNECTED_6508 ) , .prog_clk_0_N_in ( prog_clk_0_wires[233] ) , .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6509 ) , - .prog_clk_1_W_in ( p1858 ) , .prog_clk_1_E_in ( p677 ) , + .prog_clk_1_W_in ( p1626 ) , .prog_clk_1_E_in ( p499 ) , .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_6510 ) , .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_6511 ) , - .prog_clk_2_E_in ( p1835 ) , .prog_clk_2_W_in ( p1683 ) , + .prog_clk_2_E_in ( p2206 ) , .prog_clk_2_W_in ( p1731 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6512 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6513 ) , .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_6514 ) , .prog_clk_3_E_in ( prog_clk_3_wires[2] ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6515 ) , - .prog_clk_3_W_out ( prog_clk_3_wires[3] ) , .clk_1_W_in ( p1426 ) , - .clk_1_E_in ( p532 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_6516 ) , - .clk_1_S_out ( SYNOPSYS_UNCONNECTED_6517 ) , .clk_2_E_in ( p1835 ) , - .clk_2_W_in ( p1109 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6518 ) , + .prog_clk_3_W_out ( prog_clk_3_wires[3] ) , .clk_1_W_in ( p2030 ) , + .clk_1_E_in ( p200 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_6516 ) , + .clk_1_S_out ( SYNOPSYS_UNCONNECTED_6517 ) , .clk_2_E_in ( p2239 ) , + .clk_2_W_in ( p943 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6518 ) , .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6519 ) , .clk_3_W_in ( SYNOPSYS_UNCONNECTED_6520 ) , .clk_3_E_in ( clk_3_wires[2] ) , @@ -120709,7 +125231,7 @@ cbx_1__1_ cbx_6__7_ ( .bottom_grid_pin_13_ ( cbx_1__1__61_bottom_grid_pin_13_ ) , .bottom_grid_pin_14_ ( cbx_1__1__61_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__61_bottom_grid_pin_15_ ) , - .ccff_tail ( cbx_1__1__61_ccff_tail ) , .SC_IN_TOP ( p2649 ) , + .ccff_tail ( cbx_1__1__61_ccff_tail ) , .SC_IN_TOP ( p2256 ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_6523 ) , .SC_IN_BOT ( scff_Wires[147] ) , .SC_OUT_TOP ( scff_Wires[148] ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[61] ) , @@ -120725,20 +125247,20 @@ cbx_1__1_ cbx_6__7_ ( .prog_clk_1_W_in ( prog_clk_1_wires[106] ) , .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_6527 ) , .prog_clk_1_N_out ( prog_clk_1_wires[110] ) , - .prog_clk_1_S_out ( prog_clk_1_wires[111] ) , .prog_clk_2_E_in ( p1559 ) , - .prog_clk_2_W_in ( p988 ) , + .prog_clk_1_S_out ( prog_clk_1_wires[111] ) , .prog_clk_2_E_in ( p2620 ) , + .prog_clk_2_W_in ( p2444 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6528 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6529 ) , - .prog_clk_3_W_in ( p1954 ) , .prog_clk_3_E_in ( p2535 ) , + .prog_clk_3_W_in ( p2614 ) , .prog_clk_3_E_in ( p2489 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6530 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6531 ) , .clk_1_W_in ( clk_1_wires[106] ) , .clk_1_E_in ( SYNOPSYS_UNCONNECTED_6532 ) , .clk_1_N_out ( clk_1_wires[110] ) , .clk_1_S_out ( clk_1_wires[111] ) , - .clk_2_E_in ( p1559 ) , .clk_2_W_in ( p1628 ) , + .clk_2_E_in ( p2846 ) , .clk_2_W_in ( p2677 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6533 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6534 ) , .clk_3_W_in ( p1341 ) , - .clk_3_E_in ( p549 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6535 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6534 ) , .clk_3_W_in ( p2848 ) , + .clk_3_E_in ( p2726 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6535 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6536 ) ) ; cbx_1__1_ cbx_6__8_ ( .pReset ( { SYNOPSYS_UNCONNECTED_6537 } ) , @@ -120763,7 +125285,7 @@ cbx_1__1_ cbx_6__8_ ( .bottom_grid_pin_13_ ( cbx_1__1__62_bottom_grid_pin_13_ ) , .bottom_grid_pin_14_ ( cbx_1__1__62_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__62_bottom_grid_pin_15_ ) , - .ccff_tail ( cbx_1__1__62_ccff_tail ) , .SC_IN_TOP ( p1538 ) , + .ccff_tail ( cbx_1__1__62_ccff_tail ) , .SC_IN_TOP ( p2006 ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_6538 ) , .SC_IN_BOT ( scff_Wires[149] ) , .SC_OUT_TOP ( scff_Wires[150] ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[62] ) , @@ -120776,20 +125298,20 @@ cbx_1__1_ cbx_6__8_ ( .pReset_E_out ( SYNOPSYS_UNCONNECTED_6540 ) , .prog_clk_0_N_in ( prog_clk_0_wires[239] ) , .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6541 ) , - .prog_clk_1_W_in ( p2447 ) , .prog_clk_1_E_in ( p218 ) , + .prog_clk_1_W_in ( p1407 ) , .prog_clk_1_E_in ( p552 ) , .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_6542 ) , .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_6543 ) , - .prog_clk_2_E_in ( p1943 ) , .prog_clk_2_W_in ( p2371 ) , + .prog_clk_2_E_in ( p3329 ) , .prog_clk_2_W_in ( p2700 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6544 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6545 ) , - .prog_clk_3_W_in ( p1619 ) , .prog_clk_3_E_in ( p1041 ) , + .prog_clk_3_W_in ( p2777 ) , .prog_clk_3_E_in ( p3288 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6546 ) , - .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6547 ) , .clk_1_W_in ( p994 ) , - .clk_1_E_in ( p624 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_6548 ) , - .clk_1_S_out ( SYNOPSYS_UNCONNECTED_6549 ) , .clk_2_E_in ( p1943 ) , - .clk_2_W_in ( p2738 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6550 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6551 ) , .clk_3_W_in ( p2781 ) , - .clk_3_E_in ( p1722 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6552 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6547 ) , .clk_1_W_in ( p1550 ) , + .clk_1_E_in ( p697 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_6548 ) , + .clk_1_S_out ( SYNOPSYS_UNCONNECTED_6549 ) , .clk_2_E_in ( p1588 ) , + .clk_2_W_in ( p3185 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6550 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6551 ) , .clk_3_W_in ( p3237 ) , + .clk_3_E_in ( p929 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6552 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6553 ) ) ; cbx_1__1_ cbx_6__9_ ( .pReset ( { SYNOPSYS_UNCONNECTED_6554 } ) , @@ -120814,7 +125336,7 @@ cbx_1__1_ cbx_6__9_ ( .bottom_grid_pin_13_ ( cbx_1__1__63_bottom_grid_pin_13_ ) , .bottom_grid_pin_14_ ( cbx_1__1__63_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__63_bottom_grid_pin_15_ ) , - .ccff_tail ( cbx_1__1__63_ccff_tail ) , .SC_IN_TOP ( p2199 ) , + .ccff_tail ( cbx_1__1__63_ccff_tail ) , .SC_IN_TOP ( p1321 ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_6555 ) , .SC_IN_BOT ( scff_Wires[151] ) , .SC_OUT_TOP ( scff_Wires[152] ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[63] ) , @@ -120830,20 +125352,20 @@ cbx_1__1_ cbx_6__9_ ( .prog_clk_1_W_in ( prog_clk_1_wires[113] ) , .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_6559 ) , .prog_clk_1_N_out ( prog_clk_1_wires[117] ) , - .prog_clk_1_S_out ( prog_clk_1_wires[118] ) , .prog_clk_2_E_in ( p2155 ) , - .prog_clk_2_W_in ( p430 ) , + .prog_clk_1_S_out ( prog_clk_1_wires[118] ) , .prog_clk_2_E_in ( p2641 ) , + .prog_clk_2_W_in ( p2717 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6560 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6561 ) , - .prog_clk_3_W_in ( p3312 ) , .prog_clk_3_E_in ( p2078 ) , + .prog_clk_3_W_in ( p2851 ) , .prog_clk_3_E_in ( p2423 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6562 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6563 ) , .clk_1_W_in ( clk_1_wires[113] ) , .clk_1_E_in ( SYNOPSYS_UNCONNECTED_6564 ) , .clk_1_N_out ( clk_1_wires[117] ) , .clk_1_S_out ( clk_1_wires[118] ) , - .clk_2_E_in ( p2155 ) , .clk_2_W_in ( p3280 ) , + .clk_2_E_in ( p2229 ) , .clk_2_W_in ( p3443 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6565 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6566 ) , .clk_3_W_in ( p2251 ) , - .clk_3_E_in ( p2059 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6567 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6566 ) , .clk_3_W_in ( p3459 ) , + .clk_3_E_in ( p2176 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6567 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6568 ) ) ; cbx_1__1_ cbx_6__10_ ( .pReset ( { SYNOPSYS_UNCONNECTED_6569 } ) , @@ -120868,7 +125390,7 @@ cbx_1__1_ cbx_6__10_ ( .bottom_grid_pin_13_ ( cbx_1__1__64_bottom_grid_pin_13_ ) , .bottom_grid_pin_14_ ( cbx_1__1__64_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__64_bottom_grid_pin_15_ ) , - .ccff_tail ( cbx_1__1__64_ccff_tail ) , .SC_IN_TOP ( p2219 ) , + .ccff_tail ( cbx_1__1__64_ccff_tail ) , .SC_IN_TOP ( p1380 ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_6570 ) , .SC_IN_BOT ( scff_Wires[153] ) , .SC_OUT_TOP ( scff_Wires[154] ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[64] ) , @@ -120881,20 +125403,20 @@ cbx_1__1_ cbx_6__10_ ( .pReset_E_out ( SYNOPSYS_UNCONNECTED_6572 ) , .prog_clk_0_N_in ( prog_clk_0_wires[245] ) , .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6573 ) , - .prog_clk_1_W_in ( p1815 ) , .prog_clk_1_E_in ( p119 ) , + .prog_clk_1_W_in ( p1530 ) , .prog_clk_1_E_in ( p124 ) , .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_6574 ) , .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_6575 ) , - .prog_clk_2_E_in ( p1405 ) , .prog_clk_2_W_in ( p1743 ) , + .prog_clk_2_E_in ( p2970 ) , .prog_clk_2_W_in ( p1790 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6576 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6577 ) , - .prog_clk_3_W_in ( p2629 ) , .prog_clk_3_E_in ( p2053 ) , + .prog_clk_3_W_in ( p1992 ) , .prog_clk_3_E_in ( p2924 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6578 ) , - .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6579 ) , .clk_1_W_in ( p1483 ) , - .clk_1_E_in ( p665 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_6580 ) , - .clk_1_S_out ( SYNOPSYS_UNCONNECTED_6581 ) , .clk_2_E_in ( p1405 ) , - .clk_2_W_in ( p2572 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6582 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6583 ) , .clk_3_W_in ( p2429 ) , - .clk_3_E_in ( p1021 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6584 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6579 ) , .clk_1_W_in ( p1940 ) , + .clk_1_E_in ( p222 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_6580 ) , + .clk_1_S_out ( SYNOPSYS_UNCONNECTED_6581 ) , .clk_2_E_in ( p1814 ) , + .clk_2_W_in ( p1719 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6582 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6583 ) , .clk_3_W_in ( p1970 ) , + .clk_3_E_in ( p1824 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6584 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6585 ) ) ; cbx_1__1_ cbx_6__11_ ( .pReset ( { SYNOPSYS_UNCONNECTED_6586 } ) , @@ -120919,7 +125441,7 @@ cbx_1__1_ cbx_6__11_ ( .bottom_grid_pin_13_ ( cbx_1__1__65_bottom_grid_pin_13_ ) , .bottom_grid_pin_14_ ( cbx_1__1__65_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__65_bottom_grid_pin_15_ ) , - .ccff_tail ( cbx_1__1__65_ccff_tail ) , .SC_IN_TOP ( p2171 ) , + .ccff_tail ( cbx_1__1__65_ccff_tail ) , .SC_IN_TOP ( p2373 ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_6587 ) , .SC_IN_BOT ( scff_Wires[155] ) , .SC_OUT_TOP ( scff_Wires[156] ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[65] ) , @@ -120935,20 +125457,20 @@ cbx_1__1_ cbx_6__11_ ( .prog_clk_1_W_in ( prog_clk_1_wires[120] ) , .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_6591 ) , .prog_clk_1_N_out ( prog_clk_1_wires[124] ) , - .prog_clk_1_S_out ( prog_clk_1_wires[125] ) , .prog_clk_2_E_in ( p2701 ) , - .prog_clk_2_W_in ( p693 ) , + .prog_clk_1_S_out ( prog_clk_1_wires[125] ) , .prog_clk_2_E_in ( p3147 ) , + .prog_clk_2_W_in ( p3297 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6592 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6593 ) , - .prog_clk_3_W_in ( p3104 ) , .prog_clk_3_E_in ( p2014 ) , + .prog_clk_3_W_in ( p3357 ) , .prog_clk_3_E_in ( p3060 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6594 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6595 ) , .clk_1_W_in ( clk_1_wires[120] ) , .clk_1_E_in ( SYNOPSYS_UNCONNECTED_6596 ) , .clk_1_N_out ( clk_1_wires[124] ) , .clk_1_S_out ( clk_1_wires[125] ) , - .clk_2_E_in ( p2701 ) , .clk_2_W_in ( p3042 ) , + .clk_2_E_in ( p3152 ) , .clk_2_W_in ( p2479 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6597 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6598 ) , .clk_3_W_in ( p2618 ) , - .clk_3_E_in ( p2567 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6599 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6598 ) , .clk_3_W_in ( p2527 ) , + .clk_3_E_in ( p3099 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6599 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6600 ) ) ; cbx_1__1_ cbx_7__1_ ( .pReset ( { SYNOPSYS_UNCONNECTED_6601 } ) , @@ -120974,7 +125496,7 @@ cbx_1__1_ cbx_7__1_ ( .bottom_grid_pin_14_ ( cbx_1__1__66_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__66_bottom_grid_pin_15_ ) , .ccff_tail ( cbx_1__1__66_ccff_tail ) , .SC_IN_TOP ( scff_Wires[181] ) , - .SC_OUT_BOT ( scff_Wires[182] ) , .SC_IN_BOT ( p2222 ) , + .SC_OUT_BOT ( scff_Wires[182] ) , .SC_IN_BOT ( p1595 ) , .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_6602 ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[66] ) , .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[66] ) , @@ -120989,19 +125511,19 @@ cbx_1__1_ cbx_7__1_ ( .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_6606 ) , .prog_clk_1_E_in ( prog_clk_1_wires[128] ) , .prog_clk_1_N_out ( prog_clk_1_wires[129] ) , - .prog_clk_1_S_out ( prog_clk_1_wires[130] ) , .prog_clk_2_E_in ( p1543 ) , - .prog_clk_2_W_in ( p1051 ) , + .prog_clk_1_S_out ( prog_clk_1_wires[130] ) , .prog_clk_2_E_in ( p3142 ) , + .prog_clk_2_W_in ( p3545 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6607 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6608 ) , - .prog_clk_3_W_in ( p3399 ) , .prog_clk_3_E_in ( p585 ) , + .prog_clk_3_W_in ( p3558 ) , .prog_clk_3_E_in ( p3092 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6609 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6610 ) , .clk_1_W_in ( SYNOPSYS_UNCONNECTED_6611 ) , .clk_1_E_in ( clk_1_wires[128] ) , .clk_1_N_out ( clk_1_wires[129] ) , - .clk_1_S_out ( clk_1_wires[130] ) , .clk_2_E_in ( p1543 ) , - .clk_2_W_in ( p3386 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6612 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6613 ) , .clk_3_W_in ( p3076 ) , - .clk_3_E_in ( p27 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6614 ) , + .clk_1_S_out ( clk_1_wires[130] ) , .clk_2_E_in ( p2293 ) , + .clk_2_W_in ( p2470 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6612 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6613 ) , .clk_3_W_in ( p2519 ) , + .clk_3_E_in ( p2078 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6614 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6615 ) ) ; cbx_1__1_ cbx_7__2_ ( .pReset ( { SYNOPSYS_UNCONNECTED_6616 } ) , @@ -121027,7 +125549,7 @@ cbx_1__1_ cbx_7__2_ ( .bottom_grid_pin_14_ ( cbx_1__1__67_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__67_bottom_grid_pin_15_ ) , .ccff_tail ( cbx_1__1__67_ccff_tail ) , .SC_IN_TOP ( scff_Wires[179] ) , - .SC_OUT_BOT ( scff_Wires[180] ) , .SC_IN_BOT ( p2129 ) , + .SC_OUT_BOT ( scff_Wires[180] ) , .SC_IN_BOT ( p2203 ) , .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_6617 ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[67] ) , .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[67] ) , @@ -121039,20 +125561,20 @@ cbx_1__1_ cbx_7__2_ ( .pReset_S_out ( pResetWires[137] ) , .pReset_E_out ( pResetWires[136] ) , .prog_clk_0_N_in ( prog_clk_0_wires[259] ) , .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6620 ) , - .prog_clk_1_W_in ( p1243 ) , .prog_clk_1_E_in ( p1621 ) , + .prog_clk_1_W_in ( p1440 ) , .prog_clk_1_E_in ( p2080 ) , .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_6621 ) , .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_6622 ) , - .prog_clk_2_E_in ( p2454 ) , .prog_clk_2_W_in ( p1157 ) , + .prog_clk_2_E_in ( p2530 ) , .prog_clk_2_W_in ( p3071 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6623 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6624 ) , - .prog_clk_3_W_in ( p2697 ) , .prog_clk_3_E_in ( p134 ) , + .prog_clk_3_W_in ( p3138 ) , .prog_clk_3_E_in ( p2481 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6625 ) , - .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6626 ) , .clk_1_W_in ( p1609 ) , - .clk_1_E_in ( p2000 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_6627 ) , - .clk_1_S_out ( SYNOPSYS_UNCONNECTED_6628 ) , .clk_2_E_in ( p2454 ) , - .clk_2_W_in ( p2742 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6629 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6630 ) , .clk_3_W_in ( p2862 ) , - .clk_3_E_in ( p2271 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6631 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6626 ) , .clk_1_W_in ( p1653 ) , + .clk_1_E_in ( p148 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_6627 ) , + .clk_1_S_out ( SYNOPSYS_UNCONNECTED_6628 ) , .clk_2_E_in ( p2854 ) , + .clk_2_W_in ( p2873 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6629 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6630 ) , .clk_3_W_in ( p2984 ) , + .clk_3_E_in ( p2681 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6631 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6632 ) ) ; cbx_1__1_ cbx_7__3_ ( .pReset ( { SYNOPSYS_UNCONNECTED_6633 } ) , @@ -121078,7 +125600,7 @@ cbx_1__1_ cbx_7__3_ ( .bottom_grid_pin_14_ ( cbx_1__1__68_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__68_bottom_grid_pin_15_ ) , .ccff_tail ( cbx_1__1__68_ccff_tail ) , .SC_IN_TOP ( scff_Wires[177] ) , - .SC_OUT_BOT ( scff_Wires[178] ) , .SC_IN_BOT ( p1261 ) , + .SC_OUT_BOT ( scff_Wires[178] ) , .SC_IN_BOT ( p1207 ) , .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_6634 ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[68] ) , .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[68] ) , @@ -121093,19 +125615,19 @@ cbx_1__1_ cbx_7__3_ ( .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_6638 ) , .prog_clk_1_E_in ( prog_clk_1_wires[135] ) , .prog_clk_1_N_out ( prog_clk_1_wires[136] ) , - .prog_clk_1_S_out ( prog_clk_1_wires[137] ) , .prog_clk_2_E_in ( p2218 ) , - .prog_clk_2_W_in ( p564 ) , + .prog_clk_1_S_out ( prog_clk_1_wires[137] ) , .prog_clk_2_E_in ( p2770 ) , + .prog_clk_2_W_in ( p3291 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6639 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6640 ) , - .prog_clk_3_W_in ( p3166 ) , .prog_clk_3_E_in ( p1171 ) , + .prog_clk_3_W_in ( p3335 ) , .prog_clk_3_E_in ( p2706 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6641 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6642 ) , .clk_1_W_in ( SYNOPSYS_UNCONNECTED_6643 ) , .clk_1_E_in ( clk_1_wires[135] ) , .clk_1_N_out ( clk_1_wires[136] ) , - .clk_1_S_out ( clk_1_wires[137] ) , .clk_2_E_in ( p2218 ) , - .clk_2_W_in ( p3142 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6644 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6645 ) , .clk_3_W_in ( p2973 ) , - .clk_3_E_in ( p2079 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6646 ) , + .clk_1_S_out ( clk_1_wires[137] ) , .clk_2_E_in ( p2294 ) , + .clk_2_W_in ( p2456 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6644 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6645 ) , .clk_3_W_in ( p2491 ) , + .clk_3_E_in ( p2096 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6646 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6647 ) ) ; cbx_1__1_ cbx_7__4_ ( .pReset ( { SYNOPSYS_UNCONNECTED_6648 } ) , @@ -121131,7 +125653,7 @@ cbx_1__1_ cbx_7__4_ ( .bottom_grid_pin_14_ ( cbx_1__1__69_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__69_bottom_grid_pin_15_ ) , .ccff_tail ( cbx_1__1__69_ccff_tail ) , .SC_IN_TOP ( scff_Wires[175] ) , - .SC_OUT_BOT ( scff_Wires[176] ) , .SC_IN_BOT ( p1814 ) , + .SC_OUT_BOT ( scff_Wires[176] ) , .SC_IN_BOT ( p1614 ) , .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_6649 ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[69] ) , .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[69] ) , @@ -121143,20 +125665,20 @@ cbx_1__1_ cbx_7__4_ ( .pReset_S_out ( pResetWires[235] ) , .pReset_E_out ( pResetWires[234] ) , .prog_clk_0_N_in ( prog_clk_0_wires[265] ) , .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6652 ) , - .prog_clk_1_W_in ( p2159 ) , .prog_clk_1_E_in ( p1709 ) , + .prog_clk_1_W_in ( p1571 ) , .prog_clk_1_E_in ( p425 ) , .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_6653 ) , .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_6654 ) , - .prog_clk_2_E_in ( p2245 ) , .prog_clk_2_W_in ( p2075 ) , + .prog_clk_2_E_in ( p3229 ) , .prog_clk_2_W_in ( p3439 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6655 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6656 ) , - .prog_clk_3_W_in ( p3253 ) , .prog_clk_3_E_in ( p1178 ) , + .prog_clk_3_W_in ( p3462 ) , .prog_clk_3_E_in ( p3205 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6657 ) , - .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6658 ) , .clk_1_W_in ( p1540 ) , - .clk_1_E_in ( p1700 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_6659 ) , - .clk_1_S_out ( SYNOPSYS_UNCONNECTED_6660 ) , .clk_2_E_in ( p2216 ) , - .clk_2_W_in ( p3233 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6661 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6662 ) , .clk_3_W_in ( p2243 ) , - .clk_3_E_in ( p2027 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6663 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6658 ) , .clk_1_W_in ( p1285 ) , + .clk_1_E_in ( p2066 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_6659 ) , + .clk_1_S_out ( SYNOPSYS_UNCONNECTED_6660 ) , .clk_2_E_in ( p2508 ) , + .clk_2_W_in ( p2874 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6661 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6662 ) , .clk_3_W_in ( p2971 ) , + .clk_3_E_in ( p2375 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6663 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6664 ) ) ; cbx_1__1_ cbx_7__5_ ( .pReset ( { SYNOPSYS_UNCONNECTED_6665 } ) , @@ -121182,7 +125704,7 @@ cbx_1__1_ cbx_7__5_ ( .bottom_grid_pin_14_ ( cbx_1__1__70_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__70_bottom_grid_pin_15_ ) , .ccff_tail ( cbx_1__1__70_ccff_tail ) , .SC_IN_TOP ( scff_Wires[173] ) , - .SC_OUT_BOT ( scff_Wires[174] ) , .SC_IN_BOT ( p1854 ) , + .SC_OUT_BOT ( scff_Wires[174] ) , .SC_IN_BOT ( p1897 ) , .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_6666 ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[70] ) , .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[70] ) , @@ -121197,19 +125719,19 @@ cbx_1__1_ cbx_7__5_ ( .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_6670 ) , .prog_clk_1_E_in ( prog_clk_1_wires[142] ) , .prog_clk_1_N_out ( prog_clk_1_wires[143] ) , - .prog_clk_1_S_out ( prog_clk_1_wires[144] ) , .prog_clk_2_E_in ( p1823 ) , - .prog_clk_2_W_in ( p194 ) , + .prog_clk_1_S_out ( prog_clk_1_wires[144] ) , .prog_clk_2_E_in ( p2991 ) , + .prog_clk_2_W_in ( p1745 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6671 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6672 ) , - .prog_clk_3_W_in ( p3328 ) , .prog_clk_3_E_in ( p467 ) , + .prog_clk_3_W_in ( p1847 ) , .prog_clk_3_E_in ( p2858 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6673 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6674 ) , .clk_1_W_in ( SYNOPSYS_UNCONNECTED_6675 ) , .clk_1_E_in ( clk_1_wires[142] ) , .clk_1_N_out ( clk_1_wires[143] ) , - .clk_1_S_out ( clk_1_wires[144] ) , .clk_2_E_in ( p1823 ) , - .clk_2_W_in ( p3298 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6676 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6677 ) , .clk_3_W_in ( p2790 ) , - .clk_3_E_in ( p1701 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6678 ) , + .clk_1_S_out ( clk_1_wires[144] ) , .clk_2_E_in ( p2536 ) , + .clk_2_W_in ( p3053 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6676 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6677 ) , .clk_3_W_in ( p3168 ) , + .clk_3_E_in ( p2453 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6678 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6679 ) ) ; cbx_1__1_ cbx_7__6_ ( .pReset ( { SYNOPSYS_UNCONNECTED_6680 } ) , @@ -121235,7 +125757,7 @@ cbx_1__1_ cbx_7__6_ ( .bottom_grid_pin_14_ ( cbx_1__1__71_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__71_bottom_grid_pin_15_ ) , .ccff_tail ( cbx_1__1__71_ccff_tail ) , .SC_IN_TOP ( scff_Wires[171] ) , - .SC_OUT_BOT ( scff_Wires[172] ) , .SC_IN_BOT ( p1902 ) , + .SC_OUT_BOT ( scff_Wires[172] ) , .SC_IN_BOT ( p720 ) , .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_6681 ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[71] ) , .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[71] ) , @@ -121247,19 +125769,19 @@ cbx_1__1_ cbx_7__6_ ( .pReset_S_out ( pResetWires[333] ) , .pReset_E_out ( pResetWires[332] ) , .prog_clk_0_N_in ( prog_clk_0_wires[271] ) , .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6684 ) , - .prog_clk_1_W_in ( p2636 ) , .prog_clk_1_E_in ( p404 ) , + .prog_clk_1_W_in ( p1300 ) , .prog_clk_1_E_in ( p402 ) , .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_6685 ) , .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_6686 ) , - .prog_clk_2_E_in ( p1348 ) , .prog_clk_2_W_in ( p2585 ) , + .prog_clk_2_E_in ( p1422 ) , .prog_clk_2_W_in ( p2127 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6687 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6688 ) , .prog_clk_3_W_in ( prog_clk_3_wires[0] ) , .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_6689 ) , .prog_clk_3_E_out ( prog_clk_3_wires[1] ) , - .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6690 ) , .clk_1_W_in ( p1439 ) , - .clk_1_E_in ( p1678 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_6691 ) , - .clk_1_S_out ( SYNOPSYS_UNCONNECTED_6692 ) , .clk_2_E_in ( p1348 ) , - .clk_2_W_in ( p329 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6693 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6690 ) , .clk_1_W_in ( p2358 ) , + .clk_1_E_in ( p199 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_6691 ) , + .clk_1_S_out ( SYNOPSYS_UNCONNECTED_6692 ) , .clk_2_E_in ( p1422 ) , + .clk_2_W_in ( p675 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6693 ) , .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6694 ) , .clk_3_W_in ( clk_3_wires[0] ) , .clk_3_E_in ( SYNOPSYS_UNCONNECTED_6695 ) , @@ -121289,7 +125811,7 @@ cbx_1__1_ cbx_7__7_ ( .bottom_grid_pin_14_ ( cbx_1__1__72_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__72_bottom_grid_pin_15_ ) , .ccff_tail ( cbx_1__1__72_ccff_tail ) , .SC_IN_TOP ( scff_Wires[169] ) , - .SC_OUT_BOT ( scff_Wires[170] ) , .SC_IN_BOT ( p1283 ) , + .SC_OUT_BOT ( scff_Wires[170] ) , .SC_IN_BOT ( p920 ) , .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_6698 ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[72] ) , .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[72] ) , @@ -121304,19 +125826,19 @@ cbx_1__1_ cbx_7__7_ ( .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_6702 ) , .prog_clk_1_E_in ( prog_clk_1_wires[149] ) , .prog_clk_1_N_out ( prog_clk_1_wires[150] ) , - .prog_clk_1_S_out ( prog_clk_1_wires[151] ) , .prog_clk_2_E_in ( p1522 ) , - .prog_clk_2_W_in ( p480 ) , + .prog_clk_1_S_out ( prog_clk_1_wires[151] ) , .prog_clk_2_E_in ( p2340 ) , + .prog_clk_2_W_in ( p2701 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6703 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6704 ) , - .prog_clk_3_W_in ( p3448 ) , .prog_clk_3_E_in ( p914 ) , + .prog_clk_3_W_in ( p2751 ) , .prog_clk_3_E_in ( p2125 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6705 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6706 ) , .clk_1_W_in ( SYNOPSYS_UNCONNECTED_6707 ) , .clk_1_E_in ( clk_1_wires[149] ) , .clk_1_N_out ( clk_1_wires[150] ) , - .clk_1_S_out ( clk_1_wires[151] ) , .clk_2_E_in ( p1522 ) , - .clk_2_W_in ( p3438 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6708 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6709 ) , .clk_3_W_in ( p2980 ) , - .clk_3_E_in ( p608 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6710 ) , + .clk_1_S_out ( clk_1_wires[151] ) , .clk_2_E_in ( p2309 ) , + .clk_2_W_in ( p2163 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6708 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6709 ) , .clk_3_W_in ( p2336 ) , + .clk_3_E_in ( p2140 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6710 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6711 ) ) ; cbx_1__1_ cbx_7__8_ ( .pReset ( { SYNOPSYS_UNCONNECTED_6712 } ) , @@ -121342,7 +125864,7 @@ cbx_1__1_ cbx_7__8_ ( .bottom_grid_pin_14_ ( cbx_1__1__73_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__73_bottom_grid_pin_15_ ) , .ccff_tail ( cbx_1__1__73_ccff_tail ) , .SC_IN_TOP ( scff_Wires[167] ) , - .SC_OUT_BOT ( scff_Wires[168] ) , .SC_IN_BOT ( p2198 ) , + .SC_OUT_BOT ( scff_Wires[168] ) , .SC_IN_BOT ( p2039 ) , .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_6713 ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[73] ) , .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[73] ) , @@ -121354,20 +125876,20 @@ cbx_1__1_ cbx_7__8_ ( .pReset_S_out ( pResetWires[431] ) , .pReset_E_out ( pResetWires[430] ) , .prog_clk_0_N_in ( prog_clk_0_wires[277] ) , .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6716 ) , - .prog_clk_1_W_in ( p2485 ) , .prog_clk_1_E_in ( p2051 ) , + .prog_clk_1_W_in ( p1394 ) , .prog_clk_1_E_in ( p1684 ) , .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_6717 ) , .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_6718 ) , - .prog_clk_2_E_in ( p2126 ) , .prog_clk_2_W_in ( p2361 ) , + .prog_clk_2_E_in ( p2976 ) , .prog_clk_2_W_in ( p2090 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6719 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6720 ) , - .prog_clk_3_W_in ( p3362 ) , .prog_clk_3_E_in ( p1244 ) , + .prog_clk_3_W_in ( p2194 ) , .prog_clk_3_E_in ( p2907 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6721 ) , - .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6722 ) , .clk_1_W_in ( p1513 ) , - .clk_1_E_in ( p1982 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_6723 ) , - .clk_1_S_out ( SYNOPSYS_UNCONNECTED_6724 ) , .clk_2_E_in ( p2126 ) , - .clk_2_W_in ( p3341 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6725 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6726 ) , .clk_3_W_in ( p2470 ) , - .clk_3_E_in ( p2007 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6727 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6722 ) , .clk_1_W_in ( p2350 ) , + .clk_1_E_in ( p406 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_6723 ) , + .clk_1_S_out ( SYNOPSYS_UNCONNECTED_6724 ) , .clk_2_E_in ( p2238 ) , + .clk_2_W_in ( p2438 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6725 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6726 ) , .clk_3_W_in ( p2589 ) , + .clk_3_E_in ( p2132 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6727 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6728 ) ) ; cbx_1__1_ cbx_7__9_ ( .pReset ( { SYNOPSYS_UNCONNECTED_6729 } ) , @@ -121393,7 +125915,7 @@ cbx_1__1_ cbx_7__9_ ( .bottom_grid_pin_14_ ( cbx_1__1__74_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__74_bottom_grid_pin_15_ ) , .ccff_tail ( cbx_1__1__74_ccff_tail ) , .SC_IN_TOP ( scff_Wires[165] ) , - .SC_OUT_BOT ( scff_Wires[166] ) , .SC_IN_BOT ( p1402 ) , + .SC_OUT_BOT ( scff_Wires[166] ) , .SC_IN_BOT ( p1579 ) , .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_6730 ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[74] ) , .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[74] ) , @@ -121408,19 +125930,19 @@ cbx_1__1_ cbx_7__9_ ( .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_6734 ) , .prog_clk_1_E_in ( prog_clk_1_wires[156] ) , .prog_clk_1_N_out ( prog_clk_1_wires[157] ) , - .prog_clk_1_S_out ( prog_clk_1_wires[158] ) , .prog_clk_2_E_in ( p1488 ) , - .prog_clk_2_W_in ( p1105 ) , + .prog_clk_1_S_out ( prog_clk_1_wires[158] ) , .prog_clk_2_E_in ( p3233 ) , + .prog_clk_2_W_in ( p3057 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6735 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6736 ) , - .prog_clk_3_W_in ( p3096 ) , .prog_clk_3_E_in ( p976 ) , + .prog_clk_3_W_in ( p3119 ) , .prog_clk_3_E_in ( p3213 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6737 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6738 ) , .clk_1_W_in ( SYNOPSYS_UNCONNECTED_6739 ) , .clk_1_E_in ( clk_1_wires[156] ) , .clk_1_N_out ( clk_1_wires[157] ) , - .clk_1_S_out ( clk_1_wires[158] ) , .clk_2_E_in ( p1488 ) , - .clk_2_W_in ( p3027 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6740 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6741 ) , .clk_3_W_in ( p3066 ) , - .clk_3_E_in ( p627 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6742 ) , + .clk_1_S_out ( clk_1_wires[158] ) , .clk_2_E_in ( p2214 ) , + .clk_2_W_in ( p2473 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6740 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6741 ) , .clk_3_W_in ( p2537 ) , + .clk_3_E_in ( p2158 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6742 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6743 ) ) ; cbx_1__1_ cbx_7__10_ ( .pReset ( { SYNOPSYS_UNCONNECTED_6744 } ) , @@ -121446,7 +125968,7 @@ cbx_1__1_ cbx_7__10_ ( .bottom_grid_pin_14_ ( cbx_1__1__75_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__75_bottom_grid_pin_15_ ) , .ccff_tail ( cbx_1__1__75_ccff_tail ) , .SC_IN_TOP ( scff_Wires[163] ) , - .SC_OUT_BOT ( scff_Wires[164] ) , .SC_IN_BOT ( p1227 ) , + .SC_OUT_BOT ( scff_Wires[164] ) , .SC_IN_BOT ( p1534 ) , .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_6745 ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[75] ) , .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[75] ) , @@ -121458,20 +125980,20 @@ cbx_1__1_ cbx_7__10_ ( .pReset_S_out ( pResetWires[529] ) , .pReset_E_out ( pResetWires[528] ) , .prog_clk_0_N_in ( prog_clk_0_wires[283] ) , .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6748 ) , - .prog_clk_1_W_in ( p2483 ) , .prog_clk_1_E_in ( p614 ) , + .prog_clk_1_W_in ( p1369 ) , .prog_clk_1_E_in ( p471 ) , .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_6749 ) , .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_6750 ) , - .prog_clk_2_E_in ( p1464 ) , .prog_clk_2_W_in ( p2315 ) , + .prog_clk_2_E_in ( p2988 ) , .prog_clk_2_W_in ( p3050 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6751 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6752 ) , - .prog_clk_3_W_in ( p2956 ) , .prog_clk_3_E_in ( p1172 ) , + .prog_clk_3_W_in ( p2052 ) , .prog_clk_3_E_in ( p2909 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6753 ) , - .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6754 ) , .clk_1_W_in ( p1798 ) , - .clk_1_E_in ( p160 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_6755 ) , - .clk_1_S_out ( SYNOPSYS_UNCONNECTED_6756 ) , .clk_2_E_in ( p1464 ) , - .clk_2_W_in ( p2885 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6757 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6758 ) , .clk_3_W_in ( p2399 ) , - .clk_3_E_in ( p185 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6759 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6754 ) , .clk_1_W_in ( p3100 ) , + .clk_1_E_in ( p563 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_6755 ) , + .clk_1_S_out ( SYNOPSYS_UNCONNECTED_6756 ) , .clk_2_E_in ( p2273 ) , + .clk_2_W_in ( p3214 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6757 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6758 ) , .clk_3_W_in ( p3236 ) , + .clk_3_E_in ( p2137 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6759 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6760 ) ) ; cbx_1__1_ cbx_7__11_ ( .pReset ( { SYNOPSYS_UNCONNECTED_6761 } ) , @@ -121497,7 +126019,7 @@ cbx_1__1_ cbx_7__11_ ( .bottom_grid_pin_14_ ( cbx_1__1__76_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__76_bottom_grid_pin_15_ ) , .ccff_tail ( cbx_1__1__76_ccff_tail ) , .SC_IN_TOP ( scff_Wires[161] ) , - .SC_OUT_BOT ( scff_Wires[162] ) , .SC_IN_BOT ( p1608 ) , + .SC_OUT_BOT ( scff_Wires[162] ) , .SC_IN_BOT ( p1183 ) , .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_6762 ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[76] ) , .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[76] ) , @@ -121512,19 +126034,19 @@ cbx_1__1_ cbx_7__11_ ( .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_6766 ) , .prog_clk_1_E_in ( prog_clk_1_wires[163] ) , .prog_clk_1_N_out ( prog_clk_1_wires[164] ) , - .prog_clk_1_S_out ( prog_clk_1_wires[165] ) , .prog_clk_2_E_in ( p2453 ) , - .prog_clk_2_W_in ( p1029 ) , + .prog_clk_1_S_out ( prog_clk_1_wires[165] ) , .prog_clk_2_E_in ( p2803 ) , + .prog_clk_2_W_in ( p3309 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6767 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6768 ) , - .prog_clk_3_W_in ( p3306 ) , .prog_clk_3_E_in ( p1158 ) , + .prog_clk_3_W_in ( p3326 ) , .prog_clk_3_E_in ( p2688 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6769 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6770 ) , .clk_1_W_in ( SYNOPSYS_UNCONNECTED_6771 ) , .clk_1_E_in ( clk_1_wires[163] ) , .clk_1_N_out ( clk_1_wires[164] ) , - .clk_1_S_out ( clk_1_wires[165] ) , .clk_2_E_in ( p2453 ) , - .clk_2_W_in ( p3278 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6772 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6773 ) , .clk_3_W_in ( p2616 ) , - .clk_3_E_in ( p2373 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6774 ) , + .clk_1_S_out ( clk_1_wires[165] ) , .clk_2_E_in ( p2342 ) , + .clk_2_W_in ( p2454 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6772 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6773 ) , .clk_3_W_in ( p2566 ) , + .clk_3_E_in ( p2187 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6774 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6775 ) ) ; cbx_1__1_ cbx_8__1_ ( .pReset ( { SYNOPSYS_UNCONNECTED_6776 } ) , @@ -121549,7 +126071,7 @@ cbx_1__1_ cbx_8__1_ ( .bottom_grid_pin_13_ ( cbx_1__1__77_bottom_grid_pin_13_ ) , .bottom_grid_pin_14_ ( cbx_1__1__77_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__77_bottom_grid_pin_15_ ) , - .ccff_tail ( cbx_1__1__77_ccff_tail ) , .SC_IN_TOP ( p1879 ) , + .ccff_tail ( cbx_1__1__77_ccff_tail ) , .SC_IN_TOP ( p1583 ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_6777 ) , .SC_IN_BOT ( scff_Wires[188] ) , .SC_OUT_TOP ( scff_Wires[189] ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[77] ) , @@ -121565,20 +126087,20 @@ cbx_1__1_ cbx_8__1_ ( .prog_clk_1_W_in ( prog_clk_1_wires[127] ) , .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_6781 ) , .prog_clk_1_N_out ( prog_clk_1_wires[131] ) , - .prog_clk_1_S_out ( prog_clk_1_wires[132] ) , .prog_clk_2_E_in ( p1424 ) , - .prog_clk_2_W_in ( p1230 ) , + .prog_clk_1_S_out ( prog_clk_1_wires[132] ) , .prog_clk_2_E_in ( p2964 ) , + .prog_clk_2_W_in ( p2183 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6782 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6783 ) , - .prog_clk_3_W_in ( p670 ) , .prog_clk_3_E_in ( p1667 ) , + .prog_clk_3_W_in ( p2232 ) , .prog_clk_3_E_in ( p2878 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6784 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6785 ) , .clk_1_W_in ( clk_1_wires[127] ) , .clk_1_E_in ( SYNOPSYS_UNCONNECTED_6786 ) , .clk_1_N_out ( clk_1_wires[131] ) , .clk_1_S_out ( clk_1_wires[132] ) , - .clk_2_E_in ( p1424 ) , .clk_2_W_in ( p2582 ) , + .clk_2_E_in ( p2778 ) , .clk_2_W_in ( p3303 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6787 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6788 ) , .clk_3_W_in ( p2678 ) , - .clk_3_E_in ( p193 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6789 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6788 ) , .clk_3_W_in ( p3330 ) , + .clk_3_E_in ( p2680 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6789 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6790 ) ) ; cbx_1__1_ cbx_8__2_ ( .pReset ( { SYNOPSYS_UNCONNECTED_6791 } ) , @@ -121603,7 +126125,7 @@ cbx_1__1_ cbx_8__2_ ( .bottom_grid_pin_13_ ( cbx_1__1__78_bottom_grid_pin_13_ ) , .bottom_grid_pin_14_ ( cbx_1__1__78_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__78_bottom_grid_pin_15_ ) , - .ccff_tail ( cbx_1__1__78_ccff_tail ) , .SC_IN_TOP ( p1928 ) , + .ccff_tail ( cbx_1__1__78_ccff_tail ) , .SC_IN_TOP ( p1517 ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_6792 ) , .SC_IN_BOT ( scff_Wires[190] ) , .SC_OUT_TOP ( scff_Wires[191] ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[78] ) , @@ -121616,23 +126138,23 @@ cbx_1__1_ cbx_8__2_ ( .pReset_S_out ( pResetWires[141] ) , .pReset_E_out ( pResetWires[140] ) , .prog_clk_0_N_in ( prog_clk_0_wires[297] ) , .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6795 ) , - .prog_clk_1_W_in ( p1121 ) , .prog_clk_1_E_in ( p2025 ) , + .prog_clk_1_W_in ( p1060 ) , .prog_clk_1_E_in ( p204 ) , .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_6796 ) , .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_6797 ) , .prog_clk_2_E_in ( prog_clk_2_wires[71] ) , .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_6798 ) , .prog_clk_2_W_out ( prog_clk_2_wires[72] ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6799 ) , - .prog_clk_3_W_in ( p1121 ) , .prog_clk_3_E_in ( p1679 ) , + .prog_clk_3_W_in ( p1562 ) , .prog_clk_3_E_in ( p936 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6800 ) , - .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6801 ) , .clk_1_W_in ( p1121 ) , - .clk_1_E_in ( p98 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_6802 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6801 ) , .clk_1_W_in ( p1452 ) , + .clk_1_E_in ( p1671 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_6802 ) , .clk_1_S_out ( SYNOPSYS_UNCONNECTED_6803 ) , .clk_2_E_in ( clk_2_wires[71] ) , .clk_2_W_in ( SYNOPSYS_UNCONNECTED_6804 ) , .clk_2_W_out ( clk_2_wires[72] ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6805 ) , .clk_3_W_in ( p2230 ) , - .clk_3_E_in ( p2022 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6806 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6805 ) , .clk_3_W_in ( p1562 ) , + .clk_3_E_in ( p1793 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6806 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6807 ) ) ; cbx_1__1_ cbx_8__3_ ( .pReset ( { SYNOPSYS_UNCONNECTED_6808 } ) , @@ -121657,7 +126179,7 @@ cbx_1__1_ cbx_8__3_ ( .bottom_grid_pin_13_ ( cbx_1__1__79_bottom_grid_pin_13_ ) , .bottom_grid_pin_14_ ( cbx_1__1__79_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__79_bottom_grid_pin_15_ ) , - .ccff_tail ( cbx_1__1__79_ccff_tail ) , .SC_IN_TOP ( p2378 ) , + .ccff_tail ( cbx_1__1__79_ccff_tail ) , .SC_IN_TOP ( p1922 ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_6809 ) , .SC_IN_BOT ( scff_Wires[192] ) , .SC_OUT_TOP ( scff_Wires[193] ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[79] ) , @@ -121673,20 +126195,20 @@ cbx_1__1_ cbx_8__3_ ( .prog_clk_1_W_in ( prog_clk_1_wires[134] ) , .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_6813 ) , .prog_clk_1_N_out ( prog_clk_1_wires[138] ) , - .prog_clk_1_S_out ( prog_clk_1_wires[139] ) , .prog_clk_2_E_in ( p1235 ) , - .prog_clk_2_W_in ( p648 ) , + .prog_clk_1_S_out ( prog_clk_1_wires[139] ) , .prog_clk_2_E_in ( p2514 ) , + .prog_clk_2_W_in ( p3207 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6814 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6815 ) , - .prog_clk_3_W_in ( p2705 ) , .prog_clk_3_E_in ( p2349 ) , + .prog_clk_3_W_in ( p3245 ) , .prog_clk_3_E_in ( p2486 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6816 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6817 ) , .clk_1_W_in ( clk_1_wires[134] ) , .clk_1_E_in ( SYNOPSYS_UNCONNECTED_6818 ) , .clk_1_N_out ( clk_1_wires[138] ) , .clk_1_S_out ( clk_1_wires[139] ) , - .clk_2_E_in ( p1235 ) , .clk_2_W_in ( p2578 ) , + .clk_2_E_in ( p2754 ) , .clk_2_W_in ( p2393 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6819 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6820 ) , .clk_3_W_in ( p2393 ) , - .clk_3_E_in ( p1237 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6821 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6820 ) , .clk_3_W_in ( p2565 ) , + .clk_3_E_in ( p2691 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6821 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6822 ) ) ; cbx_1__1_ cbx_8__4_ ( .pReset ( { SYNOPSYS_UNCONNECTED_6823 } ) , @@ -121711,7 +126233,7 @@ cbx_1__1_ cbx_8__4_ ( .bottom_grid_pin_13_ ( cbx_1__1__80_bottom_grid_pin_13_ ) , .bottom_grid_pin_14_ ( cbx_1__1__80_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__80_bottom_grid_pin_15_ ) , - .ccff_tail ( cbx_1__1__80_ccff_tail ) , .SC_IN_TOP ( p1551 ) , + .ccff_tail ( cbx_1__1__80_ccff_tail ) , .SC_IN_TOP ( p1893 ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_6824 ) , .SC_IN_BOT ( scff_Wires[194] ) , .SC_OUT_TOP ( scff_Wires[195] ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[80] ) , @@ -121724,23 +126246,23 @@ cbx_1__1_ cbx_8__4_ ( .pReset_S_out ( pResetWires[239] ) , .pReset_E_out ( pResetWires[238] ) , .prog_clk_0_N_in ( prog_clk_0_wires[303] ) , .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6827 ) , - .prog_clk_1_W_in ( p1920 ) , .prog_clk_1_E_in ( p685 ) , + .prog_clk_1_W_in ( p1453 ) , .prog_clk_1_E_in ( p295 ) , .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_6828 ) , .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_6829 ) , .prog_clk_2_E_in ( prog_clk_2_wires[80] ) , .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_6830 ) , .prog_clk_2_W_out ( prog_clk_2_wires[81] ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6831 ) , - .prog_clk_3_W_in ( p1801 ) , .prog_clk_3_E_in ( p1294 ) , + .prog_clk_3_W_in ( p1275 ) , .prog_clk_3_E_in ( p1739 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6832 ) , - .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6833 ) , .clk_1_W_in ( p1468 ) , - .clk_1_E_in ( p556 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_6834 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6833 ) , .clk_1_W_in ( p1169 ) , + .clk_1_E_in ( p631 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_6834 ) , .clk_1_S_out ( SYNOPSYS_UNCONNECTED_6835 ) , .clk_2_E_in ( clk_2_wires[80] ) , .clk_2_W_in ( SYNOPSYS_UNCONNECTED_6836 ) , .clk_2_W_out ( clk_2_wires[81] ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6837 ) , .clk_3_W_in ( p1801 ) , - .clk_3_E_in ( p358 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6838 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6837 ) , .clk_3_W_in ( p1275 ) , + .clk_3_E_in ( p1015 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6838 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6839 ) ) ; cbx_1__1_ cbx_8__5_ ( .pReset ( { SYNOPSYS_UNCONNECTED_6840 } ) , @@ -121765,7 +126287,7 @@ cbx_1__1_ cbx_8__5_ ( .bottom_grid_pin_13_ ( cbx_1__1__81_bottom_grid_pin_13_ ) , .bottom_grid_pin_14_ ( cbx_1__1__81_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__81_bottom_grid_pin_15_ ) , - .ccff_tail ( cbx_1__1__81_ccff_tail ) , .SC_IN_TOP ( p1898 ) , + .ccff_tail ( cbx_1__1__81_ccff_tail ) , .SC_IN_TOP ( p2368 ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_6841 ) , .SC_IN_BOT ( scff_Wires[196] ) , .SC_OUT_TOP ( scff_Wires[197] ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[81] ) , @@ -121781,20 +126303,20 @@ cbx_1__1_ cbx_8__5_ ( .prog_clk_1_W_in ( prog_clk_1_wires[141] ) , .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_6845 ) , .prog_clk_1_N_out ( prog_clk_1_wires[145] ) , - .prog_clk_1_S_out ( prog_clk_1_wires[146] ) , .prog_clk_2_E_in ( p1950 ) , - .prog_clk_2_W_in ( p521 ) , + .prog_clk_1_S_out ( prog_clk_1_wires[146] ) , .prog_clk_2_E_in ( p2962 ) , + .prog_clk_2_W_in ( p2191 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6846 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6847 ) , - .prog_clk_3_W_in ( p2610 ) , .prog_clk_3_E_in ( p1763 ) , + .prog_clk_3_W_in ( p2303 ) , .prog_clk_3_E_in ( p2897 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6848 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6849 ) , .clk_1_W_in ( clk_1_wires[141] ) , .clk_1_E_in ( SYNOPSYS_UNCONNECTED_6850 ) , .clk_1_N_out ( clk_1_wires[145] ) , .clk_1_S_out ( clk_1_wires[146] ) , - .clk_2_E_in ( p1950 ) , .clk_2_W_in ( p3149 ) , + .clk_2_E_in ( p1895 ) , .clk_2_W_in ( p2095 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6851 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6852 ) , .clk_3_W_in ( p3182 ) , - .clk_3_E_in ( p1662 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6853 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6852 ) , .clk_3_W_in ( p2276 ) , + .clk_3_E_in ( p1693 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6853 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6854 ) ) ; cbx_1__1_ cbx_8__6_ ( .pReset ( { SYNOPSYS_UNCONNECTED_6855 } ) , @@ -121819,7 +126341,7 @@ cbx_1__1_ cbx_8__6_ ( .bottom_grid_pin_13_ ( cbx_1__1__82_bottom_grid_pin_13_ ) , .bottom_grid_pin_14_ ( cbx_1__1__82_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__82_bottom_grid_pin_15_ ) , - .ccff_tail ( cbx_1__1__82_ccff_tail ) , .SC_IN_TOP ( p1592 ) , + .ccff_tail ( cbx_1__1__82_ccff_tail ) , .SC_IN_TOP ( p1514 ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_6856 ) , .SC_IN_BOT ( scff_Wires[198] ) , .SC_OUT_TOP ( scff_Wires[199] ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[82] ) , @@ -121832,19 +126354,19 @@ cbx_1__1_ cbx_8__6_ ( .pReset_S_out ( pResetWires[337] ) , .pReset_E_out ( pResetWires[336] ) , .prog_clk_0_N_in ( prog_clk_0_wires[309] ) , .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6859 ) , - .prog_clk_1_W_in ( p2414 ) , .prog_clk_1_E_in ( p466 ) , + .prog_clk_1_W_in ( p809 ) , .prog_clk_1_E_in ( p589 ) , .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_6860 ) , .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_6861 ) , - .prog_clk_2_E_in ( p1597 ) , .prog_clk_2_W_in ( p2323 ) , + .prog_clk_2_E_in ( p1414 ) , .prog_clk_2_W_in ( p2113 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6862 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6863 ) , .prog_clk_3_W_in ( prog_clk_3_wires[4] ) , .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_6864 ) , .prog_clk_3_E_out ( prog_clk_3_wires[5] ) , - .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6865 ) , .clk_1_W_in ( p1360 ) , - .clk_1_E_in ( p285 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_6866 ) , - .clk_1_S_out ( SYNOPSYS_UNCONNECTED_6867 ) , .clk_2_E_in ( p1597 ) , - .clk_2_W_in ( p1135 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6868 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6865 ) , .clk_1_W_in ( p2301 ) , + .clk_1_E_in ( p356 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_6866 ) , + .clk_1_S_out ( SYNOPSYS_UNCONNECTED_6867 ) , .clk_2_E_in ( p1414 ) , + .clk_2_W_in ( p798 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6868 ) , .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6869 ) , .clk_3_W_in ( clk_3_wires[4] ) , .clk_3_E_in ( SYNOPSYS_UNCONNECTED_6870 ) , @@ -121873,7 +126395,7 @@ cbx_1__1_ cbx_8__7_ ( .bottom_grid_pin_13_ ( cbx_1__1__83_bottom_grid_pin_13_ ) , .bottom_grid_pin_14_ ( cbx_1__1__83_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__83_bottom_grid_pin_15_ ) , - .ccff_tail ( cbx_1__1__83_ccff_tail ) , .SC_IN_TOP ( p2135 ) , + .ccff_tail ( cbx_1__1__83_ccff_tail ) , .SC_IN_TOP ( p1474 ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_6873 ) , .SC_IN_BOT ( scff_Wires[200] ) , .SC_OUT_TOP ( scff_Wires[201] ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[83] ) , @@ -121889,20 +126411,20 @@ cbx_1__1_ cbx_8__7_ ( .prog_clk_1_W_in ( prog_clk_1_wires[148] ) , .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_6877 ) , .prog_clk_1_N_out ( prog_clk_1_wires[152] ) , - .prog_clk_1_S_out ( prog_clk_1_wires[153] ) , .prog_clk_2_E_in ( p1830 ) , - .prog_clk_2_W_in ( p882 ) , + .prog_clk_1_S_out ( prog_clk_1_wires[153] ) , .prog_clk_2_E_in ( p1986 ) , + .prog_clk_2_W_in ( p3526 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6878 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6879 ) , - .prog_clk_3_W_in ( p3309 ) , .prog_clk_3_E_in ( p2033 ) , + .prog_clk_3_W_in ( p3536 ) , .prog_clk_3_E_in ( p1737 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6880 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6881 ) , .clk_1_W_in ( clk_1_wires[148] ) , .clk_1_E_in ( SYNOPSYS_UNCONNECTED_6882 ) , .clk_1_N_out ( clk_1_wires[152] ) , .clk_1_S_out ( clk_1_wires[153] ) , - .clk_2_E_in ( p1830 ) , .clk_2_W_in ( p3291 ) , + .clk_2_E_in ( p1979 ) , .clk_2_W_in ( p3544 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6883 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6884 ) , .clk_3_W_in ( p2987 ) , - .clk_3_E_in ( p1672 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6885 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6884 ) , .clk_3_W_in ( p3555 ) , + .clk_3_E_in ( p1752 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6885 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6886 ) ) ; cbx_1__1_ cbx_8__8_ ( .pReset ( { SYNOPSYS_UNCONNECTED_6887 } ) , @@ -121927,7 +126449,7 @@ cbx_1__1_ cbx_8__8_ ( .bottom_grid_pin_13_ ( cbx_1__1__84_bottom_grid_pin_13_ ) , .bottom_grid_pin_14_ ( cbx_1__1__84_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__84_bottom_grid_pin_15_ ) , - .ccff_tail ( cbx_1__1__84_ccff_tail ) , .SC_IN_TOP ( p2706 ) , + .ccff_tail ( cbx_1__1__84_ccff_tail ) , .SC_IN_TOP ( p1383 ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_6888 ) , .SC_IN_BOT ( scff_Wires[202] ) , .SC_OUT_TOP ( scff_Wires[203] ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[84] ) , @@ -121940,23 +126462,23 @@ cbx_1__1_ cbx_8__8_ ( .pReset_S_out ( pResetWires[435] ) , .pReset_E_out ( pResetWires[434] ) , .prog_clk_0_N_in ( prog_clk_0_wires[315] ) , .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6891 ) , - .prog_clk_1_W_in ( p962 ) , .prog_clk_1_E_in ( p675 ) , + .prog_clk_1_W_in ( p1633 ) , .prog_clk_1_E_in ( p384 ) , .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_6892 ) , .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_6893 ) , .prog_clk_2_E_in ( prog_clk_2_wires[93] ) , .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_6894 ) , .prog_clk_2_W_out ( prog_clk_2_wires[94] ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6895 ) , - .prog_clk_3_W_in ( p962 ) , .prog_clk_3_E_in ( p2539 ) , + .prog_clk_3_W_in ( p1361 ) , .prog_clk_3_E_in ( p948 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6896 ) , - .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6897 ) , .clk_1_W_in ( p1355 ) , - .clk_1_E_in ( p199 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_6898 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6897 ) , .clk_1_W_in ( p1361 ) , + .clk_1_E_in ( p772 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_6898 ) , .clk_1_S_out ( SYNOPSYS_UNCONNECTED_6899 ) , .clk_2_E_in ( clk_2_wires[93] ) , .clk_2_W_in ( SYNOPSYS_UNCONNECTED_6900 ) , .clk_2_W_out ( clk_2_wires[94] ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6901 ) , .clk_3_W_in ( p962 ) , - .clk_3_E_in ( p539 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6902 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6901 ) , .clk_3_W_in ( p1361 ) , + .clk_3_E_in ( p504 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6902 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6903 ) ) ; cbx_1__1_ cbx_8__9_ ( .pReset ( { SYNOPSYS_UNCONNECTED_6904 } ) , @@ -121981,7 +126503,7 @@ cbx_1__1_ cbx_8__9_ ( .bottom_grid_pin_13_ ( cbx_1__1__85_bottom_grid_pin_13_ ) , .bottom_grid_pin_14_ ( cbx_1__1__85_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__85_bottom_grid_pin_15_ ) , - .ccff_tail ( cbx_1__1__85_ccff_tail ) , .SC_IN_TOP ( p1589 ) , + .ccff_tail ( cbx_1__1__85_ccff_tail ) , .SC_IN_TOP ( p2360 ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_6905 ) , .SC_IN_BOT ( scff_Wires[204] ) , .SC_OUT_TOP ( scff_Wires[205] ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[85] ) , @@ -121997,20 +126519,20 @@ cbx_1__1_ cbx_8__9_ ( .prog_clk_1_W_in ( prog_clk_1_wires[155] ) , .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_6909 ) , .prog_clk_1_N_out ( prog_clk_1_wires[159] ) , - .prog_clk_1_S_out ( prog_clk_1_wires[160] ) , .prog_clk_2_E_in ( p1780 ) , - .prog_clk_2_W_in ( p1056 ) , + .prog_clk_1_S_out ( prog_clk_1_wires[160] ) , .prog_clk_2_E_in ( p2274 ) , + .prog_clk_2_W_in ( p2648 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6910 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6911 ) , - .prog_clk_3_W_in ( p3254 ) , .prog_clk_3_E_in ( p655 ) , + .prog_clk_3_W_in ( p2753 ) , .prog_clk_3_E_in ( p2161 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6912 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6913 ) , .clk_1_W_in ( clk_1_wires[155] ) , .clk_1_E_in ( SYNOPSYS_UNCONNECTED_6914 ) , .clk_1_N_out ( clk_1_wires[159] ) , .clk_1_S_out ( clk_1_wires[160] ) , - .clk_2_E_in ( p1780 ) , .clk_2_W_in ( p3216 ) , + .clk_2_E_in ( p2553 ) , .clk_2_W_in ( p2149 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6915 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6916 ) , .clk_3_W_in ( p1905 ) , - .clk_3_E_in ( p1710 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6917 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6916 ) , .clk_3_W_in ( p2367 ) , + .clk_3_E_in ( p2380 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6917 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6918 ) ) ; cbx_1__1_ cbx_8__10_ ( .pReset ( { SYNOPSYS_UNCONNECTED_6919 } ) , @@ -122035,7 +126557,7 @@ cbx_1__1_ cbx_8__10_ ( .bottom_grid_pin_13_ ( cbx_1__1__86_bottom_grid_pin_13_ ) , .bottom_grid_pin_14_ ( cbx_1__1__86_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__86_bottom_grid_pin_15_ ) , - .ccff_tail ( cbx_1__1__86_ccff_tail ) , .SC_IN_TOP ( p2165 ) , + .ccff_tail ( cbx_1__1__86_ccff_tail ) , .SC_IN_TOP ( p2225 ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_6920 ) , .SC_IN_BOT ( scff_Wires[206] ) , .SC_OUT_TOP ( scff_Wires[207] ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[86] ) , @@ -122048,23 +126570,23 @@ cbx_1__1_ cbx_8__10_ ( .pReset_S_out ( pResetWires[533] ) , .pReset_E_out ( pResetWires[532] ) , .prog_clk_0_N_in ( prog_clk_0_wires[321] ) , .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6923 ) , - .prog_clk_1_W_in ( p1804 ) , .prog_clk_1_E_in ( p2058 ) , + .prog_clk_1_W_in ( p1347 ) , .prog_clk_1_E_in ( p702 ) , .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_6924 ) , .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_6925 ) , .prog_clk_2_E_in ( prog_clk_2_wires[106] ) , .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_6926 ) , .prog_clk_2_W_out ( prog_clk_2_wires[107] ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6927 ) , - .prog_clk_3_W_in ( p1959 ) , .prog_clk_3_E_in ( p2081 ) , + .prog_clk_3_W_in ( p1600 ) , .prog_clk_3_E_in ( p2131 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6928 ) , - .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6929 ) , .clk_1_W_in ( p1410 ) , - .clk_1_E_in ( p599 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_6930 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6929 ) , .clk_1_W_in ( p1324 ) , + .clk_1_E_in ( p100 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_6930 ) , .clk_1_S_out ( SYNOPSYS_UNCONNECTED_6931 ) , .clk_2_E_in ( clk_2_wires[106] ) , .clk_2_W_in ( SYNOPSYS_UNCONNECTED_6932 ) , .clk_2_W_out ( clk_2_wires[107] ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6933 ) , .clk_3_W_in ( p1959 ) , - .clk_3_E_in ( p1964 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6934 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6933 ) , .clk_3_W_in ( p1600 ) , + .clk_3_E_in ( p546 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6934 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6935 ) ) ; cbx_1__1_ cbx_8__11_ ( .pReset ( { SYNOPSYS_UNCONNECTED_6936 } ) , @@ -122089,7 +126611,7 @@ cbx_1__1_ cbx_8__11_ ( .bottom_grid_pin_13_ ( cbx_1__1__87_bottom_grid_pin_13_ ) , .bottom_grid_pin_14_ ( cbx_1__1__87_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__87_bottom_grid_pin_15_ ) , - .ccff_tail ( cbx_1__1__87_ccff_tail ) , .SC_IN_TOP ( p2491 ) , + .ccff_tail ( cbx_1__1__87_ccff_tail ) , .SC_IN_TOP ( p1876 ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_6937 ) , .SC_IN_BOT ( scff_Wires[208] ) , .SC_OUT_TOP ( scff_Wires[209] ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[87] ) , @@ -122105,20 +126627,20 @@ cbx_1__1_ cbx_8__11_ ( .prog_clk_1_W_in ( prog_clk_1_wires[162] ) , .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_6941 ) , .prog_clk_1_N_out ( prog_clk_1_wires[166] ) , - .prog_clk_1_S_out ( prog_clk_1_wires[167] ) , .prog_clk_2_E_in ( p2402 ) , - .prog_clk_2_W_in ( p242 ) , + .prog_clk_1_S_out ( prog_clk_1_wires[167] ) , .prog_clk_2_E_in ( p3121 ) , + .prog_clk_2_W_in ( p3484 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6942 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6943 ) , - .prog_clk_3_W_in ( p2482 ) , .prog_clk_3_E_in ( p2364 ) , + .prog_clk_3_W_in ( p3496 ) , .prog_clk_3_E_in ( p3079 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6944 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6945 ) , .clk_1_W_in ( clk_1_wires[162] ) , .clk_1_E_in ( SYNOPSYS_UNCONNECTED_6946 ) , .clk_1_N_out ( clk_1_wires[166] ) , .clk_1_S_out ( clk_1_wires[167] ) , - .clk_2_E_in ( p2402 ) , .clk_2_W_in ( p2339 ) , + .clk_2_E_in ( p2755 ) , .clk_2_W_in ( p2433 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6947 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6948 ) , .clk_3_W_in ( p2506 ) , - .clk_3_E_in ( p2270 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6949 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6948 ) , .clk_3_W_in ( p2568 ) , + .clk_3_E_in ( p2692 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6949 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6950 ) ) ; cbx_1__1_ cbx_9__1_ ( .pReset ( { SYNOPSYS_UNCONNECTED_6951 } ) , @@ -122144,7 +126666,7 @@ cbx_1__1_ cbx_9__1_ ( .bottom_grid_pin_14_ ( cbx_1__1__88_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__88_bottom_grid_pin_15_ ) , .ccff_tail ( cbx_1__1__88_ccff_tail ) , .SC_IN_TOP ( scff_Wires[234] ) , - .SC_OUT_BOT ( scff_Wires[235] ) , .SC_IN_BOT ( p946 ) , + .SC_OUT_BOT ( scff_Wires[235] ) , .SC_IN_BOT ( p1237 ) , .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_6952 ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[88] ) , .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[88] ) , @@ -122159,19 +126681,19 @@ cbx_1__1_ cbx_9__1_ ( .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_6956 ) , .prog_clk_1_E_in ( prog_clk_1_wires[170] ) , .prog_clk_1_N_out ( prog_clk_1_wires[171] ) , - .prog_clk_1_S_out ( prog_clk_1_wires[172] ) , .prog_clk_2_E_in ( p1816 ) , - .prog_clk_2_W_in ( p643 ) , + .prog_clk_1_S_out ( prog_clk_1_wires[172] ) , .prog_clk_2_E_in ( p3009 ) , + .prog_clk_2_W_in ( p3037 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6957 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6958 ) , - .prog_clk_3_W_in ( p2673 ) , .prog_clk_3_E_in ( p427 ) , + .prog_clk_3_W_in ( p3150 ) , .prog_clk_3_E_in ( p2862 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6959 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6960 ) , .clk_1_W_in ( SYNOPSYS_UNCONNECTED_6961 ) , .clk_1_E_in ( clk_1_wires[170] ) , .clk_1_N_out ( clk_1_wires[171] ) , - .clk_1_S_out ( clk_1_wires[172] ) , .clk_2_E_in ( p1816 ) , - .clk_2_W_in ( p2761 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6962 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6963 ) , .clk_3_W_in ( p2787 ) , - .clk_3_E_in ( p1706 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6964 ) , + .clk_1_S_out ( clk_1_wires[172] ) , .clk_2_E_in ( p2835 ) , + .clk_2_W_in ( p3381 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6962 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6963 ) , .clk_3_W_in ( p3423 ) , + .clk_3_E_in ( p2713 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6964 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6965 ) ) ; cbx_1__1_ cbx_9__2_ ( .pReset ( { SYNOPSYS_UNCONNECTED_6966 } ) , @@ -122197,7 +126719,7 @@ cbx_1__1_ cbx_9__2_ ( .bottom_grid_pin_14_ ( cbx_1__1__89_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__89_bottom_grid_pin_15_ ) , .ccff_tail ( cbx_1__1__89_ccff_tail ) , .SC_IN_TOP ( scff_Wires[232] ) , - .SC_OUT_BOT ( scff_Wires[233] ) , .SC_IN_BOT ( p1832 ) , + .SC_OUT_BOT ( scff_Wires[233] ) , .SC_IN_BOT ( p1536 ) , .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_6967 ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[89] ) , .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[89] ) , @@ -122209,23 +126731,23 @@ cbx_1__1_ cbx_9__2_ ( .pReset_S_out ( pResetWires[145] ) , .pReset_E_out ( pResetWires[144] ) , .prog_clk_0_N_in ( prog_clk_0_wires[335] ) , .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6970 ) , - .prog_clk_1_W_in ( p1887 ) , .prog_clk_1_E_in ( p451 ) , + .prog_clk_1_W_in ( p1271 ) , .prog_clk_1_E_in ( p634 ) , .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_6971 ) , .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_6972 ) , .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_6973 ) , .prog_clk_2_W_in ( prog_clk_2_wires[69] ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6974 ) , - .prog_clk_2_E_out ( prog_clk_2_wires[70] ) , .prog_clk_3_W_in ( p1887 ) , - .prog_clk_3_E_in ( p1027 ) , + .prog_clk_2_E_out ( prog_clk_2_wires[70] ) , .prog_clk_3_W_in ( p1635 ) , + .prog_clk_3_E_in ( p173 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6975 ) , - .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6976 ) , .clk_1_W_in ( p1430 ) , - .clk_1_E_in ( p1682 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_6977 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6976 ) , .clk_1_W_in ( p1493 ) , + .clk_1_E_in ( p608 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_6977 ) , .clk_1_S_out ( SYNOPSYS_UNCONNECTED_6978 ) , .clk_2_E_in ( SYNOPSYS_UNCONNECTED_6979 ) , .clk_2_W_in ( clk_2_wires[69] ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6980 ) , - .clk_2_E_out ( clk_2_wires[70] ) , .clk_3_W_in ( p1887 ) , - .clk_3_E_in ( p164 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6981 ) , + .clk_2_E_out ( clk_2_wires[70] ) , .clk_3_W_in ( p1635 ) , + .clk_3_E_in ( p945 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6981 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6982 ) ) ; cbx_1__1_ cbx_9__3_ ( .pReset ( { SYNOPSYS_UNCONNECTED_6983 } ) , @@ -122251,7 +126773,7 @@ cbx_1__1_ cbx_9__3_ ( .bottom_grid_pin_14_ ( cbx_1__1__90_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__90_bottom_grid_pin_15_ ) , .ccff_tail ( cbx_1__1__90_ccff_tail ) , .SC_IN_TOP ( scff_Wires[230] ) , - .SC_OUT_BOT ( scff_Wires[231] ) , .SC_IN_BOT ( p1533 ) , + .SC_OUT_BOT ( scff_Wires[231] ) , .SC_IN_BOT ( p1456 ) , .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_6984 ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[90] ) , .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[90] ) , @@ -122266,19 +126788,19 @@ cbx_1__1_ cbx_9__3_ ( .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_6988 ) , .prog_clk_1_E_in ( prog_clk_1_wires[177] ) , .prog_clk_1_N_out ( prog_clk_1_wires[178] ) , - .prog_clk_1_S_out ( prog_clk_1_wires[179] ) , .prog_clk_2_E_in ( p2605 ) , - .prog_clk_2_W_in ( p977 ) , + .prog_clk_1_S_out ( prog_clk_1_wires[179] ) , .prog_clk_2_E_in ( p3345 ) , + .prog_clk_2_W_in ( p2686 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6989 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6990 ) , - .prog_clk_3_W_in ( p3248 ) , .prog_clk_3_E_in ( p817 ) , + .prog_clk_3_W_in ( p2780 ) , .prog_clk_3_E_in ( p3281 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6991 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6992 ) , .clk_1_W_in ( SYNOPSYS_UNCONNECTED_6993 ) , .clk_1_E_in ( clk_1_wires[177] ) , .clk_1_N_out ( clk_1_wires[178] ) , - .clk_1_S_out ( clk_1_wires[179] ) , .clk_2_E_in ( p2605 ) , - .clk_2_W_in ( p3230 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6994 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6995 ) , .clk_3_W_in ( p2229 ) , - .clk_3_E_in ( p2568 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6996 ) , + .clk_1_S_out ( clk_1_wires[179] ) , .clk_2_E_in ( p1404 ) , + .clk_2_W_in ( p83 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6994 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6995 ) , .clk_3_W_in ( p1311 ) , + .clk_3_E_in ( p779 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6996 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6997 ) ) ; cbx_1__1_ cbx_9__4_ ( .pReset ( { SYNOPSYS_UNCONNECTED_6998 } ) , @@ -122304,7 +126826,7 @@ cbx_1__1_ cbx_9__4_ ( .bottom_grid_pin_14_ ( cbx_1__1__91_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__91_bottom_grid_pin_15_ ) , .ccff_tail ( cbx_1__1__91_ccff_tail ) , .SC_IN_TOP ( scff_Wires[228] ) , - .SC_OUT_BOT ( scff_Wires[229] ) , .SC_IN_BOT ( p1449 ) , + .SC_OUT_BOT ( scff_Wires[229] ) , .SC_IN_BOT ( p1841 ) , .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_6999 ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[91] ) , .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[91] ) , @@ -122316,23 +126838,23 @@ cbx_1__1_ cbx_9__4_ ( .pReset_S_out ( pResetWires[243] ) , .pReset_E_out ( pResetWires[242] ) , .prog_clk_0_N_in ( prog_clk_0_wires[341] ) , .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_7002 ) , - .prog_clk_1_W_in ( p1549 ) , .prog_clk_1_E_in ( p150 ) , + .prog_clk_1_W_in ( p1145 ) , .prog_clk_1_E_in ( p1676 ) , .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_7003 ) , .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_7004 ) , .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_7005 ) , .prog_clk_2_W_in ( prog_clk_2_wires[78] ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_7006 ) , - .prog_clk_2_E_out ( prog_clk_2_wires[79] ) , .prog_clk_3_W_in ( p809 ) , - .prog_clk_3_E_in ( p1212 ) , + .prog_clk_2_E_out ( prog_clk_2_wires[79] ) , .prog_clk_3_W_in ( p1263 ) , + .prog_clk_3_E_in ( p465 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_7007 ) , - .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_7008 ) , .clk_1_W_in ( p1482 ) , - .clk_1_E_in ( p489 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_7009 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_7008 ) , .clk_1_W_in ( p1263 ) , + .clk_1_E_in ( p2162 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_7009 ) , .clk_1_S_out ( SYNOPSYS_UNCONNECTED_7010 ) , .clk_2_E_in ( SYNOPSYS_UNCONNECTED_7011 ) , .clk_2_W_in ( clk_2_wires[78] ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7012 ) , - .clk_2_E_out ( clk_2_wires[79] ) , .clk_3_W_in ( p809 ) , - .clk_3_E_in ( p526 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7013 ) , + .clk_2_E_out ( clk_2_wires[79] ) , .clk_3_W_in ( p1263 ) , + .clk_3_E_in ( p2086 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7013 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7014 ) ) ; cbx_1__1_ cbx_9__5_ ( .pReset ( { SYNOPSYS_UNCONNECTED_7015 } ) , @@ -122358,7 +126880,7 @@ cbx_1__1_ cbx_9__5_ ( .bottom_grid_pin_14_ ( cbx_1__1__92_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__92_bottom_grid_pin_15_ ) , .ccff_tail ( cbx_1__1__92_ccff_tail ) , .SC_IN_TOP ( scff_Wires[226] ) , - .SC_OUT_BOT ( scff_Wires[227] ) , .SC_IN_BOT ( p1611 ) , + .SC_OUT_BOT ( scff_Wires[227] ) , .SC_IN_BOT ( p1511 ) , .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_7016 ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[92] ) , .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[92] ) , @@ -122373,19 +126895,19 @@ cbx_1__1_ cbx_9__5_ ( .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_7020 ) , .prog_clk_1_E_in ( prog_clk_1_wires[184] ) , .prog_clk_1_N_out ( prog_clk_1_wires[185] ) , - .prog_clk_1_S_out ( prog_clk_1_wires[186] ) , .prog_clk_2_E_in ( p1598 ) , - .prog_clk_2_W_in ( p415 ) , + .prog_clk_1_S_out ( prog_clk_1_wires[186] ) , .prog_clk_2_E_in ( p2855 ) , + .prog_clk_2_W_in ( p696 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_7021 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_7022 ) , - .prog_clk_3_W_in ( p3366 ) , .prog_clk_3_E_in ( p1245 ) , + .prog_clk_3_W_in ( p1213 ) , .prog_clk_3_E_in ( p2657 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_7023 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_7024 ) , .clk_1_W_in ( SYNOPSYS_UNCONNECTED_7025 ) , .clk_1_E_in ( clk_1_wires[184] ) , .clk_1_N_out ( clk_1_wires[185] ) , - .clk_1_S_out ( clk_1_wires[186] ) , .clk_2_E_in ( p1598 ) , - .clk_2_W_in ( p3338 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7026 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7027 ) , .clk_3_W_in ( p2778 ) , - .clk_3_E_in ( p487 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7028 ) , + .clk_1_S_out ( clk_1_wires[186] ) , .clk_2_E_in ( p2330 ) , + .clk_2_W_in ( p1777 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7026 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7027 ) , .clk_3_W_in ( p2019 ) , + .clk_3_E_in ( p2177 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7028 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7029 ) ) ; cbx_1__1_ cbx_9__6_ ( .pReset ( { SYNOPSYS_UNCONNECTED_7030 } ) , @@ -122411,7 +126933,7 @@ cbx_1__1_ cbx_9__6_ ( .bottom_grid_pin_14_ ( cbx_1__1__93_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__93_bottom_grid_pin_15_ ) , .ccff_tail ( cbx_1__1__93_ccff_tail ) , .SC_IN_TOP ( scff_Wires[224] ) , - .SC_OUT_BOT ( scff_Wires[225] ) , .SC_IN_BOT ( p1587 ) , + .SC_OUT_BOT ( scff_Wires[225] ) , .SC_IN_BOT ( p1314 ) , .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_7031 ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[93] ) , .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[93] ) , @@ -122423,19 +126945,19 @@ cbx_1__1_ cbx_9__6_ ( .pReset_S_out ( pResetWires[341] ) , .pReset_E_out ( pResetWires[340] ) , .prog_clk_0_N_in ( prog_clk_0_wires[347] ) , .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_7034 ) , - .prog_clk_1_W_in ( p1599 ) , .prog_clk_1_E_in ( p747 ) , + .prog_clk_1_W_in ( p1322 ) , .prog_clk_1_E_in ( p431 ) , .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_7035 ) , .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_7036 ) , - .prog_clk_2_E_in ( p1379 ) , .prog_clk_2_W_in ( p1048 ) , + .prog_clk_2_E_in ( p1482 ) , .prog_clk_2_W_in ( p2434 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_7037 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_7038 ) , .prog_clk_3_W_in ( prog_clk_3_wires[44] ) , .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_7039 ) , .prog_clk_3_E_out ( prog_clk_3_wires[45] ) , - .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_7040 ) , .clk_1_W_in ( p1494 ) , - .clk_1_E_in ( p586 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_7041 ) , - .clk_1_S_out ( SYNOPSYS_UNCONNECTED_7042 ) , .clk_2_E_in ( p1379 ) , - .clk_2_W_in ( p506 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7043 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_7040 ) , .clk_1_W_in ( p2632 ) , + .clk_1_E_in ( p901 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_7041 ) , + .clk_1_S_out ( SYNOPSYS_UNCONNECTED_7042 ) , .clk_2_E_in ( p1482 ) , + .clk_2_W_in ( p238 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7043 ) , .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7044 ) , .clk_3_W_in ( clk_3_wires[44] ) , .clk_3_E_in ( SYNOPSYS_UNCONNECTED_7045 ) , @@ -122465,7 +126987,7 @@ cbx_1__1_ cbx_9__7_ ( .bottom_grid_pin_14_ ( cbx_1__1__94_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__94_bottom_grid_pin_15_ ) , .ccff_tail ( cbx_1__1__94_ccff_tail ) , .SC_IN_TOP ( scff_Wires[222] ) , - .SC_OUT_BOT ( scff_Wires[223] ) , .SC_IN_BOT ( p1606 ) , + .SC_OUT_BOT ( scff_Wires[223] ) , .SC_IN_BOT ( p1532 ) , .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_7048 ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[94] ) , .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[94] ) , @@ -122480,19 +127002,19 @@ cbx_1__1_ cbx_9__7_ ( .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_7052 ) , .prog_clk_1_E_in ( prog_clk_1_wires[191] ) , .prog_clk_1_N_out ( prog_clk_1_wires[192] ) , - .prog_clk_1_S_out ( prog_clk_1_wires[193] ) , .prog_clk_2_E_in ( p1797 ) , - .prog_clk_2_W_in ( p605 ) , + .prog_clk_1_S_out ( prog_clk_1_wires[193] ) , .prog_clk_2_E_in ( p2957 ) , + .prog_clk_2_W_in ( p1662 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_7053 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_7054 ) , - .prog_clk_3_W_in ( p3161 ) , .prog_clk_3_E_in ( p1095 ) , + .prog_clk_3_W_in ( p1975 ) , .prog_clk_3_E_in ( p2882 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_7055 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_7056 ) , .clk_1_W_in ( SYNOPSYS_UNCONNECTED_7057 ) , .clk_1_E_in ( clk_1_wires[191] ) , .clk_1_N_out ( clk_1_wires[192] ) , - .clk_1_S_out ( clk_1_wires[193] ) , .clk_2_E_in ( p1797 ) , - .clk_2_W_in ( p3118 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7058 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7059 ) , .clk_3_W_in ( p2996 ) , - .clk_3_E_in ( p1684 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7060 ) , + .clk_1_S_out ( clk_1_wires[193] ) , .clk_2_E_in ( p2288 ) , + .clk_2_W_in ( p3200 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7058 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7059 ) , .clk_3_W_in ( p3235 ) , + .clk_3_E_in ( p2172 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7060 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7061 ) ) ; cbx_1__1_ cbx_9__8_ ( .pReset ( { SYNOPSYS_UNCONNECTED_7062 } ) , @@ -122518,7 +127040,7 @@ cbx_1__1_ cbx_9__8_ ( .bottom_grid_pin_14_ ( cbx_1__1__95_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__95_bottom_grid_pin_15_ ) , .ccff_tail ( cbx_1__1__95_ccff_tail ) , .SC_IN_TOP ( scff_Wires[220] ) , - .SC_OUT_BOT ( scff_Wires[221] ) , .SC_IN_BOT ( p1839 ) , + .SC_OUT_BOT ( scff_Wires[221] ) , .SC_IN_BOT ( p1371 ) , .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_7063 ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[95] ) , .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[95] ) , @@ -122530,23 +127052,23 @@ cbx_1__1_ cbx_9__8_ ( .pReset_S_out ( pResetWires[439] ) , .pReset_E_out ( pResetWires[438] ) , .prog_clk_0_N_in ( prog_clk_0_wires[353] ) , .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_7066 ) , - .prog_clk_1_W_in ( p1324 ) , .prog_clk_1_E_in ( p1652 ) , + .prog_clk_1_W_in ( p1140 ) , .prog_clk_1_E_in ( p500 ) , .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_7067 ) , .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_7068 ) , .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_7069 ) , .prog_clk_2_W_in ( prog_clk_2_wires[91] ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_7070 ) , - .prog_clk_2_E_out ( prog_clk_2_wires[92] ) , .prog_clk_3_W_in ( p1595 ) , - .prog_clk_3_E_in ( p1112 ) , + .prog_clk_2_E_out ( prog_clk_2_wires[92] ) , .prog_clk_3_W_in ( p1021 ) , + .prog_clk_3_E_in ( p909 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_7071 ) , - .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_7072 ) , .clk_1_W_in ( p1414 ) , - .clk_1_E_in ( p1723 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_7073 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_7072 ) , .clk_1_W_in ( p1021 ) , + .clk_1_E_in ( p739 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_7073 ) , .clk_1_S_out ( SYNOPSYS_UNCONNECTED_7074 ) , .clk_2_E_in ( SYNOPSYS_UNCONNECTED_7075 ) , .clk_2_W_in ( clk_2_wires[91] ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7076 ) , - .clk_2_E_out ( clk_2_wires[92] ) , .clk_3_W_in ( p1595 ) , - .clk_3_E_in ( p1734 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7077 ) , + .clk_2_E_out ( clk_2_wires[92] ) , .clk_3_W_in ( p1021 ) , + .clk_3_E_in ( p1 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7077 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7078 ) ) ; cbx_1__1_ cbx_9__9_ ( .pReset ( { SYNOPSYS_UNCONNECTED_7079 } ) , @@ -122572,7 +127094,7 @@ cbx_1__1_ cbx_9__9_ ( .bottom_grid_pin_14_ ( cbx_1__1__96_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__96_bottom_grid_pin_15_ ) , .ccff_tail ( cbx_1__1__96_ccff_tail ) , .SC_IN_TOP ( scff_Wires[218] ) , - .SC_OUT_BOT ( scff_Wires[219] ) , .SC_IN_BOT ( p1334 ) , + .SC_OUT_BOT ( scff_Wires[219] ) , .SC_IN_BOT ( p1641 ) , .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_7080 ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[96] ) , .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[96] ) , @@ -122587,19 +127109,19 @@ cbx_1__1_ cbx_9__9_ ( .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_7084 ) , .prog_clk_1_E_in ( prog_clk_1_wires[198] ) , .prog_clk_1_N_out ( prog_clk_1_wires[199] ) , - .prog_clk_1_S_out ( prog_clk_1_wires[200] ) , .prog_clk_2_E_in ( p1 ) , - .prog_clk_2_W_in ( p155 ) , + .prog_clk_1_S_out ( prog_clk_1_wires[200] ) , .prog_clk_2_E_in ( p2817 ) , + .prog_clk_2_W_in ( p1811 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_7085 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_7086 ) , - .prog_clk_3_W_in ( p3324 ) , .prog_clk_3_E_in ( p918 ) , + .prog_clk_3_W_in ( p1982 ) , .prog_clk_3_E_in ( p2652 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_7087 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_7088 ) , .clk_1_W_in ( SYNOPSYS_UNCONNECTED_7089 ) , .clk_1_E_in ( clk_1_wires[198] ) , .clk_1_N_out ( clk_1_wires[199] ) , - .clk_1_S_out ( clk_1_wires[200] ) , .clk_2_E_in ( p1 ) , - .clk_2_W_in ( p3293 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7090 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7091 ) , .clk_3_W_in ( p2395 ) , - .clk_3_E_in ( p697 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7092 ) , + .clk_1_S_out ( clk_1_wires[200] ) , .clk_2_E_in ( p2607 ) , + .clk_2_W_in ( p2708 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7090 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7091 ) , .clk_3_W_in ( p2840 ) , + .clk_3_E_in ( p2478 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7092 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7093 ) ) ; cbx_1__1_ cbx_9__10_ ( .pReset ( { SYNOPSYS_UNCONNECTED_7094 } ) , @@ -122625,7 +127147,7 @@ cbx_1__1_ cbx_9__10_ ( .bottom_grid_pin_14_ ( cbx_1__1__97_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__97_bottom_grid_pin_15_ ) , .ccff_tail ( cbx_1__1__97_ccff_tail ) , .SC_IN_TOP ( scff_Wires[216] ) , - .SC_OUT_BOT ( scff_Wires[217] ) , .SC_IN_BOT ( p719 ) , + .SC_OUT_BOT ( scff_Wires[217] ) , .SC_IN_BOT ( p1320 ) , .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_7095 ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[97] ) , .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[97] ) , @@ -122637,23 +127159,23 @@ cbx_1__1_ cbx_9__10_ ( .pReset_S_out ( pResetWires[537] ) , .pReset_E_out ( pResetWires[536] ) , .prog_clk_0_N_in ( prog_clk_0_wires[359] ) , .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_7098 ) , - .prog_clk_1_W_in ( p2195 ) , .prog_clk_1_E_in ( p610 ) , + .prog_clk_1_W_in ( p1488 ) , .prog_clk_1_E_in ( p455 ) , .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_7099 ) , .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_7100 ) , .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_7101 ) , .prog_clk_2_W_in ( prog_clk_2_wires[104] ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_7102 ) , - .prog_clk_2_E_out ( prog_clk_2_wires[105] ) , .prog_clk_3_W_in ( p2169 ) , - .prog_clk_3_E_in ( p500 ) , + .prog_clk_2_E_out ( prog_clk_2_wires[105] ) , .prog_clk_3_W_in ( p1386 ) , + .prog_clk_3_E_in ( p1065 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_7103 ) , - .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_7104 ) , .clk_1_W_in ( p1417 ) , - .clk_1_E_in ( p436 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_7105 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_7104 ) , .clk_1_W_in ( p1386 ) , + .clk_1_E_in ( p1810 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_7105 ) , .clk_1_S_out ( SYNOPSYS_UNCONNECTED_7106 ) , .clk_2_E_in ( SYNOPSYS_UNCONNECTED_7107 ) , .clk_2_W_in ( clk_2_wires[104] ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7108 ) , - .clk_2_E_out ( clk_2_wires[105] ) , .clk_3_W_in ( p2169 ) , - .clk_3_E_in ( p1127 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7109 ) , + .clk_2_E_out ( clk_2_wires[105] ) , .clk_3_W_in ( p1386 ) , + .clk_3_E_in ( p1656 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7109 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7110 ) ) ; cbx_1__1_ cbx_9__11_ ( .pReset ( { SYNOPSYS_UNCONNECTED_7111 } ) , @@ -122679,7 +127201,7 @@ cbx_1__1_ cbx_9__11_ ( .bottom_grid_pin_14_ ( cbx_1__1__98_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__98_bottom_grid_pin_15_ ) , .ccff_tail ( cbx_1__1__98_ccff_tail ) , .SC_IN_TOP ( scff_Wires[214] ) , - .SC_OUT_BOT ( scff_Wires[215] ) , .SC_IN_BOT ( p1844 ) , + .SC_OUT_BOT ( scff_Wires[215] ) , .SC_IN_BOT ( p1845 ) , .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_7112 ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[98] ) , .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[98] ) , @@ -122694,19 +127216,19 @@ cbx_1__1_ cbx_9__11_ ( .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_7116 ) , .prog_clk_1_E_in ( prog_clk_1_wires[205] ) , .prog_clk_1_N_out ( prog_clk_1_wires[206] ) , - .prog_clk_1_S_out ( prog_clk_1_wires[207] ) , .prog_clk_2_E_in ( p1537 ) , - .prog_clk_2_W_in ( p1206 ) , + .prog_clk_1_S_out ( prog_clk_1_wires[207] ) , .prog_clk_2_E_in ( p3468 ) , + .prog_clk_2_W_in ( p2459 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_7117 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_7118 ) , - .prog_clk_3_W_in ( p3181 ) , .prog_clk_3_E_in ( p1197 ) , + .prog_clk_3_W_in ( p2603 ) , .prog_clk_3_E_in ( p3428 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_7119 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_7120 ) , .clk_1_W_in ( SYNOPSYS_UNCONNECTED_7121 ) , .clk_1_E_in ( clk_1_wires[205] ) , .clk_1_N_out ( clk_1_wires[206] ) , - .clk_1_S_out ( clk_1_wires[207] ) , .clk_2_E_in ( p1537 ) , - .clk_2_W_in ( p3146 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7122 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7123 ) , .clk_3_W_in ( p2390 ) , - .clk_3_E_in ( p259 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7124 ) , + .clk_1_S_out ( clk_1_wires[207] ) , .clk_2_E_in ( p2510 ) , + .clk_2_W_in ( p3072 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7122 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7123 ) , .clk_3_W_in ( p3169 ) , + .clk_3_E_in ( p2474 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7124 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7125 ) ) ; cbx_1__1_ cbx_10__1_ ( .pReset ( { SYNOPSYS_UNCONNECTED_7126 } ) , @@ -122731,7 +127253,7 @@ cbx_1__1_ cbx_10__1_ ( .bottom_grid_pin_13_ ( cbx_1__1__99_bottom_grid_pin_13_ ) , .bottom_grid_pin_14_ ( cbx_1__1__99_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__99_bottom_grid_pin_15_ ) , - .ccff_tail ( cbx_1__1__99_ccff_tail ) , .SC_IN_TOP ( p1541 ) , + .ccff_tail ( cbx_1__1__99_ccff_tail ) , .SC_IN_TOP ( p1254 ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_7127 ) , .SC_IN_BOT ( scff_Wires[241] ) , .SC_OUT_TOP ( scff_Wires[242] ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[99] ) , @@ -122747,20 +127269,20 @@ cbx_1__1_ cbx_10__1_ ( .prog_clk_1_W_in ( prog_clk_1_wires[169] ) , .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_7131 ) , .prog_clk_1_N_out ( prog_clk_1_wires[173] ) , - .prog_clk_1_S_out ( prog_clk_1_wires[174] ) , .prog_clk_2_E_in ( p2175 ) , - .prog_clk_2_W_in ( p1775 ) , + .prog_clk_1_S_out ( prog_clk_1_wires[174] ) , .prog_clk_2_E_in ( p2626 ) , + .prog_clk_2_W_in ( p3224 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_7132 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_7133 ) , - .prog_clk_3_W_in ( p3198 ) , .prog_clk_3_E_in ( p1305 ) , + .prog_clk_3_W_in ( p3238 ) , .prog_clk_3_E_in ( p2499 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_7134 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_7135 ) , .clk_1_W_in ( clk_1_wires[169] ) , .clk_1_E_in ( SYNOPSYS_UNCONNECTED_7136 ) , .clk_1_N_out ( clk_1_wires[173] ) , .clk_1_S_out ( clk_1_wires[174] ) , - .clk_2_E_in ( p2175 ) , .clk_2_W_in ( p3156 ) , + .clk_2_E_in ( p1265 ) , .clk_2_W_in ( p3393 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7137 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7138 ) , .clk_3_W_in ( p2644 ) , - .clk_3_E_in ( p2099 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7139 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7138 ) , .clk_3_W_in ( p3406 ) , + .clk_3_E_in ( p1605 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7139 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7140 ) ) ; cbx_1__1_ cbx_10__2_ ( .pReset ( { SYNOPSYS_UNCONNECTED_7141 } ) , @@ -122785,7 +127307,7 @@ cbx_1__1_ cbx_10__2_ ( .bottom_grid_pin_13_ ( cbx_1__1__100_bottom_grid_pin_13_ ) , .bottom_grid_pin_14_ ( cbx_1__1__100_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__100_bottom_grid_pin_15_ ) , - .ccff_tail ( cbx_1__1__100_ccff_tail ) , .SC_IN_TOP ( p1771 ) , + .ccff_tail ( cbx_1__1__100_ccff_tail ) , .SC_IN_TOP ( p1819 ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_7142 ) , .SC_IN_BOT ( scff_Wires[243] ) , .SC_OUT_TOP ( scff_Wires[244] ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[100] ) , @@ -122798,20 +127320,20 @@ cbx_1__1_ cbx_10__2_ ( .pReset_S_out ( pResetWires[149] ) , .pReset_E_out ( pResetWires[148] ) , .prog_clk_0_N_in ( prog_clk_0_wires[373] ) , .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_7145 ) , - .prog_clk_1_W_in ( p2231 ) , .prog_clk_1_E_in ( p1258 ) , + .prog_clk_1_W_in ( p1430 ) , .prog_clk_1_E_in ( p1179 ) , .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_7146 ) , .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_7147 ) , - .prog_clk_2_E_in ( p2681 ) , .prog_clk_2_W_in ( p2080 ) , + .prog_clk_2_E_in ( p1819 ) , .prog_clk_2_W_in ( p3390 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_7148 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_7149 ) , - .prog_clk_3_W_in ( p2367 ) , .prog_clk_3_E_in ( p1890 ) , + .prog_clk_3_W_in ( p3424 ) , .prog_clk_3_E_in ( p1930 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_7150 ) , - .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_7151 ) , .clk_1_W_in ( p1286 ) , - .clk_1_E_in ( p867 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_7152 ) , - .clk_1_S_out ( SYNOPSYS_UNCONNECTED_7153 ) , .clk_2_E_in ( p2681 ) , - .clk_2_W_in ( p2493 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7154 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7155 ) , .clk_3_W_in ( p2419 ) , - .clk_3_E_in ( p2604 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7156 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_7151 ) , .clk_1_W_in ( p2289 ) , + .clk_1_E_in ( p1373 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_7152 ) , + .clk_1_S_out ( SYNOPSYS_UNCONNECTED_7153 ) , .clk_2_E_in ( p1521 ) , + .clk_2_W_in ( p2938 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7154 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7155 ) , .clk_3_W_in ( p2946 ) , + .clk_3_E_in ( p428 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7156 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7157 ) ) ; cbx_1__1_ cbx_10__3_ ( .pReset ( { SYNOPSYS_UNCONNECTED_7158 } ) , @@ -122836,7 +127358,7 @@ cbx_1__1_ cbx_10__3_ ( .bottom_grid_pin_13_ ( cbx_1__1__101_bottom_grid_pin_13_ ) , .bottom_grid_pin_14_ ( cbx_1__1__101_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__101_bottom_grid_pin_15_ ) , - .ccff_tail ( cbx_1__1__101_ccff_tail ) , .SC_IN_TOP ( p1880 ) , + .ccff_tail ( cbx_1__1__101_ccff_tail ) , .SC_IN_TOP ( p1861 ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_7159 ) , .SC_IN_BOT ( scff_Wires[245] ) , .SC_OUT_TOP ( scff_Wires[246] ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[101] ) , @@ -122852,20 +127374,20 @@ cbx_1__1_ cbx_10__3_ ( .prog_clk_1_W_in ( prog_clk_1_wires[176] ) , .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_7163 ) , .prog_clk_1_N_out ( prog_clk_1_wires[180] ) , - .prog_clk_1_S_out ( prog_clk_1_wires[181] ) , .prog_clk_2_E_in ( p2451 ) , - .prog_clk_2_W_in ( p1343 ) , + .prog_clk_1_S_out ( prog_clk_1_wires[181] ) , .prog_clk_2_E_in ( p2190 ) , + .prog_clk_2_W_in ( p3220 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_7164 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_7165 ) , - .prog_clk_3_W_in ( p2822 ) , .prog_clk_3_E_in ( p1779 ) , + .prog_clk_3_W_in ( p3269 ) , .prog_clk_3_E_in ( p2365 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_7166 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_7167 ) , .clk_1_W_in ( clk_1_wires[176] ) , .clk_1_E_in ( SYNOPSYS_UNCONNECTED_7168 ) , .clk_1_N_out ( clk_1_wires[180] ) , .clk_1_S_out ( clk_1_wires[181] ) , - .clk_2_E_in ( p2451 ) , .clk_2_W_in ( p2769 ) , + .clk_2_E_in ( p2189 ) , .clk_2_W_in ( p2925 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7169 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7170 ) , .clk_3_W_in ( p1952 ) , - .clk_3_E_in ( p2347 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7171 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7170 ) , .clk_3_W_in ( p2979 ) , + .clk_3_E_in ( p2156 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7171 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7172 ) ) ; cbx_1__1_ cbx_10__4_ ( .pReset ( { SYNOPSYS_UNCONNECTED_7173 } ) , @@ -122890,7 +127412,7 @@ cbx_1__1_ cbx_10__4_ ( .bottom_grid_pin_13_ ( cbx_1__1__102_bottom_grid_pin_13_ ) , .bottom_grid_pin_14_ ( cbx_1__1__102_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__102_bottom_grid_pin_15_ ) , - .ccff_tail ( cbx_1__1__102_ccff_tail ) , .SC_IN_TOP ( p2427 ) , + .ccff_tail ( cbx_1__1__102_ccff_tail ) , .SC_IN_TOP ( p1610 ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_7174 ) , .SC_IN_BOT ( scff_Wires[247] ) , .SC_OUT_TOP ( scff_Wires[248] ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[102] ) , @@ -122903,20 +127425,20 @@ cbx_1__1_ cbx_10__4_ ( .pReset_S_out ( pResetWires[247] ) , .pReset_E_out ( pResetWires[246] ) , .prog_clk_0_N_in ( prog_clk_0_wires[379] ) , .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_7177 ) , - .prog_clk_1_W_in ( p2613 ) , .prog_clk_1_E_in ( p1096 ) , + .prog_clk_1_W_in ( p1516 ) , .prog_clk_1_E_in ( p847 ) , .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_7178 ) , .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_7179 ) , - .prog_clk_2_E_in ( p1914 ) , .prog_clk_2_W_in ( p2611 ) , + .prog_clk_2_E_in ( p1959 ) , .prog_clk_2_W_in ( p3206 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_7180 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_7181 ) , - .prog_clk_3_W_in ( p3183 ) , .prog_clk_3_E_in ( p2360 ) , + .prog_clk_3_W_in ( p3247 ) , .prog_clk_3_E_in ( p1761 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_7182 ) , - .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_7183 ) , .clk_1_W_in ( p1591 ) , - .clk_1_E_in ( p779 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_7184 ) , - .clk_1_S_out ( SYNOPSYS_UNCONNECTED_7185 ) , .clk_2_E_in ( p1914 ) , - .clk_2_W_in ( p3148 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7186 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7187 ) , .clk_3_W_in ( p2178 ) , - .clk_3_E_in ( p1756 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7188 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_7183 ) , .clk_1_W_in ( p2271 ) , + .clk_1_E_in ( p1050 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_7184 ) , + .clk_1_S_out ( SYNOPSYS_UNCONNECTED_7185 ) , .clk_2_E_in ( p2794 ) , + .clk_2_W_in ( p3103 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7186 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7187 ) , .clk_3_W_in ( p3112 ) , + .clk_3_E_in ( p2733 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7188 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7189 ) ) ; cbx_1__1_ cbx_10__5_ ( .pReset ( { SYNOPSYS_UNCONNECTED_7190 } ) , @@ -122941,7 +127463,7 @@ cbx_1__1_ cbx_10__5_ ( .bottom_grid_pin_13_ ( cbx_1__1__103_bottom_grid_pin_13_ ) , .bottom_grid_pin_14_ ( cbx_1__1__103_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__103_bottom_grid_pin_15_ ) , - .ccff_tail ( cbx_1__1__103_ccff_tail ) , .SC_IN_TOP ( p2108 ) , + .ccff_tail ( cbx_1__1__103_ccff_tail ) , .SC_IN_TOP ( p2244 ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_7191 ) , .SC_IN_BOT ( scff_Wires[249] ) , .SC_OUT_TOP ( scff_Wires[250] ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[103] ) , @@ -122957,20 +127479,20 @@ cbx_1__1_ cbx_10__5_ ( .prog_clk_1_W_in ( prog_clk_1_wires[183] ) , .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_7195 ) , .prog_clk_1_N_out ( prog_clk_1_wires[187] ) , - .prog_clk_1_S_out ( prog_clk_1_wires[188] ) , .prog_clk_2_E_in ( p2142 ) , - .prog_clk_2_W_in ( p1047 ) , + .prog_clk_1_S_out ( prog_clk_1_wires[188] ) , .prog_clk_2_E_in ( p3020 ) , + .prog_clk_2_W_in ( p2495 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_7196 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_7197 ) , - .prog_clk_3_W_in ( p3052 ) , .prog_clk_3_E_in ( p2072 ) , + .prog_clk_3_W_in ( p2608 ) , .prog_clk_3_E_in ( p2931 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_7198 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_7199 ) , .clk_1_W_in ( clk_1_wires[183] ) , .clk_1_E_in ( SYNOPSYS_UNCONNECTED_7200 ) , .clk_1_N_out ( clk_1_wires[187] ) , .clk_1_S_out ( clk_1_wires[188] ) , - .clk_2_E_in ( p2142 ) , .clk_2_W_in ( p3049 ) , + .clk_2_E_in ( p2327 ) , .clk_2_W_in ( p2426 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7201 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7202 ) , .clk_3_W_in ( p1808 ) , - .clk_3_E_in ( p2213 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7203 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7202 ) , .clk_3_W_in ( p2576 ) , + .clk_3_E_in ( p2144 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7203 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7204 ) ) ; cbx_1__1_ cbx_10__6_ ( .pReset ( { SYNOPSYS_UNCONNECTED_7205 } ) , @@ -122995,7 +127517,7 @@ cbx_1__1_ cbx_10__6_ ( .bottom_grid_pin_13_ ( cbx_1__1__104_bottom_grid_pin_13_ ) , .bottom_grid_pin_14_ ( cbx_1__1__104_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__104_bottom_grid_pin_15_ ) , - .ccff_tail ( cbx_1__1__104_ccff_tail ) , .SC_IN_TOP ( p1531 ) , + .ccff_tail ( cbx_1__1__104_ccff_tail ) , .SC_IN_TOP ( p1479 ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_7206 ) , .SC_IN_BOT ( scff_Wires[251] ) , .SC_OUT_TOP ( scff_Wires[252] ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[104] ) , @@ -123008,19 +127530,19 @@ cbx_1__1_ cbx_10__6_ ( .pReset_S_out ( pResetWires[345] ) , .pReset_E_out ( pResetWires[344] ) , .prog_clk_0_N_in ( prog_clk_0_wires[385] ) , .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_7209 ) , - .prog_clk_1_W_in ( p1610 ) , .prog_clk_1_E_in ( p1108 ) , + .prog_clk_1_W_in ( p1512 ) , .prog_clk_1_E_in ( p1000 ) , .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_7210 ) , .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_7211 ) , - .prog_clk_2_E_in ( p1531 ) , .prog_clk_2_W_in ( p1376 ) , + .prog_clk_2_E_in ( p1649 ) , .prog_clk_2_W_in ( p2168 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_7212 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_7213 ) , .prog_clk_3_W_in ( prog_clk_3_wires[48] ) , .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_7214 ) , .prog_clk_3_E_out ( prog_clk_3_wires[49] ) , - .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_7215 ) , .clk_1_W_in ( p1588 ) , - .clk_1_E_in ( p1131 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_7216 ) , - .clk_1_S_out ( SYNOPSYS_UNCONNECTED_7217 ) , .clk_2_E_in ( p1531 ) , - .clk_2_W_in ( p898 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7218 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_7215 ) , .clk_1_W_in ( p2296 ) , + .clk_1_E_in ( p769 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_7216 ) , + .clk_1_S_out ( SYNOPSYS_UNCONNECTED_7217 ) , .clk_2_E_in ( p1344 ) , + .clk_2_W_in ( p1235 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7218 ) , .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7219 ) , .clk_3_W_in ( clk_3_wires[48] ) , .clk_3_E_in ( SYNOPSYS_UNCONNECTED_7220 ) , @@ -123049,7 +127571,7 @@ cbx_1__1_ cbx_10__7_ ( .bottom_grid_pin_13_ ( cbx_1__1__105_bottom_grid_pin_13_ ) , .bottom_grid_pin_14_ ( cbx_1__1__105_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__105_bottom_grid_pin_15_ ) , - .ccff_tail ( cbx_1__1__105_ccff_tail ) , .SC_IN_TOP ( p1454 ) , + .ccff_tail ( cbx_1__1__105_ccff_tail ) , .SC_IN_TOP ( p1539 ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_7223 ) , .SC_IN_BOT ( scff_Wires[253] ) , .SC_OUT_TOP ( scff_Wires[254] ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[105] ) , @@ -123065,20 +127587,20 @@ cbx_1__1_ cbx_10__7_ ( .prog_clk_1_W_in ( prog_clk_1_wires[190] ) , .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_7227 ) , .prog_clk_1_N_out ( prog_clk_1_wires[194] ) , - .prog_clk_1_S_out ( prog_clk_1_wires[195] ) , .prog_clk_2_E_in ( p2418 ) , - .prog_clk_2_W_in ( p1729 ) , + .prog_clk_1_S_out ( prog_clk_1_wires[195] ) , .prog_clk_2_E_in ( p3251 ) , + .prog_clk_2_W_in ( p1068 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_7228 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_7229 ) , - .prog_clk_3_W_in ( p3106 ) , .prog_clk_3_E_in ( p849 ) , + .prog_clk_3_W_in ( p1410 ) , .prog_clk_3_E_in ( p3202 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_7230 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_7231 ) , .clk_1_W_in ( clk_1_wires[190] ) , .clk_1_E_in ( SYNOPSYS_UNCONNECTED_7232 ) , .clk_1_N_out ( clk_1_wires[194] ) , .clk_1_S_out ( clk_1_wires[195] ) , - .clk_2_E_in ( p2418 ) , .clk_2_W_in ( p3046 ) , + .clk_2_E_in ( p2507 ) , .clk_2_W_in ( p3218 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7233 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7234 ) , .clk_3_W_in ( p1805 ) , - .clk_3_E_in ( p2368 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7235 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7234 ) , .clk_3_W_in ( p3246 ) , + .clk_3_E_in ( p2506 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7235 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7236 ) ) ; cbx_1__1_ cbx_10__8_ ( .pReset ( { SYNOPSYS_UNCONNECTED_7237 } ) , @@ -123103,7 +127625,7 @@ cbx_1__1_ cbx_10__8_ ( .bottom_grid_pin_13_ ( cbx_1__1__106_bottom_grid_pin_13_ ) , .bottom_grid_pin_14_ ( cbx_1__1__106_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__106_bottom_grid_pin_15_ ) , - .ccff_tail ( cbx_1__1__106_ccff_tail ) , .SC_IN_TOP ( p1856 ) , + .ccff_tail ( cbx_1__1__106_ccff_tail ) , .SC_IN_TOP ( p2268 ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_7238 ) , .SC_IN_BOT ( scff_Wires[255] ) , .SC_OUT_TOP ( scff_Wires[256] ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[106] ) , @@ -123116,20 +127638,20 @@ cbx_1__1_ cbx_10__8_ ( .pReset_S_out ( pResetWires[443] ) , .pReset_E_out ( pResetWires[442] ) , .prog_clk_0_N_in ( prog_clk_0_wires[391] ) , .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_7241 ) , - .prog_clk_1_W_in ( p2516 ) , .prog_clk_1_E_in ( p462 ) , + .prog_clk_1_W_in ( p1513 ) , .prog_clk_1_E_in ( p462 ) , .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_7242 ) , .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_7243 ) , - .prog_clk_2_E_in ( p2863 ) , .prog_clk_2_W_in ( p2316 ) , + .prog_clk_2_E_in ( p3395 ) , .prog_clk_2_W_in ( p3314 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_7244 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_7245 ) , - .prog_clk_3_W_in ( p3330 ) , .prog_clk_3_E_in ( p1693 ) , + .prog_clk_3_W_in ( p3340 ) , .prog_clk_3_E_in ( p3376 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_7246 ) , - .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_7247 ) , .clk_1_W_in ( p1820 ) , - .clk_1_E_in ( p678 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_7248 ) , - .clk_1_S_out ( SYNOPSYS_UNCONNECTED_7249 ) , .clk_2_E_in ( p2863 ) , - .clk_2_W_in ( p3302 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7250 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7251 ) , .clk_3_W_in ( p2238 ) , - .clk_3_E_in ( p2751 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7252 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_7247 ) , .clk_1_W_in ( p1134 ) , + .clk_1_E_in ( p619 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_7248 ) , + .clk_1_S_out ( SYNOPSYS_UNCONNECTED_7249 ) , .clk_2_E_in ( p2748 ) , + .clk_2_W_in ( p3049 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7250 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7251 ) , .clk_3_W_in ( p3144 ) , + .clk_3_E_in ( p2745 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7252 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7253 ) ) ; cbx_1__1_ cbx_10__9_ ( .pReset ( { SYNOPSYS_UNCONNECTED_7254 } ) , @@ -123154,7 +127676,7 @@ cbx_1__1_ cbx_10__9_ ( .bottom_grid_pin_13_ ( cbx_1__1__107_bottom_grid_pin_13_ ) , .bottom_grid_pin_14_ ( cbx_1__1__107_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__107_bottom_grid_pin_15_ ) , - .ccff_tail ( cbx_1__1__107_ccff_tail ) , .SC_IN_TOP ( p2244 ) , + .ccff_tail ( cbx_1__1__107_ccff_tail ) , .SC_IN_TOP ( p1988 ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_7255 ) , .SC_IN_BOT ( scff_Wires[257] ) , .SC_OUT_TOP ( scff_Wires[258] ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[107] ) , @@ -123170,20 +127692,20 @@ cbx_1__1_ cbx_10__9_ ( .prog_clk_1_W_in ( prog_clk_1_wires[197] ) , .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_7259 ) , .prog_clk_1_N_out ( prog_clk_1_wires[201] ) , - .prog_clk_1_S_out ( prog_clk_1_wires[202] ) , .prog_clk_2_E_in ( p1479 ) , - .prog_clk_2_W_in ( p689 ) , + .prog_clk_1_S_out ( prog_clk_1_wires[202] ) , .prog_clk_2_E_in ( p1988 ) , + .prog_clk_2_W_in ( p2487 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_7260 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_7261 ) , - .prog_clk_3_W_in ( p1423 ) , .prog_clk_3_E_in ( p2050 ) , + .prog_clk_3_W_in ( p2599 ) , .prog_clk_3_E_in ( p1794 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_7262 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_7263 ) , .clk_1_W_in ( clk_1_wires[197] ) , .clk_1_E_in ( SYNOPSYS_UNCONNECTED_7264 ) , .clk_1_N_out ( clk_1_wires[201] ) , .clk_1_S_out ( clk_1_wires[202] ) , - .clk_2_E_in ( p1479 ) , .clk_2_W_in ( p2917 ) , + .clk_2_E_in ( p1827 ) , .clk_2_W_in ( p1833 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7265 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7266 ) , .clk_3_W_in ( p2952 ) , - .clk_3_E_in ( p1315 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7267 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7266 ) , .clk_3_W_in ( p1948 ) , + .clk_3_E_in ( p1873 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7267 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7268 ) ) ; cbx_1__1_ cbx_10__10_ ( .pReset ( { SYNOPSYS_UNCONNECTED_7269 } ) , @@ -123208,7 +127730,7 @@ cbx_1__1_ cbx_10__10_ ( .bottom_grid_pin_13_ ( cbx_1__1__108_bottom_grid_pin_13_ ) , .bottom_grid_pin_14_ ( cbx_1__1__108_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__108_bottom_grid_pin_15_ ) , - .ccff_tail ( cbx_1__1__108_ccff_tail ) , .SC_IN_TOP ( p1239 ) , + .ccff_tail ( cbx_1__1__108_ccff_tail ) , .SC_IN_TOP ( p1487 ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_7270 ) , .SC_IN_BOT ( scff_Wires[259] ) , .SC_OUT_TOP ( scff_Wires[260] ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[108] ) , @@ -123221,20 +127743,20 @@ cbx_1__1_ cbx_10__10_ ( .pReset_S_out ( pResetWires[541] ) , .pReset_E_out ( pResetWires[540] ) , .prog_clk_0_N_in ( prog_clk_0_wires[397] ) , .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_7273 ) , - .prog_clk_1_W_in ( p1233 ) , .prog_clk_1_E_in ( p1037 ) , + .prog_clk_1_W_in ( p1157 ) , .prog_clk_1_E_in ( p993 ) , .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_7274 ) , .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_7275 ) , - .prog_clk_2_E_in ( p1583 ) , .prog_clk_2_W_in ( p1373 ) , + .prog_clk_2_E_in ( p1293 ) , .prog_clk_2_W_in ( p1389 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_7276 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_7277 ) , - .prog_clk_3_W_in ( p1373 ) , .prog_clk_3_E_in ( p1239 ) , + .prog_clk_3_W_in ( p1389 ) , .prog_clk_3_E_in ( p1293 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_7278 ) , - .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_7279 ) , .clk_1_W_in ( p1467 ) , - .clk_1_E_in ( p853 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_7280 ) , - .clk_1_S_out ( SYNOPSYS_UNCONNECTED_7281 ) , .clk_2_E_in ( p1583 ) , - .clk_2_W_in ( p1373 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7282 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7283 ) , .clk_3_W_in ( p1373 ) , - .clk_3_E_in ( p1239 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7284 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_7279 ) , .clk_1_W_in ( p1389 ) , + .clk_1_E_in ( p835 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_7280 ) , + .clk_1_S_out ( SYNOPSYS_UNCONNECTED_7281 ) , .clk_2_E_in ( p1507 ) , + .clk_2_W_in ( p1389 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7282 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7283 ) , .clk_3_W_in ( p1389 ) , + .clk_3_E_in ( p1507 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7284 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7285 ) ) ; cbx_1__1_ cbx_10__11_ ( .pReset ( { SYNOPSYS_UNCONNECTED_7286 } ) , @@ -123259,7 +127781,7 @@ cbx_1__1_ cbx_10__11_ ( .bottom_grid_pin_13_ ( cbx_1__1__109_bottom_grid_pin_13_ ) , .bottom_grid_pin_14_ ( cbx_1__1__109_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__109_bottom_grid_pin_15_ ) , - .ccff_tail ( cbx_1__1__109_ccff_tail ) , .SC_IN_TOP ( p2125 ) , + .ccff_tail ( cbx_1__1__109_ccff_tail ) , .SC_IN_TOP ( p1485 ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_7287 ) , .SC_IN_BOT ( scff_Wires[261] ) , .SC_OUT_TOP ( scff_Wires[262] ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[109] ) , @@ -123275,20 +127797,20 @@ cbx_1__1_ cbx_10__11_ ( .prog_clk_1_W_in ( prog_clk_1_wires[204] ) , .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_7291 ) , .prog_clk_1_N_out ( prog_clk_1_wires[208] ) , - .prog_clk_1_S_out ( prog_clk_1_wires[209] ) , .prog_clk_2_E_in ( p1963 ) , - .prog_clk_2_W_in ( p1746 ) , + .prog_clk_1_S_out ( prog_clk_1_wires[209] ) , .prog_clk_2_E_in ( p1485 ) , + .prog_clk_2_W_in ( p1166 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_7292 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_7293 ) , - .prog_clk_3_W_in ( p3045 ) , .prog_clk_3_E_in ( p2125 ) , + .prog_clk_3_W_in ( p1166 ) , .prog_clk_3_E_in ( p1485 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_7294 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_7295 ) , .clk_1_W_in ( clk_1_wires[204] ) , .clk_1_E_in ( SYNOPSYS_UNCONNECTED_7296 ) , .clk_1_N_out ( clk_1_wires[208] ) , .clk_1_S_out ( clk_1_wires[209] ) , - .clk_2_E_in ( p1963 ) , .clk_2_W_in ( p3045 ) , + .clk_2_E_in ( p2196 ) , .clk_2_W_in ( p1244 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7297 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7298 ) , .clk_3_W_in ( p3070 ) , - .clk_3_E_in ( p2104 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7299 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7298 ) , .clk_3_W_in ( p1244 ) , + .clk_3_E_in ( p2235 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7299 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7300 ) ) ; cbx_1__1_ cbx_11__1_ ( .pReset ( { SYNOPSYS_UNCONNECTED_7301 } ) , @@ -123314,7 +127836,7 @@ cbx_1__1_ cbx_11__1_ ( .bottom_grid_pin_14_ ( cbx_1__1__110_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__110_bottom_grid_pin_15_ ) , .ccff_tail ( cbx_1__1__110_ccff_tail ) , .SC_IN_TOP ( scff_Wires[287] ) , - .SC_OUT_BOT ( scff_Wires[288] ) , .SC_IN_BOT ( p1433 ) , + .SC_OUT_BOT ( scff_Wires[288] ) , .SC_IN_BOT ( p1594 ) , .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_7302 ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[110] ) , .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[110] ) , @@ -123329,19 +127851,19 @@ cbx_1__1_ cbx_11__1_ ( .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_7306 ) , .prog_clk_1_E_in ( prog_clk_1_wires[212] ) , .prog_clk_1_N_out ( prog_clk_1_wires[213] ) , - .prog_clk_1_S_out ( prog_clk_1_wires[214] ) , .prog_clk_2_E_in ( p1901 ) , - .prog_clk_2_W_in ( p813 ) , + .prog_clk_1_S_out ( prog_clk_1_wires[214] ) , .prog_clk_2_E_in ( p2332 ) , + .prog_clk_2_W_in ( p2725 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_7307 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_7308 ) , - .prog_clk_3_W_in ( p2660 ) , .prog_clk_3_E_in ( p1896 ) , + .prog_clk_3_W_in ( p2773 ) , .prog_clk_3_E_in ( p2188 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_7309 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_7310 ) , .clk_1_W_in ( SYNOPSYS_UNCONNECTED_7311 ) , .clk_1_E_in ( clk_1_wires[212] ) , .clk_1_N_out ( clk_1_wires[213] ) , - .clk_1_S_out ( clk_1_wires[214] ) , .clk_2_E_in ( p1901 ) , - .clk_2_W_in ( p2914 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7312 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7313 ) , .clk_3_W_in ( p2951 ) , - .clk_3_E_in ( p1752 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7314 ) , + .clk_1_S_out ( clk_1_wires[214] ) , .clk_2_E_in ( p1317 ) , + .clk_2_W_in ( p1082 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7312 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7313 ) , .clk_3_W_in ( p1592 ) , + .clk_3_E_in ( p689 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7314 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7315 ) ) ; cbx_1__1_ cbx_11__2_ ( .pReset ( { SYNOPSYS_UNCONNECTED_7316 } ) , @@ -123367,7 +127889,7 @@ cbx_1__1_ cbx_11__2_ ( .bottom_grid_pin_14_ ( cbx_1__1__111_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__111_bottom_grid_pin_15_ ) , .ccff_tail ( cbx_1__1__111_ccff_tail ) , .SC_IN_TOP ( scff_Wires[285] ) , - .SC_OUT_BOT ( scff_Wires[286] ) , .SC_IN_BOT ( p2127 ) , + .SC_OUT_BOT ( scff_Wires[286] ) , .SC_IN_BOT ( p1464 ) , .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_7317 ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[111] ) , .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[111] ) , @@ -123379,23 +127901,23 @@ cbx_1__1_ cbx_11__2_ ( .pReset_S_out ( pResetWires[153] ) , .pReset_E_out ( pResetWires[152] ) , .prog_clk_0_N_in ( prog_clk_0_wires[411] ) , .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_7320 ) , - .prog_clk_1_W_in ( p1399 ) , .prog_clk_1_E_in ( p1737 ) , + .prog_clk_1_W_in ( p1162 ) , .prog_clk_1_E_in ( p718 ) , .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_7321 ) , .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_7322 ) , .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_7323 ) , .prog_clk_2_W_in ( prog_clk_2_wires[114] ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_7324 ) , - .prog_clk_2_E_out ( prog_clk_2_wires[113] ) , .prog_clk_3_W_in ( p1413 ) , - .prog_clk_3_E_in ( p1339 ) , + .prog_clk_2_E_out ( prog_clk_2_wires[113] ) , .prog_clk_3_W_in ( p1162 ) , + .prog_clk_3_E_in ( p722 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_7325 ) , - .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_7326 ) , .clk_1_W_in ( p1453 ) , - .clk_1_E_in ( p2066 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_7327 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_7326 ) , .clk_1_W_in ( p1162 ) , + .clk_1_E_in ( p1848 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_7327 ) , .clk_1_S_out ( SYNOPSYS_UNCONNECTED_7328 ) , .clk_2_E_in ( SYNOPSYS_UNCONNECTED_7329 ) , .clk_2_W_in ( clk_2_wires[114] ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7330 ) , - .clk_2_E_out ( clk_2_wires[113] ) , .clk_3_W_in ( p1413 ) , - .clk_3_E_in ( p1724 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7331 ) , + .clk_2_E_out ( clk_2_wires[113] ) , .clk_3_W_in ( p1851 ) , + .clk_3_E_in ( p1764 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7331 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7332 ) ) ; cbx_1__1_ cbx_11__3_ ( .pReset ( { SYNOPSYS_UNCONNECTED_7333 } ) , @@ -123421,7 +127943,7 @@ cbx_1__1_ cbx_11__3_ ( .bottom_grid_pin_14_ ( cbx_1__1__112_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__112_bottom_grid_pin_15_ ) , .ccff_tail ( cbx_1__1__112_ccff_tail ) , .SC_IN_TOP ( scff_Wires[283] ) , - .SC_OUT_BOT ( scff_Wires[284] ) , .SC_IN_BOT ( p1603 ) , + .SC_OUT_BOT ( scff_Wires[284] ) , .SC_IN_BOT ( p2022 ) , .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_7334 ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[112] ) , .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[112] ) , @@ -123436,19 +127958,19 @@ cbx_1__1_ cbx_11__3_ ( .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_7338 ) , .prog_clk_1_E_in ( prog_clk_1_wires[219] ) , .prog_clk_1_N_out ( prog_clk_1_wires[220] ) , - .prog_clk_1_S_out ( prog_clk_1_wires[221] ) , .prog_clk_2_E_in ( p2507 ) , - .prog_clk_2_W_in ( p1204 ) , + .prog_clk_1_S_out ( prog_clk_1_wires[221] ) , .prog_clk_2_E_in ( p2236 ) , + .prog_clk_2_W_in ( p3034 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_7339 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_7340 ) , - .prog_clk_3_W_in ( p2953 ) , .prog_clk_3_E_in ( p607 ) , + .prog_clk_3_W_in ( p3143 ) , .prog_clk_3_E_in ( p2181 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_7341 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_7342 ) , .clk_1_W_in ( SYNOPSYS_UNCONNECTED_7343 ) , .clk_1_E_in ( clk_1_wires[219] ) , .clk_1_N_out ( clk_1_wires[220] ) , - .clk_1_S_out ( clk_1_wires[221] ) , .clk_2_E_in ( p2507 ) , - .clk_2_W_in ( p2913 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7344 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7345 ) , .clk_3_W_in ( p1888 ) , - .clk_3_E_in ( p2383 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7346 ) , + .clk_1_S_out ( clk_1_wires[221] ) , .clk_2_E_in ( p2042 ) , + .clk_2_W_in ( p2734 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7344 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7345 ) , .clk_3_W_in ( p2676 ) , + .clk_3_E_in ( p1786 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7346 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7347 ) ) ; cbx_1__1_ cbx_11__4_ ( .pReset ( { SYNOPSYS_UNCONNECTED_7348 } ) , @@ -123474,7 +127996,7 @@ cbx_1__1_ cbx_11__4_ ( .bottom_grid_pin_14_ ( cbx_1__1__113_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__113_bottom_grid_pin_15_ ) , .ccff_tail ( cbx_1__1__113_ccff_tail ) , .SC_IN_TOP ( scff_Wires[281] ) , - .SC_OUT_BOT ( scff_Wires[282] ) , .SC_IN_BOT ( p1143 ) , + .SC_OUT_BOT ( scff_Wires[282] ) , .SC_IN_BOT ( p1974 ) , .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_7349 ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[113] ) , .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[113] ) , @@ -123486,23 +128008,23 @@ cbx_1__1_ cbx_11__4_ ( .pReset_S_out ( pResetWires[251] ) , .pReset_E_out ( pResetWires[250] ) , .prog_clk_0_N_in ( prog_clk_0_wires[417] ) , .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_7352 ) , - .prog_clk_1_W_in ( p1504 ) , .prog_clk_1_E_in ( p2380 ) , + .prog_clk_1_W_in ( p1333 ) , .prog_clk_1_E_in ( p1835 ) , .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_7353 ) , .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_7354 ) , .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_7355 ) , .prog_clk_2_W_in ( prog_clk_2_wires[119] ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_7356 ) , - .prog_clk_2_E_out ( prog_clk_2_wires[118] ) , .prog_clk_3_W_in ( p1306 ) , - .prog_clk_3_E_in ( p541 ) , + .prog_clk_2_E_out ( prog_clk_2_wires[118] ) , .prog_clk_3_W_in ( p1243 ) , + .prog_clk_3_E_in ( p1242 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_7357 ) , - .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_7358 ) , .clk_1_W_in ( p1473 ) , - .clk_1_E_in ( p1023 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_7359 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_7358 ) , .clk_1_W_in ( p1243 ) , + .clk_1_E_in ( p2477 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_7359 ) , .clk_1_S_out ( SYNOPSYS_UNCONNECTED_7360 ) , .clk_2_E_in ( SYNOPSYS_UNCONNECTED_7361 ) , .clk_2_W_in ( clk_2_wires[119] ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7362 ) , - .clk_2_E_out ( clk_2_wires[118] ) , .clk_3_W_in ( p1306 ) , - .clk_3_E_in ( p2276 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7363 ) , + .clk_2_E_out ( clk_2_wires[118] ) , .clk_3_W_in ( p1243 ) , + .clk_3_E_in ( p2457 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7363 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7364 ) ) ; cbx_1__1_ cbx_11__5_ ( .pReset ( { SYNOPSYS_UNCONNECTED_7365 } ) , @@ -123528,7 +128050,7 @@ cbx_1__1_ cbx_11__5_ ( .bottom_grid_pin_14_ ( cbx_1__1__114_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__114_bottom_grid_pin_15_ ) , .ccff_tail ( cbx_1__1__114_ccff_tail ) , .SC_IN_TOP ( scff_Wires[279] ) , - .SC_OUT_BOT ( scff_Wires[280] ) , .SC_IN_BOT ( p2144 ) , + .SC_OUT_BOT ( scff_Wires[280] ) , .SC_IN_BOT ( p1372 ) , .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_7366 ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[114] ) , .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[114] ) , @@ -123543,19 +128065,19 @@ cbx_1__1_ cbx_11__5_ ( .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_7370 ) , .prog_clk_1_E_in ( prog_clk_1_wires[226] ) , .prog_clk_1_N_out ( prog_clk_1_wires[227] ) , - .prog_clk_1_S_out ( prog_clk_1_wires[228] ) , .prog_clk_2_E_in ( p2450 ) , - .prog_clk_2_W_in ( p1252 ) , + .prog_clk_1_S_out ( prog_clk_1_wires[228] ) , .prog_clk_2_E_in ( p3117 ) , + .prog_clk_2_W_in ( p3364 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_7371 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_7372 ) , - .prog_clk_3_W_in ( p2925 ) , .prog_clk_3_E_in ( p974 ) , + .prog_clk_3_W_in ( p3420 ) , .prog_clk_3_E_in ( p3094 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_7373 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_7374 ) , .clk_1_W_in ( SYNOPSYS_UNCONNECTED_7375 ) , .clk_1_E_in ( clk_1_wires[226] ) , .clk_1_N_out ( clk_1_wires[227] ) , - .clk_1_S_out ( clk_1_wires[228] ) , .clk_2_E_in ( p2450 ) , - .clk_2_W_in ( p2920 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7376 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7377 ) , .clk_3_W_in ( p2663 ) , - .clk_3_E_in ( p2377 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7378 ) , + .clk_1_S_out ( clk_1_wires[228] ) , .clk_2_E_in ( p1998 ) , + .clk_2_W_in ( p1402 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7376 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7377 ) , .clk_3_W_in ( p1045 ) , + .clk_3_E_in ( p1830 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7378 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7379 ) ) ; cbx_1__1_ cbx_11__6_ ( .pReset ( { SYNOPSYS_UNCONNECTED_7380 } ) , @@ -123581,7 +128103,7 @@ cbx_1__1_ cbx_11__6_ ( .bottom_grid_pin_14_ ( cbx_1__1__115_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__115_bottom_grid_pin_15_ ) , .ccff_tail ( cbx_1__1__115_ccff_tail ) , .SC_IN_TOP ( scff_Wires[277] ) , - .SC_OUT_BOT ( scff_Wires[278] ) , .SC_IN_BOT ( p1102 ) , + .SC_OUT_BOT ( scff_Wires[278] ) , .SC_IN_BOT ( p1585 ) , .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_7381 ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[115] ) , .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[115] ) , @@ -123593,20 +128115,20 @@ cbx_1__1_ cbx_11__6_ ( .pReset_S_out ( pResetWires[349] ) , .pReset_E_out ( pResetWires[348] ) , .prog_clk_0_N_in ( prog_clk_0_wires[423] ) , .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_7384 ) , - .prog_clk_1_W_in ( p2434 ) , .prog_clk_1_E_in ( p770 ) , + .prog_clk_1_W_in ( p1376 ) , .prog_clk_1_E_in ( p614 ) , .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_7385 ) , .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_7386 ) , - .prog_clk_2_E_in ( p2512 ) , .prog_clk_2_W_in ( p2348 ) , + .prog_clk_2_E_in ( p1896 ) , .prog_clk_2_W_in ( p2743 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_7387 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_7388 ) , - .prog_clk_3_W_in ( p1881 ) , .prog_clk_3_E_in ( p1375 ) , + .prog_clk_3_W_in ( p2776 ) , .prog_clk_3_E_in ( p1834 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_7389 ) , - .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_7390 ) , .clk_1_W_in ( p1946 ) , - .clk_1_E_in ( p464 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_7391 ) , - .clk_1_S_out ( SYNOPSYS_UNCONNECTED_7392 ) , .clk_2_E_in ( p2512 ) , - .clk_2_W_in ( p2757 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7393 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7394 ) , .clk_3_W_in ( p2820 ) , - .clk_3_E_in ( p2375 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7395 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_7390 ) , .clk_1_W_in ( p2799 ) , + .clk_1_E_in ( p1135 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_7391 ) , + .clk_1_S_out ( SYNOPSYS_UNCONNECTED_7392 ) , .clk_2_E_in ( p1983 ) , + .clk_2_W_in ( p2915 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7393 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7394 ) , .clk_3_W_in ( p2977 ) , + .clk_3_E_in ( p1660 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7395 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7396 ) ) ; cbx_1__1_ cbx_11__7_ ( .pReset ( { SYNOPSYS_UNCONNECTED_7397 } ) , @@ -123632,7 +128154,7 @@ cbx_1__1_ cbx_11__7_ ( .bottom_grid_pin_14_ ( cbx_1__1__116_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__116_bottom_grid_pin_15_ ) , .ccff_tail ( cbx_1__1__116_ccff_tail ) , .SC_IN_TOP ( scff_Wires[275] ) , - .SC_OUT_BOT ( scff_Wires[276] ) , .SC_IN_BOT ( p1427 ) , + .SC_OUT_BOT ( scff_Wires[276] ) , .SC_IN_BOT ( p1355 ) , .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_7398 ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[116] ) , .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[116] ) , @@ -123647,19 +128169,19 @@ cbx_1__1_ cbx_11__7_ ( .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_7402 ) , .prog_clk_1_E_in ( prog_clk_1_wires[233] ) , .prog_clk_1_N_out ( prog_clk_1_wires[234] ) , - .prog_clk_1_S_out ( prog_clk_1_wires[235] ) , .prog_clk_2_E_in ( p1892 ) , - .prog_clk_2_W_in ( p1177 ) , + .prog_clk_1_S_out ( prog_clk_1_wires[235] ) , .prog_clk_2_E_in ( p3339 ) , + .prog_clk_2_W_in ( p2860 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_7403 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_7404 ) , - .prog_clk_3_W_in ( p3250 ) , .prog_clk_3_E_in ( p1146 ) , + .prog_clk_3_W_in ( p2947 ) , .prog_clk_3_E_in ( p3318 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_7405 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_7406 ) , .clk_1_W_in ( SYNOPSYS_UNCONNECTED_7407 ) , .clk_1_E_in ( clk_1_wires[233] ) , .clk_1_N_out ( clk_1_wires[234] ) , - .clk_1_S_out ( clk_1_wires[235] ) , .clk_2_E_in ( p1892 ) , - .clk_2_W_in ( p3236 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7408 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7409 ) , .clk_3_W_in ( p2686 ) , - .clk_3_E_in ( p1781 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7410 ) , + .clk_1_S_out ( clk_1_wires[235] ) , .clk_2_E_in ( p2590 ) , + .clk_2_W_in ( p3445 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7408 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7409 ) , .clk_3_W_in ( p3467 ) , + .clk_3_E_in ( p2500 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7410 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7411 ) ) ; cbx_1__1_ cbx_11__8_ ( .pReset ( { SYNOPSYS_UNCONNECTED_7412 } ) , @@ -123685,7 +128207,7 @@ cbx_1__1_ cbx_11__8_ ( .bottom_grid_pin_14_ ( cbx_1__1__117_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__117_bottom_grid_pin_15_ ) , .ccff_tail ( cbx_1__1__117_ccff_tail ) , .SC_IN_TOP ( scff_Wires[273] ) , - .SC_OUT_BOT ( scff_Wires[274] ) , .SC_IN_BOT ( p1601 ) , + .SC_OUT_BOT ( scff_Wires[274] ) , .SC_IN_BOT ( p2282 ) , .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_7413 ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[117] ) , .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[117] ) , @@ -123697,23 +128219,23 @@ cbx_1__1_ cbx_11__8_ ( .pReset_S_out ( pResetWires[447] ) , .pReset_E_out ( pResetWires[446] ) , .prog_clk_0_N_in ( prog_clk_0_wires[429] ) , .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_7416 ) , - .prog_clk_1_W_in ( p444 ) , .prog_clk_1_E_in ( p2358 ) , + .prog_clk_1_W_in ( p1620 ) , .prog_clk_1_E_in ( p2110 ) , .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_7417 ) , .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_7418 ) , .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_7419 ) , .prog_clk_2_W_in ( prog_clk_2_wires[126] ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_7420 ) , - .prog_clk_2_E_out ( prog_clk_2_wires[125] ) , .prog_clk_3_W_in ( p1460 ) , - .prog_clk_3_E_in ( p316 ) , + .prog_clk_2_E_out ( prog_clk_2_wires[125] ) , .prog_clk_3_W_in ( p1339 ) , + .prog_clk_3_E_in ( p1186 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_7421 ) , - .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_7422 ) , .clk_1_W_in ( p1284 ) , - .clk_1_E_in ( p423 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_7423 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_7422 ) , .clk_1_W_in ( p1104 ) , + .clk_1_E_in ( p1809 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_7423 ) , .clk_1_S_out ( SYNOPSYS_UNCONNECTED_7424 ) , .clk_2_E_in ( SYNOPSYS_UNCONNECTED_7425 ) , .clk_2_W_in ( clk_2_wires[126] ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7426 ) , - .clk_2_E_out ( clk_2_wires[125] ) , .clk_3_W_in ( p1460 ) , - .clk_3_E_in ( p2345 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7427 ) , + .clk_2_E_out ( clk_2_wires[125] ) , .clk_3_W_in ( p1339 ) , + .clk_3_E_in ( p1720 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7427 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7428 ) ) ; cbx_1__1_ cbx_11__9_ ( .pReset ( { SYNOPSYS_UNCONNECTED_7429 } ) , @@ -123739,7 +128261,7 @@ cbx_1__1_ cbx_11__9_ ( .bottom_grid_pin_14_ ( cbx_1__1__118_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__118_bottom_grid_pin_15_ ) , .ccff_tail ( cbx_1__1__118_ccff_tail ) , .SC_IN_TOP ( scff_Wires[271] ) , - .SC_OUT_BOT ( scff_Wires[272] ) , .SC_IN_BOT ( p1009 ) , + .SC_OUT_BOT ( scff_Wires[272] ) , .SC_IN_BOT ( p1377 ) , .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_7430 ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[118] ) , .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[118] ) , @@ -123754,19 +128276,19 @@ cbx_1__1_ cbx_11__9_ ( .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_7434 ) , .prog_clk_1_E_in ( prog_clk_1_wires[240] ) , .prog_clk_1_N_out ( prog_clk_1_wires[241] ) , - .prog_clk_1_S_out ( prog_clk_1_wires[242] ) , .prog_clk_2_E_in ( p1777 ) , - .prog_clk_2_W_in ( p1240 ) , + .prog_clk_1_S_out ( prog_clk_1_wires[242] ) , .prog_clk_2_E_in ( p2328 ) , + .prog_clk_2_W_in ( p3307 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_7435 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_7436 ) , - .prog_clk_3_W_in ( p3398 ) , .prog_clk_3_E_in ( p1381 ) , + .prog_clk_3_W_in ( p3352 ) , .prog_clk_3_E_in ( p2065 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_7437 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_7438 ) , .clk_1_W_in ( SYNOPSYS_UNCONNECTED_7439 ) , .clk_1_E_in ( clk_1_wires[240] ) , .clk_1_N_out ( clk_1_wires[241] ) , - .clk_1_S_out ( clk_1_wires[242] ) , .clk_2_E_in ( p1777 ) , - .clk_2_W_in ( p3385 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7440 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7441 ) , .clk_3_W_in ( p2521 ) , - .clk_3_E_in ( p1626 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7442 ) , + .clk_1_S_out ( clk_1_wires[242] ) , .clk_2_E_in ( p2595 ) , + .clk_2_W_in ( p3221 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7440 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7441 ) , .clk_3_W_in ( p3230 ) , + .clk_3_E_in ( p2482 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7442 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7443 ) ) ; cbx_1__1_ cbx_11__10_ ( .pReset ( { SYNOPSYS_UNCONNECTED_7444 } ) , @@ -123792,7 +128314,7 @@ cbx_1__1_ cbx_11__10_ ( .bottom_grid_pin_14_ ( cbx_1__1__119_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__119_bottom_grid_pin_15_ ) , .ccff_tail ( cbx_1__1__119_ccff_tail ) , .SC_IN_TOP ( scff_Wires[269] ) , - .SC_OUT_BOT ( scff_Wires[270] ) , .SC_IN_BOT ( p1077 ) , + .SC_OUT_BOT ( scff_Wires[270] ) , .SC_IN_BOT ( p1987 ) , .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_7445 ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[119] ) , .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[119] ) , @@ -123804,23 +128326,23 @@ cbx_1__1_ cbx_11__10_ ( .pReset_S_out ( pResetWires[545] ) , .pReset_E_out ( pResetWires[544] ) , .prog_clk_0_N_in ( prog_clk_0_wires[435] ) , .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_7448 ) , - .prog_clk_1_W_in ( p1874 ) , .prog_clk_1_E_in ( p497 ) , + .prog_clk_1_W_in ( p1298 ) , .prog_clk_1_E_in ( p1756 ) , .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_7449 ) , .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_7450 ) , .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_7451 ) , .prog_clk_2_W_in ( prog_clk_2_wires[133] ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_7452 ) , - .prog_clk_2_E_out ( prog_clk_2_wires[132] ) , .prog_clk_3_W_in ( p1874 ) , - .prog_clk_3_E_in ( p961 ) , + .prog_clk_2_E_out ( prog_clk_2_wires[132] ) , .prog_clk_3_W_in ( p1109 ) , + .prog_clk_3_E_in ( p601 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_7453 ) , - .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_7454 ) , .clk_1_W_in ( p1837 ) , - .clk_1_E_in ( p722 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_7455 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_7454 ) , .clk_1_W_in ( p1109 ) , + .clk_1_E_in ( p1820 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_7455 ) , .clk_1_S_out ( SYNOPSYS_UNCONNECTED_7456 ) , .clk_2_E_in ( SYNOPSYS_UNCONNECTED_7457 ) , .clk_2_W_in ( clk_2_wires[133] ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7458 ) , - .clk_2_E_out ( clk_2_wires[132] ) , .clk_3_W_in ( p1874 ) , - .clk_3_E_in ( p1481 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7459 ) , + .clk_2_E_out ( clk_2_wires[132] ) , .clk_3_W_in ( p1109 ) , + .clk_3_E_in ( p1795 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7459 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7460 ) ) ; cbx_1__1_ cbx_11__11_ ( .pReset ( { SYNOPSYS_UNCONNECTED_7461 } ) , @@ -123846,7 +128368,7 @@ cbx_1__1_ cbx_11__11_ ( .bottom_grid_pin_14_ ( cbx_1__1__120_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__120_bottom_grid_pin_15_ ) , .ccff_tail ( cbx_1__1__120_ccff_tail ) , .SC_IN_TOP ( scff_Wires[267] ) , - .SC_OUT_BOT ( scff_Wires[268] ) , .SC_IN_BOT ( p1300 ) , + .SC_OUT_BOT ( scff_Wires[268] ) , .SC_IN_BOT ( p1413 ) , .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_7462 ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[120] ) , .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[120] ) , @@ -123861,19 +128383,19 @@ cbx_1__1_ cbx_11__11_ ( .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_7466 ) , .prog_clk_1_E_in ( prog_clk_1_wires[247] ) , .prog_clk_1_N_out ( prog_clk_1_wires[248] ) , - .prog_clk_1_S_out ( prog_clk_1_wires[249] ) , .prog_clk_2_E_in ( p2107 ) , - .prog_clk_2_W_in ( p718 ) , + .prog_clk_1_S_out ( prog_clk_1_wires[249] ) , .prog_clk_2_E_in ( p3145 ) , + .prog_clk_2_W_in ( p1832 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_7467 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_7468 ) , - .prog_clk_3_W_in ( p1894 ) , .prog_clk_3_E_in ( p1232 ) , + .prog_clk_3_W_in ( p1889 ) , .prog_clk_3_E_in ( p3096 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_7469 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_7470 ) , .clk_1_W_in ( SYNOPSYS_UNCONNECTED_7471 ) , .clk_1_E_in ( clk_1_wires[247] ) , .clk_1_N_out ( clk_1_wires[248] ) , - .clk_1_S_out ( clk_1_wires[249] ) , .clk_2_E_in ( p2107 ) , - .clk_2_W_in ( p2369 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7472 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7473 ) , .clk_3_W_in ( p2428 ) , - .clk_3_E_in ( p2086 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7474 ) , + .clk_1_S_out ( clk_1_wires[249] ) , .clk_2_E_in ( p2534 ) , + .clk_2_W_in ( p3546 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7472 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7473 ) , .clk_3_W_in ( p3560 ) , + .clk_3_E_in ( p2502 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7474 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7475 ) ) ; cbx_1__1_ cbx_12__1_ ( .pReset ( { SYNOPSYS_UNCONNECTED_7476 } ) , @@ -123898,7 +128420,7 @@ cbx_1__1_ cbx_12__1_ ( .bottom_grid_pin_13_ ( cbx_1__1__121_bottom_grid_pin_13_ ) , .bottom_grid_pin_14_ ( cbx_1__1__121_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__121_bottom_grid_pin_15_ ) , - .ccff_tail ( cbx_1__1__121_ccff_tail ) , .SC_IN_TOP ( p1446 ) , + .ccff_tail ( cbx_1__1__121_ccff_tail ) , .SC_IN_TOP ( p1907 ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_7477 ) , .SC_IN_BOT ( scff_Wires[294] ) , .SC_OUT_TOP ( scff_Wires[295] ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[121] ) , @@ -123914,20 +128436,20 @@ cbx_1__1_ cbx_12__1_ ( .prog_clk_1_W_in ( prog_clk_1_wires[211] ) , .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_7481 ) , .prog_clk_1_N_out ( prog_clk_1_wires[215] ) , - .prog_clk_1_S_out ( prog_clk_1_wires[216] ) , .prog_clk_2_E_in ( p2185 ) , - .prog_clk_2_W_in ( p1323 ) , + .prog_clk_1_S_out ( prog_clk_1_wires[216] ) , .prog_clk_2_E_in ( p2764 ) , + .prog_clk_2_W_in ( p3033 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_7482 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_7483 ) , - .prog_clk_3_W_in ( p2325 ) , .prog_clk_3_E_in ( p1380 ) , + .prog_clk_3_W_in ( p3160 ) , .prog_clk_3_E_in ( p2728 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_7484 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_7485 ) , .clk_1_W_in ( clk_1_wires[211] ) , .clk_1_E_in ( SYNOPSYS_UNCONNECTED_7486 ) , .clk_1_N_out ( clk_1_wires[215] ) , .clk_1_S_out ( clk_1_wires[216] ) , - .clk_2_E_in ( p2185 ) , .clk_2_W_in ( p2401 ) , + .clk_2_E_in ( p2533 ) , .clk_2_W_in ( p3313 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7487 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7488 ) , .clk_3_W_in ( p1546 ) , - .clk_3_E_in ( p2054 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7489 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7488 ) , .clk_3_W_in ( p3319 ) , + .clk_3_E_in ( p2441 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7489 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7490 ) ) ; cbx_1__1_ cbx_12__2_ ( .pReset ( { SYNOPSYS_UNCONNECTED_7491 } ) , @@ -123952,7 +128474,7 @@ cbx_1__1_ cbx_12__2_ ( .bottom_grid_pin_13_ ( cbx_1__1__122_bottom_grid_pin_13_ ) , .bottom_grid_pin_14_ ( cbx_1__1__122_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__122_bottom_grid_pin_15_ ) , - .ccff_tail ( cbx_1__1__122_ccff_tail ) , .SC_IN_TOP ( p1593 ) , + .ccff_tail ( cbx_1__1__122_ccff_tail ) , .SC_IN_TOP ( p1965 ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_7492 ) , .SC_IN_BOT ( scff_Wires[296] ) , .SC_OUT_TOP ( scff_Wires[297] ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[122] ) , @@ -123965,20 +128487,20 @@ cbx_1__1_ cbx_12__2_ ( .pReset_S_out ( pResetWires[157] ) , .pReset_E_out ( pResetWires[156] ) , .prog_clk_0_N_in ( prog_clk_0_wires[449] ) , .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_7495 ) , - .prog_clk_1_W_in ( p2188 ) , .prog_clk_1_E_in ( p1117 ) , + .prog_clk_1_W_in ( p1226 ) , .prog_clk_1_E_in ( p325 ) , .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_7496 ) , .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_7497 ) , - .prog_clk_2_E_in ( p1774 ) , .prog_clk_2_W_in ( p2085 ) , + .prog_clk_2_E_in ( p1944 ) , .prog_clk_2_W_in ( p2430 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_7498 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_7499 ) , - .prog_clk_3_W_in ( p2464 ) , .prog_clk_3_E_in ( p1582 ) , + .prog_clk_3_W_in ( p2517 ) , .prog_clk_3_E_in ( p1708 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_7500 ) , - .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_7501 ) , .clk_1_W_in ( p1093 ) , - .clk_1_E_in ( p1000 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_7502 ) , - .clk_1_S_out ( SYNOPSYS_UNCONNECTED_7503 ) , .clk_2_E_in ( p1774 ) , - .clk_2_W_in ( p3037 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7504 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7505 ) , .clk_3_W_in ( p3111 ) , - .clk_3_E_in ( p1707 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7506 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_7501 ) , .clk_1_W_in ( p1891 ) , + .clk_1_E_in ( p586 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_7502 ) , + .clk_1_S_out ( SYNOPSYS_UNCONNECTED_7503 ) , .clk_2_E_in ( p2741 ) , + .clk_2_W_in ( p3070 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7504 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7505 ) , .clk_3_W_in ( p3115 ) , + .clk_3_E_in ( p2684 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7506 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7507 ) ) ; cbx_1__1_ cbx_12__3_ ( .pReset ( { SYNOPSYS_UNCONNECTED_7508 } ) , @@ -124003,7 +128525,7 @@ cbx_1__1_ cbx_12__3_ ( .bottom_grid_pin_13_ ( cbx_1__1__123_bottom_grid_pin_13_ ) , .bottom_grid_pin_14_ ( cbx_1__1__123_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__123_bottom_grid_pin_15_ ) , - .ccff_tail ( cbx_1__1__123_ccff_tail ) , .SC_IN_TOP ( p1515 ) , + .ccff_tail ( cbx_1__1__123_ccff_tail ) , .SC_IN_TOP ( p1527 ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_7509 ) , .SC_IN_BOT ( scff_Wires[298] ) , .SC_OUT_TOP ( scff_Wires[299] ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[123] ) , @@ -124019,20 +128541,20 @@ cbx_1__1_ cbx_12__3_ ( .prog_clk_1_W_in ( prog_clk_1_wires[218] ) , .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_7513 ) , .prog_clk_1_N_out ( prog_clk_1_wires[222] ) , - .prog_clk_1_S_out ( prog_clk_1_wires[223] ) , .prog_clk_2_E_in ( p1458 ) , - .prog_clk_2_W_in ( p970 ) , + .prog_clk_1_S_out ( prog_clk_1_wires[223] ) , .prog_clk_2_E_in ( p2969 ) , + .prog_clk_2_W_in ( p3481 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_7514 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_7515 ) , - .prog_clk_3_W_in ( p3450 ) , .prog_clk_3_E_in ( p935 ) , + .prog_clk_3_W_in ( p3500 ) , .prog_clk_3_E_in ( p2903 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_7516 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_7517 ) , .clk_1_W_in ( clk_1_wires[218] ) , .clk_1_E_in ( SYNOPSYS_UNCONNECTED_7518 ) , .clk_1_N_out ( clk_1_wires[222] ) , .clk_1_S_out ( clk_1_wires[223] ) , - .clk_2_E_in ( p1458 ) , .clk_2_W_in ( p3442 ) , + .clk_2_E_in ( p1884 ) , .clk_2_W_in ( p2494 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7519 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7520 ) , .clk_3_W_in ( p2793 ) , - .clk_3_E_in ( p604 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7521 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7520 ) , .clk_3_W_in ( p2592 ) , + .clk_3_E_in ( p1839 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7521 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7522 ) ) ; cbx_1__1_ cbx_12__4_ ( .pReset ( { SYNOPSYS_UNCONNECTED_7523 } ) , @@ -124057,7 +128579,7 @@ cbx_1__1_ cbx_12__4_ ( .bottom_grid_pin_13_ ( cbx_1__1__124_bottom_grid_pin_13_ ) , .bottom_grid_pin_14_ ( cbx_1__1__124_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__124_bottom_grid_pin_15_ ) , - .ccff_tail ( cbx_1__1__124_ccff_tail ) , .SC_IN_TOP ( p1862 ) , + .ccff_tail ( cbx_1__1__124_ccff_tail ) , .SC_IN_TOP ( p1939 ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_7524 ) , .SC_IN_BOT ( scff_Wires[300] ) , .SC_OUT_TOP ( scff_Wires[301] ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[124] ) , @@ -124070,20 +128592,20 @@ cbx_1__1_ cbx_12__4_ ( .pReset_S_out ( pResetWires[255] ) , .pReset_E_out ( pResetWires[254] ) , .prog_clk_0_N_in ( prog_clk_0_wires[455] ) , .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_7527 ) , - .prog_clk_1_W_in ( p2179 ) , .prog_clk_1_E_in ( p919 ) , + .prog_clk_1_W_in ( p1382 ) , .prog_clk_1_E_in ( p482 ) , .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_7528 ) , .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_7529 ) , - .prog_clk_2_E_in ( p1877 ) , .prog_clk_2_W_in ( p2101 ) , + .prog_clk_2_E_in ( p3018 ) , .prog_clk_2_W_in ( p3089 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_7530 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_7531 ) , - .prog_clk_3_W_in ( p3239 ) , .prog_clk_3_E_in ( p1757 ) , + .prog_clk_3_W_in ( p3125 ) , .prog_clk_3_E_in ( p2927 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_7532 ) , - .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_7533 ) , .clk_1_W_in ( p1542 ) , - .clk_1_E_in ( p517 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_7534 ) , - .clk_1_S_out ( SYNOPSYS_UNCONNECTED_7535 ) , .clk_2_E_in ( p1877 ) , - .clk_2_W_in ( p3210 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7536 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7537 ) , .clk_3_W_in ( p2855 ) , - .clk_3_E_in ( p1664 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7538 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_7533 ) , .clk_1_W_in ( p2349 ) , + .clk_1_E_in ( p547 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_7534 ) , + .clk_1_S_out ( SYNOPSYS_UNCONNECTED_7535 ) , .clk_2_E_in ( p2844 ) , + .clk_2_W_in ( p2889 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7536 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7537 ) , .clk_3_W_in ( p2955 ) , + .clk_3_E_in ( p2710 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7538 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7539 ) ) ; cbx_1__1_ cbx_12__5_ ( .pReset ( { SYNOPSYS_UNCONNECTED_7540 } ) , @@ -124108,7 +128630,7 @@ cbx_1__1_ cbx_12__5_ ( .bottom_grid_pin_13_ ( cbx_1__1__125_bottom_grid_pin_13_ ) , .bottom_grid_pin_14_ ( cbx_1__1__125_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__125_bottom_grid_pin_15_ ) , - .ccff_tail ( cbx_1__1__125_ccff_tail ) , .SC_IN_TOP ( p2132 ) , + .ccff_tail ( cbx_1__1__125_ccff_tail ) , .SC_IN_TOP ( p1904 ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_7541 ) , .SC_IN_BOT ( scff_Wires[302] ) , .SC_OUT_TOP ( scff_Wires[303] ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[125] ) , @@ -124124,20 +128646,20 @@ cbx_1__1_ cbx_12__5_ ( .prog_clk_1_W_in ( prog_clk_1_wires[225] ) , .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_7545 ) , .prog_clk_1_N_out ( prog_clk_1_wires[229] ) , - .prog_clk_1_S_out ( prog_clk_1_wires[230] ) , .prog_clk_2_E_in ( p2651 ) , - .prog_clk_2_W_in ( p548 ) , + .prog_clk_1_S_out ( prog_clk_1_wires[230] ) , .prog_clk_2_E_in ( p3416 ) , + .prog_clk_2_W_in ( p3567 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_7546 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_7547 ) , - .prog_clk_3_W_in ( p3314 ) , .prog_clk_3_E_in ( p2040 ) , + .prog_clk_3_W_in ( p3576 ) , .prog_clk_3_E_in ( p3388 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_7548 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_7549 ) , .clk_1_W_in ( clk_1_wires[225] ) , .clk_1_E_in ( SYNOPSYS_UNCONNECTED_7550 ) , .clk_1_N_out ( clk_1_wires[229] ) , .clk_1_S_out ( clk_1_wires[230] ) , - .clk_2_E_in ( p2651 ) , .clk_2_W_in ( p3303 ) , + .clk_2_E_in ( p2800 ) , .clk_2_W_in ( p1823 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7551 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7552 ) , .clk_3_W_in ( p2812 ) , - .clk_3_E_in ( p2576 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7553 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7552 ) , .clk_3_W_in ( p2016 ) , + .clk_3_E_in ( p2730 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7553 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7554 ) ) ; cbx_1__1_ cbx_12__6_ ( .pReset ( { SYNOPSYS_UNCONNECTED_7555 } ) , @@ -124162,7 +128684,7 @@ cbx_1__1_ cbx_12__6_ ( .bottom_grid_pin_13_ ( cbx_1__1__126_bottom_grid_pin_13_ ) , .bottom_grid_pin_14_ ( cbx_1__1__126_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__126_bottom_grid_pin_15_ ) , - .ccff_tail ( cbx_1__1__126_ccff_tail ) , .SC_IN_TOP ( p2124 ) , + .ccff_tail ( cbx_1__1__126_ccff_tail ) , .SC_IN_TOP ( p1632 ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_7556 ) , .SC_IN_BOT ( scff_Wires[304] ) , .SC_OUT_TOP ( scff_Wires[305] ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[126] ) , @@ -124175,20 +128697,20 @@ cbx_1__1_ cbx_12__6_ ( .pReset_S_out ( pResetWires[353] ) , .pReset_E_out ( pResetWires[352] ) , .prog_clk_0_N_in ( prog_clk_0_wires[461] ) , .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_7559 ) , - .prog_clk_1_W_in ( p2411 ) , .prog_clk_1_E_in ( p9 ) , + .prog_clk_1_W_in ( p1327 ) , .prog_clk_1_E_in ( p861 ) , .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_7560 ) , .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_7561 ) , - .prog_clk_2_E_in ( p1692 ) , .prog_clk_2_W_in ( p2370 ) , + .prog_clk_2_E_in ( p2345 ) , .prog_clk_2_W_in ( p3082 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_7562 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_7563 ) , - .prog_clk_3_W_in ( p3405 ) , .prog_clk_3_E_in ( p2064 ) , + .prog_clk_3_W_in ( p3124 ) , .prog_clk_3_E_in ( p2180 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_7564 ) , - .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_7565 ) , .clk_1_W_in ( p1561 ) , - .clk_1_E_in ( p418 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_7566 ) , - .clk_1_S_out ( SYNOPSYS_UNCONNECTED_7567 ) , .clk_2_E_in ( p1692 ) , - .clk_2_W_in ( p3383 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7568 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7569 ) , .clk_3_W_in ( p3067 ) , - .clk_3_E_in ( p1745 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7570 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_7565 ) , .clk_1_W_in ( p1209 ) , + .clk_1_E_in ( p980 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_7566 ) , + .clk_1_S_out ( SYNOPSYS_UNCONNECTED_7567 ) , .clk_2_E_in ( p2563 ) , + .clk_2_W_in ( p2918 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7568 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7569 ) , .clk_3_W_in ( p2995 ) , + .clk_3_E_in ( p2463 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7570 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7571 ) ) ; cbx_1__1_ cbx_12__7_ ( .pReset ( { SYNOPSYS_UNCONNECTED_7572 } ) , @@ -124213,7 +128735,7 @@ cbx_1__1_ cbx_12__7_ ( .bottom_grid_pin_13_ ( cbx_1__1__127_bottom_grid_pin_13_ ) , .bottom_grid_pin_14_ ( cbx_1__1__127_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__127_bottom_grid_pin_15_ ) , - .ccff_tail ( cbx_1__1__127_ccff_tail ) , .SC_IN_TOP ( p2255 ) , + .ccff_tail ( cbx_1__1__127_ccff_tail ) , .SC_IN_TOP ( p2277 ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_7573 ) , .SC_IN_BOT ( scff_Wires[306] ) , .SC_OUT_TOP ( scff_Wires[307] ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[127] ) , @@ -124229,20 +128751,20 @@ cbx_1__1_ cbx_12__7_ ( .prog_clk_1_W_in ( prog_clk_1_wires[232] ) , .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_7577 ) , .prog_clk_1_N_out ( prog_clk_1_wires[236] ) , - .prog_clk_1_S_out ( prog_clk_1_wires[237] ) , .prog_clk_2_E_in ( p2798 ) , - .prog_clk_2_W_in ( p791 ) , + .prog_clk_1_S_out ( prog_clk_1_wires[237] ) , .prog_clk_2_E_in ( p2826 ) , + .prog_clk_2_W_in ( p2440 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_7578 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_7579 ) , - .prog_clk_3_W_in ( p2968 ) , .prog_clk_3_E_in ( p2006 ) , + .prog_clk_3_W_in ( p2497 ) , .prog_clk_3_E_in ( p2674 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_7580 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_7581 ) , .clk_1_W_in ( clk_1_wires[232] ) , .clk_1_E_in ( SYNOPSYS_UNCONNECTED_7582 ) , .clk_1_N_out ( clk_1_wires[236] ) , .clk_1_S_out ( clk_1_wires[237] ) , - .clk_2_E_in ( p2798 ) , .clk_2_W_in ( p2868 ) , + .clk_2_E_in ( p2366 ) , .clk_2_W_in ( p3311 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7583 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7584 ) , .clk_3_W_in ( p2687 ) , - .clk_3_E_in ( p2766 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7585 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7584 ) , .clk_3_W_in ( p3356 ) , + .clk_3_E_in ( p2192 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7585 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7586 ) ) ; cbx_1__1_ cbx_12__8_ ( .pReset ( { SYNOPSYS_UNCONNECTED_7587 } ) , @@ -124267,7 +128789,7 @@ cbx_1__1_ cbx_12__8_ ( .bottom_grid_pin_13_ ( cbx_1__1__128_bottom_grid_pin_13_ ) , .bottom_grid_pin_14_ ( cbx_1__1__128_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__128_bottom_grid_pin_15_ ) , - .ccff_tail ( cbx_1__1__128_ccff_tail ) , .SC_IN_TOP ( p2688 ) , + .ccff_tail ( cbx_1__1__128_ccff_tail ) , .SC_IN_TOP ( p1905 ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_7588 ) , .SC_IN_BOT ( scff_Wires[308] ) , .SC_OUT_TOP ( scff_Wires[309] ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[128] ) , @@ -124280,20 +128802,20 @@ cbx_1__1_ cbx_12__8_ ( .pReset_S_out ( pResetWires[451] ) , .pReset_E_out ( pResetWires[450] ) , .prog_clk_0_N_in ( prog_clk_0_wires[467] ) , .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_7591 ) , - .prog_clk_1_W_in ( p2508 ) , .prog_clk_1_E_in ( p771 ) , + .prog_clk_1_W_in ( p1165 ) , .prog_clk_1_E_in ( p960 ) , .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_7592 ) , .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_7593 ) , - .prog_clk_2_E_in ( p2432 ) , .prog_clk_2_W_in ( p2320 ) , + .prog_clk_2_E_in ( p2034 ) , .prog_clk_2_W_in ( p1729 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_7594 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_7595 ) , - .prog_clk_3_W_in ( p2713 ) , .prog_clk_3_E_in ( p2548 ) , + .prog_clk_3_W_in ( p1960 ) , .prog_clk_3_E_in ( p1707 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_7596 ) , - .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_7597 ) , .clk_1_W_in ( p1363 ) , - .clk_1_E_in ( p272 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_7598 ) , - .clk_1_S_out ( SYNOPSYS_UNCONNECTED_7599 ) , .clk_2_E_in ( p2432 ) , - .clk_2_W_in ( p2608 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7600 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7601 ) , .clk_3_W_in ( p2591 ) , - .clk_3_E_in ( p2353 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7602 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_7597 ) , .clk_1_W_in ( p1427 ) , + .clk_1_E_in ( p381 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_7598 ) , + .clk_1_S_out ( SYNOPSYS_UNCONNECTED_7599 ) , .clk_2_E_in ( p1647 ) , + .clk_2_W_in ( p3432 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7600 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7601 ) , .clk_3_W_in ( p3452 ) , + .clk_3_E_in ( p1115 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7602 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7603 ) ) ; cbx_1__1_ cbx_12__9_ ( .pReset ( { SYNOPSYS_UNCONNECTED_7604 } ) , @@ -124318,7 +128840,7 @@ cbx_1__1_ cbx_12__9_ ( .bottom_grid_pin_13_ ( cbx_1__1__129_bottom_grid_pin_13_ ) , .bottom_grid_pin_14_ ( cbx_1__1__129_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__129_bottom_grid_pin_15_ ) , - .ccff_tail ( cbx_1__1__129_ccff_tail ) , .SC_IN_TOP ( p1406 ) , + .ccff_tail ( cbx_1__1__129_ccff_tail ) , .SC_IN_TOP ( p1348 ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_7605 ) , .SC_IN_BOT ( scff_Wires[310] ) , .SC_OUT_TOP ( scff_Wires[311] ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[129] ) , @@ -124334,20 +128856,20 @@ cbx_1__1_ cbx_12__9_ ( .prog_clk_1_W_in ( prog_clk_1_wires[239] ) , .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_7609 ) , .prog_clk_1_N_out ( prog_clk_1_wires[243] ) , - .prog_clk_1_S_out ( prog_clk_1_wires[244] ) , .prog_clk_2_E_in ( p2190 ) , - .prog_clk_2_W_in ( p679 ) , + .prog_clk_1_S_out ( prog_clk_1_wires[244] ) , .prog_clk_2_E_in ( p1728 ) , + .prog_clk_2_W_in ( p3216 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_7610 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_7611 ) , - .prog_clk_3_W_in ( p2861 ) , .prog_clk_3_E_in ( p1264 ) , + .prog_clk_3_W_in ( p3276 ) , .prog_clk_3_E_in ( p1869 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_7612 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_7613 ) , .clk_1_W_in ( clk_1_wires[239] ) , .clk_1_E_in ( SYNOPSYS_UNCONNECTED_7614 ) , .clk_1_N_out ( clk_1_wires[243] ) , .clk_1_S_out ( clk_1_wires[244] ) , - .clk_2_E_in ( p2190 ) , .clk_2_W_in ( p2904 ) , + .clk_2_E_in ( p2547 ) , .clk_2_W_in ( p3068 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7615 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7616 ) , .clk_3_W_in ( p2923 ) , - .clk_3_E_in ( p2029 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7617 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7616 ) , .clk_3_W_in ( p3132 ) , + .clk_3_E_in ( p2408 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7617 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7618 ) ) ; cbx_1__1_ cbx_12__10_ ( .pReset ( { SYNOPSYS_UNCONNECTED_7619 } ) , @@ -124372,7 +128894,7 @@ cbx_1__1_ cbx_12__10_ ( .bottom_grid_pin_13_ ( cbx_1__1__130_bottom_grid_pin_13_ ) , .bottom_grid_pin_14_ ( cbx_1__1__130_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__130_bottom_grid_pin_15_ ) , - .ccff_tail ( cbx_1__1__130_ccff_tail ) , .SC_IN_TOP ( p2252 ) , + .ccff_tail ( cbx_1__1__130_ccff_tail ) , .SC_IN_TOP ( p965 ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_7620 ) , .SC_IN_BOT ( scff_Wires[312] ) , .SC_OUT_TOP ( scff_Wires[313] ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[130] ) , @@ -124385,20 +128907,20 @@ cbx_1__1_ cbx_12__10_ ( .pReset_S_out ( pResetWires[549] ) , .pReset_E_out ( pResetWires[548] ) , .prog_clk_0_N_in ( prog_clk_0_wires[473] ) , .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_7623 ) , - .prog_clk_1_W_in ( p2366 ) , .prog_clk_1_E_in ( p405 ) , + .prog_clk_1_W_in ( p1356 ) , .prog_clk_1_E_in ( p941 ) , .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_7624 ) , .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_7625 ) , - .prog_clk_2_E_in ( p2600 ) , .prog_clk_2_W_in ( p2391 ) , + .prog_clk_2_E_in ( p2980 ) , .prog_clk_2_W_in ( p3223 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_7626 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_7627 ) , - .prog_clk_3_W_in ( p3319 ) , .prog_clk_3_E_in ( p2119 ) , + .prog_clk_3_W_in ( p3227 ) , .prog_clk_3_E_in ( p2904 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_7628 ) , - .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_7629 ) , .clk_1_W_in ( p1401 ) , - .clk_1_E_in ( p628 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_7630 ) , - .clk_1_S_out ( SYNOPSYS_UNCONNECTED_7631 ) , .clk_2_E_in ( p2600 ) , - .clk_2_W_in ( p3279 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7632 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7633 ) , .clk_3_W_in ( p3246 ) , - .clk_3_E_in ( p2562 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7634 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_7629 ) , .clk_1_W_in ( p1395 ) , + .clk_1_E_in ( p1236 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_7630 ) , + .clk_1_S_out ( SYNOPSYS_UNCONNECTED_7631 ) , .clk_2_E_in ( p2347 ) , + .clk_2_W_in ( p3387 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7632 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7633 ) , .clk_3_W_in ( p3413 ) , + .clk_3_E_in ( p2103 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7634 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7635 ) ) ; cbx_1__1_ cbx_12__11_ ( .pReset ( { SYNOPSYS_UNCONNECTED_7636 } ) , @@ -124423,7 +128945,7 @@ cbx_1__1_ cbx_12__11_ ( .bottom_grid_pin_13_ ( cbx_1__1__131_bottom_grid_pin_13_ ) , .bottom_grid_pin_14_ ( cbx_1__1__131_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__131_bottom_grid_pin_15_ ) , - .ccff_tail ( cbx_1__1__131_ccff_tail ) , .SC_IN_TOP ( p2114 ) , + .ccff_tail ( cbx_1__1__131_ccff_tail ) , .SC_IN_TOP ( p2231 ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_7637 ) , .SC_IN_BOT ( scff_Wires[314] ) , .SC_OUT_TOP ( scff_Wires[315] ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[131] ) , @@ -124439,20 +128961,20 @@ cbx_1__1_ cbx_12__11_ ( .prog_clk_1_W_in ( prog_clk_1_wires[246] ) , .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_7641 ) , .prog_clk_1_N_out ( prog_clk_1_wires[250] ) , - .prog_clk_1_S_out ( prog_clk_1_wires[251] ) , .prog_clk_2_E_in ( p2480 ) , - .prog_clk_2_W_in ( p1256 ) , + .prog_clk_1_S_out ( prog_clk_1_wires[251] ) , .prog_clk_2_E_in ( p2604 ) , + .prog_clk_2_W_in ( p2926 ) , .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_7642 ) , .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_7643 ) , - .prog_clk_3_W_in ( p2509 ) , .prog_clk_3_E_in ( p1974 ) , + .prog_clk_3_W_in ( p3012 ) , .prog_clk_3_E_in ( p2445 ) , .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_7644 ) , .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_7645 ) , .clk_1_W_in ( clk_1_wires[246] ) , .clk_1_E_in ( SYNOPSYS_UNCONNECTED_7646 ) , .clk_1_N_out ( clk_1_wires[250] ) , .clk_1_S_out ( clk_1_wires[251] ) , - .clk_2_E_in ( p2480 ) , .clk_2_W_in ( p2720 ) , + .clk_2_E_in ( p2847 ) , .clk_2_W_in ( p3199 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7647 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7648 ) , .clk_3_W_in ( p2823 ) , - .clk_3_E_in ( p2274 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7649 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7648 ) , .clk_3_W_in ( p3266 ) , + .clk_3_E_in ( p2693 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7649 ) , .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7650 ) ) ; cbx_1__2_ cbx_1__12_ ( .pReset ( { SYNOPSYS_UNCONNECTED_7651 } ) , @@ -124486,7 +129008,7 @@ cbx_1__2_ cbx_1__12_ ( .bottom_width_0_height_0__pin_1_upper ( grid_io_top_0_bottom_width_0_height_0__pin_1_upper ) , .bottom_width_0_height_0__pin_1_lower ( grid_io_top_0_bottom_width_0_height_0__pin_1_lower ) , .SC_IN_TOP ( scff_Wires[0] ) , .SC_OUT_BOT ( scff_Wires[1] ) , - .SC_IN_BOT ( p1216 ) , .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_7652 ) , + .SC_IN_BOT ( p1338 ) , .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_7652 ) , .pReset_E_in ( pResetWires[601] ) , .pReset_W_in ( SYNOPSYS_UNCONNECTED_7653 ) , .pReset_W_out ( pResetWires[600] ) , .pReset_S_out ( pResetWires[602] ) , @@ -124524,7 +129046,7 @@ cbx_1__2_ cbx_2__12_ ( .bottom_width_0_height_0__pin_0_ ( cbx_1__12__1_top_grid_pin_0_ ) , .bottom_width_0_height_0__pin_1_upper ( grid_io_top_1_bottom_width_0_height_0__pin_1_upper ) , .bottom_width_0_height_0__pin_1_lower ( grid_io_top_1_bottom_width_0_height_0__pin_1_lower ) , - .SC_IN_TOP ( p1789 ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_7656 ) , + .SC_IN_TOP ( p1639 ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_7656 ) , .SC_IN_BOT ( scff_Wires[51] ) , .SC_OUT_TOP ( scff_Wires[52] ) , .pReset_E_in ( pResetWires[605] ) , .pReset_W_in ( SYNOPSYS_UNCONNECTED_7657 ) , @@ -124564,7 +129086,7 @@ cbx_1__2_ cbx_3__12_ ( .bottom_width_0_height_0__pin_1_upper ( grid_io_top_2_bottom_width_0_height_0__pin_1_upper ) , .bottom_width_0_height_0__pin_1_lower ( grid_io_top_2_bottom_width_0_height_0__pin_1_lower ) , .SC_IN_TOP ( scff_Wires[53] ) , .SC_OUT_BOT ( scff_Wires[54] ) , - .SC_IN_BOT ( p1272 ) , .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_7661 ) , + .SC_IN_BOT ( p1606 ) , .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_7661 ) , .pReset_E_in ( pResetWires[608] ) , .pReset_W_in ( SYNOPSYS_UNCONNECTED_7662 ) , .pReset_W_out ( pResetWires[607] ) , .pReset_S_out ( pResetWires[609] ) , @@ -124602,7 +129124,7 @@ cbx_1__2_ cbx_4__12_ ( .bottom_width_0_height_0__pin_0_ ( cbx_1__12__3_top_grid_pin_0_ ) , .bottom_width_0_height_0__pin_1_upper ( grid_io_top_3_bottom_width_0_height_0__pin_1_upper ) , .bottom_width_0_height_0__pin_1_lower ( grid_io_top_3_bottom_width_0_height_0__pin_1_lower ) , - .SC_IN_TOP ( p1618 ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_7666 ) , + .SC_IN_TOP ( p1397 ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_7666 ) , .SC_IN_BOT ( scff_Wires[104] ) , .SC_OUT_TOP ( scff_Wires[105] ) , .pReset_E_in ( pResetWires[611] ) , .pReset_W_in ( SYNOPSYS_UNCONNECTED_7667 ) , @@ -124642,7 +129164,7 @@ cbx_1__2_ cbx_5__12_ ( .bottom_width_0_height_0__pin_1_upper ( grid_io_top_4_bottom_width_0_height_0__pin_1_upper ) , .bottom_width_0_height_0__pin_1_lower ( grid_io_top_4_bottom_width_0_height_0__pin_1_lower ) , .SC_IN_TOP ( scff_Wires[106] ) , .SC_OUT_BOT ( scff_Wires[107] ) , - .SC_IN_BOT ( p1199 ) , .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_7671 ) , + .SC_IN_BOT ( p1412 ) , .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_7671 ) , .pReset_E_in ( pResetWires[614] ) , .pReset_W_in ( SYNOPSYS_UNCONNECTED_7672 ) , .pReset_W_out ( pResetWires[613] ) , .pReset_S_out ( pResetWires[615] ) , @@ -124680,7 +129202,7 @@ cbx_1__2_ cbx_6__12_ ( .bottom_width_0_height_0__pin_0_ ( cbx_1__12__5_top_grid_pin_0_ ) , .bottom_width_0_height_0__pin_1_upper ( grid_io_top_5_bottom_width_0_height_0__pin_1_upper ) , .bottom_width_0_height_0__pin_1_lower ( grid_io_top_5_bottom_width_0_height_0__pin_1_lower ) , - .SC_IN_TOP ( p1560 ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_7676 ) , + .SC_IN_TOP ( p1252 ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_7676 ) , .SC_IN_BOT ( scff_Wires[157] ) , .SC_OUT_TOP ( scff_Wires[158] ) , .pReset_E_in ( pResetWires[617] ) , .pReset_W_in ( SYNOPSYS_UNCONNECTED_7677 ) , @@ -124720,7 +129242,7 @@ cbx_1__2_ cbx_7__12_ ( .bottom_width_0_height_0__pin_1_upper ( grid_io_top_6_bottom_width_0_height_0__pin_1_upper ) , .bottom_width_0_height_0__pin_1_lower ( grid_io_top_6_bottom_width_0_height_0__pin_1_lower ) , .SC_IN_TOP ( scff_Wires[159] ) , .SC_OUT_BOT ( scff_Wires[160] ) , - .SC_IN_BOT ( p1307 ) , .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_7681 ) , + .SC_IN_BOT ( p1461 ) , .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_7681 ) , .pReset_E_in ( SYNOPSYS_UNCONNECTED_7682 ) , .pReset_W_in ( pResetWires[619] ) , .pReset_W_out ( SYNOPSYS_UNCONNECTED_7683 ) , @@ -124758,7 +129280,7 @@ cbx_1__2_ cbx_8__12_ ( .bottom_width_0_height_0__pin_0_ ( cbx_1__12__7_top_grid_pin_0_ ) , .bottom_width_0_height_0__pin_1_upper ( grid_io_top_7_bottom_width_0_height_0__pin_1_upper ) , .bottom_width_0_height_0__pin_1_lower ( grid_io_top_7_bottom_width_0_height_0__pin_1_lower ) , - .SC_IN_TOP ( p1438 ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_7686 ) , + .SC_IN_TOP ( p1565 ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_7686 ) , .SC_IN_BOT ( scff_Wires[210] ) , .SC_OUT_TOP ( scff_Wires[211] ) , .pReset_E_in ( SYNOPSYS_UNCONNECTED_7687 ) , .pReset_W_in ( pResetWires[622] ) , @@ -124798,7 +129320,7 @@ cbx_1__2_ cbx_9__12_ ( .bottom_width_0_height_0__pin_1_upper ( grid_io_top_8_bottom_width_0_height_0__pin_1_upper ) , .bottom_width_0_height_0__pin_1_lower ( grid_io_top_8_bottom_width_0_height_0__pin_1_lower ) , .SC_IN_TOP ( scff_Wires[212] ) , .SC_OUT_BOT ( scff_Wires[213] ) , - .SC_IN_BOT ( p1396 ) , .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_7691 ) , + .SC_IN_BOT ( p1360 ) , .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_7691 ) , .pReset_E_in ( SYNOPSYS_UNCONNECTED_7692 ) , .pReset_W_in ( pResetWires[625] ) , .pReset_W_out ( SYNOPSYS_UNCONNECTED_7693 ) , @@ -124836,7 +129358,7 @@ cbx_1__2_ cbx_10__12_ ( .bottom_width_0_height_0__pin_0_ ( cbx_1__12__9_top_grid_pin_0_ ) , .bottom_width_0_height_0__pin_1_upper ( grid_io_top_9_bottom_width_0_height_0__pin_1_upper ) , .bottom_width_0_height_0__pin_1_lower ( grid_io_top_9_bottom_width_0_height_0__pin_1_lower ) , - .SC_IN_TOP ( p1434 ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_7696 ) , + .SC_IN_TOP ( p1642 ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_7696 ) , .SC_IN_BOT ( scff_Wires[263] ) , .SC_OUT_TOP ( scff_Wires[264] ) , .pReset_E_in ( SYNOPSYS_UNCONNECTED_7697 ) , .pReset_W_in ( pResetWires[628] ) , @@ -124876,7 +129398,7 @@ cbx_1__2_ cbx_11__12_ ( .bottom_width_0_height_0__pin_1_upper ( grid_io_top_10_bottom_width_0_height_0__pin_1_upper ) , .bottom_width_0_height_0__pin_1_lower ( grid_io_top_10_bottom_width_0_height_0__pin_1_lower ) , .SC_IN_TOP ( scff_Wires[265] ) , .SC_OUT_BOT ( scff_Wires[266] ) , - .SC_IN_BOT ( p1310 ) , .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_7701 ) , + .SC_IN_BOT ( p1480 ) , .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_7701 ) , .pReset_E_in ( SYNOPSYS_UNCONNECTED_7702 ) , .pReset_W_in ( pResetWires[631] ) , .pReset_W_out ( SYNOPSYS_UNCONNECTED_7703 ) , @@ -124914,7 +129436,7 @@ cbx_1__2_ cbx_12__12_ ( .bottom_width_0_height_0__pin_0_ ( cbx_1__12__11_top_grid_pin_0_ ) , .bottom_width_0_height_0__pin_1_upper ( grid_io_top_11_bottom_width_0_height_0__pin_1_upper ) , .bottom_width_0_height_0__pin_1_lower ( grid_io_top_11_bottom_width_0_height_0__pin_1_lower ) , - .SC_IN_TOP ( p1784 ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_7706 ) , + .SC_IN_TOP ( p1354 ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_7706 ) , .SC_IN_BOT ( scff_Wires[316] ) , .SC_OUT_TOP ( scff_Wires[317] ) , .pReset_E_in ( SYNOPSYS_UNCONNECTED_7707 ) , .pReset_W_in ( pResetWires[634] ) , @@ -125167,15 +129689,15 @@ cby_1__1_ cby_1__1_ ( .prog_clk_0_W_in ( prog_clk_0_wires[1] ) , .prog_clk_0_S_out ( prog_clk_0_wires[2] ) , .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_7732 ) , - .prog_clk_2_N_in ( p1955 ) , .prog_clk_2_S_in ( p775 ) , + .prog_clk_2_N_in ( p2253 ) , .prog_clk_2_S_in ( p663 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_7733 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_7734 ) , - .prog_clk_3_S_in ( p2955 ) , .prog_clk_3_N_in ( p1656 ) , + .prog_clk_3_S_in ( p2279 ) , .prog_clk_3_N_in ( p2062 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_7735 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_7736 ) , .clk_2_N_in ( p2139 ) , - .clk_2_S_in ( p3344 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_7737 ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_7738 ) , .clk_3_S_in ( p3363 ) , - .clk_3_N_in ( p2013 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_7739 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_7736 ) , .clk_2_N_in ( p1330 ) , + .clk_2_S_in ( p3056 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_7737 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_7738 ) , .clk_3_S_in ( p3137 ) , + .clk_3_N_in ( p1110 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_7739 ) , .clk_3_S_out ( SYNOPSYS_UNCONNECTED_7740 ) ) ; cby_1__1_ cby_1__2_ ( .pReset ( { SYNOPSYS_UNCONNECTED_7741 } ) , @@ -125222,14 +129744,14 @@ cby_1__1_ cby_1__2_ ( .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_7752 ) , .prog_clk_2_S_out ( prog_clk_2_wires[4] ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_7753 ) , - .prog_clk_3_S_in ( p1866 ) , .prog_clk_3_N_in ( p835 ) , + .prog_clk_3_S_in ( p2035 ) , .prog_clk_3_N_in ( p389 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_7754 ) , .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_7755 ) , .clk_2_N_in ( clk_2_wires[3] ) , .clk_2_S_in ( SYNOPSYS_UNCONNECTED_7756 ) , .clk_2_S_out ( clk_2_wires[4] ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_7757 ) , .clk_3_S_in ( p1866 ) , - .clk_3_N_in ( p89 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_7758 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_7757 ) , .clk_3_S_in ( p2035 ) , + .clk_3_N_in ( p883 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_7758 ) , .clk_3_S_out ( SYNOPSYS_UNCONNECTED_7759 ) ) ; cby_1__1_ cby_1__3_ ( .pReset ( { SYNOPSYS_UNCONNECTED_7760 } ) , @@ -125272,15 +129794,15 @@ cby_1__1_ cby_1__3_ ( .prog_clk_0_W_in ( prog_clk_0_wires[12] ) , .prog_clk_0_S_out ( prog_clk_0_wires[13] ) , .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_7770 ) , - .prog_clk_2_N_in ( p3171 ) , .prog_clk_2_S_in ( p934 ) , + .prog_clk_2_N_in ( p2275 ) , .prog_clk_2_S_in ( p679 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_7771 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_7772 ) , - .prog_clk_3_S_in ( p2665 ) , .prog_clk_3_N_in ( p3152 ) , + .prog_clk_3_S_in ( p2958 ) , .prog_clk_3_N_in ( p2155 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_7773 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_7774 ) , .clk_2_N_in ( p2960 ) , - .clk_2_S_in ( p2732 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_7775 ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_7776 ) , .clk_3_S_in ( p2814 ) , - .clk_3_N_in ( p2879 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_7777 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_7774 ) , .clk_2_N_in ( p3001 ) , + .clk_2_S_in ( p2892 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_7775 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_7776 ) , .clk_3_S_in ( p2956 ) , + .clk_3_N_in ( p2905 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_7777 ) , .clk_3_S_out ( SYNOPSYS_UNCONNECTED_7778 ) ) ; cby_1__1_ cby_1__4_ ( .pReset ( { SYNOPSYS_UNCONNECTED_7779 } ) , @@ -125327,14 +129849,14 @@ cby_1__1_ cby_1__4_ ( .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_7790 ) , .prog_clk_2_S_out ( prog_clk_2_wires[11] ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_7791 ) , - .prog_clk_3_S_in ( p2097 ) , .prog_clk_3_N_in ( p220 ) , + .prog_clk_3_S_in ( p1640 ) , .prog_clk_3_N_in ( p423 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_7792 ) , .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_7793 ) , .clk_2_N_in ( clk_2_wires[10] ) , .clk_2_S_in ( SYNOPSYS_UNCONNECTED_7794 ) , .clk_2_S_out ( clk_2_wires[11] ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_7795 ) , .clk_3_S_in ( p2097 ) , - .clk_3_N_in ( p490 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_7796 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_7795 ) , .clk_3_S_in ( p1640 ) , + .clk_3_N_in ( p950 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_7796 ) , .clk_3_S_out ( SYNOPSYS_UNCONNECTED_7797 ) ) ; cby_1__1_ cby_1__5_ ( .pReset ( { SYNOPSYS_UNCONNECTED_7798 } ) , @@ -125380,15 +129902,15 @@ cby_1__1_ cby_1__5_ ( .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_7809 ) , .prog_clk_2_S_in ( prog_clk_2_wires[8] ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_7810 ) , - .prog_clk_2_N_out ( prog_clk_2_wires[9] ) , .prog_clk_3_S_in ( p1951 ) , - .prog_clk_3_N_in ( p25 ) , + .prog_clk_2_N_out ( prog_clk_2_wires[9] ) , .prog_clk_3_S_in ( p2304 ) , + .prog_clk_3_N_in ( p91 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_7811 ) , .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_7812 ) , .clk_2_N_in ( SYNOPSYS_UNCONNECTED_7813 ) , .clk_2_S_in ( clk_2_wires[8] ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_7814 ) , - .clk_2_N_out ( clk_2_wires[9] ) , .clk_3_S_in ( p1834 ) , - .clk_3_N_in ( p682 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_7815 ) , + .clk_2_N_out ( clk_2_wires[9] ) , .clk_3_S_in ( p2304 ) , + .clk_3_N_in ( p1092 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_7815 ) , .clk_3_S_out ( SYNOPSYS_UNCONNECTED_7816 ) ) ; cby_1__1_ cby_1__6_ ( .pReset ( { SYNOPSYS_UNCONNECTED_7817 } ) , @@ -125431,15 +129953,15 @@ cby_1__1_ cby_1__6_ ( .prog_clk_0_W_in ( prog_clk_0_wires[27] ) , .prog_clk_0_S_out ( prog_clk_0_wires[28] ) , .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_7827 ) , - .prog_clk_2_N_in ( p2435 ) , .prog_clk_2_S_in ( p519 ) , + .prog_clk_2_N_in ( p2569 ) , .prog_clk_2_S_in ( p864 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_7828 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_7829 ) , - .prog_clk_3_S_in ( p2479 ) , .prog_clk_3_N_in ( p2365 ) , + .prog_clk_3_S_in ( p2642 ) , .prog_clk_3_N_in ( p2466 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_7830 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_7831 ) , .clk_2_N_in ( p3262 ) , - .clk_2_S_in ( p2355 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_7832 ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_7833 ) , .clk_3_S_in ( p1512 ) , - .clk_3_N_in ( p3222 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_7834 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_7831 ) , .clk_2_N_in ( p2586 ) , + .clk_2_S_in ( p3084 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_7832 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_7833 ) , .clk_3_S_in ( p3111 ) , + .clk_3_N_in ( p2415 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_7834 ) , .clk_3_S_out ( SYNOPSYS_UNCONNECTED_7835 ) ) ; cby_1__1_ cby_1__7_ ( .pReset ( { SYNOPSYS_UNCONNECTED_7836 } ) , @@ -125482,15 +130004,15 @@ cby_1__1_ cby_1__7_ ( .prog_clk_0_W_in ( prog_clk_0_wires[32] ) , .prog_clk_0_S_out ( prog_clk_0_wires[33] ) , .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_7846 ) , - .prog_clk_2_N_in ( p2449 ) , .prog_clk_2_S_in ( p488 ) , + .prog_clk_2_N_in ( p1523 ) , .prog_clk_2_S_in ( p570 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_7847 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_7848 ) , - .prog_clk_3_S_in ( p3372 ) , .prog_clk_3_N_in ( p2363 ) , + .prog_clk_3_S_in ( p1955 ) , .prog_clk_3_N_in ( p162 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_7849 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_7850 ) , .clk_2_N_in ( p2930 ) , - .clk_2_S_in ( p3337 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_7851 ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_7852 ) , .clk_3_S_in ( p2827 ) , - .clk_3_N_in ( p2908 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_7853 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_7850 ) , .clk_2_N_in ( p1900 ) , + .clk_2_S_in ( p2381 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_7851 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_7852 ) , .clk_3_S_in ( p2581 ) , + .clk_3_N_in ( p1730 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_7853 ) , .clk_3_S_out ( SYNOPSYS_UNCONNECTED_7854 ) ) ; cby_1__1_ cby_1__8_ ( .pReset ( { SYNOPSYS_UNCONNECTED_7855 } ) , @@ -125537,14 +130059,14 @@ cby_1__1_ cby_1__8_ ( .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_7866 ) , .prog_clk_2_S_out ( prog_clk_2_wires[18] ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_7867 ) , - .prog_clk_3_S_in ( p1602 ) , .prog_clk_3_N_in ( p1128 ) , + .prog_clk_3_S_in ( p1607 ) , .prog_clk_3_N_in ( p636 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_7868 ) , .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_7869 ) , .clk_2_N_in ( clk_2_wires[17] ) , .clk_2_S_in ( SYNOPSYS_UNCONNECTED_7870 ) , .clk_2_S_out ( clk_2_wires[18] ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_7871 ) , .clk_3_S_in ( p1602 ) , - .clk_3_N_in ( p491 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_7872 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_7871 ) , .clk_3_S_in ( p1607 ) , + .clk_3_N_in ( p1091 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_7872 ) , .clk_3_S_out ( SYNOPSYS_UNCONNECTED_7873 ) ) ; cby_1__1_ cby_1__9_ ( .pReset ( { SYNOPSYS_UNCONNECTED_7874 } ) , @@ -125590,15 +130112,15 @@ cby_1__1_ cby_1__9_ ( .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_7885 ) , .prog_clk_2_S_in ( prog_clk_2_wires[15] ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_7886 ) , - .prog_clk_2_N_out ( prog_clk_2_wires[16] ) , .prog_clk_3_S_in ( p1899 ) , - .prog_clk_3_N_in ( p445 ) , + .prog_clk_2_N_out ( prog_clk_2_wires[16] ) , .prog_clk_3_S_in ( p1337 ) , + .prog_clk_3_N_in ( p27 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_7887 ) , .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_7888 ) , .clk_2_N_in ( SYNOPSYS_UNCONNECTED_7889 ) , .clk_2_S_in ( clk_2_wires[15] ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_7890 ) , - .clk_2_N_out ( clk_2_wires[16] ) , .clk_3_S_in ( p1899 ) , - .clk_3_N_in ( p922 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_7891 ) , + .clk_2_N_out ( clk_2_wires[16] ) , .clk_3_S_in ( p1337 ) , + .clk_3_N_in ( p1170 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_7891 ) , .clk_3_S_out ( SYNOPSYS_UNCONNECTED_7892 ) ) ; cby_1__1_ cby_1__10_ ( .pReset ( { SYNOPSYS_UNCONNECTED_7893 } ) , @@ -125641,15 +130163,15 @@ cby_1__1_ cby_1__10_ ( .prog_clk_0_W_in ( prog_clk_0_wires[47] ) , .prog_clk_0_S_out ( prog_clk_0_wires[48] ) , .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_7903 ) , - .prog_clk_2_N_in ( p2860 ) , .prog_clk_2_S_in ( p876 ) , + .prog_clk_2_N_in ( p1390 ) , .prog_clk_2_S_in ( p908 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_7904 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_7905 ) , - .prog_clk_3_S_in ( p1545 ) , .prog_clk_3_N_in ( p2767 ) , + .prog_clk_3_S_in ( p3008 ) , .prog_clk_3_N_in ( p1008 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_7906 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_7907 ) , .clk_2_N_in ( p3064 ) , - .clk_2_S_in ( p3289 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_7908 ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_7909 ) , .clk_3_S_in ( p3315 ) , - .clk_3_N_in ( p3007 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_7910 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_7907 ) , .clk_2_N_in ( p2943 ) , + .clk_2_S_in ( p2883 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_7908 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_7909 ) , .clk_3_S_in ( p2278 ) , + .clk_3_N_in ( p2870 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_7910 ) , .clk_3_S_out ( SYNOPSYS_UNCONNECTED_7911 ) ) ; cby_1__1_ cby_1__11_ ( .pReset ( { SYNOPSYS_UNCONNECTED_7912 } ) , @@ -125695,15 +130217,15 @@ cby_1__1_ cby_1__11_ ( .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_7923 ) , .prog_clk_2_S_in ( prog_clk_2_wires[22] ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_7924 ) , - .prog_clk_2_N_out ( prog_clk_2_wires[23] ) , .prog_clk_3_S_in ( p1906 ) , - .prog_clk_3_N_in ( p138 ) , + .prog_clk_2_N_out ( prog_clk_2_wires[23] ) , .prog_clk_3_S_in ( p1546 ) , + .prog_clk_3_N_in ( p509 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_7925 ) , .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_7926 ) , .clk_2_N_in ( SYNOPSYS_UNCONNECTED_7927 ) , .clk_2_S_in ( clk_2_wires[22] ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_7928 ) , - .clk_2_N_out ( clk_2_wires[23] ) , .clk_3_S_in ( p1906 ) , - .clk_3_N_in ( p776 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_7929 ) , + .clk_2_N_out ( clk_2_wires[23] ) , .clk_3_S_in ( p1546 ) , + .clk_3_N_in ( p526 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_7929 ) , .clk_3_S_out ( SYNOPSYS_UNCONNECTED_7930 ) ) ; cby_1__1_ cby_1__12_ ( .pReset ( { SYNOPSYS_UNCONNECTED_7931 } ) , @@ -125745,16 +130267,16 @@ cby_1__1_ cby_1__12_ ( .Reset_E_out ( SYNOPSYS_UNCONNECTED_7940 ) , .prog_clk_0_W_in ( prog_clk_0_wires[57] ) , .prog_clk_0_S_out ( prog_clk_0_wires[58] ) , - .prog_clk_0_N_out ( prog_clk_0_wires[60] ) , .prog_clk_2_N_in ( p2831 ) , - .prog_clk_2_S_in ( p391 ) , + .prog_clk_0_N_out ( prog_clk_0_wires[60] ) , .prog_clk_2_N_in ( p2774 ) , + .prog_clk_2_S_in ( p1040 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_7941 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_7942 ) , - .prog_clk_3_S_in ( p2430 ) , .prog_clk_3_N_in ( p2726 ) , + .prog_clk_3_S_in ( p2837 ) , .prog_clk_3_N_in ( p2646 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_7943 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_7944 ) , .clk_2_N_in ( p3260 ) , - .clk_2_S_in ( p2283 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_7945 ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_7946 ) , .clk_3_S_in ( p2519 ) , - .clk_3_N_in ( p3223 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_7947 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_7944 ) , .clk_2_N_in ( p2562 ) , + .clk_2_S_in ( p2720 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_7945 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_7946 ) , .clk_3_S_in ( p349 ) , + .clk_3_N_in ( p2435 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_7947 ) , .clk_3_S_out ( SYNOPSYS_UNCONNECTED_7948 ) ) ; cby_1__1_ cby_2__1_ ( .pReset ( { SYNOPSYS_UNCONNECTED_7949 } ) , @@ -125797,15 +130319,15 @@ cby_1__1_ cby_2__1_ ( .prog_clk_0_W_in ( prog_clk_0_wires[64] ) , .prog_clk_0_S_out ( prog_clk_0_wires[65] ) , .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_7959 ) , - .prog_clk_2_N_in ( p2834 ) , .prog_clk_2_S_in ( p638 ) , + .prog_clk_2_N_in ( p1695 ) , .prog_clk_2_S_in ( p707 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_7960 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_7961 ) , - .prog_clk_3_S_in ( p2166 ) , .prog_clk_3_N_in ( p2765 ) , + .prog_clk_3_S_in ( p2944 ) , .prog_clk_3_N_in ( p1812 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_7962 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_7963 ) , .clk_2_N_in ( p2184 ) , - .clk_2_S_in ( p2538 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_7964 ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_7965 ) , .clk_3_S_in ( p2667 ) , - .clk_3_N_in ( p2046 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_7966 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_7963 ) , .clk_2_N_in ( p3242 ) , + .clk_2_S_in ( p2884 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_7964 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_7965 ) , .clk_3_S_in ( p2518 ) , + .clk_3_N_in ( p3172 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_7966 ) , .clk_3_S_out ( SYNOPSYS_UNCONNECTED_7967 ) ) ; cby_1__1_ cby_2__2_ ( .pReset ( { SYNOPSYS_UNCONNECTED_7968 } ) , @@ -125848,15 +130370,15 @@ cby_1__1_ cby_2__2_ ( .prog_clk_0_W_in ( prog_clk_0_wires[67] ) , .prog_clk_0_S_out ( prog_clk_0_wires[68] ) , .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_7978 ) , - .prog_clk_2_N_in ( p2406 ) , .prog_clk_2_S_in ( p1044 ) , + .prog_clk_2_N_in ( p2747 ) , .prog_clk_2_S_in ( p309 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_7979 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_7980 ) , - .prog_clk_3_S_in ( p2486 ) , .prog_clk_3_N_in ( p2376 ) , + .prog_clk_3_S_in ( p2843 ) , .prog_clk_3_N_in ( p2659 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_7981 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_7982 ) , .clk_2_N_in ( p3174 ) , - .clk_2_S_in ( p2291 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_7983 ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_7984 ) , .clk_3_S_in ( p1933 ) , - .clk_3_N_in ( p3120 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_7985 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_7982 ) , .clk_2_N_in ( p2545 ) , + .clk_2_S_in ( p3043 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_7983 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_7984 ) , .clk_3_S_in ( p3133 ) , + .clk_3_N_in ( p2418 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_7985 ) , .clk_3_S_out ( SYNOPSYS_UNCONNECTED_7986 ) ) ; cby_1__1_ cby_2__3_ ( .pReset ( { SYNOPSYS_UNCONNECTED_7987 } ) , @@ -125899,14 +130421,14 @@ cby_1__1_ cby_2__3_ ( .prog_clk_0_W_in ( prog_clk_0_wires[70] ) , .prog_clk_0_S_out ( prog_clk_0_wires[71] ) , .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_7997 ) , - .prog_clk_2_N_in ( p1484 ) , .prog_clk_2_S_in ( p820 ) , + .prog_clk_2_N_in ( p1946 ) , .prog_clk_2_S_in ( p785 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_7998 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_7999 ) , .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_8000 ) , .prog_clk_3_N_in ( prog_clk_3_wires[68] ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_8001 ) , - .prog_clk_3_S_out ( prog_clk_3_wires[69] ) , .clk_2_N_in ( p1484 ) , - .clk_2_S_in ( p375 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8002 ) , + .prog_clk_3_S_out ( prog_clk_3_wires[69] ) , .clk_2_N_in ( p1946 ) , + .clk_2_S_in ( p2 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8002 ) , .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8003 ) , .clk_3_S_in ( SYNOPSYS_UNCONNECTED_8004 ) , .clk_3_N_in ( clk_3_wires[68] ) , @@ -125953,14 +130475,14 @@ cby_1__1_ cby_2__4_ ( .prog_clk_0_W_in ( prog_clk_0_wires[73] ) , .prog_clk_0_S_out ( prog_clk_0_wires[74] ) , .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_8016 ) , - .prog_clk_2_N_in ( p1497 ) , .prog_clk_2_S_in ( p2596 ) , + .prog_clk_2_N_in ( p1292 ) , .prog_clk_2_S_in ( p335 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_8017 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_8018 ) , .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_8019 ) , .prog_clk_3_N_in ( prog_clk_3_wires[64] ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_8020 ) , - .prog_clk_3_S_out ( prog_clk_3_wires[65] ) , .clk_2_N_in ( p1497 ) , - .clk_2_S_in ( p2523 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8021 ) , + .prog_clk_3_S_out ( prog_clk_3_wires[65] ) , .clk_2_N_in ( p1292 ) , + .clk_2_S_in ( p2442 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8021 ) , .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8022 ) , .clk_3_S_in ( SYNOPSYS_UNCONNECTED_8023 ) , .clk_3_N_in ( clk_3_wires[64] ) , @@ -126007,14 +130529,14 @@ cby_1__1_ cby_2__5_ ( .prog_clk_0_W_in ( prog_clk_0_wires[76] ) , .prog_clk_0_S_out ( prog_clk_0_wires[77] ) , .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_8035 ) , - .prog_clk_2_N_in ( p1113 ) , .prog_clk_2_S_in ( p232 ) , + .prog_clk_2_N_in ( p1883 ) , .prog_clk_2_S_in ( p1747 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_8036 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_8037 ) , .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_8038 ) , .prog_clk_3_N_in ( prog_clk_3_wires[58] ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_8039 ) , - .prog_clk_3_S_out ( prog_clk_3_wires[59] ) , .clk_2_N_in ( p1113 ) , - .clk_2_S_in ( p330 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8040 ) , + .prog_clk_3_S_out ( prog_clk_3_wires[59] ) , .clk_2_N_in ( p1883 ) , + .clk_2_S_in ( p890 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8040 ) , .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8041 ) , .clk_3_S_in ( SYNOPSYS_UNCONNECTED_8042 ) , .clk_3_N_in ( clk_3_wires[58] ) , @@ -126061,14 +130583,14 @@ cby_1__1_ cby_2__6_ ( .prog_clk_0_W_in ( prog_clk_0_wires[79] ) , .prog_clk_0_S_out ( prog_clk_0_wires[80] ) , .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_8054 ) , - .prog_clk_2_N_in ( p1572 ) , .prog_clk_2_S_in ( p2599 ) , + .prog_clk_2_N_in ( p1914 ) , .prog_clk_2_S_in ( p1787 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_8055 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_8056 ) , .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_8057 ) , .prog_clk_3_N_in ( prog_clk_3_wires[54] ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_8058 ) , - .prog_clk_3_S_out ( prog_clk_3_wires[55] ) , .clk_2_N_in ( p1572 ) , - .clk_2_S_in ( p2741 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8059 ) , + .prog_clk_3_S_out ( prog_clk_3_wires[55] ) , .clk_2_N_in ( p1789 ) , + .clk_2_S_in ( p1746 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8059 ) , .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8060 ) , .clk_3_S_in ( SYNOPSYS_UNCONNECTED_8061 ) , .clk_3_N_in ( clk_3_wires[54] ) , @@ -126115,14 +130637,14 @@ cby_1__1_ cby_2__7_ ( .prog_clk_0_W_in ( prog_clk_0_wires[82] ) , .prog_clk_0_S_out ( prog_clk_0_wires[83] ) , .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_8073 ) , - .prog_clk_2_N_in ( p1594 ) , .prog_clk_2_S_in ( p1691 ) , + .prog_clk_2_N_in ( p1378 ) , .prog_clk_2_S_in ( p2143 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_8074 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_8075 ) , .prog_clk_3_S_in ( prog_clk_3_wires[52] ) , .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_8076 ) , .prog_clk_3_N_out ( prog_clk_3_wires[53] ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8077 ) , .clk_2_N_in ( p1594 ) , - .clk_2_S_in ( p2003 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8078 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8077 ) , .clk_2_N_in ( p1524 ) , + .clk_2_S_in ( p2073 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8078 ) , .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8079 ) , .clk_3_S_in ( clk_3_wires[52] ) , .clk_3_N_in ( SYNOPSYS_UNCONNECTED_8080 ) , @@ -126169,14 +130691,14 @@ cby_1__1_ cby_2__8_ ( .prog_clk_0_W_in ( prog_clk_0_wires[85] ) , .prog_clk_0_S_out ( prog_clk_0_wires[86] ) , .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_8092 ) , - .prog_clk_2_N_in ( p1297 ) , .prog_clk_2_S_in ( p2070 ) , + .prog_clk_2_N_in ( p991 ) , .prog_clk_2_S_in ( p168 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_8093 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_8094 ) , .prog_clk_3_S_in ( prog_clk_3_wires[56] ) , .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_8095 ) , .prog_clk_3_N_out ( prog_clk_3_wires[57] ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8096 ) , .clk_2_N_in ( p1297 ) , - .clk_2_S_in ( p1975 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8097 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8096 ) , .clk_2_N_in ( p1460 ) , + .clk_2_S_in ( p2129 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8097 ) , .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8098 ) , .clk_3_S_in ( clk_3_wires[56] ) , .clk_3_N_in ( SYNOPSYS_UNCONNECTED_8099 ) , @@ -126223,14 +130745,14 @@ cby_1__1_ cby_2__9_ ( .prog_clk_0_W_in ( prog_clk_0_wires[88] ) , .prog_clk_0_S_out ( prog_clk_0_wires[89] ) , .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_8111 ) , - .prog_clk_2_N_in ( p1362 ) , .prog_clk_2_S_in ( p443 ) , + .prog_clk_2_N_in ( p1416 ) , .prog_clk_2_S_in ( p1679 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_8112 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_8113 ) , .prog_clk_3_S_in ( prog_clk_3_wires[62] ) , .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_8114 ) , .prog_clk_3_N_out ( prog_clk_3_wires[63] ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8115 ) , .clk_2_N_in ( p1362 ) , - .clk_2_S_in ( p828 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8116 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8115 ) , .clk_2_N_in ( p1363 ) , + .clk_2_S_in ( p44 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8116 ) , .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8117 ) , .clk_3_S_in ( clk_3_wires[62] ) , .clk_3_N_in ( SYNOPSYS_UNCONNECTED_8118 ) , @@ -126277,14 +130799,14 @@ cby_1__1_ cby_2__10_ ( .prog_clk_0_W_in ( prog_clk_0_wires[91] ) , .prog_clk_0_S_out ( prog_clk_0_wires[92] ) , .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_8130 ) , - .prog_clk_2_N_in ( p1883 ) , .prog_clk_2_S_in ( p2074 ) , + .prog_clk_2_N_in ( p1359 ) , .prog_clk_2_S_in ( p988 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_8131 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_8132 ) , .prog_clk_3_S_in ( prog_clk_3_wires[66] ) , .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_8133 ) , .prog_clk_3_N_out ( prog_clk_3_wires[67] ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8134 ) , .clk_2_N_in ( p1883 ) , - .clk_2_S_in ( p2019 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8135 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8134 ) , .clk_2_N_in ( p1359 ) , + .clk_2_S_in ( p2697 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8135 ) , .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8136 ) , .clk_3_S_in ( clk_3_wires[66] ) , .clk_3_N_in ( SYNOPSYS_UNCONNECTED_8137 ) , @@ -126331,15 +130853,15 @@ cby_1__1_ cby_2__11_ ( .prog_clk_0_W_in ( prog_clk_0_wires[94] ) , .prog_clk_0_S_out ( prog_clk_0_wires[95] ) , .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_8149 ) , - .prog_clk_2_N_in ( p2096 ) , .prog_clk_2_S_in ( p800 ) , + .prog_clk_2_N_in ( p2025 ) , .prog_clk_2_S_in ( p1042 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_8150 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_8151 ) , - .prog_clk_3_S_in ( p2979 ) , .prog_clk_3_N_in ( p2067 ) , + .prog_clk_3_S_in ( p2532 ) , .prog_clk_3_N_in ( p1733 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_8152 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8153 ) , .clk_2_N_in ( p2807 ) , - .clk_2_S_in ( p2872 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8154 ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8155 ) , .clk_3_S_in ( p2819 ) , - .clk_3_N_in ( p2747 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8156 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8153 ) , .clk_2_N_in ( p3239 ) , + .clk_2_S_in ( p2425 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8154 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8155 ) , .clk_3_S_in ( p2033 ) , + .clk_3_N_in ( p3180 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8156 ) , .clk_3_S_out ( SYNOPSYS_UNCONNECTED_8157 ) ) ; cby_1__1_ cby_2__12_ ( .pReset ( { SYNOPSYS_UNCONNECTED_8158 } ) , @@ -126381,16 +130903,16 @@ cby_1__1_ cby_2__12_ ( .Reset_E_out ( SYNOPSYS_UNCONNECTED_8167 ) , .prog_clk_0_W_in ( prog_clk_0_wires[97] ) , .prog_clk_0_S_out ( prog_clk_0_wires[98] ) , - .prog_clk_0_N_out ( prog_clk_0_wires[100] ) , .prog_clk_2_N_in ( p2196 ) , - .prog_clk_2_S_in ( p901 ) , + .prog_clk_0_N_out ( prog_clk_0_wires[100] ) , .prog_clk_2_N_in ( p2204 ) , + .prog_clk_2_S_in ( p366 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_8168 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_8169 ) , - .prog_clk_3_S_in ( p2805 ) , .prog_clk_3_N_in ( p1968 ) , + .prog_clk_3_S_in ( p2639 ) , .prog_clk_3_N_in ( p2060 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_8170 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8171 ) , .clk_2_N_in ( p3080 ) , - .clk_2_S_in ( p3034 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8172 ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8173 ) , .clk_3_S_in ( p3087 ) , - .clk_3_N_in ( p2998 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8174 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8171 ) , .clk_2_N_in ( p2503 ) , + .clk_2_S_in ( p2472 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8172 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8173 ) , .clk_3_S_in ( p1989 ) , + .clk_3_N_in ( p2387 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8174 ) , .clk_3_S_out ( SYNOPSYS_UNCONNECTED_8175 ) ) ; cby_1__1_ cby_3__1_ ( .pReset ( { SYNOPSYS_UNCONNECTED_8176 } ) , @@ -126433,15 +130955,15 @@ cby_1__1_ cby_3__1_ ( .prog_clk_0_W_in ( prog_clk_0_wires[102] ) , .prog_clk_0_S_out ( prog_clk_0_wires[103] ) , .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_8186 ) , - .prog_clk_2_N_in ( p2262 ) , .prog_clk_2_S_in ( p793 ) , + .prog_clk_2_N_in ( p1857 ) , .prog_clk_2_S_in ( p45 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_8187 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_8188 ) , - .prog_clk_3_S_in ( p2257 ) , .prog_clk_3_N_in ( p2038 ) , + .prog_clk_3_S_in ( p2038 ) , .prog_clk_3_N_in ( p1755 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_8189 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8190 ) , .clk_2_N_in ( p2800 ) , - .clk_2_S_in ( p1988 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8191 ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8192 ) , .clk_3_S_in ( p1886 ) , - .clk_3_N_in ( p2716 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8193 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8190 ) , .clk_2_N_in ( p2752 ) , + .clk_2_S_in ( p3182 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8191 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8192 ) , .clk_3_S_in ( p3264 ) , + .clk_3_N_in ( p2654 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8193 ) , .clk_3_S_out ( SYNOPSYS_UNCONNECTED_8194 ) ) ; cby_1__1_ cby_3__2_ ( .pReset ( { SYNOPSYS_UNCONNECTED_8195 } ) , @@ -126488,14 +131010,14 @@ cby_1__1_ cby_3__2_ ( .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_8206 ) , .prog_clk_2_S_out ( prog_clk_2_wires[30] ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_8207 ) , - .prog_clk_3_S_in ( p2109 ) , .prog_clk_3_N_in ( p344 ) , + .prog_clk_3_S_in ( p2237 ) , .prog_clk_3_N_in ( p666 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_8208 ) , .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8209 ) , .clk_2_N_in ( clk_2_wires[29] ) , .clk_2_S_in ( SYNOPSYS_UNCONNECTED_8210 ) , .clk_2_S_out ( clk_2_wires[30] ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8211 ) , .clk_3_S_in ( p2109 ) , - .clk_3_N_in ( p738 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8212 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8211 ) , .clk_3_S_in ( p2237 ) , + .clk_3_N_in ( p970 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8212 ) , .clk_3_S_out ( SYNOPSYS_UNCONNECTED_8213 ) ) ; cby_1__1_ cby_3__3_ ( .pReset ( { SYNOPSYS_UNCONNECTED_8214 } ) , @@ -126538,15 +131060,15 @@ cby_1__1_ cby_3__3_ ( .prog_clk_0_W_in ( prog_clk_0_wires[108] ) , .prog_clk_0_S_out ( prog_clk_0_wires[109] ) , .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_8224 ) , - .prog_clk_2_N_in ( p1911 ) , .prog_clk_2_S_in ( p743 ) , + .prog_clk_2_N_in ( p2783 ) , .prog_clk_2_S_in ( p457 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_8225 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_8226 ) , - .prog_clk_3_S_in ( p2797 ) , .prog_clk_3_N_in ( p1638 ) , + .prog_clk_3_S_in ( p1575 ) , .prog_clk_3_N_in ( p2651 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_8227 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8228 ) , .clk_2_N_in ( p2400 ) , - .clk_2_S_in ( p2725 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8229 ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8230 ) , .clk_3_S_in ( p2268 ) , - .clk_3_N_in ( p2322 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8231 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8228 ) , .clk_2_N_in ( p2790 ) , + .clk_2_S_in ( p3044 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8229 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8230 ) , .clk_3_S_in ( p3127 ) , + .clk_3_N_in ( p2721 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8231 ) , .clk_3_S_out ( SYNOPSYS_UNCONNECTED_8232 ) ) ; cby_1__1_ cby_3__4_ ( .pReset ( { SYNOPSYS_UNCONNECTED_8233 } ) , @@ -126593,14 +131115,14 @@ cby_1__1_ cby_3__4_ ( .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_8244 ) , .prog_clk_2_S_out ( prog_clk_2_wires[41] ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_8245 ) , - .prog_clk_3_S_in ( p1547 ) , .prog_clk_3_N_in ( p369 ) , + .prog_clk_3_S_in ( p895 ) , .prog_clk_3_N_in ( p497 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_8246 ) , .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8247 ) , .clk_2_N_in ( clk_2_wires[40] ) , .clk_2_S_in ( SYNOPSYS_UNCONNECTED_8248 ) , .clk_2_S_out ( clk_2_wires[41] ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8249 ) , .clk_3_S_in ( p1547 ) , - .clk_3_N_in ( p198 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8250 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8249 ) , .clk_3_S_in ( p895 ) , + .clk_3_N_in ( p429 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8250 ) , .clk_3_S_out ( SYNOPSYS_UNCONNECTED_8251 ) ) ; cby_1__1_ cby_3__5_ ( .pReset ( { SYNOPSYS_UNCONNECTED_8252 } ) , @@ -126646,15 +131168,15 @@ cby_1__1_ cby_3__5_ ( .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_8263 ) , .prog_clk_2_S_in ( prog_clk_2_wires[38] ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_8264 ) , - .prog_clk_2_N_out ( prog_clk_2_wires[39] ) , .prog_clk_3_S_in ( p2131 ) , - .prog_clk_3_N_in ( p606 ) , + .prog_clk_2_N_out ( prog_clk_2_wires[39] ) , .prog_clk_3_S_in ( p1520 ) , + .prog_clk_3_N_in ( p642 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_8265 ) , .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8266 ) , .clk_2_N_in ( SYNOPSYS_UNCONNECTED_8267 ) , .clk_2_S_in ( clk_2_wires[38] ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8268 ) , - .clk_2_N_out ( clk_2_wires[39] ) , .clk_3_S_in ( p2131 ) , - .clk_3_N_in ( p88 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8269 ) , + .clk_2_N_out ( clk_2_wires[39] ) , .clk_3_S_in ( p1520 ) , + .clk_3_N_in ( p1215 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8269 ) , .clk_3_S_out ( SYNOPSYS_UNCONNECTED_8270 ) ) ; cby_1__1_ cby_3__6_ ( .pReset ( { SYNOPSYS_UNCONNECTED_8271 } ) , @@ -126697,15 +131219,15 @@ cby_1__1_ cby_3__6_ ( .prog_clk_0_W_in ( prog_clk_0_wires[117] ) , .prog_clk_0_S_out ( prog_clk_0_wires[118] ) , .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_8281 ) , - .prog_clk_2_N_in ( p1366 ) , .prog_clk_2_S_in ( p349 ) , + .prog_clk_2_N_in ( p2827 ) , .prog_clk_2_S_in ( p588 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_8282 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_8283 ) , - .prog_clk_3_S_in ( p2423 ) , .prog_clk_3_N_in ( p768 ) , + .prog_clk_3_S_in ( p1403 ) , .prog_clk_3_N_in ( p2703 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_8284 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8285 ) , .clk_2_N_in ( p2412 ) , - .clk_2_S_in ( p3237 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8286 ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8287 ) , .clk_3_S_in ( p3256 ) , - .clk_3_N_in ( p2351 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8288 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8285 ) , .clk_2_N_in ( p2963 ) , + .clk_2_S_in ( p2867 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8286 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8287 ) , .clk_3_S_in ( p2940 ) , + .clk_3_N_in ( p2866 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8288 ) , .clk_3_S_out ( SYNOPSYS_UNCONNECTED_8289 ) ) ; cby_1__1_ cby_3__7_ ( .pReset ( { SYNOPSYS_UNCONNECTED_8290 } ) , @@ -126748,15 +131270,15 @@ cby_1__1_ cby_3__7_ ( .prog_clk_0_W_in ( prog_clk_0_wires[120] ) , .prog_clk_0_S_out ( prog_clk_0_wires[121] ) , .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_8300 ) , - .prog_clk_2_N_in ( p2704 ) , .prog_clk_2_S_in ( p1750 ) , + .prog_clk_2_N_in ( p2003 ) , .prog_clk_2_S_in ( p2160 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_8301 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_8302 ) , - .prog_clk_3_S_in ( p1480 ) , .prog_clk_3_N_in ( p2553 ) , + .prog_clk_3_S_in ( p3170 ) , .prog_clk_3_N_in ( p1723 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_8303 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8304 ) , .clk_2_N_in ( p2707 ) , - .clk_2_S_in ( p2541 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8305 ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8306 ) , .clk_3_S_in ( p2641 ) , - .clk_3_N_in ( p2602 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8307 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8304 ) , .clk_2_N_in ( p2985 ) , + .clk_2_S_in ( p3055 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8305 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8306 ) , .clk_3_S_in ( p3153 ) , + .clk_3_N_in ( p2896 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8307 ) , .clk_3_S_out ( SYNOPSYS_UNCONNECTED_8308 ) ) ; cby_1__1_ cby_3__8_ ( .pReset ( { SYNOPSYS_UNCONNECTED_8309 } ) , @@ -126803,14 +131325,14 @@ cby_1__1_ cby_3__8_ ( .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_8320 ) , .prog_clk_2_S_out ( prog_clk_2_wires[54] ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_8321 ) , - .prog_clk_3_S_in ( p1474 ) , .prog_clk_3_N_in ( p576 ) , + .prog_clk_3_S_in ( p1455 ) , .prog_clk_3_N_in ( p1033 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_8322 ) , .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8323 ) , .clk_2_N_in ( clk_2_wires[53] ) , .clk_2_S_in ( SYNOPSYS_UNCONNECTED_8324 ) , .clk_2_S_out ( clk_2_wires[54] ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8325 ) , .clk_3_S_in ( p1474 ) , - .clk_3_N_in ( p885 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8326 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8325 ) , .clk_3_S_in ( p1455 ) , + .clk_3_N_in ( p752 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8326 ) , .clk_3_S_out ( SYNOPSYS_UNCONNECTED_8327 ) ) ; cby_1__1_ cby_3__9_ ( .pReset ( { SYNOPSYS_UNCONNECTED_8328 } ) , @@ -126856,15 +131378,15 @@ cby_1__1_ cby_3__9_ ( .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_8339 ) , .prog_clk_2_S_in ( prog_clk_2_wires[51] ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_8340 ) , - .prog_clk_2_N_out ( prog_clk_2_wires[52] ) , .prog_clk_3_S_in ( p1758 ) , - .prog_clk_3_N_in ( p525 ) , + .prog_clk_2_N_out ( prog_clk_2_wires[52] ) , .prog_clk_3_S_in ( p2014 ) , + .prog_clk_3_N_in ( p539 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_8341 ) , .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8342 ) , .clk_2_N_in ( SYNOPSYS_UNCONNECTED_8343 ) , .clk_2_S_in ( clk_2_wires[51] ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8344 ) , - .clk_2_N_out ( clk_2_wires[52] ) , .clk_3_S_in ( p1758 ) , - .clk_3_N_in ( p936 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8345 ) , + .clk_2_N_out ( clk_2_wires[52] ) , .clk_3_S_in ( p2014 ) , + .clk_3_N_in ( p652 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8345 ) , .clk_3_S_out ( SYNOPSYS_UNCONNECTED_8346 ) ) ; cby_1__1_ cby_3__10_ ( .pReset ( { SYNOPSYS_UNCONNECTED_8347 } ) , @@ -126907,15 +131429,15 @@ cby_1__1_ cby_3__10_ ( .prog_clk_0_W_in ( prog_clk_0_wires[129] ) , .prog_clk_0_S_out ( prog_clk_0_wires[130] ) , .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_8357 ) , - .prog_clk_2_N_in ( p2153 ) , .prog_clk_2_S_in ( p603 ) , + .prog_clk_2_N_in ( p2270 ) , .prog_clk_2_S_in ( p524 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_8358 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_8359 ) , - .prog_clk_3_S_in ( p2197 ) , .prog_clk_3_N_in ( p2057 ) , + .prog_clk_3_S_in ( p3028 ) , .prog_clk_3_N_in ( p2173 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_8360 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8361 ) , .clk_2_N_in ( p2382 ) , - .clk_2_S_in ( p3335 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8362 ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8363 ) , .clk_3_S_in ( p3361 ) , - .clk_3_N_in ( p2314 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8364 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8361 ) , .clk_2_N_in ( p2785 ) , + .clk_2_S_in ( p2872 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8362 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8363 ) , .clk_3_S_in ( p1525 ) , + .clk_3_N_in ( p2678 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8364 ) , .clk_3_S_out ( SYNOPSYS_UNCONNECTED_8365 ) ) ; cby_1__1_ cby_3__11_ ( .pReset ( { SYNOPSYS_UNCONNECTED_8366 } ) , @@ -126961,15 +131483,15 @@ cby_1__1_ cby_3__11_ ( .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_8377 ) , .prog_clk_2_S_in ( prog_clk_2_wires[64] ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_8378 ) , - .prog_clk_2_N_out ( prog_clk_2_wires[65] ) , .prog_clk_3_S_in ( p2160 ) , - .prog_clk_3_N_in ( p903 ) , + .prog_clk_2_N_out ( prog_clk_2_wires[65] ) , .prog_clk_3_S_in ( p1472 ) , + .prog_clk_3_N_in ( p760 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_8379 ) , .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8380 ) , .clk_2_N_in ( SYNOPSYS_UNCONNECTED_8381 ) , .clk_2_S_in ( clk_2_wires[64] ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8382 ) , - .clk_2_N_out ( clk_2_wires[65] ) , .clk_3_S_in ( p2160 ) , - .clk_3_N_in ( p572 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8383 ) , + .clk_2_N_out ( clk_2_wires[65] ) , .clk_3_S_in ( p1472 ) , + .clk_3_N_in ( p525 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8383 ) , .clk_3_S_out ( SYNOPSYS_UNCONNECTED_8384 ) ) ; cby_1__1_ cby_3__12_ ( .pReset ( { SYNOPSYS_UNCONNECTED_8385 } ) , @@ -127011,16 +131533,16 @@ cby_1__1_ cby_3__12_ ( .Reset_E_out ( SYNOPSYS_UNCONNECTED_8394 ) , .prog_clk_0_W_in ( prog_clk_0_wires[135] ) , .prog_clk_0_S_out ( prog_clk_0_wires[136] ) , - .prog_clk_0_N_out ( prog_clk_0_wires[138] ) , .prog_clk_2_N_in ( p2462 ) , - .prog_clk_2_S_in ( p707 ) , + .prog_clk_0_N_out ( prog_clk_0_wires[138] ) , .prog_clk_2_N_in ( p1836 ) , + .prog_clk_2_S_in ( p1024 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_8395 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_8396 ) , - .prog_clk_3_S_in ( p3247 ) , .prog_clk_3_N_in ( p2298 ) , + .prog_clk_3_S_in ( p3394 ) , .prog_clk_3_N_in ( p1740 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_8397 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8398 ) , .clk_2_N_in ( p3203 ) , - .clk_2_S_in ( p3299 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8399 ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8400 ) , .clk_3_S_in ( p3305 ) , - .clk_3_N_in ( p3113 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8401 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8398 ) , .clk_2_N_in ( p3095 ) , + .clk_2_S_in ( p3384 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8399 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8400 ) , .clk_3_S_in ( p1853 ) , + .clk_3_N_in ( p3074 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8401 ) , .clk_3_S_out ( SYNOPSYS_UNCONNECTED_8402 ) ) ; cby_1__1_ cby_4__1_ ( .pReset ( { SYNOPSYS_UNCONNECTED_8403 } ) , @@ -127063,15 +131585,15 @@ cby_1__1_ cby_4__1_ ( .prog_clk_0_W_in ( prog_clk_0_wires[140] ) , .prog_clk_0_S_out ( prog_clk_0_wires[141] ) , .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_8413 ) , - .prog_clk_2_N_in ( p2950 ) , .prog_clk_2_S_in ( p372 ) , + .prog_clk_2_N_in ( p2326 ) , .prog_clk_2_S_in ( p79 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_8414 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_8415 ) , - .prog_clk_3_S_in ( p2671 ) , .prog_clk_3_N_in ( p2877 ) , + .prog_clk_3_S_in ( p2829 ) , .prog_clk_3_N_in ( p2179 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_8416 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8417 ) , .clk_2_N_in ( p3255 ) , - .clk_2_S_in ( p2903 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8418 ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8419 ) , .clk_3_S_in ( p2946 ) , - .clk_3_N_in ( p3207 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8420 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8417 ) , .clk_2_N_in ( p2359 ) , + .clk_2_S_in ( p2661 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8418 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8419 ) , .clk_3_S_in ( p2606 ) , + .clk_3_N_in ( p2130 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8420 ) , .clk_3_S_out ( SYNOPSYS_UNCONNECTED_8421 ) ) ; cby_1__1_ cby_4__2_ ( .pReset ( { SYNOPSYS_UNCONNECTED_8422 } ) , @@ -127114,15 +131636,15 @@ cby_1__1_ cby_4__2_ ( .prog_clk_0_W_in ( prog_clk_0_wires[143] ) , .prog_clk_0_S_out ( prog_clk_0_wires[144] ) , .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_8432 ) , - .prog_clk_2_N_in ( p2228 ) , .prog_clk_2_S_in ( p282 ) , + .prog_clk_2_N_in ( p2254 ) , .prog_clk_2_S_in ( p995 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_8433 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_8434 ) , - .prog_clk_3_S_in ( p1935 ) , .prog_clk_3_N_in ( p2062 ) , + .prog_clk_3_S_in ( p3021 ) , .prog_clk_3_N_in ( p2075 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_8435 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8436 ) , .clk_2_N_in ( p2012 ) , - .clk_2_S_in ( p3151 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8437 ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8438 ) , .clk_3_S_in ( p3170 ) , - .clk_3_N_in ( p2083 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8439 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8436 ) , .clk_2_N_in ( p3126 ) , + .clk_2_S_in ( p2923 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8437 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8438 ) , .clk_3_S_in ( p2967 ) , + .clk_3_N_in ( p3036 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8439 ) , .clk_3_S_out ( SYNOPSYS_UNCONNECTED_8440 ) ) ; cby_1__1_ cby_4__3_ ( .pReset ( { SYNOPSYS_UNCONNECTED_8441 } ) , @@ -127165,14 +131687,14 @@ cby_1__1_ cby_4__3_ ( .prog_clk_0_W_in ( prog_clk_0_wires[146] ) , .prog_clk_0_S_out ( prog_clk_0_wires[147] ) , .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_8451 ) , - .prog_clk_2_N_in ( p2240 ) , .prog_clk_2_S_in ( p661 ) , + .prog_clk_2_N_in ( p1564 ) , .prog_clk_2_S_in ( p344 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_8452 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_8453 ) , .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_8454 ) , .prog_clk_3_N_in ( prog_clk_3_wires[24] ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_8455 ) , - .prog_clk_3_S_out ( prog_clk_3_wires[25] ) , .clk_2_N_in ( p2240 ) , - .clk_2_S_in ( p1059 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8456 ) , + .prog_clk_3_S_out ( prog_clk_3_wires[25] ) , .clk_2_N_in ( p1564 ) , + .clk_2_S_in ( p1083 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8456 ) , .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8457 ) , .clk_3_S_in ( SYNOPSYS_UNCONNECTED_8458 ) , .clk_3_N_in ( clk_3_wires[24] ) , @@ -127219,14 +131741,14 @@ cby_1__1_ cby_4__4_ ( .prog_clk_0_W_in ( prog_clk_0_wires[149] ) , .prog_clk_0_S_out ( prog_clk_0_wires[150] ) , .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_8470 ) , - .prog_clk_2_N_in ( p1596 ) , .prog_clk_2_S_in ( p1663 ) , + .prog_clk_2_N_in ( p1280 ) , .prog_clk_2_S_in ( p892 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_8471 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_8472 ) , .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_8473 ) , .prog_clk_3_N_in ( prog_clk_3_wires[20] ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_8474 ) , - .prog_clk_3_S_out ( prog_clk_3_wires[21] ) , .clk_2_N_in ( p1596 ) , - .clk_2_S_in ( p2313 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8475 ) , + .prog_clk_3_S_out ( prog_clk_3_wires[21] ) , .clk_2_N_in ( p1280 ) , + .clk_2_S_in ( p212 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8475 ) , .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8476 ) , .clk_3_S_in ( SYNOPSYS_UNCONNECTED_8477 ) , .clk_3_N_in ( clk_3_wires[20] ) , @@ -127273,14 +131795,14 @@ cby_1__1_ cby_4__5_ ( .prog_clk_0_W_in ( prog_clk_0_wires[152] ) , .prog_clk_0_S_out ( prog_clk_0_wires[153] ) , .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_8489 ) , - .prog_clk_2_N_in ( p1367 ) , .prog_clk_2_S_in ( p271 ) , + .prog_clk_2_N_in ( p1630 ) , .prog_clk_2_S_in ( p322 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_8490 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_8491 ) , .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_8492 ) , .prog_clk_3_N_in ( prog_clk_3_wires[14] ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_8493 ) , - .prog_clk_3_S_out ( prog_clk_3_wires[15] ) , .clk_2_N_in ( p1367 ) , - .clk_2_S_in ( p761 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8494 ) , + .prog_clk_3_S_out ( prog_clk_3_wires[15] ) , .clk_2_N_in ( p1630 ) , + .clk_2_S_in ( p1006 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8494 ) , .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8495 ) , .clk_3_S_in ( SYNOPSYS_UNCONNECTED_8496 ) , .clk_3_N_in ( clk_3_wires[14] ) , @@ -127327,14 +131849,14 @@ cby_1__1_ cby_4__6_ ( .prog_clk_0_W_in ( prog_clk_0_wires[155] ) , .prog_clk_0_S_out ( prog_clk_0_wires[156] ) , .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_8508 ) , - .prog_clk_2_N_in ( p1296 ) , .prog_clk_2_S_in ( p327 ) , + .prog_clk_2_N_in ( p2044 ) , .prog_clk_2_S_in ( p1775 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_8509 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_8510 ) , .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_8511 ) , .prog_clk_3_N_in ( prog_clk_3_wires[10] ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_8512 ) , - .prog_clk_3_S_out ( prog_clk_3_wires[11] ) , .clk_2_N_in ( p1296 ) , - .clk_2_S_in ( p456 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8513 ) , + .prog_clk_3_S_out ( prog_clk_3_wires[11] ) , .clk_2_N_in ( p2044 ) , + .clk_2_S_in ( p2099 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8513 ) , .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8514 ) , .clk_3_S_in ( SYNOPSYS_UNCONNECTED_8515 ) , .clk_3_N_in ( clk_3_wires[10] ) , @@ -127381,14 +131903,14 @@ cby_1__1_ cby_4__7_ ( .prog_clk_0_W_in ( prog_clk_0_wires[158] ) , .prog_clk_0_S_out ( prog_clk_0_wires[159] ) , .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_8527 ) , - .prog_clk_2_N_in ( p2223 ) , .prog_clk_2_S_in ( p2372 ) , + .prog_clk_2_N_in ( p2320 ) , .prog_clk_2_S_in ( p2409 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_8528 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_8529 ) , .prog_clk_3_S_in ( prog_clk_3_wires[8] ) , .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_8530 ) , .prog_clk_3_N_out ( prog_clk_3_wires[9] ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8531 ) , .clk_2_N_in ( p2223 ) , - .clk_2_S_in ( p2536 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8532 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8531 ) , .clk_2_N_in ( p2217 ) , + .clk_2_S_in ( p2469 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8532 ) , .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8533 ) , .clk_3_S_in ( clk_3_wires[8] ) , .clk_3_N_in ( SYNOPSYS_UNCONNECTED_8534 ) , @@ -127435,14 +131957,14 @@ cby_1__1_ cby_4__8_ ( .prog_clk_0_W_in ( prog_clk_0_wires[161] ) , .prog_clk_0_S_out ( prog_clk_0_wires[162] ) , .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_8546 ) , - .prog_clk_2_N_in ( p538 ) , .prog_clk_2_S_in ( p1979 ) , + .prog_clk_2_N_in ( p1256 ) , .prog_clk_2_S_in ( p1664 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_8547 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_8548 ) , .prog_clk_3_S_in ( prog_clk_3_wires[12] ) , .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_8549 ) , .prog_clk_3_N_out ( prog_clk_3_wires[13] ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8550 ) , .clk_2_N_in ( p538 ) , - .clk_2_S_in ( p2754 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8551 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8550 ) , .clk_2_N_in ( p1256 ) , + .clk_2_S_in ( p1727 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8551 ) , .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8552 ) , .clk_3_S_in ( clk_3_wires[12] ) , .clk_3_N_in ( SYNOPSYS_UNCONNECTED_8553 ) , @@ -127489,14 +132011,14 @@ cby_1__1_ cby_4__9_ ( .prog_clk_0_W_in ( prog_clk_0_wires[164] ) , .prog_clk_0_S_out ( prog_clk_0_wires[165] ) , .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_8565 ) , - .prog_clk_2_N_in ( p1904 ) , .prog_clk_2_S_in ( p1696 ) , + .prog_clk_2_N_in ( p1436 ) , .prog_clk_2_S_in ( p109 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_8566 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_8567 ) , .prog_clk_3_S_in ( prog_clk_3_wires[18] ) , .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_8568 ) , .prog_clk_3_N_out ( prog_clk_3_wires[19] ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8569 ) , .clk_2_N_in ( p1904 ) , - .clk_2_S_in ( p595 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8570 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8569 ) , .clk_2_N_in ( p1637 ) , + .clk_2_S_in ( p692 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8570 ) , .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8571 ) , .clk_3_S_in ( clk_3_wires[18] ) , .clk_3_N_in ( SYNOPSYS_UNCONNECTED_8572 ) , @@ -127543,14 +132065,14 @@ cby_1__1_ cby_4__10_ ( .prog_clk_0_W_in ( prog_clk_0_wires[167] ) , .prog_clk_0_S_out ( prog_clk_0_wires[168] ) , .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_8584 ) , - .prog_clk_2_N_in ( p1179 ) , .prog_clk_2_S_in ( p2306 ) , + .prog_clk_2_N_in ( p1111 ) , .prog_clk_2_S_in ( p2413 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_8585 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_8586 ) , .prog_clk_3_S_in ( prog_clk_3_wires[22] ) , .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_8587 ) , .prog_clk_3_N_out ( prog_clk_3_wires[23] ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8588 ) , .clk_2_N_in ( p1179 ) , - .clk_2_S_in ( p2545 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8589 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8588 ) , .clk_2_N_in ( p1111 ) , + .clk_2_S_in ( p2448 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8589 ) , .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8590 ) , .clk_3_S_in ( clk_3_wires[22] ) , .clk_3_N_in ( SYNOPSYS_UNCONNECTED_8591 ) , @@ -127597,15 +132119,15 @@ cby_1__1_ cby_4__11_ ( .prog_clk_0_W_in ( prog_clk_0_wires[170] ) , .prog_clk_0_S_out ( prog_clk_0_wires[171] ) , .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_8603 ) , - .prog_clk_2_N_in ( p2503 ) , .prog_clk_2_S_in ( p931 ) , + .prog_clk_2_N_in ( p2539 ) , .prog_clk_2_S_in ( p591 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_8604 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_8605 ) , - .prog_clk_3_S_in ( p1772 ) , .prog_clk_3_N_in ( p2293 ) , + .prog_clk_3_S_in ( p2792 ) , .prog_clk_3_N_in ( p2399 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_8606 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8607 ) , .clk_2_N_in ( p3079 ) , - .clk_2_S_in ( p2280 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8608 ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8609 ) , .clk_3_S_in ( p2498 ) , - .clk_3_N_in ( p3031 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8610 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8607 ) , .clk_2_N_in ( p1892 ) , + .clk_2_S_in ( p3302 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8608 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8609 ) , .clk_3_S_in ( p3350 ) , + .clk_3_N_in ( p1776 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8610 ) , .clk_3_S_out ( SYNOPSYS_UNCONNECTED_8611 ) ) ; cby_1__1_ cby_4__12_ ( .pReset ( { SYNOPSYS_UNCONNECTED_8612 } ) , @@ -127647,16 +132169,16 @@ cby_1__1_ cby_4__12_ ( .Reset_E_out ( SYNOPSYS_UNCONNECTED_8621 ) , .prog_clk_0_W_in ( prog_clk_0_wires[173] ) , .prog_clk_0_S_out ( prog_clk_0_wires[174] ) , - .prog_clk_0_N_out ( prog_clk_0_wires[176] ) , .prog_clk_2_N_in ( p1762 ) , - .prog_clk_2_S_in ( p622 ) , + .prog_clk_0_N_out ( prog_clk_0_wires[176] ) , .prog_clk_2_N_in ( p1862 ) , + .prog_clk_2_S_in ( p133 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_8622 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_8623 ) , - .prog_clk_3_S_in ( p2404 ) , .prog_clk_3_N_in ( p1754 ) , + .prog_clk_3_S_in ( p1868 ) , .prog_clk_3_N_in ( p1788 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_8624 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8625 ) , .clk_2_N_in ( p2396 ) , - .clk_2_S_in ( p2326 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8626 ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8627 ) , .clk_3_S_in ( p2415 ) , - .clk_3_N_in ( p2303 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8628 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8625 ) , .clk_2_N_in ( p2972 ) , + .clk_2_S_in ( p2468 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8626 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8627 ) , .clk_3_S_in ( p2600 ) , + .clk_3_N_in ( p2898 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8628 ) , .clk_3_S_out ( SYNOPSYS_UNCONNECTED_8629 ) ) ; cby_1__1_ cby_5__1_ ( .pReset ( { SYNOPSYS_UNCONNECTED_8630 } ) , @@ -127699,15 +132221,15 @@ cby_1__1_ cby_5__1_ ( .prog_clk_0_W_in ( prog_clk_0_wires[178] ) , .prog_clk_0_S_out ( prog_clk_0_wires[179] ) , .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_8640 ) , - .prog_clk_2_N_in ( p1869 ) , .prog_clk_2_S_in ( p41 ) , + .prog_clk_2_N_in ( p1901 ) , .prog_clk_2_S_in ( p17 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_8641 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_8642 ) , - .prog_clk_3_S_in ( p2976 ) , .prog_clk_3_N_in ( p1669 ) , + .prog_clk_3_S_in ( p2830 ) , .prog_clk_3_N_in ( p1666 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_8643 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8644 ) , .clk_2_N_in ( p2425 ) , - .clk_2_S_in ( p2881 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8645 ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8646 ) , .clk_3_S_in ( p2261 ) , - .clk_3_N_in ( p2299 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8647 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8644 ) , .clk_2_N_in ( p2242 ) , + .clk_2_S_in ( p2679 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8645 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8646 ) , .clk_3_S_in ( p2298 ) , + .clk_3_N_in ( p2146 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8647 ) , .clk_3_S_out ( SYNOPSYS_UNCONNECTED_8648 ) ) ; cby_1__1_ cby_5__2_ ( .pReset ( { SYNOPSYS_UNCONNECTED_8649 } ) , @@ -127754,14 +132276,14 @@ cby_1__1_ cby_5__2_ ( .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_8660 ) , .prog_clk_2_S_out ( prog_clk_2_wires[32] ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_8661 ) , - .prog_clk_3_S_in ( p2177 ) , .prog_clk_3_N_in ( p1115 ) , + .prog_clk_3_S_in ( p1917 ) , .prog_clk_3_N_in ( p399 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_8662 ) , .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8663 ) , .clk_2_N_in ( clk_2_wires[31] ) , .clk_2_S_in ( SYNOPSYS_UNCONNECTED_8664 ) , .clk_2_S_out ( clk_2_wires[32] ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8665 ) , .clk_3_S_in ( p2177 ) , - .clk_3_N_in ( p644 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8666 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8665 ) , .clk_3_S_in ( p1917 ) , + .clk_3_N_in ( p611 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8666 ) , .clk_3_S_out ( SYNOPSYS_UNCONNECTED_8667 ) ) ; cby_1__1_ cby_5__3_ ( .pReset ( { SYNOPSYS_UNCONNECTED_8668 } ) , @@ -127804,15 +132326,15 @@ cby_1__1_ cby_5__3_ ( .prog_clk_0_W_in ( prog_clk_0_wires[184] ) , .prog_clk_0_S_out ( prog_clk_0_wires[185] ) , .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_8678 ) , - .prog_clk_2_N_in ( p1863 ) , .prog_clk_2_S_in ( p400 ) , + .prog_clk_2_N_in ( p2286 ) , .prog_clk_2_S_in ( p496 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_8679 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_8680 ) , - .prog_clk_3_S_in ( p2852 ) , .prog_clk_3_N_in ( p1635 ) , + .prog_clk_3_S_in ( p1406 ) , .prog_clk_3_N_in ( p2159 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_8681 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8682 ) , .clk_2_N_in ( p2801 ) , - .clk_2_S_in ( p3112 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8683 ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8684 ) , .clk_3_S_in ( p3179 ) , - .clk_3_N_in ( p2722 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8685 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8682 ) , .clk_2_N_in ( p2769 ) , + .clk_2_S_in ( p1741 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8683 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8684 ) , .clk_3_S_in ( p1890 ) , + .clk_3_N_in ( p2687 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8685 ) , .clk_3_S_out ( SYNOPSYS_UNCONNECTED_8686 ) ) ; cby_1__1_ cby_5__4_ ( .pReset ( { SYNOPSYS_UNCONNECTED_8687 } ) , @@ -127859,14 +132381,14 @@ cby_1__1_ cby_5__4_ ( .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_8698 ) , .prog_clk_2_S_out ( prog_clk_2_wires[45] ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_8699 ) , - .prog_clk_3_S_in ( p1507 ) , .prog_clk_3_N_in ( p16 ) , + .prog_clk_3_S_in ( p1623 ) , .prog_clk_3_N_in ( p484 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_8700 ) , .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8701 ) , .clk_2_N_in ( clk_2_wires[44] ) , .clk_2_S_in ( SYNOPSYS_UNCONNECTED_8702 ) , .clk_2_S_out ( clk_2_wires[45] ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8703 ) , .clk_3_S_in ( p1507 ) , - .clk_3_N_in ( p642 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8704 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8703 ) , .clk_3_S_in ( p1623 ) , + .clk_3_N_in ( p822 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8704 ) , .clk_3_S_out ( SYNOPSYS_UNCONNECTED_8705 ) ) ; cby_1__1_ cby_5__5_ ( .pReset ( { SYNOPSYS_UNCONNECTED_8706 } ) , @@ -127912,15 +132434,15 @@ cby_1__1_ cby_5__5_ ( .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_8717 ) , .prog_clk_2_S_in ( prog_clk_2_wires[42] ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_8718 ) , - .prog_clk_2_N_out ( prog_clk_2_wires[43] ) , .prog_clk_3_S_in ( p2661 ) , - .prog_clk_3_N_in ( p582 ) , + .prog_clk_2_N_out ( prog_clk_2_wires[43] ) , .prog_clk_3_S_in ( p1888 ) , + .prog_clk_3_N_in ( p1180 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_8719 ) , .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8720 ) , .clk_2_N_in ( SYNOPSYS_UNCONNECTED_8721 ) , .clk_2_S_in ( clk_2_wires[42] ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8722 ) , - .clk_2_N_out ( clk_2_wires[43] ) , .clk_3_S_in ( p2661 ) , - .clk_3_N_in ( p1003 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8723 ) , + .clk_2_N_out ( clk_2_wires[43] ) , .clk_3_S_in ( p1888 ) , + .clk_3_N_in ( p488 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8723 ) , .clk_3_S_out ( SYNOPSYS_UNCONNECTED_8724 ) ) ; cby_1__1_ cby_5__6_ ( .pReset ( { SYNOPSYS_UNCONNECTED_8725 } ) , @@ -127963,15 +132485,15 @@ cby_1__1_ cby_5__6_ ( .prog_clk_0_W_in ( prog_clk_0_wires[193] ) , .prog_clk_0_S_out ( prog_clk_0_wires[194] ) , .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_8735 ) , - .prog_clk_2_N_in ( p2457 ) , .prog_clk_2_S_in ( p950 ) , + .prog_clk_2_N_in ( p2808 ) , .prog_clk_2_S_in ( p523 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_8736 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_8737 ) , - .prog_clk_3_S_in ( p2832 ) , .prog_clk_3_N_in ( p2341 ) , + .prog_clk_3_S_in ( p3107 ) , .prog_clk_3_N_in ( p2671 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_8738 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8739 ) , .clk_2_N_in ( p3191 ) , - .clk_2_S_in ( p3040 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8740 ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8741 ) , .clk_3_S_in ( p3081 ) , - .clk_3_N_in ( p3124 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8742 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8739 ) , .clk_2_N_in ( p2807 ) , + .clk_2_S_in ( p3046 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8740 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8741 ) , .clk_3_S_in ( p2541 ) , + .clk_3_N_in ( p2732 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8742 ) , .clk_3_S_out ( SYNOPSYS_UNCONNECTED_8743 ) ) ; cby_1__1_ cby_5__7_ ( .pReset ( { SYNOPSYS_UNCONNECTED_8744 } ) , @@ -128014,15 +132536,15 @@ cby_1__1_ cby_5__7_ ( .prog_clk_0_W_in ( prog_clk_0_wires[196] ) , .prog_clk_0_S_out ( prog_clk_0_wires[197] ) , .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_8754 ) , - .prog_clk_2_N_in ( p2799 ) , .prog_clk_2_S_in ( p275 ) , + .prog_clk_2_N_in ( p1468 ) , .prog_clk_2_S_in ( p2376 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_8755 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_8756 ) , - .prog_clk_3_S_in ( p2098 ) , .prog_clk_3_N_in ( p2729 ) , + .prog_clk_3_S_in ( p2593 ) , .prog_clk_3_N_in ( p373 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_8757 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8758 ) , .clk_2_N_in ( p3197 ) , - .clk_2_S_in ( p2756 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8759 ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8760 ) , .clk_3_S_in ( p2837 ) , - .clk_3_N_in ( p3141 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8761 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8758 ) , .clk_2_N_in ( p2343 ) , + .clk_2_S_in ( p2460 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8759 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8760 ) , .clk_3_S_in ( p2564 ) , + .clk_3_N_in ( p2085 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8761 ) , .clk_3_S_out ( SYNOPSYS_UNCONNECTED_8762 ) ) ; cby_1__1_ cby_5__8_ ( .pReset ( { SYNOPSYS_UNCONNECTED_8763 } ) , @@ -128069,14 +132591,14 @@ cby_1__1_ cby_5__8_ ( .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_8774 ) , .prog_clk_2_S_out ( prog_clk_2_wires[58] ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_8775 ) , - .prog_clk_3_S_in ( p1889 ) , .prog_clk_3_N_in ( p721 ) , + .prog_clk_3_S_in ( p1977 ) , .prog_clk_3_N_in ( p25 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_8776 ) , .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8777 ) , .clk_2_N_in ( clk_2_wires[57] ) , .clk_2_S_in ( SYNOPSYS_UNCONNECTED_8778 ) , .clk_2_S_out ( clk_2_wires[58] ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8779 ) , .clk_3_S_in ( p1889 ) , - .clk_3_N_in ( p759 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8780 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8779 ) , .clk_3_S_in ( p1977 ) , + .clk_3_N_in ( p613 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8780 ) , .clk_3_S_out ( SYNOPSYS_UNCONNECTED_8781 ) ) ; cby_1__1_ cby_5__9_ ( .pReset ( { SYNOPSYS_UNCONNECTED_8782 } ) , @@ -128122,15 +132644,15 @@ cby_1__1_ cby_5__9_ ( .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_8793 ) , .prog_clk_2_S_in ( prog_clk_2_wires[55] ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_8794 ) , - .prog_clk_2_N_out ( prog_clk_2_wires[56] ) , .prog_clk_3_S_in ( p1753 ) , + .prog_clk_2_N_out ( prog_clk_2_wires[56] ) , .prog_clk_3_S_in ( p1951 ) , .prog_clk_3_N_in ( p21 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_8795 ) , .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8796 ) , .clk_2_N_in ( SYNOPSYS_UNCONNECTED_8797 ) , .clk_2_S_in ( clk_2_wires[55] ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8798 ) , - .clk_2_N_out ( clk_2_wires[56] ) , .clk_3_S_in ( p1753 ) , - .clk_3_N_in ( p1147 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8799 ) , + .clk_2_N_out ( clk_2_wires[56] ) , .clk_3_S_in ( p1822 ) , + .clk_3_N_in ( p926 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8799 ) , .clk_3_S_out ( SYNOPSYS_UNCONNECTED_8800 ) ) ; cby_1__1_ cby_5__10_ ( .pReset ( { SYNOPSYS_UNCONNECTED_8801 } ) , @@ -128173,15 +132695,15 @@ cby_1__1_ cby_5__10_ ( .prog_clk_0_W_in ( prog_clk_0_wires[205] ) , .prog_clk_0_S_out ( prog_clk_0_wires[206] ) , .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_8811 ) , - .prog_clk_2_N_in ( p2927 ) , .prog_clk_2_S_in ( p65 ) , + .prog_clk_2_N_in ( p2255 ) , .prog_clk_2_S_in ( p695 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_8812 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_8813 ) , - .prog_clk_3_S_in ( p2655 ) , .prog_clk_3_N_in ( p2882 ) , + .prog_clk_3_S_in ( p2315 ) , .prog_clk_3_N_in ( p2054 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_8814 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8815 ) , .clk_2_N_in ( p3276 ) , - .clk_2_S_in ( p2588 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8816 ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8817 ) , .clk_3_S_in ( p2233 ) , - .clk_3_N_in ( p3220 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8818 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8815 ) , .clk_2_N_in ( p2540 ) , + .clk_2_S_in ( p3088 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8816 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8817 ) , .clk_3_S_in ( p3123 ) , + .clk_3_N_in ( p2446 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8818 ) , .clk_3_S_out ( SYNOPSYS_UNCONNECTED_8819 ) ) ; cby_1__1_ cby_5__11_ ( .pReset ( { SYNOPSYS_UNCONNECTED_8820 } ) , @@ -128227,15 +132749,15 @@ cby_1__1_ cby_5__11_ ( .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_8831 ) , .prog_clk_2_S_in ( prog_clk_2_wires[66] ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_8832 ) , - .prog_clk_2_N_out ( prog_clk_2_wires[67] ) , .prog_clk_3_S_in ( p1554 ) , - .prog_clk_3_N_in ( p59 ) , + .prog_clk_2_N_out ( prog_clk_2_wires[67] ) , .prog_clk_3_S_in ( p1912 ) , + .prog_clk_3_N_in ( p1018 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_8833 ) , .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8834 ) , .clk_2_N_in ( SYNOPSYS_UNCONNECTED_8835 ) , .clk_2_S_in ( clk_2_wires[66] ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8836 ) , - .clk_2_N_out ( clk_2_wires[67] ) , .clk_3_S_in ( p1554 ) , - .clk_3_N_in ( p696 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8837 ) , + .clk_2_N_out ( clk_2_wires[67] ) , .clk_3_S_in ( p1912 ) , + .clk_3_N_in ( p183 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8837 ) , .clk_3_S_out ( SYNOPSYS_UNCONNECTED_8838 ) ) ; cby_1__1_ cby_5__12_ ( .pReset ( { SYNOPSYS_UNCONNECTED_8839 } ) , @@ -128277,16 +132799,16 @@ cby_1__1_ cby_5__12_ ( .Reset_E_out ( SYNOPSYS_UNCONNECTED_8848 ) , .prog_clk_0_W_in ( prog_clk_0_wires[211] ) , .prog_clk_0_S_out ( prog_clk_0_wires[212] ) , - .prog_clk_0_N_out ( prog_clk_0_wires[214] ) , .prog_clk_2_N_in ( p2794 ) , - .prog_clk_2_S_in ( p694 ) , + .prog_clk_0_N_out ( prog_clk_0_wires[214] ) , .prog_clk_2_N_in ( p1537 ) , + .prog_clk_2_S_in ( p487 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_8849 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_8850 ) , - .prog_clk_3_S_in ( p2929 ) , .prog_clk_3_N_in ( p2734 ) , + .prog_clk_3_S_in ( p1911 ) , .prog_clk_3_N_in ( p1075 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_8851 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8852 ) , .clk_2_N_in ( p2456 ) , - .clk_2_S_in ( p3346 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8853 ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8854 ) , .clk_3_S_in ( p3368 ) , - .clk_3_N_in ( p2295 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8855 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8852 ) , .clk_2_N_in ( p2640 ) , + .clk_2_S_in ( p2450 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8853 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8854 ) , .clk_3_S_in ( p2572 ) , + .clk_3_N_in ( p2436 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8855 ) , .clk_3_S_out ( SYNOPSYS_UNCONNECTED_8856 ) ) ; cby_1__1_ cby_6__1_ ( .pReset ( { SYNOPSYS_UNCONNECTED_8857 } ) , @@ -128325,14 +132847,14 @@ cby_1__1_ cby_6__1_ ( .prog_clk_0_W_in ( prog_clk_0_wires[216] ) , .prog_clk_0_S_out ( prog_clk_0_wires[217] ) , .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_8862 ) , - .prog_clk_2_N_in ( p1755 ) , .prog_clk_2_S_in ( p334 ) , + .prog_clk_2_N_in ( p1572 ) , .prog_clk_2_S_in ( p889 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_8863 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_8864 ) , .prog_clk_3_S_in ( prog_clk_3_wires[90] ) , .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_8865 ) , .prog_clk_3_N_out ( prog_clk_3_wires[89] ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8866 ) , .clk_2_N_in ( p1755 ) , - .clk_2_S_in ( p1686 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8867 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8866 ) , .clk_2_N_in ( p1572 ) , + .clk_2_S_in ( p378 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8867 ) , .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8868 ) , .clk_3_S_in ( clk_3_wires[90] ) , .clk_3_N_in ( SYNOPSYS_UNCONNECTED_8869 ) , @@ -128375,14 +132897,14 @@ cby_1__1_ cby_6__2_ ( .prog_clk_0_W_in ( prog_clk_0_wires[219] ) , .prog_clk_0_S_out ( prog_clk_0_wires[220] ) , .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_8876 ) , - .prog_clk_2_N_in ( p1957 ) , .prog_clk_2_S_in ( p739 ) , + .prog_clk_2_N_in ( p1528 ) , .prog_clk_2_S_in ( p438 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_8877 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_8878 ) , .prog_clk_3_S_in ( prog_clk_3_wires[92] ) , .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_8879 ) , .prog_clk_3_N_out ( prog_clk_3_wires[91] ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8880 ) , .clk_2_N_in ( p1953 ) , - .clk_2_S_in ( p392 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8881 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8880 ) , .clk_2_N_in ( p1528 ) , + .clk_2_S_in ( p1020 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8881 ) , .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8882 ) , .clk_3_S_in ( clk_3_wires[92] ) , .clk_3_N_in ( SYNOPSYS_UNCONNECTED_8883 ) , @@ -128425,14 +132947,14 @@ cby_1__1_ cby_6__3_ ( .prog_clk_0_W_in ( prog_clk_0_wires[222] ) , .prog_clk_0_S_out ( prog_clk_0_wires[223] ) , .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_8890 ) , - .prog_clk_2_N_in ( p1936 ) , .prog_clk_2_S_in ( p1744 ) , + .prog_clk_2_N_in ( p1574 ) , .prog_clk_2_S_in ( p2420 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_8891 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_8892 ) , .prog_clk_3_S_in ( prog_clk_3_wires[94] ) , .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_8893 ) , .prog_clk_3_N_out ( prog_clk_3_wires[93] ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8894 ) , .clk_2_N_in ( p1936 ) , - .clk_2_S_in ( p2532 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8895 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8894 ) , .clk_2_N_in ( p1574 ) , + .clk_2_S_in ( p2402 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8895 ) , .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8896 ) , .clk_3_S_in ( clk_3_wires[94] ) , .clk_3_N_in ( SYNOPSYS_UNCONNECTED_8897 ) , @@ -128475,14 +132997,14 @@ cby_1__1_ cby_6__4_ ( .prog_clk_0_W_in ( prog_clk_0_wires[225] ) , .prog_clk_0_S_out ( prog_clk_0_wires[226] ) , .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_8904 ) , - .prog_clk_2_N_in ( p1818 ) , .prog_clk_2_S_in ( p1639 ) , + .prog_clk_2_N_in ( p1947 ) , .prog_clk_2_S_in ( p1805 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_8905 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_8906 ) , .prog_clk_3_S_in ( prog_clk_3_wires[96] ) , .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_8907 ) , .prog_clk_3_N_out ( prog_clk_3_wires[95] ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8908 ) , .clk_2_N_in ( p1818 ) , - .clk_2_S_in ( p1733 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8909 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8908 ) , .clk_2_N_in ( p2008 ) , + .clk_2_S_in ( p3052 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8909 ) , .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8910 ) , .clk_3_S_in ( clk_3_wires[96] ) , .clk_3_N_in ( SYNOPSYS_UNCONNECTED_8911 ) , @@ -128526,14 +133048,14 @@ cby_1__1_ cby_6__5_ ( .prog_clk_0_W_in ( prog_clk_0_wires[228] ) , .prog_clk_0_S_out ( prog_clk_0_wires[229] ) , .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_8918 ) , - .prog_clk_2_N_in ( p1916 ) , .prog_clk_2_S_in ( p2352 ) , + .prog_clk_2_N_in ( p1297 ) , .prog_clk_2_S_in ( p169 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_8919 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_8920 ) , .prog_clk_3_S_in ( prog_clk_3_wires[98] ) , .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_8921 ) , .prog_clk_3_N_out ( prog_clk_3_wires[97] ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8922 ) , .clk_2_N_in ( p1916 ) , - .clk_2_S_in ( p2907 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8923 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8922 ) , .clk_2_N_in ( p1297 ) , + .clk_2_S_in ( p2094 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8923 ) , .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8924 ) , .clk_3_S_in ( clk_3_wires[98] ) , .clk_3_N_in ( SYNOPSYS_UNCONNECTED_8925 ) , @@ -128577,14 +133099,14 @@ cby_1__1_ cby_6__6_ ( .prog_clk_0_W_in ( prog_clk_0_wires[231] ) , .prog_clk_0_S_out ( prog_clk_0_wires[232] ) , .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_8932 ) , - .prog_clk_2_N_in ( p2141 ) , .prog_clk_2_S_in ( p2597 ) , + .prog_clk_2_N_in ( p1419 ) , .prog_clk_2_S_in ( p1798 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_8933 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_8934 ) , .prog_clk_3_S_in ( prog_clk_3_wires[100] ) , .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_8935 ) , .prog_clk_3_N_out ( prog_clk_3_wires[99] ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8936 ) , .clk_2_N_in ( p2205 ) , - .clk_2_S_in ( p2752 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8937 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8936 ) , .clk_2_N_in ( p1419 ) , + .clk_2_S_in ( p1713 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8937 ) , .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8938 ) , .clk_3_S_in ( clk_3_wires[100] ) , .clk_3_N_in ( SYNOPSYS_UNCONNECTED_8939 ) , @@ -128628,15 +133150,15 @@ cby_1__1_ cby_6__7_ ( .prog_clk_0_W_in ( prog_clk_0_wires[234] ) , .prog_clk_0_S_out ( prog_clk_0_wires[235] ) , .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_8946 ) , - .prog_clk_2_N_in ( p2448 ) , .prog_clk_2_S_in ( p1728 ) , + .prog_clk_2_N_in ( p1334 ) , .prog_clk_2_S_in ( p1694 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_8947 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_8948 ) , - .prog_clk_3_S_in ( p1435 ) , .prog_clk_3_N_in ( p2350 ) , + .prog_clk_3_S_in ( p2746 ) , .prog_clk_3_N_in ( p737 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_8949 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8950 ) , .clk_2_N_in ( p2459 ) , - .clk_2_S_in ( p2884 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8951 ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8952 ) , .clk_3_S_in ( p2977 ) , - .clk_3_N_in ( p2327 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8953 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8950 ) , .clk_2_N_in ( p3332 ) , + .clk_2_S_in ( p2888 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8951 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8952 ) , .clk_3_S_in ( p2370 ) , + .clk_3_N_in ( p3287 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8953 ) , .clk_3_S_out ( SYNOPSYS_UNCONNECTED_8954 ) ) ; cby_1__1_ cby_6__8_ ( .pReset ( { SYNOPSYS_UNCONNECTED_8955 } ) , @@ -128676,15 +133198,15 @@ cby_1__1_ cby_6__8_ ( .prog_clk_0_W_in ( prog_clk_0_wires[237] ) , .prog_clk_0_S_out ( prog_clk_0_wires[238] ) , .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_8960 ) , - .prog_clk_2_N_in ( p1478 ) , .prog_clk_2_S_in ( p737 ) , + .prog_clk_2_N_in ( p2233 ) , .prog_clk_2_S_in ( p735 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_8961 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_8962 ) , - .prog_clk_3_S_in ( p2615 ) , .prog_clk_3_N_in ( p645 ) , + .prog_clk_3_S_in ( p3010 ) , .prog_clk_3_N_in ( p2157 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_8963 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8964 ) , .clk_2_N_in ( p3189 ) , - .clk_2_S_in ( p2768 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8965 ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8966 ) , .clk_3_S_in ( p2851 ) , - .clk_3_N_in ( p3117 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8967 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8964 ) , .clk_2_N_in ( p3104 ) , + .clk_2_S_in ( p2887 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8965 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8966 ) , .clk_3_S_in ( p1879 ) , + .clk_3_N_in ( p3042 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8967 ) , .clk_3_S_out ( SYNOPSYS_UNCONNECTED_8968 ) ) ; cby_1__1_ cby_6__9_ ( .pReset ( { SYNOPSYS_UNCONNECTED_8969 } ) , @@ -128724,15 +133246,15 @@ cby_1__1_ cby_6__9_ ( .prog_clk_0_W_in ( prog_clk_0_wires[240] ) , .prog_clk_0_S_out ( prog_clk_0_wires[241] ) , .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_8974 ) , - .prog_clk_2_N_in ( p2489 ) , .prog_clk_2_S_in ( p357 ) , + .prog_clk_2_N_in ( p2560 ) , .prog_clk_2_S_in ( p54 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_8975 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_8976 ) , - .prog_clk_3_S_in ( p2958 ) , .prog_clk_3_N_in ( p2294 ) , + .prog_clk_3_S_in ( p2509 ) , .prog_clk_3_N_in ( p2427 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_8977 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8978 ) , .clk_2_N_in ( p2639 ) , - .clk_2_S_in ( p2886 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8979 ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8980 ) , .clk_3_S_in ( p2857 ) , - .clk_3_N_in ( p2574 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8981 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8978 ) , .clk_2_N_in ( p2337 ) , + .clk_2_S_in ( p3090 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8979 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8980 ) , .clk_3_S_in ( p3156 ) , + .clk_3_N_in ( p2098 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8981 ) , .clk_3_S_out ( SYNOPSYS_UNCONNECTED_8982 ) ) ; cby_1__1_ cby_6__10_ ( .pReset ( { SYNOPSYS_UNCONNECTED_8983 } ) , @@ -128772,15 +133294,15 @@ cby_1__1_ cby_6__10_ ( .prog_clk_0_W_in ( prog_clk_0_wires[243] ) , .prog_clk_0_S_out ( prog_clk_0_wires[244] ) , .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_8988 ) , - .prog_clk_2_N_in ( p2264 ) , .prog_clk_2_S_in ( p226 ) , + .prog_clk_2_N_in ( p1943 ) , .prog_clk_2_S_in ( p230 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_8989 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_8990 ) , - .prog_clk_3_S_in ( p2624 ) , .prog_clk_3_N_in ( p2084 ) , + .prog_clk_3_S_in ( p2542 ) , .prog_clk_3_N_in ( p1796 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_8991 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8992 ) , .clk_2_N_in ( p3196 ) , - .clk_2_S_in ( p3005 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8993 ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8994 ) , .clk_3_S_in ( p3086 ) , - .clk_3_N_in ( p3127 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8995 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8992 ) , .clk_2_N_in ( p3258 ) , + .clk_2_S_in ( p2465 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8993 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8994 ) , .clk_3_S_in ( p2291 ) , + .clk_3_N_in ( p3194 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8995 ) , .clk_3_S_out ( SYNOPSYS_UNCONNECTED_8996 ) ) ; cby_1__1_ cby_6__11_ ( .pReset ( { SYNOPSYS_UNCONNECTED_8997 } ) , @@ -128820,15 +133342,15 @@ cby_1__1_ cby_6__11_ ( .prog_clk_0_W_in ( prog_clk_0_wires[246] ) , .prog_clk_0_S_out ( prog_clk_0_wires[247] ) , .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_9002 ) , - .prog_clk_2_N_in ( p2458 ) , .prog_clk_2_S_in ( p382 ) , + .prog_clk_2_N_in ( p1894 ) , .prog_clk_2_S_in ( p460 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_9003 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_9004 ) , - .prog_clk_3_S_in ( p3102 ) , .prog_clk_3_N_in ( p2305 ) , + .prog_clk_3_S_in ( p2012 ) , .prog_clk_3_N_in ( p1711 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_9005 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9006 ) , .clk_2_N_in ( p3369 ) , - .clk_2_S_in ( p3039 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9007 ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9008 ) , .clk_3_S_in ( p1782 ) , - .clk_3_N_in ( p3350 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9009 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9006 ) , .clk_2_N_in ( p2374 ) , + .clk_2_S_in ( p2424 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9007 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9008 ) , .clk_3_S_in ( p2531 ) , + .clk_3_N_in ( p2115 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9009 ) , .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9010 ) ) ; cby_1__1_ cby_6__12_ ( .pReset ( { SYNOPSYS_UNCONNECTED_9011 } ) , @@ -128867,16 +133389,16 @@ cby_1__1_ cby_6__12_ ( .Reset_W_out ( ResetWires[275] ) , .Reset_E_out ( ResetWires[277] ) , .prog_clk_0_W_in ( prog_clk_0_wires[249] ) , .prog_clk_0_S_out ( prog_clk_0_wires[250] ) , - .prog_clk_0_N_out ( prog_clk_0_wires[252] ) , .prog_clk_2_N_in ( p2203 ) , - .prog_clk_2_S_in ( p999 ) , + .prog_clk_0_N_out ( prog_clk_0_wires[252] ) , .prog_clk_2_N_in ( p2281 ) , + .prog_clk_2_S_in ( p287 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_9018 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_9019 ) , - .prog_clk_3_S_in ( p3091 ) , .prog_clk_3_N_in ( p2041 ) , + .prog_clk_3_S_in ( p2371 ) , .prog_clk_3_N_in ( p2165 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_9020 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9021 ) , .clk_2_N_in ( p3257 ) , - .clk_2_S_in ( p3225 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9022 ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9023 ) , .clk_3_S_in ( p3269 ) , - .clk_3_N_in ( p3206 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9024 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9021 ) , .clk_2_N_in ( p2978 ) , + .clk_2_S_in ( p3078 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9022 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9023 ) , .clk_3_S_in ( p3110 ) , + .clk_3_N_in ( p2886 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9024 ) , .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9025 ) ) ; cby_1__1_ cby_7__1_ ( .pReset ( { SYNOPSYS_UNCONNECTED_9026 } ) , @@ -128918,15 +133440,15 @@ cby_1__1_ cby_7__1_ ( .prog_clk_0_W_in ( prog_clk_0_wires[254] ) , .prog_clk_0_S_out ( prog_clk_0_wires[255] ) , .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_9036 ) , - .prog_clk_2_N_in ( p2249 ) , .prog_clk_2_S_in ( p49 ) , + .prog_clk_2_N_in ( p1906 ) , .prog_clk_2_S_in ( p646 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_9037 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_9038 ) , - .prog_clk_3_S_in ( p2784 ) , .prog_clk_3_N_in ( p2002 ) , + .prog_clk_3_S_in ( p2811 ) , .prog_clk_3_N_in ( p1722 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_9039 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9040 ) , .clk_2_N_in ( p3175 ) , - .clk_2_S_in ( p2727 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9041 ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9042 ) , .clk_3_S_in ( p2806 ) , - .clk_3_N_in ( p3133 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9043 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9040 ) , .clk_2_N_in ( p1558 ) , + .clk_2_S_in ( p2675 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9041 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9042 ) , .clk_3_S_in ( p2557 ) , + .clk_3_N_in ( p1013 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9043 ) , .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9044 ) ) ; cby_1__1_ cby_7__2_ ( .pReset ( { SYNOPSYS_UNCONNECTED_9045 } ) , @@ -128972,14 +133494,14 @@ cby_1__1_ cby_7__2_ ( .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_9056 ) , .prog_clk_2_S_out ( prog_clk_2_wires[74] ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_9057 ) , - .prog_clk_3_S_in ( p1548 ) , .prog_clk_3_N_in ( p1097 ) , + .prog_clk_3_S_in ( p1882 ) , .prog_clk_3_N_in ( p599 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_9058 ) , .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9059 ) , .clk_2_N_in ( clk_2_wires[73] ) , .clk_2_S_in ( SYNOPSYS_UNCONNECTED_9060 ) , .clk_2_S_out ( clk_2_wires[74] ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9061 ) , .clk_3_S_in ( p1548 ) , - .clk_3_N_in ( p111 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9062 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9061 ) , .clk_3_S_in ( p1882 ) , + .clk_3_N_in ( p113 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9062 ) , .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9063 ) ) ; cby_1__1_ cby_7__3_ ( .pReset ( { SYNOPSYS_UNCONNECTED_9064 } ) , @@ -129021,15 +133543,15 @@ cby_1__1_ cby_7__3_ ( .prog_clk_0_W_in ( prog_clk_0_wires[260] ) , .prog_clk_0_S_out ( prog_clk_0_wires[261] ) , .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_9074 ) , - .prog_clk_2_N_in ( p1508 ) , .prog_clk_2_S_in ( p741 ) , + .prog_clk_2_N_in ( p1519 ) , .prog_clk_2_S_in ( p30 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_9075 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_9076 ) , - .prog_clk_3_S_in ( p3193 ) , .prog_clk_3_N_in ( p31 ) , + .prog_clk_3_S_in ( p2357 ) , .prog_clk_3_N_in ( p732 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_9077 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9078 ) , .clk_2_N_in ( p2672 ) , - .clk_2_S_in ( p3134 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9079 ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9080 ) , .clk_3_S_in ( p2792 ) , - .clk_3_N_in ( p2594 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9081 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9078 ) , .clk_2_N_in ( p2960 ) , + .clk_2_S_in ( p2694 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9079 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9080 ) , .clk_3_S_in ( p2823 ) , + .clk_3_N_in ( p2894 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9081 ) , .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9082 ) ) ; cby_1__1_ cby_7__4_ ( .pReset ( { SYNOPSYS_UNCONNECTED_9083 } ) , @@ -129075,14 +133597,14 @@ cby_1__1_ cby_7__4_ ( .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_9094 ) , .prog_clk_2_S_out ( prog_clk_2_wires[85] ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_9095 ) , - .prog_clk_3_S_in ( p1812 ) , .prog_clk_3_N_in ( p748 ) , + .prog_clk_3_S_in ( p1927 ) , .prog_clk_3_N_in ( p742 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_9096 ) , .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9097 ) , .clk_2_N_in ( clk_2_wires[84] ) , .clk_2_S_in ( SYNOPSYS_UNCONNECTED_9098 ) , .clk_2_S_out ( clk_2_wires[85] ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9099 ) , .clk_3_S_in ( p1812 ) , - .clk_3_N_in ( p362 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9100 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9099 ) , .clk_3_S_in ( p1927 ) , + .clk_3_N_in ( p1074 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9100 ) , .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9101 ) ) ; cby_1__1_ cby_7__5_ ( .pReset ( { SYNOPSYS_UNCONNECTED_9102 } ) , @@ -129127,15 +133649,15 @@ cby_1__1_ cby_7__5_ ( .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_9113 ) , .prog_clk_2_S_in ( prog_clk_2_wires[82] ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_9114 ) , - .prog_clk_2_N_out ( prog_clk_2_wires[83] ) , .prog_clk_3_S_in ( p2163 ) , - .prog_clk_3_N_in ( p1014 ) , + .prog_clk_2_N_out ( prog_clk_2_wires[83] ) , .prog_clk_3_S_in ( p2322 ) , + .prog_clk_3_N_in ( p1073 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_9115 ) , .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9116 ) , .clk_2_N_in ( SYNOPSYS_UNCONNECTED_9117 ) , .clk_2_S_in ( clk_2_wires[82] ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9118 ) , - .clk_2_N_out ( clk_2_wires[83] ) , .clk_3_S_in ( p2163 ) , - .clk_3_N_in ( p559 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9119 ) , + .clk_2_N_out ( clk_2_wires[83] ) , .clk_3_S_in ( p2322 ) , + .clk_3_N_in ( p398 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9119 ) , .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9120 ) ) ; cby_1__1_ cby_7__6_ ( .pReset ( { SYNOPSYS_UNCONNECTED_9121 } ) , @@ -129177,15 +133699,15 @@ cby_1__1_ cby_7__6_ ( .prog_clk_0_W_in ( prog_clk_0_wires[269] ) , .prog_clk_0_S_out ( prog_clk_0_wires[270] ) , .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_9131 ) , - .prog_clk_2_N_in ( p2156 ) , .prog_clk_2_S_in ( p1035 ) , + .prog_clk_2_N_in ( p2013 ) , .prog_clk_2_S_in ( p481 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_9132 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_9133 ) , - .prog_clk_3_S_in ( p2214 ) , .prog_clk_3_N_in ( p2032 ) , + .prog_clk_3_S_in ( p2552 ) , .prog_clk_3_N_in ( p1759 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_9134 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9135 ) , .clk_2_N_in ( p3167 ) , - .clk_2_S_in ( p3414 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9136 ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9137 ) , .clk_3_S_in ( p3426 ) , - .clk_3_N_in ( p3150 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9138 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9135 ) , .clk_2_N_in ( p3324 ) , + .clk_2_S_in ( p3080 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9136 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9137 ) , .clk_3_S_in ( p3116 ) , + .clk_3_N_in ( p3292 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9138 ) , .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9139 ) ) ; cby_1__1_ cby_7__7_ ( .pReset ( { SYNOPSYS_UNCONNECTED_9140 } ) , @@ -129227,15 +133749,15 @@ cby_1__1_ cby_7__7_ ( .prog_clk_0_W_in ( prog_clk_0_wires[272] ) , .prog_clk_0_S_out ( prog_clk_0_wires[273] ) , .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_9150 ) , - .prog_clk_2_N_in ( p2714 ) , .prog_clk_2_S_in ( p2290 ) , + .prog_clk_2_N_in ( p1245 ) , .prog_clk_2_S_in ( p355 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_9151 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_9152 ) , - .prog_clk_3_S_in ( p2477 ) , .prog_clk_3_N_in ( p2592 ) , + .prog_clk_3_S_in ( p3344 ) , .prog_clk_3_N_in ( p65 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_9153 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9154 ) , .clk_2_N_in ( p2670 ) , - .clk_2_S_in ( p2362 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9155 ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9156 ) , .clk_3_S_in ( p2173 ) , - .clk_3_N_in ( p2563 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9157 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9154 ) , .clk_2_N_in ( p2771 ) , + .clk_2_S_in ( p3280 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9155 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9156 ) , .clk_3_S_in ( p3253 ) , + .clk_3_N_in ( p2695 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9157 ) , .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9158 ) ) ; cby_1__1_ cby_7__8_ ( .pReset ( { SYNOPSYS_UNCONNECTED_9159 } ) , @@ -129281,14 +133803,14 @@ cby_1__1_ cby_7__8_ ( .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_9170 ) , .prog_clk_2_S_out ( prog_clk_2_wires[98] ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_9171 ) , - .prog_clk_3_S_in ( p2143 ) , .prog_clk_3_N_in ( p76 ) , + .prog_clk_3_S_in ( p1154 ) , .prog_clk_3_N_in ( p681 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_9172 ) , .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9173 ) , .clk_2_N_in ( clk_2_wires[97] ) , .clk_2_S_in ( SYNOPSYS_UNCONNECTED_9174 ) , .clk_2_S_out ( clk_2_wires[98] ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9175 ) , .clk_3_S_in ( p2143 ) , - .clk_3_N_in ( p995 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9176 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9175 ) , .clk_3_S_in ( p1154 ) , + .clk_3_N_in ( p353 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9176 ) , .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9177 ) ) ; cby_1__1_ cby_7__9_ ( .pReset ( { SYNOPSYS_UNCONNECTED_9178 } ) , @@ -129333,15 +133855,15 @@ cby_1__1_ cby_7__9_ ( .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_9189 ) , .prog_clk_2_S_in ( prog_clk_2_wires[95] ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_9190 ) , - .prog_clk_2_N_out ( prog_clk_2_wires[96] ) , .prog_clk_3_S_in ( p1536 ) , - .prog_clk_3_N_in ( p422 ) , + .prog_clk_2_N_out ( prog_clk_2_wires[96] ) , .prog_clk_3_S_in ( p1496 ) , + .prog_clk_3_N_in ( p997 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_9191 ) , .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9192 ) , .clk_2_N_in ( SYNOPSYS_UNCONNECTED_9193 ) , .clk_2_S_in ( clk_2_wires[95] ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9194 ) , - .clk_2_N_out ( clk_2_wires[96] ) , .clk_3_S_in ( p1536 ) , - .clk_3_N_in ( p951 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9195 ) , + .clk_2_N_out ( clk_2_wires[96] ) , .clk_3_S_in ( p1496 ) , + .clk_3_N_in ( p80 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9195 ) , .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9196 ) ) ; cby_1__1_ cby_7__10_ ( .pReset ( { SYNOPSYS_UNCONNECTED_9197 } ) , @@ -129383,15 +133905,15 @@ cby_1__1_ cby_7__10_ ( .prog_clk_0_W_in ( prog_clk_0_wires[281] ) , .prog_clk_0_S_out ( prog_clk_0_wires[282] ) , .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_9207 ) , - .prog_clk_2_N_in ( p2260 ) , .prog_clk_2_S_in ( p933 ) , + .prog_clk_2_N_in ( p2223 ) , .prog_clk_2_S_in ( p1055 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_9208 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_9209 ) , - .prog_clk_3_S_in ( p2844 ) , .prog_clk_3_N_in ( p2034 ) , + .prog_clk_3_S_in ( p2789 ) , .prog_clk_3_N_in ( p2154 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_9210 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9211 ) , .clk_2_N_in ( p1505 ) , - .clk_2_S_in ( p2763 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9212 ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9213 ) , .clk_3_S_in ( p2517 ) , - .clk_3_N_in ( p288 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9214 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9211 ) , .clk_2_N_in ( p2953 ) , + .clk_2_S_in ( p2696 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9212 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9213 ) , .clk_3_S_in ( p2319 ) , + .clk_3_N_in ( p2890 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9214 ) , .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9215 ) ) ; cby_1__1_ cby_7__11_ ( .pReset ( { SYNOPSYS_UNCONNECTED_9216 } ) , @@ -129436,15 +133958,15 @@ cby_1__1_ cby_7__11_ ( .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_9227 ) , .prog_clk_2_S_in ( prog_clk_2_wires[108] ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_9228 ) , - .prog_clk_2_N_out ( prog_clk_2_wires[109] ) , .prog_clk_3_S_in ( p1961 ) , - .prog_clk_3_N_in ( p755 ) , + .prog_clk_2_N_out ( prog_clk_2_wires[109] ) , .prog_clk_3_S_in ( p1405 ) , + .prog_clk_3_N_in ( p714 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_9229 ) , .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9230 ) , .clk_2_N_in ( SYNOPSYS_UNCONNECTED_9231 ) , .clk_2_S_in ( clk_2_wires[108] ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9232 ) , - .clk_2_N_out ( clk_2_wires[109] ) , .clk_3_S_in ( p1961 ) , - .clk_3_N_in ( p732 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9233 ) , + .clk_2_N_out ( clk_2_wires[109] ) , .clk_3_S_in ( p1405 ) , + .clk_3_N_in ( p234 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9233 ) , .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9234 ) ) ; cby_1__1_ cby_7__12_ ( .pReset ( { SYNOPSYS_UNCONNECTED_9235 } ) , @@ -129485,16 +134007,16 @@ cby_1__1_ cby_7__12_ ( .Reset_E_out ( ResetWires[279] ) , .prog_clk_0_W_in ( prog_clk_0_wires[287] ) , .prog_clk_0_S_out ( prog_clk_0_wires[288] ) , - .prog_clk_0_N_out ( prog_clk_0_wires[290] ) , .prog_clk_2_N_in ( p2481 ) , - .prog_clk_2_S_in ( p850 ) , + .prog_clk_0_N_out ( prog_clk_0_wires[290] ) , .prog_clk_2_N_in ( p1229 ) , + .prog_clk_2_S_in ( p650 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_9245 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_9246 ) , - .prog_clk_3_S_in ( p1831 ) , .prog_clk_3_N_in ( p2329 ) , + .prog_clk_3_S_in ( p2511 ) , .prog_clk_3_N_in ( p383 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_9247 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9248 ) , .clk_2_N_in ( p2638 ) , - .clk_2_S_in ( p3119 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9249 ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9250 ) , .clk_3_S_in ( p3158 ) , - .clk_3_N_in ( p2552 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9251 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9248 ) , .clk_2_N_in ( p2937 ) , + .clk_2_S_in ( p2422 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9249 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9250 ) , .clk_3_S_in ( p2582 ) , + .clk_3_N_in ( p2899 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9251 ) , .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9252 ) ) ; cby_1__1_ cby_8__1_ ( .pReset ( { SYNOPSYS_UNCONNECTED_9253 } ) , @@ -129536,15 +134058,15 @@ cby_1__1_ cby_8__1_ ( .prog_clk_0_W_in ( prog_clk_0_wires[292] ) , .prog_clk_0_S_out ( prog_clk_0_wires[293] ) , .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_9263 ) , - .prog_clk_2_N_in ( p1440 ) , .prog_clk_2_S_in ( p267 ) , + .prog_clk_2_N_in ( p1470 ) , .prog_clk_2_S_in ( p391 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_9264 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_9265 ) , - .prog_clk_3_S_in ( p2945 ) , .prog_clk_3_N_in ( p1125 ) , + .prog_clk_3_S_in ( p2573 ) , .prog_clk_3_N_in ( p904 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_9266 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9267 ) , .clk_2_N_in ( p2966 ) , - .clk_2_S_in ( p3147 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9268 ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9269 ) , .clk_3_S_in ( p3184 ) , - .clk_3_N_in ( p2876 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9270 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9267 ) , .clk_2_N_in ( p1618 ) , + .clk_2_S_in ( p2414 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9268 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9269 ) , .clk_3_S_in ( p2318 ) , + .clk_3_N_in ( p314 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9270 ) , .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9271 ) ) ; cby_1__1_ cby_8__2_ ( .pReset ( { SYNOPSYS_UNCONNECTED_9272 } ) , @@ -129586,15 +134108,15 @@ cby_1__1_ cby_8__2_ ( .prog_clk_0_W_in ( prog_clk_0_wires[295] ) , .prog_clk_0_S_out ( prog_clk_0_wires[296] ) , .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_9282 ) , - .prog_clk_2_N_in ( p1578 ) , .prog_clk_2_S_in ( p107 ) , + .prog_clk_2_N_in ( p2307 ) , .prog_clk_2_S_in ( p146 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_9283 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_9284 ) , - .prog_clk_3_S_in ( p3065 ) , .prog_clk_3_N_in ( p124 ) , + .prog_clk_3_S_in ( p2841 ) , .prog_clk_3_N_in ( p2056 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_9285 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9286 ) , .clk_2_N_in ( p3088 ) , - .clk_2_S_in ( p3047 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9287 ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9288 ) , .clk_3_S_in ( p3105 ) , - .clk_3_N_in ( p3010 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9289 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9286 ) , .clk_2_N_in ( p3257 ) , + .clk_2_S_in ( p3075 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9287 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9288 ) , .clk_3_S_in ( p3136 ) , + .clk_3_N_in ( p3187 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9289 ) , .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9290 ) ) ; cby_1__1_ cby_8__3_ ( .pReset ( { SYNOPSYS_UNCONNECTED_9291 } ) , @@ -129636,14 +134158,14 @@ cby_1__1_ cby_8__3_ ( .prog_clk_0_W_in ( prog_clk_0_wires[298] ) , .prog_clk_0_S_out ( prog_clk_0_wires[299] ) , .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_9301 ) , - .prog_clk_2_N_in ( p2250 ) , .prog_clk_2_S_in ( p749 ) , + .prog_clk_2_N_in ( p1859 ) , .prog_clk_2_S_in ( p420 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_9302 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_9303 ) , .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_9304 ) , .prog_clk_3_N_in ( prog_clk_3_wires[42] ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_9305 ) , - .prog_clk_3_S_out ( prog_clk_3_wires[43] ) , .clk_2_N_in ( p2250 ) , - .clk_2_S_in ( p33 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9306 ) , + .prog_clk_3_S_out ( prog_clk_3_wires[43] ) , .clk_2_N_in ( p1859 ) , + .clk_2_S_in ( p32 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9306 ) , .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9307 ) , .clk_3_S_in ( SYNOPSYS_UNCONNECTED_9308 ) , .clk_3_N_in ( clk_3_wires[42] ) , @@ -129689,14 +134211,14 @@ cby_1__1_ cby_8__4_ ( .prog_clk_0_W_in ( prog_clk_0_wires[301] ) , .prog_clk_0_S_out ( prog_clk_0_wires[302] ) , .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_9320 ) , - .prog_clk_2_N_in ( p1364 ) , .prog_clk_2_S_in ( p2063 ) , + .prog_clk_2_N_in ( p1283 ) , .prog_clk_2_S_in ( p447 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_9321 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_9322 ) , .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_9323 ) , .prog_clk_3_N_in ( prog_clk_3_wires[38] ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_9324 ) , - .prog_clk_3_S_out ( prog_clk_3_wires[39] ) , .clk_2_N_in ( p1364 ) , - .clk_2_S_in ( p2024 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9325 ) , + .prog_clk_3_S_out ( prog_clk_3_wires[39] ) , .clk_2_N_in ( p1283 ) , + .clk_2_S_in ( p2108 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9325 ) , .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9326 ) , .clk_3_S_in ( SYNOPSYS_UNCONNECTED_9327 ) , .clk_3_N_in ( clk_3_wires[38] ) , @@ -129742,14 +134264,14 @@ cby_1__1_ cby_8__5_ ( .prog_clk_0_W_in ( prog_clk_0_wires[304] ) , .prog_clk_0_S_out ( prog_clk_0_wires[305] ) , .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_9339 ) , - .prog_clk_2_N_in ( p1860 ) , .prog_clk_2_S_in ( p32 ) , + .prog_clk_2_N_in ( p2261 ) , .prog_clk_2_S_in ( p1700 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_9340 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_9341 ) , .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_9342 ) , .prog_clk_3_N_in ( prog_clk_3_wires[32] ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_9343 ) , - .prog_clk_3_S_out ( prog_clk_3_wires[33] ) , .clk_2_N_in ( p1860 ) , - .clk_2_S_in ( p940 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9344 ) , + .prog_clk_3_S_out ( prog_clk_3_wires[33] ) , .clk_2_N_in ( p2197 ) , + .clk_2_S_in ( p31 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9344 ) , .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9345 ) , .clk_3_S_in ( SYNOPSYS_UNCONNECTED_9346 ) , .clk_3_N_in ( clk_3_wires[32] ) , @@ -129795,14 +134317,14 @@ cby_1__1_ cby_8__6_ ( .prog_clk_0_W_in ( prog_clk_0_wires[307] ) , .prog_clk_0_S_out ( prog_clk_0_wires[308] ) , .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_9358 ) , - .prog_clk_2_N_in ( p1949 ) , .prog_clk_2_S_in ( p1739 ) , + .prog_clk_2_N_in ( p1396 ) , .prog_clk_2_S_in ( p1735 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_9359 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_9360 ) , .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_9361 ) , .prog_clk_3_N_in ( prog_clk_3_wires[28] ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_9362 ) , - .prog_clk_3_S_out ( prog_clk_3_wires[29] ) , .clk_2_N_in ( p1949 ) , - .clk_2_S_in ( p1646 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9363 ) , + .prog_clk_3_S_out ( prog_clk_3_wires[29] ) , .clk_2_N_in ( p1396 ) , + .clk_2_S_in ( p2421 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9363 ) , .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9364 ) , .clk_3_S_in ( SYNOPSYS_UNCONNECTED_9365 ) , .clk_3_N_in ( clk_3_wires[28] ) , @@ -129848,14 +134370,14 @@ cby_1__1_ cby_8__7_ ( .prog_clk_0_W_in ( prog_clk_0_wires[310] ) , .prog_clk_0_S_out ( prog_clk_0_wires[311] ) , .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_9377 ) , - .prog_clk_2_N_in ( p1778 ) , .prog_clk_2_S_in ( p2887 ) , + .prog_clk_2_N_in ( p1522 ) , .prog_clk_2_S_in ( p1808 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_9378 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_9379 ) , .prog_clk_3_S_in ( prog_clk_3_wires[26] ) , .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_9380 ) , .prog_clk_3_N_out ( prog_clk_3_wires[27] ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9381 ) , .clk_2_N_in ( p1778 ) , - .clk_2_S_in ( p2912 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9382 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9381 ) , .clk_2_N_in ( p1522 ) , + .clk_2_S_in ( p1698 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9382 ) , .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9383 ) , .clk_3_S_in ( clk_3_wires[26] ) , .clk_3_N_in ( SYNOPSYS_UNCONNECTED_9384 ) , @@ -129901,14 +134423,14 @@ cby_1__1_ cby_8__8_ ( .prog_clk_0_W_in ( prog_clk_0_wires[313] ) , .prog_clk_0_S_out ( prog_clk_0_wires[314] ) , .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_9396 ) , - .prog_clk_2_N_in ( p1387 ) , .prog_clk_2_S_in ( p2272 ) , + .prog_clk_2_N_in ( p1431 ) , .prog_clk_2_S_in ( p2378 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_9397 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_9398 ) , .prog_clk_3_S_in ( prog_clk_3_wires[30] ) , .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_9399 ) , .prog_clk_3_N_out ( prog_clk_3_wires[31] ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9400 ) , .clk_2_N_in ( p1387 ) , - .clk_2_S_in ( p2340 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9401 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9400 ) , .clk_2_N_in ( p1431 ) , + .clk_2_S_in ( p2458 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9401 ) , .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9402 ) , .clk_3_S_in ( clk_3_wires[30] ) , .clk_3_N_in ( SYNOPSYS_UNCONNECTED_9403 ) , @@ -129954,14 +134476,14 @@ cby_1__1_ cby_8__9_ ( .prog_clk_0_W_in ( prog_clk_0_wires[316] ) , .prog_clk_0_S_out ( prog_clk_0_wires[317] ) , .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_9415 ) , - .prog_clk_2_N_in ( p2207 ) , .prog_clk_2_S_in ( p1648 ) , + .prog_clk_2_N_in ( p1644 ) , .prog_clk_2_S_in ( p144 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_9416 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_9417 ) , .prog_clk_3_S_in ( prog_clk_3_wires[36] ) , .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_9418 ) , .prog_clk_3_N_out ( prog_clk_3_wires[37] ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9419 ) , .clk_2_N_in ( p2207 ) , - .clk_2_S_in ( p851 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9420 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9419 ) , .clk_2_N_in ( p1644 ) , + .clk_2_S_in ( p567 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9420 ) , .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9421 ) , .clk_3_S_in ( clk_3_wires[36] ) , .clk_3_N_in ( SYNOPSYS_UNCONNECTED_9422 ) , @@ -130007,14 +134529,14 @@ cby_1__1_ cby_8__10_ ( .prog_clk_0_W_in ( prog_clk_0_wires[319] ) , .prog_clk_0_S_out ( prog_clk_0_wires[320] ) , .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_9434 ) , - .prog_clk_2_N_in ( p2103 ) , .prog_clk_2_S_in ( p2071 ) , + .prog_clk_2_N_in ( p2372 ) , .prog_clk_2_S_in ( p1732 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_9435 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_9436 ) , .prog_clk_3_S_in ( prog_clk_3_wires[40] ) , .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_9437 ) , .prog_clk_3_N_out ( prog_clk_3_wires[41] ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9438 ) , .clk_2_N_in ( p2103 ) , - .clk_2_S_in ( p2312 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9439 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9438 ) , .clk_2_N_in ( p2208 ) , + .clk_2_S_in ( p1780 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9439 ) , .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9440 ) , .clk_3_S_in ( clk_3_wires[40] ) , .clk_3_N_in ( SYNOPSYS_UNCONNECTED_9441 ) , @@ -130060,15 +134582,15 @@ cby_1__1_ cby_8__11_ ( .prog_clk_0_W_in ( prog_clk_0_wires[322] ) , .prog_clk_0_S_out ( prog_clk_0_wires[323] ) , .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_9453 ) , - .prog_clk_2_N_in ( p1857 ) , .prog_clk_2_S_in ( p570 ) , + .prog_clk_2_N_in ( p2215 ) , .prog_clk_2_S_in ( p834 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_9454 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_9455 ) , - .prog_clk_3_S_in ( p3205 ) , .prog_clk_3_N_in ( p1705 ) , + .prog_clk_3_S_in ( p2845 ) , .prog_clk_3_N_in ( p2121 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_9456 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9457 ) , .clk_2_N_in ( p2621 ) , - .clk_2_S_in ( p3135 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9458 ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9459 ) , .clk_3_S_in ( p2474 ) , - .clk_3_N_in ( p2527 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9460 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9457 ) , .clk_2_N_in ( p2032 ) , + .clk_2_S_in ( p2879 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9458 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9459 ) , .clk_3_S_in ( p2992 ) , + .clk_3_N_in ( p1703 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9460 ) , .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9461 ) ) ; cby_1__1_ cby_8__12_ ( .pReset ( { SYNOPSYS_UNCONNECTED_9462 } ) , @@ -130109,16 +134631,16 @@ cby_1__1_ cby_8__12_ ( .Reset_E_out ( ResetWires[281] ) , .prog_clk_0_W_in ( prog_clk_0_wires[325] ) , .prog_clk_0_S_out ( prog_clk_0_wires[326] ) , - .prog_clk_0_N_out ( prog_clk_0_wires[328] ) , .prog_clk_2_N_in ( p2677 ) , - .prog_clk_2_S_in ( p229 ) , + .prog_clk_0_N_out ( prog_clk_0_wires[328] ) , .prog_clk_2_N_in ( p2588 ) , + .prog_clk_2_S_in ( p282 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_9472 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_9473 ) , - .prog_clk_3_S_in ( p2469 ) , .prog_clk_3_N_in ( p2589 ) , + .prog_clk_3_S_in ( p2806 ) , .prog_clk_3_N_in ( p2419 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_9474 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9475 ) , .clk_2_N_in ( p2785 ) , - .clk_2_S_in ( p2296 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9476 ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9477 ) , .clk_3_S_in ( p2510 ) , - .clk_3_N_in ( p2737 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9478 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9475 ) , .clk_2_N_in ( p1899 ) , + .clk_2_S_in ( p3298 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9476 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9477 ) , .clk_3_S_in ( p3327 ) , + .clk_3_N_in ( p1816 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9478 ) , .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9479 ) ) ; cby_1__1_ cby_9__1_ ( .pReset ( { SYNOPSYS_UNCONNECTED_9480 } ) , @@ -130160,15 +134682,15 @@ cby_1__1_ cby_9__1_ ( .prog_clk_0_W_in ( prog_clk_0_wires[330] ) , .prog_clk_0_S_out ( prog_clk_0_wires[331] ) , .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_9490 ) , - .prog_clk_2_N_in ( p2679 ) , .prog_clk_2_S_in ( p905 ) , + .prog_clk_2_N_in ( p2272 ) , .prog_clk_2_S_in ( p467 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_9491 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_9492 ) , - .prog_clk_3_S_in ( p1852 ) , .prog_clk_3_N_in ( p2565 ) , + .prog_clk_3_S_in ( p3346 ) , .prog_clk_3_N_in ( p2148 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_9493 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9494 ) , .clk_2_N_in ( p2499 ) , - .clk_2_S_in ( p1986 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9495 ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9496 ) , .clk_3_S_in ( p2208 ) , - .clk_3_N_in ( p2300 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9497 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9494 ) , .clk_2_N_in ( p3108 ) , + .clk_2_S_in ( p3285 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9495 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9496 ) , .clk_3_S_in ( p2857 ) , + .clk_3_N_in ( p3045 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9497 ) , .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9498 ) ) ; cby_1__1_ cby_9__2_ ( .pReset ( { SYNOPSYS_UNCONNECTED_9499 } ) , @@ -130214,14 +134736,14 @@ cby_1__1_ cby_9__2_ ( .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_9510 ) , .prog_clk_2_S_out ( prog_clk_2_wires[76] ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_9511 ) , - .prog_clk_3_S_in ( p1617 ) , .prog_clk_3_N_in ( p69 ) , + .prog_clk_3_S_in ( p2201 ) , .prog_clk_3_N_in ( p841 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_9512 ) , .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9513 ) , .clk_2_N_in ( clk_2_wires[75] ) , .clk_2_S_in ( SYNOPSYS_UNCONNECTED_9514 ) , .clk_2_S_out ( clk_2_wires[76] ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9515 ) , .clk_3_S_in ( p1617 ) , - .clk_3_N_in ( p701 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9516 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9515 ) , .clk_3_S_in ( p2201 ) , + .clk_3_N_in ( p291 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9516 ) , .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9517 ) ) ; cby_1__1_ cby_9__3_ ( .pReset ( { SYNOPSYS_UNCONNECTED_9518 } ) , @@ -130263,15 +134785,15 @@ cby_1__1_ cby_9__3_ ( .prog_clk_0_W_in ( prog_clk_0_wires[336] ) , .prog_clk_0_S_out ( prog_clk_0_wires[337] ) , .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_9528 ) , - .prog_clk_2_N_in ( p2200 ) , .prog_clk_2_S_in ( p245 ) , + .prog_clk_2_N_in ( p2611 ) , .prog_clk_2_S_in ( p569 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_9529 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_9530 ) , - .prog_clk_3_S_in ( p2810 ) , .prog_clk_3_N_in ( p2004 ) , + .prog_clk_3_S_in ( p2335 ) , .prog_clk_3_N_in ( p2404 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_9531 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9532 ) , .clk_2_N_in ( p3157 ) , - .clk_2_S_in ( p3122 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9533 ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9534 ) , .clk_3_S_in ( p3163 ) , - .clk_3_N_in ( p3154 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9535 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9532 ) , .clk_2_N_in ( p2815 ) , + .clk_2_S_in ( p2699 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9533 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9534 ) , .clk_3_S_in ( p2782 ) , + .clk_3_N_in ( p2644 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9535 ) , .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9536 ) ) ; cby_1__1_ cby_9__4_ ( .pReset ( { SYNOPSYS_UNCONNECTED_9537 } ) , @@ -130317,14 +134839,14 @@ cby_1__1_ cby_9__4_ ( .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_9548 ) , .prog_clk_2_S_out ( prog_clk_2_wires[89] ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_9549 ) , - .prog_clk_3_S_in ( p1259 ) , .prog_clk_3_N_in ( p1039 ) , + .prog_clk_3_S_in ( p2364 ) , .prog_clk_3_N_in ( p915 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_9550 ) , .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9551 ) , .clk_2_N_in ( clk_2_wires[88] ) , .clk_2_S_in ( SYNOPSYS_UNCONNECTED_9552 ) , .clk_2_S_out ( clk_2_wires[89] ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9553 ) , .clk_3_S_in ( p1259 ) , - .clk_3_N_in ( p322 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9554 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9553 ) , .clk_3_S_in ( p2364 ) , + .clk_3_N_in ( p856 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9554 ) , .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9555 ) ) ; cby_1__1_ cby_9__5_ ( .pReset ( { SYNOPSYS_UNCONNECTED_9556 } ) , @@ -130369,15 +134891,15 @@ cby_1__1_ cby_9__5_ ( .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_9567 ) , .prog_clk_2_S_in ( prog_clk_2_wires[86] ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_9568 ) , - .prog_clk_2_N_out ( prog_clk_2_wires[87] ) , .prog_clk_3_S_in ( p2140 ) , - .prog_clk_3_N_in ( p12 ) , + .prog_clk_2_N_out ( prog_clk_2_wires[87] ) , .prog_clk_3_S_in ( p1972 ) , + .prog_clk_3_N_in ( p921 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_9569 ) , .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9570 ) , .clk_2_N_in ( SYNOPSYS_UNCONNECTED_9571 ) , .clk_2_S_in ( clk_2_wires[86] ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9572 ) , - .clk_2_N_out ( clk_2_wires[87] ) , .clk_3_S_in ( p2140 ) , - .clk_3_N_in ( p859 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9573 ) , + .clk_2_N_out ( clk_2_wires[87] ) , .clk_3_S_in ( p1972 ) , + .clk_3_N_in ( p14 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9573 ) , .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9574 ) ) ; cby_1__1_ cby_9__6_ ( .pReset ( { SYNOPSYS_UNCONNECTED_9575 } ) , @@ -130419,15 +134941,15 @@ cby_1__1_ cby_9__6_ ( .prog_clk_0_W_in ( prog_clk_0_wires[345] ) , .prog_clk_0_S_out ( prog_clk_0_wires[346] ) , .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_9585 ) , - .prog_clk_2_N_in ( p2232 ) , .prog_clk_2_S_in ( p428 ) , + .prog_clk_2_N_in ( p2765 ) , .prog_clk_2_S_in ( p261 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_9586 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_9587 ) , - .prog_clk_3_S_in ( p2935 ) , .prog_clk_3_N_in ( p2055 ) , + .prog_clk_3_S_in ( p2050 ) , .prog_clk_3_N_in ( p2650 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_9588 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9589 ) , .clk_2_N_in ( p2978 ) , - .clk_2_S_in ( p2874 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9590 ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9591 ) , .clk_3_S_in ( p2137 ) , - .clk_3_N_in ( p2900 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9592 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9589 ) , .clk_2_N_in ( p2308 ) , + .clk_2_S_in ( p2403 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9590 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9591 ) , .clk_3_S_in ( p2610 ) , + .clk_3_N_in ( p2152 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9592 ) , .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9593 ) ) ; cby_1__1_ cby_9__7_ ( .pReset ( { SYNOPSYS_UNCONNECTED_9594 } ) , @@ -130469,15 +134991,15 @@ cby_1__1_ cby_9__7_ ( .prog_clk_0_W_in ( prog_clk_0_wires[348] ) , .prog_clk_0_S_out ( prog_clk_0_wires[349] ) , .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_9604 ) , - .prog_clk_2_N_in ( p2990 ) , .prog_clk_2_S_in ( p1660 ) , + .prog_clk_2_N_in ( p2505 ) , .prog_clk_2_S_in ( p1801 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_9605 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_9606 ) , - .prog_clk_3_S_in ( p2656 ) , .prog_clk_3_N_in ( p2921 ) , + .prog_clk_3_S_in ( p2772 ) , .prog_clk_3_N_in ( p2391 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_9607 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9608 ) , .clk_2_N_in ( p2961 ) , - .clk_2_S_in ( p2717 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9609 ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9610 ) , .clk_3_S_in ( p2782 ) , - .clk_3_N_in ( p2873 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9611 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9608 ) , .clk_2_N_in ( p3005 ) , + .clk_2_S_in ( p2662 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9609 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9610 ) , .clk_3_S_in ( p2749 ) , + .clk_3_N_in ( p2900 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9611 ) , .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9612 ) ) ; cby_1__1_ cby_9__8_ ( .pReset ( { SYNOPSYS_UNCONNECTED_9613 } ) , @@ -130523,14 +135045,14 @@ cby_1__1_ cby_9__8_ ( .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_9624 ) , .prog_clk_2_S_out ( prog_clk_2_wires[102] ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_9625 ) , - .prog_clk_3_S_in ( p1842 ) , .prog_clk_3_N_in ( p278 ) , + .prog_clk_3_S_in ( p1303 ) , .prog_clk_3_N_in ( p1014 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_9626 ) , .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9627 ) , .clk_2_N_in ( clk_2_wires[101] ) , .clk_2_S_in ( SYNOPSYS_UNCONNECTED_9628 ) , .clk_2_S_out ( clk_2_wires[102] ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9629 ) , .clk_3_S_in ( p1842 ) , - .clk_3_N_in ( p499 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9630 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9629 ) , .clk_3_S_in ( p1303 ) , + .clk_3_N_in ( p143 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9630 ) , .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9631 ) ) ; cby_1__1_ cby_9__9_ ( .pReset ( { SYNOPSYS_UNCONNECTED_9632 } ) , @@ -130575,15 +135097,15 @@ cby_1__1_ cby_9__9_ ( .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_9643 ) , .prog_clk_2_S_in ( prog_clk_2_wires[99] ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_9644 ) , - .prog_clk_2_N_out ( prog_clk_2_wires[100] ) , .prog_clk_3_S_in ( p1463 ) , - .prog_clk_3_N_in ( p785 ) , + .prog_clk_2_N_out ( prog_clk_2_wires[100] ) , .prog_clk_3_S_in ( p1643 ) , + .prog_clk_3_N_in ( p164 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_9645 ) , .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9646 ) , .clk_2_N_in ( SYNOPSYS_UNCONNECTED_9647 ) , .clk_2_S_in ( clk_2_wires[99] ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9648 ) , - .clk_2_N_out ( clk_2_wires[100] ) , .clk_3_S_in ( p1463 ) , - .clk_3_N_in ( p896 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9649 ) , + .clk_2_N_out ( clk_2_wires[100] ) , .clk_3_S_in ( p1643 ) , + .clk_3_N_in ( p913 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9649 ) , .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9650 ) ) ; cby_1__1_ cby_9__10_ ( .pReset ( { SYNOPSYS_UNCONNECTED_9651 } ) , @@ -130625,15 +135147,15 @@ cby_1__1_ cby_9__10_ ( .prog_clk_0_W_in ( prog_clk_0_wires[357] ) , .prog_clk_0_S_out ( prog_clk_0_wires[358] ) , .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_9661 ) , - .prog_clk_2_N_in ( p1173 ) , .prog_clk_2_S_in ( p424 ) , + .prog_clk_2_N_in ( p1401 ) , .prog_clk_2_S_in ( p251 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_9662 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_9663 ) , - .prog_clk_3_S_in ( p2815 ) , .prog_clk_3_N_in ( p1068 ) , + .prog_clk_3_S_in ( p2263 ) , .prog_clk_3_N_in ( p740 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_9664 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9665 ) , .clk_2_N_in ( p2828 ) , - .clk_2_S_in ( p2880 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9666 ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9667 ) , .clk_3_S_in ( p2941 ) , - .clk_3_N_in ( p2746 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9668 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9665 ) , .clk_2_N_in ( p2623 ) , + .clk_2_S_in ( p2653 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9666 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9667 ) , .clk_3_S_in ( p2763 ) , + .clk_3_N_in ( p2412 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9668 ) , .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9669 ) ) ; cby_1__1_ cby_9__11_ ( .pReset ( { SYNOPSYS_UNCONNECTED_9670 } ) , @@ -130678,15 +135200,15 @@ cby_1__1_ cby_9__11_ ( .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_9681 ) , .prog_clk_2_S_in ( prog_clk_2_wires[110] ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_9682 ) , - .prog_clk_2_N_out ( prog_clk_2_wires[111] ) , .prog_clk_3_S_in ( p1580 ) , - .prog_clk_3_N_in ( p420 ) , + .prog_clk_2_N_out ( prog_clk_2_wires[111] ) , .prog_clk_3_S_in ( p1286 ) , + .prog_clk_3_N_in ( p651 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_9683 ) , .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9684 ) , .clk_2_N_in ( SYNOPSYS_UNCONNECTED_9685 ) , .clk_2_S_in ( clk_2_wires[110] ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9686 ) , - .clk_2_N_out ( clk_2_wires[111] ) , .clk_3_S_in ( p1580 ) , - .clk_3_N_in ( p493 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9687 ) , + .clk_2_N_out ( clk_2_wires[111] ) , .clk_3_S_in ( p1286 ) , + .clk_3_N_in ( p775 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9687 ) , .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9688 ) ) ; cby_1__1_ cby_9__12_ ( .pReset ( { SYNOPSYS_UNCONNECTED_9689 } ) , @@ -130727,16 +135249,16 @@ cby_1__1_ cby_9__12_ ( .Reset_E_out ( ResetWires[283] ) , .prog_clk_0_W_in ( prog_clk_0_wires[363] ) , .prog_clk_0_S_out ( prog_clk_0_wires[364] ) , - .prog_clk_0_N_out ( prog_clk_0_wires[366] ) , .prog_clk_2_N_in ( p2786 ) , - .prog_clk_2_S_in ( p463 ) , + .prog_clk_0_N_out ( prog_clk_0_wires[366] ) , .prog_clk_2_N_in ( p1593 ) , + .prog_clk_2_S_in ( p472 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_9699 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_9700 ) , - .prog_clk_3_S_in ( p3266 ) , .prog_clk_3_N_in ( p2772 ) , + .prog_clk_3_S_in ( p3026 ) , .prog_clk_3_N_in ( p770 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_9701 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9702 ) , .clk_2_N_in ( p3059 ) , - .clk_2_S_in ( p3238 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9703 ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9704 ) , .clk_3_S_in ( p3195 ) , - .clk_3_N_in ( p3032 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9705 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9702 ) , .clk_2_N_in ( p1929 ) , + .clk_2_S_in ( p2916 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9703 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9704 ) , .clk_3_S_in ( p2758 ) , + .clk_3_N_in ( p1685 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9705 ) , .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9706 ) ) ; cby_1__1_ cby_10__1_ ( .pReset ( { SYNOPSYS_UNCONNECTED_9707 } ) , @@ -130778,15 +135300,15 @@ cby_1__1_ cby_10__1_ ( .prog_clk_0_W_in ( prog_clk_0_wires[368] ) , .prog_clk_0_S_out ( prog_clk_0_wires[369] ) , .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_9717 ) , - .prog_clk_2_N_in ( p1788 ) , .prog_clk_2_S_in ( p171 ) , + .prog_clk_2_N_in ( p1865 ) , .prog_clk_2_S_in ( p643 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_9718 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_9719 ) , - .prog_clk_3_S_in ( p2217 ) , .prog_clk_3_N_in ( p1716 ) , + .prog_clk_3_S_in ( p2341 ) , .prog_clk_3_N_in ( p1804 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_9720 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9721 ) , .clk_2_N_in ( p2627 ) , - .clk_2_S_in ( p2031 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9722 ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9723 ) , .clk_3_S_in ( p2221 ) , - .clk_3_N_in ( p2524 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9724 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9721 ) , .clk_2_N_in ( p3354 ) , + .clk_2_S_in ( p2123 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9722 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9723 ) , .clk_3_S_in ( p2029 ) , + .clk_3_N_in ( p3290 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9724 ) , .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9725 ) ) ; cby_1__1_ cby_10__2_ ( .pReset ( { SYNOPSYS_UNCONNECTED_9726 } ) , @@ -130828,15 +135350,15 @@ cby_1__1_ cby_10__2_ ( .prog_clk_0_W_in ( prog_clk_0_wires[371] ) , .prog_clk_0_S_out ( prog_clk_0_wires[372] ) , .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_9736 ) , - .prog_clk_2_N_in ( p2148 ) , .prog_clk_2_S_in ( p932 ) , + .prog_clk_2_N_in ( p1619 ) , .prog_clk_2_S_in ( p301 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_9737 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_9738 ) , - .prog_clk_3_S_in ( p2664 ) , .prog_clk_3_N_in ( p2089 ) , + .prog_clk_3_S_in ( p2609 ) , .prog_clk_3_N_in ( p154 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_9739 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9740 ) , .clk_2_N_in ( p2856 ) , - .clk_2_S_in ( p2603 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9741 ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9742 ) , .clk_3_S_in ( p2116 ) , - .clk_3_N_in ( p2744 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9743 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9740 ) , .clk_2_N_in ( p3158 ) , + .clk_2_S_in ( p2668 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9741 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9742 ) , .clk_3_S_in ( p2853 ) , + .clk_3_N_in ( p3058 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9743 ) , .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9744 ) ) ; cby_1__1_ cby_10__3_ ( .pReset ( { SYNOPSYS_UNCONNECTED_9745 } ) , @@ -130878,14 +135400,14 @@ cby_1__1_ cby_10__3_ ( .prog_clk_0_W_in ( prog_clk_0_wires[374] ) , .prog_clk_0_S_out ( prog_clk_0_wires[375] ) , .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_9755 ) , - .prog_clk_2_N_in ( p1918 ) , .prog_clk_2_S_in ( p1065 ) , + .prog_clk_2_N_in ( p1913 ) , .prog_clk_2_S_in ( p648 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_9756 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_9757 ) , .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_9758 ) , .prog_clk_3_N_in ( prog_clk_3_wires[86] ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_9759 ) , - .prog_clk_3_S_out ( prog_clk_3_wires[87] ) , .clk_2_N_in ( p1838 ) , - .clk_2_S_in ( p736 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9760 ) , + .prog_clk_3_S_out ( prog_clk_3_wires[87] ) , .clk_2_N_in ( p1913 ) , + .clk_2_S_in ( p896 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9760 ) , .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9761 ) , .clk_3_S_in ( SYNOPSYS_UNCONNECTED_9762 ) , .clk_3_N_in ( clk_3_wires[86] ) , @@ -130931,14 +135453,14 @@ cby_1__1_ cby_10__4_ ( .prog_clk_0_W_in ( prog_clk_0_wires[377] ) , .prog_clk_0_S_out ( prog_clk_0_wires[378] ) , .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_9774 ) , - .prog_clk_2_N_in ( p1437 ) , .prog_clk_2_S_in ( p2559 ) , + .prog_clk_2_N_in ( p1437 ) , .prog_clk_2_S_in ( p1696 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_9775 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_9776 ) , .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_9777 ) , .prog_clk_3_N_in ( prog_clk_3_wires[82] ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_9778 ) , .prog_clk_3_S_out ( prog_clk_3_wires[83] ) , .clk_2_N_in ( p1437 ) , - .clk_2_S_in ( p2864 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9779 ) , + .clk_2_S_in ( p1826 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9779 ) , .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9780 ) , .clk_3_S_in ( SYNOPSYS_UNCONNECTED_9781 ) , .clk_3_N_in ( clk_3_wires[82] ) , @@ -130984,14 +135506,14 @@ cby_1__1_ cby_10__5_ ( .prog_clk_0_W_in ( prog_clk_0_wires[380] ) , .prog_clk_0_S_out ( prog_clk_0_wires[381] ) , .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_9793 ) , - .prog_clk_2_N_in ( p1120 ) , .prog_clk_2_S_in ( p317 ) , + .prog_clk_2_N_in ( p1446 ) , .prog_clk_2_S_in ( p891 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_9794 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_9795 ) , .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_9796 ) , .prog_clk_3_N_in ( prog_clk_3_wires[76] ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_9797 ) , - .prog_clk_3_S_out ( prog_clk_3_wires[77] ) , .clk_2_N_in ( p1120 ) , - .clk_2_S_in ( p899 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9798 ) , + .prog_clk_3_S_out ( prog_clk_3_wires[77] ) , .clk_2_N_in ( p1446 ) , + .clk_2_S_in ( p77 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9798 ) , .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9799 ) , .clk_3_S_in ( SYNOPSYS_UNCONNECTED_9800 ) , .clk_3_N_in ( clk_3_wires[76] ) , @@ -131037,14 +135559,14 @@ cby_1__1_ cby_10__6_ ( .prog_clk_0_W_in ( prog_clk_0_wires[383] ) , .prog_clk_0_S_out ( prog_clk_0_wires[384] ) , .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_9812 ) , - .prog_clk_2_N_in ( p1897 ) , .prog_clk_2_S_in ( p2528 ) , + .prog_clk_2_N_in ( p1466 ) , .prog_clk_2_S_in ( p2719 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_9813 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_9814 ) , .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_9815 ) , .prog_clk_3_N_in ( prog_clk_3_wires[72] ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_9816 ) , - .prog_clk_3_S_out ( prog_clk_3_wires[73] ) , .clk_2_N_in ( p1917 ) , - .clk_2_S_in ( p2601 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9817 ) , + .prog_clk_3_S_out ( prog_clk_3_wires[73] ) , .clk_2_N_in ( p1466 ) , + .clk_2_S_in ( p2875 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9817 ) , .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9818 ) , .clk_3_S_in ( SYNOPSYS_UNCONNECTED_9819 ) , .clk_3_N_in ( clk_3_wires[72] ) , @@ -131090,14 +135612,14 @@ cby_1__1_ cby_10__7_ ( .prog_clk_0_W_in ( prog_clk_0_wires[386] ) , .prog_clk_0_S_out ( prog_clk_0_wires[387] ) , .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_9831 ) , - .prog_clk_2_N_in ( p1532 ) , .prog_clk_2_S_in ( p2087 ) , + .prog_clk_2_N_in ( p1569 ) , .prog_clk_2_S_in ( p416 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_9832 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_9833 ) , .prog_clk_3_S_in ( prog_clk_3_wires[70] ) , .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_9834 ) , .prog_clk_3_N_out ( prog_clk_3_wires[71] ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9835 ) , .clk_2_N_in ( p1532 ) , - .clk_2_S_in ( p2030 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9836 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9835 ) , .clk_2_N_in ( p1569 ) , + .clk_2_S_in ( p2396 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9836 ) , .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9837 ) , .clk_3_S_in ( clk_3_wires[70] ) , .clk_3_N_in ( SYNOPSYS_UNCONNECTED_9838 ) , @@ -131143,14 +135665,14 @@ cby_1__1_ cby_10__8_ ( .prog_clk_0_W_in ( prog_clk_0_wires[389] ) , .prog_clk_0_S_out ( prog_clk_0_wires[390] ) , .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_9850 ) , - .prog_clk_2_N_in ( p1612 ) , .prog_clk_2_S_in ( p2731 ) , + .prog_clk_2_N_in ( p1544 ) , .prog_clk_2_S_in ( p250 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_9851 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_9852 ) , .prog_clk_3_S_in ( prog_clk_3_wires[74] ) , .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_9853 ) , .prog_clk_3_N_out ( prog_clk_3_wires[75] ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9854 ) , .clk_2_N_in ( p1612 ) , - .clk_2_S_in ( p2770 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9855 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9854 ) , .clk_2_N_in ( p1544 ) , + .clk_2_S_in ( p824 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9855 ) , .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9856 ) , .clk_3_S_in ( clk_3_wires[74] ) , .clk_3_N_in ( SYNOPSYS_UNCONNECTED_9857 ) , @@ -131196,14 +135718,14 @@ cby_1__1_ cby_10__9_ ( .prog_clk_0_W_in ( prog_clk_0_wires[392] ) , .prog_clk_0_S_out ( prog_clk_0_wires[393] ) , .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_9869 ) , - .prog_clk_2_N_in ( p1923 ) , .prog_clk_2_S_in ( p2039 ) , + .prog_clk_2_N_in ( p1950 ) , .prog_clk_2_S_in ( p450 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_9870 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_9871 ) , .prog_clk_3_S_in ( prog_clk_3_wires[80] ) , .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_9872 ) , .prog_clk_3_N_out ( prog_clk_3_wires[81] ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9873 ) , .clk_2_N_in ( p1923 ) , - .clk_2_S_in ( p702 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9874 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9873 ) , .clk_2_N_in ( p1950 ) , + .clk_2_S_in ( p224 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9874 ) , .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9875 ) , .clk_3_S_in ( clk_3_wires[80] ) , .clk_3_N_in ( SYNOPSYS_UNCONNECTED_9876 ) , @@ -131249,14 +135771,14 @@ cby_1__1_ cby_10__10_ ( .prog_clk_0_W_in ( prog_clk_0_wires[395] ) , .prog_clk_0_S_out ( prog_clk_0_wires[396] ) , .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_9888 ) , - .prog_clk_2_N_in ( p2134 ) , .prog_clk_2_S_in ( p1641 ) , + .prog_clk_2_N_in ( p1345 ) , .prog_clk_2_S_in ( p2071 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_9889 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_9890 ) , .prog_clk_3_S_in ( prog_clk_3_wires[84] ) , .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_9891 ) , .prog_clk_3_N_out ( prog_clk_3_wires[85] ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9892 ) , .clk_2_N_in ( p2134 ) , - .clk_2_S_in ( p1721 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9893 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9892 ) , .clk_2_N_in ( p1345 ) , + .clk_2_S_in ( p2877 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9893 ) , .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9894 ) , .clk_3_S_in ( clk_3_wires[84] ) , .clk_3_N_in ( SYNOPSYS_UNCONNECTED_9895 ) , @@ -131302,15 +135824,15 @@ cby_1__1_ cby_10__11_ ( .prog_clk_0_W_in ( prog_clk_0_wires[398] ) , .prog_clk_0_S_out ( prog_clk_0_wires[399] ) , .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_9907 ) , - .prog_clk_2_N_in ( p2520 ) , .prog_clk_2_S_in ( p735 ) , + .prog_clk_2_N_in ( p1634 ) , .prog_clk_2_S_in ( p661 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_9908 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_9909 ) , - .prog_clk_3_S_in ( p2813 ) , .prog_clk_3_N_in ( p2328 ) , + .prog_clk_3_S_in ( p2954 ) , .prog_clk_3_N_in ( p939 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_9910 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9911 ) , .clk_2_N_in ( p2220 ) , - .clk_2_S_in ( p3115 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9912 ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9913 ) , .clk_3_S_in ( p3185 ) , - .clk_3_N_in ( p2023 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9914 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9911 ) , .clk_2_N_in ( p2601 ) , + .clk_2_S_in ( p2864 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9912 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9913 ) , .clk_3_S_in ( p2820 ) , + .clk_3_N_in ( p2382 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9914 ) , .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9915 ) ) ; cby_1__1_ cby_10__12_ ( .pReset ( { SYNOPSYS_UNCONNECTED_9916 } ) , @@ -131351,16 +135873,16 @@ cby_1__1_ cby_10__12_ ( .Reset_E_out ( ResetWires[285] ) , .prog_clk_0_W_in ( prog_clk_0_wires[401] ) , .prog_clk_0_S_out ( prog_clk_0_wires[402] ) , - .prog_clk_0_N_out ( prog_clk_0_wires[404] ) , .prog_clk_2_N_in ( p2405 ) , - .prog_clk_2_S_in ( p504 ) , + .prog_clk_0_N_out ( prog_clk_0_wires[404] ) , .prog_clk_2_N_in ( p1962 ) , + .prog_clk_2_S_in ( p1030 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_9926 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_9927 ) , - .prog_clk_3_S_in ( p2971 ) , .prog_clk_3_N_in ( p2374 ) , + .prog_clk_3_S_in ( p1584 ) , .prog_clk_3_N_in ( p1751 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_9928 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9929 ) , .clk_2_N_in ( p2954 ) , - .clk_2_S_in ( p3155 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9930 ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9931 ) , .clk_3_S_in ( p3180 ) , - .clk_3_N_in ( p2865 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9932 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9929 ) , .clk_2_N_in ( p2643 ) , + .clk_2_S_in ( p2410 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9930 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9931 ) , .clk_3_S_in ( p2485 ) , + .clk_3_N_in ( p2439 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9932 ) , .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9933 ) ) ; cby_1__1_ cby_11__1_ ( .pReset ( { SYNOPSYS_UNCONNECTED_9934 } ) , @@ -131402,15 +135924,15 @@ cby_1__1_ cby_11__1_ ( .prog_clk_0_W_in ( prog_clk_0_wires[406] ) , .prog_clk_0_S_out ( prog_clk_0_wires[407] ) , .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_9944 ) , - .prog_clk_2_N_in ( p2246 ) , .prog_clk_2_S_in ( p657 ) , + .prog_clk_2_N_in ( p2220 ) , .prog_clk_2_S_in ( p1001 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_9945 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_9946 ) , - .prog_clk_3_S_in ( p2829 ) , .prog_clk_3_N_in ( p2052 ) , + .prog_clk_3_S_in ( p2226 ) , .prog_clk_3_N_in ( p2133 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_9947 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9948 ) , .clk_2_N_in ( p3258 ) , - .clk_2_S_in ( p2724 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9949 ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9950 ) , .clk_3_S_in ( p1485 ) , - .clk_3_N_in ( p3213 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9951 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9948 ) , .clk_2_N_in ( p1570 ) , + .clk_2_S_in ( p2885 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9949 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9950 ) , .clk_3_S_in ( p2989 ) , + .clk_3_N_in ( p879 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9951 ) , .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9952 ) ) ; cby_1__1_ cby_11__2_ ( .pReset ( { SYNOPSYS_UNCONNECTED_9953 } ) , @@ -131456,14 +135978,14 @@ cby_1__1_ cby_11__2_ ( .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_9964 ) , .prog_clk_2_S_out ( prog_clk_2_wires[116] ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_9965 ) , - .prog_clk_3_S_in ( p1309 ) , .prog_clk_3_N_in ( p44 ) , + .prog_clk_3_S_in ( p2005 ) , .prog_clk_3_N_in ( p192 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_9966 ) , .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9967 ) , .clk_2_N_in ( clk_2_wires[115] ) , .clk_2_S_in ( SYNOPSYS_UNCONNECTED_9968 ) , .clk_2_S_out ( clk_2_wires[116] ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9969 ) , .clk_3_S_in ( p1309 ) , - .clk_3_N_in ( p477 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9970 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9969 ) , .clk_3_S_in ( p2005 ) , + .clk_3_N_in ( p979 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9970 ) , .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9971 ) ) ; cby_1__1_ cby_11__3_ ( .pReset ( { SYNOPSYS_UNCONNECTED_9972 } ) , @@ -131505,15 +136027,15 @@ cby_1__1_ cby_11__3_ ( .prog_clk_0_W_in ( prog_clk_0_wires[412] ) , .prog_clk_0_S_out ( prog_clk_0_wires[413] ) , .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_9982 ) , - .prog_clk_2_N_in ( p2984 ) , .prog_clk_2_S_in ( p568 ) , + .prog_clk_2_N_in ( p1844 ) , .prog_clk_2_S_in ( p925 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_9983 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_9984 ) , - .prog_clk_3_S_in ( p2172 ) , .prog_clk_3_N_in ( p2901 ) , + .prog_clk_3_S_in ( p2010 ) , .prog_clk_3_N_in ( p1750 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_9985 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9986 ) , .clk_2_N_in ( p3404 ) , - .clk_2_S_in ( p3139 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9987 ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9988 ) , .clk_3_S_in ( p3178 ) , - .clk_3_N_in ( p3384 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9989 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9986 ) , .clk_2_N_in ( p2994 ) , + .clk_2_S_in ( p2138 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9987 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9988 ) , .clk_3_S_in ( p2287 ) , + .clk_3_N_in ( p2880 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9989 ) , .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9990 ) ) ; cby_1__1_ cby_11__4_ ( .pReset ( { SYNOPSYS_UNCONNECTED_9991 } ) , @@ -131559,14 +136081,14 @@ cby_1__1_ cby_11__4_ ( .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_10002 ) , .prog_clk_2_S_out ( prog_clk_2_wires[123] ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_10003 ) , - .prog_clk_3_S_in ( p1761 ) , .prog_clk_3_N_in ( p183 ) , + .prog_clk_3_S_in ( p1409 ) , .prog_clk_3_N_in ( p188 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_10004 ) , .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_10005 ) , .clk_2_N_in ( clk_2_wires[122] ) , .clk_2_S_in ( SYNOPSYS_UNCONNECTED_10006 ) , .clk_2_S_out ( clk_2_wires[123] ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_10007 ) , .clk_3_S_in ( p1761 ) , - .clk_3_N_in ( p1032 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_10008 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_10007 ) , .clk_3_S_in ( p1409 ) , + .clk_3_N_in ( p767 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_10008 ) , .clk_3_S_out ( SYNOPSYS_UNCONNECTED_10009 ) ) ; cby_1__1_ cby_11__5_ ( .pReset ( { SYNOPSYS_UNCONNECTED_10010 } ) , @@ -131611,15 +136133,15 @@ cby_1__1_ cby_11__5_ ( .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_10021 ) , .prog_clk_2_S_in ( prog_clk_2_wires[120] ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_10022 ) , - .prog_clk_2_N_out ( prog_clk_2_wires[121] ) , .prog_clk_3_S_in ( p1441 ) , - .prog_clk_3_N_in ( p969 ) , + .prog_clk_2_N_out ( prog_clk_2_wires[121] ) , .prog_clk_3_S_in ( p1161 ) , + .prog_clk_3_N_in ( p579 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_10023 ) , .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_10024 ) , .clk_2_N_in ( SYNOPSYS_UNCONNECTED_10025 ) , .clk_2_S_in ( clk_2_wires[120] ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_10026 ) , - .clk_2_N_out ( clk_2_wires[121] ) , .clk_3_S_in ( p1441 ) , - .clk_3_N_in ( p1049 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_10027 ) , + .clk_2_N_out ( clk_2_wires[121] ) , .clk_3_S_in ( p1589 ) , + .clk_3_N_in ( p485 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_10027 ) , .clk_3_S_out ( SYNOPSYS_UNCONNECTED_10028 ) ) ; cby_1__1_ cby_11__6_ ( .pReset ( { SYNOPSYS_UNCONNECTED_10029 } ) , @@ -131661,15 +136183,15 @@ cby_1__1_ cby_11__6_ ( .prog_clk_0_W_in ( prog_clk_0_wires[421] ) , .prog_clk_0_S_out ( prog_clk_0_wires[422] ) , .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_10039 ) , - .prog_clk_2_N_in ( p1895 ) , .prog_clk_2_S_in ( p781 ) , + .prog_clk_2_N_in ( p2768 ) , .prog_clk_2_S_in ( p262 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_10040 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_10041 ) , - .prog_clk_3_S_in ( p2518 ) , .prog_clk_3_N_in ( p1699 ) , + .prog_clk_3_S_in ( p2849 ) , .prog_clk_3_N_in ( p2723 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_10042 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_10043 ) , .clk_2_N_in ( p2212 ) , - .clk_2_S_in ( p3339 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_10044 ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_10045 ) , .clk_3_S_in ( p3365 ) , - .clk_3_N_in ( p2065 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_10046 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_10043 ) , .clk_2_N_in ( p2942 ) , + .clk_2_S_in ( p2711 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_10044 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_10045 ) , .clk_3_S_in ( p1587 ) , + .clk_3_N_in ( p2869 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_10046 ) , .clk_3_S_out ( SYNOPSYS_UNCONNECTED_10047 ) ) ; cby_1__1_ cby_11__7_ ( .pReset ( { SYNOPSYS_UNCONNECTED_10048 } ) , @@ -131711,15 +136233,15 @@ cby_1__1_ cby_11__7_ ( .prog_clk_0_W_in ( prog_clk_0_wires[424] ) , .prog_clk_0_S_out ( prog_clk_0_wires[425] ) , .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_10058 ) , - .prog_clk_2_N_in ( p2092 ) , .prog_clk_2_S_in ( p458 ) , + .prog_clk_2_N_in ( p1351 ) , .prog_clk_2_S_in ( p766 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_10059 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_10060 ) , - .prog_clk_3_S_in ( p2690 ) , .prog_clk_3_N_in ( p2061 ) , + .prog_clk_3_S_in ( p2950 ) , .prog_clk_3_N_in ( p1163 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_10061 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_10062 ) , .clk_2_N_in ( p2657 ) , - .clk_2_S_in ( p3048 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_10063 ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_10064 ) , .clk_3_S_in ( p3084 ) , - .clk_3_N_in ( p2547 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_10065 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_10062 ) , .clk_2_N_in ( p3014 ) , + .clk_2_S_in ( p2919 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_10063 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_10064 ) , .clk_3_S_in ( p2951 ) , + .clk_3_N_in ( p2912 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_10065 ) , .clk_3_S_out ( SYNOPSYS_UNCONNECTED_10066 ) ) ; cby_1__1_ cby_11__8_ ( .pReset ( { SYNOPSYS_UNCONNECTED_10067 } ) , @@ -131765,14 +136287,14 @@ cby_1__1_ cby_11__8_ ( .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_10078 ) , .prog_clk_2_S_out ( prog_clk_2_wires[130] ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_10079 ) , - .prog_clk_3_S_in ( p1893 ) , .prog_clk_3_N_in ( p574 ) , + .prog_clk_3_S_in ( p1568 ) , .prog_clk_3_N_in ( p1051 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_10080 ) , .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_10081 ) , .clk_2_N_in ( clk_2_wires[129] ) , .clk_2_S_in ( SYNOPSYS_UNCONNECTED_10082 ) , .clk_2_S_out ( clk_2_wires[130] ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_10083 ) , .clk_3_S_in ( p1893 ) , - .clk_3_N_in ( p983 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_10084 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_10083 ) , .clk_3_S_in ( p1568 ) , + .clk_3_N_in ( p239 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_10084 ) , .clk_3_S_out ( SYNOPSYS_UNCONNECTED_10085 ) ) ; cby_1__1_ cby_11__9_ ( .pReset ( { SYNOPSYS_UNCONNECTED_10086 } ) , @@ -131817,15 +136339,15 @@ cby_1__1_ cby_11__9_ ( .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_10097 ) , .prog_clk_2_S_in ( prog_clk_2_wires[127] ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_10098 ) , - .prog_clk_2_N_out ( prog_clk_2_wires[128] ) , .prog_clk_3_S_in ( p1948 ) , - .prog_clk_3_N_in ( p1094 ) , + .prog_clk_2_N_out ( prog_clk_2_wires[128] ) , .prog_clk_3_S_in ( p1938 ) , + .prog_clk_3_N_in ( p713 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_10099 ) , .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_10100 ) , .clk_2_N_in ( SYNOPSYS_UNCONNECTED_10101 ) , .clk_2_S_in ( clk_2_wires[127] ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_10102 ) , - .clk_2_N_out ( clk_2_wires[128] ) , .clk_3_S_in ( p1948 ) , - .clk_3_N_in ( p243 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_10103 ) , + .clk_2_N_out ( clk_2_wires[128] ) , .clk_3_S_in ( p1938 ) , + .clk_3_N_in ( p102 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_10103 ) , .clk_3_S_out ( SYNOPSYS_UNCONNECTED_10104 ) ) ; cby_1__1_ cby_11__10_ ( .pReset ( { SYNOPSYS_UNCONNECTED_10105 } ) , @@ -131867,15 +136389,15 @@ cby_1__1_ cby_11__10_ ( .prog_clk_0_W_in ( prog_clk_0_wires[433] ) , .prog_clk_0_S_out ( prog_clk_0_wires[434] ) , .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_10115 ) , - .prog_clk_2_N_in ( p2975 ) , .prog_clk_2_S_in ( p324 ) , + .prog_clk_2_N_in ( p1535 ) , .prog_clk_2_S_in ( p877 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_10116 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_10117 ) , - .prog_clk_3_S_in ( p2858 ) , .prog_clk_3_N_in ( p2890 ) , + .prog_clk_3_S_in ( p2784 ) , .prog_clk_3_N_in ( p986 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_10118 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_10119 ) , .clk_2_N_in ( p3263 ) , - .clk_2_S_in ( p3208 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_10120 ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_10121 ) , .clk_3_S_in ( p3265 ) , - .clk_3_N_in ( p3227 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_10122 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_10119 ) , .clk_2_N_in ( p2602 ) , + .clk_2_S_in ( p2689 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_10120 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_10121 ) , .clk_3_S_in ( p2842 ) , + .clk_3_N_in ( p2452 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_10122 ) , .clk_3_S_out ( SYNOPSYS_UNCONNECTED_10123 ) ) ; cby_1__1_ cby_11__11_ ( .pReset ( { SYNOPSYS_UNCONNECTED_10124 } ) , @@ -131920,15 +136442,15 @@ cby_1__1_ cby_11__11_ ( .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_10135 ) , .prog_clk_2_S_in ( prog_clk_2_wires[134] ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_10136 ) , - .prog_clk_2_N_out ( prog_clk_2_wires[135] ) , .prog_clk_3_S_in ( p1295 ) , - .prog_clk_3_N_in ( p852 ) , + .prog_clk_2_N_out ( prog_clk_2_wires[135] ) , .prog_clk_3_S_in ( p1463 ) , + .prog_clk_3_N_in ( p978 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_10137 ) , .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_10138 ) , .clk_2_N_in ( SYNOPSYS_UNCONNECTED_10139 ) , .clk_2_S_in ( clk_2_wires[134] ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_10140 ) , - .clk_2_N_out ( clk_2_wires[135] ) , .clk_3_S_in ( p1295 ) , - .clk_3_N_in ( p22 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_10141 ) , + .clk_2_N_out ( clk_2_wires[135] ) , .clk_3_S_in ( p1463 ) , + .clk_3_N_in ( p771 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_10141 ) , .clk_3_S_out ( SYNOPSYS_UNCONNECTED_10142 ) ) ; cby_1__1_ cby_11__12_ ( .pReset ( { SYNOPSYS_UNCONNECTED_10143 } ) , @@ -131969,16 +136491,16 @@ cby_1__1_ cby_11__12_ ( .Reset_E_out ( ResetWires[287] ) , .prog_clk_0_W_in ( prog_clk_0_wires[439] ) , .prog_clk_0_S_out ( prog_clk_0_wires[440] ) , - .prog_clk_0_N_out ( prog_clk_0_wires[442] ) , .prog_clk_2_N_in ( p1455 ) , - .prog_clk_2_S_in ( p496 ) , + .prog_clk_0_N_out ( prog_clk_0_wires[442] ) , .prog_clk_2_N_in ( p1598 ) , + .prog_clk_2_S_in ( p616 ) , .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_10153 ) , .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_10154 ) , - .prog_clk_3_S_in ( p2993 ) , .prog_clk_3_N_in ( p965 ) , + .prog_clk_3_S_in ( p2362 ) , .prog_clk_3_N_in ( p22 ) , .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_10155 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_10156 ) , .clk_2_N_in ( p2623 ) , - .clk_2_S_in ( p3013 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_10157 ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_10158 ) , .clk_3_S_in ( p3056 ) , - .clk_3_N_in ( p2529 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_10159 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_10156 ) , .clk_2_N_in ( p3022 ) , + .clk_2_S_in ( p2461 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_10157 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_10158 ) , .clk_3_S_in ( p2616 ) , + .clk_3_N_in ( p2901 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_10159 ) , .clk_3_S_out ( SYNOPSYS_UNCONNECTED_10160 ) ) ; cby_2__1_ cby_12__1_ ( .pReset ( { SYNOPSYS_UNCONNECTED_10161 } ) , @@ -135152,7 +139674,63 @@ fpga_core fpga_core_uut ( .pReset ( io_in[3] ) , .prog_clk ( io_in[37] ) , .p3502 ( optlc_net_3522 ) , .p3503 ( optlc_net_3523 ) , .p3504 ( optlc_net_3524 ) , .p3505 ( optlc_net_3525 ) , .p3506 ( optlc_net_3526 ) , .p3507 ( optlc_net_3527 ) , - .p3508 ( optlc_net_3528 ) , .p3509 ( optlc_net_3529 ) ) ; + .p3508 ( optlc_net_3528 ) , .p3509 ( optlc_net_3529 ) , + .p3510 ( optlc_net_3530 ) , .p3511 ( optlc_net_3531 ) , + .p3512 ( optlc_net_3532 ) , .p3513 ( optlc_net_3533 ) , + .p3514 ( optlc_net_3534 ) , .p3515 ( optlc_net_3535 ) , + .p3516 ( optlc_net_3536 ) , .p3517 ( optlc_net_3537 ) , + .p3518 ( optlc_net_3538 ) , .p3519 ( optlc_net_3539 ) , + .p3520 ( optlc_net_3540 ) , .p3521 ( optlc_net_3541 ) , + .p3522 ( optlc_net_3542 ) , .p3523 ( optlc_net_3543 ) , + .p3524 ( optlc_net_3544 ) , .p3525 ( optlc_net_3545 ) , + .p3526 ( optlc_net_3546 ) , .p3527 ( optlc_net_3547 ) , + .p3528 ( optlc_net_3548 ) , .p3529 ( optlc_net_3549 ) , + .p3530 ( optlc_net_3550 ) , .p3531 ( optlc_net_3551 ) , + .p3532 ( optlc_net_3552 ) , .p3533 ( optlc_net_3553 ) , + .p3534 ( optlc_net_3554 ) , .p3535 ( optlc_net_3555 ) , + .p3536 ( optlc_net_3556 ) , .p3537 ( optlc_net_3557 ) , + .p3538 ( optlc_net_3558 ) , .p3539 ( optlc_net_3559 ) , + .p3540 ( optlc_net_3560 ) , .p3541 ( optlc_net_3561 ) , + .p3542 ( optlc_net_3562 ) , .p3543 ( optlc_net_3563 ) , + .p3544 ( optlc_net_3564 ) , .p3545 ( optlc_net_3565 ) , + .p3546 ( optlc_net_3566 ) , .p3547 ( optlc_net_3567 ) , + .p3548 ( optlc_net_3568 ) , .p3549 ( optlc_net_3569 ) , + .p3550 ( optlc_net_3570 ) , .p3551 ( optlc_net_3571 ) , + .p3552 ( optlc_net_3572 ) , .p3553 ( optlc_net_3573 ) , + .p3554 ( optlc_net_3574 ) , .p3555 ( optlc_net_3575 ) , + .p3556 ( optlc_net_3576 ) , .p3557 ( optlc_net_3577 ) , + .p3558 ( optlc_net_3578 ) , .p3559 ( optlc_net_3579 ) , + .p3560 ( optlc_net_3580 ) , .p3561 ( optlc_net_3581 ) , + .p3562 ( optlc_net_3582 ) , .p3563 ( optlc_net_3583 ) , + .p3564 ( optlc_net_3584 ) , .p3565 ( optlc_net_3585 ) , + .p3566 ( optlc_net_3586 ) , .p3567 ( optlc_net_3587 ) , + .p3568 ( optlc_net_3588 ) , .p3569 ( optlc_net_3589 ) , + .p3570 ( optlc_net_3590 ) , .p3571 ( optlc_net_3591 ) , + .p3572 ( optlc_net_3592 ) , .p3573 ( optlc_net_3593 ) , + .p3574 ( optlc_net_3594 ) , .p3575 ( optlc_net_3595 ) , + .p3576 ( optlc_net_3596 ) , .p3577 ( optlc_net_3597 ) , + .p3578 ( optlc_net_3598 ) , .p3579 ( optlc_net_3599 ) , + .p3580 ( optlc_net_3600 ) , .p3581 ( optlc_net_3601 ) , + .p3582 ( optlc_net_3602 ) , .p3583 ( optlc_net_3603 ) , + .p3584 ( optlc_net_3604 ) , .p3585 ( optlc_net_3605 ) , + .p3586 ( optlc_net_3606 ) , .p3587 ( optlc_net_3607 ) , + .p3588 ( optlc_net_3608 ) , .p3589 ( optlc_net_3609 ) , + .p3590 ( optlc_net_3610 ) , .p3591 ( optlc_net_3611 ) , + .p3592 ( optlc_net_3612 ) , .p3593 ( optlc_net_3613 ) , + .p3594 ( optlc_net_3614 ) , .p3595 ( optlc_net_3615 ) , + .p3596 ( optlc_net_3616 ) , .p3597 ( optlc_net_3617 ) , + .p3598 ( optlc_net_3618 ) , .p3599 ( optlc_net_3619 ) , + .p3600 ( optlc_net_3620 ) , .p3601 ( optlc_net_3621 ) , + .p3602 ( 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optlc_543 ( .LO ( optlc_net_542 ) , .HI ( SYNOPSYS_UNCONNECTED_544 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_545 ( .LO ( optlc_net_543 ) , +sky130_fd_sc_hd__conb_1 optlc_544 ( .LO ( optlc_net_543 ) , .HI ( SYNOPSYS_UNCONNECTED_545 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_546 ( .LO ( optlc_net_544 ) , +sky130_fd_sc_hd__conb_1 optlc_545 ( .LO ( optlc_net_544 ) , .HI ( SYNOPSYS_UNCONNECTED_546 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_547 ( .LO ( optlc_net_545 ) , +sky130_fd_sc_hd__conb_1 optlc_546 ( .LO ( optlc_net_545 ) , .HI ( SYNOPSYS_UNCONNECTED_547 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_548 ( .LO ( optlc_net_546 ) , +sky130_fd_sc_hd__conb_1 optlc_547 ( .LO ( optlc_net_546 ) , .HI ( SYNOPSYS_UNCONNECTED_548 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_549 ( .LO ( optlc_net_547 ) , +sky130_fd_sc_hd__conb_1 optlc_548 ( .LO ( optlc_net_547 ) , .HI ( SYNOPSYS_UNCONNECTED_549 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_550 ( .LO ( optlc_net_548 ) , +sky130_fd_sc_hd__conb_1 optlc_549 ( .LO ( optlc_net_548 ) , .HI ( SYNOPSYS_UNCONNECTED_550 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_551 ( .LO ( optlc_net_549 ) , +sky130_fd_sc_hd__conb_1 optlc_550 ( .LO ( optlc_net_549 ) , .HI ( SYNOPSYS_UNCONNECTED_551 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_552 ( .LO ( optlc_net_550 ) , +sky130_fd_sc_hd__conb_1 optlc_551 ( .LO ( optlc_net_550 ) , .HI ( SYNOPSYS_UNCONNECTED_552 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_553 ( .LO ( optlc_net_551 ) , +sky130_fd_sc_hd__conb_1 optlc_552 ( .LO ( optlc_net_551 ) , .HI ( SYNOPSYS_UNCONNECTED_553 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_554 ( .LO ( optlc_net_552 ) , +sky130_fd_sc_hd__conb_1 optlc_553 ( .LO ( optlc_net_552 ) , .HI ( SYNOPSYS_UNCONNECTED_554 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_555 ( .LO ( optlc_net_553 ) , +sky130_fd_sc_hd__conb_1 optlc_554 ( .LO ( optlc_net_553 ) , .HI ( SYNOPSYS_UNCONNECTED_555 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_556 ( .LO ( optlc_net_554 ) , +sky130_fd_sc_hd__conb_1 optlc_555 ( .LO ( optlc_net_554 ) , .HI ( SYNOPSYS_UNCONNECTED_556 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_557 ( .LO ( optlc_net_555 ) , +sky130_fd_sc_hd__conb_1 optlc_556 ( .LO ( optlc_net_555 ) , .HI ( SYNOPSYS_UNCONNECTED_557 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_558 ( .LO ( optlc_net_556 ) , +sky130_fd_sc_hd__conb_1 optlc_557 ( .LO ( optlc_net_556 ) , .HI ( SYNOPSYS_UNCONNECTED_558 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_559 ( .LO ( optlc_net_557 ) , +sky130_fd_sc_hd__conb_1 optlc_558 ( .LO ( optlc_net_557 ) , .HI ( SYNOPSYS_UNCONNECTED_559 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_561 ( .LO ( optlc_net_558 ) , +sky130_fd_sc_hd__conb_1 optlc_559 ( .LO ( optlc_net_558 ) , .HI ( SYNOPSYS_UNCONNECTED_560 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_562 ( .LO ( optlc_net_559 ) , +sky130_fd_sc_hd__conb_1 optlc_560 ( .LO ( optlc_net_559 ) , .HI ( SYNOPSYS_UNCONNECTED_561 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_563 ( .LO ( optlc_net_560 ) , +sky130_fd_sc_hd__conb_1 optlc_561 ( .LO ( optlc_net_560 ) , .HI ( SYNOPSYS_UNCONNECTED_562 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_564 ( .LO ( optlc_net_561 ) , +sky130_fd_sc_hd__conb_1 optlc_562 ( .LO ( optlc_net_561 ) , .HI ( SYNOPSYS_UNCONNECTED_563 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_565 ( .LO ( optlc_net_562 ) , +sky130_fd_sc_hd__conb_1 optlc_563 ( .LO ( optlc_net_562 ) , .HI ( SYNOPSYS_UNCONNECTED_564 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_566 ( .LO ( optlc_net_563 ) , +sky130_fd_sc_hd__conb_1 optlc_564 ( .LO ( optlc_net_563 ) , .HI ( SYNOPSYS_UNCONNECTED_565 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_567 ( .LO ( optlc_net_564 ) , +sky130_fd_sc_hd__conb_1 optlc_565 ( .LO ( optlc_net_564 ) , .HI ( SYNOPSYS_UNCONNECTED_566 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_568 ( .LO ( optlc_net_565 ) , +sky130_fd_sc_hd__conb_1 optlc_566 ( .LO ( optlc_net_565 ) , .HI ( SYNOPSYS_UNCONNECTED_567 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_569 ( .LO ( optlc_net_566 ) , +sky130_fd_sc_hd__conb_1 optlc_567 ( .LO ( optlc_net_566 ) , .HI ( SYNOPSYS_UNCONNECTED_568 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_570 ( .LO ( optlc_net_567 ) , +sky130_fd_sc_hd__conb_1 optlc_568 ( .LO ( optlc_net_567 ) , .HI ( SYNOPSYS_UNCONNECTED_569 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_571 ( .LO ( optlc_net_568 ) , +sky130_fd_sc_hd__conb_1 optlc_569 ( .LO ( optlc_net_568 ) , .HI ( SYNOPSYS_UNCONNECTED_570 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_572 ( .LO ( optlc_net_569 ) , +sky130_fd_sc_hd__conb_1 optlc_570 ( .LO ( optlc_net_569 ) , .HI ( SYNOPSYS_UNCONNECTED_571 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_573 ( .LO ( optlc_net_570 ) , +sky130_fd_sc_hd__conb_1 optlc_571 ( .LO ( optlc_net_570 ) , .HI ( SYNOPSYS_UNCONNECTED_572 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_574 ( .LO ( optlc_net_571 ) , +sky130_fd_sc_hd__conb_1 optlc_572 ( .LO ( optlc_net_571 ) , .HI ( SYNOPSYS_UNCONNECTED_573 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_575 ( .LO ( optlc_net_572 ) , +sky130_fd_sc_hd__conb_1 optlc_573 ( .LO ( optlc_net_572 ) , .HI ( SYNOPSYS_UNCONNECTED_574 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_576 ( .LO ( optlc_net_573 ) , +sky130_fd_sc_hd__conb_1 optlc_574 ( .LO ( optlc_net_573 ) , .HI ( SYNOPSYS_UNCONNECTED_575 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_577 ( .LO ( optlc_net_574 ) , +sky130_fd_sc_hd__conb_1 optlc_575 ( .LO ( optlc_net_574 ) , .HI ( SYNOPSYS_UNCONNECTED_576 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_578 ( .LO ( optlc_net_575 ) , +sky130_fd_sc_hd__conb_1 optlc_576 ( .LO ( optlc_net_575 ) , .HI ( SYNOPSYS_UNCONNECTED_577 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_579 ( .LO ( optlc_net_576 ) , +sky130_fd_sc_hd__conb_1 optlc_577 ( .LO ( optlc_net_576 ) , .HI ( SYNOPSYS_UNCONNECTED_578 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_580 ( .LO ( optlc_net_577 ) , +sky130_fd_sc_hd__conb_1 optlc_578 ( .LO ( optlc_net_577 ) , .HI ( SYNOPSYS_UNCONNECTED_579 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_581 ( .LO ( optlc_net_578 ) , +sky130_fd_sc_hd__conb_1 optlc_579 ( .LO ( optlc_net_578 ) , .HI ( SYNOPSYS_UNCONNECTED_580 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_582 ( .LO ( optlc_net_579 ) , +sky130_fd_sc_hd__conb_1 optlc_580 ( .LO ( optlc_net_579 ) , .HI ( SYNOPSYS_UNCONNECTED_581 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_583 ( .LO ( optlc_net_580 ) , +sky130_fd_sc_hd__conb_1 optlc_581 ( .LO ( optlc_net_580 ) , .HI ( SYNOPSYS_UNCONNECTED_582 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_584 ( .LO ( optlc_net_581 ) , +sky130_fd_sc_hd__conb_1 optlc_582 ( .LO ( optlc_net_581 ) , .HI ( SYNOPSYS_UNCONNECTED_583 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_585 ( .LO ( optlc_net_582 ) , +sky130_fd_sc_hd__conb_1 optlc_583 ( .LO ( optlc_net_582 ) , .HI ( SYNOPSYS_UNCONNECTED_584 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_586 ( .LO ( optlc_net_583 ) , +sky130_fd_sc_hd__conb_1 optlc_584 ( .LO ( optlc_net_583 ) , .HI ( SYNOPSYS_UNCONNECTED_585 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_587 ( .LO ( optlc_net_584 ) , +sky130_fd_sc_hd__conb_1 optlc_585 ( .LO ( optlc_net_584 ) , .HI ( SYNOPSYS_UNCONNECTED_586 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_588 ( .LO ( optlc_net_585 ) , +sky130_fd_sc_hd__conb_1 optlc_586 ( .LO ( optlc_net_585 ) , .HI ( SYNOPSYS_UNCONNECTED_587 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_589 ( .LO ( optlc_net_586 ) , +sky130_fd_sc_hd__conb_1 optlc_587 ( .LO ( optlc_net_586 ) , .HI ( SYNOPSYS_UNCONNECTED_588 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_590 ( .LO ( optlc_net_587 ) , +sky130_fd_sc_hd__conb_1 optlc_588 ( .LO ( optlc_net_587 ) , .HI ( SYNOPSYS_UNCONNECTED_589 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_591 ( .LO ( optlc_net_588 ) , +sky130_fd_sc_hd__conb_1 optlc_589 ( .LO ( optlc_net_588 ) , .HI ( SYNOPSYS_UNCONNECTED_590 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_592 ( .LO ( optlc_net_589 ) , +sky130_fd_sc_hd__conb_1 optlc_590 ( .LO ( optlc_net_589 ) , .HI ( SYNOPSYS_UNCONNECTED_591 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_593 ( .LO ( optlc_net_590 ) , +sky130_fd_sc_hd__conb_1 optlc_591 ( .LO ( optlc_net_590 ) , .HI ( SYNOPSYS_UNCONNECTED_592 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_594 ( .LO ( optlc_net_591 ) , +sky130_fd_sc_hd__conb_1 optlc_592 ( .LO ( optlc_net_591 ) , .HI ( SYNOPSYS_UNCONNECTED_593 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_595 ( .LO ( optlc_net_592 ) , +sky130_fd_sc_hd__conb_1 optlc_593 ( .LO ( optlc_net_592 ) , .HI ( SYNOPSYS_UNCONNECTED_594 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_596 ( .LO ( optlc_net_593 ) , +sky130_fd_sc_hd__conb_1 optlc_594 ( .LO ( optlc_net_593 ) , .HI ( SYNOPSYS_UNCONNECTED_595 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_597 ( .LO ( optlc_net_594 ) , +sky130_fd_sc_hd__conb_1 optlc_595 ( .LO ( optlc_net_594 ) , .HI ( SYNOPSYS_UNCONNECTED_596 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_598 ( .LO ( optlc_net_595 ) , +sky130_fd_sc_hd__conb_1 optlc_596 ( .LO ( optlc_net_595 ) , .HI ( SYNOPSYS_UNCONNECTED_597 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_599 ( .LO ( optlc_net_596 ) , +sky130_fd_sc_hd__conb_1 optlc_597 ( .LO ( optlc_net_596 ) , .HI ( SYNOPSYS_UNCONNECTED_598 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_600 ( .LO ( optlc_net_597 ) , +sky130_fd_sc_hd__conb_1 optlc_598 ( .LO ( optlc_net_597 ) , .HI ( SYNOPSYS_UNCONNECTED_599 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_601 ( .LO ( optlc_net_598 ) , +sky130_fd_sc_hd__conb_1 optlc_599 ( .LO ( optlc_net_598 ) , .HI ( SYNOPSYS_UNCONNECTED_600 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_602 ( .LO ( optlc_net_599 ) , +sky130_fd_sc_hd__conb_1 optlc_600 ( .LO ( optlc_net_599 ) , .HI ( SYNOPSYS_UNCONNECTED_601 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_603 ( .LO ( optlc_net_600 ) , +sky130_fd_sc_hd__conb_1 optlc_601 ( .LO ( optlc_net_600 ) , .HI ( SYNOPSYS_UNCONNECTED_602 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_604 ( .LO ( optlc_net_601 ) , +sky130_fd_sc_hd__conb_1 optlc_602 ( .LO ( optlc_net_601 ) , .HI ( SYNOPSYS_UNCONNECTED_603 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_605 ( .LO ( optlc_net_602 ) , +sky130_fd_sc_hd__conb_1 optlc_603 ( .LO ( optlc_net_602 ) , .HI ( SYNOPSYS_UNCONNECTED_604 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_606 ( .LO ( optlc_net_603 ) , +sky130_fd_sc_hd__conb_1 optlc_604 ( .LO ( optlc_net_603 ) , .HI ( SYNOPSYS_UNCONNECTED_605 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_607 ( .LO ( optlc_net_604 ) , +sky130_fd_sc_hd__conb_1 optlc_605 ( .LO ( optlc_net_604 ) , .HI ( SYNOPSYS_UNCONNECTED_606 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_608 ( .LO ( optlc_net_605 ) , +sky130_fd_sc_hd__conb_1 optlc_606 ( .LO ( optlc_net_605 ) , .HI ( SYNOPSYS_UNCONNECTED_607 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_609 ( .LO ( optlc_net_606 ) , +sky130_fd_sc_hd__conb_1 optlc_607 ( .LO ( optlc_net_606 ) , .HI ( SYNOPSYS_UNCONNECTED_608 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_610 ( .LO ( optlc_net_607 ) , +sky130_fd_sc_hd__conb_1 optlc_608 ( .LO ( optlc_net_607 ) , .HI ( SYNOPSYS_UNCONNECTED_609 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_611 ( .LO ( optlc_net_608 ) , +sky130_fd_sc_hd__conb_1 optlc_609 ( .LO ( optlc_net_608 ) , .HI ( SYNOPSYS_UNCONNECTED_610 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_612 ( .LO ( optlc_net_609 ) , +sky130_fd_sc_hd__conb_1 optlc_610 ( .LO ( optlc_net_609 ) , .HI ( SYNOPSYS_UNCONNECTED_611 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_613 ( .LO ( optlc_net_610 ) , +sky130_fd_sc_hd__conb_1 optlc_611 ( .LO ( optlc_net_610 ) , .HI ( SYNOPSYS_UNCONNECTED_612 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_614 ( .LO ( optlc_net_611 ) , +sky130_fd_sc_hd__conb_1 optlc_612 ( .LO ( optlc_net_611 ) , .HI ( SYNOPSYS_UNCONNECTED_613 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_615 ( .LO ( optlc_net_612 ) , +sky130_fd_sc_hd__conb_1 optlc_613 ( .LO ( optlc_net_612 ) , .HI ( SYNOPSYS_UNCONNECTED_614 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_616 ( .LO ( optlc_net_613 ) , +sky130_fd_sc_hd__conb_1 optlc_614 ( .LO ( optlc_net_613 ) , .HI ( SYNOPSYS_UNCONNECTED_615 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_617 ( .LO ( optlc_net_614 ) , +sky130_fd_sc_hd__conb_1 optlc_615 ( .LO ( optlc_net_614 ) , .HI ( SYNOPSYS_UNCONNECTED_616 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_618 ( .LO ( optlc_net_615 ) , +sky130_fd_sc_hd__conb_1 optlc_616 ( .LO ( optlc_net_615 ) , .HI ( SYNOPSYS_UNCONNECTED_617 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_619 ( .LO ( optlc_net_616 ) , +sky130_fd_sc_hd__conb_1 optlc_617 ( .LO ( optlc_net_616 ) , .HI ( SYNOPSYS_UNCONNECTED_618 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_620 ( .LO ( optlc_net_617 ) , +sky130_fd_sc_hd__conb_1 optlc_618 ( .LO ( optlc_net_617 ) , .HI ( SYNOPSYS_UNCONNECTED_619 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_621 ( .LO ( optlc_net_618 ) , +sky130_fd_sc_hd__conb_1 optlc_619 ( .LO ( optlc_net_618 ) , .HI ( SYNOPSYS_UNCONNECTED_620 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_622 ( .LO ( optlc_net_619 ) , +sky130_fd_sc_hd__conb_1 optlc_620 ( .LO ( optlc_net_619 ) , .HI ( SYNOPSYS_UNCONNECTED_621 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_623 ( .LO ( optlc_net_620 ) , +sky130_fd_sc_hd__conb_1 optlc_621 ( .LO ( optlc_net_620 ) , .HI ( SYNOPSYS_UNCONNECTED_622 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_624 ( .LO ( optlc_net_621 ) , +sky130_fd_sc_hd__conb_1 optlc_622 ( .LO ( optlc_net_621 ) , .HI ( SYNOPSYS_UNCONNECTED_623 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_625 ( .LO ( optlc_net_622 ) , +sky130_fd_sc_hd__conb_1 optlc_623 ( .LO ( optlc_net_622 ) , .HI ( SYNOPSYS_UNCONNECTED_624 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_626 ( .LO ( optlc_net_623 ) , +sky130_fd_sc_hd__conb_1 optlc_624 ( .LO ( optlc_net_623 ) , .HI ( SYNOPSYS_UNCONNECTED_625 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_627 ( .LO ( optlc_net_624 ) , +sky130_fd_sc_hd__conb_1 optlc_625 ( .LO ( optlc_net_624 ) , .HI ( SYNOPSYS_UNCONNECTED_626 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_628 ( .LO ( optlc_net_625 ) , +sky130_fd_sc_hd__conb_1 optlc_626 ( .LO ( optlc_net_625 ) , .HI ( SYNOPSYS_UNCONNECTED_627 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_629 ( .LO ( optlc_net_626 ) , +sky130_fd_sc_hd__conb_1 optlc_627 ( .LO ( optlc_net_626 ) , .HI ( SYNOPSYS_UNCONNECTED_628 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_630 ( .LO ( optlc_net_627 ) , +sky130_fd_sc_hd__conb_1 optlc_628 ( .LO ( optlc_net_627 ) , .HI ( SYNOPSYS_UNCONNECTED_629 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_631 ( .LO ( optlc_net_628 ) , +sky130_fd_sc_hd__conb_1 optlc_629 ( .LO ( optlc_net_628 ) , .HI ( SYNOPSYS_UNCONNECTED_630 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_632 ( .LO ( optlc_net_629 ) , +sky130_fd_sc_hd__conb_1 optlc_630 ( .LO ( optlc_net_629 ) , .HI ( SYNOPSYS_UNCONNECTED_631 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_633 ( .LO ( optlc_net_630 ) , +sky130_fd_sc_hd__conb_1 optlc_631 ( .LO ( optlc_net_630 ) , .HI ( SYNOPSYS_UNCONNECTED_632 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_634 ( .LO ( optlc_net_631 ) , +sky130_fd_sc_hd__conb_1 optlc_632 ( .LO ( optlc_net_631 ) , .HI ( SYNOPSYS_UNCONNECTED_633 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_635 ( .LO ( optlc_net_632 ) , +sky130_fd_sc_hd__conb_1 optlc_633 ( .LO ( optlc_net_632 ) , .HI ( SYNOPSYS_UNCONNECTED_634 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_636 ( .LO ( optlc_net_633 ) , +sky130_fd_sc_hd__conb_1 optlc_634 ( .LO ( optlc_net_633 ) , .HI ( SYNOPSYS_UNCONNECTED_635 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_637 ( .LO ( optlc_net_634 ) , +sky130_fd_sc_hd__conb_1 optlc_635 ( .LO ( optlc_net_634 ) , .HI ( SYNOPSYS_UNCONNECTED_636 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_638 ( .LO ( optlc_net_635 ) , +sky130_fd_sc_hd__conb_1 optlc_636 ( .LO ( optlc_net_635 ) , .HI ( SYNOPSYS_UNCONNECTED_637 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_639 ( .LO ( optlc_net_636 ) , +sky130_fd_sc_hd__conb_1 optlc_637 ( .LO ( optlc_net_636 ) , .HI ( SYNOPSYS_UNCONNECTED_638 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_640 ( .LO ( optlc_net_637 ) , +sky130_fd_sc_hd__conb_1 optlc_638 ( .LO ( optlc_net_637 ) , .HI ( SYNOPSYS_UNCONNECTED_639 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_641 ( .LO ( optlc_net_638 ) , +sky130_fd_sc_hd__conb_1 optlc_639 ( .LO ( optlc_net_638 ) , .HI ( SYNOPSYS_UNCONNECTED_640 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_642 ( .LO ( optlc_net_639 ) , +sky130_fd_sc_hd__conb_1 optlc_640 ( .LO ( optlc_net_639 ) , .HI ( SYNOPSYS_UNCONNECTED_641 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_643 ( .LO ( optlc_net_640 ) , +sky130_fd_sc_hd__conb_1 optlc_641 ( .LO ( optlc_net_640 ) , .HI ( SYNOPSYS_UNCONNECTED_642 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_644 ( .LO ( optlc_net_641 ) , +sky130_fd_sc_hd__conb_1 optlc_642 ( .LO ( optlc_net_641 ) , .HI ( SYNOPSYS_UNCONNECTED_643 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_645 ( .LO ( optlc_net_642 ) , +sky130_fd_sc_hd__conb_1 optlc_643 ( .LO ( optlc_net_642 ) , .HI ( SYNOPSYS_UNCONNECTED_644 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_646 ( .LO ( optlc_net_643 ) , +sky130_fd_sc_hd__conb_1 optlc_644 ( .LO ( optlc_net_643 ) , .HI ( SYNOPSYS_UNCONNECTED_645 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_647 ( .LO ( optlc_net_644 ) , +sky130_fd_sc_hd__conb_1 optlc_645 ( .LO ( optlc_net_644 ) , .HI ( SYNOPSYS_UNCONNECTED_646 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_648 ( .LO ( optlc_net_645 ) , +sky130_fd_sc_hd__conb_1 optlc_646 ( .LO ( optlc_net_645 ) , .HI ( SYNOPSYS_UNCONNECTED_647 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_649 ( .LO ( optlc_net_646 ) , +sky130_fd_sc_hd__conb_1 optlc_647 ( .LO ( optlc_net_646 ) , .HI ( SYNOPSYS_UNCONNECTED_648 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_650 ( .LO ( optlc_net_647 ) , +sky130_fd_sc_hd__conb_1 optlc_648 ( .LO ( optlc_net_647 ) , .HI ( SYNOPSYS_UNCONNECTED_649 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_651 ( .LO ( optlc_net_648 ) , +sky130_fd_sc_hd__conb_1 optlc_649 ( .LO ( optlc_net_648 ) , .HI ( SYNOPSYS_UNCONNECTED_650 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_652 ( .LO ( optlc_net_649 ) , +sky130_fd_sc_hd__conb_1 optlc_650 ( .LO ( optlc_net_649 ) , .HI ( SYNOPSYS_UNCONNECTED_651 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_653 ( .LO ( optlc_net_650 ) , +sky130_fd_sc_hd__conb_1 optlc_651 ( .LO ( optlc_net_650 ) , .HI ( SYNOPSYS_UNCONNECTED_652 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_654 ( .LO ( optlc_net_651 ) , +sky130_fd_sc_hd__conb_1 optlc_652 ( .LO ( optlc_net_651 ) , .HI ( SYNOPSYS_UNCONNECTED_653 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_655 ( .LO ( optlc_net_652 ) , +sky130_fd_sc_hd__conb_1 optlc_653 ( .LO ( optlc_net_652 ) , .HI ( SYNOPSYS_UNCONNECTED_654 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_656 ( .LO ( optlc_net_653 ) , +sky130_fd_sc_hd__conb_1 optlc_654 ( .LO ( optlc_net_653 ) , .HI ( SYNOPSYS_UNCONNECTED_655 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_657 ( .LO ( optlc_net_654 ) , +sky130_fd_sc_hd__conb_1 optlc_655 ( .LO ( optlc_net_654 ) , .HI ( SYNOPSYS_UNCONNECTED_656 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_658 ( .LO ( optlc_net_655 ) , +sky130_fd_sc_hd__conb_1 optlc_656 ( .LO ( optlc_net_655 ) , .HI ( SYNOPSYS_UNCONNECTED_657 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_659 ( .LO ( optlc_net_656 ) , +sky130_fd_sc_hd__conb_1 optlc_657 ( .LO ( optlc_net_656 ) , .HI ( SYNOPSYS_UNCONNECTED_658 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_660 ( .LO ( optlc_net_657 ) , +sky130_fd_sc_hd__conb_1 optlc_658 ( .LO ( optlc_net_657 ) , .HI ( SYNOPSYS_UNCONNECTED_659 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_661 ( .LO ( optlc_net_658 ) , +sky130_fd_sc_hd__conb_1 optlc_659 ( .LO ( optlc_net_658 ) , .HI ( SYNOPSYS_UNCONNECTED_660 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_662 ( .LO ( optlc_net_659 ) , +sky130_fd_sc_hd__conb_1 optlc_660 ( .LO ( optlc_net_659 ) , .HI ( SYNOPSYS_UNCONNECTED_661 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_663 ( .LO ( optlc_net_660 ) , +sky130_fd_sc_hd__conb_1 optlc_661 ( .LO ( optlc_net_660 ) , .HI ( SYNOPSYS_UNCONNECTED_662 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_664 ( .LO ( optlc_net_661 ) , +sky130_fd_sc_hd__conb_1 optlc_662 ( .LO ( optlc_net_661 ) , .HI ( SYNOPSYS_UNCONNECTED_663 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_665 ( .LO ( optlc_net_662 ) , +sky130_fd_sc_hd__conb_1 optlc_663 ( .LO ( optlc_net_662 ) , .HI ( SYNOPSYS_UNCONNECTED_664 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_666 ( .LO ( optlc_net_663 ) , +sky130_fd_sc_hd__conb_1 optlc_664 ( .LO ( optlc_net_663 ) , .HI ( SYNOPSYS_UNCONNECTED_665 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_667 ( .LO ( optlc_net_664 ) , +sky130_fd_sc_hd__conb_1 optlc_665 ( .LO ( optlc_net_664 ) , .HI ( SYNOPSYS_UNCONNECTED_666 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_668 ( .LO ( optlc_net_665 ) , +sky130_fd_sc_hd__conb_1 optlc_666 ( .LO ( optlc_net_665 ) , .HI ( SYNOPSYS_UNCONNECTED_667 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_669 ( .LO ( optlc_net_666 ) , +sky130_fd_sc_hd__conb_1 optlc_667 ( .LO ( optlc_net_666 ) , .HI ( SYNOPSYS_UNCONNECTED_668 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_670 ( .LO ( optlc_net_667 ) , +sky130_fd_sc_hd__conb_1 optlc_668 ( .LO ( optlc_net_667 ) , .HI ( SYNOPSYS_UNCONNECTED_669 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_671 ( .LO ( optlc_net_668 ) , +sky130_fd_sc_hd__conb_1 optlc_669 ( .LO ( optlc_net_668 ) , .HI ( SYNOPSYS_UNCONNECTED_670 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_672 ( .LO ( optlc_net_669 ) , +sky130_fd_sc_hd__conb_1 optlc_670 ( .LO ( optlc_net_669 ) , .HI ( SYNOPSYS_UNCONNECTED_671 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_673 ( .LO ( optlc_net_670 ) , +sky130_fd_sc_hd__conb_1 optlc_671 ( .LO ( optlc_net_670 ) , .HI ( SYNOPSYS_UNCONNECTED_672 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_674 ( .LO ( optlc_net_671 ) , +sky130_fd_sc_hd__conb_1 optlc_672 ( .LO ( optlc_net_671 ) , .HI ( SYNOPSYS_UNCONNECTED_673 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_675 ( .LO ( optlc_net_672 ) , +sky130_fd_sc_hd__conb_1 optlc_673 ( .LO ( optlc_net_672 ) , .HI ( SYNOPSYS_UNCONNECTED_674 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_676 ( .LO ( optlc_net_673 ) , +sky130_fd_sc_hd__conb_1 optlc_674 ( .LO ( optlc_net_673 ) , .HI ( SYNOPSYS_UNCONNECTED_675 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_677 ( .LO ( optlc_net_674 ) , +sky130_fd_sc_hd__conb_1 optlc_675 ( .LO ( optlc_net_674 ) , .HI ( SYNOPSYS_UNCONNECTED_676 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_678 ( .LO ( optlc_net_675 ) , +sky130_fd_sc_hd__conb_1 optlc_676 ( .LO ( optlc_net_675 ) , .HI ( SYNOPSYS_UNCONNECTED_677 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_679 ( .LO ( optlc_net_676 ) , +sky130_fd_sc_hd__conb_1 optlc_677 ( .LO ( optlc_net_676 ) , .HI ( SYNOPSYS_UNCONNECTED_678 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_680 ( .LO ( optlc_net_677 ) , +sky130_fd_sc_hd__conb_1 optlc_678 ( .LO ( optlc_net_677 ) , .HI ( SYNOPSYS_UNCONNECTED_679 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_681 ( .LO ( optlc_net_678 ) , +sky130_fd_sc_hd__conb_1 optlc_679 ( .LO ( optlc_net_678 ) , .HI ( SYNOPSYS_UNCONNECTED_680 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_682 ( .LO ( optlc_net_679 ) , +sky130_fd_sc_hd__conb_1 optlc_680 ( .LO ( optlc_net_679 ) , .HI ( SYNOPSYS_UNCONNECTED_681 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_683 ( .LO ( optlc_net_680 ) , +sky130_fd_sc_hd__conb_1 optlc_681 ( .LO ( optlc_net_680 ) , .HI ( SYNOPSYS_UNCONNECTED_682 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_684 ( .LO ( optlc_net_681 ) , +sky130_fd_sc_hd__conb_1 optlc_682 ( .LO ( optlc_net_681 ) , .HI ( SYNOPSYS_UNCONNECTED_683 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_685 ( .LO ( optlc_net_682 ) , +sky130_fd_sc_hd__conb_1 optlc_683 ( .LO ( optlc_net_682 ) , .HI ( SYNOPSYS_UNCONNECTED_684 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_686 ( .LO ( optlc_net_683 ) , +sky130_fd_sc_hd__conb_1 optlc_684 ( .LO ( optlc_net_683 ) , .HI ( SYNOPSYS_UNCONNECTED_685 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_687 ( .LO ( optlc_net_684 ) , +sky130_fd_sc_hd__conb_1 optlc_685 ( .LO ( optlc_net_684 ) , .HI ( SYNOPSYS_UNCONNECTED_686 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_688 ( .LO ( optlc_net_685 ) , +sky130_fd_sc_hd__conb_1 optlc_686 ( .LO ( optlc_net_685 ) , .HI ( SYNOPSYS_UNCONNECTED_687 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_689 ( .LO ( optlc_net_686 ) , +sky130_fd_sc_hd__conb_1 optlc_687 ( .LO ( optlc_net_686 ) , .HI ( SYNOPSYS_UNCONNECTED_688 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_690 ( .LO ( optlc_net_687 ) , +sky130_fd_sc_hd__conb_1 optlc_688 ( .LO ( optlc_net_687 ) , .HI ( SYNOPSYS_UNCONNECTED_689 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_691 ( .LO ( optlc_net_688 ) , +sky130_fd_sc_hd__conb_1 optlc_689 ( .LO ( optlc_net_688 ) , .HI ( SYNOPSYS_UNCONNECTED_690 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_692 ( .LO ( optlc_net_689 ) , +sky130_fd_sc_hd__conb_1 optlc_690 ( .LO ( optlc_net_689 ) , .HI ( SYNOPSYS_UNCONNECTED_691 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_693 ( .LO ( optlc_net_690 ) , +sky130_fd_sc_hd__conb_1 optlc_691 ( .LO ( optlc_net_690 ) , .HI ( SYNOPSYS_UNCONNECTED_692 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_694 ( .LO ( optlc_net_691 ) , +sky130_fd_sc_hd__conb_1 optlc_692 ( .LO ( optlc_net_691 ) , .HI ( SYNOPSYS_UNCONNECTED_693 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_695 ( .LO ( optlc_net_692 ) , +sky130_fd_sc_hd__conb_1 optlc_693 ( .LO ( optlc_net_692 ) , .HI ( SYNOPSYS_UNCONNECTED_694 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_696 ( .LO ( optlc_net_693 ) , +sky130_fd_sc_hd__conb_1 optlc_694 ( .LO ( optlc_net_693 ) , .HI ( SYNOPSYS_UNCONNECTED_695 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_697 ( .LO ( optlc_net_694 ) , +sky130_fd_sc_hd__conb_1 optlc_695 ( .LO ( optlc_net_694 ) , .HI ( SYNOPSYS_UNCONNECTED_696 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_698 ( .LO ( optlc_net_695 ) , +sky130_fd_sc_hd__conb_1 optlc_696 ( .LO ( optlc_net_695 ) , .HI ( SYNOPSYS_UNCONNECTED_697 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_699 ( .LO ( optlc_net_696 ) , +sky130_fd_sc_hd__conb_1 optlc_697 ( .LO ( optlc_net_696 ) , .HI ( SYNOPSYS_UNCONNECTED_698 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_700 ( .LO ( optlc_net_697 ) , +sky130_fd_sc_hd__conb_1 optlc_698 ( .LO ( optlc_net_697 ) , .HI ( SYNOPSYS_UNCONNECTED_699 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_701 ( .LO ( optlc_net_698 ) , +sky130_fd_sc_hd__conb_1 optlc_699 ( .LO ( optlc_net_698 ) , .HI ( SYNOPSYS_UNCONNECTED_700 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_702 ( .LO ( optlc_net_699 ) , +sky130_fd_sc_hd__conb_1 optlc_700 ( .LO ( optlc_net_699 ) , .HI ( SYNOPSYS_UNCONNECTED_701 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_703 ( .LO ( optlc_net_700 ) , +sky130_fd_sc_hd__conb_1 optlc_701 ( .LO ( optlc_net_700 ) , .HI ( SYNOPSYS_UNCONNECTED_702 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_704 ( .LO ( optlc_net_701 ) , +sky130_fd_sc_hd__conb_1 optlc_702 ( .LO ( optlc_net_701 ) , .HI ( SYNOPSYS_UNCONNECTED_703 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_705 ( .LO ( optlc_net_702 ) , +sky130_fd_sc_hd__conb_1 optlc_703 ( .LO ( optlc_net_702 ) , .HI ( SYNOPSYS_UNCONNECTED_704 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_706 ( .LO ( optlc_net_703 ) , +sky130_fd_sc_hd__conb_1 optlc_704 ( .LO ( optlc_net_703 ) , .HI ( SYNOPSYS_UNCONNECTED_705 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_708 ( .LO ( optlc_net_704 ) , +sky130_fd_sc_hd__conb_1 optlc_705 ( .LO ( optlc_net_704 ) , .HI ( SYNOPSYS_UNCONNECTED_706 ) ) ; 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optlc_net_811 ) , +sky130_fd_sc_hd__conb_1 optlc_812 ( .LO ( optlc_net_811 ) , .HI ( SYNOPSYS_UNCONNECTED_813 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_817 ( .LO ( optlc_net_812 ) , +sky130_fd_sc_hd__conb_1 optlc_813 ( .LO ( optlc_net_812 ) , .HI ( SYNOPSYS_UNCONNECTED_814 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_818 ( .LO ( optlc_net_813 ) , +sky130_fd_sc_hd__conb_1 optlc_814 ( .LO ( optlc_net_813 ) , .HI ( SYNOPSYS_UNCONNECTED_815 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_819 ( .LO ( optlc_net_814 ) , +sky130_fd_sc_hd__conb_1 optlc_815 ( .LO ( optlc_net_814 ) , .HI ( SYNOPSYS_UNCONNECTED_816 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_820 ( .LO ( optlc_net_815 ) , +sky130_fd_sc_hd__conb_1 optlc_816 ( .LO ( optlc_net_815 ) , .HI ( SYNOPSYS_UNCONNECTED_817 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_821 ( .LO ( optlc_net_816 ) , +sky130_fd_sc_hd__conb_1 optlc_817 ( .LO ( optlc_net_816 ) , .HI ( SYNOPSYS_UNCONNECTED_818 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_822 ( .LO ( optlc_net_817 ) , +sky130_fd_sc_hd__conb_1 optlc_818 ( .LO ( optlc_net_817 ) , .HI ( SYNOPSYS_UNCONNECTED_819 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_823 ( .LO ( optlc_net_818 ) , +sky130_fd_sc_hd__conb_1 optlc_819 ( .LO ( optlc_net_818 ) , .HI ( SYNOPSYS_UNCONNECTED_820 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_824 ( .LO ( optlc_net_819 ) , +sky130_fd_sc_hd__conb_1 optlc_820 ( .LO ( optlc_net_819 ) , .HI ( SYNOPSYS_UNCONNECTED_821 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_825 ( .LO ( optlc_net_820 ) , +sky130_fd_sc_hd__conb_1 optlc_821 ( .LO ( optlc_net_820 ) , .HI ( SYNOPSYS_UNCONNECTED_822 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_826 ( .LO ( optlc_net_821 ) , +sky130_fd_sc_hd__conb_1 optlc_822 ( .LO ( optlc_net_821 ) , .HI ( SYNOPSYS_UNCONNECTED_823 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_827 ( .LO ( optlc_net_822 ) , +sky130_fd_sc_hd__conb_1 optlc_823 ( .LO ( optlc_net_822 ) , .HI ( SYNOPSYS_UNCONNECTED_824 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_828 ( .LO ( optlc_net_823 ) , +sky130_fd_sc_hd__conb_1 optlc_824 ( .LO ( optlc_net_823 ) , .HI ( SYNOPSYS_UNCONNECTED_825 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_829 ( .LO ( optlc_net_824 ) , +sky130_fd_sc_hd__conb_1 optlc_825 ( .LO ( optlc_net_824 ) , .HI ( SYNOPSYS_UNCONNECTED_826 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_830 ( .LO ( optlc_net_825 ) , +sky130_fd_sc_hd__conb_1 optlc_826 ( .LO ( optlc_net_825 ) , .HI ( SYNOPSYS_UNCONNECTED_827 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_831 ( .LO ( optlc_net_826 ) , +sky130_fd_sc_hd__conb_1 optlc_827 ( .LO ( optlc_net_826 ) , .HI ( SYNOPSYS_UNCONNECTED_828 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_832 ( .LO ( optlc_net_827 ) , +sky130_fd_sc_hd__conb_1 optlc_828 ( .LO ( optlc_net_827 ) , .HI ( SYNOPSYS_UNCONNECTED_829 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_833 ( .LO ( optlc_net_828 ) , +sky130_fd_sc_hd__conb_1 optlc_829 ( .LO ( optlc_net_828 ) , .HI ( SYNOPSYS_UNCONNECTED_830 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_835 ( .LO ( optlc_net_829 ) , +sky130_fd_sc_hd__conb_1 optlc_830 ( .LO ( optlc_net_829 ) , .HI ( SYNOPSYS_UNCONNECTED_831 ) ) ; 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optlc_net_836 ) , +sky130_fd_sc_hd__conb_1 optlc_838 ( .LO ( optlc_net_836 ) , .HI ( SYNOPSYS_UNCONNECTED_838 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_843 ( .LO ( optlc_net_837 ) , +sky130_fd_sc_hd__conb_1 optlc_839 ( .LO ( optlc_net_837 ) , .HI ( SYNOPSYS_UNCONNECTED_839 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_844 ( .LO ( optlc_net_838 ) , +sky130_fd_sc_hd__conb_1 optlc_840 ( .LO ( optlc_net_838 ) , .HI ( SYNOPSYS_UNCONNECTED_840 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_845 ( .LO ( optlc_net_839 ) , +sky130_fd_sc_hd__conb_1 optlc_841 ( .LO ( optlc_net_839 ) , .HI ( SYNOPSYS_UNCONNECTED_841 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_846 ( .LO ( optlc_net_840 ) , +sky130_fd_sc_hd__conb_1 optlc_842 ( .LO ( optlc_net_840 ) , .HI ( SYNOPSYS_UNCONNECTED_842 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_847 ( .LO ( optlc_net_841 ) , +sky130_fd_sc_hd__conb_1 optlc_843 ( .LO ( optlc_net_841 ) , .HI ( SYNOPSYS_UNCONNECTED_843 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_848 ( .LO ( optlc_net_842 ) , +sky130_fd_sc_hd__conb_1 optlc_844 ( .LO ( optlc_net_842 ) , .HI ( SYNOPSYS_UNCONNECTED_844 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_849 ( .LO ( optlc_net_843 ) , +sky130_fd_sc_hd__conb_1 optlc_845 ( .LO ( optlc_net_843 ) , .HI ( SYNOPSYS_UNCONNECTED_845 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_850 ( .LO ( optlc_net_844 ) , +sky130_fd_sc_hd__conb_1 optlc_846 ( .LO ( optlc_net_844 ) , .HI ( SYNOPSYS_UNCONNECTED_846 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_851 ( .LO ( optlc_net_845 ) , +sky130_fd_sc_hd__conb_1 optlc_847 ( .LO ( optlc_net_845 ) , .HI ( SYNOPSYS_UNCONNECTED_847 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_852 ( .LO ( optlc_net_846 ) , +sky130_fd_sc_hd__conb_1 optlc_848 ( .LO ( optlc_net_846 ) , .HI ( SYNOPSYS_UNCONNECTED_848 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_853 ( .LO ( optlc_net_847 ) , +sky130_fd_sc_hd__conb_1 optlc_849 ( .LO ( optlc_net_847 ) , .HI ( SYNOPSYS_UNCONNECTED_849 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_854 ( .LO ( optlc_net_848 ) , +sky130_fd_sc_hd__conb_1 optlc_850 ( .LO ( optlc_net_848 ) , .HI ( SYNOPSYS_UNCONNECTED_850 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_856 ( .LO ( optlc_net_849 ) , +sky130_fd_sc_hd__conb_1 optlc_851 ( .LO ( optlc_net_849 ) , .HI ( SYNOPSYS_UNCONNECTED_851 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_857 ( .LO ( optlc_net_850 ) , +sky130_fd_sc_hd__conb_1 optlc_852 ( .LO ( optlc_net_850 ) , .HI ( SYNOPSYS_UNCONNECTED_852 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_858 ( .LO ( optlc_net_851 ) , +sky130_fd_sc_hd__conb_1 optlc_853 ( .LO ( optlc_net_851 ) , .HI ( SYNOPSYS_UNCONNECTED_853 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_859 ( .LO ( optlc_net_852 ) , +sky130_fd_sc_hd__conb_1 optlc_854 ( .LO ( optlc_net_852 ) , .HI ( SYNOPSYS_UNCONNECTED_854 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_860 ( .LO ( optlc_net_853 ) , +sky130_fd_sc_hd__conb_1 optlc_855 ( .LO ( optlc_net_853 ) , .HI ( SYNOPSYS_UNCONNECTED_855 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_861 ( .LO ( optlc_net_854 ) , +sky130_fd_sc_hd__conb_1 optlc_856 ( .LO ( optlc_net_854 ) , .HI ( SYNOPSYS_UNCONNECTED_856 ) ) ; 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optlc_net_861 ) , +sky130_fd_sc_hd__conb_1 optlc_863 ( .LO ( optlc_net_861 ) , .HI ( SYNOPSYS_UNCONNECTED_863 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_870 ( .LO ( optlc_net_862 ) , +sky130_fd_sc_hd__conb_1 optlc_864 ( .LO ( optlc_net_862 ) , .HI ( SYNOPSYS_UNCONNECTED_864 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_871 ( .LO ( optlc_net_863 ) , +sky130_fd_sc_hd__conb_1 optlc_865 ( .LO ( optlc_net_863 ) , .HI ( SYNOPSYS_UNCONNECTED_865 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_872 ( .LO ( optlc_net_864 ) , +sky130_fd_sc_hd__conb_1 optlc_866 ( .LO ( optlc_net_864 ) , .HI ( SYNOPSYS_UNCONNECTED_866 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_873 ( .LO ( optlc_net_865 ) , +sky130_fd_sc_hd__conb_1 optlc_867 ( .LO ( optlc_net_865 ) , .HI ( SYNOPSYS_UNCONNECTED_867 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_874 ( .LO ( optlc_net_866 ) , +sky130_fd_sc_hd__conb_1 optlc_868 ( .LO ( optlc_net_866 ) , .HI ( SYNOPSYS_UNCONNECTED_868 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_875 ( .LO ( optlc_net_867 ) , +sky130_fd_sc_hd__conb_1 optlc_869 ( .LO ( optlc_net_867 ) , .HI ( SYNOPSYS_UNCONNECTED_869 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_876 ( .LO ( optlc_net_868 ) , +sky130_fd_sc_hd__conb_1 optlc_870 ( .LO ( optlc_net_868 ) , .HI ( SYNOPSYS_UNCONNECTED_870 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_877 ( .LO ( optlc_net_869 ) , +sky130_fd_sc_hd__conb_1 optlc_871 ( .LO ( optlc_net_869 ) , .HI ( SYNOPSYS_UNCONNECTED_871 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_878 ( .LO ( optlc_net_870 ) , +sky130_fd_sc_hd__conb_1 optlc_872 ( .LO ( optlc_net_870 ) , .HI ( SYNOPSYS_UNCONNECTED_872 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_879 ( .LO ( optlc_net_871 ) , +sky130_fd_sc_hd__conb_1 optlc_873 ( .LO ( optlc_net_871 ) , .HI ( SYNOPSYS_UNCONNECTED_873 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_880 ( .LO ( optlc_net_872 ) , +sky130_fd_sc_hd__conb_1 optlc_874 ( .LO ( optlc_net_872 ) , .HI ( SYNOPSYS_UNCONNECTED_874 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_881 ( .LO ( optlc_net_873 ) , +sky130_fd_sc_hd__conb_1 optlc_875 ( .LO ( optlc_net_873 ) , .HI ( SYNOPSYS_UNCONNECTED_875 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_882 ( .LO ( optlc_net_874 ) , +sky130_fd_sc_hd__conb_1 optlc_876 ( .LO ( optlc_net_874 ) , .HI ( SYNOPSYS_UNCONNECTED_876 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_883 ( .LO ( optlc_net_875 ) , +sky130_fd_sc_hd__conb_1 optlc_877 ( .LO ( optlc_net_875 ) , .HI ( SYNOPSYS_UNCONNECTED_877 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_884 ( .LO ( optlc_net_876 ) , +sky130_fd_sc_hd__conb_1 optlc_878 ( .LO ( optlc_net_876 ) , .HI ( SYNOPSYS_UNCONNECTED_878 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_885 ( .LO ( optlc_net_877 ) , +sky130_fd_sc_hd__conb_1 optlc_879 ( .LO ( optlc_net_877 ) , .HI ( SYNOPSYS_UNCONNECTED_879 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_886 ( .LO ( optlc_net_878 ) , +sky130_fd_sc_hd__conb_1 optlc_880 ( .LO ( optlc_net_878 ) , .HI ( SYNOPSYS_UNCONNECTED_880 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_887 ( .LO ( optlc_net_879 ) , +sky130_fd_sc_hd__conb_1 optlc_881 ( .LO ( optlc_net_879 ) , .HI ( SYNOPSYS_UNCONNECTED_881 ) ) ; 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+sky130_fd_sc_hd__conb_1 optlc_3875 ( .LO ( optlc_net_3524 ) , .HI ( SYNOPSYS_UNCONNECTED_3526 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_3985 ( .LO ( optlc_net_3525 ) , +sky130_fd_sc_hd__conb_1 optlc_3876 ( .LO ( optlc_net_3525 ) , .HI ( SYNOPSYS_UNCONNECTED_3527 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_3986 ( .LO ( optlc_net_3526 ) , +sky130_fd_sc_hd__conb_1 optlc_3877 ( .LO ( optlc_net_3526 ) , .HI ( SYNOPSYS_UNCONNECTED_3528 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_3987 ( .LO ( optlc_net_3527 ) , +sky130_fd_sc_hd__conb_1 optlc_3878 ( .LO ( optlc_net_3527 ) , .HI ( SYNOPSYS_UNCONNECTED_3529 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_3988 ( .LO ( optlc_net_3528 ) , +sky130_fd_sc_hd__conb_1 optlc_3879 ( .LO ( optlc_net_3528 ) , .HI ( SYNOPSYS_UNCONNECTED_3530 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_3989 ( .LO ( optlc_net_3529 ) , +sky130_fd_sc_hd__conb_1 optlc_3880 ( .LO ( optlc_net_3529 ) , .HI ( SYNOPSYS_UNCONNECTED_3531 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3881 ( .LO ( optlc_net_3530 ) , + .HI ( SYNOPSYS_UNCONNECTED_3532 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3882 ( .LO ( optlc_net_3531 ) , + .HI ( SYNOPSYS_UNCONNECTED_3533 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3883 ( .LO ( optlc_net_3532 ) , + .HI ( SYNOPSYS_UNCONNECTED_3534 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3884 ( .LO ( optlc_net_3533 ) , + .HI ( SYNOPSYS_UNCONNECTED_3535 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3885 ( .LO ( optlc_net_3534 ) , + .HI ( SYNOPSYS_UNCONNECTED_3536 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3886 ( .LO ( optlc_net_3535 ) , + .HI ( SYNOPSYS_UNCONNECTED_3537 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3887 ( .LO ( optlc_net_3536 ) , + .HI ( SYNOPSYS_UNCONNECTED_3538 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3888 ( .LO ( optlc_net_3537 ) , + .HI ( SYNOPSYS_UNCONNECTED_3539 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3889 ( .LO ( optlc_net_3538 ) , + .HI ( SYNOPSYS_UNCONNECTED_3540 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3890 ( .LO ( optlc_net_3539 ) , + .HI ( SYNOPSYS_UNCONNECTED_3541 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3891 ( .LO ( optlc_net_3540 ) , + .HI ( SYNOPSYS_UNCONNECTED_3542 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3892 ( .LO ( optlc_net_3541 ) , + .HI ( SYNOPSYS_UNCONNECTED_3543 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3893 ( .LO ( optlc_net_3542 ) , + .HI ( SYNOPSYS_UNCONNECTED_3544 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3894 ( .LO ( optlc_net_3543 ) , + .HI ( SYNOPSYS_UNCONNECTED_3545 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3895 ( .LO ( optlc_net_3544 ) , + .HI ( SYNOPSYS_UNCONNECTED_3546 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3896 ( .LO ( optlc_net_3545 ) , + .HI ( SYNOPSYS_UNCONNECTED_3547 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3897 ( .LO ( optlc_net_3546 ) , + .HI ( SYNOPSYS_UNCONNECTED_3548 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3898 ( .LO ( optlc_net_3547 ) , + .HI ( SYNOPSYS_UNCONNECTED_3549 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3899 ( .LO ( optlc_net_3548 ) , + .HI ( SYNOPSYS_UNCONNECTED_3550 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3900 ( .LO ( optlc_net_3549 ) , + .HI ( SYNOPSYS_UNCONNECTED_3551 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3901 ( .LO ( optlc_net_3550 ) , + .HI ( SYNOPSYS_UNCONNECTED_3552 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3902 ( .LO ( optlc_net_3551 ) , + .HI ( SYNOPSYS_UNCONNECTED_3553 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3903 ( .LO ( optlc_net_3552 ) , + .HI ( SYNOPSYS_UNCONNECTED_3554 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3904 ( .LO ( optlc_net_3553 ) , + .HI ( SYNOPSYS_UNCONNECTED_3555 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3905 ( .LO ( optlc_net_3554 ) , + .HI ( SYNOPSYS_UNCONNECTED_3556 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3906 ( .LO ( optlc_net_3555 ) , + .HI ( SYNOPSYS_UNCONNECTED_3557 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3907 ( .LO ( optlc_net_3556 ) , + .HI ( SYNOPSYS_UNCONNECTED_3558 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3908 ( .LO ( optlc_net_3557 ) , + .HI ( SYNOPSYS_UNCONNECTED_3559 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3909 ( .LO ( optlc_net_3558 ) , + .HI ( SYNOPSYS_UNCONNECTED_3560 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3910 ( .LO ( optlc_net_3559 ) , + .HI ( SYNOPSYS_UNCONNECTED_3561 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3911 ( .LO ( optlc_net_3560 ) , + .HI ( SYNOPSYS_UNCONNECTED_3562 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3912 ( .LO ( optlc_net_3561 ) , + .HI ( SYNOPSYS_UNCONNECTED_3563 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3913 ( .LO ( optlc_net_3562 ) , + .HI ( SYNOPSYS_UNCONNECTED_3564 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3914 ( .LO ( optlc_net_3563 ) , + .HI ( SYNOPSYS_UNCONNECTED_3565 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3915 ( .LO ( optlc_net_3564 ) , + .HI ( SYNOPSYS_UNCONNECTED_3566 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3916 ( .LO ( optlc_net_3565 ) , + .HI ( SYNOPSYS_UNCONNECTED_3567 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3917 ( .LO ( optlc_net_3566 ) , + .HI ( SYNOPSYS_UNCONNECTED_3568 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3918 ( .LO ( optlc_net_3567 ) , + .HI ( SYNOPSYS_UNCONNECTED_3569 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3919 ( .LO ( optlc_net_3568 ) , + .HI ( SYNOPSYS_UNCONNECTED_3570 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3920 ( .LO ( optlc_net_3569 ) , + .HI ( SYNOPSYS_UNCONNECTED_3571 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3921 ( .LO ( optlc_net_3570 ) , + .HI ( SYNOPSYS_UNCONNECTED_3572 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3922 ( .LO ( optlc_net_3571 ) , + .HI ( SYNOPSYS_UNCONNECTED_3573 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3923 ( .LO ( optlc_net_3572 ) , + .HI ( SYNOPSYS_UNCONNECTED_3574 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3924 ( .LO ( optlc_net_3573 ) , + .HI ( SYNOPSYS_UNCONNECTED_3575 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3925 ( .LO ( optlc_net_3574 ) , + .HI ( SYNOPSYS_UNCONNECTED_3576 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3926 ( .LO ( optlc_net_3575 ) , + .HI ( SYNOPSYS_UNCONNECTED_3577 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3927 ( .LO ( optlc_net_3576 ) , + .HI ( SYNOPSYS_UNCONNECTED_3578 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3928 ( .LO ( optlc_net_3577 ) , + .HI ( SYNOPSYS_UNCONNECTED_3579 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3929 ( .LO ( optlc_net_3578 ) , + .HI ( SYNOPSYS_UNCONNECTED_3580 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3930 ( .LO ( optlc_net_3579 ) , + .HI ( SYNOPSYS_UNCONNECTED_3581 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3931 ( .LO ( optlc_net_3580 ) , + .HI ( SYNOPSYS_UNCONNECTED_3582 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3932 ( .LO ( optlc_net_3581 ) , + .HI ( SYNOPSYS_UNCONNECTED_3583 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3933 ( .LO ( optlc_net_3582 ) , + .HI ( SYNOPSYS_UNCONNECTED_3584 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3934 ( .LO ( optlc_net_3583 ) , + .HI ( SYNOPSYS_UNCONNECTED_3585 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3935 ( .LO ( optlc_net_3584 ) , + .HI ( SYNOPSYS_UNCONNECTED_3586 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3936 ( .LO ( optlc_net_3585 ) , + .HI ( SYNOPSYS_UNCONNECTED_3587 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3937 ( .LO ( optlc_net_3586 ) , + .HI ( SYNOPSYS_UNCONNECTED_3588 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3938 ( .LO ( optlc_net_3587 ) , + .HI ( SYNOPSYS_UNCONNECTED_3589 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3939 ( .LO ( optlc_net_3588 ) , + .HI ( SYNOPSYS_UNCONNECTED_3590 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3940 ( .LO ( optlc_net_3589 ) , + .HI ( SYNOPSYS_UNCONNECTED_3591 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3941 ( .LO ( optlc_net_3590 ) , + .HI ( SYNOPSYS_UNCONNECTED_3592 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3942 ( .LO ( optlc_net_3591 ) , + .HI ( SYNOPSYS_UNCONNECTED_3593 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3943 ( .LO ( optlc_net_3592 ) , + .HI ( SYNOPSYS_UNCONNECTED_3594 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3944 ( .LO ( optlc_net_3593 ) , + .HI ( SYNOPSYS_UNCONNECTED_3595 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3945 ( .LO ( optlc_net_3594 ) , + .HI ( SYNOPSYS_UNCONNECTED_3596 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3946 ( .LO ( optlc_net_3595 ) , + .HI ( SYNOPSYS_UNCONNECTED_3597 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3947 ( .LO ( optlc_net_3596 ) , + .HI ( SYNOPSYS_UNCONNECTED_3598 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3948 ( .LO ( optlc_net_3597 ) , + .HI ( SYNOPSYS_UNCONNECTED_3599 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3949 ( .LO ( optlc_net_3598 ) , + .HI ( SYNOPSYS_UNCONNECTED_3600 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3950 ( .LO ( optlc_net_3599 ) , + .HI ( SYNOPSYS_UNCONNECTED_3601 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3951 ( .LO ( optlc_net_3600 ) , + .HI ( SYNOPSYS_UNCONNECTED_3602 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3952 ( .LO ( optlc_net_3601 ) , + .HI ( SYNOPSYS_UNCONNECTED_3603 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3953 ( .LO ( optlc_net_3602 ) , + .HI ( SYNOPSYS_UNCONNECTED_3604 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3954 ( .LO ( optlc_net_3603 ) , + .HI ( SYNOPSYS_UNCONNECTED_3605 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3955 ( .LO ( optlc_net_3604 ) , + .HI ( SYNOPSYS_UNCONNECTED_3606 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3956 ( .LO ( optlc_net_3605 ) , + .HI ( SYNOPSYS_UNCONNECTED_3607 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3957 ( .LO ( optlc_net_3606 ) , + .HI ( SYNOPSYS_UNCONNECTED_3608 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3958 ( .LO ( optlc_net_3607 ) , + .HI ( SYNOPSYS_UNCONNECTED_3609 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3959 ( .LO ( optlc_net_3608 ) , + .HI ( SYNOPSYS_UNCONNECTED_3610 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3960 ( .LO ( optlc_net_3609 ) , + .HI ( SYNOPSYS_UNCONNECTED_3611 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3961 ( .LO ( optlc_net_3610 ) , + .HI ( SYNOPSYS_UNCONNECTED_3612 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3962 ( .LO ( optlc_net_3611 ) , + .HI ( SYNOPSYS_UNCONNECTED_3613 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3963 ( .LO ( optlc_net_3612 ) , + .HI ( SYNOPSYS_UNCONNECTED_3614 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3964 ( .LO ( optlc_net_3613 ) , + .HI ( SYNOPSYS_UNCONNECTED_3615 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3965 ( .LO ( optlc_net_3614 ) , + .HI ( SYNOPSYS_UNCONNECTED_3616 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3966 ( .LO ( optlc_net_3615 ) , + .HI ( SYNOPSYS_UNCONNECTED_3617 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3967 ( .LO ( optlc_net_3616 ) , + .HI ( SYNOPSYS_UNCONNECTED_3618 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3968 ( .LO ( optlc_net_3617 ) , + .HI ( SYNOPSYS_UNCONNECTED_3619 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3969 ( .LO ( optlc_net_3618 ) , + .HI ( SYNOPSYS_UNCONNECTED_3620 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3970 ( .LO ( optlc_net_3619 ) , + .HI ( SYNOPSYS_UNCONNECTED_3621 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3971 ( .LO ( optlc_net_3620 ) , + .HI ( SYNOPSYS_UNCONNECTED_3622 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3972 ( .LO ( optlc_net_3621 ) , + .HI ( SYNOPSYS_UNCONNECTED_3623 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3973 ( .LO ( optlc_net_3622 ) , + .HI ( SYNOPSYS_UNCONNECTED_3624 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3974 ( .LO ( optlc_net_3623 ) , + .HI ( SYNOPSYS_UNCONNECTED_3625 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3975 ( .LO ( optlc_net_3624 ) , + .HI ( SYNOPSYS_UNCONNECTED_3626 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3976 ( .LO ( optlc_net_3625 ) , + .HI ( SYNOPSYS_UNCONNECTED_3627 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3977 ( .LO ( optlc_net_3626 ) , + .HI ( SYNOPSYS_UNCONNECTED_3628 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3978 ( .LO ( optlc_net_3627 ) , + .HI ( SYNOPSYS_UNCONNECTED_3629 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3979 ( .LO ( optlc_net_3628 ) , + .HI ( SYNOPSYS_UNCONNECTED_3630 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3980 ( .LO ( optlc_net_3629 ) , + .HI ( SYNOPSYS_UNCONNECTED_3631 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3981 ( .LO ( optlc_net_3630 ) , + .HI ( SYNOPSYS_UNCONNECTED_3632 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3982 ( .LO ( optlc_net_3631 ) , + .HI ( SYNOPSYS_UNCONNECTED_3633 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3983 ( .LO ( optlc_net_3632 ) , + .HI ( SYNOPSYS_UNCONNECTED_3634 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3984 ( .LO ( optlc_net_3633 ) , + .HI ( SYNOPSYS_UNCONNECTED_3635 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3985 ( .LO ( optlc_net_3634 ) , + .HI ( SYNOPSYS_UNCONNECTED_3636 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3986 ( .LO ( optlc_net_3635 ) , + .HI ( SYNOPSYS_UNCONNECTED_3637 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3987 ( .LO ( optlc_net_3636 ) , + .HI ( SYNOPSYS_UNCONNECTED_3638 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3988 ( .LO ( optlc_net_3637 ) , + .HI ( SYNOPSYS_UNCONNECTED_3639 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3989 ( .LO ( optlc_net_3638 ) , + .HI ( SYNOPSYS_UNCONNECTED_3640 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3990 ( .LO ( optlc_net_3639 ) , + .HI ( SYNOPSYS_UNCONNECTED_3641 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3991 ( .LO ( optlc_net_3640 ) , + .HI ( SYNOPSYS_UNCONNECTED_3642 ) ) ; endmodule diff --git a/FPGA1212_SOFA_CHD_PNR/fpga_top/fpga_top_icv_in_design.top_only.pt.v b/FPGA1212_SOFA_CHD_PNR/fpga_top/fpga_top_icv_in_design.top_only.pt.v index 47513f2..81d0db4 100644 --- a/FPGA1212_SOFA_CHD_PNR/fpga_top/fpga_top_icv_in_design.top_only.pt.v +++ b/FPGA1212_SOFA_CHD_PNR/fpga_top/fpga_top_icv_in_design.top_only.pt.v @@ -2753,7 +2753,63 @@ fpga_core fpga_core_uut ( .pReset ( io_in[3] ) , .prog_clk ( io_in[37] ) , .p3502 ( optlc_net_3522 ) , .p3503 ( optlc_net_3523 ) , .p3504 ( optlc_net_3524 ) , .p3505 ( optlc_net_3525 ) , .p3506 ( optlc_net_3526 ) , .p3507 ( optlc_net_3527 ) , - .p3508 ( optlc_net_3528 ) , .p3509 ( optlc_net_3529 ) ) ; + .p3508 ( optlc_net_3528 ) , .p3509 ( optlc_net_3529 ) , + .p3510 ( optlc_net_3530 ) , .p3511 ( optlc_net_3531 ) , + .p3512 ( optlc_net_3532 ) , .p3513 ( optlc_net_3533 ) , + .p3514 ( optlc_net_3534 ) , .p3515 ( optlc_net_3535 ) , + .p3516 ( optlc_net_3536 ) , .p3517 ( optlc_net_3537 ) , + .p3518 ( optlc_net_3538 ) , .p3519 ( optlc_net_3539 ) , + .p3520 ( optlc_net_3540 ) , .p3521 ( optlc_net_3541 ) , + .p3522 ( optlc_net_3542 ) , .p3523 ( optlc_net_3543 ) , + .p3524 ( optlc_net_3544 ) , .p3525 ( optlc_net_3545 ) , + .p3526 ( optlc_net_3546 ) , .p3527 ( optlc_net_3547 ) , + .p3528 ( optlc_net_3548 ) , .p3529 ( optlc_net_3549 ) , + .p3530 ( optlc_net_3550 ) , .p3531 ( optlc_net_3551 ) , + .p3532 ( optlc_net_3552 ) , .p3533 ( optlc_net_3553 ) , + .p3534 ( optlc_net_3554 ) , .p3535 ( optlc_net_3555 ) , + .p3536 ( optlc_net_3556 ) , .p3537 ( optlc_net_3557 ) , + .p3538 ( optlc_net_3558 ) , .p3539 ( optlc_net_3559 ) , + .p3540 ( optlc_net_3560 ) , .p3541 ( optlc_net_3561 ) , + .p3542 ( optlc_net_3562 ) , .p3543 ( optlc_net_3563 ) , + .p3544 ( optlc_net_3564 ) , .p3545 ( optlc_net_3565 ) , + .p3546 ( optlc_net_3566 ) , .p3547 ( optlc_net_3567 ) , + .p3548 ( optlc_net_3568 ) , .p3549 ( optlc_net_3569 ) , + .p3550 ( optlc_net_3570 ) , .p3551 ( optlc_net_3571 ) , + .p3552 ( optlc_net_3572 ) , .p3553 ( optlc_net_3573 ) , + .p3554 ( optlc_net_3574 ) , .p3555 ( optlc_net_3575 ) , + .p3556 ( optlc_net_3576 ) , .p3557 ( optlc_net_3577 ) , + .p3558 ( optlc_net_3578 ) , .p3559 ( optlc_net_3579 ) , + .p3560 ( optlc_net_3580 ) , .p3561 ( optlc_net_3581 ) , + .p3562 ( optlc_net_3582 ) , .p3563 ( optlc_net_3583 ) , + .p3564 ( optlc_net_3584 ) , .p3565 ( optlc_net_3585 ) , + .p3566 ( optlc_net_3586 ) , .p3567 ( optlc_net_3587 ) , + .p3568 ( optlc_net_3588 ) , .p3569 ( optlc_net_3589 ) , + .p3570 ( optlc_net_3590 ) , .p3571 ( optlc_net_3591 ) , + .p3572 ( optlc_net_3592 ) , .p3573 ( optlc_net_3593 ) , + .p3574 ( optlc_net_3594 ) , .p3575 ( optlc_net_3595 ) , + .p3576 ( optlc_net_3596 ) , .p3577 ( optlc_net_3597 ) , + .p3578 ( optlc_net_3598 ) , .p3579 ( optlc_net_3599 ) , + .p3580 ( optlc_net_3600 ) , .p3581 ( optlc_net_3601 ) , + .p3582 ( optlc_net_3602 ) , .p3583 ( optlc_net_3603 ) , + .p3584 ( optlc_net_3604 ) , .p3585 ( optlc_net_3605 ) , + .p3586 ( optlc_net_3606 ) , .p3587 ( optlc_net_3607 ) , + .p3588 ( optlc_net_3608 ) , .p3589 ( optlc_net_3609 ) , + .p3590 ( optlc_net_3610 ) , .p3591 ( optlc_net_3611 ) , + .p3592 ( optlc_net_3612 ) , .p3593 ( optlc_net_3613 ) , + .p3594 ( optlc_net_3614 ) , .p3595 ( optlc_net_3615 ) , + .p3596 ( optlc_net_3616 ) , .p3597 ( optlc_net_3617 ) , + .p3598 ( optlc_net_3618 ) , .p3599 ( optlc_net_3619 ) , + .p3600 ( optlc_net_3620 ) , .p3601 ( optlc_net_3621 ) , + .p3602 ( optlc_net_3622 ) , .p3603 ( optlc_net_3623 ) , + .p3604 ( optlc_net_3624 ) , .p3605 ( optlc_net_3625 ) , + .p3606 ( optlc_net_3626 ) , .p3607 ( optlc_net_3627 ) , + .p3608 ( optlc_net_3628 ) , .p3609 ( optlc_net_3629 ) , + .p3610 ( optlc_net_3630 ) , .p3611 ( optlc_net_3631 ) , + .p3612 ( optlc_net_3632 ) , .p3613 ( optlc_net_3633 ) , + .p3614 ( optlc_net_3634 ) , .p3615 ( optlc_net_3635 ) , + .p3616 ( optlc_net_3636 ) , .p3617 ( optlc_net_3637 ) , + .p3618 ( optlc_net_3638 ) , .p3619 ( optlc_net_3639 ) , + .p3620 ( optlc_net_3640 ) ) ; sky130_fd_sc_hd__conb_1 optlc_0 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , .HI ( io_oeb[0] ) ) ; sky130_fd_sc_hd__conb_1 optlc_1 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , @@ -2796,2595 +2852,2595 @@ sky130_fd_sc_hd__conb_1 optlc_19 ( .LO ( io_out[37] ) , .HI ( SYNOPSYS_UNCONNECTED_21 ) ) ; sky130_fd_sc_hd__conb_1 optlc_21 ( .LO ( optlc_net_20 ) , .HI ( SYNOPSYS_UNCONNECTED_22 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_23 ( .LO ( optlc_net_21 ) , +sky130_fd_sc_hd__conb_1 optlc_22 ( .LO ( optlc_net_21 ) , .HI ( SYNOPSYS_UNCONNECTED_23 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_24 ( .LO ( optlc_net_22 ) , +sky130_fd_sc_hd__conb_1 optlc_23 ( .LO ( optlc_net_22 ) , .HI ( SYNOPSYS_UNCONNECTED_24 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_25 ( .LO ( optlc_net_23 ) , +sky130_fd_sc_hd__conb_1 optlc_24 ( .LO ( optlc_net_23 ) , .HI ( SYNOPSYS_UNCONNECTED_25 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_26 ( .LO ( optlc_net_24 ) , +sky130_fd_sc_hd__conb_1 optlc_25 ( .LO ( optlc_net_24 ) , .HI ( SYNOPSYS_UNCONNECTED_26 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_27 ( .LO ( optlc_net_25 ) , +sky130_fd_sc_hd__conb_1 optlc_26 ( .LO ( optlc_net_25 ) , .HI ( SYNOPSYS_UNCONNECTED_27 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_28 ( .LO ( optlc_net_26 ) , +sky130_fd_sc_hd__conb_1 optlc_27 ( .LO ( optlc_net_26 ) , .HI ( SYNOPSYS_UNCONNECTED_28 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_29 ( .LO ( optlc_net_27 ) , +sky130_fd_sc_hd__conb_1 optlc_28 ( .LO ( optlc_net_27 ) , .HI ( SYNOPSYS_UNCONNECTED_29 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_30 ( .LO ( optlc_net_28 ) , +sky130_fd_sc_hd__conb_1 optlc_29 ( .LO ( optlc_net_28 ) , .HI ( SYNOPSYS_UNCONNECTED_30 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_31 ( .LO ( optlc_net_29 ) , +sky130_fd_sc_hd__conb_1 optlc_30 ( .LO ( optlc_net_29 ) , .HI ( SYNOPSYS_UNCONNECTED_31 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_32 ( .LO ( optlc_net_30 ) , +sky130_fd_sc_hd__conb_1 optlc_31 ( .LO ( optlc_net_30 ) , .HI ( SYNOPSYS_UNCONNECTED_32 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_33 ( .LO ( optlc_net_31 ) , +sky130_fd_sc_hd__conb_1 optlc_32 ( .LO ( optlc_net_31 ) , .HI ( SYNOPSYS_UNCONNECTED_33 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_34 ( .LO ( optlc_net_32 ) , +sky130_fd_sc_hd__conb_1 optlc_33 ( .LO ( optlc_net_32 ) , .HI ( SYNOPSYS_UNCONNECTED_34 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_35 ( .LO ( optlc_net_33 ) , +sky130_fd_sc_hd__conb_1 optlc_34 ( .LO ( optlc_net_33 ) , .HI ( SYNOPSYS_UNCONNECTED_35 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_36 ( .LO ( optlc_net_34 ) , +sky130_fd_sc_hd__conb_1 optlc_35 ( .LO ( optlc_net_34 ) , .HI ( SYNOPSYS_UNCONNECTED_36 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_37 ( .LO ( optlc_net_35 ) , +sky130_fd_sc_hd__conb_1 optlc_36 ( .LO ( optlc_net_35 ) , .HI ( SYNOPSYS_UNCONNECTED_37 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_38 ( .LO ( optlc_net_36 ) , +sky130_fd_sc_hd__conb_1 optlc_37 ( .LO ( optlc_net_36 ) , .HI ( SYNOPSYS_UNCONNECTED_38 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_39 ( .LO ( optlc_net_37 ) , +sky130_fd_sc_hd__conb_1 optlc_38 ( .LO ( optlc_net_37 ) , .HI ( SYNOPSYS_UNCONNECTED_39 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_40 ( .LO ( optlc_net_38 ) , +sky130_fd_sc_hd__conb_1 optlc_39 ( .LO ( optlc_net_38 ) , .HI ( SYNOPSYS_UNCONNECTED_40 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_41 ( .LO ( optlc_net_39 ) , +sky130_fd_sc_hd__conb_1 optlc_40 ( .LO ( optlc_net_39 ) , .HI ( SYNOPSYS_UNCONNECTED_41 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_42 ( .LO ( optlc_net_40 ) , +sky130_fd_sc_hd__conb_1 optlc_41 ( .LO ( optlc_net_40 ) , .HI ( SYNOPSYS_UNCONNECTED_42 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_43 ( .LO ( optlc_net_41 ) , +sky130_fd_sc_hd__conb_1 optlc_42 ( .LO ( optlc_net_41 ) , .HI ( SYNOPSYS_UNCONNECTED_43 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_44 ( .LO ( optlc_net_42 ) , +sky130_fd_sc_hd__conb_1 optlc_43 ( .LO ( optlc_net_42 ) , .HI ( SYNOPSYS_UNCONNECTED_44 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_45 ( .LO ( optlc_net_43 ) , +sky130_fd_sc_hd__conb_1 optlc_44 ( .LO ( optlc_net_43 ) , .HI ( SYNOPSYS_UNCONNECTED_45 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_46 ( .LO ( optlc_net_44 ) , +sky130_fd_sc_hd__conb_1 optlc_45 ( .LO ( optlc_net_44 ) , .HI ( SYNOPSYS_UNCONNECTED_46 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_47 ( .LO ( optlc_net_45 ) , +sky130_fd_sc_hd__conb_1 optlc_46 ( .LO ( optlc_net_45 ) , .HI ( SYNOPSYS_UNCONNECTED_47 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_48 ( .LO ( optlc_net_46 ) , +sky130_fd_sc_hd__conb_1 optlc_47 ( .LO ( optlc_net_46 ) , .HI ( SYNOPSYS_UNCONNECTED_48 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_49 ( .LO ( optlc_net_47 ) , +sky130_fd_sc_hd__conb_1 optlc_48 ( .LO ( optlc_net_47 ) , .HI ( SYNOPSYS_UNCONNECTED_49 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_50 ( .LO ( optlc_net_48 ) , +sky130_fd_sc_hd__conb_1 optlc_49 ( .LO ( optlc_net_48 ) , .HI ( SYNOPSYS_UNCONNECTED_50 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_51 ( .LO ( optlc_net_49 ) , +sky130_fd_sc_hd__conb_1 optlc_50 ( .LO ( optlc_net_49 ) , .HI ( SYNOPSYS_UNCONNECTED_51 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_52 ( .LO ( optlc_net_50 ) , +sky130_fd_sc_hd__conb_1 optlc_51 ( .LO ( optlc_net_50 ) , .HI ( SYNOPSYS_UNCONNECTED_52 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_53 ( .LO ( optlc_net_51 ) , +sky130_fd_sc_hd__conb_1 optlc_52 ( .LO ( optlc_net_51 ) , .HI ( SYNOPSYS_UNCONNECTED_53 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_54 ( .LO ( optlc_net_52 ) , +sky130_fd_sc_hd__conb_1 optlc_53 ( .LO ( optlc_net_52 ) , .HI ( SYNOPSYS_UNCONNECTED_54 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_55 ( .LO ( optlc_net_53 ) , +sky130_fd_sc_hd__conb_1 optlc_54 ( .LO ( optlc_net_53 ) , .HI ( SYNOPSYS_UNCONNECTED_55 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_56 ( .LO ( optlc_net_54 ) , +sky130_fd_sc_hd__conb_1 optlc_55 ( .LO ( optlc_net_54 ) , .HI ( SYNOPSYS_UNCONNECTED_56 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_57 ( .LO ( optlc_net_55 ) , +sky130_fd_sc_hd__conb_1 optlc_56 ( .LO ( optlc_net_55 ) , .HI ( SYNOPSYS_UNCONNECTED_57 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_58 ( .LO ( optlc_net_56 ) , +sky130_fd_sc_hd__conb_1 optlc_57 ( .LO ( optlc_net_56 ) , .HI ( SYNOPSYS_UNCONNECTED_58 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_59 ( .LO ( optlc_net_57 ) , +sky130_fd_sc_hd__conb_1 optlc_58 ( .LO ( optlc_net_57 ) , .HI ( SYNOPSYS_UNCONNECTED_59 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_60 ( .LO ( optlc_net_58 ) , +sky130_fd_sc_hd__conb_1 optlc_59 ( .LO ( optlc_net_58 ) , .HI ( SYNOPSYS_UNCONNECTED_60 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_61 ( .LO ( optlc_net_59 ) , +sky130_fd_sc_hd__conb_1 optlc_60 ( .LO ( optlc_net_59 ) , .HI ( SYNOPSYS_UNCONNECTED_61 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_62 ( .LO ( optlc_net_60 ) , +sky130_fd_sc_hd__conb_1 optlc_61 ( .LO ( optlc_net_60 ) , .HI ( SYNOPSYS_UNCONNECTED_62 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_63 ( .LO ( optlc_net_61 ) , +sky130_fd_sc_hd__conb_1 optlc_62 ( .LO ( optlc_net_61 ) , .HI ( SYNOPSYS_UNCONNECTED_63 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_64 ( .LO ( optlc_net_62 ) , +sky130_fd_sc_hd__conb_1 optlc_63 ( .LO ( optlc_net_62 ) , .HI ( SYNOPSYS_UNCONNECTED_64 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_65 ( .LO ( optlc_net_63 ) , +sky130_fd_sc_hd__conb_1 optlc_64 ( .LO ( optlc_net_63 ) , .HI ( SYNOPSYS_UNCONNECTED_65 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_66 ( .LO ( optlc_net_64 ) , +sky130_fd_sc_hd__conb_1 optlc_65 ( .LO ( optlc_net_64 ) , .HI ( SYNOPSYS_UNCONNECTED_66 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_67 ( .LO ( optlc_net_65 ) , +sky130_fd_sc_hd__conb_1 optlc_66 ( .LO ( optlc_net_65 ) , .HI ( SYNOPSYS_UNCONNECTED_67 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_68 ( .LO ( optlc_net_66 ) , +sky130_fd_sc_hd__conb_1 optlc_67 ( .LO ( optlc_net_66 ) , .HI ( SYNOPSYS_UNCONNECTED_68 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_69 ( .LO ( optlc_net_67 ) , +sky130_fd_sc_hd__conb_1 optlc_68 ( .LO ( optlc_net_67 ) , .HI ( SYNOPSYS_UNCONNECTED_69 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_70 ( .LO ( optlc_net_68 ) , +sky130_fd_sc_hd__conb_1 optlc_69 ( .LO ( optlc_net_68 ) , .HI ( SYNOPSYS_UNCONNECTED_70 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_71 ( .LO ( optlc_net_69 ) , +sky130_fd_sc_hd__conb_1 optlc_70 ( .LO ( optlc_net_69 ) , .HI ( SYNOPSYS_UNCONNECTED_71 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_72 ( .LO ( optlc_net_70 ) , +sky130_fd_sc_hd__conb_1 optlc_71 ( .LO ( optlc_net_70 ) , .HI ( SYNOPSYS_UNCONNECTED_72 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_73 ( .LO ( optlc_net_71 ) , +sky130_fd_sc_hd__conb_1 optlc_72 ( .LO ( optlc_net_71 ) , .HI ( SYNOPSYS_UNCONNECTED_73 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_74 ( .LO ( optlc_net_72 ) , +sky130_fd_sc_hd__conb_1 optlc_73 ( .LO ( optlc_net_72 ) , .HI ( SYNOPSYS_UNCONNECTED_74 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_75 ( .LO ( optlc_net_73 ) , +sky130_fd_sc_hd__conb_1 optlc_74 ( .LO ( optlc_net_73 ) , .HI ( SYNOPSYS_UNCONNECTED_75 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_76 ( 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-sky130_fd_sc_hd__conb_1 optlc_533 ( .LO ( optlc_net_531 ) , +sky130_fd_sc_hd__conb_1 optlc_532 ( .LO ( optlc_net_531 ) , .HI ( SYNOPSYS_UNCONNECTED_533 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_534 ( .LO ( optlc_net_532 ) , +sky130_fd_sc_hd__conb_1 optlc_533 ( .LO ( optlc_net_532 ) , .HI ( SYNOPSYS_UNCONNECTED_534 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_535 ( .LO ( optlc_net_533 ) , +sky130_fd_sc_hd__conb_1 optlc_534 ( .LO ( optlc_net_533 ) , .HI ( SYNOPSYS_UNCONNECTED_535 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_536 ( .LO ( optlc_net_534 ) , +sky130_fd_sc_hd__conb_1 optlc_535 ( .LO ( optlc_net_534 ) , .HI ( SYNOPSYS_UNCONNECTED_536 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_537 ( .LO ( optlc_net_535 ) , +sky130_fd_sc_hd__conb_1 optlc_536 ( .LO ( optlc_net_535 ) , .HI ( SYNOPSYS_UNCONNECTED_537 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_538 ( .LO ( optlc_net_536 ) , +sky130_fd_sc_hd__conb_1 optlc_537 ( .LO ( optlc_net_536 ) , .HI ( SYNOPSYS_UNCONNECTED_538 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_539 ( .LO ( optlc_net_537 ) , +sky130_fd_sc_hd__conb_1 optlc_538 ( .LO ( optlc_net_537 ) , .HI ( SYNOPSYS_UNCONNECTED_539 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_540 ( .LO ( optlc_net_538 ) , +sky130_fd_sc_hd__conb_1 optlc_539 ( .LO ( optlc_net_538 ) , .HI ( SYNOPSYS_UNCONNECTED_540 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_541 ( .LO ( optlc_net_539 ) , +sky130_fd_sc_hd__conb_1 optlc_540 ( .LO ( optlc_net_539 ) , .HI ( SYNOPSYS_UNCONNECTED_541 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_542 ( .LO ( optlc_net_540 ) , +sky130_fd_sc_hd__conb_1 optlc_541 ( .LO ( optlc_net_540 ) , .HI ( SYNOPSYS_UNCONNECTED_542 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_543 ( .LO ( optlc_net_541 ) , +sky130_fd_sc_hd__conb_1 optlc_542 ( .LO ( optlc_net_541 ) , .HI ( SYNOPSYS_UNCONNECTED_543 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_544 ( .LO ( optlc_net_542 ) , +sky130_fd_sc_hd__conb_1 optlc_543 ( .LO ( optlc_net_542 ) , .HI ( SYNOPSYS_UNCONNECTED_544 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_545 ( .LO ( optlc_net_543 ) , +sky130_fd_sc_hd__conb_1 optlc_544 ( .LO ( optlc_net_543 ) , .HI ( SYNOPSYS_UNCONNECTED_545 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_546 ( .LO ( optlc_net_544 ) , +sky130_fd_sc_hd__conb_1 optlc_545 ( .LO ( optlc_net_544 ) , .HI ( SYNOPSYS_UNCONNECTED_546 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_547 ( .LO ( optlc_net_545 ) , +sky130_fd_sc_hd__conb_1 optlc_546 ( .LO ( optlc_net_545 ) , .HI ( SYNOPSYS_UNCONNECTED_547 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_548 ( .LO ( optlc_net_546 ) , +sky130_fd_sc_hd__conb_1 optlc_547 ( .LO ( optlc_net_546 ) , .HI ( SYNOPSYS_UNCONNECTED_548 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_549 ( .LO ( optlc_net_547 ) , +sky130_fd_sc_hd__conb_1 optlc_548 ( .LO ( optlc_net_547 ) , .HI ( SYNOPSYS_UNCONNECTED_549 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_550 ( .LO ( optlc_net_548 ) , +sky130_fd_sc_hd__conb_1 optlc_549 ( .LO ( optlc_net_548 ) , .HI ( SYNOPSYS_UNCONNECTED_550 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_551 ( .LO ( optlc_net_549 ) , +sky130_fd_sc_hd__conb_1 optlc_550 ( .LO ( optlc_net_549 ) , .HI ( SYNOPSYS_UNCONNECTED_551 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_552 ( .LO ( optlc_net_550 ) , +sky130_fd_sc_hd__conb_1 optlc_551 ( .LO ( optlc_net_550 ) , .HI ( SYNOPSYS_UNCONNECTED_552 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_553 ( .LO ( optlc_net_551 ) , +sky130_fd_sc_hd__conb_1 optlc_552 ( .LO ( optlc_net_551 ) , .HI ( SYNOPSYS_UNCONNECTED_553 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_554 ( .LO ( optlc_net_552 ) , +sky130_fd_sc_hd__conb_1 optlc_553 ( .LO ( optlc_net_552 ) , .HI ( SYNOPSYS_UNCONNECTED_554 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_555 ( .LO ( optlc_net_553 ) , +sky130_fd_sc_hd__conb_1 optlc_554 ( .LO ( optlc_net_553 ) , .HI ( SYNOPSYS_UNCONNECTED_555 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_556 ( .LO ( optlc_net_554 ) , +sky130_fd_sc_hd__conb_1 optlc_555 ( .LO ( optlc_net_554 ) , .HI ( SYNOPSYS_UNCONNECTED_556 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_557 ( .LO ( optlc_net_555 ) , +sky130_fd_sc_hd__conb_1 optlc_556 ( .LO ( optlc_net_555 ) , .HI ( SYNOPSYS_UNCONNECTED_557 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_558 ( .LO ( optlc_net_556 ) , +sky130_fd_sc_hd__conb_1 optlc_557 ( .LO ( optlc_net_556 ) , .HI ( SYNOPSYS_UNCONNECTED_558 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_559 ( .LO ( optlc_net_557 ) , +sky130_fd_sc_hd__conb_1 optlc_558 ( .LO ( optlc_net_557 ) , .HI ( SYNOPSYS_UNCONNECTED_559 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_561 ( .LO ( optlc_net_558 ) , +sky130_fd_sc_hd__conb_1 optlc_559 ( .LO ( optlc_net_558 ) , .HI ( SYNOPSYS_UNCONNECTED_560 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_562 ( .LO ( optlc_net_559 ) , +sky130_fd_sc_hd__conb_1 optlc_560 ( .LO ( optlc_net_559 ) , .HI ( SYNOPSYS_UNCONNECTED_561 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_563 ( .LO ( optlc_net_560 ) , +sky130_fd_sc_hd__conb_1 optlc_561 ( .LO ( optlc_net_560 ) , .HI ( SYNOPSYS_UNCONNECTED_562 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_564 ( .LO ( optlc_net_561 ) , +sky130_fd_sc_hd__conb_1 optlc_562 ( .LO ( optlc_net_561 ) , .HI ( SYNOPSYS_UNCONNECTED_563 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_565 ( .LO ( optlc_net_562 ) , +sky130_fd_sc_hd__conb_1 optlc_563 ( .LO ( optlc_net_562 ) , .HI ( SYNOPSYS_UNCONNECTED_564 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_566 ( .LO ( optlc_net_563 ) , +sky130_fd_sc_hd__conb_1 optlc_564 ( .LO ( optlc_net_563 ) , .HI ( SYNOPSYS_UNCONNECTED_565 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_567 ( .LO ( optlc_net_564 ) , +sky130_fd_sc_hd__conb_1 optlc_565 ( .LO ( optlc_net_564 ) , .HI ( SYNOPSYS_UNCONNECTED_566 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_568 ( .LO ( optlc_net_565 ) , +sky130_fd_sc_hd__conb_1 optlc_566 ( .LO ( optlc_net_565 ) , .HI ( SYNOPSYS_UNCONNECTED_567 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_569 ( .LO ( optlc_net_566 ) , +sky130_fd_sc_hd__conb_1 optlc_567 ( .LO ( optlc_net_566 ) , .HI ( SYNOPSYS_UNCONNECTED_568 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_570 ( .LO ( optlc_net_567 ) , +sky130_fd_sc_hd__conb_1 optlc_568 ( .LO ( optlc_net_567 ) , .HI ( SYNOPSYS_UNCONNECTED_569 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_571 ( .LO ( optlc_net_568 ) , +sky130_fd_sc_hd__conb_1 optlc_569 ( .LO ( optlc_net_568 ) , .HI ( SYNOPSYS_UNCONNECTED_570 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_572 ( .LO ( optlc_net_569 ) , +sky130_fd_sc_hd__conb_1 optlc_570 ( .LO ( optlc_net_569 ) , .HI ( SYNOPSYS_UNCONNECTED_571 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_573 ( .LO ( optlc_net_570 ) , +sky130_fd_sc_hd__conb_1 optlc_571 ( .LO ( optlc_net_570 ) , .HI ( SYNOPSYS_UNCONNECTED_572 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_574 ( .LO ( optlc_net_571 ) , +sky130_fd_sc_hd__conb_1 optlc_572 ( .LO ( optlc_net_571 ) , .HI ( SYNOPSYS_UNCONNECTED_573 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_575 ( .LO ( optlc_net_572 ) , +sky130_fd_sc_hd__conb_1 optlc_573 ( .LO ( optlc_net_572 ) , .HI ( SYNOPSYS_UNCONNECTED_574 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_576 ( .LO ( optlc_net_573 ) , +sky130_fd_sc_hd__conb_1 optlc_574 ( .LO ( optlc_net_573 ) , .HI ( SYNOPSYS_UNCONNECTED_575 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_577 ( .LO ( optlc_net_574 ) , +sky130_fd_sc_hd__conb_1 optlc_575 ( .LO ( optlc_net_574 ) , .HI ( SYNOPSYS_UNCONNECTED_576 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_578 ( .LO ( optlc_net_575 ) , +sky130_fd_sc_hd__conb_1 optlc_576 ( .LO ( optlc_net_575 ) , .HI ( SYNOPSYS_UNCONNECTED_577 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_579 ( .LO ( optlc_net_576 ) , +sky130_fd_sc_hd__conb_1 optlc_577 ( .LO ( optlc_net_576 ) , .HI ( SYNOPSYS_UNCONNECTED_578 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_580 ( .LO ( optlc_net_577 ) , +sky130_fd_sc_hd__conb_1 optlc_578 ( .LO ( optlc_net_577 ) , .HI ( SYNOPSYS_UNCONNECTED_579 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_581 ( .LO ( optlc_net_578 ) , +sky130_fd_sc_hd__conb_1 optlc_579 ( .LO ( optlc_net_578 ) , .HI ( SYNOPSYS_UNCONNECTED_580 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_582 ( .LO ( optlc_net_579 ) , +sky130_fd_sc_hd__conb_1 optlc_580 ( .LO ( optlc_net_579 ) , .HI ( SYNOPSYS_UNCONNECTED_581 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_583 ( .LO ( optlc_net_580 ) , +sky130_fd_sc_hd__conb_1 optlc_581 ( .LO ( optlc_net_580 ) , .HI ( SYNOPSYS_UNCONNECTED_582 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_584 ( .LO ( optlc_net_581 ) , +sky130_fd_sc_hd__conb_1 optlc_582 ( .LO ( optlc_net_581 ) , .HI ( SYNOPSYS_UNCONNECTED_583 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_585 ( .LO ( optlc_net_582 ) , +sky130_fd_sc_hd__conb_1 optlc_583 ( .LO ( optlc_net_582 ) , .HI ( SYNOPSYS_UNCONNECTED_584 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_586 ( .LO ( optlc_net_583 ) , +sky130_fd_sc_hd__conb_1 optlc_584 ( .LO ( optlc_net_583 ) , .HI ( SYNOPSYS_UNCONNECTED_585 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_587 ( .LO ( optlc_net_584 ) , +sky130_fd_sc_hd__conb_1 optlc_585 ( .LO ( optlc_net_584 ) , .HI ( SYNOPSYS_UNCONNECTED_586 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_588 ( .LO ( optlc_net_585 ) , +sky130_fd_sc_hd__conb_1 optlc_586 ( .LO ( optlc_net_585 ) , .HI ( SYNOPSYS_UNCONNECTED_587 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_589 ( .LO ( optlc_net_586 ) , +sky130_fd_sc_hd__conb_1 optlc_587 ( .LO ( optlc_net_586 ) , .HI ( SYNOPSYS_UNCONNECTED_588 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_590 ( .LO ( optlc_net_587 ) , +sky130_fd_sc_hd__conb_1 optlc_588 ( .LO ( optlc_net_587 ) , .HI ( SYNOPSYS_UNCONNECTED_589 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_591 ( .LO ( optlc_net_588 ) , +sky130_fd_sc_hd__conb_1 optlc_589 ( .LO ( optlc_net_588 ) , .HI ( SYNOPSYS_UNCONNECTED_590 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_592 ( .LO ( optlc_net_589 ) , +sky130_fd_sc_hd__conb_1 optlc_590 ( .LO ( optlc_net_589 ) , .HI ( SYNOPSYS_UNCONNECTED_591 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_593 ( .LO ( optlc_net_590 ) , +sky130_fd_sc_hd__conb_1 optlc_591 ( .LO ( optlc_net_590 ) , .HI ( SYNOPSYS_UNCONNECTED_592 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_594 ( .LO ( optlc_net_591 ) , +sky130_fd_sc_hd__conb_1 optlc_592 ( .LO ( optlc_net_591 ) , .HI ( SYNOPSYS_UNCONNECTED_593 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_595 ( .LO ( optlc_net_592 ) , +sky130_fd_sc_hd__conb_1 optlc_593 ( .LO ( optlc_net_592 ) , .HI ( SYNOPSYS_UNCONNECTED_594 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_596 ( .LO ( optlc_net_593 ) , +sky130_fd_sc_hd__conb_1 optlc_594 ( .LO ( optlc_net_593 ) , .HI ( SYNOPSYS_UNCONNECTED_595 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_597 ( .LO ( optlc_net_594 ) , +sky130_fd_sc_hd__conb_1 optlc_595 ( .LO ( optlc_net_594 ) , .HI ( SYNOPSYS_UNCONNECTED_596 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_598 ( .LO ( optlc_net_595 ) , +sky130_fd_sc_hd__conb_1 optlc_596 ( .LO ( optlc_net_595 ) , .HI ( SYNOPSYS_UNCONNECTED_597 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_599 ( .LO ( optlc_net_596 ) , +sky130_fd_sc_hd__conb_1 optlc_597 ( .LO ( optlc_net_596 ) , .HI ( SYNOPSYS_UNCONNECTED_598 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_600 ( .LO ( optlc_net_597 ) , +sky130_fd_sc_hd__conb_1 optlc_598 ( .LO ( optlc_net_597 ) , .HI ( SYNOPSYS_UNCONNECTED_599 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_601 ( .LO ( optlc_net_598 ) , +sky130_fd_sc_hd__conb_1 optlc_599 ( .LO ( optlc_net_598 ) , .HI ( SYNOPSYS_UNCONNECTED_600 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_602 ( .LO ( optlc_net_599 ) , +sky130_fd_sc_hd__conb_1 optlc_600 ( .LO ( optlc_net_599 ) , .HI ( SYNOPSYS_UNCONNECTED_601 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_603 ( .LO ( optlc_net_600 ) , +sky130_fd_sc_hd__conb_1 optlc_601 ( .LO ( optlc_net_600 ) , .HI ( SYNOPSYS_UNCONNECTED_602 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_604 ( .LO ( optlc_net_601 ) , +sky130_fd_sc_hd__conb_1 optlc_602 ( .LO ( optlc_net_601 ) , .HI ( SYNOPSYS_UNCONNECTED_603 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_605 ( .LO ( optlc_net_602 ) , +sky130_fd_sc_hd__conb_1 optlc_603 ( .LO ( optlc_net_602 ) , .HI ( SYNOPSYS_UNCONNECTED_604 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_606 ( .LO ( optlc_net_603 ) , +sky130_fd_sc_hd__conb_1 optlc_604 ( .LO ( optlc_net_603 ) , .HI ( SYNOPSYS_UNCONNECTED_605 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_607 ( .LO ( optlc_net_604 ) , +sky130_fd_sc_hd__conb_1 optlc_605 ( .LO ( optlc_net_604 ) , .HI ( SYNOPSYS_UNCONNECTED_606 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_608 ( .LO ( optlc_net_605 ) , +sky130_fd_sc_hd__conb_1 optlc_606 ( .LO ( optlc_net_605 ) , .HI ( SYNOPSYS_UNCONNECTED_607 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_609 ( .LO ( optlc_net_606 ) , +sky130_fd_sc_hd__conb_1 optlc_607 ( .LO ( optlc_net_606 ) , .HI ( SYNOPSYS_UNCONNECTED_608 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_610 ( .LO ( optlc_net_607 ) , +sky130_fd_sc_hd__conb_1 optlc_608 ( .LO ( optlc_net_607 ) , .HI ( SYNOPSYS_UNCONNECTED_609 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_611 ( .LO ( optlc_net_608 ) , +sky130_fd_sc_hd__conb_1 optlc_609 ( .LO ( optlc_net_608 ) , .HI ( SYNOPSYS_UNCONNECTED_610 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_612 ( .LO ( optlc_net_609 ) , +sky130_fd_sc_hd__conb_1 optlc_610 ( .LO ( optlc_net_609 ) , .HI ( SYNOPSYS_UNCONNECTED_611 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_613 ( .LO ( optlc_net_610 ) , +sky130_fd_sc_hd__conb_1 optlc_611 ( .LO ( optlc_net_610 ) , .HI ( SYNOPSYS_UNCONNECTED_612 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_614 ( .LO ( optlc_net_611 ) , +sky130_fd_sc_hd__conb_1 optlc_612 ( .LO ( optlc_net_611 ) , .HI ( SYNOPSYS_UNCONNECTED_613 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_615 ( .LO ( optlc_net_612 ) , +sky130_fd_sc_hd__conb_1 optlc_613 ( .LO ( optlc_net_612 ) , .HI ( SYNOPSYS_UNCONNECTED_614 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_616 ( .LO ( optlc_net_613 ) , +sky130_fd_sc_hd__conb_1 optlc_614 ( .LO ( optlc_net_613 ) , .HI ( SYNOPSYS_UNCONNECTED_615 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_617 ( .LO ( optlc_net_614 ) , +sky130_fd_sc_hd__conb_1 optlc_615 ( .LO ( optlc_net_614 ) , .HI ( SYNOPSYS_UNCONNECTED_616 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_618 ( .LO ( optlc_net_615 ) , +sky130_fd_sc_hd__conb_1 optlc_616 ( .LO ( optlc_net_615 ) , .HI ( SYNOPSYS_UNCONNECTED_617 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_619 ( .LO ( optlc_net_616 ) , +sky130_fd_sc_hd__conb_1 optlc_617 ( .LO ( optlc_net_616 ) , .HI ( SYNOPSYS_UNCONNECTED_618 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_620 ( .LO ( optlc_net_617 ) , +sky130_fd_sc_hd__conb_1 optlc_618 ( .LO ( optlc_net_617 ) , .HI ( SYNOPSYS_UNCONNECTED_619 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_621 ( .LO ( optlc_net_618 ) , +sky130_fd_sc_hd__conb_1 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optlc_644 ( .LO ( optlc_net_643 ) , .HI ( SYNOPSYS_UNCONNECTED_645 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_647 ( .LO ( optlc_net_644 ) , +sky130_fd_sc_hd__conb_1 optlc_645 ( .LO ( optlc_net_644 ) , .HI ( SYNOPSYS_UNCONNECTED_646 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_648 ( .LO ( optlc_net_645 ) , +sky130_fd_sc_hd__conb_1 optlc_646 ( .LO ( optlc_net_645 ) , .HI ( SYNOPSYS_UNCONNECTED_647 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_649 ( .LO ( optlc_net_646 ) , +sky130_fd_sc_hd__conb_1 optlc_647 ( .LO ( optlc_net_646 ) , .HI ( SYNOPSYS_UNCONNECTED_648 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_650 ( .LO ( optlc_net_647 ) , +sky130_fd_sc_hd__conb_1 optlc_648 ( .LO ( optlc_net_647 ) , .HI ( SYNOPSYS_UNCONNECTED_649 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_651 ( .LO ( optlc_net_648 ) , +sky130_fd_sc_hd__conb_1 optlc_649 ( .LO ( optlc_net_648 ) , .HI ( SYNOPSYS_UNCONNECTED_650 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_652 ( .LO ( optlc_net_649 ) , +sky130_fd_sc_hd__conb_1 optlc_650 ( .LO ( optlc_net_649 ) , .HI ( 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SYNOPSYS_UNCONNECTED_3515 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_3974 ( .LO ( optlc_net_3514 ) , +sky130_fd_sc_hd__conb_1 optlc_3865 ( .LO ( optlc_net_3514 ) , .HI ( SYNOPSYS_UNCONNECTED_3516 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_3975 ( .LO ( optlc_net_3515 ) , +sky130_fd_sc_hd__conb_1 optlc_3866 ( .LO ( optlc_net_3515 ) , .HI ( SYNOPSYS_UNCONNECTED_3517 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_3976 ( .LO ( optlc_net_3516 ) , +sky130_fd_sc_hd__conb_1 optlc_3867 ( .LO ( optlc_net_3516 ) , .HI ( SYNOPSYS_UNCONNECTED_3518 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_3977 ( .LO ( optlc_net_3517 ) , +sky130_fd_sc_hd__conb_1 optlc_3868 ( .LO ( optlc_net_3517 ) , .HI ( SYNOPSYS_UNCONNECTED_3519 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_3978 ( .LO ( optlc_net_3518 ) , +sky130_fd_sc_hd__conb_1 optlc_3869 ( .LO ( optlc_net_3518 ) , .HI ( SYNOPSYS_UNCONNECTED_3520 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_3979 ( .LO ( optlc_net_3519 ) , +sky130_fd_sc_hd__conb_1 optlc_3870 ( .LO ( optlc_net_3519 ) , .HI ( SYNOPSYS_UNCONNECTED_3521 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_3980 ( .LO ( optlc_net_3520 ) , +sky130_fd_sc_hd__conb_1 optlc_3871 ( .LO ( optlc_net_3520 ) , .HI ( SYNOPSYS_UNCONNECTED_3522 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_3981 ( .LO ( optlc_net_3521 ) , +sky130_fd_sc_hd__conb_1 optlc_3872 ( .LO ( optlc_net_3521 ) , .HI ( SYNOPSYS_UNCONNECTED_3523 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_3982 ( .LO ( optlc_net_3522 ) , +sky130_fd_sc_hd__conb_1 optlc_3873 ( .LO ( optlc_net_3522 ) , .HI ( SYNOPSYS_UNCONNECTED_3524 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_3983 ( .LO ( optlc_net_3523 ) , +sky130_fd_sc_hd__conb_1 optlc_3874 ( .LO ( optlc_net_3523 ) , .HI ( SYNOPSYS_UNCONNECTED_3525 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_3984 ( .LO ( optlc_net_3524 ) , +sky130_fd_sc_hd__conb_1 optlc_3875 ( .LO ( optlc_net_3524 ) , .HI ( SYNOPSYS_UNCONNECTED_3526 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_3985 ( .LO ( optlc_net_3525 ) , +sky130_fd_sc_hd__conb_1 optlc_3876 ( .LO ( optlc_net_3525 ) , .HI ( SYNOPSYS_UNCONNECTED_3527 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_3986 ( .LO ( optlc_net_3526 ) , +sky130_fd_sc_hd__conb_1 optlc_3877 ( .LO ( optlc_net_3526 ) , .HI ( SYNOPSYS_UNCONNECTED_3528 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_3987 ( .LO ( optlc_net_3527 ) , +sky130_fd_sc_hd__conb_1 optlc_3878 ( .LO ( optlc_net_3527 ) , .HI ( SYNOPSYS_UNCONNECTED_3529 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_3988 ( .LO ( optlc_net_3528 ) , +sky130_fd_sc_hd__conb_1 optlc_3879 ( .LO ( optlc_net_3528 ) , .HI ( SYNOPSYS_UNCONNECTED_3530 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_3989 ( .LO ( optlc_net_3529 ) , +sky130_fd_sc_hd__conb_1 optlc_3880 ( .LO ( optlc_net_3529 ) , .HI ( SYNOPSYS_UNCONNECTED_3531 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3881 ( .LO ( optlc_net_3530 ) , + .HI ( SYNOPSYS_UNCONNECTED_3532 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3882 ( .LO ( optlc_net_3531 ) , + .HI ( SYNOPSYS_UNCONNECTED_3533 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3883 ( .LO ( optlc_net_3532 ) , + .HI ( SYNOPSYS_UNCONNECTED_3534 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3884 ( .LO ( optlc_net_3533 ) , + .HI ( SYNOPSYS_UNCONNECTED_3535 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3885 ( .LO ( optlc_net_3534 ) , + .HI ( SYNOPSYS_UNCONNECTED_3536 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3886 ( .LO ( optlc_net_3535 ) , + .HI ( SYNOPSYS_UNCONNECTED_3537 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3887 ( .LO ( optlc_net_3536 ) , + .HI ( SYNOPSYS_UNCONNECTED_3538 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3888 ( .LO ( optlc_net_3537 ) , + .HI ( SYNOPSYS_UNCONNECTED_3539 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3889 ( .LO ( optlc_net_3538 ) , + .HI ( SYNOPSYS_UNCONNECTED_3540 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3890 ( .LO ( optlc_net_3539 ) , + .HI ( SYNOPSYS_UNCONNECTED_3541 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3891 ( .LO ( optlc_net_3540 ) , + .HI ( SYNOPSYS_UNCONNECTED_3542 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3892 ( .LO ( optlc_net_3541 ) , + .HI ( SYNOPSYS_UNCONNECTED_3543 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3893 ( .LO ( optlc_net_3542 ) , + .HI ( SYNOPSYS_UNCONNECTED_3544 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3894 ( .LO ( optlc_net_3543 ) , + .HI ( SYNOPSYS_UNCONNECTED_3545 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3895 ( .LO ( optlc_net_3544 ) , + .HI ( SYNOPSYS_UNCONNECTED_3546 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3896 ( .LO ( optlc_net_3545 ) , + .HI ( SYNOPSYS_UNCONNECTED_3547 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3897 ( .LO ( optlc_net_3546 ) , + .HI ( SYNOPSYS_UNCONNECTED_3548 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3898 ( .LO ( optlc_net_3547 ) , + .HI ( SYNOPSYS_UNCONNECTED_3549 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3899 ( .LO ( optlc_net_3548 ) , + .HI ( SYNOPSYS_UNCONNECTED_3550 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3900 ( .LO ( optlc_net_3549 ) , + .HI ( SYNOPSYS_UNCONNECTED_3551 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3901 ( .LO ( optlc_net_3550 ) , + .HI ( SYNOPSYS_UNCONNECTED_3552 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3902 ( .LO ( optlc_net_3551 ) , + .HI ( SYNOPSYS_UNCONNECTED_3553 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3903 ( .LO ( optlc_net_3552 ) , + .HI ( SYNOPSYS_UNCONNECTED_3554 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3904 ( .LO ( optlc_net_3553 ) , + .HI ( SYNOPSYS_UNCONNECTED_3555 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3905 ( .LO ( optlc_net_3554 ) , + .HI ( SYNOPSYS_UNCONNECTED_3556 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3906 ( .LO ( optlc_net_3555 ) , + .HI ( SYNOPSYS_UNCONNECTED_3557 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3907 ( .LO ( optlc_net_3556 ) , + .HI ( SYNOPSYS_UNCONNECTED_3558 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3908 ( .LO ( optlc_net_3557 ) , + .HI ( SYNOPSYS_UNCONNECTED_3559 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3909 ( .LO ( optlc_net_3558 ) , + .HI ( SYNOPSYS_UNCONNECTED_3560 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3910 ( .LO ( optlc_net_3559 ) , + .HI ( SYNOPSYS_UNCONNECTED_3561 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3911 ( .LO ( optlc_net_3560 ) , + .HI ( SYNOPSYS_UNCONNECTED_3562 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3912 ( .LO ( optlc_net_3561 ) , + .HI ( SYNOPSYS_UNCONNECTED_3563 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3913 ( .LO ( optlc_net_3562 ) , + .HI ( SYNOPSYS_UNCONNECTED_3564 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3914 ( .LO ( optlc_net_3563 ) , + .HI ( SYNOPSYS_UNCONNECTED_3565 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3915 ( .LO ( optlc_net_3564 ) , + .HI ( SYNOPSYS_UNCONNECTED_3566 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3916 ( .LO ( optlc_net_3565 ) , + .HI ( SYNOPSYS_UNCONNECTED_3567 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3917 ( .LO ( optlc_net_3566 ) , + .HI ( SYNOPSYS_UNCONNECTED_3568 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3918 ( .LO ( optlc_net_3567 ) , + .HI ( SYNOPSYS_UNCONNECTED_3569 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3919 ( .LO ( optlc_net_3568 ) , + .HI ( SYNOPSYS_UNCONNECTED_3570 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3920 ( .LO ( optlc_net_3569 ) , + .HI ( SYNOPSYS_UNCONNECTED_3571 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3921 ( .LO ( optlc_net_3570 ) , + .HI ( SYNOPSYS_UNCONNECTED_3572 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3922 ( .LO ( optlc_net_3571 ) , + .HI ( SYNOPSYS_UNCONNECTED_3573 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3923 ( .LO ( optlc_net_3572 ) , + .HI ( SYNOPSYS_UNCONNECTED_3574 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3924 ( .LO ( optlc_net_3573 ) , + .HI ( SYNOPSYS_UNCONNECTED_3575 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3925 ( .LO ( optlc_net_3574 ) , + .HI ( SYNOPSYS_UNCONNECTED_3576 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3926 ( .LO ( optlc_net_3575 ) , + .HI ( SYNOPSYS_UNCONNECTED_3577 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3927 ( .LO ( optlc_net_3576 ) , + .HI ( SYNOPSYS_UNCONNECTED_3578 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3928 ( .LO ( optlc_net_3577 ) , + .HI ( SYNOPSYS_UNCONNECTED_3579 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3929 ( .LO ( optlc_net_3578 ) , + .HI ( SYNOPSYS_UNCONNECTED_3580 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3930 ( .LO ( optlc_net_3579 ) , + .HI ( SYNOPSYS_UNCONNECTED_3581 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3931 ( .LO ( optlc_net_3580 ) , + .HI ( SYNOPSYS_UNCONNECTED_3582 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3932 ( .LO ( optlc_net_3581 ) , + .HI ( SYNOPSYS_UNCONNECTED_3583 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3933 ( .LO ( optlc_net_3582 ) , + .HI ( SYNOPSYS_UNCONNECTED_3584 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3934 ( .LO ( optlc_net_3583 ) , + .HI ( SYNOPSYS_UNCONNECTED_3585 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3935 ( .LO ( optlc_net_3584 ) , + .HI ( SYNOPSYS_UNCONNECTED_3586 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3936 ( .LO ( optlc_net_3585 ) , + .HI ( SYNOPSYS_UNCONNECTED_3587 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3937 ( .LO ( optlc_net_3586 ) , + .HI ( SYNOPSYS_UNCONNECTED_3588 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3938 ( .LO ( optlc_net_3587 ) , + .HI ( SYNOPSYS_UNCONNECTED_3589 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3939 ( .LO ( optlc_net_3588 ) , + .HI ( SYNOPSYS_UNCONNECTED_3590 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3940 ( .LO ( optlc_net_3589 ) , + .HI ( SYNOPSYS_UNCONNECTED_3591 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3941 ( .LO ( optlc_net_3590 ) , + .HI ( SYNOPSYS_UNCONNECTED_3592 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3942 ( .LO ( optlc_net_3591 ) , + .HI ( SYNOPSYS_UNCONNECTED_3593 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3943 ( .LO ( optlc_net_3592 ) , + .HI ( SYNOPSYS_UNCONNECTED_3594 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3944 ( .LO ( optlc_net_3593 ) , + .HI ( SYNOPSYS_UNCONNECTED_3595 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3945 ( .LO ( optlc_net_3594 ) , + .HI ( SYNOPSYS_UNCONNECTED_3596 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3946 ( .LO ( optlc_net_3595 ) , + .HI ( SYNOPSYS_UNCONNECTED_3597 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3947 ( .LO ( optlc_net_3596 ) , + .HI ( SYNOPSYS_UNCONNECTED_3598 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3948 ( .LO ( optlc_net_3597 ) , + .HI ( SYNOPSYS_UNCONNECTED_3599 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3949 ( .LO ( optlc_net_3598 ) , + .HI ( SYNOPSYS_UNCONNECTED_3600 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3950 ( .LO ( optlc_net_3599 ) , + .HI ( SYNOPSYS_UNCONNECTED_3601 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3951 ( .LO ( optlc_net_3600 ) , + .HI ( SYNOPSYS_UNCONNECTED_3602 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3952 ( .LO ( optlc_net_3601 ) , + .HI ( SYNOPSYS_UNCONNECTED_3603 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3953 ( .LO ( optlc_net_3602 ) , + .HI ( SYNOPSYS_UNCONNECTED_3604 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3954 ( .LO ( optlc_net_3603 ) , + .HI ( SYNOPSYS_UNCONNECTED_3605 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3955 ( .LO ( optlc_net_3604 ) , + .HI ( SYNOPSYS_UNCONNECTED_3606 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3956 ( .LO ( optlc_net_3605 ) , + .HI ( SYNOPSYS_UNCONNECTED_3607 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3957 ( .LO ( optlc_net_3606 ) , + .HI ( SYNOPSYS_UNCONNECTED_3608 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3958 ( .LO ( optlc_net_3607 ) , + .HI ( SYNOPSYS_UNCONNECTED_3609 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3959 ( .LO ( optlc_net_3608 ) , + .HI ( SYNOPSYS_UNCONNECTED_3610 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3960 ( .LO ( optlc_net_3609 ) , + .HI ( SYNOPSYS_UNCONNECTED_3611 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3961 ( .LO ( optlc_net_3610 ) , + .HI ( SYNOPSYS_UNCONNECTED_3612 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3962 ( .LO ( optlc_net_3611 ) , + .HI ( SYNOPSYS_UNCONNECTED_3613 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3963 ( .LO ( optlc_net_3612 ) , + .HI ( SYNOPSYS_UNCONNECTED_3614 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3964 ( .LO ( optlc_net_3613 ) , + .HI ( SYNOPSYS_UNCONNECTED_3615 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3965 ( .LO ( optlc_net_3614 ) , + .HI ( SYNOPSYS_UNCONNECTED_3616 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3966 ( .LO ( optlc_net_3615 ) , + .HI ( SYNOPSYS_UNCONNECTED_3617 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3967 ( .LO ( optlc_net_3616 ) , + .HI ( SYNOPSYS_UNCONNECTED_3618 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3968 ( .LO ( optlc_net_3617 ) , + .HI ( SYNOPSYS_UNCONNECTED_3619 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3969 ( .LO ( optlc_net_3618 ) , + .HI ( SYNOPSYS_UNCONNECTED_3620 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3970 ( .LO ( optlc_net_3619 ) , + .HI ( SYNOPSYS_UNCONNECTED_3621 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3971 ( .LO ( optlc_net_3620 ) , + .HI ( SYNOPSYS_UNCONNECTED_3622 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3972 ( .LO ( optlc_net_3621 ) , + .HI ( SYNOPSYS_UNCONNECTED_3623 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3973 ( .LO ( optlc_net_3622 ) , + .HI ( SYNOPSYS_UNCONNECTED_3624 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3974 ( .LO ( optlc_net_3623 ) , + .HI ( SYNOPSYS_UNCONNECTED_3625 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3975 ( .LO ( optlc_net_3624 ) , + .HI ( SYNOPSYS_UNCONNECTED_3626 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3976 ( .LO ( optlc_net_3625 ) , + .HI ( SYNOPSYS_UNCONNECTED_3627 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3977 ( .LO ( optlc_net_3626 ) , + .HI ( SYNOPSYS_UNCONNECTED_3628 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3978 ( .LO ( optlc_net_3627 ) , + .HI ( SYNOPSYS_UNCONNECTED_3629 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3979 ( .LO ( optlc_net_3628 ) , + .HI ( SYNOPSYS_UNCONNECTED_3630 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3980 ( .LO ( optlc_net_3629 ) , + .HI ( SYNOPSYS_UNCONNECTED_3631 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3981 ( .LO ( optlc_net_3630 ) , + .HI ( SYNOPSYS_UNCONNECTED_3632 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3982 ( .LO ( optlc_net_3631 ) , + .HI ( SYNOPSYS_UNCONNECTED_3633 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3983 ( .LO ( optlc_net_3632 ) , + .HI ( SYNOPSYS_UNCONNECTED_3634 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3984 ( .LO ( optlc_net_3633 ) , + .HI ( SYNOPSYS_UNCONNECTED_3635 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3985 ( .LO ( optlc_net_3634 ) , + .HI ( SYNOPSYS_UNCONNECTED_3636 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3986 ( .LO ( optlc_net_3635 ) , + .HI ( SYNOPSYS_UNCONNECTED_3637 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3987 ( .LO ( optlc_net_3636 ) , + .HI ( SYNOPSYS_UNCONNECTED_3638 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3988 ( .LO ( optlc_net_3637 ) , + .HI ( SYNOPSYS_UNCONNECTED_3639 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3989 ( .LO ( optlc_net_3638 ) , + .HI ( SYNOPSYS_UNCONNECTED_3640 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3990 ( .LO ( optlc_net_3639 ) , + .HI ( SYNOPSYS_UNCONNECTED_3641 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3991 ( .LO ( optlc_net_3640 ) , + .HI ( SYNOPSYS_UNCONNECTED_3642 ) ) ; endmodule

p VNB $end + +$scope module base $end +$var wire 1 aK Q $end +$var wire 1 qJ CLK $end +$var wire 1 `K D $end +$var wire 1 NH RESET_B $end +$var wire 1 ?p buf_Q $end +$var wire 1 @p RESET $end +$upscope $end +$upscope $end + +$scope module FTB_75__74 $end +$var wire 1 gK X $end +$var wire 1 aK A $end +$var supply1 1 Ap VPWR $end +$var supply0 1 Bp VGND $end +$var supply1 1 Cp VPB $end +$var supply0 1 Dp VNB $end + +$scope module base $end +$var wire 1 gK X $end +$var wire 1 aK A $end +$var wire 1 Ep buf0_out_X $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mux_top_track_20 $end +$var wire 1 qH in [0] $end +$var wire 1 WJ in [1] $end +$var wire 1 9J in [2] $end +$var wire 1 ;K sram [0] $end +$var wire 1 K sram [1] $end +$var wire 1 6N sram_inv [0] $end +$var wire 1 7N sram_inv [1] $end +$var wire 1 qI out [0] $end +$var wire 1 ,M p0 $end +$var wire 1 gp mux_2level_tapbuf_basis_input2_mem1_0_out [0] $end +$var wire 1 hp mux_2level_tapbuf_basis_input2_mem1_1_out [0] $end +$var wire 1 ip mux_2level_tapbuf_basis_input2_mem1_2_out [0] $end +$var wire 1 jp SYNOPSYS_UNCONNECTED_1 $end +$var wire 1 kp SYNOPSYS_UNCONNECTED_2 $end +$var wire 1 lp SYNOPSYS_UNCONNECTED_3 $end +$var wire 1 mp SYNOPSYS_UNCONNECTED_4 $end +$var wire 1 np BUF_net_176 $end + +$scope module mux_l1_in_0_ $end +$var wire 1 rH in [0] $end +$var wire 1 XJ in [1] $end +$var wire 1 =K mem [0] $end +$var wire 1 jp mem_inv [0] $end +$var wire 1 gp out [0] $end + +$scope module sky130_fd_sc_hd__mux2_1_0 $end +$var wire 1 gp X $end +$var wire 1 XJ A0 $end +$var wire 1 rH A1 $end +$var wire 1 =K S $end +$var supply1 1 op VPWR $end +$var supply0 1 pp VGND $end +$var supply1 1 qp VPB $end +$var supply0 1 rp VNB $end + +$scope module base $end +$var wire 1 gp X $end +$var wire 1 XJ A0 $end +$var wire 1 rH A1 $end +$var wire 1 =K S $end +$var wire 1 sp mux_2to10_out_X $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mux_l1_in_1_ $end +$var wire 1 :J in [0] $end +$var wire 1 kp in [1] $end +$var wire 1 =K mem [0] $end +$var wire 1 lp mem_inv [0] $end +$var wire 1 hp out [0] $end +$var wire 1 ,M p0 $end + +$scope module sky130_fd_sc_hd__mux2_1_0 $end +$var wire 1 hp X $end +$var wire 1 ,M A0 $end +$var wire 1 :J A1 $end +$var wire 1 =K S $end +$var supply1 1 tp VPWR $end +$var supply0 1 up VGND $end +$var supply1 1 vp VPB $end +$var supply0 1 wp VNB $end + +$scope module base $end +$var wire 1 hp X $end +$var wire 1 ,M A0 $end +$var wire 1 :J A1 $end +$var wire 1 =K S $end +$var wire 1 xp mux_2to10_out_X $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mux_l2_in_0_ $end +$var wire 1 gp in [0] $end +$var wire 1 hp in [1] $end +$var wire 1 >K mem [0] $end +$var wire 1 mp mem_inv [0] $end +$var wire 1 ip out [0] $end + +$scope module sky130_fd_sc_hd__mux2_1_0 $end +$var wire 1 ip X $end +$var wire 1 hp A0 $end +$var wire 1 gp A1 $end +$var wire 1 >K S $end +$var supply1 1 yp VPWR $end +$var supply0 1 zp VGND $end +$var supply1 1 {p VPB $end +$var supply0 1 |p VNB $end + +$scope module base $end +$var wire 1 ip X $end +$var wire 1 hp A0 $end +$var wire 1 gp A1 $end +$var wire 1 >K S $end +$var wire 1 }p mux_2to10_out_X $end +$upscope $end +$upscope $end +$upscope $end + +$scope module BINV_R_175 $end +$var wire 1 qI Y $end +$var wire 1 np A $end +$var supply1 1 ~p VPWR $end +$var supply0 1 !q VGND $end +$var supply1 1 "q VPB $end +$var supply0 1 #q VNB $end + +$scope module base $end +$var wire 1 qI Y $end +$var wire 1 np A $end +$var wire 1 $q not0_out_Y $end +$upscope $end +$upscope $end + +$scope module BINV_R_176 $end +$var wire 1 np Y $end +$var wire 1 ip A $end +$var supply1 1 %q VPWR $end +$var supply0 1 &q VGND $end +$var supply1 1 'q VPB $end +$var supply0 1 (q VNB $end + +$scope module base $end +$var wire 1 np Y $end +$var wire 1 ip A $end +$var wire 1 )q not0_out_Y $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mux_top_track_24 $end +$var wire 1 sH in [0] $end +$var wire 1 YJ in [1] $end +$var wire 1 ;J in [2] $end +$var wire 1 ?K sram [0] $end +$var wire 1 @K sram [1] $end +$var wire 1 8N sram_inv [0] $end +$var wire 1 9N sram_inv [1] $end +$var wire 1 rI out [0] $end +$var wire 1 ,M p0 $end +$var wire 1 *q mux_2level_tapbuf_basis_input2_mem1_0_out [0] $end +$var wire 1 +q mux_2level_tapbuf_basis_input2_mem1_1_out [0] $end +$var wire 1 ,q mux_2level_tapbuf_basis_input2_mem1_2_out [0] $end +$var wire 1 -q SYNOPSYS_UNCONNECTED_1 $end +$var wire 1 .q SYNOPSYS_UNCONNECTED_2 $end +$var wire 1 /q SYNOPSYS_UNCONNECTED_3 $end +$var wire 1 0q SYNOPSYS_UNCONNECTED_4 $end +$var wire 1 1q BUF_net_178 $end + +$scope module mux_l1_in_0_ $end +$var wire 1 sH in [0] $end +$var wire 1 YJ in [1] $end +$var wire 1 ?K mem [0] $end +$var wire 1 -q mem_inv [0] $end +$var wire 1 *q out [0] $end + +$scope module sky130_fd_sc_hd__mux2_1_0 $end +$var wire 1 *q X $end +$var wire 1 YJ A0 $end +$var wire 1 sH A1 $end +$var wire 1 ?K S $end +$var supply1 1 2q VPWR $end +$var supply0 1 3q VGND $end +$var supply1 1 4q VPB $end +$var supply0 1 5q VNB $end + +$scope module base $end +$var wire 1 *q X $end +$var wire 1 YJ A0 $end +$var wire 1 sH A1 $end +$var wire 1 ?K S $end +$var wire 1 6q mux_2to10_out_X $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mux_l1_in_1_ $end +$var wire 1 ;J in [0] $end +$var wire 1 .q in [1] $end +$var wire 1 ?K mem [0] $end +$var wire 1 /q mem_inv [0] $end +$var wire 1 +q out [0] $end +$var wire 1 ,M p0 $end + +$scope module sky130_fd_sc_hd__mux2_1_0 $end +$var wire 1 +q X $end +$var wire 1 ,M A0 $end +$var wire 1 ;J A1 $end +$var wire 1 ?K S $end +$var supply1 1 7q VPWR $end +$var supply0 1 8q VGND $end +$var supply1 1 9q VPB $end +$var supply0 1 :q VNB $end + +$scope module base $end +$var wire 1 +q X $end +$var wire 1 ,M A0 $end +$var wire 1 ;J A1 $end +$var wire 1 ?K S $end +$var wire 1 ;q mux_2to10_out_X $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mux_l2_in_0_ $end +$var wire 1 *q in [0] $end +$var wire 1 +q in [1] $end +$var wire 1 @K mem [0] $end +$var wire 1 0q mem_inv [0] $end +$var wire 1 ,q out [0] $end + +$scope module sky130_fd_sc_hd__mux2_1_0 $end +$var wire 1 ,q X $end +$var wire 1 +q A0 $end +$var wire 1 *q A1 $end +$var wire 1 @K S $end +$var supply1 1 q VPB $end +$var supply0 1 ?q VNB $end + +$scope module base $end +$var wire 1 ,q X $end +$var wire 1 +q A0 $end +$var wire 1 *q A1 $end +$var wire 1 @K S $end +$var wire 1 @q mux_2to10_out_X $end +$upscope $end +$upscope $end +$upscope $end + +$scope module BINV_R_177 $end +$var wire 1 rI Y $end +$var wire 1 1q A $end +$var supply1 1 Aq VPWR $end +$var supply0 1 Bq VGND $end +$var supply1 1 Cq VPB $end +$var supply0 1 Dq VNB $end + +$scope module base $end +$var wire 1 rI Y $end +$var wire 1 1q A $end +$var wire 1 Eq not0_out_Y $end +$upscope $end +$upscope $end + +$scope module BINV_R_178 $end +$var wire 1 1q Y $end +$var wire 1 ,q A $end +$var supply1 1 Fq VPWR $end +$var supply0 1 Gq VGND $end +$var supply1 1 Hq VPB $end +$var supply0 1 Iq VNB $end + +$scope module base $end +$var wire 1 1q Y $end +$var wire 1 ,q A $end +$var wire 1 Jq not0_out_Y $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mux_top_track_26 $end +$var wire 1 tH in [0] $end +$var wire 1 [J in [1] $end +$var wire 1 =J in [2] $end +$var wire 1 AK sram [0] $end +$var wire 1 BK sram [1] $end +$var wire 1 :N sram_inv [0] $end +$var wire 1 ;N sram_inv [1] $end +$var wire 1 sI out [0] $end +$var wire 1 ,M p0 $end +$var wire 1 Kq mux_2level_tapbuf_basis_input2_mem1_0_out [0] $end +$var wire 1 Lq mux_2level_tapbuf_basis_input2_mem1_1_out [0] $end +$var wire 1 Mq mux_2level_tapbuf_basis_input2_mem1_2_out [0] $end +$var wire 1 Nq SYNOPSYS_UNCONNECTED_1 $end +$var wire 1 Oq SYNOPSYS_UNCONNECTED_2 $end +$var wire 1 Pq SYNOPSYS_UNCONNECTED_3 $end +$var wire 1 Qq SYNOPSYS_UNCONNECTED_4 $end + +$scope module sky130_fd_sc_hd__buf_4_0_ $end +$var wire 1 sI X $end +$var wire 1 Mq A $end +$var supply1 1 Rq VPWR $end +$var supply0 1 Sq VGND $end +$var supply1 1 Tq VPB $end +$var supply0 1 Uq VNB $end + +$scope module base $end +$var wire 1 sI X $end +$var wire 1 Mq A $end +$var wire 1 Vq buf0_out_X $end +$upscope $end +$upscope $end + +$scope module mux_l1_in_0_ $end +$var wire 1 tH in [0] $end +$var wire 1 [J in [1] $end +$var wire 1 AK mem [0] $end +$var wire 1 Nq mem_inv [0] $end +$var wire 1 Kq out [0] $end + +$scope module sky130_fd_sc_hd__mux2_1_0 $end +$var wire 1 Kq X $end +$var wire 1 [J A0 $end +$var wire 1 tH A1 $end +$var wire 1 AK S $end +$var supply1 1 Wq VPWR $end +$var supply0 1 Xq VGND $end +$var supply1 1 Yq VPB $end +$var supply0 1 Zq VNB $end + +$scope module base $end +$var wire 1 Kq X $end +$var wire 1 [J A0 $end +$var wire 1 tH A1 $end +$var wire 1 AK S $end +$var wire 1 [q mux_2to10_out_X $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mux_l1_in_1_ $end +$var wire 1 =J in [0] $end +$var wire 1 Oq in [1] $end +$var wire 1 AK mem [0] $end +$var wire 1 Pq mem_inv [0] $end +$var wire 1 Lq out [0] $end +$var wire 1 ,M p0 $end + +$scope module sky130_fd_sc_hd__mux2_1_0 $end +$var wire 1 Lq X $end +$var wire 1 ,M A0 $end +$var wire 1 =J A1 $end +$var wire 1 AK S $end +$var supply1 1 \q VPWR $end +$var supply0 1 ]q VGND $end +$var supply1 1 ^q VPB $end +$var supply0 1 _q VNB $end + +$scope module base $end +$var wire 1 Lq X $end +$var wire 1 ,M A0 $end +$var wire 1 =J A1 $end +$var wire 1 AK S $end +$var wire 1 `q mux_2to10_out_X $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mux_l2_in_0_ $end +$var wire 1 Kq in [0] $end +$var wire 1 Lq in [1] $end +$var wire 1 BK mem [0] $end +$var wire 1 Qq mem_inv [0] $end +$var wire 1 Mq out [0] $end + +$scope module sky130_fd_sc_hd__mux2_1_0 $end +$var wire 1 Mq X $end +$var wire 1 Lq A0 $end +$var wire 1 Kq A1 $end +$var wire 1 BK S $end +$var supply1 1 aq VPWR $end +$var supply0 1 bq VGND $end +$var supply1 1 cq VPB $end +$var supply0 1 dq VNB $end + +$scope module base $end +$var wire 1 Mq X $end +$var wire 1 Lq A0 $end +$var wire 1 Kq A1 $end +$var wire 1 BK S $end +$var wire 1 eq mux_2to10_out_X $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mux_top_track_36 $end +$var wire 1 mH in [0] $end +$var wire 1 aJ in [1] $end +$var wire 1 CJ in [2] $end +$var wire 1 CK sram [0] $end +$var wire 1 DK sram [1] $end +$var wire 1 K mem_out [1] $end + +$scope module sky130_fd_sc_hd__dfrtp_1_0_ $end +$var wire 1 =K Q $end +$var wire 1 qJ CLK $end +$var wire 1 EK D $end +$var wire 1 NH RESET_B $end +$var supply1 1 :r VPWR $end +$var supply0 1 ;r VGND $end +$var supply1 1 r buf_Q $end +$var wire 1 ?r RESET $end +$upscope $end +$upscope $end + +$scope module sky130_fd_sc_hd__dfrtp_1_1_ $end +$var wire 1 >K Q $end +$var wire 1 qJ CLK $end +$var wire 1 =K D $end +$var wire 1 NH RESET_B $end +$var supply1 1 @r VPWR $end +$var supply0 1 Ar VGND $end +$var supply1 1 Br VPB $end +$var supply0 1 Cr VNB $end + +$scope module base $end +$var wire 1 >K Q $end +$var wire 1 qJ CLK $end +$var wire 1 =K D $end +$var wire 1 NH RESET_B $end +$var wire 1 Dr buf_Q $end +$var wire 1 Er RESET $end +$upscope $end +$upscope $end + +$scope module FTB_77__76 $end +$var wire 1 FK X $end +$var wire 1 >K A $end +$var supply1 1 Fr VPWR $end +$var supply0 1 Gr VGND $end +$var supply1 1 Hr VPB $end +$var supply0 1 Ir VNB $end + +$scope module base $end +$var wire 1 FK X $end +$var wire 1 >K A $end +$var wire 1 Jr buf0_out_X $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mem_top_track_24 $end +$var wire 1 NH pReset [0] $end +$var wire 1 qJ prog_clk [0] $end +$var wire 1 FK ccff_head [0] $end +$var wire 1 GK ccff_tail [0] $end +$var wire 1 ?K mem_out [0] $end +$var wire 1 @K mem_out [1] $end + +$scope module sky130_fd_sc_hd__dfrtp_1_0_ $end +$var wire 1 ?K Q $end +$var wire 1 qJ CLK $end +$var wire 1 FK D $end +$var wire 1 NH RESET_B $end +$var supply1 1 Kr VPWR $end +$var supply0 1 Lr VGND $end +$var supply1 1 Mr VPB $end +$var supply0 1 Nr VNB $end + +$scope module base $end +$var wire 1 ?K Q $end +$var wire 1 qJ CLK $end +$var wire 1 FK D $end +$var wire 1 NH RESET_B $end +$var wire 1 Or buf_Q $end +$var wire 1 Pr RESET $end +$upscope $end +$upscope $end + +$scope module sky130_fd_sc_hd__dfrtp_1_1_ $end +$var wire 1 @K Q $end +$var wire 1 qJ CLK $end +$var wire 1 ?K D $end +$var wire 1 NH RESET_B $end +$var supply1 1 Qr VPWR $end +$var supply0 1 Rr VGND $end +$var supply1 1 Sr VPB $end +$var supply0 1 Tr VNB $end + +$scope module base $end +$var wire 1 @K Q $end +$var wire 1 qJ CLK $end +$var wire 1 ?K D $end +$var wire 1 NH RESET_B $end +$var wire 1 Ur buf_Q $end +$var wire 1 Vr RESET $end +$upscope $end +$upscope $end + +$scope module FTB_78__77 $end +$var wire 1 GK X $end +$var wire 1 @K A $end +$var supply1 1 Wr VPWR $end +$var supply0 1 Xr VGND $end +$var supply1 1 Yr VPB $end +$var supply0 1 Zr VNB $end + +$scope module base $end +$var wire 1 GK X $end +$var wire 1 @K A $end +$var wire 1 [r buf0_out_X $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mem_top_track_26 $end +$var wire 1 NH pReset [0] $end +$var wire 1 qJ prog_clk [0] $end +$var wire 1 GK ccff_head [0] $end +$var wire 1 HK ccff_tail [0] $end +$var wire 1 AK mem_out [0] $end +$var wire 1 BK mem_out [1] $end + +$scope module sky130_fd_sc_hd__dfrtp_1_0_ $end +$var wire 1 AK Q $end +$var wire 1 qJ CLK $end +$var wire 1 GK D $end +$var wire 1 NH RESET_B $end +$var supply1 1 \r VPWR $end +$var supply0 1 ]r VGND $end +$var supply1 1 ^r VPB $end +$var supply0 1 _r VNB $end + +$scope module base $end +$var wire 1 AK Q $end +$var wire 1 qJ CLK $end +$var wire 1 GK D $end +$var wire 1 NH RESET_B $end +$var wire 1 `r buf_Q $end +$var wire 1 ar RESET $end +$upscope $end +$upscope $end + +$scope module sky130_fd_sc_hd__dfrtp_1_1_ $end +$var wire 1 BK Q $end +$var wire 1 qJ CLK $end +$var wire 1 AK D $end +$var wire 1 NH RESET_B $end +$var supply1 1 br VPWR $end +$var supply0 1 cr VGND $end +$var supply1 1 dr VPB $end +$var supply0 1 er VNB $end + +$scope module base $end +$var wire 1 BK Q $end +$var wire 1 qJ CLK $end +$var wire 1 AK D $end +$var wire 1 NH RESET_B $end +$var wire 1 fr buf_Q $end +$var wire 1 gr RESET $end +$upscope $end +$upscope $end + +$scope module FTB_79__78 $end +$var wire 1 HK X $end +$var wire 1 BK A $end +$var supply1 1 hr VPWR $end +$var supply0 1 ir VGND $end +$var supply1 1 jr VPB $end +$var supply0 1 kr VNB $end + +$scope module base $end +$var wire 1 HK X $end +$var wire 1 BK A $end +$var wire 1 lr buf0_out_X $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mem_top_track_36 $end +$var wire 1 NH pReset [0] $end +$var wire 1 qJ prog_clk [0] $end +$var wire 1 4K ccff_head [0] $end +$var wire 1 IK ccff_tail [0] $end +$var wire 1 CK mem_out [0] $end +$var wire 1 DK mem_out [1] $end + +$scope module sky130_fd_sc_hd__dfrtp_1_0_ $end +$var wire 1 CK Q $end +$var wire 1 qJ CLK $end +$var wire 1 4K D $end +$var wire 1 NH RESET_B $end +$var supply1 1 mr VPWR $end +$var supply0 1 nr VGND $end +$var supply1 1 or VPB $end +$var supply0 1 pr VNB $end + +$scope module base $end +$var wire 1 CK Q $end +$var wire 1 qJ CLK $end +$var wire 1 4K D $end +$var wire 1 NH RESET_B $end +$var wire 1 qr buf_Q $end +$var wire 1 rr RESET $end +$upscope $end +$upscope $end + +$scope module sky130_fd_sc_hd__dfrtp_1_1_ $end +$var wire 1 DK Q $end +$var wire 1 qJ CLK $end +$var wire 1 CK D $end +$var wire 1 NH RESET_B $end +$var supply1 1 sr VPWR $end +$var supply0 1 tr VGND $end +$var supply1 1 ur VPB $end +$var supply0 1 vr VNB $end + +$scope module base $end +$var wire 1 DK Q $end +$var wire 1 qJ CLK $end +$var wire 1 CK D $end +$var wire 1 NH RESET_B $end +$var wire 1 wr buf_Q $end +$var wire 1 xr RESET $end +$upscope $end +$upscope $end + +$scope module FTB_80__79 $end +$var wire 1 IK X $end +$var wire 1 DK A $end +$var supply1 1 yr VPWR $end +$var supply0 1 zr VGND $end +$var supply1 1 {r VPB $end +$var supply0 1 |r VNB $end + +$scope module base $end +$var wire 1 IK X $end +$var wire 1 DK A $end +$var wire 1 }r buf0_out_X $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mux_top_track_28 $end +$var wire 1 \J in [0] $end +$var wire 1 >J in [1] $end +$var wire 1 xJ sram [0] $end +$var wire 1 yJ sram [1] $end +$var wire 1 >N sram_inv [0] $end +$var wire 1 ?N sram_inv [1] $end +$var wire 1 tI out [0] $end +$var wire 1 LM p0 $end +$var wire 1 ~r mux_2level_tapbuf_basis_input2_mem1_0_out [0] $end +$var wire 1 !s mux_2level_tapbuf_basis_input2_mem1_1_out [0] $end +$var wire 1 "s SYNOPSYS_UNCONNECTED_1 $end +$var wire 1 #s SYNOPSYS_UNCONNECTED_2 $end +$var wire 1 $s SYNOPSYS_UNCONNECTED_3 $end +$var wire 1 %s BUF_net_182 $end + +$scope module mux_l1_in_0_ $end +$var wire 1 \J in [0] $end +$var wire 1 >J in [1] $end +$var wire 1 xJ mem [0] $end +$var wire 1 "s mem_inv [0] $end +$var wire 1 ~r out [0] $end + +$scope module sky130_fd_sc_hd__mux2_1_0 $end +$var wire 1 ~r X $end +$var wire 1 >J A0 $end +$var wire 1 \J A1 $end +$var wire 1 xJ S $end +$var supply1 1 &s VPWR $end +$var supply0 1 's VGND $end +$var supply1 1 (s VPB $end +$var supply0 1 )s VNB $end + +$scope module base $end +$var wire 1 ~r X $end +$var wire 1 >J A0 $end +$var wire 1 \J A1 $end +$var wire 1 xJ S $end +$var wire 1 *s mux_2to10_out_X $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mux_l2_in_0_ $end +$var wire 1 ~r in [0] $end +$var wire 1 #s in [1] $end +$var wire 1 yJ mem [0] $end +$var wire 1 $s mem_inv [0] $end +$var wire 1 !s out [0] $end +$var wire 1 LM p0 $end + +$scope module sky130_fd_sc_hd__mux2_1_0 $end +$var wire 1 !s X $end +$var wire 1 LM A0 $end +$var wire 1 ~r A1 $end +$var wire 1 yJ S $end +$var supply1 1 +s VPWR $end +$var supply0 1 ,s VGND $end +$var supply1 1 -s VPB $end +$var supply0 1 .s VNB $end + +$scope module base $end +$var wire 1 !s X $end +$var wire 1 LM A0 $end +$var wire 1 ~r A1 $end +$var wire 1 yJ S $end +$var wire 1 /s mux_2to10_out_X $end +$upscope $end +$upscope $end +$upscope $end + +$scope module BINV_R_181 $end +$var wire 1 tI Y $end +$var wire 1 %s A $end +$var supply1 1 0s VPWR $end +$var supply0 1 1s VGND $end +$var supply1 1 2s VPB $end +$var supply0 1 3s VNB $end + +$scope module base $end +$var wire 1 tI Y $end +$var wire 1 %s A $end +$var wire 1 4s not0_out_Y $end +$upscope $end +$upscope $end + +$scope module BINV_R_182 $end +$var wire 1 %s Y $end +$var wire 1 !s A $end +$var supply1 1 5s VPWR $end +$var supply0 1 6s VGND $end +$var supply1 1 7s VPB $end +$var supply0 1 8s VNB $end + +$scope module base $end +$var wire 1 %s Y $end +$var wire 1 !s A $end +$var wire 1 9s not0_out_Y $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mux_top_track_30 $end +$var wire 1 ]J in [0] $end +$var wire 1 ?J in [1] $end +$var wire 1 |J sram [0] $end +$var wire 1 }J sram [1] $end +$var wire 1 @N sram_inv [0] $end +$var wire 1 AN sram_inv [1] $end +$var wire 1 uI out [0] $end +$var wire 1 9M p0 $end +$var wire 1 :s mux_2level_tapbuf_basis_input2_mem1_0_out [0] $end +$var wire 1 ;s mux_2level_tapbuf_basis_input2_mem1_1_out [0] $end +$var wire 1 s SYNOPSYS_UNCONNECTED_3 $end + +$scope module sky130_fd_sc_hd__buf_4_0_ $end +$var wire 1 uI X $end +$var wire 1 ;s A $end +$var supply1 1 ?s VPWR $end +$var supply0 1 @s VGND $end +$var supply1 1 As VPB $end +$var supply0 1 Bs VNB $end + +$scope module base $end +$var wire 1 uI X $end +$var wire 1 ;s A $end +$var wire 1 Cs buf0_out_X $end +$upscope $end +$upscope $end + +$scope module mux_l1_in_0_ $end +$var wire 1 ]J in [0] $end +$var wire 1 ?J in [1] $end +$var wire 1 |J mem [0] $end +$var wire 1 s mem_inv [0] $end +$var wire 1 ;s out [0] $end +$var wire 1 9M p0 $end + +$scope module sky130_fd_sc_hd__mux2_1_0 $end +$var wire 1 ;s X $end +$var wire 1 9M A0 $end +$var wire 1 :s A1 $end +$var wire 1 }J S $end +$var supply1 1 Is VPWR $end +$var supply0 1 Js VGND $end +$var supply1 1 Ks VPB $end +$var supply0 1 Ls VNB $end + +$scope module base $end +$var wire 1 ;s X $end +$var wire 1 9M A0 $end +$var wire 1 :s A1 $end +$var wire 1 }J S $end +$var wire 1 Ms mux_2to10_out_X $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mux_top_track_32 $end +$var wire 1 _J in [0] $end +$var wire 1 AJ in [1] $end +$var wire 1 ~J sram [0] $end +$var wire 1 !K sram [1] $end +$var wire 1 BN sram_inv [0] $end +$var wire 1 CN sram_inv [1] $end +$var wire 1 vI out [0] $end +$var wire 1 LM p0 $end +$var wire 1 Ns mux_2level_tapbuf_basis_input2_mem1_0_out [0] $end +$var wire 1 Os mux_2level_tapbuf_basis_input2_mem1_1_out [0] $end +$var wire 1 Ps SYNOPSYS_UNCONNECTED_1 $end +$var wire 1 Qs SYNOPSYS_UNCONNECTED_2 $end +$var wire 1 Rs SYNOPSYS_UNCONNECTED_3 $end + +$scope module mux_l1_in_0_ $end +$var wire 1 _J in [0] $end +$var wire 1 AJ in [1] $end +$var wire 1 ~J mem [0] $end +$var wire 1 Ps mem_inv [0] $end +$var wire 1 Ns out [0] $end + +$scope module sky130_fd_sc_hd__mux2_1_0 $end +$var wire 1 Ns X $end +$var wire 1 AJ A0 $end +$var wire 1 _J A1 $end +$var wire 1 ~J S $end +$var supply1 1 Ss VPWR $end +$var supply0 1 Ts VGND $end +$var supply1 1 Us VPB $end +$var supply0 1 Vs VNB $end + +$scope module base $end +$var wire 1 Ns X $end +$var wire 1 AJ A0 $end +$var wire 1 _J A1 $end +$var wire 1 ~J S $end +$var wire 1 Ws mux_2to10_out_X $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mux_l2_in_0_ $end +$var wire 1 Ns in [0] $end +$var wire 1 Qs in [1] $end +$var wire 1 !K mem [0] $end +$var wire 1 Rs mem_inv [0] $end +$var wire 1 Os out [0] $end +$var wire 1 LM p0 $end + +$scope module sky130_fd_sc_hd__mux2_1_0 $end +$var wire 1 Os X $end +$var wire 1 LM A0 $end +$var wire 1 Ns A1 $end +$var wire 1 !K S $end +$var supply1 1 Xs VPWR $end +$var supply0 1 Ys VGND $end +$var supply1 1 Zs VPB $end +$var supply0 1 [s VNB $end + +$scope module base $end +$var wire 1 Os X $end +$var wire 1 LM A0 $end +$var wire 1 Ns A1 $end +$var wire 1 !K S $end +$var wire 1 \s mux_2to10_out_X $end +$upscope $end +$upscope $end +$upscope $end + +$scope module BUFT_RR_183 $end +$var wire 1 vI X $end +$var wire 1 Os A $end +$var supply1 1 ]s VPWR $end +$var supply0 1 ^s VGND $end +$var supply1 1 _s VPB $end +$var supply0 1 `s VNB $end + +$scope module base $end +$var wire 1 vI X $end +$var wire 1 Os A $end +$var wire 1 as buf0_out_X $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mux_top_track_34 $end +$var wire 1 `J in [0] $end +$var wire 1 BJ in [1] $end +$var wire 1 "K sram [0] $end +$var wire 1 #K sram [1] $end +$var wire 1 DN sram_inv [0] $end +$var wire 1 EN sram_inv [1] $end +$var wire 1 wI out [0] $end +$var wire 1 LM p0 $end +$var wire 1 bs mux_2level_tapbuf_basis_input2_mem1_0_out [0] $end +$var wire 1 cs mux_2level_tapbuf_basis_input2_mem1_1_out [0] $end +$var wire 1 ds SYNOPSYS_UNCONNECTED_1 $end +$var wire 1 es SYNOPSYS_UNCONNECTED_2 $end +$var wire 1 fs SYNOPSYS_UNCONNECTED_3 $end + +$scope module sky130_fd_sc_hd__buf_4_0_ $end +$var wire 1 wI X $end +$var wire 1 cs A $end +$var supply1 1 gs VPWR $end +$var supply0 1 hs VGND $end +$var supply1 1 is VPB $end +$var supply0 1 js VNB $end + +$scope module base $end +$var wire 1 wI X $end +$var wire 1 cs A $end +$var wire 1 ks buf0_out_X $end +$upscope $end +$upscope $end + +$scope module mux_l1_in_0_ $end +$var wire 1 `J in [0] $end +$var wire 1 BJ in [1] $end +$var wire 1 "K mem [0] $end +$var wire 1 ds mem_inv [0] $end +$var wire 1 bs out [0] $end + +$scope module sky130_fd_sc_hd__mux2_1_0 $end +$var wire 1 bs X $end +$var wire 1 BJ A0 $end +$var wire 1 `J A1 $end +$var wire 1 "K S $end +$var supply1 1 ls VPWR $end +$var supply0 1 ms VGND $end +$var supply1 1 ns VPB $end +$var supply0 1 os VNB $end + +$scope module base $end +$var wire 1 bs X $end +$var wire 1 BJ A0 $end +$var wire 1 `J A1 $end +$var wire 1 "K S $end +$var wire 1 ps mux_2to10_out_X $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mux_l2_in_0_ $end +$var wire 1 bs in [0] $end +$var wire 1 es in [1] $end +$var wire 1 #K mem [0] $end +$var wire 1 fs mem_inv [0] $end +$var wire 1 cs out [0] $end +$var wire 1 LM p0 $end + +$scope module sky130_fd_sc_hd__mux2_1_0 $end +$var wire 1 cs X $end +$var wire 1 LM A0 $end +$var wire 1 bs A1 $end +$var wire 1 #K S $end +$var supply1 1 qs VPWR $end +$var supply0 1 rs VGND $end +$var supply1 1 ss VPB $end +$var supply0 1 ts VNB $end + +$scope module base $end +$var wire 1 cs X $end +$var wire 1 LM A0 $end +$var wire 1 bs A1 $end +$var wire 1 #K S $end +$var wire 1 us mux_2to10_out_X $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mux_top_track_40 $end +$var wire 1 oH in [0] $end +$var wire 1 [I in [1] $end +$var wire 1 $K sram [0] $end +$var wire 1 %K sram [1] $end +$var wire 1 FN sram_inv [0] $end +$var wire 1 GN sram_inv [1] $end +$var wire 1 zI out [0] $end +$var wire 1 BM p0 $end +$var wire 1 vs mux_2level_tapbuf_basis_input2_mem1_0_out [0] $end +$var wire 1 ws mux_2level_tapbuf_basis_input2_mem1_1_out [0] $end +$var wire 1 xs SYNOPSYS_UNCONNECTED_1 $end +$var wire 1 ys SYNOPSYS_UNCONNECTED_2 $end +$var wire 1 zs SYNOPSYS_UNCONNECTED_3 $end +$var wire 1 {s BUF_net_185 $end + +$scope module mux_l1_in_0_ $end +$var wire 1 oH in [0] $end +$var wire 1 [I in [1] $end +$var wire 1 $K mem [0] $end +$var wire 1 xs mem_inv [0] $end +$var wire 1 vs out [0] $end + +$scope module sky130_fd_sc_hd__mux2_1_0 $end +$var wire 1 vs X $end +$var wire 1 [I A0 $end +$var wire 1 oH A1 $end +$var wire 1 $K S $end +$var supply1 1 |s VPWR $end +$var supply0 1 }s VGND $end +$var supply1 1 ~s VPB $end +$var supply0 1 !t VNB $end + +$scope module base $end +$var wire 1 vs X $end +$var wire 1 [I A0 $end +$var wire 1 oH A1 $end +$var wire 1 $K S $end +$var wire 1 "t mux_2to10_out_X $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mux_l2_in_0_ $end +$var wire 1 vs in [0] $end +$var wire 1 ys in [1] $end +$var wire 1 %K mem [0] $end +$var wire 1 zs mem_inv [0] $end +$var wire 1 ws out [0] $end +$var wire 1 BM p0 $end + +$scope module sky130_fd_sc_hd__mux2_1_0 $end +$var wire 1 ws X $end +$var wire 1 BM A0 $end +$var wire 1 vs A1 $end +$var wire 1 %K S $end +$var supply1 1 #t VPWR $end +$var supply0 1 $t VGND $end +$var supply1 1 %t VPB $end +$var supply0 1 &t VNB $end + +$scope module base $end +$var wire 1 ws X $end +$var wire 1 BM A0 $end +$var wire 1 vs A1 $end +$var wire 1 %K S $end +$var wire 1 't mux_2to10_out_X $end +$upscope $end +$upscope $end +$upscope $end + +$scope module BINV_R_184 $end +$var wire 1 zI Y $end +$var wire 1 {s A $end +$var supply1 1 (t VPWR $end +$var supply0 1 )t VGND $end +$var supply1 1 *t VPB $end +$var supply0 1 +t VNB $end + +$scope module base $end +$var wire 1 zI Y $end +$var wire 1 {s A $end +$var wire 1 ,t not0_out_Y $end +$upscope $end +$upscope $end + +$scope module BINV_R_185 $end +$var wire 1 {s Y $end +$var wire 1 ws A $end +$var supply1 1 -t VPWR $end +$var supply0 1 .t VGND $end +$var supply1 1 /t VPB $end +$var supply0 1 0t VNB $end + +$scope module base $end +$var wire 1 {s Y $end +$var wire 1 ws A $end +$var wire 1 1t not0_out_Y $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mux_top_track_42 $end +$var wire 1 pH in [0] $end +$var wire 1 WI in [1] $end +$var wire 1 &K sram [0] $end +$var wire 1 'K sram [1] $end +$var wire 1 HN sram_inv [0] $end +$var wire 1 IN sram_inv [1] $end +$var wire 1 {I out [0] $end +$var wire 1 BM p0 $end +$var wire 1 2t mux_2level_tapbuf_basis_input2_mem1_0_out [0] $end +$var wire 1 3t mux_2level_tapbuf_basis_input2_mem1_1_out [0] $end +$var wire 1 4t SYNOPSYS_UNCONNECTED_1 $end +$var wire 1 5t SYNOPSYS_UNCONNECTED_2 $end +$var wire 1 6t SYNOPSYS_UNCONNECTED_3 $end + +$scope module sky130_fd_sc_hd__buf_4_0_ $end +$var wire 1 {I X $end +$var wire 1 3t A $end +$var supply1 1 7t VPWR $end +$var supply0 1 8t VGND $end +$var supply1 1 9t VPB $end +$var supply0 1 :t VNB $end + +$scope module base $end +$var wire 1 {I X $end +$var wire 1 3t A $end +$var wire 1 ;t buf0_out_X $end +$upscope $end +$upscope $end + +$scope module mux_l1_in_0_ $end +$var wire 1 pH in [0] $end +$var wire 1 WI in [1] $end +$var wire 1 &K mem [0] $end +$var wire 1 4t mem_inv [0] $end +$var wire 1 2t out [0] $end + +$scope module sky130_fd_sc_hd__mux2_1_0 $end +$var wire 1 2t X $end +$var wire 1 WI A0 $end +$var wire 1 pH A1 $end +$var wire 1 &K S $end +$var supply1 1 t VPB $end +$var supply0 1 ?t VNB $end + +$scope module base $end +$var wire 1 2t X $end +$var wire 1 WI A0 $end +$var wire 1 pH A1 $end +$var wire 1 &K S $end +$var wire 1 @t mux_2to10_out_X $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mux_l2_in_0_ $end +$var wire 1 2t in [0] $end +$var wire 1 5t in [1] $end +$var wire 1 'K mem [0] $end +$var wire 1 6t mem_inv [0] $end +$var wire 1 3t out [0] $end +$var wire 1 BM p0 $end + +$scope module sky130_fd_sc_hd__mux2_1_0 $end +$var wire 1 3t X $end +$var wire 1 BM A0 $end +$var wire 1 2t A1 $end +$var wire 1 'K S $end +$var supply1 1 At VPWR $end +$var supply0 1 Bt VGND $end +$var supply1 1 Ct VPB $end +$var supply0 1 Dt VNB $end + +$scope module base $end +$var wire 1 3t X $end +$var wire 1 BM A0 $end +$var wire 1 2t A1 $end +$var wire 1 'K S $end +$var wire 1 Et mux_2to10_out_X $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mux_top_track_44 $end +$var wire 1 qH in [0] $end +$var wire 1 SI in [1] $end +$var wire 1 (K sram [0] $end +$var wire 1 )K sram [1] $end +$var wire 1 JN sram_inv [0] $end +$var wire 1 KN sram_inv [1] $end +$var wire 1 |I out [0] $end +$var wire 1 BM p0 $end +$var wire 1 Ft mux_2level_tapbuf_basis_input2_mem1_0_out [0] $end +$var wire 1 Gt mux_2level_tapbuf_basis_input2_mem1_1_out [0] $end +$var wire 1 Ht SYNOPSYS_UNCONNECTED_1 $end +$var wire 1 It SYNOPSYS_UNCONNECTED_2 $end +$var wire 1 Jt SYNOPSYS_UNCONNECTED_3 $end +$var wire 1 Kt BUF_net_187 $end + +$scope module mux_l1_in_0_ $end +$var wire 1 qH in [0] $end +$var wire 1 SI in [1] $end +$var wire 1 (K mem [0] $end +$var wire 1 Ht mem_inv [0] $end +$var wire 1 Ft out [0] $end + +$scope module sky130_fd_sc_hd__mux2_1_0 $end +$var wire 1 Ft X $end +$var wire 1 SI A0 $end +$var wire 1 qH A1 $end +$var wire 1 (K S $end +$var supply1 1 Lt VPWR $end +$var supply0 1 Mt VGND $end +$var supply1 1 Nt VPB $end +$var supply0 1 Ot VNB $end + +$scope module base $end +$var wire 1 Ft X $end +$var wire 1 SI A0 $end +$var wire 1 qH A1 $end +$var wire 1 (K S $end +$var wire 1 Pt mux_2to10_out_X $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mux_l2_in_0_ $end +$var wire 1 Ft in [0] $end +$var wire 1 It in [1] $end +$var wire 1 )K mem [0] $end +$var wire 1 Jt mem_inv [0] $end +$var wire 1 Gt out [0] $end +$var wire 1 BM p0 $end + +$scope module sky130_fd_sc_hd__mux2_1_0 $end +$var wire 1 Gt X $end +$var wire 1 BM A0 $end +$var wire 1 Ft A1 $end +$var wire 1 )K S $end +$var supply1 1 Qt VPWR $end +$var supply0 1 Rt VGND $end +$var supply1 1 St VPB $end +$var supply0 1 Tt VNB $end + +$scope module base $end +$var wire 1 Gt X $end +$var wire 1 BM A0 $end +$var wire 1 Ft A1 $end +$var wire 1 )K S $end +$var wire 1 Ut mux_2to10_out_X $end +$upscope $end +$upscope $end +$upscope $end + +$scope module BINV_R_186 $end +$var wire 1 |I Y $end +$var wire 1 Kt A $end +$var supply1 1 Vt VPWR $end +$var supply0 1 Wt VGND $end +$var supply1 1 Xt VPB $end +$var supply0 1 Yt VNB $end + +$scope module base $end +$var wire 1 |I Y $end +$var wire 1 Kt A $end +$var wire 1 Zt not0_out_Y $end +$upscope $end +$upscope $end + +$scope module BINV_R_187 $end +$var wire 1 Kt Y $end +$var wire 1 Gt A $end +$var supply1 1 [t VPWR $end +$var supply0 1 \t VGND $end +$var supply1 1 ]t VPB $end +$var supply0 1 ^t VNB $end + +$scope module base $end +$var wire 1 Kt Y $end +$var wire 1 Gt A $end +$var wire 1 _t not0_out_Y $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mux_top_track_46 $end +$var wire 1 rH in [0] $end +$var wire 1 OI in [1] $end +$var wire 1 *K sram [0] $end +$var wire 1 +K sram [1] $end +$var wire 1 LN sram_inv [0] $end +$var wire 1 MN sram_inv [1] $end +$var wire 1 }I out [0] $end +$var wire 1 BM p0 $end +$var wire 1 `t mux_2level_tapbuf_basis_input2_mem1_0_out [0] $end +$var wire 1 at mux_2level_tapbuf_basis_input2_mem1_1_out [0] $end +$var wire 1 bt SYNOPSYS_UNCONNECTED_1 $end +$var wire 1 ct SYNOPSYS_UNCONNECTED_2 $end +$var wire 1 dt SYNOPSYS_UNCONNECTED_3 $end +$var wire 1 et BUF_net_189 $end + +$scope module mux_l1_in_0_ $end +$var wire 1 rH in [0] $end +$var wire 1 OI in [1] $end +$var wire 1 *K mem [0] $end +$var wire 1 bt mem_inv [0] $end +$var wire 1 `t out [0] $end + +$scope module sky130_fd_sc_hd__mux2_1_0 $end +$var wire 1 `t X $end +$var wire 1 OI A0 $end +$var wire 1 rH A1 $end +$var wire 1 *K S $end +$var supply1 1 ft VPWR $end +$var supply0 1 gt VGND $end +$var supply1 1 ht VPB $end +$var supply0 1 it VNB $end + +$scope module base $end +$var wire 1 `t X $end +$var wire 1 OI A0 $end +$var wire 1 rH A1 $end +$var wire 1 *K S $end +$var wire 1 jt mux_2to10_out_X $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mux_l2_in_0_ $end +$var wire 1 `t in [0] $end +$var wire 1 ct in [1] $end +$var wire 1 +K mem [0] $end +$var wire 1 dt mem_inv [0] $end +$var wire 1 at out [0] $end +$var wire 1 BM p0 $end + +$scope module sky130_fd_sc_hd__mux2_1_0 $end +$var wire 1 at X $end +$var wire 1 BM A0 $end +$var wire 1 `t A1 $end +$var wire 1 +K S $end +$var supply1 1 kt VPWR $end +$var supply0 1 lt VGND $end +$var supply1 1 mt VPB $end +$var supply0 1 nt VNB $end + +$scope module base $end +$var wire 1 at X $end +$var wire 1 BM A0 $end +$var wire 1 `t A1 $end +$var wire 1 +K S $end +$var wire 1 ot mux_2to10_out_X $end +$upscope $end +$upscope $end +$upscope $end + +$scope module BINV_R_188 $end +$var wire 1 }I Y $end +$var wire 1 et A $end +$var supply1 1 pt VPWR $end +$var supply0 1 qt VGND $end +$var supply1 1 rt VPB $end +$var supply0 1 st VNB $end + +$scope module base $end +$var wire 1 }I Y $end +$var wire 1 et A $end +$var wire 1 tt not0_out_Y $end +$upscope $end +$upscope $end + +$scope module BINV_R_189 $end +$var wire 1 et Y $end +$var wire 1 at A $end +$var supply1 1 ut VPWR $end +$var supply0 1 vt VGND $end +$var supply1 1 wt VPB $end +$var supply0 1 xt VNB $end + +$scope module base $end +$var wire 1 et Y $end +$var wire 1 at A $end +$var wire 1 yt not0_out_Y $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mux_top_track_48 $end +$var wire 1 sH in [0] $end +$var wire 1 KI in [1] $end +$var wire 1 ,K sram [0] $end +$var wire 1 -K sram [1] $end +$var wire 1 NN sram_inv [0] $end +$var wire 1 ON sram_inv [1] $end +$var wire 1 ~I out [0] $end +$var wire 1 LM p0 $end +$var wire 1 zt mux_2level_tapbuf_basis_input2_mem1_0_out [0] $end +$var wire 1 {t mux_2level_tapbuf_basis_input2_mem1_1_out [0] $end +$var wire 1 |t SYNOPSYS_UNCONNECTED_1 $end +$var wire 1 }t SYNOPSYS_UNCONNECTED_2 $end +$var wire 1 ~t SYNOPSYS_UNCONNECTED_3 $end +$var wire 1 !u BUF_net_191 $end + +$scope module mux_l1_in_0_ $end +$var wire 1 sH in [0] $end +$var wire 1 KI in [1] $end +$var wire 1 ,K mem [0] $end +$var wire 1 |t mem_inv [0] $end +$var wire 1 zt out [0] $end + +$scope module sky130_fd_sc_hd__mux2_1_0 $end +$var wire 1 zt X $end +$var wire 1 KI A0 $end +$var wire 1 sH A1 $end +$var wire 1 ,K S $end +$var supply1 1 "u VPWR $end +$var supply0 1 #u VGND $end +$var supply1 1 $u VPB $end +$var supply0 1 %u VNB $end + +$scope module base $end +$var wire 1 zt X $end +$var wire 1 KI A0 $end +$var wire 1 sH A1 $end +$var wire 1 ,K S $end +$var wire 1 &u mux_2to10_out_X $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mux_l2_in_0_ $end +$var wire 1 zt in [0] $end +$var wire 1 }t in [1] $end +$var wire 1 -K mem [0] $end +$var wire 1 ~t mem_inv [0] $end +$var wire 1 {t out [0] $end +$var wire 1 LM p0 $end + +$scope module sky130_fd_sc_hd__mux2_1_0 $end +$var wire 1 {t X $end +$var wire 1 LM A0 $end +$var wire 1 zt A1 $end +$var wire 1 -K S $end +$var supply1 1 'u VPWR $end +$var supply0 1 (u VGND $end +$var supply1 1 )u VPB $end +$var supply0 1 *u VNB $end + +$scope module base $end +$var wire 1 {t X $end +$var wire 1 LM A0 $end +$var wire 1 zt A1 $end +$var wire 1 -K S $end +$var wire 1 +u mux_2to10_out_X $end +$upscope $end +$upscope $end +$upscope $end + +$scope module BINV_R_190 $end +$var wire 1 ~I Y $end +$var wire 1 !u A $end +$var supply1 1 ,u VPWR $end +$var supply0 1 -u VGND $end +$var supply1 1 .u VPB $end +$var supply0 1 /u VNB $end + +$scope module base $end +$var wire 1 ~I Y $end +$var wire 1 !u A $end +$var wire 1 0u not0_out_Y $end +$upscope $end +$upscope $end + +$scope module BINV_R_191 $end +$var wire 1 !u Y $end +$var wire 1 {t A $end +$var supply1 1 1u VPWR $end +$var supply0 1 2u VGND $end +$var supply1 1 3u VPB $end +$var supply0 1 4u VNB $end + +$scope module base $end +$var wire 1 !u Y $end +$var wire 1 {t A $end +$var wire 1 5u not0_out_Y $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mux_top_track_50 $end +$var wire 1 tH in [0] $end +$var wire 1 GI in [1] $end +$var wire 1 .K sram [0] $end +$var wire 1 /K sram [1] $end +$var wire 1 PN sram_inv [0] $end +$var wire 1 QN sram_inv [1] $end +$var wire 1 !J out [0] $end +$var wire 1 LM p0 $end +$var wire 1 6u mux_2level_tapbuf_basis_input2_mem1_0_out [0] $end +$var wire 1 7u mux_2level_tapbuf_basis_input2_mem1_1_out [0] $end +$var wire 1 8u SYNOPSYS_UNCONNECTED_1 $end +$var wire 1 9u SYNOPSYS_UNCONNECTED_2 $end +$var wire 1 :u SYNOPSYS_UNCONNECTED_3 $end + +$scope module mux_l1_in_0_ $end +$var wire 1 tH in [0] $end +$var wire 1 GI in [1] $end +$var wire 1 .K mem [0] $end +$var wire 1 8u mem_inv [0] $end +$var wire 1 6u out [0] $end + +$scope module sky130_fd_sc_hd__mux2_1_0 $end +$var wire 1 6u X $end +$var wire 1 GI A0 $end +$var wire 1 tH A1 $end +$var wire 1 .K S $end +$var supply1 1 ;u VPWR $end +$var supply0 1 u VNB $end + +$scope module base $end +$var wire 1 6u X $end +$var wire 1 GI A0 $end +$var wire 1 tH A1 $end +$var wire 1 .K S $end +$var wire 1 ?u mux_2to10_out_X $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mux_l2_in_0_ $end +$var wire 1 6u in [0] $end +$var wire 1 9u in [1] $end +$var wire 1 /K mem [0] $end +$var wire 1 :u mem_inv [0] $end +$var wire 1 7u out [0] $end +$var wire 1 LM p0 $end + +$scope module sky130_fd_sc_hd__mux2_1_0 $end +$var wire 1 7u X $end +$var wire 1 LM A0 $end +$var wire 1 6u A1 $end +$var wire 1 /K S $end +$var supply1 1 @u VPWR $end +$var supply0 1 Au VGND $end +$var supply1 1 Bu VPB $end +$var supply0 1 Cu VNB $end + +$scope module base $end +$var wire 1 7u X $end +$var wire 1 LM A0 $end +$var wire 1 6u A1 $end +$var wire 1 /K S $end +$var wire 1 Du mux_2to10_out_X $end +$upscope $end +$upscope $end +$upscope $end + +$scope module BUFT_RR_192 $end +$var wire 1 !J X $end +$var wire 1 7u A $end +$var supply1 1 Eu VPWR $end +$var supply0 1 Fu VGND $end +$var supply1 1 Gu VPB $end +$var supply0 1 Hu VNB $end + +$scope module base $end +$var wire 1 !J X $end +$var wire 1 7u A $end +$var wire 1 Iu buf0_out_X $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mux_top_track_58 $end +$var wire 1 uH in [0] $end +$var wire 1 ?I in [1] $end +$var wire 1 zJ sram [0] $end +$var wire 1 {J sram [1] $end +$var wire 1 RN sram_inv [0] $end +$var wire 1 SN sram_inv [1] $end +$var wire 1 %J out [0] $end +$var wire 1 LM p0 $end +$var wire 1 Ju mux_2level_tapbuf_basis_input2_mem1_0_out [0] $end +$var wire 1 Ku mux_2level_tapbuf_basis_input2_mem1_1_out [0] $end +$var wire 1 Lu SYNOPSYS_UNCONNECTED_1 $end +$var wire 1 Mu SYNOPSYS_UNCONNECTED_2 $end +$var wire 1 Nu SYNOPSYS_UNCONNECTED_3 $end + +$scope module sky130_fd_sc_hd__buf_4_0_ $end +$var wire 1 %J X $end +$var wire 1 Ku A $end +$var supply1 1 Ou VPWR $end +$var supply0 1 Pu VGND $end +$var supply1 1 Qu VPB $end +$var supply0 1 Ru VNB $end + +$scope module base $end +$var wire 1 %J X $end +$var wire 1 Ku A $end +$var wire 1 Su buf0_out_X $end +$upscope $end +$upscope $end + +$scope module mux_l1_in_0_ $end +$var wire 1 uH in [0] $end +$var wire 1 ?I in [1] $end +$var wire 1 zJ mem [0] $end +$var wire 1 Lu mem_inv [0] $end +$var wire 1 Ju out [0] $end + +$scope module sky130_fd_sc_hd__mux2_1_0 $end +$var wire 1 Ju X $end +$var wire 1 ?I A0 $end +$var wire 1 uH A1 $end +$var wire 1 zJ S $end +$var supply1 1 Tu VPWR $end +$var supply0 1 Uu VGND $end +$var supply1 1 Vu VPB $end +$var supply0 1 Wu VNB $end + +$scope module base $end +$var wire 1 Ju X $end +$var wire 1 ?I A0 $end +$var wire 1 uH A1 $end +$var wire 1 zJ S $end +$var wire 1 Xu mux_2to10_out_X $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mux_l2_in_0_ $end +$var wire 1 Ju in [0] $end +$var wire 1 Mu in [1] $end +$var wire 1 {J mem [0] $end +$var wire 1 Nu mem_inv [0] $end +$var wire 1 Ku out [0] $end +$var wire 1 LM p0 $end + +$scope module sky130_fd_sc_hd__mux2_1_0 $end +$var wire 1 Ku X $end +$var wire 1 LM A0 $end +$var wire 1 Ju A1 $end +$var wire 1 {J S $end +$var supply1 1 Yu VPWR $end +$var supply0 1 Zu VGND $end +$var supply1 1 [u VPB $end +$var supply0 1 \u VNB $end + +$scope module base $end +$var wire 1 Ku X $end +$var wire 1 LM A0 $end +$var wire 1 Ju A1 $end +$var wire 1 {J S $end +$var wire 1 ]u mux_2to10_out_X $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mem_top_track_28 $end +$var wire 1 NH pReset [0] $end +$var wire 1 qJ prog_clk [0] $end +$var wire 1 HK ccff_head [0] $end +$var wire 1 0K ccff_tail [0] $end +$var wire 1 xJ mem_out [0] $end +$var wire 1 yJ mem_out [1] $end + +$scope module sky130_fd_sc_hd__dfrtp_1_0_ $end +$var wire 1 xJ Q $end +$var wire 1 qJ CLK $end +$var wire 1 HK D $end +$var wire 1 NH RESET_B $end +$var supply1 1 ^u VPWR $end +$var supply0 1 _u VGND $end +$var supply1 1 `u VPB $end +$var supply0 1 au VNB $end + +$scope module base $end +$var wire 1 xJ Q $end +$var wire 1 qJ CLK $end +$var wire 1 HK D $end +$var wire 1 NH RESET_B $end +$var wire 1 bu buf_Q $end +$var wire 1 cu RESET $end +$upscope $end +$upscope $end + +$scope module sky130_fd_sc_hd__dfrtp_1_1_ $end +$var wire 1 yJ Q $end +$var wire 1 qJ CLK $end +$var wire 1 xJ D $end +$var wire 1 NH RESET_B $end +$var supply1 1 du VPWR $end +$var supply0 1 eu VGND $end +$var supply1 1 fu VPB $end +$var supply0 1 gu VNB $end + +$scope module base $end +$var wire 1 yJ Q $end +$var wire 1 qJ CLK $end +$var wire 1 xJ D $end +$var wire 1 NH RESET_B $end +$var wire 1 hu buf_Q $end +$var wire 1 iu RESET $end +$upscope $end +$upscope $end + +$scope module FTB_81__80 $end +$var wire 1 0K X $end +$var wire 1 yJ A $end +$var supply1 1 ju VPWR $end +$var supply0 1 ku VGND $end +$var supply1 1 lu VPB $end +$var supply0 1 mu VNB $end + +$scope module base $end +$var wire 1 0K X $end +$var wire 1 yJ A $end +$var wire 1 nu buf0_out_X $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mem_top_track_30 $end +$var wire 1 NH pReset [0] $end +$var wire 1 qJ prog_clk [0] $end +$var wire 1 0K ccff_head [0] $end +$var wire 1 2K ccff_tail [0] $end +$var wire 1 |J mem_out [0] $end +$var wire 1 }J mem_out [1] $end + +$scope module sky130_fd_sc_hd__dfrtp_1_0_ $end +$var wire 1 |J Q $end +$var wire 1 qJ CLK $end +$var wire 1 0K D $end +$var wire 1 NH RESET_B $end +$var supply1 1 ou VPWR $end +$var supply0 1 pu VGND $end +$var supply1 1 qu VPB $end +$var supply0 1 ru VNB $end + +$scope module base $end +$var wire 1 |J Q $end +$var wire 1 qJ CLK $end +$var wire 1 0K D $end +$var wire 1 NH RESET_B $end +$var wire 1 su buf_Q $end +$var wire 1 tu RESET $end +$upscope $end +$upscope $end + +$scope module sky130_fd_sc_hd__dfrtp_1_1_ $end +$var wire 1 }J Q $end +$var wire 1 qJ CLK $end +$var wire 1 |J D $end +$var wire 1 NH RESET_B $end +$var supply1 1 uu VPWR $end +$var supply0 1 vu VGND $end +$var supply1 1 wu VPB $end +$var supply0 1 xu VNB $end + +$scope module base $end +$var wire 1 }J Q $end +$var wire 1 qJ CLK $end +$var wire 1 |J D $end +$var wire 1 NH RESET_B $end +$var wire 1 yu buf_Q $end +$var wire 1 zu RESET $end +$upscope $end +$upscope $end + +$scope module FTB_82__81 $end +$var wire 1 2K X $end +$var wire 1 }J A $end +$var supply1 1 {u VPWR $end +$var supply0 1 |u VGND $end +$var supply1 1 }u VPB $end +$var supply0 1 ~u VNB $end + +$scope module base $end +$var wire 1 2K X $end +$var wire 1 }J A $end +$var wire 1 !v buf0_out_X $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mem_top_track_32 $end +$var wire 1 NH pReset [0] $end +$var wire 1 qJ prog_clk [0] $end +$var wire 1 2K ccff_head [0] $end +$var wire 1 3K ccff_tail [0] $end +$var wire 1 ~J mem_out [0] $end +$var wire 1 !K mem_out [1] $end + +$scope module sky130_fd_sc_hd__dfrtp_1_0_ $end +$var wire 1 ~J Q $end +$var wire 1 qJ CLK $end +$var wire 1 2K D $end +$var wire 1 NH RESET_B $end +$var supply1 1 "v VPWR $end +$var supply0 1 #v VGND $end +$var supply1 1 $v VPB $end +$var supply0 1 %v VNB $end + +$scope module base $end +$var wire 1 ~J Q $end +$var wire 1 qJ CLK $end +$var wire 1 2K D $end +$var wire 1 NH RESET_B $end +$var wire 1 &v buf_Q $end +$var wire 1 'v RESET $end +$upscope $end +$upscope $end + +$scope module sky130_fd_sc_hd__dfrtp_1_1_ $end +$var wire 1 !K Q $end +$var wire 1 qJ CLK $end +$var wire 1 ~J D $end +$var wire 1 NH RESET_B $end +$var supply1 1 (v VPWR $end +$var supply0 1 )v VGND $end +$var supply1 1 *v VPB $end +$var supply0 1 +v VNB $end + +$scope module base $end +$var wire 1 !K Q $end +$var wire 1 qJ CLK $end +$var wire 1 ~J D $end +$var wire 1 NH RESET_B $end +$var wire 1 ,v buf_Q $end +$var wire 1 -v RESET $end +$upscope $end +$upscope $end + +$scope module FTB_83__82 $end +$var wire 1 3K X $end +$var wire 1 !K A $end +$var supply1 1 .v VPWR $end +$var supply0 1 /v VGND $end +$var supply1 1 0v VPB $end +$var supply0 1 1v VNB $end + +$scope module base $end +$var wire 1 3K X $end +$var wire 1 !K A $end +$var wire 1 2v buf0_out_X $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mem_top_track_34 $end +$var wire 1 NH pReset [0] $end +$var wire 1 qJ prog_clk [0] $end +$var wire 1 3K ccff_head [0] $end +$var wire 1 4K ccff_tail [0] $end +$var wire 1 "K mem_out [0] $end +$var wire 1 #K mem_out [1] $end + +$scope module sky130_fd_sc_hd__dfrtp_1_0_ $end +$var wire 1 "K Q $end +$var wire 1 qJ CLK $end +$var wire 1 3K D $end +$var wire 1 NH RESET_B $end +$var supply1 1 3v VPWR $end +$var supply0 1 4v VGND $end +$var supply1 1 5v VPB $end +$var supply0 1 6v VNB $end + +$scope module base $end +$var wire 1 "K Q $end +$var wire 1 qJ CLK $end +$var wire 1 3K D $end +$var wire 1 NH RESET_B $end +$var wire 1 7v buf_Q $end +$var wire 1 8v RESET $end +$upscope $end +$upscope $end + +$scope module sky130_fd_sc_hd__dfrtp_1_1_ $end +$var wire 1 #K Q $end +$var wire 1 qJ CLK $end +$var wire 1 "K D $end +$var wire 1 NH RESET_B $end +$var supply1 1 9v VPWR $end +$var supply0 1 :v VGND $end +$var supply1 1 ;v VPB $end +$var supply0 1 v RESET $end +$upscope $end +$upscope $end + +$scope module FTB_84__83 $end +$var wire 1 4K X $end +$var wire 1 #K A $end +$var supply1 1 ?v VPWR $end +$var supply0 1 @v VGND $end +$var supply1 1 Av VPB $end +$var supply0 1 Bv VNB $end + +$scope module base $end +$var wire 1 4K X $end +$var wire 1 #K A $end +$var wire 1 Cv buf0_out_X $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mem_top_track_40 $end +$var wire 1 NH pReset [0] $end +$var wire 1 qJ prog_clk [0] $end +$var wire 1 IK ccff_head [0] $end +$var wire 1 5K ccff_tail [0] $end +$var wire 1 $K mem_out [0] $end +$var wire 1 %K mem_out [1] $end + +$scope module sky130_fd_sc_hd__dfrtp_1_0_ $end +$var wire 1 $K Q $end +$var wire 1 qJ CLK $end +$var wire 1 IK D $end +$var wire 1 NH RESET_B $end +$var supply1 1 Dv VPWR $end +$var supply0 1 Ev VGND $end +$var supply1 1 Fv VPB $end +$var supply0 1 Gv VNB $end + +$scope module base $end +$var wire 1 $K Q $end +$var wire 1 qJ CLK $end +$var wire 1 IK D $end +$var wire 1 NH RESET_B $end +$var wire 1 Hv buf_Q $end +$var wire 1 Iv RESET $end +$upscope $end +$upscope $end + +$scope module sky130_fd_sc_hd__dfrtp_1_1_ $end +$var wire 1 %K Q $end +$var wire 1 qJ CLK $end +$var wire 1 $K D $end +$var wire 1 NH RESET_B $end +$var supply1 1 Jv VPWR $end +$var supply0 1 Kv VGND $end +$var supply1 1 Lv VPB $end +$var supply0 1 Mv VNB $end + +$scope module base $end +$var wire 1 %K Q $end +$var wire 1 qJ CLK $end +$var wire 1 $K D $end +$var wire 1 NH RESET_B $end +$var wire 1 Nv buf_Q $end +$var wire 1 Ov RESET $end +$upscope $end +$upscope $end + +$scope module FTB_85__84 $end +$var wire 1 5K X $end +$var wire 1 %K A $end +$var supply1 1 Pv VPWR $end +$var supply0 1 Qv VGND $end +$var supply1 1 Rv VPB $end +$var supply0 1 Sv VNB $end + +$scope module base $end +$var wire 1 5K X $end +$var wire 1 %K A $end +$var wire 1 Tv buf0_out_X $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mem_top_track_42 $end +$var wire 1 NH pReset [0] $end +$var wire 1 qJ prog_clk [0] $end +$var wire 1 5K ccff_head [0] $end +$var wire 1 6K ccff_tail [0] $end +$var wire 1 &K mem_out [0] $end +$var wire 1 'K mem_out [1] $end + +$scope module sky130_fd_sc_hd__dfrtp_1_0_ $end +$var wire 1 &K Q $end +$var wire 1 qJ CLK $end +$var wire 1 5K D $end +$var wire 1 NH RESET_B $end +$var supply1 1 Uv VPWR $end +$var supply0 1 Vv VGND $end +$var supply1 1 Wv VPB $end +$var supply0 1 Xv VNB $end + +$scope module base $end +$var wire 1 &K Q $end +$var wire 1 qJ CLK $end +$var wire 1 5K D $end +$var wire 1 NH RESET_B $end +$var wire 1 Yv buf_Q $end +$var wire 1 Zv RESET $end +$upscope $end +$upscope $end + +$scope module sky130_fd_sc_hd__dfrtp_1_1_ $end +$var wire 1 'K Q $end +$var wire 1 qJ CLK $end +$var wire 1 &K D $end +$var wire 1 NH RESET_B $end +$var supply1 1 [v VPWR $end +$var supply0 1 \v VGND $end +$var supply1 1 ]v VPB $end +$var supply0 1 ^v VNB $end + +$scope module base $end +$var wire 1 'K Q $end +$var wire 1 qJ CLK $end +$var wire 1 &K D $end +$var wire 1 NH RESET_B $end +$var wire 1 _v buf_Q $end +$var wire 1 `v RESET $end +$upscope $end +$upscope $end + +$scope module FTB_86__85 $end +$var wire 1 6K X $end +$var wire 1 'K A $end +$var supply1 1 av VPWR $end +$var supply0 1 bv VGND $end +$var supply1 1 cv VPB $end +$var supply0 1 dv VNB $end + +$scope module base $end +$var wire 1 6K X $end +$var wire 1 'K A $end +$var wire 1 ev buf0_out_X $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mem_top_track_44 $end +$var wire 1 NH pReset [0] $end +$var wire 1 qJ prog_clk [0] $end +$var wire 1 6K ccff_head [0] $end +$var wire 1 7K ccff_tail [0] $end +$var wire 1 (K mem_out [0] $end +$var wire 1 )K mem_out [1] $end + +$scope module sky130_fd_sc_hd__dfrtp_1_0_ $end +$var wire 1 (K Q $end +$var wire 1 qJ CLK $end +$var wire 1 6K D $end +$var wire 1 NH RESET_B $end +$var supply1 1 fv VPWR $end +$var supply0 1 gv VGND $end +$var supply1 1 hv VPB $end +$var supply0 1 iv VNB $end + +$scope module base $end +$var wire 1 (K Q $end +$var wire 1 qJ CLK $end +$var wire 1 6K D $end +$var wire 1 NH RESET_B $end +$var wire 1 jv buf_Q $end +$var wire 1 kv RESET $end +$upscope $end +$upscope $end + +$scope module sky130_fd_sc_hd__dfrtp_1_1_ $end +$var wire 1 )K Q $end +$var wire 1 qJ CLK $end +$var wire 1 (K D $end +$var wire 1 NH RESET_B $end +$var supply1 1 lv VPWR $end +$var supply0 1 mv VGND $end +$var supply1 1 nv VPB $end +$var supply0 1 ov VNB $end + +$scope module base $end +$var wire 1 )K Q $end +$var wire 1 qJ CLK $end +$var wire 1 (K D $end +$var wire 1 NH RESET_B $end +$var wire 1 pv buf_Q $end +$var wire 1 qv RESET $end +$upscope $end +$upscope $end + +$scope module FTB_87__86 $end +$var wire 1 7K X $end +$var wire 1 )K A $end +$var supply1 1 rv VPWR $end +$var supply0 1 sv VGND $end +$var supply1 1 tv VPB $end +$var supply0 1 uv VNB $end + +$scope module base $end +$var wire 1 7K X $end +$var wire 1 )K A $end +$var wire 1 vv buf0_out_X $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mem_top_track_46 $end +$var wire 1 NH pReset [0] $end +$var wire 1 qJ prog_clk [0] $end +$var wire 1 7K ccff_head [0] $end +$var wire 1 8K ccff_tail [0] $end +$var wire 1 *K mem_out [0] $end +$var wire 1 +K mem_out [1] $end + +$scope module sky130_fd_sc_hd__dfrtp_1_0_ $end +$var wire 1 *K Q $end +$var wire 1 qJ CLK $end +$var wire 1 7K D $end +$var wire 1 NH RESET_B $end +$var supply1 1 wv VPWR $end +$var supply0 1 xv VGND $end +$var supply1 1 yv VPB $end +$var supply0 1 zv VNB $end + +$scope module base $end +$var wire 1 *K Q $end +$var wire 1 qJ CLK $end +$var wire 1 7K D $end +$var wire 1 NH RESET_B $end +$var wire 1 {v buf_Q $end +$var wire 1 |v RESET $end +$upscope $end +$upscope $end + +$scope module sky130_fd_sc_hd__dfrtp_1_1_ $end +$var wire 1 +K Q $end +$var wire 1 qJ CLK $end +$var wire 1 *K D $end +$var wire 1 NH RESET_B $end +$var supply1 1 }v VPWR $end +$var supply0 1 ~v VGND $end +$var supply1 1 !w VPB $end +$var supply0 1 "w VNB $end + +$scope module base $end +$var wire 1 +K Q $end +$var wire 1 qJ CLK $end +$var wire 1 *K D $end +$var wire 1 NH RESET_B $end +$var wire 1 #w buf_Q $end +$var wire 1 $w RESET $end +$upscope $end +$upscope $end + +$scope module FTB_88__87 $end +$var wire 1 8K X $end +$var wire 1 +K A $end +$var supply1 1 %w VPWR $end +$var supply0 1 &w VGND $end +$var supply1 1 'w VPB $end +$var supply0 1 (w VNB $end + +$scope module base $end +$var wire 1 8K X $end +$var wire 1 +K A $end +$var wire 1 )w buf0_out_X $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mem_top_track_48 $end +$var wire 1 NH pReset [0] $end +$var wire 1 qJ prog_clk [0] $end +$var wire 1 8K ccff_head [0] $end +$var wire 1 9K ccff_tail [0] $end +$var wire 1 ,K mem_out [0] $end +$var wire 1 -K mem_out [1] $end + +$scope module sky130_fd_sc_hd__dfrtp_1_0_ $end +$var wire 1 ,K Q $end +$var wire 1 qJ CLK $end +$var wire 1 8K D $end +$var wire 1 NH RESET_B $end +$var supply1 1 *w VPWR $end +$var supply0 1 +w VGND $end +$var supply1 1 ,w VPB $end +$var supply0 1 -w VNB $end + +$scope module base $end +$var wire 1 ,K Q $end +$var wire 1 qJ CLK $end +$var wire 1 8K D $end +$var wire 1 NH RESET_B $end +$var wire 1 .w buf_Q $end +$var wire 1 /w RESET $end +$upscope $end +$upscope $end + +$scope module sky130_fd_sc_hd__dfrtp_1_1_ $end +$var wire 1 -K Q $end +$var wire 1 qJ CLK $end +$var wire 1 ,K D $end +$var wire 1 NH RESET_B $end +$var supply1 1 0w VPWR $end +$var supply0 1 1w VGND $end +$var supply1 1 2w VPB $end +$var supply0 1 3w VNB $end + +$scope module base $end +$var wire 1 -K Q $end +$var wire 1 qJ CLK $end +$var wire 1 ,K D $end +$var wire 1 NH RESET_B $end +$var wire 1 4w buf_Q $end +$var wire 1 5w RESET $end +$upscope $end +$upscope $end + +$scope module FTB_89__88 $end +$var wire 1 9K X $end +$var wire 1 -K A $end +$var supply1 1 6w VPWR $end +$var supply0 1 7w VGND $end +$var supply1 1 8w VPB $end +$var supply0 1 9w VNB $end + +$scope module base $end +$var wire 1 9K X $end +$var wire 1 -K A $end +$var wire 1 :w buf0_out_X $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mem_top_track_50 $end +$var wire 1 NH pReset [0] $end +$var wire 1 qJ prog_clk [0] $end +$var wire 1 9K ccff_head [0] $end +$var wire 1 :K ccff_tail [0] $end +$var wire 1 .K mem_out [0] $end +$var wire 1 /K mem_out [1] $end + +$scope module sky130_fd_sc_hd__dfrtp_1_0_ $end +$var wire 1 .K Q $end +$var wire 1 qJ CLK $end +$var wire 1 9K D $end +$var wire 1 NH RESET_B $end +$var supply1 1 ;w VPWR $end +$var supply0 1 w VNB $end + +$scope module base $end +$var wire 1 .K Q $end +$var wire 1 qJ CLK $end +$var wire 1 9K D $end +$var wire 1 NH RESET_B $end +$var wire 1 ?w buf_Q $end +$var wire 1 @w RESET $end +$upscope $end +$upscope $end + +$scope module sky130_fd_sc_hd__dfrtp_1_1_ $end +$var wire 1 /K Q $end +$var wire 1 qJ CLK $end +$var wire 1 .K D $end +$var wire 1 NH RESET_B $end +$var supply1 1 Aw VPWR $end +$var supply0 1 Bw VGND $end +$var supply1 1 Cw VPB $end +$var supply0 1 Dw VNB $end + +$scope module base $end +$var wire 1 /K Q $end +$var wire 1 qJ CLK $end +$var wire 1 .K D $end +$var wire 1 NH RESET_B $end +$var wire 1 Ew buf_Q $end +$var wire 1 Fw RESET $end +$upscope $end +$upscope $end + +$scope module FTB_90__89 $end +$var wire 1 :K X $end +$var wire 1 /K A $end +$var supply1 1 Gw VPWR $end +$var supply0 1 Hw VGND $end +$var supply1 1 Iw VPB $end +$var supply0 1 Jw VNB $end + +$scope module base $end +$var wire 1 :K X $end +$var wire 1 /K A $end +$var wire 1 Kw buf0_out_X $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mem_top_track_58 $end +$var wire 1 NH pReset [0] $end +$var wire 1 qJ prog_clk [0] $end +$var wire 1 :K ccff_head [0] $end +$var wire 1 1K ccff_tail [0] $end +$var wire 1 zJ mem_out [0] $end +$var wire 1 {J mem_out [1] $end + +$scope module sky130_fd_sc_hd__dfrtp_1_0_ $end +$var wire 1 zJ Q $end +$var wire 1 qJ CLK $end +$var wire 1 :K D $end +$var wire 1 NH RESET_B $end +$var supply1 1 Lw VPWR $end +$var supply0 1 Mw VGND $end +$var supply1 1 Nw VPB $end +$var supply0 1 Ow VNB $end + +$scope module base $end +$var wire 1 zJ Q $end +$var wire 1 qJ CLK $end +$var wire 1 :K D $end +$var wire 1 NH RESET_B $end +$var wire 1 Pw buf_Q $end +$var wire 1 Qw RESET $end +$upscope $end +$upscope $end + +$scope module sky130_fd_sc_hd__dfrtp_1_1_ $end +$var wire 1 {J Q $end +$var wire 1 qJ CLK $end +$var wire 1 zJ D $end +$var wire 1 NH RESET_B $end +$var supply1 1 Rw VPWR $end +$var supply0 1 Sw VGND $end +$var supply1 1 Tw VPB $end +$var supply0 1 Uw VNB $end + +$scope module base $end +$var wire 1 {J Q $end +$var wire 1 qJ CLK $end +$var wire 1 zJ D $end +$var wire 1 NH RESET_B $end +$var wire 1 Vw buf_Q $end +$var wire 1 Ww RESET $end +$upscope $end +$upscope $end + +$scope module FTB_91__90 $end +$var wire 1 1K X $end +$var wire 1 {J A $end +$var supply1 1 Xw VPWR $end +$var supply0 1 Yw VGND $end +$var supply1 1 Zw VPB $end +$var supply0 1 [w VNB $end + +$scope module base $end +$var wire 1 1K X $end +$var wire 1 {J A $end +$var wire 1 \w buf0_out_X $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mux_right_track_2 $end +$var wire 1 OH in [0] $end +$var wire 1 ZH in [1] $end +$var wire 1 eH in [2] $end +$var wire 1 6I in [3] $end +$var wire 1 9I in [4] $end +$var wire 1 x VGND $end +$var supply1 1 ?x VPB $end +$var supply0 1 @x VNB $end + +$scope module base $end +$var wire 1 gw Y $end +$var wire 1 jL A $end +$var wire 1 hw B $end +$var wire 1 Ax nand0_out_Y $end +$upscope $end +$upscope $end + +$scope module U11 $end +$var wire 1 hw Y $end +$var wire 1 ew A $end +$var supply1 1 Bx VPWR $end +$var supply0 1 Cx VGND $end +$var supply1 1 Dx VPB $end +$var supply0 1 Ex VNB $end + +$scope module base $end +$var wire 1 hw Y $end +$var wire 1 ew A $end +$var wire 1 Fx not0_out_Y $end +$upscope $end +$upscope $end + +$scope module U12 $end +$var wire 1 cw Y $end +$var wire 1 ew A $end +$var wire 1 jL B $end +$var supply1 1 Gx VPWR $end +$var supply0 1 Hx VGND $end +$var supply1 1 Ix VPB $end +$var supply0 1 Jx VNB $end + +$scope module base $end +$var wire 1 cw Y $end +$var wire 1 ew A $end +$var wire 1 jL B $end +$var wire 1 Kx nor0_out_Y $end +$upscope $end +$upscope $end + +$scope module FTB_93__92 $end +$var wire 1 ew X $end +$var wire 1 kL A $end +$var supply1 1 Lx VPWR $end +$var supply0 1 Mx VGND $end +$var supply1 1 Nx VPB $end +$var supply0 1 Ox VNB $end + +$scope module base $end +$var wire 1 ew X $end +$var wire 1 kL A $end +$var wire 1 Px buf0_out_X $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mux_l1_in_0_ $end +$var wire 1 OH in [0] $end +$var wire 1 ZH in [1] $end +$var wire 1 eH in [2] $end +$var wire 1 ]w mem [0] $end +$var wire 1 ^w mem [1] $end +$var wire 1 _w mem [2] $end +$var wire 1 `w mem_inv [0] $end +$var wire 1 aw mem_inv [1] $end +$var wire 1 bw mem_inv [2] $end +$var wire 1 iw out [0] $end + +$scope module scs8hd_muxinv3_1_0 $end +$var wire 1 iw Z $end +$var wire 1 OH Q1 $end +$var wire 1 ZH Q2 $end +$var wire 1 eH Q3 $end +$var wire 1 ]w S0 $end +$var wire 1 `w S0B $end +$var wire 1 ^w S1 $end +$var wire 1 aw S1B $end +$var wire 1 _w S2 $end +$var wire 1 bw S2B $end +$var wire 1 Qx Q1__bar $end +$var wire 1 Rx Q2__bar $end +$var wire 1 Sx Q3__bar $end +$upscope $end +$upscope $end + +$scope module mux_l1_in_1_ $end +$var wire 1 6I in [0] $end +$var wire 1 9I in [1] $end +$var wire 1 y VPWR $end +$var supply0 1 ?y VGND $end +$var supply1 1 @y VPB $end +$var supply0 1 Ay VNB $end + +$scope module base $end +$var wire 1 hx Y $end +$var wire 1 ex A $end +$var wire 1 By not0_out_Y $end +$upscope $end +$upscope $end + +$scope module U12 $end +$var wire 1 cx Y $end +$var wire 1 ex A $end +$var wire 1 nL B $end +$var supply1 1 Cy VPWR $end +$var supply0 1 Dy VGND $end +$var supply1 1 Ey VPB $end +$var supply0 1 Fy VNB $end + +$scope module base $end +$var wire 1 cx Y $end +$var wire 1 ex A $end +$var wire 1 nL B $end +$var wire 1 Gy nor0_out_Y $end +$upscope $end +$upscope $end + +$scope module FTB_95__94 $end +$var wire 1 ex X $end +$var wire 1 oL A $end +$var supply1 1 Hy VPWR $end +$var supply0 1 Iy VGND $end +$var supply1 1 Jy VPB $end +$var supply0 1 Ky VNB $end + +$scope module base $end +$var wire 1 ex X $end +$var wire 1 oL A $end +$var wire 1 Ly buf0_out_X $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mux_l1_in_0_ $end +$var wire 1 PH in [0] $end +$var wire 1 [H in [1] $end +$var wire 1 fH in [2] $end +$var wire 1 ]x mem [0] $end +$var wire 1 ^x mem [1] $end +$var wire 1 _x mem [2] $end +$var wire 1 `x mem_inv [0] $end +$var wire 1 ax mem_inv [1] $end +$var wire 1 bx mem_inv [2] $end +$var wire 1 ix out [0] $end + +$scope module scs8hd_muxinv3_1_0 $end +$var wire 1 ix Z $end +$var wire 1 PH Q1 $end +$var wire 1 [H Q2 $end +$var wire 1 fH Q3 $end +$var wire 1 ]x S0 $end +$var wire 1 `x S0B $end +$var wire 1 ^x S1 $end +$var wire 1 ax S1B $end +$var wire 1 _x S2 $end +$var wire 1 bx S2B $end +$var wire 1 My Q1__bar $end +$var wire 1 Ny Q2__bar $end +$var wire 1 Oy Q3__bar $end +$upscope $end +$upscope $end + +$scope module mux_l1_in_1_ $end +$var wire 1 7I in [0] $end +$var wire 1 :I in [1] $end +$var wire 1 =I in [2] $end +$var wire 1 ]x mem [0] $end +$var wire 1 ^x mem [1] $end +$var wire 1 _x mem [2] $end +$var wire 1 `x mem_inv [0] $end +$var wire 1 ax mem_inv [1] $end +$var wire 1 bx mem_inv [2] $end +$var wire 1 jx out [0] $end + +$scope module scs8hd_muxinv3_1_0 $end +$var wire 1 jx Z $end +$var wire 1 7I Q1 $end +$var wire 1 :I Q2 $end +$var wire 1 =I Q3 $end +$var wire 1 ]x S0 $end +$var wire 1 `x S0B $end +$var wire 1 ^x S1 $end +$var wire 1 ax S1B $end +$var wire 1 _x S2 $end +$var wire 1 bx S2B $end +$var wire 1 Py Q1__bar $end +$var wire 1 Qy Q2__bar $end +$var wire 1 Ry Q3__bar $end +$upscope $end +$upscope $end + +$scope module mux_l1_in_2_ $end +$var wire 1 .J in [0] $end +$var wire 1 =J in [1] $end +$var wire 1 mx in [2] $end +$var wire 1 ]x mem [0] $end +$var wire 1 ^x mem [1] $end +$var wire 1 _x mem [2] $end +$var wire 1 `x mem_inv [0] $end +$var wire 1 ax mem_inv [1] $end +$var wire 1 bx mem_inv [2] $end +$var wire 1 kx out [0] $end +$var wire 1 aM p0 $end + +$scope module scs8hd_muxinv3_1_0 $end +$var wire 1 kx Z $end +$var wire 1 .J Q1 $end +$var wire 1 =J Q2 $end +$var wire 1 aM Q3 $end +$var wire 1 ]x S0 $end +$var wire 1 `x S0B $end +$var wire 1 ^x S1 $end +$var wire 1 ax S1B $end +$var wire 1 _x S2 $end +$var wire 1 bx S2B $end +$var wire 1 Sy Q1__bar $end +$var wire 1 Ty Q2__bar $end +$var wire 1 Uy Q3__bar $end +$upscope $end +$upscope $end + +$scope module mux_l2_in_0_ $end +$var wire 1 ix in [0] $end +$var wire 1 jx in [1] $end +$var wire 1 kx in [2] $end +$var wire 1 cx mem [0] $end +$var wire 1 dx mem [1] $end +$var wire 1 ex mem [2] $end +$var wire 1 fx mem_inv [0] $end +$var wire 1 gx mem_inv [1] $end +$var wire 1 hx mem_inv [2] $end +$var wire 1 lx out [0] $end + +$scope module scs8hd_muxinv3_1_0 $end +$var wire 1 lx Z $end +$var wire 1 ix Q1 $end +$var wire 1 jx Q2 $end +$var wire 1 kx Q3 $end +$var wire 1 cx S0 $end +$var wire 1 fx S0B $end +$var wire 1 dx S1 $end +$var wire 1 gx S1B $end +$var wire 1 ex S2 $end +$var wire 1 hx S2B $end +$var wire 1 Vy Q1__bar $end +$var wire 1 Wy Q2__bar $end +$var wire 1 Xy Q3__bar $end +$upscope $end +$upscope $end + +$scope module BINV_R_193 $end +$var wire 1 (J Y $end +$var wire 1 nx A $end +$var supply1 1 Yy VPWR $end +$var supply0 1 Zy VGND $end +$var supply1 1 [y VPB $end +$var supply0 1 \y VNB $end + +$scope module base $end +$var wire 1 (J Y $end +$var wire 1 nx A $end +$var wire 1 ]y not0_out_Y $end +$upscope $end +$upscope $end + +$scope module BINV_R_194 $end +$var wire 1 nx Y $end +$var wire 1 lx A $end +$var supply1 1 ^y VPWR $end +$var supply0 1 _y VGND $end +$var supply1 1 `y VPB $end +$var supply0 1 ay VNB $end + +$scope module base $end +$var wire 1 nx Y $end +$var wire 1 lx A $end +$var wire 1 by not0_out_Y $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mux_left_track_1 $end +$var wire 1 OH in [0] $end +$var wire 1 ZH in [1] $end +$var wire 1 eH in [2] $end +$var wire 1 HJ in [3] $end +$var wire 1 XJ in [4] $end +$var wire 1 \I in [5] $end +$var wire 1 _I in [6] $end +$var wire 1 bI in [7] $end +$var wire 1 pL sram [0] $end +$var wire 1 qL sram [1] $end +$var wire 1 rL sram [2] $end +$var wire 1 sL sram [3] $end +$var wire 1 \N sram_inv [0] $end +$var wire 1 ]N sram_inv [1] $end +$var wire 1 ^N sram_inv [2] $end +$var wire 1 _N sram_inv [3] $end +$var wire 1 DJ out [0] $end +$var wire 1 ,M p0 $end +$var wire 1 cy local_encoder2to3_0_data [0] $end +$var wire 1 dy local_encoder2to3_0_data [1] $end +$var wire 1 ey local_encoder2to3_0_data [2] $end +$var wire 1 fy local_encoder2to3_0_data_inv [0] $end +$var wire 1 gy local_encoder2to3_0_data_inv [1] $end +$var wire 1 hy local_encoder2to3_0_data_inv [2] $end +$var wire 1 iy local_encoder2to3_1_data [0] $end +$var wire 1 jy local_encoder2to3_1_data [1] $end +$var wire 1 ky local_encoder2to3_1_data [2] $end +$var wire 1 ly local_encoder2to3_1_data_inv [0] $end +$var wire 1 my local_encoder2to3_1_data_inv [1] $end +$var wire 1 ny local_encoder2to3_1_data_inv [2] $end +$var wire 1 oy mux_2level_tapbuf_basis_input3_mem3_0_out [0] $end +$var wire 1 py mux_2level_tapbuf_basis_input3_mem3_1_out [0] $end +$var wire 1 qy mux_2level_tapbuf_basis_input3_mem3_2_out [0] $end +$var wire 1 ry mux_2level_tapbuf_basis_input3_mem3_3_out [0] $end +$var wire 1 sy SYNOPSYS_UNCONNECTED_1 $end + +$scope module sky130_fd_sc_hd__buf_4_0_ $end +$var wire 1 DJ X $end +$var wire 1 ry A $end +$var supply1 1 ty VPWR $end +$var supply0 1 uy VGND $end +$var supply1 1 vy VPB $end +$var supply0 1 wy VNB $end + +$scope module base $end +$var wire 1 DJ X $end +$var wire 1 ry A $end +$var wire 1 xy buf0_out_X $end +$upscope $end +$upscope $end + +$scope module local_encoder2to3_0_ $end +$var wire 1 pL addr [0] $end +$var wire 1 qL addr [1] $end +$var wire 1 cy data [0] $end +$var wire 1 dy data [1] $end +$var wire 1 ey data [2] $end +$var wire 1 fy data_inv [0] $end +$var wire 1 gy data_inv [1] $end +$var wire 1 hy data_inv [2] $end + +$scope module U8 $end +$var wire 1 fy Y $end +$var wire 1 cy A $end +$var supply1 1 yy VPWR $end +$var supply0 1 zy VGND $end +$var supply1 1 {y VPB $end +$var supply0 1 |y VNB $end + +$scope module base $end +$var wire 1 fy Y $end +$var wire 1 cy A $end +$var wire 1 }y not0_out_Y $end +$upscope $end +$upscope $end + +$scope module U9 $end +$var wire 1 dy Y $end +$var wire 1 gy A $end +$var supply1 1 ~y VPWR $end +$var supply0 1 !z VGND $end +$var supply1 1 "z VPB $end +$var supply0 1 #z VNB $end + +$scope module base $end +$var wire 1 dy Y $end +$var wire 1 gy A $end +$var wire 1 $z not0_out_Y $end +$upscope $end +$upscope $end + +$scope module U10 $end +$var wire 1 gy Y $end +$var wire 1 pL A $end +$var wire 1 hy B $end +$var supply1 1 %z VPWR $end +$var supply0 1 &z VGND $end +$var supply1 1 'z VPB $end +$var supply0 1 (z VNB $end + +$scope module base $end +$var wire 1 gy Y $end +$var wire 1 pL A $end +$var wire 1 hy B $end +$var wire 1 )z nand0_out_Y $end +$upscope $end +$upscope $end + +$scope module U11 $end +$var wire 1 hy Y $end +$var wire 1 ey A $end +$var supply1 1 *z VPWR $end +$var supply0 1 +z VGND $end +$var supply1 1 ,z VPB $end +$var supply0 1 -z VNB $end + +$scope module base $end +$var wire 1 hy Y $end +$var wire 1 ey A $end +$var wire 1 .z not0_out_Y $end +$upscope $end +$upscope $end + +$scope module U12 $end +$var wire 1 cy Y $end +$var wire 1 ey A $end +$var wire 1 pL B $end +$var supply1 1 /z VPWR $end +$var supply0 1 0z VGND $end +$var supply1 1 1z VPB $end +$var supply0 1 2z VNB $end + +$scope module base $end +$var wire 1 cy Y $end +$var wire 1 ey A $end +$var wire 1 pL B $end +$var wire 1 3z nor0_out_Y $end +$upscope $end +$upscope $end + +$scope module FTB_96__95 $end +$var wire 1 ey X $end +$var wire 1 qL A $end +$var supply1 1 4z VPWR $end +$var supply0 1 5z VGND $end +$var supply1 1 6z VPB $end +$var supply0 1 7z VNB $end + +$scope module base $end +$var wire 1 ey X $end +$var wire 1 qL A $end +$var wire 1 8z buf0_out_X $end +$upscope $end +$upscope $end +$upscope $end + +$scope module local_encoder2to3_1_ $end +$var wire 1 rL addr [0] $end +$var wire 1 sL addr [1] $end +$var wire 1 iy data [0] $end +$var wire 1 jy data [1] $end +$var wire 1 ky data [2] $end +$var wire 1 ly data_inv [0] $end +$var wire 1 my data_inv [1] $end +$var wire 1 ny data_inv [2] $end + +$scope module U8 $end +$var wire 1 ly Y $end +$var wire 1 iy A $end +$var supply1 1 9z VPWR $end +$var supply0 1 :z VGND $end +$var supply1 1 ;z VPB $end +$var supply0 1 z VPWR $end +$var supply0 1 ?z VGND $end +$var supply1 1 @z VPB $end +$var supply0 1 Az VNB $end + +$scope module base $end +$var wire 1 jy Y $end +$var wire 1 my A $end +$var wire 1 Bz not0_out_Y $end +$upscope $end +$upscope $end + +$scope module U10 $end +$var wire 1 my Y $end +$var wire 1 rL A $end +$var wire 1 ny B $end +$var supply1 1 Cz VPWR $end +$var supply0 1 Dz VGND $end +$var supply1 1 Ez VPB $end +$var supply0 1 Fz VNB $end + +$scope module base $end +$var wire 1 my Y $end +$var wire 1 rL A $end +$var wire 1 ny B $end +$var wire 1 Gz nand0_out_Y $end +$upscope $end +$upscope $end + +$scope module U11 $end +$var wire 1 ny Y $end +$var wire 1 ky A $end +$var supply1 1 Hz VPWR $end +$var supply0 1 Iz VGND $end +$var supply1 1 Jz VPB $end +$var supply0 1 Kz VNB $end + +$scope module base $end +$var wire 1 ny Y $end +$var wire 1 ky A $end +$var wire 1 Lz not0_out_Y $end +$upscope $end +$upscope $end + +$scope module U12 $end +$var wire 1 iy Y $end +$var wire 1 ky A $end +$var wire 1 rL B $end +$var supply1 1 Mz VPWR $end +$var supply0 1 Nz VGND $end +$var supply1 1 Oz VPB $end +$var supply0 1 Pz VNB $end + +$scope module base $end +$var wire 1 iy Y $end +$var wire 1 ky A $end +$var wire 1 rL B $end +$var wire 1 Qz nor0_out_Y $end +$upscope $end +$upscope $end + +$scope module FTB_97__96 $end +$var wire 1 ky X $end +$var wire 1 sL A $end +$var supply1 1 Rz VPWR $end +$var supply0 1 Sz VGND $end +$var supply1 1 Tz VPB $end +$var supply0 1 Uz VNB $end + +$scope module base $end +$var wire 1 ky X $end +$var wire 1 sL A $end +$var wire 1 Vz buf0_out_X $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mux_l1_in_0_ $end +$var wire 1 OH in [0] $end +$var wire 1 ZH in [1] $end +$var wire 1 eH in [2] $end +$var wire 1 cy mem [0] $end +$var wire 1 dy mem [1] $end +$var wire 1 ey mem [2] $end +$var wire 1 fy mem_inv [0] $end +$var wire 1 gy mem_inv [1] $end +$var wire 1 hy mem_inv [2] $end +$var wire 1 oy out [0] $end + +$scope module scs8hd_muxinv3_1_0 $end +$var wire 1 oy Z $end +$var wire 1 OH Q1 $end +$var wire 1 ZH Q2 $end +$var wire 1 eH Q3 $end +$var wire 1 cy S0 $end +$var wire 1 fy S0B $end +$var wire 1 dy S1 $end +$var wire 1 gy S1B $end +$var wire 1 ey S2 $end +$var wire 1 hy S2B $end +$var wire 1 Wz Q1__bar $end +$var wire 1 Xz Q2__bar $end +$var wire 1 Yz Q3__bar $end +$upscope $end +$upscope $end + +$scope module mux_l1_in_1_ $end +$var wire 1 HJ in [0] $end +$var wire 1 XJ in [1] $end +$var wire 1 \I in [2] $end +$var wire 1 cy mem [0] $end +$var wire 1 dy mem [1] $end +$var wire 1 ey mem [2] $end +$var wire 1 fy mem_inv [0] $end +$var wire 1 gy mem_inv [1] $end +$var wire 1 hy mem_inv [2] $end +$var wire 1 py out [0] $end + +$scope module scs8hd_muxinv3_1_0 $end +$var wire 1 py Z $end +$var wire 1 HJ Q1 $end +$var wire 1 XJ Q2 $end +$var wire 1 \I Q3 $end +$var wire 1 cy S0 $end +$var wire 1 fy S0B $end +$var wire 1 dy S1 $end +$var wire 1 gy S1B $end +$var wire 1 ey S2 $end +$var wire 1 hy S2B $end +$var wire 1 Zz Q1__bar $end +$var wire 1 [z Q2__bar $end +$var wire 1 \z Q3__bar $end +$upscope $end +$upscope $end + +$scope module mux_l1_in_2_ $end +$var wire 1 _I in [0] $end +$var wire 1 bI in [1] $end +$var wire 1 sy in [2] $end +$var wire 1 cy mem [0] $end +$var wire 1 dy mem [1] $end +$var wire 1 ey mem [2] $end +$var wire 1 fy mem_inv [0] $end +$var wire 1 gy mem_inv [1] $end +$var wire 1 hy mem_inv [2] $end +$var wire 1 qy out [0] $end +$var wire 1 ,M p0 $end + +$scope module scs8hd_muxinv3_1_0 $end +$var wire 1 qy Z $end +$var wire 1 _I Q1 $end +$var wire 1 bI Q2 $end +$var wire 1 ,M Q3 $end +$var wire 1 cy S0 $end +$var wire 1 fy S0B $end +$var wire 1 dy S1 $end +$var wire 1 gy S1B $end +$var wire 1 ey S2 $end +$var wire 1 hy S2B $end +$var wire 1 ]z Q1__bar $end +$var wire 1 ^z Q2__bar $end +$var wire 1 _z Q3__bar $end +$upscope $end +$upscope $end + +$scope module mux_l2_in_0_ $end +$var wire 1 oy in [0] $end +$var wire 1 py in [1] $end +$var wire 1 qy in [2] $end +$var wire 1 iy mem [0] $end +$var wire 1 jy mem [1] $end +$var wire 1 ky mem [2] $end +$var wire 1 ly mem_inv [0] $end +$var wire 1 my mem_inv [1] $end +$var wire 1 ny mem_inv [2] $end +$var wire 1 ry out [0] $end + +$scope module scs8hd_muxinv3_1_0 $end +$var wire 1 ry Z $end +$var wire 1 oy Q1 $end +$var wire 1 py Q2 $end +$var wire 1 qy Q3 $end +$var wire 1 iy S0 $end +$var wire 1 ly S0B $end +$var wire 1 jy S1 $end +$var wire 1 my S1B $end +$var wire 1 ky S2 $end +$var wire 1 ny S2B $end +$var wire 1 `z Q1__bar $end +$var wire 1 az Q2__bar $end +$var wire 1 bz Q3__bar $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mem_right_track_2 $end +$var wire 1 NH pReset [0] $end +$var wire 1 qJ prog_clk [0] $end +$var wire 1 _L ccff_head [0] $end +$var wire 1 tL ccff_tail [0] $end +$var wire 1 hL mem_out [0] $end +$var wire 1 iL mem_out [1] $end +$var wire 1 jL mem_out [2] $end +$var wire 1 kL mem_out [3] $end + +$scope module sky130_fd_sc_hd__dfrtp_1_0_ $end +$var wire 1 hL Q $end +$var wire 1 qJ CLK $end +$var wire 1 _L D $end +$var wire 1 NH RESET_B $end +$var supply1 1 cz VPWR $end +$var supply0 1 dz VGND $end +$var supply1 1 ez VPB $end +$var supply0 1 fz VNB $end + +$scope module base $end +$var wire 1 hL Q $end +$var wire 1 qJ CLK $end +$var wire 1 _L D $end +$var wire 1 NH RESET_B $end +$var wire 1 gz buf_Q $end +$var wire 1 hz RESET $end +$upscope $end +$upscope $end + +$scope module sky130_fd_sc_hd__dfrtp_1_1_ $end +$var wire 1 iL Q $end +$var wire 1 qJ CLK $end +$var wire 1 hL D $end +$var wire 1 NH RESET_B $end +$var supply1 1 iz VPWR $end +$var supply0 1 jz VGND $end +$var supply1 1 kz VPB $end +$var supply0 1 lz VNB $end + +$scope module base $end +$var wire 1 iL Q $end +$var wire 1 qJ CLK $end +$var wire 1 hL D $end +$var wire 1 NH RESET_B $end +$var wire 1 mz buf_Q $end +$var wire 1 nz RESET $end +$upscope $end +$upscope $end + +$scope module sky130_fd_sc_hd__dfrtp_1_2_ $end +$var wire 1 jL Q $end +$var wire 1 qJ CLK $end +$var wire 1 iL D $end +$var wire 1 NH RESET_B $end +$var supply1 1 oz VPWR $end +$var supply0 1 pz VGND $end +$var supply1 1 qz VPB $end +$var supply0 1 rz VNB $end + +$scope module base $end +$var wire 1 jL Q $end +$var wire 1 qJ CLK $end +$var wire 1 iL D $end +$var wire 1 NH RESET_B $end +$var wire 1 sz buf_Q $end +$var wire 1 tz RESET $end +$upscope $end +$upscope $end + +$scope module sky130_fd_sc_hd__dfrtp_1_3_ $end +$var wire 1 kL Q $end +$var wire 1 qJ CLK $end +$var wire 1 jL D $end +$var wire 1 NH RESET_B $end +$var supply1 1 uz VPWR $end +$var supply0 1 vz VGND $end +$var supply1 1 wz VPB $end +$var supply0 1 xz VNB $end + +$scope module base $end +$var wire 1 kL Q $end +$var wire 1 qJ CLK $end +$var wire 1 jL D $end +$var wire 1 NH RESET_B $end +$var wire 1 yz buf_Q $end +$var wire 1 zz RESET $end +$upscope $end +$upscope $end + +$scope module FTB_98__97 $end +$var wire 1 tL X $end +$var wire 1 kL A $end +$var supply1 1 {z VPWR $end +$var supply0 1 |z VGND $end +$var supply1 1 }z VPB $end +$var supply0 1 ~z VNB $end + +$scope module base $end +$var wire 1 tL X $end +$var wire 1 kL A $end +$var wire 1 !{ buf0_out_X $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mem_right_track_4 $end +$var wire 1 NH pReset [0] $end +$var wire 1 qJ prog_clk [0] $end +$var wire 1 tL ccff_head [0] $end +$var wire 1 uL ccff_tail [0] $end +$var wire 1 lL mem_out [0] $end +$var wire 1 mL mem_out [1] $end +$var wire 1 nL mem_out [2] $end +$var wire 1 oL mem_out [3] $end + +$scope module sky130_fd_sc_hd__dfrtp_1_0_ $end +$var wire 1 lL Q $end +$var wire 1 qJ CLK $end +$var wire 1 tL D $end +$var wire 1 NH RESET_B $end +$var supply1 1 "{ VPWR $end +$var supply0 1 #{ VGND $end +$var supply1 1 ${ VPB $end +$var supply0 1 %{ VNB $end + +$scope module base $end +$var wire 1 lL Q $end +$var wire 1 qJ CLK $end +$var wire 1 tL D $end +$var wire 1 NH RESET_B $end +$var wire 1 &{ buf_Q $end +$var wire 1 '{ RESET $end +$upscope $end +$upscope $end + +$scope module sky130_fd_sc_hd__dfrtp_1_1_ $end +$var wire 1 mL Q $end +$var wire 1 qJ CLK $end +$var wire 1 lL D $end +$var wire 1 NH RESET_B $end +$var supply1 1 ({ VPWR $end +$var supply0 1 ){ VGND $end +$var supply1 1 *{ VPB $end +$var supply0 1 +{ VNB $end + +$scope module base $end +$var wire 1 mL Q $end +$var wire 1 qJ CLK $end +$var wire 1 lL D $end +$var wire 1 NH RESET_B $end +$var wire 1 ,{ buf_Q $end +$var wire 1 -{ RESET $end +$upscope $end +$upscope $end + +$scope module sky130_fd_sc_hd__dfrtp_1_2_ $end +$var wire 1 nL Q $end +$var wire 1 qJ CLK $end +$var wire 1 mL D $end +$var wire 1 NH RESET_B $end +$var supply1 1 .{ VPWR $end +$var supply0 1 /{ VGND $end +$var supply1 1 0{ VPB $end +$var supply0 1 1{ VNB $end + +$scope module base $end +$var wire 1 nL Q $end +$var wire 1 qJ CLK $end +$var wire 1 mL D $end +$var wire 1 NH RESET_B $end +$var wire 1 2{ buf_Q $end +$var wire 1 3{ RESET $end +$upscope $end +$upscope $end + +$scope module sky130_fd_sc_hd__dfrtp_1_3_ $end +$var wire 1 oL Q $end +$var wire 1 qJ CLK $end +$var wire 1 nL D $end +$var wire 1 NH RESET_B $end +$var supply1 1 4{ VPWR $end +$var supply0 1 5{ VGND $end +$var supply1 1 6{ VPB $end +$var supply0 1 7{ VNB $end + +$scope module base $end +$var wire 1 oL Q $end +$var wire 1 qJ CLK $end +$var wire 1 nL D $end +$var wire 1 NH RESET_B $end +$var wire 1 8{ buf_Q $end +$var wire 1 9{ RESET $end +$upscope $end +$upscope $end + +$scope module FTB_99__98 $end +$var wire 1 uL X $end +$var wire 1 oL A $end +$var supply1 1 :{ VPWR $end +$var supply0 1 ;{ VGND $end +$var supply1 1 <{ VPB $end +$var supply0 1 ={ VNB $end + +$scope module base $end +$var wire 1 uL X $end +$var wire 1 oL A $end +$var wire 1 >{ buf0_out_X $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mem_left_track_1 $end +$var wire 1 NH pReset [0] $end +$var wire 1 qJ prog_clk [0] $end +$var wire 1 gK ccff_head [0] $end +$var wire 1 vL ccff_tail [0] $end +$var wire 1 pL mem_out [0] $end +$var wire 1 qL mem_out [1] $end +$var wire 1 rL mem_out [2] $end +$var wire 1 sL mem_out [3] $end + +$scope module sky130_fd_sc_hd__dfrtp_1_0_ $end +$var wire 1 pL Q $end +$var wire 1 qJ CLK $end +$var wire 1 gK D $end +$var wire 1 NH RESET_B $end +$var supply1 1 ?{ VPWR $end +$var supply0 1 @{ VGND $end +$var supply1 1 A{ VPB $end +$var supply0 1 B{ VNB $end + +$scope module base $end +$var wire 1 pL Q $end +$var wire 1 qJ CLK $end +$var wire 1 gK D $end +$var wire 1 NH RESET_B $end +$var wire 1 C{ buf_Q $end +$var wire 1 D{ RESET $end +$upscope $end +$upscope $end + +$scope module sky130_fd_sc_hd__dfrtp_1_1_ $end +$var wire 1 qL Q $end +$var wire 1 qJ CLK $end +$var wire 1 pL D $end +$var wire 1 NH RESET_B $end +$var supply1 1 E{ VPWR $end +$var supply0 1 F{ VGND $end +$var supply1 1 G{ VPB $end +$var supply0 1 H{ VNB $end + +$scope module base $end +$var wire 1 qL Q $end +$var wire 1 qJ CLK $end +$var wire 1 pL D $end +$var wire 1 NH RESET_B $end +$var wire 1 I{ buf_Q $end +$var wire 1 J{ RESET $end +$upscope $end +$upscope $end + +$scope module sky130_fd_sc_hd__dfrtp_1_2_ $end +$var wire 1 rL Q $end +$var wire 1 qJ CLK $end +$var wire 1 qL D $end +$var wire 1 NH RESET_B $end +$var supply1 1 K{ VPWR $end +$var supply0 1 L{ VGND $end +$var supply1 1 M{ VPB $end +$var supply0 1 N{ VNB $end + +$scope module base $end +$var wire 1 rL Q $end +$var wire 1 qJ CLK $end +$var wire 1 qL D $end +$var wire 1 NH RESET_B $end +$var wire 1 O{ buf_Q $end +$var wire 1 P{ RESET $end +$upscope $end +$upscope $end + +$scope module sky130_fd_sc_hd__dfrtp_1_3_ $end +$var wire 1 sL Q $end +$var wire 1 qJ CLK $end +$var wire 1 rL D $end +$var wire 1 NH RESET_B $end +$var supply1 1 Q{ VPWR $end +$var supply0 1 R{ VGND $end +$var supply1 1 S{ VPB $end +$var supply0 1 T{ VNB $end + +$scope module base $end +$var wire 1 sL Q $end +$var wire 1 qJ CLK $end +$var wire 1 rL D $end +$var wire 1 NH RESET_B $end +$var wire 1 U{ buf_Q $end +$var wire 1 V{ RESET $end +$upscope $end +$upscope $end + +$scope module FTB_100__99 $end +$var wire 1 vL X $end +$var wire 1 sL A $end +$var supply1 1 W{ VPWR $end +$var supply0 1 X{ VGND $end +$var supply1 1 Y{ VPB $end +$var supply0 1 Z{ VNB $end + +$scope module base $end +$var wire 1 vL X $end +$var wire 1 sL A $end +$var wire 1 [{ buf0_out_X $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mux_right_track_6 $end +$var wire 1 QH in [0] $end +$var wire 1 \H in [1] $end +$var wire 1 gH in [2] $end +$var wire 1 5I in [3] $end +$var wire 1 7I in [4] $end +$var wire 1 9I in [5] $end +$var wire 1 ;I in [6] $end +$var wire 1 =I in [7] $end +$var wire 1 /J in [8] $end +$var wire 1 >J in [9] $end +$var wire 1 sJ sram [0] $end +$var wire 1 tJ sram [1] $end +$var wire 1 uJ sram [2] $end +$var wire 1 vJ sram [3] $end +$var wire 1 `N sram_inv [0] $end +$var wire 1 aN sram_inv [1] $end +$var wire 1 bN sram_inv [2] $end +$var wire 1 cN sram_inv [3] $end +$var wire 1 dN out [0] $end +$var wire 1 aM p0 $end +$var wire 1 \{ local_encoder2to4_0_data [0] $end +$var wire 1 ]{ local_encoder2to4_0_data [1] $end +$var wire 1 ^{ local_encoder2to4_0_data [2] $end +$var wire 1 _{ local_encoder2to4_0_data [3] $end +$var wire 1 `{ local_encoder2to4_0_data_inv [0] $end +$var wire 1 a{ local_encoder2to4_0_data_inv [1] $end +$var wire 1 b{ local_encoder2to4_0_data_inv [2] $end +$var wire 1 c{ local_encoder2to4_0_data_inv [3] $end +$var wire 1 d{ local_encoder2to4_1_data [0] $end +$var wire 1 e{ local_encoder2to4_1_data [1] $end +$var wire 1 f{ local_encoder2to4_1_data [2] $end +$var wire 1 g{ local_encoder2to4_1_data [3] $end +$var wire 1 h{ local_encoder2to4_1_data_inv [0] $end +$var wire 1 i{ local_encoder2to4_1_data_inv [1] $end +$var wire 1 j{ local_encoder2to4_1_data_inv [2] $end +$var wire 1 k{ local_encoder2to4_1_data_inv [3] $end +$var wire 1 l{ mux_2level_tapbuf_basis_input2_mem2_0_out [0] $end +$var wire 1 m{ mux_2level_tapbuf_basis_input4_mem4_0_out [0] $end +$var wire 1 n{ mux_2level_tapbuf_basis_input4_mem4_1_out [0] $end +$var wire 1 o{ mux_2level_tapbuf_basis_input4_mem4_2_out [0] $end +$var wire 1 p{ SYNOPSYS_UNCONNECTED_1 $end + +$scope module sky130_fd_sc_hd__buf_4_0_ $end +$var wire 1 dN X $end +$var wire 1 o{ A $end +$var supply1 1 q{ VPWR $end +$var supply0 1 r{ VGND $end +$var supply1 1 s{ VPB $end +$var supply0 1 t{ VNB $end + +$scope module base $end +$var wire 1 dN X $end +$var wire 1 o{ A $end +$var wire 1 u{ buf0_out_X $end +$upscope $end +$upscope $end + +$scope module local_encoder2to4_0_ $end +$var wire 1 sJ addr [0] $end +$var wire 1 tJ addr [1] $end +$var wire 1 \{ data [0] $end +$var wire 1 ]{ data [1] $end +$var wire 1 ^{ data [2] $end +$var wire 1 _{ data [3] $end +$var wire 1 `{ data_inv [0] $end +$var wire 1 a{ data_inv [1] $end +$var wire 1 b{ data_inv [2] $end +$var wire 1 c{ data_inv [3] $end +$var wire 1 v{ n9 $end + +$scope module U13 $end +$var wire 1 \{ Y $end +$var wire 1 tJ A $end +$var wire 1 sJ B $end +$var supply1 1 w{ VPWR $end +$var supply0 1 x{ VGND $end +$var supply1 1 y{ VPB $end +$var supply0 1 z{ VNB $end + +$scope module base $end +$var wire 1 \{ Y $end +$var wire 1 tJ A $end +$var wire 1 sJ B $end +$var wire 1 {{ nor0_out_Y $end +$upscope $end +$upscope $end + +$scope module U14 $end +$var wire 1 a{ Y $end +$var wire 1 ]{ A $end +$var supply1 1 |{ VPWR $end +$var supply0 1 }{ VGND $end +$var supply1 1 ~{ VPB $end +$var supply0 1 !| VNB $end + +$scope module base $end +$var wire 1 a{ Y $end +$var wire 1 ]{ A $end +$var wire 1 "| not0_out_Y $end +$upscope $end +$upscope $end + +$scope module U15 $end +$var wire 1 `{ Y $end +$var wire 1 \{ A $end +$var supply1 1 #| VPWR $end +$var supply0 1 $| VGND $end +$var supply1 1 %| VPB $end +$var supply0 1 &| VNB $end + +$scope module base $end +$var wire 1 `{ Y $end +$var wire 1 \{ A $end +$var wire 1 '| not0_out_Y $end +$upscope $end +$upscope $end + +$scope module U16 $end +$var wire 1 ^{ Y $end +$var wire 1 b{ A $end +$var supply1 1 (| VPWR $end +$var supply0 1 )| VGND $end +$var supply1 1 *| VPB $end +$var supply0 1 +| VNB $end + +$scope module base $end +$var wire 1 ^{ Y $end +$var wire 1 b{ A $end +$var wire 1 ,| not0_out_Y $end +$upscope $end +$upscope $end + +$scope module U17 $end +$var wire 1 b{ Y $end +$var wire 1 tJ A $end +$var wire 1 v{ B $end +$var supply1 1 -| VPWR $end +$var supply0 1 .| VGND $end +$var supply1 1 /| VPB $end +$var supply0 1 0| VNB $end + +$scope module base $end +$var wire 1 b{ Y $end +$var wire 1 tJ A $end +$var wire 1 v{ B $end +$var wire 1 1| nand0_out_Y $end +$upscope $end +$upscope $end + +$scope module U18 $end +$var wire 1 ]{ Y $end +$var wire 1 v{ A $end +$var wire 1 tJ B $end +$var supply1 1 2| VPWR $end +$var supply0 1 3| VGND $end +$var supply1 1 4| VPB $end +$var supply0 1 5| VNB $end + +$scope module base $end +$var wire 1 ]{ Y $end +$var wire 1 v{ A $end +$var wire 1 tJ B $end +$var wire 1 6| nor0_out_Y $end +$upscope $end +$upscope $end + +$scope module U19 $end +$var wire 1 v{ Y $end +$var wire 1 sJ A $end +$var supply1 1 7| VPWR $end +$var supply0 1 8| VGND $end +$var supply1 1 9| VPB $end +$var supply0 1 :| VNB $end + +$scope module base $end +$var wire 1 v{ Y $end +$var wire 1 sJ A $end +$var wire 1 ;| not0_out_Y $end +$upscope $end +$upscope $end + +$scope module U20 $end +$var wire 1 _{ Y $end +$var wire 1 c{ A $end +$var supply1 1 <| VPWR $end +$var supply0 1 =| VGND $end +$var supply1 1 >| VPB $end +$var supply0 1 ?| VNB $end + +$scope module base $end +$var wire 1 _{ Y $end +$var wire 1 c{ A $end +$var wire 1 @| not0_out_Y $end +$upscope $end +$upscope $end + +$scope module U21 $end +$var wire 1 c{ Y $end +$var wire 1 tJ A $end +$var wire 1 sJ B $end +$var supply1 1 A| VPWR $end +$var supply0 1 B| VGND $end +$var supply1 1 C| VPB $end +$var supply0 1 D| VNB $end + +$scope module base $end +$var wire 1 c{ Y $end +$var wire 1 tJ A $end +$var wire 1 sJ B $end +$var wire 1 E| nand0_out_Y $end +$upscope $end +$upscope $end +$upscope $end + +$scope module local_encoder2to4_1_ $end +$var wire 1 uJ addr [0] $end +$var wire 1 vJ addr [1] $end +$var wire 1 d{ data [0] $end +$var wire 1 e{ data [1] $end +$var wire 1 f{ data [2] $end +$var wire 1 g{ data [3] $end +$var wire 1 h{ data_inv [0] $end +$var wire 1 i{ data_inv [1] $end +$var wire 1 j{ data_inv [2] $end +$var wire 1 k{ data_inv [3] $end +$var wire 1 F| n9 $end + +$scope module U13 $end +$var wire 1 d{ Y $end +$var wire 1 vJ A $end +$var wire 1 uJ B $end +$var supply1 1 G| VPWR $end +$var supply0 1 H| VGND $end +$var supply1 1 I| VPB $end +$var supply0 1 J| VNB $end + +$scope module base $end +$var wire 1 d{ Y $end +$var wire 1 vJ A $end +$var wire 1 uJ B $end +$var wire 1 K| nor0_out_Y $end +$upscope $end +$upscope $end + +$scope module U14 $end +$var wire 1 i{ Y $end +$var wire 1 e{ A $end +$var supply1 1 L| VPWR $end +$var supply0 1 M| VGND $end +$var supply1 1 N| VPB $end +$var supply0 1 O| VNB $end + +$scope module base $end +$var wire 1 i{ Y $end +$var wire 1 e{ A $end +$var wire 1 P| not0_out_Y $end +$upscope $end +$upscope $end + +$scope module U15 $end +$var wire 1 h{ Y $end +$var wire 1 d{ A $end +$var supply1 1 Q| VPWR $end +$var supply0 1 R| VGND $end +$var supply1 1 S| VPB $end +$var supply0 1 T| VNB $end + +$scope module base $end +$var wire 1 h{ Y $end +$var wire 1 d{ A $end +$var wire 1 U| not0_out_Y $end +$upscope $end +$upscope $end + +$scope module U16 $end +$var wire 1 f{ Y $end +$var wire 1 j{ A $end +$var supply1 1 V| VPWR $end +$var supply0 1 W| VGND $end +$var supply1 1 X| VPB $end +$var supply0 1 Y| VNB $end + +$scope module base $end +$var wire 1 f{ Y $end +$var wire 1 j{ A $end +$var wire 1 Z| not0_out_Y $end +$upscope $end +$upscope $end + +$scope module U17 $end +$var wire 1 j{ Y $end +$var wire 1 vJ A $end +$var wire 1 F| B $end +$var supply1 1 [| VPWR $end +$var supply0 1 \| VGND $end +$var supply1 1 ]| VPB $end +$var supply0 1 ^| VNB $end + +$scope module base $end +$var wire 1 j{ Y $end +$var wire 1 vJ A $end +$var wire 1 F| B $end +$var wire 1 _| nand0_out_Y $end +$upscope $end +$upscope $end + +$scope module U18 $end +$var wire 1 e{ Y $end +$var wire 1 F| A $end +$var wire 1 vJ B $end +$var supply1 1 `| VPWR $end +$var supply0 1 a| VGND $end +$var supply1 1 b| VPB $end +$var supply0 1 c| VNB $end + +$scope module base $end +$var wire 1 e{ Y $end +$var wire 1 F| A $end +$var wire 1 vJ B $end +$var wire 1 d| nor0_out_Y $end +$upscope $end +$upscope $end + +$scope module U19 $end +$var wire 1 F| Y $end +$var wire 1 uJ A $end +$var supply1 1 e| VPWR $end +$var supply0 1 f| VGND $end +$var supply1 1 g| VPB $end +$var supply0 1 h| VNB $end + +$scope module base $end +$var wire 1 F| Y $end +$var wire 1 uJ A $end +$var wire 1 i| not0_out_Y $end +$upscope $end +$upscope $end + +$scope module U20 $end +$var wire 1 g{ Y $end +$var wire 1 k{ A $end +$var supply1 1 j| VPWR $end +$var supply0 1 k| VGND $end +$var supply1 1 l| VPB $end +$var supply0 1 m| VNB $end + +$scope module base $end +$var wire 1 g{ Y $end +$var wire 1 k{ A $end +$var wire 1 n| not0_out_Y $end +$upscope $end +$upscope $end + +$scope module U21 $end +$var wire 1 k{ Y $end +$var wire 1 vJ A $end +$var wire 1 uJ B $end +$var supply1 1 o| VPWR $end +$var supply0 1 p| VGND $end +$var supply1 1 q| VPB $end +$var supply0 1 r| VNB $end + +$scope module base $end +$var wire 1 k{ Y $end +$var wire 1 vJ A $end +$var wire 1 uJ B $end +$var wire 1 s| nand0_out_Y $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mux_l1_in_0_ $end +$var wire 1 QH in [0] $end +$var wire 1 \H in [1] $end +$var wire 1 gH in [2] $end +$var wire 1 5I in [3] $end +$var wire 1 \{ mem [0] $end +$var wire 1 ]{ mem [1] $end +$var wire 1 ^{ mem [2] $end +$var wire 1 _{ mem [3] $end +$var wire 1 `{ mem_inv [0] $end +$var wire 1 a{ mem_inv [1] $end +$var wire 1 b{ mem_inv [2] $end +$var wire 1 c{ mem_inv [3] $end +$var wire 1 m{ out [0] $end + +$scope module scs8hd_muxinv2_1_0 $end +$var wire 1 m{ Z $end +$var wire 1 QH Q1 $end +$var wire 1 \H Q2 $end +$var wire 1 \{ S0 $end +$var wire 1 `{ S0B $end +$var wire 1 ]{ S1 $end +$var wire 1 a{ S1B $end +$var wire 1 t| Q1__bar $end +$var wire 1 u| Q2__bar $end +$upscope $end + +$scope module scs8hd_muxinv2_1_1 $end +$var wire 1 m{ Z $end +$var wire 1 gH Q1 $end +$var wire 1 5I Q2 $end +$var wire 1 ^{ S0 $end +$var wire 1 b{ S0B $end +$var wire 1 _{ S1 $end +$var wire 1 c{ S1B $end +$var wire 1 v| Q1__bar $end +$var wire 1 w| Q2__bar $end +$upscope $end +$upscope $end + +$scope module mux_l1_in_1_ $end +$var wire 1 7I in [0] $end +$var wire 1 9I in [1] $end +$var wire 1 ;I in [2] $end +$var wire 1 =I in [3] $end +$var wire 1 \{ mem [0] $end +$var wire 1 ]{ mem [1] $end +$var wire 1 ^{ mem [2] $end +$var wire 1 _{ mem [3] $end +$var wire 1 `{ mem_inv [0] $end +$var wire 1 a{ mem_inv [1] $end +$var wire 1 b{ mem_inv [2] $end +$var wire 1 c{ mem_inv [3] $end +$var wire 1 n{ out [0] $end + +$scope module scs8hd_muxinv2_1_0 $end +$var wire 1 n{ Z $end +$var wire 1 7I Q1 $end +$var wire 1 9I Q2 $end +$var wire 1 \{ S0 $end +$var wire 1 `{ S0B $end +$var wire 1 ]{ S1 $end +$var wire 1 a{ S1B $end +$var wire 1 x| Q1__bar $end +$var wire 1 y| Q2__bar $end +$upscope $end + +$scope module scs8hd_muxinv2_1_1 $end +$var wire 1 n{ Z $end +$var wire 1 ;I Q1 $end +$var wire 1 =I Q2 $end +$var wire 1 ^{ S0 $end +$var wire 1 b{ S0B $end +$var wire 1 _{ S1 $end +$var wire 1 c{ S1B $end +$var wire 1 z| Q1__bar $end +$var wire 1 {| Q2__bar $end +$upscope $end +$upscope $end + +$scope module mux_l2_in_0_ $end +$var wire 1 m{ in [0] $end +$var wire 1 n{ in [1] $end +$var wire 1 l{ in [2] $end +$var wire 1 p{ in [3] $end +$var wire 1 d{ mem [0] $end +$var wire 1 e{ mem [1] $end +$var wire 1 f{ mem [2] $end +$var wire 1 g{ mem [3] $end +$var wire 1 h{ mem_inv [0] $end +$var wire 1 i{ mem_inv [1] $end +$var wire 1 j{ mem_inv [2] $end +$var wire 1 k{ mem_inv [3] $end +$var wire 1 o{ out [0] $end +$var wire 1 aM p0 $end + +$scope module scs8hd_muxinv2_1_0 $end +$var wire 1 o{ Z $end +$var wire 1 m{ Q1 $end +$var wire 1 n{ Q2 $end +$var wire 1 d{ S0 $end +$var wire 1 h{ S0B $end +$var wire 1 e{ S1 $end +$var wire 1 i{ S1B $end +$var wire 1 || Q1__bar $end +$var wire 1 }| Q2__bar $end +$upscope $end + +$scope module scs8hd_muxinv2_1_1 $end +$var wire 1 o{ Z $end +$var wire 1 l{ Q1 $end +$var wire 1 aM Q2 $end +$var wire 1 f{ S0 $end +$var wire 1 j{ S0B $end +$var wire 1 g{ S1 $end +$var wire 1 k{ S1B $end +$var wire 1 ~| Q1__bar $end +$var wire 1 !} Q2__bar $end +$upscope $end +$upscope $end + +$scope module mux_l1_in_2_ $end +$var wire 1 /J in [0] $end +$var wire 1 >J in [1] $end +$var wire 1 \{ mem [0] $end +$var wire 1 ]{ mem [1] $end +$var wire 1 `{ mem_inv [0] $end +$var wire 1 a{ mem_inv [1] $end +$var wire 1 l{ out [0] $end + +$scope module scs8hd_muxinv2_1_0 $end +$var wire 1 l{ Z $end +$var wire 1 /J Q1 $end +$var wire 1 >J Q2 $end +$var wire 1 \{ S0 $end +$var wire 1 `{ S0B $end +$var wire 1 ]{ S1 $end +$var wire 1 a{ S1B $end +$var wire 1 "} Q1__bar $end +$var wire 1 #} Q2__bar $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mem_right_track_6 $end +$var wire 1 NH pReset [0] $end +$var wire 1 qJ prog_clk [0] $end +$var wire 1 uL ccff_head [0] $end +$var wire 1 wJ ccff_tail [0] $end +$var wire 1 sJ mem_out [0] $end +$var wire 1 tJ mem_out [1] $end +$var wire 1 uJ mem_out [2] $end +$var wire 1 vJ mem_out [3] $end + +$scope module sky130_fd_sc_hd__dfrtp_1_0_ $end +$var wire 1 sJ Q $end +$var wire 1 qJ CLK $end +$var wire 1 uL D $end +$var wire 1 NH RESET_B $end +$var supply1 1 $} VPWR $end +$var supply0 1 %} VGND $end +$var supply1 1 &} VPB $end +$var supply0 1 '} VNB $end + +$scope module base $end +$var wire 1 sJ Q $end +$var wire 1 qJ CLK $end +$var wire 1 uL D $end +$var wire 1 NH RESET_B $end +$var wire 1 (} buf_Q $end +$var wire 1 )} RESET $end +$upscope $end +$upscope $end + +$scope module sky130_fd_sc_hd__dfrtp_1_1_ $end +$var wire 1 tJ Q $end +$var wire 1 qJ CLK $end +$var wire 1 sJ D $end +$var wire 1 NH RESET_B $end +$var supply1 1 *} VPWR $end +$var supply0 1 +} VGND $end +$var supply1 1 ,} VPB $end +$var supply0 1 -} VNB $end + +$scope module base $end +$var wire 1 tJ Q $end +$var wire 1 qJ CLK $end +$var wire 1 sJ D $end +$var wire 1 NH RESET_B $end +$var wire 1 .} buf_Q $end +$var wire 1 /} RESET $end +$upscope $end +$upscope $end + +$scope module sky130_fd_sc_hd__dfrtp_1_2_ $end +$var wire 1 uJ Q $end +$var wire 1 qJ CLK $end +$var wire 1 tJ D $end +$var wire 1 NH RESET_B $end +$var supply1 1 0} VPWR $end +$var supply0 1 1} VGND $end +$var supply1 1 2} VPB $end +$var supply0 1 3} VNB $end + +$scope module base $end +$var wire 1 uJ Q $end +$var wire 1 qJ CLK $end +$var wire 1 tJ D $end +$var wire 1 NH RESET_B $end +$var wire 1 4} buf_Q $end +$var wire 1 5} RESET $end +$upscope $end +$upscope $end + +$scope module sky130_fd_sc_hd__dfrtp_1_3_ $end +$var wire 1 vJ Q $end +$var wire 1 qJ CLK $end +$var wire 1 uJ D $end +$var wire 1 NH RESET_B $end +$var supply1 1 6} VPWR $end +$var supply0 1 7} VGND $end +$var supply1 1 8} VPB $end +$var supply0 1 9} VNB $end + +$scope module base $end +$var wire 1 vJ Q $end +$var wire 1 qJ CLK $end +$var wire 1 uJ D $end +$var wire 1 NH RESET_B $end +$var wire 1 :} buf_Q $end +$var wire 1 ;} RESET $end +$upscope $end +$upscope $end + +$scope module FTB_101__100 $end +$var wire 1 wJ X $end +$var wire 1 vJ A $end +$var supply1 1 <} VPWR $end +$var supply0 1 =} VGND $end +$var supply1 1 >} VPB $end +$var supply0 1 ?} VNB $end + +$scope module base $end +$var wire 1 wJ X $end +$var wire 1 vJ A $end +$var wire 1 @} buf0_out_X $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mux_right_track_10 $end +$var wire 1 RH in [0] $end +$var wire 1 ]H in [1] $end +$var wire 1 hH in [2] $end +$var wire 1 6I in [3] $end +$var wire 1 8I in [4] $end +$var wire 1 :I in [5] $end +$var wire 1 ~ not0_out_Y $end +$upscope $end +$upscope $end + +$scope module U17 $end +$var wire 1 O} Y $end +$var wire 1 zL A $end +$var wire 1 *~ B $end +$var supply1 1 ?~ VPWR $end +$var supply0 1 @~ VGND $end +$var supply1 1 A~ VPB $end +$var supply0 1 B~ VNB $end + +$scope module base $end +$var wire 1 O} Y $end +$var wire 1 zL A $end +$var wire 1 *~ B $end +$var wire 1 C~ nand0_out_Y $end +$upscope $end +$upscope $end + +$scope module U18 $end +$var wire 1 J} Y $end +$var wire 1 *~ A $end +$var wire 1 zL B $end +$var supply1 1 D~ VPWR $end +$var supply0 1 E~ VGND $end +$var supply1 1 F~ VPB $end +$var supply0 1 G~ VNB $end + +$scope module base $end +$var wire 1 J} Y $end +$var wire 1 *~ A $end +$var wire 1 zL B $end +$var wire 1 H~ nor0_out_Y $end +$upscope $end +$upscope $end + +$scope module U19 $end +$var wire 1 *~ Y $end +$var wire 1 yL A $end +$var supply1 1 I~ VPWR $end +$var supply0 1 J~ VGND $end +$var supply1 1 K~ VPB $end +$var supply0 1 L~ VNB $end + +$scope module base $end +$var wire 1 *~ Y $end +$var wire 1 yL A $end +$var wire 1 M~ not0_out_Y $end +$upscope $end +$upscope $end + +$scope module U20 $end +$var wire 1 L} Y $end +$var wire 1 P} A $end +$var supply1 1 N~ VPWR $end +$var supply0 1 O~ VGND $end +$var supply1 1 P~ VPB $end +$var supply0 1 Q~ VNB $end + +$scope module base $end +$var wire 1 L} Y $end +$var wire 1 P} A $end +$var wire 1 R~ not0_out_Y $end +$upscope $end +$upscope $end + +$scope module U21 $end +$var wire 1 P} Y $end +$var wire 1 zL A $end +$var wire 1 yL B $end +$var supply1 1 S~ VPWR $end +$var supply0 1 T~ VGND $end +$var supply1 1 U~ VPB $end +$var supply0 1 V~ VNB $end + +$scope module base $end +$var wire 1 P} Y $end +$var wire 1 zL A $end +$var wire 1 yL B $end +$var wire 1 W~ nand0_out_Y $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mux_l1_in_0_ $end +$var wire 1 RH in [0] $end +$var wire 1 ]H in [1] $end +$var wire 1 hH in [2] $end +$var wire 1 6I in [3] $end +$var wire 1 A} mem [0] $end +$var wire 1 B} mem [1] $end +$var wire 1 C} mem [2] $end +$var wire 1 D} mem [3] $end +$var wire 1 E} mem_inv [0] $end +$var wire 1 F} mem_inv [1] $end +$var wire 1 G} mem_inv [2] $end +$var wire 1 H} mem_inv [3] $end +$var wire 1 Q} out [0] $end + +$scope module scs8hd_muxinv2_1_0 $end +$var wire 1 Q} Z $end +$var wire 1 RH Q1 $end +$var wire 1 ]H Q2 $end +$var wire 1 A} S0 $end +$var wire 1 E} S0B $end +$var wire 1 B} S1 $end +$var wire 1 F} S1B $end +$var wire 1 X~ Q1__bar $end +$var wire 1 Y~ Q2__bar $end +$upscope $end + +$scope module scs8hd_muxinv2_1_1 $end +$var wire 1 Q} Z $end +$var wire 1 hH Q1 $end +$var wire 1 6I Q2 $end +$var wire 1 C} S0 $end +$var wire 1 G} S0B $end +$var wire 1 D} S1 $end +$var wire 1 H} S1B $end +$var wire 1 Z~ Q1__bar $end +$var wire 1 [~ Q2__bar $end +$upscope $end +$upscope $end + +$scope module mux_l1_in_1_ $end +$var wire 1 8I in [0] $end +$var wire 1 :I in [1] $end +$var wire 1 !! VPWR $end +$var supply0 1 ?!! VGND $end +$var supply1 1 @!! VPB $end +$var supply0 1 A!! VNB $end + +$scope module base $end +$var wire 1 }~ Y $end +$var wire 1 {L A $end +$var wire 1 B!! not0_out_Y $end +$upscope $end +$upscope $end + +$scope module U20 $end +$var wire 1 g~ Y $end +$var wire 1 k~ A $end +$var supply1 1 C!! VPWR $end +$var supply0 1 D!! VGND $end +$var supply1 1 E!! VPB $end +$var supply0 1 F!! VNB $end + +$scope module base $end +$var wire 1 g~ Y $end +$var wire 1 k~ A $end +$var wire 1 G!! not0_out_Y $end +$upscope $end +$upscope $end + +$scope module U21 $end +$var wire 1 k~ Y $end +$var wire 1 |L A $end +$var wire 1 {L B $end +$var supply1 1 H!! VPWR $end +$var supply0 1 I!! VGND $end +$var supply1 1 J!! VPB $end +$var supply0 1 K!! VNB $end + +$scope module base $end +$var wire 1 k~ Y $end +$var wire 1 |L A $end +$var wire 1 {L B $end +$var wire 1 L!! nand0_out_Y $end +$upscope $end +$upscope $end +$upscope $end + +$scope module local_encoder2to4_1_ $end +$var wire 1 }L addr [0] $end +$var wire 1 ~L addr [1] $end +$var wire 1 l~ data [0] $end +$var wire 1 m~ data [1] $end +$var wire 1 n~ data [2] $end +$var wire 1 o~ data [3] $end +$var wire 1 p~ data_inv [0] $end +$var wire 1 q~ data_inv [1] $end +$var wire 1 r~ data_inv [2] $end +$var wire 1 s~ data_inv [3] $end +$var wire 1 M!! n9 $end + +$scope module U13 $end +$var wire 1 l~ Y $end +$var wire 1 ~L A $end +$var wire 1 }L B $end +$var supply1 1 N!! VPWR $end +$var supply0 1 O!! VGND $end +$var supply1 1 P!! VPB $end +$var supply0 1 Q!! VNB $end + +$scope module base $end +$var wire 1 l~ Y $end +$var wire 1 ~L A $end +$var wire 1 }L B $end +$var wire 1 R!! nor0_out_Y $end +$upscope $end +$upscope $end + +$scope module U14 $end +$var wire 1 q~ Y $end +$var wire 1 m~ A $end +$var supply1 1 S!! VPWR $end +$var supply0 1 T!! VGND $end +$var supply1 1 U!! VPB $end +$var supply0 1 V!! VNB $end + +$scope module base $end +$var wire 1 q~ Y $end +$var wire 1 m~ A $end +$var wire 1 W!! not0_out_Y $end +$upscope $end +$upscope $end + +$scope module U15 $end +$var wire 1 p~ Y $end +$var wire 1 l~ A $end +$var supply1 1 X!! VPWR $end +$var supply0 1 Y!! VGND $end +$var supply1 1 Z!! VPB $end +$var supply0 1 [!! VNB $end + +$scope module base $end +$var wire 1 p~ Y $end +$var wire 1 l~ A $end +$var wire 1 \!! not0_out_Y $end +$upscope $end +$upscope $end + +$scope module U16 $end +$var wire 1 n~ Y $end +$var wire 1 r~ A $end +$var supply1 1 ]!! VPWR $end +$var supply0 1 ^!! VGND $end +$var supply1 1 _!! VPB $end +$var supply0 1 `!! VNB $end + +$scope module base $end +$var wire 1 n~ Y $end +$var wire 1 r~ A $end +$var wire 1 a!! not0_out_Y $end +$upscope $end +$upscope $end + +$scope module U17 $end +$var wire 1 r~ Y $end +$var wire 1 ~L A $end +$var wire 1 M!! B $end +$var supply1 1 b!! VPWR $end +$var supply0 1 c!! VGND $end +$var supply1 1 d!! VPB $end +$var supply0 1 e!! VNB $end + +$scope module base $end +$var wire 1 r~ Y $end +$var wire 1 ~L A $end +$var wire 1 M!! B $end +$var wire 1 f!! nand0_out_Y $end +$upscope $end +$upscope $end + +$scope module U18 $end +$var wire 1 m~ Y $end +$var wire 1 M!! A $end +$var wire 1 ~L B $end +$var supply1 1 g!! VPWR $end +$var supply0 1 h!! VGND $end +$var supply1 1 i!! VPB $end +$var supply0 1 j!! VNB $end + +$scope module base $end +$var wire 1 m~ Y $end +$var wire 1 M!! A $end +$var wire 1 ~L B $end +$var wire 1 k!! nor0_out_Y $end +$upscope $end +$upscope $end + +$scope module U19 $end +$var wire 1 M!! Y $end +$var wire 1 }L A $end +$var supply1 1 l!! VPWR $end +$var supply0 1 m!! VGND $end +$var supply1 1 n!! VPB $end +$var supply0 1 o!! VNB $end + +$scope module base $end +$var wire 1 M!! Y $end +$var wire 1 }L A $end +$var wire 1 p!! not0_out_Y $end +$upscope $end +$upscope $end + +$scope module U20 $end +$var wire 1 o~ Y $end +$var wire 1 s~ A $end +$var supply1 1 q!! VPWR $end +$var supply0 1 r!! VGND $end +$var supply1 1 s!! VPB $end +$var supply0 1 t!! VNB $end + +$scope module base $end +$var wire 1 o~ Y $end +$var wire 1 s~ A $end +$var wire 1 u!! not0_out_Y $end +$upscope $end +$upscope $end + +$scope module U21 $end +$var wire 1 s~ Y $end +$var wire 1 ~L A $end +$var wire 1 }L B $end +$var supply1 1 v!! VPWR $end +$var supply0 1 w!! VGND $end +$var supply1 1 x!! VPB $end +$var supply0 1 y!! VNB $end + +$scope module base $end +$var wire 1 s~ Y $end +$var wire 1 ~L A $end +$var wire 1 }L B $end +$var wire 1 z!! nand0_out_Y $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mux_l1_in_0_ $end +$var wire 1 WH in [0] $end +$var wire 1 bH in [1] $end +$var wire 1 MJ in [2] $end +$var wire 1 \J in [3] $end +$var wire 1 d~ mem [0] $end +$var wire 1 e~ mem [1] $end +$var wire 1 f~ mem [2] $end +$var wire 1 g~ mem [3] $end +$var wire 1 h~ mem_inv [0] $end +$var wire 1 i~ mem_inv [1] $end +$var wire 1 j~ mem_inv [2] $end +$var wire 1 k~ mem_inv [3] $end +$var wire 1 t~ out [0] $end + +$scope module scs8hd_muxinv2_1_0 $end +$var wire 1 t~ Z $end +$var wire 1 WH Q1 $end +$var wire 1 bH Q2 $end +$var wire 1 d~ S0 $end +$var wire 1 h~ S0B $end +$var wire 1 e~ S1 $end +$var wire 1 i~ S1B $end +$var wire 1 {!! Q1__bar $end +$var wire 1 |!! Q2__bar $end +$upscope $end + +$scope module scs8hd_muxinv2_1_1 $end +$var wire 1 t~ Z $end +$var wire 1 MJ Q1 $end +$var wire 1 \J Q2 $end +$var wire 1 f~ S0 $end +$var wire 1 j~ S0B $end +$var wire 1 g~ S1 $end +$var wire 1 k~ S1B $end +$var wire 1 }!! Q1__bar $end +$var wire 1 ~!! Q2__bar $end +$upscope $end +$upscope $end + +$scope module mux_l1_in_1_ $end +$var wire 1 \I in [0] $end +$var wire 1 ^I in [1] $end +$var wire 1 `I in [2] $end +$var wire 1 bI in [3] $end +$var wire 1 d~ mem [0] $end +$var wire 1 e~ mem [1] $end +$var wire 1 f~ mem [2] $end +$var wire 1 g~ mem [3] $end +$var wire 1 h~ mem_inv [0] $end +$var wire 1 i~ mem_inv [1] $end +$var wire 1 j~ mem_inv [2] $end +$var wire 1 k~ mem_inv [3] $end +$var wire 1 u~ out [0] $end + +$scope module scs8hd_muxinv2_1_0 $end +$var wire 1 u~ Z $end +$var wire 1 \I Q1 $end +$var wire 1 ^I Q2 $end +$var wire 1 d~ S0 $end +$var wire 1 h~ S0B $end +$var wire 1 e~ S1 $end +$var wire 1 i~ S1B $end +$var wire 1 !"! Q1__bar $end +$var wire 1 ""! Q2__bar $end +$upscope $end + +$scope module scs8hd_muxinv2_1_1 $end +$var wire 1 u~ Z $end +$var wire 1 `I Q1 $end +$var wire 1 bI Q2 $end +$var wire 1 f~ S0 $end +$var wire 1 j~ S0B $end +$var wire 1 g~ S1 $end +$var wire 1 k~ S1B $end +$var wire 1 #"! Q1__bar $end +$var wire 1 $"! Q2__bar $end +$upscope $end +$upscope $end + +$scope module mux_l2_in_0_ $end +$var wire 1 t~ in [0] $end +$var wire 1 u~ in [1] $end +$var wire 1 dI in [2] $end +$var wire 1 w~ in [3] $end +$var wire 1 l~ mem [0] $end +$var wire 1 m~ mem [1] $end +$var wire 1 n~ mem [2] $end +$var wire 1 o~ mem [3] $end +$var wire 1 p~ mem_inv [0] $end +$var wire 1 q~ mem_inv [1] $end +$var wire 1 r~ mem_inv [2] $end +$var wire 1 s~ mem_inv [3] $end +$var wire 1 v~ out [0] $end +$var wire 1 GM p0 $end + +$scope module scs8hd_muxinv2_1_0 $end +$var wire 1 v~ Z $end +$var wire 1 t~ Q1 $end +$var wire 1 u~ Q2 $end +$var wire 1 l~ S0 $end +$var wire 1 p~ S0B $end +$var wire 1 m~ S1 $end +$var wire 1 q~ S1B $end +$var wire 1 %"! Q1__bar $end +$var wire 1 &"! Q2__bar $end +$upscope $end + +$scope module scs8hd_muxinv2_1_1 $end +$var wire 1 v~ Z $end +$var wire 1 dI Q1 $end +$var wire 1 GM Q2 $end +$var wire 1 n~ S0 $end +$var wire 1 r~ S0B $end +$var wire 1 o~ S1 $end +$var wire 1 s~ S1B $end +$var wire 1 '"! Q1__bar $end +$var wire 1 ("! Q2__bar $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mux_left_track_11 $end +$var wire 1 VH in [0] $end +$var wire 1 aH in [1] $end +$var wire 1 lH in [2] $end +$var wire 1 OJ in [3] $end +$var wire 1 ]J in [4] $end +$var wire 1 ]I in [5] $end +$var wire 1 _I in [6] $end +$var wire 1 aI in [7] $end +$var wire 1 cI in [8] $end +$var wire 1 !M sram [0] $end +$var wire 1 "M sram [1] $end +$var wire 1 #M sram [2] $end +$var wire 1 $M sram [3] $end +$var wire 1 nN sram_inv [0] $end +$var wire 1 oN sram_inv [1] $end +$var wire 1 pN sram_inv [2] $end +$var wire 1 qN sram_inv [3] $end +$var wire 1 IJ out [0] $end +$var wire 1 BM p0 $end +$var wire 1 )"! local_encoder2to4_0_data [0] $end +$var wire 1 *"! local_encoder2to4_0_data [1] $end +$var wire 1 +"! local_encoder2to4_0_data [2] $end +$var wire 1 ,"! local_encoder2to4_0_data [3] $end +$var wire 1 -"! local_encoder2to4_0_data_inv [0] $end +$var wire 1 ."! local_encoder2to4_0_data_inv [1] $end +$var wire 1 /"! local_encoder2to4_0_data_inv [2] $end +$var wire 1 0"! local_encoder2to4_0_data_inv [3] $end +$var wire 1 1"! local_encoder2to4_1_data [0] $end +$var wire 1 2"! local_encoder2to4_1_data [1] $end +$var wire 1 3"! local_encoder2to4_1_data [2] $end +$var wire 1 4"! local_encoder2to4_1_data [3] $end +$var wire 1 5"! local_encoder2to4_1_data_inv [0] $end +$var wire 1 6"! local_encoder2to4_1_data_inv [1] $end +$var wire 1 7"! local_encoder2to4_1_data_inv [2] $end +$var wire 1 8"! local_encoder2to4_1_data_inv [3] $end +$var wire 1 9"! mux_2level_tapbuf_basis_input4_mem4_0_out [0] $end +$var wire 1 :"! mux_2level_tapbuf_basis_input4_mem4_1_out [0] $end +$var wire 1 ;"! mux_2level_tapbuf_basis_input4_mem4_2_out [0] $end +$var wire 1 <"! SYNOPSYS_UNCONNECTED_1 $end + +$scope module sky130_fd_sc_hd__buf_4_0_ $end +$var wire 1 IJ X $end +$var wire 1 ;"! A $end +$var supply1 1 ="! VPWR $end +$var supply0 1 >"! VGND $end +$var supply1 1 ?"! VPB $end +$var supply0 1 @"! VNB $end + +$scope module base $end +$var wire 1 IJ X $end +$var wire 1 ;"! A $end +$var wire 1 A"! buf0_out_X $end +$upscope $end +$upscope $end + +$scope module local_encoder2to4_0_ $end +$var wire 1 !M addr [0] $end +$var wire 1 "M addr [1] $end +$var wire 1 )"! data [0] $end +$var wire 1 *"! data [1] $end +$var wire 1 +"! data [2] $end +$var wire 1 ,"! data [3] $end +$var wire 1 -"! data_inv [0] $end +$var wire 1 ."! data_inv [1] $end +$var wire 1 /"! data_inv [2] $end +$var wire 1 0"! data_inv [3] $end +$var wire 1 B"! n9 $end + +$scope module U13 $end +$var wire 1 )"! Y $end +$var wire 1 "M A $end +$var wire 1 !M B $end +$var supply1 1 C"! VPWR $end +$var supply0 1 D"! VGND $end +$var supply1 1 E"! VPB $end +$var supply0 1 F"! VNB $end + +$scope module base $end +$var wire 1 )"! Y $end +$var wire 1 "M A $end +$var wire 1 !M B $end +$var wire 1 G"! nor0_out_Y $end +$upscope $end +$upscope $end + +$scope module U14 $end +$var wire 1 ."! Y $end +$var wire 1 *"! A $end +$var supply1 1 H"! VPWR $end +$var supply0 1 I"! VGND $end +$var supply1 1 J"! VPB $end +$var supply0 1 K"! VNB $end + +$scope module base $end +$var wire 1 ."! Y $end +$var wire 1 *"! A $end +$var wire 1 L"! not0_out_Y $end +$upscope $end +$upscope $end + +$scope module U15 $end +$var wire 1 -"! Y $end +$var wire 1 )"! A $end +$var supply1 1 M"! VPWR $end +$var supply0 1 N"! VGND $end +$var supply1 1 O"! VPB $end +$var supply0 1 P"! VNB $end + +$scope module base $end +$var wire 1 -"! Y $end +$var wire 1 )"! A $end +$var wire 1 Q"! not0_out_Y $end +$upscope $end +$upscope $end + +$scope module U16 $end +$var wire 1 +"! Y $end +$var wire 1 /"! A $end +$var supply1 1 R"! VPWR $end +$var supply0 1 S"! VGND $end +$var supply1 1 T"! VPB $end +$var supply0 1 U"! VNB $end + +$scope module base $end +$var wire 1 +"! Y $end +$var wire 1 /"! A $end +$var wire 1 V"! not0_out_Y $end +$upscope $end +$upscope $end + +$scope module U17 $end +$var wire 1 /"! Y $end +$var wire 1 "M A $end +$var wire 1 B"! B $end +$var supply1 1 W"! VPWR $end +$var supply0 1 X"! VGND $end +$var supply1 1 Y"! VPB $end +$var supply0 1 Z"! VNB $end + +$scope module base $end +$var wire 1 /"! Y $end +$var wire 1 "M A $end +$var wire 1 B"! B $end +$var wire 1 ["! nand0_out_Y $end +$upscope $end +$upscope $end + +$scope module U18 $end +$var wire 1 *"! Y $end +$var wire 1 B"! A $end +$var wire 1 "M B $end +$var supply1 1 \"! VPWR $end +$var supply0 1 ]"! VGND $end +$var supply1 1 ^"! VPB $end +$var supply0 1 _"! VNB $end + +$scope module base $end +$var wire 1 *"! Y $end +$var wire 1 B"! A $end +$var wire 1 "M B $end +$var wire 1 `"! nor0_out_Y $end +$upscope $end +$upscope $end + +$scope module U19 $end +$var wire 1 B"! Y $end +$var wire 1 !M A $end +$var supply1 1 a"! VPWR $end +$var supply0 1 b"! VGND $end +$var supply1 1 c"! VPB $end +$var supply0 1 d"! VNB $end + +$scope module base $end +$var wire 1 B"! Y $end +$var wire 1 !M A $end +$var wire 1 e"! not0_out_Y $end +$upscope $end +$upscope $end + +$scope module U20 $end +$var wire 1 ,"! Y $end +$var wire 1 0"! A $end +$var supply1 1 f"! VPWR $end +$var supply0 1 g"! VGND $end +$var supply1 1 h"! VPB $end +$var supply0 1 i"! VNB $end + +$scope module base $end +$var wire 1 ,"! Y $end +$var wire 1 0"! A $end +$var wire 1 j"! not0_out_Y $end +$upscope $end +$upscope $end + +$scope module U21 $end +$var wire 1 0"! Y $end +$var wire 1 "M A $end +$var wire 1 !M B $end +$var supply1 1 k"! VPWR $end +$var supply0 1 l"! VGND $end +$var supply1 1 m"! VPB $end +$var supply0 1 n"! VNB $end + +$scope module base $end +$var wire 1 0"! Y $end +$var wire 1 "M A $end +$var wire 1 !M B $end +$var wire 1 o"! nand0_out_Y $end +$upscope $end +$upscope $end +$upscope $end + +$scope module local_encoder2to4_1_ $end +$var wire 1 #M addr [0] $end +$var wire 1 $M addr [1] $end +$var wire 1 1"! data [0] $end +$var wire 1 2"! data [1] $end +$var wire 1 3"! data [2] $end +$var wire 1 4"! data [3] $end +$var wire 1 5"! data_inv [0] $end +$var wire 1 6"! data_inv [1] $end +$var wire 1 7"! data_inv [2] $end +$var wire 1 8"! data_inv [3] $end +$var wire 1 p"! n9 $end + +$scope module U13 $end +$var wire 1 1"! Y $end +$var wire 1 $M A $end +$var wire 1 #M B $end +$var supply1 1 q"! VPWR $end +$var supply0 1 r"! VGND $end +$var supply1 1 s"! VPB $end +$var supply0 1 t"! VNB $end + +$scope module base $end +$var wire 1 1"! Y $end +$var wire 1 $M A $end +$var wire 1 #M B $end +$var wire 1 u"! nor0_out_Y $end +$upscope $end +$upscope $end + +$scope module U14 $end +$var wire 1 6"! Y $end +$var wire 1 2"! A $end +$var supply1 1 v"! VPWR $end +$var supply0 1 w"! VGND $end +$var supply1 1 x"! VPB $end +$var supply0 1 y"! VNB $end + +$scope module base $end +$var wire 1 6"! Y $end +$var wire 1 2"! A $end +$var wire 1 z"! not0_out_Y $end +$upscope $end +$upscope $end + +$scope module U15 $end +$var wire 1 5"! Y $end +$var wire 1 1"! A $end +$var supply1 1 {"! VPWR $end +$var supply0 1 |"! VGND $end +$var supply1 1 }"! VPB $end +$var supply0 1 ~"! VNB $end + +$scope module base $end +$var wire 1 5"! Y $end +$var wire 1 1"! A $end +$var wire 1 !#! not0_out_Y $end +$upscope $end +$upscope $end + +$scope module U16 $end +$var wire 1 3"! Y $end +$var wire 1 7"! A $end +$var supply1 1 "#! VPWR $end +$var supply0 1 ##! VGND $end +$var supply1 1 $#! VPB $end +$var supply0 1 %#! VNB $end + +$scope module base $end +$var wire 1 3"! Y $end +$var wire 1 7"! A $end +$var wire 1 &#! not0_out_Y $end +$upscope $end +$upscope $end + +$scope module U17 $end +$var wire 1 7"! Y $end +$var wire 1 $M A $end +$var wire 1 p"! B $end +$var supply1 1 '#! VPWR $end +$var supply0 1 (#! VGND $end +$var supply1 1 )#! VPB $end +$var supply0 1 *#! VNB $end + +$scope module base $end +$var wire 1 7"! Y $end +$var wire 1 $M A $end +$var wire 1 p"! B $end +$var wire 1 +#! nand0_out_Y $end +$upscope $end +$upscope $end + +$scope module U18 $end +$var wire 1 2"! Y $end +$var wire 1 p"! A $end +$var wire 1 $M B $end +$var supply1 1 ,#! VPWR $end +$var supply0 1 -#! VGND $end +$var supply1 1 .#! VPB $end +$var supply0 1 /#! VNB $end + +$scope module base $end +$var wire 1 2"! Y $end +$var wire 1 p"! A $end +$var wire 1 $M B $end +$var wire 1 0#! nor0_out_Y $end +$upscope $end +$upscope $end + +$scope module U19 $end +$var wire 1 p"! Y $end +$var wire 1 #M A $end +$var supply1 1 1#! VPWR $end +$var supply0 1 2#! VGND $end +$var supply1 1 3#! VPB $end +$var supply0 1 4#! VNB $end + +$scope module base $end +$var wire 1 p"! Y $end +$var wire 1 #M A $end +$var wire 1 5#! not0_out_Y $end +$upscope $end +$upscope $end + +$scope module U20 $end +$var wire 1 4"! Y $end +$var wire 1 8"! A $end +$var supply1 1 6#! VPWR $end +$var supply0 1 7#! VGND $end +$var supply1 1 8#! VPB $end +$var supply0 1 9#! VNB $end + +$scope module base $end +$var wire 1 4"! Y $end +$var wire 1 8"! A $end +$var wire 1 :#! not0_out_Y $end +$upscope $end +$upscope $end + +$scope module U21 $end +$var wire 1 8"! Y $end +$var wire 1 $M A $end +$var wire 1 #M B $end +$var supply1 1 ;#! VPWR $end +$var supply0 1 <#! VGND $end +$var supply1 1 =#! VPB $end +$var supply0 1 >#! VNB $end + +$scope module base $end +$var wire 1 8"! Y $end +$var wire 1 $M A $end +$var wire 1 #M B $end +$var wire 1 ?#! nand0_out_Y $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mux_l1_in_0_ $end +$var wire 1 VH in [0] $end +$var wire 1 aH in [1] $end +$var wire 1 lH in [2] $end +$var wire 1 OJ in [3] $end +$var wire 1 )"! mem [0] $end +$var wire 1 *"! mem [1] $end +$var wire 1 +"! mem [2] $end +$var wire 1 ,"! mem [3] $end +$var wire 1 -"! mem_inv [0] $end +$var wire 1 ."! mem_inv [1] $end +$var wire 1 /"! mem_inv [2] $end +$var wire 1 0"! mem_inv [3] $end +$var wire 1 9"! out [0] $end + +$scope module scs8hd_muxinv2_1_0 $end +$var wire 1 9"! Z $end +$var wire 1 VH Q1 $end +$var wire 1 aH Q2 $end +$var wire 1 )"! S0 $end +$var wire 1 -"! S0B $end +$var wire 1 *"! S1 $end +$var wire 1 ."! S1B $end +$var wire 1 @#! Q1__bar $end +$var wire 1 A#! Q2__bar $end +$upscope $end + +$scope module scs8hd_muxinv2_1_1 $end +$var wire 1 9"! Z $end +$var wire 1 lH Q1 $end +$var wire 1 OJ Q2 $end +$var wire 1 +"! S0 $end +$var wire 1 /"! S0B $end +$var wire 1 ,"! S1 $end +$var wire 1 0"! S1B $end +$var wire 1 B#! Q1__bar $end +$var wire 1 C#! Q2__bar $end +$upscope $end +$upscope $end + +$scope module mux_l1_in_1_ $end +$var wire 1 ]J in [0] $end +$var wire 1 ]I in [1] $end +$var wire 1 _I in [2] $end +$var wire 1 aI in [3] $end +$var wire 1 )"! mem [0] $end +$var wire 1 *"! mem [1] $end +$var wire 1 +"! mem [2] $end +$var wire 1 ,"! mem [3] $end +$var wire 1 -"! mem_inv [0] $end +$var wire 1 ."! mem_inv [1] $end +$var wire 1 /"! mem_inv [2] $end +$var wire 1 0"! mem_inv [3] $end +$var wire 1 :"! out [0] $end + +$scope module scs8hd_muxinv2_1_0 $end +$var wire 1 :"! Z $end +$var wire 1 ]J Q1 $end +$var wire 1 ]I Q2 $end +$var wire 1 )"! S0 $end +$var wire 1 -"! S0B $end +$var wire 1 *"! S1 $end +$var wire 1 ."! S1B $end +$var wire 1 D#! Q1__bar $end +$var wire 1 E#! Q2__bar $end +$upscope $end + +$scope module scs8hd_muxinv2_1_1 $end +$var wire 1 :"! Z $end +$var wire 1 _I Q1 $end +$var wire 1 aI Q2 $end +$var wire 1 +"! S0 $end +$var wire 1 /"! S0B $end +$var wire 1 ,"! S1 $end +$var wire 1 0"! S1B $end +$var wire 1 F#! Q1__bar $end +$var wire 1 G#! Q2__bar $end +$upscope $end +$upscope $end + +$scope module mux_l2_in_0_ $end +$var wire 1 9"! in [0] $end +$var wire 1 :"! in [1] $end +$var wire 1 cI in [2] $end +$var wire 1 <"! in [3] $end +$var wire 1 1"! mem [0] $end +$var wire 1 2"! mem [1] $end +$var wire 1 3"! mem [2] $end +$var wire 1 4"! mem [3] $end +$var wire 1 5"! mem_inv [0] $end +$var wire 1 6"! mem_inv [1] $end +$var wire 1 7"! mem_inv [2] $end +$var wire 1 8"! mem_inv [3] $end +$var wire 1 ;"! out [0] $end +$var wire 1 BM p0 $end + +$scope module scs8hd_muxinv2_1_0 $end +$var wire 1 ;"! Z $end +$var wire 1 9"! Q1 $end +$var wire 1 :"! Q2 $end +$var wire 1 1"! S0 $end +$var wire 1 5"! S0B $end +$var wire 1 2"! S1 $end +$var wire 1 6"! S1B $end +$var wire 1 H#! Q1__bar $end +$var wire 1 I#! Q2__bar $end +$upscope $end + +$scope module scs8hd_muxinv2_1_1 $end +$var wire 1 ;"! Z $end +$var wire 1 cI Q1 $end +$var wire 1 BM Q2 $end +$var wire 1 3"! S0 $end +$var wire 1 7"! S0B $end +$var wire 1 4"! S1 $end +$var wire 1 8"! S1B $end +$var wire 1 J#! Q1__bar $end +$var wire 1 K#! Q2__bar $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mem_right_track_10 $end +$var wire 1 NH pReset [0] $end +$var wire 1 qJ prog_clk [0] $end +$var wire 1 wJ ccff_head [0] $end +$var wire 1 %M ccff_tail [0] $end +$var wire 1 wL mem_out [0] $end +$var wire 1 xL mem_out [1] $end +$var wire 1 yL mem_out [2] $end +$var wire 1 zL mem_out [3] $end + +$scope module sky130_fd_sc_hd__dfrtp_1_0_ $end +$var wire 1 wL Q $end +$var wire 1 qJ CLK $end +$var wire 1 wJ D $end +$var wire 1 NH RESET_B $end +$var supply1 1 L#! VPWR $end +$var supply0 1 M#! VGND $end +$var supply1 1 N#! VPB $end +$var supply0 1 O#! VNB $end + +$scope module base $end +$var wire 1 wL Q $end +$var wire 1 qJ CLK $end +$var wire 1 wJ D $end +$var wire 1 NH RESET_B $end +$var wire 1 P#! buf_Q $end +$var wire 1 Q#! RESET $end +$upscope $end +$upscope $end + +$scope module sky130_fd_sc_hd__dfrtp_1_1_ $end +$var wire 1 xL Q $end +$var wire 1 qJ CLK $end +$var wire 1 wL D $end +$var wire 1 NH RESET_B $end +$var supply1 1 R#! VPWR $end +$var supply0 1 S#! VGND $end +$var supply1 1 T#! VPB $end +$var supply0 1 U#! VNB $end + +$scope module base $end +$var wire 1 xL Q $end +$var wire 1 qJ CLK $end +$var wire 1 wL D $end +$var wire 1 NH RESET_B $end +$var wire 1 V#! buf_Q $end +$var wire 1 W#! RESET $end +$upscope $end +$upscope $end + +$scope module sky130_fd_sc_hd__dfrtp_1_2_ $end +$var wire 1 yL Q $end +$var wire 1 qJ CLK $end +$var wire 1 xL D $end +$var wire 1 NH RESET_B $end +$var supply1 1 X#! VPWR $end +$var supply0 1 Y#! VGND $end +$var supply1 1 Z#! VPB $end +$var supply0 1 [#! VNB $end + +$scope module base $end +$var wire 1 yL Q $end +$var wire 1 qJ CLK $end +$var wire 1 xL D $end +$var wire 1 NH RESET_B $end +$var wire 1 \#! buf_Q $end +$var wire 1 ]#! RESET $end +$upscope $end +$upscope $end + +$scope module sky130_fd_sc_hd__dfrtp_1_3_ $end +$var wire 1 zL Q $end +$var wire 1 qJ CLK $end +$var wire 1 yL D $end +$var wire 1 NH RESET_B $end +$var supply1 1 ^#! VPWR $end +$var supply0 1 _#! VGND $end +$var supply1 1 `#! VPB $end +$var supply0 1 a#! VNB $end + +$scope module base $end +$var wire 1 zL Q $end +$var wire 1 qJ CLK $end +$var wire 1 yL D $end +$var wire 1 NH RESET_B $end +$var wire 1 b#! buf_Q $end +$var wire 1 c#! RESET $end +$upscope $end +$upscope $end + +$scope module FTB_102__101 $end +$var wire 1 %M X $end +$var wire 1 zL A $end +$var supply1 1 d#! VPWR $end +$var supply0 1 e#! VGND $end +$var supply1 1 f#! VPB $end +$var supply0 1 g#! VNB $end + +$scope module base $end +$var wire 1 %M X $end +$var wire 1 zL A $end +$var wire 1 h#! buf0_out_X $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mem_left_track_7 $end +$var wire 1 NH pReset [0] $end +$var wire 1 qJ prog_clk [0] $end +$var wire 1 dL ccff_head [0] $end +$var wire 1 &M ccff_tail [0] $end +$var wire 1 {L mem_out [0] $end +$var wire 1 |L mem_out [1] $end +$var wire 1 }L mem_out [2] $end +$var wire 1 ~L mem_out [3] $end + +$scope module sky130_fd_sc_hd__dfrtp_1_0_ $end +$var wire 1 {L Q $end +$var wire 1 qJ CLK $end +$var wire 1 dL D $end +$var wire 1 NH RESET_B $end +$var supply1 1 i#! VPWR $end +$var supply0 1 j#! VGND $end +$var supply1 1 k#! VPB $end +$var supply0 1 l#! VNB $end + +$scope module base $end +$var wire 1 {L Q $end +$var wire 1 qJ CLK $end +$var wire 1 dL D $end +$var wire 1 NH RESET_B $end +$var wire 1 m#! buf_Q $end +$var wire 1 n#! RESET $end +$upscope $end +$upscope $end + +$scope module sky130_fd_sc_hd__dfrtp_1_1_ $end +$var wire 1 |L Q $end +$var wire 1 qJ CLK $end +$var wire 1 {L D $end +$var wire 1 NH RESET_B $end +$var supply1 1 o#! VPWR $end +$var supply0 1 p#! VGND $end +$var supply1 1 q#! VPB $end +$var supply0 1 r#! VNB $end + +$scope module base $end +$var wire 1 |L Q $end +$var wire 1 qJ CLK $end +$var wire 1 {L D $end +$var wire 1 NH RESET_B $end +$var wire 1 s#! buf_Q $end +$var wire 1 t#! RESET $end +$upscope $end +$upscope $end + +$scope module sky130_fd_sc_hd__dfrtp_1_2_ $end +$var wire 1 }L Q $end +$var wire 1 qJ CLK $end +$var wire 1 |L D $end +$var wire 1 NH RESET_B $end +$var supply1 1 u#! VPWR $end +$var supply0 1 v#! VGND $end +$var supply1 1 w#! VPB $end +$var supply0 1 x#! VNB $end + +$scope module base $end +$var wire 1 }L Q $end +$var wire 1 qJ CLK $end +$var wire 1 |L D $end +$var wire 1 NH RESET_B $end +$var wire 1 y#! buf_Q $end +$var wire 1 z#! RESET $end +$upscope $end +$upscope $end + +$scope module sky130_fd_sc_hd__dfrtp_1_3_ $end +$var wire 1 ~L Q $end +$var wire 1 qJ CLK $end +$var wire 1 }L D $end +$var wire 1 NH RESET_B $end +$var supply1 1 {#! VPWR $end +$var supply0 1 |#! VGND $end +$var supply1 1 }#! VPB $end +$var supply0 1 ~#! VNB $end + +$scope module base $end +$var wire 1 ~L Q $end +$var wire 1 qJ CLK $end +$var wire 1 }L D $end +$var wire 1 NH RESET_B $end +$var wire 1 !$! buf_Q $end +$var wire 1 "$! RESET $end +$upscope $end +$upscope $end + +$scope module FTB_103__102 $end +$var wire 1 &M X $end +$var wire 1 ~L A $end +$var supply1 1 #$! VPWR $end +$var supply0 1 $$! VGND $end +$var supply1 1 %$! VPB $end +$var supply0 1 &$! VNB $end + +$scope module base $end +$var wire 1 &M X $end +$var wire 1 ~L A $end +$var wire 1 '$! buf0_out_X $end +$upscope $end +$upscope $end +$upscope $end + +$scope module mem_left_track_11 $end +$var wire 1 NH pReset [0] $end +$var wire 1 qJ prog_clk [0] $end +$var wire 1 &M ccff_head [0] $end +$var wire 1 'M ccff_tail [0] $end +$var wire 1 !M mem_out [0] $end +$var wire 1 "M mem_out [1] $end +$var wire 1 #M mem_out [2] $end +$var wire 1 $M mem_out [3] $end + +$scope module sky130_fd_sc_hd__dfrtp_1_0_ $end +$var wire 1 !M Q $end +$var wire 1 qJ CLK $end +$var wire 1 &M D $end +$var wire 1 NH RESET_B $end +$var supply1 1 ($! VPWR $end +$var supply0 1 )$! VGND $end +$var supply1 1 *$! VPB $end +$var supply0 1 +$! VNB $end + +$scope module base $end +$var wire 1 !M Q $end +$var wire 1 qJ CLK $end +$var wire 1 &M D $end +$var wire 1 NH RESET_B $end +$var wire 1 ,$! buf_Q $end +$var wire 1 -$! RESET $end +$upscope $end +$upscope $end + +$scope module sky130_fd_sc_hd__dfrtp_1_1_ $end +$var wire 1 "M Q $end +$var wire 1 qJ CLK $end +$var wire 1 !M D $end +$var wire 1 NH RESET_B $end +$var supply1 1 .$! VPWR $end +$var supply0 1 /$! VGND $end +$var supply1 1 0$! VPB $end +$var supply0 1 1$! VNB $end + +$scope module base $end +$var wire 1 "M Q $end +$var wire 1 qJ CLK $end +$var wire 1 !M D $end +$var wire 1 NH RESET_B $end +$var wire 1 2$! buf_Q $end +$var wire 1 3$! RESET $end +$upscope $end +$upscope $end + +$scope module sky130_fd_sc_hd__dfrtp_1_2_ $end +$var wire 1 #M Q $end +$var wire 1 qJ CLK $end +$var wire 1 "M D $end +$var wire 1 NH RESET_B $end +$var supply1 1 4$! VPWR $end +$var supply0 1 5$! VGND $end +$var supply1 1 6$! VPB $end +$var supply0 1 7$! VNB $end + +$scope module base $end +$var wire 1 #M Q $end +$var wire 1 qJ CLK $end +$var wire 1 "M D $end +$var wire 1 NH RESET_B $end +$var wire 1 8$! buf_Q $end +$var wire 1 9$! RESET $end +$upscope $end +$upscope $end + +$scope module sky130_fd_sc_hd__dfrtp_1_3_ $end +$var wire 1 $M Q $end +$var wire 1 qJ CLK $end +$var wire 1 #M D $end +$var wire 1 NH RESET_B $end +$var supply1 1 :$! VPWR $end +$var supply0 1 ;$! VGND $end +$var supply1 1 <$! VPB $end +$var supply0 1 =$! VNB $end + +$scope module base $end +$var wire 1 $M Q $end +$var wire 1 qJ CLK $end +$var wire 1 #M D $end +$var wire 1 NH RESET_B $end +$var wire 1 >$! buf_Q $end +$var wire 1 ?$! RESET $end +$upscope $end +$upscope $end + +$scope module FTB_104__103 $end +$var wire 1 'M X $end +$var wire 1 $M A $end +$var supply1 1 @$! VPWR $end +$var supply0 1 A$! VGND $end +$var supply1 1 B$! VPB $end +$var supply0 1 C$! VNB $end + +$scope module base $end +$var wire 1 'M X $end +$var wire 1 $M A $end +$var wire 1 D$! buf0_out_X $end +$upscope $end +$upscope $end +$upscope $end + +$scope module optlc_209 $end +$var wire 1 BM HI $end +$var wire 1 rN LO $end +$var supply1 1 E$! VPWR $end +$var supply0 1 F$! VGND $end +$var supply1 1 G$! VPB $end +$var supply0 1 H$! VNB $end + +$scope module base $end +$var wire 1 BM HI $end +$var wire 1 rN LO $end +$upscope $end +$upscope $end + +$scope module pReset_FTB00 $end +$var wire 1 NH X $end +$var wire 1 gJ A $end +$var supply1 1 I$! VPWR $end +$var supply0 1 J$! VGND $end +$var supply1 1 K$! VPB $end +$var supply0 1 L$! VNB $end + +$scope module base $end +$var wire 1 NH X $end +$var wire 1 gJ A $end +$var wire 1 M$! buf0_out_X $end +$upscope $end +$upscope $end + +$scope module pReset_N_FTB01 $end +$var wire 1 sN X $end +$var wire 1 gJ A $end +$var supply1 1 N$! VPWR $end +$var supply0 1 O$! VGND $end +$var supply1 1 P$! VPB $end +$var supply0 1 Q$! VNB $end + +$scope module base $end +$var wire 1 sN X $end +$var wire 1 gJ A $end +$var wire 1 R$! buf0_out_X $end +$upscope $end +$upscope $end + +$scope module pReset_W_FTB01 $end +$var wire 1 jJ X $end +$var wire 1 gJ A $end +$var supply1 1 S$! VPWR $end +$var supply0 1 T$! VGND $end +$var supply1 1 U$! VPB $end +$var supply0 1 V$! VNB $end + +$scope module base $end +$var wire 1 jJ X $end +$var wire 1 gJ A $end +$var wire 1 W$! buf0_out_X $end +$upscope $end +$upscope $end + +$scope module pReset_E_FTB01 $end +$var wire 1 tN X $end +$var wire 1 gJ A $end +$var supply1 1 X$! VPWR $end +$var supply0 1 Y$! VGND $end +$var supply1 1 Z$! VPB $end +$var supply0 1 [$! VNB $end + +$scope module base $end +$var wire 1 tN X $end +$var wire 1 gJ A $end +$var wire 1 \$! buf0_out_X $end +$upscope $end +$upscope $end + +$scope module optlc_211 $end +$var wire 1 aM HI $end +$var wire 1 uN LO $end +$var supply1 1 ]$! VPWR $end +$var supply0 1 ^$! VGND $end +$var supply1 1 _$! VPB $end +$var supply0 1 `$! VNB $end + +$scope module base $end +$var wire 1 aM HI $end +$var wire 1 uN LO $end +$upscope $end +$upscope $end + +$scope module prog_clk_0_FTB00 $end +$var wire 1 qJ X $end +$var wire 1 mJ A $end +$var supply1 1 a$! VPWR $end +$var supply0 1 b$! VGND $end +$var supply1 1 c$! VPB $end +$var supply0 1 d$! VNB $end + +$scope module base $end +$var wire 1 qJ X $end +$var wire 1 mJ A $end +$var wire 1 e$! buf0_out_X $end +$upscope $end +$upscope $end + +$scope module prog_clk_3_N_FTB01 $end +$var wire 1 vN X $end +$var wire 1 ! A $end +$var supply1 1 f$! VPWR $end +$var supply0 1 g$! VGND $end +$var supply1 1 h$! VPB $end +$var supply0 1 i$! VNB $end + +$scope module base $end +$var wire 1 vN X $end +$var wire 1 ! A $end +$var wire 1 j$! buf0_out_X $end +$upscope $end +$upscope $end + +$scope module clk_3_N_FTB01 $end +$var wire 1 wN X $end +$var wire 1 " A $end +$var supply1 1 k$! VPWR $end +$var supply0 1 l$! VGND $end +$var supply1 1 m$! VPB $end +$var supply0 1 n$! VNB $end + +$scope module base $end +$var wire 1 wN X $end +$var wire 1 " A $end +$var wire 1 o$! buf0_out_X $end +$upscope $end +$upscope $end + +$scope module FTB_105__104 $end +$var wire 1 yI X $end +$var wire 1 nH A $end +$var supply1 1 p$! VPWR $end +$var supply0 1 q$! VGND $end +$var supply1 1 r$! VPB $end +$var supply0 1 s$! VNB $end + +$scope module base $end +$var wire 1 yI X $end +$var wire 1 nH A $end +$var wire 1 t$! buf0_out_X $end +$upscope $end +$upscope $end + +$scope module FTB_106__105 $end +$var wire 1 HJ X $end +$var wire 1 xH A $end +$var supply1 1 u$! VPWR $end +$var supply0 1 v$! VGND $end +$var supply1 1 w$! VPB $end +$var supply0 1 x$! VNB $end + +$scope module base $end +$var wire 1 HJ X $end +$var wire 1 xH A $end +$var wire 1 y$! buf0_out_X $end +$upscope $end +$upscope $end + +$scope module FTB_107__106 $end +$var wire 1 KJ X $end +$var wire 1 {H A $end +$var supply1 1 z$! VPWR $end +$var supply0 1 {$! VGND $end +$var supply1 1 |$! VPB $end +$var supply0 1 }$! VNB $end + +$scope module base $end +$var wire 1 KJ X $end +$var wire 1 {H A $end +$var wire 1 ~$! buf0_out_X $end +$upscope $end +$upscope $end + +$scope module FTB_108__107 $end +$var wire 1 LJ X $end +$var wire 1 |H A $end +$var supply1 1 !%! VPWR $end +$var supply0 1 "%! VGND $end +$var supply1 1 #%! VPB $end +$var supply0 1 $%! VNB $end + +$scope module base $end +$var wire 1 LJ X $end +$var wire 1 |H A $end +$var wire 1 %%! buf0_out_X $end +$upscope $end +$upscope $end + +$scope module FTB_109__108 $end +$var wire 1 MJ X $end +$var wire 1 }H A $end +$var supply1 1 &%! VPWR $end +$var supply0 1 '%! VGND $end +$var supply1 1 (%! VPB $end +$var supply0 1 )%! VNB $end + +$scope module base $end +$var wire 1 MJ X $end +$var wire 1 }H A $end +$var wire 1 *%! buf0_out_X $end +$upscope $end +$upscope $end + +$scope module FTB_110__109 $end +$var wire 1 OJ X $end +$var wire 1 !I A $end +$var supply1 1 +%! VPWR $end +$var supply0 1 ,%! VGND $end +$var supply1 1 -%! VPB $end +$var supply0 1 .%! VNB $end + +$scope module base $end +$var wire 1 OJ X $end +$var wire 1 !I A $end +$var wire 1 /%! buf0_out_X $end +$upscope $end +$upscope $end + +$scope module FTB_111__110 $end +$var wire 1 PJ X $end +$var wire 1 "I A $end +$var supply1 1 0%! VPWR $end +$var supply0 1 1%! VGND $end +$var supply1 1 2%! VPB $end +$var supply0 1 3%! VNB $end + +$scope module base $end +$var wire 1 PJ X $end +$var wire 1 "I A $end +$var wire 1 4%! buf0_out_X $end +$upscope $end +$upscope $end + +$scope module FTB_112__111 $end +$var wire 1 QJ X $end +$var wire 1 #I A $end +$var supply1 1 5%! VPWR $end +$var supply0 1 6%! VGND $end +$var supply1 1 7%! VPB $end +$var supply0 1 8%! VNB $end + +$scope module base $end +$var wire 1 QJ X $end +$var wire 1 #I A $end +$var wire 1 9%! buf0_out_X $end +$upscope $end +$upscope $end + +$scope module FTB_113__112 $end +$var wire 1 SJ X $end +$var wire 1 %I A $end +$var supply1 1 :%! VPWR $end +$var supply0 1 ;%! VGND $end +$var supply1 1 <%! VPB $end +$var supply0 1 =%! VNB $end + +$scope module base $end +$var wire 1 SJ X $end +$var wire 1 %I A $end +$var wire 1 >%! buf0_out_X $end +$upscope $end +$upscope $end + +$scope module FTB_114__113 $end +$var wire 1 TJ X $end +$var wire 1 &I A $end +$var supply1 1 ?%! VPWR $end +$var supply0 1 @%! VGND $end +$var supply1 1 A%! VPB $end +$var supply0 1 B%! VNB $end + +$scope module base $end +$var wire 1 TJ X $end +$var wire 1 &I A $end +$var wire 1 C%! buf0_out_X $end +$upscope $end +$upscope $end + +$scope module FTB_115__114 $end +$var wire 1 UJ X $end +$var wire 1 'I A $end +$var supply1 1 D%! VPWR $end +$var supply0 1 E%! VGND $end +$var supply1 1 F%! VPB $end +$var supply0 1 G%! VNB $end + +$scope module base $end +$var wire 1 UJ X $end +$var wire 1 'I A $end +$var wire 1 H%! buf0_out_X $end +$upscope $end +$upscope $end + +$scope module FTB_116__115 $end +$var wire 1 WJ X $end +$var wire 1 )I A $end +$var supply1 1 I%! VPWR $end +$var supply0 1 J%! VGND $end +$var supply1 1 K%! VPB $end +$var supply0 1 L%! VNB $end + +$scope module base $end +$var wire 1 WJ X $end +$var wire 1 )I A $end +$var wire 1 M%! buf0_out_X $end +$upscope $end +$upscope $end + +$scope module FTB_117__116 $end +$var wire 1 XJ X $end +$var wire 1 *I A $end +$var supply1 1 N%! VPWR $end +$var supply0 1 O%! VGND $end +$var supply1 1 P%! VPB $end +$var supply0 1 Q%! VNB $end + +$scope module base $end +$var wire 1 XJ X $end +$var wire 1 *I A $end +$var wire 1 R%! buf0_out_X $end +$upscope $end +$upscope $end + +$scope module FTB_118__117 $end +$var wire 1 YJ X $end +$var wire 1 +I A $end +$var supply1 1 S%! VPWR $end +$var supply0 1 T%! VGND $end +$var supply1 1 U%! VPB $end +$var supply0 1 V%! VNB $end + +$scope module base $end +$var wire 1 YJ X $end +$var wire 1 +I A $end +$var wire 1 W%! buf0_out_X $end +$upscope $end +$upscope $end + +$scope module FTB_119__118 $end +$var wire 1 [J X $end +$var wire 1 -I A $end +$var supply1 1 X%! VPWR $end +$var supply0 1 Y%! VGND $end +$var supply1 1 Z%! VPB $end +$var supply0 1 [%! VNB $end + +$scope module base $end +$var wire 1 [J X $end +$var wire 1 -I A $end +$var wire 1 \%! buf0_out_X $end +$upscope $end +$upscope $end + +$scope module FTB_120__119 $end +$var wire 1 \J X $end +$var wire 1 .I A $end +$var supply1 1 ]%! VPWR $end +$var supply0 1 ^%! VGND $end +$var supply1 1 _%! VPB $end +$var supply0 1 `%! VNB $end + +$scope module base $end +$var wire 1 \J X $end +$var wire 1 .I A $end +$var wire 1 a%! buf0_out_X $end +$upscope $end +$upscope $end + +$scope module FTB_121__120 $end +$var wire 1 ]J X $end +$var wire 1 /I A $end +$var supply1 1 b%! VPWR $end +$var supply0 1 c%! VGND $end +$var supply1 1 d%! VPB $end +$var supply0 1 e%! VNB $end + +$scope module base $end +$var wire 1 ]J X $end +$var wire 1 /I A $end +$var wire 1 f%! buf0_out_X $end +$upscope $end +$upscope $end + +$scope module FTB_122__121 $end +$var wire 1 _J X $end +$var wire 1 1I A $end +$var supply1 1 g%! VPWR $end +$var supply0 1 h%! VGND $end +$var supply1 1 i%! VPB $end +$var supply0 1 j%! VNB $end + +$scope module base $end +$var wire 1 _J X $end +$var wire 1 1I A $end +$var wire 1 k%! buf0_out_X $end +$upscope $end +$upscope $end + +$scope module FTB_123__122 $end +$var wire 1 `J X $end +$var wire 1 2I A $end +$var supply1 1 l%! VPWR $end +$var supply0 1 m%! VGND $end +$var supply1 1 n%! VPB $end +$var supply0 1 o%! VNB $end + +$scope module base $end +$var wire 1 `J X $end +$var wire 1 2I A $end +$var wire 1 p%! buf0_out_X $end +$upscope $end +$upscope $end + +$scope module FTB_124__123 $end +$var wire 1 aJ X $end +$var wire 1 3I A $end +$var supply1 1 q%! VPWR $end +$var supply0 1 r%! VGND $end +$var supply1 1 s%! VPB $end +$var supply0 1 t%! VNB $end + +$scope module base $end +$var wire 1 aJ X $end +$var wire 1 3I A $end +$var wire 1 u%! buf0_out_X $end +$upscope $end +$upscope $end + +$scope module FTB_125__124 $end +$var wire 1 $J X $end +$var wire 1 @I A $end +$var supply1 1 v%! VPWR $end +$var supply0 1 w%! VGND $end +$var supply1 1 x%! VPB $end +$var supply0 1 y%! VNB $end + +$scope module base $end +$var wire 1 $J X $end +$var wire 1 @I A $end +$var wire 1 z%! buf0_out_X $end +$upscope $end +$upscope $end + +$scope module FTB_126__125 $end +$var wire 1 *J X $end +$var wire 1 AI A $end +$var supply1 1 {%! VPWR $end +$var supply0 1 |%! VGND $end +$var supply1 1 }%! VPB $end +$var supply0 1 ~%! VNB $end + +$scope module base $end +$var wire 1 *J X $end +$var wire 1 AI A $end +$var wire 1 !&! buf0_out_X $end +$upscope $end +$upscope $end + +$scope module FTB_127__126 $end +$var wire 1 pJ X $end +$var wire 1 BI A $end +$var supply1 1 "&! VPWR $end +$var supply0 1 #&! VGND $end +$var supply1 1 $&! VPB $end +$var supply0 1 %&! VNB $end + +$scope module base $end +$var wire 1 pJ X $end +$var wire 1 BI A $end +$var wire 1 &&! buf0_out_X $end +$upscope $end +$upscope $end + +$scope module FTB_128__127 $end +$var wire 1 "J X $end +$var wire 1 CI A $end +$var supply1 1 '&! VPWR $end +$var supply0 1 (&! VGND $end +$var supply1 1 )&! VPB $end +$var supply0 1 *&! VNB $end + +$scope module base $end +$var wire 1 "J X $end +$var wire 1 CI A $end +$var wire 1 +&! buf0_out_X $end +$upscope $end +$upscope $end + +$scope module FTB_129__128 $end +$var wire 1 -J X $end +$var wire 1 DI A $end +$var supply1 1 ,&! VPWR $end +$var supply0 1 -&! VGND $end +$var supply1 1 .&! VPB $end +$var supply0 1 /&! VNB $end + +$scope module base $end +$var wire 1 -J X $end +$var wire 1 DI A $end +$var wire 1 0&! buf0_out_X $end +$upscope $end +$upscope $end + +$scope module FTB_130__129 $end +$var wire 1 .J X $end +$var wire 1 EI A $end +$var supply1 1 1&! VPWR $end +$var supply0 1 2&! VGND $end +$var supply1 1 3&! VPB $end +$var supply0 1 4&! VNB $end + +$scope module base $end +$var wire 1 .J X $end +$var wire 1 EI A $end +$var wire 1 5&! buf0_out_X $end +$upscope $end +$upscope $end + +$scope module FTB_131__130 $end +$var wire 1 /J X $end +$var wire 1 FI A $end +$var supply1 1 6&! VPWR $end +$var supply0 1 7&! VGND $end +$var supply1 1 8&! VPB $end +$var supply0 1 9&! VNB $end + +$scope module base $end +$var wire 1 /J X $end +$var wire 1 FI A $end +$var wire 1 :&! buf0_out_X $end +$upscope $end +$upscope $end + +$scope module FTB_132__131 $end +$var wire 1 1J X $end +$var wire 1 HI A $end +$var supply1 1 ;&! VPWR $end +$var supply0 1 <&! VGND $end +$var supply1 1 =&! VPB $end +$var supply0 1 >&! VNB $end + +$scope module base $end +$var wire 1 1J X $end +$var wire 1 HI A $end +$var wire 1 ?&! buf0_out_X $end +$upscope $end +$upscope $end + +$scope module FTB_133__132 $end +$var wire 1 2J X $end +$var wire 1 II A $end +$var supply1 1 @&! VPWR $end +$var supply0 1 A&! VGND $end +$var supply1 1 B&! VPB $end +$var supply0 1 C&! VNB $end + +$scope module base $end +$var wire 1 2J X $end +$var wire 1 II A $end +$var wire 1 D&! buf0_out_X $end +$upscope $end +$upscope $end + +$scope module FTB_134__133 $end +$var wire 1 3J X $end +$var wire 1 JI A $end +$var supply1 1 E&! VPWR $end +$var supply0 1 F&! VGND $end +$var supply1 1 G&! VPB $end +$var supply0 1 H&! VNB $end + +$scope module base $end +$var wire 1 3J X $end +$var wire 1 JI A $end +$var wire 1 I&! buf0_out_X $end +$upscope $end +$upscope $end + +$scope module FTB_135__134 $end +$var wire 1 5J X $end +$var wire 1 LI A $end +$var supply1 1 J&! VPWR $end +$var supply0 1 K&! VGND $end +$var supply1 1 L&! VPB $end +$var supply0 1 M&! VNB $end + +$scope module base $end +$var wire 1 5J X $end +$var wire 1 LI A $end +$var wire 1 N&! buf0_out_X $end +$upscope $end +$upscope $end + +$scope module FTB_136__135 $end +$var wire 1 6J X $end +$var wire 1 MI A $end +$var supply1 1 O&! VPWR $end +$var supply0 1 P&! VGND $end +$var supply1 1 Q&! VPB $end +$var supply0 1 R&! VNB $end + +$scope module base $end +$var wire 1 6J X $end +$var wire 1 MI A $end +$var wire 1 S&! buf0_out_X $end +$upscope $end +$upscope $end + +$scope module FTB_137__136 $end +$var wire 1 7J X $end +$var wire 1 NI A $end +$var supply1 1 T&! VPWR $end +$var supply0 1 U&! VGND $end +$var supply1 1 V&! VPB $end +$var supply0 1 W&! VNB $end + +$scope module base $end +$var wire 1 7J X $end +$var wire 1 NI A $end +$var wire 1 X&! buf0_out_X $end +$upscope $end +$upscope $end + +$scope module FTB_138__137 $end +$var wire 1 9J X $end +$var wire 1 PI A $end +$var supply1 1 Y&! VPWR $end +$var supply0 1 Z&! VGND $end +$var supply1 1 [&! VPB $end +$var supply0 1 \&! VNB $end + +$scope module base $end +$var wire 1 9J X $end +$var wire 1 PI A $end +$var wire 1 ]&! buf0_out_X $end +$upscope $end +$upscope $end + +$scope module FTB_139__138 $end +$var wire 1 :J X $end +$var wire 1 QI A $end +$var supply1 1 ^&! VPWR $end +$var supply0 1 _&! VGND $end +$var supply1 1 `&! VPB $end +$var supply0 1 a&! VNB $end + +$scope module base $end +$var wire 1 :J X $end +$var wire 1 QI A $end +$var wire 1 b&! buf0_out_X $end +$upscope $end +$upscope $end + +$scope module FTB_140__139 $end +$var wire 1 ;J X $end +$var wire 1 RI A $end +$var supply1 1 c&! VPWR $end +$var supply0 1 d&! VGND $end +$var supply1 1 e&! VPB $end +$var supply0 1 f&! VNB $end + +$scope module base $end +$var wire 1 ;J X $end +$var wire 1 RI A $end +$var wire 1 g&! buf0_out_X $end +$upscope $end +$upscope $end + +$scope module FTB_141__140 $end +$var wire 1 =J X $end +$var wire 1 TI A $end +$var supply1 1 h&! VPWR $end +$var supply0 1 i&! VGND $end +$var supply1 1 j&! VPB $end +$var supply0 1 k&! VNB $end + +$scope module base $end +$var wire 1 =J X $end +$var wire 1 TI A $end +$var wire 1 l&! buf0_out_X $end +$upscope $end +$upscope $end + +$scope module FTB_142__141 $end +$var wire 1 >J X $end +$var wire 1 UI A $end +$var supply1 1 m&! VPWR $end +$var supply0 1 n&! VGND $end +$var supply1 1 o&! VPB $end +$var supply0 1 p&! VNB $end + +$scope module base $end +$var wire 1 >J X $end +$var wire 1 UI A $end +$var wire 1 q&! buf0_out_X $end +$upscope $end +$upscope $end + +$scope module FTB_143__142 $end +$var wire 1 ?J X $end +$var wire 1 VI A $end +$var supply1 1 r&! VPWR $end +$var supply0 1 s&! VGND $end +$var supply1 1 t&! VPB $end +$var supply0 1 u&! VNB $end + +$scope module base $end +$var wire 1 ?J X $end +$var wire 1 VI A $end +$var wire 1 v&! buf0_out_X $end +$upscope $end +$upscope $end + +$scope module FTB_144__143 $end +$var wire 1 AJ X $end +$var wire 1 XI A $end +$var supply1 1 w&! VPWR $end +$var supply0 1 x&! VGND $end +$var supply1 1 y&! VPB $end +$var supply0 1 z&! VNB $end + +$scope module base $end +$var wire 1 AJ X $end +$var wire 1 XI A $end +$var wire 1 {&! buf0_out_X $end +$upscope $end +$upscope $end + +$scope module FTB_145__144 $end +$var wire 1 BJ X $end +$var wire 1 YI A $end +$var supply1 1 |&! VPWR $end +$var supply0 1 }&! VGND $end +$var supply1 1 ~&! VPB $end +$var supply0 1 !'! VNB $end + +$scope module base $end +$var wire 1 BJ X $end +$var wire 1 YI A $end +$var wire 1 "'! buf0_out_X $end +$upscope $end +$upscope $end + +$scope module FTB_146__145 $end +$var wire 1 CJ X $end +$var wire 1 ZI A $end +$var supply1 1 #'! VPWR $end +$var supply0 1 $'! VGND $end +$var supply1 1 %'! VPB $end +$var supply0 1 &'! VNB $end + +$scope module base $end +$var wire 1 CJ X $end +$var wire 1 ZI A $end +$var wire 1 ''! buf0_out_X $end +$upscope $end +$upscope $end + +$scope module FTB_147__146 $end +$var wire 1 dJ X $end +$var wire 1 cJ A $end +$var supply1 1 ('! VPWR $end +$var supply0 1 )'! VGND $end +$var supply1 1 *'! VPB $end +$var supply0 1 +'! VNB $end + +$scope module base $end +$var wire 1 dJ X $end +$var wire 1 cJ A $end +$var wire 1 ,'! buf0_out_X $end +$upscope $end +$upscope $end + +$scope module BINV_R_195 $end +$var wire 1 fJ Y $end +$var wire 1 xN A $end +$var supply1 1 -'! VPWR $end +$var supply0 1 .'! VGND $end +$var supply1 1 /'! VPB $end +$var supply0 1 0'! VNB $end + +$scope module base $end +$var wire 1 fJ Y $end +$var wire 1 xN A $end +$var wire 1 1'! not0_out_Y $end +$upscope $end +$upscope $end + +$scope module BINV_R_196 $end +$var wire 1 xN Y $end +$var wire 1 eJ A $end +$var supply1 1 2'! VPWR $end +$var supply0 1 3'! VGND $end +$var supply1 1 4'! VPB $end +$var supply0 1 5'! VNB $end + +$scope module base $end +$var wire 1 xN Y $end +$var wire 1 eJ A $end +$var wire 1 6'! not0_out_Y $end +$upscope $end +$upscope $end + +$scope module BINV_R_197 $end +$var wire 1 iJ Y $end +$var wire 1 yN A $end +$var supply1 1 7'! VPWR $end +$var supply0 1 8'! VGND $end +$var supply1 1 9'! VPB $end +$var supply0 1 :'! VNB $end + +$scope module base $end +$var wire 1 iJ Y $end +$var wire 1 yN A $end +$var wire 1 ;'! not0_out_Y $end +$upscope $end +$upscope $end + +$scope module BINV_R_198 $end +$var wire 1 yN Y $end +$var wire 1 sN A $end +$var supply1 1 <'! VPWR $end +$var supply0 1 ='! VGND $end +$var supply1 1 >'! VPB $end +$var supply0 1 ?'! VNB $end + +$scope module base $end +$var wire 1 yN Y $end +$var wire 1 sN A $end +$var wire 1 @'! not0_out_Y $end +$upscope $end +$upscope $end + +$scope module BINV_R_199 $end +$var wire 1 lJ Y $end +$var wire 1 zN A $end +$var supply1 1 A'! VPWR $end +$var supply0 1 B'! VGND $end +$var supply1 1 C'! VPB $end +$var supply0 1 D'! VNB $end + +$scope module base $end +$var wire 1 lJ Y $end +$var wire 1 zN A $end +$var wire 1 E'! not0_out_Y $end +$upscope $end +$upscope $end + +$scope module BINV_R_200 $end +$var wire 1 zN Y $end +$var wire 1 # A $end +$var supply1 1 F'! VPWR $end +$var supply0 1 G'! VGND $end +$var supply1 1 H'! VPB $end +$var supply0 1 I'! VNB $end + +$scope module base $end +$var wire 1 zN Y $end +$var wire 1 # A $end +$var wire 1 J'! not0_out_Y $end +$upscope $end +$upscope $end + +$scope module BINV_R_201 $end +$var wire 1 nJ Y $end +$var wire 1 {N A $end +$var supply1 1 K'! VPWR $end +$var supply0 1 L'! VGND $end +$var supply1 1 M'! VPB $end +$var supply0 1 N'! VNB $end + +$scope module base $end +$var wire 1 nJ Y $end +$var wire 1 {N A $end +$var wire 1 O'! not0_out_Y $end +$upscope $end +$upscope $end + +$scope module BINV_R_202 $end +$var wire 1 {N Y $end +$var wire 1 vN A $end +$var supply1 1 P'! VPWR $end +$var supply0 1 Q'! VGND $end +$var supply1 1 R'! VPB $end +$var supply0 1 S'! VNB $end + +$scope module base $end +$var wire 1 {N Y $end +$var wire 1 vN A $end +$var wire 1 T'! not0_out_Y $end +$upscope $end +$upscope $end + +$scope module BINV_R_203 $end +$var wire 1 oJ Y $end +$var wire 1 |N A $end +$var supply1 1 U'! VPWR $end +$var supply0 1 V'! VGND $end +$var supply1 1 W'! VPB $end +$var supply0 1 X'! VNB $end + +$scope module base $end +$var wire 1 oJ Y $end +$var wire 1 |N A $end +$var wire 1 Y'! not0_out_Y $end +$upscope $end +$upscope $end + +$scope module BINV_R_204 $end +$var wire 1 |N Y $end +$var wire 1 wN A $end +$var supply1 1 Z'! VPWR $end +$var supply0 1 ['! VGND $end +$var supply1 1 \'! VPB $end +$var supply0 1 ]'! VNB $end + +$scope module base $end +$var wire 1 |N Y $end +$var wire 1 wN A $end +$var wire 1 ^'! not0_out_Y $end +$upscope $end +$upscope $end + +$scope module optlc_213 $end +$var wire 1 9M HI $end +$var wire 1 }N LO $end +$var supply1 1 _'! VPWR $end +$var supply0 1 `'! VGND $end +$var supply1 1 a'! VPB $end +$var supply0 1 b'! VNB $end + +$scope module base $end +$var wire 1 9M HI $end +$var wire 1 }N LO $end +$upscope $end +$upscope $end + +$scope module optlc_215 $end +$var wire 1 GM HI $end +$var wire 1 ~N LO $end +$var supply1 1 c'! VPWR $end +$var supply0 1 d'! VGND $end +$var supply1 1 e'! VPB $end +$var supply0 1 f'! VNB $end + +$scope module base $end +$var wire 1 GM HI $end +$var wire 1 ~N LO $end +$upscope $end +$upscope $end + +$scope module optlc_217 $end +$var wire 1 LM HI $end +$var wire 1 !O LO $end +$var supply1 1 g'! VPWR $end +$var supply0 1 h'! VGND $end +$var supply1 1 i'! VPB $end +$var supply0 1 j'! VNB $end + +$scope module base $end +$var wire 1 LM HI $end +$var wire 1 !O LO $end +$upscope $end +$upscope $end + +$scope module optlc_219 $end +$var wire 1 ,M HI $end +$var wire 1 "O LO $end +$var supply1 1 k'! VPWR $end +$var supply0 1 l'! VGND $end +$var supply1 1 m'! VPB $end +$var supply0 1 n'! VNB $end + +$scope module base $end +$var wire 1 ,M HI $end +$var wire 1 "O LO $end +$upscope $end +$upscope $end + +$scope module ZBUF_6_f_inst_220 $end +$var wire 1 )J X $end +$var wire 1 dN A $end +$var supply1 1 o'! VPWR $end +$var supply0 1 p'! VGND $end +$var supply1 1 q'! VPB $end +$var supply0 1 r'! VNB $end + +$scope module base $end +$var wire 1 )J X $end +$var wire 1 dN A $end +$var wire 1 s'! buf0_out_X $end +$upscope $end +$upscope $end + +$scope module ZBUF_6_f_inst_221 $end +$var wire 1 kJ X $end +$var wire 1 tN A $end +$var supply1 1 t'! VPWR $end +$var supply0 1 u'! VGND $end +$var supply1 1 v'! VPB $end +$var supply0 1 w'! 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