Merge pull request #54 from lnis-uofu/xt_dev

Critical Patches on Simulation Scripts and Testbenches

.github/workflows/quick_test.sh

@@ -20,7 +20,13 @@ python3 HDL/common/wrapper_lines_generator.py --template_netlist HDL/common/cara
 ##############################################
 # Generate post-PnR testbenches
 python3 TESTBENCH/common/generate_post_pnr_testbenches.py --pre_pnr_testbench_dir_name ./TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc --pin_assignment_file ./HDL/common/caravel_wrapper_pin_assignment_v1.0.json
-python3 TESTBENCH/common/generate_post_pnr_testbenches.py --pre_pnr_testbench_dir_name ./TESTBENCH/k4_N8_reset_caravel_io_FPGA_12x12_fdhd_cc --pin_assignment_file ./HDL/common/caravel_wrapper_pin_assignment_v1.1.json
-python3 TESTBENCH/common/generate_post_pnr_testbenches.py --pre_pnr_testbench_dir_name ./TESTBENCH/k4_N8_softadder_caravel_io_FPGA_12x12_fdhd_cc --pin_assignment_file ./HDL/common/caravel_wrapper_pin_assignment_v1.0.json
 python3 TESTBENCH/common/generate_post_pnr_testbenches.py --pre_pnr_testbench_dir_name ./TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_fdhd_cc --pin_assignment_file ./HDL/common/caravel_wrapper_pin_assignment_v1.1.json
 python3 TESTBENCH/common/generate_post_pnr_testbenches.py --pre_pnr_testbench_dir_name ./TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_customhd_cc --pin_assignment_file ./HDL/common/caravel_wrapper_pin_assignment_v1.1.json
+
+# Generate wrapper testbenches from template tesbenches for configuration chain tests
+python3 TESTBENCH/common/post_pnr_wrapper_testbench_converter.py --post_pnr_testbench TESTBENCH/common/ccff_test_post_pnr_v1.0.v --pin_assignment_file HDL/common/caravel_wrapper_pin_assignment_v1.0.json --wrapper_testbench TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/ccff_test_post_pnr_wrapper.v
+python3 TESTBENCH/common/post_pnr_wrapper_testbench_converter.py --post_pnr_testbench TESTBENCH/common/ccff_test_post_pnr_v1.1.v --pin_assignment_file HDL/common/caravel_wrapper_pin_assignment_v1.1.json --wrapper_testbench TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/ccff_test_post_pnr_wrapper.v
+
+# Generate wrapper testbenches from template tesbenches for scan chain tests
+python3 TESTBENCH/common/post_pnr_wrapper_testbench_converter.py --post_pnr_testbench TESTBENCH/common/scff_test_post_pnr_v1.0.v --pin_assignment_file HDL/common/caravel_wrapper_pin_assignment_v1.0.json --wrapper_testbench TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/scff_test_post_pnr_wrapper.v
+python3 TESTBENCH/common/post_pnr_wrapper_testbench_converter.py --post_pnr_testbench TESTBENCH/common/scff_test_post_pnr_v1.1.v --pin_assignment_file HDL/common/caravel_wrapper_pin_assignment_v1.1.json --wrapper_testbench TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/scff_test_post_pnr_wrapper.v

ARCH/openfpga_arch_template/k4_frac_N8_reset_softadder_register_scan_chain_caravel_io_skywater130nm_fdhd_cc_openfpga.xml

@@ -230,7 +230,7 @@
   </direct_connection>
   <tile_annotations>
     <global_port name="clk" tile_port="clb.clk" is_clock="true" default_val="0"/>
-    <global_port name="reset" tile_port="clb.reset" is_reset="true" default_val="1"/>
+    <global_port name="Reset" tile_port="clb.reset" is_reset="true" default_val="1"/>
   </tile_annotations>
   <pb_type_annotations>
     <!-- physical pb_type binding in complex block IO -->

HDL/common/caravel_wrapper_pin_assignment_v1.1.json

@@ -46,13 +46,13 @@
       "caravel_pin_index": ["10:4"]
     }, 
     {
-      "fpga_pin_type": "prog_reset", 
+      "fpga_pin_type": "pReset", 
       "fpga_pin_index": "0:0", 
       "caravel_pin_type": ["input"],
       "caravel_pin_index": ["3:3"]
     },
     {
-      "fpga_pin_type": "reset", 
+      "fpga_pin_type": "Reset", 
       "fpga_pin_index": "0:0", 
       "caravel_pin_type": ["input"],
       "caravel_pin_index": ["2:2"]

MSIM/common/run_post_pnr_msim_test.py

@@ -121,16 +121,24 @@ for line in vsim_log_file:
   # Check errors from self-testing testbench output
   if line.startswith("# Simulation finish with") :
     num_sim_err = int(re.findall("# Simulation finish with(\s+)(\d+) errors", line)[0][1])
-    num_err_lines_found = num_err_lines_found + 1
+    num_err_lines_found += 1
     if (0 < num_sim_err) : 
       logging.error("Simulation failed with " + str(num_sim_err) + " errors!\n")
       # Add to total errors
-      num_err = num_err + num_sim_err
+      num_err += num_sim_err
+  if line.startswith("# Simulation Failed with") :
+    print (line)
+    num_sim_err = int(re.findall("# Simulation Failed with(\s+)(\d+) error\(s\)", line)[0][1])
+    num_err_lines_found += 1
+    if (0 < num_sim_err) : 
+      logging.error("Simulation failed with " + str(num_sim_err) + " errors!\n")
+      # Add to total errors
+      num_err += num_sim_err
   # Check total errors by Modelsim
   if line.startswith("# Errors:") :
     num_msim_err = int(re.findall("# Errors:(\s)(\d+),", line)[0][1])
-    num_err_lines_found = num_err_lines_found + 1
+    num_err_lines_found += 1
-    num_err = num_err + num_msim_err
+    num_err += num_msim_err
 
 vsim_log_file.close()
 

SCRIPT/skywater_openfpga_task/k4_N8_reset_caravel_cc_fdhd_12x12/generate_fabric/config/task_template.conf

@@ -1,38 +0,0 @@
-# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
-# Configuration file for running experiments
-# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
-# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs
-# Each job execute fpga_flow script on combination of architecture & benchmark
-# timeout_each_job is timeout for each job
-# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
-
-[GENERAL]
-run_engine=openfpga_shell
-power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml
-power_analysis = true
-spice_output=false
-verilog_output=true
-timeout_each_job = 1*60
-fpga_flow=yosys_vpr
-
-[OpenFPGA_SHELL]
-openfpga_shell_template=${SKYWATER_OPENFPGA_HOME}/SCRIPT/openfpga_shell_script/skywater_generate_fabric_using_key_example_script.openfpga
-openfpga_arch_file=${SKYWATER_OPENFPGA_HOME}/ARCH/openfpga_arch/k4_frac_N8_reset_register_scan_chain_caravel_io_skywater130nm_fdhd_cc_openfpga.xml
-openfpga_sim_setting_file=${SKYWATER_OPENFPGA_HOME}/SCRIPT/openfpga_simulation_setting/efpga_12x12_sim_openfpga.xml
-openfpga_vpr_device_layout=12x12
-openfpga_vpr_route_chan_width=40
-openfpga_verilog_output_dir=${SKYWATER_OPENFPGA_HOME}/HDL/k4_N8_reset_caravel_io_FPGA_12x12_fdhd_cc
-openfpga_sdc_output_dir=${SKYWATER_OPENFPGA_HOME}/SDC/k4_N8_reset_caravel_io_FPGA_12x12_fdhd_cc
-external_fabric_key_file=${SKYWATER_OPENFPGA_HOME}/ARCH/fabric_key/fabric_key_12x12.xml
-
-[ARCHITECTURES]
-arch0=${SKYWATER_OPENFPGA_HOME}/ARCH/vpr_arch/k4_frac_N8_tileable_reset_register_scan_chain_nonLR_caravel_io_skywater130nm.xml
-
-[BENCHMARKS]
-bench0=${SKYWATER_OPENFPGA_HOME}/BENCHMARK/and2/and2.v
-
-[SYNTHESIS_PARAM]
-bench0_top = and2
-
-[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
-#end_flow_with_test=

SCRIPT/skywater_openfpga_task/k4_N8_reset_caravel_cc_fdhd_12x12/generate_sdc/config/task_template.conf

@@ -1,37 +0,0 @@
-# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
-# Configuration file for running experiments
-# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
-# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs
-# Each job execute fpga_flow script on combination of architecture & benchmark
-# timeout_each_job is timeout for each job
-# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
-
-[GENERAL]
-run_engine=openfpga_shell
-power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml
-power_analysis = true
-spice_output=false
-verilog_output=true
-timeout_each_job = 1*60
-fpga_flow=yosys_vpr
-
-[OpenFPGA_SHELL]
-openfpga_shell_template=${SKYWATER_OPENFPGA_HOME}/SCRIPT/openfpga_shell_script/skywater_generate_sdc_using_key_example_script.openfpga
-openfpga_arch_file=${SKYWATER_OPENFPGA_HOME}/ARCH/openfpga_arch/k4_frac_N8_reset_register_scan_chain_caravel_io_skywater130nm_fdhd_cc_openfpga.xml
-openfpga_sim_setting_file=${SKYWATER_OPENFPGA_HOME}/SCRIPT/openfpga_simulation_setting/efpga_12x12_sim_openfpga.xml
-openfpga_vpr_device_layout=12x12
-openfpga_vpr_route_chan_width=40
-openfpga_sdc_output_dir=${SKYWATER_OPENFPGA_HOME}/SDC/k4_N8_reset_caravel_io_FPGA_12x12_fdhd_cc
-external_fabric_key_file=${SKYWATER_OPENFPGA_HOME}/ARCH/fabric_key/fabric_key_12x12.xml
-
-[ARCHITECTURES]
-arch0=${SKYWATER_OPENFPGA_HOME}/ARCH/vpr_arch/k4_frac_N8_tileable_reset_register_scan_chain_nonLR_caravel_io_skywater130nm.xml
-
-[BENCHMARKS]
-bench0=${SKYWATER_OPENFPGA_HOME}/BENCHMARK/and2/and2.v
-
-[SYNTHESIS_PARAM]
-bench0_top = and2
-
-[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
-#end_flow_with_test=

SCRIPT/skywater_openfpga_task/k4_N8_reset_caravel_cc_fdhd_12x12/generate_testbench/config/task_template.conf

@@ -1,54 +0,0 @@
-# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
-# Configuration file for running experiments
-# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
-# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs
-# Each job execute fpga_flow script on combination of architecture & benchmark
-# timeout_each_job is timeout for each job
-# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
-
-[GENERAL]
-run_engine=openfpga_shell
-power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml
-power_analysis = true
-spice_output=false
-verilog_output=true
-timeout_each_job = 1*60
-fpga_flow=yosys_vpr
-
-[OpenFPGA_SHELL]
-openfpga_shell_template=${SKYWATER_OPENFPGA_HOME}/SCRIPT/openfpga_shell_script/skywater_generate_testbench_using_key_example_script.openfpga
-openfpga_arch_file=${SKYWATER_OPENFPGA_HOME}/ARCH/openfpga_arch/k4_frac_N8_reset_register_scan_chain_caravel_io_skywater130nm_fdhd_cc_openfpga.xml
-openfpga_sim_setting_file=${SKYWATER_OPENFPGA_HOME}/SCRIPT/openfpga_simulation_setting/efpga_12x12_sim_openfpga.xml
-openfpga_vpr_device_layout=12x12
-openfpga_vpr_route_chan_width=40
-openfpga_verilog_output_dir=${SKYWATER_OPENFPGA_HOME}/TESTBENCH/k4_N8_reset_caravel_io_FPGA_12x12_fdhd_cc/prepnr
-openfpga_fabric_verilog_netlist=${SKYWATER_OPENFPGA_HOME}/HDL/k4_N8_reset_caravel_io_FPGA_12x12_fdhd_cc/SRC/fabric_netlists.v
-external_fabric_key_file=${SKYWATER_OPENFPGA_HOME}/ARCH/fabric_key/fabric_key_12x12.xml
-
-[ARCHITECTURES]
-arch0=${SKYWATER_OPENFPGA_HOME}/ARCH/vpr_arch/k4_frac_N8_tileable_reset_register_scan_chain_nonLR_caravel_io_skywater130nm.xml
-
-[BENCHMARKS]
-bench0=${SKYWATER_OPENFPGA_HOME}/BENCHMARK/and2/and2.v
-bench1=${SKYWATER_OPENFPGA_HOME}/BENCHMARK/and2_latch/and2_latch.v
-bench2=${SKYWATER_OPENFPGA_HOME}/BENCHMARK/bin2bcd/bin2bcd.v
-bench3=${SKYWATER_OPENFPGA_HOME}/BENCHMARK/counter/counter.v
-bench4=${SKYWATER_OPENFPGA_HOME}/BENCHMARK/routing_test/routing_test.v
-# RS decoder needs 1.5k LUT4, exceeding device capacity
-#bench5=${SKYWATER_OPENFPGA_HOME}/BENCHMARK/rs_decoder/rtl/rs_decoder.v
-bench6=${SKYWATER_OPENFPGA_HOME}/BENCHMARK/simon_bit_serial/rtl/*.v
-bench7=${SKYWATER_OPENFPGA_HOME}/BENCHMARK/and2_or2/and2_or2.v
-
-[SYNTHESIS_PARAM]
-bench0_top = and2
-bench1_top = and2_latch
-bench2_top = bin2bcd
-bench3_top = counter
-bench4_top = routing_test
-# RS decoder needs 1.5k LUT4, exceeding device capacity
-#bench5_top = rs_decoder_top
-bench6_top = top_module
-bench7_top = and2_or2
-
-[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
-#end_flow_with_test=

SCRIPT/skywater_openfpga_task/k4_N8_softadder_caravel_cc_fdhd_12x12/generate_fabric/config/task_template.conf

@@ -1,38 +0,0 @@
-# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
-# Configuration file for running experiments
-# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
-# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs
-# Each job execute fpga_flow script on combination of architecture & benchmark
-# timeout_each_job is timeout for each job
-# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
-
-[GENERAL]
-run_engine=openfpga_shell
-power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml
-power_analysis = true
-spice_output=false
-verilog_output=true
-timeout_each_job = 1*60
-fpga_flow=yosys_vpr
-
-[OpenFPGA_SHELL]
-openfpga_shell_template=${SKYWATER_OPENFPGA_HOME}/SCRIPT/openfpga_shell_script/skywater_generate_fabric_using_key_example_script.openfpga
-openfpga_arch_file=${SKYWATER_OPENFPGA_HOME}/ARCH/openfpga_arch/k4_frac_N8_softadder_register_scan_chain_caravel_io_skywater130nm_fdhd_cc_openfpga.xml
-openfpga_sim_setting_file=${SKYWATER_OPENFPGA_HOME}/SCRIPT/openfpga_simulation_setting/efpga_12x12_sim_openfpga.xml
-openfpga_vpr_device_layout=12x12
-openfpga_vpr_route_chan_width=40
-openfpga_verilog_output_dir=${SKYWATER_OPENFPGA_HOME}/HDL/k4_N8_softadder_caravel_io_FPGA_12x12_fdhd_cc
-openfpga_sdc_output_dir=${SKYWATER_OPENFPGA_HOME}/SDC/k4_N8_softadder_caravel_io_FPGA_12x12_fdhd_cc
-external_fabric_key_file=${SKYWATER_OPENFPGA_HOME}/ARCH/fabric_key/fabric_key_12x12.xml
-
-[ARCHITECTURES]
-arch0=${SKYWATER_OPENFPGA_HOME}/ARCH/vpr_arch/k4_frac_N8_tileable_softadder_register_scan_chain_nonLR_caravel_io_skywater130nm.xml
-
-[BENCHMARKS]
-bench0=${SKYWATER_OPENFPGA_HOME}/BENCHMARK/and2/and2.v
-
-[SYNTHESIS_PARAM]
-bench0_top = and2
-
-[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
-#end_flow_with_test=

SCRIPT/skywater_openfpga_task/k4_N8_softadder_caravel_cc_fdhd_12x12/generate_sdc/config/task_template.conf

@@ -1,37 +0,0 @@
-# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
-# Configuration file for running experiments
-# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
-# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs
-# Each job execute fpga_flow script on combination of architecture & benchmark
-# timeout_each_job is timeout for each job
-# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
-
-[GENERAL]
-run_engine=openfpga_shell
-power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml
-power_analysis = true
-spice_output=false
-verilog_output=true
-timeout_each_job = 1*60
-fpga_flow=yosys_vpr
-
-[OpenFPGA_SHELL]
-openfpga_shell_template=${SKYWATER_OPENFPGA_HOME}/SCRIPT/openfpga_shell_script/skywater_generate_sdc_using_key_example_script.openfpga
-openfpga_arch_file=${SKYWATER_OPENFPGA_HOME}/ARCH/openfpga_arch/k4_frac_N8_softadder_register_scan_chain_caravel_io_skywater130nm_fdhd_cc_openfpga.xml
-openfpga_sim_setting_file=${SKYWATER_OPENFPGA_HOME}/SCRIPT/openfpga_simulation_setting/efpga_12x12_sim_openfpga.xml
-openfpga_vpr_device_layout=12x12
-openfpga_vpr_route_chan_width=40
-openfpga_sdc_output_dir=${SKYWATER_OPENFPGA_HOME}/SDC/k4_N8_softadder_caravel_io_FPGA_12x12_fdhd_cc
-external_fabric_key_file=${SKYWATER_OPENFPGA_HOME}/ARCH/fabric_key/fabric_key_12x12.xml
-
-[ARCHITECTURES]
-arch0=${SKYWATER_OPENFPGA_HOME}/ARCH/vpr_arch/k4_frac_N8_tileable_softadder_register_scan_chain_nonLR_caravel_io_skywater130nm.xml
-
-[BENCHMARKS]
-bench0=${SKYWATER_OPENFPGA_HOME}/BENCHMARK/and2/and2.v
-
-[SYNTHESIS_PARAM]
-bench0_top = and2
-
-[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
-#end_flow_with_test=

SCRIPT/skywater_openfpga_task/k4_N8_softadder_caravel_cc_fdhd_12x12/generate_testbench/config/task_template.conf

@@ -1,54 +0,0 @@
-# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
-# Configuration file for running experiments
-# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
-# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs
-# Each job execute fpga_flow script on combination of architecture & benchmark
-# timeout_each_job is timeout for each job
-# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
-
-[GENERAL]
-run_engine=openfpga_shell
-power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml
-power_analysis = true
-spice_output=false
-verilog_output=true
-timeout_each_job = 1*60
-fpga_flow=yosys_vpr
-
-[OpenFPGA_SHELL]
-openfpga_shell_template=${SKYWATER_OPENFPGA_HOME}/SCRIPT/openfpga_shell_script/skywater_generate_testbench_using_key_example_script.openfpga
-openfpga_arch_file=${SKYWATER_OPENFPGA_HOME}/ARCH/openfpga_arch/k4_frac_N8_softadder_register_scan_chain_caravel_io_skywater130nm_fdhd_cc_openfpga.xml
-openfpga_sim_setting_file=${SKYWATER_OPENFPGA_HOME}/SCRIPT/openfpga_simulation_setting/efpga_12x12_sim_openfpga.xml
-openfpga_vpr_device_layout=12x12
-openfpga_vpr_route_chan_width=40
-openfpga_verilog_output_dir=${SKYWATER_OPENFPGA_HOME}/TESTBENCH/k4_N8_softadder_caravel_io_FPGA_12x12_fdhd_cc/prepnr
-openfpga_fabric_verilog_netlist=${SKYWATER_OPENFPGA_HOME}/HDL/k4_N8_softadder_caravel_io_FPGA_12x12_fdhd_cc/SRC/fabric_netlists.v
-external_fabric_key_file=${SKYWATER_OPENFPGA_HOME}/ARCH/fabric_key/fabric_key_12x12.xml
-
-[ARCHITECTURES]
-arch0=${SKYWATER_OPENFPGA_HOME}/ARCH/vpr_arch/k4_frac_N8_tileable_softadder_register_scan_chain_nonLR_caravel_io_skywater130nm.xml
-
-[BENCHMARKS]
-bench0=${SKYWATER_OPENFPGA_HOME}/BENCHMARK/and2/and2.v
-bench1=${SKYWATER_OPENFPGA_HOME}/BENCHMARK/and2_latch/and2_latch.v
-bench2=${SKYWATER_OPENFPGA_HOME}/BENCHMARK/bin2bcd/bin2bcd.v
-bench3=${SKYWATER_OPENFPGA_HOME}/BENCHMARK/counter/counter.v
-bench4=${SKYWATER_OPENFPGA_HOME}/BENCHMARK/routing_test/routing_test.v
-# RS decoder needs 1.5k LUT4, exceeding device capacity
-#bench5=${SKYWATER_OPENFPGA_HOME}/BENCHMARK/rs_decoder/rtl/rs_decoder.v
-bench6=${SKYWATER_OPENFPGA_HOME}/BENCHMARK/simon_bit_serial/rtl/*.v
-bench7=${SKYWATER_OPENFPGA_HOME}/BENCHMARK/and2_or2/and2_or2.v
-
-[SYNTHESIS_PARAM]
-bench0_top = and2
-bench1_top = and2_latch
-bench2_top = bin2bcd
-bench3_top = counter
-bench4_top = routing_test
-# RS decoder needs 1.5k LUT4, exceeding device capacity
-#bench5_top = rs_decoder_top
-bench6_top = top_module
-bench7_top = and2_or2
-
-[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
-#end_flow_with_test=