From 61163de580ee9235f95238eb4be9b097e01f3a28 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Wed, 2 Dec 2020 12:00:28 -0700 Subject: [PATCH 01/13] [Testbench] Correct path to post-pnR netlists and prepare for sign-off on FPGA with reset --- .../and2_latch_post_pnr_include_netlists.v | 3 +- ..._latch_post_pnr_wrapper_include_netlists.v | 34 +++++++++++++++++-- .../and2_or2_post_pnr_include_netlists.v | 3 +- ...d2_or2_post_pnr_wrapper_include_netlists.v | 34 +++++++++++++++++-- .../and2_post_pnr_include_netlists.v | 3 +- .../and2_post_pnr_wrapper_include_netlists.v | 34 +++++++++++++++++-- .../ccff_test_post_pnr_include_netlists.v | 31 +++++++++++++++-- ...f_test_post_pnr_wrapper_include_netlists.v | 33 ++++++++++++++++-- .../routing_test_post_pnr_include_netlists.v | 3 +- ...g_test_post_pnr_wrapper_include_netlists.v | 34 +++++++++++++++++-- .../scff_test_post_pnr_include_netlists.v | 31 +++++++++++++++-- ...f_test_post_pnr_wrapper_include_netlists.v | 33 ++++++++++++++++-- .../and2_latch_post_pnr_include_netlists.v | 29 ++++++++++++++++ ..._latch_post_pnr_wrapper_include_netlists.v | 31 +++++++++++++++++ .../and2_or2_post_pnr_include_netlists.v | 29 ++++++++++++++++ ...d2_or2_post_pnr_wrapper_include_netlists.v | 31 +++++++++++++++++ .../and2_post_pnr_include_netlists.v | 29 ++++++++++++++++ .../and2_post_pnr_wrapper_include_netlists.v | 31 +++++++++++++++++ .../ccff_test_post_pnr_include_netlists.v | 28 +++++++++++++++ ...f_test_post_pnr_wrapper_include_netlists.v | 30 ++++++++++++++++ .../routing_test_post_pnr_include_netlists.v | 29 ++++++++++++++++ ...g_test_post_pnr_wrapper_include_netlists.v | 31 +++++++++++++++++ .../scff_test_post_pnr_include_netlists.v | 28 +++++++++++++++ ...f_test_post_pnr_wrapper_include_netlists.v | 30 ++++++++++++++++ 24 files changed, 600 insertions(+), 32 deletions(-) create mode 100644 TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_latch_post_pnr_include_netlists.v create mode 100644 TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_latch_post_pnr_wrapper_include_netlists.v create mode 100644 TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_or2_post_pnr_include_netlists.v create mode 100644 TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_or2_post_pnr_wrapper_include_netlists.v create mode 100644 TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_post_pnr_include_netlists.v create mode 100644 TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_post_pnr_wrapper_include_netlists.v create mode 100644 TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/ccff_test_post_pnr_include_netlists.v create mode 100644 TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/ccff_test_post_pnr_wrapper_include_netlists.v create mode 100644 TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/routing_test_post_pnr_include_netlists.v create mode 100644 TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/routing_test_post_pnr_wrapper_include_netlists.v create mode 100644 TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/scff_test_post_pnr_include_netlists.v create mode 100644 TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/scff_test_post_pnr_wrapper_include_netlists.v diff --git a/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_latch_post_pnr_include_netlists.v b/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_latch_post_pnr_include_netlists.v index c1b7265..3891371 100644 --- a/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_latch_post_pnr_include_netlists.v +++ b/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_latch_post_pnr_include_netlists.v @@ -17,8 +17,7 @@ `include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/common/post_pnr_fpga_cells.v" // ------ Include fabric top-level netlists ----- -//`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/FPGA1212_FC_HD_SKY_PNR/fpga_core/fpga_core_icv_in_design.pt.v" -`include "/research/ece/lnis/USERS/DARPA_ERI/Tapeout/Nov2020_Skywater/FPGA1212_FLAT_HD_SKY_PNR/fpga_top/fpga_top_icv_in_design.pt.v" +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/FPGA1212_FLAT_HD_SKY_PNR/fpga_top/fpga_top_icv_in_design.pt.v" `ifdef AUTOCHECKED_SIMULATION `include "and2_latch_output_verilog.v" diff --git a/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_latch_post_pnr_wrapper_include_netlists.v b/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_latch_post_pnr_wrapper_include_netlists.v index 8851916..3486b82 100644 --- a/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_latch_post_pnr_wrapper_include_netlists.v +++ b/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_latch_post_pnr_wrapper_include_netlists.v @@ -1,3 +1,31 @@ -version https://git-lfs.github.com/spec/v1 -oid sha256:92f909b526ee576979b1a02b23171c242ff03e62d862f06413b6a5236e5377cb -size 1478 +//------------------------------------------- +// FPGA Synthesizable Verilog Netlist +// Description: Netlist Summary +// Author: Xifan TANG +// Organization: University of Utah +// Date: Wed Nov 11 16:01:30 2020 +//------------------------------------------- +//----- Time scale ----- +`timescale 1ns / 1ps + +// ------ Include simulation defines ----- +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/prepnr/verilog_testbench/define_simulation.v" + +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/HDL/common/caravel_defines.v" + +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/HDL/common/skywater_function_verification.v" + +// ------ Include Skywater cell netlists ----- +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/common/post_pnr_fpga_cells.v" + +// ------ Include fabric top-level netlists ----- +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/FPGA1212_FLAT_HD_SKY_PNR/fpga_top/fpga_top_icv_in_design.pt.v" + +`ifdef AUTOCHECKED_SIMULATION + `include "and2_latch_output_verilog.v" +`endif + +`ifdef AUTOCHECKED_SIMULATION + `include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_latch_post_pnr_wrapper_autocheck_top_tb.v" +`endif + diff --git a/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_or2_post_pnr_include_netlists.v b/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_or2_post_pnr_include_netlists.v index 694c7f1..5e8fe9c 100644 --- a/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_or2_post_pnr_include_netlists.v +++ b/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_or2_post_pnr_include_netlists.v @@ -17,8 +17,7 @@ `include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/common/post_pnr_fpga_cells.v" // ------ Include fabric top-level netlists ----- -//`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/FPGA1212_FC_HD_SKY_PNR/fpga_core/fpga_core_icv_in_design.pt.v" -`include "/research/ece/lnis/USERS/DARPA_ERI/Tapeout/Nov2020_Skywater/FPGA1212_FLAT_HD_SKY_PNR/fpga_top/fpga_top_icv_in_design.pt.v" +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/FPGA1212_FLAT_HD_SKY_PNR/fpga_top/fpga_top_icv_in_design.pt.v" `ifdef AUTOCHECKED_SIMULATION `include "and2_or2_output_verilog.v" diff --git a/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_or2_post_pnr_wrapper_include_netlists.v b/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_or2_post_pnr_wrapper_include_netlists.v index 7354521..45cf601 100644 --- a/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_or2_post_pnr_wrapper_include_netlists.v +++ b/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_or2_post_pnr_wrapper_include_netlists.v @@ -1,3 +1,31 @@ -version https://git-lfs.github.com/spec/v1 -oid sha256:825a6a406d866bda71202b39eb897b967484f3dc7c3cf7a62aa18791e54df573 -size 1474 +//------------------------------------------- +// FPGA Synthesizable Verilog Netlist +// Description: Netlist Summary +// Author: Xifan TANG +// Organization: University of Utah +// Date: Wed Nov 11 16:01:30 2020 +//------------------------------------------- +//----- Time scale ----- +`timescale 1ns / 1ps + +// ------ Include simulation defines ----- +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/prepnr/verilog_testbench/define_simulation.v" + +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/HDL/common/caravel_defines.v" + +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/HDL/common/skywater_function_verification.v" + +// ------ Include Skywater cell netlists ----- +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/common/post_pnr_fpga_cells.v" + +// ------ Include fabric top-level netlists ----- +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/FPGA1212_FLAT_HD_SKY_PNR/fpga_top/fpga_top_icv_in_design.pt.v" + +`ifdef AUTOCHECKED_SIMULATION + `include "and2_or2_output_verilog.v" +`endif + +`ifdef AUTOCHECKED_SIMULATION + `include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_or2_post_pnr_wrapper_autocheck_top_tb.v" +`endif + diff --git a/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_post_pnr_include_netlists.v b/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_post_pnr_include_netlists.v index 24d1f7b..3bb3a24 100644 --- a/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_post_pnr_include_netlists.v +++ b/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_post_pnr_include_netlists.v @@ -17,8 +17,7 @@ `include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/common/post_pnr_fpga_cells.v" // ------ Include fabric top-level netlists ----- -//`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/FPGA1212_FC_HD_SKY_PNR/fpga_core/fpga_core_icv_in_design.pt.v" -`include "/research/ece/lnis/USERS/DARPA_ERI/Tapeout/Nov2020_Skywater/FPGA1212_FLAT_HD_SKY_PNR/fpga_top/fpga_top_icv_in_design.pt.v" +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/FPGA1212_FLAT_HD_SKY_PNR/fpga_top/fpga_top_icv_in_design.pt.v" `ifdef AUTOCHECKED_SIMULATION `include "and2_output_verilog.v" diff --git a/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_post_pnr_wrapper_include_netlists.v b/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_post_pnr_wrapper_include_netlists.v index 40df803..3db9134 100644 --- a/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_post_pnr_wrapper_include_netlists.v +++ b/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_post_pnr_wrapper_include_netlists.v @@ -1,3 +1,31 @@ -version https://git-lfs.github.com/spec/v1 -oid sha256:9f6df360605df5a436036afc2ccf3b950ce42b3c9ea396350cd4ebbb4d705b9d -size 1466 +//------------------------------------------- +// FPGA Synthesizable Verilog Netlist +// Description: Netlist Summary +// Author: Xifan TANG +// Organization: University of Utah +// Date: Wed Nov 11 16:01:30 2020 +//------------------------------------------- +//----- Time scale ----- +`timescale 1ns / 1ps + +// ------ Include simulation defines ----- +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/prepnr/verilog_testbench/define_simulation.v" + +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/HDL/common/caravel_defines.v" + +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/HDL/common/skywater_function_verification.v" + +// ------ Include Skywater cell netlists ----- +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/common/post_pnr_fpga_cells.v" + +// ------ Include fabric top-level netlists ----- +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/FPGA1212_FLAT_HD_SKY_PNR/fpga_top/fpga_top_icv_in_design.pt.v" + +`ifdef AUTOCHECKED_SIMULATION + `include "and2_output_verilog.v" +`endif + +`ifdef AUTOCHECKED_SIMULATION + `include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_post_pnr_wrapper_autocheck_top_tb.v" +`endif + diff --git a/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/ccff_test_post_pnr_include_netlists.v b/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/ccff_test_post_pnr_include_netlists.v index 0f03de9..9ae6575 100644 --- a/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/ccff_test_post_pnr_include_netlists.v +++ b/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/ccff_test_post_pnr_include_netlists.v @@ -1,3 +1,28 @@ -version https://git-lfs.github.com/spec/v1 -oid sha256:f3da10525b0dff707611379ed6ae1348c294eae1a8cd31499ce2e35dde3beaab -size 1329 +//------------------------------------------- +// FPGA Synthesizable Verilog Netlist +// Description: Netlist Summary +// Author: Xifan TANG +// Organization: University of Utah +// Date: Wed Nov 11 16:01:30 2020 +//------------------------------------------- +//----- Time scale ----- +`timescale 1ns / 1ps + +// Design parameter for FPGA I/O sizes +`define FPGA_IO_SIZE 144 + +// Design parameter for FPGA bitstream sizes +`define FPGA_BITSTREAM_SIZE 67960 + +// ------ Include simulation defines ----- +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/prepnr/verilog_testbench/define_simulation.v" + +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/HDL/common/skywater_function_verification.v" + +// ------ Include Skywater cell netlists ----- +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/common/post_pnr_fpga_cells.v" + +// ------ Include fabric top-level netlists ----- +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/FPGA1212_FLAT_HD_SKY_PNR/fpga_top/fpga_top_icv_in_design.pt.v" + +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/common/ccff_test_post_pnr.v" diff --git a/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/ccff_test_post_pnr_wrapper_include_netlists.v b/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/ccff_test_post_pnr_wrapper_include_netlists.v index 838b868..1946f9c 100644 --- a/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/ccff_test_post_pnr_wrapper_include_netlists.v +++ b/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/ccff_test_post_pnr_wrapper_include_netlists.v @@ -1,3 +1,30 @@ -version https://git-lfs.github.com/spec/v1 -oid sha256:06bb3d6a1ee52298d3ac59ad73f16132b268c013b3cb411d0dfe6f033f6aed36 -size 1488 +//------------------------------------------- +// FPGA Synthesizable Verilog Netlist +// Description: Netlist Summary +// Author: Xifan TANG +// Organization: University of Utah +// Date: Wed Nov 11 16:01:30 2020 +//------------------------------------------- +//----- Time scale ----- +`timescale 1ns / 1ps + +// Design parameter for FPGA I/O sizes +`define FPGA_IO_SIZE 144 + +// Design parameter for FPGA bitstream sizes +`define FPGA_BITSTREAM_SIZE 67960 + +// ------ Include simulation defines ----- +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/prepnr/verilog_testbench/define_simulation.v" + +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/HDL/common/caravel_defines.v" + +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/HDL/common/skywater_function_verification.v" + +// ------ Include Skywater cell netlists ----- +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/common/post_pnr_fpga_cells.v" + +// ------ Include fabric top-level netlists ----- +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/FPGA1212_FLAT_HD_SKY_PNR/fpga_top/fpga_top_icv_in_design.pt.v" + +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/ccff_test_post_pnr_wrapper.v" diff --git a/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/routing_test_post_pnr_include_netlists.v b/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/routing_test_post_pnr_include_netlists.v index 3f49591..3a4654c 100644 --- a/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/routing_test_post_pnr_include_netlists.v +++ b/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/routing_test_post_pnr_include_netlists.v @@ -17,8 +17,7 @@ `include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/common/post_pnr_fpga_cells.v" // ------ Include fabric top-level netlists ----- -//`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/FPGA1212_FC_HD_SKY_PNR/fpga_core/fpga_core_icv_in_design.pt.v" -`include "/research/ece/lnis/USERS/DARPA_ERI/Tapeout/Nov2020_Skywater/FPGA1212_FLAT_HD_SKY_PNR/fpga_top/fpga_top_icv_in_design.pt.v" +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/FPGA1212_FLAT_HD_SKY_PNR/fpga_top/fpga_top_icv_in_design.pt.v" `ifdef AUTOCHECKED_SIMULATION `include "routing_test_output_verilog.v" diff --git a/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/routing_test_post_pnr_wrapper_include_netlists.v b/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/routing_test_post_pnr_wrapper_include_netlists.v index 7139452..e4a342c 100644 --- a/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/routing_test_post_pnr_wrapper_include_netlists.v +++ b/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/routing_test_post_pnr_wrapper_include_netlists.v @@ -1,3 +1,31 @@ -version https://git-lfs.github.com/spec/v1 -oid sha256:3adff4e62fe53b8cef99dc752bab3ebc6890445d6263b3aad5fdec154f53fbcf -size 1482 +//------------------------------------------- +// FPGA Synthesizable Verilog Netlist +// Description: Netlist Summary +// Author: Xifan TANG +// Organization: University of Utah +// Date: Wed Nov 11 16:01:30 2020 +//------------------------------------------- +//----- Time scale ----- +`timescale 1ns / 1ps + +// ------ Include simulation defines ----- +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/prepnr/verilog_testbench/define_simulation.v" + +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/HDL/common/caravel_defines.v" + +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/HDL/common/skywater_function_verification.v" + +// ------ Include Skywater cell netlists ----- +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/common/post_pnr_fpga_cells.v" + +// ------ Include fabric top-level netlists ----- +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/FPGA1212_FLAT_HD_SKY_PNR/fpga_top/fpga_top_icv_in_design.pt.v" + +`ifdef AUTOCHECKED_SIMULATION + `include "routing_test_output_verilog.v" +`endif + +`ifdef AUTOCHECKED_SIMULATION + `include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/routing_test_post_pnr_wrapper_autocheck_top_tb.v" +`endif + diff --git a/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/scff_test_post_pnr_include_netlists.v b/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/scff_test_post_pnr_include_netlists.v index ae327f8..e2a7f73 100644 --- a/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/scff_test_post_pnr_include_netlists.v +++ b/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/scff_test_post_pnr_include_netlists.v @@ -1,3 +1,28 @@ -version https://git-lfs.github.com/spec/v1 -oid sha256:f25455fe75150d87bcfb386c5c953172a1712655ec1e38017d22aeb062314a6d -size 1328 +//------------------------------------------- +// FPGA Synthesizable Verilog Netlist +// Description: Netlist Summary +// Author: Xifan TANG +// Organization: University of Utah +// Date: Wed Nov 11 16:01:30 2020 +//------------------------------------------- +//----- Time scale ----- +`timescale 1ns / 1ps + +// Design parameter for FPGA I/O sizes +`define FPGA_IO_SIZE 144 + +// Design parameter for FPGA bitstream sizes +`define FPGA_SCANCHAIN_SIZE 2304 + +// ------ Include simulation defines ----- +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/prepnr/verilog_testbench/define_simulation.v" + +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/HDL/common/skywater_function_verification.v" + +// ------ Include Skywater cell netlists ----- +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/common/post_pnr_fpga_cells.v" + +// ------ Include fabric top-level netlists ----- +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/FPGA1212_FLAT_HD_SKY_PNR/fpga_top/fpga_top_icv_in_design.pt.v" + +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/common/scff_test_post_pnr.v" diff --git a/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/scff_test_post_pnr_wrapper_include_netlists.v b/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/scff_test_post_pnr_wrapper_include_netlists.v index 5694280..9b12e2c 100644 --- a/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/scff_test_post_pnr_wrapper_include_netlists.v +++ b/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/scff_test_post_pnr_wrapper_include_netlists.v @@ -1,3 +1,30 @@ -version https://git-lfs.github.com/spec/v1 -oid sha256:c3b64adf49892e8d7e7263273e76b566cb1f0922d404c224d550136d43b49178 -size 1487 +//------------------------------------------- +// FPGA Synthesizable Verilog Netlist +// Description: Netlist Summary +// Author: Xifan TANG +// Organization: University of Utah +// Date: Wed Nov 11 16:01:30 2020 +//------------------------------------------- +//----- Time scale ----- +`timescale 1ns / 1ps + +// Design parameter for FPGA I/O sizes +`define FPGA_IO_SIZE 144 + +// Design parameter for FPGA bitstream sizes +`define FPGA_SCANCHAIN_SIZE 2304 + +// ------ Include simulation defines ----- +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/prepnr/verilog_testbench/define_simulation.v" + +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/HDL/common/caravel_defines.v" + +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/HDL/common/skywater_function_verification.v" + +// ------ Include Skywater cell netlists ----- +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/common/post_pnr_fpga_cells.v" + +// ------ Include fabric top-level netlists ----- +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/FPGA1212_FLAT_HD_SKY_PNR/fpga_top/fpga_top_icv_in_design.pt.v" + +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/scff_test_post_pnr_wrapper.v" diff --git a/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_latch_post_pnr_include_netlists.v b/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_latch_post_pnr_include_netlists.v new file mode 100644 index 0000000..9d4b256 --- /dev/null +++ b/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_latch_post_pnr_include_netlists.v @@ -0,0 +1,29 @@ +//------------------------------------------- +// FPGA Synthesizable Verilog Netlist +// Description: Netlist Summary +// Author: Xifan TANG +// Organization: University of Utah +// Date: Wed Nov 11 16:01:30 2020 +//------------------------------------------- +//----- Time scale ----- +`timescale 1ns / 1ps + +// ------ Include simulation defines ----- +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/prepnr/verilog_testbench/define_simulation.v" + +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/HDL/common/skywater_function_verification.v" + +// ------ Include Skywater cell netlists ----- +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/common/post_pnr_fpga_cells.v" + +// ------ Include fabric top-level netlists ----- +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/FPGA1212_RESET_HD_SKY_PNR/fpga_top/fpga_top_icv_in_design.pt.v" + +`ifdef AUTOCHECKED_SIMULATION + `include "and2_latch_output_verilog.v" +`endif + +`ifdef AUTOCHECKED_SIMULATION + `include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_latch_post_pnr_autocheck_top_tb.v" +`endif + diff --git a/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_latch_post_pnr_wrapper_include_netlists.v b/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_latch_post_pnr_wrapper_include_netlists.v new file mode 100644 index 0000000..540d182 --- /dev/null +++ b/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_latch_post_pnr_wrapper_include_netlists.v @@ -0,0 +1,31 @@ +//------------------------------------------- +// FPGA Synthesizable Verilog Netlist +// Description: Netlist Summary +// Author: Xifan TANG +// Organization: University of Utah +// Date: Wed Nov 11 16:01:30 2020 +//------------------------------------------- +//----- Time scale ----- +`timescale 1ns / 1ps + +// ------ Include simulation defines ----- +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/prepnr/verilog_testbench/define_simulation.v" + +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/HDL/common/caravel_defines.v" + +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/HDL/common/skywater_function_verification.v" + +// ------ Include Skywater cell netlists ----- +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/common/post_pnr_fpga_cells.v" + +// ------ Include fabric top-level netlists ----- +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/FPGA1212_RESET_HD_SKY_PNR/fpga_top/fpga_top_icv_in_design.pt.v" + +`ifdef AUTOCHECKED_SIMULATION + `include "and2_latch_output_verilog.v" +`endif + +`ifdef AUTOCHECKED_SIMULATION + `include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_latch_post_pnr_wrapper_autocheck_top_tb.v" +`endif + diff --git a/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_or2_post_pnr_include_netlists.v b/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_or2_post_pnr_include_netlists.v new file mode 100644 index 0000000..7b2d42a --- /dev/null +++ b/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_or2_post_pnr_include_netlists.v @@ -0,0 +1,29 @@ +//------------------------------------------- +// FPGA Synthesizable Verilog Netlist +// Description: Netlist Summary +// Author: Xifan TANG +// Organization: University of Utah +// Date: Sun Nov 22 13:37:06 2020 +//------------------------------------------- +//----- Time scale ----- +`timescale 1ns / 1ps + +// ------ Include simulation defines ----- +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/prepnr/verilog_testbench/define_simulation.v" + +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/HDL/common/skywater_function_verification.v" + +// ------ Include Skywater cell netlists ----- +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/common/post_pnr_fpga_cells.v" + +// ------ Include fabric top-level netlists ----- +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/FPGA1212_RESET_HD_SKY_PNR/fpga_top/fpga_top_icv_in_design.pt.v" + +`ifdef AUTOCHECKED_SIMULATION + `include "and2_or2_output_verilog.v" +`endif + +`ifdef AUTOCHECKED_SIMULATION + `include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_or2_post_pnr_autocheck_top_tb.v" +`endif + diff --git a/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_or2_post_pnr_wrapper_include_netlists.v b/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_or2_post_pnr_wrapper_include_netlists.v new file mode 100644 index 0000000..cf3bb8f --- /dev/null +++ b/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_or2_post_pnr_wrapper_include_netlists.v @@ -0,0 +1,31 @@ +//------------------------------------------- +// FPGA Synthesizable Verilog Netlist +// Description: Netlist Summary +// Author: Xifan TANG +// Organization: University of Utah +// Date: Wed Nov 11 16:01:30 2020 +//------------------------------------------- +//----- Time scale ----- +`timescale 1ns / 1ps + +// ------ Include simulation defines ----- +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/prepnr/verilog_testbench/define_simulation.v" + +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/HDL/common/caravel_defines.v" + +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/HDL/common/skywater_function_verification.v" + +// ------ Include Skywater cell netlists ----- +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/common/post_pnr_fpga_cells.v" + +// ------ Include fabric top-level netlists ----- +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/FPGA1212_RESET_HD_SKY_PNR/fpga_top/fpga_top_icv_in_design.pt.v" + +`ifdef AUTOCHECKED_SIMULATION + `include "and2_or2_output_verilog.v" +`endif + +`ifdef AUTOCHECKED_SIMULATION + `include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_or2_post_pnr_wrapper_autocheck_top_tb.v" +`endif + diff --git a/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_post_pnr_include_netlists.v b/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_post_pnr_include_netlists.v new file mode 100644 index 0000000..3d84fa3 --- /dev/null +++ b/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_post_pnr_include_netlists.v @@ -0,0 +1,29 @@ +//------------------------------------------- +// FPGA Synthesizable Verilog Netlist +// Description: Netlist Summary +// Author: Xifan TANG +// Organization: University of Utah +// Date: Wed Nov 11 16:01:30 2020 +//------------------------------------------- +//----- Time scale ----- +`timescale 1ns / 1ps + +// ------ Include simulation defines ----- +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/prepnr/verilog_testbench/define_simulation.v" + +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/HDL/common/skywater_function_verification.v" + +// ------ Include Skywater cell netlists ----- +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/common/post_pnr_fpga_cells.v" + +// ------ Include fabric top-level netlists ----- +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/FPGA1212_RESET_HD_SKY_PNR/fpga_top/fpga_top_icv_in_design.pt.v" + +`ifdef AUTOCHECKED_SIMULATION + `include "and2_output_verilog.v" +`endif + +`ifdef AUTOCHECKED_SIMULATION + `include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_post_pnr_autocheck_top_tb.v" +`endif + diff --git a/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_post_pnr_wrapper_include_netlists.v b/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_post_pnr_wrapper_include_netlists.v new file mode 100644 index 0000000..4a7d602 --- /dev/null +++ b/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_post_pnr_wrapper_include_netlists.v @@ -0,0 +1,31 @@ +//------------------------------------------- +// FPGA Synthesizable Verilog Netlist +// Description: Netlist Summary +// Author: Xifan TANG +// Organization: University of Utah +// Date: Wed Nov 11 16:01:30 2020 +//------------------------------------------- +//----- Time scale ----- +`timescale 1ns / 1ps + +// ------ Include simulation defines ----- +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/prepnr/verilog_testbench/define_simulation.v" + +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/HDL/common/caravel_defines.v" + +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/HDL/common/skywater_function_verification.v" + +// ------ Include Skywater cell netlists ----- +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/common/post_pnr_fpga_cells.v" + +// ------ Include fabric top-level netlists ----- +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/FPGA1212_RESET_HD_SKY_PNR/fpga_top/fpga_top_icv_in_design.pt.v" + +`ifdef AUTOCHECKED_SIMULATION + `include "and2_output_verilog.v" +`endif + +`ifdef AUTOCHECKED_SIMULATION + `include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_post_pnr_wrapper_autocheck_top_tb.v" +`endif + diff --git a/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/ccff_test_post_pnr_include_netlists.v b/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/ccff_test_post_pnr_include_netlists.v new file mode 100644 index 0000000..b1183c5 --- /dev/null +++ b/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/ccff_test_post_pnr_include_netlists.v @@ -0,0 +1,28 @@ +//------------------------------------------- +// FPGA Synthesizable Verilog Netlist +// Description: Netlist Summary +// Author: Xifan TANG +// Organization: University of Utah +// Date: Wed Nov 11 16:01:30 2020 +//------------------------------------------- +//----- Time scale ----- +`timescale 1ns / 1ps + +// Design parameter for FPGA I/O sizes +`define FPGA_IO_SIZE 144 + +// Design parameter for FPGA bitstream sizes +`define FPGA_BITSTREAM_SIZE 78765 + +// ------ Include simulation defines ----- +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/prepnr/verilog_testbench/define_simulation.v" + +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/HDL/common/skywater_function_verification.v" + +// ------ Include Skywater cell netlists ----- +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/common/post_pnr_fpga_cells.v" + +// ------ Include fabric top-level netlists ----- +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/FPGA1212_RESET_HD_SKY_PNR/fpga_top/fpga_top_icv_in_design.pt.v" + +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/common/ccff_test_post_pnr.v" diff --git a/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/ccff_test_post_pnr_wrapper_include_netlists.v b/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/ccff_test_post_pnr_wrapper_include_netlists.v new file mode 100644 index 0000000..0b6a7f4 --- /dev/null +++ b/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/ccff_test_post_pnr_wrapper_include_netlists.v @@ -0,0 +1,30 @@ +//------------------------------------------- +// FPGA Synthesizable Verilog Netlist +// Description: Netlist Summary +// Author: Xifan TANG +// Organization: University of Utah +// Date: Wed Nov 11 16:01:30 2020 +//------------------------------------------- +//----- Time scale ----- +`timescale 1ns / 1ps + +// Design parameter for FPGA I/O sizes +`define FPGA_IO_SIZE 144 + +// Design parameter for FPGA bitstream sizes +`define FPGA_BITSTREAM_SIZE 78765 + +// ------ Include simulation defines ----- +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/prepnr/verilog_testbench/define_simulation.v" + +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/HDL/common/caravel_defines.v" + +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/HDL/common/skywater_function_verification.v" + +// ------ Include Skywater cell netlists ----- +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/common/post_pnr_fpga_cells.v" + +// ------ Include fabric top-level netlists ----- +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/FPGA1212_RESET_HD_SKY_PNR/fpga_top/fpga_top_icv_in_design.pt.v" + +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/ccff_test_post_pnr_wrapper.v" diff --git a/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/routing_test_post_pnr_include_netlists.v b/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/routing_test_post_pnr_include_netlists.v new file mode 100644 index 0000000..8acf961 --- /dev/null +++ b/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/routing_test_post_pnr_include_netlists.v @@ -0,0 +1,29 @@ +//------------------------------------------- +// FPGA Synthesizable Verilog Netlist +// Description: Netlist Summary +// Author: Xifan TANG +// Organization: University of Utah +// Date: Fri Nov 20 15:48:54 2020 +//------------------------------------------- +//----- Time scale ----- +`timescale 1ns / 1ps + +// ------ Include simulation defines ----- +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/prepnr/verilog_testbench/define_simulation.v" + +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/HDL/common/skywater_function_verification.v" + +// ------ Include Skywater cell netlists ----- +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/common/post_pnr_fpga_cells.v" + +// ------ Include fabric top-level netlists ----- +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/FPGA1212_RESET_HD_SKY_PNR/fpga_top/fpga_top_icv_in_design.pt.v" + +`ifdef AUTOCHECKED_SIMULATION + `include "routing_test_output_verilog.v" +`endif + +`ifdef AUTOCHECKED_SIMULATION + `include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/routing_test_post_pnr_autocheck_top_tb.v" +`endif + diff --git a/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/routing_test_post_pnr_wrapper_include_netlists.v b/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/routing_test_post_pnr_wrapper_include_netlists.v new file mode 100644 index 0000000..74e2be5 --- /dev/null +++ b/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/routing_test_post_pnr_wrapper_include_netlists.v @@ -0,0 +1,31 @@ +//------------------------------------------- +// FPGA Synthesizable Verilog Netlist +// Description: Netlist Summary +// Author: Xifan TANG +// Organization: University of Utah +// Date: Wed Nov 11 16:01:30 2020 +//------------------------------------------- +//----- Time scale ----- +`timescale 1ns / 1ps + +// ------ Include simulation defines ----- +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/prepnr/verilog_testbench/define_simulation.v" + +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/HDL/common/caravel_defines.v" + +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/HDL/common/skywater_function_verification.v" + +// ------ Include Skywater cell netlists ----- +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/common/post_pnr_fpga_cells.v" + +// ------ Include fabric top-level netlists ----- +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/FPGA1212_RESET_HD_SKY_PNR/fpga_top/fpga_top_icv_in_design.pt.v" + +`ifdef AUTOCHECKED_SIMULATION + `include "routing_test_output_verilog.v" +`endif + +`ifdef AUTOCHECKED_SIMULATION + `include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/routing_test_post_pnr_wrapper_autocheck_top_tb.v" +`endif + diff --git a/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/scff_test_post_pnr_include_netlists.v b/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/scff_test_post_pnr_include_netlists.v new file mode 100644 index 0000000..84b99ba --- /dev/null +++ b/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/scff_test_post_pnr_include_netlists.v @@ -0,0 +1,28 @@ +//------------------------------------------- +// FPGA Synthesizable Verilog Netlist +// Description: Netlist Summary +// Author: Xifan TANG +// Organization: University of Utah +// Date: Wed Nov 11 16:01:30 2020 +//------------------------------------------- +//----- Time scale ----- +`timescale 1ns / 1ps + +// Design parameter for FPGA I/O sizes +`define FPGA_IO_SIZE 144 + +// Design parameter for FPGA bitstream sizes +`define FPGA_SCANCHAIN_SIZE 2304 + +// ------ Include simulation defines ----- +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/prepnr/verilog_testbench/define_simulation.v" + +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/HDL/common/skywater_function_verification.v" + +// ------ Include Skywater cell netlists ----- +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/common/post_pnr_fpga_cells.v" + +// ------ Include fabric top-level netlists ----- +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/FPGA1212_RESET_HD_SKY_PNR/fpga_top/fpga_top_icv_in_design.pt.v" + +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/common/scff_test_post_pnr.v" diff --git a/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/scff_test_post_pnr_wrapper_include_netlists.v b/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/scff_test_post_pnr_wrapper_include_netlists.v new file mode 100644 index 0000000..4822ff7 --- /dev/null +++ b/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/scff_test_post_pnr_wrapper_include_netlists.v @@ -0,0 +1,30 @@ +//------------------------------------------- +// FPGA Synthesizable Verilog Netlist +// Description: Netlist Summary +// Author: Xifan TANG +// Organization: University of Utah +// Date: Wed Nov 11 16:01:30 2020 +//------------------------------------------- +//----- Time scale ----- +`timescale 1ns / 1ps + +// Design parameter for FPGA I/O sizes +`define FPGA_IO_SIZE 144 + +// Design parameter for FPGA bitstream sizes +`define FPGA_SCANCHAIN_SIZE 2304 + +// ------ Include simulation defines ----- +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/prepnr/verilog_testbench/define_simulation.v" + +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/HDL/common/caravel_defines.v" + +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/HDL/common/skywater_function_verification.v" + +// ------ Include Skywater cell netlists ----- +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/common/post_pnr_fpga_cells.v" + +// ------ Include fabric top-level netlists ----- +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/FPGA1212_RESET_HD_SKY_PNR/fpga_top/fpga_top_icv_in_design.pt.v" + +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/scff_test_post_pnr_wrapper.v" From 20cba3f5584efa58192188ae2f31ef785ca79a08 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Wed, 2 Dec 2020 13:43:06 -0700 Subject: [PATCH 02/13] [Testbench] Add testbench for post-PnR verification for FPGA with reset --- TESTBENCH/common/post_pnr_fpga_cells.v | 4 +-- .../and2_latch_post_pnr_include_netlists.v | 32 ++--------------- ..._latch_post_pnr_wrapper_include_netlists.v | 34 ++----------------- .../and2_or2_post_pnr_include_netlists.v | 32 ++--------------- ...d2_or2_post_pnr_wrapper_include_netlists.v | 34 ++----------------- .../and2_post_pnr_include_netlists.v | 32 ++--------------- .../and2_post_pnr_wrapper_include_netlists.v | 34 ++----------------- .../ccff_test_post_pnr_include_netlists.v | 31 ++--------------- ...f_test_post_pnr_wrapper_include_netlists.v | 33 ++---------------- .../routing_test_post_pnr_include_netlists.v | 32 ++--------------- ...g_test_post_pnr_wrapper_include_netlists.v | 34 ++----------------- .../scff_test_post_pnr_include_netlists.v | 31 ++--------------- ...f_test_post_pnr_wrapper_include_netlists.v | 33 ++---------------- .../and2_latch_post_pnr_include_netlists.v | 32 ++--------------- ..._latch_post_pnr_wrapper_include_netlists.v | 34 ++----------------- .../and2_or2_post_pnr_include_netlists.v | 32 ++--------------- ...d2_or2_post_pnr_wrapper_include_netlists.v | 34 ++----------------- .../and2_post_pnr_include_netlists.v | 32 ++--------------- .../and2_post_pnr_wrapper_include_netlists.v | 34 ++----------------- .../ccff_test_post_pnr_include_netlists.v | 31 ++--------------- ...f_test_post_pnr_wrapper_include_netlists.v | 33 ++---------------- .../routing_test_post_pnr_include_netlists.v | 32 ++--------------- ...g_test_post_pnr_wrapper_include_netlists.v | 34 ++----------------- .../scff_test_post_pnr_include_netlists.v | 31 ++--------------- ...f_test_post_pnr_wrapper_include_netlists.v | 33 ++---------------- 25 files changed, 74 insertions(+), 714 deletions(-) diff --git a/TESTBENCH/common/post_pnr_fpga_cells.v b/TESTBENCH/common/post_pnr_fpga_cells.v index cebd223..5bfa734 100644 --- a/TESTBENCH/common/post_pnr_fpga_cells.v +++ b/TESTBENCH/common/post_pnr_fpga_cells.v @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:4ae0fb278944fcfc542a395b998e06e1c5d473df8d7d192ff9a386f1ba596ee4 -size 7630 +oid sha256:89b4703e97499ddd03efb70998f547462d7a8fa5d27e2c2d2af132b2050e195d +size 7942 diff --git a/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_latch_post_pnr_include_netlists.v b/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_latch_post_pnr_include_netlists.v index 3891371..e40f43e 100644 --- a/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_latch_post_pnr_include_netlists.v +++ b/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_latch_post_pnr_include_netlists.v @@ -1,29 +1,3 @@ -//------------------------------------------- -// FPGA Synthesizable Verilog Netlist -// Description: Netlist Summary -// Author: Xifan TANG -// Organization: University of Utah -// Date: Wed Nov 11 16:01:30 2020 -//------------------------------------------- -//----- Time scale ----- -`timescale 1ns / 1ps - -// ------ Include simulation defines ----- -`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/prepnr/verilog_testbench/define_simulation.v" - -`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/HDL/common/skywater_function_verification.v" - -// ------ Include Skywater cell netlists ----- -`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/common/post_pnr_fpga_cells.v" - -// ------ Include fabric top-level netlists ----- -`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/FPGA1212_FLAT_HD_SKY_PNR/fpga_top/fpga_top_icv_in_design.pt.v" - -`ifdef AUTOCHECKED_SIMULATION - `include "and2_latch_output_verilog.v" -`endif - -`ifdef AUTOCHECKED_SIMULATION - `include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_latch_post_pnr_autocheck_top_tb.v" -`endif - +version https://git-lfs.github.com/spec/v1 +oid sha256:3140f41d14f1046308ebd07b6527c4ec781ab3c18e63b237aba9b435b9c044de +size 1239 diff --git a/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_latch_post_pnr_wrapper_include_netlists.v b/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_latch_post_pnr_wrapper_include_netlists.v index 3486b82..2781b69 100644 --- a/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_latch_post_pnr_wrapper_include_netlists.v +++ b/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_latch_post_pnr_wrapper_include_netlists.v @@ -1,31 +1,3 @@ -//------------------------------------------- -// FPGA Synthesizable Verilog Netlist -// Description: Netlist Summary -// Author: Xifan TANG -// Organization: University of Utah -// Date: Wed Nov 11 16:01:30 2020 -//------------------------------------------- -//----- Time scale ----- -`timescale 1ns / 1ps - -// ------ Include simulation defines ----- -`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/prepnr/verilog_testbench/define_simulation.v" - -`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/HDL/common/caravel_defines.v" - -`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/HDL/common/skywater_function_verification.v" - -// ------ Include Skywater cell netlists ----- -`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/common/post_pnr_fpga_cells.v" - -// ------ Include fabric top-level netlists ----- -`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/FPGA1212_FLAT_HD_SKY_PNR/fpga_top/fpga_top_icv_in_design.pt.v" - -`ifdef AUTOCHECKED_SIMULATION - `include "and2_latch_output_verilog.v" -`endif - -`ifdef AUTOCHECKED_SIMULATION - `include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_latch_post_pnr_wrapper_autocheck_top_tb.v" -`endif - +version https://git-lfs.github.com/spec/v1 +oid sha256:9d2003a31c42e9558a77f3891b6284affed509e22d38dbb150f475db968c5f8e +size 1343 diff --git a/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_or2_post_pnr_include_netlists.v b/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_or2_post_pnr_include_netlists.v index 5e8fe9c..731e086 100644 --- a/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_or2_post_pnr_include_netlists.v +++ b/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_or2_post_pnr_include_netlists.v @@ -1,29 +1,3 @@ -//------------------------------------------- -// FPGA Synthesizable Verilog Netlist -// Description: Netlist Summary -// Author: Xifan TANG -// Organization: University of Utah -// Date: Sun Nov 22 13:37:06 2020 -//------------------------------------------- -//----- Time scale ----- -`timescale 1ns / 1ps - -// ------ Include simulation defines ----- -`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/prepnr/verilog_testbench/define_simulation.v" - -`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/HDL/common/skywater_function_verification.v" - -// ------ Include Skywater cell netlists ----- -`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/common/post_pnr_fpga_cells.v" - -// ------ Include fabric top-level netlists ----- -`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/FPGA1212_FLAT_HD_SKY_PNR/fpga_top/fpga_top_icv_in_design.pt.v" - -`ifdef AUTOCHECKED_SIMULATION - `include "and2_or2_output_verilog.v" -`endif - -`ifdef AUTOCHECKED_SIMULATION - `include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_or2_post_pnr_autocheck_top_tb.v" -`endif - +version https://git-lfs.github.com/spec/v1 +oid sha256:6395e2f33f3dcb8dad1c92fa0659bc4b842b3495d683add90e50d942e28b6ef1 +size 1235 diff --git a/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_or2_post_pnr_wrapper_include_netlists.v b/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_or2_post_pnr_wrapper_include_netlists.v index 45cf601..f9dd991 100644 --- a/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_or2_post_pnr_wrapper_include_netlists.v +++ b/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_or2_post_pnr_wrapper_include_netlists.v @@ -1,31 +1,3 @@ -//------------------------------------------- -// FPGA Synthesizable Verilog Netlist -// Description: Netlist Summary -// Author: Xifan TANG -// Organization: University of Utah -// Date: Wed Nov 11 16:01:30 2020 -//------------------------------------------- -//----- Time scale ----- -`timescale 1ns / 1ps - -// ------ Include simulation defines ----- -`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/prepnr/verilog_testbench/define_simulation.v" - -`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/HDL/common/caravel_defines.v" - -`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/HDL/common/skywater_function_verification.v" - -// ------ Include Skywater cell netlists ----- -`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/common/post_pnr_fpga_cells.v" - -// ------ Include fabric top-level netlists ----- -`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/FPGA1212_FLAT_HD_SKY_PNR/fpga_top/fpga_top_icv_in_design.pt.v" - -`ifdef AUTOCHECKED_SIMULATION - `include "and2_or2_output_verilog.v" -`endif - -`ifdef AUTOCHECKED_SIMULATION - `include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_or2_post_pnr_wrapper_autocheck_top_tb.v" -`endif - +version https://git-lfs.github.com/spec/v1 +oid sha256:ec87f38ebc0e4f795a0a72b760f6181288ef6f7cc72f7708ec21d77a1ea8c28d +size 1339 diff --git a/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_post_pnr_include_netlists.v b/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_post_pnr_include_netlists.v index 3bb3a24..bf40134 100644 --- a/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_post_pnr_include_netlists.v +++ b/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_post_pnr_include_netlists.v @@ -1,29 +1,3 @@ -//------------------------------------------- -// FPGA Synthesizable Verilog Netlist -// Description: Netlist Summary -// Author: Xifan TANG -// Organization: University of Utah -// Date: Wed Nov 11 16:01:30 2020 -//------------------------------------------- -//----- Time scale ----- -`timescale 1ns / 1ps - -// ------ Include simulation defines ----- -`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/prepnr/verilog_testbench/define_simulation.v" - -`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/HDL/common/skywater_function_verification.v" - -// ------ Include Skywater cell netlists ----- -`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/common/post_pnr_fpga_cells.v" - -// ------ Include fabric top-level netlists ----- -`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/FPGA1212_FLAT_HD_SKY_PNR/fpga_top/fpga_top_icv_in_design.pt.v" - -`ifdef AUTOCHECKED_SIMULATION - `include "and2_output_verilog.v" -`endif - -`ifdef AUTOCHECKED_SIMULATION - `include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_post_pnr_autocheck_top_tb.v" -`endif - +version https://git-lfs.github.com/spec/v1 +oid sha256:0168df4405980eb7be0f0231735794d86c514199126d0941f043ba38905d0c4f +size 1227 diff --git a/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_post_pnr_wrapper_include_netlists.v b/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_post_pnr_wrapper_include_netlists.v index 3db9134..1e21a4f 100644 --- a/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_post_pnr_wrapper_include_netlists.v +++ b/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_post_pnr_wrapper_include_netlists.v @@ -1,31 +1,3 @@ -//------------------------------------------- -// FPGA Synthesizable Verilog Netlist -// Description: Netlist Summary -// Author: Xifan TANG -// Organization: University of Utah -// Date: Wed Nov 11 16:01:30 2020 -//------------------------------------------- -//----- Time scale ----- -`timescale 1ns / 1ps - -// ------ Include simulation defines ----- -`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/prepnr/verilog_testbench/define_simulation.v" - -`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/HDL/common/caravel_defines.v" - -`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/HDL/common/skywater_function_verification.v" - -// ------ Include Skywater cell netlists ----- -`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/common/post_pnr_fpga_cells.v" - -// ------ Include fabric top-level netlists ----- -`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/FPGA1212_FLAT_HD_SKY_PNR/fpga_top/fpga_top_icv_in_design.pt.v" - -`ifdef AUTOCHECKED_SIMULATION - `include "and2_output_verilog.v" -`endif - -`ifdef AUTOCHECKED_SIMULATION - `include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_post_pnr_wrapper_autocheck_top_tb.v" -`endif - +version https://git-lfs.github.com/spec/v1 +oid sha256:3fc3f03b263ff267b9543c09f338222e9e9950978915a10a16825decd8deab4c +size 1331 diff --git a/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/ccff_test_post_pnr_include_netlists.v b/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/ccff_test_post_pnr_include_netlists.v index 9ae6575..704f7a0 100644 --- a/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/ccff_test_post_pnr_include_netlists.v +++ b/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/ccff_test_post_pnr_include_netlists.v @@ -1,28 +1,3 @@ -//------------------------------------------- -// FPGA Synthesizable Verilog Netlist -// Description: Netlist Summary -// Author: Xifan TANG -// Organization: University of Utah -// Date: Wed Nov 11 16:01:30 2020 -//------------------------------------------- -//----- Time scale ----- -`timescale 1ns / 1ps - -// Design parameter for FPGA I/O sizes -`define FPGA_IO_SIZE 144 - -// Design parameter for FPGA bitstream sizes -`define FPGA_BITSTREAM_SIZE 67960 - -// ------ Include simulation defines ----- -`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/prepnr/verilog_testbench/define_simulation.v" - -`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/HDL/common/skywater_function_verification.v" - -// ------ Include Skywater cell netlists ----- -`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/common/post_pnr_fpga_cells.v" - -// ------ Include fabric top-level netlists ----- -`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/FPGA1212_FLAT_HD_SKY_PNR/fpga_top/fpga_top_icv_in_design.pt.v" - -`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/common/ccff_test_post_pnr.v" +version https://git-lfs.github.com/spec/v1 +oid sha256:c67a41b0721d08ca8fbc02d2b9c105717cfd1cf8f596c392ce97a253315d5e3e +size 1194 diff --git a/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/ccff_test_post_pnr_wrapper_include_netlists.v b/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/ccff_test_post_pnr_wrapper_include_netlists.v index 1946f9c..386cac1 100644 --- a/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/ccff_test_post_pnr_wrapper_include_netlists.v +++ b/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/ccff_test_post_pnr_wrapper_include_netlists.v @@ -1,30 +1,3 @@ -//------------------------------------------- -// FPGA Synthesizable Verilog Netlist -// Description: Netlist Summary -// Author: Xifan TANG -// Organization: University of Utah -// Date: Wed Nov 11 16:01:30 2020 -//------------------------------------------- -//----- Time scale ----- -`timescale 1ns / 1ps - -// Design parameter for FPGA I/O sizes -`define FPGA_IO_SIZE 144 - -// Design parameter for FPGA bitstream sizes -`define FPGA_BITSTREAM_SIZE 67960 - -// ------ Include simulation defines ----- -`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/prepnr/verilog_testbench/define_simulation.v" - -`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/HDL/common/caravel_defines.v" - -`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/HDL/common/skywater_function_verification.v" - -// ------ Include Skywater cell netlists ----- -`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/common/post_pnr_fpga_cells.v" - -// ------ Include fabric top-level netlists ----- -`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/FPGA1212_FLAT_HD_SKY_PNR/fpga_top/fpga_top_icv_in_design.pt.v" - -`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/ccff_test_post_pnr_wrapper.v" +version https://git-lfs.github.com/spec/v1 +oid sha256:f5fe62252b7eae6cd437a4fde8a18dcdcc61e629ab847b6bffa2d8d0d8dc60b4 +size 1353 diff --git a/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/routing_test_post_pnr_include_netlists.v b/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/routing_test_post_pnr_include_netlists.v index 3a4654c..79c523c 100644 --- a/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/routing_test_post_pnr_include_netlists.v +++ b/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/routing_test_post_pnr_include_netlists.v @@ -1,29 +1,3 @@ -//------------------------------------------- -// FPGA Synthesizable Verilog Netlist -// Description: Netlist Summary -// Author: Xifan TANG -// Organization: University of Utah -// Date: Fri Nov 20 15:48:54 2020 -//------------------------------------------- -//----- Time scale ----- -`timescale 1ns / 1ps - -// ------ Include simulation defines ----- -`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/prepnr/verilog_testbench/define_simulation.v" - -`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/HDL/common/skywater_function_verification.v" - -// ------ Include Skywater cell netlists ----- -`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/common/post_pnr_fpga_cells.v" - -// ------ Include fabric top-level netlists ----- -`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/FPGA1212_FLAT_HD_SKY_PNR/fpga_top/fpga_top_icv_in_design.pt.v" - -`ifdef AUTOCHECKED_SIMULATION - `include "routing_test_output_verilog.v" -`endif - -`ifdef AUTOCHECKED_SIMULATION - `include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/routing_test_post_pnr_autocheck_top_tb.v" -`endif - +version https://git-lfs.github.com/spec/v1 +oid sha256:9a2a5d743a10211cd55496c15a559690e5a09a328edcb0942d901ba5e5df48b8 +size 1243 diff --git a/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/routing_test_post_pnr_wrapper_include_netlists.v b/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/routing_test_post_pnr_wrapper_include_netlists.v index e4a342c..e440cab 100644 --- a/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/routing_test_post_pnr_wrapper_include_netlists.v +++ b/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/routing_test_post_pnr_wrapper_include_netlists.v @@ -1,31 +1,3 @@ -//------------------------------------------- -// FPGA Synthesizable Verilog Netlist -// Description: Netlist Summary -// Author: Xifan TANG -// Organization: University of Utah -// Date: Wed Nov 11 16:01:30 2020 -//------------------------------------------- -//----- Time scale ----- -`timescale 1ns / 1ps - -// ------ Include simulation defines ----- -`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/prepnr/verilog_testbench/define_simulation.v" - -`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/HDL/common/caravel_defines.v" - -`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/HDL/common/skywater_function_verification.v" - -// ------ Include Skywater cell netlists ----- -`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/common/post_pnr_fpga_cells.v" - -// ------ Include fabric top-level netlists ----- -`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/FPGA1212_FLAT_HD_SKY_PNR/fpga_top/fpga_top_icv_in_design.pt.v" - -`ifdef AUTOCHECKED_SIMULATION - `include "routing_test_output_verilog.v" -`endif - -`ifdef AUTOCHECKED_SIMULATION - `include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/routing_test_post_pnr_wrapper_autocheck_top_tb.v" -`endif - +version https://git-lfs.github.com/spec/v1 +oid sha256:a18b7fab25c736e3d465a51353672d7bc5dc7e693145fee2837afc1d11b78289 +size 1347 diff --git a/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/scff_test_post_pnr_include_netlists.v b/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/scff_test_post_pnr_include_netlists.v index e2a7f73..3b63c78 100644 --- a/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/scff_test_post_pnr_include_netlists.v +++ b/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/scff_test_post_pnr_include_netlists.v @@ -1,28 +1,3 @@ -//------------------------------------------- -// FPGA Synthesizable Verilog Netlist -// Description: Netlist Summary -// Author: Xifan TANG -// Organization: University of Utah -// Date: Wed Nov 11 16:01:30 2020 -//------------------------------------------- -//----- Time scale ----- -`timescale 1ns / 1ps - -// Design parameter for FPGA I/O sizes -`define FPGA_IO_SIZE 144 - -// Design parameter for FPGA bitstream sizes -`define FPGA_SCANCHAIN_SIZE 2304 - -// ------ Include simulation defines ----- -`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/prepnr/verilog_testbench/define_simulation.v" - -`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/HDL/common/skywater_function_verification.v" - -// ------ Include Skywater cell netlists ----- -`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/common/post_pnr_fpga_cells.v" - -// ------ Include fabric top-level netlists ----- -`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/FPGA1212_FLAT_HD_SKY_PNR/fpga_top/fpga_top_icv_in_design.pt.v" - -`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/common/scff_test_post_pnr.v" +version https://git-lfs.github.com/spec/v1 +oid sha256:0f73b27a645609f040e12548f221f24cce4054ed6bff9d74664a2f3c6dc70bb5 +size 1193 diff --git a/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/scff_test_post_pnr_wrapper_include_netlists.v b/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/scff_test_post_pnr_wrapper_include_netlists.v index 9b12e2c..8783bb0 100644 --- a/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/scff_test_post_pnr_wrapper_include_netlists.v +++ b/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/scff_test_post_pnr_wrapper_include_netlists.v @@ -1,30 +1,3 @@ -//------------------------------------------- -// FPGA Synthesizable Verilog Netlist -// Description: Netlist Summary -// Author: Xifan TANG -// Organization: University of Utah -// Date: Wed Nov 11 16:01:30 2020 -//------------------------------------------- -//----- Time scale ----- -`timescale 1ns / 1ps - -// Design parameter for FPGA I/O sizes -`define FPGA_IO_SIZE 144 - -// Design parameter for FPGA bitstream sizes -`define FPGA_SCANCHAIN_SIZE 2304 - -// ------ Include simulation defines ----- -`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/prepnr/verilog_testbench/define_simulation.v" - -`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/HDL/common/caravel_defines.v" - -`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/HDL/common/skywater_function_verification.v" - -// ------ Include Skywater cell netlists ----- -`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/common/post_pnr_fpga_cells.v" - -// ------ Include fabric top-level netlists ----- -`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/FPGA1212_FLAT_HD_SKY_PNR/fpga_top/fpga_top_icv_in_design.pt.v" - -`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/scff_test_post_pnr_wrapper.v" +version https://git-lfs.github.com/spec/v1 +oid sha256:5dd9f4ffe36c1f5ac05ff49da29ec5541913f2e2efce7cf7a4c7e1cb9120264e +size 1352 diff --git a/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_latch_post_pnr_include_netlists.v b/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_latch_post_pnr_include_netlists.v index 9d4b256..ca377b7 100644 --- a/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_latch_post_pnr_include_netlists.v +++ b/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_latch_post_pnr_include_netlists.v @@ -1,29 +1,3 @@ -//------------------------------------------- -// FPGA Synthesizable Verilog Netlist -// Description: Netlist Summary -// Author: Xifan TANG -// Organization: University of Utah -// Date: Wed Nov 11 16:01:30 2020 -//------------------------------------------- -//----- Time scale ----- -`timescale 1ns / 1ps - -// ------ Include simulation defines ----- -`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/prepnr/verilog_testbench/define_simulation.v" - -`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/HDL/common/skywater_function_verification.v" - -// ------ Include Skywater cell netlists ----- -`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/common/post_pnr_fpga_cells.v" - -// ------ Include fabric top-level netlists ----- -`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/FPGA1212_RESET_HD_SKY_PNR/fpga_top/fpga_top_icv_in_design.pt.v" - -`ifdef AUTOCHECKED_SIMULATION - `include "and2_latch_output_verilog.v" -`endif - -`ifdef AUTOCHECKED_SIMULATION - `include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_latch_post_pnr_autocheck_top_tb.v" -`endif - +version https://git-lfs.github.com/spec/v1 +oid sha256:32e7a27472ef1501fec8765f8a7beb44ab61c84c514a5f63801840cfdec20eb7 +size 1272 diff --git a/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_latch_post_pnr_wrapper_include_netlists.v b/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_latch_post_pnr_wrapper_include_netlists.v index 540d182..5d0b93a 100644 --- a/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_latch_post_pnr_wrapper_include_netlists.v +++ b/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_latch_post_pnr_wrapper_include_netlists.v @@ -1,31 +1,3 @@ -//------------------------------------------- -// FPGA Synthesizable Verilog Netlist -// Description: Netlist Summary -// Author: Xifan TANG -// Organization: University of Utah -// Date: Wed Nov 11 16:01:30 2020 -//------------------------------------------- -//----- Time scale ----- -`timescale 1ns / 1ps - -// ------ Include simulation defines ----- -`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/prepnr/verilog_testbench/define_simulation.v" - -`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/HDL/common/caravel_defines.v" - -`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/HDL/common/skywater_function_verification.v" - -// ------ Include Skywater cell netlists ----- -`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/common/post_pnr_fpga_cells.v" - -// ------ Include fabric top-level netlists ----- -`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/FPGA1212_RESET_HD_SKY_PNR/fpga_top/fpga_top_icv_in_design.pt.v" - -`ifdef AUTOCHECKED_SIMULATION - `include "and2_latch_output_verilog.v" -`endif - -`ifdef AUTOCHECKED_SIMULATION - `include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_latch_post_pnr_wrapper_autocheck_top_tb.v" -`endif - +version https://git-lfs.github.com/spec/v1 +oid sha256:c2067d21d21d3666ebe52b8de512bf06020ab395b65304387709e166e1d43a23 +size 1376 diff --git a/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_or2_post_pnr_include_netlists.v b/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_or2_post_pnr_include_netlists.v index 7b2d42a..b93bc4a 100644 --- a/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_or2_post_pnr_include_netlists.v +++ b/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_or2_post_pnr_include_netlists.v @@ -1,29 +1,3 @@ -//------------------------------------------- -// FPGA Synthesizable Verilog Netlist -// Description: Netlist Summary -// Author: Xifan TANG -// Organization: University of Utah -// Date: Sun Nov 22 13:37:06 2020 -//------------------------------------------- -//----- Time scale ----- -`timescale 1ns / 1ps - -// ------ Include simulation defines ----- -`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/prepnr/verilog_testbench/define_simulation.v" - -`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/HDL/common/skywater_function_verification.v" - -// ------ Include Skywater cell netlists ----- -`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/common/post_pnr_fpga_cells.v" - -// ------ Include fabric top-level netlists ----- -`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/FPGA1212_RESET_HD_SKY_PNR/fpga_top/fpga_top_icv_in_design.pt.v" - -`ifdef AUTOCHECKED_SIMULATION - `include "and2_or2_output_verilog.v" -`endif - -`ifdef AUTOCHECKED_SIMULATION - `include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_or2_post_pnr_autocheck_top_tb.v" -`endif - +version https://git-lfs.github.com/spec/v1 +oid sha256:ee2934fe5c3048ac3655a3cc6213f176d83c3495aef7428904ad229f39d424a0 +size 1268 diff --git a/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_or2_post_pnr_wrapper_include_netlists.v b/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_or2_post_pnr_wrapper_include_netlists.v index cf3bb8f..c87613f 100644 --- a/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_or2_post_pnr_wrapper_include_netlists.v +++ b/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_or2_post_pnr_wrapper_include_netlists.v @@ -1,31 +1,3 @@ -//------------------------------------------- -// FPGA Synthesizable Verilog Netlist -// Description: Netlist Summary -// Author: Xifan TANG -// Organization: University of Utah -// Date: Wed Nov 11 16:01:30 2020 -//------------------------------------------- -//----- Time scale ----- -`timescale 1ns / 1ps - -// ------ Include simulation defines ----- -`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/prepnr/verilog_testbench/define_simulation.v" - -`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/HDL/common/caravel_defines.v" - -`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/HDL/common/skywater_function_verification.v" - -// ------ Include Skywater cell netlists ----- -`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/common/post_pnr_fpga_cells.v" - -// ------ Include fabric top-level netlists ----- -`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/FPGA1212_RESET_HD_SKY_PNR/fpga_top/fpga_top_icv_in_design.pt.v" - -`ifdef AUTOCHECKED_SIMULATION - `include "and2_or2_output_verilog.v" -`endif - -`ifdef AUTOCHECKED_SIMULATION - `include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_or2_post_pnr_wrapper_autocheck_top_tb.v" -`endif - +version https://git-lfs.github.com/spec/v1 +oid sha256:1707e2d2da1c2eba04f17079d9d9144b71be24bf19b9d99c83ceefc5d46d6afd +size 1372 diff --git a/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_post_pnr_include_netlists.v b/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_post_pnr_include_netlists.v index 3d84fa3..0fe63cd 100644 --- a/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_post_pnr_include_netlists.v +++ b/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_post_pnr_include_netlists.v @@ -1,29 +1,3 @@ -//------------------------------------------- -// FPGA Synthesizable Verilog Netlist -// Description: Netlist Summary -// Author: Xifan TANG -// Organization: University of Utah -// Date: Wed Nov 11 16:01:30 2020 -//------------------------------------------- -//----- Time scale ----- -`timescale 1ns / 1ps - -// ------ Include simulation defines ----- -`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/prepnr/verilog_testbench/define_simulation.v" - -`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/HDL/common/skywater_function_verification.v" - -// ------ Include Skywater cell netlists ----- -`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/common/post_pnr_fpga_cells.v" - -// ------ Include fabric top-level netlists ----- -`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/FPGA1212_RESET_HD_SKY_PNR/fpga_top/fpga_top_icv_in_design.pt.v" - -`ifdef AUTOCHECKED_SIMULATION - `include "and2_output_verilog.v" -`endif - -`ifdef AUTOCHECKED_SIMULATION - `include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_post_pnr_autocheck_top_tb.v" -`endif - +version https://git-lfs.github.com/spec/v1 +oid sha256:35a893d7106b66061ef6c45570ba26c5eb2cc31c1ba667193e01003e1a3c8294 +size 1260 diff --git a/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_post_pnr_wrapper_include_netlists.v b/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_post_pnr_wrapper_include_netlists.v index 4a7d602..d6c6337 100644 --- a/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_post_pnr_wrapper_include_netlists.v +++ b/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_post_pnr_wrapper_include_netlists.v @@ -1,31 +1,3 @@ -//------------------------------------------- -// FPGA Synthesizable Verilog Netlist -// Description: Netlist Summary -// Author: Xifan TANG -// Organization: University of Utah -// Date: Wed Nov 11 16:01:30 2020 -//------------------------------------------- -//----- Time scale ----- -`timescale 1ns / 1ps - -// ------ Include simulation defines ----- -`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/prepnr/verilog_testbench/define_simulation.v" - -`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/HDL/common/caravel_defines.v" - -`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/HDL/common/skywater_function_verification.v" - -// ------ Include Skywater cell netlists ----- -`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/common/post_pnr_fpga_cells.v" - -// ------ Include fabric top-level netlists ----- -`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/FPGA1212_RESET_HD_SKY_PNR/fpga_top/fpga_top_icv_in_design.pt.v" - -`ifdef AUTOCHECKED_SIMULATION - `include "and2_output_verilog.v" -`endif - -`ifdef AUTOCHECKED_SIMULATION - `include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_post_pnr_wrapper_autocheck_top_tb.v" -`endif - +version https://git-lfs.github.com/spec/v1 +oid sha256:3cfd0b49a75dbcc308f61212ed162d2c74c9343bffe35d78cb39fa553507b559 +size 1364 diff --git a/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/ccff_test_post_pnr_include_netlists.v b/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/ccff_test_post_pnr_include_netlists.v index b1183c5..cabcdba 100644 --- a/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/ccff_test_post_pnr_include_netlists.v +++ b/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/ccff_test_post_pnr_include_netlists.v @@ -1,28 +1,3 @@ -//------------------------------------------- -// FPGA Synthesizable Verilog Netlist -// Description: Netlist Summary -// Author: Xifan TANG -// Organization: University of Utah -// Date: Wed Nov 11 16:01:30 2020 -//------------------------------------------- -//----- Time scale ----- -`timescale 1ns / 1ps - -// Design parameter for FPGA I/O sizes -`define FPGA_IO_SIZE 144 - -// Design parameter for FPGA bitstream sizes -`define FPGA_BITSTREAM_SIZE 78765 - -// ------ Include simulation defines ----- -`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/prepnr/verilog_testbench/define_simulation.v" - -`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/HDL/common/skywater_function_verification.v" - -// ------ Include Skywater cell netlists ----- -`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/common/post_pnr_fpga_cells.v" - -// ------ Include fabric top-level netlists ----- -`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/FPGA1212_RESET_HD_SKY_PNR/fpga_top/fpga_top_icv_in_design.pt.v" - -`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/common/ccff_test_post_pnr.v" +version https://git-lfs.github.com/spec/v1 +oid sha256:a6da97988b4c39f03920feae95a4f07c9b382d4be3687a656eaef8f75126d615 +size 1211 diff --git a/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/ccff_test_post_pnr_wrapper_include_netlists.v b/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/ccff_test_post_pnr_wrapper_include_netlists.v index 0b6a7f4..222f122 100644 --- a/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/ccff_test_post_pnr_wrapper_include_netlists.v +++ b/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/ccff_test_post_pnr_wrapper_include_netlists.v @@ -1,30 +1,3 @@ -//------------------------------------------- -// FPGA Synthesizable Verilog Netlist -// Description: Netlist Summary -// Author: Xifan TANG -// Organization: University of Utah -// Date: Wed Nov 11 16:01:30 2020 -//------------------------------------------- -//----- Time scale ----- -`timescale 1ns / 1ps - -// Design parameter for FPGA I/O sizes -`define FPGA_IO_SIZE 144 - -// Design parameter for FPGA bitstream sizes -`define FPGA_BITSTREAM_SIZE 78765 - -// ------ Include simulation defines ----- -`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/prepnr/verilog_testbench/define_simulation.v" - -`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/HDL/common/caravel_defines.v" - -`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/HDL/common/skywater_function_verification.v" - -// ------ Include Skywater cell netlists ----- -`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/common/post_pnr_fpga_cells.v" - -// ------ Include fabric top-level netlists ----- -`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/FPGA1212_RESET_HD_SKY_PNR/fpga_top/fpga_top_icv_in_design.pt.v" - -`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/ccff_test_post_pnr_wrapper.v" +version https://git-lfs.github.com/spec/v1 +oid sha256:cedd3fbe2dc2158e46da28ab3b630b45571f7015b89f29391b092bb3860fdbcc +size 1386 diff --git a/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/routing_test_post_pnr_include_netlists.v b/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/routing_test_post_pnr_include_netlists.v index 8acf961..a37047e 100644 --- a/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/routing_test_post_pnr_include_netlists.v +++ b/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/routing_test_post_pnr_include_netlists.v @@ -1,29 +1,3 @@ -//------------------------------------------- -// FPGA Synthesizable Verilog Netlist -// Description: Netlist Summary -// Author: Xifan TANG -// Organization: University of Utah -// Date: Fri Nov 20 15:48:54 2020 -//------------------------------------------- -//----- Time scale ----- -`timescale 1ns / 1ps - -// ------ Include simulation defines ----- -`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/prepnr/verilog_testbench/define_simulation.v" - -`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/HDL/common/skywater_function_verification.v" - -// ------ Include Skywater cell netlists ----- -`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/common/post_pnr_fpga_cells.v" - -// ------ Include fabric top-level netlists ----- -`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/FPGA1212_RESET_HD_SKY_PNR/fpga_top/fpga_top_icv_in_design.pt.v" - -`ifdef AUTOCHECKED_SIMULATION - `include "routing_test_output_verilog.v" -`endif - -`ifdef AUTOCHECKED_SIMULATION - `include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/routing_test_post_pnr_autocheck_top_tb.v" -`endif - +version https://git-lfs.github.com/spec/v1 +oid sha256:7dbfbefcae891ea972982503967a7dc838843bd86ff134873a38da4a1c4b4a1f +size 1276 diff --git a/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/routing_test_post_pnr_wrapper_include_netlists.v b/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/routing_test_post_pnr_wrapper_include_netlists.v index 74e2be5..d5bbb87 100644 --- a/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/routing_test_post_pnr_wrapper_include_netlists.v +++ b/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/routing_test_post_pnr_wrapper_include_netlists.v @@ -1,31 +1,3 @@ -//------------------------------------------- -// FPGA Synthesizable Verilog Netlist -// Description: Netlist Summary -// Author: Xifan TANG -// Organization: University of Utah -// Date: Wed Nov 11 16:01:30 2020 -//------------------------------------------- -//----- Time scale ----- -`timescale 1ns / 1ps - -// ------ Include simulation defines ----- -`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/prepnr/verilog_testbench/define_simulation.v" - -`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/HDL/common/caravel_defines.v" - -`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/HDL/common/skywater_function_verification.v" - -// ------ Include Skywater cell netlists ----- -`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/common/post_pnr_fpga_cells.v" - -// ------ Include fabric top-level netlists ----- -`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/FPGA1212_RESET_HD_SKY_PNR/fpga_top/fpga_top_icv_in_design.pt.v" - -`ifdef AUTOCHECKED_SIMULATION - `include "routing_test_output_verilog.v" -`endif - -`ifdef AUTOCHECKED_SIMULATION - `include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/routing_test_post_pnr_wrapper_autocheck_top_tb.v" -`endif - +version https://git-lfs.github.com/spec/v1 +oid sha256:b5388c9df5e22b40644563abea84f530445b17a43673499bcfcb9680acf5aa66 +size 1380 diff --git a/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/scff_test_post_pnr_include_netlists.v b/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/scff_test_post_pnr_include_netlists.v index 84b99ba..f24381f 100644 --- a/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/scff_test_post_pnr_include_netlists.v +++ b/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/scff_test_post_pnr_include_netlists.v @@ -1,28 +1,3 @@ -//------------------------------------------- -// FPGA Synthesizable Verilog Netlist -// Description: Netlist Summary -// Author: Xifan TANG -// Organization: University of Utah -// Date: Wed Nov 11 16:01:30 2020 -//------------------------------------------- -//----- Time scale ----- -`timescale 1ns / 1ps - -// Design parameter for FPGA I/O sizes -`define FPGA_IO_SIZE 144 - -// Design parameter for FPGA bitstream sizes -`define FPGA_SCANCHAIN_SIZE 2304 - -// ------ Include simulation defines ----- -`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/prepnr/verilog_testbench/define_simulation.v" - -`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/HDL/common/skywater_function_verification.v" - -// ------ Include Skywater cell netlists ----- -`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/common/post_pnr_fpga_cells.v" - -// ------ Include fabric top-level netlists ----- -`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/FPGA1212_RESET_HD_SKY_PNR/fpga_top/fpga_top_icv_in_design.pt.v" - -`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/common/scff_test_post_pnr.v" +version https://git-lfs.github.com/spec/v1 +oid sha256:31aeb268b252e6defeec5d00e777ec417acc65697a5dbdad6b73d211db85be36 +size 1210 diff --git a/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/scff_test_post_pnr_wrapper_include_netlists.v b/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/scff_test_post_pnr_wrapper_include_netlists.v index 4822ff7..73ead6b 100644 --- a/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/scff_test_post_pnr_wrapper_include_netlists.v +++ b/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/scff_test_post_pnr_wrapper_include_netlists.v @@ -1,30 +1,3 @@ -//------------------------------------------- -// FPGA Synthesizable Verilog Netlist -// Description: Netlist Summary -// Author: Xifan TANG -// Organization: University of Utah -// Date: Wed Nov 11 16:01:30 2020 -//------------------------------------------- -//----- Time scale ----- -`timescale 1ns / 1ps - -// Design parameter for FPGA I/O sizes -`define FPGA_IO_SIZE 144 - -// Design parameter for FPGA bitstream sizes -`define FPGA_SCANCHAIN_SIZE 2304 - -// ------ Include simulation defines ----- -`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/prepnr/verilog_testbench/define_simulation.v" - -`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/HDL/common/caravel_defines.v" - -`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/HDL/common/skywater_function_verification.v" - -// ------ Include Skywater cell netlists ----- -`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/common/post_pnr_fpga_cells.v" - -// ------ Include fabric top-level netlists ----- -`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/FPGA1212_RESET_HD_SKY_PNR/fpga_top/fpga_top_icv_in_design.pt.v" - -`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/scff_test_post_pnr_wrapper.v" +version https://git-lfs.github.com/spec/v1 +oid sha256:e7a163317878eb9295a02108efc9a8e7c3f4a5485aa05e03bd29b40445d88d88 +size 1385 From 06731e092e82e1bae3693fcf230b63610110a506 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Wed, 2 Dec 2020 13:46:40 -0700 Subject: [PATCH 03/13] [Arch] Patch reset port name to be consistent with post-PnR netlist --- ...ter_scan_chain_caravel_io_skywater130nm_fdhd_cc_openfpga.xml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/ARCH/openfpga_arch_template/k4_frac_N8_reset_softadder_register_scan_chain_caravel_io_skywater130nm_fdhd_cc_openfpga.xml b/ARCH/openfpga_arch_template/k4_frac_N8_reset_softadder_register_scan_chain_caravel_io_skywater130nm_fdhd_cc_openfpga.xml index 97989e2..06558f6 100644 --- a/ARCH/openfpga_arch_template/k4_frac_N8_reset_softadder_register_scan_chain_caravel_io_skywater130nm_fdhd_cc_openfpga.xml +++ b/ARCH/openfpga_arch_template/k4_frac_N8_reset_softadder_register_scan_chain_caravel_io_skywater130nm_fdhd_cc_openfpga.xml @@ -230,7 +230,7 @@ - + From 4875b2de95224b85aa2ef19816f94fa1f069b822 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Wed, 2 Dec 2020 14:02:18 -0700 Subject: [PATCH 04/13] [HDL] Patch pin assignment names to be consistent with post-PnR netlists --- HDL/common/caravel_wrapper_pin_assignment_v1.1.json | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/HDL/common/caravel_wrapper_pin_assignment_v1.1.json b/HDL/common/caravel_wrapper_pin_assignment_v1.1.json index abbff5b..63cf9d2 100644 --- a/HDL/common/caravel_wrapper_pin_assignment_v1.1.json +++ b/HDL/common/caravel_wrapper_pin_assignment_v1.1.json @@ -46,13 +46,13 @@ "caravel_pin_index": ["10:4"] }, { - "fpga_pin_type": "prog_reset", + "fpga_pin_type": "pReset", "fpga_pin_index": "0:0", "caravel_pin_type": ["input"], "caravel_pin_index": ["3:3"] }, { - "fpga_pin_type": "reset", + "fpga_pin_type": "Reset", "fpga_pin_index": "0:0", "caravel_pin_type": ["input"], "caravel_pin_index": ["2:2"] From 6814b3bb601dc69ed217ab6c46dd21746c9268fd Mon Sep 17 00:00:00 2001 From: tangxifan Date: Wed, 2 Dec 2020 15:22:19 -0700 Subject: [PATCH 05/13] [Testbench] Now ccff and scff testbench template have multiple versions corresponding to the FPGA variants --- .../{ccff_test_post_pnr.v => ccff_test_post_pnr_v1.0.v} | 0 TESTBENCH/common/ccff_test_post_pnr_v1.1.v | 3 +++ .../{scff_test_post_pnr.v => scff_test_post_pnr_v1.0.v} | 0 TESTBENCH/common/scff_test_post_pnr_v1.1.v | 3 +++ .../verilog_testbench/ccff_test_post_pnr_include_netlists.v | 4 ++-- .../verilog_testbench/scff_test_post_pnr_include_netlists.v | 4 ++-- .../verilog_testbench/ccff_test_post_pnr_include_netlists.v | 4 ++-- .../verilog_testbench/scff_test_post_pnr_include_netlists.v | 4 ++-- 8 files changed, 14 insertions(+), 8 deletions(-) rename TESTBENCH/common/{ccff_test_post_pnr.v => ccff_test_post_pnr_v1.0.v} (100%) create mode 100644 TESTBENCH/common/ccff_test_post_pnr_v1.1.v rename TESTBENCH/common/{scff_test_post_pnr.v => scff_test_post_pnr_v1.0.v} (100%) create mode 100644 TESTBENCH/common/scff_test_post_pnr_v1.1.v diff --git a/TESTBENCH/common/ccff_test_post_pnr.v b/TESTBENCH/common/ccff_test_post_pnr_v1.0.v similarity index 100% rename from TESTBENCH/common/ccff_test_post_pnr.v rename to TESTBENCH/common/ccff_test_post_pnr_v1.0.v diff --git a/TESTBENCH/common/ccff_test_post_pnr_v1.1.v b/TESTBENCH/common/ccff_test_post_pnr_v1.1.v new file mode 100644 index 0000000..9cc4a49 --- /dev/null +++ b/TESTBENCH/common/ccff_test_post_pnr_v1.1.v @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:5a78db8f3ba441cbbc0797772dc72de1cf80ffac9dfbe9b50c5ac5e95607dfd6 +size 6013 diff --git a/TESTBENCH/common/scff_test_post_pnr.v b/TESTBENCH/common/scff_test_post_pnr_v1.0.v similarity index 100% rename from TESTBENCH/common/scff_test_post_pnr.v rename to TESTBENCH/common/scff_test_post_pnr_v1.0.v diff --git a/TESTBENCH/common/scff_test_post_pnr_v1.1.v b/TESTBENCH/common/scff_test_post_pnr_v1.1.v new file mode 100644 index 0000000..44cd7ff --- /dev/null +++ b/TESTBENCH/common/scff_test_post_pnr_v1.1.v @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:1f819fbbdf65501141b3563a9d022851c1cf0473a39702906a81ab5e87605b4f +size 5871 diff --git a/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/ccff_test_post_pnr_include_netlists.v b/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/ccff_test_post_pnr_include_netlists.v index 704f7a0..30a2005 100644 --- a/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/ccff_test_post_pnr_include_netlists.v +++ b/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/ccff_test_post_pnr_include_netlists.v @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:c67a41b0721d08ca8fbc02d2b9c105717cfd1cf8f596c392ce97a253315d5e3e -size 1194 +oid sha256:5b1dbfb9b52a4e87e544773b46710111d2a53c24922de3e10eefd82c7d280f0b +size 1199 diff --git a/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/scff_test_post_pnr_include_netlists.v b/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/scff_test_post_pnr_include_netlists.v index 3b63c78..1edcd07 100644 --- a/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/scff_test_post_pnr_include_netlists.v +++ b/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/scff_test_post_pnr_include_netlists.v @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:0f73b27a645609f040e12548f221f24cce4054ed6bff9d74664a2f3c6dc70bb5 -size 1193 +oid sha256:98d430047e77dd1e59a84fd4fdc368b229f29e27ae0354657e166db51e2f56a3 +size 1198 diff --git a/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/ccff_test_post_pnr_include_netlists.v b/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/ccff_test_post_pnr_include_netlists.v index cabcdba..114dfab 100644 --- a/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/ccff_test_post_pnr_include_netlists.v +++ b/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/ccff_test_post_pnr_include_netlists.v @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:a6da97988b4c39f03920feae95a4f07c9b382d4be3687a656eaef8f75126d615 -size 1211 +oid sha256:fe32ecd75d97fefe74d1e1e01713ed38098f845cc37aad617b161e64a05a4e36 +size 1216 diff --git a/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/scff_test_post_pnr_include_netlists.v b/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/scff_test_post_pnr_include_netlists.v index f24381f..3c6c896 100644 --- a/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/scff_test_post_pnr_include_netlists.v +++ b/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/scff_test_post_pnr_include_netlists.v @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:31aeb268b252e6defeec5d00e777ec417acc65697a5dbdad6b73d211db85be36 -size 1210 +oid sha256:8cb80347043fd1a8fab62f8963bf174668951941f6a60e3ba6db9c2a0f439b07 +size 1215 From a19c9bdbdaeb20de47b6d00f462ae6f037bedaeb Mon Sep 17 00:00:00 2001 From: tangxifan Date: Wed, 2 Dec 2020 15:30:54 -0700 Subject: [PATCH 06/13] [CI] Add CCFF and SCFF testbench conversion to CI test --- .github/workflows/quick_test.sh | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/.github/workflows/quick_test.sh b/.github/workflows/quick_test.sh index aff8aec..04813c4 100755 --- a/.github/workflows/quick_test.sh +++ b/.github/workflows/quick_test.sh @@ -24,3 +24,11 @@ python3 TESTBENCH/common/generate_post_pnr_testbenches.py --pre_pnr_testbench_di python3 TESTBENCH/common/generate_post_pnr_testbenches.py --pre_pnr_testbench_dir_name ./TESTBENCH/k4_N8_softadder_caravel_io_FPGA_12x12_fdhd_cc --pin_assignment_file ./HDL/common/caravel_wrapper_pin_assignment_v1.0.json python3 TESTBENCH/common/generate_post_pnr_testbenches.py --pre_pnr_testbench_dir_name ./TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_fdhd_cc --pin_assignment_file ./HDL/common/caravel_wrapper_pin_assignment_v1.1.json python3 TESTBENCH/common/generate_post_pnr_testbenches.py --pre_pnr_testbench_dir_name ./TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_customhd_cc --pin_assignment_file ./HDL/common/caravel_wrapper_pin_assignment_v1.1.json + +# Generate wrapper testbenches from template tesbenches for configuration chain tests +python3 TESTBENCH/common/post_pnr_wrapper_testbench_converter.py --post_pnr_testbench TESTBENCH/common/ccff_test_post_pnr_v1.0.v --pin_assignment_file HDL/common/caravel_wrapper_pin_assignment_v1.0.json --wrapper_testbench TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/ccff_test_post_pnr_wrapper.v +python3 TESTBENCH/common/post_pnr_wrapper_testbench_converter.py --post_pnr_testbench TESTBENCH/common/ccff_test_post_pnr_v1.1.v --pin_assignment_file HDL/common/caravel_wrapper_pin_assignment_v1.1.json --wrapper_testbench TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/ccff_test_post_pnr_wrapper.v + +# Generate wrapper testbenches from template tesbenches for scan chain tests +python3 TESTBENCH/common/post_pnr_wrapper_testbench_converter.py --post_pnr_testbench TESTBENCH/common/scff_test_post_pnr_v1.0.v --pin_assignment_file HDL/common/caravel_wrapper_pin_assignment_v1.0.json --wrapper_testbench TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/scff_test_post_pnr_wrapper.v +python3 TESTBENCH/common/post_pnr_wrapper_testbench_converter.py --post_pnr_testbench TESTBENCH/common/scff_test_post_pnr_v1.1.v --pin_assignment_file HDL/common/caravel_wrapper_pin_assignment_v1.1.json --wrapper_testbench TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/scff_test_post_pnr_wrapper.v From b966829566a5765ed09bbb2c6947aa95b3eabdab Mon Sep 17 00:00:00 2001 From: tangxifan Date: Wed, 2 Dec 2020 17:50:23 -0700 Subject: [PATCH 07/13] [Script] Force a fixed number of clock cycles in simulation to avoid false-positive --- SCRIPT/openfpga_simulation_setting/efpga_12x12_sim_openfpga.xml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/SCRIPT/openfpga_simulation_setting/efpga_12x12_sim_openfpga.xml b/SCRIPT/openfpga_simulation_setting/efpga_12x12_sim_openfpga.xml index 92cf793..d9f8401 100644 --- a/SCRIPT/openfpga_simulation_setting/efpga_12x12_sim_openfpga.xml +++ b/SCRIPT/openfpga_simulation_setting/efpga_12x12_sim_openfpga.xml @@ -11,7 +11,7 @@ As the FPGA core does not share the clock with Caravel SoC the actual clock frequency could be higher --> - + - +