diff --git a/.github/workflows/quick_test.sh b/.github/workflows/quick_test.sh
index aff8aec..d6d92dc 100755
--- a/.github/workflows/quick_test.sh
+++ b/.github/workflows/quick_test.sh
@@ -20,7 +20,13 @@ python3 HDL/common/wrapper_lines_generator.py --template_netlist HDL/common/cara
 ##############################################
 # Generate post-PnR testbenches
 python3 TESTBENCH/common/generate_post_pnr_testbenches.py --pre_pnr_testbench_dir_name ./TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc --pin_assignment_file ./HDL/common/caravel_wrapper_pin_assignment_v1.0.json
-python3 TESTBENCH/common/generate_post_pnr_testbenches.py --pre_pnr_testbench_dir_name ./TESTBENCH/k4_N8_reset_caravel_io_FPGA_12x12_fdhd_cc --pin_assignment_file ./HDL/common/caravel_wrapper_pin_assignment_v1.1.json
-python3 TESTBENCH/common/generate_post_pnr_testbenches.py --pre_pnr_testbench_dir_name ./TESTBENCH/k4_N8_softadder_caravel_io_FPGA_12x12_fdhd_cc --pin_assignment_file ./HDL/common/caravel_wrapper_pin_assignment_v1.0.json
 python3 TESTBENCH/common/generate_post_pnr_testbenches.py --pre_pnr_testbench_dir_name ./TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_fdhd_cc --pin_assignment_file ./HDL/common/caravel_wrapper_pin_assignment_v1.1.json
 python3 TESTBENCH/common/generate_post_pnr_testbenches.py --pre_pnr_testbench_dir_name ./TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_customhd_cc --pin_assignment_file ./HDL/common/caravel_wrapper_pin_assignment_v1.1.json
+
+# Generate wrapper testbenches from template tesbenches for configuration chain tests
+python3 TESTBENCH/common/post_pnr_wrapper_testbench_converter.py --post_pnr_testbench TESTBENCH/common/ccff_test_post_pnr_v1.0.v --pin_assignment_file HDL/common/caravel_wrapper_pin_assignment_v1.0.json --wrapper_testbench TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/ccff_test_post_pnr_wrapper.v
+python3 TESTBENCH/common/post_pnr_wrapper_testbench_converter.py --post_pnr_testbench TESTBENCH/common/ccff_test_post_pnr_v1.1.v --pin_assignment_file HDL/common/caravel_wrapper_pin_assignment_v1.1.json --wrapper_testbench TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/ccff_test_post_pnr_wrapper.v
+
+# Generate wrapper testbenches from template tesbenches for scan chain tests
+python3 TESTBENCH/common/post_pnr_wrapper_testbench_converter.py --post_pnr_testbench TESTBENCH/common/scff_test_post_pnr_v1.0.v --pin_assignment_file HDL/common/caravel_wrapper_pin_assignment_v1.0.json --wrapper_testbench TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/scff_test_post_pnr_wrapper.v
+python3 TESTBENCH/common/post_pnr_wrapper_testbench_converter.py --post_pnr_testbench TESTBENCH/common/scff_test_post_pnr_v1.1.v --pin_assignment_file HDL/common/caravel_wrapper_pin_assignment_v1.1.json --wrapper_testbench TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/scff_test_post_pnr_wrapper.v
diff --git a/ARCH/openfpga_arch_template/k4_frac_N8_reset_softadder_register_scan_chain_caravel_io_skywater130nm_fdhd_cc_openfpga.xml b/ARCH/openfpga_arch_template/k4_frac_N8_reset_softadder_register_scan_chain_caravel_io_skywater130nm_fdhd_cc_openfpga.xml
index 97989e2..06558f6 100644
--- a/ARCH/openfpga_arch_template/k4_frac_N8_reset_softadder_register_scan_chain_caravel_io_skywater130nm_fdhd_cc_openfpga.xml
+++ b/ARCH/openfpga_arch_template/k4_frac_N8_reset_softadder_register_scan_chain_caravel_io_skywater130nm_fdhd_cc_openfpga.xml
@@ -230,7 +230,7 @@
   </direct_connection>
   <tile_annotations>
     <global_port name="clk" tile_port="clb.clk" is_clock="true" default_val="0"/>
-    <global_port name="reset" tile_port="clb.reset" is_reset="true" default_val="1"/>
+    <global_port name="Reset" tile_port="clb.reset" is_reset="true" default_val="1"/>
   </tile_annotations>
   <pb_type_annotations>
     <!-- physical pb_type binding in complex block IO -->
diff --git a/HDL/common/caravel_wrapper_pin_assignment_v1.1.json b/HDL/common/caravel_wrapper_pin_assignment_v1.1.json
index abbff5b..63cf9d2 100644
--- a/HDL/common/caravel_wrapper_pin_assignment_v1.1.json
+++ b/HDL/common/caravel_wrapper_pin_assignment_v1.1.json
@@ -46,13 +46,13 @@
       "caravel_pin_index": ["10:4"]
     }, 
     {
-      "fpga_pin_type": "prog_reset", 
+      "fpga_pin_type": "pReset", 
       "fpga_pin_index": "0:0", 
       "caravel_pin_type": ["input"],
       "caravel_pin_index": ["3:3"]
     },
     {
-      "fpga_pin_type": "reset", 
+      "fpga_pin_type": "Reset", 
       "fpga_pin_index": "0:0", 
       "caravel_pin_type": ["input"],
       "caravel_pin_index": ["2:2"]
diff --git a/MSIM/common/run_post_pnr_msim_test.py b/MSIM/common/run_post_pnr_msim_test.py
index 54d5e25..83942d4 100644
--- a/MSIM/common/run_post_pnr_msim_test.py
+++ b/MSIM/common/run_post_pnr_msim_test.py
@@ -121,16 +121,24 @@ for line in vsim_log_file:
   # Check errors from self-testing testbench output
   if line.startswith("# Simulation finish with") :
     num_sim_err = int(re.findall("# Simulation finish with(\s+)(\d+) errors", line)[0][1])
-    num_err_lines_found = num_err_lines_found + 1
+    num_err_lines_found += 1
     if (0 < num_sim_err) : 
       logging.error("Simulation failed with " + str(num_sim_err) + " errors!\n")
       # Add to total errors
-      num_err = num_err + num_sim_err
+      num_err += num_sim_err
+  if line.startswith("# Simulation Failed with") :
+    print (line)
+    num_sim_err = int(re.findall("# Simulation Failed with(\s+)(\d+) error\(s\)", line)[0][1])
+    num_err_lines_found += 1
+    if (0 < num_sim_err) : 
+      logging.error("Simulation failed with " + str(num_sim_err) + " errors!\n")
+      # Add to total errors
+      num_err += num_sim_err
   # Check total errors by Modelsim
   if line.startswith("# Errors:") :
     num_msim_err = int(re.findall("# Errors:(\s)(\d+),", line)[0][1])
-    num_err_lines_found = num_err_lines_found + 1
-    num_err = num_err + num_msim_err
+    num_err_lines_found += 1
+    num_err += num_msim_err
 
 vsim_log_file.close()
 
diff --git a/SCRIPT/skywater_openfpga_task/k4_N8_reset_caravel_cc_fdhd_12x12/generate_fabric/config/task_template.conf b/SCRIPT/skywater_openfpga_task/k4_N8_reset_caravel_cc_fdhd_12x12/generate_fabric/config/task_template.conf
deleted file mode 100644
index 9c68de0..0000000
--- a/SCRIPT/skywater_openfpga_task/k4_N8_reset_caravel_cc_fdhd_12x12/generate_fabric/config/task_template.conf
+++ /dev/null
@@ -1,38 +0,0 @@
-# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
-# Configuration file for running experiments
-# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
-# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs
-# Each job execute fpga_flow script on combination of architecture & benchmark
-# timeout_each_job is timeout for each job
-# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
-
-[GENERAL]
-run_engine=openfpga_shell
-power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml
-power_analysis = true
-spice_output=false
-verilog_output=true
-timeout_each_job = 1*60
-fpga_flow=yosys_vpr
-
-[OpenFPGA_SHELL]
-openfpga_shell_template=${SKYWATER_OPENFPGA_HOME}/SCRIPT/openfpga_shell_script/skywater_generate_fabric_using_key_example_script.openfpga
-openfpga_arch_file=${SKYWATER_OPENFPGA_HOME}/ARCH/openfpga_arch/k4_frac_N8_reset_register_scan_chain_caravel_io_skywater130nm_fdhd_cc_openfpga.xml
-openfpga_sim_setting_file=${SKYWATER_OPENFPGA_HOME}/SCRIPT/openfpga_simulation_setting/efpga_12x12_sim_openfpga.xml
-openfpga_vpr_device_layout=12x12
-openfpga_vpr_route_chan_width=40
-openfpga_verilog_output_dir=${SKYWATER_OPENFPGA_HOME}/HDL/k4_N8_reset_caravel_io_FPGA_12x12_fdhd_cc
-openfpga_sdc_output_dir=${SKYWATER_OPENFPGA_HOME}/SDC/k4_N8_reset_caravel_io_FPGA_12x12_fdhd_cc
-external_fabric_key_file=${SKYWATER_OPENFPGA_HOME}/ARCH/fabric_key/fabric_key_12x12.xml
-
-[ARCHITECTURES]
-arch0=${SKYWATER_OPENFPGA_HOME}/ARCH/vpr_arch/k4_frac_N8_tileable_reset_register_scan_chain_nonLR_caravel_io_skywater130nm.xml
-
-[BENCHMARKS]
-bench0=${SKYWATER_OPENFPGA_HOME}/BENCHMARK/and2/and2.v
-
-[SYNTHESIS_PARAM]
-bench0_top = and2
-
-[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
-#end_flow_with_test=
diff --git a/SCRIPT/skywater_openfpga_task/k4_N8_reset_caravel_cc_fdhd_12x12/generate_sdc/config/task_template.conf b/SCRIPT/skywater_openfpga_task/k4_N8_reset_caravel_cc_fdhd_12x12/generate_sdc/config/task_template.conf
deleted file mode 100644
index 32618a5..0000000
--- a/SCRIPT/skywater_openfpga_task/k4_N8_reset_caravel_cc_fdhd_12x12/generate_sdc/config/task_template.conf
+++ /dev/null
@@ -1,37 +0,0 @@
-# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
-# Configuration file for running experiments
-# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
-# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs
-# Each job execute fpga_flow script on combination of architecture & benchmark
-# timeout_each_job is timeout for each job
-# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
-
-[GENERAL]
-run_engine=openfpga_shell
-power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml
-power_analysis = true
-spice_output=false
-verilog_output=true
-timeout_each_job = 1*60
-fpga_flow=yosys_vpr
-
-[OpenFPGA_SHELL]
-openfpga_shell_template=${SKYWATER_OPENFPGA_HOME}/SCRIPT/openfpga_shell_script/skywater_generate_sdc_using_key_example_script.openfpga
-openfpga_arch_file=${SKYWATER_OPENFPGA_HOME}/ARCH/openfpga_arch/k4_frac_N8_reset_register_scan_chain_caravel_io_skywater130nm_fdhd_cc_openfpga.xml
-openfpga_sim_setting_file=${SKYWATER_OPENFPGA_HOME}/SCRIPT/openfpga_simulation_setting/efpga_12x12_sim_openfpga.xml
-openfpga_vpr_device_layout=12x12
-openfpga_vpr_route_chan_width=40
-openfpga_sdc_output_dir=${SKYWATER_OPENFPGA_HOME}/SDC/k4_N8_reset_caravel_io_FPGA_12x12_fdhd_cc
-external_fabric_key_file=${SKYWATER_OPENFPGA_HOME}/ARCH/fabric_key/fabric_key_12x12.xml
-
-[ARCHITECTURES]
-arch0=${SKYWATER_OPENFPGA_HOME}/ARCH/vpr_arch/k4_frac_N8_tileable_reset_register_scan_chain_nonLR_caravel_io_skywater130nm.xml
-
-[BENCHMARKS]
-bench0=${SKYWATER_OPENFPGA_HOME}/BENCHMARK/and2/and2.v
-
-[SYNTHESIS_PARAM]
-bench0_top = and2
-
-[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
-#end_flow_with_test=
diff --git a/SCRIPT/skywater_openfpga_task/k4_N8_reset_caravel_cc_fdhd_12x12/generate_testbench/config/task_template.conf b/SCRIPT/skywater_openfpga_task/k4_N8_reset_caravel_cc_fdhd_12x12/generate_testbench/config/task_template.conf
deleted file mode 100644
index 6fe9240..0000000
--- a/SCRIPT/skywater_openfpga_task/k4_N8_reset_caravel_cc_fdhd_12x12/generate_testbench/config/task_template.conf
+++ /dev/null
@@ -1,54 +0,0 @@
-# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
-# Configuration file for running experiments
-# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
-# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs
-# Each job execute fpga_flow script on combination of architecture & benchmark
-# timeout_each_job is timeout for each job
-# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
-
-[GENERAL]
-run_engine=openfpga_shell
-power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml
-power_analysis = true
-spice_output=false
-verilog_output=true
-timeout_each_job = 1*60
-fpga_flow=yosys_vpr
-
-[OpenFPGA_SHELL]
-openfpga_shell_template=${SKYWATER_OPENFPGA_HOME}/SCRIPT/openfpga_shell_script/skywater_generate_testbench_using_key_example_script.openfpga
-openfpga_arch_file=${SKYWATER_OPENFPGA_HOME}/ARCH/openfpga_arch/k4_frac_N8_reset_register_scan_chain_caravel_io_skywater130nm_fdhd_cc_openfpga.xml
-openfpga_sim_setting_file=${SKYWATER_OPENFPGA_HOME}/SCRIPT/openfpga_simulation_setting/efpga_12x12_sim_openfpga.xml
-openfpga_vpr_device_layout=12x12
-openfpga_vpr_route_chan_width=40
-openfpga_verilog_output_dir=${SKYWATER_OPENFPGA_HOME}/TESTBENCH/k4_N8_reset_caravel_io_FPGA_12x12_fdhd_cc/prepnr
-openfpga_fabric_verilog_netlist=${SKYWATER_OPENFPGA_HOME}/HDL/k4_N8_reset_caravel_io_FPGA_12x12_fdhd_cc/SRC/fabric_netlists.v
-external_fabric_key_file=${SKYWATER_OPENFPGA_HOME}/ARCH/fabric_key/fabric_key_12x12.xml
-
-[ARCHITECTURES]
-arch0=${SKYWATER_OPENFPGA_HOME}/ARCH/vpr_arch/k4_frac_N8_tileable_reset_register_scan_chain_nonLR_caravel_io_skywater130nm.xml
-
-[BENCHMARKS]
-bench0=${SKYWATER_OPENFPGA_HOME}/BENCHMARK/and2/and2.v
-bench1=${SKYWATER_OPENFPGA_HOME}/BENCHMARK/and2_latch/and2_latch.v
-bench2=${SKYWATER_OPENFPGA_HOME}/BENCHMARK/bin2bcd/bin2bcd.v
-bench3=${SKYWATER_OPENFPGA_HOME}/BENCHMARK/counter/counter.v
-bench4=${SKYWATER_OPENFPGA_HOME}/BENCHMARK/routing_test/routing_test.v
-# RS decoder needs 1.5k LUT4, exceeding device capacity
-#bench5=${SKYWATER_OPENFPGA_HOME}/BENCHMARK/rs_decoder/rtl/rs_decoder.v
-bench6=${SKYWATER_OPENFPGA_HOME}/BENCHMARK/simon_bit_serial/rtl/*.v
-bench7=${SKYWATER_OPENFPGA_HOME}/BENCHMARK/and2_or2/and2_or2.v
-
-[SYNTHESIS_PARAM]
-bench0_top = and2
-bench1_top = and2_latch
-bench2_top = bin2bcd
-bench3_top = counter
-bench4_top = routing_test
-# RS decoder needs 1.5k LUT4, exceeding device capacity
-#bench5_top = rs_decoder_top
-bench6_top = top_module
-bench7_top = and2_or2
-
-[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
-#end_flow_with_test=
diff --git a/SCRIPT/skywater_openfpga_task/k4_N8_softadder_caravel_cc_fdhd_12x12/generate_fabric/config/task_template.conf b/SCRIPT/skywater_openfpga_task/k4_N8_softadder_caravel_cc_fdhd_12x12/generate_fabric/config/task_template.conf
deleted file mode 100644
index 3c1d0fc..0000000
--- a/SCRIPT/skywater_openfpga_task/k4_N8_softadder_caravel_cc_fdhd_12x12/generate_fabric/config/task_template.conf
+++ /dev/null
@@ -1,38 +0,0 @@
-# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
-# Configuration file for running experiments
-# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
-# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs
-# Each job execute fpga_flow script on combination of architecture & benchmark
-# timeout_each_job is timeout for each job
-# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
-
-[GENERAL]
-run_engine=openfpga_shell
-power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml
-power_analysis = true
-spice_output=false
-verilog_output=true
-timeout_each_job = 1*60
-fpga_flow=yosys_vpr
-
-[OpenFPGA_SHELL]
-openfpga_shell_template=${SKYWATER_OPENFPGA_HOME}/SCRIPT/openfpga_shell_script/skywater_generate_fabric_using_key_example_script.openfpga
-openfpga_arch_file=${SKYWATER_OPENFPGA_HOME}/ARCH/openfpga_arch/k4_frac_N8_softadder_register_scan_chain_caravel_io_skywater130nm_fdhd_cc_openfpga.xml
-openfpga_sim_setting_file=${SKYWATER_OPENFPGA_HOME}/SCRIPT/openfpga_simulation_setting/efpga_12x12_sim_openfpga.xml
-openfpga_vpr_device_layout=12x12
-openfpga_vpr_route_chan_width=40
-openfpga_verilog_output_dir=${SKYWATER_OPENFPGA_HOME}/HDL/k4_N8_softadder_caravel_io_FPGA_12x12_fdhd_cc
-openfpga_sdc_output_dir=${SKYWATER_OPENFPGA_HOME}/SDC/k4_N8_softadder_caravel_io_FPGA_12x12_fdhd_cc
-external_fabric_key_file=${SKYWATER_OPENFPGA_HOME}/ARCH/fabric_key/fabric_key_12x12.xml
-
-[ARCHITECTURES]
-arch0=${SKYWATER_OPENFPGA_HOME}/ARCH/vpr_arch/k4_frac_N8_tileable_softadder_register_scan_chain_nonLR_caravel_io_skywater130nm.xml
-
-[BENCHMARKS]
-bench0=${SKYWATER_OPENFPGA_HOME}/BENCHMARK/and2/and2.v
-
-[SYNTHESIS_PARAM]
-bench0_top = and2
-
-[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
-#end_flow_with_test=
diff --git a/SCRIPT/skywater_openfpga_task/k4_N8_softadder_caravel_cc_fdhd_12x12/generate_sdc/config/task_template.conf b/SCRIPT/skywater_openfpga_task/k4_N8_softadder_caravel_cc_fdhd_12x12/generate_sdc/config/task_template.conf
deleted file mode 100644
index bd6bd45..0000000
--- a/SCRIPT/skywater_openfpga_task/k4_N8_softadder_caravel_cc_fdhd_12x12/generate_sdc/config/task_template.conf
+++ /dev/null
@@ -1,37 +0,0 @@
-# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
-# Configuration file for running experiments
-# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
-# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs
-# Each job execute fpga_flow script on combination of architecture & benchmark
-# timeout_each_job is timeout for each job
-# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
-
-[GENERAL]
-run_engine=openfpga_shell
-power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml
-power_analysis = true
-spice_output=false
-verilog_output=true
-timeout_each_job = 1*60
-fpga_flow=yosys_vpr
-
-[OpenFPGA_SHELL]
-openfpga_shell_template=${SKYWATER_OPENFPGA_HOME}/SCRIPT/openfpga_shell_script/skywater_generate_sdc_using_key_example_script.openfpga
-openfpga_arch_file=${SKYWATER_OPENFPGA_HOME}/ARCH/openfpga_arch/k4_frac_N8_softadder_register_scan_chain_caravel_io_skywater130nm_fdhd_cc_openfpga.xml
-openfpga_sim_setting_file=${SKYWATER_OPENFPGA_HOME}/SCRIPT/openfpga_simulation_setting/efpga_12x12_sim_openfpga.xml
-openfpga_vpr_device_layout=12x12
-openfpga_vpr_route_chan_width=40
-openfpga_sdc_output_dir=${SKYWATER_OPENFPGA_HOME}/SDC/k4_N8_softadder_caravel_io_FPGA_12x12_fdhd_cc
-external_fabric_key_file=${SKYWATER_OPENFPGA_HOME}/ARCH/fabric_key/fabric_key_12x12.xml
-
-[ARCHITECTURES]
-arch0=${SKYWATER_OPENFPGA_HOME}/ARCH/vpr_arch/k4_frac_N8_tileable_softadder_register_scan_chain_nonLR_caravel_io_skywater130nm.xml
-
-[BENCHMARKS]
-bench0=${SKYWATER_OPENFPGA_HOME}/BENCHMARK/and2/and2.v
-
-[SYNTHESIS_PARAM]
-bench0_top = and2
-
-[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
-#end_flow_with_test=
diff --git a/SCRIPT/skywater_openfpga_task/k4_N8_softadder_caravel_cc_fdhd_12x12/generate_testbench/config/task_template.conf b/SCRIPT/skywater_openfpga_task/k4_N8_softadder_caravel_cc_fdhd_12x12/generate_testbench/config/task_template.conf
deleted file mode 100644
index 69f70a1..0000000
--- a/SCRIPT/skywater_openfpga_task/k4_N8_softadder_caravel_cc_fdhd_12x12/generate_testbench/config/task_template.conf
+++ /dev/null
@@ -1,54 +0,0 @@
-# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
-# Configuration file for running experiments
-# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
-# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs
-# Each job execute fpga_flow script on combination of architecture & benchmark
-# timeout_each_job is timeout for each job
-# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
-
-[GENERAL]
-run_engine=openfpga_shell
-power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml
-power_analysis = true
-spice_output=false
-verilog_output=true
-timeout_each_job = 1*60
-fpga_flow=yosys_vpr
-
-[OpenFPGA_SHELL]
-openfpga_shell_template=${SKYWATER_OPENFPGA_HOME}/SCRIPT/openfpga_shell_script/skywater_generate_testbench_using_key_example_script.openfpga
-openfpga_arch_file=${SKYWATER_OPENFPGA_HOME}/ARCH/openfpga_arch/k4_frac_N8_softadder_register_scan_chain_caravel_io_skywater130nm_fdhd_cc_openfpga.xml
-openfpga_sim_setting_file=${SKYWATER_OPENFPGA_HOME}/SCRIPT/openfpga_simulation_setting/efpga_12x12_sim_openfpga.xml
-openfpga_vpr_device_layout=12x12
-openfpga_vpr_route_chan_width=40
-openfpga_verilog_output_dir=${SKYWATER_OPENFPGA_HOME}/TESTBENCH/k4_N8_softadder_caravel_io_FPGA_12x12_fdhd_cc/prepnr
-openfpga_fabric_verilog_netlist=${SKYWATER_OPENFPGA_HOME}/HDL/k4_N8_softadder_caravel_io_FPGA_12x12_fdhd_cc/SRC/fabric_netlists.v
-external_fabric_key_file=${SKYWATER_OPENFPGA_HOME}/ARCH/fabric_key/fabric_key_12x12.xml
-
-[ARCHITECTURES]
-arch0=${SKYWATER_OPENFPGA_HOME}/ARCH/vpr_arch/k4_frac_N8_tileable_softadder_register_scan_chain_nonLR_caravel_io_skywater130nm.xml
-
-[BENCHMARKS]
-bench0=${SKYWATER_OPENFPGA_HOME}/BENCHMARK/and2/and2.v
-bench1=${SKYWATER_OPENFPGA_HOME}/BENCHMARK/and2_latch/and2_latch.v
-bench2=${SKYWATER_OPENFPGA_HOME}/BENCHMARK/bin2bcd/bin2bcd.v
-bench3=${SKYWATER_OPENFPGA_HOME}/BENCHMARK/counter/counter.v
-bench4=${SKYWATER_OPENFPGA_HOME}/BENCHMARK/routing_test/routing_test.v
-# RS decoder needs 1.5k LUT4, exceeding device capacity
-#bench5=${SKYWATER_OPENFPGA_HOME}/BENCHMARK/rs_decoder/rtl/rs_decoder.v
-bench6=${SKYWATER_OPENFPGA_HOME}/BENCHMARK/simon_bit_serial/rtl/*.v
-bench7=${SKYWATER_OPENFPGA_HOME}/BENCHMARK/and2_or2/and2_or2.v
-
-[SYNTHESIS_PARAM]
-bench0_top = and2
-bench1_top = and2_latch
-bench2_top = bin2bcd
-bench3_top = counter
-bench4_top = routing_test
-# RS decoder needs 1.5k LUT4, exceeding device capacity
-#bench5_top = rs_decoder_top
-bench6_top = top_module
-bench7_top = and2_or2
-
-[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
-#end_flow_with_test=
diff --git a/TESTBENCH/common/ccff_test_post_pnr.v b/TESTBENCH/common/ccff_test_post_pnr_v1.0.v
similarity index 100%
rename from TESTBENCH/common/ccff_test_post_pnr.v
rename to TESTBENCH/common/ccff_test_post_pnr_v1.0.v
diff --git a/TESTBENCH/common/ccff_test_post_pnr_v1.1.v b/TESTBENCH/common/ccff_test_post_pnr_v1.1.v
new file mode 100644
index 0000000..978b08b
--- /dev/null
+++ b/TESTBENCH/common/ccff_test_post_pnr_v1.1.v
@@ -0,0 +1,3 @@
+version https://git-lfs.github.com/spec/v1
+oid sha256:54de2236bc41e29dfa92693844fc6c1f4d50a3b61f4b0055c9db9ac8877ace49
+size 6051
diff --git a/TESTBENCH/common/post_pnr_fpga_cells.v b/TESTBENCH/common/post_pnr_fpga_cells.v
index cebd223..5bfa734 100644
--- a/TESTBENCH/common/post_pnr_fpga_cells.v
+++ b/TESTBENCH/common/post_pnr_fpga_cells.v
@@ -1,3 +1,3 @@
 version https://git-lfs.github.com/spec/v1
-oid sha256:4ae0fb278944fcfc542a395b998e06e1c5d473df8d7d192ff9a386f1ba596ee4
-size 7630
+oid sha256:89b4703e97499ddd03efb70998f547462d7a8fa5d27e2c2d2af132b2050e195d
+size 7942
diff --git a/TESTBENCH/common/scff_test_post_pnr.v b/TESTBENCH/common/scff_test_post_pnr_v1.0.v
similarity index 100%
rename from TESTBENCH/common/scff_test_post_pnr.v
rename to TESTBENCH/common/scff_test_post_pnr_v1.0.v
diff --git a/TESTBENCH/common/scff_test_post_pnr_v1.1.v b/TESTBENCH/common/scff_test_post_pnr_v1.1.v
new file mode 100644
index 0000000..1b1a7b1
--- /dev/null
+++ b/TESTBENCH/common/scff_test_post_pnr_v1.1.v
@@ -0,0 +1,3 @@
+version https://git-lfs.github.com/spec/v1
+oid sha256:dcad9b2185f4571e82799aca46235e4193c3744c41b4ed6507ea2f339c9d894a
+size 5872
diff --git a/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_latch_post_pnr_include_netlists.v b/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_latch_post_pnr_include_netlists.v
index c1b7265..e40f43e 100644
--- a/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_latch_post_pnr_include_netlists.v
+++ b/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_latch_post_pnr_include_netlists.v
@@ -1,30 +1,3 @@
-//-------------------------------------------
-//	FPGA Synthesizable Verilog Netlist
-//	Description: Netlist Summary
-//	Author: Xifan TANG
-//	Organization: University of Utah
-//	Date: Wed Nov 11 16:01:30 2020
-//-------------------------------------------
-//----- Time scale -----
-`timescale 1ns / 1ps
-
-// ------ Include simulation defines -----
-`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/prepnr/verilog_testbench/define_simulation.v"
-
-`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/HDL/common/skywater_function_verification.v"
-
-// ------ Include Skywater cell netlists -----
-`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/common/post_pnr_fpga_cells.v"
-
-// ------ Include fabric top-level netlists -----
-//`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/FPGA1212_FC_HD_SKY_PNR/fpga_core/fpga_core_icv_in_design.pt.v"
-`include "/research/ece/lnis/USERS/DARPA_ERI/Tapeout/Nov2020_Skywater/FPGA1212_FLAT_HD_SKY_PNR/fpga_top/fpga_top_icv_in_design.pt.v"
-
-`ifdef AUTOCHECKED_SIMULATION
-	`include "and2_latch_output_verilog.v"
-`endif
-
-`ifdef AUTOCHECKED_SIMULATION
-	`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_latch_post_pnr_autocheck_top_tb.v"
-`endif
-
+version https://git-lfs.github.com/spec/v1
+oid sha256:3140f41d14f1046308ebd07b6527c4ec781ab3c18e63b237aba9b435b9c044de
+size 1239
diff --git a/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_latch_post_pnr_wrapper_include_netlists.v b/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_latch_post_pnr_wrapper_include_netlists.v
index 8851916..2781b69 100644
--- a/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_latch_post_pnr_wrapper_include_netlists.v
+++ b/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_latch_post_pnr_wrapper_include_netlists.v
@@ -1,3 +1,3 @@
 version https://git-lfs.github.com/spec/v1
-oid sha256:92f909b526ee576979b1a02b23171c242ff03e62d862f06413b6a5236e5377cb
-size 1478
+oid sha256:9d2003a31c42e9558a77f3891b6284affed509e22d38dbb150f475db968c5f8e
+size 1343
diff --git a/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_or2_post_pnr_include_netlists.v b/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_or2_post_pnr_include_netlists.v
index 694c7f1..731e086 100644
--- a/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_or2_post_pnr_include_netlists.v
+++ b/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_or2_post_pnr_include_netlists.v
@@ -1,30 +1,3 @@
-//-------------------------------------------
-//	FPGA Synthesizable Verilog Netlist
-//	Description: Netlist Summary
-//	Author: Xifan TANG
-//	Organization: University of Utah
-//	Date: Sun Nov 22 13:37:06 2020
-//-------------------------------------------
-//----- Time scale -----
-`timescale 1ns / 1ps
-
-// ------ Include simulation defines -----
-`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/prepnr/verilog_testbench/define_simulation.v"
-
-`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/HDL/common/skywater_function_verification.v"
-
-// ------ Include Skywater cell netlists -----
-`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/common/post_pnr_fpga_cells.v"
-
-// ------ Include fabric top-level netlists -----
-//`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/FPGA1212_FC_HD_SKY_PNR/fpga_core/fpga_core_icv_in_design.pt.v"
-`include "/research/ece/lnis/USERS/DARPA_ERI/Tapeout/Nov2020_Skywater/FPGA1212_FLAT_HD_SKY_PNR/fpga_top/fpga_top_icv_in_design.pt.v"
-
-`ifdef AUTOCHECKED_SIMULATION
-	`include "and2_or2_output_verilog.v"
-`endif
-
-`ifdef AUTOCHECKED_SIMULATION
-	`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_or2_post_pnr_autocheck_top_tb.v"
-`endif
-
+version https://git-lfs.github.com/spec/v1
+oid sha256:6395e2f33f3dcb8dad1c92fa0659bc4b842b3495d683add90e50d942e28b6ef1
+size 1235
diff --git a/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_or2_post_pnr_wrapper_include_netlists.v b/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_or2_post_pnr_wrapper_include_netlists.v
index 7354521..f9dd991 100644
--- a/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_or2_post_pnr_wrapper_include_netlists.v
+++ b/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_or2_post_pnr_wrapper_include_netlists.v
@@ -1,3 +1,3 @@
 version https://git-lfs.github.com/spec/v1
-oid sha256:825a6a406d866bda71202b39eb897b967484f3dc7c3cf7a62aa18791e54df573
-size 1474
+oid sha256:ec87f38ebc0e4f795a0a72b760f6181288ef6f7cc72f7708ec21d77a1ea8c28d
+size 1339
diff --git a/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_post_pnr_include_netlists.v b/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_post_pnr_include_netlists.v
index 24d1f7b..bf40134 100644
--- a/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_post_pnr_include_netlists.v
+++ b/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_post_pnr_include_netlists.v
@@ -1,30 +1,3 @@
-//-------------------------------------------
-//	FPGA Synthesizable Verilog Netlist
-//	Description: Netlist Summary
-//	Author: Xifan TANG
-//	Organization: University of Utah
-//	Date: Wed Nov 11 16:01:30 2020
-//-------------------------------------------
-//----- Time scale -----
-`timescale 1ns / 1ps
-
-// ------ Include simulation defines -----
-`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/prepnr/verilog_testbench/define_simulation.v"
-
-`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/HDL/common/skywater_function_verification.v"
-
-// ------ Include Skywater cell netlists -----
-`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/common/post_pnr_fpga_cells.v"
-
-// ------ Include fabric top-level netlists -----
-//`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/FPGA1212_FC_HD_SKY_PNR/fpga_core/fpga_core_icv_in_design.pt.v"
-`include "/research/ece/lnis/USERS/DARPA_ERI/Tapeout/Nov2020_Skywater/FPGA1212_FLAT_HD_SKY_PNR/fpga_top/fpga_top_icv_in_design.pt.v"
-
-`ifdef AUTOCHECKED_SIMULATION
-	`include "and2_output_verilog.v"
-`endif
-
-`ifdef AUTOCHECKED_SIMULATION
-	`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_post_pnr_autocheck_top_tb.v"
-`endif
-
+version https://git-lfs.github.com/spec/v1
+oid sha256:0168df4405980eb7be0f0231735794d86c514199126d0941f043ba38905d0c4f
+size 1227
diff --git a/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_post_pnr_wrapper_include_netlists.v b/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_post_pnr_wrapper_include_netlists.v
index 40df803..1e21a4f 100644
--- a/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_post_pnr_wrapper_include_netlists.v
+++ b/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_post_pnr_wrapper_include_netlists.v
@@ -1,3 +1,3 @@
 version https://git-lfs.github.com/spec/v1
-oid sha256:9f6df360605df5a436036afc2ccf3b950ce42b3c9ea396350cd4ebbb4d705b9d
-size 1466
+oid sha256:3fc3f03b263ff267b9543c09f338222e9e9950978915a10a16825decd8deab4c
+size 1331
diff --git a/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/ccff_test_post_pnr_include_netlists.v b/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/ccff_test_post_pnr_include_netlists.v
index 0f03de9..30a2005 100644
--- a/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/ccff_test_post_pnr_include_netlists.v
+++ b/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/ccff_test_post_pnr_include_netlists.v
@@ -1,3 +1,3 @@
 version https://git-lfs.github.com/spec/v1
-oid sha256:f3da10525b0dff707611379ed6ae1348c294eae1a8cd31499ce2e35dde3beaab
-size 1329
+oid sha256:5b1dbfb9b52a4e87e544773b46710111d2a53c24922de3e10eefd82c7d280f0b
+size 1199
diff --git a/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/ccff_test_post_pnr_wrapper_include_netlists.v b/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/ccff_test_post_pnr_wrapper_include_netlists.v
index 838b868..386cac1 100644
--- a/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/ccff_test_post_pnr_wrapper_include_netlists.v
+++ b/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/ccff_test_post_pnr_wrapper_include_netlists.v
@@ -1,3 +1,3 @@
 version https://git-lfs.github.com/spec/v1
-oid sha256:06bb3d6a1ee52298d3ac59ad73f16132b268c013b3cb411d0dfe6f033f6aed36
-size 1488
+oid sha256:f5fe62252b7eae6cd437a4fde8a18dcdcc61e629ab847b6bffa2d8d0d8dc60b4
+size 1353
diff --git a/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/routing_test_post_pnr_include_netlists.v b/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/routing_test_post_pnr_include_netlists.v
index 3f49591..79c523c 100644
--- a/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/routing_test_post_pnr_include_netlists.v
+++ b/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/routing_test_post_pnr_include_netlists.v
@@ -1,30 +1,3 @@
-//-------------------------------------------
-//	FPGA Synthesizable Verilog Netlist
-//	Description: Netlist Summary
-//	Author: Xifan TANG
-//	Organization: University of Utah
-//	Date: Fri Nov 20 15:48:54 2020
-//-------------------------------------------
-//----- Time scale -----
-`timescale 1ns / 1ps
-
-// ------ Include simulation defines -----
-`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/prepnr/verilog_testbench/define_simulation.v"
-
-`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/HDL/common/skywater_function_verification.v"
-
-// ------ Include Skywater cell netlists -----
-`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/common/post_pnr_fpga_cells.v"
-
-// ------ Include fabric top-level netlists -----
-//`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/FPGA1212_FC_HD_SKY_PNR/fpga_core/fpga_core_icv_in_design.pt.v"
-`include "/research/ece/lnis/USERS/DARPA_ERI/Tapeout/Nov2020_Skywater/FPGA1212_FLAT_HD_SKY_PNR/fpga_top/fpga_top_icv_in_design.pt.v"
-
-`ifdef AUTOCHECKED_SIMULATION
-	`include "routing_test_output_verilog.v"
-`endif
-
-`ifdef AUTOCHECKED_SIMULATION
-	`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/routing_test_post_pnr_autocheck_top_tb.v"
-`endif
-
+version https://git-lfs.github.com/spec/v1
+oid sha256:9a2a5d743a10211cd55496c15a559690e5a09a328edcb0942d901ba5e5df48b8
+size 1243
diff --git a/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/routing_test_post_pnr_wrapper_include_netlists.v b/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/routing_test_post_pnr_wrapper_include_netlists.v
index 7139452..e440cab 100644
--- a/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/routing_test_post_pnr_wrapper_include_netlists.v
+++ b/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/routing_test_post_pnr_wrapper_include_netlists.v
@@ -1,3 +1,3 @@
 version https://git-lfs.github.com/spec/v1
-oid sha256:3adff4e62fe53b8cef99dc752bab3ebc6890445d6263b3aad5fdec154f53fbcf
-size 1482
+oid sha256:a18b7fab25c736e3d465a51353672d7bc5dc7e693145fee2837afc1d11b78289
+size 1347
diff --git a/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/scff_test_post_pnr_include_netlists.v b/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/scff_test_post_pnr_include_netlists.v
index ae327f8..1edcd07 100644
--- a/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/scff_test_post_pnr_include_netlists.v
+++ b/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/scff_test_post_pnr_include_netlists.v
@@ -1,3 +1,3 @@
 version https://git-lfs.github.com/spec/v1
-oid sha256:f25455fe75150d87bcfb386c5c953172a1712655ec1e38017d22aeb062314a6d
-size 1328
+oid sha256:98d430047e77dd1e59a84fd4fdc368b229f29e27ae0354657e166db51e2f56a3
+size 1198
diff --git a/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/scff_test_post_pnr_wrapper_include_netlists.v b/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/scff_test_post_pnr_wrapper_include_netlists.v
index 5694280..8783bb0 100644
--- a/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/scff_test_post_pnr_wrapper_include_netlists.v
+++ b/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/scff_test_post_pnr_wrapper_include_netlists.v
@@ -1,3 +1,3 @@
 version https://git-lfs.github.com/spec/v1
-oid sha256:c3b64adf49892e8d7e7263273e76b566cb1f0922d404c224d550136d43b49178
-size 1487
+oid sha256:5dd9f4ffe36c1f5ac05ff49da29ec5541913f2e2efce7cf7a4c7e1cb9120264e
+size 1352
diff --git a/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_latch_post_pnr_include_netlists.v b/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_latch_post_pnr_include_netlists.v
new file mode 100644
index 0000000..ca377b7
--- /dev/null
+++ b/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_latch_post_pnr_include_netlists.v
@@ -0,0 +1,3 @@
+version https://git-lfs.github.com/spec/v1
+oid sha256:32e7a27472ef1501fec8765f8a7beb44ab61c84c514a5f63801840cfdec20eb7
+size 1272
diff --git a/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_latch_post_pnr_wrapper_include_netlists.v b/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_latch_post_pnr_wrapper_include_netlists.v
new file mode 100644
index 0000000..5d0b93a
--- /dev/null
+++ b/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_latch_post_pnr_wrapper_include_netlists.v
@@ -0,0 +1,3 @@
+version https://git-lfs.github.com/spec/v1
+oid sha256:c2067d21d21d3666ebe52b8de512bf06020ab395b65304387709e166e1d43a23
+size 1376
diff --git a/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_or2_post_pnr_include_netlists.v b/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_or2_post_pnr_include_netlists.v
new file mode 100644
index 0000000..b93bc4a
--- /dev/null
+++ b/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_or2_post_pnr_include_netlists.v
@@ -0,0 +1,3 @@
+version https://git-lfs.github.com/spec/v1
+oid sha256:ee2934fe5c3048ac3655a3cc6213f176d83c3495aef7428904ad229f39d424a0
+size 1268
diff --git a/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_or2_post_pnr_wrapper_include_netlists.v b/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_or2_post_pnr_wrapper_include_netlists.v
new file mode 100644
index 0000000..c87613f
--- /dev/null
+++ b/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_or2_post_pnr_wrapper_include_netlists.v
@@ -0,0 +1,3 @@
+version https://git-lfs.github.com/spec/v1
+oid sha256:1707e2d2da1c2eba04f17079d9d9144b71be24bf19b9d99c83ceefc5d46d6afd
+size 1372
diff --git a/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_post_pnr_include_netlists.v b/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_post_pnr_include_netlists.v
new file mode 100644
index 0000000..0fe63cd
--- /dev/null
+++ b/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_post_pnr_include_netlists.v
@@ -0,0 +1,3 @@
+version https://git-lfs.github.com/spec/v1
+oid sha256:35a893d7106b66061ef6c45570ba26c5eb2cc31c1ba667193e01003e1a3c8294
+size 1260
diff --git a/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_post_pnr_wrapper_include_netlists.v b/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_post_pnr_wrapper_include_netlists.v
new file mode 100644
index 0000000..d6c6337
--- /dev/null
+++ b/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_post_pnr_wrapper_include_netlists.v
@@ -0,0 +1,3 @@
+version https://git-lfs.github.com/spec/v1
+oid sha256:3cfd0b49a75dbcc308f61212ed162d2c74c9343bffe35d78cb39fa553507b559
+size 1364
diff --git a/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/ccff_test_post_pnr_include_netlists.v b/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/ccff_test_post_pnr_include_netlists.v
new file mode 100644
index 0000000..114dfab
--- /dev/null
+++ b/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/ccff_test_post_pnr_include_netlists.v
@@ -0,0 +1,3 @@
+version https://git-lfs.github.com/spec/v1
+oid sha256:fe32ecd75d97fefe74d1e1e01713ed38098f845cc37aad617b161e64a05a4e36
+size 1216
diff --git a/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/ccff_test_post_pnr_wrapper_include_netlists.v b/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/ccff_test_post_pnr_wrapper_include_netlists.v
new file mode 100644
index 0000000..222f122
--- /dev/null
+++ b/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/ccff_test_post_pnr_wrapper_include_netlists.v
@@ -0,0 +1,3 @@
+version https://git-lfs.github.com/spec/v1
+oid sha256:cedd3fbe2dc2158e46da28ab3b630b45571f7015b89f29391b092bb3860fdbcc
+size 1386
diff --git a/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/routing_test_post_pnr_include_netlists.v b/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/routing_test_post_pnr_include_netlists.v
new file mode 100644
index 0000000..a37047e
--- /dev/null
+++ b/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/routing_test_post_pnr_include_netlists.v
@@ -0,0 +1,3 @@
+version https://git-lfs.github.com/spec/v1
+oid sha256:7dbfbefcae891ea972982503967a7dc838843bd86ff134873a38da4a1c4b4a1f
+size 1276
diff --git a/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/routing_test_post_pnr_wrapper_include_netlists.v b/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/routing_test_post_pnr_wrapper_include_netlists.v
new file mode 100644
index 0000000..d5bbb87
--- /dev/null
+++ b/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/routing_test_post_pnr_wrapper_include_netlists.v
@@ -0,0 +1,3 @@
+version https://git-lfs.github.com/spec/v1
+oid sha256:b5388c9df5e22b40644563abea84f530445b17a43673499bcfcb9680acf5aa66
+size 1380
diff --git a/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/scff_test_post_pnr_include_netlists.v b/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/scff_test_post_pnr_include_netlists.v
new file mode 100644
index 0000000..3c6c896
--- /dev/null
+++ b/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/scff_test_post_pnr_include_netlists.v
@@ -0,0 +1,3 @@
+version https://git-lfs.github.com/spec/v1
+oid sha256:8cb80347043fd1a8fab62f8963bf174668951941f6a60e3ba6db9c2a0f439b07
+size 1215
diff --git a/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/scff_test_post_pnr_wrapper_include_netlists.v b/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/scff_test_post_pnr_wrapper_include_netlists.v
new file mode 100644
index 0000000..73ead6b
--- /dev/null
+++ b/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/scff_test_post_pnr_wrapper_include_netlists.v
@@ -0,0 +1,3 @@
+version https://git-lfs.github.com/spec/v1
+oid sha256:e7a163317878eb9295a02108efc9a8e7c3f4a5485aa05e03bd29b40445d88d88
+size 1385