SOFA/.gitignore

**/SRCOriginal
**/SRCOutline
**/TaskConfigCopy
**/*_task/run001
**/*_task/latest
**/*_task/skywater
**/*_Verilog/SRC_Skeleton
**/*_Verilog/SRCBackup
**/SRC/top_top_formal_verification.v
**/DOC/build
**/SRC**/*_tb.v
**/SDC/**/*.sdc
!**/SDC/**/disable_configure_ports.sdc
*/runOpenFPGA
**/*_task/latest
**/*_task/run**
**/*_task/config/task.conf
.vscode/
LoadTools.sh
[Design] Added FPGA22 design with SKY130_FD_SC_HD 2020-10-27 00:59:20 -05:00			`**/SRCOriginal`
			`**/SRCOutline`
			`**/TaskConfigCopy`
			`*/_task/run001`
			`*/_task/latest`
dropped symbolic link 2020-10-27 12:21:20 -05:00			`*/_task/skywater`
Updated design with new architecure and merged grid_io 2020-11-06 23:35:31 -06:00			`*/_Verilog/SRC_Skeleton`
			`*/_Verilog/SRCBackup`
[SOFA-CHD] Updated design with mux-primitive bug fixed - Calibre DRC pending 2020-12-14 01:34:42 -06:00			`**/SRC/top_top_formal_verification.v`
[Git] Add ignore files to doc compiled results 2020-11-12 20:13:20 -06:00			`**/DOC/build`
[Cleanup] Removed/Ignored testbench files from generated source 2020-12-02 13:03:24 -06:00			`/SRC/*_tb.v`
[Cleanup] Removed unused SDCs 2020-12-14 01:31:03 -06:00			`/SDC//*.sdc`
			`!/SDC//disable_configure_ports.sdc`
[Flow] Adding Makefile for running task 2021-04-03 18:54:59 -05:00			`*/runOpenFPGA`
[SOFA1212] Updated SOFA Project 2021-04-06 00:29:01 -05:00			`*/_task/latest`
			`*/_task/run**`
[SOFA] Updated task configuration 2021-05-31 13:05:36 -05:00			`*/_task/config/task.conf`
			`.vscode/`
Added SOFA-A project 2023-03-01 10:31:42 -06:00			`LoadTools.sh`