2020-10-27 00:59:20 -05:00
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**/SRCOriginal
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**/SRCOutline
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**/TaskConfigCopy
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**/*_task/run001
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**/*_task/latest
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2020-10-27 12:21:20 -05:00
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**/*_task/skywater
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2020-11-06 23:35:31 -06:00
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**/*_Verilog/SRC_Skeleton
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**/*_Verilog/SRCBackup
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2020-12-14 01:34:42 -06:00
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**/SRC/top_top_formal_verification.v
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2020-11-12 20:13:20 -06:00
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**/DOC/build
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2020-12-02 13:03:24 -06:00
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**/SRC**/*_tb.v
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2020-12-14 01:31:03 -06:00
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**/SDC/**/*.sdc
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!**/SDC/**/disable_configure_ports.sdc
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2021-04-03 18:54:59 -05:00
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*/runOpenFPGA
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2021-04-06 00:29:01 -05:00
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**/*_task/latest
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**/*_task/run**
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**/*_task/config/task.conf
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