OpenFPGA/vpr7_x2p/vpr/SRC/fpga_x2p/verilog
Baudouin Chauviere 1932d00309 Correction of the SDC to remove global clocks 2019-05-30 15:04:21 -06:00
..
verilog_api.c clean warnings 2019-05-24 16:48:08 -06:00
verilog_api.h Update VPR7 X2P with new engine 2019-04-26 12:23:47 -06:00
verilog_autocheck_top_testbench.c clean warnings 2019-05-24 16:48:08 -06:00
verilog_autocheck_top_testbench.h clean warnings 2019-05-24 16:48:08 -06:00
verilog_compact_netlist.c updated bitstream to use new RRSwitchBlock as well as the report timing engine 2019-05-24 12:54:10 -06:00
verilog_compact_netlist.h updated Verilog generator to use compact CBs and SBs. SPICE generator to be updated 2019-05-10 10:21:06 -06:00
verilog_decoder.c cleaned unused variables 2019-05-13 14:45:02 -06:00
verilog_decoder.h Update VPR7 X2P with new engine 2019-04-26 12:23:47 -06:00
verilog_formal_random_top_testbench.c clean warnings 2019-05-24 16:48:08 -06:00
verilog_formal_random_top_testbench.h clean warnings 2019-05-24 16:48:08 -06:00
verilog_formality_autodeck.c cleaned unused variables 2019-05-13 14:45:02 -06:00
verilog_formality_autodeck.h Update VPR7 X2P with new engine 2019-04-26 12:23:47 -06:00
verilog_global.c Update VPR7 X2P with new engine 2019-04-26 12:23:47 -06:00
verilog_global.h Update VPR7 X2P with new engine 2019-04-26 12:23:47 -06:00
verilog_include_netlists.c Update VPR7 X2P with new engine 2019-04-26 12:23:47 -06:00
verilog_include_netlists.h Update VPR7 X2P with new engine 2019-04-26 12:23:47 -06:00
verilog_modelsim_autodeck.c Update VPR7 X2P with new engine 2019-04-26 12:23:47 -06:00
verilog_modelsim_autodeck.h Update VPR7 X2P with new engine 2019-04-26 12:23:47 -06:00
verilog_pbtypes.c cleaned unused variables 2019-05-13 14:45:02 -06:00
verilog_pbtypes.h Update VPR7 X2P with new engine 2019-04-26 12:23:47 -06:00
verilog_primitives.c cleaned unused variables 2019-05-13 14:45:02 -06:00
verilog_primitives.h Update VPR7 X2P with new engine 2019-04-26 12:23:47 -06:00
verilog_report_timing.c updated report_timing for using RRSwitchBlock 2019-05-24 14:25:51 -06:00
verilog_report_timing.h updated bitstream to use new RRSwitchBlock as well as the report timing engine 2019-05-24 12:54:10 -06:00
verilog_routing.c keep debugging on Switch Block rotation 2019-05-27 21:10:30 -06:00
verilog_routing.h clean-up warnings Verilog routing generator 2019-05-24 16:29:17 -06:00
verilog_sdc.c Correction of the SDC to remove global clocks 2019-05-30 15:04:21 -06:00
verilog_sdc.h Clean warnings in SDC generator and use RRSwitchBlock to replace old data structure sb_info 2019-05-24 15:10:08 -06:00
verilog_sdc_pb_types.c clean up warnings in SDC pb_type generator 2019-05-24 15:23:38 -06:00
verilog_sdc_pb_types.h clean up warnings in SDC pb_type generator 2019-05-24 15:23:38 -06:00
verilog_submodules.c Merge branch 'multimode_clb' of https://github.com/LNIS-Projects/OpenFPGA into multimode_clb 2019-05-20 16:47:07 -06:00
verilog_submodules.h Update VPR7 X2P with new engine 2019-04-26 12:23:47 -06:00
verilog_tcl_utils.c updated report_timing for using RRSwitchBlock 2019-05-24 14:25:51 -06:00
verilog_tcl_utils.h updated bitstream to use new RRSwitchBlock as well as the report timing engine 2019-05-24 12:54:10 -06:00
verilog_top_netlist_utils.c Update VPR7 X2P with new engine 2019-04-26 12:23:47 -06:00
verilog_top_netlist_utils.h Update VPR7 X2P with new engine 2019-04-26 12:23:47 -06:00
verilog_top_testbench.c clean warnings 2019-05-24 16:48:08 -06:00
verilog_top_testbench.h clean warnings 2019-05-24 16:48:08 -06:00
verilog_utils.c upgrade Verilog SB generator using the RRSwitchBlock 2019-05-23 17:37:39 -06:00
verilog_utils.h upgrade Verilog SB generator using the RRSwitchBlock 2019-05-23 17:37:39 -06:00
verilog_verification_top_netlist.c clean warnings 2019-05-24 16:48:08 -06:00
verilog_verification_top_netlist.h clean warnings 2019-05-24 16:48:08 -06:00