AurelienUoU a2f6ded2a2 Add path modification in file changing a keyword into OpenFPGA full path		2019-06-04 15:21:15 -06:00
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ARCH	Update spice path in architecture	2019-05-29 10:08:58 -06:00
Circuits	Add missing Verilog source, Archictecture folder and Testbenches correction	2019-05-13 16:41:35 -06:00
SRC	add side mirror detection for RRSwitchBlock	2019-06-04 13:01:22 -06:00
SpiceNetlists	Update VPR7 X2P with new engine	2019-04-26 12:23:47 -06:00
VerilogNetlists	Add travis full path to avoid missing sources	2019-05-16 15:51:10 -06:00
CMakeLists.txt	Force graphics to false	2019-05-15 15:01:54 -06:00
Makefile	fixed bugs in CMakeLists.txt and Makefile	2019-05-03 23:03:04 -06:00
go_fpga_spice.sh	Update VPR7 X2P with new engine	2019-04-26 12:23:47 -06:00
go_fpga_verilog.sh	add side mirror detection for RRSwitchBlock	2019-06-04 13:01:22 -06:00
regression_verilog.sh	Add path modification in file changing a keyword into OpenFPGA full path	2019-06-04 15:21:15 -06:00