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OpenFPGA
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OpenFPGA/vpr7_x2p/vpr/SRC/fpga_x2p
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tangxifan 2c6780ab92 add side mirror detection for RRSwitchBlock 2019-06-04 13:01:22 -06:00
..
base add side mirror detection for RRSwitchBlock 2019-06-04 13:01:22 -06:00
bitstream updated bitstream to use new RRSwitchBlock as well as the report timing engine 2019-05-24 12:54:10 -06:00
clb_pin_remap cleaned unused variables 2019-05-13 14:45:02 -06:00
router cleaned unused variables 2019-05-13 14:45:02 -06:00
shell Merge branch 'multimode_clb' of https://github.com/LNIS-Projects/OpenFPGA into multimode_clb 2019-05-13 14:45:57 -06:00
spice Merge branch 'multimode_clb' of https://github.com/LNIS-Projects/OpenFPGA into multimode_clb 2019-05-13 14:45:57 -06:00
verilog Correction of the SDC to remove global clocks 2019-05-30 15:04:21 -06:00