OpenFPGA/openfpga_flow/benchmarks
tangxifan 9c7868cfab [hdl] add a counter design which is triggered by negative edges 2022-05-09 16:41:21 +08:00
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MCNC_Verilog Added first draft of fpga_task script 2019-08-09 00:17:06 -06:00
iwls2005 [Benchmark] Add missing RTL for IWLS2005 benchmarks 2021-04-16 16:50:41 -06:00
mcnc_big20 add explicit port mapping support in testbenches; remove dangling ports in benchmarks 2019-11-02 23:03:47 -06:00
micro_benchmark [hdl] add a counter design which is triggered by negative edges 2022-05-09 16:41:21 +08:00
quicklogic_tests add shift register test case 2021-03-05 09:06:05 -08:00
vtr_benchmark [Benchmark] Add missing DPRAM module to LU32PEEng 2021-03-22 14:41:38 -06:00