Lalit Sharma 7945628307 Adding YOSYS_ARGS instead of YOSYS_MODE. Also commenting vpr_formal_verification for lut_adder_test. Ganesh to do changes to allow yosys generated verilog to be used for verification		2021-03-07 22:25:01 -08:00
..
arch_bitstreams	[Architecture] Update external bitstream	2020-09-25 21:30:59 -06:00
benchmarks	[Benchmark] Remove replicate micro benchmarks	2021-02-22 10:22:19 -07:00
docs	Added first draft of fpga_task script	2019-08-09 00:17:06 -06:00
fabric_keys	[Architecture] Add example fabric key using multiple regions	2020-09-29 14:14:50 -06:00
misc	Replacing YOSYS_FAMILY & YOSYS_MODE with YOSYS_ARGS	2021-03-07 22:02:11 -08:00
openfpga_arch	[Arch] Comment out yosys tech lib Verilog to see if it caused CI failed in iVerilog compilation; Now suspect that iVerilog v10.1 on CI is low; Local test with iVerilog v10.3 passed	2021-02-24 11:51:10 -07:00
openfpga_cell_library	Merge pull request #227 from watcag/master	2021-02-17 10:11:34 -07:00
openfpga_shell_scripts	Merge branch 'master' into default_net_type	2021-03-01 08:38:58 -07:00
openfpga_simulation_settings	[Arch] Add simulation setting for 8-clock architectures	2021-02-22 11:10:03 -07:00
regression_test_scripts	Merge branch 'master' into default_net_type	2021-03-01 08:38:58 -07:00
scripts	Replacing YOSYS_FAMILY & YOSYS_MODE with YOSYS_ARGS	2021-03-07 22:02:11 -08:00
tasks	Adding YOSYS_ARGS instead of YOSYS_MODE. Also commenting vpr_formal_verification for lut_adder_test. Ganesh to do changes to allow yosys generated verilog to be used for verification	2021-03-07 22:25:01 -08:00
tech	Added Power Model Files	2019-08-19 18:55:23 -06:00
vpr_arch	[Arch] Patched superLUT architecture example when trying adder8 synthesis script	2021-02-23 19:00:27 -07:00
.gitignore	Added first draft of fpga_task script	2019-08-09 00:17:06 -06:00