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riscv
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OpenFPGA
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f3e7ae0823
OpenFPGA
/
vpr7_x2p
/
vpr
History
Baudouin Chauviere
f3e7ae0823
Hot fix
2019-01-10 17:37:15 -07:00
..
ARCH
Removed commercial scripts, replaced by academia ones
2019-01-09 11:56:07 -07:00
Circuits
Add new benchmark and modify go.sh to use it
2018-12-26 04:24:26 -07:00
SRC
fix a bug for supporting default circuit_model of LUTs and FFs
2019-01-10 15:10:05 -07:00
SpiceNetlists
rename customized vpr7 to vpr7 XML to Production
2018-09-17 23:10:45 -06:00
VerilogNetlists
Add timing and initialization for simulation
2018-12-04 17:32:09 -07:00
picorv
Changed for the naming
2018-12-08 16:19:38 -07:00
Makefile
rename customized vpr7 to vpr7 XML to Production
2018-09-17 23:10:45 -06:00
go.sh
Hot fix
2019-01-10 17:37:15 -07:00
picorv.sh
Changed for the naming
2018-12-08 16:19:38 -07:00