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behavioral_verilog_example_script.openfpga
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[Script] Correct bugs in example scripts using default_net_type
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2021-02-28 16:31:44 -07:00 |
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bitstream_setting_example_script.openfpga
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[Script] Now use implicit port mapping for Verilog testbenches to avoid renaming issues
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2021-02-26 09:34:52 -07:00 |
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configuration_chain_example_script.openfpga
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[Flow] Rename OpenFPGA shell script folder name to consistent with naming convention
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2020-11-22 16:37:19 -07:00 |
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custom_fabric_netlist_example_script.openfpga
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[Flow] Rename OpenFPGA shell script folder name to consistent with naming convention
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2020-11-22 16:37:19 -07:00 |
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duplicated_grid_pin_example_script.openfpga
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[Flow] Rename OpenFPGA shell script folder name to consistent with naming convention
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2020-11-22 16:37:19 -07:00 |
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example_script.openfpga
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[Script] Remove default net type from an example script; Limit it to some test cases
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2021-02-28 12:19:14 -07:00 |
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fast_configuration_example_script.openfpga
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[Flow] Rename OpenFPGA shell script folder name to consistent with naming convention
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2020-11-22 16:37:19 -07:00 |
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fix_device_example_script.openfpga
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[Flow] Rename OpenFPGA shell script folder name to consistent with naming convention
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2020-11-22 16:37:19 -07:00 |
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fix_device_global_tile_clock_example_script.openfpga
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[Flow] Add new script for fixed device layout using global tile clock
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2021-01-10 11:08:02 -07:00 |
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fix_device_route_chan_width_example_script.openfpga
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ahoy nice
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2021-02-09 17:38:19 -05:00 |
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flatten_routing_example_script.openfpga
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[Script] Add default net type option to example openfpga shell scripts
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2021-02-28 12:08:30 -07:00 |
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full_testbench_example_script.openfpga
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[Flow] Rename OpenFPGA shell script folder name to consistent with naming convention
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2020-11-22 16:37:19 -07:00 |
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generate_bitstream_example_script.openfpga
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[Flow] Rename OpenFPGA shell script folder name to consistent with naming convention
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2020-11-22 16:37:19 -07:00 |
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generate_bitstream_fix_device_example_script.openfpga
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[Flow] Rename OpenFPGA shell script folder name to consistent with naming convention
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2020-11-22 16:37:19 -07:00 |
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generate_bitstream_global_tile_multiclock_example_script.openfpga
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[Flow] Add a new script for generating bitstream for multi-clock architectures
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2021-02-22 11:31:24 -07:00 |
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generate_bitstream_global_tile_multiclock_fix_device_example_script.openfpga
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[Flow] Add new script to run bitstream generation for multi-clock fix-size FPGAs
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2021-02-22 15:01:50 -07:00 |
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generate_fabric_example_script.openfpga
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[Flow] Rename OpenFPGA shell script folder name to consistent with naming convention
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2020-11-22 16:37:19 -07:00 |
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generate_fabric_key_example_script.openfpga
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[Flow] Rename OpenFPGA shell script folder name to consistent with naming convention
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2020-11-22 16:37:19 -07:00 |
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generate_secure_fabric_example_script.openfpga
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[Flow] Rename OpenFPGA shell script folder name to consistent with naming convention
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2020-11-22 16:37:19 -07:00 |
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generate_secure_fabric_from_key_example_script.openfpga
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[Flow] Rename OpenFPGA shell script folder name to consistent with naming convention
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2020-11-22 16:37:19 -07:00 |
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generate_spice_example_script.openfpga
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[Flow] Rename OpenFPGA shell script folder name to consistent with naming convention
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2020-11-22 16:37:19 -07:00 |
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generate_testbench_example_script.openfpga
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[Flow] Rename OpenFPGA shell script folder name to consistent with naming convention
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2020-11-22 16:37:19 -07:00 |
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global_tile_clock_example_script.openfpga
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[Flow] Use implicit port mapping to avoid renaming problem between yosys and VPR
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2021-01-13 15:41:48 -07:00 |
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global_tile_multiclock_example_script.openfpga
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[Script] Now multi-clock openfpga shell script no longer needs activity file
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2021-01-29 11:40:33 -07:00 |
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implicit_verilog_example_script.openfpga
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[Script] Correct bugs in example scripts using default_net_type
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2021-02-28 16:31:44 -07:00 |
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iverilog_example_script.openfpga
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[Flow] Rename OpenFPGA shell script folder name to consistent with naming convention
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2020-11-22 16:37:19 -07:00 |
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load_external_arch_bitstream_example_script.openfpga
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[Flow] Rename OpenFPGA shell script folder name to consistent with naming convention
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2020-11-22 16:37:19 -07:00 |
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mcnc_example_script.openfpga
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[Flow] Rename OpenFPGA shell script folder name to consistent with naming convention
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2020-11-22 16:37:19 -07:00 |
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quicklogic_flow_example_script.openfpga
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For time-being yosys script running in no_adder mode.
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2021-02-28 22:07:23 -08:00 |
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rename_scripts.sh
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[Flow] Rename OpenFPGA shell script folder name to consistent with naming convention
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2020-11-22 16:37:19 -07:00 |
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sdc_time_unit_example_script.openfpga
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[Flow] Rename OpenFPGA shell script folder name to consistent with naming convention
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2020-11-22 16:37:19 -07:00 |
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skywater_tapeout_example_script.openfpga
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[Flow] Rename OpenFPGA shell script folder name to consistent with naming convention
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2020-11-22 16:37:19 -07:00 |
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verilog_default_net_type_example_script.openfpga
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[Script] Bug fix for default net type example script
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2021-02-28 12:35:44 -07:00 |
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vtr_benchmark_example_script.openfpga
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[Script] Enable fast bitstream generation for VTR benchmarks
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2021-03-22 12:54:36 -06:00 |
