| .. |
|
circuit_library_utils.cpp
|
start integrating module graph builder
|
2020-02-12 17:53:23 -07:00 |
|
circuit_library_utils.h
|
start integrating module graph builder
|
2020-02-12 17:53:23 -07:00 |
|
decoder_library_utils.cpp
|
move mux graph and decoder builders to vpr8 integration; ready to link the rr_switch to circuit models
|
2020-02-11 21:02:58 -07:00 |
|
decoder_library_utils.h
|
move mux graph and decoder builders to vpr8 integration; ready to link the rr_switch to circuit models
|
2020-02-11 21:02:58 -07:00 |
|
device_rr_gsb_utils.cpp
|
add compact_routing hierarchy command
|
2020-02-11 17:40:37 -07:00 |
|
device_rr_gsb_utils.h
|
add compact_routing hierarchy command
|
2020-02-11 17:40:37 -07:00 |
|
lut_utils.cpp
|
Critical patch on repacking about wire LUT support.
|
2020-04-19 16:42:31 -06:00 |
|
lut_utils.h
|
add truth table build up for physical LUTs
|
2020-02-25 22:39:42 -07:00 |
|
memory_utils.cpp
|
start integrating module graph builder
|
2020-02-12 17:53:23 -07:00 |
|
memory_utils.h
|
start integrating module graph builder
|
2020-02-12 17:53:23 -07:00 |
|
module_manager_utils.cpp
|
now inout must be global port and I/O port so that it will appear in the top-level module
|
2020-04-08 16:54:08 -06:00 |
|
module_manager_utils.h
|
start supporting global output ports in module manager
|
2020-04-05 15:19:46 -06:00 |
|
mux_utils.cpp
|
move mux graph and decoder builders to vpr8 integration; ready to link the rr_switch to circuit models
|
2020-02-11 21:02:58 -07:00 |
|
mux_utils.h
|
move mux graph and decoder builders to vpr8 integration; ready to link the rr_switch to circuit models
|
2020-02-11 21:02:58 -07:00 |
|
openfpga_atom_netlist_utils.cpp
|
bug fixed for clock names
|
2020-02-27 16:51:55 -07:00 |
|
openfpga_atom_netlist_utils.h
|
bug fixed for clock names
|
2020-02-27 16:51:55 -07:00 |
|
openfpga_physical_tile_utils.cpp
|
debugging multiple io_types; bug fixed to support I/Os in more flexible location of FPGA fabric
|
2020-03-27 16:03:42 -06:00 |
|
openfpga_physical_tile_utils.h
|
debugging multiple io_types; bug fixed to support I/Os in more flexible location of FPGA fabric
|
2020-03-27 16:03:42 -06:00 |
|
pb_graph_utils.cpp
|
add mux library builder
|
2020-02-12 14:58:23 -07:00 |
|
pb_graph_utils.h
|
add mux library builder
|
2020-02-12 14:58:23 -07:00 |
|
pb_type_utils.cpp
|
bug fixed for heterogeneous block instances in top module
|
2020-03-24 17:39:26 -06:00 |
|
pb_type_utils.h
|
Critical patch on repacking about wire LUT support.
|
2020-04-19 16:42:31 -06:00 |
|
physical_pb_utils.cpp
|
Critical patch on repacking about wire LUT support.
|
2020-04-19 16:42:31 -06:00 |
|
physical_pb_utils.h
|
Critical patch on repacking about wire LUT support.
|
2020-04-19 16:42:31 -06:00 |
|
rr_gsb_utils.cpp
|
update bitstream generator to use sorted edges
|
2020-03-08 15:36:47 -06:00 |
|
rr_gsb_utils.h
|
update bitstream generator to use sorted edges
|
2020-03-08 15:36:47 -06:00 |
|
simulation_utils.cpp
|
add formal random Verilog testbench generation
|
2020-02-26 20:58:16 -07:00 |
|
simulation_utils.h
|
add formal random Verilog testbench generation
|
2020-02-26 20:58:16 -07:00 |
e10cafe0a5