tangxifan e10cafe0a5 Critical patch on repacking about wire LUT support. ... Previously, the wire LUT identification is too naive and does not consider all the cases		2020-04-19 16:42:31 -06:00
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src	Critical patch on repacking about wire LUT support.	2020-04-19 16:42:31 -06:00
test_blif	add missing files for micro benchmarks	2020-03-20 11:08:55 -06:00
test_openfpga_arch	now inout must be global port and I/O port so that it will appear in the top-level module	2020-04-08 16:54:08 -06:00
test_script	now use openfpga tokenizer to trim command line string in openfpga shell	2020-04-13 11:08:31 -06:00
test_vpr_arch	bug fixed in register scan-chain architecture	2020-04-07 17:06:16 -06:00
CMakeLists.txt	add simulation ini file writer	2020-02-27 18:01:47 -07:00