tangxifan 8f9e564cd5 [Test] Add the new test to basic regression test		2021-10-09 20:45:23 -07:00
..
arch_bitstreams	[Architecture] Update external bitstream	2020-09-25 21:30:59 -06:00
benchmarks	[Benchmark] Rename the dual clock counter benchmark to follow the naming convention on counter benchmarks	2021-07-02 17:28:17 -06:00
docs	Added first draft of fpga_task script	2019-08-09 00:17:06 -06:00
fabric_keys	[Test] Add an example test key for multi-region QuickLogic memory bank using shift registers	2021-10-05 11:46:58 -07:00
misc	[Script] Update yosys script using BRAMs	2021-04-27 21:44:27 -06:00
openfpga_arch	[Arch] Add an example architecture which uses multiple shift register chain for a single-ql-bank FPGA	2021-10-09 20:43:55 -07:00
openfpga_cell_library	[HDL] Update the WL CCFF HDL modeling by adding Write-Enable signals	2021-10-01 17:06:35 -07:00
openfpga_shell_scripts	[Script] Add a new openfpga shell script for don't care bits outputting	2021-10-05 19:13:50 -07:00
openfpga_simulation_settings	[Script] Bug fix in slow clock frequency in shift register chain contraints	2021-10-06 16:49:01 -07:00
openfpga_yosys_techlib	[Script] Add dff with active-low async reset to default yosys tech lib	2021-07-02 11:17:43 -06:00
regression_test_scripts	[Test] Add the new test to basic regression test	2021-10-09 20:45:23 -07:00
scripts	Merge remote-tracking branch 'upstream/master'	2021-09-01 14:19:00 -07:00
tasks	[Test] Add a test case to validate the multi-shift-register-chain QL memory bank	2021-10-09 20:44:28 -07:00
tech	Added Power Model Files	2019-08-19 18:55:23 -06:00
vpr_arch	[Arch] Patch architecture due to missing mode bit definition	2021-07-02 11:41:29 -06:00
.gitignore	Added first draft of fpga_task script	2019-08-09 00:17:06 -06:00