OpenFPGA/vpr7_x2p/vpr/Circuits
AurelienUoU cc5a01d476 Fix waveform generation + add benchmark and update go.sh 2018-12-11 22:21:39 -07:00
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fifo_1bit.act Fix waveform generation + add benchmark and update go.sh 2018-12-11 22:21:39 -07:00
fifo_1bit.blif Fix waveform generation + add benchmark and update go.sh 2018-12-11 22:21:39 -07:00
fifo_1bit.v Fix waveform generation + add benchmark and update go.sh 2018-12-11 22:21:39 -07:00
pip_add.act Add pip_add benchmark 2018-12-11 15:29:48 -07:00
pip_add.blif Add pip_add benchmark 2018-12-11 15:29:48 -07:00
pip_add.v Update go.sh and upload pip_add.v 2018-12-11 15:47:05 -07:00
pip_add_yosys.v Edit waveform generator + fix clock mapping in autochecked testbench 2018-12-09 15:48:59 -07:00
s298_prevpr.act rename customized vpr7 to vpr7 XML to Production 2018-09-17 23:10:45 -06:00
s298_prevpr.blif rename customized vpr7 to vpr7 XML to Production 2018-09-17 23:10:45 -06:00