tangxifan cbb1545ee3 [Tool] Add connection builder for tile global ports to top-level module		2020-11-10 16:59:00 -07:00
..
annotation	[Debug aid] add pb_type full hierarchy path in the error message of architecture binding checker	2020-09-02 22:16:10 -06:00
base	[Tool] Split io location mapping builder from fabric builder	2020-11-02 18:27:34 -07:00
fabric	[Tool] Add connection builder for tile global ports to top-level module	2020-11-10 16:59:00 -07:00
fpga_bitstream	[Tool] Remove the limitation on requiring Qb ports for CCFF	2020-11-06 11:10:04 -07:00
fpga_sdc	[Tool] Refactor the codes for walking through io blocks	2020-11-03 13:21:50 -07:00
fpga_spice	[FPGA-SPICE] Add VDD/VSS ports to SPICE subckt instanciation	2020-09-20 15:21:33 -06:00
fpga_verilog	[Tool] Remove the limitation on requiring Qb ports for CCFF	2020-11-06 11:10:04 -07:00
mux_lib	bug fix in lut and mux module generation on supporting spypads	2020-04-22 14:41:16 -06:00
repack	[Tool] Relex logic block checking codes to skip zero-capacity nodes	2020-11-02 16:57:19 -07:00
tile_direct	bug fixed in tile direct builder	2020-03-21 12:43:56 -06:00
utils	[Tool] Remove redundant assertation	2020-11-09 09:42:39 -07:00
vpr_wrapper	add rr_segment binding to circuit model	2020-02-12 11:21:40 -07:00
ctag_src.sh	add ctags script to index openfpga source files	2020-01-24 10:15:16 -07:00
main.cpp	start transplanting FPGA-SPICE	2020-07-05 12:10:12 -06:00