tangxifan d64aeef5c4 add profiling to routing compact process		2019-07-03 16:57:34 -06:00
..
base	fixed a critical bug in using tileable route chan W	2019-07-03 16:46:43 -06:00
device/rr_graph	fixed a critical bug in using tileable route chan W	2019-07-03 16:46:43 -06:00
fpga_x2p	add profiling to routing compact process	2019-07-03 16:57:34 -06:00
mrfpga	cleaned unused variables	2019-05-13 14:45:02 -06:00
pack	cleaned unused variables	2019-05-13 14:45:02 -06:00
place	added Switch Block SubType and SubFs for tileable rr_graph generation	2019-07-02 10:00:02 -06:00
power	bug fixing for memory leaking in allocating pb_rr_graph and power estimation	2019-06-15 12:23:36 -06:00
route	update fpga_flow scripts to support matlab data format. Minor fix on rr_graph_area	2019-07-03 10:33:02 -06:00
timing	rename customized vpr7 to vpr7 XML to Production	2018-09-17 23:10:45 -06:00
util	basically finished the coding of tileable rr_graph generator. testing to go	2019-06-20 18:17:07 -06:00
ctags_vpr_src.sh	Correction of the SDC to remove global clocks	2019-05-30 15:04:21 -06:00
main.c	cleaned unused variables	2019-05-13 14:45:02 -06:00
shell_main.c	Update VPR7 X2P with new engine	2019-04-26 12:23:47 -06:00