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OpenFPGA
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OpenFPGA/vpr7_x2p/vpr/SRC/fpga_x2p
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tangxifan d64aeef5c4 add profiling to routing compact process 2019-07-03 16:57:34 -06:00
..
base add profiling to routing compact process 2019-07-03 16:57:34 -06:00
bitstream added Switch Block SubType and SubFs for tileable rr_graph generation 2019-07-02 10:00:02 -06:00
clb_pin_remap cleaned unused variables 2019-05-13 14:45:02 -06:00
router added Switch Block SubType and SubFs for tileable rr_graph generation 2019-07-02 10:00:02 -06:00
shell Merge branch 'multimode_clb' of https://github.com/LNIS-Projects/OpenFPGA into multimode_clb 2019-05-13 14:45:57 -06:00
spice added Switch Block SubType and SubFs for tileable rr_graph generation 2019-07-02 10:00:02 -06:00
verilog bug fixed for direct connection in CBs and direct connection in top netlist 2019-07-01 17:25:00 -06:00