tangxifan 1a1da30ae9 fixed a critical bug in using tileable route chan W		2019-07-03 16:46:43 -06:00
..
chan_node_details.cpp	bug fixing for tileable rr_graph generator.	2019-06-22 20:41:06 -06:00
chan_node_details.h	many bug fixing for tileable rr_graph generator. Still debugging	2019-06-21 17:58:46 -06:00
gsb_graph.cpp	start building object GSB graph	2019-06-17 22:10:30 -06:00
gsb_graph.h	start building object GSB graph	2019-06-17 22:10:30 -06:00
rr_graph_builder_utils.cpp	fixed a critical bug in using tileable route chan W	2019-07-03 16:46:43 -06:00
rr_graph_builder_utils.h	bug fixing in fpga_flow scripts and add more print-out message for VPR	2019-07-02 15:34:59 -06:00
rr_graph_fwd.h	fixed a bug in Verilog generator supporting SRAM5T	2019-06-13 14:42:39 -06:00
tileable_chan_details_builder.cpp	add a new option to the router to enable conversion of route_chan_width to be tileable	2019-07-03 12:11:48 -06:00
tileable_chan_details_builder.h	add a new option to the router to enable conversion of route_chan_width to be tileable	2019-07-03 12:11:48 -06:00
tileable_rr_graph_builder.cpp	bug fixing in fpga_flow scripts and add more print-out message for VPR	2019-07-02 15:34:59 -06:00
tileable_rr_graph_builder.h	add a new option to the router to enable conversion of route_chan_width to be tileable	2019-07-03 12:11:48 -06:00
tileable_rr_graph_gsb.cpp	added Switch Block SubType and SubFs for tileable rr_graph generation	2019-07-02 10:00:02 -06:00
tileable_rr_graph_gsb.h	added Switch Block SubType and SubFs for tileable rr_graph generation	2019-07-02 10:00:02 -06:00