riscv
/
OpenFPGA
mirror of https://github.com/lnis-uofu/OpenFPGA.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity
OpenFPGA/openfpga_flow
History
ganeshgore f6b3c5854a Bugfix : 
+ OpenFPGA template variables update
+ Default path for the verilog netlist
 		2020-04-11 16:45:22 -06:00
..
OpenFPGAShellScripts Bugfix : 2020-04-11 16:45:22 -06:00
SpiceNetlists Moved spice and verilog netlist folder location 2019-08-17 01:49:49 -06:00
VerilogNetlists Adding heterogeneous synthesis requirements 2019-12-03 16:09:26 -07:00
arch Added XML and benchmarks for testing 2020-04-06 00:32:06 -06:00
benchmarks Added XML and benchmarks for testing 2020-04-06 00:32:06 -06:00
docs Added first draft of fpga_task script 2019-08-09 00:17:06 -06:00
misc Updated openfpga_flow and task file to support sheel run 2020-04-06 00:34:36 -06:00
openfpga_arch Added XML and benchmarks for testing 2020-04-06 00:32:06 -06:00
scripts Bugfix : 2020-04-11 16:45:22 -06:00
tasks Bugfix : 2020-04-11 16:45:22 -06:00
tech Added Power Model Files 2019-08-19 18:55:23 -06:00
.gitignore Added first draft of fpga_task script 2019-08-09 00:17:06 -06:00