ganeshgore f6b3c5854a Bugfix : ... + OpenFPGA template variables update + Default path for the verilog netlist		2020-04-11 16:45:22 -06:00
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pro_blif.pl	Moved required files to openfpga folder	2019-08-19 18:57:42 -06:00
run_formality.py	Updated formality python script	2019-09-27 14:00:57 -06:00
run_fpga_flow.py	Bugfix :	2020-04-11 16:45:22 -06:00
run_fpga_task.conf	Updated to run with python3	2019-08-31 21:42:31 -06:00
run_fpga_task.py	Updated openfpga_flow and task file to support sheel run	2020-04-06 00:34:36 -06:00
run_modelsim.py	Updated modelsim and collected result	2019-11-16 19:10:04 -07:00
run_simulation_task.py	add python script for batch simulations	2019-11-15 14:23:03 -07:00