OpenFPGA/vpr7_x2p/vpr/SRC
tangxifan c3db880599 adding explicit file path to simulation info writer 2019-11-02 09:21:02 -06:00
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base refactoring Verilog formal verification top testbench using random vectors 2019-10-28 14:45:51 -06:00
device add local encoder support in bitstream generation refactoring 2019-10-24 22:49:24 -06:00
fpga_x2p adding explicit file path to simulation info writer 2019-11-02 09:21:02 -06:00
mrfpga cleaned unused variables 2019-05-13 14:45:02 -06:00
pack cleaned unused variables 2019-05-13 14:45:02 -06:00
place add option to compact tileable routing arch 2019-07-04 17:13:34 -06:00
power bug fixing for memory leaking in allocating pb_rr_graph and power estimation 2019-06-15 12:23:36 -06:00
route reduce some error message to warnings 2019-11-02 00:09:13 -06:00
timing rename customized vpr7 to vpr7 XML to Production 2018-09-17 23:10:45 -06:00
util Scan chain support in directlist 2019-09-27 16:53:00 -06:00
ctags_vpr_src.sh memory sanitized 2019-08-13 14:19:40 -06:00
main.c cleaned unused variables 2019-05-13 14:45:02 -06:00
shell_main.c Update VPR7 X2P with new engine 2019-04-26 12:23:47 -06:00