tangxifan c3db880599 adding explicit file path to simulation info writer		2019-11-02 09:21:02 -06:00
..
ARCH	Explicit verilog final push	2019-07-16 13:13:30 -06:00
Circuits	Add missing Verilog source, Archictecture folder and Testbenches correction	2019-05-13 16:41:35 -06:00
SRC	adding explicit file path to simulation info writer	2019-11-02 09:21:02 -06:00
SpiceNetlists	Moved spice and verilog netlist folder location	2019-08-17 01:49:49 -06:00
VerilogNetlists	Moved spice and verilog netlist folder location	2019-08-17 01:49:49 -06:00
CMakeLists.txt	Added mINI/lib - INI Read write to project	2019-09-27 13:58:48 -06:00
go_fpga_spice.sh	Update VPR7 X2P with new engine	2019-04-26 12:23:47 -06:00
go_fpga_verilog.sh	rename rr_switch_block to rr_gsb, a generic block	2019-06-06 17:41:01 -06:00
regression_verilog.sh	Moved spice and verilog netlist folder location	2019-08-17 01:49:49 -06:00