tangxifan 90a00da1df [Script] Split rewrite yosys scripts into two runs because yosys cannot output consistent verilog files using 'design -reset'		2021-03-10 13:56:35 -07:00
..
OpenFPGA_lib	Adding heterogeneous synthesis requirements	2019-12-03 16:09:26 -07:00
formality_template.tcl	Updated formality python script	2019-09-27 14:00:57 -06:00
fpgaflow_default_tool_path.conf	[Cleanup] Removed deadcode	2021-02-03 10:35:14 -07:00
modelsim_proc.tcl	Added task support for modelsim script	2019-11-15 23:23:15 -07:00
modelsim_runsim.tcl	Fixed modelsim include references	2020-06-11 19:28:13 -06:00
qlf_yosys.ys	[Script] Update quicklogic's script to output correct verilog file name	2021-03-08 21:39:44 -07:00
yosys_bram_adder_template.ys	Adding heterogeneous synthesis requirements	2019-12-03 16:09:26 -07:00
ys_tmpl_rewrite_flow.ys	[Script] Split rewrite yosys scripts into two runs because yosys cannot output consistent verilog files using 'design -reset'	2021-03-10 13:56:35 -07:00
ys_tmpl_yosys_vpr_flow.ys	Added fpga_flow script - Working Yosys	2019-08-09 16:49:05 -06:00
ys_tmpl_yosys_vpr_flow_with_rewrite.ys	[Script] Split rewrite yosys scripts into two runs because yosys cannot output consistent verilog files using 'design -reset'	2021-03-10 13:56:35 -07:00