tangxifan b9e1b1afc4 fix a critical bug in num_reserved_sram_ports		2019-06-05 17:31:01 -06:00
..
ARCH	Update spice path in architecture	2019-05-29 10:08:58 -06:00
Circuits	Add missing Verilog source, Archictecture folder and Testbenches correction	2019-05-13 16:41:35 -06:00
SRC	fix a critical bug in num_reserved_sram_ports	2019-06-05 17:31:01 -06:00
SpiceNetlists	Update VPR7 X2P with new engine	2019-04-26 12:23:47 -06:00
VerilogNetlists	Add travis full path to avoid missing sources	2019-05-16 15:51:10 -06:00
CMakeLists.txt	Force graphics to false	2019-05-15 15:01:54 -06:00
Makefile	fixed bugs in CMakeLists.txt and Makefile	2019-05-03 23:03:04 -06:00
go_fpga_spice.sh	Update VPR7 X2P with new engine	2019-04-26 12:23:47 -06:00
go_fpga_verilog.sh	add side mirror detection for RRSwitchBlock	2019-06-04 13:01:22 -06:00
regression_verilog.sh	Fix sdc analysis bug related to virtual nodes + add the option in regression test	2019-06-05 12:10:28 -06:00