Lalit Sharma b8bbb8f284 Fixing an issue in variable naming which was changed in last checkin		2021-04-19 03:36:27 -07:00
..
arch_bitstreams	[Architecture] Update external bitstream	2020-09-25 21:30:59 -06:00
benchmarks	Merge branch 'master' into dff_techmap	2021-04-16 20:54:28 -06:00
docs	Added first draft of fpga_task script	2019-08-09 00:17:06 -06:00
fabric_keys	[Architecture] Add example fabric key using multiple regions	2020-09-29 14:14:50 -06:00
misc	Providing an option to specify yosys through env var YOSYS rather than picking from the repo as yosys submodule	2021-04-19 03:36:27 -07:00
openfpga_arch	[Arch] patch architectures to be consistent with port mapping of custom DFF in yosys script	2021-04-16 20:47:39 -06:00
openfpga_cell_library	[HDL] Add HDL for 8-bit single-mode multiplier	2021-03-23 15:36:09 -06:00
openfpga_shell_scripts	[Script] Update openfpga shell script w/o ace usage to adapt pin constraint files	2021-04-17 15:04:51 -06:00
openfpga_simulation_settings	[Arch] Add simulation setting for 8-clock architectures	2021-02-22 11:10:03 -07:00
openfpga_yosys_techlib	[HDL] Patch dff models used in yosys tech map	2021-04-16 20:48:15 -06:00
regression_test_scripts	Merge branch 'master' into dff_techmap	2021-04-16 20:54:28 -06:00
scripts	Providing an option to specify yosys through env var YOSYS rather than picking from the repo as yosys submodule	2021-04-19 03:36:27 -07:00
tasks	Fixing an issue in variable naming which was changed in last checkin	2021-04-19 03:36:27 -07:00
tech	Added Power Model Files	2019-08-19 18:55:23 -06:00
vpr_arch	[Arch] Revert to old version arch due to editing by mistake	2021-04-16 20:58:32 -06:00
.gitignore	Added first draft of fpga_task script	2019-08-09 00:17:06 -06:00