Providing an option to specify yosys through env var YOSYS rather than picking from the repo as yosys submodule

openfpga_flow/misc/qlf_yosys.tcl

@@ -1,4 +1,9 @@
 # Yosys synthesis script for ${TOP_MODULE}
+yosys -import
+
+if { [info procs ql-qlf] == {} } { plugin -i ql-qlf }
+yosys -import  ;# ingest plugin commands
+
 # Read verilog files
 ${READ_VERILOG_FILE}
 

openfpga_flow/misc/ys_tmpl_rewrite_flow.tcl

@@ -1,4 +1,6 @@
 # Rewrite the .blif to Verilog
 # so that the pin sequence matches
+yosys -import
+
 read_blif rewritten_${OUTPUT_BLIF}
 write_verilog ${OUTPUT_VERILOG}

openfpga_flow/misc/ys_tmpl_yosys_vpr_bram_dsp_flow.tcl

@@ -1,4 +1,5 @@
 # Yosys synthesis script for ${TOP_MODULE}
+yosys -import
 
 #########################
 # Parse input files
@@ -14,7 +15,7 @@ read_verilog -lib -specify ${YOSYS_CELL_SIM_VERILOG}
 # Identify top module from hierarchy
 hierarchy -check -top ${TOP_MODULE}
 # - Convert process blocks to AST
-proc
+procs
 # Flatten all the gates/primitives
 flatten
 # Identify tri-state buffers from 'z' signal in AST

openfpga_flow/misc/ys_tmpl_yosys_vpr_bram_flow.tcl

@@ -1,4 +1,5 @@
 # Yosys synthesis script for ${TOP_MODULE}
+yosys -import
 
 #########################
 # Parse input files
@@ -14,7 +15,7 @@ read_verilog -lib -specify ${YOSYS_CELL_SIM_VERILOG}
 # Identify top module from hierarchy
 hierarchy -check -top ${TOP_MODULE}
 # - Convert process blocks to AST
-proc
+procs
 # Flatten all the gates/primitives
 flatten
 # Identify tri-state buffers from 'z' signal in AST

openfpga_flow/misc/ys_tmpl_yosys_vpr_dsp_flow.tcl

@@ -1,4 +1,5 @@
 # Yosys synthesis script for ${TOP_MODULE}
+yosys -import
 
 #########################
 # Parse input files
@@ -14,7 +15,7 @@ read_verilog -lib -specify ${YOSYS_CELL_SIM_VERILOG}
 # Identify top module from hierarchy
 hierarchy -check -top ${TOP_MODULE}
 # - Convert process blocks to AST
-proc
+procs
 # Flatten all the gates/primitives
 flatten
 # Identify tri-state buffers from 'z' signal in AST
@@ -93,4 +94,4 @@ stat
 # Output netlists
 #########################
 opt_clean -purge
-write_blif ${OUTPUT_BLIF}
+write_blif ${OUTPUT_BLIF}

openfpga_flow/misc/ys_tmpl_yosys_vpr_flow.tcl

@@ -1,10 +1,13 @@
 # Yosys synthesis script for ${TOP_MODULE}
+
+yosys -import
+
 # Read verilog files
 ${READ_VERILOG_FILE}
 
 # Technology mapping
 hierarchy -top ${TOP_MODULE}
-proc
+procs
 techmap -D NO_LUT -map +/adff2dff.v
 
 # Synthesis

openfpga_flow/misc/ys_tmpl_yosys_vpr_flow_with_rewrite.tcl

@@ -1,10 +1,12 @@
 # Yosys synthesis script for ${TOP_MODULE}
+yosys -import
+
 # Read verilog files
 ${READ_VERILOG_FILE}
 
 # Technology mapping
 hierarchy -top ${TOP_MODULE}
-proc
+procs
 techmap -D NO_LUT -map +/adff2dff.v
 
 # Synthesis

openfpga_flow/scripts/run_fpga_flow.py

@@ -497,13 +497,24 @@ def run_yosys_with_abc():
         ys_params[tmpVar] = OpenFPGAArgs[indx+1]
     
     yosys_template = args.yosys_tmpl if args.yosys_tmpl else os.path.join(
-        cad_tools["misc_dir"], "ys_tmpl_yosys_vpr_flow.ys")
+        cad_tools["misc_dir"], "ys_tmpl_yosys_vpr_flow.tcl")
     tmpl = Template(open(yosys_template, encoding='utf-8').read())
-    with open("yosys.ys", 'w') as archfile:
+    with open("yosys.tcl", 'w') as archfile:
         archfile.write(tmpl.safe_substitute(ys_params))
-
+    
+    yosys_path = get_yosys_path()
     run_command("Run yosys", "yosys_output.log",
-                [cad_tools["yosys_path"], 'yosys.ys'])
+                [yosys_path, 'yosys.tcl'])
+
+
+def get_yosys_path():
+    yosys_path=""
+    if 'YOSYS' in os.environ and os.environ['YOSYS'] != '':
+        yosys_path = os.environ.get("YOSYS")
+    else:
+        yosys_path = cad_tools["yosys_path"]
+    
+    return yosys_path
 
 
 def run_odin2():
@@ -696,12 +707,13 @@ def run_rewrite_verilog():
     # Rewrite the verilog after optimization
     # If there is no template script provided, use a default template
     # If there is a template script provided, replace parameters from configuration
+    yosys_path = get_yosys_path()
     if not args.ys_rewrite_tmpl:
         script_cmd = [
             "read_blif %s" % args.top_module+".blif",
             "write_verilog %s" % args.top_module+"_output_verilog.v"
         ]
-        command = [cad_tools["yosys_path"], "-p", "; ".join(script_cmd)]
+        command = [yosys_path, "-p", "; ".join(script_cmd)]
         run_command("Yosys", "yosys_rewrite.log", command)
     else:
         # Yosys script parameter mapping
@@ -724,10 +736,10 @@ def run_rewrite_verilog():
         for iteration_idx, curr_rewrite_tmpl in enumerate(args.ys_rewrite_tmpl.split(";")):
             tmpl = Template(open(curr_rewrite_tmpl, encoding='utf-8').read())
             logger.info("Yosys rewrite iteration: " + str(iteration_idx))
-            with open("yosys_rewrite_" + str(iteration_idx) + ".ys", 'w') as archfile:
+            with open("yosys_rewrite_" + str(iteration_idx) + ".tcl", 'w') as archfile:
                 archfile.write(tmpl.safe_substitute(ys_rewrite_params))
             run_command("Run yosys", "yosys_rewrite_output.log",
-                    [cad_tools["yosys_path"], "yosys_rewrite_" + str(iteration_idx) + ".ys"])
+                    [yosys_path, "yosys_rewrite_" + str(iteration_idx) + ".tcl"])
 
 
 

openfpga_flow/tasks/basic_tests/k4_series/k4n4_bram/config/task.conf

@@ -32,7 +32,7 @@ arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_frac_N4_tileable_adder_cha
 bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v
 
 [SYNTHESIS_PARAM]
-bench_yosys_common=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_yosys_vpr_bram_flow.ys
+bench_yosys_common=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_yosys_vpr_bram_flow.tcl
 bench0_top = and2
 
 [SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]

openfpga_flow/tasks/benchmark_sweep/vtr_benchmarks/config/task.conf

@@ -65,7 +65,7 @@ bench18=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/vtr_benchmark/stereovisio
 #bench21=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/vtr_benchmark/LU64PEEng.v
 
 [SYNTHESIS_PARAM]
-bench_yosys_common=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_yosys_vpr_bram_dsp_flow.ys
+bench_yosys_common=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_yosys_vpr_bram_dsp_flow.tcl
 # Benchmark ch_intrinsics
 bench0_top = bgm
 bench1_top = RLE_BlobMerging

openfpga_flow/tasks/fpga_verilog/dsp/single_mode_mult_8x8/config/task.conf

@@ -33,8 +33,8 @@ arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_frac_N8_tileable_reset_sof
 bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/mac_8/mac_8.v
 
 [SYNTHESIS_PARAM]
-bench_yosys_common=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_yosys_vpr_dsp_flow.ys
-bench_yosys_rewrite_common=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_yosys_vpr_flow_with_rewrite.ys;${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_rewrite_flow.ys
+bench_yosys_common=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_yosys_vpr_dsp_flow.tcl
+bench_yostcl=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_yosys_vpr_flow_with_rewrite.tcl;${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_rewrite_flow.tcl
 
 bench0_top = mac_8
 

openfpga_flow/tasks/quicklogic_tests/counter_5clock_test/config/task.conf

@@ -31,6 +31,6 @@ bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/quicklogic_tests/counter12
 
 [SYNTHESIS_PARAM]
 bench0_top = counter120bitx5
-bench0_yosys=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/qlf_yosys.ys
+bench0_yosys=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/qlf_yosys.tcl
 
 [SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]

openfpga_flow/tasks/quicklogic_tests/flow_test/config/task.conf

@@ -53,7 +53,7 @@ bench18=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/quicklogic_tests/multi_en
 #bench19=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/quicklogic_tests/sdc_controller/rtl/*.v
 
 [SYNTHESIS_PARAM]
-bench_yosys_common=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/qlf_yosys.ys
+bench_yosys_common=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/qlf_yosys.tcl
 
 bench0_top = io_tc1
 bench1_top = unsigned_mult_80

openfpga_flow/tasks/quicklogic_tests/lut_adder_test/config/task.conf

@@ -30,8 +30,8 @@ arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_frac_N8_tileable_reset_sof
 bench1=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/adder_8/adder_8.v
 
 [SYNTHESIS_PARAM]
-bench_yosys_common=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/qlf_yosys.ys
-bench_yosys_rewrite_common=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_yosys_vpr_flow_with_rewrite.ys;${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_rewrite_flow.ys
+bench_yosys_common=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/qlf_yosys.tcl
+bench_yosys_rewrite_common=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_yosys_vpr_flow_with_rewrite.ys;${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_rewrite_flow.tcl
 
 bench1_top = adder_8