tangxifan b374056e78 fix bug in duplicate pin addition		2019-12-26 16:24:05 -07:00
..
backend_assistant	remove unused codes and parameters	2019-12-24 20:43:29 -07:00
base	added pin duplication support to grid module builder	2019-12-25 22:24:44 -07:00
bitstream	critical bugs fixed for routing module naming; and speed up local wire detection in Verilog writer	2019-11-08 15:01:30 -07:00
clb_pin_remap	cleaned unused variables	2019-05-13 14:45:02 -06:00
module_builder	fix bug in duplicate pin addition	2019-12-26 16:24:05 -07:00
router	fixed bugs in configure pb_rr_graph and dependence on testbenches	2019-08-16 18:20:30 -06:00
shell	deleting legacy codes: fpga_verilog top-level function	2019-12-04 15:55:16 -07:00
spice	Rename SCFF to CCFF, configuration chain flip flop	2019-09-26 11:32:57 -06:00
verilog	remove legacy verilog utils functions	2019-12-04 18:02:26 -07:00