tangxifan 592e2e310c [script] typo		2023-12-12 13:45:23 -08:00
..
formality_template.tcl	Updated formality python script	2019-09-27 14:00:57 -06:00
fpgaflow_default_tool_path.conf	[script] typo	2023-12-12 13:45:23 -08:00
fpgaflow_default_tool_path_timing.conf	[script] typo	2023-12-12 13:45:23 -08:00
modelsim_proc.tcl	Added task support for modelsim script	2019-11-15 23:23:15 -07:00
modelsim_runsim.tcl	Fixed modelsim include references	2020-06-11 19:28:13 -06:00
qlf_yosys.ys	Changed HDL files reading to be as a single compilation unit in yosys_vpr flow for Verific mode. Changed '' variable to 'read_verilog ' in yosys template scripts. Updated task configs accordingly.	2022-01-17 13:21:29 +05:00
ys_tmpl_rewrite_flow.ys	[Script] Split rewrite yosys scripts into two runs because yosys cannot output consistent verilog files using 'design -reset'	2021-03-10 13:56:35 -07:00
ys_tmpl_yosys_vpr_adder_flow.ys	[test] fixed the bug in adder mapping	2023-06-20 17:09:31 -07:00
ys_tmpl_yosys_vpr_bram_dsp_dff_flow.ys	Changed HDL files reading to be as a single compilation unit in yosys_vpr flow for Verific mode. Changed '' variable to 'read_verilog ' in yosys template scripts. Updated task configs accordingly.	2022-01-17 13:21:29 +05:00
ys_tmpl_yosys_vpr_bram_dsp_flow.ys	Changed HDL files reading to be as a single compilation unit in yosys_vpr flow for Verific mode. Changed '' variable to 'read_verilog ' in yosys template scripts. Updated task configs accordingly.	2022-01-17 13:21:29 +05:00
ys_tmpl_yosys_vpr_bram_flow.ys	Changed HDL files reading to be as a single compilation unit in yosys_vpr flow for Verific mode. Changed '' variable to 'read_verilog ' in yosys template scripts. Updated task configs accordingly.	2022-01-17 13:21:29 +05:00
ys_tmpl_yosys_vpr_dff_flow.ys	Changed HDL files reading to be as a single compilation unit in yosys_vpr flow for Verific mode. Changed '' variable to 'read_verilog ' in yosys template scripts. Updated task configs accordingly.	2022-01-17 13:21:29 +05:00
ys_tmpl_yosys_vpr_dsp_flow.ys	[test] debugging	2023-01-24 17:57:34 -08:00
ys_tmpl_yosys_vpr_dsp_flow_with_rewrite.ys	[test] fixed remaining bugs	2023-01-24 18:00:04 -08:00
ys_tmpl_yosys_vpr_flow.ys	Changed HDL files reading to be as a single compilation unit in yosys_vpr flow for Verific mode. Changed '' variable to 'read_verilog ' in yosys template scripts. Updated task configs accordingly.	2022-01-17 13:21:29 +05:00
ys_tmpl_yosys_vpr_flow_with_rewrite.ys	[Script] Support simplified rewriting for Yosys on output verilog	2022-02-18 14:54:39 -08:00