tangxifan a3a98fa21d [Arch] Bug fix for port name mismatching between openfpga cell library and architecture definition		2021-04-24 14:56:10 -06:00
..
arch_bitstreams	[Architecture] Update external bitstream	2020-09-25 21:30:59 -06:00
benchmarks	[Benchmark] Add more micro benchmarks for mac ranging from 8 bit to 32 bit	2021-04-23 20:36:28 -06:00
docs	Added first draft of fpga_task script	2019-08-09 00:17:06 -06:00
fabric_keys	[Architecture] Add example fabric key using multiple regions	2020-09-29 14:14:50 -06:00
misc	[Script] Add yosys script supporting customize DFF/BRAM/DSP mapping	2021-04-21 19:50:07 -06:00
openfpga_arch	[Arch] Bug fix for port name mismatching between openfpga cell library and architecture definition	2021-04-24 14:56:10 -06:00
openfpga_cell_library	[HDL] Add verilog netlist for the fracturable 16-bit multiplier blocks	2021-04-23 22:12:26 -06:00
openfpga_shell_scripts	[Script] Enable constant net routing for heterogeneous FPGAs	2021-04-23 20:44:36 -06:00
openfpga_simulation_settings	[Arch] Add simulation setting for 8-clock architectures	2021-02-22 11:10:03 -07:00
openfpga_yosys_techlib	[HDL] Add tech library for architecture using multi-mode 16-bit DSP blocks	2021-04-24 13:30:46 -06:00
regression_test_scripts	[Test] Add golden results for IWLS2005 as a simple QoR check	2021-04-22 19:27:31 -06:00
scripts	[Script] Add tolerance options to check qor script	2021-03-23 12:26:33 -06:00
tasks	[Test] Add new test for multi-mode 16-bit DSP blocks	2021-04-24 13:29:29 -06:00
tech	Added Power Model Files	2019-08-19 18:55:23 -06:00
vpr_arch	[Arch] Add a new architecture using fracturable 16-bit DSP blocks	2021-04-24 14:01:42 -06:00
.gitignore	Added first draft of fpga_task script	2019-08-09 00:17:06 -06:00