* BRAM preload data - generic way to extract data from design
* Add docs and support special __layout__ case
* Add test
* Fix warning
* Change none-fabric to non-fabric
* LUTRAM Support Phase 1
* Add Test
* Add more protocol checking to enable LUTRAM feature
* Move the config setting under config protocol
* Revert any changes
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Co-authored-by: chungshien-chai <chungshien.chai@gmail.com>
Please reveal the following architecture features in the names to help quickly spot architecture files.
Note that an OpenFPGA architecture can be applied to multiple VPR architecture files.
k<lut_size>_: Look-Up Table (LUT) size of FPGA. If you have fracturable LUTs or multiple LUT circuits, this should be largest input size.
The keyword 'frac' is to specify if fracturable LUT is used or not.
The keyword 'Native' is to specify if fracturable LUT design is a native one (without mode switch) or a standard one (with mode switch).
N<le_size>: Number of logic elements for a CLB. If you have multiple CLB architectures, this should be largest number.
fracff<2edge>: Use multi-mode flip-flop model, where reset/set polarity is configurable. When 2edge is specified, clock polarity can be switched between postive edge triggered and negative edge triggered
adder_chain: If hard adder/carry chain is used inside CLBs
register_chain: If shift register chain is used inside CLBs
scan_chain: If scan chain testing infrastructure is used inside CLBs
__dsp<dsp_size>reg: If Digital Signal Processor (DSP) is used or not. If used, the input size should be clarified here.
The keyword 'wide' is to specify if the DSP spans more than 1 column.
The keyword 'frac' is to specify if the DSP is fracturable to operate in different modes.
The keyword 'reg' is to specify if the DSP has input and output registers. If only input or output registers are used, the keyword will be 'regin' or 'regout' respectively.
mem<mem_size>: If block RAM (BRAM) is used or not. If used, the memory size should be clarified here. The keyword wide is to specify if the BRAM spanns more than 1 column.
aib: If the Advanced Interface Bus (AIB) is used in place of some I/Os.
<bank|cc|frame|standalone>: specify the type of configuration protocol used in the architecture.
bank refers to the memory bank
cc refers to the configuration chain. Note that a postfix <int>clk may be applied when the configuration chain is controlled by more than 1 clocks
frame refers to the frame-based organization
standalone referes to the vanilla organization
fixed_sim: fixed clock frequencies in simulation settings. If auto clock frequencies are used, there is no need to appear in the naming
intermediate buffer: If intermediate buffers are used in LUT designs.
behavioral: If behavioral Verilog modeling is specified
local_encoder: If local encoders are used in routing multiplexer design
spyio/spypad: If spy I/Os are used
registerable_io: If I/Os are registerable (can be either combinational or sequential)
IoSubtile: If I/O block contains sub tiles (more compact with a higher density of I/Os)
stdcell: If circuit designs are built with standard cells only
tree_mux: If routing multiplexers are built with a tree-like structure
localClkGen: The clock signal of CLB can be generated by internal programmable resources
<feature_size>: The technology node which the delay numbers are extracted from.
powergate : The FPGA has power-gating techniques applied. If not defined, there is no power-gating.
GlobalTileClk: How many clocks are defined through global ports from physical tiles.
is the number of clocks
When specified, multiple clocks are in separated pins with different names
abspath: All the paths in the architecture file are absolute and hardcoded.
Other features are used in naming should be listed here.
