Andrew Pond 8f18a9ad9a added complete bram sizing files		2022-02-07 12:19:31 -07:00
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common	added complete bram sizing files	2022-02-07 12:19:31 -07:00
k4_frac_N8_tileable_adder_chain_dpram1K_dsp18_fracff_skywater130nm	adder chain arch working	2021-11-10 16:20:31 -07:00
k4_frac_N8_tileable_adder_chain_dpram8K_dsp18_fracff_skywater130nm	added fpgatoolperf vexriscv src	2021-09-28 13:32:41 -06:00
k6_frac_N10_tileable_adder_chain_dpram1K_dsp18_fracff_skywater130nm	fixed CI errors	2021-07-22 16:39:44 -06:00
k4_frac_N8_tileable_adder_chain_dpram1K_dsp18_fracff_skywater130nm_dff_map.v	started updating timings	2021-07-19 10:48:55 -06:00
k4_frac_N8_tileable_reset_softadder_register_scan_chain_dsp8_nonLR_caravel_io_skywater130nm_cell_sim.v	[HDL] Add yosys tech lib for a DSP-only heterogeneous FPGA	2021-03-23 15:30:41 -06:00
k4_frac_N8_tileable_reset_softadder_register_scan_chain_dsp8_nonLR_caravel_io_skywater130nm_dsp_map.v	[HDL] Add yosys tech lib for a DSP-only heterogeneous FPGA	2021-03-23 15:30:41 -06:00
k4_frac_N8_tileable_reset_softadder_register_scan_chain_frac_dsp16_nonLR_caravel_io_skywater130nm_cell_sim.v	[HDL] Add tech library for architecture using multi-mode 16-bit DSP blocks	2021-04-24 13:30:46 -06:00
k4_frac_N8_tileable_reset_softadder_register_scan_chain_frac_dsp16_nonLR_caravel_io_skywater130nm_dsp_map.v	[HDL] Add tech library for architecture using multi-mode 16-bit DSP blocks	2021-04-24 13:30:46 -06:00
k6_frac_N10_tileable_adder_chain_dpram8K_dsp36_40nm_bram.txt	[HDL] Rename tech lib to be consistent with arch name changes	2021-03-20 18:08:03 -06:00
k6_frac_N10_tileable_adder_chain_dpram8K_dsp36_40nm_bram_map.v	[HDL] Patch the yosys techlib for the heterogeneous FPGA by using little endian	2021-03-23 15:44:53 -06:00
k6_frac_N10_tileable_adder_chain_dpram8K_dsp36_40nm_cell_sim.v	[HDL] Patch the yosys techlib for the heterogeneous FPGA by using little endian	2021-03-23 15:44:53 -06:00
k6_frac_N10_tileable_adder_chain_dpram8K_dsp36_40nm_dsp_map.v	[HDL] Patch the yosys techlib for the heterogeneous FPGA by using little endian	2021-03-23 15:44:53 -06:00
k6_frac_N10_tileable_adder_chain_dpram8K_dsp36_fracff_40nm_cell_sim.v	[HDL] Enriched DFF model in yosys technology library	2021-04-21 22:49:05 -06:00
k6_frac_N10_tileable_adder_chain_dpram8K_dsp36_fracff_40nm_dff_map.v	[HDL] Enriched DFF model in yosys technology library	2021-04-21 22:49:05 -06:00
k6_frac_N10_tileable_adder_chain_mem1K_40nm_bram.txt	fixed bram CI error	2021-07-23 11:16:26 -06:00
k6_frac_N10_tileable_adder_chain_mem1K_40nm_bram_map.v	fixed bram CI error	2021-07-23 11:16:26 -06:00
k6_frac_N10_tileable_adder_chain_mem1K_40nm_cell_sim.v	finishing touches for PR	2021-07-23 12:08:32 -06:00