Go to file
tangxifan 8e817287ae
Merge pull request #808 from lnis-uofu/patch_update
Pulling refs/heads/master into master
2022-09-23 17:14:45 -07:00
.github Update patch_updater.yml 2022-09-21 21:52:23 -07:00
cmake copy missing cmake modules from vtr project 2020-01-03 21:57:19 -05:00
docker [ci] now revert to Ubuntu 18.04, see if docker can work or not 2022-08-26 21:09:27 -07:00
docs [doc] update documentation about the new option 2022-09-12 16:58:32 -07:00
libs [vpr] fixed a bug when parsing conventional pin loc 2022-09-08 16:53:00 -07:00
openfpga [engine] fixed a bug when decoding bitstream for connnection blocks: now use incoming edges from gsb 2022-09-19 18:49:54 -07:00
openfpga_flow [arch] update missing arch 2022-09-21 16:52:32 -07:00
vtr-verilog-to-routing@2f1bfd3208 [engine] update vtr 2022-09-19 15:35:23 -07:00
yosys@dca8fb54aa [Github] Now use YosysHQ v0.10 release as a submodule 2021-10-29 14:19:26 -07:00
yosys-plugins@0713ed79ab Bump yosys-plugins from `da93173` to `0713ed7` 2022-08-30 06:25:08 +00:00
.dockerignore [CiFix] Docker image 2022-08-29 00:40:37 -06:00
.gitignore Added binder temp files to ignore 2022-05-03 14:20:10 -06:00
.gitmodules [submodule] now use a feature branch of VTR as a submodule 2022-08-16 13:49:41 -07:00
.readthedocs.yml Support SVG in Sphinx Latex building (#220) 2021-02-07 18:53:16 -07:00
CMakeLists.txt [script] fixed typo on IPO options 2022-08-24 21:51:29 -07:00
Dockerfile Added binder temp files to ignore 2022-05-03 14:20:10 -06:00
LICENSE Create LICENSE 2018-06-26 21:52:08 -07:00
Makefile [ci] streamline workflow file by moving cmake commands to top-level makefile 2022-08-24 16:26:12 -07:00
README.md Updated readme 2022-09-23 11:08:44 -06:00
VERSION.md Updated Patch Count 2022-09-24 00:04:00 +00:00
openfpga.sh [test] bug fix 2022-05-22 14:47:25 +08:00
requirements.txt [Cleanup] Removed deadcode 2021-02-03 10:35:14 -07:00

README.md

Getting Started with OpenFPGA

linux build Documentation Status Binder

Version: see VERSION.md

Introduction

The award-winning OpenFPGA framework is the first open-source FPGA IP generator supporting highly-customizable homogeneous FPGA architectures. OpenFPGA provides complete EDA support for customized FPGAs, including Verilog-to-bitstream generation and self-testing verification. OpenFPGA opens the door to democratizing FPGA technology and EDA techniques with agile prototyping approaches and constantly evolving EDA tools for chip designers and researchers.

If this is your first time working with OpenFPGA, we strongly recommend you watch the introduction video about OpenFPGA

A quick overview of OpenFPGA tools can be found here. We also recommend potential users check out the summary of technical capabilities before compiling.

Compilation

A tutorial video about how to compile can be found here

Before starting, we strongly recommend you read the required dependencies at compilation guidelines. It also includes detailed information about the docker image.


Compilation Steps:

# Clone the repository and go inside it
git clone https://github.com/LNIS-Projects/OpenFPGA.git && cd OpenFPGA
make all

Quick Compilation Verification

To quickly verify the tool is well compiled, the user can run the following command from the OpenFPGA root directory.

source openfpga.sh
run-task compilation_verification --debug --show_thread_logs

Python3 and iVerilog v10.1+ are required. GUI will pop up if enabled during compilation.


Supported Operating Systems

We currently target OpenFPGA for:

  1. Ubuntu 18.04
  2. Red Hat 7.5

The tool was tested with these operating systems. It might work with earlier versions and other distributions.

Running with pre-built docker image

# To get the docker image from the repository,
docker pull ghcr.io/lnis-uofu/openfpga-master:latest

# To invoke openfpga_shell
docker run -it ghcr.io/lnis-uofu/openfpga-master:latest openfpga/openfpga bash

Backward compatibility with OpenFPGA v1.1

OpenFPGA v1.2 is a major upgrade over v1.1, which upgrades the internal VPR engine. The (VPR) architecture files used with v1.1 may not be compatible with v1.2.

You can upgrade your architecture files with script

python3 openfpga_flow/scripts/arch_file_updater.py \
    --input_file ${v1.1_arch_file} \
    --output_file ${v1.2_compatible_arch_file}

Or, If you want to stay with v1.1, the final build was (tag: _OpenFPGA:v1.1.541)

https://github.com/lnis-uofu/OpenFPGA/tree/v1.1.541

or you can download the docker image

docker pull ghcr.io/lnis-uofu/openfpga-master:v1.1.541

Documentation

OpenFPGA's full documentation includes tutorials, descriptions of the design flow, and tool options.

Tutorials

You can find a set of tutorials, with which you get familiar with the tool and use OpenFPGA for various purposes.