tangxifan 79b260f5e1 [arch] update missing arch		2022-09-21 16:52:32 -07:00
..
arch_bitstreams	[test] update arch bitstream and force a pin placement for the test case where external bistream is fixed	2022-09-20 14:14:18 -07:00
benchmarks	[benchmark] Now the rst_on_lut benchmark has a comb output driven by rst	2022-09-12 10:43:21 -07:00
docs	Added first draft of fpga_task script	2019-08-09 00:17:06 -06:00
fabric_keys	[Arch] Add an example fabric key that models a shift-register-based QuickLogic memory bank using custom chain organization	2021-10-11 09:49:22 -07:00
misc	[script] fixed a bug on wrong path to the ace2 executable	2022-08-23 10:53:44 -07:00
openfpga_arch	[test] fixed a bug	2022-09-20 18:12:23 -07:00
openfpga_cell_library	[arch] add arch that supports negative edge triggered flip-flop	2022-05-09 16:32:01 +08:00
openfpga_shell_scripts	[test] fixed a bug in pin constrain examples	2022-09-21 14:10:12 -07:00
openfpga_simulation_settings	[Script] Bug fix in slow clock frequency in shift register chain contraints	2021-10-06 16:49:01 -07:00
openfpga_yosys_techlib	[arch] fixed a few bugs	2022-05-09 17:22:48 +08:00
regression_test_scripts	Merge branch 'master' into vtr_upgrade	2022-09-20 21:08:06 -07:00
scripts	[script] now build task_result.csv from openfpgashell.log rather than vpr_stdout.log because of missing block usage numbers	2022-09-20 13:46:30 -07:00
tasks	[arch] update missing arch	2022-09-21 16:52:32 -07:00
tech	Added Power Model Files	2019-08-19 18:55:23 -06:00
vpr_arch	Merge branch 'vtr_upgrade' of github.com:lnis-uofu/OpenFPGA into vtr_upgrade	2022-09-20 22:38:06 -07:00
.gitignore	Added first draft of fpga_task script	2019-08-09 00:17:06 -06:00