tangxifan 7af6d7f07d [Benchmark] change the pin sequence of counter4bit_2clock to be easy for testbench generation		2021-01-13 15:38:44 -07:00
..
arch_bitstreams	[Architecture] Update external bitstream	2020-09-25 21:30:59 -06:00
benchmarks	[Benchmark] change the pin sequence of counter4bit_2clock to be easy for testbench generation	2021-01-13 15:38:44 -07:00
docs	Added first draft of fpga_task script	2019-08-09 00:17:06 -06:00
fabric_keys	[Architecture] Add example fabric key using multiple regions	2020-09-29 14:14:50 -06:00
misc	Bumping yosys submodule with the latest changes done in yosys repo related to OpenFPGA flow	2021-01-08 07:08:24 -08:00
openfpga_arch	[Doc] Update documentation about architecture naming rules	2021-01-12 18:01:24 -07:00
openfpga_cell_library	[HDL] Update dff netlist for SCFF used in configuration chain	2021-01-04 17:17:35 -07:00
openfpga_shell_scripts	[Flow] Add new script for fixed device layout using global tile clock	2021-01-10 11:08:02 -07:00
openfpga_simulation_settings	add example simulation setting for openfpga flow	2020-06-11 19:31:15 -06:00
scripts	[Bugfix] Honors yosys_tmpl parameter in flow script	2020-12-03 12:24:24 -07:00
tasks	[Test] Use counter4bit in the multi-clock test	2021-01-13 13:34:59 -07:00
tech	Added Power Model Files	2019-08-19 18:55:23 -06:00
vpr_arch	[Doc] Update documentation for VPR architectures	2021-01-12 17:57:40 -07:00
.gitignore	Added first draft of fpga_task script	2019-08-09 00:17:06 -06:00