tangxifan c6ac02d210 [FPGA-SPICE] Add VDD/VSS ports to SPICE subckt instanciation		2020-09-20 15:21:33 -06:00
..
annotation	[Debug aid] add pb_type full hierarchy path in the error message of architecture binding checker	2020-09-02 22:16:10 -06:00
base	[FPGA-SPICE] add SPICE writer for logic blocks	2020-09-20 12:38:24 -06:00
fabric	[OPENFPGA LIBRARY] change method names to be consistent with FPGA-SPICE needs	2020-09-20 12:03:10 -06:00
fpga_bitstream	bug fix in fabric bitstream XML syntax	2020-07-27 19:22:36 -06:00
fpga_sdc	hotfix on treating the dangling ports in pb_graph for analysis SDC generator	2020-07-09 23:28:42 -06:00
fpga_spice	[FPGA-SPICE] Add VDD/VSS ports to SPICE subckt instanciation	2020-09-20 15:21:33 -06:00
fpga_verilog	[FPGA-Verilog] Rename files and functions to distinguish from FPGA-SPICE files and functions	2020-09-20 12:58:55 -06:00
mux_lib	bug fix in lut and mux module generation on supporting spypads	2020-04-22 14:41:16 -06:00
repack	[OpenFPGA code] bug fix for fully equivalent outputs of pb_type	2020-09-16 19:26:46 -06:00
tile_direct	bug fixed in tile direct builder	2020-03-21 12:43:56 -06:00
utils	[FPGA-SPICE] Add auxiliary SPICE netlist writer	2020-09-20 12:53:28 -06:00
vpr_wrapper	add rr_segment binding to circuit model	2020-02-12 11:21:40 -07:00
ctag_src.sh	add ctags script to index openfpga source files	2020-01-24 10:15:16 -07:00
main.cpp	start transplanting FPGA-SPICE	2020-07-05 12:10:12 -06:00