OpenFPGA/fpga_flow/benchmarks/Verilog/MCNC
AurelienUoU ba05a08ef0 Path correction in tech debugging + correction of yosys rewrite file in fpga_flow 2019-05-30 09:52:19 -06:00
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alu4 Correct blif clock bame issue in fpga_flow and reload original MCNC benchmarks 2019-05-22 13:44:48 -06:00
apex2 Path correction in tech debugging + correction of yosys rewrite file in fpga_flow 2019-05-30 09:52:19 -06:00
apex4 Add MCNC Benchmarks netlists generation to travis regression test 2019-05-17 15:22:04 -06:00
bigkey Correct blif clock bame issue in fpga_flow and reload original MCNC benchmarks 2019-05-22 13:44:48 -06:00
clma Correct blif clock bame issue in fpga_flow and reload original MCNC benchmarks 2019-05-22 13:44:48 -06:00
des Add MCNC Benchmarks netlists generation to travis regression test 2019-05-17 15:22:04 -06:00
diffeq Correct blif clock bame issue in fpga_flow and reload original MCNC benchmarks 2019-05-22 13:44:48 -06:00
dsip Correct blif clock bame issue in fpga_flow and reload original MCNC benchmarks 2019-05-22 13:44:48 -06:00
elliptic Correct blif clock bame issue in fpga_flow and reload original MCNC benchmarks 2019-05-22 13:44:48 -06:00
ex5p Add MCNC Benchmarks netlists generation to travis regression test 2019-05-17 15:22:04 -06:00
ex1010 Add MCNC Benchmarks netlists generation to travis regression test 2019-05-17 15:22:04 -06:00
frisc Correct blif clock bame issue in fpga_flow and reload original MCNC benchmarks 2019-05-22 13:44:48 -06:00
misex3 Add MCNC Benchmarks netlists generation to travis regression test 2019-05-17 15:22:04 -06:00
pdc Add MCNC Benchmarks netlists generation to travis regression test 2019-05-17 15:22:04 -06:00
s298 Correct blif clock bame issue in fpga_flow and reload original MCNC benchmarks 2019-05-22 13:44:48 -06:00
s38417 Correct blif clock bame issue in fpga_flow and reload original MCNC benchmarks 2019-05-22 13:44:48 -06:00
s38584 Correct blif clock bame issue in fpga_flow and reload original MCNC benchmarks 2019-05-22 13:44:48 -06:00
seq Add MCNC Benchmarks netlists generation to travis regression test 2019-05-17 15:22:04 -06:00
spla Add MCNC Benchmarks netlists generation to travis regression test 2019-05-17 15:22:04 -06:00
tseng Correct blif clock bame issue in fpga_flow and reload original MCNC benchmarks 2019-05-22 13:44:48 -06:00