AurelienUoU
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ba05a08ef0
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Path correction in tech debugging + correction of yosys rewrite file in fpga_flow
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2019-05-30 09:52:19 -06:00 |
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AurelienUoU
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2b04376209
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Correct blif clock bame issue in fpga_flow and reload original MCNC benchmarks
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2019-05-22 13:44:48 -06:00 |
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AurelienUoU
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b4c97f86a3
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Change benchmarks clock name to avoid yosys blif generation issue (adding a clock) + execute pro_blif.pl to correct ace's blif output issue on latches
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2019-05-21 17:24:06 -06:00 |
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AurelienUoU
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df8bb0db1a
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Add MCNC Benchmarks netlists generation to travis regression test
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2019-05-17 15:22:04 -06:00 |