AurelienUoU ba05a08ef0 Path correction in tech debugging + correction of yosys rewrite file in fpga_flow		2019-05-30 09:52:19 -06:00
..
Blif	Add MCNC Benchmarks netlists generation to travis regression test	2019-05-17 15:22:04 -06:00
List	Change benchmarks clock name to avoid yosys blif generation issue (adding a clock) + execute pro_blif.pl to correct ace's blif output issue on latches	2019-05-21 17:24:06 -06:00
Verilog/MCNC	Path correction in tech debugging + correction of yosys rewrite file in fpga_flow	2019-05-30 09:52:19 -06:00