tangxifan aeeee6d8bd [core] code format		2023-04-20 15:07:54 +08:00
..
annotation	[core] code format	2023-04-20 15:07:54 +08:00
base	[core] now clock routing for programmable clock network works for 1 clock design	2023-03-07 13:13:25 -08:00
fabric	[core] now fabric generator can wire clock ports to routing blocks	2023-03-02 12:33:26 -08:00
fpga_bitstream	[core] fixed a bug: node_fan_in seems buggy	2023-03-06 22:26:27 -08:00
fpga_sdc	[engine] add missing header files after coding formatter sorts the include files	2022-10-06 18:08:57 -07:00
fpga_spice	[engine] update source files subject to code formatting rules	2022-10-06 17:08:50 -07:00
fpga_verilog	[code] fixed all the compiler warnings under openfpga/src	2023-01-31 12:51:52 -08:00
mux_lib	Merge branch 'master' into xt_clk_arch	2023-04-19 22:17:33 +08:00
repack	[engine] code format	2023-01-20 21:52:32 -08:00
tile_direct	[engine] update source files subject to code formatting rules	2022-10-06 17:08:50 -07:00
utils	[core] fix compiler warnings	2023-02-28 20:40:14 -08:00
vpr_wrapper	[core] code format	2023-04-19 11:10:42 +08:00
ctag_src.sh	[engine] remove warnings	2022-08-18 15:56:18 -07:00
main.cpp	[engine] fixed syntax errors	2022-11-23 17:06:27 -08:00
openfpga_shell.i	[script] rename shared library name for tcl, so that it is straightforward to load in tcl	2022-12-01 15:59:52 -08:00