tangxifan 67b3b25bea refactoring analysis sdc generation		2019-11-10 16:08:49 -07:00
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backend_assistant	refactoring analysis sdc generation	2019-11-10 16:08:49 -07:00
base	refactoring analysis SDC generation	2019-11-10 15:40:54 -07:00
bitstream	critical bugs fixed for routing module naming; and speed up local wire detection in Verilog writer	2019-11-08 15:01:30 -07:00
clb_pin_remap	cleaned unused variables	2019-05-13 14:45:02 -06:00
module_builder	refactored CB SDC generation	2019-11-09 11:42:38 -07:00
router	fixed bugs in configure pb_rr_graph and dependence on testbenches	2019-08-16 18:20:30 -06:00
shell	added Verilog generation for preconfig top module	2019-10-29 13:54:35 -06:00
spice	Rename SCFF to CCFF, configuration chain flip flop	2019-09-26 11:32:57 -06:00
verilog	critical bugs fixed for routing module naming; and speed up local wire detection in Verilog writer	2019-11-08 15:01:30 -07:00