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OpenFPGA/vpr7_x2p/vpr
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tangxifan 66701838ff update relative path in ARCH XML 2019-01-08 11:41:24 -07:00
..
ARCH update relative path in ARCH XML 2019-01-08 11:41:24 -07:00
Circuits Add new benchmark and modify go.sh to use it 2018-12-26 04:24:26 -07:00
SRC Correct manual testbench generation bug 2019-01-07 18:03:56 -07:00
SpiceNetlists rename customized vpr7 to vpr7 XML to Production 2018-09-17 23:10:45 -06:00
VerilogNetlists Add timing and initialization for simulation 2018-12-04 17:32:09 -07:00
picorv Changed for the naming 2018-12-08 16:19:38 -07:00
Makefile rename customized vpr7 to vpr7 XML to Production 2018-09-17 23:10:45 -06:00
go.sh Add new benchmark and modify go.sh to use it 2018-12-26 04:24:26 -07:00
picorv.sh Changed for the naming 2018-12-08 16:19:38 -07:00