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OpenFPGA/openfpga_flow/tasks/fpga_verilog
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Aram Kostanyan 6a4cc340a3 Changed HDL files reading to be as a single compilation unit in yosys_vpr flow for Verific mode. Changed '' variable to 'read_verilog ' in yosys template scripts. Updated task configs accordingly. 2022-01-17 13:21:29 +05:00
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adder [Script, Benchmark, Test] Now use circuit format in openfpga shell script to specify eblif file 2021-02-04 20:20:10 -07:00
bram Changed HDL files reading to be as a single compilation unit in yosys_vpr flow for Verific mode. Changed '' variable to 'read_verilog ' in yosys template scripts. Updated task configs accordingly. 2022-01-17 13:21:29 +05:00
depopulate_crossbar/config [Flow] Rename OpenFPGA shell script folder name to consistent with naming convention 2020-11-22 16:37:19 -07:00
dsp Changed HDL files reading to be as a single compilation unit in yosys_vpr flow for Verific mode. Changed '' variable to 'read_verilog ' in yosys template scripts. Updated task configs accordingly. 2022-01-17 13:21:29 +05:00
duplicated_grid_pin/config [Flow] Rename OpenFPGA shell script folder name to consistent with naming convention 2020-11-22 16:37:19 -07:00
fabric_chain [Flow] Rename OpenFPGA shell script folder name to consistent with naming convention 2020-11-22 16:37:19 -07:00
flatten_routing/config [Test] Deploy default net type option to test case 2021-02-28 12:20:43 -07:00
fully_connected_output_crossbar/config [Flow] Rename OpenFPGA shell script folder name to consistent with naming convention 2020-11-22 16:37:19 -07:00
io Changed HDL files reading to be as a single compilation unit in yosys_vpr flow for Verific mode. Changed '' variable to 'read_verilog ' in yosys template scripts. Updated task configs accordingly. 2022-01-17 13:21:29 +05:00
lut_design [Test] Update test case to use dedicated eblif file 2021-02-09 15:51:57 -07:00
mux_design [Flow] Rename OpenFPGA shell script folder name to consistent with naming convention 2020-11-22 16:37:19 -07:00
power_gated_design/power_gated_inverter/config Changed HDL files reading to be as a single compilation unit in yosys_vpr flow for Verific mode. Changed '' variable to 'read_verilog ' in yosys template scripts. Updated task configs accordingly. 2022-01-17 13:21:29 +05:00
spypad/config [Flow] Rename OpenFPGA shell script folder name to consistent with naming convention 2020-11-22 16:37:19 -07:00
thru_channel [Flow] Rename OpenFPGA shell script folder name to consistent with naming convention 2020-11-22 16:37:19 -07:00
untileable/config [Flow] Rename OpenFPGA shell script folder name to consistent with naming convention 2020-11-22 16:37:19 -07:00
verilog_netlist_formats Changed HDL files reading to be as a single compilation unit in yosys_vpr flow for Verific mode. Changed '' variable to 'read_verilog ' in yosys template scripts. Updated task configs accordingly. 2022-01-17 13:21:29 +05:00