Aram Kostanyan
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6a4cc340a3
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Changed HDL files reading to be as a single compilation unit in yosys_vpr flow for Verific mode. Changed '' variable to 'read_verilog ' in yosys template scripts. Updated task configs accordingly.
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2022-01-17 13:21:29 +05:00 |
tangxifan
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824a03bdca
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[Flow] Patch new test case
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2022-01-02 20:20:36 -08:00 |
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tangxifan
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55da99f4ca
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[Flow] Add a new test case to validate DSP with registers
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2022-01-02 20:08:23 -08:00 |
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tangxifan
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40d11a45d9
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[Test] Disable ACE2 in implicit verilog test cases due to Yosys upgrade
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2021-10-30 14:49:56 -07:00 |
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tangxifan
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9f03ecb160
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[Test] Patch test case due to the changes in counter benchmarks
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2021-07-02 17:57:39 -06:00 |
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tangxifan
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64dcdaec61
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[Test] Update all the tasks that use counter benchmark
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2021-07-02 17:29:13 -06:00 |
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tangxifan
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2c1692e6dc
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[Test] Bug fix
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2021-06-29 17:54:25 -06:00 |
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tangxifan
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6f0600e17f
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[Test] Added two test cases for generating preconfigured fabric wrapper in different styles
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2021-06-27 19:56:01 -06:00 |
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tangxifan
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eed30605d7
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[Test] patch test case
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2021-06-09 15:20:55 -06:00 |
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tangxifan
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52c0ed571b
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[Test] Patch test case to use proper template
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2021-06-09 14:27:02 -06:00 |
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tangxifan
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b72d4bd807
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[Test] Update test case for 1kbit DPRAM architectures
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2021-04-28 11:28:53 -06:00 |
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tangxifan
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5c729657ef
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[Test] Bug fix in test case for DPRAM whose width = 2
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2021-04-28 10:31:22 -06:00 |
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tangxifan
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0bec4b3f32
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[Test] Update task configuration to use proper openfpgashell script
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2021-04-27 23:34:42 -06:00 |
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tangxifan
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fdfbdc4613
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[Test] Update task configuration files to use dedicated yosys script
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2021-04-27 20:05:04 -06:00 |
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tangxifan
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6291871faf
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[Test] Added a test for the example architecture with 2x2 DSP blocks
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2021-04-26 16:28:43 -06:00 |
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tangxifan
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80f98328df
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[Test] Update test settings for architecture with fracturable DSP blocks
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2021-04-24 15:16:50 -06:00 |
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tangxifan
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1c6b9a23d7
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[Test] Add new test for multi-mode 16-bit DSP blocks
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2021-04-24 13:29:29 -06:00 |
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tangxifan
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189c94ff19
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[Test] Deploy new mac benchmarks to tests
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2021-04-23 20:44:14 -06:00 |
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tangxifan
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8c970a792a
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[Test] Add a new test case for heterogeneous FPGA using single-mode 8-bit multiplier
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2021-03-23 15:33:00 -06:00 |
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tangxifan
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b90a17543d
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[Test] Add new test case to test default nettype in different verilog syntax
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2021-02-28 16:16:45 -07:00 |
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tangxifan
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9f4d05da67
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[Test] Bug fix for new test case
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2021-02-28 16:11:30 -07:00 |
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tangxifan
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18a7041424
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[Test] Add default net type test for explicit port mapping
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2021-02-28 12:31:32 -07:00 |
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tangxifan
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ff29cc3dff
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[Test] Move tests to a test group
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2021-02-28 12:23:35 -07:00 |
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tangxifan
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9cb1ca42fe
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[Test] Deploy default net type option to test case
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2021-02-28 12:20:43 -07:00 |
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tangxifan
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d85d6e964e
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Merge pull request #227 from watcag/master
Standard-cell flow
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2021-02-17 10:11:34 -07:00 |
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tangxifan
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3ae501a5ea
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[Test] Update test case to use dedicated eblif file
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2021-02-09 15:51:57 -07:00 |
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tangxifan
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2b51b36dd6
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[Test] Now use the super LUT arch in the test case
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2021-02-09 15:27:44 -07:00 |
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tangxifan
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56284059de
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[Test] Add a test case for a super LUT
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2021-02-09 15:25:32 -07:00 |
Nachiket Kapre
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6bb2e29f17
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default to ns for time unit -- synopsys dc whines
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2021-02-09 17:04:52 -05:00 |
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Nachiket Kapre
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87c69460df
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what is going on
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2021-02-09 11:33:08 -05:00 |
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Nachiket Kapre
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cc74c6268a
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trying fix chan width
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2021-02-09 11:28:19 -05:00 |
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Nachiket Kapre
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b14b5f975d
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adding sweep for W
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2021-02-09 08:48:25 -05:00 |
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Nachiket Kapre
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d040ba569c
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merge for consideration;
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2021-02-08 21:29:34 -05:00 |
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Nachiket Kapre
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94f858fcde
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merge for consideration;
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2021-02-08 21:27:01 -05:00 |
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tangxifan
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8853370c60
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[Script, Benchmark, Test] Now use circuit format in openfpga shell script to specify eblif file
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2021-02-04 20:20:10 -07:00 |
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tangxifan
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31441c0b64
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[Test] Deploy adder_8 to soft adder test
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2021-02-03 09:26:38 -07:00 |
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tangxifan
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8e36ed1ab6
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[Test] Update task configuration to use and2 eblif
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2021-02-02 15:01:15 -07:00 |
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tangxifan
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5e2847bc41
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[Test] Update test case to use eblif file
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2021-02-02 09:33:41 -07:00 |
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tangxifan
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9ff5e7926b
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[Test] Update test case to use the adder benchmark
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2021-02-02 09:24:39 -07:00 |
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tangxifan
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04594cb7ab
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[Test] Adapt bitstream annotatin file to parser's requirement
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2021-02-01 17:38:36 -07:00 |
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tangxifan
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280c9620aa
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[Test] Add an example bitstream annotation file
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2021-02-01 16:01:21 -07:00 |
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tangxifan
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940dce469a
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[Test] Bug fix for test case configuration
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2021-02-01 11:19:47 -07:00 |
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tangxifan
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a80acfb547
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[Test] Add new test case to CI script
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2021-02-01 11:16:12 -07:00 |
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tangxifan
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af630dab1e
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[Test] Add soft adder test case. This is placeholder. Test arch will be elaborated
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2021-02-01 10:53:38 -07:00 |
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tangxifan
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9cce411eda
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[Test] Add adder test cases
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2021-02-01 10:42:24 -07:00 |
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tangxifan
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e58e1e86c2
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[Test] Update test case to use new shell script
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2021-01-10 11:09:10 -07:00 |
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tangxifan
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1c68e43acf
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[Test] Add new test case for registerable I/O architecture
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2021-01-10 11:00:21 -07:00 |
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tangxifan
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b8559249dc
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[Test] Bug fix in task configuration file
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2020-11-25 22:23:27 -07:00 |
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tangxifan
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26e4db56ad
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[Test] Add new test case for the native fracturable LUT4
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2020-11-25 22:21:23 -07:00 |
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tangxifan
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617f7e3062
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[Flow] disable signal initialization for behavioral verilog generation
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2020-11-22 21:13:22 -07:00 |