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OpenFPGA/openfpga_flow/tasks/basic_tests/global_tile_ports
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tangxifan 179b0ce304 [Test] Use formal verification method to reduce the runtime of iverilog simulation for global tile 2020-11-30 18:11:47 -07:00
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global_tile_clock/config [Flow] Rename OpenFPGA shell script folder name to consistent with naming convention 2020-11-22 16:37:19 -07:00
global_tile_reset/config [Test] Use formal verification method to reduce the runtime of iverilog simulation for global tile 2020-11-30 18:11:47 -07:00