tangxifan 0cb8457e21 [Test] Add test case for tileable I/O		2020-12-04 16:02:47 -07:00
..
custom_fabric_netlist_location/config	[Flow] Rename OpenFPGA shell script folder name to consistent with naming convention	2020-11-22 16:37:19 -07:00
fabric_key	[Flow] Rename OpenFPGA shell script folder name to consistent with naming convention	2020-11-22 16:37:19 -07:00
fixed_device_support/config	[Flow] Rename OpenFPGA shell script folder name to consistent with naming convention	2020-11-22 16:37:19 -07:00
fixed_simulation_settings/config	[Flow] Rename OpenFPGA shell script folder name to consistent with naming convention	2020-11-22 16:37:19 -07:00
full_testbench	[Flow] Rename OpenFPGA shell script folder name to consistent with naming convention	2020-11-22 16:37:19 -07:00
generate_fabric/config	[Flow] Rename OpenFPGA shell script folder name to consistent with naming convention	2020-11-22 16:37:19 -07:00
generate_testbench/config	[Flow] Rename OpenFPGA shell script folder name to consistent with naming convention	2020-11-22 16:37:19 -07:00
global_tile_ports	[Test] Use formal verification method to reduce the runtime of iverilog simulation for global tile	2020-11-30 18:11:47 -07:00
k4_series	[Flow] Rename OpenFPGA shell script folder name to consistent with naming convention	2020-11-22 16:37:19 -07:00
preconfig_testbench	[Flow] Rename OpenFPGA shell script folder name to consistent with naming convention	2020-11-22 16:37:19 -07:00
tile_organization	[Test] Add test case for tileable I/O	2020-12-04 16:02:47 -07:00