tangxifan
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179b0ce304
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[Test] Use formal verification method to reduce the runtime of iverilog simulation for global tile
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2020-11-30 18:11:47 -07:00 |
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tangxifan
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27a480b5f8
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[Test] arch name fix in the test case
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2020-11-30 17:45:54 -07:00 |
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tangxifan
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a1d3b439d3
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[Test] Add a new test case to define a global reset port from a global tile port
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2020-11-30 17:19:12 -07:00 |
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tangxifan
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655da9f3d0
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[Flow] Rename OpenFPGA shell script folder name to consistent with naming convention
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2020-11-22 16:37:19 -07:00 |
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tangxifan
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845436fa71
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[Test] Add sequential benchmark for global tile clock test case
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2020-11-17 14:34:54 -07:00 |
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tangxifan
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485258a9ea
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[Test] Add test case for global clock from tiles
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2020-11-10 19:24:25 -07:00 |