tangxifan 5bcd559851 [Tool] Many bug fix in the multi-region support for both memory banks and framed-based. Still have problems in multi-region framed-based verification		2020-10-30 17:29:04 -06:00
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annotation	[Debug aid] add pb_type full hierarchy path in the error message of architecture binding checker	2020-09-02 22:16:10 -06:00
base	[Tool] Now users can specify a different fabric netlist when generating Verilog testbench	2020-10-12 12:31:51 -06:00
fabric	[Tool] Many bug fix in the multi-region support for both memory banks and framed-based. Still have problems in multi-region framed-based verification	2020-10-30 17:29:04 -06:00
fpga_bitstream	[Tool] Many bug fix in the multi-region support for both memory banks and framed-based. Still have problems in multi-region framed-based verification	2020-10-30 17:29:04 -06:00
fpga_sdc	[Tool] Change analysis SDC file name to track netlist name	2020-10-10 17:43:35 -06:00
fpga_spice	[FPGA-SPICE] Add VDD/VSS ports to SPICE subckt instanciation	2020-09-20 15:21:33 -06:00
fpga_verilog	[Tool] Many bug fix in the multi-region support for both memory banks and framed-based. Still have problems in multi-region framed-based verification	2020-10-30 17:29:04 -06:00
mux_lib	bug fix in lut and mux module generation on supporting spypads	2020-04-22 14:41:16 -06:00
repack	[OpenFPGA Tool] Bug fix for repacking no local routing architecture	2020-09-21 22:22:03 -06:00
tile_direct	bug fixed in tile direct builder	2020-03-21 12:43:56 -06:00
utils	[Tool] Many bug fix in the multi-region support for both memory banks and framed-based. Still have problems in multi-region framed-based verification	2020-10-30 17:29:04 -06:00
vpr_wrapper	add rr_segment binding to circuit model	2020-02-12 11:21:40 -07:00
ctag_src.sh	add ctags script to index openfpga source files	2020-01-24 10:15:16 -07:00
main.cpp	start transplanting FPGA-SPICE	2020-07-05 12:10:12 -06:00